[linux-2.6-block.git] / drivers / thermal / mtk_thermal.c

/*
 * Copyright (c) 2015 MediaTek Inc.
 * Author: Hanyi Wu <hanyi.wu@mediatek.com>
 *         Sascha Hauer <s.hauer@pengutronix.de>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/nvmem-consumer.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/io.h>
#include <linux/thermal.h>
#include <linux/reset.h>
#include <linux/types.h>

/* AUXADC Registers */
#define AUXADC_CON0_V		0x000
#define AUXADC_CON1_V		0x004
#define AUXADC_CON1_SET_V	0x008
#define AUXADC_CON1_CLR_V	0x00c
#define AUXADC_CON2_V		0x010
#define AUXADC_DATA(channel)	(0x14 + (channel) * 4)
#define AUXADC_MISC_V		0x094

#define AUXADC_CON1_CHANNEL(x)	BIT(x)

#define APMIXED_SYS_TS_CON1	0x604

/* Thermal Controller Registers */
#define TEMP_MONCTL0		0x000
#define TEMP_MONCTL1		0x004
#define TEMP_MONCTL2		0x008
#define TEMP_MONIDET0		0x014
#define TEMP_MONIDET1		0x018
#define TEMP_MSRCTL0		0x038
#define TEMP_AHBPOLL		0x040
#define TEMP_AHBTO		0x044
#define TEMP_ADCPNP0		0x048
#define TEMP_ADCPNP1		0x04c
#define TEMP_ADCPNP2		0x050
#define TEMP_ADCPNP3		0x0b4

#define TEMP_ADCMUX		0x054
#define TEMP_ADCEN		0x060
#define TEMP_PNPMUXADDR		0x064
#define TEMP_ADCMUXADDR		0x068
#define TEMP_ADCENADDR		0x074
#define TEMP_ADCVALIDADDR	0x078
#define TEMP_ADCVOLTADDR	0x07c
#define TEMP_RDCTRL		0x080
#define TEMP_ADCVALIDMASK	0x084
#define TEMP_ADCVOLTAGESHIFT	0x088
#define TEMP_ADCWRITECTRL	0x08c
#define TEMP_MSR0		0x090
#define TEMP_MSR1		0x094
#define TEMP_MSR2		0x098
#define TEMP_MSR3		0x0B8

#define TEMP_SPARE0		0x0f0

#define PTPCORESEL		0x400

#define TEMP_MONCTL1_PERIOD_UNIT(x)	((x) & 0x3ff)

#define TEMP_MONCTL2_FILTER_INTERVAL(x)	(((x) & 0x3ff) << 16)
#define TEMP_MONCTL2_SENSOR_INTERVAL(x)	((x) & 0x3ff)

#define TEMP_AHBPOLL_ADC_POLL_INTERVAL(x)	(x)

#define TEMP_ADCWRITECTRL_ADC_PNP_WRITE		BIT(0)
#define TEMP_ADCWRITECTRL_ADC_MUX_WRITE		BIT(1)

#define TEMP_ADCVALIDMASK_VALID_HIGH		BIT(5)
#define TEMP_ADCVALIDMASK_VALID_POS(bit)	(bit)

#define MT8173_TS1	0
#define MT8173_TS2	1
#define MT8173_TS3	2
#define MT8173_TS4	3
#define MT8173_TSABB	4

/* AUXADC channel 11 is used for the temperature sensors */
#define MT8173_TEMP_AUXADC_CHANNEL	11

/* The total number of temperature sensors in the MT8173 */
#define MT8173_NUM_SENSORS		5

/* The number of banks in the MT8173 */
#define MT8173_NUM_ZONES		4

/* The number of sensing points per bank */
#define MT8173_NUM_SENSORS_PER_ZONE	4

/* Layout of the fuses providing the calibration data */
#define MT8173_CALIB_BUF0_VALID		BIT(0)
#define MT8173_CALIB_BUF1_ADC_GE(x)	(((x) >> 22) & 0x3ff)
#define MT8173_CALIB_BUF0_VTS_TS1(x)	(((x) >> 17) & 0x1ff)
#define MT8173_CALIB_BUF0_VTS_TS2(x)	(((x) >> 8) & 0x1ff)
#define MT8173_CALIB_BUF1_VTS_TS3(x)	(((x) >> 0) & 0x1ff)
#define MT8173_CALIB_BUF2_VTS_TS4(x)	(((x) >> 23) & 0x1ff)
#define MT8173_CALIB_BUF2_VTS_TSABB(x)	(((x) >> 14) & 0x1ff)
#define MT8173_CALIB_BUF0_DEGC_CALI(x)	(((x) >> 1) & 0x3f)
#define MT8173_CALIB_BUF0_O_SLOPE(x)	(((x) >> 26) & 0x3f)

#define THERMAL_NAME    "mtk-thermal"

struct mtk_thermal;

struct mtk_thermal_bank {
	struct mtk_thermal *mt;
	int id;
};

struct mtk_thermal {
	struct device *dev;
	void __iomem *thermal_base;

	struct clk *clk_peri_therm;
	struct clk *clk_auxadc;

	struct mtk_thermal_bank banks[MT8173_NUM_ZONES];

	/* lock: for getting and putting banks */
	struct mutex lock;

	/* Calibration values */
	s32 adc_ge;
	s32 degc_cali;
	s32 o_slope;
	s32 vts[MT8173_NUM_SENSORS];

};

struct mtk_thermal_bank_cfg {
	unsigned int num_sensors;
	unsigned int sensors[MT8173_NUM_SENSORS_PER_ZONE];
};

static const int sensor_mux_values[MT8173_NUM_SENSORS] = { 0, 1, 2, 3, 16 };

/*
 * The MT8173 thermal controller has four banks. Each bank can read up to
 * four temperature sensors simultaneously. The MT8173 has a total of 5
 * temperature sensors. We use each bank to measure a certain area of the
 * SoC. Since TS2 is located centrally in the SoC it is influenced by multiple
 * areas, hence is used in different banks.
 *
 * The thermal core only gets the maximum temperature of all banks, so
 * the bank concept wouldn't be necessary here. However, the SVS (Smart
 * Voltage Scaling) unit makes its decisions based on the same bank
 * data, and this indeed needs the temperatures of the individual banks
 * for making better decisions.
 */
static const struct mtk_thermal_bank_cfg bank_data[] = {
	{
		.num_sensors = 2,
		.sensors = { MT8173_TS2, MT8173_TS3 },
	}, {
		.num_sensors = 2,
		.sensors = { MT8173_TS2, MT8173_TS4 },
	}, {
		.num_sensors = 3,
		.sensors = { MT8173_TS1, MT8173_TS2, MT8173_TSABB },
	}, {
		.num_sensors = 1,
		.sensors = { MT8173_TS2 },
	},
};

struct mtk_thermal_sense_point {
	int msr;
	int adcpnp;
};

static const struct mtk_thermal_sense_point
		sensing_points[MT8173_NUM_SENSORS_PER_ZONE] = {
	{
		.msr = TEMP_MSR0,
		.adcpnp = TEMP_ADCPNP0,
	}, {
		.msr = TEMP_MSR1,
		.adcpnp = TEMP_ADCPNP1,
	}, {
		.msr = TEMP_MSR2,
		.adcpnp = TEMP_ADCPNP2,
	}, {
		.msr = TEMP_MSR3,
		.adcpnp = TEMP_ADCPNP3,
	},
};

/**
 * raw_to_mcelsius - convert a raw ADC value to mcelsius
 * @mt:		The thermal controller
 * @raw:	raw ADC value
 *
 * This converts the raw ADC value to mcelsius using the SoC specific
 * calibration constants
 */
static int raw_to_mcelsius(struct mtk_thermal *mt, int sensno, s32 raw)
{
	s32 tmp;

	raw &= 0xfff;

	tmp = 203450520 << 3;
	tmp /= 165 + mt->o_slope;
	tmp /= 10000 + mt->adc_ge;
	tmp *= raw - mt->vts[sensno] - 3350;
	tmp >>= 3;

	return mt->degc_cali * 500 - tmp;
}

/**
 * mtk_thermal_get_bank - get bank
 * @bank:	The bank
 *
 * The bank registers are banked, we have to select a bank in the
 * PTPCORESEL register to access it.
 */
static void mtk_thermal_get_bank(struct mtk_thermal_bank *bank)
{
	struct mtk_thermal *mt = bank->mt;
	u32 val;

	mutex_lock(&mt->lock);

	val = readl(mt->thermal_base + PTPCORESEL);
	val &= ~0xf;
	val |= bank->id;
	writel(val, mt->thermal_base + PTPCORESEL);
}

/**
 * mtk_thermal_put_bank - release bank
 * @bank:	The bank
 *
 * release a bank previously taken with mtk_thermal_get_bank,
 */
static void mtk_thermal_put_bank(struct mtk_thermal_bank *bank)
{
	struct mtk_thermal *mt = bank->mt;

	mutex_unlock(&mt->lock);
}

/**
 * mtk_thermal_bank_temperature - get the temperature of a bank
 * @bank:	The bank
 *
 * The temperature of a bank is considered the maximum temperature of
 * the sensors associated to the bank.
 */
static int mtk_thermal_bank_temperature(struct mtk_thermal_bank *bank)
{
	struct mtk_thermal *mt = bank->mt;
	int i, temp = INT_MIN, max = INT_MIN;
	u32 raw;

	for (i = 0; i < bank_data[bank->id].num_sensors; i++) {
		raw = readl(mt->thermal_base + sensing_points[i].msr);

		temp = raw_to_mcelsius(mt, bank_data[bank->id].sensors[i], raw);

		/*
		 * The first read of a sensor often contains very high bogus
		 * temperature value. Filter these out so that the system does
		 * not immediately shut down.
		 */
		if (temp > 200000)
			temp = 0;

		if (temp > max)
			max = temp;
	}

	return max;
}

static int mtk_read_temp(void *data, int *temperature)
{
	struct mtk_thermal *mt = data;
	int i;
	int tempmax = INT_MIN;

	for (i = 0; i < MT8173_NUM_ZONES; i++) {
		struct mtk_thermal_bank *bank = &mt->banks[i];

		mtk_thermal_get_bank(bank);

		tempmax = max(tempmax, mtk_thermal_bank_temperature(bank));

		mtk_thermal_put_bank(bank);
	}

	*temperature = tempmax;

	return 0;
}

static const struct thermal_zone_of_device_ops mtk_thermal_ops = {
	.get_temp = mtk_read_temp,
};

static void mtk_thermal_init_bank(struct mtk_thermal *mt, int num,
				  u32 apmixed_phys_base, u32 auxadc_phys_base)
{
	struct mtk_thermal_bank *bank = &mt->banks[num];
	const struct mtk_thermal_bank_cfg *cfg = &bank_data[num];
	int i;

	bank->id = num;
	bank->mt = mt;

	mtk_thermal_get_bank(bank);

	/* bus clock 66M counting unit is 12 * 15.15ns * 256 = 46.540us */
	writel(TEMP_MONCTL1_PERIOD_UNIT(12), mt->thermal_base + TEMP_MONCTL1);

	/*
	 * filt interval is 1 * 46.540us = 46.54us,
	 * sen interval is 429 * 46.540us = 19.96ms
	 */
	writel(TEMP_MONCTL2_FILTER_INTERVAL(1) |
			TEMP_MONCTL2_SENSOR_INTERVAL(429),
			mt->thermal_base + TEMP_MONCTL2);

	/* poll is set to 10u */
	writel(TEMP_AHBPOLL_ADC_POLL_INTERVAL(768),
	       mt->thermal_base + TEMP_AHBPOLL);

	/* temperature sampling control, 1 sample */
	writel(0x0, mt->thermal_base + TEMP_MSRCTL0);

	/* exceed this polling time, IRQ would be inserted */
	writel(0xffffffff, mt->thermal_base + TEMP_AHBTO);

	/* number of interrupts per event, 1 is enough */
	writel(0x0, mt->thermal_base + TEMP_MONIDET0);
	writel(0x0, mt->thermal_base + TEMP_MONIDET1);

	/*
	 * The MT8173 thermal controller does not have its own ADC. Instead it
	 * uses AHB bus accesses to control the AUXADC. To do this the thermal
	 * controller has to be programmed with the physical addresses of the
	 * AUXADC registers and with the various bit positions in the AUXADC.
	 * Also the thermal controller controls a mux in the APMIXEDSYS register
	 * space.
	 */

	/*
	 * this value will be stored to TEMP_PNPMUXADDR (TEMP_SPARE0)
	 * automatically by hw
	 */
	writel(BIT(MT8173_TEMP_AUXADC_CHANNEL), mt->thermal_base + TEMP_ADCMUX);

	/* AHB address for auxadc mux selection */
	writel(auxadc_phys_base + AUXADC_CON1_CLR_V,
	       mt->thermal_base + TEMP_ADCMUXADDR);

	/* AHB address for pnp sensor mux selection */
	writel(apmixed_phys_base + APMIXED_SYS_TS_CON1,
	       mt->thermal_base + TEMP_PNPMUXADDR);

	/* AHB value for auxadc enable */
	writel(BIT(MT8173_TEMP_AUXADC_CHANNEL), mt->thermal_base + TEMP_ADCEN);

	/* AHB address for auxadc enable (channel 0 immediate mode selected) */
	writel(auxadc_phys_base + AUXADC_CON1_SET_V,
	       mt->thermal_base + TEMP_ADCENADDR);

	/* AHB address for auxadc valid bit */
	writel(auxadc_phys_base + AUXADC_DATA(MT8173_TEMP_AUXADC_CHANNEL),
	       mt->thermal_base + TEMP_ADCVALIDADDR);

	/* AHB address for auxadc voltage output */
	writel(auxadc_phys_base + AUXADC_DATA(MT8173_TEMP_AUXADC_CHANNEL),
	       mt->thermal_base + TEMP_ADCVOLTADDR);

	/* read valid & voltage are at the same register */
	writel(0x0, mt->thermal_base + TEMP_RDCTRL);

	/* indicate where the valid bit is */
	writel(TEMP_ADCVALIDMASK_VALID_HIGH | TEMP_ADCVALIDMASK_VALID_POS(12),
	       mt->thermal_base + TEMP_ADCVALIDMASK);

	/* no shift */
	writel(0x0, mt->thermal_base + TEMP_ADCVOLTAGESHIFT);

	/* enable auxadc mux write transaction */
	writel(TEMP_ADCWRITECTRL_ADC_MUX_WRITE,
	       mt->thermal_base + TEMP_ADCWRITECTRL);

	for (i = 0; i < cfg->num_sensors; i++)
		writel(sensor_mux_values[cfg->sensors[i]],
		       mt->thermal_base + sensing_points[i].adcpnp);

	writel((1 << cfg->num_sensors) - 1, mt->thermal_base + TEMP_MONCTL0);

	writel(TEMP_ADCWRITECTRL_ADC_PNP_WRITE |
	       TEMP_ADCWRITECTRL_ADC_MUX_WRITE,
	       mt->thermal_base + TEMP_ADCWRITECTRL);

	mtk_thermal_put_bank(bank);
}

static u64 of_get_phys_base(struct device_node *np)
{
	u64 size64;
	const __be32 *regaddr_p;

	regaddr_p = of_get_address(np, 0, &size64, NULL);
	if (!regaddr_p)
		return OF_BAD_ADDR;

	return of_translate_address(np, regaddr_p);
}

static int mtk_thermal_get_calibration_data(struct device *dev,
					    struct mtk_thermal *mt)
{
	struct nvmem_cell *cell;
	u32 *buf;
	size_t len;
	int i, ret = 0;

	/* Start with default values */
	mt->adc_ge = 512;
	for (i = 0; i < MT8173_NUM_SENSORS; i++)
		mt->vts[i] = 260;
	mt->degc_cali = 40;
	mt->o_slope = 0;

	cell = nvmem_cell_get(dev, "calibration-data");
	if (IS_ERR(cell)) {
		if (PTR_ERR(cell) == -EPROBE_DEFER)
			return PTR_ERR(cell);
		return 0;
	}

	buf = (u32 *)nvmem_cell_read(cell, &len);

	nvmem_cell_put(cell);

	if (IS_ERR(buf))
		return PTR_ERR(buf);

	if (len < 3 * sizeof(u32)) {
		dev_warn(dev, "invalid calibration data\n");
		ret = -EINVAL;
		goto out;
	}

	if (buf[0] & MT8173_CALIB_BUF0_VALID) {
		mt->adc_ge = MT8173_CALIB_BUF1_ADC_GE(buf[1]);
		mt->vts[MT8173_TS1] = MT8173_CALIB_BUF0_VTS_TS1(buf[0]);
		mt->vts[MT8173_TS2] = MT8173_CALIB_BUF0_VTS_TS2(buf[0]);
		mt->vts[MT8173_TS3] = MT8173_CALIB_BUF1_VTS_TS3(buf[1]);
		mt->vts[MT8173_TS4] = MT8173_CALIB_BUF2_VTS_TS4(buf[2]);
		mt->vts[MT8173_TSABB] = MT8173_CALIB_BUF2_VTS_TSABB(buf[2]);
		mt->degc_cali = MT8173_CALIB_BUF0_DEGC_CALI(buf[0]);
		mt->o_slope = MT8173_CALIB_BUF0_O_SLOPE(buf[0]);
	} else {
		dev_info(dev, "Device not calibrated, using default calibration values\n");
	}

out:
	kfree(buf);

	return ret;
}

static int mtk_thermal_probe(struct platform_device *pdev)
{
	int ret, i;
	struct device_node *auxadc, *apmixedsys, *np = pdev->dev.of_node;
	struct mtk_thermal *mt;
	struct resource *res;
	u64 auxadc_phys_base, apmixed_phys_base;

	mt = devm_kzalloc(&pdev->dev, sizeof(*mt), GFP_KERNEL);
	if (!mt)
		return -ENOMEM;

	mt->clk_peri_therm = devm_clk_get(&pdev->dev, "therm");
	if (IS_ERR(mt->clk_peri_therm))
		return PTR_ERR(mt->clk_peri_therm);

	mt->clk_auxadc = devm_clk_get(&pdev->dev, "auxadc");
	if (IS_ERR(mt->clk_auxadc))
		return PTR_ERR(mt->clk_auxadc);

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	mt->thermal_base = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(mt->thermal_base))
		return PTR_ERR(mt->thermal_base);

	ret = mtk_thermal_get_calibration_data(&pdev->dev, mt);
	if (ret)
		return ret;

	mutex_init(&mt->lock);

	mt->dev = &pdev->dev;

	auxadc = of_parse_phandle(np, "mediatek,auxadc", 0);
	if (!auxadc) {
		dev_err(&pdev->dev, "missing auxadc node\n");
		return -ENODEV;
	}

	auxadc_phys_base = of_get_phys_base(auxadc);

	of_node_put(auxadc);

	if (auxadc_phys_base == OF_BAD_ADDR) {
		dev_err(&pdev->dev, "Can't get auxadc phys address\n");
		return -EINVAL;
	}

	apmixedsys = of_parse_phandle(np, "mediatek,apmixedsys", 0);
	if (!apmixedsys) {
		dev_err(&pdev->dev, "missing apmixedsys node\n");
		return -ENODEV;
	}

	apmixed_phys_base = of_get_phys_base(apmixedsys);

	of_node_put(apmixedsys);

	if (apmixed_phys_base == OF_BAD_ADDR) {
		dev_err(&pdev->dev, "Can't get auxadc phys address\n");
		return -EINVAL;
	}

	ret = clk_prepare_enable(mt->clk_auxadc);
	if (ret) {
		dev_err(&pdev->dev, "Can't enable auxadc clk: %d\n", ret);
		return ret;
	}

	ret = device_reset(&pdev->dev);
	if (ret)
		goto err_disable_clk_auxadc;

	ret = clk_prepare_enable(mt->clk_peri_therm);
	if (ret) {
		dev_err(&pdev->dev, "Can't enable peri clk: %d\n", ret);
		goto err_disable_clk_auxadc;
	}

	for (i = 0; i < MT8173_NUM_ZONES; i++)
		mtk_thermal_init_bank(mt, i, apmixed_phys_base,
				      auxadc_phys_base);

	platform_set_drvdata(pdev, mt);

	devm_thermal_zone_of_sensor_register(&pdev->dev, 0, mt,
					     &mtk_thermal_ops);

	return 0;

err_disable_clk_auxadc:
	clk_disable_unprepare(mt->clk_auxadc);

	return ret;
}

static int mtk_thermal_remove(struct platform_device *pdev)
{
	struct mtk_thermal *mt = platform_get_drvdata(pdev);

	clk_disable_unprepare(mt->clk_peri_therm);
	clk_disable_unprepare(mt->clk_auxadc);

	return 0;
}

static const struct of_device_id mtk_thermal_of_match[] = {
	{
		.compatible = "mediatek,mt8173-thermal",
	}, {
	},
};

static struct platform_driver mtk_thermal_driver = {
	.probe = mtk_thermal_probe,
	.remove = mtk_thermal_remove,
	.driver = {
		.name = THERMAL_NAME,
		.of_match_table = mtk_thermal_of_match,
	},
};

module_platform_driver(mtk_thermal_driver);

MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
MODULE_AUTHOR("Hanyi Wu <hanyi.wu@mediatek.com>");
MODULE_DESCRIPTION("Mediatek thermal driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
a92db1c8 SH	1	/*
	2	* Copyright (c) 2015 MediaTek Inc.
	3	* Author: Hanyi Wu <hanyi.wu@mediatek.com>
	4	* Sascha Hauer <s.hauer@pengutronix.de>
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
	14	*/
	15
	16	#include <linux/clk.h>
	17	#include <linux/delay.h>
	18	#include <linux/interrupt.h>
	19	#include <linux/kernel.h>
	20	#include <linux/module.h>
	21	#include <linux/nvmem-consumer.h>
	22	#include <linux/of.h>
	23	#include <linux/of_address.h>
	24	#include <linux/platform_device.h>
	25	#include <linux/slab.h>
	26	#include <linux/io.h>
	27	#include <linux/thermal.h>
	28	#include <linux/reset.h>
	29	#include <linux/types.h>
a92db1c8 SH	30
	31	/* AUXADC Registers */
	32	#define AUXADC_CON0_V 0x000
	33	#define AUXADC_CON1_V 0x004
	34	#define AUXADC_CON1_SET_V 0x008
	35	#define AUXADC_CON1_CLR_V 0x00c
	36	#define AUXADC_CON2_V 0x010
	37	#define AUXADC_DATA(channel) (0x14 + (channel) * 4)
	38	#define AUXADC_MISC_V 0x094
	39
	40	#define AUXADC_CON1_CHANNEL(x) BIT(x)
	41
	42	#define APMIXED_SYS_TS_CON1 0x604
	43
	44	/* Thermal Controller Registers */
	45	#define TEMP_MONCTL0 0x000
	46	#define TEMP_MONCTL1 0x004
	47	#define TEMP_MONCTL2 0x008
	48	#define TEMP_MONIDET0 0x014
	49	#define TEMP_MONIDET1 0x018
	50	#define TEMP_MSRCTL0 0x038
	51	#define TEMP_AHBPOLL 0x040
	52	#define TEMP_AHBTO 0x044
	53	#define TEMP_ADCPNP0 0x048
	54	#define TEMP_ADCPNP1 0x04c
	55	#define TEMP_ADCPNP2 0x050
	56	#define TEMP_ADCPNP3 0x0b4
	57
	58	#define TEMP_ADCMUX 0x054
	59	#define TEMP_ADCEN 0x060
	60	#define TEMP_PNPMUXADDR 0x064
	61	#define TEMP_ADCMUXADDR 0x068
	62	#define TEMP_ADCENADDR 0x074
	63	#define TEMP_ADCVALIDADDR 0x078
	64	#define TEMP_ADCVOLTADDR 0x07c
	65	#define TEMP_RDCTRL 0x080
	66	#define TEMP_ADCVALIDMASK 0x084
	67	#define TEMP_ADCVOLTAGESHIFT 0x088
	68	#define TEMP_ADCWRITECTRL 0x08c
	69	#define TEMP_MSR0 0x090
	70	#define TEMP_MSR1 0x094
	71	#define TEMP_MSR2 0x098
	72	#define TEMP_MSR3 0x0B8
	73
	74	#define TEMP_SPARE0 0x0f0
	75
	76	#define PTPCORESEL 0x400
	77
	78	#define TEMP_MONCTL1_PERIOD_UNIT(x) ((x) & 0x3ff)
	79
eb4fc33e	80	#define TEMP_MONCTL2_FILTER_INTERVAL(x) (((x) & 0x3ff) << 16)
a92db1c8 SH	81	#define TEMP_MONCTL2_SENSOR_INTERVAL(x) ((x) & 0x3ff)
	82
	83	#define TEMP_AHBPOLL_ADC_POLL_INTERVAL(x) (x)
	84
	85	#define TEMP_ADCWRITECTRL_ADC_PNP_WRITE BIT(0)
	86	#define TEMP_ADCWRITECTRL_ADC_MUX_WRITE BIT(1)
	87
	88	#define TEMP_ADCVALIDMASK_VALID_HIGH BIT(5)
	89	#define TEMP_ADCVALIDMASK_VALID_POS(bit) (bit)
	90
	91	#define MT8173_TS1 0
	92	#define MT8173_TS2 1
	93	#define MT8173_TS3 2
	94	#define MT8173_TS4 3
	95	#define MT8173_TSABB 4
	96
	97	/* AUXADC channel 11 is used for the temperature sensors */
	98	#define MT8173_TEMP_AUXADC_CHANNEL 11
	99
	100	/* The total number of temperature sensors in the MT8173 */
	101	#define MT8173_NUM_SENSORS 5
	102
	103	/* The number of banks in the MT8173 */
	104	#define MT8173_NUM_ZONES 4
	105
	106	/* The number of sensing points per bank */
	107	#define MT8173_NUM_SENSORS_PER_ZONE 4
	108
	109	/* Layout of the fuses providing the calibration data */
eb4fc33e EV	110	#define MT8173_CALIB_BUF0_VALID BIT(0)
	111	#define MT8173_CALIB_BUF1_ADC_GE(x) (((x) >> 22) & 0x3ff)
	112	#define MT8173_CALIB_BUF0_VTS_TS1(x) (((x) >> 17) & 0x1ff)
	113	#define MT8173_CALIB_BUF0_VTS_TS2(x) (((x) >> 8) & 0x1ff)
	114	#define MT8173_CALIB_BUF1_VTS_TS3(x) (((x) >> 0) & 0x1ff)
	115	#define MT8173_CALIB_BUF2_VTS_TS4(x) (((x) >> 23) & 0x1ff)
	116	#define MT8173_CALIB_BUF2_VTS_TSABB(x) (((x) >> 14) & 0x1ff)
	117	#define MT8173_CALIB_BUF0_DEGC_CALI(x) (((x) >> 1) & 0x3f)
	118	#define MT8173_CALIB_BUF0_O_SLOPE(x) (((x) >> 26) & 0x3f)
a92db1c8 SH	119
	120	#define THERMAL_NAME "mtk-thermal"
	121
	122	struct mtk_thermal;
	123
	124	struct mtk_thermal_bank {
	125	struct mtk_thermal *mt;
	126	int id;
	127	};
	128
	129	struct mtk_thermal {
	130	struct device *dev;
	131	void __iomem *thermal_base;
	132
	133	struct clk *clk_peri_therm;
	134	struct clk *clk_auxadc;
	135
	136	struct mtk_thermal_bank banks[MT8173_NUM_ZONES];
	137
eb4fc33e	138	/* lock: for getting and putting banks */
a92db1c8 SH	139	struct mutex lock;
	140
	141	/* Calibration values */
	142	s32 adc_ge;
	143	s32 degc_cali;
	144	s32 o_slope;
	145	s32 vts[MT8173_NUM_SENSORS];
	146
a92db1c8 SH	147	};
	148
	149	struct mtk_thermal_bank_cfg {
	150	unsigned int num_sensors;
	151	unsigned int sensors[MT8173_NUM_SENSORS_PER_ZONE];
	152	};
	153
	154	static const int sensor_mux_values[MT8173_NUM_SENSORS] = { 0, 1, 2, 3, 16 };
	155
	156	/*
	157	* The MT8173 thermal controller has four banks. Each bank can read up to
	158	* four temperature sensors simultaneously. The MT8173 has a total of 5
	159	* temperature sensors. We use each bank to measure a certain area of the
	160	* SoC. Since TS2 is located centrally in the SoC it is influenced by multiple
	161	* areas, hence is used in different banks.
	162	*
	163	* The thermal core only gets the maximum temperature of all banks, so
	164	* the bank concept wouldn't be necessary here. However, the SVS (Smart
	165	* Voltage Scaling) unit makes its decisions based on the same bank
	166	* data, and this indeed needs the temperatures of the individual banks
	167	* for making better decisions.
	168	*/
	169	static const struct mtk_thermal_bank_cfg bank_data[] = {
	170	{
	171	.num_sensors = 2,
	172	.sensors = { MT8173_TS2, MT8173_TS3 },
	173	}, {
	174	.num_sensors = 2,
	175	.sensors = { MT8173_TS2, MT8173_TS4 },
	176	}, {
	177	.num_sensors = 3,
	178	.sensors = { MT8173_TS1, MT8173_TS2, MT8173_TSABB },
	179	}, {
	180	.num_sensors = 1,
	181	.sensors = { MT8173_TS2 },
	182	},
	183	};
	184
	185	struct mtk_thermal_sense_point {
	186	int msr;
	187	int adcpnp;
	188	};
	189
	190	static const struct mtk_thermal_sense_point
	191	sensing_points[MT8173_NUM_SENSORS_PER_ZONE] = {
	192	{
	193	.msr = TEMP_MSR0,
	194	.adcpnp = TEMP_ADCPNP0,
	195	}, {
	196	.msr = TEMP_MSR1,
	197	.adcpnp = TEMP_ADCPNP1,
	198	}, {
	199	.msr = TEMP_MSR2,
	200	.adcpnp = TEMP_ADCPNP2,
	201	}, {
	202	.msr = TEMP_MSR3,
	203	.adcpnp = TEMP_ADCPNP3,
	204	},
	205	};
	206
	207	/**
	208	* raw_to_mcelsius - convert a raw ADC value to mcelsius
	209	* @mt: The thermal controller
	210	* @raw: raw ADC value
211	*
212	* This converts the raw ADC value to mcelsius using the SoC specific
213	* calibration constants
214	*/
215	static int raw_to_mcelsius(struct mtk_thermal *mt, int sensno, s32 raw)
216	{
217	s32 tmp;
218
219	raw &= 0xfff;
220
221	tmp = 203450520 << 3;
222	tmp /= 165 + mt->o_slope;
223	tmp /= 10000 + mt->adc_ge;
224	tmp *= raw - mt->vts[sensno] - 3350;
225	tmp >>= 3;
226
227	return mt->degc_cali * 500 - tmp;
228	}
229
230	/**
231	* mtk_thermal_get_bank - get bank
232	* @bank: The bank
233	*
234	* The bank registers are banked, we have to select a bank in the
235	* PTPCORESEL register to access it.
236	*/
237	static void mtk_thermal_get_bank(struct mtk_thermal_bank *bank)
238	{
239	struct mtk_thermal *mt = bank->mt;
240	u32 val;
241
242	mutex_lock(&mt->lock);
243
244	val = readl(mt->thermal_base + PTPCORESEL);
245	val &= ~0xf;
246	val \|= bank->id;
247	writel(val, mt->thermal_base + PTPCORESEL);
248	}
249
250	/**
251	* mtk_thermal_put_bank - release bank
252	* @bank: The bank
253	*
254	* release a bank previously taken with mtk_thermal_get_bank,
255	*/
256	static void mtk_thermal_put_bank(struct mtk_thermal_bank *bank)
257	{
258	struct mtk_thermal *mt = bank->mt;
259
260	mutex_unlock(&mt->lock);
261	}
262
263	/**
264	* mtk_thermal_bank_temperature - get the temperature of a bank
265	* @bank: The bank
266	*
267	* The temperature of a bank is considered the maximum temperature of
268	* the sensors associated to the bank.
269	*/
270	static int mtk_thermal_bank_temperature(struct mtk_thermal_bank *bank)
271	{
272	struct mtk_thermal *mt = bank->mt;
eb4fc33e	273	int i, temp = INT_MIN, max = INT_MIN;
a92db1c8 SH	274	u32 raw;
a92db1c8 SH	275
a92db1c8 SH	276	for (i = 0; i < bank_data[bank->id].num_sensors; i++) {
	277	raw = readl(mt->thermal_base + sensing_points[i].msr);
	278
	279	temp = raw_to_mcelsius(mt, bank_data[bank->id].sensors[i], raw);
	280
	281	/*
	282	* The first read of a sensor often contains very high bogus
	283	* temperature value. Filter these out so that the system does
	284	* not immediately shut down.
	285	*/
	286	if (temp > 200000)
	287	temp = 0;
	288
	289	if (temp > max)
	290	max = temp;
	291	}
	292
	293	return max;
	294	}
	295
	296	static int mtk_read_temp(void data, int temperature)
	297	{
	298	struct mtk_thermal *mt = data;
	299	int i;
	300	int tempmax = INT_MIN;
	301
	302	for (i = 0; i < MT8173_NUM_ZONES; i++) {
	303	struct mtk_thermal_bank *bank = &mt->banks[i];
	304
	305	mtk_thermal_get_bank(bank);
	306
	307	tempmax = max(tempmax, mtk_thermal_bank_temperature(bank));
	308
	309	mtk_thermal_put_bank(bank);
	310	}
	311
	312	*temperature = tempmax;
	313
	314	return 0;
	315	}
	316
	317	static const struct thermal_zone_of_device_ops mtk_thermal_ops = {
	318	.get_temp = mtk_read_temp,
	319	};
	320
	321	static void mtk_thermal_init_bank(struct mtk_thermal *mt, int num,
eb4fc33e	322	u32 apmixed_phys_base, u32 auxadc_phys_base)
a92db1c8 SH	323	{
	324	struct mtk_thermal_bank *bank = &mt->banks[num];
	325	const struct mtk_thermal_bank_cfg *cfg = &bank_data[num];
	326	int i;
	327
	328	bank->id = num;
	329	bank->mt = mt;
	330
	331	mtk_thermal_get_bank(bank);
	332
	333	/* bus clock 66M counting unit is 12 * 15.15ns * 256 = 46.540us */
	334	writel(TEMP_MONCTL1_PERIOD_UNIT(12), mt->thermal_base + TEMP_MONCTL1);
	335
	336	/*
	337	* filt interval is 1 * 46.540us = 46.54us,
	338	* sen interval is 429 * 46.540us = 19.96ms
	339	*/
	340	writel(TEMP_MONCTL2_FILTER_INTERVAL(1) \|
	341	TEMP_MONCTL2_SENSOR_INTERVAL(429),
	342	mt->thermal_base + TEMP_MONCTL2);
	343
	344	/* poll is set to 10u */
	345	writel(TEMP_AHBPOLL_ADC_POLL_INTERVAL(768),
eb4fc33e	346	mt->thermal_base + TEMP_AHBPOLL);
a92db1c8 SH	347
	348	/* temperature sampling control, 1 sample */
	349	writel(0x0, mt->thermal_base + TEMP_MSRCTL0);
	350
	351	/* exceed this polling time, IRQ would be inserted */
	352	writel(0xffffffff, mt->thermal_base + TEMP_AHBTO);
	353
	354	/* number of interrupts per event, 1 is enough */
	355	writel(0x0, mt->thermal_base + TEMP_MONIDET0);
	356	writel(0x0, mt->thermal_base + TEMP_MONIDET1);
	357
	358	/*
	359	* The MT8173 thermal controller does not have its own ADC. Instead it
	360	* uses AHB bus accesses to control the AUXADC. To do this the thermal
	361	* controller has to be programmed with the physical addresses of the
	362	* AUXADC registers and with the various bit positions in the AUXADC.
	363	* Also the thermal controller controls a mux in the APMIXEDSYS register
	364	* space.
	365	*/
	366
	367	/*
	368	* this value will be stored to TEMP_PNPMUXADDR (TEMP_SPARE0)
	369	* automatically by hw
	370	*/
	371	writel(BIT(MT8173_TEMP_AUXADC_CHANNEL), mt->thermal_base + TEMP_ADCMUX);
	372
	373	/* AHB address for auxadc mux selection */
	374	writel(auxadc_phys_base + AUXADC_CON1_CLR_V,
eb4fc33e	375	mt->thermal_base + TEMP_ADCMUXADDR);
a92db1c8 SH	376
	377	/* AHB address for pnp sensor mux selection */
	378	writel(apmixed_phys_base + APMIXED_SYS_TS_CON1,
eb4fc33e	379	mt->thermal_base + TEMP_PNPMUXADDR);
a92db1c8 SH	380
	381	/* AHB value for auxadc enable */
	382	writel(BIT(MT8173_TEMP_AUXADC_CHANNEL), mt->thermal_base + TEMP_ADCEN);
	383
	384	/* AHB address for auxadc enable (channel 0 immediate mode selected) */
	385	writel(auxadc_phys_base + AUXADC_CON1_SET_V,
eb4fc33e	386	mt->thermal_base + TEMP_ADCENADDR);
a92db1c8 SH	387
	388	/* AHB address for auxadc valid bit */
	389	writel(auxadc_phys_base + AUXADC_DATA(MT8173_TEMP_AUXADC_CHANNEL),
eb4fc33e	390	mt->thermal_base + TEMP_ADCVALIDADDR);
a92db1c8 SH	391
	392	/* AHB address for auxadc voltage output */
	393	writel(auxadc_phys_base + AUXADC_DATA(MT8173_TEMP_AUXADC_CHANNEL),
eb4fc33e	394	mt->thermal_base + TEMP_ADCVOLTADDR);
a92db1c8 SH	395
	396	/* read valid & voltage are at the same register */
	397	writel(0x0, mt->thermal_base + TEMP_RDCTRL);
	398
	399	/* indicate where the valid bit is */
	400	writel(TEMP_ADCVALIDMASK_VALID_HIGH \| TEMP_ADCVALIDMASK_VALID_POS(12),
eb4fc33e	401	mt->thermal_base + TEMP_ADCVALIDMASK);
a92db1c8 SH	402
	403	/* no shift */
	404	writel(0x0, mt->thermal_base + TEMP_ADCVOLTAGESHIFT);
	405
	406	/* enable auxadc mux write transaction */
	407	writel(TEMP_ADCWRITECTRL_ADC_MUX_WRITE,
eb4fc33e	408	mt->thermal_base + TEMP_ADCWRITECTRL);
a92db1c8 SH	409
	410	for (i = 0; i < cfg->num_sensors; i++)
	411	writel(sensor_mux_values[cfg->sensors[i]],
eb4fc33e	412	mt->thermal_base + sensing_points[i].adcpnp);
a92db1c8 SH	413
	414	writel((1 << cfg->num_sensors) - 1, mt->thermal_base + TEMP_MONCTL0);
	415
eb4fc33e EV	416	writel(TEMP_ADCWRITECTRL_ADC_PNP_WRITE \|
	417	TEMP_ADCWRITECTRL_ADC_MUX_WRITE,
	418	mt->thermal_base + TEMP_ADCWRITECTRL);
a92db1c8 SH	419
	420	mtk_thermal_put_bank(bank);
	421	}
	422
	423	static u64 of_get_phys_base(struct device_node *np)
	424	{
	425	u64 size64;
	426	const __be32 *regaddr_p;
	427
	428	regaddr_p = of_get_address(np, 0, &size64, NULL);
	429	if (!regaddr_p)
	430	return OF_BAD_ADDR;
	431
	432	return of_translate_address(np, regaddr_p);
	433	}
	434
eb4fc33e EV	435	static int mtk_thermal_get_calibration_data(struct device *dev,
eb4fc33e EV	436	struct mtk_thermal *mt)
a92db1c8 SH	437	{
	438	struct nvmem_cell *cell;
	439	u32 *buf;
	440	size_t len;
	441	int i, ret = 0;
	442
	443	/* Start with default values */
	444	mt->adc_ge = 512;
	445	for (i = 0; i < MT8173_NUM_SENSORS; i++)
	446	mt->vts[i] = 260;
	447	mt->degc_cali = 40;
	448	mt->o_slope = 0;
	449
	450	cell = nvmem_cell_get(dev, "calibration-data");
	451	if (IS_ERR(cell)) {
	452	if (PTR_ERR(cell) == -EPROBE_DEFER)
	453	return PTR_ERR(cell);
	454	return 0;
	455	}
	456
	457	buf = (u32 *)nvmem_cell_read(cell, &len);
	458
	459	nvmem_cell_put(cell);
	460
	461	if (IS_ERR(buf))
	462	return PTR_ERR(buf);
	463
	464	if (len < 3 * sizeof(u32)) {
	465	dev_warn(dev, "invalid calibration data\n");
	466	ret = -EINVAL;
	467	goto out;
	468	}
	469
	470	if (buf[0] & MT8173_CALIB_BUF0_VALID) {
	471	mt->adc_ge = MT8173_CALIB_BUF1_ADC_GE(buf[1]);
	472	mt->vts[MT8173_TS1] = MT8173_CALIB_BUF0_VTS_TS1(buf[0]);
	473	mt->vts[MT8173_TS2] = MT8173_CALIB_BUF0_VTS_TS2(buf[0]);
	474	mt->vts[MT8173_TS3] = MT8173_CALIB_BUF1_VTS_TS3(buf[1]);
	475	mt->vts[MT8173_TS4] = MT8173_CALIB_BUF2_VTS_TS4(buf[2]);
	476	mt->vts[MT8173_TSABB] = MT8173_CALIB_BUF2_VTS_TSABB(buf[2]);
	477	mt->degc_cali = MT8173_CALIB_BUF0_DEGC_CALI(buf[0]);
	478	mt->o_slope = MT8173_CALIB_BUF0_O_SLOPE(buf[0]);
	479	} else {
	480	dev_info(dev, "Device not calibrated, using default calibration values\n");
	481	}
	482
	483	out:
	484	kfree(buf);
	485
	486	return ret;
	487	}
	488
	489	static int mtk_thermal_probe(struct platform_device *pdev)
	490	{
	491	int ret, i;
	492	struct device_node auxadc, apmixedsys, *np = pdev->dev.of_node;
	493	struct mtk_thermal *mt;
	494	struct resource *res;
	495	u64 auxadc_phys_base, apmixed_phys_base;
	496
	497	mt = devm_kzalloc(&pdev->dev, sizeof(*mt), GFP_KERNEL);
	498	if (!mt)
	499	return -ENOMEM;
	500
501	mt->clk_peri_therm = devm_clk_get(&pdev->dev, "therm");
502	if (IS_ERR(mt->clk_peri_therm))
503	return PTR_ERR(mt->clk_peri_therm);
504
505	mt->clk_auxadc = devm_clk_get(&pdev->dev, "auxadc");
506	if (IS_ERR(mt->clk_auxadc))
507	return PTR_ERR(mt->clk_auxadc);
508
509	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
510	mt->thermal_base = devm_ioremap_resource(&pdev->dev, res);
511	if (IS_ERR(mt->thermal_base))
512	return PTR_ERR(mt->thermal_base);
513
514	ret = mtk_thermal_get_calibration_data(&pdev->dev, mt);
515	if (ret)
516	return ret;
517
518	mutex_init(&mt->lock);
519
520	mt->dev = &pdev->dev;
521
522	auxadc = of_parse_phandle(np, "mediatek,auxadc", 0);
523	if (!auxadc) {
524	dev_err(&pdev->dev, "missing auxadc node\n");
525	return -ENODEV;
526	}
527
528	auxadc_phys_base = of_get_phys_base(auxadc);
529
530	of_node_put(auxadc);
531
532	if (auxadc_phys_base == OF_BAD_ADDR) {
533	dev_err(&pdev->dev, "Can't get auxadc phys address\n");
534	return -EINVAL;
535	}
536
537	apmixedsys = of_parse_phandle(np, "mediatek,apmixedsys", 0);
538	if (!apmixedsys) {
539	dev_err(&pdev->dev, "missing apmixedsys node\n");
540	return -ENODEV;
541	}
542
543	apmixed_phys_base = of_get_phys_base(apmixedsys);
544
545	of_node_put(apmixedsys);
546
547	if (apmixed_phys_base == OF_BAD_ADDR) {
548	dev_err(&pdev->dev, "Can't get auxadc phys address\n");
549	return -EINVAL;
550	}
551
552	ret = clk_prepare_enable(mt->clk_auxadc);
553	if (ret) {
554	dev_err(&pdev->dev, "Can't enable auxadc clk: %d\n", ret);
555	return ret;
556	}
557
558	ret = device_reset(&pdev->dev);
559	if (ret)
560	goto err_disable_clk_auxadc;
561
562	ret = clk_prepare_enable(mt->clk_peri_therm);
563	if (ret) {
564	dev_err(&pdev->dev, "Can't enable peri clk: %d\n", ret);
565	goto err_disable_clk_auxadc;
566	}
567
568	for (i = 0; i < MT8173_NUM_ZONES; i++)
eb4fc33e EV	569	mtk_thermal_init_bank(mt, i, apmixed_phys_base,
eb4fc33e EV	570	auxadc_phys_base);
a92db1c8 SH	571
	572	platform_set_drvdata(pdev, mt);
	573
c417bded EV	574	devm_thermal_zone_of_sensor_register(&pdev->dev, 0, mt,
c417bded EV	575	&mtk_thermal_ops);
a92db1c8 SH	576
	577	return 0;
	578
a92db1c8 SH	579	err_disable_clk_auxadc:
	580	clk_disable_unprepare(mt->clk_auxadc);
	581
	582	return ret;
	583	}
	584
	585	static int mtk_thermal_remove(struct platform_device *pdev)
	586	{
	587	struct mtk_thermal *mt = platform_get_drvdata(pdev);
	588
a92db1c8 SH	589	clk_disable_unprepare(mt->clk_peri_therm);
	590	clk_disable_unprepare(mt->clk_auxadc);
	591
	592	return 0;
	593	}
	594
	595	static const struct of_device_id mtk_thermal_of_match[] = {
	596	{
	597	.compatible = "mediatek,mt8173-thermal",
	598	}, {
	599	},
	600	};
	601
	602	static struct platform_driver mtk_thermal_driver = {
	603	.probe = mtk_thermal_probe,
	604	.remove = mtk_thermal_remove,
	605	.driver = {
	606	.name = THERMAL_NAME,
	607	.of_match_table = mtk_thermal_of_match,
	608	},
	609	};
	610
	611	module_platform_driver(mtk_thermal_driver);
	612
9ebfb4e0	613	MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
a92db1c8 SH	614	MODULE_AUTHOR("Hanyi Wu <hanyi.wu@mediatek.com>");
	615	MODULE_DESCRIPTION("Mediatek thermal driver");
	616	MODULE_LICENSE("GPL v2");