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Merge branch 'pm-cpufreq'
[linux-2.6-block.git] / drivers / staging / rtl8188eu / hal / bb_cfg.c
CommitLineData
c59c7267
LF		 1/******************************************************************************
2*
3* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
4*
5* This program is free software; you can redistribute it and/or modify it
6* under the terms of version 2 of the GNU General Public License as
7* published by the Free Software Foundation.
8*
9* This program is distributed in the hope that it will be useful, but WITHOUT
10* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12* more details.
13*
14* You should have received a copy of the GNU General Public License along with
15* this program; if not, write to the Free Software Foundation, Inc.,
16* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17*
18*
19******************************************************************************/
20
21#include "odm_precomp.h"
22
9c7d45c2 23#include <phy.h>
c59c7267
LF		 24
25#define read_next_pair(array, v1, v2, i) \
26 do { \
cfa48d93
MB		 27 i += 2; \
28 v1 = array[i]; \
29 v2 = array[i+1]; \
c59c7267
LF		 30 } while (0)
31
c59c7267 32
9c7d45c2 33/* AGC_TAB_1T.TXT */
c59c7267
LF		 34
35static u32 array_agc_tab_1t_8188e[] = {
36 0xC78, 0xFB000001,
37 0xC78, 0xFB010001,
38 0xC78, 0xFB020001,
39 0xC78, 0xFB030001,
40 0xC78, 0xFB040001,
41 0xC78, 0xFB050001,
42 0xC78, 0xFA060001,
43 0xC78, 0xF9070001,
44 0xC78, 0xF8080001,
45 0xC78, 0xF7090001,
46 0xC78, 0xF60A0001,
47 0xC78, 0xF50B0001,
48 0xC78, 0xF40C0001,
49 0xC78, 0xF30D0001,
50 0xC78, 0xF20E0001,
51 0xC78, 0xF10F0001,
52 0xC78, 0xF0100001,
53 0xC78, 0xEF110001,
54 0xC78, 0xEE120001,
55 0xC78, 0xED130001,
56 0xC78, 0xEC140001,
57 0xC78, 0xEB150001,
58 0xC78, 0xEA160001,
59 0xC78, 0xE9170001,
60 0xC78, 0xE8180001,
61 0xC78, 0xE7190001,
62 0xC78, 0xE61A0001,
63 0xC78, 0xE51B0001,
64 0xC78, 0xE41C0001,
65 0xC78, 0xE31D0001,
66 0xC78, 0xE21E0001,
67 0xC78, 0xE11F0001,
68 0xC78, 0x8A200001,
69 0xC78, 0x89210001,
70 0xC78, 0x88220001,
71 0xC78, 0x87230001,
72 0xC78, 0x86240001,
73 0xC78, 0x85250001,
74 0xC78, 0x84260001,
75 0xC78, 0x83270001,
76 0xC78, 0x82280001,
77 0xC78, 0x6B290001,
78 0xC78, 0x6A2A0001,
79 0xC78, 0x692B0001,
80 0xC78, 0x682C0001,
81 0xC78, 0x672D0001,
82 0xC78, 0x662E0001,
83 0xC78, 0x652F0001,
84 0xC78, 0x64300001,
85 0xC78, 0x63310001,
86 0xC78, 0x62320001,
87 0xC78, 0x61330001,
88 0xC78, 0x46340001,
89 0xC78, 0x45350001,
90 0xC78, 0x44360001,
91 0xC78, 0x43370001,
92 0xC78, 0x42380001,
93 0xC78, 0x41390001,
94 0xC78, 0x403A0001,
95 0xC78, 0x403B0001,
96 0xC78, 0x403C0001,
97 0xC78, 0x403D0001,
98 0xC78, 0x403E0001,
99 0xC78, 0x403F0001,
100 0xC78, 0xFB400001,
101 0xC78, 0xFB410001,
102 0xC78, 0xFB420001,
103 0xC78, 0xFB430001,
104 0xC78, 0xFB440001,
105 0xC78, 0xFB450001,
106 0xC78, 0xFB460001,
107 0xC78, 0xFB470001,
108 0xC78, 0xFB480001,
109 0xC78, 0xFA490001,
110 0xC78, 0xF94A0001,
111 0xC78, 0xF84B0001,
112 0xC78, 0xF74C0001,
113 0xC78, 0xF64D0001,
114 0xC78, 0xF54E0001,
115 0xC78, 0xF44F0001,
116 0xC78, 0xF3500001,
117 0xC78, 0xF2510001,
118 0xC78, 0xF1520001,
119 0xC78, 0xF0530001,
120 0xC78, 0xEF540001,
121 0xC78, 0xEE550001,
122 0xC78, 0xED560001,
123 0xC78, 0xEC570001,
124 0xC78, 0xEB580001,
125 0xC78, 0xEA590001,
126 0xC78, 0xE95A0001,
127 0xC78, 0xE85B0001,
128 0xC78, 0xE75C0001,
129 0xC78, 0xE65D0001,
130 0xC78, 0xE55E0001,
131 0xC78, 0xE45F0001,
132 0xC78, 0xE3600001,
133 0xC78, 0xE2610001,
134 0xC78, 0xC3620001,
135 0xC78, 0xC2630001,
136 0xC78, 0xC1640001,
137 0xC78, 0x8B650001,
138 0xC78, 0x8A660001,
139 0xC78, 0x89670001,
140 0xC78, 0x88680001,
141 0xC78, 0x87690001,
142 0xC78, 0x866A0001,
143 0xC78, 0x856B0001,
144 0xC78, 0x846C0001,
145 0xC78, 0x676D0001,
146 0xC78, 0x666E0001,
147 0xC78, 0x656F0001,
148 0xC78, 0x64700001,
149 0xC78, 0x63710001,
150 0xC78, 0x62720001,
151 0xC78, 0x61730001,
152 0xC78, 0x60740001,
153 0xC78, 0x46750001,
154 0xC78, 0x45760001,
155 0xC78, 0x44770001,
156 0xC78, 0x43780001,
157 0xC78, 0x42790001,
158 0xC78, 0x417A0001,
159 0xC78, 0x407B0001,
160 0xC78, 0x407C0001,
161 0xC78, 0x407D0001,
162 0xC78, 0x407E0001,
163 0xC78, 0x407F0001,
164};
165
9c7d45c2 166static bool set_baseband_agc_config(struct adapter *adapt)
c59c7267 167{
9c7d45c2 168 u32 i;
169 u32 arraylen = sizeof(array_agc_tab_1t_8188e)/sizeof(u32);
170 u32 *array = array_agc_tab_1t_8188e;
c59c7267
LF		 171
172 for (i = 0; i < arraylen; i += 2) {
173 u32 v1 = array[i];
174 u32 v2 = array[i+1];
175
422caed9 176 if (v1 < 0xCDCDCDCD) {
9c6db651 177 phy_set_bb_reg(adapt, v1, bMaskDWord, v2);
9c7d45c2 178 udelay(1);
c59c7267
LF		 179 }
180 }
9c7d45c2 181 return true;
c59c7267
LF		 182}
183
9c7d45c2 184/* PHY_REG_1T.TXT */
c59c7267
LF		 185
186static u32 array_phy_reg_1t_8188e[] = {
187 0x800, 0x80040000,
188 0x804, 0x00000003,
189 0x808, 0x0000FC00,
190 0x80C, 0x0000000A,
191 0x810, 0x10001331,
192 0x814, 0x020C3D10,
193 0x818, 0x02200385,
194 0x81C, 0x00000000,
195 0x820, 0x01000100,
196 0x824, 0x00390204,
197 0x828, 0x00000000,
198 0x82C, 0x00000000,
199 0x830, 0x00000000,
200 0x834, 0x00000000,
201 0x838, 0x00000000,
202 0x83C, 0x00000000,
203 0x840, 0x00010000,
204 0x844, 0x00000000,
205 0x848, 0x00000000,
206 0x84C, 0x00000000,
207 0x850, 0x00000000,
208 0x854, 0x00000000,
209 0x858, 0x569A11A9,
210 0x85C, 0x01000014,
211 0x860, 0x66F60110,
212 0x864, 0x061F0649,
213 0x868, 0x00000000,
214 0x86C, 0x27272700,
215 0x870, 0x07000760,
216 0x874, 0x25004000,
217 0x878, 0x00000808,
218 0x87C, 0x00000000,
219 0x880, 0xB0000C1C,
220 0x884, 0x00000001,
221 0x888, 0x00000000,
222 0x88C, 0xCCC000C0,
223 0x890, 0x00000800,
224 0x894, 0xFFFFFFFE,
225 0x898, 0x40302010,
226 0x89C, 0x00706050,
227 0x900, 0x00000000,
228 0x904, 0x00000023,
229 0x908, 0x00000000,
230 0x90C, 0x81121111,
231 0x910, 0x00000002,
232 0x914, 0x00000201,
233 0xA00, 0x00D047C8,
234 0xA04, 0x80FF000C,
235 0xA08, 0x8C838300,
236 0xA0C, 0x2E7F120F,
237 0xA10, 0x9500BB78,
238 0xA14, 0x1114D028,
239 0xA18, 0x00881117,
240 0xA1C, 0x89140F00,
241 0xA20, 0x1A1B0000,
242 0xA24, 0x090E1317,
243 0xA28, 0x00000204,
244 0xA2C, 0x00D30000,
245 0xA70, 0x101FBF00,
246 0xA74, 0x00000007,
247 0xA78, 0x00000900,
248 0xA7C, 0x225B0606,
249 0xA80, 0x218075B1,
250 0xB2C, 0x80000000,
251 0xC00, 0x48071D40,
252 0xC04, 0x03A05611,
253 0xC08, 0x000000E4,
254 0xC0C, 0x6C6C6C6C,
255 0xC10, 0x08800000,
256 0xC14, 0x40000100,
257 0xC18, 0x08800000,
258 0xC1C, 0x40000100,
259 0xC20, 0x00000000,
260 0xC24, 0x00000000,
261 0xC28, 0x00000000,
262 0xC2C, 0x00000000,
263 0xC30, 0x69E9AC47,
264 0xC34, 0x469652AF,
265 0xC38, 0x49795994,
266 0xC3C, 0x0A97971C,
267 0xC40, 0x1F7C403F,
268 0xC44, 0x000100B7,
269 0xC48, 0xEC020107,
270 0xC4C, 0x007F037F,
271 0xC50, 0x69553420,
272 0xC54, 0x43BC0094,
273 0xC58, 0x00013169,
274 0xC5C, 0x00250492,
275 0xC60, 0x00000000,
276 0xC64, 0x7112848B,
277 0xC68, 0x47C00BFF,
278 0xC6C, 0x00000036,
279 0xC70, 0x2C7F000D,
280 0xC74, 0x020610DB,
281 0xC78, 0x0000001F,
282 0xC7C, 0x00B91612,
283 0xC80, 0x390000E4,
284 0xC84, 0x20F60000,
285 0xC88, 0x40000100,
286 0xC8C, 0x20200000,
287 0xC90, 0x00091521,
288 0xC94, 0x00000000,
289 0xC98, 0x00121820,
290 0xC9C, 0x00007F7F,
291 0xCA0, 0x00000000,
292 0xCA4, 0x000300A0,
293 0xCA8, 0x00000000,
294 0xCAC, 0x00000000,
295 0xCB0, 0x00000000,
296 0xCB4, 0x00000000,
297 0xCB8, 0x00000000,
298 0xCBC, 0x28000000,
299 0xCC0, 0x00000000,
300 0xCC4, 0x00000000,
301 0xCC8, 0x00000000,
302 0xCCC, 0x00000000,
303 0xCD0, 0x00000000,
304 0xCD4, 0x00000000,
305 0xCD8, 0x64B22427,
306 0xCDC, 0x00766932,
307 0xCE0, 0x00222222,
308 0xCE4, 0x00000000,
309 0xCE8, 0x37644302,
310 0xCEC, 0x2F97D40C,
311 0xD00, 0x00000740,
312 0xD04, 0x00020401,
313 0xD08, 0x0000907F,
314 0xD0C, 0x20010201,
315 0xD10, 0xA0633333,
316 0xD14, 0x3333BC43,
317 0xD18, 0x7A8F5B6F,
318 0xD2C, 0xCC979975,
319 0xD30, 0x00000000,
320 0xD34, 0x80608000,
321 0xD38, 0x00000000,
322 0xD3C, 0x00127353,
323 0xD40, 0x00000000,
324 0xD44, 0x00000000,
325 0xD48, 0x00000000,
326 0xD4C, 0x00000000,
327 0xD50, 0x6437140A,
328 0xD54, 0x00000000,
329 0xD58, 0x00000282,
330 0xD5C, 0x30032064,
331 0xD60, 0x4653DE68,
332 0xD64, 0x04518A3C,
333 0xD68, 0x00002101,
334 0xD6C, 0x2A201C16,
335 0xD70, 0x1812362E,
336 0xD74, 0x322C2220,
337 0xD78, 0x000E3C24,
338 0xE00, 0x2D2D2D2D,
339 0xE04, 0x2D2D2D2D,
340 0xE08, 0x0390272D,
341 0xE10, 0x2D2D2D2D,
342 0xE14, 0x2D2D2D2D,
343 0xE18, 0x2D2D2D2D,
344 0xE1C, 0x2D2D2D2D,
345 0xE28, 0x00000000,
346 0xE30, 0x1000DC1F,
347 0xE34, 0x10008C1F,
348 0xE38, 0x02140102,
349 0xE3C, 0x681604C2,
350 0xE40, 0x01007C00,
351 0xE44, 0x01004800,
352 0xE48, 0xFB000000,
353 0xE4C, 0x000028D1,
354 0xE50, 0x1000DC1F,
355 0xE54, 0x10008C1F,
356 0xE58, 0x02140102,
357 0xE5C, 0x28160D05,
358 0xE60, 0x00000008,
359 0xE68, 0x001B25A4,
360 0xE6C, 0x00C00014,
361 0xE70, 0x00C00014,
362 0xE74, 0x01000014,
363 0xE78, 0x01000014,
364 0xE7C, 0x01000014,
365 0xE80, 0x01000014,
366 0xE84, 0x00C00014,
367 0xE88, 0x01000014,
368 0xE8C, 0x00C00014,
369 0xED0, 0x00C00014,
370 0xED4, 0x00C00014,
371 0xED8, 0x00C00014,
372 0xEDC, 0x00000014,
373 0xEE0, 0x00000014,
374 0xEEC, 0x01C00014,
375 0xF14, 0x00000003,
376 0xF4C, 0x00000000,
377 0xF00, 0x00000300,
378};
379
9c7d45c2 380static void rtl_bb_delay(struct adapter *adapt, u32 addr, u32 data)
c59c7267 381{
9c7d45c2 382 if (addr == 0xfe) {
383 msleep(50);
384 } else if (addr == 0xfd) {
385 mdelay(5);
386 } else if (addr == 0xfc) {
387 mdelay(1);
388 } else if (addr == 0xfb) {
389 udelay(50);
390 } else if (addr == 0xfa) {
391 udelay(5);
392 } else if (addr == 0xf9) {
393 udelay(1);
394 } else {
9c6db651 395 phy_set_bb_reg(adapt, addr, bMaskDWord, data);
9c7d45c2 396 /* Add 1us delay between BB/RF register setting. */
397 udelay(1);
c59c7267 398 }
9c7d45c2 399}
400
401static bool set_baseband_phy_config(struct adapter *adapt)
402{
403 u32 i;
404 u32 arraylen = sizeof(array_phy_reg_1t_8188e)/sizeof(u32);
405 u32 *array = array_phy_reg_1t_8188e;
c59c7267
LF		 406
407 for (i = 0; i < arraylen; i += 2) {
408 u32 v1 = array[i];
409 u32 v2 = array[i+1];
410
9c7d45c2 411 if (v1 < 0xCDCDCDCD)
412 rtl_bb_delay(adapt, v1, v2);
c59c7267 413 }
9c7d45c2 414 return true;
c59c7267
LF		 415}
416
9c7d45c2 417/* PHY_REG_PG.TXT */
c59c7267
LF		 418
419static u32 array_phy_reg_pg_8188e[] = {
420 0xE00, 0xFFFFFFFF, 0x06070809,
421 0xE04, 0xFFFFFFFF, 0x02020405,
422 0xE08, 0x0000FF00, 0x00000006,
423 0x86C, 0xFFFFFF00, 0x00020400,
424 0xE10, 0xFFFFFFFF, 0x08090A0B,
425 0xE14, 0xFFFFFFFF, 0x01030607,
426 0xE18, 0xFFFFFFFF, 0x08090A0B,
427 0xE1C, 0xFFFFFFFF, 0x01030607,
428 0xE00, 0xFFFFFFFF, 0x00000000,
429 0xE04, 0xFFFFFFFF, 0x00000000,
430 0xE08, 0x0000FF00, 0x00000000,
431 0x86C, 0xFFFFFF00, 0x00000000,
432 0xE10, 0xFFFFFFFF, 0x00000000,
433 0xE14, 0xFFFFFFFF, 0x00000000,
434 0xE18, 0xFFFFFFFF, 0x00000000,
435 0xE1C, 0xFFFFFFFF, 0x00000000,
436 0xE00, 0xFFFFFFFF, 0x02020202,
437 0xE04, 0xFFFFFFFF, 0x00020202,
438 0xE08, 0x0000FF00, 0x00000000,
439 0x86C, 0xFFFFFF00, 0x00000000,
440 0xE10, 0xFFFFFFFF, 0x04040404,
441 0xE14, 0xFFFFFFFF, 0x00020404,
442 0xE18, 0xFFFFFFFF, 0x00000000,
443 0xE1C, 0xFFFFFFFF, 0x00000000,
444 0xE00, 0xFFFFFFFF, 0x02020202,
445 0xE04, 0xFFFFFFFF, 0x00020202,
446 0xE08, 0x0000FF00, 0x00000000,
447 0x86C, 0xFFFFFF00, 0x00000000,
448 0xE10, 0xFFFFFFFF, 0x04040404,
449 0xE14, 0xFFFFFFFF, 0x00020404,
450 0xE18, 0xFFFFFFFF, 0x00000000,
451 0xE1C, 0xFFFFFFFF, 0x00000000,
452 0xE00, 0xFFFFFFFF, 0x00000000,
453 0xE04, 0xFFFFFFFF, 0x00000000,
454 0xE08, 0x0000FF00, 0x00000000,
455 0x86C, 0xFFFFFF00, 0x00000000,
456 0xE10, 0xFFFFFFFF, 0x00000000,
457 0xE14, 0xFFFFFFFF, 0x00000000,
458 0xE18, 0xFFFFFFFF, 0x00000000,
459 0xE1C, 0xFFFFFFFF, 0x00000000,
460 0xE00, 0xFFFFFFFF, 0x02020202,
461 0xE04, 0xFFFFFFFF, 0x00020202,
462 0xE08, 0x0000FF00, 0x00000000,
463 0x86C, 0xFFFFFF00, 0x00000000,
464 0xE10, 0xFFFFFFFF, 0x04040404,
465 0xE14, 0xFFFFFFFF, 0x00020404,
466 0xE18, 0xFFFFFFFF, 0x00000000,
467 0xE1C, 0xFFFFFFFF, 0x00000000,
468 0xE00, 0xFFFFFFFF, 0x00000000,
469 0xE04, 0xFFFFFFFF, 0x00000000,
470 0xE08, 0x0000FF00, 0x00000000,
471 0x86C, 0xFFFFFF00, 0x00000000,
472 0xE10, 0xFFFFFFFF, 0x00000000,
473 0xE14, 0xFFFFFFFF, 0x00000000,
474 0xE18, 0xFFFFFFFF, 0x00000000,
475 0xE1C, 0xFFFFFFFF, 0x00000000,
476 0xE00, 0xFFFFFFFF, 0x00000000,
477 0xE04, 0xFFFFFFFF, 0x00000000,
478 0xE08, 0x0000FF00, 0x00000000,
479 0x86C, 0xFFFFFF00, 0x00000000,
480 0xE10, 0xFFFFFFFF, 0x00000000,
481 0xE14, 0xFFFFFFFF, 0x00000000,
482 0xE18, 0xFFFFFFFF, 0x00000000,
483 0xE1C, 0xFFFFFFFF, 0x00000000,
484 0xE00, 0xFFFFFFFF, 0x00000000,
485 0xE04, 0xFFFFFFFF, 0x00000000,
486 0xE08, 0x0000FF00, 0x00000000,
487 0x86C, 0xFFFFFF00, 0x00000000,
488 0xE10, 0xFFFFFFFF, 0x00000000,
489 0xE14, 0xFFFFFFFF, 0x00000000,
490 0xE18, 0xFFFFFFFF, 0x00000000,
491 0xE1C, 0xFFFFFFFF, 0x00000000,
492 0xE00, 0xFFFFFFFF, 0x00000000,
493 0xE04, 0xFFFFFFFF, 0x00000000,
494 0xE08, 0x0000FF00, 0x00000000,
495 0x86C, 0xFFFFFF00, 0x00000000,
496 0xE10, 0xFFFFFFFF, 0x00000000,
497 0xE14, 0xFFFFFFFF, 0x00000000,
498 0xE18, 0xFFFFFFFF, 0x00000000,
499 0xE1C, 0xFFFFFFFF, 0x00000000,
500 0xE00, 0xFFFFFFFF, 0x00000000,
501 0xE04, 0xFFFFFFFF, 0x00000000,
502 0xE08, 0x0000FF00, 0x00000000,
503 0x86C, 0xFFFFFF00, 0x00000000,
504 0xE10, 0xFFFFFFFF, 0x00000000,
505 0xE14, 0xFFFFFFFF, 0x00000000,
506 0xE18, 0xFFFFFFFF, 0x00000000,
507 0xE1C, 0xFFFFFFFF, 0x00000000,
508
509};
510
9c7d45c2 511static void store_pwrindex_offset(struct adapter *Adapter, u32 regaddr, u32 bitmask, u32 data)
c59c7267 512{
9c7d45c2 513 struct hal_data_8188e *hal_data = GET_HAL_DATA(Adapter);
3da741ff 514 u8 pwrGrpCnt = hal_data->pwrGroupCnt;
9c7d45c2 515
516 if (regaddr == rTxAGC_A_Rate18_06)
3da741ff 517 hal_data->MCSTxPowerLevelOriginalOffset[pwrGrpCnt][0] = data;
9c7d45c2 518 if (regaddr == rTxAGC_A_Rate54_24)
3da741ff 519 hal_data->MCSTxPowerLevelOriginalOffset[pwrGrpCnt][1] = data;
9c7d45c2 520 if (regaddr == rTxAGC_A_CCK1_Mcs32)
3da741ff 521 hal_data->MCSTxPowerLevelOriginalOffset[pwrGrpCnt][6] = data;
9c7d45c2 522 if (regaddr == rTxAGC_B_CCK11_A_CCK2_11 && bitmask == 0xffffff00)
3da741ff 523 hal_data->MCSTxPowerLevelOriginalOffset[pwrGrpCnt][7] = data;
9c7d45c2 524 if (regaddr == rTxAGC_A_Mcs03_Mcs00)
3da741ff 525 hal_data->MCSTxPowerLevelOriginalOffset[pwrGrpCnt][2] = data;
9c7d45c2 526 if (regaddr == rTxAGC_A_Mcs07_Mcs04)
3da741ff 527 hal_data->MCSTxPowerLevelOriginalOffset[pwrGrpCnt][3] = data;
9c7d45c2 528 if (regaddr == rTxAGC_A_Mcs11_Mcs08)
3da741ff 529 hal_data->MCSTxPowerLevelOriginalOffset[pwrGrpCnt][4] = data;
9c7d45c2 530 if (regaddr == rTxAGC_A_Mcs15_Mcs12) {
3da741ff 531 hal_data->MCSTxPowerLevelOriginalOffset[pwrGrpCnt][5] = data;
9c7d45c2 532 if (hal_data->rf_type == RF_1T1R)
533 hal_data->pwrGroupCnt++;
534 }
535 if (regaddr == rTxAGC_B_Rate18_06)
3da741ff 536 hal_data->MCSTxPowerLevelOriginalOffset[pwrGrpCnt][8] = data;
9c7d45c2 537 if (regaddr == rTxAGC_B_Rate54_24)
3da741ff 538 hal_data->MCSTxPowerLevelOriginalOffset[pwrGrpCnt][9] = data;
9c7d45c2 539 if (regaddr == rTxAGC_B_CCK1_55_Mcs32)
3da741ff 540 hal_data->MCSTxPowerLevelOriginalOffset[pwrGrpCnt][14] = data;
9c7d45c2 541 if (regaddr == rTxAGC_B_CCK11_A_CCK2_11 && bitmask == 0x000000ff)
3da741ff 542 hal_data->MCSTxPowerLevelOriginalOffset[pwrGrpCnt][15] = data;
9c7d45c2 543 if (regaddr == rTxAGC_B_Mcs03_Mcs00)
3da741ff 544 hal_data->MCSTxPowerLevelOriginalOffset[pwrGrpCnt][10] = data;
9c7d45c2 545 if (regaddr == rTxAGC_B_Mcs07_Mcs04)
3da741ff 546 hal_data->MCSTxPowerLevelOriginalOffset[pwrGrpCnt][11] = data;
9c7d45c2 547 if (regaddr == rTxAGC_B_Mcs11_Mcs08)
3da741ff 548 hal_data->MCSTxPowerLevelOriginalOffset[pwrGrpCnt][12] = data;
9c7d45c2 549 if (regaddr == rTxAGC_B_Mcs15_Mcs12) {
3da741ff 550 hal_data->MCSTxPowerLevelOriginalOffset[pwrGrpCnt][13] = data;
9c7d45c2 551 if (hal_data->rf_type != RF_1T1R)
552 hal_data->pwrGroupCnt++;
553 }
554}
c59c7267 555
e790d442
VH		 556static void rtl_addr_delay(struct adapter *adapt,
557 u32 addr, u32 bit_mask, u32 data)
9c7d45c2 558{
e790d442
VH		 559 switch (addr) {
560 case 0xfe:
9c7d45c2 561 msleep(50);
e790d442
VH		 562 break;
563 case 0xfd:
9c7d45c2 564 mdelay(5);
e790d442
VH		 565 break;
566 case 0xfc:
9c7d45c2 567 mdelay(1);
e790d442
VH		 568 break;
569 case 0xfb:
9c7d45c2 570 udelay(50);
e790d442
VH		 571 break;
572 case 0xfa:
9c7d45c2 573 udelay(5);
e790d442
VH		 574 break;
575 case 0xf9:
9c7d45c2 576 udelay(1);
e790d442
VH		 577 break;
578 default:
9c7d45c2 579 store_pwrindex_offset(adapt, addr, bit_mask, data);
580 }
581}
582
583static bool config_bb_with_pgheader(struct adapter *adapt)
584{
585 u32 i = 0;
586 u32 arraylen = sizeof(array_phy_reg_pg_8188e) / sizeof(u32);
587 u32 *array = array_phy_reg_pg_8188e;
c59c7267
LF		 588
589 for (i = 0; i < arraylen; i += 3) {
590 u32 v1 = array[i];
591 u32 v2 = array[i+1];
592 u32 v3 = array[i+2];
593
9c7d45c2 594 if (v1 < 0xCDCDCDCD)
595 rtl_addr_delay(adapt, v1, v2, v3);
596 }
597 return true;
598}
599
600static void rtl88e_phy_init_bb_rf_register_definition(struct adapter *Adapter)
601{
602 struct hal_data_8188e *hal_data = GET_HAL_DATA(Adapter);
fe36bad2
VH		 603 struct bb_reg_def *reg[4];
604
605 reg[RF_PATH_A] = &(hal_data->PHYRegDef[RF_PATH_A]);
606 reg[RF_PATH_B] = &(hal_data->PHYRegDef[RF_PATH_B]);
607 reg[RF_PATH_C] = &(hal_data->PHYRegDef[RF_PATH_C]);
608 reg[RF_PATH_D] = &(hal_data->PHYRegDef[RF_PATH_D]);
609
610 reg[RF_PATH_A]->rfintfs = rFPGA0_XAB_RFInterfaceSW;
611 reg[RF_PATH_B]->rfintfs = rFPGA0_XAB_RFInterfaceSW;
612 reg[RF_PATH_C]->rfintfs = rFPGA0_XCD_RFInterfaceSW;
613 reg[RF_PATH_D]->rfintfs = rFPGA0_XCD_RFInterfaceSW;
614
615 reg[RF_PATH_A]->rfintfi = rFPGA0_XAB_RFInterfaceRB;
616 reg[RF_PATH_B]->rfintfi = rFPGA0_XAB_RFInterfaceRB;
617 reg[RF_PATH_C]->rfintfi = rFPGA0_XCD_RFInterfaceRB;
618 reg[RF_PATH_D]->rfintfi = rFPGA0_XCD_RFInterfaceRB;
619
620 reg[RF_PATH_A]->rfintfo = rFPGA0_XA_RFInterfaceOE;
621 reg[RF_PATH_B]->rfintfo = rFPGA0_XB_RFInterfaceOE;
622
623 reg[RF_PATH_A]->rfintfe = rFPGA0_XA_RFInterfaceOE;
624 reg[RF_PATH_B]->rfintfe = rFPGA0_XB_RFInterfaceOE;
625
626 reg[RF_PATH_A]->rf3wireOffset = rFPGA0_XA_LSSIParameter;
627 reg[RF_PATH_B]->rf3wireOffset = rFPGA0_XB_LSSIParameter;
628
629 reg[RF_PATH_A]->rfLSSI_Select = rFPGA0_XAB_RFParameter;
630 reg[RF_PATH_B]->rfLSSI_Select = rFPGA0_XAB_RFParameter;
631 reg[RF_PATH_C]->rfLSSI_Select = rFPGA0_XCD_RFParameter;
632 reg[RF_PATH_D]->rfLSSI_Select = rFPGA0_XCD_RFParameter;
633
634 reg[RF_PATH_A]->rfTxGainStage = rFPGA0_TxGainStage;
635 reg[RF_PATH_B]->rfTxGainStage = rFPGA0_TxGainStage;
636 reg[RF_PATH_C]->rfTxGainStage = rFPGA0_TxGainStage;
637 reg[RF_PATH_D]->rfTxGainStage = rFPGA0_TxGainStage;
638
639 reg[RF_PATH_A]->rfHSSIPara1 = rFPGA0_XA_HSSIParameter1;
640 reg[RF_PATH_B]->rfHSSIPara1 = rFPGA0_XB_HSSIParameter1;
641
642 reg[RF_PATH_A]->rfHSSIPara2 = rFPGA0_XA_HSSIParameter2;
643 reg[RF_PATH_B]->rfHSSIPara2 = rFPGA0_XB_HSSIParameter2;
644
645 reg[RF_PATH_A]->rfSwitchControl = rFPGA0_XAB_SwitchControl;
646 reg[RF_PATH_B]->rfSwitchControl = rFPGA0_XAB_SwitchControl;
647 reg[RF_PATH_C]->rfSwitchControl = rFPGA0_XCD_SwitchControl;
648 reg[RF_PATH_D]->rfSwitchControl = rFPGA0_XCD_SwitchControl;
649
650 reg[RF_PATH_A]->rfAGCControl1 = rOFDM0_XAAGCCore1;
651 reg[RF_PATH_B]->rfAGCControl1 = rOFDM0_XBAGCCore1;
652 reg[RF_PATH_C]->rfAGCControl1 = rOFDM0_XCAGCCore1;
653 reg[RF_PATH_D]->rfAGCControl1 = rOFDM0_XDAGCCore1;
654
655 reg[RF_PATH_A]->rfAGCControl2 = rOFDM0_XAAGCCore2;
656 reg[RF_PATH_B]->rfAGCControl2 = rOFDM0_XBAGCCore2;
657 reg[RF_PATH_C]->rfAGCControl2 = rOFDM0_XCAGCCore2;
658 reg[RF_PATH_D]->rfAGCControl2 = rOFDM0_XDAGCCore2;
659
660 reg[RF_PATH_A]->rfRxIQImbalance = rOFDM0_XARxIQImbalance;
661 reg[RF_PATH_B]->rfRxIQImbalance = rOFDM0_XBRxIQImbalance;
662 reg[RF_PATH_C]->rfRxIQImbalance = rOFDM0_XCRxIQImbalance;
663 reg[RF_PATH_D]->rfRxIQImbalance = rOFDM0_XDRxIQImbalance;
664
665 reg[RF_PATH_A]->rfRxAFE = rOFDM0_XARxAFE;
666 reg[RF_PATH_B]->rfRxAFE = rOFDM0_XBRxAFE;
667 reg[RF_PATH_C]->rfRxAFE = rOFDM0_XCRxAFE;
668 reg[RF_PATH_D]->rfRxAFE = rOFDM0_XDRxAFE;
669
670 reg[RF_PATH_A]->rfTxIQImbalance = rOFDM0_XATxIQImbalance;
671 reg[RF_PATH_B]->rfTxIQImbalance = rOFDM0_XBTxIQImbalance;
672 reg[RF_PATH_C]->rfTxIQImbalance = rOFDM0_XCTxIQImbalance;
673 reg[RF_PATH_D]->rfTxIQImbalance = rOFDM0_XDTxIQImbalance;
674
675 reg[RF_PATH_A]->rfTxAFE = rOFDM0_XATxAFE;
676 reg[RF_PATH_B]->rfTxAFE = rOFDM0_XBTxAFE;
677 reg[RF_PATH_C]->rfTxAFE = rOFDM0_XCTxAFE;
678 reg[RF_PATH_D]->rfTxAFE = rOFDM0_XDTxAFE;
679
680 reg[RF_PATH_A]->rfLSSIReadBack = rFPGA0_XA_LSSIReadBack;
681 reg[RF_PATH_B]->rfLSSIReadBack = rFPGA0_XB_LSSIReadBack;
682 reg[RF_PATH_C]->rfLSSIReadBack = rFPGA0_XC_LSSIReadBack;
683 reg[RF_PATH_D]->rfLSSIReadBack = rFPGA0_XD_LSSIReadBack;
684
685 reg[RF_PATH_A]->rfLSSIReadBackPi = TransceiverA_HSPI_Readback;
686 reg[RF_PATH_B]->rfLSSIReadBackPi = TransceiverB_HSPI_Readback;
9c7d45c2 687}
688
689static bool config_parafile(struct adapter *adapt)
690{
691 struct eeprom_priv *pEEPROM = GET_EEPROM_EFUSE_PRIV(adapt);
692 struct hal_data_8188e *hal_data = GET_HAL_DATA(adapt);
693
694 set_baseband_phy_config(adapt);
695
696 /* If EEPROM or EFUSE autoload OK, We must config by PHY_REG_PG.txt */
697 if (!pEEPROM->bautoload_fail_flag) {
698 hal_data->pwrGroupCnt = 0;
699 config_bb_with_pgheader(adapt);
c59c7267 700 }
9c7d45c2 701 set_baseband_agc_config(adapt);
702 return true;
703}
704
90d88de8 705bool rtl88eu_phy_bb_config(struct adapter *adapt)
9c7d45c2 706{
707 int rtstatus = true;
708 struct hal_data_8188e *hal_data = GET_HAL_DATA(adapt);
709 u32 regval;
710 u8 crystal_cap;
711
712 rtl88e_phy_init_bb_rf_register_definition(adapt);
713
714 /* Enable BB and RF */
715 regval = usb_read16(adapt, REG_SYS_FUNC_EN);
716 usb_write16(adapt, REG_SYS_FUNC_EN, (u16)(regval|BIT13|BIT0|BIT1));
717
718 usb_write8(adapt, REG_RF_CTRL, RF_EN|RF_RSTB|RF_SDMRSTB);
719
720 usb_write8(adapt, REG_SYS_FUNC_EN, FEN_USBA | FEN_USBD | FEN_BB_GLB_RSTn | FEN_BBRSTB);
721
722 /* Config BB and AGC */
723 rtstatus = config_parafile(adapt);
724
725 /* write 0x24[16:11] = 0x24[22:17] = crystal_cap */
726 crystal_cap = hal_data->CrystalCap & 0x3F;
9c6db651 727 phy_set_bb_reg(adapt, REG_AFE_XTAL_CTRL, 0x7ff800, (crystal_cap | (crystal_cap << 6)));
9c7d45c2 728
729 return rtstatus;
c59c7267 730}
Linux 6.x block layer and io_uring tree(s)