[linux-2.6-block.git] / drivers / staging / goldfish / goldfish_nand.c

/*
 * drivers/mtd/devices/goldfish_nand.c
 *
 * Copyright (C) 2007 Google, Inc.
 * Copyright (C) 2012 Intel, Inc.
 * Copyright (C) 2013 Intel, Inc.
 *
 * This software is licensed under the terms of the GNU General Public
 * License version 2, as published by the Free Software Foundation, and
 * may be copied, distributed, and modified under those terms.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 */

#include <linux/io.h>
#include <linux/device.h>
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/ioport.h>
#include <linux/vmalloc.h>
#include <linux/mtd/mtd.h>
#include <linux/platform_device.h>
#include <linux/mutex.h>
#include <linux/goldfish.h>
#include <asm/div64.h>
#include <linux/dma-mapping.h>

#include "goldfish_nand_reg.h"

struct goldfish_nand {
	/* lock protects access to the device registers */
	struct mutex            lock;
	unsigned char __iomem  *base;
	struct cmd_params       *cmd_params;
	size_t                  mtd_count;
	struct mtd_info         mtd[0];
};

static u32 goldfish_nand_cmd_with_params(struct mtd_info *mtd,
					 enum nand_cmd cmd, u64 addr, u32 len,
					 void *ptr, u32 *rv)
{
	u32 cmdp;
	struct goldfish_nand *nand = mtd->priv;
	struct cmd_params *cps = nand->cmd_params;
	unsigned char __iomem  *base = nand->base;

	if (!cps)
		return -1;

	switch (cmd) {
	case NAND_CMD_ERASE:
		cmdp = NAND_CMD_ERASE_WITH_PARAMS;
		break;
	case NAND_CMD_READ:
		cmdp = NAND_CMD_READ_WITH_PARAMS;
		break;
	case NAND_CMD_WRITE:
		cmdp = NAND_CMD_WRITE_WITH_PARAMS;
		break;
	default:
		return -1;
	}
	cps->dev = mtd - nand->mtd;
	cps->addr_high = (u32)(addr >> 32);
	cps->addr_low = (u32)addr;
	cps->transfer_size = len;
	cps->data = (unsigned long)ptr;
	writel(cmdp, base + NAND_COMMAND);
	*rv = cps->result;
	return 0;
}

static u32 goldfish_nand_cmd(struct mtd_info *mtd, enum nand_cmd cmd,
			     u64 addr, u32 len, void *ptr)
{
	struct goldfish_nand *nand = mtd->priv;
	u32 rv;
	unsigned char __iomem  *base = nand->base;

	mutex_lock(&nand->lock);
	if (goldfish_nand_cmd_with_params(mtd, cmd, addr, len, ptr, &rv)) {
		writel(mtd - nand->mtd, base + NAND_DEV);
		writel((u32)(addr >> 32), base + NAND_ADDR_HIGH);
		writel((u32)addr, base + NAND_ADDR_LOW);
		writel(len, base + NAND_TRANSFER_SIZE);
		gf_write_ptr(ptr, base + NAND_DATA, base + NAND_DATA_HIGH);
		writel(cmd, base + NAND_COMMAND);
		rv = readl(base + NAND_RESULT);
	}
	mutex_unlock(&nand->lock);
	return rv;
}

static int goldfish_nand_erase(struct mtd_info *mtd, struct erase_info *instr)
{
	loff_t ofs = instr->addr;
	u32 len = instr->len;
	s32 rem;

	if (ofs + len > mtd->size)
		goto invalid_arg;
	ofs = div_s64_rem(ofs, mtd->writesize, &rem);
	if (rem)
		goto invalid_arg;
	ofs *= (mtd->writesize + mtd->oobsize);

	if (len % mtd->writesize)
		goto invalid_arg;
	len = len / mtd->writesize * (mtd->writesize + mtd->oobsize);

	if (goldfish_nand_cmd(mtd, NAND_CMD_ERASE, ofs, len, NULL) != len) {
		pr_err("goldfish_nand_erase: erase failed, start %llx, len %x, dev_size %llx, erase_size %x\n",
		       ofs, len, mtd->size, mtd->erasesize);
		return -EIO;
	}

	instr->state = MTD_ERASE_DONE;
	mtd_erase_callback(instr);

	return 0;

invalid_arg:
	pr_err("goldfish_nand_erase: invalid erase, start %llx, len %x, dev_size %llx, erase_size %x\n",
	       ofs, len, mtd->size, mtd->erasesize);
	return -EINVAL;
}

static int goldfish_nand_read_oob(struct mtd_info *mtd, loff_t ofs,
				  struct mtd_oob_ops *ops)
{
	s32 rem;

	if (ofs + ops->len > mtd->size)
		goto invalid_arg;
	if (ops->datbuf && ops->len && ops->len != mtd->writesize)
		goto invalid_arg;
	if (ops->ooblen + ops->ooboffs > mtd->oobsize)
		goto invalid_arg;

	ofs = div_s64_rem(ofs, mtd->writesize, &rem);
	if (rem)
		goto invalid_arg;
	ofs *= (mtd->writesize + mtd->oobsize);

	if (ops->datbuf)
		ops->retlen = goldfish_nand_cmd(mtd, NAND_CMD_READ, ofs,
						ops->len, ops->datbuf);
	ofs += mtd->writesize + ops->ooboffs;
	if (ops->oobbuf)
		ops->oobretlen = goldfish_nand_cmd(mtd, NAND_CMD_READ, ofs,
						ops->ooblen, ops->oobbuf);
	return 0;

invalid_arg:
	pr_err("goldfish_nand_read_oob: invalid read, start %llx, len %zx, ooblen %zx, dev_size %llx, write_size %x\n",
	       ofs, ops->len, ops->ooblen, mtd->size, mtd->writesize);
	return -EINVAL;
}

static int goldfish_nand_write_oob(struct mtd_info *mtd, loff_t ofs,
				   struct mtd_oob_ops *ops)
{
	s32 rem;

	if (ofs + ops->len > mtd->size)
		goto invalid_arg;
	if (ops->len && ops->len != mtd->writesize)
		goto invalid_arg;
	if (ops->ooblen + ops->ooboffs > mtd->oobsize)
		goto invalid_arg;

	ofs = div_s64_rem(ofs, mtd->writesize, &rem);
	if (rem)
		goto invalid_arg;
	ofs *= (mtd->writesize + mtd->oobsize);

	if (ops->datbuf)
		ops->retlen = goldfish_nand_cmd(mtd, NAND_CMD_WRITE, ofs,
						ops->len, ops->datbuf);
	ofs += mtd->writesize + ops->ooboffs;
	if (ops->oobbuf)
		ops->oobretlen = goldfish_nand_cmd(mtd, NAND_CMD_WRITE, ofs,
						ops->ooblen, ops->oobbuf);
	return 0;

invalid_arg:
	pr_err("goldfish_nand_write_oob: invalid write, start %llx, len %zx, ooblen %zx, dev_size %llx, write_size %x\n",
	       ofs, ops->len, ops->ooblen, mtd->size, mtd->writesize);
	return -EINVAL;
}

static int goldfish_nand_read(struct mtd_info *mtd, loff_t from, size_t len,
			      size_t *retlen, u_char *buf)
{
	s32 rem;

	if (from + len > mtd->size)
		goto invalid_arg;

	from = div_s64_rem(from, mtd->writesize, &rem);
	if (rem)
		goto invalid_arg;
	from *= (mtd->writesize + mtd->oobsize);

	*retlen = goldfish_nand_cmd(mtd, NAND_CMD_READ, from, len, buf);
	return 0;

invalid_arg:
	pr_err("goldfish_nand_read: invalid read, start %llx, len %zx, dev_size %llx, write_size %x\n",
	       from, len, mtd->size, mtd->writesize);
	return -EINVAL;
}

static int goldfish_nand_write(struct mtd_info *mtd, loff_t to, size_t len,
			       size_t *retlen, const u_char *buf)
{
	s32 rem;

	if (to + len > mtd->size)
		goto invalid_arg;

	to = div_s64_rem(to, mtd->writesize, &rem);
	if (rem)
		goto invalid_arg;
	to *= (mtd->writesize + mtd->oobsize);

	*retlen = goldfish_nand_cmd(mtd, NAND_CMD_WRITE, to, len, (void *)buf);
	return 0;

invalid_arg:
	pr_err("goldfish_nand_write: invalid write, start %llx, len %zx, dev_size %llx, write_size %x\n",
	       to, len, mtd->size, mtd->writesize);
	return -EINVAL;
}

static int goldfish_nand_block_isbad(struct mtd_info *mtd, loff_t ofs)
{
	s32 rem;

	if (ofs >= mtd->size)
		goto invalid_arg;

	ofs = div_s64_rem(ofs, mtd->writesize, &rem);
	if (rem)
		goto invalid_arg;
	ofs *= mtd->erasesize / mtd->writesize;
	ofs *= (mtd->writesize + mtd->oobsize);

	return goldfish_nand_cmd(mtd, NAND_CMD_BLOCK_BAD_GET, ofs, 0, NULL);

invalid_arg:
	pr_err("goldfish_nand_block_isbad: invalid arg, ofs %llx, dev_size %llx, write_size %x\n",
	       ofs, mtd->size, mtd->writesize);
	return -EINVAL;
}

static int goldfish_nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
{
	s32 rem;

	if (ofs >= mtd->size)
		goto invalid_arg;

	ofs = div_s64_rem(ofs, mtd->writesize, &rem);
	if (rem)
		goto invalid_arg;
	ofs *= mtd->erasesize / mtd->writesize;
	ofs *= (mtd->writesize + mtd->oobsize);

	if (goldfish_nand_cmd(mtd, NAND_CMD_BLOCK_BAD_SET, ofs, 0, NULL) != 1)
		return -EIO;
	return 0;

invalid_arg:
	pr_err("goldfish_nand_block_markbad: invalid arg, ofs %llx, dev_size %llx, write_size %x\n",
	       ofs, mtd->size, mtd->writesize);
	return -EINVAL;
}

static int nand_setup_cmd_params(struct platform_device *pdev,
				 struct goldfish_nand *nand)
{
	dma_addr_t dma_handle;
	unsigned char __iomem  *base = nand->base;

	nand->cmd_params = dmam_alloc_coherent(&pdev->dev,
					       sizeof(struct cmd_params),
					       &dma_handle, GFP_KERNEL);
	if (!nand->cmd_params) {
		dev_err(&pdev->dev, "allocate buffer failed\n");
		return -ENOMEM;
	}
	writel((u32)((u64)dma_handle >> 32), base + NAND_CMD_PARAMS_ADDR_HIGH);
	writel((u32)dma_handle, base + NAND_CMD_PARAMS_ADDR_LOW);
	return 0;
}

static int goldfish_nand_init_device(struct platform_device *pdev,
				     struct goldfish_nand *nand, int id)
{
	u32 name_len;
	u32 result;
	u32 flags;
	unsigned char __iomem  *base = nand->base;
	struct mtd_info *mtd = &nand->mtd[id];
	char *name;

	mutex_lock(&nand->lock);
	writel(id, base + NAND_DEV);
	flags = readl(base + NAND_DEV_FLAGS);
	name_len = readl(base + NAND_DEV_NAME_LEN);
	mtd->writesize = readl(base + NAND_DEV_PAGE_SIZE);
	mtd->size = readl(base + NAND_DEV_SIZE_LOW);
	mtd->size |= (u64)readl(base + NAND_DEV_SIZE_HIGH) << 32;
	mtd->oobsize = readl(base + NAND_DEV_EXTRA_SIZE);
	mtd->oobavail = mtd->oobsize;
	mtd->erasesize = readl(base + NAND_DEV_ERASE_SIZE) /
			(mtd->writesize + mtd->oobsize) * mtd->writesize;
	mtd->size = div_s64(mtd->size, mtd->writesize + mtd->oobsize);
	mtd->size *= mtd->writesize;
	dev_dbg(&pdev->dev,
		"goldfish nand dev%d: size %llx, page %d, extra %d, erase %d\n",
		       id, mtd->size, mtd->writesize,
		       mtd->oobsize, mtd->erasesize);
	mutex_unlock(&nand->lock);

	mtd->priv = nand;

	name = devm_kzalloc(&pdev->dev, name_len + 1, GFP_KERNEL);
	if (!name)
		return -ENOMEM;
	mtd->name = name;

	result = goldfish_nand_cmd(mtd, NAND_CMD_GET_DEV_NAME, 0, name_len,
				   name);
	if (result != name_len) {
		dev_err(&pdev->dev,
			"goldfish_nand_init_device failed to get dev name %d != %d\n",
			       result, name_len);
		return -ENODEV;
	}
	((char *)mtd->name)[name_len] = '\0';

	/* Setup the MTD structure */
	mtd->type = MTD_NANDFLASH;
	mtd->flags = MTD_CAP_NANDFLASH;
	if (flags & NAND_DEV_FLAG_READ_ONLY)
		mtd->flags &= ~MTD_WRITEABLE;
	if (flags & NAND_DEV_FLAG_CMD_PARAMS_CAP)
		nand_setup_cmd_params(pdev, nand);

	mtd->owner = THIS_MODULE;
	mtd->_erase = goldfish_nand_erase;
	mtd->_read = goldfish_nand_read;
	mtd->_write = goldfish_nand_write;
	mtd->_read_oob = goldfish_nand_read_oob;
	mtd->_write_oob = goldfish_nand_write_oob;
	mtd->_block_isbad = goldfish_nand_block_isbad;
	mtd->_block_markbad = goldfish_nand_block_markbad;

	if (mtd_device_register(mtd, NULL, 0))
		return -EIO;

	return 0;
}

static int goldfish_nand_probe(struct platform_device *pdev)
{
	u32 num_dev;
	int i;
	int err;
	u32 num_dev_working;
	u32 version;
	struct resource *r;
	struct goldfish_nand *nand;
	unsigned char __iomem  *base;

	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!r)
		return -ENODEV;

	base = devm_ioremap(&pdev->dev, r->start, PAGE_SIZE);
	if (!base)
		return -ENOMEM;

	version = readl(base + NAND_VERSION);
	if (version != NAND_VERSION_CURRENT) {
		dev_err(&pdev->dev,
			"goldfish_nand_init: version mismatch, got %d, expected %d\n",
				version, NAND_VERSION_CURRENT);
		return -ENODEV;
	}
	num_dev = readl(base + NAND_NUM_DEV);
	if (num_dev == 0)
		return -ENODEV;

	nand = devm_kzalloc(&pdev->dev, sizeof(*nand) +
				sizeof(struct mtd_info) * num_dev, GFP_KERNEL);
	if (!nand)
		return -ENOMEM;

	mutex_init(&nand->lock);
	nand->base = base;
	nand->mtd_count = num_dev;
	platform_set_drvdata(pdev, nand);

	num_dev_working = 0;
	for (i = 0; i < num_dev; i++) {
		err = goldfish_nand_init_device(pdev, nand, i);
		if (err == 0)
			num_dev_working++;
	}
	if (num_dev_working == 0)
		return -ENODEV;
	return 0;
}

static int goldfish_nand_remove(struct platform_device *pdev)
{
	struct goldfish_nand *nand = platform_get_drvdata(pdev);
	int i;

	for (i = 0; i < nand->mtd_count; i++) {
		if (nand->mtd[i].name)
			mtd_device_unregister(&nand->mtd[i]);
	}
	return 0;
}

static struct platform_driver goldfish_nand_driver = {
	.probe		= goldfish_nand_probe,
	.remove		= goldfish_nand_remove,
	.driver = {
		.name = "goldfish_nand"
	}
};

module_platform_driver(goldfish_nand_driver);
MODULE_LICENSE("GPL");
Commit	Line	Data
8e404fff AH	1	/*
	2	* drivers/mtd/devices/goldfish_nand.c
	3	*
	4	* Copyright (C) 2007 Google, Inc.
	5	* Copyright (C) 2012 Intel, Inc.
	6	* Copyright (C) 2013 Intel, Inc.
	7	*
	8	* This software is licensed under the terms of the GNU General Public
	9	* License version 2, as published by the Free Software Foundation, and
	10	* may be copied, distributed, and modified under those terms.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	*/
	18
	19	#include <linux/io.h>
	20	#include <linux/device.h>
	21	#include <linux/module.h>
	22	#include <linux/slab.h>
	23	#include <linux/ioport.h>
	24	#include <linux/vmalloc.h>
8e404fff AH	25	#include <linux/mtd/mtd.h>
8e404fff AH	26	#include <linux/platform_device.h>
67c20cfb	27	#include <linux/mutex.h>
f6279717	28	#include <linux/goldfish.h>
8e404fff	29	#include <asm/div64.h>
3e2fbc7f	30	#include <linux/dma-mapping.h>
8e404fff AH	31
	32	#include "goldfish_nand_reg.h"
	33
	34	struct goldfish_nand {
2c507415	35	/* lock protects access to the device registers */
67c20cfb	36	struct mutex lock;
8e404fff AH	37	unsigned char __iomem *base;
	38	struct cmd_params *cmd_params;
	39	size_t mtd_count;
	40	struct mtd_info mtd[0];
	41	};
	42
	43	static u32 goldfish_nand_cmd_with_params(struct mtd_info *mtd,
8f52e264 LP	44	enum nand_cmd cmd, u64 addr, u32 len,
8f52e264 LP	45	void ptr, u32 rv)
8e404fff AH	46	{
	47	u32 cmdp;
	48	struct goldfish_nand *nand = mtd->priv;
	49	struct cmd_params *cps = nand->cmd_params;
	50	unsigned char __iomem *base = nand->base;
	51
10d71084	52	if (!cps)
8e404fff AH	53	return -1;
	54
	55	switch (cmd) {
	56	case NAND_CMD_ERASE:
	57	cmdp = NAND_CMD_ERASE_WITH_PARAMS;
	58	break;
	59	case NAND_CMD_READ:
	60	cmdp = NAND_CMD_READ_WITH_PARAMS;
	61	break;
	62	case NAND_CMD_WRITE:
	63	cmdp = NAND_CMD_WRITE_WITH_PARAMS;
	64	break;
	65	default:
	66	return -1;
	67	}
	68	cps->dev = mtd - nand->mtd;
	69	cps->addr_high = (u32)(addr >> 32);
	70	cps->addr_low = (u32)addr;
	71	cps->transfer_size = len;
7f09d4a0	72	cps->data = (unsigned long)ptr;
8e404fff AH	73	writel(cmdp, base + NAND_COMMAND);
	74	*rv = cps->result;
	75	return 0;
	76	}
	77
	78	static u32 goldfish_nand_cmd(struct mtd_info *mtd, enum nand_cmd cmd,
8f52e264	79	u64 addr, u32 len, void *ptr)
8e404fff AH	80	{
	81	struct goldfish_nand *nand = mtd->priv;
	82	u32 rv;
8e404fff AH	83	unsigned char __iomem *base = nand->base;
8e404fff AH	84
67c20cfb	85	mutex_lock(&nand->lock);
8e404fff AH	86	if (goldfish_nand_cmd_with_params(mtd, cmd, addr, len, ptr, &rv)) {
	87	writel(mtd - nand->mtd, base + NAND_DEV);
	88	writel((u32)(addr >> 32), base + NAND_ADDR_HIGH);
	89	writel((u32)addr, base + NAND_ADDR_LOW);
	90	writel(len, base + NAND_TRANSFER_SIZE);
07d783fd	91	gf_write_ptr(ptr, base + NAND_DATA, base + NAND_DATA_HIGH);
8e404fff AH	92	writel(cmd, base + NAND_COMMAND);
	93	rv = readl(base + NAND_RESULT);
	94	}
67c20cfb	95	mutex_unlock(&nand->lock);
8e404fff AH	96	return rv;
	97	}
	98
	99	static int goldfish_nand_erase(struct mtd_info mtd, struct erase_info instr)
	100	{
	101	loff_t ofs = instr->addr;
	102	u32 len = instr->len;
b0e302b4	103	s32 rem;
8e404fff AH	104
	105	if (ofs + len > mtd->size)
	106	goto invalid_arg;
b0e302b4	107	ofs = div_s64_rem(ofs, mtd->writesize, &rem);
8e404fff AH	108	if (rem)
	109	goto invalid_arg;
	110	ofs *= (mtd->writesize + mtd->oobsize);
	111
	112	if (len % mtd->writesize)
	113	goto invalid_arg;
	114	len = len / mtd->writesize * (mtd->writesize + mtd->oobsize);
	115
	116	if (goldfish_nand_cmd(mtd, NAND_CMD_ERASE, ofs, len, NULL) != len) {
	117	pr_err("goldfish_nand_erase: erase failed, start %llx, len %x, dev_size %llx, erase_size %x\n",
8f52e264	118	ofs, len, mtd->size, mtd->erasesize);
8e404fff AH	119	return -EIO;
	120	}
	121
	122	instr->state = MTD_ERASE_DONE;
	123	mtd_erase_callback(instr);
	124
	125	return 0;
	126
	127	invalid_arg:
	128	pr_err("goldfish_nand_erase: invalid erase, start %llx, len %x, dev_size %llx, erase_size %x\n",
8f52e264	129	ofs, len, mtd->size, mtd->erasesize);
8e404fff AH	130	return -EINVAL;
	131	}
	132
	133	static int goldfish_nand_read_oob(struct mtd_info *mtd, loff_t ofs,
8f52e264	134	struct mtd_oob_ops *ops)
8e404fff	135	{
b0e302b4	136	s32 rem;
8e404fff AH	137
	138	if (ofs + ops->len > mtd->size)
	139	goto invalid_arg;
	140	if (ops->datbuf && ops->len && ops->len != mtd->writesize)
	141	goto invalid_arg;
	142	if (ops->ooblen + ops->ooboffs > mtd->oobsize)
	143	goto invalid_arg;
	144
b0e302b4	145	ofs = div_s64_rem(ofs, mtd->writesize, &rem);
8e404fff AH	146	if (rem)
	147	goto invalid_arg;
	148	ofs *= (mtd->writesize + mtd->oobsize);
	149
	150	if (ops->datbuf)
	151	ops->retlen = goldfish_nand_cmd(mtd, NAND_CMD_READ, ofs,
	152	ops->len, ops->datbuf);
	153	ofs += mtd->writesize + ops->ooboffs;
	154	if (ops->oobbuf)
	155	ops->oobretlen = goldfish_nand_cmd(mtd, NAND_CMD_READ, ofs,
	156	ops->ooblen, ops->oobbuf);
	157	return 0;
	158
	159	invalid_arg:
b4fcf48a	160	pr_err("goldfish_nand_read_oob: invalid read, start %llx, len %zx, ooblen %zx, dev_size %llx, write_size %x\n",
8f52e264	161	ofs, ops->len, ops->ooblen, mtd->size, mtd->writesize);
8e404fff AH	162	return -EINVAL;
	163	}
	164
	165	static int goldfish_nand_write_oob(struct mtd_info *mtd, loff_t ofs,
8f52e264	166	struct mtd_oob_ops *ops)
8e404fff	167	{
b0e302b4	168	s32 rem;
8e404fff AH	169
	170	if (ofs + ops->len > mtd->size)
	171	goto invalid_arg;
	172	if (ops->len && ops->len != mtd->writesize)
	173	goto invalid_arg;
	174	if (ops->ooblen + ops->ooboffs > mtd->oobsize)
	175	goto invalid_arg;
	176
b0e302b4	177	ofs = div_s64_rem(ofs, mtd->writesize, &rem);
8e404fff AH	178	if (rem)
	179	goto invalid_arg;
	180	ofs *= (mtd->writesize + mtd->oobsize);
	181
	182	if (ops->datbuf)
	183	ops->retlen = goldfish_nand_cmd(mtd, NAND_CMD_WRITE, ofs,
	184	ops->len, ops->datbuf);
	185	ofs += mtd->writesize + ops->ooboffs;
	186	if (ops->oobbuf)
	187	ops->oobretlen = goldfish_nand_cmd(mtd, NAND_CMD_WRITE, ofs,
	188	ops->ooblen, ops->oobbuf);
	189	return 0;
	190
	191	invalid_arg:
b4fcf48a	192	pr_err("goldfish_nand_write_oob: invalid write, start %llx, len %zx, ooblen %zx, dev_size %llx, write_size %x\n",
8f52e264	193	ofs, ops->len, ops->ooblen, mtd->size, mtd->writesize);
8e404fff AH	194	return -EINVAL;
	195	}
	196
	197	static int goldfish_nand_read(struct mtd_info *mtd, loff_t from, size_t len,
8f52e264	198	size_t retlen, u_char buf)
8e404fff	199	{
b0e302b4	200	s32 rem;
8e404fff AH	201
	202	if (from + len > mtd->size)
	203	goto invalid_arg;
8e404fff	204
b0e302b4	205	from = div_s64_rem(from, mtd->writesize, &rem);
8e404fff AH	206	if (rem)
	207	goto invalid_arg;
	208	from *= (mtd->writesize + mtd->oobsize);
	209
	210	*retlen = goldfish_nand_cmd(mtd, NAND_CMD_READ, from, len, buf);
	211	return 0;
	212
	213	invalid_arg:
b4fcf48a	214	pr_err("goldfish_nand_read: invalid read, start %llx, len %zx, dev_size %llx, write_size %x\n",
8f52e264	215	from, len, mtd->size, mtd->writesize);
8e404fff AH	216	return -EINVAL;
	217	}
	218
	219	static int goldfish_nand_write(struct mtd_info *mtd, loff_t to, size_t len,
8f52e264	220	size_t retlen, const u_char buf)
8e404fff	221	{
b0e302b4	222	s32 rem;
8e404fff AH	223
	224	if (to + len > mtd->size)
	225	goto invalid_arg;
8e404fff	226
b0e302b4	227	to = div_s64_rem(to, mtd->writesize, &rem);
8e404fff AH	228	if (rem)
	229	goto invalid_arg;
	230	to *= (mtd->writesize + mtd->oobsize);
	231
	232	retlen = goldfish_nand_cmd(mtd, NAND_CMD_WRITE, to, len, (void )buf);
	233	return 0;
	234
	235	invalid_arg:
b4fcf48a	236	pr_err("goldfish_nand_write: invalid write, start %llx, len %zx, dev_size %llx, write_size %x\n",
8f52e264	237	to, len, mtd->size, mtd->writesize);
8e404fff AH	238	return -EINVAL;
	239	}
	240
	241	static int goldfish_nand_block_isbad(struct mtd_info *mtd, loff_t ofs)
	242	{
b0e302b4	243	s32 rem;
8e404fff AH	244
	245	if (ofs >= mtd->size)
	246	goto invalid_arg;
	247
b0e302b4	248	ofs = div_s64_rem(ofs, mtd->writesize, &rem);
8e404fff AH	249	if (rem)
	250	goto invalid_arg;
	251	ofs *= mtd->erasesize / mtd->writesize;
	252	ofs *= (mtd->writesize + mtd->oobsize);
	253
	254	return goldfish_nand_cmd(mtd, NAND_CMD_BLOCK_BAD_GET, ofs, 0, NULL);
	255
	256	invalid_arg:
	257	pr_err("goldfish_nand_block_isbad: invalid arg, ofs %llx, dev_size %llx, write_size %x\n",
8f52e264	258	ofs, mtd->size, mtd->writesize);
8e404fff AH	259	return -EINVAL;
	260	}
	261
	262	static int goldfish_nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
	263	{
b0e302b4	264	s32 rem;
8e404fff AH	265
	266	if (ofs >= mtd->size)
	267	goto invalid_arg;
	268
b0e302b4	269	ofs = div_s64_rem(ofs, mtd->writesize, &rem);
8e404fff AH	270	if (rem)
	271	goto invalid_arg;
	272	ofs *= mtd->erasesize / mtd->writesize;
	273	ofs *= (mtd->writesize + mtd->oobsize);
	274
	275	if (goldfish_nand_cmd(mtd, NAND_CMD_BLOCK_BAD_SET, ofs, 0, NULL) != 1)
	276	return -EIO;
	277	return 0;
	278
	279	invalid_arg:
	280	pr_err("goldfish_nand_block_markbad: invalid arg, ofs %llx, dev_size %llx, write_size %x\n",
8f52e264	281	ofs, mtd->size, mtd->writesize);
8e404fff AH	282	return -EINVAL;
	283	}
	284
	285	static int nand_setup_cmd_params(struct platform_device *pdev,
8f52e264	286	struct goldfish_nand *nand)
8e404fff	287	{
3e2fbc7f	288	dma_addr_t dma_handle;
8e404fff AH	289	unsigned char __iomem *base = nand->base;
8e404fff AH	290
3e2fbc7f SB	291	nand->cmd_params = dmam_alloc_coherent(&pdev->dev,
	292	sizeof(struct cmd_params),
	293	&dma_handle, GFP_KERNEL);
	294	if (!nand->cmd_params) {
	295	dev_err(&pdev->dev, "allocate buffer failed\n");
	296	return -ENOMEM;
	297	}
	298	writel((u32)((u64)dma_handle >> 32), base + NAND_CMD_PARAMS_ADDR_HIGH);
	299	writel((u32)dma_handle, base + NAND_CMD_PARAMS_ADDR_LOW);
8e404fff AH	300	return 0;
	301	}
	302
	303	static int goldfish_nand_init_device(struct platform_device *pdev,
8f52e264	304	struct goldfish_nand *nand, int id)
8e404fff AH	305	{
	306	u32 name_len;
	307	u32 result;
	308	u32 flags;
8e404fff AH	309	unsigned char __iomem *base = nand->base;
	310	struct mtd_info *mtd = &nand->mtd[id];
	311	char *name;
	312
67c20cfb	313	mutex_lock(&nand->lock);
8e404fff AH	314	writel(id, base + NAND_DEV);
	315	flags = readl(base + NAND_DEV_FLAGS);
	316	name_len = readl(base + NAND_DEV_NAME_LEN);
	317	mtd->writesize = readl(base + NAND_DEV_PAGE_SIZE);
	318	mtd->size = readl(base + NAND_DEV_SIZE_LOW);
	319	mtd->size \|= (u64)readl(base + NAND_DEV_SIZE_HIGH) << 32;
	320	mtd->oobsize = readl(base + NAND_DEV_EXTRA_SIZE);
	321	mtd->oobavail = mtd->oobsize;
	322	mtd->erasesize = readl(base + NAND_DEV_ERASE_SIZE) /
	323	(mtd->writesize + mtd->oobsize) * mtd->writesize;
b0e302b4	324	mtd->size = div_s64(mtd->size, mtd->writesize + mtd->oobsize);
8e404fff	325	mtd->size *= mtd->writesize;
36270be3	326	dev_dbg(&pdev->dev,
8e404fff	327	"goldfish nand dev%d: size %llx, page %d, extra %d, erase %d\n",
13aa4016 HP	328	id, mtd->size, mtd->writesize,
13aa4016 HP	329	mtd->oobsize, mtd->erasesize);
67c20cfb	330	mutex_unlock(&nand->lock);
8e404fff AH	331
	332	mtd->priv = nand;
	333
1f11b38c	334	name = devm_kzalloc(&pdev->dev, name_len + 1, GFP_KERNEL);
6e3f3bb8	335	if (!name)
8e404fff	336	return -ENOMEM;
1f11b38c	337	mtd->name = name;
8e404fff AH	338
8e404fff AH	339	result = goldfish_nand_cmd(mtd, NAND_CMD_GET_DEV_NAME, 0, name_len,
8f52e264	340	name);
8e404fff	341	if (result != name_len) {
36270be3	342	dev_err(&pdev->dev,
8e404fff AH	343	"goldfish_nand_init_device failed to get dev name %d != %d\n",
	344	result, name_len);
	345	return -ENODEV;
	346	}
1977533a	347	((char *)mtd->name)[name_len] = '\0';
8e404fff AH	348
	349	/* Setup the MTD structure */
	350	mtd->type = MTD_NANDFLASH;
	351	mtd->flags = MTD_CAP_NANDFLASH;
	352	if (flags & NAND_DEV_FLAG_READ_ONLY)
	353	mtd->flags &= ~MTD_WRITEABLE;
	354	if (flags & NAND_DEV_FLAG_CMD_PARAMS_CAP)
	355	nand_setup_cmd_params(pdev, nand);
	356
	357	mtd->owner = THIS_MODULE;
	358	mtd->_erase = goldfish_nand_erase;
	359	mtd->_read = goldfish_nand_read;
	360	mtd->_write = goldfish_nand_write;
	361	mtd->_read_oob = goldfish_nand_read_oob;
	362	mtd->_write_oob = goldfish_nand_write_oob;
	363	mtd->_block_isbad = goldfish_nand_block_isbad;
	364	mtd->_block_markbad = goldfish_nand_block_markbad;
	365
	366	if (mtd_device_register(mtd, NULL, 0))
	367	return -EIO;
	368
	369	return 0;
	370	}
	371
	372	static int goldfish_nand_probe(struct platform_device *pdev)
	373	{
	374	u32 num_dev;
	375	int i;
	376	int err;
	377	u32 num_dev_working;
	378	u32 version;
	379	struct resource *r;
	380	struct goldfish_nand *nand;
	381	unsigned char __iomem *base;
	382
	383	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
10d71084	384	if (!r)
8e404fff AH	385	return -ENODEV;
	386
	387	base = devm_ioremap(&pdev->dev, r->start, PAGE_SIZE);
6e3f3bb8	388	if (!base)
8e404fff AH	389	return -ENOMEM;
	390
	391	version = readl(base + NAND_VERSION);
	392	if (version != NAND_VERSION_CURRENT) {
36270be3	393	dev_err(&pdev->dev,
8e404fff AH	394	"goldfish_nand_init: version mismatch, got %d, expected %d\n",
	395	version, NAND_VERSION_CURRENT);
	396	return -ENODEV;
	397	}
	398	num_dev = readl(base + NAND_NUM_DEV);
	399	if (num_dev == 0)
	400	return -ENODEV;
	401
36270be3	402	nand = devm_kzalloc(&pdev->dev, sizeof(*nand) +
8e404fff	403	sizeof(struct mtd_info) * num_dev, GFP_KERNEL);
6e3f3bb8	404	if (!nand)
8e404fff AH	405	return -ENOMEM;
8e404fff AH	406
67c20cfb	407	mutex_init(&nand->lock);
8e404fff AH	408	nand->base = base;
	409	nand->mtd_count = num_dev;
	410	platform_set_drvdata(pdev, nand);
	411
	412	num_dev_working = 0;
	413	for (i = 0; i < num_dev; i++) {
	414	err = goldfish_nand_init_device(pdev, nand, i);
	415	if (err == 0)
	416	num_dev_working++;
	417	}
	418	if (num_dev_working == 0)
	419	return -ENODEV;
	420	return 0;
	421	}
	422
	423	static int goldfish_nand_remove(struct platform_device *pdev)
	424	{
	425	struct goldfish_nand *nand = platform_get_drvdata(pdev);
	426	int i;
ef323812	427
8e404fff AH	428	for (i = 0; i < nand->mtd_count; i++) {
	429	if (nand->mtd[i].name)
	430	mtd_device_unregister(&nand->mtd[i]);
	431	}
	432	return 0;
	433	}
	434
	435	static struct platform_driver goldfish_nand_driver = {
	436	.probe = goldfish_nand_probe,
	437	.remove = goldfish_nand_remove,
	438	.driver = {
	439	.name = "goldfish_nand"
	440	}
	441	};
	442
	443	module_platform_driver(goldfish_nand_driver);
	444	MODULE_LICENSE("GPL");