Staging: et131x: Kill unused error defines
[linux-2.6-block.git] / drivers / staging / et131x / et131x_initpci.c
CommitLineData
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1/*
2 * Agere Systems Inc.
3 * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
4 *
64f93036 5 * Copyright © 2005 Agere Systems Inc.
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6 * All rights reserved.
7 * http://www.agere.com
8 *
9 *------------------------------------------------------------------------------
10 *
11 * et131x_initpci.c - Routines and data used to register the driver with the
12 * PCI (and PCI Express) subsystem, as well as basic driver
13 * init and startup.
14 *
15 *------------------------------------------------------------------------------
16 *
17 * SOFTWARE LICENSE
18 *
19 * This software is provided subject to the following terms and conditions,
20 * which you should read carefully before using the software. Using this
21 * software indicates your acceptance of these terms and conditions. If you do
22 * not agree with these terms and conditions, do not use the software.
23 *
64f93036 24 * Copyright © 2005 Agere Systems Inc.
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25 * All rights reserved.
26 *
27 * Redistribution and use in source or binary forms, with or without
28 * modifications, are permitted provided that the following conditions are met:
29 *
30 * . Redistributions of source code must retain the above copyright notice, this
31 * list of conditions and the following Disclaimer as comments in the code as
32 * well as in the documentation and/or other materials provided with the
33 * distribution.
34 *
35 * . Redistributions in binary form must reproduce the above copyright notice,
36 * this list of conditions and the following Disclaimer in the documentation
37 * and/or other materials provided with the distribution.
38 *
39 * . Neither the name of Agere Systems Inc. nor the names of the contributors
40 * may be used to endorse or promote products derived from this software
41 * without specific prior written permission.
42 *
43 * Disclaimer
44 *
64f93036 45 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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46 * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
47 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
48 * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
49 * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
50 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
51 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
52 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
53 * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
54 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
55 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
56 * DAMAGE.
57 *
58 */
59
60#include "et131x_version.h"
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61#include "et131x_defs.h"
62
63#include <linux/pci.h>
64#include <linux/init.h>
65#include <linux/module.h>
66#include <linux/types.h>
67#include <linux/kernel.h>
68
69#include <linux/sched.h>
70#include <linux/ptrace.h>
71#include <linux/slab.h>
72#include <linux/ctype.h>
73#include <linux/string.h>
74#include <linux/timer.h>
75#include <linux/interrupt.h>
76#include <linux/in.h>
77#include <linux/delay.h>
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78#include <linux/io.h>
79#include <linux/bitops.h>
cfb739b4 80#include <asm/system.h>
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81
82#include <linux/netdevice.h>
83#include <linux/etherdevice.h>
84#include <linux/skbuff.h>
85#include <linux/if_arp.h>
86#include <linux/ioport.h>
87#include <linux/random.h>
88
89#include "et1310_phy.h"
90#include "et1310_pm.h"
91#include "et1310_jagcore.h"
92
93#include "et131x_adapter.h"
94#include "et131x_netdev.h"
95#include "et131x_config.h"
96#include "et131x_isr.h"
97
98#include "et1310_address_map.h"
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99#include "et1310_tx.h"
100#include "et1310_rx.h"
101#include "et1310_mac.h"
102#include "et1310_eeprom.h"
103
104
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105/* Defines for Parameter Default/Min/Max vaules */
106#define PARM_SPEED_DUPLEX_MIN 0
107#define PARM_SPEED_DUPLEX_MAX 5
108
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109/* Module parameter for manual speed setting
110 * Set Link speed and dublex manually (0-5) [0]
111 * 1 : 10Mb Half-Duplex
112 * 2 : 10Mb Full-Duplex
113 * 3 : 100Mb Half-Duplex
114 * 4 : 100Mb Full-Duplex
115 * 5 : 1000Mb Full-Duplex
116 * 0 : Auto Speed Auto Duplex // default
117 */
118static u32 et131x_speed_set;
119module_param(et131x_speed_set, uint, 0);
120MODULE_PARM_DESC(et131x_speed_set,
121 "Set Link speed and dublex manually (0-5) [0] \n 1 : 10Mb Half-Duplex \n 2 : 10Mb Full-Duplex \n 3 : 100Mb Half-Duplex \n 4 : 100Mb Full-Duplex \n 5 : 1000Mb Full-Duplex \n 0 : Auto Speed Auto Dublex");
122
cfb739b4 123/**
c431e3c0 124 * et131x_hwaddr_init - set up the MAC Address on the ET1310
cfb739b4 125 * @adapter: pointer to our private adapter structure
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126 */
127void et131x_hwaddr_init(struct et131x_adapter *adapter)
128{
129 /* If have our default mac from init and no mac address from
130 * EEPROM then we need to generate the last octet and set it on the
131 * device
132 */
133 if (adapter->PermanentAddress[0] == 0x00 &&
134 adapter->PermanentAddress[1] == 0x00 &&
135 adapter->PermanentAddress[2] == 0x00 &&
136 adapter->PermanentAddress[3] == 0x00 &&
137 adapter->PermanentAddress[4] == 0x00 &&
138 adapter->PermanentAddress[5] == 0x00) {
139 /*
140 * We need to randomly generate the last octet so we
141 * decrease our chances of setting the mac address to
142 * same as another one of our cards in the system
143 */
144 get_random_bytes(&adapter->CurrentAddress[5], 1);
145 /*
146 * We have the default value in the register we are
147 * working with so we need to copy the current
148 * address into the permanent address
149 */
150 memcpy(adapter->PermanentAddress,
151 adapter->CurrentAddress, ETH_ALEN);
152 } else {
153 /* We do not have an override address, so set the
154 * current address to the permanent address and add
155 * it to the device
156 */
157 memcpy(adapter->CurrentAddress,
158 adapter->PermanentAddress, ETH_ALEN);
159 }
160}
161
162
163/**
164 * et131x_pci_init - initial PCI setup
165 * @adapter: pointer to our private adapter structure
166 * @pdev: our PCI device
cfb739b4 167 *
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168 * Perform the initial setup of PCI registers and if possible initialise
169 * the MAC address. At this point the I/O registers have yet to be mapped
cfb739b4 170 */
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171
172static int et131x_pci_init(struct et131x_adapter *adapter,
173 struct pci_dev *pdev)
cfb739b4 174{
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175 int i;
176 u8 max_payload;
177 u8 read_size_reg;
cfb739b4 178
4e02b4b5 179 if (et131x_init_eeprom(adapter) < 0)
cfb739b4 180 return -EIO;
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181
182 /* Let's set up the PORT LOGIC Register. First we need to know what
183 * the max_payload_size is
184 */
c431e3c0 185 if (pci_read_config_byte(pdev, ET1310_PCI_MAX_PYLD, &max_payload)) {
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186 dev_err(&pdev->dev,
187 "Could not read PCI config space for Max Payload Size\n");
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188 return -EIO;
189 }
190
191 /* Program the Ack/Nak latency and replay timers */
c431e3c0 192 max_payload &= 0x07; /* Only the lower 3 bits are valid */
cfb739b4 193
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194 if (max_payload < 2) {
195 static const u16 AckNak[2] = { 0x76, 0xD0 };
196 static const u16 Replay[2] = { 0x1E0, 0x2ED };
cfb739b4 197
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198 if (pci_write_config_word(pdev, ET1310_PCI_ACK_NACK,
199 AckNak[max_payload])) {
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200 dev_err(&pdev->dev,
201 "Could not write PCI config space for ACK/NAK\n");
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202 return -EIO;
203 }
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204 if (pci_write_config_word(pdev, ET1310_PCI_REPLAY,
205 Replay[max_payload])) {
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206 dev_err(&pdev->dev,
207 "Could not write PCI config space for Replay Timer\n");
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208 return -EIO;
209 }
210 }
211
212 /* l0s and l1 latency timers. We are using default values.
213 * Representing 001 for L0s and 010 for L1
214 */
c431e3c0 215 if (pci_write_config_byte(pdev, ET1310_PCI_L0L1LATENCY, 0x11)) {
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216 dev_err(&pdev->dev,
217 "Could not write PCI config space for Latency Timers\n");
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218 return -EIO;
219 }
220
221 /* Change the max read size to 2k */
c431e3c0 222 if (pci_read_config_byte(pdev, 0x51, &read_size_reg)) {
15700039 223 dev_err(&pdev->dev,
64f93036 224 "Could not read PCI config space for Max read size\n");
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225 return -EIO;
226 }
227
228 read_size_reg &= 0x8f;
229 read_size_reg |= 0x40;
230
c431e3c0 231 if (pci_write_config_byte(pdev, 0x51, read_size_reg)) {
15700039 232 dev_err(&pdev->dev,
64f93036 233 "Could not write PCI config space for Max read size\n");
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234 return -EIO;
235 }
236
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237 /* Get MAC address from config space if an eeprom exists, otherwise
238 * the MAC address there will not be valid
239 */
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240 if (!adapter->has_eeprom) {
241 et131x_hwaddr_init(adapter);
242 return 0;
243 }
244
245 for (i = 0; i < ETH_ALEN; i++) {
246 if (pci_read_config_byte(pdev, ET1310_PCI_MAC_ADDRESS + i,
247 adapter->PermanentAddress + i)) {
248 dev_err(&pdev->dev, "Could not read PCI config space for MAC address\n");
249 return -EIO;
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250 }
251 }
c431e3c0 252 memcpy(adapter->CurrentAddress, adapter->PermanentAddress, ETH_ALEN);
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253 return 0;
254}
255
256/**
257 * et131x_error_timer_handler
258 * @data: timer-specific variable; here a pointer to our adapter structure
259 *
260 * The routine called when the error timer expires, to track the number of
261 * recurring errors.
262 */
263void et131x_error_timer_handler(unsigned long data)
264{
25ad00bb 265 struct et131x_adapter *etdev = (struct et131x_adapter *) data;
f2c98d27 266 u32 pm_csr;
cfb739b4 267
f2c98d27 268 pm_csr = readl(&etdev->regs->global.pm_csr);
cfb739b4 269
f2c98d27 270 if ((pm_csr & ET_PM_PHY_SW_COMA) == 0)
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271 UpdateMacStatHostCounters(etdev);
272 else
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273 dev_err(&etdev->pdev->dev,
274 "No interrupts, in PHY coma, pm_csr = 0x%x\n", pm_csr);
cfb739b4 275
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276 if (!etdev->Bmsr.bits.link_status &&
277 etdev->RegistryPhyComa &&
278 etdev->PoMgmt.TransPhyComaModeOnBoot < 11) {
279 etdev->PoMgmt.TransPhyComaModeOnBoot++;
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280 }
281
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282 if (etdev->PoMgmt.TransPhyComaModeOnBoot == 10) {
283 if (!etdev->Bmsr.bits.link_status
284 && etdev->RegistryPhyComa) {
f2c98d27 285 if ((pm_csr & ET_PM_PHY_SW_COMA) == 0) {
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286 /* NOTE - This was originally a 'sync with
287 * interrupt'. How to do that under Linux?
288 */
25ad00bb
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289 et131x_enable_interrupts(etdev);
290 EnablePhyComa(etdev);
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291 }
292 }
293 }
294
295 /* This is a periodic timer, so reschedule */
25ad00bb 296 mod_timer(&etdev->ErrorTimer, jiffies +
64f93036 297 TX_ERROR_PERIOD * HZ / 1000);
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298}
299
300/**
301 * et131x_link_detection_handler
302 *
303 * Timer function for link up at driver load time
304 */
305void et131x_link_detection_handler(unsigned long data)
306{
25ad00bb 307 struct et131x_adapter *etdev = (struct et131x_adapter *) data;
37628606 308 unsigned long flags;
cfb739b4 309
25ad00bb 310 if (etdev->MediaState == 0) {
37628606 311 spin_lock_irqsave(&etdev->Lock, flags);
cfb739b4 312
25ad00bb 313 etdev->MediaState = NETIF_STATUS_MEDIA_DISCONNECT;
f6b35d66 314 etdev->Flags &= ~fMP_ADAPTER_LINK_DETECTION;
cfb739b4 315
37628606 316 spin_unlock_irqrestore(&etdev->Lock, flags);
cfb739b4 317
25ad00bb 318 netif_carrier_off(etdev->netdev);
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319 }
320}
321
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322/**
323 * et131x_configure_global_regs - configure JAGCore global regs
324 * @etdev: pointer to our adapter structure
325 *
326 * Used to configure the global registers on the JAGCore
327 */
328void ConfigGlobalRegs(struct et131x_adapter *etdev)
329{
2b903327 330 struct global_regs __iomem *regs = &etdev->regs->global;
b8c4cc46 331
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332 writel(0, &regs->rxq_start_addr);
333 writel(INTERNAL_MEM_SIZE - 1, &regs->txq_end_addr);
334
335 if (etdev->RegistryJumboPacket < 2048) {
336 /* Tx / RxDMA and Tx/Rx MAC interfaces have a 1k word
337 * block of RAM that the driver can split between Tx
338 * and Rx as it desires. Our default is to split it
339 * 50/50:
340 */
341 writel(PARM_RX_MEM_END_DEF, &regs->rxq_end_addr);
342 writel(PARM_RX_MEM_END_DEF + 1, &regs->txq_start_addr);
343 } else if (etdev->RegistryJumboPacket < 8192) {
344 /* For jumbo packets > 2k but < 8k, split 50-50. */
345 writel(INTERNAL_MEM_RX_OFFSET, &regs->rxq_end_addr);
346 writel(INTERNAL_MEM_RX_OFFSET + 1, &regs->txq_start_addr);
b8c4cc46 347 } else {
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348 /* 9216 is the only packet size greater than 8k that
349 * is available. The Tx buffer has to be big enough
350 * for one whole packet on the Tx side. We'll make
351 * the Tx 9408, and give the rest to Rx
b8c4cc46 352 */
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353 writel(0x01b3, &regs->rxq_end_addr);
354 writel(0x01b4, &regs->txq_start_addr);
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355 }
356
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357 /* Initialize the loopback register. Disable all loopbacks. */
358 writel(0, &regs->loopback);
359
b8c4cc46 360 /* MSI Register */
e266b202 361 writel(0, &regs->msi_config);
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362
363 /* By default, disable the watchdog timer. It will be enabled when
364 * a packet is queued.
365 */
e266b202 366 writel(0, &regs->watchdog_timer);
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367}
368
369
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370/**
371 * et131x_adapter_setup - Set the adapter up as per cassini+ documentation
372 * @adapter: pointer to our private adapter structure
373 *
374 * Returns 0 on success, errno on failure (as defined in errno.h)
375 */
25ad00bb 376int et131x_adapter_setup(struct et131x_adapter *etdev)
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377{
378 int status = 0;
379
cfb739b4 380 /* Configure the JAGCore */
25ad00bb 381 ConfigGlobalRegs(etdev);
cfb739b4 382
25ad00bb 383 ConfigMACRegs1(etdev);
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384
385 /* Configure the MMC registers */
386 /* All we need to do is initialize the Memory Control Register */
387 writel(ET_MMC_ENABLE, &etdev->regs->mmc.mmc_ctrl);
cfb739b4 388
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389 ConfigRxMacRegs(etdev);
390 ConfigTxMacRegs(etdev);
cfb739b4 391
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392 ConfigRxDmaRegs(etdev);
393 ConfigTxDmaRegs(etdev);
cfb739b4 394
25ad00bb 395 ConfigMacStatRegs(etdev);
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396
397 /* Move the following code to Timer function?? */
25ad00bb 398 status = et131x_xcvr_find(etdev);
cfb739b4 399
64f93036 400 if (status != 0)
15700039 401 dev_warn(&etdev->pdev->dev, "Could not find the xcvr\n");
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402
403 /* Prepare the TRUEPHY library. */
25ad00bb 404 ET1310_PhyInit(etdev);
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405
406 /* Reset the phy now so changes take place */
25ad00bb 407 ET1310_PhyReset(etdev);
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408
409 /* Power down PHY */
25ad00bb 410 ET1310_PhyPowerDown(etdev, 1);
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411
412 /*
413 * We need to turn off 1000 base half dulplex, the mac does not
414 * support it. For the 10/100 part, turn off all gig advertisement
415 */
5ec3487a 416 if (etdev->pdev->device != ET131X_PCI_DEVICE_ID_FAST)
25ad00bb 417 ET1310_PhyAdvertise1000BaseT(etdev, TRUEPHY_ADV_DUPLEX_FULL);
64f93036 418 else
25ad00bb 419 ET1310_PhyAdvertise1000BaseT(etdev, TRUEPHY_ADV_DUPLEX_NONE);
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420
421 /* Power up PHY */
25ad00bb 422 ET1310_PhyPowerDown(etdev, 0);
cfb739b4 423
25ad00bb 424 et131x_setphy_normal(etdev);
15700039 425; return status;
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426}
427
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428/**
429 * et131x_soft_reset - Issue a soft reset to the hardware, complete for ET1310
430 * @adapter: pointer to our private adapter structure
431 */
432void et131x_soft_reset(struct et131x_adapter *adapter)
433{
cfb739b4 434 /* Disable MAC Core */
c9835d97 435 writel(0xc00f0000, &adapter->regs->mac.cfg1);
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436
437 /* Set everything to a reset value */
b8c4cc46 438 writel(0x7F, &adapter->regs->global.sw_reset);
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439 writel(0x000f0000, &adapter->regs->mac.cfg1);
440 writel(0x00000000, &adapter->regs->mac.cfg1);
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441}
442
443/**
444 * et131x_align_allocated_memory - Align allocated memory on a given boundary
445 * @adapter: pointer to our adapter structure
446 * @phys_addr: pointer to Physical address
447 * @offset: pointer to the offset variable
448 * @mask: correct mask
449 */
450void et131x_align_allocated_memory(struct et131x_adapter *adapter,
451 uint64_t *phys_addr,
452 uint64_t *offset, uint64_t mask)
453{
454 uint64_t new_addr;
455
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456 *offset = 0;
457
458 new_addr = *phys_addr & ~mask;
459
460 if (new_addr != *phys_addr) {
461 /* Move to next aligned block */
462 new_addr += mask + 1;
463 /* Return offset for adjusting virt addr */
464 *offset = new_addr - *phys_addr;
465 /* Return new physical address */
466 *phys_addr = new_addr;
467 }
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468}
469
470/**
471 * et131x_adapter_memory_alloc
472 * @adapter: pointer to our private adapter structure
473 *
474 * Returns 0 on success, errno on failure (as defined in errno.h).
475 *
476 * Allocate all the memory blocks for send, receive and others.
477 */
478int et131x_adapter_memory_alloc(struct et131x_adapter *adapter)
479{
c431e3c0 480 int status;
cfb739b4 481
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482 /* Allocate memory for the Tx Ring */
483 status = et131x_tx_dma_memory_alloc(adapter);
484 if (status != 0) {
485 dev_err(&adapter->pdev->dev,
486 "et131x_tx_dma_memory_alloc FAILED\n");
487 return status;
488 }
489 /* Receive buffer memory allocation */
490 status = et131x_rx_dma_memory_alloc(adapter);
491 if (status != 0) {
492 dev_err(&adapter->pdev->dev,
493 "et131x_rx_dma_memory_alloc FAILED\n");
494 et131x_tx_dma_memory_free(adapter);
495 return status;
496 }
cfb739b4 497
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498 /* Init receive data structures */
499 status = et131x_init_recv(adapter);
500 if (status != 0) {
501 dev_err(&adapter->pdev->dev,
502 "et131x_init_recv FAILED\n");
503 et131x_tx_dma_memory_free(adapter);
504 et131x_rx_dma_memory_free(adapter);
505 }
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506 return status;
507}
508
509/**
510 * et131x_adapter_memory_free - Free all memory allocated for use by Tx & Rx
511 * @adapter: pointer to our private adapter structure
512 */
513void et131x_adapter_memory_free(struct et131x_adapter *adapter)
514{
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515 /* Free DMA memory */
516 et131x_tx_dma_memory_free(adapter);
517 et131x_rx_dma_memory_free(adapter);
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518}
519
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520
521
8c5f20f3 522/**
c431e3c0 523 * et131x_adapter_init
8c5f20f3 524 * @etdev: pointer to the private adapter struct
c431e3c0 525 * @pdev: pointer to the PCI device
8c5f20f3 526 *
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527 * Initialize the data structures for the et131x_adapter object and link
528 * them together with the platform provided device structures.
8c5f20f3 529 */
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530
531
532static struct et131x_adapter *et131x_adapter_init(struct net_device *netdev,
533 struct pci_dev *pdev)
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534{
535 static const u8 default_mac[] = { 0x00, 0x05, 0x3d, 0x00, 0x02, 0x00 };
536 static const u8 duplex[] = { 0, 1, 2, 1, 2, 2 };
537 static const u16 speed[] = { 0, 10, 10, 100, 100, 1000 };
538
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539 struct et131x_adapter *etdev;
540
541 /* Setup the fundamental net_device and private adapter structure elements */
542 SET_NETDEV_DEV(netdev, &pdev->dev);
543
544 /* Allocate private adapter struct and copy in relevant information */
545 etdev = netdev_priv(netdev);
546 etdev->pdev = pci_dev_get(pdev);
547 etdev->netdev = netdev;
548
549 /* Do the same for the netdev struct */
550 netdev->irq = pdev->irq;
551 netdev->base_addr = pci_resource_start(pdev, 0);
552
553 /* Initialize spinlocks here */
554 spin_lock_init(&etdev->Lock);
555 spin_lock_init(&etdev->TCBSendQLock);
556 spin_lock_init(&etdev->TCBReadyQLock);
557 spin_lock_init(&etdev->SendHWLock);
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558 spin_lock_init(&etdev->RcvLock);
559 spin_lock_init(&etdev->RcvPendLock);
560 spin_lock_init(&etdev->FbrLock);
561 spin_lock_init(&etdev->PHYLock);
562
563 /* Parse configuration parameters into the private adapter struct */
8c5f20f3 564 if (et131x_speed_set)
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565 dev_info(&etdev->pdev->dev,
566 "Speed set manually to : %d \n", et131x_speed_set);
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567
568 etdev->SpeedDuplex = et131x_speed_set;
569 etdev->RegistryJumboPacket = 1514; /* 1514-9216 */
570
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571 /* Set the MAC address to a default */
572 memcpy(etdev->CurrentAddress, default_mac, ETH_ALEN);
573
574 /* Decode SpeedDuplex
575 *
576 * Set up as if we are auto negotiating always and then change if we
577 * go into force mode
578 *
579 * If we are the 10/100 device, and gigabit is somehow requested then
580 * knock it down to 100 full.
581 */
582 if (etdev->pdev->device == ET131X_PCI_DEVICE_ID_FAST &&
583 etdev->SpeedDuplex == 5)
584 etdev->SpeedDuplex = 4;
585
586 etdev->AiForceSpeed = speed[etdev->SpeedDuplex];
587 etdev->AiForceDpx = duplex[etdev->SpeedDuplex]; /* Auto FDX */
8c5f20f3 588
c431e3c0 589 return etdev;
7ca5d422
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590}
591
cfb739b4
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592/**
593 * et131x_pci_setup - Perform device initialization
594 * @pdev: a pointer to the device's pci_dev structure
595 * @ent: this device's entry in the pci_device_id table
596 *
597 * Returns 0 on success, errno on failure (as defined in errno.h)
598 *
599 * Registered in the pci_driver structure, this function is called when the
600 * PCI subsystem finds a new PCI device which matches the information
601 * contained in the pci_device_id table. This routine is the equivalent to
602 * a device insertion routine.
603 */
7ca5d422 604
c431e3c0 605static int __devinit et131x_pci_setup(struct pci_dev *pdev,
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606 const struct pci_device_id *ent)
607{
c431e3c0 608 int result = -EBUSY;
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609 int pm_cap;
610 bool pci_using_dac;
c431e3c0
AC
611 struct net_device *netdev;
612 struct et131x_adapter *adapter;
cfb739b4 613
cfb739b4 614 /* Enable the device via the PCI subsystem */
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615 if (pci_enable_device(pdev) != 0) {
616 dev_err(&pdev->dev,
15700039 617 "pci_enable_device() failed\n");
c431e3c0 618 return -EIO;
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619 }
620
621 /* Perform some basic PCI checks */
622 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
c431e3c0 623 dev_err(&pdev->dev,
cfb739b4 624 "Can't find PCI device's base address\n");
c431e3c0 625 goto err_disable;
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626 }
627
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628 if (pci_request_regions(pdev, DRIVER_NAME)) {
629 dev_err(&pdev->dev,
15700039 630 "Can't get PCI resources\n");
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631 goto err_disable;
632 }
633
634 /* Enable PCI bus mastering */
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635 pci_set_master(pdev);
636
637 /* Query PCI for Power Mgmt Capabilities
638 *
639 * NOTE: Now reading PowerMgmt in another location; is this still
640 * needed?
641 */
642 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
643 if (pm_cap == 0) {
c431e3c0 644 dev_err(&pdev->dev,
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645 "Cannot find Power Management capabilities\n");
646 result = -EIO;
647 goto err_release_res;
648 }
649
650 /* Check the DMA addressing support of this device */
c431e3c0 651 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
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652 pci_using_dac = true;
653
c431e3c0 654 result = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
cfb739b4 655 if (result != 0) {
15700039 656 dev_err(&pdev->dev,
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657 "Unable to obtain 64 bit DMA for consistent allocations\n");
658 goto err_release_res;
659 }
c431e3c0 660 } else if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
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661 pci_using_dac = false;
662 } else {
c431e3c0 663 dev_err(&pdev->dev,
15700039 664 "No usable DMA addressing method\n");
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665 result = -EIO;
666 goto err_release_res;
667 }
668
669 /* Allocate netdev and private adapter structs */
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670 netdev = et131x_device_alloc();
671 if (netdev == NULL) {
c431e3c0 672 dev_err(&pdev->dev, "Couldn't alloc netdev struct\n");
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673 result = -ENOMEM;
674 goto err_release_res;
675 }
c431e3c0
AC
676 adapter = et131x_adapter_init(netdev, pdev);
677 /* Initialise the PCI setup for the device */
678 et131x_pci_init(adapter, pdev);
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679
680 /* Map the bus-relative registers to system virtual memory */
c431e3c0 681 adapter->regs = pci_ioremap_bar(pdev, 0);
f3f415a3 682 if (adapter->regs == NULL) {
15700039 683 dev_err(&pdev->dev, "Cannot map device registers\n");
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684 result = -ENOMEM;
685 goto err_free_dev;
686 }
687
cfb739b4 688 /* If Phy COMA mode was enabled when we went down, disable it here. */
f2c98d27 689 writel(ET_PMCSR_INIT, &adapter->regs->global.pm_csr);
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690
691 /* Issue a global reset to the et1310 */
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692 et131x_soft_reset(adapter);
693
694 /* Disable all interrupts (paranoid) */
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695 et131x_disable_interrupts(adapter);
696
697 /* Allocate DMA memory */
698 result = et131x_adapter_memory_alloc(adapter);
699 if (result != 0) {
15700039 700 dev_err(&pdev->dev, "Could not alloc adapater memory (DMA)\n");
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701 goto err_iounmap;
702 }
703
704 /* Init send data structures */
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705 et131x_init_send(adapter);
706
c431e3c0
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707 /*
708 * Set up the task structure for the ISR's deferred handler
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709 */
710 INIT_WORK(&adapter->task, et131x_isr_handler);
711
c431e3c0 712 /* Copy address into the net_device struct */
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713 memcpy(netdev->dev_addr, adapter->CurrentAddress, ETH_ALEN);
714
715 /* Setup et1310 as per the documentation */
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716 et131x_adapter_setup(adapter);
717
718 /* Create a timer to count errors received by the NIC */
719 init_timer(&adapter->ErrorTimer);
720
721 adapter->ErrorTimer.expires = jiffies + TX_ERROR_PERIOD * HZ / 1000;
722 adapter->ErrorTimer.function = et131x_error_timer_handler;
723 adapter->ErrorTimer.data = (unsigned long)adapter;
724
725 /* Initialize link state */
726 et131x_link_detection_handler((unsigned long)adapter);
727
64f93036
AC
728 /* Intialize variable for counting how long we do not have
729 link status */
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730 adapter->PoMgmt.TransPhyComaModeOnBoot = 0;
731
732 /* We can enable interrupts now
733 *
734 * NOTE - Because registration of interrupt handler is done in the
735 * device's open(), defer enabling device interrupts to that
736 * point
737 */
738
739 /* Register the net_device struct with the Linux network layer */
64f93036
AC
740 result = register_netdev(netdev);
741 if (result != 0) {
15700039 742 dev_err(&pdev->dev, "register_netdev() failed\n");
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743 goto err_mem_free;
744 }
745
746 /* Register the net_device struct with the PCI subsystem. Save a copy
747 * of the PCI config space for this device now that the device has
748 * been initialized, just in case it needs to be quickly restored.
749 */
750 pci_set_drvdata(pdev, netdev);
cfb739b4 751 pci_save_state(adapter->pdev);
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752 return result;
753
754err_mem_free:
755 et131x_adapter_memory_free(adapter);
756err_iounmap:
f3f415a3 757 iounmap(adapter->regs);
cfb739b4 758err_free_dev:
6ae56042 759 pci_dev_put(pdev);
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760 free_netdev(netdev);
761err_release_res:
762 pci_release_regions(pdev);
763err_disable:
764 pci_disable_device(pdev);
c431e3c0
AC
765 return result;
766}
767
768/**
769 * et131x_pci_remove
770 * @pdev: a pointer to the device's pci_dev structure
771 *
772 * Registered in the pci_driver structure, this function is called when the
773 * PCI subsystem detects that a PCI device which matches the information
774 * contained in the pci_device_id table has been removed.
775 */
776
777static void __devexit et131x_pci_remove(struct pci_dev *pdev)
778{
779 struct net_device *netdev;
780 struct et131x_adapter *adapter;
781
782 /* Retrieve the net_device pointer from the pci_dev struct, as well
783 * as the private adapter struct
784 */
785 netdev = (struct net_device *) pci_get_drvdata(pdev);
786 adapter = netdev_priv(netdev);
787
788 /* Perform device cleanup */
789 unregister_netdev(netdev);
790 et131x_adapter_memory_free(adapter);
791 iounmap(adapter->regs);
792 pci_dev_put(adapter->pdev);
793 free_netdev(netdev);
794 pci_release_regions(pdev);
795 pci_disable_device(pdev);
cfb739b4 796}
7ca5d422
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797
798static struct pci_device_id et131x_pci_table[] __devinitdata = {
799 {ET131X_PCI_VENDOR_ID, ET131X_PCI_DEVICE_ID_GIG, PCI_ANY_ID,
800 PCI_ANY_ID, 0, 0, 0UL},
801 {ET131X_PCI_VENDOR_ID, ET131X_PCI_DEVICE_ID_FAST, PCI_ANY_ID,
802 PCI_ANY_ID, 0, 0, 0UL},
803 {0,}
804};
805
806MODULE_DEVICE_TABLE(pci, et131x_pci_table);
807
808static struct pci_driver et131x_driver = {
809 .name = DRIVER_NAME,
810 .id_table = et131x_pci_table,
811 .probe = et131x_pci_setup,
812 .remove = __devexit_p(et131x_pci_remove),
813 .suspend = NULL, /* et131x_pci_suspend */
814 .resume = NULL, /* et131x_pci_resume */
815};
816
817
818/**
819 * et131x_init_module - The "main" entry point called on driver initialization
820 *
821 * Returns 0 on success, errno on failure (as defined in errno.h)
822 */
3c0d4464 823static int __init et131x_init_module(void)
7ca5d422
AC
824{
825 if (et131x_speed_set < PARM_SPEED_DUPLEX_MIN ||
826 et131x_speed_set > PARM_SPEED_DUPLEX_MAX) {
827 printk(KERN_WARNING "et131x: invalid speed setting ignored.\n");
828 et131x_speed_set = 0;
829 }
830 return pci_register_driver(&et131x_driver);
831}
832
833/**
834 * et131x_cleanup_module - The entry point called on driver cleanup
835 */
3c0d4464 836static void __exit et131x_cleanup_module(void)
7ca5d422
AC
837{
838 pci_unregister_driver(&et131x_driver);
839}
840
841module_init(et131x_init_module);
842module_exit(et131x_cleanup_module);
843
7ca5d422
AC
844/* Modinfo parameters (filled out using defines from et131x_version.h) */
845MODULE_AUTHOR(DRIVER_AUTHOR);
846MODULE_DESCRIPTION(DRIVER_INFO);
847MODULE_LICENSE(DRIVER_LICENSE);