Staging: et131x: kill NMI hacks
[linux-2.6-block.git] / drivers / staging / et131x / et131x_initpci.c
CommitLineData
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1/*
2 * Agere Systems Inc.
3 * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
4 *
64f93036 5 * Copyright © 2005 Agere Systems Inc.
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6 * All rights reserved.
7 * http://www.agere.com
8 *
9 *------------------------------------------------------------------------------
10 *
11 * et131x_initpci.c - Routines and data used to register the driver with the
12 * PCI (and PCI Express) subsystem, as well as basic driver
13 * init and startup.
14 *
15 *------------------------------------------------------------------------------
16 *
17 * SOFTWARE LICENSE
18 *
19 * This software is provided subject to the following terms and conditions,
20 * which you should read carefully before using the software. Using this
21 * software indicates your acceptance of these terms and conditions. If you do
22 * not agree with these terms and conditions, do not use the software.
23 *
64f93036 24 * Copyright © 2005 Agere Systems Inc.
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25 * All rights reserved.
26 *
27 * Redistribution and use in source or binary forms, with or without
28 * modifications, are permitted provided that the following conditions are met:
29 *
30 * . Redistributions of source code must retain the above copyright notice, this
31 * list of conditions and the following Disclaimer as comments in the code as
32 * well as in the documentation and/or other materials provided with the
33 * distribution.
34 *
35 * . Redistributions in binary form must reproduce the above copyright notice,
36 * this list of conditions and the following Disclaimer in the documentation
37 * and/or other materials provided with the distribution.
38 *
39 * . Neither the name of Agere Systems Inc. nor the names of the contributors
40 * may be used to endorse or promote products derived from this software
41 * without specific prior written permission.
42 *
43 * Disclaimer
44 *
64f93036 45 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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46 * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
47 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
48 * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
49 * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
50 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
51 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
52 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
53 * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
54 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
55 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
56 * DAMAGE.
57 *
58 */
59
60#include "et131x_version.h"
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61#include "et131x_defs.h"
62
63#include <linux/pci.h>
64#include <linux/init.h>
65#include <linux/module.h>
66#include <linux/types.h>
67#include <linux/kernel.h>
68
69#include <linux/sched.h>
70#include <linux/ptrace.h>
71#include <linux/slab.h>
72#include <linux/ctype.h>
73#include <linux/string.h>
74#include <linux/timer.h>
75#include <linux/interrupt.h>
76#include <linux/in.h>
77#include <linux/delay.h>
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78#include <linux/io.h>
79#include <linux/bitops.h>
cfb739b4 80#include <asm/system.h>
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81
82#include <linux/netdevice.h>
83#include <linux/etherdevice.h>
84#include <linux/skbuff.h>
85#include <linux/if_arp.h>
86#include <linux/ioport.h>
87#include <linux/random.h>
88
89#include "et1310_phy.h"
90#include "et1310_pm.h"
91#include "et1310_jagcore.h"
92
93#include "et131x_adapter.h"
94#include "et131x_netdev.h"
95#include "et131x_config.h"
96#include "et131x_isr.h"
97
98#include "et1310_address_map.h"
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99#include "et1310_tx.h"
100#include "et1310_rx.h"
101#include "et1310_mac.h"
102#include "et1310_eeprom.h"
103
104
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105/* Defines for Parameter Default/Min/Max vaules */
106#define PARM_SPEED_DUPLEX_MIN 0
107#define PARM_SPEED_DUPLEX_MAX 5
108
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109/* Module parameter for manual speed setting
110 * Set Link speed and dublex manually (0-5) [0]
111 * 1 : 10Mb Half-Duplex
112 * 2 : 10Mb Full-Duplex
113 * 3 : 100Mb Half-Duplex
114 * 4 : 100Mb Full-Duplex
115 * 5 : 1000Mb Full-Duplex
116 * 0 : Auto Speed Auto Duplex // default
117 */
118static u32 et131x_speed_set;
119module_param(et131x_speed_set, uint, 0);
120MODULE_PARM_DESC(et131x_speed_set,
121 "Set Link speed and dublex manually (0-5) [0] \n 1 : 10Mb Half-Duplex \n 2 : 10Mb Full-Duplex \n 3 : 100Mb Half-Duplex \n 4 : 100Mb Full-Duplex \n 5 : 1000Mb Full-Duplex \n 0 : Auto Speed Auto Dublex");
122
cfb739b4 123/**
c431e3c0 124 * et131x_hwaddr_init - set up the MAC Address on the ET1310
cfb739b4 125 * @adapter: pointer to our private adapter structure
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126 */
127void et131x_hwaddr_init(struct et131x_adapter *adapter)
128{
129 /* If have our default mac from init and no mac address from
130 * EEPROM then we need to generate the last octet and set it on the
131 * device
132 */
133 if (adapter->PermanentAddress[0] == 0x00 &&
134 adapter->PermanentAddress[1] == 0x00 &&
135 adapter->PermanentAddress[2] == 0x00 &&
136 adapter->PermanentAddress[3] == 0x00 &&
137 adapter->PermanentAddress[4] == 0x00 &&
138 adapter->PermanentAddress[5] == 0x00) {
139 /*
140 * We need to randomly generate the last octet so we
141 * decrease our chances of setting the mac address to
142 * same as another one of our cards in the system
143 */
144 get_random_bytes(&adapter->CurrentAddress[5], 1);
145 /*
146 * We have the default value in the register we are
147 * working with so we need to copy the current
148 * address into the permanent address
149 */
150 memcpy(adapter->PermanentAddress,
151 adapter->CurrentAddress, ETH_ALEN);
152 } else {
153 /* We do not have an override address, so set the
154 * current address to the permanent address and add
155 * it to the device
156 */
157 memcpy(adapter->CurrentAddress,
158 adapter->PermanentAddress, ETH_ALEN);
159 }
160}
161
162
163/**
164 * et131x_pci_init - initial PCI setup
165 * @adapter: pointer to our private adapter structure
166 * @pdev: our PCI device
cfb739b4 167 *
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168 * Perform the initial setup of PCI registers and if possible initialise
169 * the MAC address. At this point the I/O registers have yet to be mapped
cfb739b4 170 */
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171
172static int et131x_pci_init(struct et131x_adapter *adapter,
173 struct pci_dev *pdev)
cfb739b4 174{
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175 int i;
176 u8 max_payload;
177 u8 read_size_reg;
cfb739b4 178
4e02b4b5 179 if (et131x_init_eeprom(adapter) < 0)
cfb739b4 180 return -EIO;
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181
182 /* Let's set up the PORT LOGIC Register. First we need to know what
183 * the max_payload_size is
184 */
c431e3c0 185 if (pci_read_config_byte(pdev, ET1310_PCI_MAX_PYLD, &max_payload)) {
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186 dev_err(&pdev->dev,
187 "Could not read PCI config space for Max Payload Size\n");
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188 return -EIO;
189 }
190
191 /* Program the Ack/Nak latency and replay timers */
c431e3c0 192 max_payload &= 0x07; /* Only the lower 3 bits are valid */
cfb739b4 193
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194 if (max_payload < 2) {
195 static const u16 AckNak[2] = { 0x76, 0xD0 };
196 static const u16 Replay[2] = { 0x1E0, 0x2ED };
cfb739b4 197
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198 if (pci_write_config_word(pdev, ET1310_PCI_ACK_NACK,
199 AckNak[max_payload])) {
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200 dev_err(&pdev->dev,
201 "Could not write PCI config space for ACK/NAK\n");
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202 return -EIO;
203 }
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204 if (pci_write_config_word(pdev, ET1310_PCI_REPLAY,
205 Replay[max_payload])) {
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206 dev_err(&pdev->dev,
207 "Could not write PCI config space for Replay Timer\n");
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208 return -EIO;
209 }
210 }
211
212 /* l0s and l1 latency timers. We are using default values.
213 * Representing 001 for L0s and 010 for L1
214 */
c431e3c0 215 if (pci_write_config_byte(pdev, ET1310_PCI_L0L1LATENCY, 0x11)) {
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216 dev_err(&pdev->dev,
217 "Could not write PCI config space for Latency Timers\n");
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218 return -EIO;
219 }
220
221 /* Change the max read size to 2k */
c431e3c0 222 if (pci_read_config_byte(pdev, 0x51, &read_size_reg)) {
15700039 223 dev_err(&pdev->dev,
64f93036 224 "Could not read PCI config space for Max read size\n");
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225 return -EIO;
226 }
227
228 read_size_reg &= 0x8f;
229 read_size_reg |= 0x40;
230
c431e3c0 231 if (pci_write_config_byte(pdev, 0x51, read_size_reg)) {
15700039 232 dev_err(&pdev->dev,
64f93036 233 "Could not write PCI config space for Max read size\n");
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234 return -EIO;
235 }
236
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237 /* Get MAC address from config space if an eeprom exists, otherwise
238 * the MAC address there will not be valid
239 */
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240 if (!adapter->has_eeprom) {
241 et131x_hwaddr_init(adapter);
242 return 0;
243 }
244
245 for (i = 0; i < ETH_ALEN; i++) {
246 if (pci_read_config_byte(pdev, ET1310_PCI_MAC_ADDRESS + i,
247 adapter->PermanentAddress + i)) {
248 dev_err(&pdev->dev, "Could not read PCI config space for MAC address\n");
249 return -EIO;
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250 }
251 }
c431e3c0 252 memcpy(adapter->CurrentAddress, adapter->PermanentAddress, ETH_ALEN);
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253 return 0;
254}
255
256/**
257 * et131x_error_timer_handler
258 * @data: timer-specific variable; here a pointer to our adapter structure
259 *
260 * The routine called when the error timer expires, to track the number of
261 * recurring errors.
262 */
263void et131x_error_timer_handler(unsigned long data)
264{
25ad00bb 265 struct et131x_adapter *etdev = (struct et131x_adapter *) data;
f2c98d27 266 u32 pm_csr;
cfb739b4 267
f2c98d27 268 pm_csr = readl(&etdev->regs->global.pm_csr);
cfb739b4 269
f2c98d27 270 if ((pm_csr & ET_PM_PHY_SW_COMA) == 0)
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271 UpdateMacStatHostCounters(etdev);
272 else
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273 dev_err(&etdev->pdev->dev,
274 "No interrupts, in PHY coma, pm_csr = 0x%x\n", pm_csr);
cfb739b4 275
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276 if (!etdev->Bmsr.bits.link_status &&
277 etdev->RegistryPhyComa &&
278 etdev->PoMgmt.TransPhyComaModeOnBoot < 11) {
279 etdev->PoMgmt.TransPhyComaModeOnBoot++;
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280 }
281
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282 if (etdev->PoMgmt.TransPhyComaModeOnBoot == 10) {
283 if (!etdev->Bmsr.bits.link_status
284 && etdev->RegistryPhyComa) {
f2c98d27 285 if ((pm_csr & ET_PM_PHY_SW_COMA) == 0) {
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286 /* NOTE - This was originally a 'sync with
287 * interrupt'. How to do that under Linux?
288 */
25ad00bb
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289 et131x_enable_interrupts(etdev);
290 EnablePhyComa(etdev);
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291 }
292 }
293 }
294
295 /* This is a periodic timer, so reschedule */
25ad00bb 296 mod_timer(&etdev->ErrorTimer, jiffies +
64f93036 297 TX_ERROR_PERIOD * HZ / 1000);
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298}
299
300/**
301 * et131x_link_detection_handler
302 *
303 * Timer function for link up at driver load time
304 */
305void et131x_link_detection_handler(unsigned long data)
306{
25ad00bb 307 struct et131x_adapter *etdev = (struct et131x_adapter *) data;
37628606 308 unsigned long flags;
cfb739b4 309
25ad00bb 310 if (etdev->MediaState == 0) {
37628606 311 spin_lock_irqsave(&etdev->Lock, flags);
cfb739b4 312
25ad00bb 313 etdev->MediaState = NETIF_STATUS_MEDIA_DISCONNECT;
f6b35d66 314 etdev->Flags &= ~fMP_ADAPTER_LINK_DETECTION;
cfb739b4 315
37628606 316 spin_unlock_irqrestore(&etdev->Lock, flags);
cfb739b4 317
25ad00bb 318 netif_carrier_off(etdev->netdev);
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319 }
320}
321
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322/**
323 * et131x_configure_global_regs - configure JAGCore global regs
324 * @etdev: pointer to our adapter structure
325 *
326 * Used to configure the global registers on the JAGCore
327 */
328void ConfigGlobalRegs(struct et131x_adapter *etdev)
329{
e266b202 330 struct _GLOBAL_t __iomem *regs = &etdev->regs->global;
b8c4cc46 331
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332 if (etdev->RegistryPhyLoopbk == false) {
333 if (etdev->RegistryJumboPacket < 2048) {
334 /* Tx / RxDMA and Tx/Rx MAC interfaces have a 1k word
335 * block of RAM that the driver can split between Tx
336 * and Rx as it desires. Our default is to split it
337 * 50/50:
338 */
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339 writel(0, &regs->rxq_start_addr);
340 writel(PARM_RX_MEM_END_DEF, &regs->rxq_end_addr);
341 writel(PARM_RX_MEM_END_DEF + 1, &regs->txq_start_addr);
342 writel(INTERNAL_MEM_SIZE - 1, &regs->txq_end_addr);
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343 } else if (etdev->RegistryJumboPacket < 8192) {
344 /* For jumbo packets > 2k but < 8k, split 50-50. */
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345 writel(0, &regs->rxq_start_addr);
346 writel(INTERNAL_MEM_RX_OFFSET, &regs->rxq_end_addr);
347 writel(INTERNAL_MEM_RX_OFFSET + 1, &regs->txq_start_addr);
348 writel(INTERNAL_MEM_SIZE - 1, &regs->txq_end_addr);
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349 } else {
350 /* 9216 is the only packet size greater than 8k that
351 * is available. The Tx buffer has to be big enough
352 * for one whole packet on the Tx side. We'll make
353 * the Tx 9408, and give the rest to Rx
354 */
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355 writel(0x0000, &regs->rxq_start_addr);
356 writel(0x01b3, &regs->rxq_end_addr);
357 writel(0x01b4, &regs->txq_start_addr);
358 writel(INTERNAL_MEM_SIZE - 1,&regs->txq_end_addr);
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359 }
360
361 /* Initialize the loopback register. Disable all loopbacks. */
bc7f9c59 362 writel(0, &regs->loopback);
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363 } else {
364 /* For PHY Line loopback, the memory is configured as if Tx
365 * and Rx both have all the memory. This is because the
366 * RxMAC will write data into the space, and the TxMAC will
367 * read it out.
368 */
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369 writel(0, &regs->rxq_start_addr);
370 writel(INTERNAL_MEM_SIZE - 1, &regs->rxq_end_addr);
371 writel(0, &regs->txq_start_addr);
372 writel(INTERNAL_MEM_SIZE - 1, &regs->txq_end_addr);
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373
374 /* Initialize the loopback register (MAC loopback). */
bc7f9c59 375 writel(ET_LOOP_MAC, &regs->loopback);
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376 }
377
378 /* MSI Register */
e266b202 379 writel(0, &regs->msi_config);
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380
381 /* By default, disable the watchdog timer. It will be enabled when
382 * a packet is queued.
383 */
e266b202 384 writel(0, &regs->watchdog_timer);
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385}
386
387
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388/**
389 * et131x_adapter_setup - Set the adapter up as per cassini+ documentation
390 * @adapter: pointer to our private adapter structure
391 *
392 * Returns 0 on success, errno on failure (as defined in errno.h)
393 */
25ad00bb 394int et131x_adapter_setup(struct et131x_adapter *etdev)
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395{
396 int status = 0;
397
cfb739b4 398 /* Configure the JAGCore */
25ad00bb 399 ConfigGlobalRegs(etdev);
cfb739b4 400
25ad00bb 401 ConfigMACRegs1(etdev);
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402
403 /* Configure the MMC registers */
404 /* All we need to do is initialize the Memory Control Register */
405 writel(ET_MMC_ENABLE, &etdev->regs->mmc.mmc_ctrl);
cfb739b4 406
25ad00bb
AC
407 ConfigRxMacRegs(etdev);
408 ConfigTxMacRegs(etdev);
cfb739b4 409
25ad00bb
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410 ConfigRxDmaRegs(etdev);
411 ConfigTxDmaRegs(etdev);
cfb739b4 412
25ad00bb 413 ConfigMacStatRegs(etdev);
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414
415 /* Move the following code to Timer function?? */
25ad00bb 416 status = et131x_xcvr_find(etdev);
cfb739b4 417
64f93036 418 if (status != 0)
15700039 419 dev_warn(&etdev->pdev->dev, "Could not find the xcvr\n");
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420
421 /* Prepare the TRUEPHY library. */
25ad00bb 422 ET1310_PhyInit(etdev);
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423
424 /* Reset the phy now so changes take place */
25ad00bb 425 ET1310_PhyReset(etdev);
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426
427 /* Power down PHY */
25ad00bb 428 ET1310_PhyPowerDown(etdev, 1);
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429
430 /*
431 * We need to turn off 1000 base half dulplex, the mac does not
432 * support it. For the 10/100 part, turn off all gig advertisement
433 */
5ec3487a 434 if (etdev->pdev->device != ET131X_PCI_DEVICE_ID_FAST)
25ad00bb 435 ET1310_PhyAdvertise1000BaseT(etdev, TRUEPHY_ADV_DUPLEX_FULL);
64f93036 436 else
25ad00bb 437 ET1310_PhyAdvertise1000BaseT(etdev, TRUEPHY_ADV_DUPLEX_NONE);
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438
439 /* Power up PHY */
25ad00bb 440 ET1310_PhyPowerDown(etdev, 0);
cfb739b4 441
25ad00bb 442 et131x_setphy_normal(etdev);
15700039 443; return status;
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444}
445
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446/**
447 * et131x_soft_reset - Issue a soft reset to the hardware, complete for ET1310
448 * @adapter: pointer to our private adapter structure
449 */
450void et131x_soft_reset(struct et131x_adapter *adapter)
451{
cfb739b4 452 /* Disable MAC Core */
f3f415a3 453 writel(0xc00f0000, &adapter->regs->mac.cfg1.value);
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454
455 /* Set everything to a reset value */
b8c4cc46 456 writel(0x7F, &adapter->regs->global.sw_reset);
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AC
457 writel(0x000f0000, &adapter->regs->mac.cfg1.value);
458 writel(0x00000000, &adapter->regs->mac.cfg1.value);
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459}
460
461/**
462 * et131x_align_allocated_memory - Align allocated memory on a given boundary
463 * @adapter: pointer to our adapter structure
464 * @phys_addr: pointer to Physical address
465 * @offset: pointer to the offset variable
466 * @mask: correct mask
467 */
468void et131x_align_allocated_memory(struct et131x_adapter *adapter,
469 uint64_t *phys_addr,
470 uint64_t *offset, uint64_t mask)
471{
472 uint64_t new_addr;
473
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474 *offset = 0;
475
476 new_addr = *phys_addr & ~mask;
477
478 if (new_addr != *phys_addr) {
479 /* Move to next aligned block */
480 new_addr += mask + 1;
481 /* Return offset for adjusting virt addr */
482 *offset = new_addr - *phys_addr;
483 /* Return new physical address */
484 *phys_addr = new_addr;
485 }
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486}
487
488/**
489 * et131x_adapter_memory_alloc
490 * @adapter: pointer to our private adapter structure
491 *
492 * Returns 0 on success, errno on failure (as defined in errno.h).
493 *
494 * Allocate all the memory blocks for send, receive and others.
495 */
496int et131x_adapter_memory_alloc(struct et131x_adapter *adapter)
497{
c431e3c0 498 int status;
cfb739b4 499
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500 /* Allocate memory for the Tx Ring */
501 status = et131x_tx_dma_memory_alloc(adapter);
502 if (status != 0) {
503 dev_err(&adapter->pdev->dev,
504 "et131x_tx_dma_memory_alloc FAILED\n");
505 return status;
506 }
507 /* Receive buffer memory allocation */
508 status = et131x_rx_dma_memory_alloc(adapter);
509 if (status != 0) {
510 dev_err(&adapter->pdev->dev,
511 "et131x_rx_dma_memory_alloc FAILED\n");
512 et131x_tx_dma_memory_free(adapter);
513 return status;
514 }
cfb739b4 515
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516 /* Init receive data structures */
517 status = et131x_init_recv(adapter);
518 if (status != 0) {
519 dev_err(&adapter->pdev->dev,
520 "et131x_init_recv FAILED\n");
521 et131x_tx_dma_memory_free(adapter);
522 et131x_rx_dma_memory_free(adapter);
523 }
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524 return status;
525}
526
527/**
528 * et131x_adapter_memory_free - Free all memory allocated for use by Tx & Rx
529 * @adapter: pointer to our private adapter structure
530 */
531void et131x_adapter_memory_free(struct et131x_adapter *adapter)
532{
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533 /* Free DMA memory */
534 et131x_tx_dma_memory_free(adapter);
535 et131x_rx_dma_memory_free(adapter);
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536}
537
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538
539
8c5f20f3 540/**
c431e3c0 541 * et131x_adapter_init
8c5f20f3 542 * @etdev: pointer to the private adapter struct
c431e3c0 543 * @pdev: pointer to the PCI device
8c5f20f3 544 *
c431e3c0
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545 * Initialize the data structures for the et131x_adapter object and link
546 * them together with the platform provided device structures.
8c5f20f3 547 */
c431e3c0
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548
549
550static struct et131x_adapter *et131x_adapter_init(struct net_device *netdev,
551 struct pci_dev *pdev)
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552{
553 static const u8 default_mac[] = { 0x00, 0x05, 0x3d, 0x00, 0x02, 0x00 };
554 static const u8 duplex[] = { 0, 1, 2, 1, 2, 2 };
555 static const u16 speed[] = { 0, 10, 10, 100, 100, 1000 };
556
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557 struct et131x_adapter *etdev;
558
559 /* Setup the fundamental net_device and private adapter structure elements */
560 SET_NETDEV_DEV(netdev, &pdev->dev);
561
562 /* Allocate private adapter struct and copy in relevant information */
563 etdev = netdev_priv(netdev);
564 etdev->pdev = pci_dev_get(pdev);
565 etdev->netdev = netdev;
566
567 /* Do the same for the netdev struct */
568 netdev->irq = pdev->irq;
569 netdev->base_addr = pci_resource_start(pdev, 0);
570
571 /* Initialize spinlocks here */
572 spin_lock_init(&etdev->Lock);
573 spin_lock_init(&etdev->TCBSendQLock);
574 spin_lock_init(&etdev->TCBReadyQLock);
575 spin_lock_init(&etdev->SendHWLock);
576 spin_lock_init(&etdev->SendWaitLock);
577 spin_lock_init(&etdev->RcvLock);
578 spin_lock_init(&etdev->RcvPendLock);
579 spin_lock_init(&etdev->FbrLock);
580 spin_lock_init(&etdev->PHYLock);
581
582 /* Parse configuration parameters into the private adapter struct */
8c5f20f3 583 if (et131x_speed_set)
15700039
AC
584 dev_info(&etdev->pdev->dev,
585 "Speed set manually to : %d \n", et131x_speed_set);
8c5f20f3
AC
586
587 etdev->SpeedDuplex = et131x_speed_set;
588 etdev->RegistryJumboPacket = 1514; /* 1514-9216 */
589
8c5f20f3
AC
590 /* Set the MAC address to a default */
591 memcpy(etdev->CurrentAddress, default_mac, ETH_ALEN);
592
593 /* Decode SpeedDuplex
594 *
595 * Set up as if we are auto negotiating always and then change if we
596 * go into force mode
597 *
598 * If we are the 10/100 device, and gigabit is somehow requested then
599 * knock it down to 100 full.
600 */
601 if (etdev->pdev->device == ET131X_PCI_DEVICE_ID_FAST &&
602 etdev->SpeedDuplex == 5)
603 etdev->SpeedDuplex = 4;
604
605 etdev->AiForceSpeed = speed[etdev->SpeedDuplex];
606 etdev->AiForceDpx = duplex[etdev->SpeedDuplex]; /* Auto FDX */
8c5f20f3 607
c431e3c0 608 return etdev;
7ca5d422
AC
609}
610
cfb739b4
GKH
611/**
612 * et131x_pci_setup - Perform device initialization
613 * @pdev: a pointer to the device's pci_dev structure
614 * @ent: this device's entry in the pci_device_id table
615 *
616 * Returns 0 on success, errno on failure (as defined in errno.h)
617 *
618 * Registered in the pci_driver structure, this function is called when the
619 * PCI subsystem finds a new PCI device which matches the information
620 * contained in the pci_device_id table. This routine is the equivalent to
621 * a device insertion routine.
622 */
7ca5d422 623
c431e3c0 624static int __devinit et131x_pci_setup(struct pci_dev *pdev,
cfb739b4
GKH
625 const struct pci_device_id *ent)
626{
c431e3c0 627 int result = -EBUSY;
cfb739b4
GKH
628 int pm_cap;
629 bool pci_using_dac;
c431e3c0
AC
630 struct net_device *netdev;
631 struct et131x_adapter *adapter;
cfb739b4 632
cfb739b4 633 /* Enable the device via the PCI subsystem */
c431e3c0
AC
634 if (pci_enable_device(pdev) != 0) {
635 dev_err(&pdev->dev,
15700039 636 "pci_enable_device() failed\n");
c431e3c0 637 return -EIO;
cfb739b4
GKH
638 }
639
640 /* Perform some basic PCI checks */
641 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
c431e3c0 642 dev_err(&pdev->dev,
cfb739b4 643 "Can't find PCI device's base address\n");
c431e3c0 644 goto err_disable;
cfb739b4
GKH
645 }
646
c431e3c0
AC
647 if (pci_request_regions(pdev, DRIVER_NAME)) {
648 dev_err(&pdev->dev,
15700039 649 "Can't get PCI resources\n");
cfb739b4
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650 goto err_disable;
651 }
652
653 /* Enable PCI bus mastering */
cfb739b4
GKH
654 pci_set_master(pdev);
655
656 /* Query PCI for Power Mgmt Capabilities
657 *
658 * NOTE: Now reading PowerMgmt in another location; is this still
659 * needed?
660 */
661 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
662 if (pm_cap == 0) {
c431e3c0 663 dev_err(&pdev->dev,
cfb739b4
GKH
664 "Cannot find Power Management capabilities\n");
665 result = -EIO;
666 goto err_release_res;
667 }
668
669 /* Check the DMA addressing support of this device */
c431e3c0 670 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
cfb739b4
GKH
671 pci_using_dac = true;
672
c431e3c0 673 result = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
cfb739b4 674 if (result != 0) {
15700039 675 dev_err(&pdev->dev,
cfb739b4
GKH
676 "Unable to obtain 64 bit DMA for consistent allocations\n");
677 goto err_release_res;
678 }
c431e3c0 679 } else if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
cfb739b4
GKH
680 pci_using_dac = false;
681 } else {
c431e3c0 682 dev_err(&pdev->dev,
15700039 683 "No usable DMA addressing method\n");
cfb739b4
GKH
684 result = -EIO;
685 goto err_release_res;
686 }
687
688 /* Allocate netdev and private adapter structs */
cfb739b4
GKH
689 netdev = et131x_device_alloc();
690 if (netdev == NULL) {
c431e3c0 691 dev_err(&pdev->dev, "Couldn't alloc netdev struct\n");
cfb739b4
GKH
692 result = -ENOMEM;
693 goto err_release_res;
694 }
c431e3c0
AC
695 adapter = et131x_adapter_init(netdev, pdev);
696 /* Initialise the PCI setup for the device */
697 et131x_pci_init(adapter, pdev);
cfb739b4
GKH
698
699 /* Map the bus-relative registers to system virtual memory */
c431e3c0 700 adapter->regs = pci_ioremap_bar(pdev, 0);
f3f415a3 701 if (adapter->regs == NULL) {
15700039 702 dev_err(&pdev->dev, "Cannot map device registers\n");
cfb739b4
GKH
703 result = -ENOMEM;
704 goto err_free_dev;
705 }
706
cfb739b4 707 /* If Phy COMA mode was enabled when we went down, disable it here. */
f2c98d27 708 writel(ET_PMCSR_INIT, &adapter->regs->global.pm_csr);
cfb739b4
GKH
709
710 /* Issue a global reset to the et1310 */
cfb739b4
GKH
711 et131x_soft_reset(adapter);
712
713 /* Disable all interrupts (paranoid) */
cfb739b4
GKH
714 et131x_disable_interrupts(adapter);
715
716 /* Allocate DMA memory */
717 result = et131x_adapter_memory_alloc(adapter);
718 if (result != 0) {
15700039 719 dev_err(&pdev->dev, "Could not alloc adapater memory (DMA)\n");
cfb739b4
GKH
720 goto err_iounmap;
721 }
722
723 /* Init send data structures */
cfb739b4
GKH
724 et131x_init_send(adapter);
725
c431e3c0
AC
726 /*
727 * Set up the task structure for the ISR's deferred handler
cfb739b4
GKH
728 */
729 INIT_WORK(&adapter->task, et131x_isr_handler);
730
c431e3c0 731 /* Copy address into the net_device struct */
cfb739b4
GKH
732 memcpy(netdev->dev_addr, adapter->CurrentAddress, ETH_ALEN);
733
734 /* Setup et1310 as per the documentation */
cfb739b4
GKH
735 et131x_adapter_setup(adapter);
736
737 /* Create a timer to count errors received by the NIC */
738 init_timer(&adapter->ErrorTimer);
739
740 adapter->ErrorTimer.expires = jiffies + TX_ERROR_PERIOD * HZ / 1000;
741 adapter->ErrorTimer.function = et131x_error_timer_handler;
742 adapter->ErrorTimer.data = (unsigned long)adapter;
743
744 /* Initialize link state */
745 et131x_link_detection_handler((unsigned long)adapter);
746
64f93036
AC
747 /* Intialize variable for counting how long we do not have
748 link status */
cfb739b4
GKH
749 adapter->PoMgmt.TransPhyComaModeOnBoot = 0;
750
751 /* We can enable interrupts now
752 *
753 * NOTE - Because registration of interrupt handler is done in the
754 * device's open(), defer enabling device interrupts to that
755 * point
756 */
757
758 /* Register the net_device struct with the Linux network layer */
64f93036
AC
759 result = register_netdev(netdev);
760 if (result != 0) {
15700039 761 dev_err(&pdev->dev, "register_netdev() failed\n");
cfb739b4
GKH
762 goto err_mem_free;
763 }
764
765 /* Register the net_device struct with the PCI subsystem. Save a copy
766 * of the PCI config space for this device now that the device has
767 * been initialized, just in case it needs to be quickly restored.
768 */
769 pci_set_drvdata(pdev, netdev);
cfb739b4 770 pci_save_state(adapter->pdev);
cfb739b4
GKH
771 return result;
772
773err_mem_free:
774 et131x_adapter_memory_free(adapter);
775err_iounmap:
f3f415a3 776 iounmap(adapter->regs);
cfb739b4 777err_free_dev:
6ae56042 778 pci_dev_put(pdev);
cfb739b4
GKH
779 free_netdev(netdev);
780err_release_res:
781 pci_release_regions(pdev);
782err_disable:
783 pci_disable_device(pdev);
c431e3c0
AC
784 return result;
785}
786
787/**
788 * et131x_pci_remove
789 * @pdev: a pointer to the device's pci_dev structure
790 *
791 * Registered in the pci_driver structure, this function is called when the
792 * PCI subsystem detects that a PCI device which matches the information
793 * contained in the pci_device_id table has been removed.
794 */
795
796static void __devexit et131x_pci_remove(struct pci_dev *pdev)
797{
798 struct net_device *netdev;
799 struct et131x_adapter *adapter;
800
801 /* Retrieve the net_device pointer from the pci_dev struct, as well
802 * as the private adapter struct
803 */
804 netdev = (struct net_device *) pci_get_drvdata(pdev);
805 adapter = netdev_priv(netdev);
806
807 /* Perform device cleanup */
808 unregister_netdev(netdev);
809 et131x_adapter_memory_free(adapter);
810 iounmap(adapter->regs);
811 pci_dev_put(adapter->pdev);
812 free_netdev(netdev);
813 pci_release_regions(pdev);
814 pci_disable_device(pdev);
cfb739b4 815}
7ca5d422
AC
816
817static struct pci_device_id et131x_pci_table[] __devinitdata = {
818 {ET131X_PCI_VENDOR_ID, ET131X_PCI_DEVICE_ID_GIG, PCI_ANY_ID,
819 PCI_ANY_ID, 0, 0, 0UL},
820 {ET131X_PCI_VENDOR_ID, ET131X_PCI_DEVICE_ID_FAST, PCI_ANY_ID,
821 PCI_ANY_ID, 0, 0, 0UL},
822 {0,}
823};
824
825MODULE_DEVICE_TABLE(pci, et131x_pci_table);
826
827static struct pci_driver et131x_driver = {
828 .name = DRIVER_NAME,
829 .id_table = et131x_pci_table,
830 .probe = et131x_pci_setup,
831 .remove = __devexit_p(et131x_pci_remove),
832 .suspend = NULL, /* et131x_pci_suspend */
833 .resume = NULL, /* et131x_pci_resume */
834};
835
836
837/**
838 * et131x_init_module - The "main" entry point called on driver initialization
839 *
840 * Returns 0 on success, errno on failure (as defined in errno.h)
841 */
3c0d4464 842static int __init et131x_init_module(void)
7ca5d422
AC
843{
844 if (et131x_speed_set < PARM_SPEED_DUPLEX_MIN ||
845 et131x_speed_set > PARM_SPEED_DUPLEX_MAX) {
846 printk(KERN_WARNING "et131x: invalid speed setting ignored.\n");
847 et131x_speed_set = 0;
848 }
849 return pci_register_driver(&et131x_driver);
850}
851
852/**
853 * et131x_cleanup_module - The entry point called on driver cleanup
854 */
3c0d4464 855static void __exit et131x_cleanup_module(void)
7ca5d422
AC
856{
857 pci_unregister_driver(&et131x_driver);
858}
859
860module_init(et131x_init_module);
861module_exit(et131x_cleanup_module);
862
7ca5d422
AC
863/* Modinfo parameters (filled out using defines from et131x_version.h) */
864MODULE_AUTHOR(DRIVER_AUTHOR);
865MODULE_DESCRIPTION(DRIVER_INFO);
866MODULE_LICENSE(DRIVER_LICENSE);