include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit...
[linux-2.6-block.git] / drivers / staging / comedi / drivers / amplc_pci224.c
CommitLineData
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1/*
2 comedi/drivers/amplc_pci224.c
3 Driver for Amplicon PCI224 and PCI234 AO boards.
4
5 Copyright (C) 2005 MEV Ltd. <http://www.mev.co.uk/>
6
7 COMEDI - Linux Control and Measurement Device Interface
8 Copyright (C) 1998,2000 David A. Schleef <ds@schleef.org>
9
10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2 of the License, or
13 (at your option) any later version.
14
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
19
20 You should have received a copy of the GNU General Public License
21 along with this program; if not, write to the Free Software
22 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23
24*/
25/*
26Driver: amplc_pci224
27Description: Amplicon PCI224, PCI234
28Author: Ian Abbott <abbotti@mev.co.uk>
29Devices: [Amplicon] PCI224 (amplc_pci224 or pci224),
30 PCI234 (amplc_pci224 or pci234)
31Updated: Wed, 22 Oct 2008 12:25:08 +0100
32Status: works, but see caveats
33
34Supports:
35
36 - ao_insn read/write
37 - ao_do_cmd mode with the following sources:
38
39 - start_src TRIG_INT TRIG_EXT
40 - scan_begin_src TRIG_TIMER TRIG_EXT
41 - convert_src TRIG_NOW
42 - scan_end_src TRIG_COUNT
43 - stop_src TRIG_COUNT TRIG_EXT TRIG_NONE
44
45 The channel list must contain at least one channel with no repeated
46 channels. The scan end count must equal the number of channels in
47 the channel list.
48
49 There is only one external trigger source so only one of start_src,
50 scan_begin_src or stop_src may use TRIG_EXT.
51
52Configuration options - PCI224:
53 [0] - PCI bus of device (optional).
54 [1] - PCI slot of device (optional).
55 If bus/slot is not specified, the first available PCI device
56 will be used.
57 [2] - Select available ranges according to jumper LK1. All channels
58 are set to the same range:
59 0=Jumper position 1-2 (factory default), 4 software-selectable
60 internal voltage references, giving 4 bipolar and 4 unipolar
61 ranges:
62 [-10V,+10V], [-5V,+5V], [-2.5V,+2.5V], [-1.25V,+1.25V],
63 [0,+10V], [0,+5V], [0,+2.5V], [0,1.25V].
64 1=Jumper position 2-3, 1 external voltage reference, giving
65 1 bipolar and 1 unipolar range:
66 [-Vext,+Vext], [0,+Vext].
67
68Configuration options - PCI234:
69 [0] - PCI bus of device (optional).
70 [1] - PCI slot of device (optional).
71 If bus/slot is not specified, the first available PCI device
72 will be used.
73 [2] - Select internal or external voltage reference according to
74 jumper LK1. This affects all channels:
75 0=Jumper position 1-2 (factory default), Vref=5V internal.
76 1=Jumper position 2-3, Vref=Vext external.
77 [3] - Select channel 0 range according to jumper LK2:
78 0=Jumper position 2-3 (factory default), range [-2*Vref,+2*Vref]
79 (10V bipolar when options[2]=0).
80 1=Jumper position 1-2, range [-Vref,+Vref]
81 (5V bipolar when options[2]=0).
82 [4] - Select channel 1 range according to jumper LK3: cf. options[3].
83 [5] - Select channel 2 range according to jumper LK4: cf. options[3].
84 [6] - Select channel 3 range according to jumper LK5: cf. options[3].
85
86Passing a zero for an option is the same as leaving it unspecified.
87
88Caveats:
89
90 1) All channels on the PCI224 share the same range. Any change to the
91 range as a result of insn_write or a streaming command will affect
92 the output voltages of all channels, including those not specified
93 by the instruction or command.
94
95 2) For the analog output command, the first scan may be triggered
96 falsely at the start of acquisition. This occurs when the DAC scan
97 trigger source is switched from 'none' to 'timer' (scan_begin_src =
98 TRIG_TIMER) or 'external' (scan_begin_src == TRIG_EXT) at the start
99 of acquisition and the trigger source is at logic level 1 at the
100 time of the switch. This is very likely for TRIG_TIMER. For
101 TRIG_EXT, it depends on the state of the external line and whether
102 the CR_INVERT flag has been set. The remaining scans are triggered
103 correctly.
104*/
105
70265d24 106#include <linux/interrupt.h>
5a0e3ad6 107#include <linux/slab.h>
70265d24 108
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109#include "../comedidev.h"
110
111#include "comedi_pci.h"
112
113#include "comedi_fc.h"
114#include "8253.h"
115
116#define DRIVER_NAME "amplc_pci224"
117
118/*
119 * PCI IDs.
120 */
121/* #define PCI_VENDOR_ID_AMPLICON 0x14dc */
122#define PCI_DEVICE_ID_AMPLICON_PCI224 0x0007
123#define PCI_DEVICE_ID_AMPLICON_PCI234 0x0008
124#define PCI_DEVICE_ID_INVALID 0xffff
125
126/*
127 * PCI224/234 i/o space 1 (PCIBAR2) registers.
128 */
129#define PCI224_IO1_SIZE 0x20 /* Size of i/o space 1 (8-bit registers) */
130#define PCI224_Z2_CT0 0x14 /* 82C54 counter/timer 0 */
131#define PCI224_Z2_CT1 0x15 /* 82C54 counter/timer 1 */
132#define PCI224_Z2_CT2 0x16 /* 82C54 counter/timer 2 */
133#define PCI224_Z2_CTC 0x17 /* 82C54 counter/timer control word */
134#define PCI224_ZCLK_SCE 0x1A /* Group Z Clock Configuration Register */
135#define PCI224_ZGAT_SCE 0x1D /* Group Z Gate Configuration Register */
136#define PCI224_INT_SCE 0x1E /* ISR Interrupt source mask register */
137 /* /Interrupt status */
138
139/*
140 * PCI224/234 i/o space 2 (PCIBAR3) 16-bit registers.
141 */
142#define PCI224_IO2_SIZE 0x10 /* Size of i/o space 2 (16-bit registers). */
143#define PCI224_DACDATA 0x00 /* (w-o) DAC FIFO data. */
144#define PCI224_SOFTTRIG 0x00 /* (r-o) DAC software scan trigger. */
145#define PCI224_DACCON 0x02 /* (r/w) DAC status/configuration. */
146#define PCI224_FIFOSIZ 0x04 /* (w-o) FIFO size for wraparound mode. */
147#define PCI224_DACCEN 0x06 /* (w-o) DAC channel enable register. */
148
149/*
150 * DACCON values.
151 */
152/* (r/w) Scan trigger. */
153#define PCI224_DACCON_TRIG_MASK (7 << 0)
154#define PCI224_DACCON_TRIG_NONE (0 << 0) /* none */
155#define PCI224_DACCON_TRIG_SW (1 << 0) /* software trig */
156#define PCI224_DACCON_TRIG_EXTP (2 << 0) /* ext +ve edge */
157#define PCI224_DACCON_TRIG_EXTN (3 << 0) /* ext -ve edge */
158#define PCI224_DACCON_TRIG_Z2CT0 (4 << 0) /* Z2 CT0 out */
159#define PCI224_DACCON_TRIG_Z2CT1 (5 << 0) /* Z2 CT1 out */
160#define PCI224_DACCON_TRIG_Z2CT2 (6 << 0) /* Z2 CT2 out */
161/* (r/w) Polarity (PCI224 only, PCI234 always bipolar!). */
162#define PCI224_DACCON_POLAR_MASK (1 << 3)
163#define PCI224_DACCON_POLAR_UNI (0 << 3) /* range [0,Vref] */
164#define PCI224_DACCON_POLAR_BI (1 << 3) /* range [-Vref,Vref] */
165/* (r/w) Internal Vref (PCI224 only, when LK1 in position 1-2). */
166#define PCI224_DACCON_VREF_MASK (3 << 4)
167#define PCI224_DACCON_VREF_1_25 (0 << 4) /* Vref = 1.25V */
168#define PCI224_DACCON_VREF_2_5 (1 << 4) /* Vref = 2.5V */
169#define PCI224_DACCON_VREF_5 (2 << 4) /* Vref = 5V */
170#define PCI224_DACCON_VREF_10 (3 << 4) /* Vref = 10V */
171/* (r/w) Wraparound mode enable (to play back stored waveform). */
172#define PCI224_DACCON_FIFOWRAP (1 << 7)
173/* (r/w) FIFO enable. It MUST be set! */
174#define PCI224_DACCON_FIFOENAB (1 << 8)
175/* (r/w) FIFO interrupt trigger level (most values are not very useful). */
176#define PCI224_DACCON_FIFOINTR_MASK (7 << 9)
177#define PCI224_DACCON_FIFOINTR_EMPTY (0 << 9) /* when empty */
178#define PCI224_DACCON_FIFOINTR_NEMPTY (1 << 9) /* when not empty */
179#define PCI224_DACCON_FIFOINTR_NHALF (2 << 9) /* when not half full */
180#define PCI224_DACCON_FIFOINTR_HALF (3 << 9) /* when half full */
181#define PCI224_DACCON_FIFOINTR_NFULL (4 << 9) /* when not full */
182#define PCI224_DACCON_FIFOINTR_FULL (5 << 9) /* when full */
183/* (r-o) FIFO fill level. */
184#define PCI224_DACCON_FIFOFL_MASK (7 << 12)
185#define PCI224_DACCON_FIFOFL_EMPTY (1 << 12) /* 0 */
186#define PCI224_DACCON_FIFOFL_ONETOHALF (0 << 12) /* [1,2048] */
187#define PCI224_DACCON_FIFOFL_HALFTOFULL (4 << 12) /* [2049,4095] */
188#define PCI224_DACCON_FIFOFL_FULL (6 << 12) /* 4096 */
189/* (r-o) DAC busy flag. */
190#define PCI224_DACCON_BUSY (1 << 15)
191/* (w-o) FIFO reset. */
192#define PCI224_DACCON_FIFORESET (1 << 12)
193/* (w-o) Global reset (not sure what it does). */
194#define PCI224_DACCON_GLOBALRESET (1 << 13)
195
196/*
197 * DAC FIFO size.
198 */
199#define PCI224_FIFO_SIZE 4096
200
201/*
202 * DAC FIFO guaranteed minimum room available, depending on reported fill level.
203 * The maximum room available depends on the reported fill level and how much
204 * has been written!
205 */
206#define PCI224_FIFO_ROOM_EMPTY PCI224_FIFO_SIZE
207#define PCI224_FIFO_ROOM_ONETOHALF (PCI224_FIFO_SIZE / 2)
208#define PCI224_FIFO_ROOM_HALFTOFULL 1
209#define PCI224_FIFO_ROOM_FULL 0
210
211/*
212 * Counter/timer clock input configuration sources.
213 */
214#define CLK_CLK 0 /* reserved (channel-specific clock) */
215#define CLK_10MHZ 1 /* internal 10 MHz clock */
216#define CLK_1MHZ 2 /* internal 1 MHz clock */
217#define CLK_100KHZ 3 /* internal 100 kHz clock */
218#define CLK_10KHZ 4 /* internal 10 kHz clock */
219#define CLK_1KHZ 5 /* internal 1 kHz clock */
220#define CLK_OUTNM1 6 /* output of channel-1 modulo total */
221#define CLK_EXT 7 /* external clock */
222/* Macro to construct clock input configuration register value. */
223#define CLK_CONFIG(chan, src) ((((chan) & 3) << 3) | ((src) & 7))
224/* Timebases in ns. */
225#define TIMEBASE_10MHZ 100
226#define TIMEBASE_1MHZ 1000
227#define TIMEBASE_100KHZ 10000
228#define TIMEBASE_10KHZ 100000
229#define TIMEBASE_1KHZ 1000000
230
231/*
232 * Counter/timer gate input configuration sources.
233 */
234#define GAT_VCC 0 /* VCC (i.e. enabled) */
235#define GAT_GND 1 /* GND (i.e. disabled) */
236#define GAT_EXT 2 /* reserved (external gate input) */
237#define GAT_NOUTNM2 3 /* inverted output of channel-2 modulo total */
238/* Macro to construct gate input configuration register value. */
239#define GAT_CONFIG(chan, src) ((((chan) & 3) << 3) | ((src) & 7))
240
241/*
242 * Summary of CLK_OUTNM1 and GAT_NOUTNM2 connections for PCI224 and PCI234:
243 *
244 * Channel's Channel's
245 * clock input gate input
246 * Channel CLK_OUTNM1 GAT_NOUTNM2
247 * ------- ---------- -----------
248 * Z2-CT0 Z2-CT2-OUT /Z2-CT1-OUT
249 * Z2-CT1 Z2-CT0-OUT /Z2-CT2-OUT
250 * Z2-CT2 Z2-CT1-OUT /Z2-CT0-OUT
251 */
252
253/*
254 * Interrupt enable/status bits
255 */
256#define PCI224_INTR_EXT 0x01 /* rising edge on external input */
257#define PCI224_INTR_DAC 0x04 /* DAC (FIFO) interrupt */
258#define PCI224_INTR_Z2CT1 0x20 /* rising edge on Z2-CT1 output */
259
260#define PCI224_INTR_EDGE_BITS (PCI224_INTR_EXT | PCI224_INTR_Z2CT1)
261#define PCI224_INTR_LEVEL_BITS PCI224_INTR_DACFIFO
262
263/*
264 * Handy macros.
265 */
266
267/* Combine old and new bits. */
268#define COMBINE(old, new, mask) (((old) & ~(mask)) | ((new) & (mask)))
269
270/* A generic null function pointer value. */
271#define NULLFUNC 0
272
273/* Current CPU. XXX should this be hard_smp_processor_id()? */
274#define THISCPU smp_processor_id()
275
276/* State bits for use with atomic bit operations. */
277#define AO_CMD_STARTED 0
278
279/*
280 * Range tables.
281 */
282
283/* The software selectable internal ranges for PCI224 (option[2] == 0). */
9ced1de6 284static const struct comedi_lrange range_pci224_internal = {
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285 8,
286 {
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287 BIP_RANGE(10),
288 BIP_RANGE(5),
289 BIP_RANGE(2.5),
290 BIP_RANGE(1.25),
291 UNI_RANGE(10),
292 UNI_RANGE(5),
293 UNI_RANGE(2.5),
294 UNI_RANGE(1.25),
295 }
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296};
297
298static const unsigned short hwrange_pci224_internal[8] = {
299 PCI224_DACCON_POLAR_BI | PCI224_DACCON_VREF_10,
300 PCI224_DACCON_POLAR_BI | PCI224_DACCON_VREF_5,
301 PCI224_DACCON_POLAR_BI | PCI224_DACCON_VREF_2_5,
302 PCI224_DACCON_POLAR_BI | PCI224_DACCON_VREF_1_25,
303 PCI224_DACCON_POLAR_UNI | PCI224_DACCON_VREF_10,
304 PCI224_DACCON_POLAR_UNI | PCI224_DACCON_VREF_5,
305 PCI224_DACCON_POLAR_UNI | PCI224_DACCON_VREF_2_5,
306 PCI224_DACCON_POLAR_UNI | PCI224_DACCON_VREF_1_25,
307};
308
309/* The software selectable external ranges for PCI224 (option[2] == 1). */
9ced1de6 310static const struct comedi_lrange range_pci224_external = {
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311 2,
312 {
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313 RANGE_ext(-1, 1), /* bipolar [-Vref,+Vref] */
314 RANGE_ext(0, 1), /* unipolar [0,+Vref] */
315 }
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316};
317
318static const unsigned short hwrange_pci224_external[2] = {
319 PCI224_DACCON_POLAR_BI,
320 PCI224_DACCON_POLAR_UNI,
321};
322
323/* The hardware selectable Vref*2 external range for PCI234
324 * (option[2] == 1, option[3+n] == 0). */
9ced1de6 325static const struct comedi_lrange range_pci234_ext2 = {
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326 1,
327 {
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328 RANGE_ext(-2, 2),
329 }
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330};
331
332/* The hardware selectable Vref external range for PCI234
333 * (option[2] == 1, option[3+n] == 1). */
9ced1de6 334static const struct comedi_lrange range_pci234_ext = {
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335 1,
336 {
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337 RANGE_ext(-1, 1),
338 }
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339};
340
341/* This serves for all the PCI234 ranges. */
342static const unsigned short hwrange_pci234[1] = {
343 PCI224_DACCON_POLAR_BI, /* bipolar - hardware ignores it! */
344};
345
346/*
347 * Board descriptions.
348 */
349
350enum pci224_model { any_model, pci224_model, pci234_model };
351
5a676a21 352struct pci224_board {
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353 const char *name;
354 unsigned short devid;
355 enum pci224_model model;
356 unsigned int ao_chans;
357 unsigned int ao_bits;
5a676a21 358};
ea1aeae4 359
5a676a21 360static const struct pci224_board pci224_boards[] = {
ea1aeae4 361 {
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362 .name = "pci224",
363 .devid = PCI_DEVICE_ID_AMPLICON_PCI224,
364 .model = pci224_model,
365 .ao_chans = 16,
366 .ao_bits = 12,
367 },
ea1aeae4 368 {
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369 .name = "pci234",
370 .devid = PCI_DEVICE_ID_AMPLICON_PCI234,
371 .model = pci234_model,
372 .ao_chans = 4,
373 .ao_bits = 16,
374 },
ea1aeae4 375 {
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376 .name = DRIVER_NAME,
377 .devid = PCI_DEVICE_ID_INVALID,
378 .model = any_model, /* wildcard */
379 },
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380};
381
382/*
383 * PCI driver table.
384 */
385
386static DEFINE_PCI_DEVICE_TABLE(pci224_pci_table) = {
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387 {
388 PCI_VENDOR_ID_AMPLICON, PCI_DEVICE_ID_AMPLICON_PCI224,
389 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, {
390 PCI_VENDOR_ID_AMPLICON, PCI_DEVICE_ID_AMPLICON_PCI234,
391 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, {
392 0}
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393};
394
395MODULE_DEVICE_TABLE(pci, pci224_pci_table);
396
397/*
398 * Useful for shorthand access to the particular board structure
399 */
5a676a21 400#define thisboard ((struct pci224_board *)dev->board_ptr)
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401
402/* this structure is for data unique to this hardware driver. If
403 several hardware drivers keep similar information in this structure,
71b5f4f1 404 feel free to suggest moving the variable to the struct comedi_device struct. */
a27872bf 405struct pci224_private {
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406 struct pci_dev *pci_dev; /* PCI device */
407 const unsigned short *hwrange;
408 unsigned long iobase1;
409 unsigned long state;
410 spinlock_t ao_spinlock;
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BP
411 unsigned int *ao_readback;
412 short *ao_scan_vals;
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413 unsigned char *ao_scan_order;
414 int intr_cpuid;
415 short intr_running;
416 unsigned short daccon;
417 unsigned int cached_div1;
418 unsigned int cached_div2;
419 unsigned int ao_stop_count;
420 short ao_stop_continuous;
421 unsigned short ao_enab; /* max 16 channels so 'short' will do */
422 unsigned char intsce;
a27872bf 423};
ea1aeae4 424
a27872bf 425#define devpriv ((struct pci224_private *)dev->private)
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426
427/*
139dfbdf 428 * The struct comedi_driver structure tells the Comedi core module
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429 * which functions to call to configure/deconfigure (attach/detach)
430 * the board, and also about the kernel module that contains
431 * the device code.
432 */
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433static int pci224_attach(struct comedi_device *dev,
434 struct comedi_devconfig *it);
da91b269 435static int pci224_detach(struct comedi_device *dev);
139dfbdf 436static struct comedi_driver driver_amplc_pci224 = {
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437 .driver_name = DRIVER_NAME,
438 .module = THIS_MODULE,
439 .attach = pci224_attach,
440 .detach = pci224_detach,
441 .board_name = &pci224_boards[0].name,
442 .offset = sizeof(struct pci224_board),
8629efa4 443 .num_names = ARRAY_SIZE(pci224_boards),
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444};
445
446COMEDI_PCI_INITCLEANUP(driver_amplc_pci224, pci224_pci_table);
447
448/*
449 * Called from the 'insn_write' function to perform a single write.
450 */
451static void
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452pci224_ao_set_data(struct comedi_device *dev, int chan, int range,
453 unsigned int data)
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454{
455 unsigned short mangled;
456
457 /* Store unmangled data for readback. */
458 devpriv->ao_readback[chan] = data;
459 /* Enable the channel. */
460 outw(1 << chan, dev->iobase + PCI224_DACCEN);
461 /* Set range and reset FIFO. */
462 devpriv->daccon = COMBINE(devpriv->daccon, devpriv->hwrange[range],
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463 (PCI224_DACCON_POLAR_MASK |
464 PCI224_DACCON_VREF_MASK));
ea1aeae4 465 outw(devpriv->daccon | PCI224_DACCON_FIFORESET,
0a85b6f0 466 dev->iobase + PCI224_DACCON);
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467 /*
468 * Mangle the data. The hardware expects:
469 * - bipolar: 16-bit 2's complement
470 * - unipolar: 16-bit unsigned
471 */
472 mangled = (unsigned short)data << (16 - thisboard->ao_bits);
473 if ((devpriv->daccon & PCI224_DACCON_POLAR_MASK) ==
0a85b6f0 474 PCI224_DACCON_POLAR_BI) {
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475 mangled ^= 0x8000;
476 }
477 /* Write mangled data to the FIFO. */
478 outw(mangled, dev->iobase + PCI224_DACDATA);
479 /* Trigger the conversion. */
480 inw(dev->iobase + PCI224_SOFTTRIG);
481}
482
483/*
484 * 'insn_write' function for AO subdevice.
485 */
486static int
da91b269 487pci224_ao_insn_write(struct comedi_device *dev, struct comedi_subdevice *s,
0a85b6f0 488 struct comedi_insn *insn, unsigned int *data)
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489{
490 int i;
491 int chan, range;
492
493 /* Unpack channel and range. */
494 chan = CR_CHAN(insn->chanspec);
495 range = CR_RANGE(insn->chanspec);
496
497 /* Writing a list of values to an AO channel is probably not
498 * very useful, but that's how the interface is defined. */
499 for (i = 0; i < insn->n; i++) {
500 pci224_ao_set_data(dev, chan, range, data[i]);
501 }
502 return i;
503}
504
505/*
506 * 'insn_read' function for AO subdevice.
507 *
508 * N.B. The value read will not be valid if the DAC channel has
509 * never been written successfully since the device was attached
510 * or since the channel has been used by an AO streaming write
511 * command.
512 */
513static int
da91b269 514pci224_ao_insn_read(struct comedi_device *dev, struct comedi_subdevice *s,
0a85b6f0 515 struct comedi_insn *insn, unsigned int *data)
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516{
517 int i;
518 int chan;
519
520 chan = CR_CHAN(insn->chanspec);
521
522 for (i = 0; i < insn->n; i++) {
523 data[i] = devpriv->ao_readback[chan];
524 }
525
526 return i;
527}
528
529/*
530 * Just a wrapper for the inline function 'i8253_cascade_ns_to_timer'.
531 */
532static void
533pci224_cascade_ns_to_timer(int osc_base, unsigned int *d1, unsigned int *d2,
0a85b6f0 534 unsigned int *nanosec, int round_mode)
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535{
536 i8253_cascade_ns_to_timer(osc_base, d1, d2, nanosec, round_mode);
537}
538
539/*
540 * Kills a command running on the AO subdevice.
541 */
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542static void pci224_ao_stop(struct comedi_device *dev,
543 struct comedi_subdevice *s)
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544{
545 unsigned long flags;
546
547 if (!test_and_clear_bit(AO_CMD_STARTED, &devpriv->state)) {
548 return;
549 }
550
5f74ea14 551 spin_lock_irqsave(&devpriv->ao_spinlock, flags);
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552 /* Kill the interrupts. */
553 devpriv->intsce = 0;
554 outb(0, devpriv->iobase1 + PCI224_INT_SCE);
555 /*
556 * Interrupt routine may or may not be running. We may or may not
557 * have been called from the interrupt routine (directly or
558 * indirectly via a comedi_events() callback routine). It's highly
559 * unlikely that we've been called from some other interrupt routine
560 * but who knows what strange things coders get up to!
561 *
562 * If the interrupt routine is currently running, wait for it to
563 * finish, unless we appear to have been called via the interrupt
564 * routine.
565 */
566 while (devpriv->intr_running && devpriv->intr_cpuid != THISCPU) {
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567 spin_unlock_irqrestore(&devpriv->ao_spinlock, flags);
568 spin_lock_irqsave(&devpriv->ao_spinlock, flags);
ea1aeae4 569 }
5f74ea14 570 spin_unlock_irqrestore(&devpriv->ao_spinlock, flags);
ea1aeae4
IA
571 /* Reconfigure DAC for insn_write usage. */
572 outw(0, dev->iobase + PCI224_DACCEN); /* Disable channels. */
573 devpriv->daccon = COMBINE(devpriv->daccon,
0a85b6f0
MT
574 PCI224_DACCON_TRIG_SW |
575 PCI224_DACCON_FIFOINTR_EMPTY,
576 PCI224_DACCON_TRIG_MASK |
577 PCI224_DACCON_FIFOINTR_MASK);
ea1aeae4 578 outw(devpriv->daccon | PCI224_DACCON_FIFORESET,
0a85b6f0 579 dev->iobase + PCI224_DACCON);
ea1aeae4
IA
580}
581
582/*
583 * Handles start of acquisition for the AO subdevice.
584 */
0a85b6f0
MT
585static void pci224_ao_start(struct comedi_device *dev,
586 struct comedi_subdevice *s)
ea1aeae4 587{
ea6d0d4c 588 struct comedi_cmd *cmd = &s->async->cmd;
ea1aeae4
IA
589 unsigned long flags;
590
591 set_bit(AO_CMD_STARTED, &devpriv->state);
592 if (!devpriv->ao_stop_continuous && devpriv->ao_stop_count == 0) {
593 /* An empty acquisition! */
594 pci224_ao_stop(dev, s);
595 s->async->events |= COMEDI_CB_EOA;
596 comedi_event(dev, s);
597 } else {
598 /* Enable interrupts. */
5f74ea14 599 spin_lock_irqsave(&devpriv->ao_spinlock, flags);
ea1aeae4
IA
600 if (cmd->stop_src == TRIG_EXT) {
601 devpriv->intsce = PCI224_INTR_EXT | PCI224_INTR_DAC;
602 } else {
603 devpriv->intsce = PCI224_INTR_DAC;
604 }
605 outb(devpriv->intsce, devpriv->iobase1 + PCI224_INT_SCE);
5f74ea14 606 spin_unlock_irqrestore(&devpriv->ao_spinlock, flags);
ea1aeae4
IA
607 }
608}
609
610/*
611 * Handles interrupts from the DAC FIFO.
612 */
0a85b6f0
MT
613static void pci224_ao_handle_fifo(struct comedi_device *dev,
614 struct comedi_subdevice *s)
ea1aeae4 615{
ea6d0d4c 616 struct comedi_cmd *cmd = &s->async->cmd;
ea1aeae4
IA
617 unsigned int num_scans;
618 unsigned int room;
619 unsigned short dacstat;
620 unsigned int i, n;
621 unsigned int bytes_per_scan;
622
623 if (cmd->chanlist_len) {
790c5541 624 bytes_per_scan = cmd->chanlist_len * sizeof(short);
ea1aeae4
IA
625 } else {
626 /* Shouldn't get here! */
790c5541 627 bytes_per_scan = sizeof(short);
ea1aeae4
IA
628 }
629 /* Determine number of scans available in buffer. */
630 num_scans = comedi_buf_read_n_available(s->async) / bytes_per_scan;
631 if (!devpriv->ao_stop_continuous) {
632 /* Fixed number of scans. */
633 if (num_scans > devpriv->ao_stop_count) {
634 num_scans = devpriv->ao_stop_count;
635 }
636 }
637
638 /* Determine how much room is in the FIFO (in samples). */
639 dacstat = inw(dev->iobase + PCI224_DACCON);
640 switch (dacstat & PCI224_DACCON_FIFOFL_MASK) {
641 case PCI224_DACCON_FIFOFL_EMPTY:
642 room = PCI224_FIFO_ROOM_EMPTY;
0a85b6f0 643 if (!devpriv->ao_stop_continuous && devpriv->ao_stop_count == 0) {
ea1aeae4
IA
644 /* FIFO empty at end of counted acquisition. */
645 pci224_ao_stop(dev, s);
646 s->async->events |= COMEDI_CB_EOA;
647 comedi_event(dev, s);
648 return;
649 }
650 break;
651 case PCI224_DACCON_FIFOFL_ONETOHALF:
652 room = PCI224_FIFO_ROOM_ONETOHALF;
653 break;
654 case PCI224_DACCON_FIFOFL_HALFTOFULL:
655 room = PCI224_FIFO_ROOM_HALFTOFULL;
656 break;
657 default:
658 room = PCI224_FIFO_ROOM_FULL;
659 break;
660 }
661 if (room >= PCI224_FIFO_ROOM_ONETOHALF) {
662 /* FIFO is less than half-full. */
663 if (num_scans == 0) {
664 /* Nothing left to put in the FIFO. */
665 pci224_ao_stop(dev, s);
666 s->async->events |= COMEDI_CB_OVERFLOW;
5f74ea14 667 printk(KERN_ERR "comedi%d: "
0a85b6f0 668 "AO buffer underrun\n", dev->minor);
ea1aeae4
IA
669 }
670 }
671 /* Determine how many new scans can be put in the FIFO. */
672 if (cmd->chanlist_len) {
673 room /= cmd->chanlist_len;
674 }
675 /* Determine how many scans to process. */
676 if (num_scans > room) {
677 num_scans = room;
678 }
679 /* Process scans. */
680 for (n = 0; n < num_scans; n++) {
681 cfc_read_array_from_buffer(s, &devpriv->ao_scan_vals[0],
0a85b6f0 682 bytes_per_scan);
ea1aeae4 683 for (i = 0; i < cmd->chanlist_len; i++) {
0a85b6f0
MT
684 outw(devpriv->ao_scan_vals[devpriv->ao_scan_order[i]],
685 dev->iobase + PCI224_DACDATA);
ea1aeae4
IA
686 }
687 }
688 if (!devpriv->ao_stop_continuous) {
689 devpriv->ao_stop_count -= num_scans;
690 if (devpriv->ao_stop_count == 0) {
691 /*
692 * Change FIFO interrupt trigger level to wait
693 * until FIFO is empty.
694 */
695 devpriv->daccon = COMBINE(devpriv->daccon,
0a85b6f0
MT
696 PCI224_DACCON_FIFOINTR_EMPTY,
697 PCI224_DACCON_FIFOINTR_MASK);
698 outw(devpriv->daccon, dev->iobase + PCI224_DACCON);
ea1aeae4
IA
699 }
700 }
701 if ((devpriv->daccon & PCI224_DACCON_TRIG_MASK) ==
0a85b6f0 702 PCI224_DACCON_TRIG_NONE) {
ea1aeae4
IA
703 unsigned short trig;
704
705 /*
706 * This is the initial DAC FIFO interrupt at the
707 * start of the acquisition. The DAC's scan trigger
708 * has been set to 'none' up until now.
709 *
710 * Now that data has been written to the FIFO, the
711 * DAC's scan trigger source can be set to the
712 * correct value.
713 *
714 * BUG: The first scan will be triggered immediately
715 * if the scan trigger source is at logic level 1.
716 */
717 if (cmd->scan_begin_src == TRIG_TIMER) {
718 trig = PCI224_DACCON_TRIG_Z2CT0;
719 } else {
720 /* cmd->scan_begin_src == TRIG_EXT */
721 if (cmd->scan_begin_arg & CR_INVERT) {
722 trig = PCI224_DACCON_TRIG_EXTN;
723 } else {
724 trig = PCI224_DACCON_TRIG_EXTP;
725 }
726 }
727 devpriv->daccon = COMBINE(devpriv->daccon, trig,
0a85b6f0 728 PCI224_DACCON_TRIG_MASK);
ea1aeae4
IA
729 outw(devpriv->daccon, dev->iobase + PCI224_DACCON);
730 }
731 if (s->async->events) {
732 comedi_event(dev, s);
733 }
734}
735
736/*
737 * Internal trigger function to start acquisition on AO subdevice.
738 */
739static int
da91b269 740pci224_ao_inttrig_start(struct comedi_device *dev, struct comedi_subdevice *s,
0a85b6f0 741 unsigned int trignum)
ea1aeae4
IA
742{
743 if (trignum != 0)
744 return -EINVAL;
745
746 s->async->inttrig = NULLFUNC;
747 pci224_ao_start(dev, s);
748
749 return 1;
750}
751
752#define MAX_SCAN_PERIOD 0xFFFFFFFFU
753#define MIN_SCAN_PERIOD 2500
754#define CONVERT_PERIOD 625
755
756/*
757 * 'do_cmdtest' function for AO subdevice.
758 */
759static int
0a85b6f0
MT
760pci224_ao_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
761 struct comedi_cmd *cmd)
ea1aeae4
IA
762{
763 int err = 0;
764 unsigned int tmp;
765
766 /* Step 1: make sure trigger sources are trivially valid. */
767
768 tmp = cmd->start_src;
769 cmd->start_src &= TRIG_INT | TRIG_EXT;
770 if (!cmd->start_src || tmp != cmd->start_src)
771 err++;
772
773 tmp = cmd->scan_begin_src;
774 cmd->scan_begin_src &= TRIG_EXT | TRIG_TIMER;
775 if (!cmd->scan_begin_src || tmp != cmd->scan_begin_src)
776 err++;
777
778 tmp = cmd->convert_src;
779 cmd->convert_src &= TRIG_NOW;
780 if (!cmd->convert_src || tmp != cmd->convert_src)
781 err++;
782
783 tmp = cmd->scan_end_src;
784 cmd->scan_end_src &= TRIG_COUNT;
785 if (!cmd->scan_end_src || tmp != cmd->scan_end_src)
786 err++;
787
788 tmp = cmd->stop_src;
789 cmd->stop_src &= TRIG_COUNT | TRIG_EXT | TRIG_NONE;
790 if (!cmd->stop_src || tmp != cmd->stop_src)
791 err++;
792
793 if (err)
794 return 1;
795
796 /* Step 2: make sure trigger sources are unique and mutually
797 * compatible. */
798
799 /* these tests are true if more than one _src bit is set */
800 if ((cmd->start_src & (cmd->start_src - 1)) != 0)
801 err++;
802 if ((cmd->scan_begin_src & (cmd->scan_begin_src - 1)) != 0)
803 err++;
804 if ((cmd->convert_src & (cmd->convert_src - 1)) != 0)
805 err++;
806 if ((cmd->scan_end_src & (cmd->scan_end_src - 1)) != 0)
807 err++;
808 if ((cmd->stop_src & (cmd->stop_src - 1)) != 0)
809 err++;
810
811 /* There's only one external trigger signal (which makes these
812 * tests easier). Only one thing can use it. */
813 tmp = 0;
814 if (cmd->start_src & TRIG_EXT)
815 tmp++;
816 if (cmd->scan_begin_src & TRIG_EXT)
817 tmp++;
818 if (cmd->stop_src & TRIG_EXT)
819 tmp++;
820 if (tmp > 1)
821 err++;
822
823 if (err)
824 return 2;
825
826 /* Step 3: make sure arguments are trivially compatible. */
827
828 switch (cmd->start_src) {
829 case TRIG_INT:
830 if (cmd->start_arg != 0) {
831 cmd->start_arg = 0;
832 err++;
833 }
834 break;
835 case TRIG_EXT:
836 /* Force to external trigger 0. */
837 if ((cmd->start_arg & ~CR_FLAGS_MASK) != 0) {
838 cmd->start_arg = COMBINE(cmd->start_arg, 0,
0a85b6f0 839 ~CR_FLAGS_MASK);
ea1aeae4
IA
840 err++;
841 }
842 /* The only flag allowed is CR_EDGE, which is ignored. */
843 if ((cmd->start_arg & CR_FLAGS_MASK & ~CR_EDGE) != 0) {
844 cmd->start_arg = COMBINE(cmd->start_arg, 0,
0a85b6f0 845 CR_FLAGS_MASK & ~CR_EDGE);
ea1aeae4
IA
846 err++;
847 }
848 break;
849 }
850
851 switch (cmd->scan_begin_src) {
852 case TRIG_TIMER:
853 if (cmd->scan_begin_arg > MAX_SCAN_PERIOD) {
854 cmd->scan_begin_arg = MAX_SCAN_PERIOD;
855 err++;
856 }
857 tmp = cmd->chanlist_len * CONVERT_PERIOD;
858 if (tmp < MIN_SCAN_PERIOD) {
859 tmp = MIN_SCAN_PERIOD;
860 }
861 if (cmd->scan_begin_arg < tmp) {
862 cmd->scan_begin_arg = tmp;
863 err++;
864 }
865 break;
866 case TRIG_EXT:
867 /* Force to external trigger 0. */
868 if ((cmd->scan_begin_arg & ~CR_FLAGS_MASK) != 0) {
869 cmd->scan_begin_arg = COMBINE(cmd->scan_begin_arg, 0,
0a85b6f0 870 ~CR_FLAGS_MASK);
ea1aeae4
IA
871 err++;
872 }
873 /* Only allow flags CR_EDGE and CR_INVERT. Ignore CR_EDGE. */
874 if ((cmd->scan_begin_arg & CR_FLAGS_MASK &
0a85b6f0 875 ~(CR_EDGE | CR_INVERT)) != 0) {
ea1aeae4 876 cmd->scan_begin_arg = COMBINE(cmd->scan_begin_arg, 0,
0a85b6f0
MT
877 CR_FLAGS_MASK & ~(CR_EDGE
878 |
879 CR_INVERT));
ea1aeae4
IA
880 err++;
881 }
882 break;
883 }
884
885 /* cmd->convert_src == TRIG_NOW */
886 if (cmd->convert_arg != 0) {
887 cmd->convert_arg = 0;
888 err++;
889 }
890
891 /* cmd->scan_end_arg == TRIG_COUNT */
892 if (cmd->scan_end_arg != cmd->chanlist_len) {
893 cmd->scan_end_arg = cmd->chanlist_len;
894 err++;
895 }
896
897 switch (cmd->stop_src) {
898 case TRIG_COUNT:
899 /* Any count allowed. */
900 break;
901 case TRIG_EXT:
902 /* Force to external trigger 0. */
903 if ((cmd->stop_arg & ~CR_FLAGS_MASK) != 0) {
904 cmd->stop_arg = COMBINE(cmd->stop_arg, 0,
0a85b6f0 905 ~CR_FLAGS_MASK);
ea1aeae4
IA
906 err++;
907 }
908 /* The only flag allowed is CR_EDGE, which is ignored. */
909 if ((cmd->stop_arg & CR_FLAGS_MASK & ~CR_EDGE) != 0) {
910 cmd->stop_arg = COMBINE(cmd->stop_arg, 0,
0a85b6f0 911 CR_FLAGS_MASK & ~CR_EDGE);
ea1aeae4
IA
912 }
913 break;
914 case TRIG_NONE:
915 if (cmd->stop_arg != 0) {
916 cmd->stop_arg = 0;
917 err++;
918 }
919 break;
920 }
921
922 if (err)
923 return 3;
924
925 /* Step 4: fix up any arguments. */
926
927 if (cmd->scan_begin_src == TRIG_TIMER) {
928 unsigned int div1, div2, round;
929 int round_mode = cmd->flags & TRIG_ROUND_MASK;
930
931 tmp = cmd->scan_begin_arg;
932 /* Check whether to use a single timer. */
933 switch (round_mode) {
934 case TRIG_ROUND_NEAREST:
935 default:
936 round = TIMEBASE_10MHZ / 2;
937 break;
938 case TRIG_ROUND_DOWN:
939 round = 0;
940 break;
941 case TRIG_ROUND_UP:
942 round = TIMEBASE_10MHZ - 1;
943 break;
944 }
945 /* Be careful to avoid overflow! */
946 div2 = cmd->scan_begin_arg / TIMEBASE_10MHZ;
947 div2 += (round + cmd->scan_begin_arg % TIMEBASE_10MHZ) /
0a85b6f0 948 TIMEBASE_10MHZ;
ea1aeae4
IA
949 if (div2 <= 0x10000) {
950 /* A single timer will suffice. */
951 if (div2 < 2)
952 div2 = 2;
953 cmd->scan_begin_arg = div2 * TIMEBASE_10MHZ;
954 if (cmd->scan_begin_arg < div2 ||
0a85b6f0 955 cmd->scan_begin_arg < TIMEBASE_10MHZ) {
ea1aeae4
IA
956 /* Overflow! */
957 cmd->scan_begin_arg = MAX_SCAN_PERIOD;
958 }
959 } else {
960 /* Use two timers. */
961 div1 = devpriv->cached_div1;
962 div2 = devpriv->cached_div2;
963 pci224_cascade_ns_to_timer(TIMEBASE_10MHZ, &div1, &div2,
0a85b6f0
MT
964 &cmd->scan_begin_arg,
965 round_mode);
ea1aeae4
IA
966 devpriv->cached_div1 = div1;
967 devpriv->cached_div2 = div2;
968 }
969 if (tmp != cmd->scan_begin_arg) {
970 err++;
971 }
972 }
973
974 if (err)
975 return 4;
976
977 /* Step 5: check channel list. */
978
979 if (cmd->chanlist && (cmd->chanlist_len > 0)) {
980 unsigned int range;
981 enum { range_err = 1, dupchan_err = 2, };
982 unsigned errors;
983 unsigned int n;
984 unsigned int ch;
985
986 /*
987 * Check all channels have the same range index. Don't care
988 * about analogue reference, as we can't configure it.
989 *
990 * Check the list has no duplicate channels.
991 */
992 range = CR_RANGE(cmd->chanlist[0]);
993 errors = 0;
994 tmp = 0;
995 for (n = 0; n < cmd->chanlist_len; n++) {
996 ch = CR_CHAN(cmd->chanlist[n]);
997 if (tmp & (1U << ch)) {
998 errors |= dupchan_err;
999 }
1000 tmp |= (1U << ch);
1001 if (CR_RANGE(cmd->chanlist[n]) != range) {
1002 errors |= range_err;
1003 }
1004 }
1005 if (errors) {
1006 if (errors & dupchan_err) {
1007 DPRINTK("comedi%d: " DRIVER_NAME
1008 ": ao_cmdtest: "
1009 "entries in chanlist must contain no "
1010 "duplicate channels\n", dev->minor);
1011 }
1012 if (errors & range_err) {
1013 DPRINTK("comedi%d: " DRIVER_NAME
1014 ": ao_cmdtest: "
1015 "entries in chanlist must all have "
1016 "the same range index\n", dev->minor);
1017 }
1018 err++;
1019 }
1020 }
1021
1022 if (err)
1023 return 5;
1024
1025 return 0;
1026}
1027
1028/*
1029 * 'do_cmd' function for AO subdevice.
1030 */
da91b269 1031static int pci224_ao_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
ea1aeae4 1032{
ea6d0d4c 1033 struct comedi_cmd *cmd = &s->async->cmd;
ea1aeae4
IA
1034 int range;
1035 unsigned int i, j;
1036 unsigned int ch;
1037 unsigned int rank;
1038 unsigned long flags;
1039
1040 /* Cannot handle null/empty chanlist. */
1041 if (cmd->chanlist == NULL || cmd->chanlist_len == 0) {
1042 return -EINVAL;
1043 }
1044
1045 /* Determine which channels are enabled and their load order. */
1046 devpriv->ao_enab = 0;
1047
1048 for (i = 0; i < cmd->chanlist_len; i++) {
1049 ch = CR_CHAN(cmd->chanlist[i]);
1050 devpriv->ao_enab |= 1U << ch;
1051 rank = 0;
1052 for (j = 0; j < cmd->chanlist_len; j++) {
1053 if (CR_CHAN(cmd->chanlist[j]) < ch) {
1054 rank++;
1055 }
1056 }
1057 devpriv->ao_scan_order[rank] = i;
1058 }
1059
1060 /* Set enabled channels. */
1061 outw(devpriv->ao_enab, dev->iobase + PCI224_DACCEN);
1062
1063 /* Determine range and polarity. All channels the same. */
1064 range = CR_RANGE(cmd->chanlist[0]);
1065
1066 /*
1067 * Set DAC range and polarity.
1068 * Set DAC scan trigger source to 'none'.
1069 * Set DAC FIFO interrupt trigger level to 'not half full'.
1070 * Reset DAC FIFO.
1071 *
1072 * N.B. DAC FIFO interrupts are currently disabled.
1073 */
1074 devpriv->daccon = COMBINE(devpriv->daccon,
0a85b6f0
MT
1075 (devpriv->
1076 hwrange[range] | PCI224_DACCON_TRIG_NONE |
1077 PCI224_DACCON_FIFOINTR_NHALF),
1078 (PCI224_DACCON_POLAR_MASK |
1079 PCI224_DACCON_VREF_MASK |
1080 PCI224_DACCON_TRIG_MASK |
1081 PCI224_DACCON_FIFOINTR_MASK));
ea1aeae4 1082 outw(devpriv->daccon | PCI224_DACCON_FIFORESET,
0a85b6f0 1083 dev->iobase + PCI224_DACCON);
ea1aeae4
IA
1084
1085 if (cmd->scan_begin_src == TRIG_TIMER) {
1086 unsigned int div1, div2, round;
1087 unsigned int ns = cmd->scan_begin_arg;
1088 int round_mode = cmd->flags & TRIG_ROUND_MASK;
1089
1090 /* Check whether to use a single timer. */
1091 switch (round_mode) {
1092 case TRIG_ROUND_NEAREST:
1093 default:
1094 round = TIMEBASE_10MHZ / 2;
1095 break;
1096 case TRIG_ROUND_DOWN:
1097 round = 0;
1098 break;
1099 case TRIG_ROUND_UP:
1100 round = TIMEBASE_10MHZ - 1;
1101 break;
1102 }
1103 /* Be careful to avoid overflow! */
1104 div2 = cmd->scan_begin_arg / TIMEBASE_10MHZ;
1105 div2 += (round + cmd->scan_begin_arg % TIMEBASE_10MHZ) /
0a85b6f0 1106 TIMEBASE_10MHZ;
ea1aeae4
IA
1107 if (div2 <= 0x10000) {
1108 /* A single timer will suffice. */
1109 if (div2 < 2)
1110 div2 = 2;
1111 div2 &= 0xffff;
1112 div1 = 1; /* Flag that single timer to be used. */
1113 } else {
1114 /* Use two timers. */
1115 div1 = devpriv->cached_div1;
1116 div2 = devpriv->cached_div2;
1117 pci224_cascade_ns_to_timer(TIMEBASE_10MHZ, &div1, &div2,
0a85b6f0 1118 &ns, round_mode);
ea1aeae4
IA
1119 }
1120
1121 /*
1122 * The output of timer Z2-0 will be used as the scan trigger
1123 * source.
1124 */
1125 /* Make sure Z2-0 is gated on. */
1126 outb(GAT_CONFIG(0, GAT_VCC),
0a85b6f0 1127 devpriv->iobase1 + PCI224_ZGAT_SCE);
ea1aeae4
IA
1128 if (div1 == 1) {
1129 /* Not cascading. Z2-0 needs 10 MHz clock. */
1130 outb(CLK_CONFIG(0, CLK_10MHZ),
0a85b6f0 1131 devpriv->iobase1 + PCI224_ZCLK_SCE);
ea1aeae4
IA
1132 } else {
1133 /* Cascading with Z2-2. */
1134 /* Make sure Z2-2 is gated on. */
1135 outb(GAT_CONFIG(2, GAT_VCC),
0a85b6f0 1136 devpriv->iobase1 + PCI224_ZGAT_SCE);
ea1aeae4
IA
1137 /* Z2-2 needs 10 MHz clock. */
1138 outb(CLK_CONFIG(2, CLK_10MHZ),
0a85b6f0 1139 devpriv->iobase1 + PCI224_ZCLK_SCE);
ea1aeae4
IA
1140 /* Load Z2-2 mode (2) and counter (div1). */
1141 i8254_load(devpriv->iobase1 + PCI224_Z2_CT0, 0,
0a85b6f0 1142 2, div1, 2);
ea1aeae4
IA
1143 /* Z2-0 is clocked from Z2-2's output. */
1144 outb(CLK_CONFIG(0, CLK_OUTNM1),
0a85b6f0 1145 devpriv->iobase1 + PCI224_ZCLK_SCE);
ea1aeae4
IA
1146 }
1147 /* Load Z2-0 mode (2) and counter (div2). */
1148 i8254_load(devpriv->iobase1 + PCI224_Z2_CT0, 0, 0, div2, 2);
1149 }
1150
1151 /*
1152 * Sort out end of acquisition.
1153 */
1154 switch (cmd->stop_src) {
1155 case TRIG_COUNT:
1156 /* Fixed number of scans. */
1157 devpriv->ao_stop_continuous = 0;
1158 devpriv->ao_stop_count = cmd->stop_arg;
1159 break;
1160 default:
1161 /* Continuous scans. */
1162 devpriv->ao_stop_continuous = 1;
1163 devpriv->ao_stop_count = 0;
1164 break;
1165 }
1166
1167 /*
1168 * Sort out start of acquisition.
1169 */
1170 switch (cmd->start_src) {
1171 case TRIG_INT:
5f74ea14 1172 spin_lock_irqsave(&devpriv->ao_spinlock, flags);
ea1aeae4 1173 s->async->inttrig = &pci224_ao_inttrig_start;
5f74ea14 1174 spin_unlock_irqrestore(&devpriv->ao_spinlock, flags);
ea1aeae4
IA
1175 break;
1176 case TRIG_EXT:
1177 /* Enable external interrupt trigger to start acquisition. */
5f74ea14 1178 spin_lock_irqsave(&devpriv->ao_spinlock, flags);
ea1aeae4
IA
1179 devpriv->intsce |= PCI224_INTR_EXT;
1180 outb(devpriv->intsce, devpriv->iobase1 + PCI224_INT_SCE);
5f74ea14 1181 spin_unlock_irqrestore(&devpriv->ao_spinlock, flags);
ea1aeae4
IA
1182 break;
1183 }
1184
1185 return 0;
1186}
1187
1188/*
1189 * 'cancel' function for AO subdevice.
1190 */
0a85b6f0
MT
1191static int pci224_ao_cancel(struct comedi_device *dev,
1192 struct comedi_subdevice *s)
ea1aeae4
IA
1193{
1194 pci224_ao_stop(dev, s);
1195 return 0;
1196}
1197
1198/*
1199 * 'munge' data for AO command.
1200 */
1201static void
0a85b6f0
MT
1202pci224_ao_munge(struct comedi_device *dev, struct comedi_subdevice *s,
1203 void *data, unsigned int num_bytes, unsigned int chan_index)
ea1aeae4 1204{
d163679c 1205 struct comedi_async *async = s->async;
790c5541 1206 short *array = data;
ea1aeae4
IA
1207 unsigned int length = num_bytes / sizeof(*array);
1208 unsigned int offset;
1209 unsigned int shift;
1210 unsigned int i;
1211
1212 /* The hardware expects 16-bit numbers. */
1213 shift = 16 - thisboard->ao_bits;
1214 /* Channels will be all bipolar or all unipolar. */
1215 if ((devpriv->hwrange[CR_RANGE(async->cmd.chanlist[0])] &
0a85b6f0 1216 PCI224_DACCON_POLAR_MASK) == PCI224_DACCON_POLAR_UNI) {
ea1aeae4
IA
1217 /* Unipolar */
1218 offset = 0;
1219 } else {
1220 /* Bipolar */
1221 offset = 32768;
1222 }
1223 /* Munge the data. */
1224 for (i = 0; i < length; i++) {
1225 array[i] = (array[i] << shift) - offset;
1226 }
1227}
1228
1229/*
1230 * Interrupt handler.
1231 */
70265d24 1232static irqreturn_t pci224_interrupt(int irq, void *d)
ea1aeae4 1233{
71b5f4f1 1234 struct comedi_device *dev = d;
34c43922 1235 struct comedi_subdevice *s = &dev->subdevices[0];
ea6d0d4c 1236 struct comedi_cmd *cmd;
ea1aeae4
IA
1237 unsigned char intstat, valid_intstat;
1238 unsigned char curenab;
1239 int retval = 0;
1240 unsigned long flags;
1241
1242 intstat = inb(devpriv->iobase1 + PCI224_INT_SCE) & 0x3F;
1243 if (intstat) {
1244 retval = 1;
5f74ea14 1245 spin_lock_irqsave(&devpriv->ao_spinlock, flags);
ea1aeae4
IA
1246 valid_intstat = devpriv->intsce & intstat;
1247 /* Temporarily disable interrupt sources. */
1248 curenab = devpriv->intsce & ~intstat;
1249 outb(curenab, devpriv->iobase1 + PCI224_INT_SCE);
1250 devpriv->intr_running = 1;
1251 devpriv->intr_cpuid = THISCPU;
5f74ea14 1252 spin_unlock_irqrestore(&devpriv->ao_spinlock, flags);
ea1aeae4
IA
1253 if (valid_intstat != 0) {
1254 cmd = &s->async->cmd;
1255 if (valid_intstat & PCI224_INTR_EXT) {
1256 devpriv->intsce &= ~PCI224_INTR_EXT;
1257 if (cmd->start_src == TRIG_EXT) {
1258 pci224_ao_start(dev, s);
1259 } else if (cmd->stop_src == TRIG_EXT) {
1260 pci224_ao_stop(dev, s);
1261 }
1262 }
1263 if (valid_intstat & PCI224_INTR_DAC) {
1264 pci224_ao_handle_fifo(dev, s);
1265 }
1266 }
1267 /* Reenable interrupt sources. */
5f74ea14 1268 spin_lock_irqsave(&devpriv->ao_spinlock, flags);
ea1aeae4
IA
1269 if (curenab != devpriv->intsce) {
1270 outb(devpriv->intsce,
0a85b6f0 1271 devpriv->iobase1 + PCI224_INT_SCE);
ea1aeae4
IA
1272 }
1273 devpriv->intr_running = 0;
5f74ea14 1274 spin_unlock_irqrestore(&devpriv->ao_spinlock, flags);
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IA
1275 }
1276 return IRQ_RETVAL(retval);
1277}
1278
1279/*
1280 * This function looks for a PCI device matching the requested board name,
1281 * bus and slot.
1282 */
1283static int
da91b269 1284pci224_find_pci(struct comedi_device *dev, int bus, int slot,
0a85b6f0 1285 struct pci_dev **pci_dev_p)
ea1aeae4
IA
1286{
1287 struct pci_dev *pci_dev = NULL;
1288
1289 *pci_dev_p = NULL;
1290
1291 /* Look for matching PCI device. */
1292 for (pci_dev = pci_get_device(PCI_VENDOR_ID_AMPLICON, PCI_ANY_ID, NULL);
0a85b6f0
MT
1293 pci_dev != NULL;
1294 pci_dev = pci_get_device(PCI_VENDOR_ID_AMPLICON, PCI_ANY_ID,
1295 pci_dev)) {
ea1aeae4
IA
1296 /* If bus/slot specified, check them. */
1297 if (bus || slot) {
1298 if (bus != pci_dev->bus->number
0a85b6f0 1299 || slot != PCI_SLOT(pci_dev->devfn))
ea1aeae4
IA
1300 continue;
1301 }
1302 if (thisboard->model == any_model) {
1303 /* Match any supported model. */
1304 int i;
1305
1306 for (i = 0; i < ARRAY_SIZE(pci224_boards); i++) {
1307 if (pci_dev->device == pci224_boards[i].devid) {
1308 /* Change board_ptr to matched board. */
1309 dev->board_ptr = &pci224_boards[i];
1310 break;
1311 }
1312 }
1313 if (i == ARRAY_SIZE(pci224_boards))
1314 continue;
1315 } else {
1316 /* Match specific model name. */
1317 if (thisboard->devid != pci_dev->device)
1318 continue;
1319 }
1320
1321 /* Found a match. */
1322 *pci_dev_p = pci_dev;
1323 return 0;
1324 }
1325 /* No match found. */
1326 if (bus || slot) {
1327 printk(KERN_ERR "comedi%d: error! "
0a85b6f0
MT
1328 "no %s found at pci %02x:%02x!\n",
1329 dev->minor, thisboard->name, bus, slot);
ea1aeae4
IA
1330 } else {
1331 printk(KERN_ERR "comedi%d: error! no %s found!\n",
0a85b6f0 1332 dev->minor, thisboard->name);
ea1aeae4
IA
1333 }
1334 return -EIO;
1335}
1336
1337/*
1338 * Attach is called by the Comedi core to configure the driver
1339 * for a particular board. If you specified a board_name array
1340 * in the driver structure, dev->board_ptr contains that
1341 * address.
1342 */
da91b269 1343static int pci224_attach(struct comedi_device *dev, struct comedi_devconfig *it)
ea1aeae4 1344{
34c43922 1345 struct comedi_subdevice *s;
ea1aeae4
IA
1346 struct pci_dev *pci_dev;
1347 unsigned int irq;
1348 int bus = 0, slot = 0;
1349 unsigned n;
1350 int ret;
1351
1352 printk(KERN_DEBUG "comedi%d: %s: attach\n", dev->minor, DRIVER_NAME);
1353
1354 bus = it->options[0];
1355 slot = it->options[1];
c3744138
BP
1356 ret = alloc_private(dev, sizeof(struct pci224_private));
1357 if (ret < 0) {
ea1aeae4 1358 printk(KERN_ERR "comedi%d: error! out of memory!\n",
0a85b6f0 1359 dev->minor);
ea1aeae4
IA
1360 return ret;
1361 }
c3744138
BP
1362
1363 ret = pci224_find_pci(dev, bus, slot, &pci_dev);
1364 if (ret < 0)
ea1aeae4 1365 return ret;
ea1aeae4 1366
c3744138
BP
1367 devpriv->pci_dev = pci_dev;
1368 ret = comedi_pci_enable(pci_dev, DRIVER_NAME);
1369 if (ret < 0) {
ea1aeae4 1370 printk(KERN_ERR
0a85b6f0
MT
1371 "comedi%d: error! cannot enable PCI device "
1372 "and request regions!\n", dev->minor);
ea1aeae4
IA
1373 return ret;
1374 }
1375 spin_lock_init(&devpriv->ao_spinlock);
1376
1377 devpriv->iobase1 = pci_resource_start(pci_dev, 2);
1378 dev->iobase = pci_resource_start(pci_dev, 3);
1379 irq = pci_dev->irq;
1380
1381 /* Allocate readback buffer for AO channels. */
1382 devpriv->ao_readback = kmalloc(sizeof(devpriv->ao_readback[0]) *
0a85b6f0 1383 thisboard->ao_chans, GFP_KERNEL);
ea1aeae4
IA
1384 if (!devpriv->ao_readback) {
1385 return -ENOMEM;
1386 }
1387
1388 /* Allocate buffer to hold values for AO channel scan. */
1389 devpriv->ao_scan_vals = kmalloc(sizeof(devpriv->ao_scan_vals[0]) *
0a85b6f0 1390 thisboard->ao_chans, GFP_KERNEL);
ea1aeae4
IA
1391 if (!devpriv->ao_scan_vals) {
1392 return -ENOMEM;
1393 }
1394
1395 /* Allocate buffer to hold AO channel scan order. */
1396 devpriv->ao_scan_order = kmalloc(sizeof(devpriv->ao_scan_order[0]) *
0a85b6f0 1397 thisboard->ao_chans, GFP_KERNEL);
ea1aeae4
IA
1398 if (!devpriv->ao_scan_order) {
1399 return -ENOMEM;
1400 }
1401
1402 /* Disable interrupt sources. */
1403 devpriv->intsce = 0;
1404 outb(0, devpriv->iobase1 + PCI224_INT_SCE);
1405
1406 /* Initialize the DAC hardware. */
1407 outw(PCI224_DACCON_GLOBALRESET, dev->iobase + PCI224_DACCON);
1408 outw(0, dev->iobase + PCI224_DACCEN);
1409 outw(0, dev->iobase + PCI224_FIFOSIZ);
1410 devpriv->daccon = (PCI224_DACCON_TRIG_SW | PCI224_DACCON_POLAR_BI |
0a85b6f0
MT
1411 PCI224_DACCON_FIFOENAB |
1412 PCI224_DACCON_FIFOINTR_EMPTY);
ea1aeae4 1413 outw(devpriv->daccon | PCI224_DACCON_FIFORESET,
0a85b6f0 1414 dev->iobase + PCI224_DACCON);
ea1aeae4
IA
1415
1416 /* Allocate subdevices. There is only one! */
c3744138
BP
1417 ret = alloc_subdevices(dev, 1);
1418 if (ret < 0) {
ea1aeae4 1419 printk(KERN_ERR "comedi%d: error! out of memory!\n",
0a85b6f0 1420 dev->minor);
ea1aeae4
IA
1421 return ret;
1422 }
1423
1424 s = dev->subdevices + 0;
1425 /* Analog output subdevice. */
1426 s->type = COMEDI_SUBD_AO;
1427 s->subdev_flags = SDF_WRITABLE | SDF_GROUND | SDF_CMD_WRITE;
1428 s->n_chan = thisboard->ao_chans;
1429 s->maxdata = (1 << thisboard->ao_bits) - 1;
1430 s->insn_write = &pci224_ao_insn_write;
1431 s->insn_read = &pci224_ao_insn_read;
1432 s->len_chanlist = s->n_chan;
1433
1434 dev->write_subdev = s;
1435 s->do_cmd = &pci224_ao_cmd;
1436 s->do_cmdtest = &pci224_ao_cmdtest;
1437 s->cancel = &pci224_ao_cancel;
1438 s->munge = &pci224_ao_munge;
1439
1440 /* Sort out channel range options. */
1441 if (thisboard->model == pci234_model) {
1442 /* PCI234 range options. */
9ced1de6 1443 const struct comedi_lrange **range_table_list;
ea1aeae4
IA
1444
1445 s->range_table_list = range_table_list =
0a85b6f0
MT
1446 kmalloc(sizeof(struct comedi_lrange *) * s->n_chan,
1447 GFP_KERNEL);
ea1aeae4
IA
1448 if (!s->range_table_list) {
1449 return -ENOMEM;
1450 }
1451 for (n = 2; n < 3 + s->n_chan; n++) {
1452 if (it->options[n] < 0 || it->options[n] > 1) {
1453 printk(KERN_WARNING "comedi%d: %s: warning! "
0a85b6f0
MT
1454 "bad options[%u]=%d\n",
1455 dev->minor, DRIVER_NAME, n,
1456 it->options[n]);
ea1aeae4
IA
1457 }
1458 }
1459 for (n = 0; n < s->n_chan; n++) {
1460 if (n < COMEDI_NDEVCONFOPTS - 3 &&
0a85b6f0 1461 it->options[3 + n] == 1) {
ea1aeae4
IA
1462 if (it->options[2] == 1) {
1463 range_table_list[n] = &range_pci234_ext;
1464 } else {
1465 range_table_list[n] = &range_bipolar5;
1466 }
1467 } else {
1468 if (it->options[2] == 1) {
1469 range_table_list[n] =
0a85b6f0 1470 &range_pci234_ext2;
ea1aeae4
IA
1471 } else {
1472 range_table_list[n] = &range_bipolar10;
1473 }
1474 }
1475 }
1476 devpriv->hwrange = hwrange_pci234;
1477 } else {
1478 /* PCI224 range options. */
1479 if (it->options[2] == 1) {
1480 s->range_table = &range_pci224_external;
1481 devpriv->hwrange = hwrange_pci224_external;
1482 } else {
1483 if (it->options[2] != 0) {
1484 printk(KERN_WARNING "comedi%d: %s: warning! "
0a85b6f0
MT
1485 "bad options[2]=%d\n",
1486 dev->minor, DRIVER_NAME, it->options[2]);
ea1aeae4
IA
1487 }
1488 s->range_table = &range_pci224_internal;
1489 devpriv->hwrange = hwrange_pci224_internal;
1490 }
1491 }
1492
1493 dev->board_name = thisboard->name;
1494
1495 if (irq) {
5f74ea14
GKH
1496 ret = request_irq(irq, pci224_interrupt, IRQF_SHARED,
1497 DRIVER_NAME, dev);
ea1aeae4
IA
1498 if (ret < 0) {
1499 printk(KERN_ERR "comedi%d: error! "
0a85b6f0 1500 "unable to allocate irq %u\n", dev->minor, irq);
ea1aeae4
IA
1501 return ret;
1502 } else {
1503 dev->irq = irq;
1504 }
1505 }
1506
1507 printk(KERN_INFO "comedi%d: %s ", dev->minor, dev->board_name);
1508 printk("(pci %s) ", pci_name(pci_dev));
1509 if (irq) {
1510 printk("(irq %u%s) ", irq, (dev->irq ? "" : " UNAVAILABLE"));
1511 } else {
1512 printk("(no irq) ");
1513 }
1514
1515 printk("attached\n");
1516
1517 return 1;
1518}
1519
1520/*
1521 * _detach is called to deconfigure a device. It should deallocate
1522 * resources.
1523 * This function is also called when _attach() fails, so it should be
1524 * careful not to release resources that were not necessarily
1525 * allocated by _attach(). dev->private and dev->subdevices are
1526 * deallocated automatically by the core.
1527 */
da91b269 1528static int pci224_detach(struct comedi_device *dev)
ea1aeae4
IA
1529{
1530 printk(KERN_DEBUG "comedi%d: %s: detach\n", dev->minor, DRIVER_NAME);
1531
1532 if (dev->irq) {
5f74ea14 1533 free_irq(dev->irq, dev);
ea1aeae4
IA
1534 }
1535 if (dev->subdevices) {
34c43922 1536 struct comedi_subdevice *s;
ea1aeae4
IA
1537
1538 s = dev->subdevices + 0;
1539 /* AO subdevice */
48d07f2b 1540 kfree(s->range_table_list);
ea1aeae4
IA
1541 }
1542 if (devpriv) {
48d07f2b 1543 kfree(devpriv->ao_readback);
1544 kfree(devpriv->ao_scan_vals);
1545 kfree(devpriv->ao_scan_order);
ea1aeae4
IA
1546 if (devpriv->pci_dev) {
1547 if (dev->iobase) {
1548 comedi_pci_disable(devpriv->pci_dev);
1549 }
1550 pci_dev_put(devpriv->pci_dev);
1551 }
1552 }
1553 if (dev->board_name) {
1554 printk(KERN_INFO "comedi%d: %s removed\n",
0a85b6f0 1555 dev->minor, dev->board_name);
ea1aeae4
IA
1556 }
1557
1558 return 0;
1559}