[linux-2.6-block.git] / drivers / spi / xilinx_spi.c

/*
 * xilinx_spi.c
 *
 * Xilinx SPI controller driver (master mode only)
 *
 * Author: MontaVista Software, Inc.
 *	source@mvista.com
 *
 * 2002-2007 (c) MontaVista Software, Inc.  This file is licensed under the
 * terms of the GNU General Public License version 2.  This program is licensed
 * "as is" without any warranty of any kind, whether express or implied.
 */

#include <linux/module.h>
#include <linux/init.h>
#include <linux/interrupt.h>

#include <linux/spi/spi.h>
#include <linux/spi/spi_bitbang.h>
#include <linux/io.h>

#include "xilinx_spi.h"
#include <linux/spi/xilinx_spi.h>

#define XILINX_SPI_NAME "xilinx_spi"

/* Register definitions as per "OPB Serial Peripheral Interface (SPI) (v1.00e)
 * Product Specification", DS464
 */
#define XSPI_CR_OFFSET		0x60	/* Control Register */

#define XSPI_CR_ENABLE		0x02
#define XSPI_CR_MASTER_MODE	0x04
#define XSPI_CR_CPOL		0x08
#define XSPI_CR_CPHA		0x10
#define XSPI_CR_MODE_MASK	(XSPI_CR_CPHA | XSPI_CR_CPOL)
#define XSPI_CR_TXFIFO_RESET	0x20
#define XSPI_CR_RXFIFO_RESET	0x40
#define XSPI_CR_MANUAL_SSELECT	0x80
#define XSPI_CR_TRANS_INHIBIT	0x100
#define XSPI_CR_LSB_FIRST	0x200

#define XSPI_SR_OFFSET		0x64	/* Status Register */

#define XSPI_SR_RX_EMPTY_MASK	0x01	/* Receive FIFO is empty */
#define XSPI_SR_RX_FULL_MASK	0x02	/* Receive FIFO is full */
#define XSPI_SR_TX_EMPTY_MASK	0x04	/* Transmit FIFO is empty */
#define XSPI_SR_TX_FULL_MASK	0x08	/* Transmit FIFO is full */
#define XSPI_SR_MODE_FAULT_MASK	0x10	/* Mode fault error */

#define XSPI_TXD_OFFSET		0x68	/* Data Transmit Register */
#define XSPI_RXD_OFFSET		0x6c	/* Data Receive Register */

#define XSPI_SSR_OFFSET		0x70	/* 32-bit Slave Select Register */

/* Register definitions as per "OPB IPIF (v3.01c) Product Specification", DS414
 * IPIF registers are 32 bit
 */
#define XIPIF_V123B_DGIER_OFFSET	0x1c	/* IPIF global int enable reg */
#define XIPIF_V123B_GINTR_ENABLE	0x80000000

#define XIPIF_V123B_IISR_OFFSET		0x20	/* IPIF interrupt status reg */
#define XIPIF_V123B_IIER_OFFSET		0x28	/* IPIF interrupt enable reg */

#define XSPI_INTR_MODE_FAULT		0x01	/* Mode fault error */
#define XSPI_INTR_SLAVE_MODE_FAULT	0x02	/* Selected as slave while
						 * disabled */
#define XSPI_INTR_TX_EMPTY		0x04	/* TxFIFO is empty */
#define XSPI_INTR_TX_UNDERRUN		0x08	/* TxFIFO was underrun */
#define XSPI_INTR_RX_FULL		0x10	/* RxFIFO is full */
#define XSPI_INTR_RX_OVERRUN		0x20	/* RxFIFO was overrun */
#define XSPI_INTR_TX_HALF_EMPTY		0x40	/* TxFIFO is half empty */

#define XIPIF_V123B_RESETR_OFFSET	0x40	/* IPIF reset register */
#define XIPIF_V123B_RESET_MASK		0x0a	/* the value to write */

struct xilinx_spi {
	/* bitbang has to be first */
	struct spi_bitbang bitbang;
	struct completion done;
	struct resource mem; /* phys mem */
	void __iomem	*regs;	/* virt. address of the control registers */

	u32		irq;

	u8 *rx_ptr;		/* pointer in the Tx buffer */
	const u8 *tx_ptr;	/* pointer in the Rx buffer */
	int remaining_bytes;	/* the number of bytes left to transfer */
	u8 bits_per_word;
	unsigned int (*read_fn) (void __iomem *);
	void (*write_fn) (u32, void __iomem *);
	void (*tx_fn) (struct xilinx_spi *);
	void (*rx_fn) (struct xilinx_spi *);
};

static void xspi_tx8(struct xilinx_spi *xspi)
{
	xspi->write_fn(*xspi->tx_ptr, xspi->regs + XSPI_TXD_OFFSET);
	xspi->tx_ptr++;
}

static void xspi_tx16(struct xilinx_spi *xspi)
{
	xspi->write_fn(*(u16 *)(xspi->tx_ptr), xspi->regs + XSPI_TXD_OFFSET);
	xspi->tx_ptr += 2;
}

static void xspi_tx32(struct xilinx_spi *xspi)
{
	xspi->write_fn(*(u32 *)(xspi->tx_ptr), xspi->regs + XSPI_TXD_OFFSET);
	xspi->tx_ptr += 4;
}

static void xspi_rx8(struct xilinx_spi *xspi)
{
	u32 data = xspi->read_fn(xspi->regs + XSPI_RXD_OFFSET);
	if (xspi->rx_ptr) {
		*xspi->rx_ptr = data & 0xff;
		xspi->rx_ptr++;
	}
}

static void xspi_rx16(struct xilinx_spi *xspi)
{
	u32 data = xspi->read_fn(xspi->regs + XSPI_RXD_OFFSET);
	if (xspi->rx_ptr) {
		*(u16 *)(xspi->rx_ptr) = data & 0xffff;
		xspi->rx_ptr += 2;
	}
}

static void xspi_rx32(struct xilinx_spi *xspi)
{
	u32 data = xspi->read_fn(xspi->regs + XSPI_RXD_OFFSET);
	if (xspi->rx_ptr) {
		*(u32 *)(xspi->rx_ptr) = data;
		xspi->rx_ptr += 4;
	}
}

static void xspi_init_hw(struct xilinx_spi *xspi)
{
	void __iomem *regs_base = xspi->regs;

	/* Reset the SPI device */
	xspi->write_fn(XIPIF_V123B_RESET_MASK,
		regs_base + XIPIF_V123B_RESETR_OFFSET);
	/* Disable all the interrupts just in case */
	xspi->write_fn(0, regs_base + XIPIF_V123B_IIER_OFFSET);
	/* Enable the global IPIF interrupt */
	xspi->write_fn(XIPIF_V123B_GINTR_ENABLE,
		regs_base + XIPIF_V123B_DGIER_OFFSET);
	/* Deselect the slave on the SPI bus */
	xspi->write_fn(0xffff, regs_base + XSPI_SSR_OFFSET);
	/* Disable the transmitter, enable Manual Slave Select Assertion,
	 * put SPI controller into master mode, and enable it */
	xspi->write_fn(XSPI_CR_TRANS_INHIBIT | XSPI_CR_MANUAL_SSELECT |
		XSPI_CR_MASTER_MODE | XSPI_CR_ENABLE | XSPI_CR_TXFIFO_RESET |
		XSPI_CR_RXFIFO_RESET, regs_base + XSPI_CR_OFFSET);
}

static void xilinx_spi_chipselect(struct spi_device *spi, int is_on)
{
	struct xilinx_spi *xspi = spi_master_get_devdata(spi->master);

	if (is_on == BITBANG_CS_INACTIVE) {
		/* Deselect the slave on the SPI bus */
		xspi->write_fn(0xffff, xspi->regs + XSPI_SSR_OFFSET);
	} else if (is_on == BITBANG_CS_ACTIVE) {
		/* Set the SPI clock phase and polarity */
		u16 cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET)
			 & ~XSPI_CR_MODE_MASK;
		if (spi->mode & SPI_CPHA)
			cr |= XSPI_CR_CPHA;
		if (spi->mode & SPI_CPOL)
			cr |= XSPI_CR_CPOL;
		xspi->write_fn(cr, xspi->regs + XSPI_CR_OFFSET);

		/* We do not check spi->max_speed_hz here as the SPI clock
		 * frequency is not software programmable (the IP block design
		 * parameter)
		 */

		/* Activate the chip select */
		xspi->write_fn(~(0x0001 << spi->chip_select),
			xspi->regs + XSPI_SSR_OFFSET);
	}
}

/* spi_bitbang requires custom setup_transfer() to be defined if there is a
 * custom txrx_bufs(). We have nothing to setup here as the SPI IP block
 * supports 8 or 16 bits per word which cannot be changed in software.
 * SPI clock can't be changed in software either.
 * Check for correct bits per word. Chip select delay calculations could be
 * added here as soon as bitbang_work() can be made aware of the delay value.
 */
static int xilinx_spi_setup_transfer(struct spi_device *spi,
		struct spi_transfer *t)
{
	struct xilinx_spi *xspi = spi_master_get_devdata(spi->master);
	u8 bits_per_word;

	bits_per_word = (t && t->bits_per_word)
			 ? t->bits_per_word : spi->bits_per_word;
	if (bits_per_word != xspi->bits_per_word) {
		dev_err(&spi->dev, "%s, unsupported bits_per_word=%d\n",
			__func__, bits_per_word);
		return -EINVAL;
	}

	return 0;
}

static int xilinx_spi_setup(struct spi_device *spi)
{
	/* always return 0, we can not check the number of bits.
	 * There are cases when SPI setup is called before any driver is
	 * there, in that case the SPI core defaults to 8 bits, which we
	 * do not support in some cases. But if we return an error, the
	 * SPI device would not be registered and no driver can get hold of it
	 * When the driver is there, it will call SPI setup again with the
	 * correct number of bits per transfer.
	 * If a driver setups with the wrong bit number, it will fail when
	 * it tries to do a transfer
	 */
	return 0;
}

static void xilinx_spi_fill_tx_fifo(struct xilinx_spi *xspi)
{
	u8 sr;

	/* Fill the Tx FIFO with as many bytes as possible */
	sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET);
	while ((sr & XSPI_SR_TX_FULL_MASK) == 0 && xspi->remaining_bytes > 0) {
		if (xspi->tx_ptr)
			xspi->tx_fn(xspi);
		else
			xspi->write_fn(0, xspi->regs + XSPI_TXD_OFFSET);
		xspi->remaining_bytes -= xspi->bits_per_word / 8;
		sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET);
	}
}

static int xilinx_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *t)
{
	struct xilinx_spi *xspi = spi_master_get_devdata(spi->master);
	u32 ipif_ier;
	u16 cr;

	/* We get here with transmitter inhibited */

	xspi->tx_ptr = t->tx_buf;
	xspi->rx_ptr = t->rx_buf;
	xspi->remaining_bytes = t->len;
	INIT_COMPLETION(xspi->done);

	xilinx_spi_fill_tx_fifo(xspi);

	/* Enable the transmit empty interrupt, which we use to determine
	 * progress on the transmission.
	 */
	ipif_ier = xspi->read_fn(xspi->regs + XIPIF_V123B_IIER_OFFSET);
	xspi->write_fn(ipif_ier | XSPI_INTR_TX_EMPTY,
		xspi->regs + XIPIF_V123B_IIER_OFFSET);

	/* Start the transfer by not inhibiting the transmitter any longer */
	cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET) &
		~XSPI_CR_TRANS_INHIBIT;
	xspi->write_fn(cr, xspi->regs + XSPI_CR_OFFSET);

	wait_for_completion(&xspi->done);

	/* Disable the transmit empty interrupt */
	xspi->write_fn(ipif_ier, xspi->regs + XIPIF_V123B_IIER_OFFSET);

	return t->len - xspi->remaining_bytes;
}


/* This driver supports single master mode only. Hence Tx FIFO Empty
 * is the only interrupt we care about.
 * Receive FIFO Overrun, Transmit FIFO Underrun, Mode Fault, and Slave Mode
 * Fault are not to happen.
 */
static irqreturn_t xilinx_spi_irq(int irq, void *dev_id)
{
	struct xilinx_spi *xspi = dev_id;
	u32 ipif_isr;

	/* Get the IPIF interrupts, and clear them immediately */
	ipif_isr = xspi->read_fn(xspi->regs + XIPIF_V123B_IISR_OFFSET);
	xspi->write_fn(ipif_isr, xspi->regs + XIPIF_V123B_IISR_OFFSET);

	if (ipif_isr & XSPI_INTR_TX_EMPTY) {	/* Transmission completed */
		u16 cr;
		u8 sr;

		/* A transmit has just completed. Process received data and
		 * check for more data to transmit. Always inhibit the
		 * transmitter while the Isr refills the transmit register/FIFO,
		 * or make sure it is stopped if we're done.
		 */
		cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET);
		xspi->write_fn(cr | XSPI_CR_TRANS_INHIBIT,
			xspi->regs + XSPI_CR_OFFSET);

		/* Read out all the data from the Rx FIFO */
		sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET);
		while ((sr & XSPI_SR_RX_EMPTY_MASK) == 0) {
			xspi->rx_fn(xspi);
			sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET);
		}

		/* See if there is more data to send */
		if (xspi->remaining_bytes > 0) {
			xilinx_spi_fill_tx_fifo(xspi);
			/* Start the transfer by not inhibiting the
			 * transmitter any longer
			 */
			xspi->write_fn(cr, xspi->regs + XSPI_CR_OFFSET);
		} else {
			/* No more data to send.
			 * Indicate the transfer is completed.
			 */
			complete(&xspi->done);
		}
	}

	return IRQ_HANDLED;
}

struct spi_master *xilinx_spi_init(struct device *dev, struct resource *mem,
	u32 irq, s16 bus_num)
{
	struct spi_master *master;
	struct xilinx_spi *xspi;
	struct xspi_platform_data *pdata = dev->platform_data;
	int ret;

	if (!pdata) {
		dev_err(dev, "No platform data attached\n");
		return NULL;
	}

	master = spi_alloc_master(dev, sizeof(struct xilinx_spi));
	if (!master)
		return NULL;

	/* the spi->mode bits understood by this driver: */
	master->mode_bits = SPI_CPOL | SPI_CPHA;

	xspi = spi_master_get_devdata(master);
	xspi->bitbang.master = spi_master_get(master);
	xspi->bitbang.chipselect = xilinx_spi_chipselect;
	xspi->bitbang.setup_transfer = xilinx_spi_setup_transfer;
	xspi->bitbang.txrx_bufs = xilinx_spi_txrx_bufs;
	xspi->bitbang.master->setup = xilinx_spi_setup;
	init_completion(&xspi->done);

	if (!request_mem_region(mem->start, resource_size(mem),
		XILINX_SPI_NAME))
		goto put_master;

	xspi->regs = ioremap(mem->start, resource_size(mem));
	if (xspi->regs == NULL) {
		dev_warn(dev, "ioremap failure\n");
		goto map_failed;
	}

	master->bus_num = bus_num;
	master->num_chipselect = pdata->num_chipselect;

	xspi->mem = *mem;
	xspi->irq = irq;
	if (pdata->little_endian) {
		xspi->read_fn = ioread32;
		xspi->write_fn = iowrite32;
	} else {
		xspi->read_fn = ioread32be;
		xspi->write_fn = iowrite32be;
	}
	xspi->bits_per_word = pdata->bits_per_word;
	if (xspi->bits_per_word == 8) {
		xspi->tx_fn = xspi_tx8;
		xspi->rx_fn = xspi_rx8;
	} else if (xspi->bits_per_word == 16) {
		xspi->tx_fn = xspi_tx16;
		xspi->rx_fn = xspi_rx16;
	} else if (xspi->bits_per_word == 32) {
		xspi->tx_fn = xspi_tx32;
		xspi->rx_fn = xspi_rx32;
	} else
		goto unmap_io;


	/* SPI controller initializations */
	xspi_init_hw(xspi);

	/* Register for SPI Interrupt */
	ret = request_irq(xspi->irq, xilinx_spi_irq, 0, XILINX_SPI_NAME, xspi);
	if (ret)
		goto unmap_io;

	ret = spi_bitbang_start(&xspi->bitbang);
	if (ret) {
		dev_err(dev, "spi_bitbang_start FAILED\n");
		goto free_irq;
	}

	dev_info(dev, "at 0x%08llX mapped to 0x%p, irq=%d\n",
		(unsigned long long)mem->start, xspi->regs, xspi->irq);
	return master;

free_irq:
	free_irq(xspi->irq, xspi);
unmap_io:
	iounmap(xspi->regs);
map_failed:
	release_mem_region(mem->start, resource_size(mem));
put_master:
	spi_master_put(master);
	return NULL;
}
EXPORT_SYMBOL(xilinx_spi_init);

void xilinx_spi_deinit(struct spi_master *master)
{
	struct xilinx_spi *xspi;

	xspi = spi_master_get_devdata(master);

	spi_bitbang_stop(&xspi->bitbang);
	free_irq(xspi->irq, xspi);
	iounmap(xspi->regs);

	release_mem_region(xspi->mem.start, resource_size(&xspi->mem));
	spi_master_put(xspi->bitbang.master);
}
EXPORT_SYMBOL(xilinx_spi_deinit);

MODULE_AUTHOR("MontaVista Software, Inc. <source@mvista.com>");
MODULE_DESCRIPTION("Xilinx SPI driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
ae918c02 AK	1	/*
	2	* xilinx_spi.c
	3	*
	4	* Xilinx SPI controller driver (master mode only)
	5	*
	6	* Author: MontaVista Software, Inc.
	7	* source@mvista.com
	8	*
	9	* 2002-2007 (c) MontaVista Software, Inc. This file is licensed under the
	10	* terms of the GNU General Public License version 2. This program is licensed
	11	* "as is" without any warranty of any kind, whether express or implied.
	12	*/
	13
	14	#include <linux/module.h>
	15	#include <linux/init.h>
	16	#include <linux/interrupt.h>
ff82c587	17
ae918c02 AK	18	#include <linux/spi/spi.h>
	19	#include <linux/spi/spi_bitbang.h>
	20	#include <linux/io.h>
	21
d5af91a1 RR	22	#include "xilinx_spi.h"
	23	#include <linux/spi/xilinx_spi.h>
	24
fc3ba952	25	#define XILINX_SPI_NAME "xilinx_spi"
ae918c02 AK	26
	27	/* Register definitions as per "OPB Serial Peripheral Interface (SPI) (v1.00e)
	28	* Product Specification", DS464
	29	*/
c9da2e12	30	#define XSPI_CR_OFFSET 0x60 /* Control Register */
ae918c02 AK	31
	32	#define XSPI_CR_ENABLE 0x02
	33	#define XSPI_CR_MASTER_MODE 0x04
	34	#define XSPI_CR_CPOL 0x08
	35	#define XSPI_CR_CPHA 0x10
	36	#define XSPI_CR_MODE_MASK (XSPI_CR_CPHA \| XSPI_CR_CPOL)
	37	#define XSPI_CR_TXFIFO_RESET 0x20
	38	#define XSPI_CR_RXFIFO_RESET 0x40
	39	#define XSPI_CR_MANUAL_SSELECT 0x80
	40	#define XSPI_CR_TRANS_INHIBIT 0x100
c9da2e12	41	#define XSPI_CR_LSB_FIRST 0x200
ae918c02	42
c9da2e12	43	#define XSPI_SR_OFFSET 0x64 /* Status Register */
ae918c02 AK	44
	45	#define XSPI_SR_RX_EMPTY_MASK 0x01 /* Receive FIFO is empty */
	46	#define XSPI_SR_RX_FULL_MASK 0x02 /* Receive FIFO is full */
	47	#define XSPI_SR_TX_EMPTY_MASK 0x04 /* Transmit FIFO is empty */
	48	#define XSPI_SR_TX_FULL_MASK 0x08 /* Transmit FIFO is full */
	49	#define XSPI_SR_MODE_FAULT_MASK 0x10 /* Mode fault error */
	50
c9da2e12 RR	51	#define XSPI_TXD_OFFSET 0x68 /* Data Transmit Register */
c9da2e12 RR	52	#define XSPI_RXD_OFFSET 0x6c /* Data Receive Register */
ae918c02 AK	53
	54	#define XSPI_SSR_OFFSET 0x70 /* 32-bit Slave Select Register */
	55
	56	/* Register definitions as per "OPB IPIF (v3.01c) Product Specification", DS414
	57	* IPIF registers are 32 bit
	58	*/
	59	#define XIPIF_V123B_DGIER_OFFSET 0x1c /* IPIF global int enable reg */
	60	#define XIPIF_V123B_GINTR_ENABLE 0x80000000
	61
	62	#define XIPIF_V123B_IISR_OFFSET 0x20 /* IPIF interrupt status reg */
	63	#define XIPIF_V123B_IIER_OFFSET 0x28 /* IPIF interrupt enable reg */
	64
	65	#define XSPI_INTR_MODE_FAULT 0x01 /* Mode fault error */
	66	#define XSPI_INTR_SLAVE_MODE_FAULT 0x02 /* Selected as slave while
	67	* disabled */
	68	#define XSPI_INTR_TX_EMPTY 0x04 /* TxFIFO is empty */
	69	#define XSPI_INTR_TX_UNDERRUN 0x08 /* TxFIFO was underrun */
	70	#define XSPI_INTR_RX_FULL 0x10 /* RxFIFO is full */
	71	#define XSPI_INTR_RX_OVERRUN 0x20 /* RxFIFO was overrun */
c9da2e12	72	#define XSPI_INTR_TX_HALF_EMPTY 0x40 /* TxFIFO is half empty */
ae918c02 AK	73
	74	#define XIPIF_V123B_RESETR_OFFSET 0x40 /* IPIF reset register */
	75	#define XIPIF_V123B_RESET_MASK 0x0a /* the value to write */
	76
	77	struct xilinx_spi {
	78	/* bitbang has to be first */
	79	struct spi_bitbang bitbang;
	80	struct completion done;
d5af91a1	81	struct resource mem; /* phys mem */
ae918c02 AK	82	void __iomem regs; / virt. address of the control registers */
	83
	84	u32 irq;
	85
ae918c02 AK	86	u8 rx_ptr; / pointer in the Tx buffer */
	87	const u8 tx_ptr; / pointer in the Rx buffer */
	88	int remaining_bytes; /* the number of bytes left to transfer */
c9da2e12	89	u8 bits_per_word;
86fc5935 RR	90	unsigned int (read_fn) (void __iomem );
86fc5935 RR	91	void (write_fn) (u32, void __iomem );
c9da2e12 RR	92	void (tx_fn) (struct xilinx_spi );
c9da2e12 RR	93	void (rx_fn) (struct xilinx_spi );
ae918c02 AK	94	};
ae918c02 AK	95
c9da2e12 RR	96	static void xspi_tx8(struct xilinx_spi *xspi)
	97	{
	98	xspi->write_fn(*xspi->tx_ptr, xspi->regs + XSPI_TXD_OFFSET);
	99	xspi->tx_ptr++;
	100	}
	101
	102	static void xspi_tx16(struct xilinx_spi *xspi)
	103	{
	104	xspi->write_fn((u16 )(xspi->tx_ptr), xspi->regs + XSPI_TXD_OFFSET);
	105	xspi->tx_ptr += 2;
	106	}
	107
	108	static void xspi_tx32(struct xilinx_spi *xspi)
	109	{
	110	xspi->write_fn((u32 )(xspi->tx_ptr), xspi->regs + XSPI_TXD_OFFSET);
	111	xspi->tx_ptr += 4;
	112	}
	113
	114	static void xspi_rx8(struct xilinx_spi *xspi)
	115	{
	116	u32 data = xspi->read_fn(xspi->regs + XSPI_RXD_OFFSET);
	117	if (xspi->rx_ptr) {
	118	*xspi->rx_ptr = data & 0xff;
	119	xspi->rx_ptr++;
	120	}
	121	}
	122
	123	static void xspi_rx16(struct xilinx_spi *xspi)
	124	{
	125	u32 data = xspi->read_fn(xspi->regs + XSPI_RXD_OFFSET);
	126	if (xspi->rx_ptr) {
	127	(u16 )(xspi->rx_ptr) = data & 0xffff;
	128	xspi->rx_ptr += 2;
	129	}
	130	}
	131
	132	static void xspi_rx32(struct xilinx_spi *xspi)
	133	{
	134	u32 data = xspi->read_fn(xspi->regs + XSPI_RXD_OFFSET);
	135	if (xspi->rx_ptr) {
	136	(u32 )(xspi->rx_ptr) = data;
	137	xspi->rx_ptr += 4;
	138	}
	139	}
	140
86fc5935	141	static void xspi_init_hw(struct xilinx_spi *xspi)
ae918c02	142	{
86fc5935 RR	143	void __iomem *regs_base = xspi->regs;
86fc5935 RR	144
ae918c02	145	/* Reset the SPI device */
86fc5935 RR	146	xspi->write_fn(XIPIF_V123B_RESET_MASK,
86fc5935 RR	147	regs_base + XIPIF_V123B_RESETR_OFFSET);
ae918c02	148	/* Disable all the interrupts just in case */
86fc5935	149	xspi->write_fn(0, regs_base + XIPIF_V123B_IIER_OFFSET);
ae918c02	150	/* Enable the global IPIF interrupt */
86fc5935 RR	151	xspi->write_fn(XIPIF_V123B_GINTR_ENABLE,
86fc5935 RR	152	regs_base + XIPIF_V123B_DGIER_OFFSET);
ae918c02	153	/* Deselect the slave on the SPI bus */
86fc5935	154	xspi->write_fn(0xffff, regs_base + XSPI_SSR_OFFSET);
ae918c02 AK	155	/* Disable the transmitter, enable Manual Slave Select Assertion,
ae918c02 AK	156	* put SPI controller into master mode, and enable it */
86fc5935	157	xspi->write_fn(XSPI_CR_TRANS_INHIBIT \| XSPI_CR_MANUAL_SSELECT \|
c9da2e12 RR	158	XSPI_CR_MASTER_MODE \| XSPI_CR_ENABLE \| XSPI_CR_TXFIFO_RESET \|
c9da2e12 RR	159	XSPI_CR_RXFIFO_RESET, regs_base + XSPI_CR_OFFSET);
ae918c02 AK	160	}
	161
	162	static void xilinx_spi_chipselect(struct spi_device *spi, int is_on)
	163	{
	164	struct xilinx_spi *xspi = spi_master_get_devdata(spi->master);
	165
	166	if (is_on == BITBANG_CS_INACTIVE) {
	167	/* Deselect the slave on the SPI bus */
86fc5935	168	xspi->write_fn(0xffff, xspi->regs + XSPI_SSR_OFFSET);
ae918c02 AK	169	} else if (is_on == BITBANG_CS_ACTIVE) {
ae918c02 AK	170	/* Set the SPI clock phase and polarity */
86fc5935	171	u16 cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET)
ae918c02 AK	172	& ~XSPI_CR_MODE_MASK;
	173	if (spi->mode & SPI_CPHA)
	174	cr \|= XSPI_CR_CPHA;
	175	if (spi->mode & SPI_CPOL)
	176	cr \|= XSPI_CR_CPOL;
86fc5935	177	xspi->write_fn(cr, xspi->regs + XSPI_CR_OFFSET);
ae918c02 AK	178
	179	/* We do not check spi->max_speed_hz here as the SPI clock
	180	* frequency is not software programmable (the IP block design
	181	* parameter)
	182	*/
	183
	184	/* Activate the chip select */
86fc5935 RR	185	xspi->write_fn(~(0x0001 << spi->chip_select),
86fc5935 RR	186	xspi->regs + XSPI_SSR_OFFSET);
ae918c02 AK	187	}
	188	}
	189
	190	/* spi_bitbang requires custom setup_transfer() to be defined if there is a
	191	* custom txrx_bufs(). We have nothing to setup here as the SPI IP block
c9da2e12 RR	192	* supports 8 or 16 bits per word which cannot be changed in software.
	193	* SPI clock can't be changed in software either.
	194	* Check for correct bits per word. Chip select delay calculations could be
ae918c02 AK	195	* added here as soon as bitbang_work() can be made aware of the delay value.
	196	*/
	197	static int xilinx_spi_setup_transfer(struct spi_device *spi,
	198	struct spi_transfer *t)
	199	{
c9da2e12	200	struct xilinx_spi *xspi = spi_master_get_devdata(spi->master);
ae918c02	201	u8 bits_per_word;
ae918c02	202
1a8d3b77 JL	203	bits_per_word = (t && t->bits_per_word)
1a8d3b77 JL	204	? t->bits_per_word : spi->bits_per_word;
c9da2e12	205	if (bits_per_word != xspi->bits_per_word) {
ae918c02	206	dev_err(&spi->dev, "%s, unsupported bits_per_word=%d\n",
b687d2a8	207	__func__, bits_per_word);
ae918c02 AK	208	return -EINVAL;
	209	}
	210
ae918c02 AK	211	return 0;
	212	}
	213
ae918c02 AK	214	static int xilinx_spi_setup(struct spi_device *spi)
ae918c02 AK	215	{
c9da2e12 RR	216	/* always return 0, we can not check the number of bits.
	217	* There are cases when SPI setup is called before any driver is
	218	* there, in that case the SPI core defaults to 8 bits, which we
	219	* do not support in some cases. But if we return an error, the
	220	* SPI device would not be registered and no driver can get hold of it
	221	* When the driver is there, it will call SPI setup again with the
	222	* correct number of bits per transfer.
	223	* If a driver setups with the wrong bit number, it will fail when
	224	* it tries to do a transfer
	225	*/
ae918c02 AK	226	return 0;
	227	}
	228
	229	static void xilinx_spi_fill_tx_fifo(struct xilinx_spi *xspi)
	230	{
	231	u8 sr;
	232
	233	/* Fill the Tx FIFO with as many bytes as possible */
86fc5935	234	sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET);
ae918c02	235	while ((sr & XSPI_SR_TX_FULL_MASK) == 0 && xspi->remaining_bytes > 0) {
86fc5935	236	if (xspi->tx_ptr)
c9da2e12	237	xspi->tx_fn(xspi);
86fc5935 RR	238	else
86fc5935 RR	239	xspi->write_fn(0, xspi->regs + XSPI_TXD_OFFSET);
c9da2e12	240	xspi->remaining_bytes -= xspi->bits_per_word / 8;
86fc5935	241	sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET);
ae918c02 AK	242	}
	243	}
	244
	245	static int xilinx_spi_txrx_bufs(struct spi_device spi, struct spi_transfer t)
	246	{
	247	struct xilinx_spi *xspi = spi_master_get_devdata(spi->master);
	248	u32 ipif_ier;
	249	u16 cr;
	250
	251	/* We get here with transmitter inhibited */
	252
	253	xspi->tx_ptr = t->tx_buf;
	254	xspi->rx_ptr = t->rx_buf;
	255	xspi->remaining_bytes = t->len;
	256	INIT_COMPLETION(xspi->done);
	257
	258	xilinx_spi_fill_tx_fifo(xspi);
	259
	260	/* Enable the transmit empty interrupt, which we use to determine
	261	* progress on the transmission.
	262	*/
86fc5935 RR	263	ipif_ier = xspi->read_fn(xspi->regs + XIPIF_V123B_IIER_OFFSET);
	264	xspi->write_fn(ipif_ier \| XSPI_INTR_TX_EMPTY,
	265	xspi->regs + XIPIF_V123B_IIER_OFFSET);
ae918c02 AK	266
ae918c02 AK	267	/* Start the transfer by not inhibiting the transmitter any longer */
86fc5935 RR	268	cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET) &
	269	~XSPI_CR_TRANS_INHIBIT;
	270	xspi->write_fn(cr, xspi->regs + XSPI_CR_OFFSET);
ae918c02 AK	271
	272	wait_for_completion(&xspi->done);
	273
	274	/* Disable the transmit empty interrupt */
86fc5935	275	xspi->write_fn(ipif_ier, xspi->regs + XIPIF_V123B_IIER_OFFSET);
ae918c02 AK	276
	277	return t->len - xspi->remaining_bytes;
	278	}
	279
	280
	281	/* This driver supports single master mode only. Hence Tx FIFO Empty
	282	* is the only interrupt we care about.
	283	* Receive FIFO Overrun, Transmit FIFO Underrun, Mode Fault, and Slave Mode
	284	* Fault are not to happen.
	285	*/
	286	static irqreturn_t xilinx_spi_irq(int irq, void *dev_id)
	287	{
	288	struct xilinx_spi *xspi = dev_id;
	289	u32 ipif_isr;
	290
	291	/* Get the IPIF interrupts, and clear them immediately */
86fc5935 RR	292	ipif_isr = xspi->read_fn(xspi->regs + XIPIF_V123B_IISR_OFFSET);
86fc5935 RR	293	xspi->write_fn(ipif_isr, xspi->regs + XIPIF_V123B_IISR_OFFSET);
ae918c02 AK	294
	295	if (ipif_isr & XSPI_INTR_TX_EMPTY) { /* Transmission completed */
	296	u16 cr;
	297	u8 sr;
	298
	299	/* A transmit has just completed. Process received data and
	300	* check for more data to transmit. Always inhibit the
	301	* transmitter while the Isr refills the transmit register/FIFO,
	302	* or make sure it is stopped if we're done.
	303	*/
86fc5935 RR	304	cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET);
	305	xspi->write_fn(cr \| XSPI_CR_TRANS_INHIBIT,
	306	xspi->regs + XSPI_CR_OFFSET);
ae918c02 AK	307
ae918c02 AK	308	/* Read out all the data from the Rx FIFO */
86fc5935	309	sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET);
ae918c02	310	while ((sr & XSPI_SR_RX_EMPTY_MASK) == 0) {
c9da2e12	311	xspi->rx_fn(xspi);
86fc5935	312	sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET);
ae918c02 AK	313	}
	314
	315	/* See if there is more data to send */
	316	if (xspi->remaining_bytes > 0) {
	317	xilinx_spi_fill_tx_fifo(xspi);
	318	/* Start the transfer by not inhibiting the
	319	* transmitter any longer
	320	*/
86fc5935	321	xspi->write_fn(cr, xspi->regs + XSPI_CR_OFFSET);
ae918c02 AK	322	} else {
	323	/* No more data to send.
	324	* Indicate the transfer is completed.
	325	*/
	326	complete(&xspi->done);
	327	}
	328	}
	329
	330	return IRQ_HANDLED;
	331	}
	332
d5af91a1 RR	333	struct spi_master xilinx_spi_init(struct device dev, struct resource *mem,
d5af91a1 RR	334	u32 irq, s16 bus_num)
ae918c02	335	{
ae918c02 AK	336	struct spi_master *master;
ae918c02 AK	337	struct xilinx_spi *xspi;
d5af91a1 RR	338	struct xspi_platform_data *pdata = dev->platform_data;
d5af91a1 RR	339	int ret;
ae918c02	340
d5af91a1 RR	341	if (!pdata) {
	342	dev_err(dev, "No platform data attached\n");
	343	return NULL;
ae918c02 AK	344	}
ae918c02 AK	345
d5af91a1 RR	346	master = spi_alloc_master(dev, sizeof(struct xilinx_spi));
	347	if (!master)
	348	return NULL;
ae918c02	349
e7db06b5 DB	350	/* the spi->mode bits understood by this driver: */
	351	master->mode_bits = SPI_CPOL \| SPI_CPHA;
	352
ae918c02 AK	353	xspi = spi_master_get_devdata(master);
	354	xspi->bitbang.master = spi_master_get(master);
	355	xspi->bitbang.chipselect = xilinx_spi_chipselect;
	356	xspi->bitbang.setup_transfer = xilinx_spi_setup_transfer;
	357	xspi->bitbang.txrx_bufs = xilinx_spi_txrx_bufs;
	358	xspi->bitbang.master->setup = xilinx_spi_setup;
	359	init_completion(&xspi->done);
	360
d5af91a1 RR	361	if (!request_mem_region(mem->start, resource_size(mem),
d5af91a1 RR	362	XILINX_SPI_NAME))
ae918c02	363	goto put_master;
ae918c02	364
d5af91a1	365	xspi->regs = ioremap(mem->start, resource_size(mem));
ae918c02	366	if (xspi->regs == NULL) {
d5af91a1 RR	367	dev_warn(dev, "ioremap failure\n");
d5af91a1 RR	368	goto map_failed;
ae918c02 AK	369	}
ae918c02 AK	370
d5af91a1 RR	371	master->bus_num = bus_num;
d5af91a1 RR	372	master->num_chipselect = pdata->num_chipselect;
ae918c02	373
d5af91a1 RR	374	xspi->mem = *mem;
d5af91a1 RR	375	xspi->irq = irq;
86fc5935 RR	376	if (pdata->little_endian) {
	377	xspi->read_fn = ioread32;
	378	xspi->write_fn = iowrite32;
	379	} else {
	380	xspi->read_fn = ioread32be;
	381	xspi->write_fn = iowrite32be;
	382	}
c9da2e12 RR	383	xspi->bits_per_word = pdata->bits_per_word;
	384	if (xspi->bits_per_word == 8) {
	385	xspi->tx_fn = xspi_tx8;
	386	xspi->rx_fn = xspi_rx8;
	387	} else if (xspi->bits_per_word == 16) {
	388	xspi->tx_fn = xspi_tx16;
	389	xspi->rx_fn = xspi_rx16;
	390	} else if (xspi->bits_per_word == 32) {
	391	xspi->tx_fn = xspi_tx32;
	392	xspi->rx_fn = xspi_rx32;
	393	} else
	394	goto unmap_io;
	395
ae918c02 AK	396
ae918c02 AK	397	/* SPI controller initializations */
86fc5935	398	xspi_init_hw(xspi);
ae918c02 AK	399
ae918c02 AK	400	/* Register for SPI Interrupt */
d5af91a1 RR	401	ret = request_irq(xspi->irq, xilinx_spi_irq, 0, XILINX_SPI_NAME, xspi);
d5af91a1 RR	402	if (ret)
ae918c02 AK	403	goto unmap_io;
ae918c02 AK	404
d5af91a1 RR	405	ret = spi_bitbang_start(&xspi->bitbang);
	406	if (ret) {
	407	dev_err(dev, "spi_bitbang_start FAILED\n");
ae918c02 AK	408	goto free_irq;
	409	}
	410
920712af GL	411	dev_info(dev, "at 0x%08llX mapped to 0x%p, irq=%d\n",
920712af GL	412	(unsigned long long)mem->start, xspi->regs, xspi->irq);
d5af91a1	413	return master;
ae918c02 AK	414
	415	free_irq:
	416	free_irq(xspi->irq, xspi);
	417	unmap_io:
	418	iounmap(xspi->regs);
d5af91a1 RR	419	map_failed:
d5af91a1 RR	420	release_mem_region(mem->start, resource_size(mem));
ae918c02 AK	421	put_master:
ae918c02 AK	422	spi_master_put(master);
d5af91a1	423	return NULL;
ae918c02	424	}
d5af91a1	425	EXPORT_SYMBOL(xilinx_spi_init);
ae918c02	426
d5af91a1	427	void xilinx_spi_deinit(struct spi_master *master)
ae918c02 AK	428	{
ae918c02 AK	429	struct xilinx_spi *xspi;
ae918c02	430
ae918c02 AK	431	xspi = spi_master_get_devdata(master);
	432
	433	spi_bitbang_stop(&xspi->bitbang);
	434	free_irq(xspi->irq, xspi);
	435	iounmap(xspi->regs);
ff82c587	436
d5af91a1 RR	437	release_mem_region(xspi->mem.start, resource_size(&xspi->mem));
d5af91a1 RR	438	spi_master_put(xspi->bitbang.master);
ae918c02	439	}
d5af91a1	440	EXPORT_SYMBOL(xilinx_spi_deinit);
ae918c02	441
ae918c02 AK	442	MODULE_AUTHOR("MontaVista Software, Inc. <source@mvista.com>");
	443	MODULE_DESCRIPTION("Xilinx SPI driver");
	444	MODULE_LICENSE("GPL");