Commit | Line | Data |
---|---|---|
ccf06998 | 1 | /* |
575c5807 | 2 | * MPC8xxx SPI controller driver. |
ccf06998 KG |
3 | * |
4 | * Maintainer: Kumar Gala | |
5 | * | |
6 | * Copyright (C) 2006 Polycom, Inc. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of the GNU General Public License as published by the | |
10 | * Free Software Foundation; either version 2 of the License, or (at your | |
11 | * option) any later version. | |
12 | */ | |
13 | #include <linux/module.h> | |
14 | #include <linux/init.h> | |
15 | #include <linux/types.h> | |
16 | #include <linux/kernel.h> | |
fd8a11e1 | 17 | #include <linux/bug.h> |
35b4b3c0 AV |
18 | #include <linux/errno.h> |
19 | #include <linux/err.h> | |
9effb959 | 20 | #include <linux/io.h> |
ccf06998 KG |
21 | #include <linux/completion.h> |
22 | #include <linux/interrupt.h> | |
23 | #include <linux/delay.h> | |
24 | #include <linux/irq.h> | |
25 | #include <linux/device.h> | |
26 | #include <linux/spi/spi.h> | |
27 | #include <linux/spi/spi_bitbang.h> | |
28 | #include <linux/platform_device.h> | |
29 | #include <linux/fsl_devices.h> | |
35b4b3c0 AV |
30 | #include <linux/of.h> |
31 | #include <linux/of_platform.h> | |
32 | #include <linux/gpio.h> | |
33 | #include <linux/of_gpio.h> | |
34 | #include <linux/of_spi.h> | |
ccf06998 | 35 | |
35b4b3c0 | 36 | #include <sysdev/fsl_soc.h> |
ccf06998 | 37 | #include <asm/irq.h> |
ccf06998 KG |
38 | |
39 | /* SPI Controller registers */ | |
575c5807 | 40 | struct mpc8xxx_spi_reg { |
ccf06998 KG |
41 | u8 res1[0x20]; |
42 | __be32 mode; | |
43 | __be32 event; | |
44 | __be32 mask; | |
45 | __be32 command; | |
46 | __be32 transmit; | |
47 | __be32 receive; | |
48 | }; | |
49 | ||
50 | /* SPI Controller mode register definitions */ | |
2a485d7a | 51 | #define SPMODE_LOOP (1 << 30) |
ccf06998 KG |
52 | #define SPMODE_CI_INACTIVEHIGH (1 << 29) |
53 | #define SPMODE_CP_BEGIN_EDGECLK (1 << 28) | |
54 | #define SPMODE_DIV16 (1 << 27) | |
55 | #define SPMODE_REV (1 << 26) | |
56 | #define SPMODE_MS (1 << 25) | |
57 | #define SPMODE_ENABLE (1 << 24) | |
58 | #define SPMODE_LEN(x) ((x) << 20) | |
59 | #define SPMODE_PM(x) ((x) << 16) | |
f29ba280 | 60 | #define SPMODE_OP (1 << 14) |
c9bfcb31 | 61 | #define SPMODE_CG(x) ((x) << 7) |
ccf06998 KG |
62 | |
63 | /* | |
64 | * Default for SPI Mode: | |
65 | * SPI MODE 0 (inactive low, phase middle, MSB, 8-bit length, slow clk | |
66 | */ | |
67 | #define SPMODE_INIT_VAL (SPMODE_CI_INACTIVEHIGH | SPMODE_DIV16 | SPMODE_REV | \ | |
68 | SPMODE_MS | SPMODE_LEN(7) | SPMODE_PM(0xf)) | |
69 | ||
70 | /* SPIE register values */ | |
71 | #define SPIE_NE 0x00000200 /* Not empty */ | |
72 | #define SPIE_NF 0x00000100 /* Not full */ | |
73 | ||
74 | /* SPIM register values */ | |
75 | #define SPIM_NE 0x00000200 /* Not empty */ | |
76 | #define SPIM_NF 0x00000100 /* Not full */ | |
77 | ||
78 | /* SPI Controller driver's private data. */ | |
575c5807 AV |
79 | struct mpc8xxx_spi { |
80 | struct mpc8xxx_spi_reg __iomem *base; | |
ccf06998 KG |
81 | |
82 | /* rx & tx bufs from the spi_transfer */ | |
83 | const void *tx; | |
84 | void *rx; | |
85 | ||
86 | /* functions to deal with different sized buffers */ | |
575c5807 AV |
87 | void (*get_rx) (u32 rx_data, struct mpc8xxx_spi *); |
88 | u32(*get_tx) (struct mpc8xxx_spi *); | |
ccf06998 KG |
89 | |
90 | unsigned int count; | |
35b4b3c0 | 91 | unsigned int irq; |
ccf06998 KG |
92 | |
93 | unsigned nsecs; /* (clock cycle time)/2 */ | |
94 | ||
e24a4d1e | 95 | u32 spibrg; /* SPIBRG input clock */ |
f29ba280 JT |
96 | u32 rx_shift; /* RX data reg shift when in qe mode */ |
97 | u32 tx_shift; /* TX data reg shift when in qe mode */ | |
98 | ||
99 | bool qe_mode; | |
100 | ||
c9bfcb31 JT |
101 | struct workqueue_struct *workqueue; |
102 | struct work_struct work; | |
103 | ||
104 | struct list_head queue; | |
105 | spinlock_t lock; | |
106 | ||
107 | struct completion done; | |
108 | }; | |
109 | ||
575c5807 | 110 | struct spi_mpc8xxx_cs { |
c9bfcb31 | 111 | /* functions to deal with different sized buffers */ |
575c5807 AV |
112 | void (*get_rx) (u32 rx_data, struct mpc8xxx_spi *); |
113 | u32 (*get_tx) (struct mpc8xxx_spi *); | |
c9bfcb31 JT |
114 | u32 rx_shift; /* RX data reg shift when in qe mode */ |
115 | u32 tx_shift; /* TX data reg shift when in qe mode */ | |
116 | u32 hw_mode; /* Holds HW mode register settings */ | |
ccf06998 KG |
117 | }; |
118 | ||
575c5807 | 119 | static inline void mpc8xxx_spi_write_reg(__be32 __iomem *reg, u32 val) |
ccf06998 KG |
120 | { |
121 | out_be32(reg, val); | |
122 | } | |
123 | ||
575c5807 | 124 | static inline u32 mpc8xxx_spi_read_reg(__be32 __iomem *reg) |
ccf06998 KG |
125 | { |
126 | return in_be32(reg); | |
127 | } | |
128 | ||
129 | #define MPC83XX_SPI_RX_BUF(type) \ | |
34c8a20c | 130 | static \ |
575c5807 | 131 | void mpc8xxx_spi_rx_buf_##type(u32 data, struct mpc8xxx_spi *mpc8xxx_spi) \ |
ccf06998 | 132 | { \ |
575c5807 AV |
133 | type *rx = mpc8xxx_spi->rx; \ |
134 | *rx++ = (type)(data >> mpc8xxx_spi->rx_shift); \ | |
135 | mpc8xxx_spi->rx = rx; \ | |
ccf06998 KG |
136 | } |
137 | ||
138 | #define MPC83XX_SPI_TX_BUF(type) \ | |
34c8a20c | 139 | static \ |
575c5807 | 140 | u32 mpc8xxx_spi_tx_buf_##type(struct mpc8xxx_spi *mpc8xxx_spi) \ |
ccf06998 KG |
141 | { \ |
142 | u32 data; \ | |
575c5807 | 143 | const type *tx = mpc8xxx_spi->tx; \ |
4b1badf5 DB |
144 | if (!tx) \ |
145 | return 0; \ | |
575c5807 AV |
146 | data = *tx++ << mpc8xxx_spi->tx_shift; \ |
147 | mpc8xxx_spi->tx = tx; \ | |
ccf06998 KG |
148 | return data; \ |
149 | } | |
150 | ||
151 | MPC83XX_SPI_RX_BUF(u8) | |
152 | MPC83XX_SPI_RX_BUF(u16) | |
153 | MPC83XX_SPI_RX_BUF(u32) | |
154 | MPC83XX_SPI_TX_BUF(u8) | |
155 | MPC83XX_SPI_TX_BUF(u16) | |
156 | MPC83XX_SPI_TX_BUF(u32) | |
157 | ||
a35c1710 AV |
158 | static void mpc8xxx_spi_change_mode(struct spi_device *spi) |
159 | { | |
160 | struct mpc8xxx_spi *mspi = spi_master_get_devdata(spi->master); | |
161 | struct spi_mpc8xxx_cs *cs = spi->controller_state; | |
162 | __be32 __iomem *mode = &mspi->base->mode; | |
163 | unsigned long flags; | |
164 | ||
165 | if (cs->hw_mode == mpc8xxx_spi_read_reg(mode)) | |
166 | return; | |
167 | ||
168 | /* Turn off IRQs locally to minimize time that SPI is disabled. */ | |
169 | local_irq_save(flags); | |
170 | ||
171 | /* Turn off SPI unit prior changing mode */ | |
172 | mpc8xxx_spi_write_reg(mode, cs->hw_mode & ~SPMODE_ENABLE); | |
173 | mpc8xxx_spi_write_reg(mode, cs->hw_mode); | |
174 | ||
175 | local_irq_restore(flags); | |
176 | } | |
177 | ||
575c5807 | 178 | static void mpc8xxx_spi_chipselect(struct spi_device *spi, int value) |
ccf06998 | 179 | { |
575c5807 | 180 | struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master); |
364fdbc0 AV |
181 | struct fsl_spi_platform_data *pdata = spi->dev.parent->platform_data; |
182 | bool pol = spi->mode & SPI_CS_HIGH; | |
575c5807 | 183 | struct spi_mpc8xxx_cs *cs = spi->controller_state; |
ccf06998 | 184 | |
ccf06998 | 185 | if (value == BITBANG_CS_INACTIVE) { |
364fdbc0 AV |
186 | if (pdata->cs_control) |
187 | pdata->cs_control(spi, !pol); | |
ccf06998 KG |
188 | } |
189 | ||
190 | if (value == BITBANG_CS_ACTIVE) { | |
575c5807 AV |
191 | mpc8xxx_spi->rx_shift = cs->rx_shift; |
192 | mpc8xxx_spi->tx_shift = cs->tx_shift; | |
193 | mpc8xxx_spi->get_rx = cs->get_rx; | |
194 | mpc8xxx_spi->get_tx = cs->get_tx; | |
c9bfcb31 | 195 | |
a35c1710 AV |
196 | mpc8xxx_spi_change_mode(spi); |
197 | ||
364fdbc0 AV |
198 | if (pdata->cs_control) |
199 | pdata->cs_control(spi, pol); | |
ccf06998 KG |
200 | } |
201 | } | |
202 | ||
203 | static | |
575c5807 | 204 | int mpc8xxx_spi_setup_transfer(struct spi_device *spi, struct spi_transfer *t) |
ccf06998 | 205 | { |
575c5807 | 206 | struct mpc8xxx_spi *mpc8xxx_spi; |
c9bfcb31 | 207 | u8 bits_per_word, pm; |
ccf06998 | 208 | u32 hz; |
575c5807 | 209 | struct spi_mpc8xxx_cs *cs = spi->controller_state; |
ccf06998 | 210 | |
575c5807 | 211 | mpc8xxx_spi = spi_master_get_devdata(spi->master); |
ccf06998 KG |
212 | |
213 | if (t) { | |
214 | bits_per_word = t->bits_per_word; | |
215 | hz = t->speed_hz; | |
216 | } else { | |
217 | bits_per_word = 0; | |
218 | hz = 0; | |
219 | } | |
220 | ||
221 | /* spi_transfer level calls that work per-word */ | |
222 | if (!bits_per_word) | |
223 | bits_per_word = spi->bits_per_word; | |
224 | ||
225 | /* Make sure its a bit width we support [4..16, 32] */ | |
226 | if ((bits_per_word < 4) | |
227 | || ((bits_per_word > 16) && (bits_per_word != 32))) | |
228 | return -EINVAL; | |
229 | ||
c9bfcb31 JT |
230 | if (!hz) |
231 | hz = spi->max_speed_hz; | |
232 | ||
233 | cs->rx_shift = 0; | |
234 | cs->tx_shift = 0; | |
ccf06998 | 235 | if (bits_per_word <= 8) { |
575c5807 AV |
236 | cs->get_rx = mpc8xxx_spi_rx_buf_u8; |
237 | cs->get_tx = mpc8xxx_spi_tx_buf_u8; | |
238 | if (mpc8xxx_spi->qe_mode) { | |
c9bfcb31 JT |
239 | cs->rx_shift = 16; |
240 | cs->tx_shift = 24; | |
f29ba280 | 241 | } |
ccf06998 | 242 | } else if (bits_per_word <= 16) { |
575c5807 AV |
243 | cs->get_rx = mpc8xxx_spi_rx_buf_u16; |
244 | cs->get_tx = mpc8xxx_spi_tx_buf_u16; | |
245 | if (mpc8xxx_spi->qe_mode) { | |
c9bfcb31 JT |
246 | cs->rx_shift = 16; |
247 | cs->tx_shift = 16; | |
f29ba280 | 248 | } |
ccf06998 | 249 | } else if (bits_per_word <= 32) { |
575c5807 AV |
250 | cs->get_rx = mpc8xxx_spi_rx_buf_u32; |
251 | cs->get_tx = mpc8xxx_spi_tx_buf_u32; | |
ccf06998 KG |
252 | } else |
253 | return -EINVAL; | |
254 | ||
575c5807 | 255 | if (mpc8xxx_spi->qe_mode && spi->mode & SPI_LSB_FIRST) { |
c9bfcb31 | 256 | cs->tx_shift = 0; |
35cc0b97 | 257 | if (bits_per_word <= 8) |
c9bfcb31 | 258 | cs->rx_shift = 8; |
35cc0b97 | 259 | else |
c9bfcb31 | 260 | cs->rx_shift = 0; |
35cc0b97 AV |
261 | } |
262 | ||
575c5807 AV |
263 | mpc8xxx_spi->rx_shift = cs->rx_shift; |
264 | mpc8xxx_spi->tx_shift = cs->tx_shift; | |
265 | mpc8xxx_spi->get_rx = cs->get_rx; | |
266 | mpc8xxx_spi->get_tx = cs->get_tx; | |
ccf06998 KG |
267 | |
268 | if (bits_per_word == 32) | |
269 | bits_per_word = 0; | |
270 | else | |
271 | bits_per_word = bits_per_word - 1; | |
272 | ||
32421daa | 273 | /* mask out bits we are going to set */ |
c9bfcb31 JT |
274 | cs->hw_mode &= ~(SPMODE_LEN(0xF) | SPMODE_DIV16 |
275 | | SPMODE_PM(0xF)); | |
276 | ||
277 | cs->hw_mode |= SPMODE_LEN(bits_per_word); | |
278 | ||
575c5807 | 279 | if ((mpc8xxx_spi->spibrg / hz) > 64) { |
53604dbe | 280 | cs->hw_mode |= SPMODE_DIV16; |
575c5807 | 281 | pm = mpc8xxx_spi->spibrg / (hz * 64); |
fd8a11e1 AV |
282 | |
283 | WARN_ONCE(pm > 16, "%s: Requested speed is too low: %d Hz. " | |
284 | "Will use %d Hz instead.\n", dev_name(&spi->dev), | |
575c5807 | 285 | hz, mpc8xxx_spi->spibrg / 1024); |
fd8a11e1 | 286 | if (pm > 16) |
53604dbe | 287 | pm = 16; |
a61f5345 | 288 | } else |
575c5807 | 289 | pm = mpc8xxx_spi->spibrg / (hz * 4); |
a61f5345 CG |
290 | if (pm) |
291 | pm--; | |
292 | ||
293 | cs->hw_mode |= SPMODE_PM(pm); | |
a35c1710 AV |
294 | |
295 | mpc8xxx_spi_change_mode(spi); | |
c9bfcb31 JT |
296 | return 0; |
297 | } | |
ccf06998 | 298 | |
575c5807 | 299 | static int mpc8xxx_spi_bufs(struct spi_device *spi, struct spi_transfer *t) |
c9bfcb31 | 300 | { |
575c5807 | 301 | struct mpc8xxx_spi *mpc8xxx_spi; |
c9bfcb31 | 302 | u32 word, len, bits_per_word; |
ccf06998 | 303 | |
575c5807 | 304 | mpc8xxx_spi = spi_master_get_devdata(spi->master); |
c9bfcb31 | 305 | |
575c5807 AV |
306 | mpc8xxx_spi->tx = t->tx_buf; |
307 | mpc8xxx_spi->rx = t->rx_buf; | |
c9bfcb31 JT |
308 | bits_per_word = spi->bits_per_word; |
309 | if (t->bits_per_word) | |
310 | bits_per_word = t->bits_per_word; | |
311 | len = t->len; | |
aa77d96b PK |
312 | if (bits_per_word > 8) { |
313 | /* invalid length? */ | |
314 | if (len & 1) | |
315 | return -EINVAL; | |
c9bfcb31 | 316 | len /= 2; |
aa77d96b PK |
317 | } |
318 | if (bits_per_word > 16) { | |
319 | /* invalid length? */ | |
320 | if (len & 1) | |
321 | return -EINVAL; | |
c9bfcb31 | 322 | len /= 2; |
aa77d96b | 323 | } |
575c5807 | 324 | mpc8xxx_spi->count = len; |
aa77d96b | 325 | |
575c5807 | 326 | INIT_COMPLETION(mpc8xxx_spi->done); |
c9bfcb31 JT |
327 | |
328 | /* enable rx ints */ | |
575c5807 | 329 | mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->mask, SPIM_NE); |
c9bfcb31 JT |
330 | |
331 | /* transmit word */ | |
575c5807 AV |
332 | word = mpc8xxx_spi->get_tx(mpc8xxx_spi); |
333 | mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->transmit, word); | |
c9bfcb31 | 334 | |
575c5807 | 335 | wait_for_completion(&mpc8xxx_spi->done); |
c9bfcb31 JT |
336 | |
337 | /* disable rx ints */ | |
575c5807 | 338 | mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->mask, 0); |
c9bfcb31 | 339 | |
575c5807 | 340 | return mpc8xxx_spi->count; |
c9bfcb31 JT |
341 | } |
342 | ||
575c5807 | 343 | static void mpc8xxx_spi_do_one_msg(struct spi_message *m) |
c9bfcb31 | 344 | { |
b9b9af11 AV |
345 | struct spi_device *spi = m->spi; |
346 | struct spi_transfer *t; | |
347 | unsigned int cs_change; | |
348 | const int nsecs = 50; | |
349 | int status; | |
350 | ||
351 | cs_change = 1; | |
352 | status = 0; | |
353 | list_for_each_entry(t, &m->transfers, transfer_list) { | |
354 | if (t->bits_per_word || t->speed_hz) { | |
355 | /* Don't allow changes if CS is active */ | |
356 | status = -EINVAL; | |
357 | ||
358 | if (cs_change) | |
575c5807 | 359 | status = mpc8xxx_spi_setup_transfer(spi, t); |
b9b9af11 | 360 | if (status < 0) |
c9bfcb31 | 361 | break; |
b9b9af11 | 362 | } |
c9bfcb31 | 363 | |
b9b9af11 | 364 | if (cs_change) { |
575c5807 | 365 | mpc8xxx_spi_chipselect(spi, BITBANG_CS_ACTIVE); |
b9b9af11 AV |
366 | ndelay(nsecs); |
367 | } | |
368 | cs_change = t->cs_change; | |
369 | if (t->len) | |
575c5807 | 370 | status = mpc8xxx_spi_bufs(spi, t); |
b9b9af11 AV |
371 | if (status) { |
372 | status = -EMSGSIZE; | |
373 | break; | |
c9bfcb31 | 374 | } |
b9b9af11 | 375 | m->actual_length += t->len; |
c9bfcb31 | 376 | |
b9b9af11 AV |
377 | if (t->delay_usecs) |
378 | udelay(t->delay_usecs); | |
c9bfcb31 | 379 | |
b9b9af11 | 380 | if (cs_change) { |
c9bfcb31 | 381 | ndelay(nsecs); |
575c5807 | 382 | mpc8xxx_spi_chipselect(spi, BITBANG_CS_INACTIVE); |
b9b9af11 | 383 | ndelay(nsecs); |
c9bfcb31 | 384 | } |
b9b9af11 AV |
385 | } |
386 | ||
387 | m->status = status; | |
388 | m->complete(m->context); | |
389 | ||
390 | if (status || !cs_change) { | |
391 | ndelay(nsecs); | |
575c5807 | 392 | mpc8xxx_spi_chipselect(spi, BITBANG_CS_INACTIVE); |
b9b9af11 AV |
393 | } |
394 | ||
575c5807 | 395 | mpc8xxx_spi_setup_transfer(spi, NULL); |
b9b9af11 AV |
396 | } |
397 | ||
575c5807 | 398 | static void mpc8xxx_spi_work(struct work_struct *work) |
b9b9af11 | 399 | { |
575c5807 | 400 | struct mpc8xxx_spi *mpc8xxx_spi = container_of(work, struct mpc8xxx_spi, |
b9b9af11 AV |
401 | work); |
402 | ||
575c5807 AV |
403 | spin_lock_irq(&mpc8xxx_spi->lock); |
404 | while (!list_empty(&mpc8xxx_spi->queue)) { | |
405 | struct spi_message *m = container_of(mpc8xxx_spi->queue.next, | |
b9b9af11 AV |
406 | struct spi_message, queue); |
407 | ||
408 | list_del_init(&m->queue); | |
575c5807 | 409 | spin_unlock_irq(&mpc8xxx_spi->lock); |
c9bfcb31 | 410 | |
575c5807 | 411 | mpc8xxx_spi_do_one_msg(m); |
c9bfcb31 | 412 | |
575c5807 | 413 | spin_lock_irq(&mpc8xxx_spi->lock); |
c9bfcb31 | 414 | } |
575c5807 | 415 | spin_unlock_irq(&mpc8xxx_spi->lock); |
ccf06998 KG |
416 | } |
417 | ||
575c5807 | 418 | static int mpc8xxx_spi_setup(struct spi_device *spi) |
ccf06998 | 419 | { |
575c5807 | 420 | struct mpc8xxx_spi *mpc8xxx_spi; |
ccf06998 | 421 | int retval; |
c9bfcb31 | 422 | u32 hw_mode; |
575c5807 | 423 | struct spi_mpc8xxx_cs *cs = spi->controller_state; |
ccf06998 KG |
424 | |
425 | if (!spi->max_speed_hz) | |
426 | return -EINVAL; | |
427 | ||
c9bfcb31 JT |
428 | if (!cs) { |
429 | cs = kzalloc(sizeof *cs, GFP_KERNEL); | |
430 | if (!cs) | |
431 | return -ENOMEM; | |
432 | spi->controller_state = cs; | |
433 | } | |
575c5807 | 434 | mpc8xxx_spi = spi_master_get_devdata(spi->master); |
ccf06998 | 435 | |
c9bfcb31 | 436 | hw_mode = cs->hw_mode; /* Save orginal settings */ |
575c5807 | 437 | cs->hw_mode = mpc8xxx_spi_read_reg(&mpc8xxx_spi->base->mode); |
c9bfcb31 JT |
438 | /* mask out bits we are going to set */ |
439 | cs->hw_mode &= ~(SPMODE_CP_BEGIN_EDGECLK | SPMODE_CI_INACTIVEHIGH | |
440 | | SPMODE_REV | SPMODE_LOOP); | |
441 | ||
442 | if (spi->mode & SPI_CPHA) | |
443 | cs->hw_mode |= SPMODE_CP_BEGIN_EDGECLK; | |
444 | if (spi->mode & SPI_CPOL) | |
445 | cs->hw_mode |= SPMODE_CI_INACTIVEHIGH; | |
446 | if (!(spi->mode & SPI_LSB_FIRST)) | |
447 | cs->hw_mode |= SPMODE_REV; | |
448 | if (spi->mode & SPI_LOOP) | |
449 | cs->hw_mode |= SPMODE_LOOP; | |
450 | ||
575c5807 | 451 | retval = mpc8xxx_spi_setup_transfer(spi, NULL); |
c9bfcb31 JT |
452 | if (retval < 0) { |
453 | cs->hw_mode = hw_mode; /* Restore settings */ | |
ccf06998 | 454 | return retval; |
c9bfcb31 | 455 | } |
ccf06998 KG |
456 | return 0; |
457 | } | |
458 | ||
575c5807 | 459 | static irqreturn_t mpc8xxx_spi_irq(s32 irq, void *context_data) |
ccf06998 | 460 | { |
575c5807 | 461 | struct mpc8xxx_spi *mpc8xxx_spi = context_data; |
ccf06998 KG |
462 | u32 event; |
463 | irqreturn_t ret = IRQ_NONE; | |
464 | ||
465 | /* Get interrupt events(tx/rx) */ | |
575c5807 | 466 | event = mpc8xxx_spi_read_reg(&mpc8xxx_spi->base->event); |
ccf06998 KG |
467 | |
468 | /* We need handle RX first */ | |
469 | if (event & SPIE_NE) { | |
575c5807 | 470 | u32 rx_data = mpc8xxx_spi_read_reg(&mpc8xxx_spi->base->receive); |
ccf06998 | 471 | |
575c5807 AV |
472 | if (mpc8xxx_spi->rx) |
473 | mpc8xxx_spi->get_rx(rx_data, mpc8xxx_spi); | |
ccf06998 KG |
474 | |
475 | ret = IRQ_HANDLED; | |
476 | } | |
477 | ||
478 | if ((event & SPIE_NF) == 0) | |
479 | /* spin until TX is done */ | |
480 | while (((event = | |
575c5807 | 481 | mpc8xxx_spi_read_reg(&mpc8xxx_spi->base->event)) & |
ccf06998 | 482 | SPIE_NF) == 0) |
9effb959 | 483 | cpu_relax(); |
ccf06998 | 484 | |
575c5807 AV |
485 | mpc8xxx_spi->count -= 1; |
486 | if (mpc8xxx_spi->count) { | |
487 | u32 word = mpc8xxx_spi->get_tx(mpc8xxx_spi); | |
488 | mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->transmit, word); | |
ccf06998 | 489 | } else { |
575c5807 | 490 | complete(&mpc8xxx_spi->done); |
ccf06998 KG |
491 | } |
492 | ||
493 | /* Clear the events */ | |
575c5807 | 494 | mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->event, event); |
ccf06998 KG |
495 | |
496 | return ret; | |
497 | } | |
575c5807 | 498 | static int mpc8xxx_spi_transfer(struct spi_device *spi, |
c9bfcb31 JT |
499 | struct spi_message *m) |
500 | { | |
575c5807 | 501 | struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master); |
c9bfcb31 JT |
502 | unsigned long flags; |
503 | ||
504 | m->actual_length = 0; | |
505 | m->status = -EINPROGRESS; | |
506 | ||
575c5807 AV |
507 | spin_lock_irqsave(&mpc8xxx_spi->lock, flags); |
508 | list_add_tail(&m->queue, &mpc8xxx_spi->queue); | |
509 | queue_work(mpc8xxx_spi->workqueue, &mpc8xxx_spi->work); | |
510 | spin_unlock_irqrestore(&mpc8xxx_spi->lock, flags); | |
c9bfcb31 JT |
511 | |
512 | return 0; | |
513 | } | |
514 | ||
515 | ||
575c5807 | 516 | static void mpc8xxx_spi_cleanup(struct spi_device *spi) |
c9bfcb31 JT |
517 | { |
518 | kfree(spi->controller_state); | |
519 | } | |
ccf06998 | 520 | |
35b4b3c0 | 521 | static struct spi_master * __devinit |
575c5807 | 522 | mpc8xxx_spi_probe(struct device *dev, struct resource *mem, unsigned int irq) |
ccf06998 | 523 | { |
35b4b3c0 | 524 | struct fsl_spi_platform_data *pdata = dev->platform_data; |
ccf06998 | 525 | struct spi_master *master; |
575c5807 | 526 | struct mpc8xxx_spi *mpc8xxx_spi; |
ccf06998 KG |
527 | u32 regval; |
528 | int ret = 0; | |
529 | ||
575c5807 | 530 | master = spi_alloc_master(dev, sizeof(struct mpc8xxx_spi)); |
ccf06998 KG |
531 | if (master == NULL) { |
532 | ret = -ENOMEM; | |
533 | goto err; | |
534 | } | |
535 | ||
35b4b3c0 | 536 | dev_set_drvdata(dev, master); |
ccf06998 | 537 | |
e7db06b5 DB |
538 | /* the spi->mode bits understood by this driver: */ |
539 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | |
540 | | SPI_LSB_FIRST | SPI_LOOP; | |
541 | ||
575c5807 AV |
542 | master->setup = mpc8xxx_spi_setup; |
543 | master->transfer = mpc8xxx_spi_transfer; | |
544 | master->cleanup = mpc8xxx_spi_cleanup; | |
545 | ||
546 | mpc8xxx_spi = spi_master_get_devdata(master); | |
547 | mpc8xxx_spi->qe_mode = pdata->qe_mode; | |
548 | mpc8xxx_spi->get_rx = mpc8xxx_spi_rx_buf_u8; | |
549 | mpc8xxx_spi->get_tx = mpc8xxx_spi_tx_buf_u8; | |
550 | mpc8xxx_spi->spibrg = pdata->sysclk; | |
551 | ||
552 | mpc8xxx_spi->rx_shift = 0; | |
553 | mpc8xxx_spi->tx_shift = 0; | |
554 | if (mpc8xxx_spi->qe_mode) { | |
555 | mpc8xxx_spi->rx_shift = 16; | |
556 | mpc8xxx_spi->tx_shift = 24; | |
f29ba280 JT |
557 | } |
558 | ||
575c5807 | 559 | init_completion(&mpc8xxx_spi->done); |
ccf06998 | 560 | |
575c5807 AV |
561 | mpc8xxx_spi->base = ioremap(mem->start, mem->end - mem->start + 1); |
562 | if (mpc8xxx_spi->base == NULL) { | |
ccf06998 KG |
563 | ret = -ENOMEM; |
564 | goto put_master; | |
565 | } | |
566 | ||
575c5807 | 567 | mpc8xxx_spi->irq = irq; |
ccf06998 KG |
568 | |
569 | /* Register for SPI Interrupt */ | |
575c5807 AV |
570 | ret = request_irq(mpc8xxx_spi->irq, mpc8xxx_spi_irq, |
571 | 0, "mpc8xxx_spi", mpc8xxx_spi); | |
ccf06998 KG |
572 | |
573 | if (ret != 0) | |
574 | goto unmap_io; | |
575 | ||
576 | master->bus_num = pdata->bus_num; | |
577 | master->num_chipselect = pdata->max_chipselect; | |
578 | ||
579 | /* SPI controller initializations */ | |
575c5807 AV |
580 | mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->mode, 0); |
581 | mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->mask, 0); | |
582 | mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->command, 0); | |
583 | mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->event, 0xffffffff); | |
ccf06998 KG |
584 | |
585 | /* Enable SPI interface */ | |
586 | regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE; | |
f29ba280 JT |
587 | if (pdata->qe_mode) |
588 | regval |= SPMODE_OP; | |
589 | ||
575c5807 AV |
590 | mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->mode, regval); |
591 | spin_lock_init(&mpc8xxx_spi->lock); | |
592 | init_completion(&mpc8xxx_spi->done); | |
593 | INIT_WORK(&mpc8xxx_spi->work, mpc8xxx_spi_work); | |
594 | INIT_LIST_HEAD(&mpc8xxx_spi->queue); | |
ccf06998 | 595 | |
575c5807 | 596 | mpc8xxx_spi->workqueue = create_singlethread_workqueue( |
6c7377ab | 597 | dev_name(master->dev.parent)); |
575c5807 | 598 | if (mpc8xxx_spi->workqueue == NULL) { |
c9bfcb31 | 599 | ret = -EBUSY; |
ccf06998 | 600 | goto free_irq; |
c9bfcb31 JT |
601 | } |
602 | ||
603 | ret = spi_register_master(master); | |
604 | if (ret < 0) | |
605 | goto unreg_master; | |
ccf06998 KG |
606 | |
607 | printk(KERN_INFO | |
575c5807 AV |
608 | "%s: MPC8xxx SPI Controller driver at 0x%p (irq = %d)\n", |
609 | dev_name(dev), mpc8xxx_spi->base, mpc8xxx_spi->irq); | |
ccf06998 | 610 | |
35b4b3c0 | 611 | return master; |
ccf06998 | 612 | |
c9bfcb31 | 613 | unreg_master: |
575c5807 | 614 | destroy_workqueue(mpc8xxx_spi->workqueue); |
ccf06998 | 615 | free_irq: |
575c5807 | 616 | free_irq(mpc8xxx_spi->irq, mpc8xxx_spi); |
ccf06998 | 617 | unmap_io: |
575c5807 | 618 | iounmap(mpc8xxx_spi->base); |
ccf06998 KG |
619 | put_master: |
620 | spi_master_put(master); | |
ccf06998 | 621 | err: |
35b4b3c0 | 622 | return ERR_PTR(ret); |
ccf06998 KG |
623 | } |
624 | ||
575c5807 | 625 | static int __devexit mpc8xxx_spi_remove(struct device *dev) |
ccf06998 | 626 | { |
575c5807 | 627 | struct mpc8xxx_spi *mpc8xxx_spi; |
ccf06998 KG |
628 | struct spi_master *master; |
629 | ||
35b4b3c0 | 630 | master = dev_get_drvdata(dev); |
575c5807 | 631 | mpc8xxx_spi = spi_master_get_devdata(master); |
ccf06998 | 632 | |
575c5807 AV |
633 | flush_workqueue(mpc8xxx_spi->workqueue); |
634 | destroy_workqueue(mpc8xxx_spi->workqueue); | |
c9bfcb31 JT |
635 | spi_unregister_master(master); |
636 | ||
575c5807 AV |
637 | free_irq(mpc8xxx_spi->irq, mpc8xxx_spi); |
638 | iounmap(mpc8xxx_spi->base); | |
ccf06998 KG |
639 | |
640 | return 0; | |
641 | } | |
642 | ||
575c5807 | 643 | struct mpc8xxx_spi_probe_info { |
35b4b3c0 AV |
644 | struct fsl_spi_platform_data pdata; |
645 | int *gpios; | |
646 | bool *alow_flags; | |
647 | }; | |
648 | ||
575c5807 | 649 | static struct mpc8xxx_spi_probe_info * |
35b4b3c0 AV |
650 | to_of_pinfo(struct fsl_spi_platform_data *pdata) |
651 | { | |
575c5807 | 652 | return container_of(pdata, struct mpc8xxx_spi_probe_info, pdata); |
35b4b3c0 AV |
653 | } |
654 | ||
575c5807 | 655 | static void mpc8xxx_spi_cs_control(struct spi_device *spi, bool on) |
35b4b3c0 AV |
656 | { |
657 | struct device *dev = spi->dev.parent; | |
575c5807 | 658 | struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(dev->platform_data); |
35b4b3c0 AV |
659 | u16 cs = spi->chip_select; |
660 | int gpio = pinfo->gpios[cs]; | |
661 | bool alow = pinfo->alow_flags[cs]; | |
662 | ||
663 | gpio_set_value(gpio, on ^ alow); | |
664 | } | |
665 | ||
575c5807 | 666 | static int of_mpc8xxx_spi_get_chipselects(struct device *dev) |
35b4b3c0 AV |
667 | { |
668 | struct device_node *np = dev_archdata_get_node(&dev->archdata); | |
669 | struct fsl_spi_platform_data *pdata = dev->platform_data; | |
575c5807 | 670 | struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(pdata); |
35b4b3c0 AV |
671 | unsigned int ngpios; |
672 | int i = 0; | |
673 | int ret; | |
674 | ||
675 | ngpios = of_gpio_count(np); | |
676 | if (!ngpios) { | |
677 | /* | |
678 | * SPI w/o chip-select line. One SPI device is still permitted | |
679 | * though. | |
680 | */ | |
681 | pdata->max_chipselect = 1; | |
682 | return 0; | |
683 | } | |
684 | ||
02141546 | 685 | pinfo->gpios = kmalloc(ngpios * sizeof(*pinfo->gpios), GFP_KERNEL); |
35b4b3c0 AV |
686 | if (!pinfo->gpios) |
687 | return -ENOMEM; | |
02141546 | 688 | memset(pinfo->gpios, -1, ngpios * sizeof(*pinfo->gpios)); |
35b4b3c0 | 689 | |
02141546 | 690 | pinfo->alow_flags = kzalloc(ngpios * sizeof(*pinfo->alow_flags), |
35b4b3c0 AV |
691 | GFP_KERNEL); |
692 | if (!pinfo->alow_flags) { | |
693 | ret = -ENOMEM; | |
694 | goto err_alloc_flags; | |
695 | } | |
696 | ||
697 | for (; i < ngpios; i++) { | |
698 | int gpio; | |
699 | enum of_gpio_flags flags; | |
700 | ||
701 | gpio = of_get_gpio_flags(np, i, &flags); | |
702 | if (!gpio_is_valid(gpio)) { | |
703 | dev_err(dev, "invalid gpio #%d: %d\n", i, gpio); | |
783058fd | 704 | ret = gpio; |
35b4b3c0 AV |
705 | goto err_loop; |
706 | } | |
707 | ||
708 | ret = gpio_request(gpio, dev_name(dev)); | |
709 | if (ret) { | |
710 | dev_err(dev, "can't request gpio #%d: %d\n", i, ret); | |
711 | goto err_loop; | |
712 | } | |
713 | ||
714 | pinfo->gpios[i] = gpio; | |
715 | pinfo->alow_flags[i] = flags & OF_GPIO_ACTIVE_LOW; | |
716 | ||
717 | ret = gpio_direction_output(pinfo->gpios[i], | |
718 | pinfo->alow_flags[i]); | |
719 | if (ret) { | |
720 | dev_err(dev, "can't set output direction for gpio " | |
721 | "#%d: %d\n", i, ret); | |
722 | goto err_loop; | |
723 | } | |
724 | } | |
725 | ||
726 | pdata->max_chipselect = ngpios; | |
575c5807 | 727 | pdata->cs_control = mpc8xxx_spi_cs_control; |
35b4b3c0 AV |
728 | |
729 | return 0; | |
730 | ||
731 | err_loop: | |
732 | while (i >= 0) { | |
733 | if (gpio_is_valid(pinfo->gpios[i])) | |
734 | gpio_free(pinfo->gpios[i]); | |
735 | i--; | |
736 | } | |
737 | ||
738 | kfree(pinfo->alow_flags); | |
739 | pinfo->alow_flags = NULL; | |
740 | err_alloc_flags: | |
741 | kfree(pinfo->gpios); | |
742 | pinfo->gpios = NULL; | |
743 | return ret; | |
744 | } | |
745 | ||
575c5807 | 746 | static int of_mpc8xxx_spi_free_chipselects(struct device *dev) |
35b4b3c0 AV |
747 | { |
748 | struct fsl_spi_platform_data *pdata = dev->platform_data; | |
575c5807 | 749 | struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(pdata); |
35b4b3c0 AV |
750 | int i; |
751 | ||
752 | if (!pinfo->gpios) | |
753 | return 0; | |
754 | ||
755 | for (i = 0; i < pdata->max_chipselect; i++) { | |
756 | if (gpio_is_valid(pinfo->gpios[i])) | |
757 | gpio_free(pinfo->gpios[i]); | |
758 | } | |
759 | ||
760 | kfree(pinfo->gpios); | |
761 | kfree(pinfo->alow_flags); | |
762 | return 0; | |
763 | } | |
764 | ||
575c5807 | 765 | static int __devinit of_mpc8xxx_spi_probe(struct of_device *ofdev, |
35b4b3c0 AV |
766 | const struct of_device_id *ofid) |
767 | { | |
768 | struct device *dev = &ofdev->dev; | |
769 | struct device_node *np = ofdev->node; | |
575c5807 | 770 | struct mpc8xxx_spi_probe_info *pinfo; |
35b4b3c0 AV |
771 | struct fsl_spi_platform_data *pdata; |
772 | struct spi_master *master; | |
773 | struct resource mem; | |
774 | struct resource irq; | |
775 | const void *prop; | |
776 | int ret = -ENOMEM; | |
777 | ||
778 | pinfo = kzalloc(sizeof(*pinfo), GFP_KERNEL); | |
779 | if (!pinfo) | |
780 | return -ENOMEM; | |
781 | ||
782 | pdata = &pinfo->pdata; | |
783 | dev->platform_data = pdata; | |
784 | ||
785 | /* Allocate bus num dynamically. */ | |
786 | pdata->bus_num = -1; | |
787 | ||
788 | /* SPI controller is either clocked from QE or SoC clock. */ | |
789 | pdata->sysclk = get_brgfreq(); | |
790 | if (pdata->sysclk == -1) { | |
791 | pdata->sysclk = fsl_get_sys_freq(); | |
792 | if (pdata->sysclk == -1) { | |
793 | ret = -ENODEV; | |
794 | goto err_clk; | |
795 | } | |
796 | } | |
797 | ||
798 | prop = of_get_property(np, "mode", NULL); | |
799 | if (prop && !strcmp(prop, "cpu-qe")) | |
800 | pdata->qe_mode = 1; | |
801 | ||
575c5807 | 802 | ret = of_mpc8xxx_spi_get_chipselects(dev); |
35b4b3c0 AV |
803 | if (ret) |
804 | goto err; | |
805 | ||
806 | ret = of_address_to_resource(np, 0, &mem); | |
807 | if (ret) | |
808 | goto err; | |
809 | ||
810 | ret = of_irq_to_resource(np, 0, &irq); | |
811 | if (!ret) { | |
812 | ret = -EINVAL; | |
813 | goto err; | |
814 | } | |
815 | ||
575c5807 | 816 | master = mpc8xxx_spi_probe(dev, &mem, irq.start); |
35b4b3c0 AV |
817 | if (IS_ERR(master)) { |
818 | ret = PTR_ERR(master); | |
819 | goto err; | |
820 | } | |
821 | ||
822 | of_register_spi_devices(master, np); | |
823 | ||
824 | return 0; | |
825 | ||
826 | err: | |
575c5807 | 827 | of_mpc8xxx_spi_free_chipselects(dev); |
35b4b3c0 AV |
828 | err_clk: |
829 | kfree(pinfo); | |
830 | return ret; | |
831 | } | |
832 | ||
575c5807 | 833 | static int __devexit of_mpc8xxx_spi_remove(struct of_device *ofdev) |
35b4b3c0 AV |
834 | { |
835 | int ret; | |
836 | ||
575c5807 | 837 | ret = mpc8xxx_spi_remove(&ofdev->dev); |
35b4b3c0 AV |
838 | if (ret) |
839 | return ret; | |
575c5807 | 840 | of_mpc8xxx_spi_free_chipselects(&ofdev->dev); |
35b4b3c0 AV |
841 | return 0; |
842 | } | |
843 | ||
575c5807 | 844 | static const struct of_device_id of_mpc8xxx_spi_match[] = { |
35b4b3c0 AV |
845 | { .compatible = "fsl,spi" }, |
846 | {}, | |
847 | }; | |
575c5807 | 848 | MODULE_DEVICE_TABLE(of, of_mpc8xxx_spi_match); |
35b4b3c0 | 849 | |
575c5807 AV |
850 | static struct of_platform_driver of_mpc8xxx_spi_driver = { |
851 | .name = "mpc8xxx_spi", | |
852 | .match_table = of_mpc8xxx_spi_match, | |
853 | .probe = of_mpc8xxx_spi_probe, | |
854 | .remove = __devexit_p(of_mpc8xxx_spi_remove), | |
35b4b3c0 AV |
855 | }; |
856 | ||
857 | #ifdef CONFIG_MPC832x_RDB | |
858 | /* | |
859 | * XXX XXX XXX | |
860 | * This is "legacy" platform driver, was used by the MPC8323E-RDB boards | |
861 | * only. The driver should go away soon, since newer MPC8323E-RDB's device | |
862 | * tree can work with OpenFirmware driver. But for now we support old trees | |
863 | * as well. | |
864 | */ | |
575c5807 | 865 | static int __devinit plat_mpc8xxx_spi_probe(struct platform_device *pdev) |
35b4b3c0 AV |
866 | { |
867 | struct resource *mem; | |
868 | unsigned int irq; | |
869 | struct spi_master *master; | |
870 | ||
871 | if (!pdev->dev.platform_data) | |
872 | return -EINVAL; | |
873 | ||
874 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
875 | if (!mem) | |
876 | return -EINVAL; | |
877 | ||
878 | irq = platform_get_irq(pdev, 0); | |
879 | if (!irq) | |
880 | return -EINVAL; | |
881 | ||
575c5807 | 882 | master = mpc8xxx_spi_probe(&pdev->dev, mem, irq); |
35b4b3c0 AV |
883 | if (IS_ERR(master)) |
884 | return PTR_ERR(master); | |
885 | return 0; | |
886 | } | |
887 | ||
575c5807 | 888 | static int __devexit plat_mpc8xxx_spi_remove(struct platform_device *pdev) |
35b4b3c0 | 889 | { |
575c5807 | 890 | return mpc8xxx_spi_remove(&pdev->dev); |
35b4b3c0 AV |
891 | } |
892 | ||
575c5807 AV |
893 | MODULE_ALIAS("platform:mpc8xxx_spi"); |
894 | static struct platform_driver mpc8xxx_spi_driver = { | |
895 | .probe = plat_mpc8xxx_spi_probe, | |
896 | .remove = __exit_p(plat_mpc8xxx_spi_remove), | |
ccf06998 | 897 | .driver = { |
575c5807 | 898 | .name = "mpc8xxx_spi", |
7e38c3c4 | 899 | .owner = THIS_MODULE, |
ccf06998 KG |
900 | }, |
901 | }; | |
902 | ||
35b4b3c0 AV |
903 | static bool legacy_driver_failed; |
904 | ||
905 | static void __init legacy_driver_register(void) | |
906 | { | |
575c5807 | 907 | legacy_driver_failed = platform_driver_register(&mpc8xxx_spi_driver); |
35b4b3c0 AV |
908 | } |
909 | ||
910 | static void __exit legacy_driver_unregister(void) | |
911 | { | |
912 | if (legacy_driver_failed) | |
913 | return; | |
575c5807 | 914 | platform_driver_unregister(&mpc8xxx_spi_driver); |
35b4b3c0 AV |
915 | } |
916 | #else | |
917 | static void __init legacy_driver_register(void) {} | |
918 | static void __exit legacy_driver_unregister(void) {} | |
919 | #endif /* CONFIG_MPC832x_RDB */ | |
920 | ||
575c5807 | 921 | static int __init mpc8xxx_spi_init(void) |
ccf06998 | 922 | { |
35b4b3c0 | 923 | legacy_driver_register(); |
575c5807 | 924 | return of_register_platform_driver(&of_mpc8xxx_spi_driver); |
ccf06998 KG |
925 | } |
926 | ||
575c5807 | 927 | static void __exit mpc8xxx_spi_exit(void) |
ccf06998 | 928 | { |
575c5807 | 929 | of_unregister_platform_driver(&of_mpc8xxx_spi_driver); |
35b4b3c0 | 930 | legacy_driver_unregister(); |
ccf06998 KG |
931 | } |
932 | ||
575c5807 AV |
933 | module_init(mpc8xxx_spi_init); |
934 | module_exit(mpc8xxx_spi_exit); | |
ccf06998 KG |
935 | |
936 | MODULE_AUTHOR("Kumar Gala"); | |
575c5807 | 937 | MODULE_DESCRIPTION("Simple MPC8xxx SPI Driver"); |
ccf06998 | 938 | MODULE_LICENSE("GPL"); |