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spi_bfin: wait for tx to complete on some cs_chg paths
[linux-2.6-block.git] / drivers / spi / spi_bfin5xx.c
CommitLineData
a5f6abd4 1/*
131b17d4
BW		 2 * File: drivers/spi/bfin5xx_spi.c
3 * Maintainer:
4 * Bryan Wu <bryan.wu@analog.com>
5 * Original Author:
6 * Luke Yang (Analog Devices Inc.)
a5f6abd4 7 *
131b17d4
BW		 8 * Created: March. 10th 2006
9 * Description: SPI controller driver for Blackfin BF5xx
10 * Bugs: Enter bugs at http://blackfin.uclinux.org/
a5f6abd4
WB		 11 *
12 * Modified:
13 * March 10, 2006 bfin5xx_spi.c Created. (Luke Yang)
14 * August 7, 2006 added full duplex mode (Axel Weiss & Luke Yang)
131b17d4 15 * July 17, 2007 add support for BF54x SPI0 controller (Bryan Wu)
a32c691d
BW		 16 * July 30, 2007 add platfrom_resource interface to support multi-port
17 * SPI controller (Bryan Wu)
a5f6abd4 18 *
131b17d4 19 * Copyright 2004-2007 Analog Devices Inc.
a5f6abd4
WB		 20 *
21 * This program is free software ; you can redistribute it and/or modify
22 * it under the terms of the GNU General Public License as published by
23 * the Free Software Foundation ; either version 2, or (at your option)
24 * any later version.
25 *
26 * This program is distributed in the hope that it will be useful,
27 * but WITHOUT ANY WARRANTY ; without even the implied warranty of
28 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
29 * GNU General Public License for more details.
30 *
31 * You should have received a copy of the GNU General Public License
32 * along with this program ; see the file COPYING.
33 * If not, write to the Free Software Foundation,
34 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
35 */
36
37#include <linux/init.h>
38#include <linux/module.h>
131b17d4 39#include <linux/delay.h>
a5f6abd4 40#include <linux/device.h>
131b17d4 41#include <linux/io.h>
a5f6abd4 42#include <linux/ioport.h>
131b17d4 43#include <linux/irq.h>
a5f6abd4
WB		 44#include <linux/errno.h>
45#include <linux/interrupt.h>
46#include <linux/platform_device.h>
47#include <linux/dma-mapping.h>
48#include <linux/spi/spi.h>
49#include <linux/workqueue.h>
a5f6abd4 50
a5f6abd4 51#include <asm/dma.h>
131b17d4 52#include <asm/portmux.h>
a5f6abd4
WB		 53#include <asm/bfin5xx_spi.h>
54
a32c691d
BW		 55#define DRV_NAME "bfin-spi"
56#define DRV_AUTHOR "Bryan Wu, Luke Yang"
6b1a8028 57#define DRV_DESC "Blackfin BF5xx on-chip SPI Controller Driver"
a32c691d
BW		 58#define DRV_VERSION "1.0"
59
60MODULE_AUTHOR(DRV_AUTHOR);
61MODULE_DESCRIPTION(DRV_DESC);
a5f6abd4
WB		 62MODULE_LICENSE("GPL");
63
bb90eb00 64#define IS_DMA_ALIGNED(x) (((u32)(x)&0x07) == 0)
a5f6abd4 65
bb90eb00
BW		 66#define START_STATE ((void *)0)
67#define RUNNING_STATE ((void *)1)
68#define DONE_STATE ((void *)2)
69#define ERROR_STATE ((void *)-1)
70#define QUEUE_RUNNING 0
71#define QUEUE_STOPPED 1
a5f6abd4
WB		 72
73struct driver_data {
74 /* Driver model hookup */
75 struct platform_device *pdev;
76
77 /* SPI framework hookup */
78 struct spi_master *master;
79
bb90eb00 80 /* Regs base of SPI controller */
f452126c 81 void __iomem *regs_base;
bb90eb00 82
003d9226
BW		 83 /* Pin request list */
84 u16 *pin_req;
85
a5f6abd4
WB		 86 /* BFIN hookup */
87 struct bfin5xx_spi_master *master_info;
88
89 /* Driver message queue */
90 struct workqueue_struct *workqueue;
91 struct work_struct pump_messages;
92 spinlock_t lock;
93 struct list_head queue;
94 int busy;
95 int run;
96
97 /* Message Transfer pump */
98 struct tasklet_struct pump_transfers;
99
100 /* Current message transfer state info */
101 struct spi_message *cur_msg;
102 struct spi_transfer *cur_transfer;
103 struct chip_data *cur_chip;
104 size_t len_in_bytes;
105 size_t len;
106 void *tx;
107 void *tx_end;
108 void *rx;
109 void *rx_end;
bb90eb00
BW		 110
111 /* DMA stuffs */
112 int dma_channel;
a5f6abd4 113 int dma_mapped;
bb90eb00 114 int dma_requested;
a5f6abd4
WB		 115 dma_addr_t rx_dma;
116 dma_addr_t tx_dma;
bb90eb00 117
a5f6abd4
WB		 118 size_t rx_map_len;
119 size_t tx_map_len;
120 u8 n_bytes;
fad91c89 121 int cs_change;
a5f6abd4
WB		 122 void (*write) (struct driver_data *);
123 void (*read) (struct driver_data *);
124 void (*duplex) (struct driver_data *);
125};
126
127struct chip_data {
128 u16 ctl_reg;
129 u16 baud;
130 u16 flag;
131
132 u8 chip_select_num;
133 u8 n_bytes;
88b40369 134 u8 width; /* 0 or 1 */
a5f6abd4
WB		 135 u8 enable_dma;
136 u8 bits_per_word; /* 8 or 16 */
137 u8 cs_change_per_word;
62310e51 138 u16 cs_chg_udelay; /* Some devices require > 255usec delay */
a5f6abd4
WB		 139 void (*write) (struct driver_data *);
140 void (*read) (struct driver_data *);
141 void (*duplex) (struct driver_data *);
142};
143
bb90eb00
BW		 144#define DEFINE_SPI_REG(reg, off) \
145static inline u16 read_##reg(struct driver_data *drv_data) \
146 { return bfin_read16(drv_data->regs_base + off); } \
147static inline void write_##reg(struct driver_data *drv_data, u16 v) \
148 { bfin_write16(drv_data->regs_base + off, v); }
149
150DEFINE_SPI_REG(CTRL, 0x00)
151DEFINE_SPI_REG(FLAG, 0x04)
152DEFINE_SPI_REG(STAT, 0x08)
153DEFINE_SPI_REG(TDBR, 0x0C)
154DEFINE_SPI_REG(RDBR, 0x10)
155DEFINE_SPI_REG(BAUD, 0x14)
156DEFINE_SPI_REG(SHAW, 0x18)
157
88b40369 158static void bfin_spi_enable(struct driver_data *drv_data)
a5f6abd4
WB		 159{
160 u16 cr;
161
bb90eb00
BW		 162 cr = read_CTRL(drv_data);
163 write_CTRL(drv_data, (cr | BIT_CTL_ENABLE));
a5f6abd4
WB		 164}
165
88b40369 166static void bfin_spi_disable(struct driver_data *drv_data)
a5f6abd4
WB		 167{
168 u16 cr;
169
bb90eb00
BW		 170 cr = read_CTRL(drv_data);
171 write_CTRL(drv_data, (cr & (~BIT_CTL_ENABLE)));
a5f6abd4
WB		 172}
173
174/* Caculate the SPI_BAUD register value based on input HZ */
175static u16 hz_to_spi_baud(u32 speed_hz)
176{
177 u_long sclk = get_sclk();
178 u16 spi_baud = (sclk / (2 * speed_hz));
179
180 if ((sclk % (2 * speed_hz)) > 0)
181 spi_baud++;
182
a5f6abd4
WB		 183 return spi_baud;
184}
185
186static int flush(struct driver_data *drv_data)
187{
188 unsigned long limit = loops_per_jiffy << 1;
189
190 /* wait for stop and clear stat */
bb90eb00 191 while (!(read_STAT(drv_data) & BIT_STAT_SPIF) && limit--)
d8c05008 192 cpu_relax();
a5f6abd4 193
bb90eb00 194 write_STAT(drv_data, BIT_STAT_CLR);
a5f6abd4
WB		 195
196 return limit;
197}
198
fad91c89 199/* Chip select operation functions for cs_change flag */
bb90eb00 200static void cs_active(struct driver_data *drv_data, struct chip_data *chip)
fad91c89 201{
bb90eb00 202 u16 flag = read_FLAG(drv_data);
fad91c89
BW		 203
204 flag |= chip->flag;
205 flag &= ~(chip->flag << 8);
206
bb90eb00 207 write_FLAG(drv_data, flag);
fad91c89
BW		 208}
209
bb90eb00 210static void cs_deactive(struct driver_data *drv_data, struct chip_data *chip)
fad91c89 211{
bb90eb00 212 u16 flag = read_FLAG(drv_data);
fad91c89
BW		 213
214 flag |= (chip->flag << 8);
215
bb90eb00 216 write_FLAG(drv_data, flag);
62310e51
BW		 217
218 /* Move delay here for consistency */
219 if (chip->cs_chg_udelay)
220 udelay(chip->cs_chg_udelay);
fad91c89
BW		 221}
222
7c4ef094 223#define MAX_SPI_SSEL 7
5fec5b5a 224
a5f6abd4 225/* stop controller and re-config current chip*/
8d20d0a7 226static void restore_state(struct driver_data *drv_data)
a5f6abd4
WB		 227{
228 struct chip_data *chip = drv_data->cur_chip;
12e17c42 229
a5f6abd4 230 /* Clear status and disable clock */
bb90eb00 231 write_STAT(drv_data, BIT_STAT_CLR);
a5f6abd4 232 bfin_spi_disable(drv_data);
88b40369 233 dev_dbg(&drv_data->pdev->dev, "restoring spi ctl state\n");
a5f6abd4 234
5fec5b5a 235 /* Load the registers */
bb90eb00 236 write_CTRL(drv_data, chip->ctl_reg);
092e1fda 237 write_BAUD(drv_data, chip->baud);
cc487e73
SZ		 238
239 bfin_spi_enable(drv_data);
07612e5f 240 cs_active(drv_data, chip);
a5f6abd4
WB		 241}
242
243/* used to kick off transfer in rx mode */
bb90eb00 244static unsigned short dummy_read(struct driver_data *drv_data)
a5f6abd4
WB		 245{
246 unsigned short tmp;
bb90eb00 247 tmp = read_RDBR(drv_data);
a5f6abd4
WB		 248 return tmp;
249}
250
251static void null_writer(struct driver_data *drv_data)
252{
253 u8 n_bytes = drv_data->n_bytes;
254
255 while (drv_data->tx < drv_data->tx_end) {
bb90eb00
BW		 256 write_TDBR(drv_data, 0);
257 while ((read_STAT(drv_data) & BIT_STAT_TXS))
d8c05008 258 cpu_relax();
a5f6abd4
WB		 259 drv_data->tx += n_bytes;
260 }
261}
262
263static void null_reader(struct driver_data *drv_data)
264{
265 u8 n_bytes = drv_data->n_bytes;
bb90eb00 266 dummy_read(drv_data);
a5f6abd4
WB		 267
268 while (drv_data->rx < drv_data->rx_end) {
bb90eb00 269 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
d8c05008 270 cpu_relax();
bb90eb00 271 dummy_read(drv_data);
a5f6abd4
WB		 272 drv_data->rx += n_bytes;
273 }
274}
275
276static void u8_writer(struct driver_data *drv_data)
277{
131b17d4 278 dev_dbg(&drv_data->pdev->dev,
bb90eb00 279 "cr8-s is 0x%x\n", read_STAT(drv_data));
cc487e73 280
3f479a65 281 /* poll for SPI completion before start */
bb90eb00 282 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
d8c05008 283 cpu_relax();
3f479a65 284
a5f6abd4 285 while (drv_data->tx < drv_data->tx_end) {
bb90eb00
BW		 286 write_TDBR(drv_data, (*(u8 *) (drv_data->tx)));
287 while (read_STAT(drv_data) & BIT_STAT_TXS)
d8c05008 288 cpu_relax();
a5f6abd4
WB		 289 ++drv_data->tx;
290 }
a5f6abd4
WB		 291}
292
293static void u8_cs_chg_writer(struct driver_data *drv_data)
294{
295 struct chip_data *chip = drv_data->cur_chip;
296
297 while (drv_data->tx < drv_data->tx_end) {
bb90eb00 298 cs_active(drv_data, chip);
a5f6abd4 299
bb90eb00
BW		 300 write_TDBR(drv_data, (*(u8 *) (drv_data->tx)));
301 while (read_STAT(drv_data) & BIT_STAT_TXS)
d8c05008 302 cpu_relax();
e26aa015
BW		 303 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
304 cpu_relax();
62310e51 305
bb90eb00 306 cs_deactive(drv_data, chip);
5fec5b5a 307
a5f6abd4
WB		 308 ++drv_data->tx;
309 }
a5f6abd4
WB		 310}
311
312static void u8_reader(struct driver_data *drv_data)
313{
131b17d4 314 dev_dbg(&drv_data->pdev->dev,
bb90eb00 315 "cr-8 is 0x%x\n", read_STAT(drv_data));
a5f6abd4 316
3f479a65 317 /* poll for SPI completion before start */
bb90eb00 318 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
d8c05008 319 cpu_relax();
3f479a65 320
a5f6abd4 321 /* clear TDBR buffer before read(else it will be shifted out) */
bb90eb00 322 write_TDBR(drv_data, 0xFFFF);
a5f6abd4 323
bb90eb00 324 dummy_read(drv_data);
cc487e73 325
a5f6abd4 326 while (drv_data->rx < drv_data->rx_end - 1) {
bb90eb00 327 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
d8c05008 328 cpu_relax();
bb90eb00 329 *(u8 *) (drv_data->rx) = read_RDBR(drv_data);
a5f6abd4
WB		 330 ++drv_data->rx;
331 }
332
bb90eb00 333 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
d8c05008 334 cpu_relax();
bb90eb00 335 *(u8 *) (drv_data->rx) = read_SHAW(drv_data);
a5f6abd4
WB		 336 ++drv_data->rx;
337}
338
339static void u8_cs_chg_reader(struct driver_data *drv_data)
340{
341 struct chip_data *chip = drv_data->cur_chip;
342
e26aa015
BW		 343 while (drv_data->rx < drv_data->rx_end) {
344 cs_active(drv_data, chip);
345 read_RDBR(drv_data); /* kick off */
a5f6abd4 346
e26aa015
BW		 347 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
348 cpu_relax();
349 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
350 cpu_relax();
cc487e73 351
e26aa015 352 *(u8 *) (drv_data->rx) = read_SHAW(drv_data);
bb90eb00 353 cs_deactive(drv_data, chip);
5fec5b5a 354
a5f6abd4
WB		 355 ++drv_data->rx;
356 }
a5f6abd4
WB		 357}
358
359static void u8_duplex(struct driver_data *drv_data)
360{
3f479a65 361 /* poll for SPI completion before start */
bb90eb00 362 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
d8c05008 363 cpu_relax();
3f479a65 364
a5f6abd4
WB		 365 /* in duplex mode, clk is triggered by writing of TDBR */
366 while (drv_data->rx < drv_data->rx_end) {
bb90eb00
BW		 367 write_TDBR(drv_data, (*(u8 *) (drv_data->tx)));
368 while (read_STAT(drv_data) & BIT_STAT_TXS)
d8c05008 369 cpu_relax();
bb90eb00 370 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
d8c05008 371 cpu_relax();
bb90eb00 372 *(u8 *) (drv_data->rx) = read_RDBR(drv_data);
a5f6abd4
WB		 373 ++drv_data->rx;
374 ++drv_data->tx;
375 }
376}
377
378static void u8_cs_chg_duplex(struct driver_data *drv_data)
379{
380 struct chip_data *chip = drv_data->cur_chip;
381
382 while (drv_data->rx < drv_data->rx_end) {
bb90eb00 383 cs_active(drv_data, chip);
5fec5b5a 384
bb90eb00 385 write_TDBR(drv_data, (*(u8 *) (drv_data->tx)));
e26aa015
BW		 386
387 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
d8c05008 388 cpu_relax();
bb90eb00 389 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
d8c05008 390 cpu_relax();
bb90eb00 391 *(u8 *) (drv_data->rx) = read_RDBR(drv_data);
62310e51 392
bb90eb00 393 cs_deactive(drv_data, chip);
5fec5b5a 394
a5f6abd4
WB		 395 ++drv_data->rx;
396 ++drv_data->tx;
397 }
a5f6abd4
WB		 398}
399
400static void u16_writer(struct driver_data *drv_data)
401{
131b17d4 402 dev_dbg(&drv_data->pdev->dev,
bb90eb00 403 "cr16 is 0x%x\n", read_STAT(drv_data));
88b40369 404
3f479a65 405 /* poll for SPI completion before start */
bb90eb00 406 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
d8c05008 407 cpu_relax();
3f479a65 408
a5f6abd4 409 while (drv_data->tx < drv_data->tx_end) {
bb90eb00
BW		 410 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
411 while ((read_STAT(drv_data) & BIT_STAT_TXS))
d8c05008 412 cpu_relax();
a5f6abd4
WB		 413 drv_data->tx += 2;
414 }
a5f6abd4
WB		 415}
416
417static void u16_cs_chg_writer(struct driver_data *drv_data)
418{
419 struct chip_data *chip = drv_data->cur_chip;
420
3f479a65 421 /* poll for SPI completion before start */
bb90eb00 422 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
d8c05008 423 cpu_relax();
3f479a65 424
a5f6abd4 425 while (drv_data->tx < drv_data->tx_end) {
bb90eb00 426 cs_active(drv_data, chip);
a5f6abd4 427
bb90eb00
BW		 428 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
429 while ((read_STAT(drv_data) & BIT_STAT_TXS))
d8c05008 430 cpu_relax();
62310e51 431
bb90eb00 432 cs_deactive(drv_data, chip);
5fec5b5a 433
a5f6abd4
WB		 434 drv_data->tx += 2;
435 }
a5f6abd4
WB		 436}
437
438static void u16_reader(struct driver_data *drv_data)
439{
88b40369 440 dev_dbg(&drv_data->pdev->dev,
bb90eb00 441 "cr-16 is 0x%x\n", read_STAT(drv_data));
cc487e73 442
3f479a65 443 /* poll for SPI completion before start */
bb90eb00 444 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
d8c05008 445 cpu_relax();
3f479a65 446
cc487e73 447 /* clear TDBR buffer before read(else it will be shifted out) */
bb90eb00 448 write_TDBR(drv_data, 0xFFFF);
cc487e73 449
bb90eb00 450 dummy_read(drv_data);
a5f6abd4
WB		 451
452 while (drv_data->rx < (drv_data->rx_end - 2)) {
bb90eb00 453 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
d8c05008 454 cpu_relax();
bb90eb00 455 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
a5f6abd4
WB		 456 drv_data->rx += 2;
457 }
458
bb90eb00 459 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
d8c05008 460 cpu_relax();
bb90eb00 461 *(u16 *) (drv_data->rx) = read_SHAW(drv_data);
a5f6abd4
WB		 462 drv_data->rx += 2;
463}
464
465static void u16_cs_chg_reader(struct driver_data *drv_data)
466{
467 struct chip_data *chip = drv_data->cur_chip;
468
3f479a65 469 /* poll for SPI completion before start */
bb90eb00 470 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
d8c05008 471 cpu_relax();
3f479a65 472
cc487e73 473 /* clear TDBR buffer before read(else it will be shifted out) */
bb90eb00 474 write_TDBR(drv_data, 0xFFFF);
a5f6abd4 475
bb90eb00
BW		 476 cs_active(drv_data, chip);
477 dummy_read(drv_data);
cc487e73 478
c3061abb 479 while (drv_data->rx < drv_data->rx_end - 2) {
bb90eb00 480 cs_deactive(drv_data, chip);
5fec5b5a 481
bb90eb00 482 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
d8c05008 483 cpu_relax();
bb90eb00
BW		 484 cs_active(drv_data, chip);
485 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
a5f6abd4
WB		 486 drv_data->rx += 2;
487 }
bb90eb00 488 cs_deactive(drv_data, chip);
cc487e73 489
bb90eb00 490 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
d8c05008 491 cpu_relax();
bb90eb00 492 *(u16 *) (drv_data->rx) = read_SHAW(drv_data);
cc487e73 493 drv_data->rx += 2;
a5f6abd4
WB		 494}
495
496static void u16_duplex(struct driver_data *drv_data)
497{
3f479a65 498 /* poll for SPI completion before start */
bb90eb00 499 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
d8c05008 500 cpu_relax();
3f479a65 501
a5f6abd4
WB		 502 /* in duplex mode, clk is triggered by writing of TDBR */
503 while (drv_data->tx < drv_data->tx_end) {
bb90eb00
BW		 504 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
505 while (read_STAT(drv_data) & BIT_STAT_TXS)
d8c05008 506 cpu_relax();
bb90eb00 507 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
d8c05008 508 cpu_relax();
bb90eb00 509 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
a5f6abd4
WB		 510 drv_data->rx += 2;
511 drv_data->tx += 2;
512 }
513}
514
515static void u16_cs_chg_duplex(struct driver_data *drv_data)
516{
517 struct chip_data *chip = drv_data->cur_chip;
518
3f479a65 519 /* poll for SPI completion before start */
bb90eb00 520 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
d8c05008 521 cpu_relax();
3f479a65 522
a5f6abd4 523 while (drv_data->tx < drv_data->tx_end) {
bb90eb00 524 cs_active(drv_data, chip);
a5f6abd4 525
bb90eb00
BW		 526 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
527 while (read_STAT(drv_data) & BIT_STAT_TXS)
d8c05008 528 cpu_relax();
bb90eb00 529 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
d8c05008 530 cpu_relax();
bb90eb00 531 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
62310e51 532
bb90eb00 533 cs_deactive(drv_data, chip);
5fec5b5a 534
a5f6abd4
WB		 535 drv_data->rx += 2;
536 drv_data->tx += 2;
537 }
a5f6abd4
WB		 538}
539
540/* test if ther is more transfer to be done */
541static void *next_transfer(struct driver_data *drv_data)
542{
543 struct spi_message *msg = drv_data->cur_msg;
544 struct spi_transfer *trans = drv_data->cur_transfer;
545
546 /* Move to next transfer */
547 if (trans->transfer_list.next != &msg->transfers) {
548 drv_data->cur_transfer =
549 list_entry(trans->transfer_list.next,
550 struct spi_transfer, transfer_list);
551 return RUNNING_STATE;
552 } else
553 return DONE_STATE;
554}
555
556/*
557 * caller already set message->status;
558 * dma and pio irqs are blocked give finished message back
559 */
560static void giveback(struct driver_data *drv_data)
561{
fad91c89 562 struct chip_data *chip = drv_data->cur_chip;
a5f6abd4
WB		 563 struct spi_transfer *last_transfer;
564 unsigned long flags;
565 struct spi_message *msg;
566
567 spin_lock_irqsave(&drv_data->lock, flags);
568 msg = drv_data->cur_msg;
569 drv_data->cur_msg = NULL;
570 drv_data->cur_transfer = NULL;
571 drv_data->cur_chip = NULL;
572 queue_work(drv_data->workqueue, &drv_data->pump_messages);
573 spin_unlock_irqrestore(&drv_data->lock, flags);
574
575 last_transfer = list_entry(msg->transfers.prev,
576 struct spi_transfer, transfer_list);
577
578 msg->state = NULL;
579
580 /* disable chip select signal. And not stop spi in autobuffer mode */
581 if (drv_data->tx_dma != 0xFFFF) {
bb90eb00 582 cs_deactive(drv_data, chip);
a5f6abd4
WB		 583 bfin_spi_disable(drv_data);
584 }
585
fad91c89 586 if (!drv_data->cs_change)
bb90eb00 587 cs_deactive(drv_data, chip);
fad91c89 588
a5f6abd4
WB		 589 if (msg->complete)
590 msg->complete(msg->context);
591}
592
88b40369 593static irqreturn_t dma_irq_handler(int irq, void *dev_id)
a5f6abd4 594{
15aafa2f 595 struct driver_data *drv_data = dev_id;
fad91c89 596 struct chip_data *chip = drv_data->cur_chip;
bb90eb00 597 struct spi_message *msg = drv_data->cur_msg;
a5f6abd4 598
88b40369 599 dev_dbg(&drv_data->pdev->dev, "in dma_irq_handler\n");
bb90eb00 600 clear_dma_irqstat(drv_data->dma_channel);
a5f6abd4 601
d6fe89b0 602 /* Wait for DMA to complete */
bb90eb00 603 while (get_dma_curr_irqstat(drv_data->dma_channel) & DMA_RUN)
d8c05008 604 cpu_relax();
d6fe89b0 605
a5f6abd4 606 /*
d6fe89b0
BW		 607 * wait for the last transaction shifted out. HRM states:
608 * at this point there may still be data in the SPI DMA FIFO waiting
609 * to be transmitted ... software needs to poll TXS in the SPI_STAT
610 * register until it goes low for 2 successive reads
a5f6abd4
WB		 611 */
612 if (drv_data->tx != NULL) {
bb90eb00
BW		 613 while ((read_STAT(drv_data) & TXS) ||
614 (read_STAT(drv_data) & TXS))
d8c05008 615 cpu_relax();
a5f6abd4
WB		 616 }
617
bb90eb00 618 while (!(read_STAT(drv_data) & SPIF))
d8c05008 619 cpu_relax();
a5f6abd4 620
a5f6abd4
WB		 621 msg->actual_length += drv_data->len_in_bytes;
622
fad91c89 623 if (drv_data->cs_change)
bb90eb00 624 cs_deactive(drv_data, chip);
fad91c89 625
a5f6abd4
WB		 626 /* Move to next transfer */
627 msg->state = next_transfer(drv_data);
628
629 /* Schedule transfer tasklet */
630 tasklet_schedule(&drv_data->pump_transfers);
631
632 /* free the irq handler before next transfer */
88b40369
BW		 633 dev_dbg(&drv_data->pdev->dev,
634 "disable dma channel irq%d\n",
bb90eb00
BW		 635 drv_data->dma_channel);
636 dma_disable_irq(drv_data->dma_channel);
a5f6abd4
WB		 637
638 return IRQ_HANDLED;
639}
640
641static void pump_transfers(unsigned long data)
642{
643 struct driver_data *drv_data = (struct driver_data *)data;
644 struct spi_message *message = NULL;
645 struct spi_transfer *transfer = NULL;
646 struct spi_transfer *previous = NULL;
647 struct chip_data *chip = NULL;
88b40369
BW		 648 u8 width;
649 u16 cr, dma_width, dma_config;
a5f6abd4
WB		 650 u32 tranf_success = 1;
651
652 /* Get current state information */
653 message = drv_data->cur_msg;
654 transfer = drv_data->cur_transfer;
655 chip = drv_data->cur_chip;
092e1fda 656
a5f6abd4
WB		 657 /*
658 * if msg is error or done, report it back using complete() callback
659 */
660
661 /* Handle for abort */
662 if (message->state == ERROR_STATE) {
663 message->status = -EIO;
664 giveback(drv_data);
665 return;
666 }
667
668 /* Handle end of message */
669 if (message->state == DONE_STATE) {
670 message->status = 0;
671 giveback(drv_data);
672 return;
673 }
674
675 /* Delay if requested at end of transfer */
676 if (message->state == RUNNING_STATE) {
677 previous = list_entry(transfer->transfer_list.prev,
678 struct spi_transfer, transfer_list);
679 if (previous->delay_usecs)
680 udelay(previous->delay_usecs);
681 }
682
683 /* Setup the transfer state based on the type of transfer */
684 if (flush(drv_data) == 0) {
685 dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n");
686 message->status = -EIO;
687 giveback(drv_data);
688 return;
689 }
690
691 if (transfer->tx_buf != NULL) {
692 drv_data->tx = (void *)transfer->tx_buf;
693 drv_data->tx_end = drv_data->tx + transfer->len;
88b40369
BW		 694 dev_dbg(&drv_data->pdev->dev, "tx_buf is %p, tx_end is %p\n",
695 transfer->tx_buf, drv_data->tx_end);
a5f6abd4
WB		 696 } else {
697 drv_data->tx = NULL;
698 }
699
700 if (transfer->rx_buf != NULL) {
701 drv_data->rx = transfer->rx_buf;
702 drv_data->rx_end = drv_data->rx + transfer->len;
88b40369
BW		 703 dev_dbg(&drv_data->pdev->dev, "rx_buf is %p, rx_end is %p\n",
704 transfer->rx_buf, drv_data->rx_end);
a5f6abd4
WB		 705 } else {
706 drv_data->rx = NULL;
707 }
708
709 drv_data->rx_dma = transfer->rx_dma;
710 drv_data->tx_dma = transfer->tx_dma;
711 drv_data->len_in_bytes = transfer->len;
fad91c89 712 drv_data->cs_change = transfer->cs_change;
a5f6abd4 713
092e1fda
BW		 714 /* Bits per word setup */
715 switch (transfer->bits_per_word) {
716 case 8:
717 drv_data->n_bytes = 1;
718 width = CFG_SPI_WORDSIZE8;
719 drv_data->read = chip->cs_change_per_word ?
720 u8_cs_chg_reader : u8_reader;
721 drv_data->write = chip->cs_change_per_word ?
722 u8_cs_chg_writer : u8_writer;
723 drv_data->duplex = chip->cs_change_per_word ?
724 u8_cs_chg_duplex : u8_duplex;
725 break;
726
727 case 16:
728 drv_data->n_bytes = 2;
729 width = CFG_SPI_WORDSIZE16;
730 drv_data->read = chip->cs_change_per_word ?
731 u16_cs_chg_reader : u16_reader;
732 drv_data->write = chip->cs_change_per_word ?
733 u16_cs_chg_writer : u16_writer;
734 drv_data->duplex = chip->cs_change_per_word ?
735 u16_cs_chg_duplex : u16_duplex;
736 break;
737
738 default:
739 /* No change, the same as default setting */
740 drv_data->n_bytes = chip->n_bytes;
741 width = chip->width;
742 drv_data->write = drv_data->tx ? chip->write : null_writer;
743 drv_data->read = drv_data->rx ? chip->read : null_reader;
744 drv_data->duplex = chip->duplex ? chip->duplex : null_writer;
745 break;
746 }
747 cr = (read_CTRL(drv_data) & (~BIT_CTL_TIMOD));
748 cr |= (width << 8);
749 write_CTRL(drv_data, cr);
750
a5f6abd4
WB		 751 if (width == CFG_SPI_WORDSIZE16) {
752 drv_data->len = (transfer->len) >> 1;
753 } else {
754 drv_data->len = transfer->len;
755 }
131b17d4
BW		 756 dev_dbg(&drv_data->pdev->dev, "transfer: ",
757 "drv_data->write is %p, chip->write is %p, null_wr is %p\n",
758 drv_data->write, chip->write, null_writer);
a5f6abd4
WB		 759
760 /* speed and width has been set on per message */
761 message->state = RUNNING_STATE;
762 dma_config = 0;
763
092e1fda
BW		 764 /* Speed setup (surely valid because already checked) */
765 if (transfer->speed_hz)
766 write_BAUD(drv_data, hz_to_spi_baud(transfer->speed_hz));
767 else
768 write_BAUD(drv_data, chip->baud);
769
bb90eb00
BW		 770 write_STAT(drv_data, BIT_STAT_CLR);
771 cr = (read_CTRL(drv_data) & (~BIT_CTL_TIMOD));
772 cs_active(drv_data, chip);
a5f6abd4 773
88b40369
BW		 774 dev_dbg(&drv_data->pdev->dev,
775 "now pumping a transfer: width is %d, len is %d\n",
776 width, transfer->len);
a5f6abd4
WB		 777
778 /*
779 * Try to map dma buffer and do a dma transfer if
780 * successful use different way to r/w according to
781 * drv_data->cur_chip->enable_dma
782 */
783 if (drv_data->cur_chip->enable_dma && drv_data->len > 6) {
784
bb90eb00
BW		 785 disable_dma(drv_data->dma_channel);
786 clear_dma_irqstat(drv_data->dma_channel);
07612e5f 787 bfin_spi_disable(drv_data);
a5f6abd4
WB		 788
789 /* config dma channel */
88b40369 790 dev_dbg(&drv_data->pdev->dev, "doing dma transfer\n");
a5f6abd4 791 if (width == CFG_SPI_WORDSIZE16) {
bb90eb00
BW		 792 set_dma_x_count(drv_data->dma_channel, drv_data->len);
793 set_dma_x_modify(drv_data->dma_channel, 2);
a5f6abd4
WB		 794 dma_width = WDSIZE_16;
795 } else {
bb90eb00
BW		 796 set_dma_x_count(drv_data->dma_channel, drv_data->len);
797 set_dma_x_modify(drv_data->dma_channel, 1);
a5f6abd4
WB		 798 dma_width = WDSIZE_8;
799 }
800
3f479a65 801 /* poll for SPI completion before start */
bb90eb00 802 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
d8c05008 803 cpu_relax();
3f479a65 804
a5f6abd4
WB		 805 /* dirty hack for autobuffer DMA mode */
806 if (drv_data->tx_dma == 0xFFFF) {
88b40369
BW		 807 dev_dbg(&drv_data->pdev->dev,
808 "doing autobuffer DMA out.\n");
a5f6abd4
WB		 809
810 /* no irq in autobuffer mode */
811 dma_config =
812 (DMAFLOW_AUTO | RESTART | dma_width | DI_EN);
bb90eb00
BW		 813 set_dma_config(drv_data->dma_channel, dma_config);
814 set_dma_start_addr(drv_data->dma_channel,
a32c691d 815 (unsigned long)drv_data->tx);
bb90eb00 816 enable_dma(drv_data->dma_channel);
a5f6abd4 817
07612e5f
SZ		 818 /* start SPI transfer */
819 write_CTRL(drv_data,
820 (cr | CFG_SPI_DMAWRITE | BIT_CTL_ENABLE));
821
822 /* just return here, there can only be one transfer
823 * in this mode
824 */
a5f6abd4
WB		 825 message->status = 0;
826 giveback(drv_data);
827 return;
828 }
829
830 /* In dma mode, rx or tx must be NULL in one transfer */
831 if (drv_data->rx != NULL) {
832 /* set transfer mode, and enable SPI */
88b40369 833 dev_dbg(&drv_data->pdev->dev, "doing DMA in.\n");
a5f6abd4 834
a5f6abd4 835 /* clear tx reg soformer data is not shifted out */
bb90eb00 836 write_TDBR(drv_data, 0xFFFF);
a5f6abd4 837
bb90eb00 838 set_dma_x_count(drv_data->dma_channel, drv_data->len);
a5f6abd4
WB		 839
840 /* start dma */
bb90eb00 841 dma_enable_irq(drv_data->dma_channel);
a5f6abd4 842 dma_config = (WNR | RESTART | dma_width | DI_EN);
bb90eb00
BW		 843 set_dma_config(drv_data->dma_channel, dma_config);
844 set_dma_start_addr(drv_data->dma_channel,
a32c691d 845 (unsigned long)drv_data->rx);
bb90eb00 846 enable_dma(drv_data->dma_channel);
a5f6abd4 847
07612e5f
SZ		 848 /* start SPI transfer */
849 write_CTRL(drv_data,
850 (cr | CFG_SPI_DMAREAD | BIT_CTL_ENABLE));
851
a5f6abd4 852 } else if (drv_data->tx != NULL) {
88b40369 853 dev_dbg(&drv_data->pdev->dev, "doing DMA out.\n");
a5f6abd4
WB		 854
855 /* start dma */
bb90eb00 856 dma_enable_irq(drv_data->dma_channel);
a5f6abd4 857 dma_config = (RESTART | dma_width | DI_EN);
bb90eb00
BW		 858 set_dma_config(drv_data->dma_channel, dma_config);
859 set_dma_start_addr(drv_data->dma_channel,
a32c691d 860 (unsigned long)drv_data->tx);
bb90eb00 861 enable_dma(drv_data->dma_channel);
07612e5f
SZ		 862
863 /* start SPI transfer */
864 write_CTRL(drv_data,
865 (cr | CFG_SPI_DMAWRITE | BIT_CTL_ENABLE));
a5f6abd4
WB		 866 }
867 } else {
868 /* IO mode write then read */
88b40369 869 dev_dbg(&drv_data->pdev->dev, "doing IO transfer\n");
a5f6abd4 870
a5f6abd4
WB		 871 if (drv_data->tx != NULL && drv_data->rx != NULL) {
872 /* full duplex mode */
873 BUG_ON((drv_data->tx_end - drv_data->tx) !=
874 (drv_data->rx_end - drv_data->rx));
88b40369
BW		 875 dev_dbg(&drv_data->pdev->dev,
876 "IO duplex: cr is 0x%x\n", cr);
a5f6abd4 877
cc487e73 878 /* set SPI transfer mode */
bb90eb00 879 write_CTRL(drv_data, (cr | CFG_SPI_WRITE));
a5f6abd4
WB		 880
881 drv_data->duplex(drv_data);
882
883 if (drv_data->tx != drv_data->tx_end)
884 tranf_success = 0;
885 } else if (drv_data->tx != NULL) {
886 /* write only half duplex */
131b17d4 887 dev_dbg(&drv_data->pdev->dev,
88b40369 888 "IO write: cr is 0x%x\n", cr);
a5f6abd4 889
cc487e73 890 /* set SPI transfer mode */
bb90eb00 891 write_CTRL(drv_data, (cr | CFG_SPI_WRITE));
a5f6abd4
WB		 892
893 drv_data->write(drv_data);
894
895 if (drv_data->tx != drv_data->tx_end)
896 tranf_success = 0;
897 } else if (drv_data->rx != NULL) {
898 /* read only half duplex */
131b17d4 899 dev_dbg(&drv_data->pdev->dev,
88b40369 900 "IO read: cr is 0x%x\n", cr);
a5f6abd4 901
cc487e73 902 /* set SPI transfer mode */
bb90eb00 903 write_CTRL(drv_data, (cr | CFG_SPI_READ));
a5f6abd4
WB		 904
905 drv_data->read(drv_data);
906 if (drv_data->rx != drv_data->rx_end)
907 tranf_success = 0;
908 }
909
910 if (!tranf_success) {
131b17d4 911 dev_dbg(&drv_data->pdev->dev,
88b40369 912 "IO write error!\n");
a5f6abd4
WB		 913 message->state = ERROR_STATE;
914 } else {
915 /* Update total byte transfered */
916 message->actual_length += drv_data->len;
917
918 /* Move to next transfer of this msg */
919 message->state = next_transfer(drv_data);
920 }
921
922 /* Schedule next transfer tasklet */
923 tasklet_schedule(&drv_data->pump_transfers);
924
925 }
926}
927
928/* pop a msg from queue and kick off real transfer */
929static void pump_messages(struct work_struct *work)
930{
131b17d4 931 struct driver_data *drv_data;
a5f6abd4
WB		 932 unsigned long flags;
933
131b17d4
BW		 934 drv_data = container_of(work, struct driver_data, pump_messages);
935
a5f6abd4
WB		 936 /* Lock queue and check for queue work */
937 spin_lock_irqsave(&drv_data->lock, flags);
938 if (list_empty(&drv_data->queue) || drv_data->run == QUEUE_STOPPED) {
939 /* pumper kicked off but no work to do */
940 drv_data->busy = 0;
941 spin_unlock_irqrestore(&drv_data->lock, flags);
942 return;
943 }
944
945 /* Make sure we are not already running a message */
946 if (drv_data->cur_msg) {
947 spin_unlock_irqrestore(&drv_data->lock, flags);
948 return;
949 }
950
951 /* Extract head of queue */
952 drv_data->cur_msg = list_entry(drv_data->queue.next,
953 struct spi_message, queue);
5fec5b5a
BW		 954
955 /* Setup the SSP using the per chip configuration */
956 drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi);
8d20d0a7 957 restore_state(drv_data);
5fec5b5a 958
a5f6abd4
WB		 959 list_del_init(&drv_data->cur_msg->queue);
960
961 /* Initial message state */
962 drv_data->cur_msg->state = START_STATE;
963 drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next,
964 struct spi_transfer, transfer_list);
965
5fec5b5a
BW		 966 dev_dbg(&drv_data->pdev->dev, "got a message to pump, "
967 "state is set to: baud %d, flag 0x%x, ctl 0x%x\n",
968 drv_data->cur_chip->baud, drv_data->cur_chip->flag,
969 drv_data->cur_chip->ctl_reg);
131b17d4
BW		 970
971 dev_dbg(&drv_data->pdev->dev,
88b40369
BW		 972 "the first transfer len is %d\n",
973 drv_data->cur_transfer->len);
a5f6abd4
WB		 974
975 /* Mark as busy and launch transfers */
976 tasklet_schedule(&drv_data->pump_transfers);
977
978 drv_data->busy = 1;
979 spin_unlock_irqrestore(&drv_data->lock, flags);
980}
981
982/*
983 * got a msg to transfer, queue it in drv_data->queue.
984 * And kick off message pumper
985 */
986static int transfer(struct spi_device *spi, struct spi_message *msg)
987{
988 struct driver_data *drv_data = spi_master_get_devdata(spi->master);
989 unsigned long flags;
990
991 spin_lock_irqsave(&drv_data->lock, flags);
992
993 if (drv_data->run == QUEUE_STOPPED) {
994 spin_unlock_irqrestore(&drv_data->lock, flags);
995 return -ESHUTDOWN;
996 }
997
998 msg->actual_length = 0;
999 msg->status = -EINPROGRESS;
1000 msg->state = START_STATE;
1001
88b40369 1002 dev_dbg(&spi->dev, "adding an msg in transfer() \n");
a5f6abd4
WB		 1003 list_add_tail(&msg->queue, &drv_data->queue);
1004
1005 if (drv_data->run == QUEUE_RUNNING && !drv_data->busy)
1006 queue_work(drv_data->workqueue, &drv_data->pump_messages);
1007
1008 spin_unlock_irqrestore(&drv_data->lock, flags);
1009
1010 return 0;
1011}
1012
12e17c42
SZ		 1013#define MAX_SPI_SSEL 7
1014
1015static u16 ssel[3][MAX_SPI_SSEL] = {
1016 {P_SPI0_SSEL1, P_SPI0_SSEL2, P_SPI0_SSEL3,
1017 P_SPI0_SSEL4, P_SPI0_SSEL5,
1018 P_SPI0_SSEL6, P_SPI0_SSEL7},
1019
1020 {P_SPI1_SSEL1, P_SPI1_SSEL2, P_SPI1_SSEL3,
1021 P_SPI1_SSEL4, P_SPI1_SSEL5,
1022 P_SPI1_SSEL6, P_SPI1_SSEL7},
1023
1024 {P_SPI2_SSEL1, P_SPI2_SSEL2, P_SPI2_SSEL3,
1025 P_SPI2_SSEL4, P_SPI2_SSEL5,
1026 P_SPI2_SSEL6, P_SPI2_SSEL7},
1027};
1028
a5f6abd4
WB		 1029/* first setup for new devices */
1030static int setup(struct spi_device *spi)
1031{
1032 struct bfin5xx_spi_chip *chip_info = NULL;
1033 struct chip_data *chip;
1034 struct driver_data *drv_data = spi_master_get_devdata(spi->master);
1035 u8 spi_flg;
1036
1037 /* Abort device setup if requested features are not supported */
1038 if (spi->mode & ~(SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST)) {
1039 dev_err(&spi->dev, "requested mode not fully supported\n");
1040 return -EINVAL;
1041 }
1042
1043 /* Zero (the default) here means 8 bits */
1044 if (!spi->bits_per_word)
1045 spi->bits_per_word = 8;
1046
1047 if (spi->bits_per_word != 8 && spi->bits_per_word != 16)
1048 return -EINVAL;
1049
1050 /* Only alloc (or use chip_info) on first setup */
1051 chip = spi_get_ctldata(spi);
1052 if (chip == NULL) {
1053 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
1054 if (!chip)
1055 return -ENOMEM;
1056
1057 chip->enable_dma = 0;
1058 chip_info = spi->controller_data;
1059 }
1060
1061 /* chip_info isn't always needed */
1062 if (chip_info) {
2ed35516
MF		 1063 /* Make sure people stop trying to set fields via ctl_reg
1064 * when they should actually be using common SPI framework.
1065 * Currently we let through: WOM EMISO PSSE GM SZ TIMOD.
1066 * Not sure if a user actually needs/uses any of these,
1067 * but let's assume (for now) they do.
1068 */
1069 if (chip_info->ctl_reg & (SPE|MSTR|CPOL|CPHA|LSBF|SIZE)) {
1070 dev_err(&spi->dev, "do not set bits in ctl_reg "
1071 "that the SPI framework manages\n");
1072 return -EINVAL;
1073 }
1074
a5f6abd4
WB		 1075 chip->enable_dma = chip_info->enable_dma != 0
1076 && drv_data->master_info->enable_dma;
1077 chip->ctl_reg = chip_info->ctl_reg;
1078 chip->bits_per_word = chip_info->bits_per_word;
1079 chip->cs_change_per_word = chip_info->cs_change_per_word;
1080 chip->cs_chg_udelay = chip_info->cs_chg_udelay;
1081 }
1082
1083 /* translate common spi framework into our register */
1084 if (spi->mode & SPI_CPOL)
1085 chip->ctl_reg |= CPOL;
1086 if (spi->mode & SPI_CPHA)
1087 chip->ctl_reg |= CPHA;
1088 if (spi->mode & SPI_LSB_FIRST)
1089 chip->ctl_reg |= LSBF;
1090 /* we dont support running in slave mode (yet?) */
1091 chip->ctl_reg |= MSTR;
1092
1093 /*
1094 * if any one SPI chip is registered and wants DMA, request the
1095 * DMA channel for it
1096 */
bb90eb00 1097 if (chip->enable_dma && !drv_data->dma_requested) {
a5f6abd4 1098 /* register dma irq handler */
bb90eb00 1099 if (request_dma(drv_data->dma_channel, "BF53x_SPI_DMA") < 0) {
88b40369
BW		 1100 dev_dbg(&spi->dev,
1101 "Unable to request BlackFin SPI DMA channel\n");
a5f6abd4
WB		 1102 return -ENODEV;
1103 }
bb90eb00
BW		 1104 if (set_dma_callback(drv_data->dma_channel,
1105 (void *)dma_irq_handler, drv_data) < 0) {
88b40369 1106 dev_dbg(&spi->dev, "Unable to set dma callback\n");
a5f6abd4
WB		 1107 return -EPERM;
1108 }
bb90eb00
BW		 1109 dma_disable_irq(drv_data->dma_channel);
1110 drv_data->dma_requested = 1;
a5f6abd4
WB		 1111 }
1112
1113 /*
1114 * Notice: for blackfin, the speed_hz is the value of register
1115 * SPI_BAUD, not the real baudrate
1116 */
1117 chip->baud = hz_to_spi_baud(spi->max_speed_hz);
1118 spi_flg = ~(1 << (spi->chip_select));
1119 chip->flag = ((u16) spi_flg << 8) | (1 << (spi->chip_select));
1120 chip->chip_select_num = spi->chip_select;
1121
1122 switch (chip->bits_per_word) {
1123 case 8:
1124 chip->n_bytes = 1;
1125 chip->width = CFG_SPI_WORDSIZE8;
1126 chip->read = chip->cs_change_per_word ?
1127 u8_cs_chg_reader : u8_reader;
1128 chip->write = chip->cs_change_per_word ?
1129 u8_cs_chg_writer : u8_writer;
1130 chip->duplex = chip->cs_change_per_word ?
1131 u8_cs_chg_duplex : u8_duplex;
1132 break;
1133
1134 case 16:
1135 chip->n_bytes = 2;
1136 chip->width = CFG_SPI_WORDSIZE16;
1137 chip->read = chip->cs_change_per_word ?
1138 u16_cs_chg_reader : u16_reader;
1139 chip->write = chip->cs_change_per_word ?
1140 u16_cs_chg_writer : u16_writer;
1141 chip->duplex = chip->cs_change_per_word ?
1142 u16_cs_chg_duplex : u16_duplex;
1143 break;
1144
1145 default:
1146 dev_err(&spi->dev, "%d bits_per_word is not supported\n",
1147 chip->bits_per_word);
1148 kfree(chip);
1149 return -ENODEV;
1150 }
1151
898eb71c 1152 dev_dbg(&spi->dev, "setup spi chip %s, width is %d, dma is %d\n",
a5f6abd4 1153 spi->modalias, chip->width, chip->enable_dma);
88b40369 1154 dev_dbg(&spi->dev, "ctl_reg is 0x%x, flag_reg is 0x%x\n",
a5f6abd4
WB		 1155 chip->ctl_reg, chip->flag);
1156
1157 spi_set_ctldata(spi, chip);
1158
12e17c42
SZ		 1159 dev_dbg(&spi->dev, "chip select number is %d\n", chip->chip_select_num);
1160 if ((chip->chip_select_num > 0)
1161 && (chip->chip_select_num <= spi->master->num_chipselect))
1162 peripheral_request(ssel[spi->master->bus_num]
aab0d83e 1163 [chip->chip_select_num-1], spi->modalias);
12e17c42 1164
07612e5f
SZ		 1165 cs_deactive(drv_data, chip);
1166
a5f6abd4
WB		 1167 return 0;
1168}
1169
1170/*
1171 * callback for spi framework.
1172 * clean driver specific data
1173 */
88b40369 1174static void cleanup(struct spi_device *spi)
a5f6abd4 1175{
27bb9e79 1176 struct chip_data *chip = spi_get_ctldata(spi);
a5f6abd4 1177
12e17c42
SZ		 1178 if ((chip->chip_select_num > 0)
1179 && (chip->chip_select_num <= spi->master->num_chipselect))
1180 peripheral_free(ssel[spi->master->bus_num]
1181 [chip->chip_select_num-1]);
1182
a5f6abd4
WB		 1183 kfree(chip);
1184}
1185
1186static inline int init_queue(struct driver_data *drv_data)
1187{
1188 INIT_LIST_HEAD(&drv_data->queue);
1189 spin_lock_init(&drv_data->lock);
1190
1191 drv_data->run = QUEUE_STOPPED;
1192 drv_data->busy = 0;
1193
1194 /* init transfer tasklet */
1195 tasklet_init(&drv_data->pump_transfers,
1196 pump_transfers, (unsigned long)drv_data);
1197
1198 /* init messages workqueue */
1199 INIT_WORK(&drv_data->pump_messages, pump_messages);
1200 drv_data->workqueue =
49dce689 1201 create_singlethread_workqueue(drv_data->master->dev.parent->bus_id);
a5f6abd4
WB		 1202 if (drv_data->workqueue == NULL)
1203 return -EBUSY;
1204
1205 return 0;
1206}
1207
1208static inline int start_queue(struct driver_data *drv_data)
1209{
1210 unsigned long flags;
1211
1212 spin_lock_irqsave(&drv_data->lock, flags);
1213
1214 if (drv_data->run == QUEUE_RUNNING || drv_data->busy) {
1215 spin_unlock_irqrestore(&drv_data->lock, flags);
1216 return -EBUSY;
1217 }
1218
1219 drv_data->run = QUEUE_RUNNING;
1220 drv_data->cur_msg = NULL;
1221 drv_data->cur_transfer = NULL;
1222 drv_data->cur_chip = NULL;
1223 spin_unlock_irqrestore(&drv_data->lock, flags);
1224
1225 queue_work(drv_data->workqueue, &drv_data->pump_messages);
1226
1227 return 0;
1228}
1229
1230static inline int stop_queue(struct driver_data *drv_data)
1231{
1232 unsigned long flags;
1233 unsigned limit = 500;
1234 int status = 0;
1235
1236 spin_lock_irqsave(&drv_data->lock, flags);
1237
1238 /*
1239 * This is a bit lame, but is optimized for the common execution path.
1240 * A wait_queue on the drv_data->busy could be used, but then the common
1241 * execution path (pump_messages) would be required to call wake_up or
1242 * friends on every SPI message. Do this instead
1243 */
1244 drv_data->run = QUEUE_STOPPED;
1245 while (!list_empty(&drv_data->queue) && drv_data->busy && limit--) {
1246 spin_unlock_irqrestore(&drv_data->lock, flags);
1247 msleep(10);
1248 spin_lock_irqsave(&drv_data->lock, flags);
1249 }
1250
1251 if (!list_empty(&drv_data->queue) || drv_data->busy)
1252 status = -EBUSY;
1253
1254 spin_unlock_irqrestore(&drv_data->lock, flags);
1255
1256 return status;
1257}
1258
1259static inline int destroy_queue(struct driver_data *drv_data)
1260{
1261 int status;
1262
1263 status = stop_queue(drv_data);
1264 if (status != 0)
1265 return status;
1266
1267 destroy_workqueue(drv_data->workqueue);
1268
1269 return 0;
1270}
1271
1272static int __init bfin5xx_spi_probe(struct platform_device *pdev)
1273{
1274 struct device *dev = &pdev->dev;
1275 struct bfin5xx_spi_master *platform_info;
1276 struct spi_master *master;
1277 struct driver_data *drv_data = 0;
a32c691d 1278 struct resource *res;
a5f6abd4
WB		 1279 int status = 0;
1280
1281 platform_info = dev->platform_data;
1282
1283 /* Allocate master with space for drv_data */
1284 master = spi_alloc_master(dev, sizeof(struct driver_data) + 16);
1285 if (!master) {
1286 dev_err(&pdev->dev, "can not alloc spi_master\n");
1287 return -ENOMEM;
1288 }
131b17d4 1289
a5f6abd4
WB		 1290 drv_data = spi_master_get_devdata(master);
1291 drv_data->master = master;
1292 drv_data->master_info = platform_info;
1293 drv_data->pdev = pdev;
003d9226 1294 drv_data->pin_req = platform_info->pin_req;
a5f6abd4
WB		 1295
1296 master->bus_num = pdev->id;
1297 master->num_chipselect = platform_info->num_chipselect;
1298 master->cleanup = cleanup;
1299 master->setup = setup;
1300 master->transfer = transfer;
1301
a32c691d
BW		 1302 /* Find and map our resources */
1303 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1304 if (res == NULL) {
1305 dev_err(dev, "Cannot get IORESOURCE_MEM\n");
1306 status = -ENOENT;
1307 goto out_error_get_res;
1308 }
1309
f452126c
BW		 1310 drv_data->regs_base = ioremap(res->start, (res->end - res->start + 1));
1311 if (drv_data->regs_base == NULL) {
a32c691d
BW		 1312 dev_err(dev, "Cannot map IO\n");
1313 status = -ENXIO;
1314 goto out_error_ioremap;
1315 }
1316
bb90eb00
BW		 1317 drv_data->dma_channel = platform_get_irq(pdev, 0);
1318 if (drv_data->dma_channel < 0) {
a32c691d
BW		 1319 dev_err(dev, "No DMA channel specified\n");
1320 status = -ENOENT;
1321 goto out_error_no_dma_ch;
1322 }
1323
a5f6abd4
WB		 1324 /* Initial and start queue */
1325 status = init_queue(drv_data);
1326 if (status != 0) {
a32c691d 1327 dev_err(dev, "problem initializing queue\n");
a5f6abd4
WB		 1328 goto out_error_queue_alloc;
1329 }
a32c691d 1330
a5f6abd4
WB		 1331 status = start_queue(drv_data);
1332 if (status != 0) {
a32c691d 1333 dev_err(dev, "problem starting queue\n");
a5f6abd4
WB		 1334 goto out_error_queue_alloc;
1335 }
1336
1337 /* Register with the SPI framework */
1338 platform_set_drvdata(pdev, drv_data);
1339 status = spi_register_master(master);
1340 if (status != 0) {
a32c691d 1341 dev_err(dev, "problem registering spi master\n");
a5f6abd4
WB		 1342 goto out_error_queue_alloc;
1343 }
a32c691d 1344
003d9226
BW		 1345 status = peripheral_request_list(drv_data->pin_req, DRV_NAME);
1346 if (status != 0) {
7c4ef094
SZ		 1347 dev_err(&pdev->dev, ": Requesting Peripherals failed\n");
1348 goto out_error;
1349 }
1350
f452126c 1351 dev_info(dev, "%s, Version %s, regs_base@%p, dma channel@%d\n",
bb90eb00
BW		 1352 DRV_DESC, DRV_VERSION, drv_data->regs_base,
1353 drv_data->dma_channel);
a5f6abd4
WB		 1354 return status;
1355
cc2f81a6 1356out_error_queue_alloc:
a5f6abd4 1357 destroy_queue(drv_data);
a32c691d 1358out_error_no_dma_ch:
bb90eb00 1359 iounmap((void *) drv_data->regs_base);
a32c691d
BW		 1360out_error_ioremap:
1361out_error_get_res:
cc2f81a6 1362out_error:
a5f6abd4 1363 spi_master_put(master);
cc2f81a6 1364
a5f6abd4
WB		 1365 return status;
1366}
1367
1368/* stop hardware and remove the driver */
1369static int __devexit bfin5xx_spi_remove(struct platform_device *pdev)
1370{
1371 struct driver_data *drv_data = platform_get_drvdata(pdev);
1372 int status = 0;
1373
1374 if (!drv_data)
1375 return 0;
1376
1377 /* Remove the queue */
1378 status = destroy_queue(drv_data);
1379 if (status != 0)
1380 return status;
1381
1382 /* Disable the SSP at the peripheral and SOC level */
1383 bfin_spi_disable(drv_data);
1384
1385 /* Release DMA */
1386 if (drv_data->master_info->enable_dma) {
bb90eb00
BW		 1387 if (dma_channel_active(drv_data->dma_channel))
1388 free_dma(drv_data->dma_channel);
a5f6abd4
WB		 1389 }
1390
1391 /* Disconnect from the SPI framework */
1392 spi_unregister_master(drv_data->master);
1393
003d9226 1394 peripheral_free_list(drv_data->pin_req);
cc2f81a6 1395
a5f6abd4
WB		 1396 /* Prevent double remove */
1397 platform_set_drvdata(pdev, NULL);
1398
1399 return 0;
1400}
1401
1402#ifdef CONFIG_PM
1403static int bfin5xx_spi_suspend(struct platform_device *pdev, pm_message_t state)
1404{
1405 struct driver_data *drv_data = platform_get_drvdata(pdev);
1406 int status = 0;
1407
1408 status = stop_queue(drv_data);
1409 if (status != 0)
1410 return status;
1411
1412 /* stop hardware */
1413 bfin_spi_disable(drv_data);
1414
1415 return 0;
1416}
1417
1418static int bfin5xx_spi_resume(struct platform_device *pdev)
1419{
1420 struct driver_data *drv_data = platform_get_drvdata(pdev);
1421 int status = 0;
1422
1423 /* Enable the SPI interface */
1424 bfin_spi_enable(drv_data);
1425
1426 /* Start the queue running */
1427 status = start_queue(drv_data);
1428 if (status != 0) {
1429 dev_err(&pdev->dev, "problem starting queue (%d)\n", status);
1430 return status;
1431 }
1432
1433 return 0;
1434}
1435#else
1436#define bfin5xx_spi_suspend NULL
1437#define bfin5xx_spi_resume NULL
1438#endif /* CONFIG_PM */
1439
fc3ba952 1440MODULE_ALIAS("bfin-spi-master"); /* for platform bus hotplug */
a5f6abd4 1441static struct platform_driver bfin5xx_spi_driver = {
fc3ba952 1442 .driver = {
a32c691d 1443 .name = DRV_NAME,
88b40369
BW		 1444 .owner = THIS_MODULE,
1445 },
1446 .suspend = bfin5xx_spi_suspend,
1447 .resume = bfin5xx_spi_resume,
1448 .remove = __devexit_p(bfin5xx_spi_remove),
a5f6abd4
WB		 1449};
1450
1451static int __init bfin5xx_spi_init(void)
1452{
88b40369 1453 return platform_driver_probe(&bfin5xx_spi_driver, bfin5xx_spi_probe);
a5f6abd4 1454}
a5f6abd4
WB		 1455module_init(bfin5xx_spi_init);
1456
1457static void __exit bfin5xx_spi_exit(void)
1458{
1459 platform_driver_unregister(&bfin5xx_spi_driver);
1460}
a5f6abd4 1461module_exit(bfin5xx_spi_exit);
Linux 6.x block layer and io_uring tree(s)