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[linux-2.6-block.git] / drivers / spi / spi-zynqmp-gqspi.c
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dfe11a11
RW		 1/*
2 * Xilinx Zynq UltraScale+ MPSoC Quad-SPI (QSPI) controller driver
3 * (master mode only)
4 *
5 * Copyright (C) 2009 - 2015 Xilinx, Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published
9 * by the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 */
12
13#include <linux/clk.h>
14#include <linux/delay.h>
15#include <linux/dma-mapping.h>
16#include <linux/dmaengine.h>
17#include <linux/interrupt.h>
18#include <linux/io.h>
19#include <linux/module.h>
20#include <linux/of_irq.h>
21#include <linux/of_address.h>
22#include <linux/platform_device.h>
23#include <linux/spi/spi.h>
24#include <linux/spinlock.h>
25#include <linux/workqueue.h>
26
27/* Generic QSPI register offsets */
28#define GQSPI_CONFIG_OFST 0x00000100
29#define GQSPI_ISR_OFST 0x00000104
30#define GQSPI_IDR_OFST 0x0000010C
31#define GQSPI_IER_OFST 0x00000108
32#define GQSPI_IMASK_OFST 0x00000110
33#define GQSPI_EN_OFST 0x00000114
34#define GQSPI_TXD_OFST 0x0000011C
35#define GQSPI_RXD_OFST 0x00000120
36#define GQSPI_TX_THRESHOLD_OFST 0x00000128
37#define GQSPI_RX_THRESHOLD_OFST 0x0000012C
38#define GQSPI_LPBK_DLY_ADJ_OFST 0x00000138
39#define GQSPI_GEN_FIFO_OFST 0x00000140
40#define GQSPI_SEL_OFST 0x00000144
41#define GQSPI_GF_THRESHOLD_OFST 0x00000150
42#define GQSPI_FIFO_CTRL_OFST 0x0000014C
43#define GQSPI_QSPIDMA_DST_CTRL_OFST 0x0000080C
44#define GQSPI_QSPIDMA_DST_SIZE_OFST 0x00000804
45#define GQSPI_QSPIDMA_DST_STS_OFST 0x00000808
46#define GQSPI_QSPIDMA_DST_I_STS_OFST 0x00000814
47#define GQSPI_QSPIDMA_DST_I_EN_OFST 0x00000818
48#define GQSPI_QSPIDMA_DST_I_DIS_OFST 0x0000081C
49#define GQSPI_QSPIDMA_DST_I_MASK_OFST 0x00000820
50#define GQSPI_QSPIDMA_DST_ADDR_OFST 0x00000800
51#define GQSPI_QSPIDMA_DST_ADDR_MSB_OFST 0x00000828
52
53/* GQSPI register bit masks */
54#define GQSPI_SEL_MASK 0x00000001
55#define GQSPI_EN_MASK 0x00000001
56#define GQSPI_LPBK_DLY_ADJ_USE_LPBK_MASK 0x00000020
57#define GQSPI_ISR_WR_TO_CLR_MASK 0x00000002
58#define GQSPI_IDR_ALL_MASK 0x00000FBE
59#define GQSPI_CFG_MODE_EN_MASK 0xC0000000
60#define GQSPI_CFG_GEN_FIFO_START_MODE_MASK 0x20000000
61#define GQSPI_CFG_ENDIAN_MASK 0x04000000
62#define GQSPI_CFG_EN_POLL_TO_MASK 0x00100000
63#define GQSPI_CFG_WP_HOLD_MASK 0x00080000
64#define GQSPI_CFG_BAUD_RATE_DIV_MASK 0x00000038
65#define GQSPI_CFG_CLK_PHA_MASK 0x00000004
66#define GQSPI_CFG_CLK_POL_MASK 0x00000002
67#define GQSPI_CFG_START_GEN_FIFO_MASK 0x10000000
68#define GQSPI_GENFIFO_IMM_DATA_MASK 0x000000FF
69#define GQSPI_GENFIFO_DATA_XFER 0x00000100
70#define GQSPI_GENFIFO_EXP 0x00000200
71#define GQSPI_GENFIFO_MODE_SPI 0x00000400
72#define GQSPI_GENFIFO_MODE_DUALSPI 0x00000800
73#define GQSPI_GENFIFO_MODE_QUADSPI 0x00000C00
74#define GQSPI_GENFIFO_MODE_MASK 0x00000C00
75#define GQSPI_GENFIFO_CS_LOWER 0x00001000
76#define GQSPI_GENFIFO_CS_UPPER 0x00002000
77#define GQSPI_GENFIFO_BUS_LOWER 0x00004000
78#define GQSPI_GENFIFO_BUS_UPPER 0x00008000
79#define GQSPI_GENFIFO_BUS_BOTH 0x0000C000
80#define GQSPI_GENFIFO_BUS_MASK 0x0000C000
81#define GQSPI_GENFIFO_TX 0x00010000
82#define GQSPI_GENFIFO_RX 0x00020000
83#define GQSPI_GENFIFO_STRIPE 0x00040000
84#define GQSPI_GENFIFO_POLL 0x00080000
85#define GQSPI_GENFIFO_EXP_START 0x00000100
86#define GQSPI_FIFO_CTRL_RST_RX_FIFO_MASK 0x00000004
87#define GQSPI_FIFO_CTRL_RST_TX_FIFO_MASK 0x00000002
88#define GQSPI_FIFO_CTRL_RST_GEN_FIFO_MASK 0x00000001
89#define GQSPI_ISR_RXEMPTY_MASK 0x00000800
90#define GQSPI_ISR_GENFIFOFULL_MASK 0x00000400
91#define GQSPI_ISR_GENFIFONOT_FULL_MASK 0x00000200
92#define GQSPI_ISR_TXEMPTY_MASK 0x00000100
93#define GQSPI_ISR_GENFIFOEMPTY_MASK 0x00000080
94#define GQSPI_ISR_RXFULL_MASK 0x00000020
95#define GQSPI_ISR_RXNEMPTY_MASK 0x00000010
96#define GQSPI_ISR_TXFULL_MASK 0x00000008
97#define GQSPI_ISR_TXNOT_FULL_MASK 0x00000004
98#define GQSPI_ISR_POLL_TIME_EXPIRE_MASK 0x00000002
99#define GQSPI_IER_TXNOT_FULL_MASK 0x00000004
100#define GQSPI_IER_RXEMPTY_MASK 0x00000800
101#define GQSPI_IER_POLL_TIME_EXPIRE_MASK 0x00000002
102#define GQSPI_IER_RXNEMPTY_MASK 0x00000010
103#define GQSPI_IER_GENFIFOEMPTY_MASK 0x00000080
104#define GQSPI_IER_TXEMPTY_MASK 0x00000100
105#define GQSPI_QSPIDMA_DST_INTR_ALL_MASK 0x000000FE
106#define GQSPI_QSPIDMA_DST_STS_WTC 0x0000E000
107#define GQSPI_CFG_MODE_EN_DMA_MASK 0x80000000
108#define GQSPI_ISR_IDR_MASK 0x00000994
109#define GQSPI_QSPIDMA_DST_I_EN_DONE_MASK 0x00000002
110#define GQSPI_QSPIDMA_DST_I_STS_DONE_MASK 0x00000002
111#define GQSPI_IRQ_MASK 0x00000980
112
113#define GQSPI_CFG_BAUD_RATE_DIV_SHIFT 3
114#define GQSPI_GENFIFO_CS_SETUP 0x4
115#define GQSPI_GENFIFO_CS_HOLD 0x3
116#define GQSPI_TXD_DEPTH 64
117#define GQSPI_RX_FIFO_THRESHOLD 32
118#define GQSPI_RX_FIFO_FILL (GQSPI_RX_FIFO_THRESHOLD * 4)
119#define GQSPI_TX_FIFO_THRESHOLD_RESET_VAL 32
120#define GQSPI_TX_FIFO_FILL (GQSPI_TXD_DEPTH -\
121 GQSPI_TX_FIFO_THRESHOLD_RESET_VAL)
122#define GQSPI_GEN_FIFO_THRESHOLD_RESET_VAL 0X10
123#define GQSPI_QSPIDMA_DST_CTRL_RESET_VAL 0x803FFA00
124#define GQSPI_SELECT_FLASH_CS_LOWER 0x1
125#define GQSPI_SELECT_FLASH_CS_UPPER 0x2
126#define GQSPI_SELECT_FLASH_CS_BOTH 0x3
127#define GQSPI_SELECT_FLASH_BUS_LOWER 0x1
128#define GQSPI_SELECT_FLASH_BUS_UPPER 0x2
129#define GQSPI_SELECT_FLASH_BUS_BOTH 0x3
130#define GQSPI_BAUD_DIV_MAX 7 /* Baud rate divisor maximum */
131#define GQSPI_BAUD_DIV_SHIFT 2 /* Baud rate divisor shift */
132#define GQSPI_SELECT_MODE_SPI 0x1
133#define GQSPI_SELECT_MODE_DUALSPI 0x2
134#define GQSPI_SELECT_MODE_QUADSPI 0x4
135#define GQSPI_DMA_UNALIGN 0x3
136#define GQSPI_DEFAULT_NUM_CS 1 /* Default number of chip selects */
137
138enum mode_type {GQSPI_MODE_IO, GQSPI_MODE_DMA};
139
140/**
141 * struct zynqmp_qspi - Defines qspi driver instance
142 * @regs: Virtual address of the QSPI controller registers
143 * @refclk: Pointer to the peripheral clock
144 * @pclk: Pointer to the APB clock
145 * @irq: IRQ number
146 * @dev: Pointer to struct device
147 * @txbuf: Pointer to the TX buffer
148 * @rxbuf: Pointer to the RX buffer
149 * @bytes_to_transfer: Number of bytes left to transfer
150 * @bytes_to_receive: Number of bytes left to receive
151 * @genfifocs: Used for chip select
152 * @genfifobus: Used to select the upper or lower bus
153 * @dma_rx_bytes: Remaining bytes to receive by DMA mode
154 * @dma_addr: DMA address after mapping the kernel buffer
155 * @genfifoentry: Used for storing the genfifoentry instruction.
156 * @mode: Defines the mode in which QSPI is operating
157 */
158struct zynqmp_qspi {
159 void __iomem *regs;
160 struct clk *refclk;
161 struct clk *pclk;
162 int irq;
163 struct device *dev;
164 const void *txbuf;
165 void *rxbuf;
166 int bytes_to_transfer;
167 int bytes_to_receive;
168 u32 genfifocs;
169 u32 genfifobus;
170 u32 dma_rx_bytes;
171 dma_addr_t dma_addr;
172 u32 genfifoentry;
173 enum mode_type mode;
174};
175
176/**
177 * zynqmp_gqspi_read: For GQSPI controller read operation
178 * @xqspi: Pointer to the zynqmp_qspi structure
179 * @offset: Offset from where to read
180 */
181static u32 zynqmp_gqspi_read(struct zynqmp_qspi *xqspi, u32 offset)
182{
183 return readl_relaxed(xqspi->regs + offset);
184}
185
186/**
187 * zynqmp_gqspi_write: For GQSPI controller write operation
188 * @xqspi: Pointer to the zynqmp_qspi structure
189 * @offset: Offset where to write
190 * @val: Value to be written
191 */
192static inline void zynqmp_gqspi_write(struct zynqmp_qspi *xqspi, u32 offset,
193 u32 val)
194{
195 writel_relaxed(val, (xqspi->regs + offset));
196}
197
198/**
199 * zynqmp_gqspi_selectslave: For selection of slave device
200 * @instanceptr: Pointer to the zynqmp_qspi structure
201 * @flashcs: For chip select
202 * @flashbus: To check which bus is selected- upper or lower
203 */
204static void zynqmp_gqspi_selectslave(struct zynqmp_qspi *instanceptr,
205 u8 slavecs, u8 slavebus)
206{
207 /*
208 * Bus and CS lines selected here will be updated in the instance and
209 * used for subsequent GENFIFO entries during transfer.
210 */
211
212 /* Choose slave select line */
213 switch (slavecs) {
214 case GQSPI_SELECT_FLASH_CS_BOTH:
215 instanceptr->genfifocs = GQSPI_GENFIFO_CS_LOWER |
216 GQSPI_GENFIFO_CS_UPPER;
217 case GQSPI_SELECT_FLASH_CS_UPPER:
218 instanceptr->genfifocs = GQSPI_GENFIFO_CS_UPPER;
219 break;
220 case GQSPI_SELECT_FLASH_CS_LOWER:
221 instanceptr->genfifocs = GQSPI_GENFIFO_CS_LOWER;
222 break;
223 default:
224 dev_warn(instanceptr->dev, "Invalid slave select\n");
225 }
226
227 /* Choose the bus */
228 switch (slavebus) {
229 case GQSPI_SELECT_FLASH_BUS_BOTH:
230 instanceptr->genfifobus = GQSPI_GENFIFO_BUS_LOWER |
231 GQSPI_GENFIFO_BUS_UPPER;
232 break;
233 case GQSPI_SELECT_FLASH_BUS_UPPER:
234 instanceptr->genfifobus = GQSPI_GENFIFO_BUS_UPPER;
235 break;
236 case GQSPI_SELECT_FLASH_BUS_LOWER:
237 instanceptr->genfifobus = GQSPI_GENFIFO_BUS_LOWER;
238 break;
239 default:
240 dev_warn(instanceptr->dev, "Invalid slave bus\n");
241 }
242}
243
244/**
245 * zynqmp_qspi_init_hw: Initialize the hardware
246 * @xqspi: Pointer to the zynqmp_qspi structure
247 *
248 * The default settings of the QSPI controller's configurable parameters on
249 * reset are
250 * - Master mode
251 * - TX threshold set to 1
252 * - RX threshold set to 1
253 * - Flash memory interface mode enabled
254 * This function performs the following actions
255 * - Disable and clear all the interrupts
256 * - Enable manual slave select
257 * - Enable manual start
258 * - Deselect all the chip select lines
259 * - Set the little endian mode of TX FIFO and
260 * - Enable the QSPI controller
261 */
262static void zynqmp_qspi_init_hw(struct zynqmp_qspi *xqspi)
263{
264 u32 config_reg;
265
266 /* Select the GQSPI mode */
267 zynqmp_gqspi_write(xqspi, GQSPI_SEL_OFST, GQSPI_SEL_MASK);
268 /* Clear and disable interrupts */
269 zynqmp_gqspi_write(xqspi, GQSPI_ISR_OFST,
270 zynqmp_gqspi_read(xqspi, GQSPI_ISR_OFST) |
271 GQSPI_ISR_WR_TO_CLR_MASK);
272 /* Clear the DMA STS */
273 zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_I_STS_OFST,
274 zynqmp_gqspi_read(xqspi,
275 GQSPI_QSPIDMA_DST_I_STS_OFST));
276 zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_STS_OFST,
277 zynqmp_gqspi_read(xqspi,
278 GQSPI_QSPIDMA_DST_STS_OFST) |
279 GQSPI_QSPIDMA_DST_STS_WTC);
280 zynqmp_gqspi_write(xqspi, GQSPI_IDR_OFST, GQSPI_IDR_ALL_MASK);
281 zynqmp_gqspi_write(xqspi,
282 GQSPI_QSPIDMA_DST_I_DIS_OFST,
283 GQSPI_QSPIDMA_DST_INTR_ALL_MASK);
284 /* Disable the GQSPI */
285 zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, 0x0);
286 config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);
287 config_reg &= ~GQSPI_CFG_MODE_EN_MASK;
288 /* Manual start */
289 config_reg |= GQSPI_CFG_GEN_FIFO_START_MODE_MASK;
290 /* Little endian by default */
291 config_reg &= ~GQSPI_CFG_ENDIAN_MASK;
292 /* Disable poll time out */
293 config_reg &= ~GQSPI_CFG_EN_POLL_TO_MASK;
294 /* Set hold bit */
295 config_reg |= GQSPI_CFG_WP_HOLD_MASK;
296 /* Clear pre-scalar by default */
297 config_reg &= ~GQSPI_CFG_BAUD_RATE_DIV_MASK;
298 /* CPHA 0 */
299 config_reg &= ~GQSPI_CFG_CLK_PHA_MASK;
300 /* CPOL 0 */
301 config_reg &= ~GQSPI_CFG_CLK_POL_MASK;
302 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);
303
304 /* Clear the TX and RX FIFO */
305 zynqmp_gqspi_write(xqspi, GQSPI_FIFO_CTRL_OFST,
306 GQSPI_FIFO_CTRL_RST_RX_FIFO_MASK |
307 GQSPI_FIFO_CTRL_RST_TX_FIFO_MASK |
308 GQSPI_FIFO_CTRL_RST_GEN_FIFO_MASK);
309 /* Set by default to allow for high frequencies */
310 zynqmp_gqspi_write(xqspi, GQSPI_LPBK_DLY_ADJ_OFST,
311 zynqmp_gqspi_read(xqspi, GQSPI_LPBK_DLY_ADJ_OFST) |
312 GQSPI_LPBK_DLY_ADJ_USE_LPBK_MASK);
313 /* Reset thresholds */
314 zynqmp_gqspi_write(xqspi, GQSPI_TX_THRESHOLD_OFST,
315 GQSPI_TX_FIFO_THRESHOLD_RESET_VAL);
316 zynqmp_gqspi_write(xqspi, GQSPI_RX_THRESHOLD_OFST,
317 GQSPI_RX_FIFO_THRESHOLD);
318 zynqmp_gqspi_write(xqspi, GQSPI_GF_THRESHOLD_OFST,
319 GQSPI_GEN_FIFO_THRESHOLD_RESET_VAL);
320 zynqmp_gqspi_selectslave(xqspi,
321 GQSPI_SELECT_FLASH_CS_LOWER,
322 GQSPI_SELECT_FLASH_BUS_LOWER);
323 /* Initialize DMA */
324 zynqmp_gqspi_write(xqspi,
325 GQSPI_QSPIDMA_DST_CTRL_OFST,
326 GQSPI_QSPIDMA_DST_CTRL_RESET_VAL);
327
328 /* Enable the GQSPI */
329 zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, GQSPI_EN_MASK);
330}
331
332/**
333 * zynqmp_qspi_copy_read_data: Copy data to RX buffer
334 * @xqspi: Pointer to the zynqmp_qspi structure
335 * @data: The variable where data is stored
336 * @size: Number of bytes to be copied from data to RX buffer
337 */
338static void zynqmp_qspi_copy_read_data(struct zynqmp_qspi *xqspi,
339 ulong data, u8 size)
340{
341 memcpy(xqspi->rxbuf, &data, size);
342 xqspi->rxbuf += size;
343 xqspi->bytes_to_receive -= size;
344}
345
346/**
347 * zynqmp_prepare_transfer_hardware: Prepares hardware for transfer.
348 * @master: Pointer to the spi_master structure which provides
349 * information about the controller.
350 *
351 * This function enables SPI master controller.
352 *
353 * Return: 0 on success; error value otherwise
354 */
355static int zynqmp_prepare_transfer_hardware(struct spi_master *master)
356{
357 struct zynqmp_qspi *xqspi = spi_master_get_devdata(master);
358 int ret;
359
360 ret = clk_enable(xqspi->refclk);
361 if (ret)
362 goto clk_err;
363
364 ret = clk_enable(xqspi->pclk);
365 if (ret)
366 goto clk_err;
367
368 zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, GQSPI_EN_MASK);
369 return 0;
370clk_err:
371 return ret;
372}
373
374/**
375 * zynqmp_unprepare_transfer_hardware: Relaxes hardware after transfer
376 * @master: Pointer to the spi_master structure which provides
377 * information about the controller.
378 *
379 * This function disables the SPI master controller.
380 *
381 * Return: Always 0
382 */
383static int zynqmp_unprepare_transfer_hardware(struct spi_master *master)
384{
385 struct zynqmp_qspi *xqspi = spi_master_get_devdata(master);
386
387 zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, 0x0);
388 clk_disable(xqspi->refclk);
389 clk_disable(xqspi->pclk);
390 return 0;
391}
392
393/**
394 * zynqmp_qspi_chipselect: Select or deselect the chip select line
395 * @qspi: Pointer to the spi_device structure
396 * @is_high: Select(0) or deselect (1) the chip select line
397 */
398static void zynqmp_qspi_chipselect(struct spi_device *qspi, bool is_high)
399{
400 struct zynqmp_qspi *xqspi = spi_master_get_devdata(qspi->master);
401 ulong timeout;
402 u32 genfifoentry = 0x0, statusreg;
403
404 genfifoentry |= GQSPI_GENFIFO_MODE_SPI;
405 genfifoentry |= xqspi->genfifobus;
406
407 if (!is_high) {
408 genfifoentry |= xqspi->genfifocs;
409 genfifoentry |= GQSPI_GENFIFO_CS_SETUP;
410 } else {
411 genfifoentry |= GQSPI_GENFIFO_CS_HOLD;
412 }
413
414 zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, genfifoentry);
415
416 /* Dummy generic FIFO entry */
417 zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, 0x0);
418
419 /* Manually start the generic FIFO command */
420 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,
421 zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST) |
422 GQSPI_CFG_START_GEN_FIFO_MASK);
423
424 timeout = jiffies + msecs_to_jiffies(1000);
425
426 /* Wait until the generic FIFO command is empty */
427 do {
428 statusreg = zynqmp_gqspi_read(xqspi, GQSPI_ISR_OFST);
429
430 if ((statusreg & GQSPI_ISR_GENFIFOEMPTY_MASK) &&
431 (statusreg & GQSPI_ISR_TXEMPTY_MASK))
432 break;
433 else
434 cpu_relax();
435 } while (!time_after_eq(jiffies, timeout));
436
437 if (time_after_eq(jiffies, timeout))
438 dev_err(xqspi->dev, "Chip select timed out\n");
439}
440
441/**
442 * zynqmp_qspi_setup_transfer: Configure QSPI controller for specified
443 * transfer
444 * @qspi: Pointer to the spi_device structure
445 * @transfer: Pointer to the spi_transfer structure which provides
446 * information about next transfer setup parameters
447 *
448 * Sets the operational mode of QSPI controller for the next QSPI transfer and
449 * sets the requested clock frequency.
450 *
451 * Return: Always 0
452 *
453 * Note:
454 * If the requested frequency is not an exact match with what can be
455 * obtained using the pre-scalar value, the driver sets the clock
456 * frequency which is lower than the requested frequency (maximum lower)
457 * for the transfer.
458 *
459 * If the requested frequency is higher or lower than that is supported
460 * by the QSPI controller the driver will set the highest or lowest
461 * frequency supported by controller.
462 */
463static int zynqmp_qspi_setup_transfer(struct spi_device *qspi,
464 struct spi_transfer *transfer)
465{
466 struct zynqmp_qspi *xqspi = spi_master_get_devdata(qspi->master);
467 ulong clk_rate;
468 u32 config_reg, req_hz, baud_rate_val = 0;
469
470 if (transfer)
471 req_hz = transfer->speed_hz;
472 else
473 req_hz = qspi->max_speed_hz;
474
475 /* Set the clock frequency */
476 /* If req_hz == 0, default to lowest speed */
477 clk_rate = clk_get_rate(xqspi->refclk);
478
479 while ((baud_rate_val < GQSPI_BAUD_DIV_MAX) &&
480 (clk_rate /
481 (GQSPI_BAUD_DIV_SHIFT << baud_rate_val)) > req_hz)
482 baud_rate_val++;
483
484 config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);
485
486 /* Set the QSPI clock phase and clock polarity */
487 config_reg &= (~GQSPI_CFG_CLK_PHA_MASK) & (~GQSPI_CFG_CLK_POL_MASK);
488
489 if (qspi->mode & SPI_CPHA)
490 config_reg |= GQSPI_CFG_CLK_PHA_MASK;
491 if (qspi->mode & SPI_CPOL)
492 config_reg |= GQSPI_CFG_CLK_POL_MASK;
493
494 config_reg &= ~GQSPI_CFG_BAUD_RATE_DIV_MASK;
495 config_reg |= (baud_rate_val << GQSPI_CFG_BAUD_RATE_DIV_SHIFT);
496 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);
497 return 0;
498}
499
500/**
501 * zynqmp_qspi_setup: Configure the QSPI controller
502 * @qspi: Pointer to the spi_device structure
503 *
504 * Sets the operational mode of QSPI controller for the next QSPI transfer,
505 * baud rate and divisor value to setup the requested qspi clock.
506 *
507 * Return: 0 on success; error value otherwise.
508 */
509static int zynqmp_qspi_setup(struct spi_device *qspi)
510{
511 if (qspi->master->busy)
512 return -EBUSY;
513 return 0;
514}
515
516/**
517 * zynqmp_qspi_filltxfifo: Fills the TX FIFO as long as there is room in
518 * the FIFO or the bytes required to be
519 * transmitted.
520 * @xqspi: Pointer to the zynqmp_qspi structure
521 * @size: Number of bytes to be copied from TX buffer to TX FIFO
522 */
523static void zynqmp_qspi_filltxfifo(struct zynqmp_qspi *xqspi, int size)
524{
525 u32 count = 0, intermediate;
526
527 while ((xqspi->bytes_to_transfer > 0) && (count < size)) {
528 memcpy(&intermediate, xqspi->txbuf, 4);
529 zynqmp_gqspi_write(xqspi, GQSPI_TXD_OFST, intermediate);
530
531 if (xqspi->bytes_to_transfer >= 4) {
532 xqspi->txbuf += 4;
533 xqspi->bytes_to_transfer -= 4;
534 } else {
535 xqspi->txbuf += xqspi->bytes_to_transfer;
536 xqspi->bytes_to_transfer = 0;
537 }
538 count++;
539 }
540}
541
542/**
543 * zynqmp_qspi_readrxfifo: Fills the RX FIFO as long as there is room in
544 * the FIFO.
545 * @xqspi: Pointer to the zynqmp_qspi structure
546 * @size: Number of bytes to be copied from RX buffer to RX FIFO
547 */
548static void zynqmp_qspi_readrxfifo(struct zynqmp_qspi *xqspi, u32 size)
549{
550 ulong data;
551 int count = 0;
552
553 while ((count < size) && (xqspi->bytes_to_receive > 0)) {
554 if (xqspi->bytes_to_receive >= 4) {
555 (*(u32 *) xqspi->rxbuf) =
556 zynqmp_gqspi_read(xqspi, GQSPI_RXD_OFST);
557 xqspi->rxbuf += 4;
558 xqspi->bytes_to_receive -= 4;
559 count += 4;
560 } else {
561 data = zynqmp_gqspi_read(xqspi, GQSPI_RXD_OFST);
562 count += xqspi->bytes_to_receive;
563 zynqmp_qspi_copy_read_data(xqspi, data,
564 xqspi->bytes_to_receive);
565 xqspi->bytes_to_receive = 0;
566 }
567 }
568}
569
570/**
571 * zynqmp_process_dma_irq: Handler for DMA done interrupt of QSPI
572 * controller
573 * @xqspi: zynqmp_qspi instance pointer
574 *
575 * This function handles DMA interrupt only.
576 */
577static void zynqmp_process_dma_irq(struct zynqmp_qspi *xqspi)
578{
579 u32 config_reg, genfifoentry;
580
581 dma_unmap_single(xqspi->dev, xqspi->dma_addr,
582 xqspi->dma_rx_bytes, DMA_FROM_DEVICE);
583 xqspi->rxbuf += xqspi->dma_rx_bytes;
584 xqspi->bytes_to_receive -= xqspi->dma_rx_bytes;
585 xqspi->dma_rx_bytes = 0;
586
587 /* Disabling the DMA interrupts */
588 zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_I_DIS_OFST,
589 GQSPI_QSPIDMA_DST_I_EN_DONE_MASK);
590
591 if (xqspi->bytes_to_receive > 0) {
592 /* Switch to IO mode,for remaining bytes to receive */
593 config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);
594 config_reg &= ~GQSPI_CFG_MODE_EN_MASK;
595 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);
596
597 /* Initiate the transfer of remaining bytes */
598 genfifoentry = xqspi->genfifoentry;
599 genfifoentry |= xqspi->bytes_to_receive;
600 zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, genfifoentry);
601
602 /* Dummy generic FIFO entry */
603 zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, 0x0);
604
605 /* Manual start */
606 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,
607 (zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST) |
608 GQSPI_CFG_START_GEN_FIFO_MASK));
609
610 /* Enable the RX interrupts for IO mode */
611 zynqmp_gqspi_write(xqspi, GQSPI_IER_OFST,
612 GQSPI_IER_GENFIFOEMPTY_MASK |
613 GQSPI_IER_RXNEMPTY_MASK |
614 GQSPI_IER_RXEMPTY_MASK);
615 }
616}
617
618/**
619 * zynqmp_qspi_irq: Interrupt service routine of the QSPI controller
620 * @irq: IRQ number
621 * @dev_id: Pointer to the xqspi structure
622 *
623 * This function handles TX empty only.
624 * On TX empty interrupt this function reads the received data from RX FIFO
625 * and fills the TX FIFO if there is any data remaining to be transferred.
626 *
627 * Return: IRQ_HANDLED when interrupt is handled
628 * IRQ_NONE otherwise.
629 */
630static irqreturn_t zynqmp_qspi_irq(int irq, void *dev_id)
631{
632 struct spi_master *master = dev_id;
633 struct zynqmp_qspi *xqspi = spi_master_get_devdata(master);
634 int ret = IRQ_NONE;
635 u32 status, mask, dma_status = 0;
636
637 status = zynqmp_gqspi_read(xqspi, GQSPI_ISR_OFST);
638 zynqmp_gqspi_write(xqspi, GQSPI_ISR_OFST, status);
639 mask = (status & ~(zynqmp_gqspi_read(xqspi, GQSPI_IMASK_OFST)));
640
641 /* Read and clear DMA status */
642 if (xqspi->mode == GQSPI_MODE_DMA) {
643 dma_status =
644 zynqmp_gqspi_read(xqspi, GQSPI_QSPIDMA_DST_I_STS_OFST);
645 zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_I_STS_OFST,
646 dma_status);
647 }
648
649 if (mask & GQSPI_ISR_TXNOT_FULL_MASK) {
650 zynqmp_qspi_filltxfifo(xqspi, GQSPI_TX_FIFO_FILL);
651 ret = IRQ_HANDLED;
652 }
653
654 if (dma_status & GQSPI_QSPIDMA_DST_I_STS_DONE_MASK) {
655 zynqmp_process_dma_irq(xqspi);
656 ret = IRQ_HANDLED;
657 } else if (!(mask & GQSPI_IER_RXEMPTY_MASK) &&
658 (mask & GQSPI_IER_GENFIFOEMPTY_MASK)) {
659 zynqmp_qspi_readrxfifo(xqspi, GQSPI_RX_FIFO_FILL);
660 ret = IRQ_HANDLED;
661 }
662
663 if ((xqspi->bytes_to_receive == 0) && (xqspi->bytes_to_transfer == 0)
664 && ((status & GQSPI_IRQ_MASK) == GQSPI_IRQ_MASK)) {
665 zynqmp_gqspi_write(xqspi, GQSPI_IDR_OFST, GQSPI_ISR_IDR_MASK);
666 spi_finalize_current_transfer(master);
667 ret = IRQ_HANDLED;
668 }
669 return ret;
670}
671
672/**
673 * zynqmp_qspi_selectspimode: Selects SPI mode - x1 or x2 or x4.
674 * @xqspi: xqspi is a pointer to the GQSPI instance
675 * @spimode: spimode - SPI or DUAL or QUAD.
676 * Return: Mask to set desired SPI mode in GENFIFO entry.
677 */
678static inline u32 zynqmp_qspi_selectspimode(struct zynqmp_qspi *xqspi,
679 u8 spimode)
680{
681 u32 mask = 0;
682
683 switch (spimode) {
684 case GQSPI_SELECT_MODE_DUALSPI:
685 mask = GQSPI_GENFIFO_MODE_DUALSPI;
686 break;
687 case GQSPI_SELECT_MODE_QUADSPI:
688 mask = GQSPI_GENFIFO_MODE_QUADSPI;
689 break;
690 case GQSPI_SELECT_MODE_SPI:
691 mask = GQSPI_GENFIFO_MODE_SPI;
692 break;
693 default:
694 dev_warn(xqspi->dev, "Invalid SPI mode\n");
695 }
696
697 return mask;
698}
699
700/**
701 * zynq_qspi_setuprxdma: This function sets up the RX DMA operation
702 * @xqspi: xqspi is a pointer to the GQSPI instance.
703 */
704static void zynq_qspi_setuprxdma(struct zynqmp_qspi *xqspi)
705{
706 u32 rx_bytes, rx_rem, config_reg;
707 dma_addr_t addr;
708 u64 dma_align = (u64)(uintptr_t)xqspi->rxbuf;
709
710 if ((xqspi->bytes_to_receive < 8) ||
711 ((dma_align & GQSPI_DMA_UNALIGN) != 0x0)) {
712 /* Setting to IO mode */
713 config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);
714 config_reg &= ~GQSPI_CFG_MODE_EN_MASK;
715 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);
716 xqspi->mode = GQSPI_MODE_IO;
717 xqspi->dma_rx_bytes = 0;
718 return;
719 }
720
721 rx_rem = xqspi->bytes_to_receive % 4;
722 rx_bytes = (xqspi->bytes_to_receive - rx_rem);
723
724 addr = dma_map_single(xqspi->dev, (void *)xqspi->rxbuf,
725 rx_bytes, DMA_FROM_DEVICE);
726 if (dma_mapping_error(xqspi->dev, addr))
727 dev_err(xqspi->dev, "ERR:rxdma:memory not mapped\n");
728
729 xqspi->dma_rx_bytes = rx_bytes;
730 xqspi->dma_addr = addr;
731 zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_ADDR_OFST,
732 (u32)(addr & 0xffffffff));
733 addr = ((addr >> 16) >> 16);
734 zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_ADDR_MSB_OFST,
735 ((u32)addr) & 0xfff);
736
737 /* Enabling the DMA mode */
738 config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);
739 config_reg &= ~GQSPI_CFG_MODE_EN_MASK;
740 config_reg |= GQSPI_CFG_MODE_EN_DMA_MASK;
741 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);
742
743 /* Switch to DMA mode */
744 xqspi->mode = GQSPI_MODE_DMA;
745
746 /* Write the number of bytes to transfer */
747 zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_SIZE_OFST, rx_bytes);
748}
749
750/**
751 * zynqmp_qspi_txrxsetup: This function checks the TX/RX buffers in
752 * the transfer and sets up the GENFIFO entries,
753 * TX FIFO as required.
754 * @xqspi: xqspi is a pointer to the GQSPI instance.
755 * @transfer: It is a pointer to the structure containing transfer data.
756 * @genfifoentry: genfifoentry is pointer to the variable in which
757 * GENFIFO mask is returned to calling function
758 */
759static void zynqmp_qspi_txrxsetup(struct zynqmp_qspi *xqspi,
760 struct spi_transfer *transfer,
761 u32 *genfifoentry)
762{
763 u32 config_reg;
764
765 /* Transmit */
766 if ((xqspi->txbuf != NULL) && (xqspi->rxbuf == NULL)) {
767 /* Setup data to be TXed */
768 *genfifoentry &= ~GQSPI_GENFIFO_RX;
769 *genfifoentry |= GQSPI_GENFIFO_DATA_XFER;
770 *genfifoentry |= GQSPI_GENFIFO_TX;
771 *genfifoentry |=
772 zynqmp_qspi_selectspimode(xqspi, transfer->tx_nbits);
773 xqspi->bytes_to_transfer = transfer->len;
774 if (xqspi->mode == GQSPI_MODE_DMA) {
775 config_reg = zynqmp_gqspi_read(xqspi,
776 GQSPI_CONFIG_OFST);
777 config_reg &= ~GQSPI_CFG_MODE_EN_MASK;
778 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,
779 config_reg);
780 xqspi->mode = GQSPI_MODE_IO;
781 }
782 zynqmp_qspi_filltxfifo(xqspi, GQSPI_TXD_DEPTH);
783 /* Discard RX data */
784 xqspi->bytes_to_receive = 0;
785 } else if ((xqspi->txbuf == NULL) && (xqspi->rxbuf != NULL)) {
786 /* Receive */
787
788 /* TX auto fill */
789 *genfifoentry &= ~GQSPI_GENFIFO_TX;
790 /* Setup RX */
791 *genfifoentry |= GQSPI_GENFIFO_DATA_XFER;
792 *genfifoentry |= GQSPI_GENFIFO_RX;
793 *genfifoentry |=
794 zynqmp_qspi_selectspimode(xqspi, transfer->rx_nbits);
795 xqspi->bytes_to_transfer = 0;
796 xqspi->bytes_to_receive = transfer->len;
797 zynq_qspi_setuprxdma(xqspi);
798 }
799}
800
801/**
802 * zynqmp_qspi_start_transfer: Initiates the QSPI transfer
803 * @master: Pointer to the spi_master structure which provides
804 * information about the controller.
805 * @qspi: Pointer to the spi_device structure
806 * @transfer: Pointer to the spi_transfer structure which provide information
807 * about next transfer parameters
808 *
809 * This function fills the TX FIFO, starts the QSPI transfer, and waits for the
810 * transfer to be completed.
811 *
812 * Return: Number of bytes transferred in the last transfer
813 */
814static int zynqmp_qspi_start_transfer(struct spi_master *master,
815 struct spi_device *qspi,
816 struct spi_transfer *transfer)
817{
818 struct zynqmp_qspi *xqspi = spi_master_get_devdata(master);
819 u32 genfifoentry = 0x0, transfer_len;
820
821 xqspi->txbuf = transfer->tx_buf;
822 xqspi->rxbuf = transfer->rx_buf;
823
824 zynqmp_qspi_setup_transfer(qspi, transfer);
825
826 genfifoentry |= xqspi->genfifocs;
827 genfifoentry |= xqspi->genfifobus;
828
829 zynqmp_qspi_txrxsetup(xqspi, transfer, &genfifoentry);
830
831 if (xqspi->mode == GQSPI_MODE_DMA)
832 transfer_len = xqspi->dma_rx_bytes;
833 else
834 transfer_len = transfer->len;
835
836 xqspi->genfifoentry = genfifoentry;
837 if ((transfer_len) < GQSPI_GENFIFO_IMM_DATA_MASK) {
838 genfifoentry &= ~GQSPI_GENFIFO_IMM_DATA_MASK;
839 genfifoentry |= transfer_len;
840 zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, genfifoentry);
841 } else {
842 int tempcount = transfer_len;
843 u32 exponent = 8; /* 2^8 = 256 */
844 u8 imm_data = tempcount & 0xFF;
845
846 tempcount &= ~(tempcount & 0xFF);
847 /* Immediate entry */
848 if (tempcount != 0) {
849 /* Exponent entries */
850 genfifoentry |= GQSPI_GENFIFO_EXP;
851 while (tempcount != 0) {
852 if (tempcount & GQSPI_GENFIFO_EXP_START) {
853 genfifoentry &=
854 ~GQSPI_GENFIFO_IMM_DATA_MASK;
855 genfifoentry |= exponent;
856 zynqmp_gqspi_write(xqspi,
857 GQSPI_GEN_FIFO_OFST,
858 genfifoentry);
859 }
860 tempcount = tempcount >> 1;
861 exponent++;
862 }
863 }
864 if (imm_data != 0) {
865 genfifoentry &= ~GQSPI_GENFIFO_EXP;
866 genfifoentry &= ~GQSPI_GENFIFO_IMM_DATA_MASK;
867 genfifoentry |= (u8) (imm_data & 0xFF);
868 zynqmp_gqspi_write(xqspi,
869 GQSPI_GEN_FIFO_OFST, genfifoentry);
870 }
871 }
872
873 if ((xqspi->mode == GQSPI_MODE_IO) &&
874 (xqspi->rxbuf != NULL)) {
875 /* Dummy generic FIFO entry */
876 zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, 0x0);
877 }
878
879 /* Since we are using manual mode */
880 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,
881 zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST) |
882 GQSPI_CFG_START_GEN_FIFO_MASK);
883
884 if (xqspi->txbuf != NULL)
885 /* Enable interrupts for TX */
886 zynqmp_gqspi_write(xqspi, GQSPI_IER_OFST,
887 GQSPI_IER_TXEMPTY_MASK |
888 GQSPI_IER_GENFIFOEMPTY_MASK |
889 GQSPI_IER_TXNOT_FULL_MASK);
890
891 if (xqspi->rxbuf != NULL) {
892 /* Enable interrupts for RX */
893 if (xqspi->mode == GQSPI_MODE_DMA) {
894 /* Enable DMA interrupts */
895 zynqmp_gqspi_write(xqspi,
896 GQSPI_QSPIDMA_DST_I_EN_OFST,
897 GQSPI_QSPIDMA_DST_I_EN_DONE_MASK);
898 } else {
899 zynqmp_gqspi_write(xqspi, GQSPI_IER_OFST,
900 GQSPI_IER_GENFIFOEMPTY_MASK |
901 GQSPI_IER_RXNEMPTY_MASK |
902 GQSPI_IER_RXEMPTY_MASK);
903 }
904 }
905
906 return transfer->len;
907}
908
909/**
910 * zynqmp_qspi_suspend: Suspend method for the QSPI driver
911 * @_dev: Address of the platform_device structure
912 *
913 * This function stops the QSPI driver queue and disables the QSPI controller
914 *
915 * Return: Always 0
916 */
917static int __maybe_unused zynqmp_qspi_suspend(struct device *dev)
918{
919 struct platform_device *pdev = container_of(dev,
920 struct platform_device,
921 dev);
922 struct spi_master *master = platform_get_drvdata(pdev);
923
924 spi_master_suspend(master);
925
926 zynqmp_unprepare_transfer_hardware(master);
927
928 return 0;
929}
930
931/**
932 * zynqmp_qspi_resume: Resume method for the QSPI driver
933 * @dev: Address of the platform_device structure
934 *
935 * The function starts the QSPI driver queue and initializes the QSPI
936 * controller
937 *
938 * Return: 0 on success; error value otherwise
939 */
940static int __maybe_unused zynqmp_qspi_resume(struct device *dev)
941{
942 struct platform_device *pdev = container_of(dev,
943 struct platform_device,
944 dev);
945 struct spi_master *master = platform_get_drvdata(pdev);
946 struct zynqmp_qspi *xqspi = spi_master_get_devdata(master);
947 int ret = 0;
948
949 ret = clk_enable(xqspi->pclk);
950 if (ret) {
951 dev_err(dev, "Cannot enable APB clock.\n");
952 return ret;
953 }
954
955 ret = clk_enable(xqspi->refclk);
956 if (ret) {
957 dev_err(dev, "Cannot enable device clock.\n");
958 clk_disable(xqspi->pclk);
959 return ret;
960 }
961
962 spi_master_resume(master);
963
964 return 0;
965}
966
967static SIMPLE_DEV_PM_OPS(zynqmp_qspi_dev_pm_ops, zynqmp_qspi_suspend,
968 zynqmp_qspi_resume);
969
970/**
971 * zynqmp_qspi_probe: Probe method for the QSPI driver
972 * @pdev: Pointer to the platform_device structure
973 *
974 * This function initializes the driver data structures and the hardware.
975 *
976 * Return: 0 on success; error value otherwise
977 */
978static int zynqmp_qspi_probe(struct platform_device *pdev)
979{
980 int ret = 0;
981 struct spi_master *master;
982 struct zynqmp_qspi *xqspi;
983 struct resource *res;
984 struct device *dev = &pdev->dev;
985
986 master = spi_alloc_master(&pdev->dev, sizeof(*xqspi));
987 if (!master)
988 return -ENOMEM;
989
990 xqspi = spi_master_get_devdata(master);
991 master->dev.of_node = pdev->dev.of_node;
992 platform_set_drvdata(pdev, master);
993
994 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
995 xqspi->regs = devm_ioremap_resource(&pdev->dev, res);
996 if (IS_ERR(xqspi->regs)) {
997 ret = PTR_ERR(xqspi->regs);
998 goto remove_master;
999 }
1000
1001 xqspi->dev = dev;
1002 xqspi->pclk = devm_clk_get(&pdev->dev, "pclk");
1003 if (IS_ERR(xqspi->pclk)) {
1004 dev_err(dev, "pclk clock not found.\n");
1005 ret = PTR_ERR(xqspi->pclk);
1006 goto remove_master;
1007 }
1008
1009 ret = clk_prepare_enable(xqspi->pclk);
1010 if (ret) {
1011 dev_err(dev, "Unable to enable APB clock.\n");
1012 goto remove_master;
1013 }
1014
1015 xqspi->refclk = devm_clk_get(&pdev->dev, "ref_clk");
1016 if (IS_ERR(xqspi->refclk)) {
1017 dev_err(dev, "ref_clk clock not found.\n");
1018 ret = PTR_ERR(xqspi->refclk);
1019 goto clk_dis_pclk;
1020 }
1021
1022 ret = clk_prepare_enable(xqspi->refclk);
1023 if (ret) {
1024 dev_err(dev, "Unable to enable device clock.\n");
1025 goto clk_dis_pclk;
1026 }
1027
1028 /* QSPI controller initializations */
1029 zynqmp_qspi_init_hw(xqspi);
1030
1031 xqspi->irq = platform_get_irq(pdev, 0);
1032 if (xqspi->irq <= 0) {
1033 ret = -ENXIO;
1034 dev_err(dev, "irq resource not found\n");
1035 goto clk_dis_all;
1036 }
1037 ret = devm_request_irq(&pdev->dev, xqspi->irq, zynqmp_qspi_irq,
1038 0, pdev->name, master);
1039 if (ret != 0) {
1040 ret = -ENXIO;
1041 dev_err(dev, "request_irq failed\n");
1042 goto clk_dis_all;
1043 }
1044
1045 master->num_chipselect = GQSPI_DEFAULT_NUM_CS;
1046
1047 master->setup = zynqmp_qspi_setup;
1048 master->set_cs = zynqmp_qspi_chipselect;
1049 master->transfer_one = zynqmp_qspi_start_transfer;
1050 master->prepare_transfer_hardware = zynqmp_prepare_transfer_hardware;
1051 master->unprepare_transfer_hardware =
1052 zynqmp_unprepare_transfer_hardware;
1053 master->max_speed_hz = clk_get_rate(xqspi->refclk) / 2;
1054 master->bits_per_word_mask = SPI_BPW_MASK(8);
1055 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_RX_DUAL | SPI_RX_QUAD |
1056 SPI_TX_DUAL | SPI_TX_QUAD;
1057
1058 if (master->dev.parent == NULL)
1059 master->dev.parent = &master->dev;
1060
1061 ret = spi_register_master(master);
1062 if (ret)
1063 goto clk_dis_all;
1064
1065 return 0;
1066
1067clk_dis_all:
1068 clk_disable_unprepare(xqspi->refclk);
1069clk_dis_pclk:
1070 clk_disable_unprepare(xqspi->pclk);
1071remove_master:
1072 spi_master_put(master);
1073
1074 return ret;
1075}
1076
1077/**
1078 * zynqmp_qspi_remove: Remove method for the QSPI driver
1079 * @pdev: Pointer to the platform_device structure
1080 *
1081 * This function is called if a device is physically removed from the system or
1082 * if the driver module is being unloaded. It frees all resources allocated to
1083 * the device.
1084 *
1085 * Return: 0 Always
1086 */
1087static int zynqmp_qspi_remove(struct platform_device *pdev)
1088{
1089 struct spi_master *master = platform_get_drvdata(pdev);
1090 struct zynqmp_qspi *xqspi = spi_master_get_devdata(master);
1091
1092 zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, 0x0);
1093 clk_disable_unprepare(xqspi->refclk);
1094 clk_disable_unprepare(xqspi->pclk);
1095
1096 spi_unregister_master(master);
1097
1098 return 0;
1099}
1100
1101static const struct of_device_id zynqmp_qspi_of_match[] = {
1102 { .compatible = "xlnx,zynqmp-qspi-1.0", },
1103 { /* End of table */ }
1104};
1105
1106MODULE_DEVICE_TABLE(of, zynqmp_qspi_of_match);
1107
1108static struct platform_driver zynqmp_qspi_driver = {
1109 .probe = zynqmp_qspi_probe,
1110 .remove = zynqmp_qspi_remove,
1111 .driver = {
1112 .name = "zynqmp-qspi",
1113 .of_match_table = zynqmp_qspi_of_match,
1114 .pm = &zynqmp_qspi_dev_pm_ops,
1115 },
1116};
1117
1118module_platform_driver(zynqmp_qspi_driver);
1119
1120MODULE_AUTHOR("Xilinx, Inc.");
1121MODULE_DESCRIPTION("Xilinx Zynqmp QSPI driver");
1122MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)