[linux-2.6-block.git] / drivers / spi / spi-ti-qspi.c

/*
 * TI QSPI driver
 *
 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
 * Author: Sourav Poddar <sourav.poddar@ti.com>
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GPLv2.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/device.h>
#include <linux/delay.h>
#include <linux/dma-mapping.h>
#include <linux/dmaengine.h>
#include <linux/omap-dma.h>
#include <linux/platform_device.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/slab.h>
#include <linux/pm_runtime.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/pinctrl/consumer.h>
#include <linux/mfd/syscon.h>
#include <linux/regmap.h>

#include <linux/spi/spi.h>

struct ti_qspi_regs {
	u32 clkctrl;
};

struct ti_qspi {
	/* list synchronization */
	struct mutex            list_lock;

	struct spi_master	*master;
	void __iomem            *base;
	void __iomem            *mmap_base;
	struct regmap		*ctrl_base;
	unsigned int		ctrl_reg;
	struct clk		*fclk;
	struct device           *dev;

	struct ti_qspi_regs     ctx_reg;

	u32 spi_max_frequency;
	u32 cmd;
	u32 dc;

	bool mmap_enabled;
};

#define QSPI_PID			(0x0)
#define QSPI_SYSCONFIG			(0x10)
#define QSPI_SPI_CLOCK_CNTRL_REG	(0x40)
#define QSPI_SPI_DC_REG			(0x44)
#define QSPI_SPI_CMD_REG		(0x48)
#define QSPI_SPI_STATUS_REG		(0x4c)
#define QSPI_SPI_DATA_REG		(0x50)
#define QSPI_SPI_SETUP_REG(n)		((0x54 + 4 * n))
#define QSPI_SPI_SWITCH_REG		(0x64)
#define QSPI_SPI_DATA_REG_1		(0x68)
#define QSPI_SPI_DATA_REG_2		(0x6c)
#define QSPI_SPI_DATA_REG_3		(0x70)

#define QSPI_COMPLETION_TIMEOUT		msecs_to_jiffies(2000)

#define QSPI_FCLK			192000000

/* Clock Control */
#define QSPI_CLK_EN			(1 << 31)
#define QSPI_CLK_DIV_MAX		0xffff

/* Command */
#define QSPI_EN_CS(n)			(n << 28)
#define QSPI_WLEN(n)			((n - 1) << 19)
#define QSPI_3_PIN			(1 << 18)
#define QSPI_RD_SNGL			(1 << 16)
#define QSPI_WR_SNGL			(2 << 16)
#define QSPI_RD_DUAL			(3 << 16)
#define QSPI_RD_QUAD			(7 << 16)
#define QSPI_INVAL			(4 << 16)
#define QSPI_FLEN(n)			((n - 1) << 0)
#define QSPI_WLEN_MAX_BITS		128
#define QSPI_WLEN_MAX_BYTES		16

/* STATUS REGISTER */
#define BUSY				0x01
#define WC				0x02

/* Device Control */
#define QSPI_DD(m, n)			(m << (3 + n * 8))
#define QSPI_CKPHA(n)			(1 << (2 + n * 8))
#define QSPI_CSPOL(n)			(1 << (1 + n * 8))
#define QSPI_CKPOL(n)			(1 << (n * 8))

#define	QSPI_FRAME			4096

#define QSPI_AUTOSUSPEND_TIMEOUT         2000

#define MEM_CS_EN(n)			((n + 1) << 8)
#define MEM_CS_MASK			(7 << 8)

#define MM_SWITCH			0x1

#define QSPI_SETUP_RD_NORMAL		(0x0 << 12)
#define QSPI_SETUP_RD_DUAL		(0x1 << 12)
#define QSPI_SETUP_RD_QUAD		(0x3 << 12)
#define QSPI_SETUP_ADDR_SHIFT		8
#define QSPI_SETUP_DUMMY_SHIFT		10

static inline unsigned long ti_qspi_read(struct ti_qspi *qspi,
		unsigned long reg)
{
	return readl(qspi->base + reg);
}

static inline void ti_qspi_write(struct ti_qspi *qspi,
		unsigned long val, unsigned long reg)
{
	writel(val, qspi->base + reg);
}

static int ti_qspi_setup(struct spi_device *spi)
{
	struct ti_qspi	*qspi = spi_master_get_devdata(spi->master);
	struct ti_qspi_regs *ctx_reg = &qspi->ctx_reg;
	int clk_div = 0, ret;
	u32 clk_ctrl_reg, clk_rate, clk_mask;

	if (spi->master->busy) {
		dev_dbg(qspi->dev, "master busy doing other trasnfers\n");
		return -EBUSY;
	}

	if (!qspi->spi_max_frequency) {
		dev_err(qspi->dev, "spi max frequency not defined\n");
		return -EINVAL;
	}

	clk_rate = clk_get_rate(qspi->fclk);

	clk_div = DIV_ROUND_UP(clk_rate, qspi->spi_max_frequency) - 1;

	if (clk_div < 0) {
		dev_dbg(qspi->dev, "clock divider < 0, using /1 divider\n");
		return -EINVAL;
	}

	if (clk_div > QSPI_CLK_DIV_MAX) {
		dev_dbg(qspi->dev, "clock divider >%d , using /%d divider\n",
				QSPI_CLK_DIV_MAX, QSPI_CLK_DIV_MAX + 1);
		return -EINVAL;
	}

	dev_dbg(qspi->dev, "hz: %d, clock divider %d\n",
			qspi->spi_max_frequency, clk_div);

	ret = pm_runtime_get_sync(qspi->dev);
	if (ret < 0) {
		dev_err(qspi->dev, "pm_runtime_get_sync() failed\n");
		return ret;
	}

	clk_ctrl_reg = ti_qspi_read(qspi, QSPI_SPI_CLOCK_CNTRL_REG);

	clk_ctrl_reg &= ~QSPI_CLK_EN;

	/* disable SCLK */
	ti_qspi_write(qspi, clk_ctrl_reg, QSPI_SPI_CLOCK_CNTRL_REG);

	/* enable SCLK */
	clk_mask = QSPI_CLK_EN | clk_div;
	ti_qspi_write(qspi, clk_mask, QSPI_SPI_CLOCK_CNTRL_REG);
	ctx_reg->clkctrl = clk_mask;

	pm_runtime_mark_last_busy(qspi->dev);
	ret = pm_runtime_put_autosuspend(qspi->dev);
	if (ret < 0) {
		dev_err(qspi->dev, "pm_runtime_put_autosuspend() failed\n");
		return ret;
	}

	return 0;
}

static void ti_qspi_restore_ctx(struct ti_qspi *qspi)
{
	struct ti_qspi_regs *ctx_reg = &qspi->ctx_reg;

	ti_qspi_write(qspi, ctx_reg->clkctrl, QSPI_SPI_CLOCK_CNTRL_REG);
}

static inline u32 qspi_is_busy(struct ti_qspi *qspi)
{
	u32 stat;
	unsigned long timeout = jiffies + QSPI_COMPLETION_TIMEOUT;

	stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG);
	while ((stat & BUSY) && time_after(timeout, jiffies)) {
		cpu_relax();
		stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG);
	}

	WARN(stat & BUSY, "qspi busy\n");
	return stat & BUSY;
}

static inline int ti_qspi_poll_wc(struct ti_qspi *qspi)
{
	u32 stat;
	unsigned long timeout = jiffies + QSPI_COMPLETION_TIMEOUT;

	do {
		stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG);
		if (stat & WC)
			return 0;
		cpu_relax();
	} while (time_after(timeout, jiffies));

	stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG);
	if (stat & WC)
		return 0;
	return  -ETIMEDOUT;
}

static int qspi_write_msg(struct ti_qspi *qspi, struct spi_transfer *t)
{
	int wlen, count, xfer_len;
	unsigned int cmd;
	const u8 *txbuf;
	u32 data;

	txbuf = t->tx_buf;
	cmd = qspi->cmd | QSPI_WR_SNGL;
	count = t->len;
	wlen = t->bits_per_word >> 3;	/* in bytes */
	xfer_len = wlen;

	while (count) {
		if (qspi_is_busy(qspi))
			return -EBUSY;

		switch (wlen) {
		case 1:
			dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %02x\n",
					cmd, qspi->dc, *txbuf);
			if (count >= QSPI_WLEN_MAX_BYTES) {
				u32 *txp = (u32 *)txbuf;

				data = cpu_to_be32(*txp++);
				writel(data, qspi->base +
				       QSPI_SPI_DATA_REG_3);
				data = cpu_to_be32(*txp++);
				writel(data, qspi->base +
				       QSPI_SPI_DATA_REG_2);
				data = cpu_to_be32(*txp++);
				writel(data, qspi->base +
				       QSPI_SPI_DATA_REG_1);
				data = cpu_to_be32(*txp++);
				writel(data, qspi->base +
				       QSPI_SPI_DATA_REG);
				xfer_len = QSPI_WLEN_MAX_BYTES;
				cmd |= QSPI_WLEN(QSPI_WLEN_MAX_BITS);
			} else {
				writeb(*txbuf, qspi->base + QSPI_SPI_DATA_REG);
				cmd = qspi->cmd | QSPI_WR_SNGL;
				xfer_len = wlen;
				cmd |= QSPI_WLEN(wlen);
			}
			break;
		case 2:
			dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %04x\n",
					cmd, qspi->dc, *txbuf);
			writew(*((u16 *)txbuf), qspi->base + QSPI_SPI_DATA_REG);
			break;
		case 4:
			dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %08x\n",
					cmd, qspi->dc, *txbuf);
			writel(*((u32 *)txbuf), qspi->base + QSPI_SPI_DATA_REG);
			break;
		}

		ti_qspi_write(qspi, cmd, QSPI_SPI_CMD_REG);
		if (ti_qspi_poll_wc(qspi)) {
			dev_err(qspi->dev, "write timed out\n");
			return -ETIMEDOUT;
		}
		txbuf += xfer_len;
		count -= xfer_len;
	}

	return 0;
}

static int qspi_read_msg(struct ti_qspi *qspi, struct spi_transfer *t)
{
	int wlen, count;
	unsigned int cmd;
	u8 *rxbuf;

	rxbuf = t->rx_buf;
	cmd = qspi->cmd;
	switch (t->rx_nbits) {
	case SPI_NBITS_DUAL:
		cmd |= QSPI_RD_DUAL;
		break;
	case SPI_NBITS_QUAD:
		cmd |= QSPI_RD_QUAD;
		break;
	default:
		cmd |= QSPI_RD_SNGL;
		break;
	}
	count = t->len;
	wlen = t->bits_per_word >> 3;	/* in bytes */

	while (count) {
		dev_dbg(qspi->dev, "rx cmd %08x dc %08x\n", cmd, qspi->dc);
		if (qspi_is_busy(qspi))
			return -EBUSY;

		ti_qspi_write(qspi, cmd, QSPI_SPI_CMD_REG);
		if (ti_qspi_poll_wc(qspi)) {
			dev_err(qspi->dev, "read timed out\n");
			return -ETIMEDOUT;
		}
		switch (wlen) {
		case 1:
			*rxbuf = readb(qspi->base + QSPI_SPI_DATA_REG);
			break;
		case 2:
			*((u16 *)rxbuf) = readw(qspi->base + QSPI_SPI_DATA_REG);
			break;
		case 4:
			*((u32 *)rxbuf) = readl(qspi->base + QSPI_SPI_DATA_REG);
			break;
		}
		rxbuf += wlen;
		count -= wlen;
	}

	return 0;
}

static int qspi_transfer_msg(struct ti_qspi *qspi, struct spi_transfer *t)
{
	int ret;

	if (t->tx_buf) {
		ret = qspi_write_msg(qspi, t);
		if (ret) {
			dev_dbg(qspi->dev, "Error while writing\n");
			return ret;
		}
	}

	if (t->rx_buf) {
		ret = qspi_read_msg(qspi, t);
		if (ret) {
			dev_dbg(qspi->dev, "Error while reading\n");
			return ret;
		}
	}

	return 0;
}

static void ti_qspi_enable_memory_map(struct spi_device *spi)
{
	struct ti_qspi  *qspi = spi_master_get_devdata(spi->master);

	ti_qspi_write(qspi, MM_SWITCH, QSPI_SPI_SWITCH_REG);
	if (qspi->ctrl_base) {
		regmap_update_bits(qspi->ctrl_base, qspi->ctrl_reg,
				   MEM_CS_EN(spi->chip_select),
				   MEM_CS_MASK);
	}
	qspi->mmap_enabled = true;
}

static void ti_qspi_disable_memory_map(struct spi_device *spi)
{
	struct ti_qspi  *qspi = spi_master_get_devdata(spi->master);

	ti_qspi_write(qspi, 0, QSPI_SPI_SWITCH_REG);
	if (qspi->ctrl_base)
		regmap_update_bits(qspi->ctrl_base, qspi->ctrl_reg,
				   0, MEM_CS_MASK);
	qspi->mmap_enabled = false;
}

static void ti_qspi_setup_mmap_read(struct spi_device *spi,
				    struct spi_flash_read_message *msg)
{
	struct ti_qspi  *qspi = spi_master_get_devdata(spi->master);
	u32 memval = msg->read_opcode;

	switch (msg->data_nbits) {
	case SPI_NBITS_QUAD:
		memval |= QSPI_SETUP_RD_QUAD;
		break;
	case SPI_NBITS_DUAL:
		memval |= QSPI_SETUP_RD_DUAL;
		break;
	default:
		memval |= QSPI_SETUP_RD_NORMAL;
		break;
	}
	memval |= ((msg->addr_width - 1) << QSPI_SETUP_ADDR_SHIFT |
		   msg->dummy_bytes << QSPI_SETUP_DUMMY_SHIFT);
	ti_qspi_write(qspi, memval,
		      QSPI_SPI_SETUP_REG(spi->chip_select));
}

static int ti_qspi_spi_flash_read(struct  spi_device *spi,
				  struct spi_flash_read_message *msg)
{
	struct ti_qspi *qspi = spi_master_get_devdata(spi->master);
	int ret = 0;

	mutex_lock(&qspi->list_lock);

	if (!qspi->mmap_enabled)
		ti_qspi_enable_memory_map(spi);
	ti_qspi_setup_mmap_read(spi, msg);
	memcpy_fromio(msg->buf, qspi->mmap_base + msg->from, msg->len);
	msg->retlen = msg->len;

	mutex_unlock(&qspi->list_lock);

	return ret;
}

static int ti_qspi_start_transfer_one(struct spi_master *master,
		struct spi_message *m)
{
	struct ti_qspi *qspi = spi_master_get_devdata(master);
	struct spi_device *spi = m->spi;
	struct spi_transfer *t;
	int status = 0, ret;
	int frame_length;

	/* setup device control reg */
	qspi->dc = 0;

	if (spi->mode & SPI_CPHA)
		qspi->dc |= QSPI_CKPHA(spi->chip_select);
	if (spi->mode & SPI_CPOL)
		qspi->dc |= QSPI_CKPOL(spi->chip_select);
	if (spi->mode & SPI_CS_HIGH)
		qspi->dc |= QSPI_CSPOL(spi->chip_select);

	frame_length = (m->frame_length << 3) / spi->bits_per_word;

	frame_length = clamp(frame_length, 0, QSPI_FRAME);

	/* setup command reg */
	qspi->cmd = 0;
	qspi->cmd |= QSPI_EN_CS(spi->chip_select);
	qspi->cmd |= QSPI_FLEN(frame_length);

	ti_qspi_write(qspi, qspi->dc, QSPI_SPI_DC_REG);

	mutex_lock(&qspi->list_lock);

	if (qspi->mmap_enabled)
		ti_qspi_disable_memory_map(spi);

	list_for_each_entry(t, &m->transfers, transfer_list) {
		qspi->cmd |= QSPI_WLEN(t->bits_per_word);

		ret = qspi_transfer_msg(qspi, t);
		if (ret) {
			dev_dbg(qspi->dev, "transfer message failed\n");
			mutex_unlock(&qspi->list_lock);
			return -EINVAL;
		}

		m->actual_length += t->len;
	}

	mutex_unlock(&qspi->list_lock);

	ti_qspi_write(qspi, qspi->cmd | QSPI_INVAL, QSPI_SPI_CMD_REG);
	m->status = status;
	spi_finalize_current_message(master);

	return status;
}

static int ti_qspi_runtime_resume(struct device *dev)
{
	struct ti_qspi      *qspi;

	qspi = dev_get_drvdata(dev);
	ti_qspi_restore_ctx(qspi);

	return 0;
}

static const struct of_device_id ti_qspi_match[] = {
	{.compatible = "ti,dra7xxx-qspi" },
	{.compatible = "ti,am4372-qspi" },
	{},
};
MODULE_DEVICE_TABLE(of, ti_qspi_match);

static int ti_qspi_probe(struct platform_device *pdev)
{
	struct  ti_qspi *qspi;
	struct spi_master *master;
	struct resource         *r, *res_mmap;
	struct device_node *np = pdev->dev.of_node;
	u32 max_freq;
	int ret = 0, num_cs, irq;

	master = spi_alloc_master(&pdev->dev, sizeof(*qspi));
	if (!master)
		return -ENOMEM;

	master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_RX_DUAL | SPI_RX_QUAD;

	master->flags = SPI_MASTER_HALF_DUPLEX;
	master->setup = ti_qspi_setup;
	master->auto_runtime_pm = true;
	master->transfer_one_message = ti_qspi_start_transfer_one;
	master->dev.of_node = pdev->dev.of_node;
	master->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(16) |
				     SPI_BPW_MASK(8);

	if (!of_property_read_u32(np, "num-cs", &num_cs))
		master->num_chipselect = num_cs;

	qspi = spi_master_get_devdata(master);
	qspi->master = master;
	qspi->dev = &pdev->dev;
	platform_set_drvdata(pdev, qspi);

	r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi_base");
	if (r == NULL) {
		r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
		if (r == NULL) {
			dev_err(&pdev->dev, "missing platform data\n");
			return -ENODEV;
		}
	}

	res_mmap = platform_get_resource_byname(pdev,
			IORESOURCE_MEM, "qspi_mmap");
	if (res_mmap == NULL) {
		res_mmap = platform_get_resource(pdev, IORESOURCE_MEM, 1);
		if (res_mmap == NULL) {
			dev_err(&pdev->dev,
				"memory mapped resource not required\n");
		}
	}

	irq = platform_get_irq(pdev, 0);
	if (irq < 0) {
		dev_err(&pdev->dev, "no irq resource?\n");
		return irq;
	}

	mutex_init(&qspi->list_lock);

	qspi->base = devm_ioremap_resource(&pdev->dev, r);
	if (IS_ERR(qspi->base)) {
		ret = PTR_ERR(qspi->base);
		goto free_master;
	}

	if (res_mmap) {
		qspi->mmap_base = devm_ioremap_resource(&pdev->dev,
							res_mmap);
		master->spi_flash_read = ti_qspi_spi_flash_read;
		if (IS_ERR(qspi->mmap_base)) {
			dev_err(&pdev->dev,
				"falling back to PIO mode\n");
			master->spi_flash_read = NULL;
		}
	}
	qspi->mmap_enabled = false;

	if (of_property_read_bool(np, "syscon-chipselects")) {
		qspi->ctrl_base =
		syscon_regmap_lookup_by_phandle(np,
						"syscon-chipselects");
		if (IS_ERR(qspi->ctrl_base))
			return PTR_ERR(qspi->ctrl_base);
		ret = of_property_read_u32_index(np,
						 "syscon-chipselects",
						 1, &qspi->ctrl_reg);
		if (ret) {
			dev_err(&pdev->dev,
				"couldn't get ctrl_mod reg index\n");
			return ret;
		}
	}

	qspi->fclk = devm_clk_get(&pdev->dev, "fck");
	if (IS_ERR(qspi->fclk)) {
		ret = PTR_ERR(qspi->fclk);
		dev_err(&pdev->dev, "could not get clk: %d\n", ret);
	}

	pm_runtime_use_autosuspend(&pdev->dev);
	pm_runtime_set_autosuspend_delay(&pdev->dev, QSPI_AUTOSUSPEND_TIMEOUT);
	pm_runtime_enable(&pdev->dev);

	if (!of_property_read_u32(np, "spi-max-frequency", &max_freq))
		qspi->spi_max_frequency = max_freq;

	ret = devm_spi_register_master(&pdev->dev, master);
	if (ret)
		goto free_master;

	return 0;

free_master:
	spi_master_put(master);
	return ret;
}

static int ti_qspi_remove(struct platform_device *pdev)
{
	pm_runtime_put_sync(&pdev->dev);
	pm_runtime_disable(&pdev->dev);

	return 0;
}

static const struct dev_pm_ops ti_qspi_pm_ops = {
	.runtime_resume = ti_qspi_runtime_resume,
};

static struct platform_driver ti_qspi_driver = {
	.probe	= ti_qspi_probe,
	.remove = ti_qspi_remove,
	.driver = {
		.name	= "ti-qspi",
		.pm =   &ti_qspi_pm_ops,
		.of_match_table = ti_qspi_match,
	}
};

module_platform_driver(ti_qspi_driver);

MODULE_AUTHOR("Sourav Poddar <sourav.poddar@ti.com>");
MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("TI QSPI controller driver");
MODULE_ALIAS("platform:ti-qspi");
Commit	Line	Data
505a1495 SP	1	/*
	2	* TI QSPI driver
	3	*
	4	* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
	5	* Author: Sourav Poddar <sourav.poddar@ti.com>
	6	*
	7	* This program is free software; you can redistribute it and/or
	8	* modify it under the terms of the GPLv2.
	9	*
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
	13	* GNU General Public License for more details.
	14	*/
	15
	16	#include <linux/kernel.h>
	17	#include <linux/init.h>
	18	#include <linux/interrupt.h>
	19	#include <linux/module.h>
	20	#include <linux/device.h>
	21	#include <linux/delay.h>
	22	#include <linux/dma-mapping.h>
	23	#include <linux/dmaengine.h>
	24	#include <linux/omap-dma.h>
	25	#include <linux/platform_device.h>
	26	#include <linux/err.h>
	27	#include <linux/clk.h>
	28	#include <linux/io.h>
	29	#include <linux/slab.h>
	30	#include <linux/pm_runtime.h>
	31	#include <linux/of.h>
	32	#include <linux/of_device.h>
	33	#include <linux/pinctrl/consumer.h>
4dea6c9b V	34	#include <linux/mfd/syscon.h>
4dea6c9b V	35	#include <linux/regmap.h>
505a1495 SP	36
	37	#include <linux/spi/spi.h>
	38
	39	struct ti_qspi_regs {
	40	u32 clkctrl;
	41	};
	42
	43	struct ti_qspi {
505a1495 SP	44	/* list synchronization */
	45	struct mutex list_lock;
	46
	47	struct spi_master *master;
	48	void __iomem *base;
6b3938ae	49	void __iomem *mmap_base;
4dea6c9b V	50	struct regmap *ctrl_base;
4dea6c9b V	51	unsigned int ctrl_reg;
505a1495 SP	52	struct clk *fclk;
	53	struct device *dev;
	54
	55	struct ti_qspi_regs ctx_reg;
	56
	57	u32 spi_max_frequency;
	58	u32 cmd;
	59	u32 dc;
6b3938ae	60
4dea6c9b	61	bool mmap_enabled;
505a1495 SP	62	};
	63
	64	#define QSPI_PID (0x0)
	65	#define QSPI_SYSCONFIG (0x10)
505a1495 SP	66	#define QSPI_SPI_CLOCK_CNTRL_REG (0x40)
	67	#define QSPI_SPI_DC_REG (0x44)
	68	#define QSPI_SPI_CMD_REG (0x48)
	69	#define QSPI_SPI_STATUS_REG (0x4c)
	70	#define QSPI_SPI_DATA_REG (0x50)
4dea6c9b	71	#define QSPI_SPI_SETUP_REG(n) ((0x54 + 4 * n))
505a1495	72	#define QSPI_SPI_SWITCH_REG (0x64)
505a1495 SP	73	#define QSPI_SPI_DATA_REG_1 (0x68)
	74	#define QSPI_SPI_DATA_REG_2 (0x6c)
	75	#define QSPI_SPI_DATA_REG_3 (0x70)
	76
	77	#define QSPI_COMPLETION_TIMEOUT msecs_to_jiffies(2000)
	78
	79	#define QSPI_FCLK 192000000
	80
	81	/* Clock Control */
	82	#define QSPI_CLK_EN (1 << 31)
	83	#define QSPI_CLK_DIV_MAX 0xffff
	84
	85	/* Command */
	86	#define QSPI_EN_CS(n) (n << 28)
	87	#define QSPI_WLEN(n) ((n - 1) << 19)
	88	#define QSPI_3_PIN (1 << 18)
	89	#define QSPI_RD_SNGL (1 << 16)
	90	#define QSPI_WR_SNGL (2 << 16)
	91	#define QSPI_RD_DUAL (3 << 16)
	92	#define QSPI_RD_QUAD (7 << 16)
	93	#define QSPI_INVAL (4 << 16)
505a1495	94	#define QSPI_FLEN(n) ((n - 1) << 0)
f682c4ff V	95	#define QSPI_WLEN_MAX_BITS 128
f682c4ff V	96	#define QSPI_WLEN_MAX_BYTES 16
505a1495 SP	97
505a1495 SP	98	/* STATUS REGISTER */
00611047	99	#define BUSY 0x01
505a1495 SP	100	#define WC 0x02
505a1495 SP	101
505a1495 SP	102	/* Device Control */
	103	#define QSPI_DD(m, n) (m << (3 + n * 8))
	104	#define QSPI_CKPHA(n) (1 << (2 + n * 8))
	105	#define QSPI_CSPOL(n) (1 << (1 + n * 8))
	106	#define QSPI_CKPOL(n) (1 << (n * 8))
	107
	108	#define QSPI_FRAME 4096
	109
	110	#define QSPI_AUTOSUSPEND_TIMEOUT 2000
	111
4dea6c9b V	112	#define MEM_CS_EN(n) ((n + 1) << 8)
	113	#define MEM_CS_MASK (7 << 8)
	114
	115	#define MM_SWITCH 0x1
	116
	117	#define QSPI_SETUP_RD_NORMAL (0x0 << 12)
	118	#define QSPI_SETUP_RD_DUAL (0x1 << 12)
	119	#define QSPI_SETUP_RD_QUAD (0x3 << 12)
	120	#define QSPI_SETUP_ADDR_SHIFT 8
	121	#define QSPI_SETUP_DUMMY_SHIFT 10
	122
505a1495 SP	123	static inline unsigned long ti_qspi_read(struct ti_qspi *qspi,
	124	unsigned long reg)
	125	{
	126	return readl(qspi->base + reg);
	127	}
	128
	129	static inline void ti_qspi_write(struct ti_qspi *qspi,
	130	unsigned long val, unsigned long reg)
	131	{
	132	writel(val, qspi->base + reg);
	133	}
	134
	135	static int ti_qspi_setup(struct spi_device *spi)
	136	{
	137	struct ti_qspi *qspi = spi_master_get_devdata(spi->master);
	138	struct ti_qspi_regs *ctx_reg = &qspi->ctx_reg;
	139	int clk_div = 0, ret;
	140	u32 clk_ctrl_reg, clk_rate, clk_mask;
	141
	142	if (spi->master->busy) {
	143	dev_dbg(qspi->dev, "master busy doing other trasnfers\n");
	144	return -EBUSY;
	145	}
	146
	147	if (!qspi->spi_max_frequency) {
	148	dev_err(qspi->dev, "spi max frequency not defined\n");
	149	return -EINVAL;
	150	}
	151
	152	clk_rate = clk_get_rate(qspi->fclk);
	153
	154	clk_div = DIV_ROUND_UP(clk_rate, qspi->spi_max_frequency) - 1;
	155
	156	if (clk_div < 0) {
	157	dev_dbg(qspi->dev, "clock divider < 0, using /1 divider\n");
	158	return -EINVAL;
	159	}
	160
	161	if (clk_div > QSPI_CLK_DIV_MAX) {
	162	dev_dbg(qspi->dev, "clock divider >%d , using /%d divider\n",
	163	QSPI_CLK_DIV_MAX, QSPI_CLK_DIV_MAX + 1);
	164	return -EINVAL;
	165	}
	166
	167	dev_dbg(qspi->dev, "hz: %d, clock divider %d\n",
	168	qspi->spi_max_frequency, clk_div);
	169
	170	ret = pm_runtime_get_sync(qspi->dev);
05b96675	171	if (ret < 0) {
505a1495 SP	172	dev_err(qspi->dev, "pm_runtime_get_sync() failed\n");
	173	return ret;
	174	}
	175
	176	clk_ctrl_reg = ti_qspi_read(qspi, QSPI_SPI_CLOCK_CNTRL_REG);
	177
	178	clk_ctrl_reg &= ~QSPI_CLK_EN;
	179
	180	/* disable SCLK */
	181	ti_qspi_write(qspi, clk_ctrl_reg, QSPI_SPI_CLOCK_CNTRL_REG);
	182
	183	/* enable SCLK */
	184	clk_mask = QSPI_CLK_EN \| clk_div;
	185	ti_qspi_write(qspi, clk_mask, QSPI_SPI_CLOCK_CNTRL_REG);
	186	ctx_reg->clkctrl = clk_mask;
	187
	188	pm_runtime_mark_last_busy(qspi->dev);
	189	ret = pm_runtime_put_autosuspend(qspi->dev);
	190	if (ret < 0) {
	191	dev_err(qspi->dev, "pm_runtime_put_autosuspend() failed\n");
	192	return ret;
	193	}
	194
	195	return 0;
	196	}
	197
	198	static void ti_qspi_restore_ctx(struct ti_qspi *qspi)
	199	{
	200	struct ti_qspi_regs *ctx_reg = &qspi->ctx_reg;
	201
	202	ti_qspi_write(qspi, ctx_reg->clkctrl, QSPI_SPI_CLOCK_CNTRL_REG);
	203	}
	204
00611047 M	205	static inline u32 qspi_is_busy(struct ti_qspi *qspi)
	206	{
	207	u32 stat;
	208	unsigned long timeout = jiffies + QSPI_COMPLETION_TIMEOUT;
	209
	210	stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG);
	211	while ((stat & BUSY) && time_after(timeout, jiffies)) {
	212	cpu_relax();
	213	stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG);
	214	}
	215
	216	WARN(stat & BUSY, "qspi busy\n");
	217	return stat & BUSY;
	218	}
	219
57c2ecd9 V	220	static inline int ti_qspi_poll_wc(struct ti_qspi *qspi)
	221	{
	222	u32 stat;
	223	unsigned long timeout = jiffies + QSPI_COMPLETION_TIMEOUT;
	224
	225	do {
	226	stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG);
	227	if (stat & WC)
	228	return 0;
	229	cpu_relax();
	230	} while (time_after(timeout, jiffies));
	231
	232	stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG);
	233	if (stat & WC)
	234	return 0;
	235	return -ETIMEDOUT;
	236	}
	237
505a1495 SP	238	static int qspi_write_msg(struct ti_qspi qspi, struct spi_transfer t)
505a1495 SP	239	{
f682c4ff	240	int wlen, count, xfer_len;
505a1495 SP	241	unsigned int cmd;
505a1495 SP	242	const u8 *txbuf;
f682c4ff	243	u32 data;
505a1495 SP	244
	245	txbuf = t->tx_buf;
	246	cmd = qspi->cmd \| QSPI_WR_SNGL;
	247	count = t->len;
3ab54620	248	wlen = t->bits_per_word >> 3; /* in bytes */
f682c4ff	249	xfer_len = wlen;
505a1495 SP	250
505a1495 SP	251	while (count) {
00611047 M	252	if (qspi_is_busy(qspi))
	253	return -EBUSY;
	254
505a1495	255	switch (wlen) {
3ab54620	256	case 1:
505a1495 SP	257	dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %02x\n",
505a1495 SP	258	cmd, qspi->dc, *txbuf);
f682c4ff V	259	if (count >= QSPI_WLEN_MAX_BYTES) {
	260	u32 txp = (u32 )txbuf;
	261
	262	data = cpu_to_be32(*txp++);
	263	writel(data, qspi->base +
	264	QSPI_SPI_DATA_REG_3);
	265	data = cpu_to_be32(*txp++);
	266	writel(data, qspi->base +
	267	QSPI_SPI_DATA_REG_2);
	268	data = cpu_to_be32(*txp++);
	269	writel(data, qspi->base +
	270	QSPI_SPI_DATA_REG_1);
	271	data = cpu_to_be32(*txp++);
	272	writel(data, qspi->base +
	273	QSPI_SPI_DATA_REG);
	274	xfer_len = QSPI_WLEN_MAX_BYTES;
	275	cmd \|= QSPI_WLEN(QSPI_WLEN_MAX_BITS);
	276	} else {
	277	writeb(*txbuf, qspi->base + QSPI_SPI_DATA_REG);
	278	cmd = qspi->cmd \| QSPI_WR_SNGL;
	279	xfer_len = wlen;
	280	cmd \|= QSPI_WLEN(wlen);
	281	}
505a1495	282	break;
3ab54620	283	case 2:
505a1495 SP	284	dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %04x\n",
	285	cmd, qspi->dc, *txbuf);
	286	writew(((u16 )txbuf), qspi->base + QSPI_SPI_DATA_REG);
505a1495	287	break;
3ab54620	288	case 4:
505a1495 SP	289	dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %08x\n",
	290	cmd, qspi->dc, *txbuf);
	291	writel(((u32 )txbuf), qspi->base + QSPI_SPI_DATA_REG);
505a1495 SP	292	break;
505a1495 SP	293	}
3ab54620 AL	294
3ab54620 AL	295	ti_qspi_write(qspi, cmd, QSPI_SPI_CMD_REG);
57c2ecd9	296	if (ti_qspi_poll_wc(qspi)) {
3ab54620 AL	297	dev_err(qspi->dev, "write timed out\n");
	298	return -ETIMEDOUT;
	299	}
f682c4ff V	300	txbuf += xfer_len;
f682c4ff V	301	count -= xfer_len;
505a1495 SP	302	}
	303
	304	return 0;
	305	}
	306
	307	static int qspi_read_msg(struct ti_qspi qspi, struct spi_transfer t)
	308	{
060556a9	309	int wlen, count;
505a1495 SP	310	unsigned int cmd;
	311	u8 *rxbuf;
	312
	313	rxbuf = t->rx_buf;
70e2e976 SP	314	cmd = qspi->cmd;
	315	switch (t->rx_nbits) {
	316	case SPI_NBITS_DUAL:
	317	cmd \|= QSPI_RD_DUAL;
	318	break;
	319	case SPI_NBITS_QUAD:
	320	cmd \|= QSPI_RD_QUAD;
	321	break;
	322	default:
	323	cmd \|= QSPI_RD_SNGL;
	324	break;
	325	}
505a1495	326	count = t->len;
3ab54620	327	wlen = t->bits_per_word >> 3; /* in bytes */
505a1495 SP	328
	329	while (count) {
	330	dev_dbg(qspi->dev, "rx cmd %08x dc %08x\n", cmd, qspi->dc);
00611047 M	331	if (qspi_is_busy(qspi))
	332	return -EBUSY;
	333
505a1495	334	ti_qspi_write(qspi, cmd, QSPI_SPI_CMD_REG);
57c2ecd9	335	if (ti_qspi_poll_wc(qspi)) {
505a1495 SP	336	dev_err(qspi->dev, "read timed out\n");
	337	return -ETIMEDOUT;
	338	}
	339	switch (wlen) {
3ab54620	340	case 1:
505a1495	341	*rxbuf = readb(qspi->base + QSPI_SPI_DATA_REG);
505a1495	342	break;
3ab54620	343	case 2:
505a1495	344	((u16 )rxbuf) = readw(qspi->base + QSPI_SPI_DATA_REG);
505a1495	345	break;
3ab54620	346	case 4:
505a1495	347	((u32 )rxbuf) = readl(qspi->base + QSPI_SPI_DATA_REG);
505a1495 SP	348	break;
505a1495 SP	349	}
3ab54620 AL	350	rxbuf += wlen;
3ab54620 AL	351	count -= wlen;
505a1495 SP	352	}
	353
	354	return 0;
	355	}
	356
	357	static int qspi_transfer_msg(struct ti_qspi qspi, struct spi_transfer t)
	358	{
	359	int ret;
	360
	361	if (t->tx_buf) {
	362	ret = qspi_write_msg(qspi, t);
	363	if (ret) {
	364	dev_dbg(qspi->dev, "Error while writing\n");
	365	return ret;
	366	}
	367	}
	368
	369	if (t->rx_buf) {
	370	ret = qspi_read_msg(qspi, t);
	371	if (ret) {
	372	dev_dbg(qspi->dev, "Error while reading\n");
	373	return ret;
	374	}
	375	}
	376
	377	return 0;
	378	}
	379
4dea6c9b V	380	static void ti_qspi_enable_memory_map(struct spi_device *spi)
	381	{
	382	struct ti_qspi *qspi = spi_master_get_devdata(spi->master);
	383
	384	ti_qspi_write(qspi, MM_SWITCH, QSPI_SPI_SWITCH_REG);
	385	if (qspi->ctrl_base) {
	386	regmap_update_bits(qspi->ctrl_base, qspi->ctrl_reg,
	387	MEM_CS_EN(spi->chip_select),
	388	MEM_CS_MASK);
	389	}
	390	qspi->mmap_enabled = true;
	391	}
	392
	393	static void ti_qspi_disable_memory_map(struct spi_device *spi)
	394	{
	395	struct ti_qspi *qspi = spi_master_get_devdata(spi->master);
	396
	397	ti_qspi_write(qspi, 0, QSPI_SPI_SWITCH_REG);
	398	if (qspi->ctrl_base)
	399	regmap_update_bits(qspi->ctrl_base, qspi->ctrl_reg,
	400	0, MEM_CS_MASK);
	401	qspi->mmap_enabled = false;
	402	}
	403
	404	static void ti_qspi_setup_mmap_read(struct spi_device *spi,
	405	struct spi_flash_read_message *msg)
	406	{
	407	struct ti_qspi *qspi = spi_master_get_devdata(spi->master);
	408	u32 memval = msg->read_opcode;
	409
	410	switch (msg->data_nbits) {
	411	case SPI_NBITS_QUAD:
	412	memval \|= QSPI_SETUP_RD_QUAD;
	413	break;
	414	case SPI_NBITS_DUAL:
	415	memval \|= QSPI_SETUP_RD_DUAL;
	416	break;
	417	default:
	418	memval \|= QSPI_SETUP_RD_NORMAL;
	419	break;
	420	}
	421	memval \|= ((msg->addr_width - 1) << QSPI_SETUP_ADDR_SHIFT \|
	422	msg->dummy_bytes << QSPI_SETUP_DUMMY_SHIFT);
	423	ti_qspi_write(qspi, memval,
	424	QSPI_SPI_SETUP_REG(spi->chip_select));
	425	}
	426
	427	static int ti_qspi_spi_flash_read(struct spi_device *spi,
	428	struct spi_flash_read_message *msg)
	429	{
	430	struct ti_qspi *qspi = spi_master_get_devdata(spi->master);
	431	int ret = 0;
	432
	433	mutex_lock(&qspi->list_lock);
	434
	435	if (!qspi->mmap_enabled)
	436	ti_qspi_enable_memory_map(spi);
	437	ti_qspi_setup_mmap_read(spi, msg);
	438	memcpy_fromio(msg->buf, qspi->mmap_base + msg->from, msg->len);
	439	msg->retlen = msg->len;
	440
	441	mutex_unlock(&qspi->list_lock);
	442
	443	return ret;
444	}
445
505a1495 SP	446	static int ti_qspi_start_transfer_one(struct spi_master *master,
	447	struct spi_message *m)
	448	{
	449	struct ti_qspi *qspi = spi_master_get_devdata(master);
	450	struct spi_device *spi = m->spi;
	451	struct spi_transfer *t;
	452	int status = 0, ret;
	453	int frame_length;
	454
	455	/* setup device control reg */
	456	qspi->dc = 0;
	457
	458	if (spi->mode & SPI_CPHA)
	459	qspi->dc \|= QSPI_CKPHA(spi->chip_select);
	460	if (spi->mode & SPI_CPOL)
	461	qspi->dc \|= QSPI_CKPOL(spi->chip_select);
	462	if (spi->mode & SPI_CS_HIGH)
	463	qspi->dc \|= QSPI_CSPOL(spi->chip_select);
	464
	465	frame_length = (m->frame_length << 3) / spi->bits_per_word;
	466
	467	frame_length = clamp(frame_length, 0, QSPI_FRAME);
	468
	469	/* setup command reg */
	470	qspi->cmd = 0;
	471	qspi->cmd \|= QSPI_EN_CS(spi->chip_select);
	472	qspi->cmd \|= QSPI_FLEN(frame_length);
505a1495	473
505a1495 SP	474	ti_qspi_write(qspi, qspi->dc, QSPI_SPI_DC_REG);
	475
	476	mutex_lock(&qspi->list_lock);
	477
4dea6c9b V	478	if (qspi->mmap_enabled)
	479	ti_qspi_disable_memory_map(spi);
	480
505a1495 SP	481	list_for_each_entry(t, &m->transfers, transfer_list) {
	482	qspi->cmd \|= QSPI_WLEN(t->bits_per_word);
	483
	484	ret = qspi_transfer_msg(qspi, t);
	485	if (ret) {
	486	dev_dbg(qspi->dev, "transfer message failed\n");
b6460366	487	mutex_unlock(&qspi->list_lock);
505a1495 SP	488	return -EINVAL;
	489	}
	490
	491	m->actual_length += t->len;
	492	}
	493
	494	mutex_unlock(&qspi->list_lock);
	495
bc27a539	496	ti_qspi_write(qspi, qspi->cmd \| QSPI_INVAL, QSPI_SPI_CMD_REG);
505a1495 SP	497	m->status = status;
	498	spi_finalize_current_message(master);
	499
505a1495 SP	500	return status;
	501	}
	502
505a1495 SP	503	static int ti_qspi_runtime_resume(struct device *dev)
	504	{
	505	struct ti_qspi *qspi;
505a1495	506
f17414c4	507	qspi = dev_get_drvdata(dev);
505a1495 SP	508	ti_qspi_restore_ctx(qspi);
	509
	510	return 0;
	511	}
	512
	513	static const struct of_device_id ti_qspi_match[] = {
	514	{.compatible = "ti,dra7xxx-qspi" },
09222fc3	515	{.compatible = "ti,am4372-qspi" },
505a1495 SP	516	{},
505a1495 SP	517	};
e1432d30	518	MODULE_DEVICE_TABLE(of, ti_qspi_match);
505a1495 SP	519
	520	static int ti_qspi_probe(struct platform_device *pdev)
	521	{
	522	struct ti_qspi *qspi;
	523	struct spi_master *master;
4dea6c9b	524	struct resource r, res_mmap;
505a1495 SP	525	struct device_node *np = pdev->dev.of_node;
	526	u32 max_freq;
	527	int ret = 0, num_cs, irq;
	528
	529	master = spi_alloc_master(&pdev->dev, sizeof(*qspi));
	530	if (!master)
	531	return -ENOMEM;
	532
633795b9	533	master->mode_bits = SPI_CPOL \| SPI_CPHA \| SPI_RX_DUAL \| SPI_RX_QUAD;
505a1495	534
505a1495 SP	535	master->flags = SPI_MASTER_HALF_DUPLEX;
	536	master->setup = ti_qspi_setup;
	537	master->auto_runtime_pm = true;
	538	master->transfer_one_message = ti_qspi_start_transfer_one;
	539	master->dev.of_node = pdev->dev.of_node;
aa188f90 AL	540	master->bits_per_word_mask = SPI_BPW_MASK(32) \| SPI_BPW_MASK(16) \|
aa188f90 AL	541	SPI_BPW_MASK(8);
505a1495 SP	542
	543	if (!of_property_read_u32(np, "num-cs", &num_cs))
	544	master->num_chipselect = num_cs;
	545
505a1495 SP	546	qspi = spi_master_get_devdata(master);
	547	qspi->master = master;
	548	qspi->dev = &pdev->dev;
160a0613	549	platform_set_drvdata(pdev, qspi);
505a1495	550
6b3938ae SP	551	r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi_base");
	552	if (r == NULL) {
	553	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	554	if (r == NULL) {
	555	dev_err(&pdev->dev, "missing platform data\n");
	556	return -ENODEV;
	557	}
	558	}
505a1495	559
6b3938ae SP	560	res_mmap = platform_get_resource_byname(pdev,
	561	IORESOURCE_MEM, "qspi_mmap");
	562	if (res_mmap == NULL) {
	563	res_mmap = platform_get_resource(pdev, IORESOURCE_MEM, 1);
	564	if (res_mmap == NULL) {
	565	dev_err(&pdev->dev,
	566	"memory mapped resource not required\n");
6b3938ae SP	567	}
	568	}
	569
505a1495 SP	570	irq = platform_get_irq(pdev, 0);
	571	if (irq < 0) {
	572	dev_err(&pdev->dev, "no irq resource?\n");
	573	return irq;
	574	}
	575
505a1495 SP	576	mutex_init(&qspi->list_lock);
	577
	578	qspi->base = devm_ioremap_resource(&pdev->dev, r);
	579	if (IS_ERR(qspi->base)) {
	580	ret = PTR_ERR(qspi->base);
	581	goto free_master;
	582	}
	583
6b3938ae	584	if (res_mmap) {
4dea6c9b V	585	qspi->mmap_base = devm_ioremap_resource(&pdev->dev,
	586	res_mmap);
	587	master->spi_flash_read = ti_qspi_spi_flash_read;
6b3938ae	588	if (IS_ERR(qspi->mmap_base)) {
4dea6c9b V	589	dev_err(&pdev->dev,
	590	"falling back to PIO mode\n");
	591	master->spi_flash_read = NULL;
	592	}
	593	}
	594	qspi->mmap_enabled = false;
	595
	596	if (of_property_read_bool(np, "syscon-chipselects")) {
	597	qspi->ctrl_base =
	598	syscon_regmap_lookup_by_phandle(np,
	599	"syscon-chipselects");
	600	if (IS_ERR(qspi->ctrl_base))
	601	return PTR_ERR(qspi->ctrl_base);
	602	ret = of_property_read_u32_index(np,
	603	"syscon-chipselects",
	604	1, &qspi->ctrl_reg);
	605	if (ret) {
	606	dev_err(&pdev->dev,
	607	"couldn't get ctrl_mod reg index\n");
	608	return ret;
6b3938ae SP	609	}
	610	}
	611
505a1495 SP	612	qspi->fclk = devm_clk_get(&pdev->dev, "fck");
	613	if (IS_ERR(qspi->fclk)) {
	614	ret = PTR_ERR(qspi->fclk);
	615	dev_err(&pdev->dev, "could not get clk: %d\n", ret);
	616	}
	617
505a1495 SP	618	pm_runtime_use_autosuspend(&pdev->dev);
	619	pm_runtime_set_autosuspend_delay(&pdev->dev, QSPI_AUTOSUSPEND_TIMEOUT);
	620	pm_runtime_enable(&pdev->dev);
	621
	622	if (!of_property_read_u32(np, "spi-max-frequency", &max_freq))
	623	qspi->spi_max_frequency = max_freq;
	624
7388c03b	625	ret = devm_spi_register_master(&pdev->dev, master);
505a1495 SP	626	if (ret)
	627	goto free_master;
	628
	629	return 0;
	630
	631	free_master:
	632	spi_master_put(master);
	633	return ret;
	634	}
	635
	636	static int ti_qspi_remove(struct platform_device *pdev)
	637	{
e6b5140b	638	pm_runtime_put_sync(&pdev->dev);
cbcabb7a SP	639	pm_runtime_disable(&pdev->dev);
cbcabb7a SP	640
505a1495 SP	641	return 0;
	642	}
	643
	644	static const struct dev_pm_ops ti_qspi_pm_ops = {
	645	.runtime_resume = ti_qspi_runtime_resume,
	646	};
	647
	648	static struct platform_driver ti_qspi_driver = {
	649	.probe = ti_qspi_probe,
dabefd56	650	.remove = ti_qspi_remove,
505a1495	651	.driver = {
5a33d30f	652	.name = "ti-qspi",
505a1495 SP	653	.pm = &ti_qspi_pm_ops,
	654	.of_match_table = ti_qspi_match,
	655	}
	656	};
	657
	658	module_platform_driver(ti_qspi_driver);
	659
	660	MODULE_AUTHOR("Sourav Poddar <sourav.poddar@ti.com>");
	661	MODULE_LICENSE("GPL v2");
	662	MODULE_DESCRIPTION("TI QSPI controller driver");
5a33d30f	663	MODULE_ALIAS("platform:ti-qspi");