[linux-2.6-block.git] / drivers / spi / spi-ti-qspi.c

/*
 * TI QSPI driver
 *
 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
 * Author: Sourav Poddar <sourav.poddar@ti.com>
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GPLv2.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/device.h>
#include <linux/delay.h>
#include <linux/dma-mapping.h>
#include <linux/dmaengine.h>
#include <linux/omap-dma.h>
#include <linux/platform_device.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/slab.h>
#include <linux/pm_runtime.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/pinctrl/consumer.h>

#include <linux/spi/spi.h>

struct ti_qspi_regs {
	u32 clkctrl;
};

struct ti_qspi {
	struct completion       transfer_complete;

	/* list synchronization */
	struct mutex            list_lock;

	struct spi_master	*master;
	void __iomem            *base;
	void __iomem            *ctrl_base;
	void __iomem            *mmap_base;
	struct clk		*fclk;
	struct device           *dev;

	struct ti_qspi_regs     ctx_reg;

	u32 spi_max_frequency;
	u32 cmd;
	u32 dc;

	bool ctrl_mod;
};

#define QSPI_PID			(0x0)
#define QSPI_SYSCONFIG			(0x10)
#define QSPI_INTR_STATUS_RAW_SET	(0x20)
#define QSPI_INTR_STATUS_ENABLED_CLEAR	(0x24)
#define QSPI_INTR_ENABLE_SET_REG	(0x28)
#define QSPI_INTR_ENABLE_CLEAR_REG	(0x2c)
#define QSPI_SPI_CLOCK_CNTRL_REG	(0x40)
#define QSPI_SPI_DC_REG			(0x44)
#define QSPI_SPI_CMD_REG		(0x48)
#define QSPI_SPI_STATUS_REG		(0x4c)
#define QSPI_SPI_DATA_REG		(0x50)
#define QSPI_SPI_SETUP0_REG		(0x54)
#define QSPI_SPI_SWITCH_REG		(0x64)
#define QSPI_SPI_SETUP1_REG		(0x58)
#define QSPI_SPI_SETUP2_REG		(0x5c)
#define QSPI_SPI_SETUP3_REG		(0x60)
#define QSPI_SPI_DATA_REG_1		(0x68)
#define QSPI_SPI_DATA_REG_2		(0x6c)
#define QSPI_SPI_DATA_REG_3		(0x70)

#define QSPI_COMPLETION_TIMEOUT		msecs_to_jiffies(2000)

#define QSPI_FCLK			192000000

/* Clock Control */
#define QSPI_CLK_EN			(1 << 31)
#define QSPI_CLK_DIV_MAX		0xffff

/* Command */
#define QSPI_EN_CS(n)			(n << 28)
#define QSPI_WLEN(n)			((n - 1) << 19)
#define QSPI_3_PIN			(1 << 18)
#define QSPI_RD_SNGL			(1 << 16)
#define QSPI_WR_SNGL			(2 << 16)
#define QSPI_RD_DUAL			(3 << 16)
#define QSPI_RD_QUAD			(7 << 16)
#define QSPI_INVAL			(4 << 16)
#define QSPI_WC_CMD_INT_EN			(1 << 14)
#define QSPI_FLEN(n)			((n - 1) << 0)

/* STATUS REGISTER */
#define BUSY				0x01
#define WC				0x02

/* INTERRUPT REGISTER */
#define QSPI_WC_INT_EN				(1 << 1)
#define QSPI_WC_INT_DISABLE			(1 << 1)

/* Device Control */
#define QSPI_DD(m, n)			(m << (3 + n * 8))
#define QSPI_CKPHA(n)			(1 << (2 + n * 8))
#define QSPI_CSPOL(n)			(1 << (1 + n * 8))
#define QSPI_CKPOL(n)			(1 << (n * 8))

#define	QSPI_FRAME			4096

#define QSPI_AUTOSUSPEND_TIMEOUT         2000

static inline unsigned long ti_qspi_read(struct ti_qspi *qspi,
		unsigned long reg)
{
	return readl(qspi->base + reg);
}

static inline void ti_qspi_write(struct ti_qspi *qspi,
		unsigned long val, unsigned long reg)
{
	writel(val, qspi->base + reg);
}

static int ti_qspi_setup(struct spi_device *spi)
{
	struct ti_qspi	*qspi = spi_master_get_devdata(spi->master);
	struct ti_qspi_regs *ctx_reg = &qspi->ctx_reg;
	int clk_div = 0, ret;
	u32 clk_ctrl_reg, clk_rate, clk_mask;

	if (spi->master->busy) {
		dev_dbg(qspi->dev, "master busy doing other trasnfers\n");
		return -EBUSY;
	}

	if (!qspi->spi_max_frequency) {
		dev_err(qspi->dev, "spi max frequency not defined\n");
		return -EINVAL;
	}

	clk_rate = clk_get_rate(qspi->fclk);

	clk_div = DIV_ROUND_UP(clk_rate, qspi->spi_max_frequency) - 1;

	if (clk_div < 0) {
		dev_dbg(qspi->dev, "clock divider < 0, using /1 divider\n");
		return -EINVAL;
	}

	if (clk_div > QSPI_CLK_DIV_MAX) {
		dev_dbg(qspi->dev, "clock divider >%d , using /%d divider\n",
				QSPI_CLK_DIV_MAX, QSPI_CLK_DIV_MAX + 1);
		return -EINVAL;
	}

	dev_dbg(qspi->dev, "hz: %d, clock divider %d\n",
			qspi->spi_max_frequency, clk_div);

	ret = pm_runtime_get_sync(qspi->dev);
	if (ret < 0) {
		dev_err(qspi->dev, "pm_runtime_get_sync() failed\n");
		return ret;
	}

	clk_ctrl_reg = ti_qspi_read(qspi, QSPI_SPI_CLOCK_CNTRL_REG);

	clk_ctrl_reg &= ~QSPI_CLK_EN;

	/* disable SCLK */
	ti_qspi_write(qspi, clk_ctrl_reg, QSPI_SPI_CLOCK_CNTRL_REG);

	/* enable SCLK */
	clk_mask = QSPI_CLK_EN | clk_div;
	ti_qspi_write(qspi, clk_mask, QSPI_SPI_CLOCK_CNTRL_REG);
	ctx_reg->clkctrl = clk_mask;

	pm_runtime_mark_last_busy(qspi->dev);
	ret = pm_runtime_put_autosuspend(qspi->dev);
	if (ret < 0) {
		dev_err(qspi->dev, "pm_runtime_put_autosuspend() failed\n");
		return ret;
	}

	return 0;
}

static void ti_qspi_restore_ctx(struct ti_qspi *qspi)
{
	struct ti_qspi_regs *ctx_reg = &qspi->ctx_reg;

	ti_qspi_write(qspi, ctx_reg->clkctrl, QSPI_SPI_CLOCK_CNTRL_REG);
}

static inline u32 qspi_is_busy(struct ti_qspi *qspi)
{
	u32 stat;
	unsigned long timeout = jiffies + QSPI_COMPLETION_TIMEOUT;

	stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG);
	while ((stat & BUSY) && time_after(timeout, jiffies)) {
		cpu_relax();
		stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG);
	}

	WARN(stat & BUSY, "qspi busy\n");
	return stat & BUSY;
}

static int qspi_write_msg(struct ti_qspi *qspi, struct spi_transfer *t)
{
	int wlen, count;
	unsigned int cmd;
	const u8 *txbuf;

	txbuf = t->tx_buf;
	cmd = qspi->cmd | QSPI_WR_SNGL;
	count = t->len;
	wlen = t->bits_per_word >> 3;	/* in bytes */

	while (count) {
		if (qspi_is_busy(qspi))
			return -EBUSY;

		switch (wlen) {
		case 1:
			dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %02x\n",
					cmd, qspi->dc, *txbuf);
			writeb(*txbuf, qspi->base + QSPI_SPI_DATA_REG);
			break;
		case 2:
			dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %04x\n",
					cmd, qspi->dc, *txbuf);
			writew(*((u16 *)txbuf), qspi->base + QSPI_SPI_DATA_REG);
			break;
		case 4:
			dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %08x\n",
					cmd, qspi->dc, *txbuf);
			writel(*((u32 *)txbuf), qspi->base + QSPI_SPI_DATA_REG);
			break;
		}

		ti_qspi_write(qspi, cmd, QSPI_SPI_CMD_REG);
		if (!wait_for_completion_timeout(&qspi->transfer_complete,
						 QSPI_COMPLETION_TIMEOUT)) {
			dev_err(qspi->dev, "write timed out\n");
			return -ETIMEDOUT;
		}
		txbuf += wlen;
		count -= wlen;
	}

	return 0;
}

static int qspi_read_msg(struct ti_qspi *qspi, struct spi_transfer *t)
{
	int wlen, count;
	unsigned int cmd;
	u8 *rxbuf;

	rxbuf = t->rx_buf;
	cmd = qspi->cmd;
	switch (t->rx_nbits) {
	case SPI_NBITS_DUAL:
		cmd |= QSPI_RD_DUAL;
		break;
	case SPI_NBITS_QUAD:
		cmd |= QSPI_RD_QUAD;
		break;
	default:
		cmd |= QSPI_RD_SNGL;
		break;
	}
	count = t->len;
	wlen = t->bits_per_word >> 3;	/* in bytes */

	while (count) {
		dev_dbg(qspi->dev, "rx cmd %08x dc %08x\n", cmd, qspi->dc);
		if (qspi_is_busy(qspi))
			return -EBUSY;

		ti_qspi_write(qspi, cmd, QSPI_SPI_CMD_REG);
		if (!wait_for_completion_timeout(&qspi->transfer_complete,
						 QSPI_COMPLETION_TIMEOUT)) {
			dev_err(qspi->dev, "read timed out\n");
			return -ETIMEDOUT;
		}
		switch (wlen) {
		case 1:
			*rxbuf = readb(qspi->base + QSPI_SPI_DATA_REG);
			break;
		case 2:
			*((u16 *)rxbuf) = readw(qspi->base + QSPI_SPI_DATA_REG);
			break;
		case 4:
			*((u32 *)rxbuf) = readl(qspi->base + QSPI_SPI_DATA_REG);
			break;
		}
		rxbuf += wlen;
		count -= wlen;
	}

	return 0;
}

static int qspi_transfer_msg(struct ti_qspi *qspi, struct spi_transfer *t)
{
	int ret;

	if (t->tx_buf) {
		ret = qspi_write_msg(qspi, t);
		if (ret) {
			dev_dbg(qspi->dev, "Error while writing\n");
			return ret;
		}
	}

	if (t->rx_buf) {
		ret = qspi_read_msg(qspi, t);
		if (ret) {
			dev_dbg(qspi->dev, "Error while reading\n");
			return ret;
		}
	}

	return 0;
}

static int ti_qspi_start_transfer_one(struct spi_master *master,
		struct spi_message *m)
{
	struct ti_qspi *qspi = spi_master_get_devdata(master);
	struct spi_device *spi = m->spi;
	struct spi_transfer *t;
	int status = 0, ret;
	int frame_length;

	/* setup device control reg */
	qspi->dc = 0;

	if (spi->mode & SPI_CPHA)
		qspi->dc |= QSPI_CKPHA(spi->chip_select);
	if (spi->mode & SPI_CPOL)
		qspi->dc |= QSPI_CKPOL(spi->chip_select);
	if (spi->mode & SPI_CS_HIGH)
		qspi->dc |= QSPI_CSPOL(spi->chip_select);

	frame_length = (m->frame_length << 3) / spi->bits_per_word;

	frame_length = clamp(frame_length, 0, QSPI_FRAME);

	/* setup command reg */
	qspi->cmd = 0;
	qspi->cmd |= QSPI_EN_CS(spi->chip_select);
	qspi->cmd |= QSPI_FLEN(frame_length);
	qspi->cmd |= QSPI_WC_CMD_INT_EN;

	ti_qspi_write(qspi, QSPI_WC_INT_EN, QSPI_INTR_ENABLE_SET_REG);
	ti_qspi_write(qspi, qspi->dc, QSPI_SPI_DC_REG);

	mutex_lock(&qspi->list_lock);

	list_for_each_entry(t, &m->transfers, transfer_list) {
		qspi->cmd |= QSPI_WLEN(t->bits_per_word);

		ret = qspi_transfer_msg(qspi, t);
		if (ret) {
			dev_dbg(qspi->dev, "transfer message failed\n");
			mutex_unlock(&qspi->list_lock);
			return -EINVAL;
		}

		m->actual_length += t->len;
	}

	mutex_unlock(&qspi->list_lock);

	m->status = status;
	spi_finalize_current_message(master);

	ti_qspi_write(qspi, qspi->cmd | QSPI_INVAL, QSPI_SPI_CMD_REG);

	return status;
}

static irqreturn_t ti_qspi_isr(int irq, void *dev_id)
{
	struct ti_qspi *qspi = dev_id;
	u16 int_stat;
	u32 stat;

	irqreturn_t ret = IRQ_HANDLED;

	int_stat = ti_qspi_read(qspi, QSPI_INTR_STATUS_ENABLED_CLEAR);
	stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG);

	if (!int_stat) {
		dev_dbg(qspi->dev, "No IRQ triggered\n");
		ret = IRQ_NONE;
		goto out;
	}

	ti_qspi_write(qspi, QSPI_WC_INT_DISABLE,
				QSPI_INTR_STATUS_ENABLED_CLEAR);
	if (stat & WC)
		complete(&qspi->transfer_complete);
out:
	return ret;
}

static int ti_qspi_runtime_resume(struct device *dev)
{
	struct ti_qspi      *qspi;

	qspi = dev_get_drvdata(dev);
	ti_qspi_restore_ctx(qspi);

	return 0;
}

static const struct of_device_id ti_qspi_match[] = {
	{.compatible = "ti,dra7xxx-qspi" },
	{.compatible = "ti,am4372-qspi" },
	{},
};
MODULE_DEVICE_TABLE(of, ti_qspi_match);

static int ti_qspi_probe(struct platform_device *pdev)
{
	struct  ti_qspi *qspi;
	struct spi_master *master;
	struct resource         *r, *res_ctrl, *res_mmap;
	struct device_node *np = pdev->dev.of_node;
	u32 max_freq;
	int ret = 0, num_cs, irq;

	master = spi_alloc_master(&pdev->dev, sizeof(*qspi));
	if (!master)
		return -ENOMEM;

	master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_RX_DUAL | SPI_RX_QUAD;

	master->flags = SPI_MASTER_HALF_DUPLEX;
	master->setup = ti_qspi_setup;
	master->auto_runtime_pm = true;
	master->transfer_one_message = ti_qspi_start_transfer_one;
	master->dev.of_node = pdev->dev.of_node;
	master->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(16) |
				     SPI_BPW_MASK(8);

	if (!of_property_read_u32(np, "num-cs", &num_cs))
		master->num_chipselect = num_cs;

	qspi = spi_master_get_devdata(master);
	qspi->master = master;
	qspi->dev = &pdev->dev;
	platform_set_drvdata(pdev, qspi);

	r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi_base");
	if (r == NULL) {
		r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
		if (r == NULL) {
			dev_err(&pdev->dev, "missing platform data\n");
			return -ENODEV;
		}
	}

	res_mmap = platform_get_resource_byname(pdev,
			IORESOURCE_MEM, "qspi_mmap");
	if (res_mmap == NULL) {
		res_mmap = platform_get_resource(pdev, IORESOURCE_MEM, 1);
		if (res_mmap == NULL) {
			dev_err(&pdev->dev,
				"memory mapped resource not required\n");
		}
	}

	res_ctrl = platform_get_resource_byname(pdev,
			IORESOURCE_MEM, "qspi_ctrlmod");
	if (res_ctrl == NULL) {
		res_ctrl = platform_get_resource(pdev, IORESOURCE_MEM, 2);
		if (res_ctrl == NULL) {
			dev_dbg(&pdev->dev,
				"control module resources not required\n");
		}
	}

	irq = platform_get_irq(pdev, 0);
	if (irq < 0) {
		dev_err(&pdev->dev, "no irq resource?\n");
		return irq;
	}

	mutex_init(&qspi->list_lock);

	qspi->base = devm_ioremap_resource(&pdev->dev, r);
	if (IS_ERR(qspi->base)) {
		ret = PTR_ERR(qspi->base);
		goto free_master;
	}

	if (res_ctrl) {
		qspi->ctrl_mod = true;
		qspi->ctrl_base = devm_ioremap_resource(&pdev->dev, res_ctrl);
		if (IS_ERR(qspi->ctrl_base)) {
			ret = PTR_ERR(qspi->ctrl_base);
			goto free_master;
		}
	}

	if (res_mmap) {
		qspi->mmap_base = devm_ioremap_resource(&pdev->dev, res_mmap);
		if (IS_ERR(qspi->mmap_base)) {
			ret = PTR_ERR(qspi->mmap_base);
			goto free_master;
		}
	}

	ret = devm_request_irq(&pdev->dev, irq, ti_qspi_isr, 0,
			dev_name(&pdev->dev), qspi);
	if (ret < 0) {
		dev_err(&pdev->dev, "Failed to register ISR for IRQ %d\n",
				irq);
		goto free_master;
	}

	qspi->fclk = devm_clk_get(&pdev->dev, "fck");
	if (IS_ERR(qspi->fclk)) {
		ret = PTR_ERR(qspi->fclk);
		dev_err(&pdev->dev, "could not get clk: %d\n", ret);
	}

	init_completion(&qspi->transfer_complete);

	pm_runtime_use_autosuspend(&pdev->dev);
	pm_runtime_set_autosuspend_delay(&pdev->dev, QSPI_AUTOSUSPEND_TIMEOUT);
	pm_runtime_enable(&pdev->dev);

	if (!of_property_read_u32(np, "spi-max-frequency", &max_freq))
		qspi->spi_max_frequency = max_freq;

	ret = devm_spi_register_master(&pdev->dev, master);
	if (ret)
		goto free_master;

	return 0;

free_master:
	spi_master_put(master);
	return ret;
}

static int ti_qspi_remove(struct platform_device *pdev)
{
	struct ti_qspi *qspi = platform_get_drvdata(pdev);
	int ret;

	ret = pm_runtime_get_sync(qspi->dev);
	if (ret < 0) {
		dev_err(qspi->dev, "pm_runtime_get_sync() failed\n");
		return ret;
	}

	ti_qspi_write(qspi, QSPI_WC_INT_DISABLE, QSPI_INTR_ENABLE_CLEAR_REG);

	pm_runtime_put(qspi->dev);
	pm_runtime_disable(&pdev->dev);

	return 0;
}

static const struct dev_pm_ops ti_qspi_pm_ops = {
	.runtime_resume = ti_qspi_runtime_resume,
};

static struct platform_driver ti_qspi_driver = {
	.probe	= ti_qspi_probe,
	.remove = ti_qspi_remove,
	.driver = {
		.name	= "ti-qspi",
		.pm =   &ti_qspi_pm_ops,
		.of_match_table = ti_qspi_match,
	}
};

module_platform_driver(ti_qspi_driver);

MODULE_AUTHOR("Sourav Poddar <sourav.poddar@ti.com>");
MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("TI QSPI controller driver");
MODULE_ALIAS("platform:ti-qspi");
Commit	Line	Data
505a1495 SP	1	/*
	2	* TI QSPI driver
	3	*
	4	* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
	5	* Author: Sourav Poddar <sourav.poddar@ti.com>
	6	*
	7	* This program is free software; you can redistribute it and/or
	8	* modify it under the terms of the GPLv2.
	9	*
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
	13	* GNU General Public License for more details.
	14	*/
	15
	16	#include <linux/kernel.h>
	17	#include <linux/init.h>
	18	#include <linux/interrupt.h>
	19	#include <linux/module.h>
	20	#include <linux/device.h>
	21	#include <linux/delay.h>
	22	#include <linux/dma-mapping.h>
	23	#include <linux/dmaengine.h>
	24	#include <linux/omap-dma.h>
	25	#include <linux/platform_device.h>
	26	#include <linux/err.h>
	27	#include <linux/clk.h>
	28	#include <linux/io.h>
	29	#include <linux/slab.h>
	30	#include <linux/pm_runtime.h>
	31	#include <linux/of.h>
	32	#include <linux/of_device.h>
	33	#include <linux/pinctrl/consumer.h>
	34
	35	#include <linux/spi/spi.h>
	36
	37	struct ti_qspi_regs {
	38	u32 clkctrl;
	39	};
	40
	41	struct ti_qspi {
	42	struct completion transfer_complete;
	43
505a1495 SP	44	/* list synchronization */
	45	struct mutex list_lock;
	46
	47	struct spi_master *master;
	48	void __iomem *base;
6b3938ae SP	49	void __iomem *ctrl_base;
6b3938ae SP	50	void __iomem *mmap_base;
505a1495 SP	51	struct clk *fclk;
	52	struct device *dev;
	53
	54	struct ti_qspi_regs ctx_reg;
	55
	56	u32 spi_max_frequency;
	57	u32 cmd;
	58	u32 dc;
6b3938ae SP	59
6b3938ae SP	60	bool ctrl_mod;
505a1495 SP	61	};
	62
	63	#define QSPI_PID (0x0)
	64	#define QSPI_SYSCONFIG (0x10)
	65	#define QSPI_INTR_STATUS_RAW_SET (0x20)
	66	#define QSPI_INTR_STATUS_ENABLED_CLEAR (0x24)
	67	#define QSPI_INTR_ENABLE_SET_REG (0x28)
	68	#define QSPI_INTR_ENABLE_CLEAR_REG (0x2c)
	69	#define QSPI_SPI_CLOCK_CNTRL_REG (0x40)
	70	#define QSPI_SPI_DC_REG (0x44)
	71	#define QSPI_SPI_CMD_REG (0x48)
	72	#define QSPI_SPI_STATUS_REG (0x4c)
	73	#define QSPI_SPI_DATA_REG (0x50)
	74	#define QSPI_SPI_SETUP0_REG (0x54)
	75	#define QSPI_SPI_SWITCH_REG (0x64)
	76	#define QSPI_SPI_SETUP1_REG (0x58)
	77	#define QSPI_SPI_SETUP2_REG (0x5c)
	78	#define QSPI_SPI_SETUP3_REG (0x60)
	79	#define QSPI_SPI_DATA_REG_1 (0x68)
	80	#define QSPI_SPI_DATA_REG_2 (0x6c)
	81	#define QSPI_SPI_DATA_REG_3 (0x70)
	82
	83	#define QSPI_COMPLETION_TIMEOUT msecs_to_jiffies(2000)
	84
	85	#define QSPI_FCLK 192000000
	86
	87	/* Clock Control */
	88	#define QSPI_CLK_EN (1 << 31)
	89	#define QSPI_CLK_DIV_MAX 0xffff
	90
	91	/* Command */
	92	#define QSPI_EN_CS(n) (n << 28)
	93	#define QSPI_WLEN(n) ((n - 1) << 19)
	94	#define QSPI_3_PIN (1 << 18)
	95	#define QSPI_RD_SNGL (1 << 16)
	96	#define QSPI_WR_SNGL (2 << 16)
	97	#define QSPI_RD_DUAL (3 << 16)
	98	#define QSPI_RD_QUAD (7 << 16)
	99	#define QSPI_INVAL (4 << 16)
	100	#define QSPI_WC_CMD_INT_EN (1 << 14)
	101	#define QSPI_FLEN(n) ((n - 1) << 0)
	102
	103	/* STATUS REGISTER */
00611047	104	#define BUSY 0x01
505a1495 SP	105	#define WC 0x02
	106
	107	/* INTERRUPT REGISTER */
	108	#define QSPI_WC_INT_EN (1 << 1)
	109	#define QSPI_WC_INT_DISABLE (1 << 1)
	110
	111	/* Device Control */
	112	#define QSPI_DD(m, n) (m << (3 + n * 8))
	113	#define QSPI_CKPHA(n) (1 << (2 + n * 8))
	114	#define QSPI_CSPOL(n) (1 << (1 + n * 8))
	115	#define QSPI_CKPOL(n) (1 << (n * 8))
	116
	117	#define QSPI_FRAME 4096
	118
	119	#define QSPI_AUTOSUSPEND_TIMEOUT 2000
	120
	121	static inline unsigned long ti_qspi_read(struct ti_qspi *qspi,
	122	unsigned long reg)
	123	{
	124	return readl(qspi->base + reg);
	125	}
	126
	127	static inline void ti_qspi_write(struct ti_qspi *qspi,
	128	unsigned long val, unsigned long reg)
	129	{
	130	writel(val, qspi->base + reg);
	131	}
	132
	133	static int ti_qspi_setup(struct spi_device *spi)
	134	{
	135	struct ti_qspi *qspi = spi_master_get_devdata(spi->master);
	136	struct ti_qspi_regs *ctx_reg = &qspi->ctx_reg;
	137	int clk_div = 0, ret;
	138	u32 clk_ctrl_reg, clk_rate, clk_mask;
	139
	140	if (spi->master->busy) {
	141	dev_dbg(qspi->dev, "master busy doing other trasnfers\n");
	142	return -EBUSY;
	143	}
	144
	145	if (!qspi->spi_max_frequency) {
	146	dev_err(qspi->dev, "spi max frequency not defined\n");
	147	return -EINVAL;
	148	}
	149
	150	clk_rate = clk_get_rate(qspi->fclk);
	151
	152	clk_div = DIV_ROUND_UP(clk_rate, qspi->spi_max_frequency) - 1;
	153
	154	if (clk_div < 0) {
	155	dev_dbg(qspi->dev, "clock divider < 0, using /1 divider\n");
	156	return -EINVAL;
	157	}
	158
	159	if (clk_div > QSPI_CLK_DIV_MAX) {
	160	dev_dbg(qspi->dev, "clock divider >%d , using /%d divider\n",
	161	QSPI_CLK_DIV_MAX, QSPI_CLK_DIV_MAX + 1);
	162	return -EINVAL;
	163	}
	164
	165	dev_dbg(qspi->dev, "hz: %d, clock divider %d\n",
	166	qspi->spi_max_frequency, clk_div);
	167
	168	ret = pm_runtime_get_sync(qspi->dev);
05b96675	169	if (ret < 0) {
505a1495 SP	170	dev_err(qspi->dev, "pm_runtime_get_sync() failed\n");
	171	return ret;
	172	}
	173
	174	clk_ctrl_reg = ti_qspi_read(qspi, QSPI_SPI_CLOCK_CNTRL_REG);
	175
	176	clk_ctrl_reg &= ~QSPI_CLK_EN;
	177
	178	/* disable SCLK */
	179	ti_qspi_write(qspi, clk_ctrl_reg, QSPI_SPI_CLOCK_CNTRL_REG);
	180
	181	/* enable SCLK */
	182	clk_mask = QSPI_CLK_EN \| clk_div;
	183	ti_qspi_write(qspi, clk_mask, QSPI_SPI_CLOCK_CNTRL_REG);
	184	ctx_reg->clkctrl = clk_mask;
	185
	186	pm_runtime_mark_last_busy(qspi->dev);
	187	ret = pm_runtime_put_autosuspend(qspi->dev);
	188	if (ret < 0) {
	189	dev_err(qspi->dev, "pm_runtime_put_autosuspend() failed\n");
	190	return ret;
	191	}
	192
	193	return 0;
	194	}
	195
	196	static void ti_qspi_restore_ctx(struct ti_qspi *qspi)
	197	{
	198	struct ti_qspi_regs *ctx_reg = &qspi->ctx_reg;
	199
	200	ti_qspi_write(qspi, ctx_reg->clkctrl, QSPI_SPI_CLOCK_CNTRL_REG);
	201	}
	202
00611047 M	203	static inline u32 qspi_is_busy(struct ti_qspi *qspi)
	204	{
	205	u32 stat;
	206	unsigned long timeout = jiffies + QSPI_COMPLETION_TIMEOUT;
	207
	208	stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG);
	209	while ((stat & BUSY) && time_after(timeout, jiffies)) {
	210	cpu_relax();
	211	stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG);
	212	}
	213
	214	WARN(stat & BUSY, "qspi busy\n");
	215	return stat & BUSY;
	216	}
	217
505a1495 SP	218	static int qspi_write_msg(struct ti_qspi qspi, struct spi_transfer t)
505a1495 SP	219	{
060556a9	220	int wlen, count;
505a1495 SP	221	unsigned int cmd;
	222	const u8 *txbuf;
	223
	224	txbuf = t->tx_buf;
	225	cmd = qspi->cmd \| QSPI_WR_SNGL;
	226	count = t->len;
3ab54620	227	wlen = t->bits_per_word >> 3; /* in bytes */
505a1495 SP	228
505a1495 SP	229	while (count) {
00611047 M	230	if (qspi_is_busy(qspi))
	231	return -EBUSY;
	232
505a1495	233	switch (wlen) {
3ab54620	234	case 1:
505a1495 SP	235	dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %02x\n",
	236	cmd, qspi->dc, *txbuf);
	237	writeb(*txbuf, qspi->base + QSPI_SPI_DATA_REG);
505a1495	238	break;
3ab54620	239	case 2:
505a1495 SP	240	dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %04x\n",
	241	cmd, qspi->dc, *txbuf);
	242	writew(((u16 )txbuf), qspi->base + QSPI_SPI_DATA_REG);
505a1495	243	break;
3ab54620	244	case 4:
505a1495 SP	245	dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %08x\n",
	246	cmd, qspi->dc, *txbuf);
	247	writel(((u32 )txbuf), qspi->base + QSPI_SPI_DATA_REG);
505a1495 SP	248	break;
505a1495 SP	249	}
3ab54620 AL	250
3ab54620 AL	251	ti_qspi_write(qspi, cmd, QSPI_SPI_CMD_REG);
060556a9 NMG	252	if (!wait_for_completion_timeout(&qspi->transfer_complete,
060556a9 NMG	253	QSPI_COMPLETION_TIMEOUT)) {
3ab54620 AL	254	dev_err(qspi->dev, "write timed out\n");
	255	return -ETIMEDOUT;
	256	}
	257	txbuf += wlen;
	258	count -= wlen;
505a1495 SP	259	}
	260
	261	return 0;
	262	}
	263
	264	static int qspi_read_msg(struct ti_qspi qspi, struct spi_transfer t)
	265	{
060556a9	266	int wlen, count;
505a1495 SP	267	unsigned int cmd;
	268	u8 *rxbuf;
	269
	270	rxbuf = t->rx_buf;
70e2e976 SP	271	cmd = qspi->cmd;
	272	switch (t->rx_nbits) {
	273	case SPI_NBITS_DUAL:
	274	cmd \|= QSPI_RD_DUAL;
	275	break;
	276	case SPI_NBITS_QUAD:
	277	cmd \|= QSPI_RD_QUAD;
	278	break;
	279	default:
	280	cmd \|= QSPI_RD_SNGL;
	281	break;
	282	}
505a1495	283	count = t->len;
3ab54620	284	wlen = t->bits_per_word >> 3; /* in bytes */
505a1495 SP	285
	286	while (count) {
	287	dev_dbg(qspi->dev, "rx cmd %08x dc %08x\n", cmd, qspi->dc);
00611047 M	288	if (qspi_is_busy(qspi))
	289	return -EBUSY;
	290
505a1495	291	ti_qspi_write(qspi, cmd, QSPI_SPI_CMD_REG);
060556a9 NMG	292	if (!wait_for_completion_timeout(&qspi->transfer_complete,
060556a9 NMG	293	QSPI_COMPLETION_TIMEOUT)) {
505a1495 SP	294	dev_err(qspi->dev, "read timed out\n");
	295	return -ETIMEDOUT;
	296	}
	297	switch (wlen) {
3ab54620	298	case 1:
505a1495	299	*rxbuf = readb(qspi->base + QSPI_SPI_DATA_REG);
505a1495	300	break;
3ab54620	301	case 2:
505a1495	302	((u16 )rxbuf) = readw(qspi->base + QSPI_SPI_DATA_REG);
505a1495	303	break;
3ab54620	304	case 4:
505a1495	305	((u32 )rxbuf) = readl(qspi->base + QSPI_SPI_DATA_REG);
505a1495 SP	306	break;
505a1495 SP	307	}
3ab54620 AL	308	rxbuf += wlen;
3ab54620 AL	309	count -= wlen;
505a1495 SP	310	}
	311
	312	return 0;
	313	}
	314
	315	static int qspi_transfer_msg(struct ti_qspi qspi, struct spi_transfer t)
	316	{
	317	int ret;
	318
	319	if (t->tx_buf) {
	320	ret = qspi_write_msg(qspi, t);
	321	if (ret) {
	322	dev_dbg(qspi->dev, "Error while writing\n");
	323	return ret;
	324	}
	325	}
	326
	327	if (t->rx_buf) {
	328	ret = qspi_read_msg(qspi, t);
	329	if (ret) {
	330	dev_dbg(qspi->dev, "Error while reading\n");
	331	return ret;
	332	}
	333	}
	334
	335	return 0;
	336	}
	337
	338	static int ti_qspi_start_transfer_one(struct spi_master *master,
	339	struct spi_message *m)
	340	{
	341	struct ti_qspi *qspi = spi_master_get_devdata(master);
	342	struct spi_device *spi = m->spi;
	343	struct spi_transfer *t;
	344	int status = 0, ret;
	345	int frame_length;
	346
	347	/* setup device control reg */
	348	qspi->dc = 0;
	349
	350	if (spi->mode & SPI_CPHA)
	351	qspi->dc \|= QSPI_CKPHA(spi->chip_select);
	352	if (spi->mode & SPI_CPOL)
	353	qspi->dc \|= QSPI_CKPOL(spi->chip_select);
	354	if (spi->mode & SPI_CS_HIGH)
	355	qspi->dc \|= QSPI_CSPOL(spi->chip_select);
	356
	357	frame_length = (m->frame_length << 3) / spi->bits_per_word;
	358
	359	frame_length = clamp(frame_length, 0, QSPI_FRAME);
	360
	361	/* setup command reg */
	362	qspi->cmd = 0;
	363	qspi->cmd \|= QSPI_EN_CS(spi->chip_select);
	364	qspi->cmd \|= QSPI_FLEN(frame_length);
	365	qspi->cmd \|= QSPI_WC_CMD_INT_EN;
	366
	367	ti_qspi_write(qspi, QSPI_WC_INT_EN, QSPI_INTR_ENABLE_SET_REG);
	368	ti_qspi_write(qspi, qspi->dc, QSPI_SPI_DC_REG);
	369
	370	mutex_lock(&qspi->list_lock);
	371
	372	list_for_each_entry(t, &m->transfers, transfer_list) {
	373	qspi->cmd \|= QSPI_WLEN(t->bits_per_word);
374
375	ret = qspi_transfer_msg(qspi, t);
376	if (ret) {
377	dev_dbg(qspi->dev, "transfer message failed\n");
b6460366	378	mutex_unlock(&qspi->list_lock);
505a1495 SP	379	return -EINVAL;
	380	}
	381
	382	m->actual_length += t->len;
	383	}
	384
	385	mutex_unlock(&qspi->list_lock);
	386
	387	m->status = status;
	388	spi_finalize_current_message(master);
	389
	390	ti_qspi_write(qspi, qspi->cmd \| QSPI_INVAL, QSPI_SPI_CMD_REG);
	391
	392	return status;
	393	}
	394
	395	static irqreturn_t ti_qspi_isr(int irq, void *dev_id)
	396	{
	397	struct ti_qspi *qspi = dev_id;
	398	u16 int_stat;
3b3a8001	399	u32 stat;
505a1495 SP	400
	401	irqreturn_t ret = IRQ_HANDLED;
	402
505a1495	403	int_stat = ti_qspi_read(qspi, QSPI_INTR_STATUS_ENABLED_CLEAR);
3b3a8001	404	stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG);
505a1495 SP	405
	406	if (!int_stat) {
	407	dev_dbg(qspi->dev, "No IRQ triggered\n");
	408	ret = IRQ_NONE;
	409	goto out;
	410	}
	411
505a1495 SP	412	ti_qspi_write(qspi, QSPI_WC_INT_DISABLE,
505a1495 SP	413	QSPI_INTR_STATUS_ENABLED_CLEAR);
3b3a8001 SAS	414	if (stat & WC)
3b3a8001 SAS	415	complete(&qspi->transfer_complete);
505a1495	416	out:
505a1495 SP	417	return ret;
	418	}
	419
505a1495 SP	420	static int ti_qspi_runtime_resume(struct device *dev)
	421	{
	422	struct ti_qspi *qspi;
505a1495	423
f17414c4	424	qspi = dev_get_drvdata(dev);
505a1495 SP	425	ti_qspi_restore_ctx(qspi);
	426
	427	return 0;
	428	}
	429
	430	static const struct of_device_id ti_qspi_match[] = {
	431	{.compatible = "ti,dra7xxx-qspi" },
09222fc3	432	{.compatible = "ti,am4372-qspi" },
505a1495 SP	433	{},
505a1495 SP	434	};
e1432d30	435	MODULE_DEVICE_TABLE(of, ti_qspi_match);
505a1495 SP	436
	437	static int ti_qspi_probe(struct platform_device *pdev)
	438	{
	439	struct ti_qspi *qspi;
	440	struct spi_master *master;
6b3938ae	441	struct resource r, res_ctrl, *res_mmap;
505a1495 SP	442	struct device_node *np = pdev->dev.of_node;
	443	u32 max_freq;
	444	int ret = 0, num_cs, irq;
	445
	446	master = spi_alloc_master(&pdev->dev, sizeof(*qspi));
	447	if (!master)
	448	return -ENOMEM;
	449
633795b9	450	master->mode_bits = SPI_CPOL \| SPI_CPHA \| SPI_RX_DUAL \| SPI_RX_QUAD;
505a1495	451
505a1495 SP	452	master->flags = SPI_MASTER_HALF_DUPLEX;
	453	master->setup = ti_qspi_setup;
	454	master->auto_runtime_pm = true;
	455	master->transfer_one_message = ti_qspi_start_transfer_one;
	456	master->dev.of_node = pdev->dev.of_node;
aa188f90 AL	457	master->bits_per_word_mask = SPI_BPW_MASK(32) \| SPI_BPW_MASK(16) \|
aa188f90 AL	458	SPI_BPW_MASK(8);
505a1495 SP	459
	460	if (!of_property_read_u32(np, "num-cs", &num_cs))
	461	master->num_chipselect = num_cs;
	462
505a1495 SP	463	qspi = spi_master_get_devdata(master);
	464	qspi->master = master;
	465	qspi->dev = &pdev->dev;
160a0613	466	platform_set_drvdata(pdev, qspi);
505a1495	467
6b3938ae SP	468	r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi_base");
	469	if (r == NULL) {
	470	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	471	if (r == NULL) {
	472	dev_err(&pdev->dev, "missing platform data\n");
	473	return -ENODEV;
	474	}
	475	}
505a1495	476
6b3938ae SP	477	res_mmap = platform_get_resource_byname(pdev,
	478	IORESOURCE_MEM, "qspi_mmap");
	479	if (res_mmap == NULL) {
	480	res_mmap = platform_get_resource(pdev, IORESOURCE_MEM, 1);
	481	if (res_mmap == NULL) {
	482	dev_err(&pdev->dev,
	483	"memory mapped resource not required\n");
6b3938ae SP	484	}
	485	}
	486
	487	res_ctrl = platform_get_resource_byname(pdev,
	488	IORESOURCE_MEM, "qspi_ctrlmod");
	489	if (res_ctrl == NULL) {
	490	res_ctrl = platform_get_resource(pdev, IORESOURCE_MEM, 2);
	491	if (res_ctrl == NULL) {
	492	dev_dbg(&pdev->dev,
	493	"control module resources not required\n");
	494	}
	495	}
505a1495 SP	496
	497	irq = platform_get_irq(pdev, 0);
	498	if (irq < 0) {
	499	dev_err(&pdev->dev, "no irq resource?\n");
	500	return irq;
	501	}
	502
505a1495 SP	503	mutex_init(&qspi->list_lock);
	504
	505	qspi->base = devm_ioremap_resource(&pdev->dev, r);
	506	if (IS_ERR(qspi->base)) {
	507	ret = PTR_ERR(qspi->base);
	508	goto free_master;
	509	}
	510
6b3938ae SP	511	if (res_ctrl) {
	512	qspi->ctrl_mod = true;
	513	qspi->ctrl_base = devm_ioremap_resource(&pdev->dev, res_ctrl);
	514	if (IS_ERR(qspi->ctrl_base)) {
	515	ret = PTR_ERR(qspi->ctrl_base);
	516	goto free_master;
	517	}
	518	}
	519
	520	if (res_mmap) {
	521	qspi->mmap_base = devm_ioremap_resource(&pdev->dev, res_mmap);
	522	if (IS_ERR(qspi->mmap_base)) {
	523	ret = PTR_ERR(qspi->mmap_base);
	524	goto free_master;
	525	}
	526	}
	527
3b3a8001	528	ret = devm_request_irq(&pdev->dev, irq, ti_qspi_isr, 0,
505a1495 SP	529	dev_name(&pdev->dev), qspi);
	530	if (ret < 0) {
	531	dev_err(&pdev->dev, "Failed to register ISR for IRQ %d\n",
	532	irq);
	533	goto free_master;
	534	}
	535
	536	qspi->fclk = devm_clk_get(&pdev->dev, "fck");
	537	if (IS_ERR(qspi->fclk)) {
	538	ret = PTR_ERR(qspi->fclk);
	539	dev_err(&pdev->dev, "could not get clk: %d\n", ret);
	540	}
	541
	542	init_completion(&qspi->transfer_complete);
	543
	544	pm_runtime_use_autosuspend(&pdev->dev);
	545	pm_runtime_set_autosuspend_delay(&pdev->dev, QSPI_AUTOSUSPEND_TIMEOUT);
	546	pm_runtime_enable(&pdev->dev);
	547
	548	if (!of_property_read_u32(np, "spi-max-frequency", &max_freq))
	549	qspi->spi_max_frequency = max_freq;
	550
7388c03b	551	ret = devm_spi_register_master(&pdev->dev, master);
505a1495 SP	552	if (ret)
	553	goto free_master;
	554
	555	return 0;
	556
	557	free_master:
	558	spi_master_put(master);
	559	return ret;
	560	}
	561
	562	static int ti_qspi_remove(struct platform_device *pdev)
	563	{
e3d8bee3	564	struct ti_qspi *qspi = platform_get_drvdata(pdev);
cbcabb7a SP	565	int ret;
cbcabb7a SP	566
cbcabb7a SP	567	ret = pm_runtime_get_sync(qspi->dev);
	568	if (ret < 0) {
	569	dev_err(qspi->dev, "pm_runtime_get_sync() failed\n");
	570	return ret;
	571	}
505a1495	572
3b3a8001	573	ti_qspi_write(qspi, QSPI_WC_INT_DISABLE, QSPI_INTR_ENABLE_CLEAR_REG);
505a1495	574
cbcabb7a SP	575	pm_runtime_put(qspi->dev);
	576	pm_runtime_disable(&pdev->dev);
	577
505a1495 SP	578	return 0;
	579	}
	580
	581	static const struct dev_pm_ops ti_qspi_pm_ops = {
	582	.runtime_resume = ti_qspi_runtime_resume,
	583	};
	584
	585	static struct platform_driver ti_qspi_driver = {
	586	.probe = ti_qspi_probe,
dabefd56	587	.remove = ti_qspi_remove,
505a1495	588	.driver = {
5a33d30f	589	.name = "ti-qspi",
505a1495 SP	590	.pm = &ti_qspi_pm_ops,
	591	.of_match_table = ti_qspi_match,
	592	}
	593	};
	594
	595	module_platform_driver(ti_qspi_driver);
	596
	597	MODULE_AUTHOR("Sourav Poddar <sourav.poddar@ti.com>");
	598	MODULE_LICENSE("GPL v2");
	599	MODULE_DESCRIPTION("TI QSPI controller driver");
5a33d30f	600	MODULE_ALIAS("platform:ti-qspi");