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c942fddf | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
b43d65f7 | 2 | /* |
b43d65f7 LW |
3 | * A driver for the ARM PL022 PrimeCell SSP/SPI bus master. |
4 | * | |
aeef9915 | 5 | * Copyright (C) 2008-2012 ST-Ericsson AB |
b43d65f7 LW |
6 | * Copyright (C) 2006 STMicroelectronics Pvt. Ltd. |
7 | * | |
8 | * Author: Linus Walleij <linus.walleij@stericsson.com> | |
9 | * | |
10 | * Initial version inspired by: | |
11 | * linux-2.6.17-rc3-mm1/drivers/spi/pxa2xx_spi.c | |
12 | * Initial adoption to PL022 by: | |
13 | * Sachin Verma <sachin.verma@st.com> | |
b43d65f7 LW |
14 | */ |
15 | ||
b43d65f7 LW |
16 | #include <linux/init.h> |
17 | #include <linux/module.h> | |
18 | #include <linux/device.h> | |
19 | #include <linux/ioport.h> | |
20 | #include <linux/errno.h> | |
21 | #include <linux/interrupt.h> | |
22 | #include <linux/spi/spi.h> | |
b43d65f7 LW |
23 | #include <linux/delay.h> |
24 | #include <linux/clk.h> | |
25 | #include <linux/err.h> | |
26 | #include <linux/amba/bus.h> | |
27 | #include <linux/amba/pl022.h> | |
28 | #include <linux/io.h> | |
5a0e3ad6 | 29 | #include <linux/slab.h> |
b1b6b9aa LW |
30 | #include <linux/dmaengine.h> |
31 | #include <linux/dma-mapping.h> | |
32 | #include <linux/scatterlist.h> | |
bcda6ff8 | 33 | #include <linux/pm_runtime.h> |
f6f46de1 | 34 | #include <linux/gpio.h> |
6d3952a7 | 35 | #include <linux/of_gpio.h> |
4f5e1b37 | 36 | #include <linux/pinctrl/consumer.h> |
b43d65f7 LW |
37 | |
38 | /* | |
39 | * This macro is used to define some register default values. | |
40 | * reg is masked with mask, the OR:ed with an (again masked) | |
41 | * val shifted sb steps to the left. | |
42 | */ | |
43 | #define SSP_WRITE_BITS(reg, val, mask, sb) \ | |
44 | ((reg) = (((reg) & ~(mask)) | (((val)<<(sb)) & (mask)))) | |
45 | ||
46 | /* | |
47 | * This macro is also used to define some default values. | |
48 | * It will just shift val by sb steps to the left and mask | |
49 | * the result with mask. | |
50 | */ | |
51 | #define GEN_MASK_BITS(val, mask, sb) \ | |
52 | (((val)<<(sb)) & (mask)) | |
53 | ||
54 | #define DRIVE_TX 0 | |
55 | #define DO_NOT_DRIVE_TX 1 | |
56 | ||
57 | #define DO_NOT_QUEUE_DMA 0 | |
58 | #define QUEUE_DMA 1 | |
59 | ||
60 | #define RX_TRANSFER 1 | |
61 | #define TX_TRANSFER 2 | |
62 | ||
63 | /* | |
64 | * Macros to access SSP Registers with their offsets | |
65 | */ | |
66 | #define SSP_CR0(r) (r + 0x000) | |
67 | #define SSP_CR1(r) (r + 0x004) | |
68 | #define SSP_DR(r) (r + 0x008) | |
69 | #define SSP_SR(r) (r + 0x00C) | |
70 | #define SSP_CPSR(r) (r + 0x010) | |
71 | #define SSP_IMSC(r) (r + 0x014) | |
72 | #define SSP_RIS(r) (r + 0x018) | |
73 | #define SSP_MIS(r) (r + 0x01C) | |
74 | #define SSP_ICR(r) (r + 0x020) | |
75 | #define SSP_DMACR(r) (r + 0x024) | |
db4fa45e | 76 | #define SSP_CSR(r) (r + 0x030) /* vendor extension */ |
b43d65f7 LW |
77 | #define SSP_ITCR(r) (r + 0x080) |
78 | #define SSP_ITIP(r) (r + 0x084) | |
79 | #define SSP_ITOP(r) (r + 0x088) | |
80 | #define SSP_TDR(r) (r + 0x08C) | |
81 | ||
82 | #define SSP_PID0(r) (r + 0xFE0) | |
83 | #define SSP_PID1(r) (r + 0xFE4) | |
84 | #define SSP_PID2(r) (r + 0xFE8) | |
85 | #define SSP_PID3(r) (r + 0xFEC) | |
86 | ||
87 | #define SSP_CID0(r) (r + 0xFF0) | |
88 | #define SSP_CID1(r) (r + 0xFF4) | |
89 | #define SSP_CID2(r) (r + 0xFF8) | |
90 | #define SSP_CID3(r) (r + 0xFFC) | |
91 | ||
92 | /* | |
93 | * SSP Control Register 0 - SSP_CR0 | |
94 | */ | |
556f4aeb LW |
95 | #define SSP_CR0_MASK_DSS (0x0FUL << 0) |
96 | #define SSP_CR0_MASK_FRF (0x3UL << 4) | |
b43d65f7 LW |
97 | #define SSP_CR0_MASK_SPO (0x1UL << 6) |
98 | #define SSP_CR0_MASK_SPH (0x1UL << 7) | |
99 | #define SSP_CR0_MASK_SCR (0xFFUL << 8) | |
556f4aeb LW |
100 | |
101 | /* | |
102 | * The ST version of this block moves som bits | |
103 | * in SSP_CR0 and extends it to 32 bits | |
104 | */ | |
105 | #define SSP_CR0_MASK_DSS_ST (0x1FUL << 0) | |
106 | #define SSP_CR0_MASK_HALFDUP_ST (0x1UL << 5) | |
107 | #define SSP_CR0_MASK_CSS_ST (0x1FUL << 16) | |
108 | #define SSP_CR0_MASK_FRF_ST (0x3UL << 21) | |
109 | ||
b43d65f7 LW |
110 | /* |
111 | * SSP Control Register 0 - SSP_CR1 | |
112 | */ | |
113 | #define SSP_CR1_MASK_LBM (0x1UL << 0) | |
114 | #define SSP_CR1_MASK_SSE (0x1UL << 1) | |
115 | #define SSP_CR1_MASK_MS (0x1UL << 2) | |
116 | #define SSP_CR1_MASK_SOD (0x1UL << 3) | |
b43d65f7 LW |
117 | |
118 | /* | |
556f4aeb LW |
119 | * The ST version of this block adds some bits |
120 | * in SSP_CR1 | |
b43d65f7 | 121 | */ |
556f4aeb LW |
122 | #define SSP_CR1_MASK_RENDN_ST (0x1UL << 4) |
123 | #define SSP_CR1_MASK_TENDN_ST (0x1UL << 5) | |
124 | #define SSP_CR1_MASK_MWAIT_ST (0x1UL << 6) | |
125 | #define SSP_CR1_MASK_RXIFLSEL_ST (0x7UL << 7) | |
126 | #define SSP_CR1_MASK_TXIFLSEL_ST (0x7UL << 10) | |
781c7b12 LW |
127 | /* This one is only in the PL023 variant */ |
128 | #define SSP_CR1_MASK_FBCLKDEL_ST (0x7UL << 13) | |
b43d65f7 LW |
129 | |
130 | /* | |
131 | * SSP Status Register - SSP_SR | |
132 | */ | |
133 | #define SSP_SR_MASK_TFE (0x1UL << 0) /* Transmit FIFO empty */ | |
134 | #define SSP_SR_MASK_TNF (0x1UL << 1) /* Transmit FIFO not full */ | |
135 | #define SSP_SR_MASK_RNE (0x1UL << 2) /* Receive FIFO not empty */ | |
556f4aeb | 136 | #define SSP_SR_MASK_RFF (0x1UL << 3) /* Receive FIFO full */ |
b43d65f7 LW |
137 | #define SSP_SR_MASK_BSY (0x1UL << 4) /* Busy Flag */ |
138 | ||
139 | /* | |
140 | * SSP Clock Prescale Register - SSP_CPSR | |
141 | */ | |
142 | #define SSP_CPSR_MASK_CPSDVSR (0xFFUL << 0) | |
143 | ||
144 | /* | |
145 | * SSP Interrupt Mask Set/Clear Register - SSP_IMSC | |
146 | */ | |
147 | #define SSP_IMSC_MASK_RORIM (0x1UL << 0) /* Receive Overrun Interrupt mask */ | |
148 | #define SSP_IMSC_MASK_RTIM (0x1UL << 1) /* Receive timeout Interrupt mask */ | |
149 | #define SSP_IMSC_MASK_RXIM (0x1UL << 2) /* Receive FIFO Interrupt mask */ | |
150 | #define SSP_IMSC_MASK_TXIM (0x1UL << 3) /* Transmit FIFO Interrupt mask */ | |
151 | ||
152 | /* | |
153 | * SSP Raw Interrupt Status Register - SSP_RIS | |
154 | */ | |
155 | /* Receive Overrun Raw Interrupt status */ | |
156 | #define SSP_RIS_MASK_RORRIS (0x1UL << 0) | |
157 | /* Receive Timeout Raw Interrupt status */ | |
158 | #define SSP_RIS_MASK_RTRIS (0x1UL << 1) | |
159 | /* Receive FIFO Raw Interrupt status */ | |
160 | #define SSP_RIS_MASK_RXRIS (0x1UL << 2) | |
161 | /* Transmit FIFO Raw Interrupt status */ | |
162 | #define SSP_RIS_MASK_TXRIS (0x1UL << 3) | |
163 | ||
164 | /* | |
165 | * SSP Masked Interrupt Status Register - SSP_MIS | |
166 | */ | |
167 | /* Receive Overrun Masked Interrupt status */ | |
168 | #define SSP_MIS_MASK_RORMIS (0x1UL << 0) | |
169 | /* Receive Timeout Masked Interrupt status */ | |
170 | #define SSP_MIS_MASK_RTMIS (0x1UL << 1) | |
171 | /* Receive FIFO Masked Interrupt status */ | |
172 | #define SSP_MIS_MASK_RXMIS (0x1UL << 2) | |
173 | /* Transmit FIFO Masked Interrupt status */ | |
174 | #define SSP_MIS_MASK_TXMIS (0x1UL << 3) | |
175 | ||
176 | /* | |
177 | * SSP Interrupt Clear Register - SSP_ICR | |
178 | */ | |
179 | /* Receive Overrun Raw Clear Interrupt bit */ | |
180 | #define SSP_ICR_MASK_RORIC (0x1UL << 0) | |
181 | /* Receive Timeout Clear Interrupt bit */ | |
182 | #define SSP_ICR_MASK_RTIC (0x1UL << 1) | |
183 | ||
184 | /* | |
185 | * SSP DMA Control Register - SSP_DMACR | |
186 | */ | |
187 | /* Receive DMA Enable bit */ | |
188 | #define SSP_DMACR_MASK_RXDMAE (0x1UL << 0) | |
189 | /* Transmit DMA Enable bit */ | |
190 | #define SSP_DMACR_MASK_TXDMAE (0x1UL << 1) | |
191 | ||
db4fa45e AB |
192 | /* |
193 | * SSP Chip Select Control Register - SSP_CSR | |
194 | * (vendor extension) | |
195 | */ | |
196 | #define SSP_CSR_CSVALUE_MASK (0x1FUL << 0) | |
197 | ||
b43d65f7 LW |
198 | /* |
199 | * SSP Integration Test control Register - SSP_ITCR | |
200 | */ | |
201 | #define SSP_ITCR_MASK_ITEN (0x1UL << 0) | |
202 | #define SSP_ITCR_MASK_TESTFIFO (0x1UL << 1) | |
203 | ||
204 | /* | |
205 | * SSP Integration Test Input Register - SSP_ITIP | |
206 | */ | |
207 | #define ITIP_MASK_SSPRXD (0x1UL << 0) | |
208 | #define ITIP_MASK_SSPFSSIN (0x1UL << 1) | |
209 | #define ITIP_MASK_SSPCLKIN (0x1UL << 2) | |
210 | #define ITIP_MASK_RXDMAC (0x1UL << 3) | |
211 | #define ITIP_MASK_TXDMAC (0x1UL << 4) | |
212 | #define ITIP_MASK_SSPTXDIN (0x1UL << 5) | |
213 | ||
214 | /* | |
215 | * SSP Integration Test output Register - SSP_ITOP | |
216 | */ | |
217 | #define ITOP_MASK_SSPTXD (0x1UL << 0) | |
218 | #define ITOP_MASK_SSPFSSOUT (0x1UL << 1) | |
219 | #define ITOP_MASK_SSPCLKOUT (0x1UL << 2) | |
220 | #define ITOP_MASK_SSPOEn (0x1UL << 3) | |
221 | #define ITOP_MASK_SSPCTLOEn (0x1UL << 4) | |
222 | #define ITOP_MASK_RORINTR (0x1UL << 5) | |
223 | #define ITOP_MASK_RTINTR (0x1UL << 6) | |
224 | #define ITOP_MASK_RXINTR (0x1UL << 7) | |
225 | #define ITOP_MASK_TXINTR (0x1UL << 8) | |
226 | #define ITOP_MASK_INTR (0x1UL << 9) | |
227 | #define ITOP_MASK_RXDMABREQ (0x1UL << 10) | |
228 | #define ITOP_MASK_RXDMASREQ (0x1UL << 11) | |
229 | #define ITOP_MASK_TXDMABREQ (0x1UL << 12) | |
230 | #define ITOP_MASK_TXDMASREQ (0x1UL << 13) | |
231 | ||
232 | /* | |
233 | * SSP Test Data Register - SSP_TDR | |
234 | */ | |
556f4aeb | 235 | #define TDR_MASK_TESTDATA (0xFFFFFFFF) |
b43d65f7 LW |
236 | |
237 | /* | |
238 | * Message State | |
239 | * we use the spi_message.state (void *) pointer to | |
240 | * hold a single state value, that's why all this | |
241 | * (void *) casting is done here. | |
242 | */ | |
556f4aeb LW |
243 | #define STATE_START ((void *) 0) |
244 | #define STATE_RUNNING ((void *) 1) | |
245 | #define STATE_DONE ((void *) 2) | |
246 | #define STATE_ERROR ((void *) -1) | |
7aef2b64 | 247 | #define STATE_TIMEOUT ((void *) -2) |
b43d65f7 | 248 | |
b43d65f7 LW |
249 | /* |
250 | * SSP State - Whether Enabled or Disabled | |
251 | */ | |
556f4aeb LW |
252 | #define SSP_DISABLED (0) |
253 | #define SSP_ENABLED (1) | |
b43d65f7 LW |
254 | |
255 | /* | |
256 | * SSP DMA State - Whether DMA Enabled or Disabled | |
257 | */ | |
556f4aeb LW |
258 | #define SSP_DMA_DISABLED (0) |
259 | #define SSP_DMA_ENABLED (1) | |
b43d65f7 LW |
260 | |
261 | /* | |
262 | * SSP Clock Defaults | |
263 | */ | |
556f4aeb LW |
264 | #define SSP_DEFAULT_CLKRATE 0x2 |
265 | #define SSP_DEFAULT_PRESCALE 0x40 | |
b43d65f7 LW |
266 | |
267 | /* | |
268 | * SSP Clock Parameter ranges | |
269 | */ | |
270 | #define CPSDVR_MIN 0x02 | |
271 | #define CPSDVR_MAX 0xFE | |
272 | #define SCR_MIN 0x00 | |
273 | #define SCR_MAX 0xFF | |
274 | ||
275 | /* | |
276 | * SSP Interrupt related Macros | |
277 | */ | |
278 | #define DEFAULT_SSP_REG_IMSC 0x0UL | |
279 | #define DISABLE_ALL_INTERRUPTS DEFAULT_SSP_REG_IMSC | |
85fa4e1f AS |
280 | #define ENABLE_ALL_INTERRUPTS ( \ |
281 | SSP_IMSC_MASK_RORIM | \ | |
282 | SSP_IMSC_MASK_RTIM | \ | |
283 | SSP_IMSC_MASK_RXIM | \ | |
284 | SSP_IMSC_MASK_TXIM \ | |
285 | ) | |
b43d65f7 LW |
286 | |
287 | #define CLEAR_ALL_INTERRUPTS 0x3 | |
288 | ||
a18c266f MT |
289 | #define SPI_POLLING_TIMEOUT 1000 |
290 | ||
b43d65f7 LW |
291 | /* |
292 | * The type of reading going on on this chip | |
293 | */ | |
294 | enum ssp_reading { | |
295 | READING_NULL, | |
296 | READING_U8, | |
297 | READING_U16, | |
298 | READING_U32 | |
299 | }; | |
300 | ||
301 | /** | |
302 | * The type of writing going on on this chip | |
303 | */ | |
304 | enum ssp_writing { | |
305 | WRITING_NULL, | |
306 | WRITING_U8, | |
307 | WRITING_U16, | |
308 | WRITING_U32 | |
309 | }; | |
310 | ||
311 | /** | |
312 | * struct vendor_data - vendor-specific config parameters | |
313 | * for PL022 derivates | |
314 | * @fifodepth: depth of FIFOs (both) | |
315 | * @max_bpw: maximum number of bits per word | |
316 | * @unidir: supports unidirection transfers | |
556f4aeb LW |
317 | * @extended_cr: 32 bit wide control register 0 with extra |
318 | * features and extra features in CR1 as found in the ST variants | |
781c7b12 | 319 | * @pl023: supports a subset of the ST extensions called "PL023" |
db4fa45e | 320 | * @internal_cs_ctrl: supports chip select control register |
b43d65f7 LW |
321 | */ |
322 | struct vendor_data { | |
323 | int fifodepth; | |
324 | int max_bpw; | |
325 | bool unidir; | |
556f4aeb | 326 | bool extended_cr; |
781c7b12 | 327 | bool pl023; |
06fb01fd | 328 | bool loopback; |
db4fa45e | 329 | bool internal_cs_ctrl; |
b43d65f7 LW |
330 | }; |
331 | ||
332 | /** | |
333 | * struct pl022 - This is the private SSP driver data structure | |
334 | * @adev: AMBA device model hookup | |
12e8b325 LW |
335 | * @vendor: vendor data for the IP block |
336 | * @phybase: the physical memory where the SSP device resides | |
337 | * @virtbase: the virtual memory where the SSP is mapped | |
338 | * @clk: outgoing clock "SPICLK" for the SPI bus | |
b43d65f7 LW |
339 | * @master: SPI framework hookup |
340 | * @master_info: controller-specific data from machine setup | |
b43d65f7 LW |
341 | * @pump_transfers: Tasklet used in Interrupt Transfer mode |
342 | * @cur_msg: Pointer to current spi_message being processed | |
343 | * @cur_transfer: Pointer to current spi_transfer | |
344 | * @cur_chip: pointer to current clients chip(assigned from controller_state) | |
8b8d7191 VS |
345 | * @next_msg_cs_active: the next message in the queue has been examined |
346 | * and it was found that it uses the same chip select as the previous | |
347 | * message, so we left it active after the previous transfer, and it's | |
348 | * active already. | |
b43d65f7 LW |
349 | * @tx: current position in TX buffer to be read |
350 | * @tx_end: end position in TX buffer to be read | |
351 | * @rx: current position in RX buffer to be written | |
352 | * @rx_end: end position in RX buffer to be written | |
12e8b325 LW |
353 | * @read: the type of read currently going on |
354 | * @write: the type of write currently going on | |
355 | * @exp_fifo_level: expected FIFO level | |
356 | * @dma_rx_channel: optional channel for RX DMA | |
357 | * @dma_tx_channel: optional channel for TX DMA | |
358 | * @sgt_rx: scattertable for the RX transfer | |
359 | * @sgt_tx: scattertable for the TX transfer | |
360 | * @dummypage: a dummy page used for driving data on the bus with DMA | |
f6f46de1 RS |
361 | * @cur_cs: current chip select (gpio) |
362 | * @chipselects: list of chipselects (gpios) | |
b43d65f7 LW |
363 | */ |
364 | struct pl022 { | |
365 | struct amba_device *adev; | |
366 | struct vendor_data *vendor; | |
367 | resource_size_t phybase; | |
368 | void __iomem *virtbase; | |
369 | struct clk *clk; | |
370 | struct spi_master *master; | |
371 | struct pl022_ssp_controller *master_info; | |
ffbbdd21 | 372 | /* Message per-transfer pump */ |
b43d65f7 LW |
373 | struct tasklet_struct pump_transfers; |
374 | struct spi_message *cur_msg; | |
375 | struct spi_transfer *cur_transfer; | |
376 | struct chip_data *cur_chip; | |
8b8d7191 | 377 | bool next_msg_cs_active; |
b43d65f7 LW |
378 | void *tx; |
379 | void *tx_end; | |
380 | void *rx; | |
381 | void *rx_end; | |
382 | enum ssp_reading read; | |
383 | enum ssp_writing write; | |
fc05475f | 384 | u32 exp_fifo_level; |
083be3f0 LW |
385 | enum ssp_rx_level_trig rx_lev_trig; |
386 | enum ssp_tx_level_trig tx_lev_trig; | |
b1b6b9aa LW |
387 | /* DMA settings */ |
388 | #ifdef CONFIG_DMA_ENGINE | |
389 | struct dma_chan *dma_rx_channel; | |
390 | struct dma_chan *dma_tx_channel; | |
391 | struct sg_table sgt_rx; | |
392 | struct sg_table sgt_tx; | |
393 | char *dummypage; | |
ffbbdd21 | 394 | bool dma_running; |
b1b6b9aa | 395 | #endif |
f6f46de1 RS |
396 | int cur_cs; |
397 | int *chipselects; | |
b43d65f7 LW |
398 | }; |
399 | ||
400 | /** | |
401 | * struct chip_data - To maintain runtime state of SSP for each client chip | |
556f4aeb LW |
402 | * @cr0: Value of control register CR0 of SSP - on later ST variants this |
403 | * register is 32 bits wide rather than just 16 | |
b43d65f7 LW |
404 | * @cr1: Value of control register CR1 of SSP |
405 | * @dmacr: Value of DMA control Register of SSP | |
406 | * @cpsr: Value of Clock prescale register | |
407 | * @n_bytes: how many bytes(power of 2) reqd for a given data width of client | |
408 | * @enable_dma: Whether to enable DMA or not | |
b43d65f7 | 409 | * @read: function ptr to be used to read when doing xfer for this chip |
12e8b325 | 410 | * @write: function ptr to be used to write when doing xfer for this chip |
b43d65f7 LW |
411 | * @cs_control: chip select callback provided by chip |
412 | * @xfer_type: polling/interrupt/DMA | |
413 | * | |
414 | * Runtime state of the SSP controller, maintained per chip, | |
415 | * This would be set according to the current message that would be served | |
416 | */ | |
417 | struct chip_data { | |
556f4aeb | 418 | u32 cr0; |
b43d65f7 LW |
419 | u16 cr1; |
420 | u16 dmacr; | |
421 | u16 cpsr; | |
422 | u8 n_bytes; | |
b1b6b9aa | 423 | bool enable_dma; |
b43d65f7 LW |
424 | enum ssp_reading read; |
425 | enum ssp_writing write; | |
426 | void (*cs_control) (u32 command); | |
427 | int xfer_type; | |
428 | }; | |
429 | ||
430 | /** | |
431 | * null_cs_control - Dummy chip select function | |
432 | * @command: select/delect the chip | |
433 | * | |
434 | * If no chip select function is provided by client this is used as dummy | |
435 | * chip select | |
436 | */ | |
437 | static void null_cs_control(u32 command) | |
438 | { | |
439 | pr_debug("pl022: dummy chip select control, CS=0x%x\n", command); | |
440 | } | |
441 | ||
db4fa45e AB |
442 | /** |
443 | * internal_cs_control - Control chip select signals via SSP_CSR. | |
444 | * @pl022: SSP driver private data structure | |
445 | * @command: select/delect the chip | |
446 | * | |
447 | * Used on controller with internal chip select control via SSP_CSR register | |
448 | * (vendor extension). Each of the 5 LSB in the register controls one chip | |
449 | * select signal. | |
450 | */ | |
451 | static void internal_cs_control(struct pl022 *pl022, u32 command) | |
452 | { | |
453 | u32 tmp; | |
454 | ||
455 | tmp = readw(SSP_CSR(pl022->virtbase)); | |
456 | if (command == SSP_CHIP_SELECT) | |
457 | tmp &= ~BIT(pl022->cur_cs); | |
458 | else | |
459 | tmp |= BIT(pl022->cur_cs); | |
460 | writew(tmp, SSP_CSR(pl022->virtbase)); | |
461 | } | |
462 | ||
f6f46de1 RS |
463 | static void pl022_cs_control(struct pl022 *pl022, u32 command) |
464 | { | |
db4fa45e AB |
465 | if (pl022->vendor->internal_cs_ctrl) |
466 | internal_cs_control(pl022, command); | |
467 | else if (gpio_is_valid(pl022->cur_cs)) | |
f6f46de1 RS |
468 | gpio_set_value(pl022->cur_cs, command); |
469 | else | |
470 | pl022->cur_chip->cs_control(command); | |
471 | } | |
472 | ||
b43d65f7 LW |
473 | /** |
474 | * giveback - current spi_message is over, schedule next message and call | |
475 | * callback of this message. Assumes that caller already | |
476 | * set message->status; dma and pio irqs are blocked | |
477 | * @pl022: SSP driver private data structure | |
478 | */ | |
479 | static void giveback(struct pl022 *pl022) | |
480 | { | |
481 | struct spi_transfer *last_transfer; | |
8b8d7191 | 482 | pl022->next_msg_cs_active = false; |
b43d65f7 | 483 | |
23e2c2aa AL |
484 | last_transfer = list_last_entry(&pl022->cur_msg->transfers, |
485 | struct spi_transfer, transfer_list); | |
b43d65f7 LW |
486 | |
487 | /* Delay if requested before any change in chip select */ | |
e74dc5c7 AA |
488 | /* |
489 | * FIXME: This runs in interrupt context. | |
490 | * Is this really smart? | |
491 | */ | |
492 | spi_transfer_delay_exec(last_transfer); | |
b43d65f7 | 493 | |
8b8d7191 | 494 | if (!last_transfer->cs_change) { |
b43d65f7 LW |
495 | struct spi_message *next_msg; |
496 | ||
8b8d7191 VS |
497 | /* |
498 | * cs_change was not set. We can keep the chip select | |
499 | * enabled if there is message in the queue and it is | |
500 | * for the same spi device. | |
b43d65f7 LW |
501 | * |
502 | * We cannot postpone this until pump_messages, because | |
503 | * after calling msg->complete (below) the driver that | |
504 | * sent the current message could be unloaded, which | |
505 | * could invalidate the cs_control() callback... | |
506 | */ | |
b43d65f7 | 507 | /* get a pointer to the next message, if any */ |
ffbbdd21 | 508 | next_msg = spi_get_next_queued_message(pl022->master); |
b43d65f7 | 509 | |
8b8d7191 VS |
510 | /* |
511 | * see if the next and current messages point | |
512 | * to the same spi device. | |
b43d65f7 | 513 | */ |
8b8d7191 | 514 | if (next_msg && next_msg->spi != pl022->cur_msg->spi) |
b43d65f7 | 515 | next_msg = NULL; |
8b8d7191 | 516 | if (!next_msg || pl022->cur_msg->state == STATE_ERROR) |
f6f46de1 | 517 | pl022_cs_control(pl022, SSP_CHIP_DESELECT); |
8b8d7191 VS |
518 | else |
519 | pl022->next_msg_cs_active = true; | |
ffbbdd21 | 520 | |
b43d65f7 | 521 | } |
8b8d7191 | 522 | |
8b8d7191 VS |
523 | pl022->cur_msg = NULL; |
524 | pl022->cur_transfer = NULL; | |
525 | pl022->cur_chip = NULL; | |
fd316941 VS |
526 | |
527 | /* disable the SPI/SSP operation */ | |
528 | writew((readw(SSP_CR1(pl022->virtbase)) & | |
529 | (~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase)); | |
530 | ||
cd6fa8d2 | 531 | spi_finalize_current_message(pl022->master); |
b43d65f7 LW |
532 | } |
533 | ||
534 | /** | |
535 | * flush - flush the FIFO to reach a clean state | |
536 | * @pl022: SSP driver private data structure | |
537 | */ | |
538 | static int flush(struct pl022 *pl022) | |
539 | { | |
540 | unsigned long limit = loops_per_jiffy << 1; | |
541 | ||
542 | dev_dbg(&pl022->adev->dev, "flush\n"); | |
543 | do { | |
544 | while (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE) | |
545 | readw(SSP_DR(pl022->virtbase)); | |
546 | } while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_BSY) && limit--); | |
fc05475f LW |
547 | |
548 | pl022->exp_fifo_level = 0; | |
549 | ||
b43d65f7 LW |
550 | return limit; |
551 | } | |
552 | ||
553 | /** | |
554 | * restore_state - Load configuration of current chip | |
555 | * @pl022: SSP driver private data structure | |
556 | */ | |
557 | static void restore_state(struct pl022 *pl022) | |
558 | { | |
559 | struct chip_data *chip = pl022->cur_chip; | |
560 | ||
556f4aeb LW |
561 | if (pl022->vendor->extended_cr) |
562 | writel(chip->cr0, SSP_CR0(pl022->virtbase)); | |
563 | else | |
564 | writew(chip->cr0, SSP_CR0(pl022->virtbase)); | |
b43d65f7 LW |
565 | writew(chip->cr1, SSP_CR1(pl022->virtbase)); |
566 | writew(chip->dmacr, SSP_DMACR(pl022->virtbase)); | |
567 | writew(chip->cpsr, SSP_CPSR(pl022->virtbase)); | |
568 | writew(DISABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase)); | |
569 | writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase)); | |
570 | } | |
571 | ||
b43d65f7 LW |
572 | /* |
573 | * Default SSP Register Values | |
574 | */ | |
575 | #define DEFAULT_SSP_REG_CR0 ( \ | |
576 | GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS, 0) | \ | |
556f4aeb LW |
577 | GEN_MASK_BITS(SSP_INTERFACE_MOTOROLA_SPI, SSP_CR0_MASK_FRF, 4) | \ |
578 | GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \ | |
579 | GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \ | |
580 | GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) \ | |
581 | ) | |
582 | ||
583 | /* ST versions have slightly different bit layout */ | |
584 | #define DEFAULT_SSP_REG_CR0_ST ( \ | |
585 | GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS_ST, 0) | \ | |
586 | GEN_MASK_BITS(SSP_MICROWIRE_CHANNEL_FULL_DUPLEX, SSP_CR0_MASK_HALFDUP_ST, 5) | \ | |
b43d65f7 | 587 | GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \ |
ee2b805c | 588 | GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \ |
556f4aeb LW |
589 | GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) | \ |
590 | GEN_MASK_BITS(SSP_BITS_8, SSP_CR0_MASK_CSS_ST, 16) | \ | |
591 | GEN_MASK_BITS(SSP_INTERFACE_MOTOROLA_SPI, SSP_CR0_MASK_FRF_ST, 21) \ | |
b43d65f7 LW |
592 | ) |
593 | ||
781c7b12 LW |
594 | /* The PL023 version is slightly different again */ |
595 | #define DEFAULT_SSP_REG_CR0_ST_PL023 ( \ | |
596 | GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS_ST, 0) | \ | |
597 | GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \ | |
598 | GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \ | |
599 | GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) \ | |
600 | ) | |
601 | ||
b43d65f7 LW |
602 | #define DEFAULT_SSP_REG_CR1 ( \ |
603 | GEN_MASK_BITS(LOOPBACK_DISABLED, SSP_CR1_MASK_LBM, 0) | \ | |
604 | GEN_MASK_BITS(SSP_DISABLED, SSP_CR1_MASK_SSE, 1) | \ | |
605 | GEN_MASK_BITS(SSP_MASTER, SSP_CR1_MASK_MS, 2) | \ | |
556f4aeb | 606 | GEN_MASK_BITS(DO_NOT_DRIVE_TX, SSP_CR1_MASK_SOD, 3) \ |
b43d65f7 LW |
607 | ) |
608 | ||
556f4aeb LW |
609 | /* ST versions extend this register to use all 16 bits */ |
610 | #define DEFAULT_SSP_REG_CR1_ST ( \ | |
611 | DEFAULT_SSP_REG_CR1 | \ | |
612 | GEN_MASK_BITS(SSP_RX_MSB, SSP_CR1_MASK_RENDN_ST, 4) | \ | |
613 | GEN_MASK_BITS(SSP_TX_MSB, SSP_CR1_MASK_TENDN_ST, 5) | \ | |
614 | GEN_MASK_BITS(SSP_MWIRE_WAIT_ZERO, SSP_CR1_MASK_MWAIT_ST, 6) |\ | |
615 | GEN_MASK_BITS(SSP_RX_1_OR_MORE_ELEM, SSP_CR1_MASK_RXIFLSEL_ST, 7) | \ | |
616 | GEN_MASK_BITS(SSP_TX_1_OR_MORE_EMPTY_LOC, SSP_CR1_MASK_TXIFLSEL_ST, 10) \ | |
617 | ) | |
618 | ||
781c7b12 LW |
619 | /* |
620 | * The PL023 variant has further differences: no loopback mode, no microwire | |
621 | * support, and a new clock feedback delay setting. | |
622 | */ | |
623 | #define DEFAULT_SSP_REG_CR1_ST_PL023 ( \ | |
624 | GEN_MASK_BITS(SSP_DISABLED, SSP_CR1_MASK_SSE, 1) | \ | |
625 | GEN_MASK_BITS(SSP_MASTER, SSP_CR1_MASK_MS, 2) | \ | |
626 | GEN_MASK_BITS(DO_NOT_DRIVE_TX, SSP_CR1_MASK_SOD, 3) | \ | |
627 | GEN_MASK_BITS(SSP_RX_MSB, SSP_CR1_MASK_RENDN_ST, 4) | \ | |
628 | GEN_MASK_BITS(SSP_TX_MSB, SSP_CR1_MASK_TENDN_ST, 5) | \ | |
629 | GEN_MASK_BITS(SSP_RX_1_OR_MORE_ELEM, SSP_CR1_MASK_RXIFLSEL_ST, 7) | \ | |
630 | GEN_MASK_BITS(SSP_TX_1_OR_MORE_EMPTY_LOC, SSP_CR1_MASK_TXIFLSEL_ST, 10) | \ | |
631 | GEN_MASK_BITS(SSP_FEEDBACK_CLK_DELAY_NONE, SSP_CR1_MASK_FBCLKDEL_ST, 13) \ | |
632 | ) | |
556f4aeb | 633 | |
b43d65f7 | 634 | #define DEFAULT_SSP_REG_CPSR ( \ |
556f4aeb | 635 | GEN_MASK_BITS(SSP_DEFAULT_PRESCALE, SSP_CPSR_MASK_CPSDVSR, 0) \ |
b43d65f7 LW |
636 | ) |
637 | ||
638 | #define DEFAULT_SSP_REG_DMACR (\ | |
639 | GEN_MASK_BITS(SSP_DMA_DISABLED, SSP_DMACR_MASK_RXDMAE, 0) | \ | |
640 | GEN_MASK_BITS(SSP_DMA_DISABLED, SSP_DMACR_MASK_TXDMAE, 1) \ | |
641 | ) | |
642 | ||
781c7b12 LW |
643 | /** |
644 | * load_ssp_default_config - Load default configuration for SSP | |
645 | * @pl022: SSP driver private data structure | |
646 | */ | |
b43d65f7 LW |
647 | static void load_ssp_default_config(struct pl022 *pl022) |
648 | { | |
781c7b12 LW |
649 | if (pl022->vendor->pl023) { |
650 | writel(DEFAULT_SSP_REG_CR0_ST_PL023, SSP_CR0(pl022->virtbase)); | |
651 | writew(DEFAULT_SSP_REG_CR1_ST_PL023, SSP_CR1(pl022->virtbase)); | |
652 | } else if (pl022->vendor->extended_cr) { | |
556f4aeb LW |
653 | writel(DEFAULT_SSP_REG_CR0_ST, SSP_CR0(pl022->virtbase)); |
654 | writew(DEFAULT_SSP_REG_CR1_ST, SSP_CR1(pl022->virtbase)); | |
655 | } else { | |
656 | writew(DEFAULT_SSP_REG_CR0, SSP_CR0(pl022->virtbase)); | |
657 | writew(DEFAULT_SSP_REG_CR1, SSP_CR1(pl022->virtbase)); | |
658 | } | |
b43d65f7 LW |
659 | writew(DEFAULT_SSP_REG_DMACR, SSP_DMACR(pl022->virtbase)); |
660 | writew(DEFAULT_SSP_REG_CPSR, SSP_CPSR(pl022->virtbase)); | |
661 | writew(DISABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase)); | |
662 | writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase)); | |
663 | } | |
664 | ||
665 | /** | |
666 | * This will write to TX and read from RX according to the parameters | |
667 | * set in pl022. | |
668 | */ | |
669 | static void readwriter(struct pl022 *pl022) | |
670 | { | |
671 | ||
672 | /* | |
25985edc | 673 | * The FIFO depth is different between primecell variants. |
b43d65f7 LW |
674 | * I believe filling in too much in the FIFO might cause |
675 | * errons in 8bit wide transfers on ARM variants (just 8 words | |
676 | * FIFO, means only 8x8 = 64 bits in FIFO) at least. | |
677 | * | |
fc05475f LW |
678 | * To prevent this issue, the TX FIFO is only filled to the |
679 | * unused RX FIFO fill length, regardless of what the TX | |
680 | * FIFO status flag indicates. | |
b43d65f7 LW |
681 | */ |
682 | dev_dbg(&pl022->adev->dev, | |
683 | "%s, rx: %p, rxend: %p, tx: %p, txend: %p\n", | |
684 | __func__, pl022->rx, pl022->rx_end, pl022->tx, pl022->tx_end); | |
685 | ||
686 | /* Read as much as you can */ | |
687 | while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE) | |
688 | && (pl022->rx < pl022->rx_end)) { | |
689 | switch (pl022->read) { | |
690 | case READING_NULL: | |
691 | readw(SSP_DR(pl022->virtbase)); | |
692 | break; | |
693 | case READING_U8: | |
694 | *(u8 *) (pl022->rx) = | |
695 | readw(SSP_DR(pl022->virtbase)) & 0xFFU; | |
696 | break; | |
697 | case READING_U16: | |
698 | *(u16 *) (pl022->rx) = | |
699 | (u16) readw(SSP_DR(pl022->virtbase)); | |
700 | break; | |
701 | case READING_U32: | |
702 | *(u32 *) (pl022->rx) = | |
703 | readl(SSP_DR(pl022->virtbase)); | |
704 | break; | |
705 | } | |
706 | pl022->rx += (pl022->cur_chip->n_bytes); | |
fc05475f | 707 | pl022->exp_fifo_level--; |
b43d65f7 LW |
708 | } |
709 | /* | |
fc05475f | 710 | * Write as much as possible up to the RX FIFO size |
b43d65f7 | 711 | */ |
fc05475f | 712 | while ((pl022->exp_fifo_level < pl022->vendor->fifodepth) |
b43d65f7 LW |
713 | && (pl022->tx < pl022->tx_end)) { |
714 | switch (pl022->write) { | |
715 | case WRITING_NULL: | |
716 | writew(0x0, SSP_DR(pl022->virtbase)); | |
717 | break; | |
718 | case WRITING_U8: | |
719 | writew(*(u8 *) (pl022->tx), SSP_DR(pl022->virtbase)); | |
720 | break; | |
721 | case WRITING_U16: | |
722 | writew((*(u16 *) (pl022->tx)), SSP_DR(pl022->virtbase)); | |
723 | break; | |
724 | case WRITING_U32: | |
725 | writel(*(u32 *) (pl022->tx), SSP_DR(pl022->virtbase)); | |
726 | break; | |
727 | } | |
728 | pl022->tx += (pl022->cur_chip->n_bytes); | |
fc05475f | 729 | pl022->exp_fifo_level++; |
b43d65f7 LW |
730 | /* |
731 | * This inner reader takes care of things appearing in the RX | |
732 | * FIFO as we're transmitting. This will happen a lot since the | |
733 | * clock starts running when you put things into the TX FIFO, | |
25985edc | 734 | * and then things are continuously clocked into the RX FIFO. |
b43d65f7 LW |
735 | */ |
736 | while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE) | |
737 | && (pl022->rx < pl022->rx_end)) { | |
738 | switch (pl022->read) { | |
739 | case READING_NULL: | |
740 | readw(SSP_DR(pl022->virtbase)); | |
741 | break; | |
742 | case READING_U8: | |
743 | *(u8 *) (pl022->rx) = | |
744 | readw(SSP_DR(pl022->virtbase)) & 0xFFU; | |
745 | break; | |
746 | case READING_U16: | |
747 | *(u16 *) (pl022->rx) = | |
748 | (u16) readw(SSP_DR(pl022->virtbase)); | |
749 | break; | |
750 | case READING_U32: | |
751 | *(u32 *) (pl022->rx) = | |
752 | readl(SSP_DR(pl022->virtbase)); | |
753 | break; | |
754 | } | |
755 | pl022->rx += (pl022->cur_chip->n_bytes); | |
fc05475f | 756 | pl022->exp_fifo_level--; |
b43d65f7 LW |
757 | } |
758 | } | |
759 | /* | |
760 | * When we exit here the TX FIFO should be full and the RX FIFO | |
761 | * should be empty | |
762 | */ | |
763 | } | |
764 | ||
b43d65f7 LW |
765 | /** |
766 | * next_transfer - Move to the Next transfer in the current spi message | |
767 | * @pl022: SSP driver private data structure | |
768 | * | |
769 | * This function moves though the linked list of spi transfers in the | |
770 | * current spi message and returns with the state of current spi | |
771 | * message i.e whether its last transfer is done(STATE_DONE) or | |
772 | * Next transfer is ready(STATE_RUNNING) | |
773 | */ | |
774 | static void *next_transfer(struct pl022 *pl022) | |
775 | { | |
776 | struct spi_message *msg = pl022->cur_msg; | |
777 | struct spi_transfer *trans = pl022->cur_transfer; | |
778 | ||
779 | /* Move to next transfer */ | |
780 | if (trans->transfer_list.next != &msg->transfers) { | |
781 | pl022->cur_transfer = | |
782 | list_entry(trans->transfer_list.next, | |
783 | struct spi_transfer, transfer_list); | |
784 | return STATE_RUNNING; | |
785 | } | |
786 | return STATE_DONE; | |
787 | } | |
b1b6b9aa LW |
788 | |
789 | /* | |
790 | * This DMA functionality is only compiled in if we have | |
791 | * access to the generic DMA devices/DMA engine. | |
792 | */ | |
793 | #ifdef CONFIG_DMA_ENGINE | |
794 | static void unmap_free_dma_scatter(struct pl022 *pl022) | |
795 | { | |
796 | /* Unmap and free the SG tables */ | |
b7298896 | 797 | dma_unmap_sg(pl022->dma_tx_channel->device->dev, pl022->sgt_tx.sgl, |
b1b6b9aa | 798 | pl022->sgt_tx.nents, DMA_TO_DEVICE); |
b7298896 | 799 | dma_unmap_sg(pl022->dma_rx_channel->device->dev, pl022->sgt_rx.sgl, |
b1b6b9aa LW |
800 | pl022->sgt_rx.nents, DMA_FROM_DEVICE); |
801 | sg_free_table(&pl022->sgt_rx); | |
802 | sg_free_table(&pl022->sgt_tx); | |
803 | } | |
804 | ||
805 | static void dma_callback(void *data) | |
806 | { | |
807 | struct pl022 *pl022 = data; | |
808 | struct spi_message *msg = pl022->cur_msg; | |
809 | ||
810 | BUG_ON(!pl022->sgt_rx.sgl); | |
811 | ||
812 | #ifdef VERBOSE_DEBUG | |
813 | /* | |
814 | * Optionally dump out buffers to inspect contents, this is | |
815 | * good if you want to convince yourself that the loopback | |
816 | * read/write contents are the same, when adopting to a new | |
817 | * DMA engine. | |
818 | */ | |
819 | { | |
820 | struct scatterlist *sg; | |
821 | unsigned int i; | |
822 | ||
823 | dma_sync_sg_for_cpu(&pl022->adev->dev, | |
824 | pl022->sgt_rx.sgl, | |
825 | pl022->sgt_rx.nents, | |
826 | DMA_FROM_DEVICE); | |
827 | ||
828 | for_each_sg(pl022->sgt_rx.sgl, sg, pl022->sgt_rx.nents, i) { | |
829 | dev_dbg(&pl022->adev->dev, "SPI RX SG ENTRY: %d", i); | |
830 | print_hex_dump(KERN_ERR, "SPI RX: ", | |
831 | DUMP_PREFIX_OFFSET, | |
832 | 16, | |
833 | 1, | |
834 | sg_virt(sg), | |
835 | sg_dma_len(sg), | |
836 | 1); | |
837 | } | |
838 | for_each_sg(pl022->sgt_tx.sgl, sg, pl022->sgt_tx.nents, i) { | |
839 | dev_dbg(&pl022->adev->dev, "SPI TX SG ENTRY: %d", i); | |
840 | print_hex_dump(KERN_ERR, "SPI TX: ", | |
841 | DUMP_PREFIX_OFFSET, | |
842 | 16, | |
843 | 1, | |
844 | sg_virt(sg), | |
845 | sg_dma_len(sg), | |
846 | 1); | |
847 | } | |
848 | } | |
849 | #endif | |
850 | ||
851 | unmap_free_dma_scatter(pl022); | |
852 | ||
25985edc | 853 | /* Update total bytes transferred */ |
b1b6b9aa | 854 | msg->actual_length += pl022->cur_transfer->len; |
b1b6b9aa LW |
855 | /* Move to next transfer */ |
856 | msg->state = next_transfer(pl022); | |
c0b07605 FT |
857 | if (msg->state != STATE_DONE && pl022->cur_transfer->cs_change) |
858 | pl022_cs_control(pl022, SSP_CHIP_DESELECT); | |
b1b6b9aa LW |
859 | tasklet_schedule(&pl022->pump_transfers); |
860 | } | |
861 | ||
862 | static void setup_dma_scatter(struct pl022 *pl022, | |
863 | void *buffer, | |
864 | unsigned int length, | |
865 | struct sg_table *sgtab) | |
866 | { | |
867 | struct scatterlist *sg; | |
868 | int bytesleft = length; | |
869 | void *bufp = buffer; | |
870 | int mapbytes; | |
871 | int i; | |
872 | ||
873 | if (buffer) { | |
874 | for_each_sg(sgtab->sgl, sg, sgtab->nents, i) { | |
875 | /* | |
876 | * If there are less bytes left than what fits | |
877 | * in the current page (plus page alignment offset) | |
878 | * we just feed in this, else we stuff in as much | |
879 | * as we can. | |
880 | */ | |
881 | if (bytesleft < (PAGE_SIZE - offset_in_page(bufp))) | |
882 | mapbytes = bytesleft; | |
883 | else | |
884 | mapbytes = PAGE_SIZE - offset_in_page(bufp); | |
885 | sg_set_page(sg, virt_to_page(bufp), | |
886 | mapbytes, offset_in_page(bufp)); | |
887 | bufp += mapbytes; | |
888 | bytesleft -= mapbytes; | |
889 | dev_dbg(&pl022->adev->dev, | |
890 | "set RX/TX target page @ %p, %d bytes, %d left\n", | |
891 | bufp, mapbytes, bytesleft); | |
892 | } | |
893 | } else { | |
894 | /* Map the dummy buffer on every page */ | |
895 | for_each_sg(sgtab->sgl, sg, sgtab->nents, i) { | |
896 | if (bytesleft < PAGE_SIZE) | |
897 | mapbytes = bytesleft; | |
898 | else | |
899 | mapbytes = PAGE_SIZE; | |
900 | sg_set_page(sg, virt_to_page(pl022->dummypage), | |
901 | mapbytes, 0); | |
902 | bytesleft -= mapbytes; | |
903 | dev_dbg(&pl022->adev->dev, | |
904 | "set RX/TX to dummy page %d bytes, %d left\n", | |
905 | mapbytes, bytesleft); | |
906 | ||
907 | } | |
908 | } | |
909 | BUG_ON(bytesleft); | |
910 | } | |
911 | ||
912 | /** | |
913 | * configure_dma - configures the channels for the next transfer | |
914 | * @pl022: SSP driver's private data structure | |
915 | */ | |
916 | static int configure_dma(struct pl022 *pl022) | |
917 | { | |
918 | struct dma_slave_config rx_conf = { | |
919 | .src_addr = SSP_DR(pl022->phybase), | |
a485df4b | 920 | .direction = DMA_DEV_TO_MEM, |
258aea76 | 921 | .device_fc = false, |
b1b6b9aa LW |
922 | }; |
923 | struct dma_slave_config tx_conf = { | |
924 | .dst_addr = SSP_DR(pl022->phybase), | |
a485df4b | 925 | .direction = DMA_MEM_TO_DEV, |
258aea76 | 926 | .device_fc = false, |
b1b6b9aa LW |
927 | }; |
928 | unsigned int pages; | |
929 | int ret; | |
082086f2 | 930 | int rx_sglen, tx_sglen; |
b1b6b9aa LW |
931 | struct dma_chan *rxchan = pl022->dma_rx_channel; |
932 | struct dma_chan *txchan = pl022->dma_tx_channel; | |
933 | struct dma_async_tx_descriptor *rxdesc; | |
934 | struct dma_async_tx_descriptor *txdesc; | |
b1b6b9aa LW |
935 | |
936 | /* Check that the channels are available */ | |
937 | if (!rxchan || !txchan) | |
938 | return -ENODEV; | |
939 | ||
083be3f0 LW |
940 | /* |
941 | * If supplied, the DMA burstsize should equal the FIFO trigger level. | |
942 | * Notice that the DMA engine uses one-to-one mapping. Since we can | |
943 | * not trigger on 2 elements this needs explicit mapping rather than | |
944 | * calculation. | |
945 | */ | |
946 | switch (pl022->rx_lev_trig) { | |
947 | case SSP_RX_1_OR_MORE_ELEM: | |
948 | rx_conf.src_maxburst = 1; | |
949 | break; | |
950 | case SSP_RX_4_OR_MORE_ELEM: | |
951 | rx_conf.src_maxburst = 4; | |
952 | break; | |
953 | case SSP_RX_8_OR_MORE_ELEM: | |
954 | rx_conf.src_maxburst = 8; | |
955 | break; | |
956 | case SSP_RX_16_OR_MORE_ELEM: | |
957 | rx_conf.src_maxburst = 16; | |
958 | break; | |
959 | case SSP_RX_32_OR_MORE_ELEM: | |
960 | rx_conf.src_maxburst = 32; | |
961 | break; | |
962 | default: | |
963 | rx_conf.src_maxburst = pl022->vendor->fifodepth >> 1; | |
964 | break; | |
965 | } | |
966 | ||
967 | switch (pl022->tx_lev_trig) { | |
968 | case SSP_TX_1_OR_MORE_EMPTY_LOC: | |
969 | tx_conf.dst_maxburst = 1; | |
970 | break; | |
971 | case SSP_TX_4_OR_MORE_EMPTY_LOC: | |
972 | tx_conf.dst_maxburst = 4; | |
973 | break; | |
974 | case SSP_TX_8_OR_MORE_EMPTY_LOC: | |
975 | tx_conf.dst_maxburst = 8; | |
976 | break; | |
977 | case SSP_TX_16_OR_MORE_EMPTY_LOC: | |
978 | tx_conf.dst_maxburst = 16; | |
979 | break; | |
980 | case SSP_TX_32_OR_MORE_EMPTY_LOC: | |
981 | tx_conf.dst_maxburst = 32; | |
982 | break; | |
983 | default: | |
984 | tx_conf.dst_maxburst = pl022->vendor->fifodepth >> 1; | |
985 | break; | |
986 | } | |
987 | ||
b1b6b9aa LW |
988 | switch (pl022->read) { |
989 | case READING_NULL: | |
990 | /* Use the same as for writing */ | |
991 | rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED; | |
992 | break; | |
993 | case READING_U8: | |
994 | rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; | |
995 | break; | |
996 | case READING_U16: | |
997 | rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; | |
998 | break; | |
999 | case READING_U32: | |
1000 | rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; | |
1001 | break; | |
1002 | } | |
1003 | ||
1004 | switch (pl022->write) { | |
1005 | case WRITING_NULL: | |
1006 | /* Use the same as for reading */ | |
1007 | tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED; | |
1008 | break; | |
1009 | case WRITING_U8: | |
1010 | tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; | |
1011 | break; | |
1012 | case WRITING_U16: | |
1013 | tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; | |
1014 | break; | |
1015 | case WRITING_U32: | |
bc3f67a3 | 1016 | tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; |
b1b6b9aa LW |
1017 | break; |
1018 | } | |
1019 | ||
1020 | /* SPI pecularity: we need to read and write the same width */ | |
1021 | if (rx_conf.src_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) | |
1022 | rx_conf.src_addr_width = tx_conf.dst_addr_width; | |
1023 | if (tx_conf.dst_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) | |
1024 | tx_conf.dst_addr_width = rx_conf.src_addr_width; | |
1025 | BUG_ON(rx_conf.src_addr_width != tx_conf.dst_addr_width); | |
1026 | ||
ecd442fd LW |
1027 | dmaengine_slave_config(rxchan, &rx_conf); |
1028 | dmaengine_slave_config(txchan, &tx_conf); | |
b1b6b9aa LW |
1029 | |
1030 | /* Create sglists for the transfers */ | |
b181565e | 1031 | pages = DIV_ROUND_UP(pl022->cur_transfer->len, PAGE_SIZE); |
b1b6b9aa LW |
1032 | dev_dbg(&pl022->adev->dev, "using %d pages for transfer\n", pages); |
1033 | ||
538a18dc | 1034 | ret = sg_alloc_table(&pl022->sgt_rx, pages, GFP_ATOMIC); |
b1b6b9aa LW |
1035 | if (ret) |
1036 | goto err_alloc_rx_sg; | |
1037 | ||
538a18dc | 1038 | ret = sg_alloc_table(&pl022->sgt_tx, pages, GFP_ATOMIC); |
b1b6b9aa LW |
1039 | if (ret) |
1040 | goto err_alloc_tx_sg; | |
1041 | ||
1042 | /* Fill in the scatterlists for the RX+TX buffers */ | |
1043 | setup_dma_scatter(pl022, pl022->rx, | |
1044 | pl022->cur_transfer->len, &pl022->sgt_rx); | |
1045 | setup_dma_scatter(pl022, pl022->tx, | |
1046 | pl022->cur_transfer->len, &pl022->sgt_tx); | |
1047 | ||
1048 | /* Map DMA buffers */ | |
082086f2 | 1049 | rx_sglen = dma_map_sg(rxchan->device->dev, pl022->sgt_rx.sgl, |
b1b6b9aa | 1050 | pl022->sgt_rx.nents, DMA_FROM_DEVICE); |
082086f2 | 1051 | if (!rx_sglen) |
b1b6b9aa LW |
1052 | goto err_rx_sgmap; |
1053 | ||
082086f2 | 1054 | tx_sglen = dma_map_sg(txchan->device->dev, pl022->sgt_tx.sgl, |
b1b6b9aa | 1055 | pl022->sgt_tx.nents, DMA_TO_DEVICE); |
082086f2 | 1056 | if (!tx_sglen) |
b1b6b9aa LW |
1057 | goto err_tx_sgmap; |
1058 | ||
1059 | /* Send both scatterlists */ | |
16052827 | 1060 | rxdesc = dmaengine_prep_slave_sg(rxchan, |
b1b6b9aa | 1061 | pl022->sgt_rx.sgl, |
082086f2 | 1062 | rx_sglen, |
a485df4b | 1063 | DMA_DEV_TO_MEM, |
b1b6b9aa LW |
1064 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
1065 | if (!rxdesc) | |
1066 | goto err_rxdesc; | |
1067 | ||
16052827 | 1068 | txdesc = dmaengine_prep_slave_sg(txchan, |
b1b6b9aa | 1069 | pl022->sgt_tx.sgl, |
082086f2 | 1070 | tx_sglen, |
a485df4b | 1071 | DMA_MEM_TO_DEV, |
b1b6b9aa LW |
1072 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
1073 | if (!txdesc) | |
1074 | goto err_txdesc; | |
1075 | ||
1076 | /* Put the callback on the RX transfer only, that should finish last */ | |
1077 | rxdesc->callback = dma_callback; | |
1078 | rxdesc->callback_param = pl022; | |
1079 | ||
1080 | /* Submit and fire RX and TX with TX last so we're ready to read! */ | |
ecd442fd LW |
1081 | dmaengine_submit(rxdesc); |
1082 | dmaengine_submit(txdesc); | |
1083 | dma_async_issue_pending(rxchan); | |
1084 | dma_async_issue_pending(txchan); | |
ffbbdd21 | 1085 | pl022->dma_running = true; |
b1b6b9aa LW |
1086 | |
1087 | return 0; | |
1088 | ||
b1b6b9aa | 1089 | err_txdesc: |
ecd442fd | 1090 | dmaengine_terminate_all(txchan); |
b1b6b9aa | 1091 | err_rxdesc: |
ecd442fd | 1092 | dmaengine_terminate_all(rxchan); |
b7298896 | 1093 | dma_unmap_sg(txchan->device->dev, pl022->sgt_tx.sgl, |
b1b6b9aa LW |
1094 | pl022->sgt_tx.nents, DMA_TO_DEVICE); |
1095 | err_tx_sgmap: | |
b7298896 | 1096 | dma_unmap_sg(rxchan->device->dev, pl022->sgt_rx.sgl, |
3ffa6158 | 1097 | pl022->sgt_rx.nents, DMA_FROM_DEVICE); |
b1b6b9aa LW |
1098 | err_rx_sgmap: |
1099 | sg_free_table(&pl022->sgt_tx); | |
1100 | err_alloc_tx_sg: | |
1101 | sg_free_table(&pl022->sgt_rx); | |
1102 | err_alloc_rx_sg: | |
1103 | return -ENOMEM; | |
1104 | } | |
1105 | ||
fd4a319b | 1106 | static int pl022_dma_probe(struct pl022 *pl022) |
b1b6b9aa LW |
1107 | { |
1108 | dma_cap_mask_t mask; | |
1109 | ||
1110 | /* Try to acquire a generic DMA engine slave channel */ | |
1111 | dma_cap_zero(mask); | |
1112 | dma_cap_set(DMA_SLAVE, mask); | |
1113 | /* | |
1114 | * We need both RX and TX channels to do DMA, else do none | |
1115 | * of them. | |
1116 | */ | |
1117 | pl022->dma_rx_channel = dma_request_channel(mask, | |
1118 | pl022->master_info->dma_filter, | |
1119 | pl022->master_info->dma_rx_param); | |
1120 | if (!pl022->dma_rx_channel) { | |
43c64015 | 1121 | dev_dbg(&pl022->adev->dev, "no RX DMA channel!\n"); |
b1b6b9aa LW |
1122 | goto err_no_rxchan; |
1123 | } | |
1124 | ||
1125 | pl022->dma_tx_channel = dma_request_channel(mask, | |
1126 | pl022->master_info->dma_filter, | |
1127 | pl022->master_info->dma_tx_param); | |
1128 | if (!pl022->dma_tx_channel) { | |
43c64015 | 1129 | dev_dbg(&pl022->adev->dev, "no TX DMA channel!\n"); |
b1b6b9aa LW |
1130 | goto err_no_txchan; |
1131 | } | |
1132 | ||
1133 | pl022->dummypage = kmalloc(PAGE_SIZE, GFP_KERNEL); | |
77538f4a | 1134 | if (!pl022->dummypage) |
b1b6b9aa | 1135 | goto err_no_dummypage; |
b1b6b9aa LW |
1136 | |
1137 | dev_info(&pl022->adev->dev, "setup for DMA on RX %s, TX %s\n", | |
1138 | dma_chan_name(pl022->dma_rx_channel), | |
1139 | dma_chan_name(pl022->dma_tx_channel)); | |
1140 | ||
1141 | return 0; | |
1142 | ||
1143 | err_no_dummypage: | |
1144 | dma_release_channel(pl022->dma_tx_channel); | |
1145 | err_no_txchan: | |
1146 | dma_release_channel(pl022->dma_rx_channel); | |
1147 | pl022->dma_rx_channel = NULL; | |
1148 | err_no_rxchan: | |
43c64015 VK |
1149 | dev_err(&pl022->adev->dev, |
1150 | "Failed to work in dma mode, work without dma!\n"); | |
b1b6b9aa LW |
1151 | return -ENODEV; |
1152 | } | |
1153 | ||
dc715452 AB |
1154 | static int pl022_dma_autoprobe(struct pl022 *pl022) |
1155 | { | |
1156 | struct device *dev = &pl022->adev->dev; | |
f3d4bb33 RV |
1157 | struct dma_chan *chan; |
1158 | int err; | |
dc715452 AB |
1159 | |
1160 | /* automatically configure DMA channels from platform, normally using DT */ | |
c1008957 | 1161 | chan = dma_request_chan(dev, "rx"); |
f3d4bb33 RV |
1162 | if (IS_ERR(chan)) { |
1163 | err = PTR_ERR(chan); | |
dc715452 | 1164 | goto err_no_rxchan; |
f3d4bb33 RV |
1165 | } |
1166 | ||
1167 | pl022->dma_rx_channel = chan; | |
dc715452 | 1168 | |
c1008957 | 1169 | chan = dma_request_chan(dev, "tx"); |
f3d4bb33 RV |
1170 | if (IS_ERR(chan)) { |
1171 | err = PTR_ERR(chan); | |
dc715452 | 1172 | goto err_no_txchan; |
f3d4bb33 RV |
1173 | } |
1174 | ||
1175 | pl022->dma_tx_channel = chan; | |
dc715452 AB |
1176 | |
1177 | pl022->dummypage = kmalloc(PAGE_SIZE, GFP_KERNEL); | |
f3d4bb33 RV |
1178 | if (!pl022->dummypage) { |
1179 | err = -ENOMEM; | |
dc715452 | 1180 | goto err_no_dummypage; |
f3d4bb33 | 1181 | } |
dc715452 AB |
1182 | |
1183 | return 0; | |
1184 | ||
1185 | err_no_dummypage: | |
1186 | dma_release_channel(pl022->dma_tx_channel); | |
1187 | pl022->dma_tx_channel = NULL; | |
1188 | err_no_txchan: | |
1189 | dma_release_channel(pl022->dma_rx_channel); | |
1190 | pl022->dma_rx_channel = NULL; | |
1191 | err_no_rxchan: | |
f3d4bb33 | 1192 | return err; |
dc715452 AB |
1193 | } |
1194 | ||
b1b6b9aa LW |
1195 | static void terminate_dma(struct pl022 *pl022) |
1196 | { | |
1197 | struct dma_chan *rxchan = pl022->dma_rx_channel; | |
1198 | struct dma_chan *txchan = pl022->dma_tx_channel; | |
1199 | ||
ecd442fd LW |
1200 | dmaengine_terminate_all(rxchan); |
1201 | dmaengine_terminate_all(txchan); | |
b1b6b9aa | 1202 | unmap_free_dma_scatter(pl022); |
ffbbdd21 | 1203 | pl022->dma_running = false; |
b1b6b9aa LW |
1204 | } |
1205 | ||
1206 | static void pl022_dma_remove(struct pl022 *pl022) | |
1207 | { | |
ffbbdd21 | 1208 | if (pl022->dma_running) |
b1b6b9aa LW |
1209 | terminate_dma(pl022); |
1210 | if (pl022->dma_tx_channel) | |
1211 | dma_release_channel(pl022->dma_tx_channel); | |
1212 | if (pl022->dma_rx_channel) | |
1213 | dma_release_channel(pl022->dma_rx_channel); | |
1214 | kfree(pl022->dummypage); | |
1215 | } | |
1216 | ||
1217 | #else | |
1218 | static inline int configure_dma(struct pl022 *pl022) | |
1219 | { | |
1220 | return -ENODEV; | |
1221 | } | |
1222 | ||
dc715452 AB |
1223 | static inline int pl022_dma_autoprobe(struct pl022 *pl022) |
1224 | { | |
1225 | return 0; | |
1226 | } | |
1227 | ||
b1b6b9aa LW |
1228 | static inline int pl022_dma_probe(struct pl022 *pl022) |
1229 | { | |
1230 | return 0; | |
1231 | } | |
1232 | ||
1233 | static inline void pl022_dma_remove(struct pl022 *pl022) | |
1234 | { | |
1235 | } | |
1236 | #endif | |
1237 | ||
b43d65f7 LW |
1238 | /** |
1239 | * pl022_interrupt_handler - Interrupt handler for SSP controller | |
1240 | * | |
1241 | * This function handles interrupts generated for an interrupt based transfer. | |
1242 | * If a receive overrun (ROR) interrupt is there then we disable SSP, flag the | |
1243 | * current message's state as STATE_ERROR and schedule the tasklet | |
1244 | * pump_transfers which will do the postprocessing of the current message by | |
1245 | * calling giveback(). Otherwise it reads data from RX FIFO till there is no | |
1246 | * more data, and writes data in TX FIFO till it is not full. If we complete | |
1247 | * the transfer we move to the next transfer and schedule the tasklet. | |
1248 | */ | |
1249 | static irqreturn_t pl022_interrupt_handler(int irq, void *dev_id) | |
1250 | { | |
1251 | struct pl022 *pl022 = dev_id; | |
1252 | struct spi_message *msg = pl022->cur_msg; | |
1253 | u16 irq_status = 0; | |
b43d65f7 LW |
1254 | |
1255 | if (unlikely(!msg)) { | |
1256 | dev_err(&pl022->adev->dev, | |
1257 | "bad message state in interrupt handler"); | |
1258 | /* Never fail */ | |
1259 | return IRQ_HANDLED; | |
1260 | } | |
1261 | ||
1262 | /* Read the Interrupt Status Register */ | |
1263 | irq_status = readw(SSP_MIS(pl022->virtbase)); | |
1264 | ||
1265 | if (unlikely(!irq_status)) | |
1266 | return IRQ_NONE; | |
1267 | ||
b1b6b9aa LW |
1268 | /* |
1269 | * This handles the FIFO interrupts, the timeout | |
1270 | * interrupts are flatly ignored, they cannot be | |
1271 | * trusted. | |
1272 | */ | |
b43d65f7 LW |
1273 | if (unlikely(irq_status & SSP_MIS_MASK_RORMIS)) { |
1274 | /* | |
1275 | * Overrun interrupt - bail out since our Data has been | |
1276 | * corrupted | |
1277 | */ | |
b1b6b9aa | 1278 | dev_err(&pl022->adev->dev, "FIFO overrun\n"); |
b43d65f7 LW |
1279 | if (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RFF) |
1280 | dev_err(&pl022->adev->dev, | |
1281 | "RXFIFO is full\n"); | |
b43d65f7 LW |
1282 | |
1283 | /* | |
1284 | * Disable and clear interrupts, disable SSP, | |
1285 | * mark message with bad status so it can be | |
1286 | * retried. | |
1287 | */ | |
1288 | writew(DISABLE_ALL_INTERRUPTS, | |
1289 | SSP_IMSC(pl022->virtbase)); | |
1290 | writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase)); | |
1291 | writew((readw(SSP_CR1(pl022->virtbase)) & | |
1292 | (~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase)); | |
1293 | msg->state = STATE_ERROR; | |
1294 | ||
1295 | /* Schedule message queue handler */ | |
1296 | tasklet_schedule(&pl022->pump_transfers); | |
1297 | return IRQ_HANDLED; | |
1298 | } | |
1299 | ||
1300 | readwriter(pl022); | |
1301 | ||
7183d1eb | 1302 | if (pl022->tx == pl022->tx_end) { |
172289df CB |
1303 | /* Disable Transmit interrupt, enable receive interrupt */ |
1304 | writew((readw(SSP_IMSC(pl022->virtbase)) & | |
1305 | ~SSP_IMSC_MASK_TXIM) | SSP_IMSC_MASK_RXIM, | |
b43d65f7 LW |
1306 | SSP_IMSC(pl022->virtbase)); |
1307 | } | |
1308 | ||
1309 | /* | |
1310 | * Since all transactions must write as much as shall be read, | |
1311 | * we can conclude the entire transaction once RX is complete. | |
1312 | * At this point, all TX will always be finished. | |
1313 | */ | |
1314 | if (pl022->rx >= pl022->rx_end) { | |
1315 | writew(DISABLE_ALL_INTERRUPTS, | |
1316 | SSP_IMSC(pl022->virtbase)); | |
1317 | writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase)); | |
1318 | if (unlikely(pl022->rx > pl022->rx_end)) { | |
1319 | dev_warn(&pl022->adev->dev, "read %u surplus " | |
1320 | "bytes (did you request an odd " | |
1321 | "number of bytes on a 16bit bus?)\n", | |
1322 | (u32) (pl022->rx - pl022->rx_end)); | |
1323 | } | |
25985edc | 1324 | /* Update total bytes transferred */ |
b43d65f7 | 1325 | msg->actual_length += pl022->cur_transfer->len; |
b43d65f7 LW |
1326 | /* Move to next transfer */ |
1327 | msg->state = next_transfer(pl022); | |
c0b07605 FT |
1328 | if (msg->state != STATE_DONE && pl022->cur_transfer->cs_change) |
1329 | pl022_cs_control(pl022, SSP_CHIP_DESELECT); | |
b43d65f7 LW |
1330 | tasklet_schedule(&pl022->pump_transfers); |
1331 | return IRQ_HANDLED; | |
1332 | } | |
1333 | ||
1334 | return IRQ_HANDLED; | |
1335 | } | |
1336 | ||
1337 | /** | |
1338 | * This sets up the pointers to memory for the next message to | |
1339 | * send out on the SPI bus. | |
1340 | */ | |
1341 | static int set_up_next_transfer(struct pl022 *pl022, | |
1342 | struct spi_transfer *transfer) | |
1343 | { | |
1344 | int residue; | |
1345 | ||
1346 | /* Sanity check the message for this bus width */ | |
1347 | residue = pl022->cur_transfer->len % pl022->cur_chip->n_bytes; | |
1348 | if (unlikely(residue != 0)) { | |
1349 | dev_err(&pl022->adev->dev, | |
1350 | "message of %u bytes to transmit but the current " | |
1351 | "chip bus has a data width of %u bytes!\n", | |
1352 | pl022->cur_transfer->len, | |
1353 | pl022->cur_chip->n_bytes); | |
1354 | dev_err(&pl022->adev->dev, "skipping this message\n"); | |
1355 | return -EIO; | |
1356 | } | |
1357 | pl022->tx = (void *)transfer->tx_buf; | |
1358 | pl022->tx_end = pl022->tx + pl022->cur_transfer->len; | |
1359 | pl022->rx = (void *)transfer->rx_buf; | |
1360 | pl022->rx_end = pl022->rx + pl022->cur_transfer->len; | |
1361 | pl022->write = | |
1362 | pl022->tx ? pl022->cur_chip->write : WRITING_NULL; | |
1363 | pl022->read = pl022->rx ? pl022->cur_chip->read : READING_NULL; | |
1364 | return 0; | |
1365 | } | |
1366 | ||
1367 | /** | |
b1b6b9aa LW |
1368 | * pump_transfers - Tasklet function which schedules next transfer |
1369 | * when running in interrupt or DMA transfer mode. | |
b43d65f7 LW |
1370 | * @data: SSP driver private data structure |
1371 | * | |
1372 | */ | |
1373 | static void pump_transfers(unsigned long data) | |
1374 | { | |
1375 | struct pl022 *pl022 = (struct pl022 *) data; | |
1376 | struct spi_message *message = NULL; | |
1377 | struct spi_transfer *transfer = NULL; | |
1378 | struct spi_transfer *previous = NULL; | |
1379 | ||
1380 | /* Get current state information */ | |
1381 | message = pl022->cur_msg; | |
1382 | transfer = pl022->cur_transfer; | |
1383 | ||
1384 | /* Handle for abort */ | |
1385 | if (message->state == STATE_ERROR) { | |
1386 | message->status = -EIO; | |
1387 | giveback(pl022); | |
1388 | return; | |
1389 | } | |
1390 | ||
1391 | /* Handle end of message */ | |
1392 | if (message->state == STATE_DONE) { | |
1393 | message->status = 0; | |
1394 | giveback(pl022); | |
1395 | return; | |
1396 | } | |
1397 | ||
1398 | /* Delay if requested at end of transfer before CS change */ | |
1399 | if (message->state == STATE_RUNNING) { | |
1400 | previous = list_entry(transfer->transfer_list.prev, | |
1401 | struct spi_transfer, | |
1402 | transfer_list); | |
e74dc5c7 AA |
1403 | /* |
1404 | * FIXME: This runs in interrupt context. | |
1405 | * Is this really smart? | |
1406 | */ | |
1407 | spi_transfer_delay_exec(previous); | |
b43d65f7 | 1408 | |
8b8d7191 | 1409 | /* Reselect chip select only if cs_change was requested */ |
b43d65f7 | 1410 | if (previous->cs_change) |
f6f46de1 | 1411 | pl022_cs_control(pl022, SSP_CHIP_SELECT); |
b43d65f7 LW |
1412 | } else { |
1413 | /* STATE_START */ | |
1414 | message->state = STATE_RUNNING; | |
1415 | } | |
1416 | ||
1417 | if (set_up_next_transfer(pl022, transfer)) { | |
1418 | message->state = STATE_ERROR; | |
1419 | message->status = -EIO; | |
1420 | giveback(pl022); | |
1421 | return; | |
1422 | } | |
1423 | /* Flush the FIFOs and let's go! */ | |
1424 | flush(pl022); | |
b43d65f7 | 1425 | |
b1b6b9aa LW |
1426 | if (pl022->cur_chip->enable_dma) { |
1427 | if (configure_dma(pl022)) { | |
1428 | dev_dbg(&pl022->adev->dev, | |
1429 | "configuration of DMA failed, fall back to interrupt mode\n"); | |
1430 | goto err_config_dma; | |
1431 | } | |
b43d65f7 LW |
1432 | return; |
1433 | } | |
b43d65f7 | 1434 | |
b1b6b9aa | 1435 | err_config_dma: |
172289df CB |
1436 | /* enable all interrupts except RX */ |
1437 | writew(ENABLE_ALL_INTERRUPTS & ~SSP_IMSC_MASK_RXIM, SSP_IMSC(pl022->virtbase)); | |
b43d65f7 LW |
1438 | } |
1439 | ||
b1b6b9aa | 1440 | static void do_interrupt_dma_transfer(struct pl022 *pl022) |
b43d65f7 | 1441 | { |
172289df CB |
1442 | /* |
1443 | * Default is to enable all interrupts except RX - | |
1444 | * this will be enabled once TX is complete | |
1445 | */ | |
d555ea05 | 1446 | u32 irqflags = (u32)(ENABLE_ALL_INTERRUPTS & ~SSP_IMSC_MASK_RXIM); |
b43d65f7 | 1447 | |
8b8d7191 VS |
1448 | /* Enable target chip, if not already active */ |
1449 | if (!pl022->next_msg_cs_active) | |
f6f46de1 | 1450 | pl022_cs_control(pl022, SSP_CHIP_SELECT); |
b43d65f7 | 1451 | |
b43d65f7 LW |
1452 | if (set_up_next_transfer(pl022, pl022->cur_transfer)) { |
1453 | /* Error path */ | |
1454 | pl022->cur_msg->state = STATE_ERROR; | |
1455 | pl022->cur_msg->status = -EIO; | |
1456 | giveback(pl022); | |
1457 | return; | |
1458 | } | |
b1b6b9aa LW |
1459 | /* If we're using DMA, set up DMA here */ |
1460 | if (pl022->cur_chip->enable_dma) { | |
1461 | /* Configure DMA transfer */ | |
1462 | if (configure_dma(pl022)) { | |
1463 | dev_dbg(&pl022->adev->dev, | |
1464 | "configuration of DMA failed, fall back to interrupt mode\n"); | |
1465 | goto err_config_dma; | |
1466 | } | |
1467 | /* Disable interrupts in DMA mode, IRQ from DMA controller */ | |
1468 | irqflags = DISABLE_ALL_INTERRUPTS; | |
1469 | } | |
1470 | err_config_dma: | |
b43d65f7 LW |
1471 | /* Enable SSP, turn on interrupts */ |
1472 | writew((readw(SSP_CR1(pl022->virtbase)) | SSP_CR1_MASK_SSE), | |
1473 | SSP_CR1(pl022->virtbase)); | |
b1b6b9aa | 1474 | writew(irqflags, SSP_IMSC(pl022->virtbase)); |
b43d65f7 LW |
1475 | } |
1476 | ||
7aef2b64 JS |
1477 | static void print_current_status(struct pl022 *pl022) |
1478 | { | |
1479 | u32 read_cr0; | |
1480 | u16 read_cr1, read_dmacr, read_sr; | |
1481 | ||
1482 | if (pl022->vendor->extended_cr) | |
1483 | read_cr0 = readl(SSP_CR0(pl022->virtbase)); | |
1484 | else | |
1485 | read_cr0 = readw(SSP_CR0(pl022->virtbase)); | |
1486 | read_cr1 = readw(SSP_CR1(pl022->virtbase)); | |
1487 | read_dmacr = readw(SSP_DMACR(pl022->virtbase)); | |
1488 | read_sr = readw(SSP_SR(pl022->virtbase)); | |
1489 | ||
1490 | dev_warn(&pl022->adev->dev, "spi-pl022 CR0: %x\n", read_cr0); | |
1491 | dev_warn(&pl022->adev->dev, "spi-pl022 CR1: %x\n", read_cr1); | |
1492 | dev_warn(&pl022->adev->dev, "spi-pl022 DMACR: %x\n", read_dmacr); | |
1493 | dev_warn(&pl022->adev->dev, "spi-pl022 SR: %x\n", read_sr); | |
1494 | dev_warn(&pl022->adev->dev, | |
1495 | "spi-pl022 exp_fifo_level/fifodepth: %u/%d\n", | |
1496 | pl022->exp_fifo_level, | |
1497 | pl022->vendor->fifodepth); | |
1498 | ||
1499 | } | |
1500 | ||
b1b6b9aa | 1501 | static void do_polling_transfer(struct pl022 *pl022) |
b43d65f7 | 1502 | { |
b43d65f7 LW |
1503 | struct spi_message *message = NULL; |
1504 | struct spi_transfer *transfer = NULL; | |
1505 | struct spi_transfer *previous = NULL; | |
a18c266f | 1506 | unsigned long time, timeout; |
b43d65f7 | 1507 | |
b43d65f7 LW |
1508 | message = pl022->cur_msg; |
1509 | ||
1510 | while (message->state != STATE_DONE) { | |
1511 | /* Handle for abort */ | |
1512 | if (message->state == STATE_ERROR) | |
1513 | break; | |
1514 | transfer = pl022->cur_transfer; | |
1515 | ||
1516 | /* Delay if requested at end of transfer */ | |
1517 | if (message->state == STATE_RUNNING) { | |
1518 | previous = | |
1519 | list_entry(transfer->transfer_list.prev, | |
1520 | struct spi_transfer, transfer_list); | |
e74dc5c7 | 1521 | spi_transfer_delay_exec(previous); |
b43d65f7 | 1522 | if (previous->cs_change) |
f6f46de1 | 1523 | pl022_cs_control(pl022, SSP_CHIP_SELECT); |
b43d65f7 LW |
1524 | } else { |
1525 | /* STATE_START */ | |
1526 | message->state = STATE_RUNNING; | |
8b8d7191 | 1527 | if (!pl022->next_msg_cs_active) |
f6f46de1 | 1528 | pl022_cs_control(pl022, SSP_CHIP_SELECT); |
b43d65f7 LW |
1529 | } |
1530 | ||
1531 | /* Configuration Changing Per Transfer */ | |
1532 | if (set_up_next_transfer(pl022, transfer)) { | |
1533 | /* Error path */ | |
1534 | message->state = STATE_ERROR; | |
1535 | break; | |
1536 | } | |
1537 | /* Flush FIFOs and enable SSP */ | |
1538 | flush(pl022); | |
1539 | writew((readw(SSP_CR1(pl022->virtbase)) | SSP_CR1_MASK_SSE), | |
1540 | SSP_CR1(pl022->virtbase)); | |
1541 | ||
556f4aeb | 1542 | dev_dbg(&pl022->adev->dev, "polling transfer ongoing ...\n"); |
a18c266f MT |
1543 | |
1544 | timeout = jiffies + msecs_to_jiffies(SPI_POLLING_TIMEOUT); | |
1545 | while (pl022->tx < pl022->tx_end || pl022->rx < pl022->rx_end) { | |
1546 | time = jiffies; | |
b43d65f7 | 1547 | readwriter(pl022); |
a18c266f MT |
1548 | if (time_after(time, timeout)) { |
1549 | dev_warn(&pl022->adev->dev, | |
1550 | "%s: timeout!\n", __func__); | |
7aef2b64 JS |
1551 | message->state = STATE_TIMEOUT; |
1552 | print_current_status(pl022); | |
a18c266f MT |
1553 | goto out; |
1554 | } | |
521999bd | 1555 | cpu_relax(); |
a18c266f | 1556 | } |
b43d65f7 | 1557 | |
25985edc | 1558 | /* Update total byte transferred */ |
b43d65f7 | 1559 | message->actual_length += pl022->cur_transfer->len; |
b43d65f7 LW |
1560 | /* Move to next transfer */ |
1561 | message->state = next_transfer(pl022); | |
c0b07605 FT |
1562 | if (message->state != STATE_DONE |
1563 | && pl022->cur_transfer->cs_change) | |
1564 | pl022_cs_control(pl022, SSP_CHIP_DESELECT); | |
b43d65f7 | 1565 | } |
a18c266f | 1566 | out: |
b43d65f7 LW |
1567 | /* Handle end of message */ |
1568 | if (message->state == STATE_DONE) | |
1569 | message->status = 0; | |
7aef2b64 JS |
1570 | else if (message->state == STATE_TIMEOUT) |
1571 | message->status = -EAGAIN; | |
b43d65f7 LW |
1572 | else |
1573 | message->status = -EIO; | |
1574 | ||
1575 | giveback(pl022); | |
1576 | return; | |
1577 | } | |
1578 | ||
ffbbdd21 LW |
1579 | static int pl022_transfer_one_message(struct spi_master *master, |
1580 | struct spi_message *msg) | |
b43d65f7 | 1581 | { |
ffbbdd21 | 1582 | struct pl022 *pl022 = spi_master_get_devdata(master); |
b43d65f7 LW |
1583 | |
1584 | /* Initial message state */ | |
ffbbdd21 LW |
1585 | pl022->cur_msg = msg; |
1586 | msg->state = STATE_START; | |
1587 | ||
1588 | pl022->cur_transfer = list_entry(msg->transfers.next, | |
1589 | struct spi_transfer, transfer_list); | |
b43d65f7 LW |
1590 | |
1591 | /* Setup the SPI using the per chip configuration */ | |
ffbbdd21 | 1592 | pl022->cur_chip = spi_get_ctldata(msg->spi); |
f6f46de1 | 1593 | pl022->cur_cs = pl022->chipselects[msg->spi->chip_select]; |
d4b6af2e | 1594 | |
b43d65f7 LW |
1595 | restore_state(pl022); |
1596 | flush(pl022); | |
1597 | ||
1598 | if (pl022->cur_chip->xfer_type == POLLING_TRANSFER) | |
1599 | do_polling_transfer(pl022); | |
b43d65f7 | 1600 | else |
b1b6b9aa | 1601 | do_interrupt_dma_transfer(pl022); |
b43d65f7 LW |
1602 | |
1603 | return 0; | |
1604 | } | |
1605 | ||
ffbbdd21 | 1606 | static int pl022_unprepare_transfer_hardware(struct spi_master *master) |
b43d65f7 | 1607 | { |
ffbbdd21 | 1608 | struct pl022 *pl022 = spi_master_get_devdata(master); |
b43d65f7 | 1609 | |
ffbbdd21 LW |
1610 | /* nothing more to do - disable spi/ssp and power off */ |
1611 | writew((readw(SSP_CR1(pl022->virtbase)) & | |
1612 | (~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase)); | |
b43d65f7 | 1613 | |
b43d65f7 LW |
1614 | return 0; |
1615 | } | |
1616 | ||
1617 | static int verify_controller_parameters(struct pl022 *pl022, | |
f9d629c7 | 1618 | struct pl022_config_chip const *chip_info) |
b43d65f7 | 1619 | { |
b43d65f7 LW |
1620 | if ((chip_info->iface < SSP_INTERFACE_MOTOROLA_SPI) |
1621 | || (chip_info->iface > SSP_INTERFACE_UNIDIRECTIONAL)) { | |
5a1c98be | 1622 | dev_err(&pl022->adev->dev, |
b43d65f7 LW |
1623 | "interface is configured incorrectly\n"); |
1624 | return -EINVAL; | |
1625 | } | |
1626 | if ((chip_info->iface == SSP_INTERFACE_UNIDIRECTIONAL) && | |
1627 | (!pl022->vendor->unidir)) { | |
5a1c98be | 1628 | dev_err(&pl022->adev->dev, |
b43d65f7 LW |
1629 | "unidirectional mode not supported in this " |
1630 | "hardware version\n"); | |
1631 | return -EINVAL; | |
1632 | } | |
1633 | if ((chip_info->hierarchy != SSP_MASTER) | |
1634 | && (chip_info->hierarchy != SSP_SLAVE)) { | |
5a1c98be | 1635 | dev_err(&pl022->adev->dev, |
b43d65f7 LW |
1636 | "hierarchy is configured incorrectly\n"); |
1637 | return -EINVAL; | |
1638 | } | |
b43d65f7 LW |
1639 | if ((chip_info->com_mode != INTERRUPT_TRANSFER) |
1640 | && (chip_info->com_mode != DMA_TRANSFER) | |
1641 | && (chip_info->com_mode != POLLING_TRANSFER)) { | |
5a1c98be | 1642 | dev_err(&pl022->adev->dev, |
b43d65f7 LW |
1643 | "Communication mode is configured incorrectly\n"); |
1644 | return -EINVAL; | |
1645 | } | |
78b2b911 LW |
1646 | switch (chip_info->rx_lev_trig) { |
1647 | case SSP_RX_1_OR_MORE_ELEM: | |
1648 | case SSP_RX_4_OR_MORE_ELEM: | |
1649 | case SSP_RX_8_OR_MORE_ELEM: | |
1650 | /* These are always OK, all variants can handle this */ | |
1651 | break; | |
1652 | case SSP_RX_16_OR_MORE_ELEM: | |
1653 | if (pl022->vendor->fifodepth < 16) { | |
1654 | dev_err(&pl022->adev->dev, | |
1655 | "RX FIFO Trigger Level is configured incorrectly\n"); | |
1656 | return -EINVAL; | |
1657 | } | |
1658 | break; | |
1659 | case SSP_RX_32_OR_MORE_ELEM: | |
1660 | if (pl022->vendor->fifodepth < 32) { | |
1661 | dev_err(&pl022->adev->dev, | |
1662 | "RX FIFO Trigger Level is configured incorrectly\n"); | |
1663 | return -EINVAL; | |
1664 | } | |
1665 | break; | |
1666 | default: | |
5a1c98be | 1667 | dev_err(&pl022->adev->dev, |
b43d65f7 LW |
1668 | "RX FIFO Trigger Level is configured incorrectly\n"); |
1669 | return -EINVAL; | |
1670 | } | |
78b2b911 LW |
1671 | switch (chip_info->tx_lev_trig) { |
1672 | case SSP_TX_1_OR_MORE_EMPTY_LOC: | |
1673 | case SSP_TX_4_OR_MORE_EMPTY_LOC: | |
1674 | case SSP_TX_8_OR_MORE_EMPTY_LOC: | |
1675 | /* These are always OK, all variants can handle this */ | |
1676 | break; | |
1677 | case SSP_TX_16_OR_MORE_EMPTY_LOC: | |
1678 | if (pl022->vendor->fifodepth < 16) { | |
1679 | dev_err(&pl022->adev->dev, | |
1680 | "TX FIFO Trigger Level is configured incorrectly\n"); | |
1681 | return -EINVAL; | |
1682 | } | |
1683 | break; | |
1684 | case SSP_TX_32_OR_MORE_EMPTY_LOC: | |
1685 | if (pl022->vendor->fifodepth < 32) { | |
1686 | dev_err(&pl022->adev->dev, | |
1687 | "TX FIFO Trigger Level is configured incorrectly\n"); | |
1688 | return -EINVAL; | |
1689 | } | |
1690 | break; | |
1691 | default: | |
5a1c98be | 1692 | dev_err(&pl022->adev->dev, |
b43d65f7 LW |
1693 | "TX FIFO Trigger Level is configured incorrectly\n"); |
1694 | return -EINVAL; | |
1695 | } | |
b43d65f7 LW |
1696 | if (chip_info->iface == SSP_INTERFACE_NATIONAL_MICROWIRE) { |
1697 | if ((chip_info->ctrl_len < SSP_BITS_4) | |
1698 | || (chip_info->ctrl_len > SSP_BITS_32)) { | |
5a1c98be | 1699 | dev_err(&pl022->adev->dev, |
b43d65f7 LW |
1700 | "CTRL LEN is configured incorrectly\n"); |
1701 | return -EINVAL; | |
1702 | } | |
1703 | if ((chip_info->wait_state != SSP_MWIRE_WAIT_ZERO) | |
1704 | && (chip_info->wait_state != SSP_MWIRE_WAIT_ONE)) { | |
5a1c98be | 1705 | dev_err(&pl022->adev->dev, |
b43d65f7 LW |
1706 | "Wait State is configured incorrectly\n"); |
1707 | return -EINVAL; | |
1708 | } | |
556f4aeb LW |
1709 | /* Half duplex is only available in the ST Micro version */ |
1710 | if (pl022->vendor->extended_cr) { | |
1711 | if ((chip_info->duplex != | |
1712 | SSP_MICROWIRE_CHANNEL_FULL_DUPLEX) | |
1713 | && (chip_info->duplex != | |
4a4fd471 | 1714 | SSP_MICROWIRE_CHANNEL_HALF_DUPLEX)) { |
5a1c98be | 1715 | dev_err(&pl022->adev->dev, |
556f4aeb LW |
1716 | "Microwire duplex mode is configured incorrectly\n"); |
1717 | return -EINVAL; | |
4a4fd471 | 1718 | } |
556f4aeb LW |
1719 | } else { |
1720 | if (chip_info->duplex != SSP_MICROWIRE_CHANNEL_FULL_DUPLEX) | |
5a1c98be | 1721 | dev_err(&pl022->adev->dev, |
556f4aeb LW |
1722 | "Microwire half duplex mode requested," |
1723 | " but this is only available in the" | |
1724 | " ST version of PL022\n"); | |
b43d65f7 LW |
1725 | return -EINVAL; |
1726 | } | |
1727 | } | |
b43d65f7 LW |
1728 | return 0; |
1729 | } | |
1730 | ||
0379b2a3 VK |
1731 | static inline u32 spi_rate(u32 rate, u16 cpsdvsr, u16 scr) |
1732 | { | |
1733 | return rate / (cpsdvsr * (1 + scr)); | |
1734 | } | |
1735 | ||
1736 | static int calculate_effective_freq(struct pl022 *pl022, int freq, struct | |
1737 | ssp_clock_params * clk_freq) | |
b43d65f7 LW |
1738 | { |
1739 | /* Lets calculate the frequency parameters */ | |
0379b2a3 VK |
1740 | u16 cpsdvsr = CPSDVR_MIN, scr = SCR_MIN; |
1741 | u32 rate, max_tclk, min_tclk, best_freq = 0, best_cpsdvsr = 0, | |
1742 | best_scr = 0, tmp, found = 0; | |
b43d65f7 LW |
1743 | |
1744 | rate = clk_get_rate(pl022->clk); | |
1745 | /* cpsdvscr = 2 & scr 0 */ | |
0379b2a3 | 1746 | max_tclk = spi_rate(rate, CPSDVR_MIN, SCR_MIN); |
b43d65f7 | 1747 | /* cpsdvsr = 254 & scr = 255 */ |
0379b2a3 VK |
1748 | min_tclk = spi_rate(rate, CPSDVR_MAX, SCR_MAX); |
1749 | ||
ea505bc9 VK |
1750 | if (freq > max_tclk) |
1751 | dev_warn(&pl022->adev->dev, | |
1752 | "Max speed that can be programmed is %d Hz, you requested %d\n", | |
1753 | max_tclk, freq); | |
1754 | ||
1755 | if (freq < min_tclk) { | |
b43d65f7 | 1756 | dev_err(&pl022->adev->dev, |
ea505bc9 VK |
1757 | "Requested frequency: %d Hz is less than minimum possible %d Hz\n", |
1758 | freq, min_tclk); | |
b43d65f7 LW |
1759 | return -EINVAL; |
1760 | } | |
0379b2a3 VK |
1761 | |
1762 | /* | |
1763 | * best_freq will give closest possible available rate (<= requested | |
1764 | * freq) for all values of scr & cpsdvsr. | |
1765 | */ | |
1766 | while ((cpsdvsr <= CPSDVR_MAX) && !found) { | |
1767 | while (scr <= SCR_MAX) { | |
1768 | tmp = spi_rate(rate, cpsdvsr, scr); | |
1769 | ||
5eb806a3 VK |
1770 | if (tmp > freq) { |
1771 | /* we need lower freq */ | |
0379b2a3 | 1772 | scr++; |
5eb806a3 VK |
1773 | continue; |
1774 | } | |
1775 | ||
0379b2a3 | 1776 | /* |
5eb806a3 VK |
1777 | * If found exact value, mark found and break. |
1778 | * If found more closer value, update and break. | |
0379b2a3 | 1779 | */ |
5eb806a3 | 1780 | if (tmp > best_freq) { |
0379b2a3 VK |
1781 | best_freq = tmp; |
1782 | best_cpsdvsr = cpsdvsr; | |
1783 | best_scr = scr; | |
1784 | ||
1785 | if (tmp == freq) | |
5eb806a3 | 1786 | found = 1; |
0379b2a3 | 1787 | } |
5eb806a3 VK |
1788 | /* |
1789 | * increased scr will give lower rates, which are not | |
1790 | * required | |
1791 | */ | |
1792 | break; | |
0379b2a3 VK |
1793 | } |
1794 | cpsdvsr += 2; | |
1795 | scr = SCR_MIN; | |
1796 | } | |
1797 | ||
5eb806a3 VK |
1798 | WARN(!best_freq, "pl022: Matching cpsdvsr and scr not found for %d Hz rate \n", |
1799 | freq); | |
1800 | ||
0379b2a3 VK |
1801 | clk_freq->cpsdvsr = (u8) (best_cpsdvsr & 0xFF); |
1802 | clk_freq->scr = (u8) (best_scr & 0xFF); | |
1803 | dev_dbg(&pl022->adev->dev, | |
1804 | "SSP Target Frequency is: %u, Effective Frequency is %u\n", | |
1805 | freq, best_freq); | |
1806 | dev_dbg(&pl022->adev->dev, "SSP cpsdvsr = %d, scr = %d\n", | |
1807 | clk_freq->cpsdvsr, clk_freq->scr); | |
1808 | ||
b43d65f7 LW |
1809 | return 0; |
1810 | } | |
1811 | ||
f9d629c7 LW |
1812 | /* |
1813 | * A piece of default chip info unless the platform | |
1814 | * supplies it. | |
1815 | */ | |
1816 | static const struct pl022_config_chip pl022_default_chip_info = { | |
1817 | .com_mode = POLLING_TRANSFER, | |
1818 | .iface = SSP_INTERFACE_MOTOROLA_SPI, | |
1819 | .hierarchy = SSP_SLAVE, | |
1820 | .slave_tx_disable = DO_NOT_DRIVE_TX, | |
1821 | .rx_lev_trig = SSP_RX_1_OR_MORE_ELEM, | |
1822 | .tx_lev_trig = SSP_TX_1_OR_MORE_EMPTY_LOC, | |
1823 | .ctrl_len = SSP_BITS_8, | |
1824 | .wait_state = SSP_MWIRE_WAIT_ZERO, | |
1825 | .duplex = SSP_MICROWIRE_CHANNEL_FULL_DUPLEX, | |
1826 | .cs_control = null_cs_control, | |
1827 | }; | |
1828 | ||
b43d65f7 LW |
1829 | /** |
1830 | * pl022_setup - setup function registered to SPI master framework | |
1831 | * @spi: spi device which is requesting setup | |
1832 | * | |
1833 | * This function is registered to the SPI framework for this SPI master | |
1834 | * controller. If it is the first time when setup is called by this device, | |
1835 | * this function will initialize the runtime state for this chip and save | |
1836 | * the same in the device structure. Else it will update the runtime info | |
1837 | * with the updated chip info. Nothing is really being written to the | |
1838 | * controller hardware here, that is not done until the actual transfer | |
1839 | * commence. | |
1840 | */ | |
b43d65f7 LW |
1841 | static int pl022_setup(struct spi_device *spi) |
1842 | { | |
f9d629c7 | 1843 | struct pl022_config_chip const *chip_info; |
6d3952a7 | 1844 | struct pl022_config_chip chip_info_dt; |
b43d65f7 | 1845 | struct chip_data *chip; |
c4a47843 | 1846 | struct ssp_clock_params clk_freq = { .cpsdvsr = 0, .scr = 0}; |
b43d65f7 LW |
1847 | int status = 0; |
1848 | struct pl022 *pl022 = spi_master_get_devdata(spi->master); | |
bde435a9 KW |
1849 | unsigned int bits = spi->bits_per_word; |
1850 | u32 tmp; | |
6d3952a7 | 1851 | struct device_node *np = spi->dev.of_node; |
b43d65f7 LW |
1852 | |
1853 | if (!spi->max_speed_hz) | |
1854 | return -EINVAL; | |
1855 | ||
1856 | /* Get controller_state if one is supplied */ | |
1857 | chip = spi_get_ctldata(spi); | |
1858 | ||
1859 | if (chip == NULL) { | |
1860 | chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL); | |
77538f4a | 1861 | if (!chip) |
b43d65f7 | 1862 | return -ENOMEM; |
b43d65f7 LW |
1863 | dev_dbg(&spi->dev, |
1864 | "allocated memory for controller's runtime state\n"); | |
1865 | } | |
1866 | ||
1867 | /* Get controller data if one is supplied */ | |
1868 | chip_info = spi->controller_data; | |
1869 | ||
1870 | if (chip_info == NULL) { | |
6d3952a7 RS |
1871 | if (np) { |
1872 | chip_info_dt = pl022_default_chip_info; | |
1873 | ||
1874 | chip_info_dt.hierarchy = SSP_MASTER; | |
1875 | of_property_read_u32(np, "pl022,interface", | |
1876 | &chip_info_dt.iface); | |
1877 | of_property_read_u32(np, "pl022,com-mode", | |
1878 | &chip_info_dt.com_mode); | |
1879 | of_property_read_u32(np, "pl022,rx-level-trig", | |
1880 | &chip_info_dt.rx_lev_trig); | |
1881 | of_property_read_u32(np, "pl022,tx-level-trig", | |
1882 | &chip_info_dt.tx_lev_trig); | |
1883 | of_property_read_u32(np, "pl022,ctrl-len", | |
1884 | &chip_info_dt.ctrl_len); | |
1885 | of_property_read_u32(np, "pl022,wait-state", | |
1886 | &chip_info_dt.wait_state); | |
1887 | of_property_read_u32(np, "pl022,duplex", | |
1888 | &chip_info_dt.duplex); | |
1889 | ||
1890 | chip_info = &chip_info_dt; | |
1891 | } else { | |
1892 | chip_info = &pl022_default_chip_info; | |
1893 | /* spi_board_info.controller_data not is supplied */ | |
1894 | dev_dbg(&spi->dev, | |
1895 | "using default controller_data settings\n"); | |
1896 | } | |
f9d629c7 | 1897 | } else |
b43d65f7 LW |
1898 | dev_dbg(&spi->dev, |
1899 | "using user supplied controller_data settings\n"); | |
b43d65f7 LW |
1900 | |
1901 | /* | |
1902 | * We can override with custom divisors, else we use the board | |
1903 | * frequency setting | |
1904 | */ | |
1905 | if ((0 == chip_info->clk_freq.cpsdvsr) | |
1906 | && (0 == chip_info->clk_freq.scr)) { | |
1907 | status = calculate_effective_freq(pl022, | |
1908 | spi->max_speed_hz, | |
f9d629c7 | 1909 | &clk_freq); |
b43d65f7 LW |
1910 | if (status < 0) |
1911 | goto err_config_params; | |
1912 | } else { | |
f9d629c7 LW |
1913 | memcpy(&clk_freq, &chip_info->clk_freq, sizeof(clk_freq)); |
1914 | if ((clk_freq.cpsdvsr % 2) != 0) | |
1915 | clk_freq.cpsdvsr = | |
1916 | clk_freq.cpsdvsr - 1; | |
b43d65f7 | 1917 | } |
f9d629c7 LW |
1918 | if ((clk_freq.cpsdvsr < CPSDVR_MIN) |
1919 | || (clk_freq.cpsdvsr > CPSDVR_MAX)) { | |
e3f88ae9 | 1920 | status = -EINVAL; |
f9d629c7 LW |
1921 | dev_err(&spi->dev, |
1922 | "cpsdvsr is configured incorrectly\n"); | |
1923 | goto err_config_params; | |
1924 | } | |
1925 | ||
b43d65f7 LW |
1926 | status = verify_controller_parameters(pl022, chip_info); |
1927 | if (status) { | |
1928 | dev_err(&spi->dev, "controller data is incorrect"); | |
1929 | goto err_config_params; | |
1930 | } | |
f9d629c7 | 1931 | |
083be3f0 LW |
1932 | pl022->rx_lev_trig = chip_info->rx_lev_trig; |
1933 | pl022->tx_lev_trig = chip_info->tx_lev_trig; | |
1934 | ||
b43d65f7 LW |
1935 | /* Now set controller state based on controller data */ |
1936 | chip->xfer_type = chip_info->com_mode; | |
f9d629c7 LW |
1937 | if (!chip_info->cs_control) { |
1938 | chip->cs_control = null_cs_control; | |
f6f46de1 RS |
1939 | if (!gpio_is_valid(pl022->chipselects[spi->chip_select])) |
1940 | dev_warn(&spi->dev, | |
1941 | "invalid chip select\n"); | |
f9d629c7 LW |
1942 | } else |
1943 | chip->cs_control = chip_info->cs_control; | |
b43d65f7 | 1944 | |
eb798c64 VS |
1945 | /* Check bits per word with vendor specific range */ |
1946 | if ((bits <= 3) || (bits > pl022->vendor->max_bpw)) { | |
bde435a9 | 1947 | status = -ENOTSUPP; |
eb798c64 VS |
1948 | dev_err(&spi->dev, "illegal data size for this controller!\n"); |
1949 | dev_err(&spi->dev, "This controller can only handle 4 <= n <= %d bit words\n", | |
1950 | pl022->vendor->max_bpw); | |
bde435a9 KW |
1951 | goto err_config_params; |
1952 | } else if (bits <= 8) { | |
1953 | dev_dbg(&spi->dev, "4 <= n <=8 bits per word\n"); | |
b43d65f7 LW |
1954 | chip->n_bytes = 1; |
1955 | chip->read = READING_U8; | |
1956 | chip->write = WRITING_U8; | |
bde435a9 | 1957 | } else if (bits <= 16) { |
b43d65f7 LW |
1958 | dev_dbg(&spi->dev, "9 <= n <= 16 bits per word\n"); |
1959 | chip->n_bytes = 2; | |
1960 | chip->read = READING_U16; | |
1961 | chip->write = WRITING_U16; | |
1962 | } else { | |
eb798c64 VS |
1963 | dev_dbg(&spi->dev, "17 <= n <= 32 bits per word\n"); |
1964 | chip->n_bytes = 4; | |
1965 | chip->read = READING_U32; | |
1966 | chip->write = WRITING_U32; | |
b43d65f7 LW |
1967 | } |
1968 | ||
1969 | /* Now Initialize all register settings required for this chip */ | |
1970 | chip->cr0 = 0; | |
1971 | chip->cr1 = 0; | |
1972 | chip->dmacr = 0; | |
1973 | chip->cpsr = 0; | |
1974 | if ((chip_info->com_mode == DMA_TRANSFER) | |
1975 | && ((pl022->master_info)->enable_dma)) { | |
b1b6b9aa | 1976 | chip->enable_dma = true; |
b43d65f7 | 1977 | dev_dbg(&spi->dev, "DMA mode set in controller state\n"); |
b43d65f7 LW |
1978 | SSP_WRITE_BITS(chip->dmacr, SSP_DMA_ENABLED, |
1979 | SSP_DMACR_MASK_RXDMAE, 0); | |
1980 | SSP_WRITE_BITS(chip->dmacr, SSP_DMA_ENABLED, | |
1981 | SSP_DMACR_MASK_TXDMAE, 1); | |
1982 | } else { | |
b1b6b9aa | 1983 | chip->enable_dma = false; |
b43d65f7 LW |
1984 | dev_dbg(&spi->dev, "DMA mode NOT set in controller state\n"); |
1985 | SSP_WRITE_BITS(chip->dmacr, SSP_DMA_DISABLED, | |
1986 | SSP_DMACR_MASK_RXDMAE, 0); | |
1987 | SSP_WRITE_BITS(chip->dmacr, SSP_DMA_DISABLED, | |
1988 | SSP_DMACR_MASK_TXDMAE, 1); | |
1989 | } | |
1990 | ||
f9d629c7 | 1991 | chip->cpsr = clk_freq.cpsdvsr; |
b43d65f7 | 1992 | |
556f4aeb LW |
1993 | /* Special setup for the ST micro extended control registers */ |
1994 | if (pl022->vendor->extended_cr) { | |
bde435a9 KW |
1995 | u32 etx; |
1996 | ||
781c7b12 LW |
1997 | if (pl022->vendor->pl023) { |
1998 | /* These bits are only in the PL023 */ | |
1999 | SSP_WRITE_BITS(chip->cr1, chip_info->clkdelay, | |
2000 | SSP_CR1_MASK_FBCLKDEL_ST, 13); | |
2001 | } else { | |
2002 | /* These bits are in the PL022 but not PL023 */ | |
2003 | SSP_WRITE_BITS(chip->cr0, chip_info->duplex, | |
2004 | SSP_CR0_MASK_HALFDUP_ST, 5); | |
2005 | SSP_WRITE_BITS(chip->cr0, chip_info->ctrl_len, | |
2006 | SSP_CR0_MASK_CSS_ST, 16); | |
2007 | SSP_WRITE_BITS(chip->cr0, chip_info->iface, | |
2008 | SSP_CR0_MASK_FRF_ST, 21); | |
2009 | SSP_WRITE_BITS(chip->cr1, chip_info->wait_state, | |
2010 | SSP_CR1_MASK_MWAIT_ST, 6); | |
2011 | } | |
bde435a9 | 2012 | SSP_WRITE_BITS(chip->cr0, bits - 1, |
556f4aeb | 2013 | SSP_CR0_MASK_DSS_ST, 0); |
bde435a9 KW |
2014 | |
2015 | if (spi->mode & SPI_LSB_FIRST) { | |
2016 | tmp = SSP_RX_LSB; | |
2017 | etx = SSP_TX_LSB; | |
2018 | } else { | |
2019 | tmp = SSP_RX_MSB; | |
2020 | etx = SSP_TX_MSB; | |
2021 | } | |
2022 | SSP_WRITE_BITS(chip->cr1, tmp, SSP_CR1_MASK_RENDN_ST, 4); | |
2023 | SSP_WRITE_BITS(chip->cr1, etx, SSP_CR1_MASK_TENDN_ST, 5); | |
556f4aeb LW |
2024 | SSP_WRITE_BITS(chip->cr1, chip_info->rx_lev_trig, |
2025 | SSP_CR1_MASK_RXIFLSEL_ST, 7); | |
2026 | SSP_WRITE_BITS(chip->cr1, chip_info->tx_lev_trig, | |
2027 | SSP_CR1_MASK_TXIFLSEL_ST, 10); | |
2028 | } else { | |
bde435a9 | 2029 | SSP_WRITE_BITS(chip->cr0, bits - 1, |
556f4aeb LW |
2030 | SSP_CR0_MASK_DSS, 0); |
2031 | SSP_WRITE_BITS(chip->cr0, chip_info->iface, | |
2032 | SSP_CR0_MASK_FRF, 4); | |
2033 | } | |
bde435a9 | 2034 | |
556f4aeb | 2035 | /* Stuff that is common for all versions */ |
bde435a9 KW |
2036 | if (spi->mode & SPI_CPOL) |
2037 | tmp = SSP_CLK_POL_IDLE_HIGH; | |
2038 | else | |
2039 | tmp = SSP_CLK_POL_IDLE_LOW; | |
2040 | SSP_WRITE_BITS(chip->cr0, tmp, SSP_CR0_MASK_SPO, 6); | |
2041 | ||
2042 | if (spi->mode & SPI_CPHA) | |
2043 | tmp = SSP_CLK_SECOND_EDGE; | |
2044 | else | |
2045 | tmp = SSP_CLK_FIRST_EDGE; | |
2046 | SSP_WRITE_BITS(chip->cr0, tmp, SSP_CR0_MASK_SPH, 7); | |
2047 | ||
f9d629c7 | 2048 | SSP_WRITE_BITS(chip->cr0, clk_freq.scr, SSP_CR0_MASK_SCR, 8); |
781c7b12 | 2049 | /* Loopback is available on all versions except PL023 */ |
06fb01fd | 2050 | if (pl022->vendor->loopback) { |
bde435a9 KW |
2051 | if (spi->mode & SPI_LOOP) |
2052 | tmp = LOOPBACK_ENABLED; | |
2053 | else | |
2054 | tmp = LOOPBACK_DISABLED; | |
2055 | SSP_WRITE_BITS(chip->cr1, tmp, SSP_CR1_MASK_LBM, 0); | |
2056 | } | |
b43d65f7 LW |
2057 | SSP_WRITE_BITS(chip->cr1, SSP_DISABLED, SSP_CR1_MASK_SSE, 1); |
2058 | SSP_WRITE_BITS(chip->cr1, chip_info->hierarchy, SSP_CR1_MASK_MS, 2); | |
f1e45f86 VK |
2059 | SSP_WRITE_BITS(chip->cr1, chip_info->slave_tx_disable, SSP_CR1_MASK_SOD, |
2060 | 3); | |
b43d65f7 LW |
2061 | |
2062 | /* Save controller_state */ | |
2063 | spi_set_ctldata(spi, chip); | |
2064 | return status; | |
2065 | err_config_params: | |
bde435a9 | 2066 | spi_set_ctldata(spi, NULL); |
b43d65f7 LW |
2067 | kfree(chip); |
2068 | return status; | |
2069 | } | |
2070 | ||
2071 | /** | |
2072 | * pl022_cleanup - cleanup function registered to SPI master framework | |
2073 | * @spi: spi device which is requesting cleanup | |
2074 | * | |
2075 | * This function is registered to the SPI framework for this SPI master | |
2076 | * controller. It will free the runtime state of chip. | |
2077 | */ | |
2078 | static void pl022_cleanup(struct spi_device *spi) | |
2079 | { | |
2080 | struct chip_data *chip = spi_get_ctldata(spi); | |
2081 | ||
2082 | spi_set_ctldata(spi, NULL); | |
2083 | kfree(chip); | |
2084 | } | |
2085 | ||
39a6ac11 RS |
2086 | static struct pl022_ssp_controller * |
2087 | pl022_platform_data_dt_get(struct device *dev) | |
2088 | { | |
2089 | struct device_node *np = dev->of_node; | |
2090 | struct pl022_ssp_controller *pd; | |
849794c5 | 2091 | u32 tmp = 0; |
39a6ac11 RS |
2092 | |
2093 | if (!np) { | |
2094 | dev_err(dev, "no dt node defined\n"); | |
2095 | return NULL; | |
2096 | } | |
2097 | ||
2098 | pd = devm_kzalloc(dev, sizeof(struct pl022_ssp_controller), GFP_KERNEL); | |
77538f4a | 2099 | if (!pd) |
39a6ac11 | 2100 | return NULL; |
39a6ac11 RS |
2101 | |
2102 | pd->bus_id = -1; | |
dbd897b9 | 2103 | pd->enable_dma = 1; |
39a6ac11 RS |
2104 | of_property_read_u32(np, "num-cs", &tmp); |
2105 | pd->num_chipselect = tmp; | |
2106 | of_property_read_u32(np, "pl022,autosuspend-delay", | |
2107 | &pd->autosuspend_delay); | |
2108 | pd->rt = of_property_read_bool(np, "pl022,rt"); | |
2109 | ||
2110 | return pd; | |
2111 | } | |
2112 | ||
fd4a319b | 2113 | static int pl022_probe(struct amba_device *adev, const struct amba_id *id) |
b43d65f7 LW |
2114 | { |
2115 | struct device *dev = &adev->dev; | |
8074cf06 JH |
2116 | struct pl022_ssp_controller *platform_info = |
2117 | dev_get_platdata(&adev->dev); | |
b43d65f7 LW |
2118 | struct spi_master *master; |
2119 | struct pl022 *pl022 = NULL; /*Data for this driver */ | |
6d3952a7 RS |
2120 | struct device_node *np = adev->dev.of_node; |
2121 | int status = 0, i, num_cs; | |
b43d65f7 LW |
2122 | |
2123 | dev_info(&adev->dev, | |
2124 | "ARM PL022 driver, device ID: 0x%08x\n", adev->periphid); | |
39a6ac11 RS |
2125 | if (!platform_info && IS_ENABLED(CONFIG_OF)) |
2126 | platform_info = pl022_platform_data_dt_get(dev); | |
2127 | ||
2128 | if (!platform_info) { | |
2129 | dev_err(dev, "probe: no platform data defined\n"); | |
aeef9915 | 2130 | return -ENODEV; |
b43d65f7 LW |
2131 | } |
2132 | ||
6d3952a7 RS |
2133 | if (platform_info->num_chipselect) { |
2134 | num_cs = platform_info->num_chipselect; | |
6d3952a7 | 2135 | } else { |
39a6ac11 | 2136 | dev_err(dev, "probe: no chip select defined\n"); |
aeef9915 | 2137 | return -ENODEV; |
6d3952a7 RS |
2138 | } |
2139 | ||
b43d65f7 | 2140 | /* Allocate master with space for data */ |
b4b84826 | 2141 | master = spi_alloc_master(dev, sizeof(struct pl022)); |
b43d65f7 LW |
2142 | if (master == NULL) { |
2143 | dev_err(&adev->dev, "probe - cannot alloc SPI master\n"); | |
aeef9915 | 2144 | return -ENOMEM; |
b43d65f7 LW |
2145 | } |
2146 | ||
2147 | pl022 = spi_master_get_devdata(master); | |
2148 | pl022->master = master; | |
2149 | pl022->master_info = platform_info; | |
2150 | pl022->adev = adev; | |
2151 | pl022->vendor = id->data; | |
a86854d0 | 2152 | pl022->chipselects = devm_kcalloc(dev, num_cs, sizeof(int), |
b4b84826 | 2153 | GFP_KERNEL); |
73e3f1eb KP |
2154 | if (!pl022->chipselects) { |
2155 | status = -ENOMEM; | |
2156 | goto err_no_mem; | |
2157 | } | |
b43d65f7 LW |
2158 | |
2159 | /* | |
2160 | * Bus Number Which has been Assigned to this SSP controller | |
2161 | * on this board | |
2162 | */ | |
2163 | master->bus_num = platform_info->bus_id; | |
6d3952a7 | 2164 | master->num_chipselect = num_cs; |
b43d65f7 LW |
2165 | master->cleanup = pl022_cleanup; |
2166 | master->setup = pl022_setup; | |
29b6e906 | 2167 | master->auto_runtime_pm = true; |
ffbbdd21 LW |
2168 | master->transfer_one_message = pl022_transfer_one_message; |
2169 | master->unprepare_transfer_hardware = pl022_unprepare_transfer_hardware; | |
2170 | master->rt = platform_info->rt; | |
6d3952a7 | 2171 | master->dev.of_node = dev->of_node; |
b43d65f7 | 2172 | |
6d3952a7 RS |
2173 | if (platform_info->num_chipselect && platform_info->chipselects) { |
2174 | for (i = 0; i < num_cs; i++) | |
f6f46de1 | 2175 | pl022->chipselects[i] = platform_info->chipselects[i]; |
db4fa45e AB |
2176 | } else if (pl022->vendor->internal_cs_ctrl) { |
2177 | for (i = 0; i < num_cs; i++) | |
2178 | pl022->chipselects[i] = i; | |
6d3952a7 RS |
2179 | } else if (IS_ENABLED(CONFIG_OF)) { |
2180 | for (i = 0; i < num_cs; i++) { | |
2181 | int cs_gpio = of_get_named_gpio(np, "cs-gpios", i); | |
2182 | ||
2183 | if (cs_gpio == -EPROBE_DEFER) { | |
2184 | status = -EPROBE_DEFER; | |
2185 | goto err_no_gpio; | |
2186 | } | |
2187 | ||
2188 | pl022->chipselects[i] = cs_gpio; | |
2189 | ||
2190 | if (gpio_is_valid(cs_gpio)) { | |
aeef9915 | 2191 | if (devm_gpio_request(dev, cs_gpio, "ssp-pl022")) |
6d3952a7 RS |
2192 | dev_err(&adev->dev, |
2193 | "could not request %d gpio\n", | |
2194 | cs_gpio); | |
2195 | else if (gpio_direction_output(cs_gpio, 1)) | |
2196 | dev_err(&adev->dev, | |
61e89e65 | 2197 | "could not set gpio %d as output\n", |
6d3952a7 RS |
2198 | cs_gpio); |
2199 | } | |
2200 | } | |
2201 | } | |
f6f46de1 | 2202 | |
bde435a9 KW |
2203 | /* |
2204 | * Supports mode 0-3, loopback, and active low CS. Transfers are | |
2205 | * always MS bit first on the original pl022. | |
2206 | */ | |
2207 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP; | |
2208 | if (pl022->vendor->extended_cr) | |
2209 | master->mode_bits |= SPI_LSB_FIRST; | |
2210 | ||
b43d65f7 LW |
2211 | dev_dbg(&adev->dev, "BUSNO: %d\n", master->bus_num); |
2212 | ||
2213 | status = amba_request_regions(adev, NULL); | |
2214 | if (status) | |
2215 | goto err_no_ioregion; | |
2216 | ||
b1b6b9aa | 2217 | pl022->phybase = adev->res.start; |
aeef9915 LW |
2218 | pl022->virtbase = devm_ioremap(dev, adev->res.start, |
2219 | resource_size(&adev->res)); | |
b43d65f7 LW |
2220 | if (pl022->virtbase == NULL) { |
2221 | status = -ENOMEM; | |
2222 | goto err_no_ioremap; | |
2223 | } | |
2c067509 JH |
2224 | dev_info(&adev->dev, "mapped registers from %pa to %p\n", |
2225 | &adev->res.start, pl022->virtbase); | |
b43d65f7 | 2226 | |
aeef9915 | 2227 | pl022->clk = devm_clk_get(&adev->dev, NULL); |
b43d65f7 LW |
2228 | if (IS_ERR(pl022->clk)) { |
2229 | status = PTR_ERR(pl022->clk); | |
2230 | dev_err(&adev->dev, "could not retrieve SSP/SPI bus clock\n"); | |
2231 | goto err_no_clk; | |
2232 | } | |
7ff6bcf0 | 2233 | |
6cac167b | 2234 | status = clk_prepare_enable(pl022->clk); |
71e63e74 UH |
2235 | if (status) { |
2236 | dev_err(&adev->dev, "could not enable SSP/SPI bus clock\n"); | |
2237 | goto err_no_clk_en; | |
2238 | } | |
2239 | ||
ffbbdd21 LW |
2240 | /* Initialize transfer pump */ |
2241 | tasklet_init(&pl022->pump_transfers, pump_transfers, | |
2242 | (unsigned long)pl022); | |
2243 | ||
b43d65f7 | 2244 | /* Disable SSP */ |
b43d65f7 LW |
2245 | writew((readw(SSP_CR1(pl022->virtbase)) & (~SSP_CR1_MASK_SSE)), |
2246 | SSP_CR1(pl022->virtbase)); | |
2247 | load_ssp_default_config(pl022); | |
b43d65f7 | 2248 | |
aeef9915 LW |
2249 | status = devm_request_irq(dev, adev->irq[0], pl022_interrupt_handler, |
2250 | 0, "pl022", pl022); | |
b43d65f7 LW |
2251 | if (status < 0) { |
2252 | dev_err(&adev->dev, "probe - cannot get IRQ (%d)\n", status); | |
2253 | goto err_no_irq; | |
2254 | } | |
b1b6b9aa | 2255 | |
dc715452 AB |
2256 | /* Get DMA channels, try autoconfiguration first */ |
2257 | status = pl022_dma_autoprobe(pl022); | |
f3d4bb33 RV |
2258 | if (status == -EPROBE_DEFER) { |
2259 | dev_dbg(dev, "deferring probe to get DMA channel\n"); | |
2260 | goto err_no_irq; | |
2261 | } | |
dc715452 AB |
2262 | |
2263 | /* If that failed, use channels from platform_info */ | |
2264 | if (status == 0) | |
2265 | platform_info->enable_dma = 1; | |
2266 | else if (platform_info->enable_dma) { | |
b1b6b9aa LW |
2267 | status = pl022_dma_probe(pl022); |
2268 | if (status != 0) | |
43c64015 | 2269 | platform_info->enable_dma = 0; |
b1b6b9aa LW |
2270 | } |
2271 | ||
b43d65f7 LW |
2272 | /* Register with the SPI framework */ |
2273 | amba_set_drvdata(adev, pl022); | |
35794a77 | 2274 | status = devm_spi_register_master(&adev->dev, master); |
b43d65f7 LW |
2275 | if (status != 0) { |
2276 | dev_err(&adev->dev, | |
2277 | "probe - problem registering spi master\n"); | |
2278 | goto err_spi_register; | |
2279 | } | |
25985edc | 2280 | dev_dbg(dev, "probe succeeded\n"); |
92b97f0a RK |
2281 | |
2282 | /* let runtime pm put suspend */ | |
53e4acea CB |
2283 | if (platform_info->autosuspend_delay > 0) { |
2284 | dev_info(&adev->dev, | |
2285 | "will use autosuspend for runtime pm, delay %dms\n", | |
2286 | platform_info->autosuspend_delay); | |
2287 | pm_runtime_set_autosuspend_delay(dev, | |
2288 | platform_info->autosuspend_delay); | |
2289 | pm_runtime_use_autosuspend(dev); | |
53e4acea | 2290 | } |
0df34994 UH |
2291 | pm_runtime_put(dev); |
2292 | ||
b43d65f7 LW |
2293 | return 0; |
2294 | ||
2295 | err_spi_register: | |
3e3ea716 VK |
2296 | if (platform_info->enable_dma) |
2297 | pl022_dma_remove(pl022); | |
b43d65f7 | 2298 | err_no_irq: |
6cac167b | 2299 | clk_disable_unprepare(pl022->clk); |
71e63e74 | 2300 | err_no_clk_en: |
b43d65f7 | 2301 | err_no_clk: |
b43d65f7 LW |
2302 | err_no_ioremap: |
2303 | amba_release_regions(adev); | |
2304 | err_no_ioregion: | |
6d3952a7 | 2305 | err_no_gpio: |
73e3f1eb | 2306 | err_no_mem: |
b43d65f7 | 2307 | spi_master_put(master); |
b43d65f7 LW |
2308 | return status; |
2309 | } | |
2310 | ||
fd4a319b | 2311 | static int |
b43d65f7 LW |
2312 | pl022_remove(struct amba_device *adev) |
2313 | { | |
2314 | struct pl022 *pl022 = amba_get_drvdata(adev); | |
50658b66 | 2315 | |
b43d65f7 LW |
2316 | if (!pl022) |
2317 | return 0; | |
2318 | ||
92b97f0a RK |
2319 | /* |
2320 | * undo pm_runtime_put() in probe. I assume that we're not | |
2321 | * accessing the primecell here. | |
2322 | */ | |
2323 | pm_runtime_get_noresume(&adev->dev); | |
2324 | ||
b43d65f7 | 2325 | load_ssp_default_config(pl022); |
3e3ea716 VK |
2326 | if (pl022->master_info->enable_dma) |
2327 | pl022_dma_remove(pl022); | |
2328 | ||
6cac167b | 2329 | clk_disable_unprepare(pl022->clk); |
b43d65f7 LW |
2330 | amba_release_regions(adev); |
2331 | tasklet_disable(&pl022->pump_transfers); | |
b43d65f7 LW |
2332 | return 0; |
2333 | } | |
2334 | ||
84a5dc41 | 2335 | #ifdef CONFIG_PM_SLEEP |
6cfa6279 | 2336 | static int pl022_suspend(struct device *dev) |
b43d65f7 | 2337 | { |
92b97f0a | 2338 | struct pl022 *pl022 = dev_get_drvdata(dev); |
ffbbdd21 | 2339 | int ret; |
b43d65f7 | 2340 | |
ffbbdd21 | 2341 | ret = spi_master_suspend(pl022->master); |
7c5d8a24 | 2342 | if (ret) |
ffbbdd21 | 2343 | return ret; |
4964a26d | 2344 | |
84a5dc41 UH |
2345 | ret = pm_runtime_force_suspend(dev); |
2346 | if (ret) { | |
2347 | spi_master_resume(pl022->master); | |
2348 | return ret; | |
2349 | } | |
2350 | ||
2351 | pinctrl_pm_select_sleep_state(dev); | |
b43d65f7 | 2352 | |
6cfa6279 | 2353 | dev_dbg(dev, "suspended\n"); |
b43d65f7 LW |
2354 | return 0; |
2355 | } | |
2356 | ||
92b97f0a | 2357 | static int pl022_resume(struct device *dev) |
b43d65f7 | 2358 | { |
92b97f0a | 2359 | struct pl022 *pl022 = dev_get_drvdata(dev); |
ffbbdd21 | 2360 | int ret; |
b43d65f7 | 2361 | |
84a5dc41 UH |
2362 | ret = pm_runtime_force_resume(dev); |
2363 | if (ret) | |
2364 | dev_err(dev, "problem resuming\n"); | |
ada7aec7 | 2365 | |
b43d65f7 | 2366 | /* Start the queue running */ |
ffbbdd21 | 2367 | ret = spi_master_resume(pl022->master); |
7c5d8a24 | 2368 | if (!ret) |
92b97f0a | 2369 | dev_dbg(dev, "resumed\n"); |
b43d65f7 | 2370 | |
ffbbdd21 | 2371 | return ret; |
b43d65f7 | 2372 | } |
84a5dc41 | 2373 | #endif |
b43d65f7 | 2374 | |
736198b0 | 2375 | #ifdef CONFIG_PM |
92b97f0a RK |
2376 | static int pl022_runtime_suspend(struct device *dev) |
2377 | { | |
2378 | struct pl022 *pl022 = dev_get_drvdata(dev); | |
4f5e1b37 | 2379 | |
84a5dc41 UH |
2380 | clk_disable_unprepare(pl022->clk); |
2381 | pinctrl_pm_select_idle_state(dev); | |
2382 | ||
92b97f0a RK |
2383 | return 0; |
2384 | } | |
2385 | ||
2386 | static int pl022_runtime_resume(struct device *dev) | |
2387 | { | |
2388 | struct pl022 *pl022 = dev_get_drvdata(dev); | |
92b97f0a | 2389 | |
84a5dc41 UH |
2390 | pinctrl_pm_select_default_state(dev); |
2391 | clk_prepare_enable(pl022->clk); | |
2392 | ||
92b97f0a RK |
2393 | return 0; |
2394 | } | |
2395 | #endif | |
2396 | ||
2397 | static const struct dev_pm_ops pl022_dev_pm_ops = { | |
2398 | SET_SYSTEM_SLEEP_PM_OPS(pl022_suspend, pl022_resume) | |
6ed23b80 | 2399 | SET_RUNTIME_PM_OPS(pl022_runtime_suspend, pl022_runtime_resume, NULL) |
92b97f0a RK |
2400 | }; |
2401 | ||
b43d65f7 LW |
2402 | static struct vendor_data vendor_arm = { |
2403 | .fifodepth = 8, | |
2404 | .max_bpw = 16, | |
2405 | .unidir = false, | |
556f4aeb | 2406 | .extended_cr = false, |
781c7b12 | 2407 | .pl023 = false, |
06fb01fd | 2408 | .loopback = true, |
db4fa45e | 2409 | .internal_cs_ctrl = false, |
b43d65f7 LW |
2410 | }; |
2411 | ||
b43d65f7 LW |
2412 | static struct vendor_data vendor_st = { |
2413 | .fifodepth = 32, | |
2414 | .max_bpw = 32, | |
2415 | .unidir = false, | |
556f4aeb | 2416 | .extended_cr = true, |
781c7b12 | 2417 | .pl023 = false, |
06fb01fd | 2418 | .loopback = true, |
db4fa45e | 2419 | .internal_cs_ctrl = false, |
781c7b12 LW |
2420 | }; |
2421 | ||
2422 | static struct vendor_data vendor_st_pl023 = { | |
2423 | .fifodepth = 32, | |
2424 | .max_bpw = 32, | |
2425 | .unidir = false, | |
2426 | .extended_cr = true, | |
2427 | .pl023 = true, | |
06fb01fd | 2428 | .loopback = false, |
db4fa45e AB |
2429 | .internal_cs_ctrl = false, |
2430 | }; | |
2431 | ||
2432 | static struct vendor_data vendor_lsi = { | |
2433 | .fifodepth = 8, | |
2434 | .max_bpw = 16, | |
2435 | .unidir = false, | |
2436 | .extended_cr = false, | |
2437 | .pl023 = false, | |
2438 | .loopback = true, | |
2439 | .internal_cs_ctrl = true, | |
06fb01fd PL |
2440 | }; |
2441 | ||
5b8d5ad2 | 2442 | static const struct amba_id pl022_ids[] = { |
b43d65f7 LW |
2443 | { |
2444 | /* | |
2445 | * ARM PL022 variant, this has a 16bit wide | |
2446 | * and 8 locations deep TX/RX FIFO | |
2447 | */ | |
2448 | .id = 0x00041022, | |
2449 | .mask = 0x000fffff, | |
2450 | .data = &vendor_arm, | |
2451 | }, | |
2452 | { | |
2453 | /* | |
2454 | * ST Micro derivative, this has 32bit wide | |
2455 | * and 32 locations deep TX/RX FIFO | |
2456 | */ | |
e89e04fc | 2457 | .id = 0x01080022, |
b43d65f7 LW |
2458 | .mask = 0xffffffff, |
2459 | .data = &vendor_st, | |
2460 | }, | |
781c7b12 LW |
2461 | { |
2462 | /* | |
2463 | * ST-Ericsson derivative "PL023" (this is not | |
2464 | * an official ARM number), this is a PL022 SSP block | |
2465 | * stripped to SPI mode only, it has 32bit wide | |
2466 | * and 32 locations deep TX/RX FIFO but no extended | |
2467 | * CR0/CR1 register | |
2468 | */ | |
f1e45f86 VK |
2469 | .id = 0x00080023, |
2470 | .mask = 0xffffffff, | |
2471 | .data = &vendor_st_pl023, | |
781c7b12 | 2472 | }, |
db4fa45e AB |
2473 | { |
2474 | /* | |
2475 | * PL022 variant that has a chip select control register whih | |
2476 | * allows control of 5 output signals nCS[0:4]. | |
2477 | */ | |
2478 | .id = 0x000b6022, | |
2479 | .mask = 0x000fffff, | |
2480 | .data = &vendor_lsi, | |
2481 | }, | |
b43d65f7 LW |
2482 | { 0, 0 }, |
2483 | }; | |
2484 | ||
7eeac71b DM |
2485 | MODULE_DEVICE_TABLE(amba, pl022_ids); |
2486 | ||
b43d65f7 LW |
2487 | static struct amba_driver pl022_driver = { |
2488 | .drv = { | |
2489 | .name = "ssp-pl022", | |
92b97f0a | 2490 | .pm = &pl022_dev_pm_ops, |
b43d65f7 LW |
2491 | }, |
2492 | .id_table = pl022_ids, | |
2493 | .probe = pl022_probe, | |
fd4a319b | 2494 | .remove = pl022_remove, |
b43d65f7 LW |
2495 | }; |
2496 | ||
b43d65f7 LW |
2497 | static int __init pl022_init(void) |
2498 | { | |
2499 | return amba_driver_register(&pl022_driver); | |
2500 | } | |
25c8e03b | 2501 | subsys_initcall(pl022_init); |
b43d65f7 LW |
2502 | |
2503 | static void __exit pl022_exit(void) | |
2504 | { | |
2505 | amba_driver_unregister(&pl022_driver); | |
2506 | } | |
b43d65f7 LW |
2507 | module_exit(pl022_exit); |
2508 | ||
2509 | MODULE_AUTHOR("Linus Walleij <linus.walleij@stericsson.com>"); | |
2510 | MODULE_DESCRIPTION("PL022 SSP Controller Driver"); | |
2511 | MODULE_LICENSE("GPL"); |