[linux-2.6-block.git] / drivers / spi / spi-orion.c

/*
 * Marvell Orion SPI controller driver
 *
 * Author: Shadi Ammouri <shadi@marvell.com>
 * Copyright (C) 2007-2008 Marvell Ltd.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/interrupt.h>
#include <linux/delay.h>
#include <linux/platform_device.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/spi/spi.h>
#include <linux/module.h>
#include <linux/pm_runtime.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/clk.h>
#include <linux/sizes.h>
#include <asm/unaligned.h>

#define DRIVER_NAME			"orion_spi"

/* Runtime PM autosuspend timeout: PM is fairly light on this driver */
#define SPI_AUTOSUSPEND_TIMEOUT		200

/* Some SoCs using this driver support up to 8 chip selects.
 * It is up to the implementer to only use the chip selects
 * that are available.
 */
#define ORION_NUM_CHIPSELECTS		8

#define ORION_SPI_WAIT_RDY_MAX_LOOP	2000 /* in usec */

#define ORION_SPI_IF_CTRL_REG		0x00
#define ORION_SPI_IF_CONFIG_REG		0x04
#define ORION_SPI_DATA_OUT_REG		0x08
#define ORION_SPI_DATA_IN_REG		0x0c
#define ORION_SPI_INT_CAUSE_REG		0x10

#define ORION_SPI_MODE_CPOL		(1 << 11)
#define ORION_SPI_MODE_CPHA		(1 << 12)
#define ORION_SPI_IF_8_16_BIT_MODE	(1 << 5)
#define ORION_SPI_CLK_PRESCALE_MASK	0x1F
#define ARMADA_SPI_CLK_PRESCALE_MASK	0xDF
#define ORION_SPI_MODE_MASK		(ORION_SPI_MODE_CPOL | \
					 ORION_SPI_MODE_CPHA)
#define ORION_SPI_CS_MASK	0x1C
#define ORION_SPI_CS_SHIFT	2
#define ORION_SPI_CS(cs)	((cs << ORION_SPI_CS_SHIFT) & \
					ORION_SPI_CS_MASK)

enum orion_spi_type {
	ORION_SPI,
	ARMADA_SPI,
};

struct orion_spi_dev {
	enum orion_spi_type	typ;
	unsigned int		min_divisor;
	unsigned int		max_divisor;
	u32			prescale_mask;
};

struct orion_spi {
	struct spi_master	*master;
	void __iomem		*base;
	struct clk              *clk;
	const struct orion_spi_dev *devdata;
};

static inline void __iomem *spi_reg(struct orion_spi *orion_spi, u32 reg)
{
	return orion_spi->base + reg;
}

static inline void
orion_spi_setbits(struct orion_spi *orion_spi, u32 reg, u32 mask)
{
	void __iomem *reg_addr = spi_reg(orion_spi, reg);
	u32 val;

	val = readl(reg_addr);
	val |= mask;
	writel(val, reg_addr);
}

static inline void
orion_spi_clrbits(struct orion_spi *orion_spi, u32 reg, u32 mask)
{
	void __iomem *reg_addr = spi_reg(orion_spi, reg);
	u32 val;

	val = readl(reg_addr);
	val &= ~mask;
	writel(val, reg_addr);
}

static int orion_spi_baudrate_set(struct spi_device *spi, unsigned int speed)
{
	u32 tclk_hz;
	u32 rate;
	u32 prescale;
	u32 reg;
	struct orion_spi *orion_spi;
	const struct orion_spi_dev *devdata;

	orion_spi = spi_master_get_devdata(spi->master);
	devdata = orion_spi->devdata;

	tclk_hz = clk_get_rate(orion_spi->clk);

	if (devdata->typ == ARMADA_SPI) {
		unsigned int clk, spr, sppr, sppr2, err;
		unsigned int best_spr, best_sppr, best_err;

		best_err = speed;
		best_spr = 0;
		best_sppr = 0;

		/* Iterate over the valid range looking for best fit */
		for (sppr = 0; sppr < 8; sppr++) {
			sppr2 = 0x1 << sppr;

			spr = tclk_hz / sppr2;
			spr = DIV_ROUND_UP(spr, speed);
			if ((spr == 0) || (spr > 15))
				continue;

			clk = tclk_hz / (spr * sppr2);
			err = speed - clk;

			if (err < best_err) {
				best_spr = spr;
				best_sppr = sppr;
				best_err = err;
			}
		}

		if ((best_sppr == 0) && (best_spr == 0))
			return -EINVAL;

		prescale = ((best_sppr & 0x6) << 5) |
			((best_sppr & 0x1) << 4) | best_spr;
	} else {
		/*
		 * the supported rates are: 4,6,8...30
		 * round up as we look for equal or less speed
		 */
		rate = DIV_ROUND_UP(tclk_hz, speed);
		rate = roundup(rate, 2);

		/* check if requested speed is too small */
		if (rate > 30)
			return -EINVAL;

		if (rate < 4)
			rate = 4;

		/* Convert the rate to SPI clock divisor value.	*/
		prescale = 0x10 + rate/2;
	}

	reg = readl(spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG));
	reg = ((reg & ~devdata->prescale_mask) | prescale);
	writel(reg, spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG));

	return 0;
}

static void
orion_spi_mode_set(struct spi_device *spi)
{
	u32 reg;
	struct orion_spi *orion_spi;

	orion_spi = spi_master_get_devdata(spi->master);

	reg = readl(spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG));
	reg &= ~ORION_SPI_MODE_MASK;
	if (spi->mode & SPI_CPOL)
		reg |= ORION_SPI_MODE_CPOL;
	if (spi->mode & SPI_CPHA)
		reg |= ORION_SPI_MODE_CPHA;
	writel(reg, spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG));
}

/*
 * called only when no transfer is active on the bus
 */
static int
orion_spi_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
{
	struct orion_spi *orion_spi;
	unsigned int speed = spi->max_speed_hz;
	unsigned int bits_per_word = spi->bits_per_word;
	int	rc;

	orion_spi = spi_master_get_devdata(spi->master);

	if ((t != NULL) && t->speed_hz)
		speed = t->speed_hz;

	if ((t != NULL) && t->bits_per_word)
		bits_per_word = t->bits_per_word;

	orion_spi_mode_set(spi);

	rc = orion_spi_baudrate_set(spi, speed);
	if (rc)
		return rc;

	if (bits_per_word == 16)
		orion_spi_setbits(orion_spi, ORION_SPI_IF_CONFIG_REG,
				  ORION_SPI_IF_8_16_BIT_MODE);
	else
		orion_spi_clrbits(orion_spi, ORION_SPI_IF_CONFIG_REG,
				  ORION_SPI_IF_8_16_BIT_MODE);

	return 0;
}

static void orion_spi_set_cs(struct spi_device *spi, bool enable)
{
	struct orion_spi *orion_spi;

	orion_spi = spi_master_get_devdata(spi->master);

	orion_spi_clrbits(orion_spi, ORION_SPI_IF_CTRL_REG, ORION_SPI_CS_MASK);
	orion_spi_setbits(orion_spi, ORION_SPI_IF_CTRL_REG,
				ORION_SPI_CS(spi->chip_select));

	/* Chip select logic is inverted from spi_set_cs */
	if (!enable)
		orion_spi_setbits(orion_spi, ORION_SPI_IF_CTRL_REG, 0x1);
	else
		orion_spi_clrbits(orion_spi, ORION_SPI_IF_CTRL_REG, 0x1);
}

static inline int orion_spi_wait_till_ready(struct orion_spi *orion_spi)
{
	int i;

	for (i = 0; i < ORION_SPI_WAIT_RDY_MAX_LOOP; i++) {
		if (readl(spi_reg(orion_spi, ORION_SPI_INT_CAUSE_REG)))
			return 1;

		udelay(1);
	}

	return -1;
}

static inline int
orion_spi_write_read_8bit(struct spi_device *spi,
			  const u8 **tx_buf, u8 **rx_buf)
{
	void __iomem *tx_reg, *rx_reg, *int_reg;
	struct orion_spi *orion_spi;

	orion_spi = spi_master_get_devdata(spi->master);
	tx_reg = spi_reg(orion_spi, ORION_SPI_DATA_OUT_REG);
	rx_reg = spi_reg(orion_spi, ORION_SPI_DATA_IN_REG);
	int_reg = spi_reg(orion_spi, ORION_SPI_INT_CAUSE_REG);

	/* clear the interrupt cause register */
	writel(0x0, int_reg);

	if (tx_buf && *tx_buf)
		writel(*(*tx_buf)++, tx_reg);
	else
		writel(0, tx_reg);

	if (orion_spi_wait_till_ready(orion_spi) < 0) {
		dev_err(&spi->dev, "TXS timed out\n");
		return -1;
	}

	if (rx_buf && *rx_buf)
		*(*rx_buf)++ = readl(rx_reg);

	return 1;
}

static inline int
orion_spi_write_read_16bit(struct spi_device *spi,
			   const u16 **tx_buf, u16 **rx_buf)
{
	void __iomem *tx_reg, *rx_reg, *int_reg;
	struct orion_spi *orion_spi;

	orion_spi = spi_master_get_devdata(spi->master);
	tx_reg = spi_reg(orion_spi, ORION_SPI_DATA_OUT_REG);
	rx_reg = spi_reg(orion_spi, ORION_SPI_DATA_IN_REG);
	int_reg = spi_reg(orion_spi, ORION_SPI_INT_CAUSE_REG);

	/* clear the interrupt cause register */
	writel(0x0, int_reg);

	if (tx_buf && *tx_buf)
		writel(__cpu_to_le16(get_unaligned((*tx_buf)++)), tx_reg);
	else
		writel(0, tx_reg);

	if (orion_spi_wait_till_ready(orion_spi) < 0) {
		dev_err(&spi->dev, "TXS timed out\n");
		return -1;
	}

	if (rx_buf && *rx_buf)
		put_unaligned(__le16_to_cpu(readl(rx_reg)), (*rx_buf)++);

	return 1;
}

static unsigned int
orion_spi_write_read(struct spi_device *spi, struct spi_transfer *xfer)
{
	unsigned int count;
	int word_len;

	word_len = spi->bits_per_word;
	count = xfer->len;

	if (word_len == 8) {
		const u8 *tx = xfer->tx_buf;
		u8 *rx = xfer->rx_buf;

		do {
			if (orion_spi_write_read_8bit(spi, &tx, &rx) < 0)
				goto out;
			count--;
		} while (count);
	} else if (word_len == 16) {
		const u16 *tx = xfer->tx_buf;
		u16 *rx = xfer->rx_buf;

		do {
			if (orion_spi_write_read_16bit(spi, &tx, &rx) < 0)
				goto out;
			count -= 2;
		} while (count);
	}

out:
	return xfer->len - count;
}

static int orion_spi_transfer_one(struct spi_master *master,
					struct spi_device *spi,
					struct spi_transfer *t)
{
	int status = 0;

	status = orion_spi_setup_transfer(spi, t);
	if (status < 0)
		return status;

	if (t->len)
		orion_spi_write_read(spi, t);

	return status;
}

static int orion_spi_setup(struct spi_device *spi)
{
	return orion_spi_setup_transfer(spi, NULL);
}

static int orion_spi_reset(struct orion_spi *orion_spi)
{
	/* Verify that the CS is deasserted */
	orion_spi_clrbits(orion_spi, ORION_SPI_IF_CTRL_REG, 0x1);
	return 0;
}

static const struct orion_spi_dev orion_spi_dev_data = {
	.typ = ORION_SPI,
	.min_divisor = 4,
	.max_divisor = 30,
	.prescale_mask = ORION_SPI_CLK_PRESCALE_MASK,
};

static const struct orion_spi_dev armada_spi_dev_data = {
	.typ = ARMADA_SPI,
	.min_divisor = 1,
	.max_divisor = 1920,
	.prescale_mask = ARMADA_SPI_CLK_PRESCALE_MASK,
};

static const struct of_device_id orion_spi_of_match_table[] = {
	{ .compatible = "marvell,orion-spi", .data = &orion_spi_dev_data, },
	{ .compatible = "marvell,armada-370-spi", .data = &armada_spi_dev_data, },
	{}
};
MODULE_DEVICE_TABLE(of, orion_spi_of_match_table);

static int orion_spi_probe(struct platform_device *pdev)
{
	const struct of_device_id *of_id;
	const struct orion_spi_dev *devdata;
	struct spi_master *master;
	struct orion_spi *spi;
	struct resource *r;
	unsigned long tclk_hz;
	int status = 0;

	master = spi_alloc_master(&pdev->dev, sizeof(*spi));
	if (master == NULL) {
		dev_dbg(&pdev->dev, "master allocation failed\n");
		return -ENOMEM;
	}

	if (pdev->id != -1)
		master->bus_num = pdev->id;
	if (pdev->dev.of_node) {
		u32 cell_index;

		if (!of_property_read_u32(pdev->dev.of_node, "cell-index",
					  &cell_index))
			master->bus_num = cell_index;
	}

	/* we support only mode 0, and no options */
	master->mode_bits = SPI_CPHA | SPI_CPOL;
	master->set_cs = orion_spi_set_cs;
	master->transfer_one = orion_spi_transfer_one;
	master->num_chipselect = ORION_NUM_CHIPSELECTS;
	master->setup = orion_spi_setup;
	master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16);
	master->auto_runtime_pm = true;

	platform_set_drvdata(pdev, master);

	spi = spi_master_get_devdata(master);
	spi->master = master;

	of_id = of_match_device(orion_spi_of_match_table, &pdev->dev);
	devdata = (of_id) ? of_id->data : &orion_spi_dev_data;
	spi->devdata = devdata;

	spi->clk = devm_clk_get(&pdev->dev, NULL);
	if (IS_ERR(spi->clk)) {
		status = PTR_ERR(spi->clk);
		goto out;
	}

	status = clk_prepare_enable(spi->clk);
	if (status)
		goto out;

	tclk_hz = clk_get_rate(spi->clk);
	master->max_speed_hz = DIV_ROUND_UP(tclk_hz, devdata->min_divisor);
	master->min_speed_hz = DIV_ROUND_UP(tclk_hz, devdata->max_divisor);

	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	spi->base = devm_ioremap_resource(&pdev->dev, r);
	if (IS_ERR(spi->base)) {
		status = PTR_ERR(spi->base);
		goto out_rel_clk;
	}

	pm_runtime_set_active(&pdev->dev);
	pm_runtime_use_autosuspend(&pdev->dev);
	pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT);
	pm_runtime_enable(&pdev->dev);

	status = orion_spi_reset(spi);
	if (status < 0)
		goto out_rel_pm;

	pm_runtime_mark_last_busy(&pdev->dev);
	pm_runtime_put_autosuspend(&pdev->dev);

	master->dev.of_node = pdev->dev.of_node;
	status = spi_register_master(master);
	if (status < 0)
		goto out_rel_pm;

	return status;

out_rel_pm:
	pm_runtime_disable(&pdev->dev);
out_rel_clk:
	clk_disable_unprepare(spi->clk);
out:
	spi_master_put(master);
	return status;
}


static int orion_spi_remove(struct platform_device *pdev)
{
	struct spi_master *master = platform_get_drvdata(pdev);
	struct orion_spi *spi = spi_master_get_devdata(master);

	pm_runtime_get_sync(&pdev->dev);
	clk_disable_unprepare(spi->clk);

	spi_unregister_master(master);
	pm_runtime_disable(&pdev->dev);

	return 0;
}

MODULE_ALIAS("platform:" DRIVER_NAME);

#ifdef CONFIG_PM
static int orion_spi_runtime_suspend(struct device *dev)
{
	struct spi_master *master = dev_get_drvdata(dev);
	struct orion_spi *spi = spi_master_get_devdata(master);

	clk_disable_unprepare(spi->clk);
	return 0;
}

static int orion_spi_runtime_resume(struct device *dev)
{
	struct spi_master *master = dev_get_drvdata(dev);
	struct orion_spi *spi = spi_master_get_devdata(master);

	return clk_prepare_enable(spi->clk);
}
#endif

static const struct dev_pm_ops orion_spi_pm_ops = {
	SET_RUNTIME_PM_OPS(orion_spi_runtime_suspend,
			   orion_spi_runtime_resume,
			   NULL)
};

static struct platform_driver orion_spi_driver = {
	.driver = {
		.name	= DRIVER_NAME,
		.pm	= &orion_spi_pm_ops,
		.of_match_table = of_match_ptr(orion_spi_of_match_table),
	},
	.probe		= orion_spi_probe,
	.remove		= orion_spi_remove,
};

module_platform_driver(orion_spi_driver);

MODULE_DESCRIPTION("Orion SPI driver");
MODULE_AUTHOR("Shadi Ammouri <shadi@marvell.com>");
MODULE_LICENSE("GPL");
Commit	Line	Data
60cadec9	1	/*
ca632f55	2	* Marvell Orion SPI controller driver
60cadec9 SA	3	*
	4	* Author: Shadi Ammouri <shadi@marvell.com>
	5	* Copyright (C) 2007-2008 Marvell Ltd.
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*/
	11
60cadec9 SA	12	#include <linux/interrupt.h>
	13	#include <linux/delay.h>
	14	#include <linux/platform_device.h>
	15	#include <linux/err.h>
	16	#include <linux/io.h>
	17	#include <linux/spi/spi.h>
d7614de4	18	#include <linux/module.h>
5c678694	19	#include <linux/pm_runtime.h>
f814f9ac	20	#include <linux/of.h>
df59fa7f	21	#include <linux/of_device.h>
4574b886	22	#include <linux/clk.h>
895248f8	23	#include <linux/sizes.h>
60cadec9 SA	24	#include <asm/unaligned.h>
	25
	26	#define DRIVER_NAME "orion_spi"
	27
5c678694 RK	28	/* Runtime PM autosuspend timeout: PM is fairly light on this driver */
	29	#define SPI_AUTOSUSPEND_TIMEOUT 200
	30
23244404 KW	31	/* Some SoCs using this driver support up to 8 chip selects.
	32	* It is up to the implementer to only use the chip selects
	33	* that are available.
	34	*/
	35	#define ORION_NUM_CHIPSELECTS 8
	36
60cadec9 SA	37	#define ORION_SPI_WAIT_RDY_MAX_LOOP 2000 /* in usec */
	38
	39	#define ORION_SPI_IF_CTRL_REG 0x00
	40	#define ORION_SPI_IF_CONFIG_REG 0x04
	41	#define ORION_SPI_DATA_OUT_REG 0x08
	42	#define ORION_SPI_DATA_IN_REG 0x0c
	43	#define ORION_SPI_INT_CAUSE_REG 0x10
	44
b15d5d70 JG	45	#define ORION_SPI_MODE_CPOL (1 << 11)
b15d5d70 JG	46	#define ORION_SPI_MODE_CPHA (1 << 12)
60cadec9 SA	47	#define ORION_SPI_IF_8_16_BIT_MODE (1 << 5)
60cadec9 SA	48	#define ORION_SPI_CLK_PRESCALE_MASK 0x1F
df59fa7f	49	#define ARMADA_SPI_CLK_PRESCALE_MASK 0xDF
b15d5d70 JG	50	#define ORION_SPI_MODE_MASK (ORION_SPI_MODE_CPOL \| \
b15d5d70 JG	51	ORION_SPI_MODE_CPHA)
23244404 KW	52	#define ORION_SPI_CS_MASK 0x1C
	53	#define ORION_SPI_CS_SHIFT 2
	54	#define ORION_SPI_CS(cs) ((cs << ORION_SPI_CS_SHIFT) & \
	55	ORION_SPI_CS_MASK)
60cadec9	56
df59fa7f GU	57	enum orion_spi_type {
	58	ORION_SPI,
	59	ARMADA_SPI,
	60	};
	61
	62	struct orion_spi_dev {
	63	enum orion_spi_type typ;
	64	unsigned int min_divisor;
	65	unsigned int max_divisor;
	66	u32 prescale_mask;
	67	};
	68
60cadec9	69	struct orion_spi {
60cadec9 SA	70	struct spi_master *master;
60cadec9 SA	71	void __iomem *base;
4574b886	72	struct clk *clk;
df59fa7f	73	const struct orion_spi_dev *devdata;
60cadec9 SA	74	};
60cadec9 SA	75
60cadec9 SA	76	static inline void __iomem spi_reg(struct orion_spi orion_spi, u32 reg)
	77	{
	78	return orion_spi->base + reg;
	79	}
	80
	81	static inline void
	82	orion_spi_setbits(struct orion_spi *orion_spi, u32 reg, u32 mask)
	83	{
	84	void __iomem *reg_addr = spi_reg(orion_spi, reg);
	85	u32 val;
	86
	87	val = readl(reg_addr);
	88	val \|= mask;
	89	writel(val, reg_addr);
	90	}
	91
	92	static inline void
	93	orion_spi_clrbits(struct orion_spi *orion_spi, u32 reg, u32 mask)
	94	{
	95	void __iomem *reg_addr = spi_reg(orion_spi, reg);
	96	u32 val;
	97
	98	val = readl(reg_addr);
	99	val &= ~mask;
	100	writel(val, reg_addr);
	101	}
	102
60cadec9 SA	103	static int orion_spi_baudrate_set(struct spi_device *spi, unsigned int speed)
	104	{
	105	u32 tclk_hz;
	106	u32 rate;
	107	u32 prescale;
	108	u32 reg;
	109	struct orion_spi *orion_spi;
df59fa7f	110	const struct orion_spi_dev *devdata;
60cadec9 SA	111
60cadec9 SA	112	orion_spi = spi_master_get_devdata(spi->master);
df59fa7f	113	devdata = orion_spi->devdata;
60cadec9	114
4574b886	115	tclk_hz = clk_get_rate(orion_spi->clk);
60cadec9	116
df59fa7f GU	117	if (devdata->typ == ARMADA_SPI) {
	118	unsigned int clk, spr, sppr, sppr2, err;
	119	unsigned int best_spr, best_sppr, best_err;
60cadec9	120
df59fa7f GU	121	best_err = speed;
	122	best_spr = 0;
	123	best_sppr = 0;
60cadec9	124
df59fa7f GU	125	/* Iterate over the valid range looking for best fit */
	126	for (sppr = 0; sppr < 8; sppr++) {
	127	sppr2 = 0x1 << sppr;
	128
	129	spr = tclk_hz / sppr2;
	130	spr = DIV_ROUND_UP(spr, speed);
	131	if ((spr == 0) \|\| (spr > 15))
	132	continue;
60cadec9	133
df59fa7f GU	134	clk = tclk_hz / (spr * sppr2);
df59fa7f GU	135	err = speed - clk;
60cadec9	136
df59fa7f GU	137	if (err < best_err) {
	138	best_spr = spr;
	139	best_sppr = sppr;
	140	best_err = err;
	141	}
	142	}
60cadec9	143
df59fa7f GU	144	if ((best_sppr == 0) && (best_spr == 0))
	145	return -EINVAL;
	146
	147	prescale = ((best_sppr & 0x6) << 5) \|
	148	((best_sppr & 0x1) << 4) \| best_spr;
	149	} else {
	150	/*
	151	* the supported rates are: 4,6,8...30
	152	* round up as we look for equal or less speed
	153	*/
	154	rate = DIV_ROUND_UP(tclk_hz, speed);
	155	rate = roundup(rate, 2);
	156
	157	/* check if requested speed is too small */
	158	if (rate > 30)
	159	return -EINVAL;
60cadec9	160
df59fa7f GU	161	if (rate < 4)
	162	rate = 4;
	163
	164	/* Convert the rate to SPI clock divisor value. */
	165	prescale = 0x10 + rate/2;
	166	}
60cadec9 SA	167
60cadec9 SA	168	reg = readl(spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG));
df59fa7f	169	reg = ((reg & ~devdata->prescale_mask) \| prescale);
60cadec9 SA	170	writel(reg, spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG));
	171
	172	return 0;
	173	}
	174
b15d5d70 JG	175	static void
	176	orion_spi_mode_set(struct spi_device *spi)
	177	{
	178	u32 reg;
	179	struct orion_spi *orion_spi;
	180
	181	orion_spi = spi_master_get_devdata(spi->master);
	182
	183	reg = readl(spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG));
	184	reg &= ~ORION_SPI_MODE_MASK;
	185	if (spi->mode & SPI_CPOL)
	186	reg \|= ORION_SPI_MODE_CPOL;
	187	if (spi->mode & SPI_CPHA)
	188	reg \|= ORION_SPI_MODE_CPHA;
	189	writel(reg, spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG));
	190	}
	191
60cadec9 SA	192	/*
	193	* called only when no transfer is active on the bus
	194	*/
	195	static int
	196	orion_spi_setup_transfer(struct spi_device spi, struct spi_transfer t)
	197	{
	198	struct orion_spi *orion_spi;
	199	unsigned int speed = spi->max_speed_hz;
	200	unsigned int bits_per_word = spi->bits_per_word;
	201	int rc;
	202
	203	orion_spi = spi_master_get_devdata(spi->master);
	204
	205	if ((t != NULL) && t->speed_hz)
	206	speed = t->speed_hz;
	207
	208	if ((t != NULL) && t->bits_per_word)
	209	bits_per_word = t->bits_per_word;
	210
b15d5d70 JG	211	orion_spi_mode_set(spi);
b15d5d70 JG	212
60cadec9 SA	213	rc = orion_spi_baudrate_set(spi, speed);
	214	if (rc)
	215	return rc;
	216
495b3358 AL	217	if (bits_per_word == 16)
	218	orion_spi_setbits(orion_spi, ORION_SPI_IF_CONFIG_REG,
	219	ORION_SPI_IF_8_16_BIT_MODE);
	220	else
	221	orion_spi_clrbits(orion_spi, ORION_SPI_IF_CONFIG_REG,
	222	ORION_SPI_IF_8_16_BIT_MODE);
	223
	224	return 0;
60cadec9 SA	225	}
60cadec9 SA	226
75872ebe	227	static void orion_spi_set_cs(struct spi_device *spi, bool enable)
60cadec9	228	{
75872ebe KW	229	struct orion_spi *orion_spi;
	230
	231	orion_spi = spi_master_get_devdata(spi->master);
	232
23244404 KW	233	orion_spi_clrbits(orion_spi, ORION_SPI_IF_CTRL_REG, ORION_SPI_CS_MASK);
	234	orion_spi_setbits(orion_spi, ORION_SPI_IF_CTRL_REG,
	235	ORION_SPI_CS(spi->chip_select));
	236
75872ebe KW	237	/* Chip select logic is inverted from spi_set_cs */
75872ebe KW	238	if (!enable)
60cadec9 SA	239	orion_spi_setbits(orion_spi, ORION_SPI_IF_CTRL_REG, 0x1);
	240	else
	241	orion_spi_clrbits(orion_spi, ORION_SPI_IF_CTRL_REG, 0x1);
	242	}
	243
	244	static inline int orion_spi_wait_till_ready(struct orion_spi *orion_spi)
	245	{
	246	int i;
	247
	248	for (i = 0; i < ORION_SPI_WAIT_RDY_MAX_LOOP; i++) {
	249	if (readl(spi_reg(orion_spi, ORION_SPI_INT_CAUSE_REG)))
	250	return 1;
b8434048 JH	251
b8434048 JH	252	udelay(1);
60cadec9 SA	253	}
	254
	255	return -1;
	256	}
	257
	258	static inline int
	259	orion_spi_write_read_8bit(struct spi_device *spi,
	260	const u8 tx_buf, u8 rx_buf)
	261	{
	262	void __iomem tx_reg, rx_reg, *int_reg;
	263	struct orion_spi *orion_spi;
	264
	265	orion_spi = spi_master_get_devdata(spi->master);
	266	tx_reg = spi_reg(orion_spi, ORION_SPI_DATA_OUT_REG);
	267	rx_reg = spi_reg(orion_spi, ORION_SPI_DATA_IN_REG);
	268	int_reg = spi_reg(orion_spi, ORION_SPI_INT_CAUSE_REG);
	269
	270	/* clear the interrupt cause register */
	271	writel(0x0, int_reg);
	272
	273	if (tx_buf && *tx_buf)
	274	writel((tx_buf)++, tx_reg);
	275	else
	276	writel(0, tx_reg);
	277
	278	if (orion_spi_wait_till_ready(orion_spi) < 0) {
	279	dev_err(&spi->dev, "TXS timed out\n");
	280	return -1;
	281	}
	282
	283	if (rx_buf && *rx_buf)
	284	(rx_buf)++ = readl(rx_reg);
	285
	286	return 1;
	287	}
	288
	289	static inline int
	290	orion_spi_write_read_16bit(struct spi_device *spi,
	291	const u16 tx_buf, u16 rx_buf)
	292	{
	293	void __iomem tx_reg, rx_reg, *int_reg;
	294	struct orion_spi *orion_spi;
	295
	296	orion_spi = spi_master_get_devdata(spi->master);
	297	tx_reg = spi_reg(orion_spi, ORION_SPI_DATA_OUT_REG);
	298	rx_reg = spi_reg(orion_spi, ORION_SPI_DATA_IN_REG);
	299	int_reg = spi_reg(orion_spi, ORION_SPI_INT_CAUSE_REG);
	300
	301	/* clear the interrupt cause register */
	302	writel(0x0, int_reg);
	303
	304	if (tx_buf && *tx_buf)
	305	writel(__cpu_to_le16(get_unaligned((*tx_buf)++)), tx_reg);
	306	else
	307	writel(0, tx_reg);
	308
	309	if (orion_spi_wait_till_ready(orion_spi) < 0) {
	310	dev_err(&spi->dev, "TXS timed out\n");
	311	return -1;
	312	}
	313
	314	if (rx_buf && *rx_buf)
	315	put_unaligned(__le16_to_cpu(readl(rx_reg)), (*rx_buf)++);
	316
317	return 1;
318	}
319
320	static unsigned int
321	orion_spi_write_read(struct spi_device spi, struct spi_transfer xfer)
322	{
60cadec9 SA	323	unsigned int count;
	324	int word_len;
	325
60cadec9 SA	326	word_len = spi->bits_per_word;
	327	count = xfer->len;
	328
	329	if (word_len == 8) {
	330	const u8 *tx = xfer->tx_buf;
	331	u8 *rx = xfer->rx_buf;
	332
	333	do {
	334	if (orion_spi_write_read_8bit(spi, &tx, &rx) < 0)
	335	goto out;
	336	count--;
	337	} while (count);
	338	} else if (word_len == 16) {
	339	const u16 *tx = xfer->tx_buf;
	340	u16 *rx = xfer->rx_buf;
	341
	342	do {
	343	if (orion_spi_write_read_16bit(spi, &tx, &rx) < 0)
	344	goto out;
	345	count -= 2;
	346	} while (count);
	347	}
	348
	349	out:
	350	return xfer->len - count;
	351	}
	352
75872ebe KW	353	static int orion_spi_transfer_one(struct spi_master *master,
	354	struct spi_device *spi,
	355	struct spi_transfer *t)
60cadec9	356	{
ba59a807	357	int status = 0;
60cadec9	358
75872ebe	359	status = orion_spi_setup_transfer(spi, t);
ba59a807	360	if (status < 0)
75872ebe	361	return status;
60cadec9	362
75872ebe KW	363	if (t->len)
75872ebe KW	364	orion_spi_write_read(spi, t);
ba59a807	365
75872ebe KW	366	return status;
75872ebe KW	367	}
ba59a807	368
75872ebe KW	369	static int orion_spi_setup(struct spi_device *spi)
	370	{
	371	return orion_spi_setup_transfer(spi, NULL);
60cadec9 SA	372	}
60cadec9 SA	373
2deff8d6	374	static int orion_spi_reset(struct orion_spi *orion_spi)
60cadec9 SA	375	{
60cadec9 SA	376	/* Verify that the CS is deasserted */
75872ebe	377	orion_spi_clrbits(orion_spi, ORION_SPI_IF_CTRL_REG, 0x1);
60cadec9 SA	378	return 0;
	379	}
	380
df59fa7f GU	381	static const struct orion_spi_dev orion_spi_dev_data = {
	382	.typ = ORION_SPI,
	383	.min_divisor = 4,
	384	.max_divisor = 30,
	385	.prescale_mask = ORION_SPI_CLK_PRESCALE_MASK,
	386	};
	387
	388	static const struct orion_spi_dev armada_spi_dev_data = {
	389	.typ = ARMADA_SPI,
	390	.min_divisor = 1,
	391	.max_divisor = 1920,
	392	.prescale_mask = ARMADA_SPI_CLK_PRESCALE_MASK,
	393	};
	394
	395	static const struct of_device_id orion_spi_of_match_table[] = {
	396	{ .compatible = "marvell,orion-spi", .data = &orion_spi_dev_data, },
	397	{ .compatible = "marvell,armada-370-spi", .data = &armada_spi_dev_data, },
	398	{}
	399	};
	400	MODULE_DEVICE_TABLE(of, orion_spi_of_match_table);
	401
2deff8d6	402	static int orion_spi_probe(struct platform_device *pdev)
60cadec9	403	{
df59fa7f GU	404	const struct of_device_id *of_id;
df59fa7f GU	405	const struct orion_spi_dev *devdata;
60cadec9 SA	406	struct spi_master *master;
	407	struct orion_spi *spi;
	408	struct resource *r;
4574b886	409	unsigned long tclk_hz;
60cadec9 SA	410	int status = 0;
60cadec9 SA	411
3fed8068	412	master = spi_alloc_master(&pdev->dev, sizeof(*spi));
60cadec9 SA	413	if (master == NULL) {
	414	dev_dbg(&pdev->dev, "master allocation failed\n");
	415	return -ENOMEM;
	416	}
	417
	418	if (pdev->id != -1)
	419	master->bus_num = pdev->id;
f814f9ac	420	if (pdev->dev.of_node) {
e06871cd	421	u32 cell_index;
b8434048	422
e06871cd TP	423	if (!of_property_read_u32(pdev->dev.of_node, "cell-index",
	424	&cell_index))
	425	master->bus_num = cell_index;
f814f9ac	426	}
60cadec9	427
e7db06b5	428	/* we support only mode 0, and no options */
b15d5d70	429	master->mode_bits = SPI_CPHA \| SPI_CPOL;
75872ebe KW	430	master->set_cs = orion_spi_set_cs;
75872ebe KW	431	master->transfer_one = orion_spi_transfer_one;
60cadec9	432	master->num_chipselect = ORION_NUM_CHIPSELECTS;
75872ebe	433	master->setup = orion_spi_setup;
495b3358	434	master->bits_per_word_mask = SPI_BPW_MASK(8) \| SPI_BPW_MASK(16);
5c678694	435	master->auto_runtime_pm = true;
60cadec9	436
24b5a82c	437	platform_set_drvdata(pdev, master);
60cadec9 SA	438
	439	spi = spi_master_get_devdata(master);
	440	spi->master = master;
60cadec9	441
df59fa7f	442	of_id = of_match_device(orion_spi_of_match_table, &pdev->dev);
9a2d3635	443	devdata = (of_id) ? of_id->data : &orion_spi_dev_data;
df59fa7f GU	444	spi->devdata = devdata;
df59fa7f GU	445
bb489841	446	spi->clk = devm_clk_get(&pdev->dev, NULL);
4574b886 AL	447	if (IS_ERR(spi->clk)) {
	448	status = PTR_ERR(spi->clk);
	449	goto out;
	450	}
	451
c85012ad RK	452	status = clk_prepare_enable(spi->clk);
	453	if (status)
	454	goto out;
	455
4574b886	456	tclk_hz = clk_get_rate(spi->clk);
df59fa7f GU	457	master->max_speed_hz = DIV_ROUND_UP(tclk_hz, devdata->min_divisor);
df59fa7f GU	458	master->min_speed_hz = DIV_ROUND_UP(tclk_hz, devdata->max_divisor);
60cadec9 SA	459
60cadec9 SA	460	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1729ce34 MB	461	spi->base = devm_ioremap_resource(&pdev->dev, r);
	462	if (IS_ERR(spi->base)) {
	463	status = PTR_ERR(spi->base);
4574b886	464	goto out_rel_clk;
60cadec9 SA	465	}
60cadec9 SA	466
5c678694 RK	467	pm_runtime_set_active(&pdev->dev);
	468	pm_runtime_use_autosuspend(&pdev->dev);
	469	pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT);
	470	pm_runtime_enable(&pdev->dev);
	471
14033816 WY	472	status = orion_spi_reset(spi);
14033816 WY	473	if (status < 0)
5c678694 RK	474	goto out_rel_pm;
	475
	476	pm_runtime_mark_last_busy(&pdev->dev);
	477	pm_runtime_put_autosuspend(&pdev->dev);
60cadec9	478
f814f9ac	479	master->dev.of_node = pdev->dev.of_node;
5c678694	480	status = spi_register_master(master);
60cadec9	481	if (status < 0)
5c678694	482	goto out_rel_pm;
60cadec9 SA	483
	484	return status;
	485
5c678694 RK	486	out_rel_pm:
5c678694 RK	487	pm_runtime_disable(&pdev->dev);
4574b886 AL	488	out_rel_clk:
4574b886 AL	489	clk_disable_unprepare(spi->clk);
60cadec9 SA	490	out:
	491	spi_master_put(master);
	492	return status;
	493	}
	494
	495
2deff8d6	496	static int orion_spi_remove(struct platform_device *pdev)
60cadec9	497	{
5c678694 RK	498	struct spi_master *master = platform_get_drvdata(pdev);
5c678694 RK	499	struct orion_spi *spi = spi_master_get_devdata(master);
60cadec9	500
5c678694	501	pm_runtime_get_sync(&pdev->dev);
4574b886	502	clk_disable_unprepare(spi->clk);
4574b886	503
5c678694 RK	504	spi_unregister_master(master);
	505	pm_runtime_disable(&pdev->dev);
	506
60cadec9 SA	507	return 0;
	508	}
	509
	510	MODULE_ALIAS("platform:" DRIVER_NAME);
	511
ec833050	512	#ifdef CONFIG_PM
5c678694 RK	513	static int orion_spi_runtime_suspend(struct device *dev)
	514	{
	515	struct spi_master *master = dev_get_drvdata(dev);
	516	struct orion_spi *spi = spi_master_get_devdata(master);
	517
	518	clk_disable_unprepare(spi->clk);
	519	return 0;
	520	}
	521
	522	static int orion_spi_runtime_resume(struct device *dev)
	523	{
	524	struct spi_master *master = dev_get_drvdata(dev);
	525	struct orion_spi *spi = spi_master_get_devdata(master);
	526
	527	return clk_prepare_enable(spi->clk);
	528	}
	529	#endif
	530
	531	static const struct dev_pm_ops orion_spi_pm_ops = {
	532	SET_RUNTIME_PM_OPS(orion_spi_runtime_suspend,
	533	orion_spi_runtime_resume,
	534	NULL)
	535	};
	536
60cadec9 SA	537	static struct platform_driver orion_spi_driver = {
	538	.driver = {
	539	.name = DRIVER_NAME,
5c678694	540	.pm = &orion_spi_pm_ops,
f814f9ac	541	.of_match_table = of_match_ptr(orion_spi_of_match_table),
60cadec9	542	},
41ab724a	543	.probe = orion_spi_probe,
2deff8d6	544	.remove = orion_spi_remove,
60cadec9 SA	545	};
60cadec9 SA	546
41ab724a	547	module_platform_driver(orion_spi_driver);
60cadec9 SA	548
	549	MODULE_DESCRIPTION("Orion SPI driver");
	550	MODULE_AUTHOR("Shadi Ammouri <shadi@marvell.com>");
	551	MODULE_LICENSE("GPL");