[linux-2.6-block.git] / drivers / spi / spi-omap-uwire.c

/*
 * MicroWire interface driver for OMAP
 *
 * Copyright 2003 MontaVista Software Inc. <source@mvista.com>
 *
 * Ported to 2.6 OMAP uwire interface.
 * Copyright (C) 2004 Texas Instruments.
 *
 * Generalization patches by Juha Yrjola <juha.yrjola@nokia.com>
 *
 * Copyright (C) 2005 David Brownell (ported to 2.6 SPI interface)
 * Copyright (C) 2006 Nokia
 *
 * Many updates by Imre Deak <imre.deak@nokia.com>
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by the
 * Free Software Foundation; either version 2 of the License, or (at your
 * option) any later version.
 *
 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/platform_device.h>
#include <linux/interrupt.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/slab.h>
#include <linux/device.h>

#include <linux/spi/spi.h>
#include <linux/spi/spi_bitbang.h>
#include <linux/module.h>
#include <linux/io.h>

#include <mach/hardware.h>
#include <asm/mach-types.h>

#include <mach/mux.h>

#include <mach/omap7xx.h>	/* OMAP7XX_IO_CONF registers */


/* FIXME address is now a platform device resource,
 * and irqs should show there too...
 */
#define UWIRE_BASE_PHYS		0xFFFB3000

/* uWire Registers: */
#define UWIRE_IO_SIZE 0x20
#define UWIRE_TDR     0x00
#define UWIRE_RDR     0x00
#define UWIRE_CSR     0x01
#define UWIRE_SR1     0x02
#define UWIRE_SR2     0x03
#define UWIRE_SR3     0x04
#define UWIRE_SR4     0x05
#define UWIRE_SR5     0x06

/* CSR bits */
#define	RDRB	(1 << 15)
#define	CSRB	(1 << 14)
#define	START	(1 << 13)
#define	CS_CMD	(1 << 12)

/* SR1 or SR2 bits */
#define UWIRE_READ_FALLING_EDGE		0x0001
#define UWIRE_READ_RISING_EDGE		0x0000
#define UWIRE_WRITE_FALLING_EDGE	0x0000
#define UWIRE_WRITE_RISING_EDGE		0x0002
#define UWIRE_CS_ACTIVE_LOW		0x0000
#define UWIRE_CS_ACTIVE_HIGH		0x0004
#define UWIRE_FREQ_DIV_2		0x0000
#define UWIRE_FREQ_DIV_4		0x0008
#define UWIRE_FREQ_DIV_8		0x0010
#define UWIRE_CHK_READY			0x0020
#define UWIRE_CLK_INVERTED		0x0040


struct uwire_spi {
	struct spi_bitbang	bitbang;
	struct clk		*ck;
};

struct uwire_state {
	unsigned	div1_idx;
};

/* REVISIT compile time constant for idx_shift? */
/*
 * Or, put it in a structure which is used throughout the driver;
 * that avoids having to issue two loads for each bit of static data.
 */
static unsigned int uwire_idx_shift;
static void __iomem *uwire_base;

static inline void uwire_write_reg(int idx, u16 val)
{
	__raw_writew(val, uwire_base + (idx << uwire_idx_shift));
}

static inline u16 uwire_read_reg(int idx)
{
	return __raw_readw(uwire_base + (idx << uwire_idx_shift));
}

static inline void omap_uwire_configure_mode(u8 cs, unsigned long flags)
{
	u16	w, val = 0;
	int	shift, reg;

	if (flags & UWIRE_CLK_INVERTED)
		val ^= 0x03;
	val = flags & 0x3f;
	if (cs & 1)
		shift = 6;
	else
		shift = 0;
	if (cs <= 1)
		reg = UWIRE_SR1;
	else
		reg = UWIRE_SR2;

	w = uwire_read_reg(reg);
	w &= ~(0x3f << shift);
	w |= val << shift;
	uwire_write_reg(reg, w);
}

static int wait_uwire_csr_flag(u16 mask, u16 val, int might_not_catch)
{
	u16 w;
	int c = 0;
	unsigned long max_jiffies = jiffies + HZ;

	for (;;) {
		w = uwire_read_reg(UWIRE_CSR);
		if ((w & mask) == val)
			break;
		if (time_after(jiffies, max_jiffies)) {
			printk(KERN_ERR "%s: timeout. reg=%#06x "
					"mask=%#06x val=%#06x\n",
			       __func__, w, mask, val);
			return -1;
		}
		c++;
		if (might_not_catch && c > 64)
			break;
	}
	return 0;
}

static void uwire_set_clk1_div(int div1_idx)
{
	u16 w;

	w = uwire_read_reg(UWIRE_SR3);
	w &= ~(0x03 << 1);
	w |= div1_idx << 1;
	uwire_write_reg(UWIRE_SR3, w);
}

static void uwire_chipselect(struct spi_device *spi, int value)
{
	struct	uwire_state *ust = spi->controller_state;
	u16	w;
	int	old_cs;


	BUG_ON(wait_uwire_csr_flag(CSRB, 0, 0));

	w = uwire_read_reg(UWIRE_CSR);
	old_cs = (w >> 10) & 0x03;
	if (value == BITBANG_CS_INACTIVE || old_cs != spi->chip_select) {
		/* Deselect this CS, or the previous CS */
		w &= ~CS_CMD;
		uwire_write_reg(UWIRE_CSR, w);
	}
	/* activate specfied chipselect */
	if (value == BITBANG_CS_ACTIVE) {
		uwire_set_clk1_div(ust->div1_idx);
		/* invert clock? */
		if (spi->mode & SPI_CPOL)
			uwire_write_reg(UWIRE_SR4, 1);
		else
			uwire_write_reg(UWIRE_SR4, 0);

		w = spi->chip_select << 10;
		w |= CS_CMD;
		uwire_write_reg(UWIRE_CSR, w);
	}
}

static int uwire_txrx(struct spi_device *spi, struct spi_transfer *t)
{
	unsigned	len = t->len;
	unsigned	bits = t->bits_per_word;
	unsigned	bytes;
	u16		val, w;
	int		status = 0;

	if (!t->tx_buf && !t->rx_buf)
		return 0;

	w = spi->chip_select << 10;
	w |= CS_CMD;

	if (t->tx_buf) {
		const u8	*buf = t->tx_buf;

		/* NOTE:  DMA could be used for TX transfers */

		/* write one or two bytes at a time */
		while (len >= 1) {
			/* tx bit 15 is first sent; we byteswap multibyte words
			 * (msb-first) on the way out from memory.
			 */
			val = *buf++;
			if (bits > 8) {
				bytes = 2;
				val |= *buf++ << 8;
			} else
				bytes = 1;
			val <<= 16 - bits;

#ifdef	VERBOSE
			pr_debug("%s: write-%d =%04x\n",
					dev_name(&spi->dev), bits, val);
#endif
			if (wait_uwire_csr_flag(CSRB, 0, 0))
				goto eio;

			uwire_write_reg(UWIRE_TDR, val);

			/* start write */
			val = START | w | (bits << 5);

			uwire_write_reg(UWIRE_CSR, val);
			len -= bytes;

			/* Wait till write actually starts.
			 * This is needed with MPU clock 60+ MHz.
			 * REVISIT: we may not have time to catch it...
			 */
			if (wait_uwire_csr_flag(CSRB, CSRB, 1))
				goto eio;

			status += bytes;
		}

		/* REVISIT:  save this for later to get more i/o overlap */
		if (wait_uwire_csr_flag(CSRB, 0, 0))
			goto eio;

	} else if (t->rx_buf) {
		u8		*buf = t->rx_buf;

		/* read one or two bytes at a time */
		while (len) {
			if (bits > 8) {
				bytes = 2;
			} else
				bytes = 1;

			/* start read */
			val = START | w | (bits << 0);
			uwire_write_reg(UWIRE_CSR, val);
			len -= bytes;

			/* Wait till read actually starts */
			(void) wait_uwire_csr_flag(CSRB, CSRB, 1);

			if (wait_uwire_csr_flag(RDRB | CSRB,
						RDRB, 0))
				goto eio;

			/* rx bit 0 is last received; multibyte words will
			 * be properly byteswapped on the way to memory.
			 */
			val = uwire_read_reg(UWIRE_RDR);
			val &= (1 << bits) - 1;
			*buf++ = (u8) val;
			if (bytes == 2)
				*buf++ = val >> 8;
			status += bytes;
#ifdef	VERBOSE
			pr_debug("%s: read-%d =%04x\n",
					dev_name(&spi->dev), bits, val);
#endif

		}
	}
	return status;
eio:
	return -EIO;
}

static int uwire_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
{
	struct uwire_state	*ust = spi->controller_state;
	struct uwire_spi	*uwire;
	unsigned		flags = 0;
	unsigned		hz;
	unsigned long		rate;
	int			div1_idx;
	int			div1;
	int			div2;
	int			status;

	uwire = spi_master_get_devdata(spi->master);

	/* mode 0..3, clock inverted separately;
	 * standard nCS signaling;
	 * don't treat DI=high as "not ready"
	 */
	if (spi->mode & SPI_CS_HIGH)
		flags |= UWIRE_CS_ACTIVE_HIGH;

	if (spi->mode & SPI_CPOL)
		flags |= UWIRE_CLK_INVERTED;

	switch (spi->mode & (SPI_CPOL | SPI_CPHA)) {
	case SPI_MODE_0:
	case SPI_MODE_3:
		flags |= UWIRE_WRITE_FALLING_EDGE | UWIRE_READ_RISING_EDGE;
		break;
	case SPI_MODE_1:
	case SPI_MODE_2:
		flags |= UWIRE_WRITE_RISING_EDGE | UWIRE_READ_FALLING_EDGE;
		break;
	}

	/* assume it's already enabled */
	rate = clk_get_rate(uwire->ck);

	if (t != NULL)
		hz = t->speed_hz;
	else
		hz = spi->max_speed_hz;

	if (!hz) {
		pr_debug("%s: zero speed?\n", dev_name(&spi->dev));
		status = -EINVAL;
		goto done;
	}

	/* F_INT = mpu_xor_clk / DIV1 */
	for (div1_idx = 0; div1_idx < 4; div1_idx++) {
		switch (div1_idx) {
		case 0:
			div1 = 2;
			break;
		case 1:
			div1 = 4;
			break;
		case 2:
			div1 = 7;
			break;
		default:
		case 3:
			div1 = 10;
			break;
		}
		div2 = (rate / div1 + hz - 1) / hz;
		if (div2 <= 8)
			break;
	}
	if (div1_idx == 4) {
		pr_debug("%s: lowest clock %ld, need %d\n",
			dev_name(&spi->dev), rate / 10 / 8, hz);
		status = -EDOM;
		goto done;
	}

	/* we have to cache this and reset in uwire_chipselect as this is a
	 * global parameter and another uwire device can change it under
	 * us */
	ust->div1_idx = div1_idx;
	uwire_set_clk1_div(div1_idx);

	rate /= div1;

	switch (div2) {
	case 0:
	case 1:
	case 2:
		flags |= UWIRE_FREQ_DIV_2;
		rate /= 2;
		break;
	case 3:
	case 4:
		flags |= UWIRE_FREQ_DIV_4;
		rate /= 4;
		break;
	case 5:
	case 6:
	case 7:
	case 8:
		flags |= UWIRE_FREQ_DIV_8;
		rate /= 8;
		break;
	}
	omap_uwire_configure_mode(spi->chip_select, flags);
	pr_debug("%s: uwire flags %02x, armxor %lu KHz, SCK %lu KHz\n",
			__func__, flags,
			clk_get_rate(uwire->ck) / 1000,
			rate / 1000);
	status = 0;
done:
	return status;
}

static int uwire_setup(struct spi_device *spi)
{
	struct uwire_state *ust = spi->controller_state;

	if (ust == NULL) {
		ust = kzalloc(sizeof(*ust), GFP_KERNEL);
		if (ust == NULL)
			return -ENOMEM;
		spi->controller_state = ust;
	}

	return uwire_setup_transfer(spi, NULL);
}

static void uwire_cleanup(struct spi_device *spi)
{
	kfree(spi->controller_state);
}

static void uwire_off(struct uwire_spi *uwire)
{
	uwire_write_reg(UWIRE_SR3, 0);
	clk_disable(uwire->ck);
	spi_master_put(uwire->bitbang.master);
}

static int uwire_probe(struct platform_device *pdev)
{
	struct spi_master	*master;
	struct uwire_spi	*uwire;
	int			status;

	master = spi_alloc_master(&pdev->dev, sizeof *uwire);
	if (!master)
		return -ENODEV;

	uwire = spi_master_get_devdata(master);

	uwire_base = devm_ioremap(&pdev->dev, UWIRE_BASE_PHYS, UWIRE_IO_SIZE);
	if (!uwire_base) {
		dev_dbg(&pdev->dev, "can't ioremap UWIRE\n");
		spi_master_put(master);
		return -ENOMEM;
	}

	platform_set_drvdata(pdev, uwire);

	uwire->ck = devm_clk_get(&pdev->dev, "fck");
	if (IS_ERR(uwire->ck)) {
		status = PTR_ERR(uwire->ck);
		dev_dbg(&pdev->dev, "no functional clock?\n");
		spi_master_put(master);
		return status;
	}
	clk_enable(uwire->ck);

	if (cpu_is_omap7xx())
		uwire_idx_shift = 1;
	else
		uwire_idx_shift = 2;

	uwire_write_reg(UWIRE_SR3, 1);

	/* the spi->mode bits understood by this driver: */
	master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
	master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 16);
	master->flags = SPI_MASTER_HALF_DUPLEX;

	master->bus_num = 2;	/* "official" */
	master->num_chipselect = 4;
	master->setup = uwire_setup;
	master->cleanup = uwire_cleanup;

	uwire->bitbang.master = master;
	uwire->bitbang.chipselect = uwire_chipselect;
	uwire->bitbang.setup_transfer = uwire_setup_transfer;
	uwire->bitbang.txrx_bufs = uwire_txrx;

	status = spi_bitbang_start(&uwire->bitbang);
	if (status < 0) {
		uwire_off(uwire);
	}
	return status;
}

static int uwire_remove(struct platform_device *pdev)
{
	struct uwire_spi	*uwire = platform_get_drvdata(pdev);

	// FIXME remove all child devices, somewhere ...

	spi_bitbang_stop(&uwire->bitbang);
	uwire_off(uwire);
	return 0;
}

/* work with hotplug and coldplug */
MODULE_ALIAS("platform:omap_uwire");

static struct platform_driver uwire_driver = {
	.driver = {
		.name		= "omap_uwire",
	},
	.probe = uwire_probe,
	.remove = uwire_remove,
	// suspend ... unuse ck
	// resume ... use ck
};

static int __init omap_uwire_init(void)
{
	/* FIXME move these into the relevant board init code. also, include
	 * H3 support; it uses tsc2101 like H2 (on a different chipselect).
	 */

	if (machine_is_omap_h2()) {
		/* defaults: W21 SDO, U18 SDI, V19 SCL */
		omap_cfg_reg(N14_1610_UWIRE_CS0);
		omap_cfg_reg(N15_1610_UWIRE_CS1);
	}
	if (machine_is_omap_perseus2()) {
		/* configure pins: MPU_UW_nSCS1, MPU_UW_SDO, MPU_UW_SCLK */
		int val = omap_readl(OMAP7XX_IO_CONF_9) & ~0x00EEE000;
		omap_writel(val | 0x00AAA000, OMAP7XX_IO_CONF_9);
	}

	return platform_driver_register(&uwire_driver);
}

static void __exit omap_uwire_exit(void)
{
	platform_driver_unregister(&uwire_driver);
}

subsys_initcall(omap_uwire_init);
module_exit(omap_uwire_exit);

MODULE_LICENSE("GPL");
Commit	Line	Data
fdb3c18d	1	/*
ca632f55	2	* MicroWire interface driver for OMAP
fdb3c18d DB	3	*
	4	* Copyright 2003 MontaVista Software Inc. <source@mvista.com>
	5	*
	6	* Ported to 2.6 OMAP uwire interface.
	7	* Copyright (C) 2004 Texas Instruments.
	8	*
	9	* Generalization patches by Juha Yrjola <juha.yrjola@nokia.com>
	10	*
	11	* Copyright (C) 2005 David Brownell (ported to 2.6 SPI interface)
	12	* Copyright (C) 2006 Nokia
	13	*
	14	* Many updates by Imre Deak <imre.deak@nokia.com>
	15	*
	16	* This program is free software; you can redistribute it and/or modify it
	17	* under the terms of the GNU General Public License as published by the
	18	* Free Software Foundation; either version 2 of the License, or (at your
	19	* option) any later version.
	20	*
	21	* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
	22	* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
	23	* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
	24	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
	25	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
	26	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
	27	* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
	28	* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
	29	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
	30	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
fdb3c18d DB	31	*/
	32	#include <linux/kernel.h>
	33	#include <linux/init.h>
	34	#include <linux/delay.h>
	35	#include <linux/platform_device.h>
fdb3c18d DB	36	#include <linux/interrupt.h>
	37	#include <linux/err.h>
	38	#include <linux/clk.h>
5a0e3ad6	39	#include <linux/slab.h>
1820a8fc	40	#include <linux/device.h>
fdb3c18d DB	41
	42	#include <linux/spi/spi.h>
	43	#include <linux/spi/spi_bitbang.h>
d7614de4	44	#include <linux/module.h>
ec17a7f2	45	#include <linux/io.h>
fdb3c18d	46
a09e64fb	47	#include <mach/hardware.h>
fdb3c18d DB	48	#include <asm/mach-types.h>
fdb3c18d DB	49
70c494c3	50	#include <mach/mux.h>
68cb700c TL	51
68cb700c TL	52	#include <mach/omap7xx.h> /* OMAP7XX_IO_CONF registers */
fdb3c18d DB	53
	54
	55	/* FIXME address is now a platform device resource,
	56	* and irqs should show there too...
	57	*/
	58	#define UWIRE_BASE_PHYS 0xFFFB3000
fdb3c18d DB	59
	60	/* uWire Registers: */
	61	#define UWIRE_IO_SIZE 0x20
	62	#define UWIRE_TDR 0x00
	63	#define UWIRE_RDR 0x00
	64	#define UWIRE_CSR 0x01
	65	#define UWIRE_SR1 0x02
	66	#define UWIRE_SR2 0x03
	67	#define UWIRE_SR3 0x04
	68	#define UWIRE_SR4 0x05
	69	#define UWIRE_SR5 0x06
	70
	71	/* CSR bits */
	72	#define RDRB (1 << 15)
	73	#define CSRB (1 << 14)
	74	#define START (1 << 13)
	75	#define CS_CMD (1 << 12)
	76
	77	/* SR1 or SR2 bits */
	78	#define UWIRE_READ_FALLING_EDGE 0x0001
	79	#define UWIRE_READ_RISING_EDGE 0x0000
	80	#define UWIRE_WRITE_FALLING_EDGE 0x0000
	81	#define UWIRE_WRITE_RISING_EDGE 0x0002
	82	#define UWIRE_CS_ACTIVE_LOW 0x0000
	83	#define UWIRE_CS_ACTIVE_HIGH 0x0004
	84	#define UWIRE_FREQ_DIV_2 0x0000
	85	#define UWIRE_FREQ_DIV_4 0x0008
	86	#define UWIRE_FREQ_DIV_8 0x0010
	87	#define UWIRE_CHK_READY 0x0020
	88	#define UWIRE_CLK_INVERTED 0x0040
	89
	90
	91	struct uwire_spi {
	92	struct spi_bitbang bitbang;
	93	struct clk *ck;
	94	};
	95
	96	struct uwire_state {
fdb3c18d DB	97	unsigned div1_idx;
	98	};
	99
	100	/* REVISIT compile time constant for idx_shift? */
55c381e4 RK	101	/*
	102	* Or, put it in a structure which is used throughout the driver;
	103	* that avoids having to issue two loads for each bit of static data.
	104	*/
fdb3c18d	105	static unsigned int uwire_idx_shift;
55c381e4	106	static void __iomem *uwire_base;
fdb3c18d DB	107
	108	static inline void uwire_write_reg(int idx, u16 val)
	109	{
55c381e4	110	__raw_writew(val, uwire_base + (idx << uwire_idx_shift));
fdb3c18d DB	111	}
	112
	113	static inline u16 uwire_read_reg(int idx)
	114	{
55c381e4	115	return __raw_readw(uwire_base + (idx << uwire_idx_shift));
fdb3c18d DB	116	}
	117
	118	static inline void omap_uwire_configure_mode(u8 cs, unsigned long flags)
	119	{
	120	u16 w, val = 0;
	121	int shift, reg;
	122
	123	if (flags & UWIRE_CLK_INVERTED)
	124	val ^= 0x03;
	125	val = flags & 0x3f;
	126	if (cs & 1)
	127	shift = 6;
	128	else
	129	shift = 0;
	130	if (cs <= 1)
	131	reg = UWIRE_SR1;
	132	else
	133	reg = UWIRE_SR2;
	134
	135	w = uwire_read_reg(reg);
	136	w &= ~(0x3f << shift);
	137	w \|= val << shift;
	138	uwire_write_reg(reg, w);
	139	}
	140
	141	static int wait_uwire_csr_flag(u16 mask, u16 val, int might_not_catch)
	142	{
	143	u16 w;
	144	int c = 0;
	145	unsigned long max_jiffies = jiffies + HZ;
	146
	147	for (;;) {
	148	w = uwire_read_reg(UWIRE_CSR);
	149	if ((w & mask) == val)
	150	break;
	151	if (time_after(jiffies, max_jiffies)) {
	152	printk(KERN_ERR "%s: timeout. reg=%#06x "
	153	"mask=%#06x val=%#06x\n",
b687d2a8	154	__func__, w, mask, val);
fdb3c18d DB	155	return -1;
	156	}
	157	c++;
	158	if (might_not_catch && c > 64)
	159	break;
	160	}
	161	return 0;
	162	}
	163
	164	static void uwire_set_clk1_div(int div1_idx)
	165	{
	166	u16 w;
	167
	168	w = uwire_read_reg(UWIRE_SR3);
	169	w &= ~(0x03 << 1);
	170	w \|= div1_idx << 1;
	171	uwire_write_reg(UWIRE_SR3, w);
	172	}
	173
	174	static void uwire_chipselect(struct spi_device *spi, int value)
	175	{
	176	struct uwire_state *ust = spi->controller_state;
	177	u16 w;
	178	int old_cs;
	179
	180
	181	BUG_ON(wait_uwire_csr_flag(CSRB, 0, 0));
	182
	183	w = uwire_read_reg(UWIRE_CSR);
	184	old_cs = (w >> 10) & 0x03;
	185	if (value == BITBANG_CS_INACTIVE \|\| old_cs != spi->chip_select) {
	186	/* Deselect this CS, or the previous CS */
	187	w &= ~CS_CMD;
	188	uwire_write_reg(UWIRE_CSR, w);
	189	}
	190	/* activate specfied chipselect */
	191	if (value == BITBANG_CS_ACTIVE) {
	192	uwire_set_clk1_div(ust->div1_idx);
	193	/* invert clock? */
	194	if (spi->mode & SPI_CPOL)
	195	uwire_write_reg(UWIRE_SR4, 1);
	196	else
	197	uwire_write_reg(UWIRE_SR4, 0);
	198
	199	w = spi->chip_select << 10;
	200	w \|= CS_CMD;
	201	uwire_write_reg(UWIRE_CSR, w);
	202	}
	203	}
	204
	205	static int uwire_txrx(struct spi_device spi, struct spi_transfer t)
	206	{
fdb3c18d	207	unsigned len = t->len;
160f8d06	208	unsigned bits = t->bits_per_word;
fdb3c18d DB	209	unsigned bytes;
fdb3c18d DB	210	u16 val, w;
a419aef8	211	int status = 0;
fdb3c18d DB	212
	213	if (!t->tx_buf && !t->rx_buf)
	214	return 0;
	215
fdb3c18d DB	216	w = spi->chip_select << 10;
	217	w \|= CS_CMD;
	218
	219	if (t->tx_buf) {
	220	const u8 *buf = t->tx_buf;
	221
	222	/* NOTE: DMA could be used for TX transfers */
	223
	224	/* write one or two bytes at a time */
	225	while (len >= 1) {
	226	/* tx bit 15 is first sent; we byteswap multibyte words
	227	* (msb-first) on the way out from memory.
	228	*/
	229	val = *buf++;
	230	if (bits > 8) {
	231	bytes = 2;
	232	val \|= *buf++ << 8;
	233	} else
	234	bytes = 1;
	235	val <<= 16 - bits;
	236
	237	#ifdef VERBOSE
	238	pr_debug("%s: write-%d =%04x\n",
6c7377ab	239	dev_name(&spi->dev), bits, val);
fdb3c18d DB	240	#endif
	241	if (wait_uwire_csr_flag(CSRB, 0, 0))
	242	goto eio;
	243
	244	uwire_write_reg(UWIRE_TDR, val);
	245
	246	/* start write */
	247	val = START \| w \| (bits << 5);
	248
	249	uwire_write_reg(UWIRE_CSR, val);
	250	len -= bytes;
	251
	252	/* Wait till write actually starts.
	253	* This is needed with MPU clock 60+ MHz.
	254	* REVISIT: we may not have time to catch it...
	255	*/
	256	if (wait_uwire_csr_flag(CSRB, CSRB, 1))
	257	goto eio;
	258
	259	status += bytes;
	260	}
	261
	262	/* REVISIT: save this for later to get more i/o overlap */
	263	if (wait_uwire_csr_flag(CSRB, 0, 0))
	264	goto eio;
	265
	266	} else if (t->rx_buf) {
	267	u8 *buf = t->rx_buf;
	268
	269	/* read one or two bytes at a time */
	270	while (len) {
	271	if (bits > 8) {
	272	bytes = 2;
	273	} else
	274	bytes = 1;
	275
	276	/* start read */
	277	val = START \| w \| (bits << 0);
	278	uwire_write_reg(UWIRE_CSR, val);
	279	len -= bytes;
	280
	281	/* Wait till read actually starts */
	282	(void) wait_uwire_csr_flag(CSRB, CSRB, 1);
	283
	284	if (wait_uwire_csr_flag(RDRB \| CSRB,
	285	RDRB, 0))
	286	goto eio;
	287
	288	/* rx bit 0 is last received; multibyte words will
	289	* be properly byteswapped on the way to memory.
	290	*/
	291	val = uwire_read_reg(UWIRE_RDR);
	292	val &= (1 << bits) - 1;
	293	*buf++ = (u8) val;
	294	if (bytes == 2)
	295	*buf++ = val >> 8;
	296	status += bytes;
	297	#ifdef VERBOSE
	298	pr_debug("%s: read-%d =%04x\n",
6c7377ab	299	dev_name(&spi->dev), bits, val);
fdb3c18d DB	300	#endif
	301
	302	}
	303	}
	304	return status;
	305	eio:
	306	return -EIO;
	307	}
	308
	309	static int uwire_setup_transfer(struct spi_device spi, struct spi_transfer t)
	310	{
	311	struct uwire_state *ust = spi->controller_state;
	312	struct uwire_spi *uwire;
	313	unsigned flags = 0;
fdb3c18d DB	314	unsigned hz;
	315	unsigned long rate;
	316	int div1_idx;
	317	int div1;
	318	int div2;
	319	int status;
	320
	321	uwire = spi_master_get_devdata(spi->master);
	322
fdb3c18d DB	323	/* mode 0..3, clock inverted separately;
	324	* standard nCS signaling;
	325	* don't treat DI=high as "not ready"
	326	*/
	327	if (spi->mode & SPI_CS_HIGH)
	328	flags \|= UWIRE_CS_ACTIVE_HIGH;
	329
	330	if (spi->mode & SPI_CPOL)
	331	flags \|= UWIRE_CLK_INVERTED;
	332
	333	switch (spi->mode & (SPI_CPOL \| SPI_CPHA)) {
	334	case SPI_MODE_0:
	335	case SPI_MODE_3:
e5f1b194	336	flags \|= UWIRE_WRITE_FALLING_EDGE \| UWIRE_READ_RISING_EDGE;
fdb3c18d DB	337	break;
	338	case SPI_MODE_1:
	339	case SPI_MODE_2:
e5f1b194	340	flags \|= UWIRE_WRITE_RISING_EDGE \| UWIRE_READ_FALLING_EDGE;
fdb3c18d DB	341	break;
	342	}
	343
	344	/* assume it's already enabled */
	345	rate = clk_get_rate(uwire->ck);
	346
160f8d06	347	if (t != NULL)
fdb3c18d	348	hz = t->speed_hz;
160f8d06 JN	349	else
160f8d06 JN	350	hz = spi->max_speed_hz;
fdb3c18d DB	351
fdb3c18d DB	352	if (!hz) {
6c7377ab	353	pr_debug("%s: zero speed?\n", dev_name(&spi->dev));
fdb3c18d DB	354	status = -EINVAL;
	355	goto done;
	356	}
	357
	358	/* F_INT = mpu_xor_clk / DIV1 */
	359	for (div1_idx = 0; div1_idx < 4; div1_idx++) {
	360	switch (div1_idx) {
	361	case 0:
	362	div1 = 2;
	363	break;
	364	case 1:
	365	div1 = 4;
	366	break;
	367	case 2:
	368	div1 = 7;
	369	break;
	370	default:
	371	case 3:
	372	div1 = 10;
	373	break;
	374	}
	375	div2 = (rate / div1 + hz - 1) / hz;
	376	if (div2 <= 8)
	377	break;
	378	}
	379	if (div1_idx == 4) {
	380	pr_debug("%s: lowest clock %ld, need %d\n",
6c7377ab	381	dev_name(&spi->dev), rate / 10 / 8, hz);
fdb3c18d DB	382	status = -EDOM;
	383	goto done;
	384	}
	385
	386	/* we have to cache this and reset in uwire_chipselect as this is a
	387	* global parameter and another uwire device can change it under
	388	* us */
	389	ust->div1_idx = div1_idx;
	390	uwire_set_clk1_div(div1_idx);
	391
	392	rate /= div1;
	393
	394	switch (div2) {
	395	case 0:
	396	case 1:
	397	case 2:
	398	flags \|= UWIRE_FREQ_DIV_2;
	399	rate /= 2;
	400	break;
	401	case 3:
	402	case 4:
	403	flags \|= UWIRE_FREQ_DIV_4;
	404	rate /= 4;
	405	break;
	406	case 5:
	407	case 6:
	408	case 7:
	409	case 8:
	410	flags \|= UWIRE_FREQ_DIV_8;
	411	rate /= 8;
	412	break;
	413	}
	414	omap_uwire_configure_mode(spi->chip_select, flags);
	415	pr_debug("%s: uwire flags %02x, armxor %lu KHz, SCK %lu KHz\n",
b687d2a8	416	__func__, flags,
fdb3c18d DB	417	clk_get_rate(uwire->ck) / 1000,
	418	rate / 1000);
	419	status = 0;
	420	done:
	421	return status;
	422	}
	423
	424	static int uwire_setup(struct spi_device *spi)
	425	{
	426	struct uwire_state *ust = spi->controller_state;
	427
	428	if (ust == NULL) {
	429	ust = kzalloc(sizeof(*ust), GFP_KERNEL);
	430	if (ust == NULL)
	431	return -ENOMEM;
	432	spi->controller_state = ust;
	433	}
	434
	435	return uwire_setup_transfer(spi, NULL);
	436	}
	437
bb2d1c36	438	static void uwire_cleanup(struct spi_device *spi)
fdb3c18d DB	439	{
	440	kfree(spi->controller_state);
	441	}
	442
	443	static void uwire_off(struct uwire_spi *uwire)
	444	{
	445	uwire_write_reg(UWIRE_SR3, 0);
	446	clk_disable(uwire->ck);
fdb3c18d DB	447	spi_master_put(uwire->bitbang.master);
	448	}
	449
2deff8d6	450	static int uwire_probe(struct platform_device *pdev)
fdb3c18d DB	451	{
	452	struct spi_master *master;
	453	struct uwire_spi *uwire;
	454	int status;
	455
	456	master = spi_alloc_master(&pdev->dev, sizeof *uwire);
	457	if (!master)
	458	return -ENODEV;
	459
	460	uwire = spi_master_get_devdata(master);
55c381e4	461
b3f6a575	462	uwire_base = devm_ioremap(&pdev->dev, UWIRE_BASE_PHYS, UWIRE_IO_SIZE);
55c381e4 RK	463	if (!uwire_base) {
	464	dev_dbg(&pdev->dev, "can't ioremap UWIRE\n");
	465	spi_master_put(master);
	466	return -ENOMEM;
	467	}
	468
24b5a82c	469	platform_set_drvdata(pdev, uwire);
fdb3c18d	470
b3f6a575	471	uwire->ck = devm_clk_get(&pdev->dev, "fck");
b1ad3796 RK	472	if (IS_ERR(uwire->ck)) {
	473	status = PTR_ERR(uwire->ck);
	474	dev_dbg(&pdev->dev, "no functional clock?\n");
fdb3c18d	475	spi_master_put(master);
b1ad3796	476	return status;
fdb3c18d DB	477	}
	478	clk_enable(uwire->ck);
	479
7a8f48f8	480	if (cpu_is_omap7xx())
fdb3c18d DB	481	uwire_idx_shift = 1;
	482	else
	483	uwire_idx_shift = 2;
	484
	485	uwire_write_reg(UWIRE_SR3, 1);
	486
e7db06b5 DB	487	/* the spi->mode bits understood by this driver: */
e7db06b5 DB	488	master->mode_bits = SPI_CPOL \| SPI_CPHA \| SPI_CS_HIGH;
790fc55a	489	master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 16);
70d6027f DB	490	master->flags = SPI_MASTER_HALF_DUPLEX;
70d6027f DB	491
fdb3c18d DB	492	master->bus_num = 2; /* "official" */
	493	master->num_chipselect = 4;
	494	master->setup = uwire_setup;
	495	master->cleanup = uwire_cleanup;
	496
	497	uwire->bitbang.master = master;
	498	uwire->bitbang.chipselect = uwire_chipselect;
	499	uwire->bitbang.setup_transfer = uwire_setup_transfer;
	500	uwire->bitbang.txrx_bufs = uwire_txrx;
	501
	502	status = spi_bitbang_start(&uwire->bitbang);
55c381e4	503	if (status < 0) {
fdb3c18d	504	uwire_off(uwire);
55c381e4	505	}
fdb3c18d DB	506	return status;
	507	}
	508
2deff8d6	509	static int uwire_remove(struct platform_device *pdev)
fdb3c18d	510	{
24b5a82c	511	struct uwire_spi *uwire = platform_get_drvdata(pdev);
fdb3c18d DB	512
	513	// FIXME remove all child devices, somewhere ...
	514
d9721ae1	515	spi_bitbang_stop(&uwire->bitbang);
fdb3c18d	516	uwire_off(uwire);
d9721ae1	517	return 0;
fdb3c18d DB	518	}
fdb3c18d DB	519
7e38c3c4 KS	520	/* work with hotplug and coldplug */
	521	MODULE_ALIAS("platform:omap_uwire");
	522
fdb3c18d DB	523	static struct platform_driver uwire_driver = {
	524	.driver = {
	525	.name = "omap_uwire",
fdb3c18d	526	},
93e9c900 WS	527	.probe = uwire_probe,
93e9c900 WS	528	.remove = uwire_remove,
fdb3c18d DB	529	// suspend ... unuse ck
	530	// resume ... use ck
	531	};
	532
	533	static int __init omap_uwire_init(void)
	534	{
	535	/* FIXME move these into the relevant board init code. also, include
	536	* H3 support; it uses tsc2101 like H2 (on a different chipselect).
	537	*/
	538
	539	if (machine_is_omap_h2()) {
	540	/* defaults: W21 SDO, U18 SDI, V19 SCL */
	541	omap_cfg_reg(N14_1610_UWIRE_CS0);
	542	omap_cfg_reg(N15_1610_UWIRE_CS1);
	543	}
	544	if (machine_is_omap_perseus2()) {
	545	/* configure pins: MPU_UW_nSCS1, MPU_UW_SDO, MPU_UW_SCLK */
7a8f48f8 AB	546	int val = omap_readl(OMAP7XX_IO_CONF_9) & ~0x00EEE000;
7a8f48f8 AB	547	omap_writel(val \| 0x00AAA000, OMAP7XX_IO_CONF_9);
fdb3c18d DB	548	}
fdb3c18d DB	549
93e9c900	550	return platform_driver_register(&uwire_driver);
fdb3c18d DB	551	}
	552
	553	static void __exit omap_uwire_exit(void)
	554	{
	555	platform_driver_unregister(&uwire_driver);
	556	}
	557
	558	subsys_initcall(omap_uwire_init);
	559	module_exit(omap_uwire_exit);
	560
	561	MODULE_LICENSE("GPL");
	562