[linux-2.6-block.git] / drivers / spi / spi-fsl-dspi.c

/*
 * drivers/spi/spi-fsl-dspi.c
 *
 * Copyright 2013 Freescale Semiconductor, Inc.
 *
 * Freescale DSPI driver
 * This file contains a driver for the Freescale DSPI
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 */

#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/errno.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/math64.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <linux/sched.h>
#include <linux/spi/spi.h>
#include <linux/spi/spi_bitbang.h>
#include <linux/time.h>

#define DRIVER_NAME "fsl-dspi"

#define TRAN_STATE_RX_VOID		0x01
#define TRAN_STATE_TX_VOID		0x02
#define TRAN_STATE_WORD_ODD_NUM	0x04

#define DSPI_FIFO_SIZE			4

#define SPI_MCR		0x00
#define SPI_MCR_MASTER		(1 << 31)
#define SPI_MCR_PCSIS		(0x3F << 16)
#define SPI_MCR_CLR_TXF	(1 << 11)
#define SPI_MCR_CLR_RXF	(1 << 10)

#define SPI_TCR			0x08

#define SPI_CTAR(x)		(0x0c + (((x) & 0x3) * 4))
#define SPI_CTAR_FMSZ(x)	(((x) & 0x0000000f) << 27)
#define SPI_CTAR_CPOL(x)	((x) << 26)
#define SPI_CTAR_CPHA(x)	((x) << 25)
#define SPI_CTAR_LSBFE(x)	((x) << 24)
#define SPI_CTAR_PCSSCK(x)	(((x) & 0x00000003) << 22)
#define SPI_CTAR_PASC(x)	(((x) & 0x00000003) << 20)
#define SPI_CTAR_PDT(x)	(((x) & 0x00000003) << 18)
#define SPI_CTAR_PBR(x)	(((x) & 0x00000003) << 16)
#define SPI_CTAR_CSSCK(x)	(((x) & 0x0000000f) << 12)
#define SPI_CTAR_ASC(x)	(((x) & 0x0000000f) << 8)
#define SPI_CTAR_DT(x)		(((x) & 0x0000000f) << 4)
#define SPI_CTAR_BR(x)		((x) & 0x0000000f)
#define SPI_CTAR_SCALE_BITS	0xf

#define SPI_CTAR0_SLAVE	0x0c

#define SPI_SR			0x2c
#define SPI_SR_EOQF		0x10000000

#define SPI_RSER		0x30
#define SPI_RSER_EOQFE		0x10000000

#define SPI_PUSHR		0x34
#define SPI_PUSHR_CONT		(1 << 31)
#define SPI_PUSHR_CTAS(x)	(((x) & 0x00000003) << 28)
#define SPI_PUSHR_EOQ		(1 << 27)
#define SPI_PUSHR_CTCNT	(1 << 26)
#define SPI_PUSHR_PCS(x)	(((1 << x) & 0x0000003f) << 16)
#define SPI_PUSHR_TXDATA(x)	((x) & 0x0000ffff)

#define SPI_PUSHR_SLAVE	0x34

#define SPI_POPR		0x38
#define SPI_POPR_RXDATA(x)	((x) & 0x0000ffff)

#define SPI_TXFR0		0x3c
#define SPI_TXFR1		0x40
#define SPI_TXFR2		0x44
#define SPI_TXFR3		0x48
#define SPI_RXFR0		0x7c
#define SPI_RXFR1		0x80
#define SPI_RXFR2		0x84
#define SPI_RXFR3		0x88

#define SPI_FRAME_BITS(bits)	SPI_CTAR_FMSZ((bits) - 1)
#define SPI_FRAME_BITS_MASK	SPI_CTAR_FMSZ(0xf)
#define SPI_FRAME_BITS_16	SPI_CTAR_FMSZ(0xf)
#define SPI_FRAME_BITS_8	SPI_CTAR_FMSZ(0x7)

#define SPI_CS_INIT		0x01
#define SPI_CS_ASSERT		0x02
#define SPI_CS_DROP		0x04

struct chip_data {
	u32 mcr_val;
	u32 ctar_val;
	u16 void_write_data;
};

struct fsl_dspi {
	struct spi_master	*master;
	struct platform_device	*pdev;

	struct regmap		*regmap;
	int			irq;
	struct clk		*clk;

	struct spi_transfer	*cur_transfer;
	struct spi_message	*cur_msg;
	struct chip_data	*cur_chip;
	size_t			len;
	void			*tx;
	void			*tx_end;
	void			*rx;
	void			*rx_end;
	char			dataflags;
	u8			cs;
	u16			void_write_data;
	u32			cs_change;

	wait_queue_head_t	waitq;
	u32			waitflags;
};

static inline int is_double_byte_mode(struct fsl_dspi *dspi)
{
	unsigned int val;

	regmap_read(dspi->regmap, SPI_CTAR(dspi->cs), &val);

	return ((val & SPI_FRAME_BITS_MASK) == SPI_FRAME_BITS(8)) ? 0 : 1;
}

static void hz_to_spi_baud(char *pbr, char *br, int speed_hz,
		unsigned long clkrate)
{
	/* Valid baud rate pre-scaler values */
	int pbr_tbl[4] = {2, 3, 5, 7};
	int brs[16] = {	2,	4,	6,	8,
		16,	32,	64,	128,
		256,	512,	1024,	2048,
		4096,	8192,	16384,	32768 };
	int scale_needed, scale, minscale = INT_MAX;
	int i, j;

	scale_needed = clkrate / speed_hz;
	if (clkrate % speed_hz)
		scale_needed++;

	for (i = 0; i < ARRAY_SIZE(brs); i++)
		for (j = 0; j < ARRAY_SIZE(pbr_tbl); j++) {
			scale = brs[i] * pbr_tbl[j];
			if (scale >= scale_needed) {
				if (scale < minscale) {
					minscale = scale;
					*br = i;
					*pbr = j;
				}
				break;
			}
		}

	if (minscale == INT_MAX) {
		pr_warn("Can not find valid baud rate,speed_hz is %d,clkrate is %ld, we use the max prescaler value.\n",
			speed_hz, clkrate);
		*pbr = ARRAY_SIZE(pbr_tbl) - 1;
		*br =  ARRAY_SIZE(brs) - 1;
	}
}

static void ns_delay_scale(char *psc, char *sc, int delay_ns,
		unsigned long clkrate)
{
	int pscale_tbl[4] = {1, 3, 5, 7};
	int scale_needed, scale, minscale = INT_MAX;
	int i, j;
	u32 remainder;

	scale_needed = div_u64_rem((u64)delay_ns * clkrate, NSEC_PER_SEC,
			&remainder);
	if (remainder)
		scale_needed++;

	for (i = 0; i < ARRAY_SIZE(pscale_tbl); i++)
		for (j = 0; j <= SPI_CTAR_SCALE_BITS; j++) {
			scale = pscale_tbl[i] * (2 << j);
			if (scale >= scale_needed) {
				if (scale < minscale) {
					minscale = scale;
					*psc = i;
					*sc = j;
				}
				break;
			}
		}

	if (minscale == INT_MAX) {
		pr_warn("Cannot find correct scale values for %dns delay at clkrate %ld, using max prescaler value",
			delay_ns, clkrate);
		*psc = ARRAY_SIZE(pscale_tbl) - 1;
		*sc = SPI_CTAR_SCALE_BITS;
	}
}

static int dspi_transfer_write(struct fsl_dspi *dspi)
{
	int tx_count = 0;
	int tx_word;
	u16 d16;
	u8  d8;
	u32 dspi_pushr = 0;
	int first = 1;

	tx_word = is_double_byte_mode(dspi);

	/* If we are in word mode, but only have a single byte to transfer
	 * then switch to byte mode temporarily.  Will switch back at the
	 * end of the transfer.
	 */
	if (tx_word && (dspi->len == 1)) {
		dspi->dataflags |= TRAN_STATE_WORD_ODD_NUM;
		regmap_update_bits(dspi->regmap, SPI_CTAR(dspi->cs),
				SPI_FRAME_BITS_MASK, SPI_FRAME_BITS(8));
		tx_word = 0;
	}

	while (dspi->len && (tx_count < DSPI_FIFO_SIZE)) {
		if (tx_word) {
			if (dspi->len == 1)
				break;

			if (!(dspi->dataflags & TRAN_STATE_TX_VOID)) {
				d16 = *(u16 *)dspi->tx;
				dspi->tx += 2;
			} else {
				d16 = dspi->void_write_data;
			}

			dspi_pushr = SPI_PUSHR_TXDATA(d16) |
				SPI_PUSHR_PCS(dspi->cs) |
				SPI_PUSHR_CTAS(dspi->cs) |
				SPI_PUSHR_CONT;

			dspi->len -= 2;
		} else {
			if (!(dspi->dataflags & TRAN_STATE_TX_VOID)) {

				d8 = *(u8 *)dspi->tx;
				dspi->tx++;
			} else {
				d8 = (u8)dspi->void_write_data;
			}

			dspi_pushr = SPI_PUSHR_TXDATA(d8) |
				SPI_PUSHR_PCS(dspi->cs) |
				SPI_PUSHR_CTAS(dspi->cs) |
				SPI_PUSHR_CONT;

			dspi->len--;
		}

		if (dspi->len == 0 || tx_count == DSPI_FIFO_SIZE - 1) {
			/* last transfer in the transfer */
			dspi_pushr |= SPI_PUSHR_EOQ;
			if ((dspi->cs_change) && (!dspi->len))
				dspi_pushr &= ~SPI_PUSHR_CONT;
		} else if (tx_word && (dspi->len == 1))
			dspi_pushr |= SPI_PUSHR_EOQ;

		if (first) {
			first = 0;
			dspi_pushr |= SPI_PUSHR_CTCNT; /* clear counter */
		}

		regmap_write(dspi->regmap, SPI_PUSHR, dspi_pushr);

		tx_count++;
	}

	return tx_count * (tx_word + 1);
}

static int dspi_transfer_read(struct fsl_dspi *dspi)
{
	int rx_count = 0;
	int rx_word = is_double_byte_mode(dspi);
	u16 d;

	while ((dspi->rx < dspi->rx_end)
			&& (rx_count < DSPI_FIFO_SIZE)) {
		if (rx_word) {
			unsigned int val;

			if ((dspi->rx_end - dspi->rx) == 1)
				break;

			regmap_read(dspi->regmap, SPI_POPR, &val);
			d = SPI_POPR_RXDATA(val);

			if (!(dspi->dataflags & TRAN_STATE_RX_VOID))
				*(u16 *)dspi->rx = d;
			dspi->rx += 2;

		} else {
			unsigned int val;

			regmap_read(dspi->regmap, SPI_POPR, &val);
			d = SPI_POPR_RXDATA(val);
			if (!(dspi->dataflags & TRAN_STATE_RX_VOID))
				*(u8 *)dspi->rx = d;
			dspi->rx++;
		}
		rx_count++;
	}

	return rx_count;
}

static int dspi_transfer_one_message(struct spi_master *master,
		struct spi_message *message)
{
	struct fsl_dspi *dspi = spi_master_get_devdata(master);
	struct spi_device *spi = message->spi;
	struct spi_transfer *transfer;
	int status = 0;
	message->actual_length = 0;

	list_for_each_entry(transfer, &message->transfers, transfer_list) {
		dspi->cur_transfer = transfer;
		dspi->cur_msg = message;
		dspi->cur_chip = spi_get_ctldata(spi);
		dspi->cs = spi->chip_select;
		if (dspi->cur_transfer->transfer_list.next
				== &dspi->cur_msg->transfers)
			transfer->cs_change = 1;
		dspi->cs_change = transfer->cs_change;
		dspi->void_write_data = dspi->cur_chip->void_write_data;

		dspi->dataflags = 0;
		dspi->tx = (void *)transfer->tx_buf;
		dspi->tx_end = dspi->tx + transfer->len;
		dspi->rx = transfer->rx_buf;
		dspi->rx_end = dspi->rx + transfer->len;
		dspi->len = transfer->len;

		if (!dspi->rx)
			dspi->dataflags |= TRAN_STATE_RX_VOID;

		if (!dspi->tx)
			dspi->dataflags |= TRAN_STATE_TX_VOID;

		regmap_write(dspi->regmap, SPI_MCR, dspi->cur_chip->mcr_val);
		regmap_update_bits(dspi->regmap, SPI_MCR,
				SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF,
				SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF);
		regmap_write(dspi->regmap, SPI_CTAR(dspi->cs),
				dspi->cur_chip->ctar_val);
		if (transfer->speed_hz)
			regmap_write(dspi->regmap, SPI_CTAR(dspi->cs),
					dspi->cur_chip->ctar_val);

		regmap_write(dspi->regmap, SPI_RSER, SPI_RSER_EOQFE);
		message->actual_length += dspi_transfer_write(dspi);

		if (wait_event_interruptible(dspi->waitq, dspi->waitflags))
			dev_err(&dspi->pdev->dev, "wait transfer complete fail!\n");
		dspi->waitflags = 0;

		if (transfer->delay_usecs)
			udelay(transfer->delay_usecs);
	}

	message->status = status;
	spi_finalize_current_message(master);

	return status;
}

static int dspi_setup(struct spi_device *spi)
{
	struct chip_data *chip;
	struct fsl_dspi *dspi = spi_master_get_devdata(spi->master);
	u32 cs_sck_delay = 0, sck_cs_delay = 0;
	unsigned char br = 0, pbr = 0, pcssck = 0, cssck = 0;
	unsigned char pasc = 0, asc = 0, fmsz = 0;
	unsigned long clkrate;

	if ((spi->bits_per_word >= 4) && (spi->bits_per_word <= 16)) {
		fmsz = spi->bits_per_word - 1;
	} else {
		pr_err("Invalid wordsize\n");
		return -ENODEV;
	}

	/* Only alloc on first setup */
	chip = spi_get_ctldata(spi);
	if (chip == NULL) {
		chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
		if (!chip)
			return -ENOMEM;
	}

	of_property_read_u32(spi->dev.of_node, "fsl,spi-cs-sck-delay",
			&cs_sck_delay);

	of_property_read_u32(spi->dev.of_node, "fsl,spi-sck-cs-delay",
			&sck_cs_delay);

	chip->mcr_val = SPI_MCR_MASTER | SPI_MCR_PCSIS |
		SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF;

	chip->void_write_data = 0;

	clkrate = clk_get_rate(dspi->clk);
	hz_to_spi_baud(&pbr, &br, spi->max_speed_hz, clkrate);

	/* Set PCS to SCK delay scale values */
	ns_delay_scale(&pcssck, &cssck, cs_sck_delay, clkrate);

	/* Set After SCK delay scale values */
	ns_delay_scale(&pasc, &asc, sck_cs_delay, clkrate);

	chip->ctar_val =  SPI_CTAR_FMSZ(fmsz)
		| SPI_CTAR_CPOL(spi->mode & SPI_CPOL ? 1 : 0)
		| SPI_CTAR_CPHA(spi->mode & SPI_CPHA ? 1 : 0)
		| SPI_CTAR_LSBFE(spi->mode & SPI_LSB_FIRST ? 1 : 0)
		| SPI_CTAR_PCSSCK(pcssck)
		| SPI_CTAR_CSSCK(cssck)
		| SPI_CTAR_PASC(pasc)
		| SPI_CTAR_ASC(asc)
		| SPI_CTAR_PBR(pbr)
		| SPI_CTAR_BR(br);

	spi_set_ctldata(spi, chip);

	return 0;
}

static void dspi_cleanup(struct spi_device *spi)
{
	struct chip_data *chip = spi_get_ctldata((struct spi_device *)spi);

	dev_dbg(&spi->dev, "spi_device %u.%u cleanup\n",
			spi->master->bus_num, spi->chip_select);

	kfree(chip);
}

static irqreturn_t dspi_interrupt(int irq, void *dev_id)
{
	struct fsl_dspi *dspi = (struct fsl_dspi *)dev_id;

	struct spi_message *msg = dspi->cur_msg;

	regmap_write(dspi->regmap, SPI_SR, SPI_SR_EOQF);
	dspi_transfer_read(dspi);

	if (!dspi->len) {
		if (dspi->dataflags & TRAN_STATE_WORD_ODD_NUM)
			regmap_update_bits(dspi->regmap, SPI_CTAR(dspi->cs),
			SPI_FRAME_BITS_MASK, SPI_FRAME_BITS(16));

		dspi->waitflags = 1;
		wake_up_interruptible(&dspi->waitq);
	} else
		msg->actual_length += dspi_transfer_write(dspi);

	return IRQ_HANDLED;
}

static const struct of_device_id fsl_dspi_dt_ids[] = {
	{ .compatible = "fsl,vf610-dspi", .data = NULL, },
	{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, fsl_dspi_dt_ids);

#ifdef CONFIG_PM_SLEEP
static int dspi_suspend(struct device *dev)
{
	struct spi_master *master = dev_get_drvdata(dev);
	struct fsl_dspi *dspi = spi_master_get_devdata(master);

	spi_master_suspend(master);
	clk_disable_unprepare(dspi->clk);

	return 0;
}

static int dspi_resume(struct device *dev)
{
	struct spi_master *master = dev_get_drvdata(dev);
	struct fsl_dspi *dspi = spi_master_get_devdata(master);

	clk_prepare_enable(dspi->clk);
	spi_master_resume(master);

	return 0;
}
#endif /* CONFIG_PM_SLEEP */

static SIMPLE_DEV_PM_OPS(dspi_pm, dspi_suspend, dspi_resume);

static const struct regmap_config dspi_regmap_config = {
	.reg_bits = 32,
	.val_bits = 32,
	.reg_stride = 4,
	.max_register = 0x88,
};

static int dspi_probe(struct platform_device *pdev)
{
	struct device_node *np = pdev->dev.of_node;
	struct spi_master *master;
	struct fsl_dspi *dspi;
	struct resource *res;
	void __iomem *base;
	int ret = 0, cs_num, bus_num;

	master = spi_alloc_master(&pdev->dev, sizeof(struct fsl_dspi));
	if (!master)
		return -ENOMEM;

	dspi = spi_master_get_devdata(master);
	dspi->pdev = pdev;
	dspi->master = master;

	master->transfer = NULL;
	master->setup = dspi_setup;
	master->transfer_one_message = dspi_transfer_one_message;
	master->dev.of_node = pdev->dev.of_node;

	master->cleanup = dspi_cleanup;
	master->mode_bits = SPI_CPOL | SPI_CPHA;
	master->bits_per_word_mask = SPI_BPW_MASK(4) | SPI_BPW_MASK(8) |
					SPI_BPW_MASK(16);

	ret = of_property_read_u32(np, "spi-num-chipselects", &cs_num);
	if (ret < 0) {
		dev_err(&pdev->dev, "can't get spi-num-chipselects\n");
		goto out_master_put;
	}
	master->num_chipselect = cs_num;

	ret = of_property_read_u32(np, "bus-num", &bus_num);
	if (ret < 0) {
		dev_err(&pdev->dev, "can't get bus-num\n");
		goto out_master_put;
	}
	master->bus_num = bus_num;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	base = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(base)) {
		ret = PTR_ERR(base);
		goto out_master_put;
	}

	dspi->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "dspi", base,
						&dspi_regmap_config);
	if (IS_ERR(dspi->regmap)) {
		dev_err(&pdev->dev, "failed to init regmap: %ld\n",
				PTR_ERR(dspi->regmap));
		return PTR_ERR(dspi->regmap);
	}

	dspi->irq = platform_get_irq(pdev, 0);
	if (dspi->irq < 0) {
		dev_err(&pdev->dev, "can't get platform irq\n");
		ret = dspi->irq;
		goto out_master_put;
	}

	ret = devm_request_irq(&pdev->dev, dspi->irq, dspi_interrupt, 0,
			pdev->name, dspi);
	if (ret < 0) {
		dev_err(&pdev->dev, "Unable to attach DSPI interrupt\n");
		goto out_master_put;
	}

	dspi->clk = devm_clk_get(&pdev->dev, "dspi");
	if (IS_ERR(dspi->clk)) {
		ret = PTR_ERR(dspi->clk);
		dev_err(&pdev->dev, "unable to get clock\n");
		goto out_master_put;
	}
	clk_prepare_enable(dspi->clk);

	init_waitqueue_head(&dspi->waitq);
	platform_set_drvdata(pdev, master);

	ret = spi_register_master(master);
	if (ret != 0) {
		dev_err(&pdev->dev, "Problem registering DSPI master\n");
		goto out_clk_put;
	}

	return ret;

out_clk_put:
	clk_disable_unprepare(dspi->clk);
out_master_put:
	spi_master_put(master);

	return ret;
}

static int dspi_remove(struct platform_device *pdev)
{
	struct spi_master *master = platform_get_drvdata(pdev);
	struct fsl_dspi *dspi = spi_master_get_devdata(master);

	/* Disconnect from the SPI framework */
	clk_disable_unprepare(dspi->clk);
	spi_unregister_master(dspi->master);
	spi_master_put(dspi->master);

	return 0;
}

static struct platform_driver fsl_dspi_driver = {
	.driver.name    = DRIVER_NAME,
	.driver.of_match_table = fsl_dspi_dt_ids,
	.driver.owner   = THIS_MODULE,
	.driver.pm = &dspi_pm,
	.probe          = dspi_probe,
	.remove		= dspi_remove,
};
module_platform_driver(fsl_dspi_driver);

MODULE_DESCRIPTION("Freescale DSPI Controller Driver");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:" DRIVER_NAME);
Commit	Line	Data
349ad66c CF	1	/*
	2	* drivers/spi/spi-fsl-dspi.c
	3	*
	4	* Copyright 2013 Freescale Semiconductor, Inc.
	5	*
	6	* Freescale DSPI driver
	7	* This file contains a driver for the Freescale DSPI
	8	*
	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License as published by
	11	* the Free Software Foundation; either version 2 of the License, or
	12	* (at your option) any later version.
	13	*
	14	*/
	15
a3108360 XL	16	#include <linux/clk.h>
	17	#include <linux/delay.h>
	18	#include <linux/err.h>
	19	#include <linux/errno.h>
	20	#include <linux/interrupt.h>
	21	#include <linux/io.h>
349ad66c	22	#include <linux/kernel.h>
95bf15f3	23	#include <linux/math64.h>
349ad66c	24	#include <linux/module.h>
a3108360 XL	25	#include <linux/of.h>
a3108360 XL	26	#include <linux/of_device.h>
349ad66c	27	#include <linux/platform_device.h>
a3108360	28	#include <linux/pm_runtime.h>
1acbdeb9	29	#include <linux/regmap.h>
349ad66c	30	#include <linux/sched.h>
349ad66c CF	31	#include <linux/spi/spi.h>
349ad66c CF	32	#include <linux/spi/spi_bitbang.h>
95bf15f3	33	#include <linux/time.h>
349ad66c CF	34
	35	#define DRIVER_NAME "fsl-dspi"
	36
	37	#define TRAN_STATE_RX_VOID 0x01
	38	#define TRAN_STATE_TX_VOID 0x02
	39	#define TRAN_STATE_WORD_ODD_NUM 0x04
	40
	41	#define DSPI_FIFO_SIZE 4
	42
	43	#define SPI_MCR 0x00
	44	#define SPI_MCR_MASTER (1 << 31)
	45	#define SPI_MCR_PCSIS (0x3F << 16)
	46	#define SPI_MCR_CLR_TXF (1 << 11)
	47	#define SPI_MCR_CLR_RXF (1 << 10)
	48
	49	#define SPI_TCR 0x08
	50
5cc7b047	51	#define SPI_CTAR(x) (0x0c + (((x) & 0x3) * 4))
349ad66c CF	52	#define SPI_CTAR_FMSZ(x) (((x) & 0x0000000f) << 27)
	53	#define SPI_CTAR_CPOL(x) ((x) << 26)
	54	#define SPI_CTAR_CPHA(x) ((x) << 25)
	55	#define SPI_CTAR_LSBFE(x) ((x) << 24)
95bf15f3	56	#define SPI_CTAR_PCSSCK(x) (((x) & 0x00000003) << 22)
349ad66c CF	57	#define SPI_CTAR_PASC(x) (((x) & 0x00000003) << 20)
	58	#define SPI_CTAR_PDT(x) (((x) & 0x00000003) << 18)
	59	#define SPI_CTAR_PBR(x) (((x) & 0x00000003) << 16)
	60	#define SPI_CTAR_CSSCK(x) (((x) & 0x0000000f) << 12)
	61	#define SPI_CTAR_ASC(x) (((x) & 0x0000000f) << 8)
	62	#define SPI_CTAR_DT(x) (((x) & 0x0000000f) << 4)
	63	#define SPI_CTAR_BR(x) ((x) & 0x0000000f)
95bf15f3	64	#define SPI_CTAR_SCALE_BITS 0xf
349ad66c CF	65
	66	#define SPI_CTAR0_SLAVE 0x0c
	67
	68	#define SPI_SR 0x2c
	69	#define SPI_SR_EOQF 0x10000000
	70
	71	#define SPI_RSER 0x30
	72	#define SPI_RSER_EOQFE 0x10000000
	73
	74	#define SPI_PUSHR 0x34
	75	#define SPI_PUSHR_CONT (1 << 31)
5cc7b047	76	#define SPI_PUSHR_CTAS(x) (((x) & 0x00000003) << 28)
349ad66c CF	77	#define SPI_PUSHR_EOQ (1 << 27)
	78	#define SPI_PUSHR_CTCNT (1 << 26)
	79	#define SPI_PUSHR_PCS(x) (((1 << x) & 0x0000003f) << 16)
	80	#define SPI_PUSHR_TXDATA(x) ((x) & 0x0000ffff)
	81
	82	#define SPI_PUSHR_SLAVE 0x34
	83
	84	#define SPI_POPR 0x38
	85	#define SPI_POPR_RXDATA(x) ((x) & 0x0000ffff)
	86
	87	#define SPI_TXFR0 0x3c
	88	#define SPI_TXFR1 0x40
	89	#define SPI_TXFR2 0x44
	90	#define SPI_TXFR3 0x48
	91	#define SPI_RXFR0 0x7c
	92	#define SPI_RXFR1 0x80
	93	#define SPI_RXFR2 0x84
	94	#define SPI_RXFR3 0x88
	95
	96	#define SPI_FRAME_BITS(bits) SPI_CTAR_FMSZ((bits) - 1)
	97	#define SPI_FRAME_BITS_MASK SPI_CTAR_FMSZ(0xf)
	98	#define SPI_FRAME_BITS_16 SPI_CTAR_FMSZ(0xf)
	99	#define SPI_FRAME_BITS_8 SPI_CTAR_FMSZ(0x7)
	100
	101	#define SPI_CS_INIT 0x01
	102	#define SPI_CS_ASSERT 0x02
	103	#define SPI_CS_DROP 0x04
	104
	105	struct chip_data {
	106	u32 mcr_val;
	107	u32 ctar_val;
	108	u16 void_write_data;
	109	};
	110
	111	struct fsl_dspi {
9298bc72	112	struct spi_master *master;
349ad66c CF	113	struct platform_device *pdev;
349ad66c CF	114
1acbdeb9	115	struct regmap *regmap;
349ad66c	116	int irq;
88386e85	117	struct clk *clk;
349ad66c	118
88386e85	119	struct spi_transfer *cur_transfer;
9298bc72	120	struct spi_message *cur_msg;
349ad66c CF	121	struct chip_data *cur_chip;
	122	size_t len;
	123	void *tx;
	124	void *tx_end;
	125	void *rx;
	126	void *rx_end;
	127	char dataflags;
	128	u8 cs;
	129	u16 void_write_data;
9298bc72	130	u32 cs_change;
349ad66c	131
88386e85 CF	132	wait_queue_head_t waitq;
88386e85 CF	133	u32 waitflags;
349ad66c CF	134	};
	135
	136	static inline int is_double_byte_mode(struct fsl_dspi *dspi)
	137	{
1acbdeb9	138	unsigned int val;
349ad66c	139
1acbdeb9	140	regmap_read(dspi->regmap, SPI_CTAR(dspi->cs), &val);
349ad66c	141
1acbdeb9	142	return ((val & SPI_FRAME_BITS_MASK) == SPI_FRAME_BITS(8)) ? 0 : 1;
349ad66c CF	143	}
	144
	145	static void hz_to_spi_baud(char pbr, char br, int speed_hz,
	146	unsigned long clkrate)
	147	{
	148	/* Valid baud rate pre-scaler values */
	149	int pbr_tbl[4] = {2, 3, 5, 7};
	150	int brs[16] = { 2, 4, 6, 8,
	151	16, 32, 64, 128,
	152	256, 512, 1024, 2048,
	153	4096, 8192, 16384, 32768 };
6fd63087 AB	154	int scale_needed, scale, minscale = INT_MAX;
	155	int i, j;
	156
	157	scale_needed = clkrate / speed_hz;
e689d6df AB	158	if (clkrate % speed_hz)
e689d6df AB	159	scale_needed++;
6fd63087 AB	160
	161	for (i = 0; i < ARRAY_SIZE(brs); i++)
	162	for (j = 0; j < ARRAY_SIZE(pbr_tbl); j++) {
	163	scale = brs[i] * pbr_tbl[j];
	164	if (scale >= scale_needed) {
	165	if (scale < minscale) {
	166	minscale = scale;
	167	*br = i;
	168	*pbr = j;
	169	}
	170	break;
349ad66c CF	171	}
	172	}
	173
6fd63087 AB	174	if (minscale == INT_MAX) {
	175	pr_warn("Can not find valid baud rate,speed_hz is %d,clkrate is %ld, we use the max prescaler value.\n",
	176	speed_hz, clkrate);
	177	*pbr = ARRAY_SIZE(pbr_tbl) - 1;
	178	*br = ARRAY_SIZE(brs) - 1;
	179	}
349ad66c CF	180	}
349ad66c CF	181
95bf15f3 AB	182	static void ns_delay_scale(char psc, char sc, int delay_ns,
	183	unsigned long clkrate)
	184	{
	185	int pscale_tbl[4] = {1, 3, 5, 7};
	186	int scale_needed, scale, minscale = INT_MAX;
	187	int i, j;
	188	u32 remainder;
	189
	190	scale_needed = div_u64_rem((u64)delay_ns * clkrate, NSEC_PER_SEC,
	191	&remainder);
	192	if (remainder)
	193	scale_needed++;
	194
	195	for (i = 0; i < ARRAY_SIZE(pscale_tbl); i++)
	196	for (j = 0; j <= SPI_CTAR_SCALE_BITS; j++) {
	197	scale = pscale_tbl[i] * (2 << j);
	198	if (scale >= scale_needed) {
	199	if (scale < minscale) {
	200	minscale = scale;
	201	*psc = i;
	202	*sc = j;
	203	}
	204	break;
	205	}
	206	}
	207
	208	if (minscale == INT_MAX) {
	209	pr_warn("Cannot find correct scale values for %dns delay at clkrate %ld, using max prescaler value",
	210	delay_ns, clkrate);
	211	*psc = ARRAY_SIZE(pscale_tbl) - 1;
	212	*sc = SPI_CTAR_SCALE_BITS;
	213	}
	214	}
	215
349ad66c CF	216	static int dspi_transfer_write(struct fsl_dspi *dspi)
	217	{
	218	int tx_count = 0;
	219	int tx_word;
	220	u16 d16;
	221	u8 d8;
	222	u32 dspi_pushr = 0;
	223	int first = 1;
	224
	225	tx_word = is_double_byte_mode(dspi);
	226
	227	/* If we are in word mode, but only have a single byte to transfer
	228	* then switch to byte mode temporarily. Will switch back at the
	229	* end of the transfer.
	230	*/
	231	if (tx_word && (dspi->len == 1)) {
	232	dspi->dataflags \|= TRAN_STATE_WORD_ODD_NUM;
1acbdeb9 CF	233	regmap_update_bits(dspi->regmap, SPI_CTAR(dspi->cs),
1acbdeb9 CF	234	SPI_FRAME_BITS_MASK, SPI_FRAME_BITS(8));
349ad66c CF	235	tx_word = 0;
	236	}
	237
	238	while (dspi->len && (tx_count < DSPI_FIFO_SIZE)) {
	239	if (tx_word) {
	240	if (dspi->len == 1)
	241	break;
	242
	243	if (!(dspi->dataflags & TRAN_STATE_TX_VOID)) {
	244	d16 = (u16 )dspi->tx;
	245	dspi->tx += 2;
	246	} else {
	247	d16 = dspi->void_write_data;
	248	}
	249
	250	dspi_pushr = SPI_PUSHR_TXDATA(d16) \|
	251	SPI_PUSHR_PCS(dspi->cs) \|
	252	SPI_PUSHR_CTAS(dspi->cs) \|
	253	SPI_PUSHR_CONT;
	254
	255	dspi->len -= 2;
	256	} else {
	257	if (!(dspi->dataflags & TRAN_STATE_TX_VOID)) {
	258
	259	d8 = (u8 )dspi->tx;
	260	dspi->tx++;
	261	} else {
	262	d8 = (u8)dspi->void_write_data;
	263	}
	264
	265	dspi_pushr = SPI_PUSHR_TXDATA(d8) \|
	266	SPI_PUSHR_PCS(dspi->cs) \|
	267	SPI_PUSHR_CTAS(dspi->cs) \|
	268	SPI_PUSHR_CONT;
	269
	270	dspi->len--;
	271	}
	272
	273	if (dspi->len == 0 \|\| tx_count == DSPI_FIFO_SIZE - 1) {
	274	/* last transfer in the transfer */
	275	dspi_pushr \|= SPI_PUSHR_EOQ;
9298bc72 CF	276	if ((dspi->cs_change) && (!dspi->len))
9298bc72 CF	277	dspi_pushr &= ~SPI_PUSHR_CONT;
349ad66c CF	278	} else if (tx_word && (dspi->len == 1))
	279	dspi_pushr \|= SPI_PUSHR_EOQ;
	280
	281	if (first) {
	282	first = 0;
	283	dspi_pushr \|= SPI_PUSHR_CTCNT; /* clear counter */
	284	}
	285
1acbdeb9 CF	286	regmap_write(dspi->regmap, SPI_PUSHR, dspi_pushr);
1acbdeb9 CF	287
349ad66c CF	288	tx_count++;
	289	}
	290
	291	return tx_count * (tx_word + 1);
	292	}
	293
	294	static int dspi_transfer_read(struct fsl_dspi *dspi)
	295	{
	296	int rx_count = 0;
	297	int rx_word = is_double_byte_mode(dspi);
	298	u16 d;
9298bc72	299
349ad66c CF	300	while ((dspi->rx < dspi->rx_end)
	301	&& (rx_count < DSPI_FIFO_SIZE)) {
	302	if (rx_word) {
1acbdeb9 CF	303	unsigned int val;
1acbdeb9 CF	304
349ad66c CF	305	if ((dspi->rx_end - dspi->rx) == 1)
	306	break;
	307
1acbdeb9 CF	308	regmap_read(dspi->regmap, SPI_POPR, &val);
1acbdeb9 CF	309	d = SPI_POPR_RXDATA(val);
349ad66c CF	310
	311	if (!(dspi->dataflags & TRAN_STATE_RX_VOID))
	312	(u16 )dspi->rx = d;
	313	dspi->rx += 2;
	314
	315	} else {
1acbdeb9 CF	316	unsigned int val;
	317
	318	regmap_read(dspi->regmap, SPI_POPR, &val);
	319	d = SPI_POPR_RXDATA(val);
349ad66c CF	320	if (!(dspi->dataflags & TRAN_STATE_RX_VOID))
	321	(u8 )dspi->rx = d;
	322	dspi->rx++;
	323	}
	324	rx_count++;
	325	}
	326
	327	return rx_count;
	328	}
	329
9298bc72 CF	330	static int dspi_transfer_one_message(struct spi_master *master,
9298bc72 CF	331	struct spi_message *message)
349ad66c	332	{
9298bc72 CF	333	struct fsl_dspi *dspi = spi_master_get_devdata(master);
	334	struct spi_device *spi = message->spi;
	335	struct spi_transfer *transfer;
	336	int status = 0;
	337	message->actual_length = 0;
	338
	339	list_for_each_entry(transfer, &message->transfers, transfer_list) {
	340	dspi->cur_transfer = transfer;
	341	dspi->cur_msg = message;
	342	dspi->cur_chip = spi_get_ctldata(spi);
	343	dspi->cs = spi->chip_select;
	344	if (dspi->cur_transfer->transfer_list.next
	345	== &dspi->cur_msg->transfers)
	346	transfer->cs_change = 1;
	347	dspi->cs_change = transfer->cs_change;
	348	dspi->void_write_data = dspi->cur_chip->void_write_data;
	349
	350	dspi->dataflags = 0;
	351	dspi->tx = (void *)transfer->tx_buf;
	352	dspi->tx_end = dspi->tx + transfer->len;
	353	dspi->rx = transfer->rx_buf;
	354	dspi->rx_end = dspi->rx + transfer->len;
	355	dspi->len = transfer->len;
	356
	357	if (!dspi->rx)
	358	dspi->dataflags \|= TRAN_STATE_RX_VOID;
	359
	360	if (!dspi->tx)
	361	dspi->dataflags \|= TRAN_STATE_TX_VOID;
	362
	363	regmap_write(dspi->regmap, SPI_MCR, dspi->cur_chip->mcr_val);
	364	regmap_update_bits(dspi->regmap, SPI_MCR,
	365	SPI_MCR_CLR_TXF \| SPI_MCR_CLR_RXF,
	366	SPI_MCR_CLR_TXF \| SPI_MCR_CLR_RXF);
1acbdeb9 CF	367	regmap_write(dspi->regmap, SPI_CTAR(dspi->cs),
1acbdeb9 CF	368	dspi->cur_chip->ctar_val);
9298bc72 CF	369	if (transfer->speed_hz)
	370	regmap_write(dspi->regmap, SPI_CTAR(dspi->cs),
	371	dspi->cur_chip->ctar_val);
349ad66c	372
9298bc72 CF	373	regmap_write(dspi->regmap, SPI_RSER, SPI_RSER_EOQFE);
9298bc72 CF	374	message->actual_length += dspi_transfer_write(dspi);
1acbdeb9	375
9298bc72 CF	376	if (wait_event_interruptible(dspi->waitq, dspi->waitflags))
	377	dev_err(&dspi->pdev->dev, "wait transfer complete fail!\n");
	378	dspi->waitflags = 0;
349ad66c	379
9298bc72 CF	380	if (transfer->delay_usecs)
9298bc72 CF	381	udelay(transfer->delay_usecs);
349ad66c CF	382	}
349ad66c CF	383
9298bc72 CF	384	message->status = status;
	385	spi_finalize_current_message(master);
	386
	387	return status;
349ad66c CF	388	}
349ad66c CF	389
9298bc72	390	static int dspi_setup(struct spi_device *spi)
349ad66c CF	391	{
	392	struct chip_data *chip;
	393	struct fsl_dspi *dspi = spi_master_get_devdata(spi->master);
95bf15f3 AB	394	u32 cs_sck_delay = 0, sck_cs_delay = 0;
	395	unsigned char br = 0, pbr = 0, pcssck = 0, cssck = 0;
	396	unsigned char pasc = 0, asc = 0, fmsz = 0;
	397	unsigned long clkrate;
349ad66c	398
ceadfd8d BD	399	if ((spi->bits_per_word >= 4) && (spi->bits_per_word <= 16)) {
	400	fmsz = spi->bits_per_word - 1;
	401	} else {
	402	pr_err("Invalid wordsize\n");
	403	return -ENODEV;
	404	}
	405
349ad66c CF	406	/* Only alloc on first setup */
	407	chip = spi_get_ctldata(spi);
	408	if (chip == NULL) {
973fbce6	409	chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
349ad66c CF	410	if (!chip)
	411	return -ENOMEM;
	412	}
	413
95bf15f3 AB	414	of_property_read_u32(spi->dev.of_node, "fsl,spi-cs-sck-delay",
	415	&cs_sck_delay);
	416
	417	of_property_read_u32(spi->dev.of_node, "fsl,spi-sck-cs-delay",
	418	&sck_cs_delay);
	419
349ad66c CF	420	chip->mcr_val = SPI_MCR_MASTER \| SPI_MCR_PCSIS \|
349ad66c CF	421	SPI_MCR_CLR_TXF \| SPI_MCR_CLR_RXF;
349ad66c CF	422
	423	chip->void_write_data = 0;
	424
95bf15f3 AB	425	clkrate = clk_get_rate(dspi->clk);
	426	hz_to_spi_baud(&pbr, &br, spi->max_speed_hz, clkrate);
	427
	428	/* Set PCS to SCK delay scale values */
	429	ns_delay_scale(&pcssck, &cssck, cs_sck_delay, clkrate);
	430
	431	/* Set After SCK delay scale values */
	432	ns_delay_scale(&pasc, &asc, sck_cs_delay, clkrate);
349ad66c CF	433
	434	chip->ctar_val = SPI_CTAR_FMSZ(fmsz)
	435	\| SPI_CTAR_CPOL(spi->mode & SPI_CPOL ? 1 : 0)
	436	\| SPI_CTAR_CPHA(spi->mode & SPI_CPHA ? 1 : 0)
	437	\| SPI_CTAR_LSBFE(spi->mode & SPI_LSB_FIRST ? 1 : 0)
95bf15f3 AB	438	\| SPI_CTAR_PCSSCK(pcssck)
	439	\| SPI_CTAR_CSSCK(cssck)
	440	\| SPI_CTAR_PASC(pasc)
	441	\| SPI_CTAR_ASC(asc)
349ad66c CF	442	\| SPI_CTAR_PBR(pbr)
	443	\| SPI_CTAR_BR(br);
	444
	445	spi_set_ctldata(spi, chip);
	446
	447	return 0;
	448	}
	449
973fbce6 BD	450	static void dspi_cleanup(struct spi_device *spi)
	451	{
	452	struct chip_data chip = spi_get_ctldata((struct spi_device )spi);
	453
	454	dev_dbg(&spi->dev, "spi_device %u.%u cleanup\n",
	455	spi->master->bus_num, spi->chip_select);
	456
	457	kfree(chip);
	458	}
	459
349ad66c CF	460	static irqreturn_t dspi_interrupt(int irq, void *dev_id)
	461	{
	462	struct fsl_dspi dspi = (struct fsl_dspi )dev_id;
	463
9298bc72	464	struct spi_message *msg = dspi->cur_msg;
349ad66c	465
9298bc72	466	regmap_write(dspi->regmap, SPI_SR, SPI_SR_EOQF);
349ad66c CF	467	dspi_transfer_read(dspi);
	468
	469	if (!dspi->len) {
	470	if (dspi->dataflags & TRAN_STATE_WORD_ODD_NUM)
1acbdeb9	471	regmap_update_bits(dspi->regmap, SPI_CTAR(dspi->cs),
9298bc72	472	SPI_FRAME_BITS_MASK, SPI_FRAME_BITS(16));
1acbdeb9	473
349ad66c CF	474	dspi->waitflags = 1;
349ad66c CF	475	wake_up_interruptible(&dspi->waitq);
9298bc72 CF	476	} else
9298bc72 CF	477	msg->actual_length += dspi_transfer_write(dspi);
349ad66c CF	478
	479	return IRQ_HANDLED;
	480	}
	481
790d1902	482	static const struct of_device_id fsl_dspi_dt_ids[] = {
349ad66c CF	483	{ .compatible = "fsl,vf610-dspi", .data = NULL, },
	484	{ /* sentinel */ }
	485	};
	486	MODULE_DEVICE_TABLE(of, fsl_dspi_dt_ids);
	487
	488	#ifdef CONFIG_PM_SLEEP
	489	static int dspi_suspend(struct device *dev)
	490	{
	491	struct spi_master *master = dev_get_drvdata(dev);
	492	struct fsl_dspi *dspi = spi_master_get_devdata(master);
	493
	494	spi_master_suspend(master);
	495	clk_disable_unprepare(dspi->clk);
	496
	497	return 0;
	498	}
	499
	500	static int dspi_resume(struct device *dev)
	501	{
349ad66c CF	502	struct spi_master *master = dev_get_drvdata(dev);
	503	struct fsl_dspi *dspi = spi_master_get_devdata(master);
	504
	505	clk_prepare_enable(dspi->clk);
	506	spi_master_resume(master);
	507
	508	return 0;
	509	}
	510	#endif /* CONFIG_PM_SLEEP */
	511
ba811add	512	static SIMPLE_DEV_PM_OPS(dspi_pm, dspi_suspend, dspi_resume);
349ad66c	513
409851c3	514	static const struct regmap_config dspi_regmap_config = {
1acbdeb9 CF	515	.reg_bits = 32,
	516	.val_bits = 32,
	517	.reg_stride = 4,
	518	.max_register = 0x88,
349ad66c CF	519	};
	520
	521	static int dspi_probe(struct platform_device *pdev)
	522	{
	523	struct device_node *np = pdev->dev.of_node;
	524	struct spi_master *master;
	525	struct fsl_dspi *dspi;
	526	struct resource *res;
1acbdeb9	527	void __iomem *base;
349ad66c CF	528	int ret = 0, cs_num, bus_num;
	529
	530	master = spi_alloc_master(&pdev->dev, sizeof(struct fsl_dspi));
	531	if (!master)
	532	return -ENOMEM;
	533
	534	dspi = spi_master_get_devdata(master);
	535	dspi->pdev = pdev;
9298bc72 CF	536	dspi->master = master;
	537
	538	master->transfer = NULL;
	539	master->setup = dspi_setup;
	540	master->transfer_one_message = dspi_transfer_one_message;
	541	master->dev.of_node = pdev->dev.of_node;
349ad66c	542
973fbce6	543	master->cleanup = dspi_cleanup;
349ad66c CF	544	master->mode_bits = SPI_CPOL \| SPI_CPHA;
	545	master->bits_per_word_mask = SPI_BPW_MASK(4) \| SPI_BPW_MASK(8) \|
	546	SPI_BPW_MASK(16);
	547
	548	ret = of_property_read_u32(np, "spi-num-chipselects", &cs_num);
	549	if (ret < 0) {
	550	dev_err(&pdev->dev, "can't get spi-num-chipselects\n");
	551	goto out_master_put;
	552	}
	553	master->num_chipselect = cs_num;
	554
	555	ret = of_property_read_u32(np, "bus-num", &bus_num);
	556	if (ret < 0) {
	557	dev_err(&pdev->dev, "can't get bus-num\n");
	558	goto out_master_put;
	559	}
	560	master->bus_num = bus_num;
	561
	562	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1acbdeb9 CF	563	base = devm_ioremap_resource(&pdev->dev, res);
	564	if (IS_ERR(base)) {
	565	ret = PTR_ERR(base);
349ad66c CF	566	goto out_master_put;
	567	}
	568
1acbdeb9 CF	569	dspi->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "dspi", base,
	570	&dspi_regmap_config);
	571	if (IS_ERR(dspi->regmap)) {
	572	dev_err(&pdev->dev, "failed to init regmap: %ld\n",
	573	PTR_ERR(dspi->regmap));
	574	return PTR_ERR(dspi->regmap);
	575	}
	576
349ad66c CF	577	dspi->irq = platform_get_irq(pdev, 0);
	578	if (dspi->irq < 0) {
	579	dev_err(&pdev->dev, "can't get platform irq\n");
	580	ret = dspi->irq;
	581	goto out_master_put;
	582	}
	583
	584	ret = devm_request_irq(&pdev->dev, dspi->irq, dspi_interrupt, 0,
	585	pdev->name, dspi);
	586	if (ret < 0) {
	587	dev_err(&pdev->dev, "Unable to attach DSPI interrupt\n");
	588	goto out_master_put;
	589	}
	590
	591	dspi->clk = devm_clk_get(&pdev->dev, "dspi");
	592	if (IS_ERR(dspi->clk)) {
	593	ret = PTR_ERR(dspi->clk);
	594	dev_err(&pdev->dev, "unable to get clock\n");
	595	goto out_master_put;
	596	}
	597	clk_prepare_enable(dspi->clk);
	598
	599	init_waitqueue_head(&dspi->waitq);
017145fe	600	platform_set_drvdata(pdev, master);
349ad66c	601
9298bc72	602	ret = spi_register_master(master);
349ad66c CF	603	if (ret != 0) {
	604	dev_err(&pdev->dev, "Problem registering DSPI master\n");
	605	goto out_clk_put;
	606	}
	607
349ad66c CF	608	return ret;
	609
	610	out_clk_put:
	611	clk_disable_unprepare(dspi->clk);
	612	out_master_put:
	613	spi_master_put(master);
349ad66c CF	614
	615	return ret;
	616	}
	617
	618	static int dspi_remove(struct platform_device *pdev)
	619	{
017145fe AL	620	struct spi_master *master = platform_get_drvdata(pdev);
017145fe AL	621	struct fsl_dspi *dspi = spi_master_get_devdata(master);
349ad66c CF	622
349ad66c CF	623	/* Disconnect from the SPI framework */
05209f45	624	clk_disable_unprepare(dspi->clk);
9298bc72 CF	625	spi_unregister_master(dspi->master);
9298bc72 CF	626	spi_master_put(dspi->master);
349ad66c CF	627
	628	return 0;
	629	}
	630
	631	static struct platform_driver fsl_dspi_driver = {
	632	.driver.name = DRIVER_NAME,
	633	.driver.of_match_table = fsl_dspi_dt_ids,
	634	.driver.owner = THIS_MODULE,
	635	.driver.pm = &dspi_pm,
	636	.probe = dspi_probe,
	637	.remove = dspi_remove,
	638	};
	639	module_platform_driver(fsl_dspi_driver);
	640
	641	MODULE_DESCRIPTION("Freescale DSPI Controller Driver");
b444d1df	642	MODULE_LICENSE("GPL");
349ad66c	643	MODULE_ALIAS("platform:" DRIVER_NAME);