[linux-2.6-block.git] / drivers / spi / spi-bcm63xx.c

/*
 * Broadcom BCM63xx SPI controller support
 *
 * Copyright (C) 2009-2012 Florian Fainelli <florian@openwrt.org>
 * Copyright (C) 2010 Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com>
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/kernel.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/spi/spi.h>
#include <linux/completion.h>
#include <linux/err.h>
#include <linux/pm_runtime.h>

/* BCM 6338/6348 SPI core */
#define SPI_6348_RSET_SIZE		64
#define SPI_6348_CMD			0x00	/* 16-bits register */
#define SPI_6348_INT_STATUS		0x02
#define SPI_6348_INT_MASK_ST		0x03
#define SPI_6348_INT_MASK		0x04
#define SPI_6348_ST			0x05
#define SPI_6348_CLK_CFG		0x06
#define SPI_6348_FILL_BYTE		0x07
#define SPI_6348_MSG_TAIL		0x09
#define SPI_6348_RX_TAIL		0x0b
#define SPI_6348_MSG_CTL		0x40	/* 8-bits register */
#define SPI_6348_MSG_CTL_WIDTH		8
#define SPI_6348_MSG_DATA		0x41
#define SPI_6348_MSG_DATA_SIZE		0x3f
#define SPI_6348_RX_DATA		0x80
#define SPI_6348_RX_DATA_SIZE		0x3f

/* BCM 3368/6358/6262/6368 SPI core */
#define SPI_6358_RSET_SIZE		1804
#define SPI_6358_MSG_CTL		0x00	/* 16-bits register */
#define SPI_6358_MSG_CTL_WIDTH		16
#define SPI_6358_MSG_DATA		0x02
#define SPI_6358_MSG_DATA_SIZE		0x21e
#define SPI_6358_RX_DATA		0x400
#define SPI_6358_RX_DATA_SIZE		0x220
#define SPI_6358_CMD			0x700	/* 16-bits register */
#define SPI_6358_INT_STATUS		0x702
#define SPI_6358_INT_MASK_ST		0x703
#define SPI_6358_INT_MASK		0x704
#define SPI_6358_ST			0x705
#define SPI_6358_CLK_CFG		0x706
#define SPI_6358_FILL_BYTE		0x707
#define SPI_6358_MSG_TAIL		0x709
#define SPI_6358_RX_TAIL		0x70B

/* Shared SPI definitions */

/* Message configuration */
#define SPI_FD_RW			0x00
#define SPI_HD_W			0x01
#define SPI_HD_R			0x02
#define SPI_BYTE_CNT_SHIFT		0
#define SPI_6348_MSG_TYPE_SHIFT		6
#define SPI_6358_MSG_TYPE_SHIFT		14

/* Command */
#define SPI_CMD_NOOP			0x00
#define SPI_CMD_SOFT_RESET		0x01
#define SPI_CMD_HARD_RESET		0x02
#define SPI_CMD_START_IMMEDIATE		0x03
#define SPI_CMD_COMMAND_SHIFT		0
#define SPI_CMD_COMMAND_MASK		0x000f
#define SPI_CMD_DEVICE_ID_SHIFT		4
#define SPI_CMD_PREPEND_BYTE_CNT_SHIFT	8
#define SPI_CMD_ONE_BYTE_SHIFT		11
#define SPI_CMD_ONE_WIRE_SHIFT		12
#define SPI_DEV_ID_0			0
#define SPI_DEV_ID_1			1
#define SPI_DEV_ID_2			2
#define SPI_DEV_ID_3			3

/* Interrupt mask */
#define SPI_INTR_CMD_DONE		0x01
#define SPI_INTR_RX_OVERFLOW		0x02
#define SPI_INTR_TX_UNDERFLOW		0x04
#define SPI_INTR_TX_OVERFLOW		0x08
#define SPI_INTR_RX_UNDERFLOW		0x10
#define SPI_INTR_CLEAR_ALL		0x1f

/* Status */
#define SPI_RX_EMPTY			0x02
#define SPI_CMD_BUSY			0x04
#define SPI_SERIAL_BUSY			0x08

/* Clock configuration */
#define SPI_CLK_20MHZ			0x00
#define SPI_CLK_0_391MHZ		0x01
#define SPI_CLK_0_781MHZ		0x02	/* default */
#define SPI_CLK_1_563MHZ		0x03
#define SPI_CLK_3_125MHZ		0x04
#define SPI_CLK_6_250MHZ		0x05
#define SPI_CLK_12_50MHZ		0x06
#define SPI_CLK_MASK			0x07
#define SPI_SSOFFTIME_MASK		0x38
#define SPI_SSOFFTIME_SHIFT		3
#define SPI_BYTE_SWAP			0x80

enum bcm63xx_regs_spi {
	SPI_CMD,
	SPI_INT_STATUS,
	SPI_INT_MASK_ST,
	SPI_INT_MASK,
	SPI_ST,
	SPI_CLK_CFG,
	SPI_FILL_BYTE,
	SPI_MSG_TAIL,
	SPI_RX_TAIL,
	SPI_MSG_CTL,
	SPI_MSG_DATA,
	SPI_RX_DATA,
	SPI_MSG_TYPE_SHIFT,
	SPI_MSG_CTL_WIDTH,
	SPI_MSG_DATA_SIZE,
};

#define BCM63XX_SPI_MAX_PREPEND		15

#define BCM63XX_SPI_MAX_CS		8
#define BCM63XX_SPI_BUS_NUM		0

struct bcm63xx_spi {
	struct completion	done;

	void __iomem		*regs;
	int			irq;

	/* Platform data */
	const unsigned long	*reg_offsets;
	unsigned		fifo_size;
	unsigned int		msg_type_shift;
	unsigned int		msg_ctl_width;

	/* data iomem */
	u8 __iomem		*tx_io;
	const u8 __iomem	*rx_io;

	struct clk		*clk;
	struct platform_device	*pdev;
};

static inline u8 bcm_spi_readb(struct bcm63xx_spi *bs,
			       unsigned int offset)
{
	return readb(bs->regs + bs->reg_offsets[offset]);
}

static inline u16 bcm_spi_readw(struct bcm63xx_spi *bs,
				unsigned int offset)
{
#ifdef CONFIG_CPU_BIG_ENDIAN
	return ioread16be(bs->regs + bs->reg_offsets[offset]);
#else
	return readw(bs->regs + bs->reg_offsets[offset]);
#endif
}

static inline void bcm_spi_writeb(struct bcm63xx_spi *bs,
				  u8 value, unsigned int offset)
{
	writeb(value, bs->regs + bs->reg_offsets[offset]);
}

static inline void bcm_spi_writew(struct bcm63xx_spi *bs,
				  u16 value, unsigned int offset)
{
#ifdef CONFIG_CPU_BIG_ENDIAN
	iowrite16be(value, bs->regs + bs->reg_offsets[offset]);
#else
	writew(value, bs->regs + bs->reg_offsets[offset]);
#endif
}

static const unsigned bcm63xx_spi_freq_table[SPI_CLK_MASK][2] = {
	{ 20000000, SPI_CLK_20MHZ },
	{ 12500000, SPI_CLK_12_50MHZ },
	{  6250000, SPI_CLK_6_250MHZ },
	{  3125000, SPI_CLK_3_125MHZ },
	{  1563000, SPI_CLK_1_563MHZ },
	{   781000, SPI_CLK_0_781MHZ },
	{   391000, SPI_CLK_0_391MHZ }
};

static void bcm63xx_spi_setup_transfer(struct spi_device *spi,
				      struct spi_transfer *t)
{
	struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);
	u8 clk_cfg, reg;
	int i;

	/* Default to lowest clock configuration */
	clk_cfg = SPI_CLK_0_391MHZ;

	/* Find the closest clock configuration */
	for (i = 0; i < SPI_CLK_MASK; i++) {
		if (t->speed_hz >= bcm63xx_spi_freq_table[i][0]) {
			clk_cfg = bcm63xx_spi_freq_table[i][1];
			break;
		}
	}

	/* clear existing clock configuration bits of the register */
	reg = bcm_spi_readb(bs, SPI_CLK_CFG);
	reg &= ~SPI_CLK_MASK;
	reg |= clk_cfg;

	bcm_spi_writeb(bs, reg, SPI_CLK_CFG);
	dev_dbg(&spi->dev, "Setting clock register to %02x (hz %d)\n",
		clk_cfg, t->speed_hz);
}

/* the spi->mode bits understood by this driver: */
#define MODEBITS (SPI_CPOL | SPI_CPHA)

static int bcm63xx_txrx_bufs(struct spi_device *spi, struct spi_transfer *first,
				unsigned int num_transfers)
{
	struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);
	u16 msg_ctl;
	u16 cmd;
	unsigned int i, timeout = 0, prepend_len = 0, len = 0;
	struct spi_transfer *t = first;
	bool do_rx = false;
	bool do_tx = false;

	/* Disable the CMD_DONE interrupt */
	bcm_spi_writeb(bs, 0, SPI_INT_MASK);

	dev_dbg(&spi->dev, "txrx: tx %p, rx %p, len %d\n",
		t->tx_buf, t->rx_buf, t->len);

	if (num_transfers > 1 && t->tx_buf && t->len <= BCM63XX_SPI_MAX_PREPEND)
		prepend_len = t->len;

	/* prepare the buffer */
	for (i = 0; i < num_transfers; i++) {
		if (t->tx_buf) {
			do_tx = true;
			memcpy_toio(bs->tx_io + len, t->tx_buf, t->len);

			/* don't prepend more than one tx */
			if (t != first)
				prepend_len = 0;
		}

		if (t->rx_buf) {
			do_rx = true;
			/* prepend is half-duplex write only */
			if (t == first)
				prepend_len = 0;
		}

		len += t->len;

		t = list_entry(t->transfer_list.next, struct spi_transfer,
			       transfer_list);
	}

	reinit_completion(&bs->done);

	/* Fill in the Message control register */
	msg_ctl = (len << SPI_BYTE_CNT_SHIFT);

	if (do_rx && do_tx && prepend_len == 0)
		msg_ctl |= (SPI_FD_RW << bs->msg_type_shift);
	else if (do_rx)
		msg_ctl |= (SPI_HD_R << bs->msg_type_shift);
	else if (do_tx)
		msg_ctl |= (SPI_HD_W << bs->msg_type_shift);

	switch (bs->msg_ctl_width) {
	case 8:
		bcm_spi_writeb(bs, msg_ctl, SPI_MSG_CTL);
		break;
	case 16:
		bcm_spi_writew(bs, msg_ctl, SPI_MSG_CTL);
		break;
	}

	/* Issue the transfer */
	cmd = SPI_CMD_START_IMMEDIATE;
	cmd |= (prepend_len << SPI_CMD_PREPEND_BYTE_CNT_SHIFT);
	cmd |= (spi->chip_select << SPI_CMD_DEVICE_ID_SHIFT);
	bcm_spi_writew(bs, cmd, SPI_CMD);

	/* Enable the CMD_DONE interrupt */
	bcm_spi_writeb(bs, SPI_INTR_CMD_DONE, SPI_INT_MASK);

	timeout = wait_for_completion_timeout(&bs->done, HZ);
	if (!timeout)
		return -ETIMEDOUT;

	if (!do_rx)
		return 0;

	len = 0;
	t = first;
	/* Read out all the data */
	for (i = 0; i < num_transfers; i++) {
		if (t->rx_buf)
			memcpy_fromio(t->rx_buf, bs->rx_io + len, t->len);

		if (t != first || prepend_len == 0)
			len += t->len;

		t = list_entry(t->transfer_list.next, struct spi_transfer,
			       transfer_list);
	}

	return 0;
}

static int bcm63xx_spi_transfer_one(struct spi_master *master,
					struct spi_message *m)
{
	struct bcm63xx_spi *bs = spi_master_get_devdata(master);
	struct spi_transfer *t, *first = NULL;
	struct spi_device *spi = m->spi;
	int status = 0;
	unsigned int n_transfers = 0, total_len = 0;
	bool can_use_prepend = false;

	/*
	 * This SPI controller does not support keeping CS active after a
	 * transfer.
	 * Work around this by merging as many transfers we can into one big
	 * full-duplex transfers.
	 */
	list_for_each_entry(t, &m->transfers, transfer_list) {
		if (!first)
			first = t;

		n_transfers++;
		total_len += t->len;

		if (n_transfers == 2 && !first->rx_buf && !t->tx_buf &&
		    first->len <= BCM63XX_SPI_MAX_PREPEND)
			can_use_prepend = true;
		else if (can_use_prepend && t->tx_buf)
			can_use_prepend = false;

		/* we can only transfer one fifo worth of data */
		if ((can_use_prepend &&
		     total_len > (bs->fifo_size + BCM63XX_SPI_MAX_PREPEND)) ||
		    (!can_use_prepend && total_len > bs->fifo_size)) {
			dev_err(&spi->dev, "unable to do transfers larger than FIFO size (%i > %i)\n",
				total_len, bs->fifo_size);
			status = -EINVAL;
			goto exit;
		}

		/* all combined transfers have to have the same speed */
		if (t->speed_hz != first->speed_hz) {
			dev_err(&spi->dev, "unable to change speed between transfers\n");
			status = -EINVAL;
			goto exit;
		}

		/* CS will be deasserted directly after transfer */
		if (t->delay_usecs) {
			dev_err(&spi->dev, "unable to keep CS asserted after transfer\n");
			status = -EINVAL;
			goto exit;
		}

		if (t->cs_change ||
		    list_is_last(&t->transfer_list, &m->transfers)) {
			/* configure adapter for a new transfer */
			bcm63xx_spi_setup_transfer(spi, first);

			/* send the data */
			status = bcm63xx_txrx_bufs(spi, first, n_transfers);
			if (status)
				goto exit;

			m->actual_length += total_len;

			first = NULL;
			n_transfers = 0;
			total_len = 0;
			can_use_prepend = false;
		}
	}
exit:
	m->status = status;
	spi_finalize_current_message(master);

	return 0;
}

/* This driver supports single master mode only. Hence
 * CMD_DONE is the only interrupt we care about
 */
static irqreturn_t bcm63xx_spi_interrupt(int irq, void *dev_id)
{
	struct spi_master *master = (struct spi_master *)dev_id;
	struct bcm63xx_spi *bs = spi_master_get_devdata(master);
	u8 intr;

	/* Read interupts and clear them immediately */
	intr = bcm_spi_readb(bs, SPI_INT_STATUS);
	bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS);
	bcm_spi_writeb(bs, 0, SPI_INT_MASK);

	/* A transfer completed */
	if (intr & SPI_INTR_CMD_DONE)
		complete(&bs->done);

	return IRQ_HANDLED;
}

static const unsigned long bcm6348_spi_reg_offsets[] = {
	[SPI_CMD]		= SPI_6348_CMD,
	[SPI_INT_STATUS]	= SPI_6348_INT_STATUS,
	[SPI_INT_MASK_ST]	= SPI_6348_INT_MASK_ST,
	[SPI_INT_MASK]		= SPI_6348_INT_MASK,
	[SPI_ST]		= SPI_6348_ST,
	[SPI_CLK_CFG]		= SPI_6348_CLK_CFG,
	[SPI_FILL_BYTE]		= SPI_6348_FILL_BYTE,
	[SPI_MSG_TAIL]		= SPI_6348_MSG_TAIL,
	[SPI_RX_TAIL]		= SPI_6348_RX_TAIL,
	[SPI_MSG_CTL]		= SPI_6348_MSG_CTL,
	[SPI_MSG_DATA]		= SPI_6348_MSG_DATA,
	[SPI_RX_DATA]		= SPI_6348_RX_DATA,
	[SPI_MSG_TYPE_SHIFT]	= SPI_6348_MSG_TYPE_SHIFT,
	[SPI_MSG_CTL_WIDTH]	= SPI_6348_MSG_CTL_WIDTH,
	[SPI_MSG_DATA_SIZE]	= SPI_6348_MSG_DATA_SIZE,
};

static const unsigned long bcm6358_spi_reg_offsets[] = {
	[SPI_CMD]		= SPI_6358_CMD,
	[SPI_INT_STATUS]	= SPI_6358_INT_STATUS,
	[SPI_INT_MASK_ST]	= SPI_6358_INT_MASK_ST,
	[SPI_INT_MASK]		= SPI_6358_INT_MASK,
	[SPI_ST]		= SPI_6358_ST,
	[SPI_CLK_CFG]		= SPI_6358_CLK_CFG,
	[SPI_FILL_BYTE]		= SPI_6358_FILL_BYTE,
	[SPI_MSG_TAIL]		= SPI_6358_MSG_TAIL,
	[SPI_RX_TAIL]		= SPI_6358_RX_TAIL,
	[SPI_MSG_CTL]		= SPI_6358_MSG_CTL,
	[SPI_MSG_DATA]		= SPI_6358_MSG_DATA,
	[SPI_RX_DATA]		= SPI_6358_RX_DATA,
	[SPI_MSG_TYPE_SHIFT]	= SPI_6358_MSG_TYPE_SHIFT,
	[SPI_MSG_CTL_WIDTH]	= SPI_6358_MSG_CTL_WIDTH,
	[SPI_MSG_DATA_SIZE]	= SPI_6358_MSG_DATA_SIZE,
};

static const struct platform_device_id bcm63xx_spi_dev_match[] = {
	{
		.name = "bcm6348-spi",
		.driver_data = (unsigned long)bcm6348_spi_reg_offsets,
	},
	{
		.name = "bcm6358-spi",
		.driver_data = (unsigned long)bcm6358_spi_reg_offsets,
	},
	{
	},
};

static int bcm63xx_spi_probe(struct platform_device *pdev)
{
	struct resource *r;
	const unsigned long *bcm63xx_spireg;
	struct device *dev = &pdev->dev;
	int irq;
	struct spi_master *master;
	struct clk *clk;
	struct bcm63xx_spi *bs;
	int ret;

	if (!pdev->id_entry->driver_data)
		return -EINVAL;

	bcm63xx_spireg = (const unsigned long *)pdev->id_entry->driver_data;

	irq = platform_get_irq(pdev, 0);
	if (irq < 0) {
		dev_err(dev, "no irq\n");
		return -ENXIO;
	}

	clk = devm_clk_get(dev, "spi");
	if (IS_ERR(clk)) {
		dev_err(dev, "no clock for device\n");
		return PTR_ERR(clk);
	}

	master = spi_alloc_master(dev, sizeof(*bs));
	if (!master) {
		dev_err(dev, "out of memory\n");
		return -ENOMEM;
	}

	bs = spi_master_get_devdata(master);
	init_completion(&bs->done);

	platform_set_drvdata(pdev, master);
	bs->pdev = pdev;

	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	bs->regs = devm_ioremap_resource(&pdev->dev, r);
	if (IS_ERR(bs->regs)) {
		ret = PTR_ERR(bs->regs);
		goto out_err;
	}

	bs->irq = irq;
	bs->clk = clk;
	bs->reg_offsets = bcm63xx_spireg;
	bs->fifo_size = bs->reg_offsets[SPI_MSG_DATA_SIZE];

	ret = devm_request_irq(&pdev->dev, irq, bcm63xx_spi_interrupt, 0,
							pdev->name, master);
	if (ret) {
		dev_err(dev, "unable to request irq\n");
		goto out_err;
	}

	master->bus_num = BCM63XX_SPI_BUS_NUM;
	master->num_chipselect = BCM63XX_SPI_MAX_CS;
	master->transfer_one_message = bcm63xx_spi_transfer_one;
	master->mode_bits = MODEBITS;
	master->bits_per_word_mask = SPI_BPW_MASK(8);
	master->auto_runtime_pm = true;
	bs->msg_type_shift = bs->reg_offsets[SPI_MSG_TYPE_SHIFT];
	bs->msg_ctl_width = bs->reg_offsets[SPI_MSG_CTL_WIDTH];
	bs->tx_io = (u8 *)(bs->regs + bs->reg_offsets[SPI_MSG_DATA]);
	bs->rx_io = (const u8 *)(bs->regs + bs->reg_offsets[SPI_RX_DATA]);

	/* Initialize hardware */
	ret = clk_prepare_enable(bs->clk);
	if (ret)
		goto out_err;

	bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS);

	/* register and we are done */
	ret = devm_spi_register_master(dev, master);
	if (ret) {
		dev_err(dev, "spi register failed\n");
		goto out_clk_disable;
	}

	dev_info(dev, "at %pr (irq %d, FIFOs size %d)\n",
		 r, irq, bs->fifo_size);

	return 0;

out_clk_disable:
	clk_disable_unprepare(clk);
out_err:
	spi_master_put(master);
	return ret;
}

static int bcm63xx_spi_remove(struct platform_device *pdev)
{
	struct spi_master *master = platform_get_drvdata(pdev);
	struct bcm63xx_spi *bs = spi_master_get_devdata(master);

	/* reset spi block */
	bcm_spi_writeb(bs, 0, SPI_INT_MASK);

	/* HW shutdown */
	clk_disable_unprepare(bs->clk);

	return 0;
}

#ifdef CONFIG_PM_SLEEP
static int bcm63xx_spi_suspend(struct device *dev)
{
	struct spi_master *master = dev_get_drvdata(dev);
	struct bcm63xx_spi *bs = spi_master_get_devdata(master);

	spi_master_suspend(master);

	clk_disable_unprepare(bs->clk);

	return 0;
}

static int bcm63xx_spi_resume(struct device *dev)
{
	struct spi_master *master = dev_get_drvdata(dev);
	struct bcm63xx_spi *bs = spi_master_get_devdata(master);
	int ret;

	ret = clk_prepare_enable(bs->clk);
	if (ret)
		return ret;

	spi_master_resume(master);

	return 0;
}
#endif

static const struct dev_pm_ops bcm63xx_spi_pm_ops = {
	SET_SYSTEM_SLEEP_PM_OPS(bcm63xx_spi_suspend, bcm63xx_spi_resume)
};

static struct platform_driver bcm63xx_spi_driver = {
	.driver = {
		.name	= "bcm63xx-spi",
		.pm	= &bcm63xx_spi_pm_ops,
	},
	.id_table	= bcm63xx_spi_dev_match,
	.probe		= bcm63xx_spi_probe,
	.remove		= bcm63xx_spi_remove,
};

module_platform_driver(bcm63xx_spi_driver);

MODULE_ALIAS("platform:bcm63xx_spi");
MODULE_AUTHOR("Florian Fainelli <florian@openwrt.org>");
MODULE_AUTHOR("Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com>");
MODULE_DESCRIPTION("Broadcom BCM63xx SPI Controller driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
b42dfed8 FF	1	/*
	2	* Broadcom BCM63xx SPI controller support
	3	*
cde4384e	4	* Copyright (C) 2009-2012 Florian Fainelli <florian@openwrt.org>
b42dfed8 FF	5	* Copyright (C) 2010 Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com>
	6	*
	7	* This program is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU General Public License
	9	* as published by the Free Software Foundation; either version 2
	10	* of the License, or (at your option) any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
b42dfed8 FF	16	*/
	17
	18	#include <linux/kernel.h>
b42dfed8 FF	19	#include <linux/clk.h>
	20	#include <linux/io.h>
	21	#include <linux/module.h>
	22	#include <linux/platform_device.h>
	23	#include <linux/delay.h>
	24	#include <linux/interrupt.h>
	25	#include <linux/spi/spi.h>
	26	#include <linux/completion.h>
	27	#include <linux/err.h>
cde4384e	28	#include <linux/pm_runtime.h>
b42dfed8	29
44d8fb30 JG	30	/* BCM 6338/6348 SPI core */
	31	#define SPI_6348_RSET_SIZE 64
	32	#define SPI_6348_CMD 0x00 /* 16-bits register */
	33	#define SPI_6348_INT_STATUS 0x02
	34	#define SPI_6348_INT_MASK_ST 0x03
	35	#define SPI_6348_INT_MASK 0x04
	36	#define SPI_6348_ST 0x05
	37	#define SPI_6348_CLK_CFG 0x06
	38	#define SPI_6348_FILL_BYTE 0x07
	39	#define SPI_6348_MSG_TAIL 0x09
	40	#define SPI_6348_RX_TAIL 0x0b
	41	#define SPI_6348_MSG_CTL 0x40 /* 8-bits register */
	42	#define SPI_6348_MSG_CTL_WIDTH 8
	43	#define SPI_6348_MSG_DATA 0x41
	44	#define SPI_6348_MSG_DATA_SIZE 0x3f
	45	#define SPI_6348_RX_DATA 0x80
	46	#define SPI_6348_RX_DATA_SIZE 0x3f
	47
	48	/* BCM 3368/6358/6262/6368 SPI core */
	49	#define SPI_6358_RSET_SIZE 1804
	50	#define SPI_6358_MSG_CTL 0x00 /* 16-bits register */
	51	#define SPI_6358_MSG_CTL_WIDTH 16
	52	#define SPI_6358_MSG_DATA 0x02
	53	#define SPI_6358_MSG_DATA_SIZE 0x21e
	54	#define SPI_6358_RX_DATA 0x400
	55	#define SPI_6358_RX_DATA_SIZE 0x220
	56	#define SPI_6358_CMD 0x700 /* 16-bits register */
	57	#define SPI_6358_INT_STATUS 0x702
	58	#define SPI_6358_INT_MASK_ST 0x703
	59	#define SPI_6358_INT_MASK 0x704
	60	#define SPI_6358_ST 0x705
	61	#define SPI_6358_CLK_CFG 0x706
	62	#define SPI_6358_FILL_BYTE 0x707
	63	#define SPI_6358_MSG_TAIL 0x709
	64	#define SPI_6358_RX_TAIL 0x70B
	65
	66	/* Shared SPI definitions */
	67
	68	/* Message configuration */
	69	#define SPI_FD_RW 0x00
	70	#define SPI_HD_W 0x01
	71	#define SPI_HD_R 0x02
	72	#define SPI_BYTE_CNT_SHIFT 0
	73	#define SPI_6348_MSG_TYPE_SHIFT 6
	74	#define SPI_6358_MSG_TYPE_SHIFT 14
	75
	76	/* Command */
	77	#define SPI_CMD_NOOP 0x00
	78	#define SPI_CMD_SOFT_RESET 0x01
	79	#define SPI_CMD_HARD_RESET 0x02
	80	#define SPI_CMD_START_IMMEDIATE 0x03
	81	#define SPI_CMD_COMMAND_SHIFT 0
	82	#define SPI_CMD_COMMAND_MASK 0x000f
	83	#define SPI_CMD_DEVICE_ID_SHIFT 4
	84	#define SPI_CMD_PREPEND_BYTE_CNT_SHIFT 8
	85	#define SPI_CMD_ONE_BYTE_SHIFT 11
	86	#define SPI_CMD_ONE_WIRE_SHIFT 12
	87	#define SPI_DEV_ID_0 0
	88	#define SPI_DEV_ID_1 1
	89	#define SPI_DEV_ID_2 2
	90	#define SPI_DEV_ID_3 3
	91
	92	/* Interrupt mask */
	93	#define SPI_INTR_CMD_DONE 0x01
94	#define SPI_INTR_RX_OVERFLOW 0x02
95	#define SPI_INTR_TX_UNDERFLOW 0x04
96	#define SPI_INTR_TX_OVERFLOW 0x08
97	#define SPI_INTR_RX_UNDERFLOW 0x10
98	#define SPI_INTR_CLEAR_ALL 0x1f
99
100	/* Status */
101	#define SPI_RX_EMPTY 0x02
102	#define SPI_CMD_BUSY 0x04
103	#define SPI_SERIAL_BUSY 0x08
104
105	/* Clock configuration */
106	#define SPI_CLK_20MHZ 0x00
107	#define SPI_CLK_0_391MHZ 0x01
108	#define SPI_CLK_0_781MHZ 0x02 /* default */
109	#define SPI_CLK_1_563MHZ 0x03
110	#define SPI_CLK_3_125MHZ 0x04
111	#define SPI_CLK_6_250MHZ 0x05
112	#define SPI_CLK_12_50MHZ 0x06
113	#define SPI_CLK_MASK 0x07
114	#define SPI_SSOFFTIME_MASK 0x38
115	#define SPI_SSOFFTIME_SHIFT 3
116	#define SPI_BYTE_SWAP 0x80
117
118	enum bcm63xx_regs_spi {
119	SPI_CMD,
120	SPI_INT_STATUS,
121	SPI_INT_MASK_ST,
122	SPI_INT_MASK,
123	SPI_ST,
124	SPI_CLK_CFG,
125	SPI_FILL_BYTE,
126	SPI_MSG_TAIL,
127	SPI_RX_TAIL,
128	SPI_MSG_CTL,
129	SPI_MSG_DATA,
130	SPI_RX_DATA,
131	SPI_MSG_TYPE_SHIFT,
132	SPI_MSG_CTL_WIDTH,
133	SPI_MSG_DATA_SIZE,
134	};
b42dfed8	135
b17de076 JG	136	#define BCM63XX_SPI_MAX_PREPEND 15
b17de076 JG	137
65059997	138	#define BCM63XX_SPI_MAX_CS 8
a45fcea5	139	#define BCM63XX_SPI_BUS_NUM 0
65059997	140
b42dfed8	141	struct bcm63xx_spi {
b42dfed8 FF	142	struct completion done;
	143
	144	void __iomem *regs;
	145	int irq;
	146
	147	/* Platform data */
44d8fb30	148	const unsigned long *reg_offsets;
b42dfed8	149	unsigned fifo_size;
5a670445 FF	150	unsigned int msg_type_shift;
5a670445 FF	151	unsigned int msg_ctl_width;
b42dfed8	152
b42dfed8 FF	153	/* data iomem */
	154	u8 __iomem *tx_io;
	155	const u8 __iomem *rx_io;
	156
b42dfed8 FF	157	struct clk *clk;
	158	struct platform_device *pdev;
	159	};
	160
	161	static inline u8 bcm_spi_readb(struct bcm63xx_spi *bs,
44d8fb30	162	unsigned int offset)
b42dfed8	163	{
44d8fb30	164	return readb(bs->regs + bs->reg_offsets[offset]);
b42dfed8 FF	165	}
	166
	167	static inline u16 bcm_spi_readw(struct bcm63xx_spi *bs,
	168	unsigned int offset)
	169	{
682b5280	170	#ifdef CONFIG_CPU_BIG_ENDIAN
44d8fb30	171	return ioread16be(bs->regs + bs->reg_offsets[offset]);
158fcc4e	172	#else
44d8fb30	173	return readw(bs->regs + bs->reg_offsets[offset]);
158fcc4e	174	#endif
b42dfed8 FF	175	}
	176
	177	static inline void bcm_spi_writeb(struct bcm63xx_spi *bs,
	178	u8 value, unsigned int offset)
	179	{
44d8fb30	180	writeb(value, bs->regs + bs->reg_offsets[offset]);
b42dfed8 FF	181	}
	182
	183	static inline void bcm_spi_writew(struct bcm63xx_spi *bs,
	184	u16 value, unsigned int offset)
	185	{
682b5280	186	#ifdef CONFIG_CPU_BIG_ENDIAN
44d8fb30	187	iowrite16be(value, bs->regs + bs->reg_offsets[offset]);
158fcc4e	188	#else
44d8fb30	189	writew(value, bs->regs + bs->reg_offsets[offset]);
158fcc4e	190	#endif
b42dfed8 FF	191	}
	192
	193	static const unsigned bcm63xx_spi_freq_table[SPI_CLK_MASK][2] = {
	194	{ 20000000, SPI_CLK_20MHZ },
	195	{ 12500000, SPI_CLK_12_50MHZ },
	196	{ 6250000, SPI_CLK_6_250MHZ },
	197	{ 3125000, SPI_CLK_3_125MHZ },
	198	{ 1563000, SPI_CLK_1_563MHZ },
	199	{ 781000, SPI_CLK_0_781MHZ },
	200	{ 391000, SPI_CLK_0_391MHZ }
	201	};
	202
cde4384e FF	203	static void bcm63xx_spi_setup_transfer(struct spi_device *spi,
	204	struct spi_transfer *t)
	205	{
	206	struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);
cde4384e FF	207	u8 clk_cfg, reg;
	208	int i;
	209
4dde99bd GU	210	/* Default to lowest clock configuration */
	211	clk_cfg = SPI_CLK_0_391MHZ;
	212
b42dfed8 FF	213	/* Find the closest clock configuration */
b42dfed8 FF	214	for (i = 0; i < SPI_CLK_MASK; i++) {
68792e2a	215	if (t->speed_hz >= bcm63xx_spi_freq_table[i][0]) {
b42dfed8 FF	216	clk_cfg = bcm63xx_spi_freq_table[i][1];
	217	break;
	218	}
	219	}
	220
b42dfed8 FF	221	/* clear existing clock configuration bits of the register */
	222	reg = bcm_spi_readb(bs, SPI_CLK_CFG);
	223	reg &= ~SPI_CLK_MASK;
	224	reg \|= clk_cfg;
	225
	226	bcm_spi_writeb(bs, reg, SPI_CLK_CFG);
	227	dev_dbg(&spi->dev, "Setting clock register to %02x (hz %d)\n",
68792e2a	228	clk_cfg, t->speed_hz);
b42dfed8 FF	229	}
	230
	231	/* the spi->mode bits understood by this driver: */
	232	#define MODEBITS (SPI_CPOL \| SPI_CPHA)
	233
b17de076 JG	234	static int bcm63xx_txrx_bufs(struct spi_device spi, struct spi_transfer first,
b17de076 JG	235	unsigned int num_transfers)
b42dfed8 FF	236	{
	237	struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);
	238	u16 msg_ctl;
	239	u16 cmd;
b17de076 JG	240	unsigned int i, timeout = 0, prepend_len = 0, len = 0;
	241	struct spi_transfer *t = first;
	242	bool do_rx = false;
	243	bool do_tx = false;
b42dfed8	244
cde4384e FF	245	/* Disable the CMD_DONE interrupt */
	246	bcm_spi_writeb(bs, 0, SPI_INT_MASK);
	247
b42dfed8 FF	248	dev_dbg(&spi->dev, "txrx: tx %p, rx %p, len %d\n",
	249	t->tx_buf, t->rx_buf, t->len);
	250
b17de076 JG	251	if (num_transfers > 1 && t->tx_buf && t->len <= BCM63XX_SPI_MAX_PREPEND)
	252	prepend_len = t->len;
	253
	254	/* prepare the buffer */
	255	for (i = 0; i < num_transfers; i++) {
	256	if (t->tx_buf) {
	257	do_tx = true;
	258	memcpy_toio(bs->tx_io + len, t->tx_buf, t->len);
	259
	260	/* don't prepend more than one tx */
	261	if (t != first)
	262	prepend_len = 0;
	263	}
	264
	265	if (t->rx_buf) {
	266	do_rx = true;
	267	/* prepend is half-duplex write only */
	268	if (t == first)
	269	prepend_len = 0;
	270	}
	271
	272	len += t->len;
	273
	274	t = list_entry(t->transfer_list.next, struct spi_transfer,
	275	transfer_list);
	276	}
	277
aa0fe826	278	reinit_completion(&bs->done);
b42dfed8 FF	279
b42dfed8 FF	280	/* Fill in the Message control register */
b17de076	281	msg_ctl = (len << SPI_BYTE_CNT_SHIFT);
b42dfed8	282
b17de076	283	if (do_rx && do_tx && prepend_len == 0)
5a670445	284	msg_ctl \|= (SPI_FD_RW << bs->msg_type_shift);
b17de076	285	else if (do_rx)
5a670445	286	msg_ctl \|= (SPI_HD_R << bs->msg_type_shift);
b17de076	287	else if (do_tx)
5a670445 FF	288	msg_ctl \|= (SPI_HD_W << bs->msg_type_shift);
	289
	290	switch (bs->msg_ctl_width) {
	291	case 8:
	292	bcm_spi_writeb(bs, msg_ctl, SPI_MSG_CTL);
	293	break;
	294	case 16:
	295	bcm_spi_writew(bs, msg_ctl, SPI_MSG_CTL);
	296	break;
	297	}
b42dfed8 FF	298
	299	/* Issue the transfer */
	300	cmd = SPI_CMD_START_IMMEDIATE;
b17de076	301	cmd \|= (prepend_len << SPI_CMD_PREPEND_BYTE_CNT_SHIFT);
b42dfed8 FF	302	cmd \|= (spi->chip_select << SPI_CMD_DEVICE_ID_SHIFT);
b42dfed8 FF	303	bcm_spi_writew(bs, cmd, SPI_CMD);
b42dfed8	304
cde4384e FF	305	/* Enable the CMD_DONE interrupt */
cde4384e FF	306	bcm_spi_writeb(bs, SPI_INTR_CMD_DONE, SPI_INT_MASK);
b42dfed8	307
c0fde3ba JG	308	timeout = wait_for_completion_timeout(&bs->done, HZ);
	309	if (!timeout)
	310	return -ETIMEDOUT;
	311
20e9e78f	312	if (!do_rx)
b17de076 JG	313	return 0;
	314
	315	len = 0;
	316	t = first;
c0fde3ba	317	/* Read out all the data */
b17de076 JG	318	for (i = 0; i < num_transfers; i++) {
	319	if (t->rx_buf)
	320	memcpy_fromio(t->rx_buf, bs->rx_io + len, t->len);
	321
	322	if (t != first \|\| prepend_len == 0)
	323	len += t->len;
	324
	325	t = list_entry(t->transfer_list.next, struct spi_transfer,
	326	transfer_list);
	327	}
c0fde3ba JG	328
c0fde3ba JG	329	return 0;
b42dfed8 FF	330	}
b42dfed8 FF	331
cde4384e FF	332	static int bcm63xx_spi_transfer_one(struct spi_master *master,
	333	struct spi_message *m)
	334	{
	335	struct bcm63xx_spi *bs = spi_master_get_devdata(master);
b17de076	336	struct spi_transfer t, first = NULL;
cde4384e FF	337	struct spi_device *spi = m->spi;
cde4384e FF	338	int status = 0;
b17de076 JG	339	unsigned int n_transfers = 0, total_len = 0;
	340	bool can_use_prepend = false;
	341
	342	/*
	343	* This SPI controller does not support keeping CS active after a
	344	* transfer.
	345	* Work around this by merging as many transfers we can into one big
	346	* full-duplex transfers.
	347	*/
b42dfed8	348	list_for_each_entry(t, &m->transfers, transfer_list) {
b17de076 JG	349	if (!first)
	350	first = t;
	351
	352	n_transfers++;
	353	total_len += t->len;
	354
	355	if (n_transfers == 2 && !first->rx_buf && !t->tx_buf &&
	356	first->len <= BCM63XX_SPI_MAX_PREPEND)
	357	can_use_prepend = true;
	358	else if (can_use_prepend && t->tx_buf)
	359	can_use_prepend = false;
	360
c0fde3ba	361	/* we can only transfer one fifo worth of data */
b17de076 JG	362	if ((can_use_prepend &&
	363	total_len > (bs->fifo_size + BCM63XX_SPI_MAX_PREPEND)) \|\|
	364	(!can_use_prepend && total_len > bs->fifo_size)) {
c0fde3ba	365	dev_err(&spi->dev, "unable to do transfers larger than FIFO size (%i > %i)\n",
b17de076	366	total_len, bs->fifo_size);
c0fde3ba JG	367	status = -EINVAL;
	368	goto exit;
	369	}
cde4384e	370
b17de076 JG	371	/* all combined transfers have to have the same speed */
	372	if (t->speed_hz != first->speed_hz) {
	373	dev_err(&spi->dev, "unable to change speed between transfers\n");
c0fde3ba JG	374	status = -EINVAL;
	375	goto exit;
	376	}
cde4384e	377
b17de076 JG	378	/* CS will be deasserted directly after transfer */
	379	if (t->delay_usecs) {
	380	dev_err(&spi->dev, "unable to keep CS asserted after transfer\n");
c0fde3ba JG	381	status = -EINVAL;
	382	goto exit;
	383	}
cde4384e	384
b17de076 JG	385	if (t->cs_change \|\|
	386	list_is_last(&t->transfer_list, &m->transfers)) {
	387	/* configure adapter for a new transfer */
	388	bcm63xx_spi_setup_transfer(spi, first);
cde4384e	389
b17de076 JG	390	/* send the data */
	391	status = bcm63xx_txrx_bufs(spi, first, n_transfers);
	392	if (status)
	393	goto exit;
	394
	395	m->actual_length += total_len;
b42dfed8	396
b17de076 JG	397	first = NULL;
	398	n_transfers = 0;
	399	total_len = 0;
	400	can_use_prepend = false;
	401	}
cde4384e FF	402	}
	403	exit:
	404	m->status = status;
	405	spi_finalize_current_message(master);
b42dfed8	406
cde4384e	407	return 0;
b42dfed8 FF	408	}
	409
	410	/* This driver supports single master mode only. Hence
	411	* CMD_DONE is the only interrupt we care about
	412	*/
	413	static irqreturn_t bcm63xx_spi_interrupt(int irq, void *dev_id)
	414	{
	415	struct spi_master master = (struct spi_master )dev_id;
	416	struct bcm63xx_spi *bs = spi_master_get_devdata(master);
	417	u8 intr;
b42dfed8 FF	418
	419	/* Read interupts and clear them immediately */
	420	intr = bcm_spi_readb(bs, SPI_INT_STATUS);
	421	bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS);
	422	bcm_spi_writeb(bs, 0, SPI_INT_MASK);
	423
cde4384e FF	424	/* A transfer completed */
	425	if (intr & SPI_INTR_CMD_DONE)
	426	complete(&bs->done);
b42dfed8 FF	427
	428	return IRQ_HANDLED;
	429	}
	430
44d8fb30 JG	431	static const unsigned long bcm6348_spi_reg_offsets[] = {
	432	[SPI_CMD] = SPI_6348_CMD,
	433	[SPI_INT_STATUS] = SPI_6348_INT_STATUS,
	434	[SPI_INT_MASK_ST] = SPI_6348_INT_MASK_ST,
	435	[SPI_INT_MASK] = SPI_6348_INT_MASK,
	436	[SPI_ST] = SPI_6348_ST,
	437	[SPI_CLK_CFG] = SPI_6348_CLK_CFG,
	438	[SPI_FILL_BYTE] = SPI_6348_FILL_BYTE,
	439	[SPI_MSG_TAIL] = SPI_6348_MSG_TAIL,
	440	[SPI_RX_TAIL] = SPI_6348_RX_TAIL,
	441	[SPI_MSG_CTL] = SPI_6348_MSG_CTL,
	442	[SPI_MSG_DATA] = SPI_6348_MSG_DATA,
	443	[SPI_RX_DATA] = SPI_6348_RX_DATA,
	444	[SPI_MSG_TYPE_SHIFT] = SPI_6348_MSG_TYPE_SHIFT,
	445	[SPI_MSG_CTL_WIDTH] = SPI_6348_MSG_CTL_WIDTH,
	446	[SPI_MSG_DATA_SIZE] = SPI_6348_MSG_DATA_SIZE,
	447	};
	448
	449	static const unsigned long bcm6358_spi_reg_offsets[] = {
	450	[SPI_CMD] = SPI_6358_CMD,
	451	[SPI_INT_STATUS] = SPI_6358_INT_STATUS,
	452	[SPI_INT_MASK_ST] = SPI_6358_INT_MASK_ST,
	453	[SPI_INT_MASK] = SPI_6358_INT_MASK,
	454	[SPI_ST] = SPI_6358_ST,
	455	[SPI_CLK_CFG] = SPI_6358_CLK_CFG,
	456	[SPI_FILL_BYTE] = SPI_6358_FILL_BYTE,
	457	[SPI_MSG_TAIL] = SPI_6358_MSG_TAIL,
	458	[SPI_RX_TAIL] = SPI_6358_RX_TAIL,
	459	[SPI_MSG_CTL] = SPI_6358_MSG_CTL,
	460	[SPI_MSG_DATA] = SPI_6358_MSG_DATA,
	461	[SPI_RX_DATA] = SPI_6358_RX_DATA,
	462	[SPI_MSG_TYPE_SHIFT] = SPI_6358_MSG_TYPE_SHIFT,
	463	[SPI_MSG_CTL_WIDTH] = SPI_6358_MSG_CTL_WIDTH,
	464	[SPI_MSG_DATA_SIZE] = SPI_6358_MSG_DATA_SIZE,
	465	};
	466
	467	static const struct platform_device_id bcm63xx_spi_dev_match[] = {
	468	{
	469	.name = "bcm6348-spi",
	470	.driver_data = (unsigned long)bcm6348_spi_reg_offsets,
	471	},
	472	{
	473	.name = "bcm6358-spi",
	474	.driver_data = (unsigned long)bcm6358_spi_reg_offsets,
	475	},
	476	{
	477	},
	478	};
b42dfed8	479
fd4a319b	480	static int bcm63xx_spi_probe(struct platform_device *pdev)
b42dfed8 FF	481	{
b42dfed8 FF	482	struct resource *r;
44d8fb30	483	const unsigned long *bcm63xx_spireg;
b42dfed8	484	struct device *dev = &pdev->dev;
b42dfed8 FF	485	int irq;
	486	struct spi_master *master;
	487	struct clk *clk;
	488	struct bcm63xx_spi *bs;
	489	int ret;
	490
44d8fb30 JG	491	if (!pdev->id_entry->driver_data)
	492	return -EINVAL;
	493
	494	bcm63xx_spireg = (const unsigned long *)pdev->id_entry->driver_data;
	495
b42dfed8 FF	496	irq = platform_get_irq(pdev, 0);
	497	if (irq < 0) {
	498	dev_err(dev, "no irq\n");
acf4fc6f	499	return -ENXIO;
b42dfed8 FF	500	}
b42dfed8 FF	501
acf4fc6f	502	clk = devm_clk_get(dev, "spi");
b42dfed8 FF	503	if (IS_ERR(clk)) {
b42dfed8 FF	504	dev_err(dev, "no clock for device\n");
acf4fc6f	505	return PTR_ERR(clk);
b42dfed8 FF	506	}
	507
	508	master = spi_alloc_master(dev, sizeof(*bs));
	509	if (!master) {
	510	dev_err(dev, "out of memory\n");
acf4fc6f	511	return -ENOMEM;
b42dfed8 FF	512	}
	513
	514	bs = spi_master_get_devdata(master);
aa0fe826	515	init_completion(&bs->done);
b42dfed8 FF	516
	517	platform_set_drvdata(pdev, master);
	518	bs->pdev = pdev;
	519
de0fa83c	520	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
b66c7730 JG	521	bs->regs = devm_ioremap_resource(&pdev->dev, r);
	522	if (IS_ERR(bs->regs)) {
	523	ret = PTR_ERR(bs->regs);
b42dfed8 FF	524	goto out_err;
	525	}
	526
	527	bs->irq = irq;
	528	bs->clk = clk;
44d8fb30 JG	529	bs->reg_offsets = bcm63xx_spireg;
44d8fb30 JG	530	bs->fifo_size = bs->reg_offsets[SPI_MSG_DATA_SIZE];
b42dfed8 FF	531
	532	ret = devm_request_irq(&pdev->dev, irq, bcm63xx_spi_interrupt, 0,
	533	pdev->name, master);
	534	if (ret) {
	535	dev_err(dev, "unable to request irq\n");
	536	goto out_err;
	537	}
	538
a45fcea5	539	master->bus_num = BCM63XX_SPI_BUS_NUM;
65059997	540	master->num_chipselect = BCM63XX_SPI_MAX_CS;
cde4384e	541	master->transfer_one_message = bcm63xx_spi_transfer_one;
88a3a255	542	master->mode_bits = MODEBITS;
24778be2	543	master->bits_per_word_mask = SPI_BPW_MASK(8);
5355d96d	544	master->auto_runtime_pm = true;
44d8fb30 JG	545	bs->msg_type_shift = bs->reg_offsets[SPI_MSG_TYPE_SHIFT];
	546	bs->msg_ctl_width = bs->reg_offsets[SPI_MSG_CTL_WIDTH];
	547	bs->tx_io = (u8 *)(bs->regs + bs->reg_offsets[SPI_MSG_DATA]);
	548	bs->rx_io = (const u8 *)(bs->regs + bs->reg_offsets[SPI_RX_DATA]);
5a670445	549
b42dfed8	550	/* Initialize hardware */
ea01e8a4 JG	551	ret = clk_prepare_enable(bs->clk);
	552	if (ret)
	553	goto out_err;
	554
b42dfed8 FF	555	bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS);
	556
	557	/* register and we are done */
bca76931	558	ret = devm_spi_register_master(dev, master);
b42dfed8 FF	559	if (ret) {
	560	dev_err(dev, "spi register failed\n");
	561	goto out_clk_disable;
	562	}
	563
0ba2cf70 AB	564	dev_info(dev, "at %pr (irq %d, FIFOs size %d)\n",
0ba2cf70 AB	565	r, irq, bs->fifo_size);
b42dfed8 FF	566
	567	return 0;
	568
	569	out_clk_disable:
4fbb82a7	570	clk_disable_unprepare(clk);
b42dfed8	571	out_err:
b42dfed8	572	spi_master_put(master);
b42dfed8 FF	573	return ret;
	574	}
	575
fd4a319b	576	static int bcm63xx_spi_remove(struct platform_device *pdev)
b42dfed8	577	{
9637b86f	578	struct spi_master *master = platform_get_drvdata(pdev);
b42dfed8 FF	579	struct bcm63xx_spi *bs = spi_master_get_devdata(master);
	580
	581	/* reset spi block */
	582	bcm_spi_writeb(bs, 0, SPI_INT_MASK);
b42dfed8 FF	583
b42dfed8 FF	584	/* HW shutdown */
4fbb82a7	585	clk_disable_unprepare(bs->clk);
b42dfed8	586
b42dfed8 FF	587	return 0;
	588	}
	589
1bae2028	590	#ifdef CONFIG_PM_SLEEP
b42dfed8 FF	591	static int bcm63xx_spi_suspend(struct device *dev)
b42dfed8 FF	592	{
a1216394	593	struct spi_master *master = dev_get_drvdata(dev);
b42dfed8 FF	594	struct bcm63xx_spi *bs = spi_master_get_devdata(master);
b42dfed8 FF	595
96519957 FF	596	spi_master_suspend(master);
96519957 FF	597
4fbb82a7	598	clk_disable_unprepare(bs->clk);
b42dfed8 FF	599
	600	return 0;
	601	}
	602
	603	static int bcm63xx_spi_resume(struct device *dev)
	604	{
a1216394	605	struct spi_master *master = dev_get_drvdata(dev);
b42dfed8	606	struct bcm63xx_spi *bs = spi_master_get_devdata(master);
ea01e8a4	607	int ret;
b42dfed8	608
ea01e8a4 JG	609	ret = clk_prepare_enable(bs->clk);
	610	if (ret)
	611	return ret;
b42dfed8	612
96519957 FF	613	spi_master_resume(master);
96519957 FF	614
b42dfed8 FF	615	return 0;
b42dfed8 FF	616	}
1bae2028	617	#endif
b42dfed8 FF	618
b42dfed8 FF	619	static const struct dev_pm_ops bcm63xx_spi_pm_ops = {
1bae2028	620	SET_SYSTEM_SLEEP_PM_OPS(bcm63xx_spi_suspend, bcm63xx_spi_resume)
b42dfed8 FF	621	};
b42dfed8 FF	622
b42dfed8 FF	623	static struct platform_driver bcm63xx_spi_driver = {
	624	.driver = {
	625	.name = "bcm63xx-spi",
1bae2028	626	.pm = &bcm63xx_spi_pm_ops,
b42dfed8	627	},
44d8fb30	628	.id_table = bcm63xx_spi_dev_match,
b42dfed8	629	.probe = bcm63xx_spi_probe,
fd4a319b	630	.remove = bcm63xx_spi_remove,
b42dfed8 FF	631	};
	632
	633	module_platform_driver(bcm63xx_spi_driver);
	634
	635	MODULE_ALIAS("platform:bcm63xx_spi");
	636	MODULE_AUTHOR("Florian Fainelli <florian@openwrt.org>");
	637	MODULE_AUTHOR("Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com>");
	638	MODULE_DESCRIPTION("Broadcom BCM63xx SPI Controller driver");
	639	MODULE_LICENSE("GPL");