[linux-2.6-block.git] / drivers / spi / spi-bcm2835.c

/*
 * Driver for Broadcom BCM2835 SPI Controllers
 *
 * Copyright (C) 2012 Chris Boot
 * Copyright (C) 2013 Stephen Warren
 * Copyright (C) 2015 Martin Sperl
 *
 * This driver is inspired by:
 * spi-ath79.c, Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
 * spi-atmel.c, Copyright (C) 2006 Atmel Corporation
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/clk.h>
#include <linux/completion.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_irq.h>
#include <linux/of_gpio.h>
#include <linux/of_device.h>
#include <linux/spi/spi.h>

/* SPI register offsets */
#define BCM2835_SPI_CS			0x00
#define BCM2835_SPI_FIFO		0x04
#define BCM2835_SPI_CLK			0x08
#define BCM2835_SPI_DLEN		0x0c
#define BCM2835_SPI_LTOH		0x10
#define BCM2835_SPI_DC			0x14

/* Bitfields in CS */
#define BCM2835_SPI_CS_LEN_LONG		0x02000000
#define BCM2835_SPI_CS_DMA_LEN		0x01000000
#define BCM2835_SPI_CS_CSPOL2		0x00800000
#define BCM2835_SPI_CS_CSPOL1		0x00400000
#define BCM2835_SPI_CS_CSPOL0		0x00200000
#define BCM2835_SPI_CS_RXF		0x00100000
#define BCM2835_SPI_CS_RXR		0x00080000
#define BCM2835_SPI_CS_TXD		0x00040000
#define BCM2835_SPI_CS_RXD		0x00020000
#define BCM2835_SPI_CS_DONE		0x00010000
#define BCM2835_SPI_CS_LEN		0x00002000
#define BCM2835_SPI_CS_REN		0x00001000
#define BCM2835_SPI_CS_ADCS		0x00000800
#define BCM2835_SPI_CS_INTR		0x00000400
#define BCM2835_SPI_CS_INTD		0x00000200
#define BCM2835_SPI_CS_DMAEN		0x00000100
#define BCM2835_SPI_CS_TA		0x00000080
#define BCM2835_SPI_CS_CSPOL		0x00000040
#define BCM2835_SPI_CS_CLEAR_RX		0x00000020
#define BCM2835_SPI_CS_CLEAR_TX		0x00000010
#define BCM2835_SPI_CS_CPOL		0x00000008
#define BCM2835_SPI_CS_CPHA		0x00000004
#define BCM2835_SPI_CS_CS_10		0x00000002
#define BCM2835_SPI_CS_CS_01		0x00000001

#define BCM2835_SPI_POLLING_LIMIT_US	30
#define BCM2835_SPI_TIMEOUT_MS		30000
#define BCM2835_SPI_MODE_BITS	(SPI_CPOL | SPI_CPHA | SPI_CS_HIGH \
				| SPI_NO_CS | SPI_3WIRE)

#define DRV_NAME	"spi-bcm2835"

struct bcm2835_spi {
	void __iomem *regs;
	struct clk *clk;
	int irq;
	const u8 *tx_buf;
	u8 *rx_buf;
	int tx_len;
	int rx_len;
};

static inline u32 bcm2835_rd(struct bcm2835_spi *bs, unsigned reg)
{
	return readl(bs->regs + reg);
}

static inline void bcm2835_wr(struct bcm2835_spi *bs, unsigned reg, u32 val)
{
	writel(val, bs->regs + reg);
}

static inline void bcm2835_rd_fifo(struct bcm2835_spi *bs)
{
	u8 byte;

	while ((bs->rx_len) &&
	       (bcm2835_rd(bs, BCM2835_SPI_CS) & BCM2835_SPI_CS_RXD)) {
		byte = bcm2835_rd(bs, BCM2835_SPI_FIFO);
		if (bs->rx_buf)
			*bs->rx_buf++ = byte;
		bs->rx_len--;
	}
}

static inline void bcm2835_wr_fifo(struct bcm2835_spi *bs)
{
	u8 byte;

	while ((bs->tx_len) &&
	       (bcm2835_rd(bs, BCM2835_SPI_CS) & BCM2835_SPI_CS_TXD)) {
		byte = bs->tx_buf ? *bs->tx_buf++ : 0;
		bcm2835_wr(bs, BCM2835_SPI_FIFO, byte);
		bs->tx_len--;
	}
}

static void bcm2835_spi_reset_hw(struct spi_master *master)
{
	struct bcm2835_spi *bs = spi_master_get_devdata(master);
	u32 cs = bcm2835_rd(bs, BCM2835_SPI_CS);

	/* Disable SPI interrupts and transfer */
	cs &= ~(BCM2835_SPI_CS_INTR |
		BCM2835_SPI_CS_INTD |
		BCM2835_SPI_CS_TA);
	/* and reset RX/TX FIFOS */
	cs |= BCM2835_SPI_CS_CLEAR_RX | BCM2835_SPI_CS_CLEAR_TX;

	/* and reset the SPI_HW */
	bcm2835_wr(bs, BCM2835_SPI_CS, cs);
}

static irqreturn_t bcm2835_spi_interrupt(int irq, void *dev_id)
{
	struct spi_master *master = dev_id;
	struct bcm2835_spi *bs = spi_master_get_devdata(master);

	/* Read as many bytes as possible from FIFO */
	bcm2835_rd_fifo(bs);
	/* Write as many bytes as possible to FIFO */
	bcm2835_wr_fifo(bs);

	/* based on flags decide if we can finish the transfer */
	if (bcm2835_rd(bs, BCM2835_SPI_CS) & BCM2835_SPI_CS_DONE) {
		/* Transfer complete - reset SPI HW */
		bcm2835_spi_reset_hw(master);
		/* wake up the framework */
		complete(&master->xfer_completion);
	}

	return IRQ_HANDLED;
}

static int bcm2835_spi_transfer_one_poll(struct spi_master *master,
					 struct spi_device *spi,
					 struct spi_transfer *tfr,
					 u32 cs,
					 unsigned long xfer_time_us)
{
	struct bcm2835_spi *bs = spi_master_get_devdata(master);
	unsigned long timeout = jiffies +
		max(4 * xfer_time_us * HZ / 1000000, 2uL);

	/* enable HW block without interrupts */
	bcm2835_wr(bs, BCM2835_SPI_CS, cs | BCM2835_SPI_CS_TA);

	/* set timeout to 4x the expected time, or 2 jiffies */
	/* loop until finished the transfer */
	while (bs->rx_len) {
		/* read from fifo as much as possible */
		bcm2835_rd_fifo(bs);
		/* fill in tx fifo as much as possible */
		bcm2835_wr_fifo(bs);
		/* if we still expect some data after the read,
		 * check for a possible timeout
		 */
		if (bs->rx_len && time_after(jiffies, timeout)) {
			/* Transfer complete - reset SPI HW */
			bcm2835_spi_reset_hw(master);
			/* and return timeout */
			return -ETIMEDOUT;
		}
	}

	/* Transfer complete - reset SPI HW */
	bcm2835_spi_reset_hw(master);
	/* and return without waiting for completion */
	return 0;
}

static int bcm2835_spi_transfer_one_irq(struct spi_master *master,
					struct spi_device *spi,
					struct spi_transfer *tfr,
					u32 cs)
{
	struct bcm2835_spi *bs = spi_master_get_devdata(master);

	/* fill in fifo if we have gpio-cs
	 * note that there have been rare events where the native-CS
	 * flapped for <1us which may change the behaviour
	 * with gpio-cs this does not happen, so it is implemented
	 * only for this case
	 */
	if (gpio_is_valid(spi->cs_gpio)) {
		/* enable HW block, but without interrupts enabled
		 * this would triggern an immediate interrupt
		 */
		bcm2835_wr(bs, BCM2835_SPI_CS,
			   cs | BCM2835_SPI_CS_TA);
		/* fill in tx fifo as much as possible */
		bcm2835_wr_fifo(bs);
	}

	/*
	 * Enable the HW block. This will immediately trigger a DONE (TX
	 * empty) interrupt, upon which we will fill the TX FIFO with the
	 * first TX bytes. Pre-filling the TX FIFO here to avoid the
	 * interrupt doesn't work:-(
	 */
	cs |= BCM2835_SPI_CS_INTR | BCM2835_SPI_CS_INTD | BCM2835_SPI_CS_TA;
	bcm2835_wr(bs, BCM2835_SPI_CS, cs);

	/* signal that we need to wait for completion */
	return 1;
}

static int bcm2835_spi_transfer_one(struct spi_master *master,
				    struct spi_device *spi,
				    struct spi_transfer *tfr)
{
	struct bcm2835_spi *bs = spi_master_get_devdata(master);
	unsigned long spi_hz, clk_hz, cdiv;
	unsigned long spi_used_hz, xfer_time_us;
	u32 cs = bcm2835_rd(bs, BCM2835_SPI_CS);

	/* set clock */
	spi_hz = tfr->speed_hz;
	clk_hz = clk_get_rate(bs->clk);

	if (spi_hz >= clk_hz / 2) {
		cdiv = 2; /* clk_hz/2 is the fastest we can go */
	} else if (spi_hz) {
		/* CDIV must be a multiple of two */
		cdiv = DIV_ROUND_UP(clk_hz, spi_hz);
		cdiv += (cdiv % 2);

		if (cdiv >= 65536)
			cdiv = 0; /* 0 is the slowest we can go */
	} else {
		cdiv = 0; /* 0 is the slowest we can go */
	}
	spi_used_hz = cdiv ? (clk_hz / cdiv) : (clk_hz / 65536);
	bcm2835_wr(bs, BCM2835_SPI_CLK, cdiv);

	/* handle all the modes */
	if ((spi->mode & SPI_3WIRE) && (tfr->rx_buf))
		cs |= BCM2835_SPI_CS_REN;
	if (spi->mode & SPI_CPOL)
		cs |= BCM2835_SPI_CS_CPOL;
	if (spi->mode & SPI_CPHA)
		cs |= BCM2835_SPI_CS_CPHA;

	/* for gpio_cs set dummy CS so that no HW-CS get changed
	 * we can not run this in bcm2835_spi_set_cs, as it does
	 * not get called for cs_gpio cases, so we need to do it here
	 */
	if (gpio_is_valid(spi->cs_gpio) || (spi->mode & SPI_NO_CS))
		cs |= BCM2835_SPI_CS_CS_10 | BCM2835_SPI_CS_CS_01;

	/* set transmit buffers and length */
	bs->tx_buf = tfr->tx_buf;
	bs->rx_buf = tfr->rx_buf;
	bs->tx_len = tfr->len;
	bs->rx_len = tfr->len;

	/* calculate the estimated time in us the transfer runs */
	xfer_time_us = tfr->len
		* 9 /* clocks/byte - SPI-HW waits 1 clock after each byte */
		* 1000000 / spi_used_hz;

	/* for short requests run polling*/
	if (xfer_time_us <= BCM2835_SPI_POLLING_LIMIT_US)
		return bcm2835_spi_transfer_one_poll(master, spi, tfr,
						     cs, xfer_time_us);

	return bcm2835_spi_transfer_one_irq(master, spi, tfr, cs);
}

static void bcm2835_spi_handle_err(struct spi_master *master,
				   struct spi_message *msg)
{
	bcm2835_spi_reset_hw(master);
}

static void bcm2835_spi_set_cs(struct spi_device *spi, bool gpio_level)
{
	/*
	 * we can assume that we are "native" as per spi_set_cs
	 *   calling us ONLY when cs_gpio is not set
	 * we can also assume that we are CS < 3 as per bcm2835_spi_setup
	 *   we would not get called because of error handling there.
	 * the level passed is the electrical level not enabled/disabled
	 *   so it has to get translated back to enable/disable
	 *   see spi_set_cs in spi.c for the implementation
	 */

	struct spi_master *master = spi->master;
	struct bcm2835_spi *bs = spi_master_get_devdata(master);
	u32 cs = bcm2835_rd(bs, BCM2835_SPI_CS);
	bool enable;

	/* calculate the enable flag from the passed gpio_level */
	enable = (spi->mode & SPI_CS_HIGH) ? gpio_level : !gpio_level;

	/* set flags for "reverse" polarity in the registers */
	if (spi->mode & SPI_CS_HIGH) {
		/* set the correct CS-bits */
		cs |= BCM2835_SPI_CS_CSPOL;
		cs |= BCM2835_SPI_CS_CSPOL0 << spi->chip_select;
	} else {
		/* clean the CS-bits */
		cs &= ~BCM2835_SPI_CS_CSPOL;
		cs &= ~(BCM2835_SPI_CS_CSPOL0 << spi->chip_select);
	}

	/* select the correct chip_select depending on disabled/enabled */
	if (enable) {
		/* set cs correctly */
		if (spi->mode & SPI_NO_CS) {
			/* use the "undefined" chip-select */
			cs |= BCM2835_SPI_CS_CS_10 | BCM2835_SPI_CS_CS_01;
		} else {
			/* set the chip select */
			cs &= ~(BCM2835_SPI_CS_CS_10 | BCM2835_SPI_CS_CS_01);
			cs |= spi->chip_select;
		}
	} else {
		/* disable CSPOL which puts HW-CS into deselected state */
		cs &= ~BCM2835_SPI_CS_CSPOL;
		/* use the "undefined" chip-select as precaution */
		cs |= BCM2835_SPI_CS_CS_10 | BCM2835_SPI_CS_CS_01;
	}

	/* finally set the calculated flags in SPI_CS */
	bcm2835_wr(bs, BCM2835_SPI_CS, cs);
}

static int chip_match_name(struct gpio_chip *chip, void *data)
{
	return !strcmp(chip->label, data);
}

static int bcm2835_spi_setup(struct spi_device *spi)
{
	int err;
	struct gpio_chip *chip;
	/*
	 * sanity checking the native-chipselects
	 */
	if (spi->mode & SPI_NO_CS)
		return 0;
	if (gpio_is_valid(spi->cs_gpio))
		return 0;
	if (spi->chip_select > 1) {
		/* error in the case of native CS requested with CS > 1
		 * officially there is a CS2, but it is not documented
		 * which GPIO is connected with that...
		 */
		dev_err(&spi->dev,
			"setup: only two native chip-selects are supported\n");
		return -EINVAL;
	}
	/* now translate native cs to GPIO */

	/* get the gpio chip for the base */
	chip = gpiochip_find("pinctrl-bcm2835", chip_match_name);
	if (!chip)
		return 0;

	/* and calculate the real CS */
	spi->cs_gpio = chip->base + 8 - spi->chip_select;

	/* and set up the "mode" and level */
	dev_info(&spi->dev, "setting up native-CS%i as GPIO %i\n",
		 spi->chip_select, spi->cs_gpio);

	/* set up GPIO as output and pull to the correct level */
	err = gpio_direction_output(spi->cs_gpio,
				    (spi->mode & SPI_CS_HIGH) ? 0 : 1);
	if (err) {
		dev_err(&spi->dev,
			"could not set CS%i gpio %i as output: %i",
			spi->chip_select, spi->cs_gpio, err);
		return err;
	}
	/* the implementation of pinctrl-bcm2835 currently does not
	 * set the GPIO value when using gpio_direction_output
	 * so we are setting it here explicitly
	 */
	gpio_set_value(spi->cs_gpio, (spi->mode & SPI_CS_HIGH) ? 0 : 1);

	return 0;
}

static int bcm2835_spi_probe(struct platform_device *pdev)
{
	struct spi_master *master;
	struct bcm2835_spi *bs;
	struct resource *res;
	int err;

	master = spi_alloc_master(&pdev->dev, sizeof(*bs));
	if (!master) {
		dev_err(&pdev->dev, "spi_alloc_master() failed\n");
		return -ENOMEM;
	}

	platform_set_drvdata(pdev, master);

	master->mode_bits = BCM2835_SPI_MODE_BITS;
	master->bits_per_word_mask = SPI_BPW_MASK(8);
	master->num_chipselect = 3;
	master->setup = bcm2835_spi_setup;
	master->set_cs = bcm2835_spi_set_cs;
	master->transfer_one = bcm2835_spi_transfer_one;
	master->handle_err = bcm2835_spi_handle_err;
	master->dev.of_node = pdev->dev.of_node;

	bs = spi_master_get_devdata(master);

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	bs->regs = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(bs->regs)) {
		err = PTR_ERR(bs->regs);
		goto out_master_put;
	}

	bs->clk = devm_clk_get(&pdev->dev, NULL);
	if (IS_ERR(bs->clk)) {
		err = PTR_ERR(bs->clk);
		dev_err(&pdev->dev, "could not get clk: %d\n", err);
		goto out_master_put;
	}

	bs->irq = irq_of_parse_and_map(pdev->dev.of_node, 0);
	if (bs->irq <= 0) {
		dev_err(&pdev->dev, "could not get IRQ: %d\n", bs->irq);
		err = bs->irq ? bs->irq : -ENODEV;
		goto out_master_put;
	}

	clk_prepare_enable(bs->clk);

	err = devm_request_irq(&pdev->dev, bs->irq, bcm2835_spi_interrupt, 0,
			       dev_name(&pdev->dev), master);
	if (err) {
		dev_err(&pdev->dev, "could not request IRQ: %d\n", err);
		goto out_clk_disable;
	}

	/* initialise the hardware with the default polarities */
	bcm2835_wr(bs, BCM2835_SPI_CS,
		   BCM2835_SPI_CS_CLEAR_RX | BCM2835_SPI_CS_CLEAR_TX);

	err = devm_spi_register_master(&pdev->dev, master);
	if (err) {
		dev_err(&pdev->dev, "could not register SPI master: %d\n", err);
		goto out_clk_disable;
	}

	return 0;

out_clk_disable:
	clk_disable_unprepare(bs->clk);
out_master_put:
	spi_master_put(master);
	return err;
}

static int bcm2835_spi_remove(struct platform_device *pdev)
{
	struct spi_master *master = platform_get_drvdata(pdev);
	struct bcm2835_spi *bs = spi_master_get_devdata(master);

	/* Clear FIFOs, and disable the HW block */
	bcm2835_wr(bs, BCM2835_SPI_CS,
		   BCM2835_SPI_CS_CLEAR_RX | BCM2835_SPI_CS_CLEAR_TX);

	clk_disable_unprepare(bs->clk);

	return 0;
}

static const struct of_device_id bcm2835_spi_match[] = {
	{ .compatible = "brcm,bcm2835-spi", },
	{}
};
MODULE_DEVICE_TABLE(of, bcm2835_spi_match);

static struct platform_driver bcm2835_spi_driver = {
	.driver		= {
		.name		= DRV_NAME,
		.of_match_table	= bcm2835_spi_match,
	},
	.probe		= bcm2835_spi_probe,
	.remove		= bcm2835_spi_remove,
};
module_platform_driver(bcm2835_spi_driver);

MODULE_DESCRIPTION("SPI controller driver for Broadcom BCM2835");
MODULE_AUTHOR("Chris Boot <bootc@bootc.net>");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
f8043872 CB	1	/*
	2	* Driver for Broadcom BCM2835 SPI Controllers
	3	*
	4	* Copyright (C) 2012 Chris Boot
	5	* Copyright (C) 2013 Stephen Warren
e34ff011	6	* Copyright (C) 2015 Martin Sperl
f8043872 CB	7	*
	8	* This driver is inspired by:
	9	* spi-ath79.c, Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
	10	* spi-atmel.c, Copyright (C) 2006 Atmel Corporation
	11	*
	12	* This program is free software; you can redistribute it and/or modify
	13	* it under the terms of the GNU General Public License as published by
	14	* the Free Software Foundation; either version 2 of the License, or
	15	* (at your option) any later version.
	16	*
	17	* This program is distributed in the hope that it will be useful,
	18	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	20	* GNU General Public License for more details.
f8043872 CB	21	*/
	22
	23	#include <linux/clk.h>
	24	#include <linux/completion.h>
	25	#include <linux/delay.h>
	26	#include <linux/err.h>
	27	#include <linux/interrupt.h>
	28	#include <linux/io.h>
	29	#include <linux/kernel.h>
	30	#include <linux/module.h>
	31	#include <linux/of.h>
	32	#include <linux/of_irq.h>
e34ff011	33	#include <linux/of_gpio.h>
f8043872 CB	34	#include <linux/of_device.h>
	35	#include <linux/spi/spi.h>
	36
	37	/* SPI register offsets */
	38	#define BCM2835_SPI_CS 0x00
	39	#define BCM2835_SPI_FIFO 0x04
	40	#define BCM2835_SPI_CLK 0x08
	41	#define BCM2835_SPI_DLEN 0x0c
	42	#define BCM2835_SPI_LTOH 0x10
	43	#define BCM2835_SPI_DC 0x14
	44
	45	/* Bitfields in CS */
	46	#define BCM2835_SPI_CS_LEN_LONG 0x02000000
	47	#define BCM2835_SPI_CS_DMA_LEN 0x01000000
	48	#define BCM2835_SPI_CS_CSPOL2 0x00800000
	49	#define BCM2835_SPI_CS_CSPOL1 0x00400000
	50	#define BCM2835_SPI_CS_CSPOL0 0x00200000
	51	#define BCM2835_SPI_CS_RXF 0x00100000
	52	#define BCM2835_SPI_CS_RXR 0x00080000
	53	#define BCM2835_SPI_CS_TXD 0x00040000
	54	#define BCM2835_SPI_CS_RXD 0x00020000
	55	#define BCM2835_SPI_CS_DONE 0x00010000
	56	#define BCM2835_SPI_CS_LEN 0x00002000
	57	#define BCM2835_SPI_CS_REN 0x00001000
	58	#define BCM2835_SPI_CS_ADCS 0x00000800
	59	#define BCM2835_SPI_CS_INTR 0x00000400
	60	#define BCM2835_SPI_CS_INTD 0x00000200
	61	#define BCM2835_SPI_CS_DMAEN 0x00000100
	62	#define BCM2835_SPI_CS_TA 0x00000080
	63	#define BCM2835_SPI_CS_CSPOL 0x00000040
	64	#define BCM2835_SPI_CS_CLEAR_RX 0x00000020
	65	#define BCM2835_SPI_CS_CLEAR_TX 0x00000010
	66	#define BCM2835_SPI_CS_CPOL 0x00000008
	67	#define BCM2835_SPI_CS_CPHA 0x00000004
	68	#define BCM2835_SPI_CS_CS_10 0x00000002
	69	#define BCM2835_SPI_CS_CS_01 0x00000001
	70
704f32d4 MS	71	#define BCM2835_SPI_POLLING_LIMIT_US 30
704f32d4 MS	72	#define BCM2835_SPI_TIMEOUT_MS 30000
6935224d MS	73	#define BCM2835_SPI_MODE_BITS (SPI_CPOL \| SPI_CPHA \| SPI_CS_HIGH \
6935224d MS	74	\| SPI_NO_CS \| SPI_3WIRE)
f8043872 CB	75
	76	#define DRV_NAME "spi-bcm2835"
	77
	78	struct bcm2835_spi {
	79	void __iomem *regs;
	80	struct clk *clk;
	81	int irq;
f8043872 CB	82	const u8 *tx_buf;
f8043872 CB	83	u8 *rx_buf;
e34ff011 MS	84	int tx_len;
e34ff011 MS	85	int rx_len;
f8043872 CB	86	};
	87
	88	static inline u32 bcm2835_rd(struct bcm2835_spi *bs, unsigned reg)
	89	{
	90	return readl(bs->regs + reg);
	91	}
	92
	93	static inline void bcm2835_wr(struct bcm2835_spi *bs, unsigned reg, u32 val)
	94	{
	95	writel(val, bs->regs + reg);
	96	}
	97
4adf3129	98	static inline void bcm2835_rd_fifo(struct bcm2835_spi *bs)
f8043872 CB	99	{
	100	u8 byte;
	101
e34ff011 MS	102	while ((bs->rx_len) &&
e34ff011 MS	103	(bcm2835_rd(bs, BCM2835_SPI_CS) & BCM2835_SPI_CS_RXD)) {
f8043872 CB	104	byte = bcm2835_rd(bs, BCM2835_SPI_FIFO);
	105	if (bs->rx_buf)
	106	*bs->rx_buf++ = byte;
e34ff011	107	bs->rx_len--;
f8043872 CB	108	}
	109	}
	110
4adf3129	111	static inline void bcm2835_wr_fifo(struct bcm2835_spi *bs)
f8043872 CB	112	{
	113	u8 byte;
	114
e34ff011	115	while ((bs->tx_len) &&
4adf3129	116	(bcm2835_rd(bs, BCM2835_SPI_CS) & BCM2835_SPI_CS_TXD)) {
f8043872 CB	117	byte = bs->tx_buf ? *bs->tx_buf++ : 0;
f8043872 CB	118	bcm2835_wr(bs, BCM2835_SPI_FIFO, byte);
e34ff011	119	bs->tx_len--;
f8043872 CB	120	}
	121	}
	122
e34ff011 MS	123	static void bcm2835_spi_reset_hw(struct spi_master *master)
	124	{
	125	struct bcm2835_spi *bs = spi_master_get_devdata(master);
	126	u32 cs = bcm2835_rd(bs, BCM2835_SPI_CS);
	127
	128	/* Disable SPI interrupts and transfer */
	129	cs &= ~(BCM2835_SPI_CS_INTR \|
	130	BCM2835_SPI_CS_INTD \|
	131	BCM2835_SPI_CS_TA);
	132	/* and reset RX/TX FIFOS */
	133	cs \|= BCM2835_SPI_CS_CLEAR_RX \| BCM2835_SPI_CS_CLEAR_TX;
	134
	135	/* and reset the SPI_HW */
	136	bcm2835_wr(bs, BCM2835_SPI_CS, cs);
	137	}
	138
f8043872 CB	139	static irqreturn_t bcm2835_spi_interrupt(int irq, void *dev_id)
	140	{
	141	struct spi_master *master = dev_id;
	142	struct bcm2835_spi *bs = spi_master_get_devdata(master);
f8043872	143
4adf3129 MS	144	/* Read as many bytes as possible from FIFO */
4adf3129 MS	145	bcm2835_rd_fifo(bs);
e34ff011 MS	146	/* Write as many bytes as possible to FIFO */
	147	bcm2835_wr_fifo(bs);
	148
	149	/* based on flags decide if we can finish the transfer */
	150	if (bcm2835_rd(bs, BCM2835_SPI_CS) & BCM2835_SPI_CS_DONE) {
	151	/* Transfer complete - reset SPI HW */
	152	bcm2835_spi_reset_hw(master);
	153	/* wake up the framework */
	154	complete(&master->xfer_completion);
f8043872 CB	155	}
f8043872 CB	156
4adf3129	157	return IRQ_HANDLED;
f8043872 CB	158	}
f8043872 CB	159
704f32d4 MS	160	static int bcm2835_spi_transfer_one_poll(struct spi_master *master,
	161	struct spi_device *spi,
	162	struct spi_transfer *tfr,
	163	u32 cs,
	164	unsigned long xfer_time_us)
	165	{
	166	struct bcm2835_spi *bs = spi_master_get_devdata(master);
	167	unsigned long timeout = jiffies +
	168	max(4 * xfer_time_us * HZ / 1000000, 2uL);
	169
	170	/* enable HW block without interrupts */
	171	bcm2835_wr(bs, BCM2835_SPI_CS, cs \| BCM2835_SPI_CS_TA);
	172
	173	/* set timeout to 4x the expected time, or 2 jiffies */
	174	/* loop until finished the transfer */
	175	while (bs->rx_len) {
	176	/* read from fifo as much as possible */
	177	bcm2835_rd_fifo(bs);
	178	/* fill in tx fifo as much as possible */
	179	bcm2835_wr_fifo(bs);
	180	/* if we still expect some data after the read,
	181	* check for a possible timeout
	182	*/
	183	if (bs->rx_len && time_after(jiffies, timeout)) {
	184	/* Transfer complete - reset SPI HW */
	185	bcm2835_spi_reset_hw(master);
	186	/* and return timeout */
	187	return -ETIMEDOUT;
	188	}
	189	}
	190
	191	/* Transfer complete - reset SPI HW */
	192	bcm2835_spi_reset_hw(master);
	193	/* and return without waiting for completion */
	194	return 0;
	195	}
	196
	197	static int bcm2835_spi_transfer_one_irq(struct spi_master *master,
	198	struct spi_device *spi,
	199	struct spi_transfer *tfr,
	200	u32 cs)
	201	{
	202	struct bcm2835_spi *bs = spi_master_get_devdata(master);
	203
	204	/* fill in fifo if we have gpio-cs
	205	* note that there have been rare events where the native-CS
	206	* flapped for <1us which may change the behaviour
	207	* with gpio-cs this does not happen, so it is implemented
	208	* only for this case
	209	*/
	210	if (gpio_is_valid(spi->cs_gpio)) {
	211	/* enable HW block, but without interrupts enabled
	212	* this would triggern an immediate interrupt
	213	*/
	214	bcm2835_wr(bs, BCM2835_SPI_CS,
	215	cs \| BCM2835_SPI_CS_TA);
	216	/* fill in tx fifo as much as possible */
	217	bcm2835_wr_fifo(bs);
	218	}
	219
	220	/*
	221	* Enable the HW block. This will immediately trigger a DONE (TX
	222	* empty) interrupt, upon which we will fill the TX FIFO with the
	223	* first TX bytes. Pre-filling the TX FIFO here to avoid the
224	* interrupt doesn't work:-(
225	*/
226	cs \|= BCM2835_SPI_CS_INTR \| BCM2835_SPI_CS_INTD \| BCM2835_SPI_CS_TA;
227	bcm2835_wr(bs, BCM2835_SPI_CS, cs);
228
229	/* signal that we need to wait for completion */
230	return 1;
231	}
232
e34ff011 MS	233	static int bcm2835_spi_transfer_one(struct spi_master *master,
	234	struct spi_device *spi,
	235	struct spi_transfer *tfr)
f8043872	236	{
e34ff011	237	struct bcm2835_spi *bs = spi_master_get_devdata(master);
f8043872	238	unsigned long spi_hz, clk_hz, cdiv;
704f32d4	239	unsigned long spi_used_hz, xfer_time_us;
e34ff011	240	u32 cs = bcm2835_rd(bs, BCM2835_SPI_CS);
f8043872	241
e34ff011	242	/* set clock */
f8043872 CB	243	spi_hz = tfr->speed_hz;
	244	clk_hz = clk_get_rate(bs->clk);
	245
	246	if (spi_hz >= clk_hz / 2) {
	247	cdiv = 2; /* clk_hz/2 is the fastest we can go */
	248	} else if (spi_hz) {
210b4923 MS	249	/* CDIV must be a multiple of two */
	250	cdiv = DIV_ROUND_UP(clk_hz, spi_hz);
	251	cdiv += (cdiv % 2);
f8043872 CB	252
	253	if (cdiv >= 65536)
	254	cdiv = 0; /* 0 is the slowest we can go */
342f948a	255	} else {
f8043872	256	cdiv = 0; /* 0 is the slowest we can go */
342f948a	257	}
704f32d4	258	spi_used_hz = cdiv ? (clk_hz / cdiv) : (clk_hz / 65536);
e34ff011	259	bcm2835_wr(bs, BCM2835_SPI_CLK, cdiv);
f8043872	260
e34ff011	261	/* handle all the modes */
6935224d MS	262	if ((spi->mode & SPI_3WIRE) && (tfr->rx_buf))
6935224d MS	263	cs \|= BCM2835_SPI_CS_REN;
f8043872 CB	264	if (spi->mode & SPI_CPOL)
	265	cs \|= BCM2835_SPI_CS_CPOL;
	266	if (spi->mode & SPI_CPHA)
	267	cs \|= BCM2835_SPI_CS_CPHA;
	268
e34ff011 MS	269	/* for gpio_cs set dummy CS so that no HW-CS get changed
	270	* we can not run this in bcm2835_spi_set_cs, as it does
	271	* not get called for cs_gpio cases, so we need to do it here
	272	*/
	273	if (gpio_is_valid(spi->cs_gpio) \|\| (spi->mode & SPI_NO_CS))
	274	cs \|= BCM2835_SPI_CS_CS_10 \| BCM2835_SPI_CS_CS_01;
f8043872	275
e34ff011	276	/* set transmit buffers and length */
f8043872 CB	277	bs->tx_buf = tfr->tx_buf;
f8043872 CB	278	bs->rx_buf = tfr->rx_buf;
e34ff011 MS	279	bs->tx_len = tfr->len;
e34ff011 MS	280	bs->rx_len = tfr->len;
f8043872	281
704f32d4 MS	282	/* calculate the estimated time in us the transfer runs */
	283	xfer_time_us = tfr->len
	284	* 9 /* clocks/byte - SPI-HW waits 1 clock after each byte */
	285	* 1000000 / spi_used_hz;
e3a2be30	286
704f32d4 MS	287	/* for short requests run polling*/
	288	if (xfer_time_us <= BCM2835_SPI_POLLING_LIMIT_US)
	289	return bcm2835_spi_transfer_one_poll(master, spi, tfr,
	290	cs, xfer_time_us);
f8043872	291
704f32d4	292	return bcm2835_spi_transfer_one_irq(master, spi, tfr, cs);
f8043872 CB	293	}
f8043872 CB	294
e34ff011 MS	295	static void bcm2835_spi_handle_err(struct spi_master *master,
e34ff011 MS	296	struct spi_message *msg)
f8043872	297	{
e34ff011	298	bcm2835_spi_reset_hw(master);
f8043872 CB	299	}
f8043872 CB	300
e34ff011	301	static void bcm2835_spi_set_cs(struct spi_device *spi, bool gpio_level)
f8043872	302	{
e34ff011 MS	303	/*
	304	* we can assume that we are "native" as per spi_set_cs
	305	* calling us ONLY when cs_gpio is not set
	306	* we can also assume that we are CS < 3 as per bcm2835_spi_setup
	307	* we would not get called because of error handling there.
	308	* the level passed is the electrical level not enabled/disabled
	309	* so it has to get translated back to enable/disable
	310	* see spi_set_cs in spi.c for the implementation
	311	*/
	312
	313	struct spi_master *master = spi->master;
f8043872	314	struct bcm2835_spi *bs = spi_master_get_devdata(master);
e34ff011 MS	315	u32 cs = bcm2835_rd(bs, BCM2835_SPI_CS);
e34ff011 MS	316	bool enable;
f8043872	317
e34ff011 MS	318	/* calculate the enable flag from the passed gpio_level */
e34ff011 MS	319	enable = (spi->mode & SPI_CS_HIGH) ? gpio_level : !gpio_level;
f8043872	320
e34ff011 MS	321	/* set flags for "reverse" polarity in the registers */
	322	if (spi->mode & SPI_CS_HIGH) {
	323	/* set the correct CS-bits */
	324	cs \|= BCM2835_SPI_CS_CSPOL;
	325	cs \|= BCM2835_SPI_CS_CSPOL0 << spi->chip_select;
	326	} else {
	327	/* clean the CS-bits */
	328	cs &= ~BCM2835_SPI_CS_CSPOL;
	329	cs &= ~(BCM2835_SPI_CS_CSPOL0 << spi->chip_select);
	330	}
f8043872	331
e34ff011 MS	332	/* select the correct chip_select depending on disabled/enabled */
	333	if (enable) {
	334	/* set cs correctly */
	335	if (spi->mode & SPI_NO_CS) {
	336	/* use the "undefined" chip-select */
	337	cs \|= BCM2835_SPI_CS_CS_10 \| BCM2835_SPI_CS_CS_01;
	338	} else {
	339	/* set the chip select */
	340	cs &= ~(BCM2835_SPI_CS_CS_10 \| BCM2835_SPI_CS_CS_01);
	341	cs \|= spi->chip_select;
	342	}
	343	} else {
	344	/* disable CSPOL which puts HW-CS into deselected state */
	345	cs &= ~BCM2835_SPI_CS_CSPOL;
	346	/* use the "undefined" chip-select as precaution */
	347	cs \|= BCM2835_SPI_CS_CS_10 \| BCM2835_SPI_CS_CS_01;
f8043872 CB	348	}
f8043872 CB	349
e34ff011 MS	350	/* finally set the calculated flags in SPI_CS */
	351	bcm2835_wr(bs, BCM2835_SPI_CS, cs);
	352	}
f8043872	353
a30a555d MS	354	static int chip_match_name(struct gpio_chip chip, void data)
	355	{
	356	return !strcmp(chip->label, data);
	357	}
	358
e34ff011 MS	359	static int bcm2835_spi_setup(struct spi_device *spi)
e34ff011 MS	360	{
a30a555d MS	361	int err;
a30a555d MS	362	struct gpio_chip *chip;
e34ff011 MS	363	/*
	364	* sanity checking the native-chipselects
	365	*/
	366	if (spi->mode & SPI_NO_CS)
	367	return 0;
	368	if (gpio_is_valid(spi->cs_gpio))
	369	return 0;
a30a555d MS	370	if (spi->chip_select > 1) {
	371	/* error in the case of native CS requested with CS > 1
	372	* officially there is a CS2, but it is not documented
	373	* which GPIO is connected with that...
	374	*/
	375	dev_err(&spi->dev,
	376	"setup: only two native chip-selects are supported\n");
	377	return -EINVAL;
	378	}
	379	/* now translate native cs to GPIO */
	380
	381	/* get the gpio chip for the base */
	382	chip = gpiochip_find("pinctrl-bcm2835", chip_match_name);
	383	if (!chip)
e34ff011 MS	384	return 0;
e34ff011 MS	385
a30a555d MS	386	/* and calculate the real CS */
	387	spi->cs_gpio = chip->base + 8 - spi->chip_select;
	388
	389	/* and set up the "mode" and level */
	390	dev_info(&spi->dev, "setting up native-CS%i as GPIO %i\n",
	391	spi->chip_select, spi->cs_gpio);
	392
	393	/* set up GPIO as output and pull to the correct level */
	394	err = gpio_direction_output(spi->cs_gpio,
	395	(spi->mode & SPI_CS_HIGH) ? 0 : 1);
	396	if (err) {
	397	dev_err(&spi->dev,
	398	"could not set CS%i gpio %i as output: %i",
	399	spi->chip_select, spi->cs_gpio, err);
	400	return err;
	401	}
	402	/* the implementation of pinctrl-bcm2835 currently does not
	403	* set the GPIO value when using gpio_direction_output
	404	* so we are setting it here explicitly
	405	*/
	406	gpio_set_value(spi->cs_gpio, (spi->mode & SPI_CS_HIGH) ? 0 : 1);
	407
	408	return 0;
f8043872 CB	409	}
	410
	411	static int bcm2835_spi_probe(struct platform_device *pdev)
	412	{
	413	struct spi_master *master;
	414	struct bcm2835_spi *bs;
	415	struct resource *res;
	416	int err;
	417
	418	master = spi_alloc_master(&pdev->dev, sizeof(*bs));
	419	if (!master) {
	420	dev_err(&pdev->dev, "spi_alloc_master() failed\n");
	421	return -ENOMEM;
	422	}
	423
	424	platform_set_drvdata(pdev, master);
	425
	426	master->mode_bits = BCM2835_SPI_MODE_BITS;
c2b6a3a8	427	master->bits_per_word_mask = SPI_BPW_MASK(8);
f8043872	428	master->num_chipselect = 3;
e34ff011 MS	429	master->setup = bcm2835_spi_setup;
	430	master->set_cs = bcm2835_spi_set_cs;
	431	master->transfer_one = bcm2835_spi_transfer_one;
	432	master->handle_err = bcm2835_spi_handle_err;
f8043872 CB	433	master->dev.of_node = pdev->dev.of_node;
	434
	435	bs = spi_master_get_devdata(master);
	436
f8043872	437	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2d6e75e8 LN	438	bs->regs = devm_ioremap_resource(&pdev->dev, res);
	439	if (IS_ERR(bs->regs)) {
	440	err = PTR_ERR(bs->regs);
f8043872 CB	441	goto out_master_put;
	442	}
	443
	444	bs->clk = devm_clk_get(&pdev->dev, NULL);
	445	if (IS_ERR(bs->clk)) {
	446	err = PTR_ERR(bs->clk);
	447	dev_err(&pdev->dev, "could not get clk: %d\n", err);
	448	goto out_master_put;
	449	}
	450
	451	bs->irq = irq_of_parse_and_map(pdev->dev.of_node, 0);
	452	if (bs->irq <= 0) {
	453	dev_err(&pdev->dev, "could not get IRQ: %d\n", bs->irq);
	454	err = bs->irq ? bs->irq : -ENODEV;
	455	goto out_master_put;
	456	}
	457
	458	clk_prepare_enable(bs->clk);
	459
08bc0544	460	err = devm_request_irq(&pdev->dev, bs->irq, bcm2835_spi_interrupt, 0,
342f948a	461	dev_name(&pdev->dev), master);
f8043872 CB	462	if (err) {
	463	dev_err(&pdev->dev, "could not request IRQ: %d\n", err);
	464	goto out_clk_disable;
	465	}
	466
e34ff011	467	/* initialise the hardware with the default polarities */
f8043872 CB	468	bcm2835_wr(bs, BCM2835_SPI_CS,
	469	BCM2835_SPI_CS_CLEAR_RX \| BCM2835_SPI_CS_CLEAR_TX);
	470
247263db	471	err = devm_spi_register_master(&pdev->dev, master);
f8043872 CB	472	if (err) {
f8043872 CB	473	dev_err(&pdev->dev, "could not register SPI master: %d\n", err);
08bc0544	474	goto out_clk_disable;
f8043872 CB	475	}
	476
	477	return 0;
	478
f8043872 CB	479	out_clk_disable:
	480	clk_disable_unprepare(bs->clk);
	481	out_master_put:
	482	spi_master_put(master);
	483	return err;
	484	}
	485
	486	static int bcm2835_spi_remove(struct platform_device *pdev)
	487	{
e0b35b89	488	struct spi_master *master = platform_get_drvdata(pdev);
f8043872 CB	489	struct bcm2835_spi *bs = spi_master_get_devdata(master);
f8043872 CB	490
f8043872 CB	491	/* Clear FIFOs, and disable the HW block */
	492	bcm2835_wr(bs, BCM2835_SPI_CS,
	493	BCM2835_SPI_CS_CLEAR_RX \| BCM2835_SPI_CS_CLEAR_TX);
	494
	495	clk_disable_unprepare(bs->clk);
f8043872 CB	496
	497	return 0;
	498	}
	499
	500	static const struct of_device_id bcm2835_spi_match[] = {
	501	{ .compatible = "brcm,bcm2835-spi", },
	502	{}
	503	};
	504	MODULE_DEVICE_TABLE(of, bcm2835_spi_match);
	505
	506	static struct platform_driver bcm2835_spi_driver = {
	507	.driver = {
	508	.name = DRV_NAME,
f8043872 CB	509	.of_match_table = bcm2835_spi_match,
	510	},
	511	.probe = bcm2835_spi_probe,
	512	.remove = bcm2835_spi_remove,
	513	};
	514	module_platform_driver(bcm2835_spi_driver);
	515
	516	MODULE_DESCRIPTION("SPI controller driver for Broadcom BCM2835");
	517	MODULE_AUTHOR("Chris Boot <bootc@bootc.net>");
	518	MODULE_LICENSE("GPL v2");