[linux-2.6-block.git] / drivers / soc / tegra / fuse / tegra-apbmisc.c

/*
 * Copyright (c) 2014, NVIDIA CORPORATION.  All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 *
 */

#include <linux/kernel.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/io.h>

#include <soc/tegra/fuse.h>
#include <soc/tegra/common.h>

#include "fuse.h"

#define FUSE_SKU_INFO	0x10

#define PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT	4
#define PMC_STRAPPING_OPT_A_RAM_CODE_MASK_LONG	\
	(0xf << PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT)
#define PMC_STRAPPING_OPT_A_RAM_CODE_MASK_SHORT	\
	(0x3 << PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT)

static void __iomem *apbmisc_base;
static void __iomem *strapping_base;
static bool long_ram_code;

u32 tegra_read_chipid(void)
{
	return readl_relaxed(apbmisc_base + 4);
}

u8 tegra_get_chip_id(void)
{
	if (!apbmisc_base) {
		WARN(1, "Tegra Chip ID not yet available\n");
		return 0;
	}

	return (tegra_read_chipid() >> 8) & 0xff;
}

u32 tegra_read_straps(void)
{
	if (strapping_base)
		return readl_relaxed(strapping_base);
	else
		return 0;
}

u32 tegra_read_ram_code(void)
{
	u32 straps = tegra_read_straps();

	if (long_ram_code)
		straps &= PMC_STRAPPING_OPT_A_RAM_CODE_MASK_LONG;
	else
		straps &= PMC_STRAPPING_OPT_A_RAM_CODE_MASK_SHORT;

	return straps >> PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT;
}

static const struct of_device_id apbmisc_match[] __initconst = {
	{ .compatible = "nvidia,tegra20-apbmisc", },
	{},
};

void __init tegra_init_revision(void)
{
	u32 id, chip_id, minor_rev;
	int rev;

	id = tegra_read_chipid();
	chip_id = (id >> 8) & 0xff;
	minor_rev = (id >> 16) & 0xf;

	switch (minor_rev) {
	case 1:
		rev = TEGRA_REVISION_A01;
		break;
	case 2:
		rev = TEGRA_REVISION_A02;
		break;
	case 3:
		if (chip_id == TEGRA20 && (tegra_fuse_read_spare(18) ||
					   tegra_fuse_read_spare(19)))
			rev = TEGRA_REVISION_A03p;
		else
			rev = TEGRA_REVISION_A03;
		break;
	case 4:
		rev = TEGRA_REVISION_A04;
		break;
	default:
		rev = TEGRA_REVISION_UNKNOWN;
	}

	tegra_sku_info.revision = rev;

	tegra_sku_info.sku_id = tegra_fuse_read_early(FUSE_SKU_INFO);
}

void __init tegra_init_apbmisc(void)
{
	struct resource apbmisc, straps;
	struct device_node *np;

	np = of_find_matching_node(NULL, apbmisc_match);
	if (!np) {
		/*
		 * Fall back to legacy initialization for 32-bit ARM only. All
		 * 64-bit ARM device tree files for Tegra are required to have
		 * an APBMISC node.
		 *
		 * This is for backwards-compatibility with old device trees
		 * that didn't contain an APBMISC node.
		 */
		if (IS_ENABLED(CONFIG_ARM) && soc_is_tegra()) {
			/* APBMISC registers (chip revision, ...) */
			apbmisc.start = 0x70000800;
			apbmisc.end = 0x70000863;
			apbmisc.flags = IORESOURCE_MEM;

			/* strapping options */
			if (tegra_get_chip_id() == TEGRA124) {
				straps.start = 0x7000e864;
				straps.end = 0x7000e867;
			} else {
				straps.start = 0x70000008;
				straps.end = 0x7000000b;
			}

			straps.flags = IORESOURCE_MEM;

			pr_warn("Using APBMISC region %pR\n", &apbmisc);
			pr_warn("Using strapping options registers %pR\n",
				&straps);
		} else {
			/*
			 * At this point we're not running on Tegra, so play
			 * nice with multi-platform kernels.
			 */
			return;
		}
	} else {
		/*
		 * Extract information from the device tree if we've found a
		 * matching node.
		 */
		if (of_address_to_resource(np, 0, &apbmisc) < 0) {
			pr_err("failed to get APBMISC registers\n");
			return;
		}

		if (of_address_to_resource(np, 1, &straps) < 0) {
			pr_err("failed to get strapping options registers\n");
			return;
		}
	}

	apbmisc_base = ioremap_nocache(apbmisc.start, resource_size(&apbmisc));
	if (!apbmisc_base)
		pr_err("failed to map APBMISC registers\n");

	strapping_base = ioremap_nocache(straps.start, resource_size(&straps));
	if (!strapping_base)
		pr_err("failed to map strapping options registers\n");

	long_ram_code = of_property_read_bool(np, "nvidia,long-ram-code");
}
Commit	Line	Data
783c8f4c PDS	1	/*
	2	* Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
	3	*
	4	* This program is free software; you can redistribute it and/or modify it
	5	* under the terms and conditions of the GNU General Public License,
	6	* version 2, as published by the Free Software Foundation.
	7	*
	8	* This program is distributed in the hope it will be useful, but WITHOUT
	9	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	10	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	11	* more details.
	12	*
	13	* You should have received a copy of the GNU General Public License
	14	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	15	*
	16	*/
	17
	18	#include <linux/kernel.h>
	19	#include <linux/of.h>
	20	#include <linux/of_address.h>
	21	#include <linux/io.h>
	22
	23	#include <soc/tegra/fuse.h>
297c4f3d	24	#include <soc/tegra/common.h>
783c8f4c PDS	25
	26	#include "fuse.h"
	27
783c8f4c PDS	28	#define FUSE_SKU_INFO 0x10
783c8f4c PDS	29
6ea2609a MP	30	#define PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT 4
	31	#define PMC_STRAPPING_OPT_A_RAM_CODE_MASK_LONG \
	32	(0xf << PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT)
	33	#define PMC_STRAPPING_OPT_A_RAM_CODE_MASK_SHORT \
	34	(0x3 << PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT)
	35
783c8f4c PDS	36	static void __iomem *apbmisc_base;
783c8f4c PDS	37	static void __iomem *strapping_base;
6ea2609a	38	static bool long_ram_code;
783c8f4c PDS	39
	40	u32 tegra_read_chipid(void)
	41	{
	42	return readl_relaxed(apbmisc_base + 4);
	43	}
	44
	45	u8 tegra_get_chip_id(void)
	46	{
24fa5af8 TR	47	if (!apbmisc_base) {
	48	WARN(1, "Tegra Chip ID not yet available\n");
	49	return 0;
	50	}
783c8f4c	51
24fa5af8	52	return (tegra_read_chipid() >> 8) & 0xff;
783c8f4c PDS	53	}
	54
	55	u32 tegra_read_straps(void)
	56	{
	57	if (strapping_base)
	58	return readl_relaxed(strapping_base);
	59	else
	60	return 0;
	61	}
	62
6ea2609a MP	63	u32 tegra_read_ram_code(void)
	64	{
	65	u32 straps = tegra_read_straps();
	66
	67	if (long_ram_code)
	68	straps &= PMC_STRAPPING_OPT_A_RAM_CODE_MASK_LONG;
	69	else
	70	straps &= PMC_STRAPPING_OPT_A_RAM_CODE_MASK_SHORT;
	71
	72	return straps >> PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT;
	73	}
	74
783c8f4c PDS	75	static const struct of_device_id apbmisc_match[] __initconst = {
	76	{ .compatible = "nvidia,tegra20-apbmisc", },
	77	{},
	78	};
	79
	80	void __init tegra_init_revision(void)
	81	{
	82	u32 id, chip_id, minor_rev;
	83	int rev;
	84
	85	id = tegra_read_chipid();
	86	chip_id = (id >> 8) & 0xff;
	87	minor_rev = (id >> 16) & 0xf;
	88
	89	switch (minor_rev) {
	90	case 1:
	91	rev = TEGRA_REVISION_A01;
	92	break;
	93	case 2:
	94	rev = TEGRA_REVISION_A02;
	95	break;
	96	case 3:
7e939de1 TR	97	if (chip_id == TEGRA20 && (tegra_fuse_read_spare(18) \|\|
7e939de1 TR	98	tegra_fuse_read_spare(19)))
783c8f4c PDS	99	rev = TEGRA_REVISION_A03p;
	100	else
	101	rev = TEGRA_REVISION_A03;
	102	break;
	103	case 4:
	104	rev = TEGRA_REVISION_A04;
	105	break;
	106	default:
	107	rev = TEGRA_REVISION_UNKNOWN;
	108	}
	109
	110	tegra_sku_info.revision = rev;
	111
7e939de1	112	tegra_sku_info.sku_id = tegra_fuse_read_early(FUSE_SKU_INFO);
783c8f4c PDS	113	}
	114
	115	void __init tegra_init_apbmisc(void)
	116	{
297c4f3d	117	struct resource apbmisc, straps;
783c8f4c PDS	118	struct device_node *np;
	119
	120	np = of_find_matching_node(NULL, apbmisc_match);
297c4f3d TR	121	if (!np) {
	122	/*
	123	* Fall back to legacy initialization for 32-bit ARM only. All
	124	* 64-bit ARM device tree files for Tegra are required to have
	125	* an APBMISC node.
	126	*
	127	* This is for backwards-compatibility with old device trees
	128	* that didn't contain an APBMISC node.
	129	*/
	130	if (IS_ENABLED(CONFIG_ARM) && soc_is_tegra()) {
	131	/* APBMISC registers (chip revision, ...) */
	132	apbmisc.start = 0x70000800;
	133	apbmisc.end = 0x70000863;
	134	apbmisc.flags = IORESOURCE_MEM;
	135
	136	/* strapping options */
	137	if (tegra_get_chip_id() == TEGRA124) {
	138	straps.start = 0x7000e864;
	139	straps.end = 0x7000e867;
	140	} else {
	141	straps.start = 0x70000008;
	142	straps.end = 0x7000000b;
	143	}
	144
	145	straps.flags = IORESOURCE_MEM;
	146
	147	pr_warn("Using APBMISC region %pR\n", &apbmisc);
	148	pr_warn("Using strapping options registers %pR\n",
	149	&straps);
	150	} else {
	151	/*
	152	* At this point we're not running on Tegra, so play
	153	* nice with multi-platform kernels.
	154	*/
	155	return;
	156	}
	157	} else {
	158	/*
	159	* Extract information from the device tree if we've found a
	160	* matching node.
	161	*/
	162	if (of_address_to_resource(np, 0, &apbmisc) < 0) {
	163	pr_err("failed to get APBMISC registers\n");
	164	return;
	165	}
	166
	167	if (of_address_to_resource(np, 1, &straps) < 0) {
	168	pr_err("failed to get strapping options registers\n");
	169	return;
	170	}
783c8f4c PDS	171	}
783c8f4c PDS	172
297c4f3d TR	173	apbmisc_base = ioremap_nocache(apbmisc.start, resource_size(&apbmisc));
	174	if (!apbmisc_base)
	175	pr_err("failed to map APBMISC registers\n");
	176
	177	strapping_base = ioremap_nocache(straps.start, resource_size(&straps));
783c8f4c	178	if (!strapping_base)
297c4f3d	179	pr_err("failed to map strapping options registers\n");
6ea2609a MP	180
6ea2609a MP	181	long_ram_code = of_property_read_bool(np, "nvidia,long-ram-code");
783c8f4c	182	}