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Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/sparc
[linux-2.6-block.git] / drivers / soc / mediatek / mtk-pmic-wrap.c
CommitLineData
1f022d84
FF		 1/*
2 * Copyright (c) 2014 MediaTek Inc.
3 * Author: Flora Fu, MediaTek
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14#include <linux/clk.h>
15#include <linux/interrupt.h>
16#include <linux/io.h>
17#include <linux/kernel.h>
18#include <linux/module.h>
19#include <linux/of_device.h>
20#include <linux/platform_device.h>
21#include <linux/regmap.h>
22#include <linux/reset.h>
23
24#define PWRAP_MT8135_BRIDGE_IORD_ARB_EN 0x4
25#define PWRAP_MT8135_BRIDGE_WACS3_EN 0x10
26#define PWRAP_MT8135_BRIDGE_INIT_DONE3 0x14
27#define PWRAP_MT8135_BRIDGE_WACS4_EN 0x24
28#define PWRAP_MT8135_BRIDGE_INIT_DONE4 0x28
29#define PWRAP_MT8135_BRIDGE_INT_EN 0x38
30#define PWRAP_MT8135_BRIDGE_TIMER_EN 0x48
31#define PWRAP_MT8135_BRIDGE_WDT_UNIT 0x50
32#define PWRAP_MT8135_BRIDGE_WDT_SRC_EN 0x54
33
34/* macro for wrapper status */
35#define PWRAP_GET_WACS_RDATA(x) (((x) >> 0) & 0x0000ffff)
36#define PWRAP_GET_WACS_FSM(x) (((x) >> 16) & 0x00000007)
37#define PWRAP_GET_WACS_REQ(x) (((x) >> 19) & 0x00000001)
38#define PWRAP_STATE_SYNC_IDLE0 (1 << 20)
39#define PWRAP_STATE_INIT_DONE0 (1 << 21)
40
41/* macro for WACS FSM */
42#define PWRAP_WACS_FSM_IDLE 0x00
43#define PWRAP_WACS_FSM_REQ 0x02
44#define PWRAP_WACS_FSM_WFDLE 0x04
45#define PWRAP_WACS_FSM_WFVLDCLR 0x06
46#define PWRAP_WACS_INIT_DONE 0x01
47#define PWRAP_WACS_WACS_SYNC_IDLE 0x01
48#define PWRAP_WACS_SYNC_BUSY 0x00
49
50/* macro for device wrapper default value */
51#define PWRAP_DEW_READ_TEST_VAL 0x5aa5
52#define PWRAP_DEW_WRITE_TEST_VAL 0xa55a
53
54/* macro for manual command */
55#define PWRAP_MAN_CMD_SPI_WRITE (1 << 13)
56#define PWRAP_MAN_CMD_OP_CSH (0x0 << 8)
57#define PWRAP_MAN_CMD_OP_CSL (0x1 << 8)
58#define PWRAP_MAN_CMD_OP_CK (0x2 << 8)
59#define PWRAP_MAN_CMD_OP_OUTS (0x8 << 8)
60#define PWRAP_MAN_CMD_OP_OUTD (0x9 << 8)
61#define PWRAP_MAN_CMD_OP_OUTQ (0xa << 8)
62
a3bbfbb0
HC		 63/* macro for Watch Dog Timer Source */
64#define PWRAP_WDT_SRC_EN_STAUPD_TRIG (1 << 25)
65#define PWRAP_WDT_SRC_EN_HARB_STAUPD_DLE (1 << 20)
66#define PWRAP_WDT_SRC_EN_HARB_STAUPD_ALE (1 << 6)
67#define PWRAP_WDT_SRC_MASK_ALL 0xffffffff
68#define PWRAP_WDT_SRC_MASK_NO_STAUPD ~(PWRAP_WDT_SRC_EN_STAUPD_TRIG | \
69 PWRAP_WDT_SRC_EN_HARB_STAUPD_DLE | \
70 PWRAP_WDT_SRC_EN_HARB_STAUPD_ALE)
71
1f022d84
FF		 72/* macro for slave device wrapper registers */
73#define PWRAP_DEW_BASE 0xbc00
74#define PWRAP_DEW_EVENT_OUT_EN (PWRAP_DEW_BASE + 0x0)
75#define PWRAP_DEW_DIO_EN (PWRAP_DEW_BASE + 0x2)
76#define PWRAP_DEW_EVENT_SRC_EN (PWRAP_DEW_BASE + 0x4)
77#define PWRAP_DEW_EVENT_SRC (PWRAP_DEW_BASE + 0x6)
78#define PWRAP_DEW_EVENT_FLAG (PWRAP_DEW_BASE + 0x8)
79#define PWRAP_DEW_READ_TEST (PWRAP_DEW_BASE + 0xa)
80#define PWRAP_DEW_WRITE_TEST (PWRAP_DEW_BASE + 0xc)
81#define PWRAP_DEW_CRC_EN (PWRAP_DEW_BASE + 0xe)
82#define PWRAP_DEW_CRC_VAL (PWRAP_DEW_BASE + 0x10)
83#define PWRAP_DEW_MON_GRP_SEL (PWRAP_DEW_BASE + 0x12)
84#define PWRAP_DEW_MON_FLAG_SEL (PWRAP_DEW_BASE + 0x14)
85#define PWRAP_DEW_EVENT_TEST (PWRAP_DEW_BASE + 0x16)
86#define PWRAP_DEW_CIPHER_KEY_SEL (PWRAP_DEW_BASE + 0x18)
87#define PWRAP_DEW_CIPHER_IV_SEL (PWRAP_DEW_BASE + 0x1a)
88#define PWRAP_DEW_CIPHER_LOAD (PWRAP_DEW_BASE + 0x1c)
89#define PWRAP_DEW_CIPHER_START (PWRAP_DEW_BASE + 0x1e)
90#define PWRAP_DEW_CIPHER_RDY (PWRAP_DEW_BASE + 0x20)
91#define PWRAP_DEW_CIPHER_MODE (PWRAP_DEW_BASE + 0x22)
92#define PWRAP_DEW_CIPHER_SWRST (PWRAP_DEW_BASE + 0x24)
93#define PWRAP_MT8173_DEW_CIPHER_IV0 (PWRAP_DEW_BASE + 0x26)
94#define PWRAP_MT8173_DEW_CIPHER_IV1 (PWRAP_DEW_BASE + 0x28)
95#define PWRAP_MT8173_DEW_CIPHER_IV2 (PWRAP_DEW_BASE + 0x2a)
96#define PWRAP_MT8173_DEW_CIPHER_IV3 (PWRAP_DEW_BASE + 0x2c)
97#define PWRAP_MT8173_DEW_CIPHER_IV4 (PWRAP_DEW_BASE + 0x2e)
98#define PWRAP_MT8173_DEW_CIPHER_IV5 (PWRAP_DEW_BASE + 0x30)
99
100enum pwrap_regs {
101 PWRAP_MUX_SEL,
102 PWRAP_WRAP_EN,
103 PWRAP_DIO_EN,
104 PWRAP_SIDLY,
105 PWRAP_CSHEXT_WRITE,
106 PWRAP_CSHEXT_READ,
107 PWRAP_CSLEXT_START,
108 PWRAP_CSLEXT_END,
109 PWRAP_STAUPD_PRD,
110 PWRAP_STAUPD_GRPEN,
111 PWRAP_STAUPD_MAN_TRIG,
112 PWRAP_STAUPD_STA,
113 PWRAP_WRAP_STA,
114 PWRAP_HARB_INIT,
115 PWRAP_HARB_HPRIO,
116 PWRAP_HIPRIO_ARB_EN,
117 PWRAP_HARB_STA0,
118 PWRAP_HARB_STA1,
119 PWRAP_MAN_EN,
120 PWRAP_MAN_CMD,
121 PWRAP_MAN_RDATA,
122 PWRAP_MAN_VLDCLR,
123 PWRAP_WACS0_EN,
124 PWRAP_INIT_DONE0,
125 PWRAP_WACS0_CMD,
126 PWRAP_WACS0_RDATA,
127 PWRAP_WACS0_VLDCLR,
128 PWRAP_WACS1_EN,
129 PWRAP_INIT_DONE1,
130 PWRAP_WACS1_CMD,
131 PWRAP_WACS1_RDATA,
132 PWRAP_WACS1_VLDCLR,
133 PWRAP_WACS2_EN,
134 PWRAP_INIT_DONE2,
135 PWRAP_WACS2_CMD,
136 PWRAP_WACS2_RDATA,
137 PWRAP_WACS2_VLDCLR,
138 PWRAP_INT_EN,
139 PWRAP_INT_FLG_RAW,
140 PWRAP_INT_FLG,
141 PWRAP_INT_CLR,
142 PWRAP_SIG_ADR,
143 PWRAP_SIG_MODE,
144 PWRAP_SIG_VALUE,
145 PWRAP_SIG_ERRVAL,
146 PWRAP_CRC_EN,
147 PWRAP_TIMER_EN,
148 PWRAP_TIMER_STA,
149 PWRAP_WDT_UNIT,
150 PWRAP_WDT_SRC_EN,
151 PWRAP_WDT_FLG,
152 PWRAP_DEBUG_INT_SEL,
153 PWRAP_CIPHER_KEY_SEL,
154 PWRAP_CIPHER_IV_SEL,
155 PWRAP_CIPHER_RDY,
156 PWRAP_CIPHER_MODE,
157 PWRAP_CIPHER_SWRST,
158 PWRAP_DCM_EN,
159 PWRAP_DCM_DBC_PRD,
160
161 /* MT8135 only regs */
162 PWRAP_CSHEXT,
163 PWRAP_EVENT_IN_EN,
164 PWRAP_EVENT_DST_EN,
165 PWRAP_RRARB_INIT,
166 PWRAP_RRARB_EN,
167 PWRAP_RRARB_STA0,
168 PWRAP_RRARB_STA1,
169 PWRAP_EVENT_STA,
170 PWRAP_EVENT_STACLR,
171 PWRAP_CIPHER_LOAD,
172 PWRAP_CIPHER_START,
173
174 /* MT8173 only regs */
175 PWRAP_RDDMY,
176 PWRAP_SI_CK_CON,
177 PWRAP_DVFS_ADR0,
178 PWRAP_DVFS_WDATA0,
179 PWRAP_DVFS_ADR1,
180 PWRAP_DVFS_WDATA1,
181 PWRAP_DVFS_ADR2,
182 PWRAP_DVFS_WDATA2,
183 PWRAP_DVFS_ADR3,
184 PWRAP_DVFS_WDATA3,
185 PWRAP_DVFS_ADR4,
186 PWRAP_DVFS_WDATA4,
187 PWRAP_DVFS_ADR5,
188 PWRAP_DVFS_WDATA5,
189 PWRAP_DVFS_ADR6,
190 PWRAP_DVFS_WDATA6,
191 PWRAP_DVFS_ADR7,
192 PWRAP_DVFS_WDATA7,
193 PWRAP_SPMINF_STA,
194 PWRAP_CIPHER_EN,
195};
196
197static int mt8173_regs[] = {
198 [PWRAP_MUX_SEL] = 0x0,
199 [PWRAP_WRAP_EN] = 0x4,
200 [PWRAP_DIO_EN] = 0x8,
201 [PWRAP_SIDLY] = 0xc,
202 [PWRAP_RDDMY] = 0x10,
203 [PWRAP_SI_CK_CON] = 0x14,
204 [PWRAP_CSHEXT_WRITE] = 0x18,
205 [PWRAP_CSHEXT_READ] = 0x1c,
206 [PWRAP_CSLEXT_START] = 0x20,
207 [PWRAP_CSLEXT_END] = 0x24,
208 [PWRAP_STAUPD_PRD] = 0x28,
209 [PWRAP_STAUPD_GRPEN] = 0x2c,
210 [PWRAP_STAUPD_MAN_TRIG] = 0x40,
211 [PWRAP_STAUPD_STA] = 0x44,
212 [PWRAP_WRAP_STA] = 0x48,
213 [PWRAP_HARB_INIT] = 0x4c,
214 [PWRAP_HARB_HPRIO] = 0x50,
215 [PWRAP_HIPRIO_ARB_EN] = 0x54,
216 [PWRAP_HARB_STA0] = 0x58,
217 [PWRAP_HARB_STA1] = 0x5c,
218 [PWRAP_MAN_EN] = 0x60,
219 [PWRAP_MAN_CMD] = 0x64,
220 [PWRAP_MAN_RDATA] = 0x68,
221 [PWRAP_MAN_VLDCLR] = 0x6c,
222 [PWRAP_WACS0_EN] = 0x70,
223 [PWRAP_INIT_DONE0] = 0x74,
224 [PWRAP_WACS0_CMD] = 0x78,
225 [PWRAP_WACS0_RDATA] = 0x7c,
226 [PWRAP_WACS0_VLDCLR] = 0x80,
227 [PWRAP_WACS1_EN] = 0x84,
228 [PWRAP_INIT_DONE1] = 0x88,
229 [PWRAP_WACS1_CMD] = 0x8c,
230 [PWRAP_WACS1_RDATA] = 0x90,
231 [PWRAP_WACS1_VLDCLR] = 0x94,
232 [PWRAP_WACS2_EN] = 0x98,
233 [PWRAP_INIT_DONE2] = 0x9c,
234 [PWRAP_WACS2_CMD] = 0xa0,
235 [PWRAP_WACS2_RDATA] = 0xa4,
236 [PWRAP_WACS2_VLDCLR] = 0xa8,
237 [PWRAP_INT_EN] = 0xac,
238 [PWRAP_INT_FLG_RAW] = 0xb0,
239 [PWRAP_INT_FLG] = 0xb4,
240 [PWRAP_INT_CLR] = 0xb8,
241 [PWRAP_SIG_ADR] = 0xbc,
242 [PWRAP_SIG_MODE] = 0xc0,
243 [PWRAP_SIG_VALUE] = 0xc4,
244 [PWRAP_SIG_ERRVAL] = 0xc8,
245 [PWRAP_CRC_EN] = 0xcc,
246 [PWRAP_TIMER_EN] = 0xd0,
247 [PWRAP_TIMER_STA] = 0xd4,
248 [PWRAP_WDT_UNIT] = 0xd8,
249 [PWRAP_WDT_SRC_EN] = 0xdc,
250 [PWRAP_WDT_FLG] = 0xe0,
251 [PWRAP_DEBUG_INT_SEL] = 0xe4,
252 [PWRAP_DVFS_ADR0] = 0xe8,
253 [PWRAP_DVFS_WDATA0] = 0xec,
254 [PWRAP_DVFS_ADR1] = 0xf0,
255 [PWRAP_DVFS_WDATA1] = 0xf4,
256 [PWRAP_DVFS_ADR2] = 0xf8,
257 [PWRAP_DVFS_WDATA2] = 0xfc,
258 [PWRAP_DVFS_ADR3] = 0x100,
259 [PWRAP_DVFS_WDATA3] = 0x104,
260 [PWRAP_DVFS_ADR4] = 0x108,
261 [PWRAP_DVFS_WDATA4] = 0x10c,
262 [PWRAP_DVFS_ADR5] = 0x110,
263 [PWRAP_DVFS_WDATA5] = 0x114,
264 [PWRAP_DVFS_ADR6] = 0x118,
265 [PWRAP_DVFS_WDATA6] = 0x11c,
266 [PWRAP_DVFS_ADR7] = 0x120,
267 [PWRAP_DVFS_WDATA7] = 0x124,
268 [PWRAP_SPMINF_STA] = 0x128,
269 [PWRAP_CIPHER_KEY_SEL] = 0x12c,
270 [PWRAP_CIPHER_IV_SEL] = 0x130,
271 [PWRAP_CIPHER_EN] = 0x134,
272 [PWRAP_CIPHER_RDY] = 0x138,
273 [PWRAP_CIPHER_MODE] = 0x13c,
274 [PWRAP_CIPHER_SWRST] = 0x140,
275 [PWRAP_DCM_EN] = 0x144,
276 [PWRAP_DCM_DBC_PRD] = 0x148,
277};
278
279static int mt8135_regs[] = {
280 [PWRAP_MUX_SEL] = 0x0,
281 [PWRAP_WRAP_EN] = 0x4,
282 [PWRAP_DIO_EN] = 0x8,
283 [PWRAP_SIDLY] = 0xc,
284 [PWRAP_CSHEXT] = 0x10,
285 [PWRAP_CSHEXT_WRITE] = 0x14,
286 [PWRAP_CSHEXT_READ] = 0x18,
287 [PWRAP_CSLEXT_START] = 0x1c,
288 [PWRAP_CSLEXT_END] = 0x20,
289 [PWRAP_STAUPD_PRD] = 0x24,
290 [PWRAP_STAUPD_GRPEN] = 0x28,
291 [PWRAP_STAUPD_MAN_TRIG] = 0x2c,
292 [PWRAP_STAUPD_STA] = 0x30,
293 [PWRAP_EVENT_IN_EN] = 0x34,
294 [PWRAP_EVENT_DST_EN] = 0x38,
295 [PWRAP_WRAP_STA] = 0x3c,
296 [PWRAP_RRARB_INIT] = 0x40,
297 [PWRAP_RRARB_EN] = 0x44,
298 [PWRAP_RRARB_STA0] = 0x48,
299 [PWRAP_RRARB_STA1] = 0x4c,
300 [PWRAP_HARB_INIT] = 0x50,
301 [PWRAP_HARB_HPRIO] = 0x54,
302 [PWRAP_HIPRIO_ARB_EN] = 0x58,
303 [PWRAP_HARB_STA0] = 0x5c,
304 [PWRAP_HARB_STA1] = 0x60,
305 [PWRAP_MAN_EN] = 0x64,
306 [PWRAP_MAN_CMD] = 0x68,
307 [PWRAP_MAN_RDATA] = 0x6c,
308 [PWRAP_MAN_VLDCLR] = 0x70,
309 [PWRAP_WACS0_EN] = 0x74,
310 [PWRAP_INIT_DONE0] = 0x78,
311 [PWRAP_WACS0_CMD] = 0x7c,
312 [PWRAP_WACS0_RDATA] = 0x80,
313 [PWRAP_WACS0_VLDCLR] = 0x84,
314 [PWRAP_WACS1_EN] = 0x88,
315 [PWRAP_INIT_DONE1] = 0x8c,
316 [PWRAP_WACS1_CMD] = 0x90,
317 [PWRAP_WACS1_RDATA] = 0x94,
318 [PWRAP_WACS1_VLDCLR] = 0x98,
319 [PWRAP_WACS2_EN] = 0x9c,
320 [PWRAP_INIT_DONE2] = 0xa0,
321 [PWRAP_WACS2_CMD] = 0xa4,
322 [PWRAP_WACS2_RDATA] = 0xa8,
323 [PWRAP_WACS2_VLDCLR] = 0xac,
324 [PWRAP_INT_EN] = 0xb0,
325 [PWRAP_INT_FLG_RAW] = 0xb4,
326 [PWRAP_INT_FLG] = 0xb8,
327 [PWRAP_INT_CLR] = 0xbc,
328 [PWRAP_SIG_ADR] = 0xc0,
329 [PWRAP_SIG_MODE] = 0xc4,
330 [PWRAP_SIG_VALUE] = 0xc8,
331 [PWRAP_SIG_ERRVAL] = 0xcc,
332 [PWRAP_CRC_EN] = 0xd0,
333 [PWRAP_EVENT_STA] = 0xd4,
334 [PWRAP_EVENT_STACLR] = 0xd8,
335 [PWRAP_TIMER_EN] = 0xdc,
336 [PWRAP_TIMER_STA] = 0xe0,
337 [PWRAP_WDT_UNIT] = 0xe4,
338 [PWRAP_WDT_SRC_EN] = 0xe8,
339 [PWRAP_WDT_FLG] = 0xec,
340 [PWRAP_DEBUG_INT_SEL] = 0xf0,
341 [PWRAP_CIPHER_KEY_SEL] = 0x134,
342 [PWRAP_CIPHER_IV_SEL] = 0x138,
343 [PWRAP_CIPHER_LOAD] = 0x13c,
344 [PWRAP_CIPHER_START] = 0x140,
345 [PWRAP_CIPHER_RDY] = 0x144,
346 [PWRAP_CIPHER_MODE] = 0x148,
347 [PWRAP_CIPHER_SWRST] = 0x14c,
348 [PWRAP_DCM_EN] = 0x15c,
349 [PWRAP_DCM_DBC_PRD] = 0x160,
350};
351
352enum pwrap_type {
353 PWRAP_MT8135,
354 PWRAP_MT8173,
355};
356
357struct pmic_wrapper_type {
358 int *regs;
359 enum pwrap_type type;
360 u32 arb_en_all;
361};
362
363static struct pmic_wrapper_type pwrap_mt8135 = {
364 .regs = mt8135_regs,
365 .type = PWRAP_MT8135,
366 .arb_en_all = 0x1ff,
367};
368
369static struct pmic_wrapper_type pwrap_mt8173 = {
370 .regs = mt8173_regs,
371 .type = PWRAP_MT8173,
372 .arb_en_all = 0x3f,
373};
374
375struct pmic_wrapper {
376 struct device *dev;
377 void __iomem *base;
378 struct regmap *regmap;
379 int *regs;
380 enum pwrap_type type;
381 u32 arb_en_all;
382 struct clk *clk_spi;
383 struct clk *clk_wrap;
384 struct reset_control *rstc;
385
386 struct reset_control *rstc_bridge;
387 void __iomem *bridge_base;
388};
389
390static inline int pwrap_is_mt8135(struct pmic_wrapper *wrp)
391{
392 return wrp->type == PWRAP_MT8135;
393}
394
395static inline int pwrap_is_mt8173(struct pmic_wrapper *wrp)
396{
397 return wrp->type == PWRAP_MT8173;
398}
399
400static u32 pwrap_readl(struct pmic_wrapper *wrp, enum pwrap_regs reg)
401{
402 return readl(wrp->base + wrp->regs[reg]);
403}
404
405static void pwrap_writel(struct pmic_wrapper *wrp, u32 val, enum pwrap_regs reg)
406{
407 writel(val, wrp->base + wrp->regs[reg]);
408}
409
410static bool pwrap_is_fsm_idle(struct pmic_wrapper *wrp)
411{
412 u32 val = pwrap_readl(wrp, PWRAP_WACS2_RDATA);
413
414 return PWRAP_GET_WACS_FSM(val) == PWRAP_WACS_FSM_IDLE;
415}
416
417static bool pwrap_is_fsm_vldclr(struct pmic_wrapper *wrp)
418{
419 u32 val = pwrap_readl(wrp, PWRAP_WACS2_RDATA);
420
421 return PWRAP_GET_WACS_FSM(val) == PWRAP_WACS_FSM_WFVLDCLR;
422}
423
73efe579
HC		 424/*
425 * Timeout issue sometimes caused by the last read command
426 * failed because pmic wrap could not got the FSM_VLDCLR
427 * in time after finishing WACS2_CMD. It made state machine
428 * still on FSM_VLDCLR and timeout next time.
429 * Check the status of FSM and clear the vldclr to recovery the
430 * error.
431 */
432static inline void pwrap_leave_fsm_vldclr(struct pmic_wrapper *wrp)
433{
434 if (pwrap_is_fsm_vldclr(wrp))
435 pwrap_writel(wrp, 1, PWRAP_WACS2_VLDCLR);
436}
437
1f022d84
FF		 438static bool pwrap_is_sync_idle(struct pmic_wrapper *wrp)
439{
440 return pwrap_readl(wrp, PWRAP_WACS2_RDATA) & PWRAP_STATE_SYNC_IDLE0;
441}
442
443static bool pwrap_is_fsm_idle_and_sync_idle(struct pmic_wrapper *wrp)
444{
445 u32 val = pwrap_readl(wrp, PWRAP_WACS2_RDATA);
446
447 return (PWRAP_GET_WACS_FSM(val) == PWRAP_WACS_FSM_IDLE) &&
448 (val & PWRAP_STATE_SYNC_IDLE0);
449}
450
451static int pwrap_wait_for_state(struct pmic_wrapper *wrp,
452 bool (*fp)(struct pmic_wrapper *))
453{
454 unsigned long timeout;
455
456 timeout = jiffies + usecs_to_jiffies(255);
457
458 do {
459 if (time_after(jiffies, timeout))
460 return fp(wrp) ? 0 : -ETIMEDOUT;
461 if (fp(wrp))
462 return 0;
463 } while (1);
464}
465
466static int pwrap_write(struct pmic_wrapper *wrp, u32 adr, u32 wdata)
467{
468 int ret;
1f022d84
FF		 469
470 ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle);
73efe579
HC		 471 if (ret) {
472 pwrap_leave_fsm_vldclr(wrp);
1f022d84 473 return ret;
73efe579 474 }
1f022d84
FF		 475
476 pwrap_writel(wrp, (1 << 31) | ((adr >> 1) << 16) | wdata,
477 PWRAP_WACS2_CMD);
478
479 return 0;
480}
481
482static int pwrap_read(struct pmic_wrapper *wrp, u32 adr, u32 *rdata)
483{
484 int ret;
1f022d84
FF		 485
486 ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle);
73efe579
HC		 487 if (ret) {
488 pwrap_leave_fsm_vldclr(wrp);
1f022d84 489 return ret;
73efe579 490 }
1f022d84
FF		 491
492 pwrap_writel(wrp, (adr >> 1) << 16, PWRAP_WACS2_CMD);
493
494 ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_vldclr);
495 if (ret)
496 return ret;
497
498 *rdata = PWRAP_GET_WACS_RDATA(pwrap_readl(wrp, PWRAP_WACS2_RDATA));
499
d956b80a
SH		 500 pwrap_writel(wrp, 1, PWRAP_WACS2_VLDCLR);
501
1f022d84
FF		 502 return 0;
503}
504
505static int pwrap_regmap_read(void *context, u32 adr, u32 *rdata)
506{
507 return pwrap_read(context, adr, rdata);
508}
509
510static int pwrap_regmap_write(void *context, u32 adr, u32 wdata)
511{
512 return pwrap_write(context, adr, wdata);
513}
514
515static int pwrap_reset_spislave(struct pmic_wrapper *wrp)
516{
517 int ret, i;
518
519 pwrap_writel(wrp, 0, PWRAP_HIPRIO_ARB_EN);
520 pwrap_writel(wrp, 0, PWRAP_WRAP_EN);
521 pwrap_writel(wrp, 1, PWRAP_MUX_SEL);
522 pwrap_writel(wrp, 1, PWRAP_MAN_EN);
523 pwrap_writel(wrp, 0, PWRAP_DIO_EN);
524
525 pwrap_writel(wrp, PWRAP_MAN_CMD_SPI_WRITE | PWRAP_MAN_CMD_OP_CSL,
526 PWRAP_MAN_CMD);
527 pwrap_writel(wrp, PWRAP_MAN_CMD_SPI_WRITE | PWRAP_MAN_CMD_OP_OUTS,
528 PWRAP_MAN_CMD);
529 pwrap_writel(wrp, PWRAP_MAN_CMD_SPI_WRITE | PWRAP_MAN_CMD_OP_CSH,
530 PWRAP_MAN_CMD);
531
532 for (i = 0; i < 4; i++)
533 pwrap_writel(wrp, PWRAP_MAN_CMD_SPI_WRITE | PWRAP_MAN_CMD_OP_OUTS,
534 PWRAP_MAN_CMD);
535
536 ret = pwrap_wait_for_state(wrp, pwrap_is_sync_idle);
537 if (ret) {
538 dev_err(wrp->dev, "%s fail, ret=%d\n", __func__, ret);
539 return ret;
540 }
541
542 pwrap_writel(wrp, 0, PWRAP_MAN_EN);
543 pwrap_writel(wrp, 0, PWRAP_MUX_SEL);
544
545 return 0;
546}
547
548/*
549 * pwrap_init_sidly - configure serial input delay
550 *
551 * This configures the serial input delay. We can configure 0, 2, 4 or 6ns
552 * delay. Do a read test with all possible values and chose the best delay.
553 */
554static int pwrap_init_sidly(struct pmic_wrapper *wrp)
555{
556 u32 rdata;
557 u32 i;
558 u32 pass = 0;
559 signed char dly[16] = {
560 -1, 0, 1, 0, 2, -1, 1, 1, 3, -1, -1, -1, 3, -1, 2, 1
561 };
562
563 for (i = 0; i < 4; i++) {
564 pwrap_writel(wrp, i, PWRAP_SIDLY);
565 pwrap_read(wrp, PWRAP_DEW_READ_TEST, &rdata);
566 if (rdata == PWRAP_DEW_READ_TEST_VAL) {
567 dev_dbg(wrp->dev, "[Read Test] pass, SIDLY=%x\n", i);
568 pass |= 1 << i;
569 }
570 }
571
572 if (dly[pass] < 0) {
573 dev_err(wrp->dev, "sidly pass range 0x%x not continuous\n",
574 pass);
575 return -EIO;
576 }
577
578 pwrap_writel(wrp, dly[pass], PWRAP_SIDLY);
579
580 return 0;
581}
582
583static int pwrap_init_reg_clock(struct pmic_wrapper *wrp)
584{
d71c11f3
SH		 585 if (pwrap_is_mt8135(wrp)) {
586 pwrap_writel(wrp, 0x4, PWRAP_CSHEXT);
1f022d84
FF		 587 pwrap_writel(wrp, 0x0, PWRAP_CSHEXT_WRITE);
588 pwrap_writel(wrp, 0x4, PWRAP_CSHEXT_READ);
589 pwrap_writel(wrp, 0x0, PWRAP_CSLEXT_START);
590 pwrap_writel(wrp, 0x0, PWRAP_CSLEXT_END);
d71c11f3
SH		 591 } else {
592 pwrap_writel(wrp, 0x0, PWRAP_CSHEXT_WRITE);
593 pwrap_writel(wrp, 0x4, PWRAP_CSHEXT_READ);
594 pwrap_writel(wrp, 0x2, PWRAP_CSLEXT_START);
595 pwrap_writel(wrp, 0x2, PWRAP_CSLEXT_END);
1f022d84
FF		 596 }
597
598 return 0;
599}
600
601static bool pwrap_is_cipher_ready(struct pmic_wrapper *wrp)
602{
603 return pwrap_readl(wrp, PWRAP_CIPHER_RDY) & 1;
604}
605
606static bool pwrap_is_pmic_cipher_ready(struct pmic_wrapper *wrp)
607{
608 u32 rdata;
609 int ret;
610
611 ret = pwrap_read(wrp, PWRAP_DEW_CIPHER_RDY, &rdata);
612 if (ret)
613 return 0;
614
615 return rdata == 1;
616}
617
618static int pwrap_init_cipher(struct pmic_wrapper *wrp)
619{
620 int ret;
621 u32 rdata;
622
623 pwrap_writel(wrp, 0x1, PWRAP_CIPHER_SWRST);
624 pwrap_writel(wrp, 0x0, PWRAP_CIPHER_SWRST);
625 pwrap_writel(wrp, 0x1, PWRAP_CIPHER_KEY_SEL);
626 pwrap_writel(wrp, 0x2, PWRAP_CIPHER_IV_SEL);
627
628 if (pwrap_is_mt8135(wrp)) {
629 pwrap_writel(wrp, 1, PWRAP_CIPHER_LOAD);
630 pwrap_writel(wrp, 1, PWRAP_CIPHER_START);
631 } else {
632 pwrap_writel(wrp, 1, PWRAP_CIPHER_EN);
633 }
634
635 /* Config cipher mode @PMIC */
636 pwrap_write(wrp, PWRAP_DEW_CIPHER_SWRST, 0x1);
637 pwrap_write(wrp, PWRAP_DEW_CIPHER_SWRST, 0x0);
638 pwrap_write(wrp, PWRAP_DEW_CIPHER_KEY_SEL, 0x1);
639 pwrap_write(wrp, PWRAP_DEW_CIPHER_IV_SEL, 0x2);
640 pwrap_write(wrp, PWRAP_DEW_CIPHER_LOAD, 0x1);
641 pwrap_write(wrp, PWRAP_DEW_CIPHER_START, 0x1);
642
643 /* wait for cipher data ready@AP */
644 ret = pwrap_wait_for_state(wrp, pwrap_is_cipher_ready);
645 if (ret) {
646 dev_err(wrp->dev, "cipher data ready@AP fail, ret=%d\n", ret);
647 return ret;
648 }
649
650 /* wait for cipher data ready@PMIC */
651 ret = pwrap_wait_for_state(wrp, pwrap_is_pmic_cipher_ready);
652 if (ret) {
653 dev_err(wrp->dev, "timeout waiting for cipher data ready@PMIC\n");
654 return ret;
655 }
656
657 /* wait for cipher mode idle */
658 pwrap_write(wrp, PWRAP_DEW_CIPHER_MODE, 0x1);
659 ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle_and_sync_idle);
660 if (ret) {
661 dev_err(wrp->dev, "cipher mode idle fail, ret=%d\n", ret);
662 return ret;
663 }
664
665 pwrap_writel(wrp, 1, PWRAP_CIPHER_MODE);
666
667 /* Write Test */
668 if (pwrap_write(wrp, PWRAP_DEW_WRITE_TEST, PWRAP_DEW_WRITE_TEST_VAL) ||
669 pwrap_read(wrp, PWRAP_DEW_WRITE_TEST, &rdata) ||
670 (rdata != PWRAP_DEW_WRITE_TEST_VAL)) {
671 dev_err(wrp->dev, "rdata=0x%04X\n", rdata);
672 return -EFAULT;
673 }
674
675 return 0;
676}
677
678static int pwrap_init(struct pmic_wrapper *wrp)
679{
680 int ret;
681 u32 rdata;
682
683 reset_control_reset(wrp->rstc);
684 if (wrp->rstc_bridge)
685 reset_control_reset(wrp->rstc_bridge);
686
687 if (pwrap_is_mt8173(wrp)) {
688 /* Enable DCM */
689 pwrap_writel(wrp, 3, PWRAP_DCM_EN);
690 pwrap_writel(wrp, 0, PWRAP_DCM_DBC_PRD);
691 }
692
693 /* Reset SPI slave */
694 ret = pwrap_reset_spislave(wrp);
695 if (ret)
696 return ret;
697
698 pwrap_writel(wrp, 1, PWRAP_WRAP_EN);
699
700 pwrap_writel(wrp, wrp->arb_en_all, PWRAP_HIPRIO_ARB_EN);
701
702 pwrap_writel(wrp, 1, PWRAP_WACS2_EN);
703
704 ret = pwrap_init_reg_clock(wrp);
705 if (ret)
706 return ret;
707
708 /* Setup serial input delay */
709 ret = pwrap_init_sidly(wrp);
710 if (ret)
711 return ret;
712
713 /* Enable dual IO mode */
714 pwrap_write(wrp, PWRAP_DEW_DIO_EN, 1);
715
716 /* Check IDLE & INIT_DONE in advance */
717 ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle_and_sync_idle);
718 if (ret) {
719 dev_err(wrp->dev, "%s fail, ret=%d\n", __func__, ret);
720 return ret;
721 }
722
723 pwrap_writel(wrp, 1, PWRAP_DIO_EN);
724
725 /* Read Test */
726 pwrap_read(wrp, PWRAP_DEW_READ_TEST, &rdata);
727 if (rdata != PWRAP_DEW_READ_TEST_VAL) {
728 dev_err(wrp->dev, "Read test failed after switch to DIO mode: 0x%04x != 0x%04x\n",
729 PWRAP_DEW_READ_TEST_VAL, rdata);
730 return -EFAULT;
731 }
732
733 /* Enable encryption */
734 ret = pwrap_init_cipher(wrp);
735 if (ret)
736 return ret;
737
738 /* Signature checking - using CRC */
739 if (pwrap_write(wrp, PWRAP_DEW_CRC_EN, 0x1))
740 return -EFAULT;
741
742 pwrap_writel(wrp, 0x1, PWRAP_CRC_EN);
743 pwrap_writel(wrp, 0x0, PWRAP_SIG_MODE);
744 pwrap_writel(wrp, PWRAP_DEW_CRC_VAL, PWRAP_SIG_ADR);
745 pwrap_writel(wrp, wrp->arb_en_all, PWRAP_HIPRIO_ARB_EN);
746
747 if (pwrap_is_mt8135(wrp))
748 pwrap_writel(wrp, 0x7, PWRAP_RRARB_EN);
749
750 pwrap_writel(wrp, 0x1, PWRAP_WACS0_EN);
751 pwrap_writel(wrp, 0x1, PWRAP_WACS1_EN);
752 pwrap_writel(wrp, 0x1, PWRAP_WACS2_EN);
753 pwrap_writel(wrp, 0x5, PWRAP_STAUPD_PRD);
754 pwrap_writel(wrp, 0xff, PWRAP_STAUPD_GRPEN);
1f022d84
FF		 755
756 if (pwrap_is_mt8135(wrp)) {
757 /* enable pwrap events and pwrap bridge in AP side */
758 pwrap_writel(wrp, 0x1, PWRAP_EVENT_IN_EN);
759 pwrap_writel(wrp, 0xffff, PWRAP_EVENT_DST_EN);
760 writel(0x7f, wrp->bridge_base + PWRAP_MT8135_BRIDGE_IORD_ARB_EN);
761 writel(0x1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_WACS3_EN);
762 writel(0x1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_WACS4_EN);
763 writel(0x1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_WDT_UNIT);
764 writel(0xffff, wrp->bridge_base + PWRAP_MT8135_BRIDGE_WDT_SRC_EN);
765 writel(0x1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_TIMER_EN);
766 writel(0x7ff, wrp->bridge_base + PWRAP_MT8135_BRIDGE_INT_EN);
767
768 /* enable PMIC event out and sources */
769 if (pwrap_write(wrp, PWRAP_DEW_EVENT_OUT_EN, 0x1) ||
770 pwrap_write(wrp, PWRAP_DEW_EVENT_SRC_EN, 0xffff)) {
771 dev_err(wrp->dev, "enable dewrap fail\n");
772 return -EFAULT;
773 }
774 } else {
775 /* PMIC_DEWRAP enables */
776 if (pwrap_write(wrp, PWRAP_DEW_EVENT_OUT_EN, 0x1) ||
777 pwrap_write(wrp, PWRAP_DEW_EVENT_SRC_EN, 0xffff)) {
778 dev_err(wrp->dev, "enable dewrap fail\n");
779 return -EFAULT;
780 }
781 }
782
783 /* Setup the init done registers */
784 pwrap_writel(wrp, 1, PWRAP_INIT_DONE2);
785 pwrap_writel(wrp, 1, PWRAP_INIT_DONE0);
786 pwrap_writel(wrp, 1, PWRAP_INIT_DONE1);
787
788 if (pwrap_is_mt8135(wrp)) {
789 writel(1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_INIT_DONE3);
790 writel(1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_INIT_DONE4);
791 }
792
793 return 0;
794}
795
796static irqreturn_t pwrap_interrupt(int irqno, void *dev_id)
797{
798 u32 rdata;
799 struct pmic_wrapper *wrp = dev_id;
800
801 rdata = pwrap_readl(wrp, PWRAP_INT_FLG);
802
803 dev_err(wrp->dev, "unexpected interrupt int=0x%x\n", rdata);
804
805 pwrap_writel(wrp, 0xffffffff, PWRAP_INT_CLR);
806
807 return IRQ_HANDLED;
808}
809
810static const struct regmap_config pwrap_regmap_config = {
811 .reg_bits = 16,
812 .val_bits = 16,
813 .reg_stride = 2,
814 .reg_read = pwrap_regmap_read,
815 .reg_write = pwrap_regmap_write,
816 .max_register = 0xffff,
817};
818
819static struct of_device_id of_pwrap_match_tbl[] = {
820 {
821 .compatible = "mediatek,mt8135-pwrap",
822 .data = &pwrap_mt8135,
823 }, {
824 .compatible = "mediatek,mt8173-pwrap",
825 .data = &pwrap_mt8173,
826 }, {
827 /* sentinel */
828 }
829};
830MODULE_DEVICE_TABLE(of, of_pwrap_match_tbl);
831
832static int pwrap_probe(struct platform_device *pdev)
833{
a3bbfbb0 834 int ret, irq, wdt_src;
1f022d84
FF		 835 struct pmic_wrapper *wrp;
836 struct device_node *np = pdev->dev.of_node;
837 const struct of_device_id *of_id =
838 of_match_device(of_pwrap_match_tbl, &pdev->dev);
839 const struct pmic_wrapper_type *type;
840 struct resource *res;
841
842 wrp = devm_kzalloc(&pdev->dev, sizeof(*wrp), GFP_KERNEL);
843 if (!wrp)
844 return -ENOMEM;
845
846 platform_set_drvdata(pdev, wrp);
847
848 type = of_id->data;
849 wrp->regs = type->regs;
850 wrp->type = type->type;
851 wrp->arb_en_all = type->arb_en_all;
852 wrp->dev = &pdev->dev;
853
854 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pwrap");
855 wrp->base = devm_ioremap_resource(wrp->dev, res);
856 if (IS_ERR(wrp->base))
857 return PTR_ERR(wrp->base);
858
859 wrp->rstc = devm_reset_control_get(wrp->dev, "pwrap");
860 if (IS_ERR(wrp->rstc)) {
861 ret = PTR_ERR(wrp->rstc);
862 dev_dbg(wrp->dev, "cannot get pwrap reset: %d\n", ret);
863 return ret;
864 }
865
866 if (pwrap_is_mt8135(wrp)) {
867 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
868 "pwrap-bridge");
869 wrp->bridge_base = devm_ioremap_resource(wrp->dev, res);
870 if (IS_ERR(wrp->bridge_base))
871 return PTR_ERR(wrp->bridge_base);
872
873 wrp->rstc_bridge = devm_reset_control_get(wrp->dev, "pwrap-bridge");
874 if (IS_ERR(wrp->rstc_bridge)) {
875 ret = PTR_ERR(wrp->rstc_bridge);
876 dev_dbg(wrp->dev, "cannot get pwrap-bridge reset: %d\n", ret);
877 return ret;
878 }
879 }
880
881 wrp->clk_spi = devm_clk_get(wrp->dev, "spi");
882 if (IS_ERR(wrp->clk_spi)) {
883 dev_dbg(wrp->dev, "failed to get clock: %ld\n", PTR_ERR(wrp->clk_spi));
884 return PTR_ERR(wrp->clk_spi);
885 }
886
887 wrp->clk_wrap = devm_clk_get(wrp->dev, "wrap");
888 if (IS_ERR(wrp->clk_wrap)) {
889 dev_dbg(wrp->dev, "failed to get clock: %ld\n", PTR_ERR(wrp->clk_wrap));
890 return PTR_ERR(wrp->clk_wrap);
891 }
892
893 ret = clk_prepare_enable(wrp->clk_spi);
894 if (ret)
895 return ret;
896
897 ret = clk_prepare_enable(wrp->clk_wrap);
898 if (ret)
899 goto err_out1;
900
901 /* Enable internal dynamic clock */
902 pwrap_writel(wrp, 1, PWRAP_DCM_EN);
903 pwrap_writel(wrp, 0, PWRAP_DCM_DBC_PRD);
904
905 /*
906 * The PMIC could already be initialized by the bootloader.
907 * Skip initialization here in this case.
908 */
909 if (!pwrap_readl(wrp, PWRAP_INIT_DONE2)) {
910 ret = pwrap_init(wrp);
911 if (ret) {
912 dev_dbg(wrp->dev, "init failed with %d\n", ret);
913 goto err_out2;
914 }
915 }
916
917 if (!(pwrap_readl(wrp, PWRAP_WACS2_RDATA) & PWRAP_STATE_INIT_DONE0)) {
918 dev_dbg(wrp->dev, "initialization isn't finished\n");
919 return -ENODEV;
920 }
921
bbe379fc
HC		 922 /* Initialize watchdog, may not be done by the bootloader */
923 pwrap_writel(wrp, 0xf, PWRAP_WDT_UNIT);
a3bbfbb0
HC		 924 /*
925 * Since STAUPD was not used on mt8173 platform,
926 * so STAUPD of WDT_SRC which should be turned off
927 */
928 wdt_src = pwrap_is_mt8173(wrp) ?
929 PWRAP_WDT_SRC_MASK_NO_STAUPD : PWRAP_WDT_SRC_MASK_ALL;
930 pwrap_writel(wrp, wdt_src, PWRAP_WDT_SRC_EN);
bbe379fc
HC		 931 pwrap_writel(wrp, 0x1, PWRAP_TIMER_EN);
932 pwrap_writel(wrp, ~((1 << 31) | (1 << 1)), PWRAP_INT_EN);
933
1f022d84
FF		 934 irq = platform_get_irq(pdev, 0);
935 ret = devm_request_irq(wrp->dev, irq, pwrap_interrupt, IRQF_TRIGGER_HIGH,
936 "mt-pmic-pwrap", wrp);
937 if (ret)
938 goto err_out2;
939
940 wrp->regmap = devm_regmap_init(wrp->dev, NULL, wrp, &pwrap_regmap_config);
941 if (IS_ERR(wrp->regmap))
942 return PTR_ERR(wrp->regmap);
943
944 ret = of_platform_populate(np, NULL, NULL, wrp->dev);
945 if (ret) {
946 dev_dbg(wrp->dev, "failed to create child devices at %s\n",
947 np->full_name);
948 goto err_out2;
949 }
950
951 return 0;
952
953err_out2:
954 clk_disable_unprepare(wrp->clk_wrap);
955err_out1:
956 clk_disable_unprepare(wrp->clk_spi);
957
958 return ret;
959}
960
961static struct platform_driver pwrap_drv = {
962 .driver = {
963 .name = "mt-pmic-pwrap",
1f022d84
FF		 964 .of_match_table = of_match_ptr(of_pwrap_match_tbl),
965 },
966 .probe = pwrap_probe,
967};
968
969module_platform_driver(pwrap_drv);
970
971MODULE_AUTHOR("Flora Fu, MediaTek");
972MODULE_DESCRIPTION("MediaTek MT8135 PMIC Wrapper Driver");
973MODULE_LICENSE("GPL v2");
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