[linux-2.6-block.git] / drivers / serial / uartlite.c

/*
 * uartlite.c: Serial driver for Xilinx uartlite serial controller
 *
 * Copyright (C) 2006 Peter Korsgaard <jacmet@sunsite.dk>
 * Copyright (C) 2007 Secret Lab Technologies Ltd.
 *
 * This file is licensed under the terms of the GNU General Public License
 * version 2.  This program is licensed "as is" without any warranty of any
 * kind, whether express or implied.
 */

#include <linux/platform_device.h>
#include <linux/module.h>
#include <linux/console.h>
#include <linux/serial.h>
#include <linux/serial_core.h>
#include <linux/tty.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/init.h>
#include <asm/io.h>
#if defined(CONFIG_OF) && (defined(CONFIG_PPC32) || defined(CONFIG_MICROBLAZE))
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
#include <linux/of_platform.h>

/* Match table for of_platform binding */
static struct of_device_id ulite_of_match[] __devinitdata = {
	{ .compatible = "xlnx,opb-uartlite-1.00.b", },
	{ .compatible = "xlnx,xps-uartlite-1.00.a", },
	{}
};
MODULE_DEVICE_TABLE(of, ulite_of_match);

#endif

#define ULITE_NAME		"ttyUL"
#define ULITE_MAJOR		204
#define ULITE_MINOR		187
#define ULITE_NR_UARTS		4

/* ---------------------------------------------------------------------
 * Register definitions
 *
 * For register details see datasheet:
 * http://www.xilinx.com/bvdocs/ipcenter/data_sheet/opb_uartlite.pdf
 */

#define ULITE_RX		0x00
#define ULITE_TX		0x04
#define ULITE_STATUS		0x08
#define ULITE_CONTROL		0x0c

#define ULITE_REGION		16

#define ULITE_STATUS_RXVALID	0x01
#define ULITE_STATUS_RXFULL	0x02
#define ULITE_STATUS_TXEMPTY	0x04
#define ULITE_STATUS_TXFULL	0x08
#define ULITE_STATUS_IE		0x10
#define ULITE_STATUS_OVERRUN	0x20
#define ULITE_STATUS_FRAME	0x40
#define ULITE_STATUS_PARITY	0x80

#define ULITE_CONTROL_RST_TX	0x01
#define ULITE_CONTROL_RST_RX	0x02
#define ULITE_CONTROL_IE	0x10


static struct uart_port ulite_ports[ULITE_NR_UARTS];

/* ---------------------------------------------------------------------
 * Core UART driver operations
 */

static int ulite_receive(struct uart_port *port, int stat)
{
	struct tty_struct *tty = port->state->port.tty;
	unsigned char ch = 0;
	char flag = TTY_NORMAL;

	if ((stat & (ULITE_STATUS_RXVALID | ULITE_STATUS_OVERRUN
		     | ULITE_STATUS_FRAME)) == 0)
		return 0;

	/* stats */
	if (stat & ULITE_STATUS_RXVALID) {
		port->icount.rx++;
		ch = ioread32be(port->membase + ULITE_RX);

		if (stat & ULITE_STATUS_PARITY)
			port->icount.parity++;
	}

	if (stat & ULITE_STATUS_OVERRUN)
		port->icount.overrun++;

	if (stat & ULITE_STATUS_FRAME)
		port->icount.frame++;


	/* drop byte with parity error if IGNPAR specificed */
	if (stat & port->ignore_status_mask & ULITE_STATUS_PARITY)
		stat &= ~ULITE_STATUS_RXVALID;

	stat &= port->read_status_mask;

	if (stat & ULITE_STATUS_PARITY)
		flag = TTY_PARITY;


	stat &= ~port->ignore_status_mask;

	if (stat & ULITE_STATUS_RXVALID)
		tty_insert_flip_char(tty, ch, flag);

	if (stat & ULITE_STATUS_FRAME)
		tty_insert_flip_char(tty, 0, TTY_FRAME);

	if (stat & ULITE_STATUS_OVERRUN)
		tty_insert_flip_char(tty, 0, TTY_OVERRUN);

	return 1;
}

static int ulite_transmit(struct uart_port *port, int stat)
{
	struct circ_buf *xmit  = &port->state->xmit;

	if (stat & ULITE_STATUS_TXFULL)
		return 0;

	if (port->x_char) {
		iowrite32be(port->x_char, port->membase + ULITE_TX);
		port->x_char = 0;
		port->icount.tx++;
		return 1;
	}

	if (uart_circ_empty(xmit) || uart_tx_stopped(port))
		return 0;

	iowrite32be(xmit->buf[xmit->tail], port->membase + ULITE_TX);
	xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE-1);
	port->icount.tx++;

	/* wake up */
	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
		uart_write_wakeup(port);

	return 1;
}

static irqreturn_t ulite_isr(int irq, void *dev_id)
{
	struct uart_port *port = dev_id;
	int busy, n = 0;

	do {
		int stat = ioread32be(port->membase + ULITE_STATUS);
		busy  = ulite_receive(port, stat);
		busy |= ulite_transmit(port, stat);
		n++;
	} while (busy);

	/* work done? */
	if (n > 1) {
		tty_flip_buffer_push(port->state->port.tty);
		return IRQ_HANDLED;
	} else {
		return IRQ_NONE;
	}
}

static unsigned int ulite_tx_empty(struct uart_port *port)
{
	unsigned long flags;
	unsigned int ret;

	spin_lock_irqsave(&port->lock, flags);
	ret = ioread32be(port->membase + ULITE_STATUS);
	spin_unlock_irqrestore(&port->lock, flags);

	return ret & ULITE_STATUS_TXEMPTY ? TIOCSER_TEMT : 0;
}

static unsigned int ulite_get_mctrl(struct uart_port *port)
{
	return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
}

static void ulite_set_mctrl(struct uart_port *port, unsigned int mctrl)
{
	/* N/A */
}

static void ulite_stop_tx(struct uart_port *port)
{
	/* N/A */
}

static void ulite_start_tx(struct uart_port *port)
{
	ulite_transmit(port, ioread32be(port->membase + ULITE_STATUS));
}

static void ulite_stop_rx(struct uart_port *port)
{
	/* don't forward any more data (like !CREAD) */
	port->ignore_status_mask = ULITE_STATUS_RXVALID | ULITE_STATUS_PARITY
		| ULITE_STATUS_FRAME | ULITE_STATUS_OVERRUN;
}

static void ulite_enable_ms(struct uart_port *port)
{
	/* N/A */
}

static void ulite_break_ctl(struct uart_port *port, int ctl)
{
	/* N/A */
}

static int ulite_startup(struct uart_port *port)
{
	int ret;

	ret = request_irq(port->irq, ulite_isr,
			  IRQF_SHARED | IRQF_SAMPLE_RANDOM, "uartlite", port);
	if (ret)
		return ret;

	iowrite32be(ULITE_CONTROL_RST_RX | ULITE_CONTROL_RST_TX,
	       port->membase + ULITE_CONTROL);
	iowrite32be(ULITE_CONTROL_IE, port->membase + ULITE_CONTROL);

	return 0;
}

static void ulite_shutdown(struct uart_port *port)
{
	iowrite32be(0, port->membase + ULITE_CONTROL);
	ioread32be(port->membase + ULITE_CONTROL); /* dummy */
	free_irq(port->irq, port);
}

static void ulite_set_termios(struct uart_port *port, struct ktermios *termios,
			      struct ktermios *old)
{
	unsigned long flags;
	unsigned int baud;

	spin_lock_irqsave(&port->lock, flags);

	port->read_status_mask = ULITE_STATUS_RXVALID | ULITE_STATUS_OVERRUN
		| ULITE_STATUS_TXFULL;

	if (termios->c_iflag & INPCK)
		port->read_status_mask |=
			ULITE_STATUS_PARITY | ULITE_STATUS_FRAME;

	port->ignore_status_mask = 0;
	if (termios->c_iflag & IGNPAR)
		port->ignore_status_mask |= ULITE_STATUS_PARITY
			| ULITE_STATUS_FRAME | ULITE_STATUS_OVERRUN;

	/* ignore all characters if CREAD is not set */
	if ((termios->c_cflag & CREAD) == 0)
		port->ignore_status_mask |=
			ULITE_STATUS_RXVALID | ULITE_STATUS_PARITY
			| ULITE_STATUS_FRAME | ULITE_STATUS_OVERRUN;

	/* update timeout */
	baud = uart_get_baud_rate(port, termios, old, 0, 460800);
	uart_update_timeout(port, termios->c_cflag, baud);

	spin_unlock_irqrestore(&port->lock, flags);
}

static const char *ulite_type(struct uart_port *port)
{
	return port->type == PORT_UARTLITE ? "uartlite" : NULL;
}

static void ulite_release_port(struct uart_port *port)
{
	release_mem_region(port->mapbase, ULITE_REGION);
	iounmap(port->membase);
	port->membase = NULL;
}

static int ulite_request_port(struct uart_port *port)
{
	pr_debug("ulite console: port=%p; port->mapbase=%llx\n",
		 port, (unsigned long long) port->mapbase);

	if (!request_mem_region(port->mapbase, ULITE_REGION, "uartlite")) {
		dev_err(port->dev, "Memory region busy\n");
		return -EBUSY;
	}

	port->membase = ioremap(port->mapbase, ULITE_REGION);
	if (!port->membase) {
		dev_err(port->dev, "Unable to map registers\n");
		release_mem_region(port->mapbase, ULITE_REGION);
		return -EBUSY;
	}

	return 0;
}

static void ulite_config_port(struct uart_port *port, int flags)
{
	if (!ulite_request_port(port))
		port->type = PORT_UARTLITE;
}

static int ulite_verify_port(struct uart_port *port, struct serial_struct *ser)
{
	/* we don't want the core code to modify any port params */
	return -EINVAL;
}

static struct uart_ops ulite_ops = {
	.tx_empty	= ulite_tx_empty,
	.set_mctrl	= ulite_set_mctrl,
	.get_mctrl	= ulite_get_mctrl,
	.stop_tx	= ulite_stop_tx,
	.start_tx	= ulite_start_tx,
	.stop_rx	= ulite_stop_rx,
	.enable_ms	= ulite_enable_ms,
	.break_ctl	= ulite_break_ctl,
	.startup	= ulite_startup,
	.shutdown	= ulite_shutdown,
	.set_termios	= ulite_set_termios,
	.type		= ulite_type,
	.release_port	= ulite_release_port,
	.request_port	= ulite_request_port,
	.config_port	= ulite_config_port,
	.verify_port	= ulite_verify_port
};

/* ---------------------------------------------------------------------
 * Console driver operations
 */

#ifdef CONFIG_SERIAL_UARTLITE_CONSOLE
static void ulite_console_wait_tx(struct uart_port *port)
{
	int i;
	u8 val;

	/* Spin waiting for TX fifo to have space available */
	for (i = 0; i < 100000; i++) {
		val = ioread32be(port->membase + ULITE_STATUS);
		if ((val & ULITE_STATUS_TXFULL) == 0)
			break;
		cpu_relax();
	}
}

static void ulite_console_putchar(struct uart_port *port, int ch)
{
	ulite_console_wait_tx(port);
	iowrite32be(ch, port->membase + ULITE_TX);
}

static void ulite_console_write(struct console *co, const char *s,
				unsigned int count)
{
	struct uart_port *port = &ulite_ports[co->index];
	unsigned long flags;
	unsigned int ier;
	int locked = 1;

	if (oops_in_progress) {
		locked = spin_trylock_irqsave(&port->lock, flags);
	} else
		spin_lock_irqsave(&port->lock, flags);

	/* save and disable interrupt */
	ier = ioread32be(port->membase + ULITE_STATUS) & ULITE_STATUS_IE;
	iowrite32be(0, port->membase + ULITE_CONTROL);

	uart_console_write(port, s, count, ulite_console_putchar);

	ulite_console_wait_tx(port);

	/* restore interrupt state */
	if (ier)
		iowrite32be(ULITE_CONTROL_IE, port->membase + ULITE_CONTROL);

	if (locked)
		spin_unlock_irqrestore(&port->lock, flags);
}

static int __devinit ulite_console_setup(struct console *co, char *options)
{
	struct uart_port *port;
	int baud = 9600;
	int bits = 8;
	int parity = 'n';
	int flow = 'n';

	if (co->index < 0 || co->index >= ULITE_NR_UARTS)
		return -EINVAL;

	port = &ulite_ports[co->index];

	/* Has the device been initialized yet? */
	if (!port->mapbase) {
		pr_debug("console on ttyUL%i not present\n", co->index);
		return -ENODEV;
	}

	/* not initialized yet? */
	if (!port->membase) {
		if (ulite_request_port(port))
			return -ENODEV;
	}

	if (options)
		uart_parse_options(options, &baud, &parity, &bits, &flow);

	return uart_set_options(port, co, baud, parity, bits, flow);
}

static struct uart_driver ulite_uart_driver;

static struct console ulite_console = {
	.name	= ULITE_NAME,
	.write	= ulite_console_write,
	.device	= uart_console_device,
	.setup	= ulite_console_setup,
	.flags	= CON_PRINTBUFFER,
	.index	= -1, /* Specified on the cmdline (e.g. console=ttyUL0 ) */
	.data	= &ulite_uart_driver,
};

static int __init ulite_console_init(void)
{
	register_console(&ulite_console);
	return 0;
}

console_initcall(ulite_console_init);

#endif /* CONFIG_SERIAL_UARTLITE_CONSOLE */

static struct uart_driver ulite_uart_driver = {
	.owner		= THIS_MODULE,
	.driver_name	= "uartlite",
	.dev_name	= ULITE_NAME,
	.major		= ULITE_MAJOR,
	.minor		= ULITE_MINOR,
	.nr		= ULITE_NR_UARTS,
#ifdef CONFIG_SERIAL_UARTLITE_CONSOLE
	.cons		= &ulite_console,
#endif
};

/* ---------------------------------------------------------------------
 * Port assignment functions (mapping devices to uart_port structures)
 */

/** ulite_assign: register a uartlite device with the driver
 *
 * @dev: pointer to device structure
 * @id: requested id number.  Pass -1 for automatic port assignment
 * @base: base address of uartlite registers
 * @irq: irq number for uartlite
 *
 * Returns: 0 on success, <0 otherwise
 */
static int __devinit ulite_assign(struct device *dev, int id, u32 base, int irq)
{
	struct uart_port *port;
	int rc;

	/* if id = -1; then scan for a free id and use that */
	if (id < 0) {
		for (id = 0; id < ULITE_NR_UARTS; id++)
			if (ulite_ports[id].mapbase == 0)
				break;
	}
	if (id < 0 || id >= ULITE_NR_UARTS) {
		dev_err(dev, "%s%i too large\n", ULITE_NAME, id);
		return -EINVAL;
	}

	if ((ulite_ports[id].mapbase) && (ulite_ports[id].mapbase != base)) {
		dev_err(dev, "cannot assign to %s%i; it is already in use\n",
			ULITE_NAME, id);
		return -EBUSY;
	}

	port = &ulite_ports[id];

	spin_lock_init(&port->lock);
	port->fifosize = 16;
	port->regshift = 2;
	port->iotype = UPIO_MEM;
	port->iobase = 1; /* mark port in use */
	port->mapbase = base;
	port->membase = NULL;
	port->ops = &ulite_ops;
	port->irq = irq;
	port->flags = UPF_BOOT_AUTOCONF;
	port->dev = dev;
	port->type = PORT_UNKNOWN;
	port->line = id;

	dev_set_drvdata(dev, port);

	/* Register the port */
	rc = uart_add_one_port(&ulite_uart_driver, port);
	if (rc) {
		dev_err(dev, "uart_add_one_port() failed; err=%i\n", rc);
		port->mapbase = 0;
		dev_set_drvdata(dev, NULL);
		return rc;
	}

	return 0;
}

/** ulite_release: register a uartlite device with the driver
 *
 * @dev: pointer to device structure
 */
static int __devexit ulite_release(struct device *dev)
{
	struct uart_port *port = dev_get_drvdata(dev);
	int rc = 0;

	if (port) {
		rc = uart_remove_one_port(&ulite_uart_driver, port);
		dev_set_drvdata(dev, NULL);
		port->mapbase = 0;
	}

	return rc;
}

/* ---------------------------------------------------------------------
 * Platform bus binding
 */

static int __devinit ulite_probe(struct platform_device *pdev)
{
	struct resource *res, *res2;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!res)
		return -ENODEV;

	res2 = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
	if (!res2)
		return -ENODEV;

	return ulite_assign(&pdev->dev, pdev->id, res->start, res2->start);
}

static int __devexit ulite_remove(struct platform_device *pdev)
{
	return ulite_release(&pdev->dev);
}

/* work with hotplug and coldplug */
MODULE_ALIAS("platform:uartlite");

static struct platform_driver ulite_platform_driver = {
	.probe	= ulite_probe,
	.remove	= __devexit_p(ulite_remove),
	.driver	= {
		   .owner = THIS_MODULE,
		   .name  = "uartlite",
		   },
};

/* ---------------------------------------------------------------------
 * OF bus bindings
 */
#if defined(CONFIG_OF) && (defined(CONFIG_PPC32) || defined(CONFIG_MICROBLAZE))
static int __devinit
ulite_of_probe(struct platform_device *op, const struct of_device_id *match)
{
	struct resource res;
	const unsigned int *id;
	int irq, rc;

	dev_dbg(&op->dev, "%s(%p, %p)\n", __func__, op, match);

	rc = of_address_to_resource(op->dev.of_node, 0, &res);
	if (rc) {
		dev_err(&op->dev, "invalid address\n");
		return rc;
	}

	irq = irq_of_parse_and_map(op->dev.of_node, 0);

	id = of_get_property(op->dev.of_node, "port-number", NULL);

	return ulite_assign(&op->dev, id ? *id : -1, res.start, irq);
}

static int __devexit ulite_of_remove(struct platform_device *op)
{
	return ulite_release(&op->dev);
}

static struct of_platform_driver ulite_of_driver = {
	.probe = ulite_of_probe,
	.remove = __devexit_p(ulite_of_remove),
	.driver = {
		.name = "uartlite",
		.owner = THIS_MODULE,
		.of_match_table = ulite_of_match,
	},
};

/* Registration helpers to keep the number of #ifdefs to a minimum */
static inline int __init ulite_of_register(void)
{
	pr_debug("uartlite: calling of_register_platform_driver()\n");
	return of_register_platform_driver(&ulite_of_driver);
}

static inline void __exit ulite_of_unregister(void)
{
	of_unregister_platform_driver(&ulite_of_driver);
}
#else /* CONFIG_OF && (CONFIG_PPC32 || CONFIG_MICROBLAZE) */
/* Appropriate config not enabled; do nothing helpers */
static inline int __init ulite_of_register(void) { return 0; }
static inline void __exit ulite_of_unregister(void) { }
#endif /* CONFIG_OF && (CONFIG_PPC32 || CONFIG_MICROBLAZE) */

/* ---------------------------------------------------------------------
 * Module setup/teardown
 */

int __init ulite_init(void)
{
	int ret;

	pr_debug("uartlite: calling uart_register_driver()\n");
	ret = uart_register_driver(&ulite_uart_driver);
	if (ret)
		goto err_uart;

	ret = ulite_of_register();
	if (ret)
		goto err_of;

	pr_debug("uartlite: calling platform_driver_register()\n");
	ret = platform_driver_register(&ulite_platform_driver);
	if (ret)
		goto err_plat;

	return 0;

err_plat:
	ulite_of_unregister();
err_of:
	uart_unregister_driver(&ulite_uart_driver);
err_uart:
	printk(KERN_ERR "registering uartlite driver failed: err=%i", ret);
	return ret;
}

void __exit ulite_exit(void)
{
	platform_driver_unregister(&ulite_platform_driver);
	ulite_of_unregister();
	uart_unregister_driver(&ulite_uart_driver);
}

module_init(ulite_init);
module_exit(ulite_exit);

MODULE_AUTHOR("Peter Korsgaard <jacmet@sunsite.dk>");
MODULE_DESCRIPTION("Xilinx uartlite serial driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
238b8721 PK	1	/*
	2	* uartlite.c: Serial driver for Xilinx uartlite serial controller
	3	*
852e1ea7 GL	4	* Copyright (C) 2006 Peter Korsgaard <jacmet@sunsite.dk>
852e1ea7 GL	5	* Copyright (C) 2007 Secret Lab Technologies Ltd.
238b8721 PK	6	*
	7	* This file is licensed under the terms of the GNU General Public License
	8	* version 2. This program is licensed "as is" without any warranty of any
	9	* kind, whether express or implied.
	10	*/
	11
	12	#include <linux/platform_device.h>
	13	#include <linux/module.h>
	14	#include <linux/console.h>
	15	#include <linux/serial.h>
	16	#include <linux/serial_core.h>
	17	#include <linux/tty.h>
	18	#include <linux/delay.h>
	19	#include <linux/interrupt.h>
0e349b0e	20	#include <linux/init.h>
238b8721	21	#include <asm/io.h>
07081fd8	22	#if defined(CONFIG_OF) && (defined(CONFIG_PPC32) \|\| defined(CONFIG_MICROBLAZE))
0e349b0e	23	#include <linux/of.h>
22ae782f	24	#include <linux/of_address.h>
852e1ea7 GL	25	#include <linux/of_device.h>
852e1ea7 GL	26	#include <linux/of_platform.h>
0e349b0e SN	27
	28	/* Match table for of_platform binding */
	29	static struct of_device_id ulite_of_match[] __devinitdata = {
	30	{ .compatible = "xlnx,opb-uartlite-1.00.b", },
	31	{ .compatible = "xlnx,xps-uartlite-1.00.a", },
	32	{}
	33	};
	34	MODULE_DEVICE_TABLE(of, ulite_of_match);
	35
852e1ea7	36	#endif
238b8721	37
00775828	38	#define ULITE_NAME "ttyUL"
238b8721 PK	39	#define ULITE_MAJOR 204
	40	#define ULITE_MINOR 187
	41	#define ULITE_NR_UARTS 4
	42
435706b3 GL	43	/* ---------------------------------------------------------------------
	44	* Register definitions
	45	*
	46	* For register details see datasheet:
	47	* http://www.xilinx.com/bvdocs/ipcenter/data_sheet/opb_uartlite.pdf
	48	*/
	49
238b8721 PK	50	#define ULITE_RX 0x00
	51	#define ULITE_TX 0x04
	52	#define ULITE_STATUS 0x08
	53	#define ULITE_CONTROL 0x0c
	54
	55	#define ULITE_REGION 16
	56
	57	#define ULITE_STATUS_RXVALID 0x01
	58	#define ULITE_STATUS_RXFULL 0x02
	59	#define ULITE_STATUS_TXEMPTY 0x04
	60	#define ULITE_STATUS_TXFULL 0x08
	61	#define ULITE_STATUS_IE 0x10
	62	#define ULITE_STATUS_OVERRUN 0x20
	63	#define ULITE_STATUS_FRAME 0x40
	64	#define ULITE_STATUS_PARITY 0x80
	65
	66	#define ULITE_CONTROL_RST_TX 0x01
	67	#define ULITE_CONTROL_RST_RX 0x02
	68	#define ULITE_CONTROL_IE 0x10
	69
	70
483c79db	71	static struct uart_port ulite_ports[ULITE_NR_UARTS];
238b8721	72
435706b3 GL	73	/* ---------------------------------------------------------------------
	74	* Core UART driver operations
	75	*/
	76
238b8721 PK	77	static int ulite_receive(struct uart_port *port, int stat)
238b8721 PK	78	{
ebd2c8f6	79	struct tty_struct *tty = port->state->port.tty;
238b8721 PK	80	unsigned char ch = 0;
	81	char flag = TTY_NORMAL;
	82
	83	if ((stat & (ULITE_STATUS_RXVALID \| ULITE_STATUS_OVERRUN
	84	\| ULITE_STATUS_FRAME)) == 0)
	85	return 0;
	86
	87	/* stats */
	88	if (stat & ULITE_STATUS_RXVALID) {
	89	port->icount.rx++;
e5bbbb18	90	ch = ioread32be(port->membase + ULITE_RX);
238b8721 PK	91
	92	if (stat & ULITE_STATUS_PARITY)
	93	port->icount.parity++;
	94	}
	95
	96	if (stat & ULITE_STATUS_OVERRUN)
	97	port->icount.overrun++;
	98
	99	if (stat & ULITE_STATUS_FRAME)
	100	port->icount.frame++;
	101
	102
	103	/* drop byte with parity error if IGNPAR specificed */
	104	if (stat & port->ignore_status_mask & ULITE_STATUS_PARITY)
	105	stat &= ~ULITE_STATUS_RXVALID;
	106
	107	stat &= port->read_status_mask;
	108
	109	if (stat & ULITE_STATUS_PARITY)
	110	flag = TTY_PARITY;
	111
	112
	113	stat &= ~port->ignore_status_mask;
	114
	115	if (stat & ULITE_STATUS_RXVALID)
	116	tty_insert_flip_char(tty, ch, flag);
	117
	118	if (stat & ULITE_STATUS_FRAME)
	119	tty_insert_flip_char(tty, 0, TTY_FRAME);
	120
	121	if (stat & ULITE_STATUS_OVERRUN)
	122	tty_insert_flip_char(tty, 0, TTY_OVERRUN);
	123
	124	return 1;
	125	}
	126
	127	static int ulite_transmit(struct uart_port *port, int stat)
	128	{
ebd2c8f6	129	struct circ_buf *xmit = &port->state->xmit;
238b8721 PK	130
	131	if (stat & ULITE_STATUS_TXFULL)
	132	return 0;
	133
	134	if (port->x_char) {
e5bbbb18	135	iowrite32be(port->x_char, port->membase + ULITE_TX);
238b8721 PK	136	port->x_char = 0;
	137	port->icount.tx++;
	138	return 1;
	139	}
	140
	141	if (uart_circ_empty(xmit) \|\| uart_tx_stopped(port))
	142	return 0;
	143
e5bbbb18	144	iowrite32be(xmit->buf[xmit->tail], port->membase + ULITE_TX);
238b8721 PK	145	xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE-1);
	146	port->icount.tx++;
	147
	148	/* wake up */
	149	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
	150	uart_write_wakeup(port);
	151
	152	return 1;
	153	}
	154
	155	static irqreturn_t ulite_isr(int irq, void *dev_id)
	156	{
15aafa2f	157	struct uart_port *port = dev_id;
d2cfe962	158	int busy, n = 0;
238b8721 PK	159
238b8721 PK	160	do {
e5bbbb18	161	int stat = ioread32be(port->membase + ULITE_STATUS);
238b8721 PK	162	busy = ulite_receive(port, stat);
238b8721 PK	163	busy \|= ulite_transmit(port, stat);
d2cfe962	164	n++;
238b8721 PK	165	} while (busy);
238b8721 PK	166
d2cfe962 PK	167	/* work done? */
	168	if (n > 1) {
	169	tty_flip_buffer_push(port->state->port.tty);
	170	return IRQ_HANDLED;
	171	} else {
	172	return IRQ_NONE;
	173	}
238b8721 PK	174	}
	175
	176	static unsigned int ulite_tx_empty(struct uart_port *port)
	177	{
	178	unsigned long flags;
	179	unsigned int ret;
	180
	181	spin_lock_irqsave(&port->lock, flags);
e5bbbb18	182	ret = ioread32be(port->membase + ULITE_STATUS);
238b8721 PK	183	spin_unlock_irqrestore(&port->lock, flags);
	184
	185	return ret & ULITE_STATUS_TXEMPTY ? TIOCSER_TEMT : 0;
	186	}
	187
	188	static unsigned int ulite_get_mctrl(struct uart_port *port)
	189	{
	190	return TIOCM_CTS \| TIOCM_DSR \| TIOCM_CAR;
	191	}
	192
	193	static void ulite_set_mctrl(struct uart_port *port, unsigned int mctrl)
	194	{
	195	/* N/A */
	196	}
	197
	198	static void ulite_stop_tx(struct uart_port *port)
	199	{
	200	/* N/A */
	201	}
	202
	203	static void ulite_start_tx(struct uart_port *port)
	204	{
e5bbbb18	205	ulite_transmit(port, ioread32be(port->membase + ULITE_STATUS));
238b8721 PK	206	}
	207
	208	static void ulite_stop_rx(struct uart_port *port)
	209	{
	210	/* don't forward any more data (like !CREAD) */
	211	port->ignore_status_mask = ULITE_STATUS_RXVALID \| ULITE_STATUS_PARITY
	212	\| ULITE_STATUS_FRAME \| ULITE_STATUS_OVERRUN;
	213	}
	214
	215	static void ulite_enable_ms(struct uart_port *port)
	216	{
	217	/* N/A */
	218	}
	219
	220	static void ulite_break_ctl(struct uart_port *port, int ctl)
	221	{
	222	/* N/A */
	223	}
	224
	225	static int ulite_startup(struct uart_port *port)
	226	{
	227	int ret;
	228
	229	ret = request_irq(port->irq, ulite_isr,
d2cfe962	230	IRQF_SHARED \| IRQF_SAMPLE_RANDOM, "uartlite", port);
238b8721 PK	231	if (ret)
	232	return ret;
	233
e5bbbb18	234	iowrite32be(ULITE_CONTROL_RST_RX \| ULITE_CONTROL_RST_TX,
e077b50c	235	port->membase + ULITE_CONTROL);
e5bbbb18	236	iowrite32be(ULITE_CONTROL_IE, port->membase + ULITE_CONTROL);
238b8721 PK	237
	238	return 0;
	239	}
	240
	241	static void ulite_shutdown(struct uart_port *port)
	242	{
e5bbbb18 JL	243	iowrite32be(0, port->membase + ULITE_CONTROL);
e5bbbb18 JL	244	ioread32be(port->membase + ULITE_CONTROL); /* dummy */
238b8721 PK	245	free_irq(port->irq, port);
	246	}
	247
606d099c AC	248	static void ulite_set_termios(struct uart_port port, struct ktermios termios,
606d099c AC	249	struct ktermios *old)
238b8721 PK	250	{
	251	unsigned long flags;
	252	unsigned int baud;
	253
	254	spin_lock_irqsave(&port->lock, flags);
	255
	256	port->read_status_mask = ULITE_STATUS_RXVALID \| ULITE_STATUS_OVERRUN
	257	\| ULITE_STATUS_TXFULL;
	258
	259	if (termios->c_iflag & INPCK)
	260	port->read_status_mask \|=
	261	ULITE_STATUS_PARITY \| ULITE_STATUS_FRAME;
	262
	263	port->ignore_status_mask = 0;
	264	if (termios->c_iflag & IGNPAR)
	265	port->ignore_status_mask \|= ULITE_STATUS_PARITY
	266	\| ULITE_STATUS_FRAME \| ULITE_STATUS_OVERRUN;
	267
	268	/* ignore all characters if CREAD is not set */
	269	if ((termios->c_cflag & CREAD) == 0)
	270	port->ignore_status_mask \|=
	271	ULITE_STATUS_RXVALID \| ULITE_STATUS_PARITY
	272	\| ULITE_STATUS_FRAME \| ULITE_STATUS_OVERRUN;
	273
	274	/* update timeout */
	275	baud = uart_get_baud_rate(port, termios, old, 0, 460800);
	276	uart_update_timeout(port, termios->c_cflag, baud);
	277
	278	spin_unlock_irqrestore(&port->lock, flags);
	279	}
	280
	281	static const char ulite_type(struct uart_port port)
	282	{
	283	return port->type == PORT_UARTLITE ? "uartlite" : NULL;
	284	}
	285
	286	static void ulite_release_port(struct uart_port *port)
	287	{
	288	release_mem_region(port->mapbase, ULITE_REGION);
	289	iounmap(port->membase);
b81831c6	290	port->membase = NULL;
238b8721 PK	291	}
	292
	293	static int ulite_request_port(struct uart_port *port)
	294	{
a1080968 GL	295	pr_debug("ulite console: port=%p; port->mapbase=%llx\n",
a1080968 GL	296	port, (unsigned long long) port->mapbase);
0e349b0e	297
238b8721 PK	298	if (!request_mem_region(port->mapbase, ULITE_REGION, "uartlite")) {
	299	dev_err(port->dev, "Memory region busy\n");
	300	return -EBUSY;
	301	}
	302
	303	port->membase = ioremap(port->mapbase, ULITE_REGION);
	304	if (!port->membase) {
	305	dev_err(port->dev, "Unable to map registers\n");
	306	release_mem_region(port->mapbase, ULITE_REGION);
	307	return -EBUSY;
	308	}
	309
	310	return 0;
	311	}
	312
	313	static void ulite_config_port(struct uart_port *port, int flags)
	314	{
e21654a7 PK	315	if (!ulite_request_port(port))
e21654a7 PK	316	port->type = PORT_UARTLITE;
238b8721 PK	317	}
	318
	319	static int ulite_verify_port(struct uart_port port, struct serial_struct ser)
	320	{
	321	/* we don't want the core code to modify any port params */
	322	return -EINVAL;
	323	}
	324
	325	static struct uart_ops ulite_ops = {
	326	.tx_empty = ulite_tx_empty,
	327	.set_mctrl = ulite_set_mctrl,
	328	.get_mctrl = ulite_get_mctrl,
	329	.stop_tx = ulite_stop_tx,
	330	.start_tx = ulite_start_tx,
	331	.stop_rx = ulite_stop_rx,
	332	.enable_ms = ulite_enable_ms,
	333	.break_ctl = ulite_break_ctl,
	334	.startup = ulite_startup,
	335	.shutdown = ulite_shutdown,
	336	.set_termios = ulite_set_termios,
	337	.type = ulite_type,
	338	.release_port = ulite_release_port,
	339	.request_port = ulite_request_port,
	340	.config_port = ulite_config_port,
	341	.verify_port = ulite_verify_port
	342	};
	343
435706b3 GL	344	/* ---------------------------------------------------------------------
	345	* Console driver operations
	346	*/
	347
238b8721 PK	348	#ifdef CONFIG_SERIAL_UARTLITE_CONSOLE
	349	static void ulite_console_wait_tx(struct uart_port *port)
	350	{
	351	int i;
1d6b6987	352	u8 val;
238b8721	353
1d6b6987 GL	354	/* Spin waiting for TX fifo to have space available */
1d6b6987 GL	355	for (i = 0; i < 100000; i++) {
e5bbbb18	356	val = ioread32be(port->membase + ULITE_STATUS);
1d6b6987	357	if ((val & ULITE_STATUS_TXFULL) == 0)
238b8721	358	break;
1d6b6987	359	cpu_relax();
238b8721 PK	360	}
	361	}
	362
	363	static void ulite_console_putchar(struct uart_port *port, int ch)
	364	{
	365	ulite_console_wait_tx(port);
e5bbbb18	366	iowrite32be(ch, port->membase + ULITE_TX);
238b8721 PK	367	}
	368
	369	static void ulite_console_write(struct console co, const char s,
	370	unsigned int count)
	371	{
483c79db	372	struct uart_port *port = &ulite_ports[co->index];
238b8721 PK	373	unsigned long flags;
	374	unsigned int ier;
	375	int locked = 1;
	376
	377	if (oops_in_progress) {
	378	locked = spin_trylock_irqsave(&port->lock, flags);
	379	} else
	380	spin_lock_irqsave(&port->lock, flags);
	381
	382	/* save and disable interrupt */
e5bbbb18 JL	383	ier = ioread32be(port->membase + ULITE_STATUS) & ULITE_STATUS_IE;
e5bbbb18 JL	384	iowrite32be(0, port->membase + ULITE_CONTROL);
238b8721 PK	385
	386	uart_console_write(port, s, count, ulite_console_putchar);
	387
	388	ulite_console_wait_tx(port);
	389
	390	/* restore interrupt state */
	391	if (ier)
e5bbbb18	392	iowrite32be(ULITE_CONTROL_IE, port->membase + ULITE_CONTROL);
238b8721 PK	393
	394	if (locked)
	395	spin_unlock_irqrestore(&port->lock, flags);
	396	}
	397
03eac7bb	398	static int __devinit ulite_console_setup(struct console co, char options)
238b8721 PK	399	{
	400	struct uart_port *port;
	401	int baud = 9600;
	402	int bits = 8;
	403	int parity = 'n';
	404	int flow = 'n';
	405
	406	if (co->index < 0 \|\| co->index >= ULITE_NR_UARTS)
	407	return -EINVAL;
	408
483c79db	409	port = &ulite_ports[co->index];
238b8721	410
3de66a17	411	/* Has the device been initialized yet? */
fb4e6e66 GL	412	if (!port->mapbase) {
	413	pr_debug("console on ttyUL%i not present\n", co->index);
	414	return -ENODEV;
	415	}
	416
238b8721	417	/* not initialized yet? */
852e1ea7	418	if (!port->membase) {
fb4e6e66 GL	419	if (ulite_request_port(port))
fb4e6e66 GL	420	return -ENODEV;
852e1ea7	421	}
238b8721 PK	422
	423	if (options)
	424	uart_parse_options(options, &baud, &parity, &bits, &flow);
	425
	426	return uart_set_options(port, co, baud, parity, bits, flow);
	427	}
	428
	429	static struct uart_driver ulite_uart_driver;
	430
	431	static struct console ulite_console = {
00775828	432	.name = ULITE_NAME,
238b8721 PK	433	.write = ulite_console_write,
	434	.device = uart_console_device,
	435	.setup = ulite_console_setup,
	436	.flags = CON_PRINTBUFFER,
	437	.index = -1, /* Specified on the cmdline (e.g. console=ttyUL0 ) */
	438	.data = &ulite_uart_driver,
	439	};
	440
	441	static int __init ulite_console_init(void)
	442	{
	443	register_console(&ulite_console);
	444	return 0;
	445	}
	446
	447	console_initcall(ulite_console_init);
	448
	449	#endif /* CONFIG_SERIAL_UARTLITE_CONSOLE */
	450
	451	static struct uart_driver ulite_uart_driver = {
	452	.owner = THIS_MODULE,
	453	.driver_name = "uartlite",
00775828	454	.dev_name = ULITE_NAME,
238b8721 PK	455	.major = ULITE_MAJOR,
	456	.minor = ULITE_MINOR,
	457	.nr = ULITE_NR_UARTS,
	458	#ifdef CONFIG_SERIAL_UARTLITE_CONSOLE
	459	.cons = &ulite_console,
	460	#endif
	461	};
	462
435706b3 GL	463	/* ---------------------------------------------------------------------
	464	* Port assignment functions (mapping devices to uart_port structures)
	465	*/
	466
	467	/** ulite_assign: register a uartlite device with the driver
	468	*
	469	* @dev: pointer to device structure
	470	* @id: requested id number. Pass -1 for automatic port assignment
	471	* @base: base address of uartlite registers
	472	* @irq: irq number for uartlite
	473	*
	474	* Returns: 0 on success, <0 otherwise
	475	*/
8fa7b610	476	static int __devinit ulite_assign(struct device *dev, int id, u32 base, int irq)
238b8721	477	{
238b8721	478	struct uart_port *port;
8fa7b610	479	int rc;
238b8721	480
8fa7b610 GL	481	/* if id = -1; then scan for a free id and use that */
	482	if (id < 0) {
	483	for (id = 0; id < ULITE_NR_UARTS; id++)
	484	if (ulite_ports[id].mapbase == 0)
	485	break;
	486	}
	487	if (id < 0 \|\| id >= ULITE_NR_UARTS) {
	488	dev_err(dev, "%s%i too large\n", ULITE_NAME, id);
238b8721	489	return -EINVAL;
8fa7b610	490	}
238b8721	491
fb4e6e66	492	if ((ulite_ports[id].mapbase) && (ulite_ports[id].mapbase != base)) {
8fa7b610 GL	493	dev_err(dev, "cannot assign to %s%i; it is already in use\n",
8fa7b610 GL	494	ULITE_NAME, id);
238b8721	495	return -EBUSY;
8fa7b610	496	}
238b8721	497
8fa7b610	498	port = &ulite_ports[id];
238b8721	499
8fa7b610 GL	500	spin_lock_init(&port->lock);
	501	port->fifosize = 16;
	502	port->regshift = 2;
	503	port->iotype = UPIO_MEM;
	504	port->iobase = 1; /* mark port in use */
	505	port->mapbase = base;
	506	port->membase = NULL;
	507	port->ops = &ulite_ops;
	508	port->irq = irq;
	509	port->flags = UPF_BOOT_AUTOCONF;
	510	port->dev = dev;
	511	port->type = PORT_UNKNOWN;
	512	port->line = id;
	513
	514	dev_set_drvdata(dev, port);
	515
	516	/* Register the port */
	517	rc = uart_add_one_port(&ulite_uart_driver, port);
	518	if (rc) {
	519	dev_err(dev, "uart_add_one_port() failed; err=%i\n", rc);
	520	port->mapbase = 0;
	521	dev_set_drvdata(dev, NULL);
	522	return rc;
	523	}
238b8721	524
8fa7b610 GL	525	return 0;
8fa7b610 GL	526	}
238b8721	527
435706b3 GL	528	/** ulite_release: register a uartlite device with the driver
	529	*
	530	* @dev: pointer to device structure
	531	*/
f67702a3	532	static int __devexit ulite_release(struct device *dev)
8fa7b610 GL	533	{
	534	struct uart_port *port = dev_get_drvdata(dev);
	535	int rc = 0;
238b8721	536
8fa7b610 GL	537	if (port) {
	538	rc = uart_remove_one_port(&ulite_uart_driver, port);
	539	dev_set_drvdata(dev, NULL);
	540	port->mapbase = 0;
	541	}
238b8721	542
8fa7b610	543	return rc;
238b8721 PK	544	}
238b8721 PK	545
435706b3 GL	546	/* ---------------------------------------------------------------------
	547	* Platform bus binding
	548	*/
	549
8fa7b610	550	static int __devinit ulite_probe(struct platform_device *pdev)
238b8721	551	{
8fa7b610	552	struct resource res, res2;
238b8721	553
8fa7b610 GL	554	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	555	if (!res)
	556	return -ENODEV;
238b8721	557
8fa7b610 GL	558	res2 = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
	559	if (!res2)
	560	return -ENODEV;
238b8721	561
8fa7b610 GL	562	return ulite_assign(&pdev->dev, pdev->id, res->start, res2->start);
8fa7b610 GL	563	}
238b8721	564
f67702a3	565	static int __devexit ulite_remove(struct platform_device *pdev)
8fa7b610 GL	566	{
8fa7b610 GL	567	return ulite_release(&pdev->dev);
238b8721 PK	568	}
238b8721 PK	569
e169c139 KS	570	/* work with hotplug and coldplug */
	571	MODULE_ALIAS("platform:uartlite");
	572
238b8721 PK	573	static struct platform_driver ulite_platform_driver = {
238b8721 PK	574	.probe = ulite_probe,
f67702a3	575	.remove = __devexit_p(ulite_remove),
238b8721 PK	576	.driver = {
	577	.owner = THIS_MODULE,
	578	.name = "uartlite",
	579	},
	580	};
	581
852e1ea7 GL	582	/* ---------------------------------------------------------------------
	583	* OF bus bindings
	584	*/
07081fd8	585	#if defined(CONFIG_OF) && (defined(CONFIG_PPC32) \|\| defined(CONFIG_MICROBLAZE))
852e1ea7	586	static int __devinit
2dc11581	587	ulite_of_probe(struct platform_device op, const struct of_device_id match)
852e1ea7 GL	588	{
	589	struct resource res;
	590	const unsigned int *id;
	591	int irq, rc;
	592
71cc2c21	593	dev_dbg(&op->dev, "%s(%p, %p)\n", __func__, op, match);
852e1ea7	594
61c7a080	595	rc = of_address_to_resource(op->dev.of_node, 0, &res);
852e1ea7	596	if (rc) {
e077b50c	597	dev_err(&op->dev, "invalid address\n");
852e1ea7 GL	598	return rc;
	599	}
	600
61c7a080	601	irq = irq_of_parse_and_map(op->dev.of_node, 0);
852e1ea7	602
61c7a080	603	id = of_get_property(op->dev.of_node, "port-number", NULL);
852e1ea7	604
e5bbbb18	605	return ulite_assign(&op->dev, id ? *id : -1, res.start, irq);
852e1ea7 GL	606	}
852e1ea7 GL	607
2dc11581	608	static int __devexit ulite_of_remove(struct platform_device *op)
852e1ea7 GL	609	{
	610	return ulite_release(&op->dev);
	611	}
	612
852e1ea7	613	static struct of_platform_driver ulite_of_driver = {
852e1ea7 GL	614	.probe = ulite_of_probe,
	615	.remove = __devexit_p(ulite_of_remove),
	616	.driver = {
	617	.name = "uartlite",
4018294b GL	618	.owner = THIS_MODULE,
4018294b GL	619	.of_match_table = ulite_of_match,
852e1ea7 GL	620	},
	621	};
	622
	623	/* Registration helpers to keep the number of #ifdefs to a minimum */
	624	static inline int __init ulite_of_register(void)
	625	{
	626	pr_debug("uartlite: calling of_register_platform_driver()\n");
	627	return of_register_platform_driver(&ulite_of_driver);
	628	}
	629
	630	static inline void __exit ulite_of_unregister(void)
	631	{
	632	of_unregister_platform_driver(&ulite_of_driver);
	633	}
07081fd8 DM	634	#else /* CONFIG_OF && (CONFIG_PPC32 \|\| CONFIG_MICROBLAZE) */
07081fd8 DM	635	/* Appropriate config not enabled; do nothing helpers */
852e1ea7 GL	636	static inline int __init ulite_of_register(void) { return 0; }
852e1ea7 GL	637	static inline void __exit ulite_of_unregister(void) { }
07081fd8	638	#endif /* CONFIG_OF && (CONFIG_PPC32 \|\| CONFIG_MICROBLAZE) */
852e1ea7	639
435706b3 GL	640	/* ---------------------------------------------------------------------
	641	* Module setup/teardown
	642	*/
	643
238b8721 PK	644	int __init ulite_init(void)
	645	{
	646	int ret;
	647
852e1ea7	648	pr_debug("uartlite: calling uart_register_driver()\n");
238b8721 PK	649	ret = uart_register_driver(&ulite_uart_driver);
238b8721 PK	650	if (ret)
852e1ea7 GL	651	goto err_uart;
	652
	653	ret = ulite_of_register();
	654	if (ret)
	655	goto err_of;
238b8721	656
852e1ea7	657	pr_debug("uartlite: calling platform_driver_register()\n");
238b8721 PK	658	ret = platform_driver_register(&ulite_platform_driver);
238b8721 PK	659	if (ret)
852e1ea7 GL	660	goto err_plat;
	661
	662	return 0;
238b8721	663
852e1ea7 GL	664	err_plat:
	665	ulite_of_unregister();
	666	err_of:
	667	uart_unregister_driver(&ulite_uart_driver);
	668	err_uart:
	669	printk(KERN_ERR "registering uartlite driver failed: err=%i", ret);
238b8721 PK	670	return ret;
	671	}
	672
	673	void __exit ulite_exit(void)
	674	{
	675	platform_driver_unregister(&ulite_platform_driver);
852e1ea7	676	ulite_of_unregister();
238b8721 PK	677	uart_unregister_driver(&ulite_uart_driver);
	678	}
	679
	680	module_init(ulite_init);
	681	module_exit(ulite_exit);
	682
	683	MODULE_AUTHOR("Peter Korsgaard <jacmet@sunsite.dk>");
	684	MODULE_DESCRIPTION("Xilinx uartlite serial driver");
	685	MODULE_LICENSE("GPL");