[linux-2.6-block.git] / drivers / serial / uartlite.c

/*
 * uartlite.c: Serial driver for Xilinx uartlite serial controller
 *
 * Copyright (C) 2006 Peter Korsgaard <jacmet@sunsite.dk>
 * Copyright (C) 2007 Secret Lab Technologies Ltd.
 *
 * This file is licensed under the terms of the GNU General Public License
 * version 2.  This program is licensed "as is" without any warranty of any
 * kind, whether express or implied.
 */

#include <linux/platform_device.h>
#include <linux/module.h>
#include <linux/console.h>
#include <linux/serial.h>
#include <linux/serial_core.h>
#include <linux/tty.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/init.h>
#include <asm/io.h>
#if defined(CONFIG_OF)
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/of_platform.h>

/* Match table for of_platform binding */
static struct of_device_id ulite_of_match[] __devinitdata = {
	{ .compatible = "xlnx,opb-uartlite-1.00.b", },
	{ .compatible = "xlnx,xps-uartlite-1.00.a", },
	{}
};
MODULE_DEVICE_TABLE(of, ulite_of_match);

#endif

#define ULITE_NAME		"ttyUL"
#define ULITE_MAJOR		204
#define ULITE_MINOR		187
#define ULITE_NR_UARTS		4

/* ---------------------------------------------------------------------
 * Register definitions
 *
 * For register details see datasheet:
 * http://www.xilinx.com/bvdocs/ipcenter/data_sheet/opb_uartlite.pdf
 */

#define ULITE_RX		0x00
#define ULITE_TX		0x04
#define ULITE_STATUS		0x08
#define ULITE_CONTROL		0x0c

#define ULITE_REGION		16

#define ULITE_STATUS_RXVALID	0x01
#define ULITE_STATUS_RXFULL	0x02
#define ULITE_STATUS_TXEMPTY	0x04
#define ULITE_STATUS_TXFULL	0x08
#define ULITE_STATUS_IE		0x10
#define ULITE_STATUS_OVERRUN	0x20
#define ULITE_STATUS_FRAME	0x40
#define ULITE_STATUS_PARITY	0x80

#define ULITE_CONTROL_RST_TX	0x01
#define ULITE_CONTROL_RST_RX	0x02
#define ULITE_CONTROL_IE	0x10


static struct uart_port ulite_ports[ULITE_NR_UARTS];

/* ---------------------------------------------------------------------
 * Core UART driver operations
 */

static int ulite_receive(struct uart_port *port, int stat)
{
	struct tty_struct *tty = port->info->port.tty;
	unsigned char ch = 0;
	char flag = TTY_NORMAL;

	if ((stat & (ULITE_STATUS_RXVALID | ULITE_STATUS_OVERRUN
		     | ULITE_STATUS_FRAME)) == 0)
		return 0;

	/* stats */
	if (stat & ULITE_STATUS_RXVALID) {
		port->icount.rx++;
		ch = readb(port->membase + ULITE_RX);

		if (stat & ULITE_STATUS_PARITY)
			port->icount.parity++;
	}

	if (stat & ULITE_STATUS_OVERRUN)
		port->icount.overrun++;

	if (stat & ULITE_STATUS_FRAME)
		port->icount.frame++;


	/* drop byte with parity error if IGNPAR specificed */
	if (stat & port->ignore_status_mask & ULITE_STATUS_PARITY)
		stat &= ~ULITE_STATUS_RXVALID;

	stat &= port->read_status_mask;

	if (stat & ULITE_STATUS_PARITY)
		flag = TTY_PARITY;


	stat &= ~port->ignore_status_mask;

	if (stat & ULITE_STATUS_RXVALID)
		tty_insert_flip_char(tty, ch, flag);

	if (stat & ULITE_STATUS_FRAME)
		tty_insert_flip_char(tty, 0, TTY_FRAME);

	if (stat & ULITE_STATUS_OVERRUN)
		tty_insert_flip_char(tty, 0, TTY_OVERRUN);

	return 1;
}

static int ulite_transmit(struct uart_port *port, int stat)
{
	struct circ_buf *xmit  = &port->info->xmit;

	if (stat & ULITE_STATUS_TXFULL)
		return 0;

	if (port->x_char) {
		writeb(port->x_char, port->membase + ULITE_TX);
		port->x_char = 0;
		port->icount.tx++;
		return 1;
	}

	if (uart_circ_empty(xmit) || uart_tx_stopped(port))
		return 0;

	writeb(xmit->buf[xmit->tail], port->membase + ULITE_TX);
	xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE-1);
	port->icount.tx++;

	/* wake up */
	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
		uart_write_wakeup(port);

	return 1;
}

static irqreturn_t ulite_isr(int irq, void *dev_id)
{
	struct uart_port *port = dev_id;
	int busy;

	do {
		int stat = readb(port->membase + ULITE_STATUS);
		busy  = ulite_receive(port, stat);
		busy |= ulite_transmit(port, stat);
	} while (busy);

	tty_flip_buffer_push(port->info->port.tty);

	return IRQ_HANDLED;
}

static unsigned int ulite_tx_empty(struct uart_port *port)
{
	unsigned long flags;
	unsigned int ret;

	spin_lock_irqsave(&port->lock, flags);
	ret = readb(port->membase + ULITE_STATUS);
	spin_unlock_irqrestore(&port->lock, flags);

	return ret & ULITE_STATUS_TXEMPTY ? TIOCSER_TEMT : 0;
}

static unsigned int ulite_get_mctrl(struct uart_port *port)
{
	return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
}

static void ulite_set_mctrl(struct uart_port *port, unsigned int mctrl)
{
	/* N/A */
}

static void ulite_stop_tx(struct uart_port *port)
{
	/* N/A */
}

static void ulite_start_tx(struct uart_port *port)
{
	ulite_transmit(port, readb(port->membase + ULITE_STATUS));
}

static void ulite_stop_rx(struct uart_port *port)
{
	/* don't forward any more data (like !CREAD) */
	port->ignore_status_mask = ULITE_STATUS_RXVALID | ULITE_STATUS_PARITY
		| ULITE_STATUS_FRAME | ULITE_STATUS_OVERRUN;
}

static void ulite_enable_ms(struct uart_port *port)
{
	/* N/A */
}

static void ulite_break_ctl(struct uart_port *port, int ctl)
{
	/* N/A */
}

static int ulite_startup(struct uart_port *port)
{
	int ret;

	ret = request_irq(port->irq, ulite_isr,
			  IRQF_DISABLED | IRQF_SAMPLE_RANDOM, "uartlite", port);
	if (ret)
		return ret;

	writeb(ULITE_CONTROL_RST_RX | ULITE_CONTROL_RST_TX,
	       port->membase + ULITE_CONTROL);
	writeb(ULITE_CONTROL_IE, port->membase + ULITE_CONTROL);

	return 0;
}

static void ulite_shutdown(struct uart_port *port)
{
	writeb(0, port->membase + ULITE_CONTROL);
	readb(port->membase + ULITE_CONTROL); /* dummy */
	free_irq(port->irq, port);
}

static void ulite_set_termios(struct uart_port *port, struct ktermios *termios,
			      struct ktermios *old)
{
	unsigned long flags;
	unsigned int baud;

	spin_lock_irqsave(&port->lock, flags);

	port->read_status_mask = ULITE_STATUS_RXVALID | ULITE_STATUS_OVERRUN
		| ULITE_STATUS_TXFULL;

	if (termios->c_iflag & INPCK)
		port->read_status_mask |=
			ULITE_STATUS_PARITY | ULITE_STATUS_FRAME;

	port->ignore_status_mask = 0;
	if (termios->c_iflag & IGNPAR)
		port->ignore_status_mask |= ULITE_STATUS_PARITY
			| ULITE_STATUS_FRAME | ULITE_STATUS_OVERRUN;

	/* ignore all characters if CREAD is not set */
	if ((termios->c_cflag & CREAD) == 0)
		port->ignore_status_mask |=
			ULITE_STATUS_RXVALID | ULITE_STATUS_PARITY
			| ULITE_STATUS_FRAME | ULITE_STATUS_OVERRUN;

	/* update timeout */
	baud = uart_get_baud_rate(port, termios, old, 0, 460800);
	uart_update_timeout(port, termios->c_cflag, baud);

	spin_unlock_irqrestore(&port->lock, flags);
}

static const char *ulite_type(struct uart_port *port)
{
	return port->type == PORT_UARTLITE ? "uartlite" : NULL;
}

static void ulite_release_port(struct uart_port *port)
{
	release_mem_region(port->mapbase, ULITE_REGION);
	iounmap(port->membase);
	port->membase = NULL;
}

static int ulite_request_port(struct uart_port *port)
{
	pr_debug("ulite console: port=%p; port->mapbase=%llx\n",
		 port, (unsigned long long) port->mapbase);

	if (!request_mem_region(port->mapbase, ULITE_REGION, "uartlite")) {
		dev_err(port->dev, "Memory region busy\n");
		return -EBUSY;
	}

	port->membase = ioremap(port->mapbase, ULITE_REGION);
	if (!port->membase) {
		dev_err(port->dev, "Unable to map registers\n");
		release_mem_region(port->mapbase, ULITE_REGION);
		return -EBUSY;
	}

	return 0;
}

static void ulite_config_port(struct uart_port *port, int flags)
{
	if (!ulite_request_port(port))
		port->type = PORT_UARTLITE;
}

static int ulite_verify_port(struct uart_port *port, struct serial_struct *ser)
{
	/* we don't want the core code to modify any port params */
	return -EINVAL;
}

static struct uart_ops ulite_ops = {
	.tx_empty	= ulite_tx_empty,
	.set_mctrl	= ulite_set_mctrl,
	.get_mctrl	= ulite_get_mctrl,
	.stop_tx	= ulite_stop_tx,
	.start_tx	= ulite_start_tx,
	.stop_rx	= ulite_stop_rx,
	.enable_ms	= ulite_enable_ms,
	.break_ctl	= ulite_break_ctl,
	.startup	= ulite_startup,
	.shutdown	= ulite_shutdown,
	.set_termios	= ulite_set_termios,
	.type		= ulite_type,
	.release_port	= ulite_release_port,
	.request_port	= ulite_request_port,
	.config_port	= ulite_config_port,
	.verify_port	= ulite_verify_port
};

/* ---------------------------------------------------------------------
 * Console driver operations
 */

#ifdef CONFIG_SERIAL_UARTLITE_CONSOLE
static void ulite_console_wait_tx(struct uart_port *port)
{
	int i;
	u8 val;

	/* Spin waiting for TX fifo to have space available */
	for (i = 0; i < 100000; i++) {
		val = readb(port->membase + ULITE_STATUS);
		if ((val & ULITE_STATUS_TXFULL) == 0)
			break;
		cpu_relax();
	}
}

static void ulite_console_putchar(struct uart_port *port, int ch)
{
	ulite_console_wait_tx(port);
	writeb(ch, port->membase + ULITE_TX);
}

static void ulite_console_write(struct console *co, const char *s,
				unsigned int count)
{
	struct uart_port *port = &ulite_ports[co->index];
	unsigned long flags;
	unsigned int ier;
	int locked = 1;

	if (oops_in_progress) {
		locked = spin_trylock_irqsave(&port->lock, flags);
	} else
		spin_lock_irqsave(&port->lock, flags);

	/* save and disable interrupt */
	ier = readb(port->membase + ULITE_STATUS) & ULITE_STATUS_IE;
	writeb(0, port->membase + ULITE_CONTROL);

	uart_console_write(port, s, count, ulite_console_putchar);

	ulite_console_wait_tx(port);

	/* restore interrupt state */
	if (ier)
		writeb(ULITE_CONTROL_IE, port->membase + ULITE_CONTROL);

	if (locked)
		spin_unlock_irqrestore(&port->lock, flags);
}

static int __init ulite_console_setup(struct console *co, char *options)
{
	struct uart_port *port;
	int baud = 9600;
	int bits = 8;
	int parity = 'n';
	int flow = 'n';

	if (co->index < 0 || co->index >= ULITE_NR_UARTS)
		return -EINVAL;

	port = &ulite_ports[co->index];

	/* Has the device been initialized yet? */
	if (!port->mapbase) {
		pr_debug("console on ttyUL%i not present\n", co->index);
		return -ENODEV;
	}

	/* not initialized yet? */
	if (!port->membase) {
		if (ulite_request_port(port))
			return -ENODEV;
	}

	if (options)
		uart_parse_options(options, &baud, &parity, &bits, &flow);

	return uart_set_options(port, co, baud, parity, bits, flow);
}

static struct uart_driver ulite_uart_driver;

static struct console ulite_console = {
	.name	= ULITE_NAME,
	.write	= ulite_console_write,
	.device	= uart_console_device,
	.setup	= ulite_console_setup,
	.flags	= CON_PRINTBUFFER,
	.index	= -1, /* Specified on the cmdline (e.g. console=ttyUL0 ) */
	.data	= &ulite_uart_driver,
};

static int __init ulite_console_init(void)
{
	register_console(&ulite_console);
	return 0;
}

console_initcall(ulite_console_init);

#endif /* CONFIG_SERIAL_UARTLITE_CONSOLE */

static struct uart_driver ulite_uart_driver = {
	.owner		= THIS_MODULE,
	.driver_name	= "uartlite",
	.dev_name	= ULITE_NAME,
	.major		= ULITE_MAJOR,
	.minor		= ULITE_MINOR,
	.nr		= ULITE_NR_UARTS,
#ifdef CONFIG_SERIAL_UARTLITE_CONSOLE
	.cons		= &ulite_console,
#endif
};

/* ---------------------------------------------------------------------
 * Port assignment functions (mapping devices to uart_port structures)
 */

/** ulite_assign: register a uartlite device with the driver
 *
 * @dev: pointer to device structure
 * @id: requested id number.  Pass -1 for automatic port assignment
 * @base: base address of uartlite registers
 * @irq: irq number for uartlite
 *
 * Returns: 0 on success, <0 otherwise
 */
static int __devinit ulite_assign(struct device *dev, int id, u32 base, int irq)
{
	struct uart_port *port;
	int rc;

	/* if id = -1; then scan for a free id and use that */
	if (id < 0) {
		for (id = 0; id < ULITE_NR_UARTS; id++)
			if (ulite_ports[id].mapbase == 0)
				break;
	}
	if (id < 0 || id >= ULITE_NR_UARTS) {
		dev_err(dev, "%s%i too large\n", ULITE_NAME, id);
		return -EINVAL;
	}

	if ((ulite_ports[id].mapbase) && (ulite_ports[id].mapbase != base)) {
		dev_err(dev, "cannot assign to %s%i; it is already in use\n",
			ULITE_NAME, id);
		return -EBUSY;
	}

	port = &ulite_ports[id];

	spin_lock_init(&port->lock);
	port->fifosize = 16;
	port->regshift = 2;
	port->iotype = UPIO_MEM;
	port->iobase = 1; /* mark port in use */
	port->mapbase = base;
	port->membase = NULL;
	port->ops = &ulite_ops;
	port->irq = irq;
	port->flags = UPF_BOOT_AUTOCONF;
	port->dev = dev;
	port->type = PORT_UNKNOWN;
	port->line = id;

	dev_set_drvdata(dev, port);

	/* Register the port */
	rc = uart_add_one_port(&ulite_uart_driver, port);
	if (rc) {
		dev_err(dev, "uart_add_one_port() failed; err=%i\n", rc);
		port->mapbase = 0;
		dev_set_drvdata(dev, NULL);
		return rc;
	}

	return 0;
}

/** ulite_release: register a uartlite device with the driver
 *
 * @dev: pointer to device structure
 */
static int __devexit ulite_release(struct device *dev)
{
	struct uart_port *port = dev_get_drvdata(dev);
	int rc = 0;

	if (port) {
		rc = uart_remove_one_port(&ulite_uart_driver, port);
		dev_set_drvdata(dev, NULL);
		port->mapbase = 0;
	}

	return rc;
}

/* ---------------------------------------------------------------------
 * Platform bus binding
 */

static int __devinit ulite_probe(struct platform_device *pdev)
{
	struct resource *res, *res2;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!res)
		return -ENODEV;

	res2 = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
	if (!res2)
		return -ENODEV;

	return ulite_assign(&pdev->dev, pdev->id, res->start, res2->start);
}

static int __devexit ulite_remove(struct platform_device *pdev)
{
	return ulite_release(&pdev->dev);
}

/* work with hotplug and coldplug */
MODULE_ALIAS("platform:uartlite");

static struct platform_driver ulite_platform_driver = {
	.probe	= ulite_probe,
	.remove	= __devexit_p(ulite_remove),
	.driver	= {
		   .owner = THIS_MODULE,
		   .name  = "uartlite",
		   },
};

/* ---------------------------------------------------------------------
 * OF bus bindings
 */
#if defined(CONFIG_OF)
static int __devinit
ulite_of_probe(struct of_device *op, const struct of_device_id *match)
{
	struct resource res;
	const unsigned int *id;
	int irq, rc;

	dev_dbg(&op->dev, "%s(%p, %p)\n", __func__, op, match);

	rc = of_address_to_resource(op->node, 0, &res);
	if (rc) {
		dev_err(&op->dev, "invalid address\n");
		return rc;
	}

	irq = irq_of_parse_and_map(op->node, 0);

	id = of_get_property(op->node, "port-number", NULL);

	return ulite_assign(&op->dev, id ? *id : -1, res.start+3, irq);
}

static int __devexit ulite_of_remove(struct of_device *op)
{
	return ulite_release(&op->dev);
}

static struct of_platform_driver ulite_of_driver = {
	.owner = THIS_MODULE,
	.name = "uartlite",
	.match_table = ulite_of_match,
	.probe = ulite_of_probe,
	.remove = __devexit_p(ulite_of_remove),
	.driver = {
		.name = "uartlite",
	},
};

/* Registration helpers to keep the number of #ifdefs to a minimum */
static inline int __init ulite_of_register(void)
{
	pr_debug("uartlite: calling of_register_platform_driver()\n");
	return of_register_platform_driver(&ulite_of_driver);
}

static inline void __exit ulite_of_unregister(void)
{
	of_unregister_platform_driver(&ulite_of_driver);
}
#else /* CONFIG_OF */
/* CONFIG_OF not enabled; do nothing helpers */
static inline int __init ulite_of_register(void) { return 0; }
static inline void __exit ulite_of_unregister(void) { }
#endif /* CONFIG_OF */

/* ---------------------------------------------------------------------
 * Module setup/teardown
 */

int __init ulite_init(void)
{
	int ret;

	pr_debug("uartlite: calling uart_register_driver()\n");
	ret = uart_register_driver(&ulite_uart_driver);
	if (ret)
		goto err_uart;

	ret = ulite_of_register();
	if (ret)
		goto err_of;

	pr_debug("uartlite: calling platform_driver_register()\n");
	ret = platform_driver_register(&ulite_platform_driver);
	if (ret)
		goto err_plat;

	return 0;

err_plat:
	ulite_of_unregister();
err_of:
	uart_unregister_driver(&ulite_uart_driver);
err_uart:
	printk(KERN_ERR "registering uartlite driver failed: err=%i", ret);
	return ret;
}

void __exit ulite_exit(void)
{
	platform_driver_unregister(&ulite_platform_driver);
	ulite_of_unregister();
	uart_unregister_driver(&ulite_uart_driver);
}

module_init(ulite_init);
module_exit(ulite_exit);

MODULE_AUTHOR("Peter Korsgaard <jacmet@sunsite.dk>");
MODULE_DESCRIPTION("Xilinx uartlite serial driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
238b8721 PK	1	/*
	2	* uartlite.c: Serial driver for Xilinx uartlite serial controller
	3	*
852e1ea7 GL	4	* Copyright (C) 2006 Peter Korsgaard <jacmet@sunsite.dk>
852e1ea7 GL	5	* Copyright (C) 2007 Secret Lab Technologies Ltd.
238b8721 PK	6	*
	7	* This file is licensed under the terms of the GNU General Public License
	8	* version 2. This program is licensed "as is" without any warranty of any
	9	* kind, whether express or implied.
	10	*/
	11
	12	#include <linux/platform_device.h>
	13	#include <linux/module.h>
	14	#include <linux/console.h>
	15	#include <linux/serial.h>
	16	#include <linux/serial_core.h>
	17	#include <linux/tty.h>
	18	#include <linux/delay.h>
	19	#include <linux/interrupt.h>
0e349b0e	20	#include <linux/init.h>
238b8721	21	#include <asm/io.h>
852e1ea7	22	#if defined(CONFIG_OF)
0e349b0e	23	#include <linux/of.h>
852e1ea7 GL	24	#include <linux/of_device.h>
852e1ea7 GL	25	#include <linux/of_platform.h>
0e349b0e SN	26
	27	/* Match table for of_platform binding */
	28	static struct of_device_id ulite_of_match[] __devinitdata = {
	29	{ .compatible = "xlnx,opb-uartlite-1.00.b", },
	30	{ .compatible = "xlnx,xps-uartlite-1.00.a", },
	31	{}
	32	};
	33	MODULE_DEVICE_TABLE(of, ulite_of_match);
	34
852e1ea7	35	#endif
238b8721	36
00775828	37	#define ULITE_NAME "ttyUL"
238b8721 PK	38	#define ULITE_MAJOR 204
	39	#define ULITE_MINOR 187
	40	#define ULITE_NR_UARTS 4
	41
435706b3 GL	42	/* ---------------------------------------------------------------------
	43	* Register definitions
	44	*
	45	* For register details see datasheet:
	46	* http://www.xilinx.com/bvdocs/ipcenter/data_sheet/opb_uartlite.pdf
	47	*/
	48
238b8721 PK	49	#define ULITE_RX 0x00
	50	#define ULITE_TX 0x04
	51	#define ULITE_STATUS 0x08
	52	#define ULITE_CONTROL 0x0c
	53
	54	#define ULITE_REGION 16
	55
	56	#define ULITE_STATUS_RXVALID 0x01
	57	#define ULITE_STATUS_RXFULL 0x02
	58	#define ULITE_STATUS_TXEMPTY 0x04
	59	#define ULITE_STATUS_TXFULL 0x08
	60	#define ULITE_STATUS_IE 0x10
	61	#define ULITE_STATUS_OVERRUN 0x20
	62	#define ULITE_STATUS_FRAME 0x40
	63	#define ULITE_STATUS_PARITY 0x80
	64
	65	#define ULITE_CONTROL_RST_TX 0x01
	66	#define ULITE_CONTROL_RST_RX 0x02
	67	#define ULITE_CONTROL_IE 0x10
	68
	69
483c79db	70	static struct uart_port ulite_ports[ULITE_NR_UARTS];
238b8721	71
435706b3 GL	72	/* ---------------------------------------------------------------------
	73	* Core UART driver operations
	74	*/
	75
238b8721 PK	76	static int ulite_receive(struct uart_port *port, int stat)
238b8721 PK	77	{
a88487c7	78	struct tty_struct *tty = port->info->port.tty;
238b8721 PK	79	unsigned char ch = 0;
	80	char flag = TTY_NORMAL;
	81
	82	if ((stat & (ULITE_STATUS_RXVALID \| ULITE_STATUS_OVERRUN
	83	\| ULITE_STATUS_FRAME)) == 0)
	84	return 0;
	85
	86	/* stats */
	87	if (stat & ULITE_STATUS_RXVALID) {
	88	port->icount.rx++;
e077b50c	89	ch = readb(port->membase + ULITE_RX);
238b8721 PK	90
	91	if (stat & ULITE_STATUS_PARITY)
	92	port->icount.parity++;
	93	}
	94
	95	if (stat & ULITE_STATUS_OVERRUN)
	96	port->icount.overrun++;
	97
	98	if (stat & ULITE_STATUS_FRAME)
	99	port->icount.frame++;
	100
	101
	102	/* drop byte with parity error if IGNPAR specificed */
	103	if (stat & port->ignore_status_mask & ULITE_STATUS_PARITY)
	104	stat &= ~ULITE_STATUS_RXVALID;
	105
	106	stat &= port->read_status_mask;
	107
	108	if (stat & ULITE_STATUS_PARITY)
	109	flag = TTY_PARITY;
	110
	111
	112	stat &= ~port->ignore_status_mask;
	113
	114	if (stat & ULITE_STATUS_RXVALID)
	115	tty_insert_flip_char(tty, ch, flag);
	116
	117	if (stat & ULITE_STATUS_FRAME)
	118	tty_insert_flip_char(tty, 0, TTY_FRAME);
	119
	120	if (stat & ULITE_STATUS_OVERRUN)
	121	tty_insert_flip_char(tty, 0, TTY_OVERRUN);
	122
	123	return 1;
	124	}
	125
	126	static int ulite_transmit(struct uart_port *port, int stat)
	127	{
	128	struct circ_buf *xmit = &port->info->xmit;
	129
	130	if (stat & ULITE_STATUS_TXFULL)
	131	return 0;
	132
	133	if (port->x_char) {
e077b50c	134	writeb(port->x_char, port->membase + ULITE_TX);
238b8721 PK	135	port->x_char = 0;
	136	port->icount.tx++;
	137	return 1;
	138	}
	139
	140	if (uart_circ_empty(xmit) \|\| uart_tx_stopped(port))
	141	return 0;
	142
e077b50c	143	writeb(xmit->buf[xmit->tail], port->membase + ULITE_TX);
238b8721 PK	144	xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE-1);
	145	port->icount.tx++;
	146
	147	/* wake up */
	148	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
	149	uart_write_wakeup(port);
	150
	151	return 1;
	152	}
	153
	154	static irqreturn_t ulite_isr(int irq, void *dev_id)
	155	{
15aafa2f	156	struct uart_port *port = dev_id;
238b8721 PK	157	int busy;
	158
	159	do {
e077b50c	160	int stat = readb(port->membase + ULITE_STATUS);
238b8721 PK	161	busy = ulite_receive(port, stat);
	162	busy \|= ulite_transmit(port, stat);
	163	} while (busy);
	164
a88487c7	165	tty_flip_buffer_push(port->info->port.tty);
238b8721 PK	166
	167	return IRQ_HANDLED;
	168	}
	169
	170	static unsigned int ulite_tx_empty(struct uart_port *port)
	171	{
	172	unsigned long flags;
	173	unsigned int ret;
	174
	175	spin_lock_irqsave(&port->lock, flags);
e077b50c	176	ret = readb(port->membase + ULITE_STATUS);
238b8721 PK	177	spin_unlock_irqrestore(&port->lock, flags);
	178
	179	return ret & ULITE_STATUS_TXEMPTY ? TIOCSER_TEMT : 0;
	180	}
	181
	182	static unsigned int ulite_get_mctrl(struct uart_port *port)
	183	{
	184	return TIOCM_CTS \| TIOCM_DSR \| TIOCM_CAR;
	185	}
	186
	187	static void ulite_set_mctrl(struct uart_port *port, unsigned int mctrl)
	188	{
	189	/* N/A */
	190	}
	191
	192	static void ulite_stop_tx(struct uart_port *port)
	193	{
	194	/* N/A */
	195	}
	196
	197	static void ulite_start_tx(struct uart_port *port)
	198	{
e077b50c	199	ulite_transmit(port, readb(port->membase + ULITE_STATUS));
238b8721 PK	200	}
	201
	202	static void ulite_stop_rx(struct uart_port *port)
	203	{
	204	/* don't forward any more data (like !CREAD) */
	205	port->ignore_status_mask = ULITE_STATUS_RXVALID \| ULITE_STATUS_PARITY
	206	\| ULITE_STATUS_FRAME \| ULITE_STATUS_OVERRUN;
	207	}
	208
	209	static void ulite_enable_ms(struct uart_port *port)
	210	{
	211	/* N/A */
	212	}
	213
	214	static void ulite_break_ctl(struct uart_port *port, int ctl)
	215	{
	216	/* N/A */
	217	}
	218
	219	static int ulite_startup(struct uart_port *port)
	220	{
	221	int ret;
	222
	223	ret = request_irq(port->irq, ulite_isr,
	224	IRQF_DISABLED \| IRQF_SAMPLE_RANDOM, "uartlite", port);
	225	if (ret)
	226	return ret;
	227
e077b50c GL	228	writeb(ULITE_CONTROL_RST_RX \| ULITE_CONTROL_RST_TX,
	229	port->membase + ULITE_CONTROL);
	230	writeb(ULITE_CONTROL_IE, port->membase + ULITE_CONTROL);
238b8721 PK	231
	232	return 0;
	233	}
	234
	235	static void ulite_shutdown(struct uart_port *port)
	236	{
e077b50c GL	237	writeb(0, port->membase + ULITE_CONTROL);
e077b50c GL	238	readb(port->membase + ULITE_CONTROL); /* dummy */
238b8721 PK	239	free_irq(port->irq, port);
	240	}
	241
606d099c AC	242	static void ulite_set_termios(struct uart_port port, struct ktermios termios,
606d099c AC	243	struct ktermios *old)
238b8721 PK	244	{
	245	unsigned long flags;
	246	unsigned int baud;
	247
	248	spin_lock_irqsave(&port->lock, flags);
	249
	250	port->read_status_mask = ULITE_STATUS_RXVALID \| ULITE_STATUS_OVERRUN
	251	\| ULITE_STATUS_TXFULL;
	252
	253	if (termios->c_iflag & INPCK)
	254	port->read_status_mask \|=
	255	ULITE_STATUS_PARITY \| ULITE_STATUS_FRAME;
	256
	257	port->ignore_status_mask = 0;
	258	if (termios->c_iflag & IGNPAR)
	259	port->ignore_status_mask \|= ULITE_STATUS_PARITY
	260	\| ULITE_STATUS_FRAME \| ULITE_STATUS_OVERRUN;
	261
	262	/* ignore all characters if CREAD is not set */
	263	if ((termios->c_cflag & CREAD) == 0)
	264	port->ignore_status_mask \|=
	265	ULITE_STATUS_RXVALID \| ULITE_STATUS_PARITY
	266	\| ULITE_STATUS_FRAME \| ULITE_STATUS_OVERRUN;
	267
	268	/* update timeout */
	269	baud = uart_get_baud_rate(port, termios, old, 0, 460800);
	270	uart_update_timeout(port, termios->c_cflag, baud);
	271
	272	spin_unlock_irqrestore(&port->lock, flags);
	273	}
	274
	275	static const char ulite_type(struct uart_port port)
	276	{
	277	return port->type == PORT_UARTLITE ? "uartlite" : NULL;
	278	}
	279
	280	static void ulite_release_port(struct uart_port *port)
	281	{
	282	release_mem_region(port->mapbase, ULITE_REGION);
	283	iounmap(port->membase);
b81831c6	284	port->membase = NULL;
238b8721 PK	285	}
	286
	287	static int ulite_request_port(struct uart_port *port)
	288	{
a1080968 GL	289	pr_debug("ulite console: port=%p; port->mapbase=%llx\n",
a1080968 GL	290	port, (unsigned long long) port->mapbase);
0e349b0e	291
238b8721 PK	292	if (!request_mem_region(port->mapbase, ULITE_REGION, "uartlite")) {
	293	dev_err(port->dev, "Memory region busy\n");
	294	return -EBUSY;
	295	}
	296
	297	port->membase = ioremap(port->mapbase, ULITE_REGION);
	298	if (!port->membase) {
	299	dev_err(port->dev, "Unable to map registers\n");
	300	release_mem_region(port->mapbase, ULITE_REGION);
	301	return -EBUSY;
	302	}
	303
	304	return 0;
	305	}
	306
	307	static void ulite_config_port(struct uart_port *port, int flags)
	308	{
e21654a7 PK	309	if (!ulite_request_port(port))
e21654a7 PK	310	port->type = PORT_UARTLITE;
238b8721 PK	311	}
	312
	313	static int ulite_verify_port(struct uart_port port, struct serial_struct ser)
	314	{
	315	/* we don't want the core code to modify any port params */
	316	return -EINVAL;
	317	}
	318
	319	static struct uart_ops ulite_ops = {
	320	.tx_empty = ulite_tx_empty,
	321	.set_mctrl = ulite_set_mctrl,
	322	.get_mctrl = ulite_get_mctrl,
	323	.stop_tx = ulite_stop_tx,
	324	.start_tx = ulite_start_tx,
	325	.stop_rx = ulite_stop_rx,
	326	.enable_ms = ulite_enable_ms,
	327	.break_ctl = ulite_break_ctl,
	328	.startup = ulite_startup,
	329	.shutdown = ulite_shutdown,
	330	.set_termios = ulite_set_termios,
	331	.type = ulite_type,
	332	.release_port = ulite_release_port,
	333	.request_port = ulite_request_port,
	334	.config_port = ulite_config_port,
	335	.verify_port = ulite_verify_port
	336	};
	337
435706b3 GL	338	/* ---------------------------------------------------------------------
	339	* Console driver operations
	340	*/
	341
238b8721 PK	342	#ifdef CONFIG_SERIAL_UARTLITE_CONSOLE
	343	static void ulite_console_wait_tx(struct uart_port *port)
	344	{
	345	int i;
1d6b6987	346	u8 val;
238b8721	347
1d6b6987 GL	348	/* Spin waiting for TX fifo to have space available */
	349	for (i = 0; i < 100000; i++) {
	350	val = readb(port->membase + ULITE_STATUS);
	351	if ((val & ULITE_STATUS_TXFULL) == 0)
238b8721	352	break;
1d6b6987	353	cpu_relax();
238b8721 PK	354	}
	355	}
	356
	357	static void ulite_console_putchar(struct uart_port *port, int ch)
	358	{
	359	ulite_console_wait_tx(port);
e077b50c	360	writeb(ch, port->membase + ULITE_TX);
238b8721 PK	361	}
	362
	363	static void ulite_console_write(struct console co, const char s,
	364	unsigned int count)
	365	{
483c79db	366	struct uart_port *port = &ulite_ports[co->index];
238b8721 PK	367	unsigned long flags;
	368	unsigned int ier;
	369	int locked = 1;
	370
	371	if (oops_in_progress) {
	372	locked = spin_trylock_irqsave(&port->lock, flags);
	373	} else
	374	spin_lock_irqsave(&port->lock, flags);
	375
	376	/* save and disable interrupt */
e077b50c GL	377	ier = readb(port->membase + ULITE_STATUS) & ULITE_STATUS_IE;
e077b50c GL	378	writeb(0, port->membase + ULITE_CONTROL);
238b8721 PK	379
	380	uart_console_write(port, s, count, ulite_console_putchar);
	381
	382	ulite_console_wait_tx(port);
	383
	384	/* restore interrupt state */
	385	if (ier)
e077b50c	386	writeb(ULITE_CONTROL_IE, port->membase + ULITE_CONTROL);
238b8721 PK	387
	388	if (locked)
	389	spin_unlock_irqrestore(&port->lock, flags);
	390	}
	391
	392	static int __init ulite_console_setup(struct console co, char options)
	393	{
	394	struct uart_port *port;
	395	int baud = 9600;
	396	int bits = 8;
	397	int parity = 'n';
	398	int flow = 'n';
	399
	400	if (co->index < 0 \|\| co->index >= ULITE_NR_UARTS)
	401	return -EINVAL;
	402
483c79db	403	port = &ulite_ports[co->index];
238b8721	404
3de66a17	405	/* Has the device been initialized yet? */
fb4e6e66 GL	406	if (!port->mapbase) {
	407	pr_debug("console on ttyUL%i not present\n", co->index);
	408	return -ENODEV;
	409	}
	410
238b8721	411	/* not initialized yet? */
852e1ea7	412	if (!port->membase) {
fb4e6e66 GL	413	if (ulite_request_port(port))
fb4e6e66 GL	414	return -ENODEV;
852e1ea7	415	}
238b8721 PK	416
	417	if (options)
	418	uart_parse_options(options, &baud, &parity, &bits, &flow);
	419
	420	return uart_set_options(port, co, baud, parity, bits, flow);
	421	}
	422
	423	static struct uart_driver ulite_uart_driver;
	424
	425	static struct console ulite_console = {
00775828	426	.name = ULITE_NAME,
238b8721 PK	427	.write = ulite_console_write,
	428	.device = uart_console_device,
	429	.setup = ulite_console_setup,
	430	.flags = CON_PRINTBUFFER,
	431	.index = -1, /* Specified on the cmdline (e.g. console=ttyUL0 ) */
	432	.data = &ulite_uart_driver,
	433	};
	434
	435	static int __init ulite_console_init(void)
	436	{
	437	register_console(&ulite_console);
	438	return 0;
	439	}
	440
	441	console_initcall(ulite_console_init);
	442
	443	#endif /* CONFIG_SERIAL_UARTLITE_CONSOLE */
	444
	445	static struct uart_driver ulite_uart_driver = {
	446	.owner = THIS_MODULE,
	447	.driver_name = "uartlite",
00775828	448	.dev_name = ULITE_NAME,
238b8721 PK	449	.major = ULITE_MAJOR,
	450	.minor = ULITE_MINOR,
	451	.nr = ULITE_NR_UARTS,
	452	#ifdef CONFIG_SERIAL_UARTLITE_CONSOLE
	453	.cons = &ulite_console,
	454	#endif
	455	};
	456
435706b3 GL	457	/* ---------------------------------------------------------------------
	458	* Port assignment functions (mapping devices to uart_port structures)
	459	*/
	460
	461	/** ulite_assign: register a uartlite device with the driver
	462	*
	463	* @dev: pointer to device structure
	464	* @id: requested id number. Pass -1 for automatic port assignment
	465	* @base: base address of uartlite registers
	466	* @irq: irq number for uartlite
	467	*
	468	* Returns: 0 on success, <0 otherwise
	469	*/
8fa7b610	470	static int __devinit ulite_assign(struct device *dev, int id, u32 base, int irq)
238b8721	471	{
238b8721	472	struct uart_port *port;
8fa7b610	473	int rc;
238b8721	474
8fa7b610 GL	475	/* if id = -1; then scan for a free id and use that */
	476	if (id < 0) {
	477	for (id = 0; id < ULITE_NR_UARTS; id++)
	478	if (ulite_ports[id].mapbase == 0)
	479	break;
	480	}
	481	if (id < 0 \|\| id >= ULITE_NR_UARTS) {
	482	dev_err(dev, "%s%i too large\n", ULITE_NAME, id);
238b8721	483	return -EINVAL;
8fa7b610	484	}
238b8721	485
fb4e6e66	486	if ((ulite_ports[id].mapbase) && (ulite_ports[id].mapbase != base)) {
8fa7b610 GL	487	dev_err(dev, "cannot assign to %s%i; it is already in use\n",
8fa7b610 GL	488	ULITE_NAME, id);
238b8721	489	return -EBUSY;
8fa7b610	490	}
238b8721	491
8fa7b610	492	port = &ulite_ports[id];
238b8721	493
8fa7b610 GL	494	spin_lock_init(&port->lock);
	495	port->fifosize = 16;
	496	port->regshift = 2;
	497	port->iotype = UPIO_MEM;
	498	port->iobase = 1; /* mark port in use */
	499	port->mapbase = base;
	500	port->membase = NULL;
	501	port->ops = &ulite_ops;
	502	port->irq = irq;
	503	port->flags = UPF_BOOT_AUTOCONF;
	504	port->dev = dev;
	505	port->type = PORT_UNKNOWN;
	506	port->line = id;
	507
	508	dev_set_drvdata(dev, port);
	509
	510	/* Register the port */
	511	rc = uart_add_one_port(&ulite_uart_driver, port);
	512	if (rc) {
	513	dev_err(dev, "uart_add_one_port() failed; err=%i\n", rc);
	514	port->mapbase = 0;
	515	dev_set_drvdata(dev, NULL);
	516	return rc;
	517	}
238b8721	518
8fa7b610 GL	519	return 0;
8fa7b610 GL	520	}
238b8721	521
435706b3 GL	522	/** ulite_release: register a uartlite device with the driver
	523	*
	524	* @dev: pointer to device structure
	525	*/
f67702a3	526	static int __devexit ulite_release(struct device *dev)
8fa7b610 GL	527	{
	528	struct uart_port *port = dev_get_drvdata(dev);
	529	int rc = 0;
238b8721	530
8fa7b610 GL	531	if (port) {
	532	rc = uart_remove_one_port(&ulite_uart_driver, port);
	533	dev_set_drvdata(dev, NULL);
	534	port->mapbase = 0;
	535	}
238b8721	536
8fa7b610	537	return rc;
238b8721 PK	538	}
238b8721 PK	539
435706b3 GL	540	/* ---------------------------------------------------------------------
	541	* Platform bus binding
	542	*/
	543
8fa7b610	544	static int __devinit ulite_probe(struct platform_device *pdev)
238b8721	545	{
8fa7b610	546	struct resource res, res2;
238b8721	547
8fa7b610 GL	548	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	549	if (!res)
	550	return -ENODEV;
238b8721	551
8fa7b610 GL	552	res2 = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
	553	if (!res2)
	554	return -ENODEV;
238b8721	555
8fa7b610 GL	556	return ulite_assign(&pdev->dev, pdev->id, res->start, res2->start);
8fa7b610 GL	557	}
238b8721	558
f67702a3	559	static int __devexit ulite_remove(struct platform_device *pdev)
8fa7b610 GL	560	{
8fa7b610 GL	561	return ulite_release(&pdev->dev);
238b8721 PK	562	}
238b8721 PK	563
e169c139 KS	564	/* work with hotplug and coldplug */
	565	MODULE_ALIAS("platform:uartlite");
	566
238b8721 PK	567	static struct platform_driver ulite_platform_driver = {
238b8721 PK	568	.probe = ulite_probe,
f67702a3	569	.remove = __devexit_p(ulite_remove),
238b8721 PK	570	.driver = {
	571	.owner = THIS_MODULE,
	572	.name = "uartlite",
	573	},
	574	};
	575
852e1ea7 GL	576	/* ---------------------------------------------------------------------
	577	* OF bus bindings
	578	*/
	579	#if defined(CONFIG_OF)
	580	static int __devinit
	581	ulite_of_probe(struct of_device op, const struct of_device_id match)
	582	{
	583	struct resource res;
	584	const unsigned int *id;
	585	int irq, rc;
	586
71cc2c21	587	dev_dbg(&op->dev, "%s(%p, %p)\n", __func__, op, match);
852e1ea7 GL	588
	589	rc = of_address_to_resource(op->node, 0, &res);
	590	if (rc) {
e077b50c	591	dev_err(&op->dev, "invalid address\n");
852e1ea7 GL	592	return rc;
	593	}
	594
	595	irq = irq_of_parse_and_map(op->node, 0);
	596
	597	id = of_get_property(op->node, "port-number", NULL);
	598
e077b50c	599	return ulite_assign(&op->dev, id ? *id : -1, res.start+3, irq);
852e1ea7 GL	600	}
	601
	602	static int __devexit ulite_of_remove(struct of_device *op)
	603	{
	604	return ulite_release(&op->dev);
	605	}
	606
852e1ea7 GL	607	static struct of_platform_driver ulite_of_driver = {
	608	.owner = THIS_MODULE,
	609	.name = "uartlite",
	610	.match_table = ulite_of_match,
	611	.probe = ulite_of_probe,
	612	.remove = __devexit_p(ulite_of_remove),
	613	.driver = {
	614	.name = "uartlite",
	615	},
	616	};
	617
	618	/* Registration helpers to keep the number of #ifdefs to a minimum */
	619	static inline int __init ulite_of_register(void)
	620	{
	621	pr_debug("uartlite: calling of_register_platform_driver()\n");
	622	return of_register_platform_driver(&ulite_of_driver);
	623	}
	624
	625	static inline void __exit ulite_of_unregister(void)
	626	{
	627	of_unregister_platform_driver(&ulite_of_driver);
	628	}
	629	#else /* CONFIG_OF */
	630	/* CONFIG_OF not enabled; do nothing helpers */
	631	static inline int __init ulite_of_register(void) { return 0; }
	632	static inline void __exit ulite_of_unregister(void) { }
	633	#endif /* CONFIG_OF */
	634
435706b3 GL	635	/* ---------------------------------------------------------------------
	636	* Module setup/teardown
	637	*/
	638
238b8721 PK	639	int __init ulite_init(void)
	640	{
	641	int ret;
	642
852e1ea7	643	pr_debug("uartlite: calling uart_register_driver()\n");
238b8721 PK	644	ret = uart_register_driver(&ulite_uart_driver);
238b8721 PK	645	if (ret)
852e1ea7 GL	646	goto err_uart;
	647
	648	ret = ulite_of_register();
	649	if (ret)
	650	goto err_of;
238b8721	651
852e1ea7	652	pr_debug("uartlite: calling platform_driver_register()\n");
238b8721 PK	653	ret = platform_driver_register(&ulite_platform_driver);
238b8721 PK	654	if (ret)
852e1ea7 GL	655	goto err_plat;
	656
	657	return 0;
238b8721	658
852e1ea7 GL	659	err_plat:
	660	ulite_of_unregister();
	661	err_of:
	662	uart_unregister_driver(&ulite_uart_driver);
	663	err_uart:
	664	printk(KERN_ERR "registering uartlite driver failed: err=%i", ret);
238b8721 PK	665	return ret;
	666	}
	667
	668	void __exit ulite_exit(void)
	669	{
	670	platform_driver_unregister(&ulite_platform_driver);
852e1ea7	671	ulite_of_unregister();
238b8721 PK	672	uart_unregister_driver(&ulite_uart_driver);
	673	}
	674
	675	module_init(ulite_init);
	676	module_exit(ulite_exit);
	677
	678	MODULE_AUTHOR("Peter Korsgaard <jacmet@sunsite.dk>");
	679	MODULE_DESCRIPTION("Xilinx uartlite serial driver");
	680	MODULE_LICENSE("GPL");