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Merge commit 'v2.6.34-rc2' into perf/core
[linux-2.6-block.git] / drivers / serial / sh-sci.h
CommitLineData
1da177e4 1#include <linux/serial_core.h>
edad1f20 2#include <linux/io.h>
69edbba0 3#include <linux/gpio.h>
3ea6bc3d 4
1da177e4
LT		 5#if defined(CONFIG_H83007) || defined(CONFIG_H83068)
6#include <asm/regs306x.h>
7#endif
8#if defined(CONFIG_H8S2678)
9#include <asm/regs267x.h>
10#endif
1da177e4 11
0fbde950
MD		 12#if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
13 defined(CONFIG_CPU_SUBTYPE_SH7707) || \
14 defined(CONFIG_CPU_SUBTYPE_SH7708) || \
15 defined(CONFIG_CPU_SUBTYPE_SH7709)
1da177e4
LT		 16# define SCPCR 0xA4000116 /* 16 bit SCI and SCIF */
17# define SCPDR 0xA4000136 /* 8 bit SCI and SCIF */
18# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
1da177e4
LT		 19#elif defined(CONFIG_CPU_SUBTYPE_SH7705)
20# define SCIF0 0xA4400000
21# define SCIF2 0xA4410000
b7a76e4b
PM		 22# define SCSMR_Ir 0xA44A0000
23# define IRDA_SCIF SCIF0
1da177e4
LT		 24# define SCPCR 0xA4000116
25# define SCPDR 0xA4000136
26
27/* Set the clock source,
28 * SCIF2 (0xA4410000) -> External clock, SCK pin used as clock input
29 * SCIF0 (0xA4400000) -> Internal clock, SCK pin as serial clock output
30 */
31# define SCSCR_INIT(port) (port->mapbase == SCIF2) ? 0xF3 : 0xF0
31a49c4b 32#elif defined(CONFIG_CPU_SUBTYPE_SH7720) || \
8a77b8d0
MD		 33 defined(CONFIG_CPU_SUBTYPE_SH7721) || \
34 defined(CONFIG_ARCH_SHMOBILE)
3ea6bc3d 35# define SCSCR_INIT(port) 0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */
fd88cac9
PM		 36# define PORT_PTCR 0xA405011EUL
37# define PORT_PVCR 0xA4050122UL
38# define SCIF_ORER 0x0200 /* overrun error bit */
1da177e4 39#elif defined(CONFIG_SH_RTS7751R2D)
7abc404a 40# define SCSPTR1 0xFFE0001C /* 8 bit SCIF */
1da177e4
LT		 41# define SCSPTR2 0xFFE80020 /* 16 bit SCIF */
42# define SCIF_ORER 0x0001 /* overrun error bit */
43# define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
05627486
PM		 44#elif defined(CONFIG_CPU_SUBTYPE_SH7750) || \
45 defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
46 defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
47 defined(CONFIG_CPU_SUBTYPE_SH7091) || \
48 defined(CONFIG_CPU_SUBTYPE_SH7751) || \
49 defined(CONFIG_CPU_SUBTYPE_SH7751R)
1da177e4
LT		 50# define SCSPTR1 0xffe0001c /* 8 bit SCI */
51# define SCSPTR2 0xFFE80020 /* 16 bit SCIF */
52# define SCIF_ORER 0x0001 /* overrun error bit */
53# define SCSCR_INIT(port) (((port)->type == PORT_SCI) ? \
54 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ : \
55 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ )
1da177e4 56#elif defined(CONFIG_CPU_SUBTYPE_SH7760)
b7a76e4b
PM		 57# define SCSPTR0 0xfe600024 /* 16 bit SCIF */
58# define SCSPTR1 0xfe610024 /* 16 bit SCIF */
59# define SCSPTR2 0xfe620024 /* 16 bit SCIF */
1da177e4
LT		 60# define SCIF_ORER 0x0001 /* overrun error bit */
61# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
2b1bd1ac 62#elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
e108b2ca 63# define SCSPTR0 0xA4400000 /* 16 bit SCIF */
9465a54f
NI		 64# define SCIF_ORER 0x0001 /* overrun error bit */
65# define PACR 0xa4050100
66# define PBCR 0xa4050102
67# define SCSCR_INIT(port) 0x3B
e108b2ca
PM		 68#elif defined(CONFIG_CPU_SUBTYPE_SH7343)
69# define SCSPTR0 0xffe00010 /* 16 bit SCIF */
70# define SCSPTR1 0xffe10010 /* 16 bit SCIF */
71# define SCSPTR2 0xffe20010 /* 16 bit SCIF */
72# define SCSPTR3 0xffe30010 /* 16 bit SCIF */
73# define SCSCR_INIT(port) 0x32 /* TIE=0,RIE=0,TE=1,RE=1,REIE=0,CKE=1 */
41504c39 74#elif defined(CONFIG_CPU_SUBTYPE_SH7722)
346b7463
MD		 75# define PADR 0xA4050120
76# define PSDR 0xA405013e
77# define PWDR 0xA4050166
78# define PSCR 0xA405011E
41504c39
PM		 79# define SCIF_ORER 0x0001 /* overrun error bit */
80# define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
9109a30e
MD		 81#elif defined(CONFIG_CPU_SUBTYPE_SH7366)
82# define SCPDR0 0xA405013E /* 16 bit SCIF0 PSDR */
83# define SCSPTR0 SCPDR0
84# define SCIF_ORER 0x0001 /* overrun error bit */
85# define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
178dd0cd
PM		 86#elif defined(CONFIG_CPU_SUBTYPE_SH7723)
87# define SCSPTR0 0xa4050160
88# define SCSPTR1 0xa405013e
89# define SCSPTR2 0xa4050160
90# define SCSPTR3 0xa405013e
91# define SCSPTR4 0xa4050128
92# define SCSPTR5 0xa4050128
93# define SCIF_ORER 0x0001 /* overrun error bit */
94# define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
47948d2b
KM		 95#elif defined(CONFIG_CPU_SUBTYPE_SH7724)
96# define SCIF_ORER 0x0001 /* overrun error bit */
97# define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
1da177e4 98#elif defined(CONFIG_CPU_SUBTYPE_SH4_202)
1da177e4
LT		 99# define SCSPTR2 0xffe80020 /* 16 bit SCIF */
100# define SCIF_ORER 0x0001 /* overrun error bit */
101# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
1da177e4 102#elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103)
1da177e4
LT		 103# define SCIF_BASE_ADDR 0x01030000
104# define SCIF_ADDR_SH5 PHYS_PERIPHERAL_BLOCK+SCIF_BASE_ADDR
105# define SCIF_PTR2_OFFS 0x0000020
106# define SCIF_LSR2_OFFS 0x0000024
1da177e4
LT		 107# define SCSPTR2 ((port->mapbase)+SCIF_PTR2_OFFS) /* 16 bit SCIF */
108# define SCLSR2 ((port->mapbase)+SCIF_LSR2_OFFS) /* 16 bit SCIF */
f9669187 109# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0, TE=1,RE=1,REIE=1 */
1da177e4 110#elif defined(CONFIG_H83007) || defined(CONFIG_H83068)
1da177e4 111# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
1da177e4
LT		 112# define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port)
113#elif defined(CONFIG_H8S2678)
1da177e4 114# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
1da177e4 115# define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port)
c01f0f1a
YS		 116#elif defined(CONFIG_CPU_SUBTYPE_SH7757)
117# define SCSPTR0 0xfe4b0020
118# define SCSPTR1 0xfe4b0020
119# define SCSPTR2 0xfe4b0020
120# define SCIF_ORER 0x0001
121# define SCSCR_INIT(port) 0x38
122# define SCIF_ONLY
7d740a06
YS		 123#elif defined(CONFIG_CPU_SUBTYPE_SH7763)
124# define SCSPTR0 0xffe00024 /* 16 bit SCIF */
125# define SCSPTR1 0xffe08024 /* 16 bit SCIF */
c63847a3 126# define SCSPTR2 0xffe10020 /* 16 bit SCIF/IRDA */
7d740a06 127# define SCIF_ORER 0x0001 /* overrun error bit */
c63847a3 128# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
b7a76e4b
PM		 129#elif defined(CONFIG_CPU_SUBTYPE_SH7770)
130# define SCSPTR0 0xff923020 /* 16 bit SCIF */
131# define SCSPTR1 0xff924020 /* 16 bit SCIF */
132# define SCSPTR2 0xff925020 /* 16 bit SCIF */
133# define SCIF_ORER 0x0001 /* overrun error bit */
134# define SCSCR_INIT(port) 0x3c /* TIE=0,RIE=0,TE=1,RE=1,REIE=1,cke=2 */
b7a76e4b
PM		 135#elif defined(CONFIG_CPU_SUBTYPE_SH7780)
136# define SCSPTR0 0xffe00024 /* 16 bit SCIF */
137# define SCSPTR1 0xffe10024 /* 16 bit SCIF */
e108b2ca 138# define SCIF_ORER 0x0001 /* Overrun error bit */
b7a76e4b 139# define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
55ba99eb
KM		 140#elif defined(CONFIG_CPU_SUBTYPE_SH7785) || \
141 defined(CONFIG_CPU_SUBTYPE_SH7786)
32351a28
PM		 142# define SCSPTR0 0xffea0024 /* 16 bit SCIF */
143# define SCSPTR1 0xffeb0024 /* 16 bit SCIF */
144# define SCSPTR2 0xffec0024 /* 16 bit SCIF */
145# define SCSPTR3 0xffed0024 /* 16 bit SCIF */
146# define SCSPTR4 0xffee0024 /* 16 bit SCIF */
147# define SCSPTR5 0xffef0024 /* 16 bit SCIF */
34aeb43e 148# define SCIF_ORER 0x0001 /* Overrun error bit */
32351a28 149# define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
2825999e
PG		 150#elif defined(CONFIG_CPU_SUBTYPE_SH7201) || \
151 defined(CONFIG_CPU_SUBTYPE_SH7203) || \
a8f67f4b
PM		 152 defined(CONFIG_CPU_SUBTYPE_SH7206) || \
153 defined(CONFIG_CPU_SUBTYPE_SH7263)
9d4436a6
YS		 154# define SCSPTR0 0xfffe8020 /* 16 bit SCIF */
155# define SCSPTR1 0xfffe8820 /* 16 bit SCIF */
156# define SCSPTR2 0xfffe9020 /* 16 bit SCIF */
157# define SCSPTR3 0xfffe9820 /* 16 bit SCIF */
2825999e
PG		 158# if defined(CONFIG_CPU_SUBTYPE_SH7201)
159# define SCSPTR4 0xfffeA020 /* 16 bit SCIF */
160# define SCSPTR5 0xfffeA820 /* 16 bit SCIF */
161# define SCSPTR6 0xfffeB020 /* 16 bit SCIF */
162# define SCSPTR7 0xfffeB820 /* 16 bit SCIF */
163# endif
9d4436a6 164# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
9d4436a6
YS		 165#elif defined(CONFIG_CPU_SUBTYPE_SH7619)
166# define SCSPTR0 0xf8400020 /* 16 bit SCIF */
167# define SCSPTR1 0xf8410020 /* 16 bit SCIF */
168# define SCSPTR2 0xf8420020 /* 16 bit SCIF */
169# define SCIF_ORER 0x0001 /* overrun error bit */
170# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
2b1bd1ac
PM		 171#elif defined(CONFIG_CPU_SUBTYPE_SHX3)
172# define SCSPTR0 0xffc30020 /* 16 bit SCIF */
173# define SCSPTR1 0xffc40020 /* 16 bit SCIF */
174# define SCSPTR2 0xffc50020 /* 16 bit SCIF */
175# define SCSPTR3 0xffc60020 /* 16 bit SCIF */
176# define SCIF_ORER 0x0001 /* Overrun error bit */
177# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
1da177e4
LT		 178#else
179# error CPU subtype not defined
180#endif
181
182/* SCSCR */
183#define SCI_CTRL_FLAGS_TIE 0x80 /* all */
184#define SCI_CTRL_FLAGS_RIE 0x40 /* all */
185#define SCI_CTRL_FLAGS_TE 0x20 /* all */
186#define SCI_CTRL_FLAGS_RE 0x10 /* all */
05627486
PM		 187#if defined(CONFIG_CPU_SUBTYPE_SH7750) || \
188 defined(CONFIG_CPU_SUBTYPE_SH7091) || \
189 defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
a8884e34 190 defined(CONFIG_CPU_SUBTYPE_SH7722) || \
05627486
PM		 191 defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
192 defined(CONFIG_CPU_SUBTYPE_SH7751) || \
193 defined(CONFIG_CPU_SUBTYPE_SH7751R) || \
c63847a3 194 defined(CONFIG_CPU_SUBTYPE_SH7763) || \
05627486 195 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
2b1bd1ac 196 defined(CONFIG_CPU_SUBTYPE_SH7785) || \
55ba99eb 197 defined(CONFIG_CPU_SUBTYPE_SH7786) || \
2b1bd1ac 198 defined(CONFIG_CPU_SUBTYPE_SHX3)
1da177e4
LT		 199#define SCI_CTRL_FLAGS_REIE 0x08 /* 7750 SCIF */
200#else
201#define SCI_CTRL_FLAGS_REIE 0
202#endif
203/* SCI_CTRL_FLAGS_MPIE 0x08 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
204/* SCI_CTRL_FLAGS_TEIE 0x04 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
205/* SCI_CTRL_FLAGS_CKE1 0x02 * all */
206/* SCI_CTRL_FLAGS_CKE0 0x01 * 7707 SCI/SCIF, 7708 SCI, 7709 SCI/SCIF, 7750 SCI */
207
208/* SCxSR SCI */
209#define SCI_TDRE 0x80 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
210#define SCI_RDRF 0x40 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
211#define SCI_ORER 0x20 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
212#define SCI_FER 0x10 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
213#define SCI_PER 0x08 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
214#define SCI_TEND 0x04 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
215/* SCI_MPB 0x02 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
216/* SCI_MPBT 0x01 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
217
218#define SCI_ERRORS ( SCI_PER | SCI_FER | SCI_ORER)
219
220/* SCxSR SCIF */
221#define SCIF_ER 0x0080 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
222#define SCIF_TEND 0x0040 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
223#define SCIF_TDFE 0x0020 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
224#define SCIF_BRK 0x0010 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
225#define SCIF_FER 0x0008 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
226#define SCIF_PER 0x0004 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
227#define SCIF_RDF 0x0002 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
228#define SCIF_DR 0x0001 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
229
3ea6bc3d 230#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
31a49c4b 231 defined(CONFIG_CPU_SUBTYPE_SH7720) || \
8a77b8d0
MD		 232 defined(CONFIG_CPU_SUBTYPE_SH7721) || \
233 defined(CONFIG_ARCH_SHMOBILE)
c63847a3
NI		 234# define SCIF_ORER 0x0200
235# define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK | SCIF_ORER)
236# define SCIF_RFDC_MASK 0x007f
237# define SCIF_TXROOM_MAX 64
238#elif defined(CONFIG_CPU_SUBTYPE_SH7763)
239# define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK )
240# define SCIF_RFDC_MASK 0x007f
241# define SCIF_TXROOM_MAX 64
242/* SH7763 SCIF2 support */
243# define SCIF2_RFDC_MASK 0x001f
244# define SCIF2_TXROOM_MAX 16
1da177e4 245#else
c63847a3
NI		 246# define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK)
247# define SCIF_RFDC_MASK 0x001f
248# define SCIF_TXROOM_MAX 16
1da177e4
LT		 249#endif
250
d830fa45
PM		 251#ifndef SCIF_ORER
252#define SCIF_ORER 0x0000
253#endif
254
15c73aaa
PM		 255#define SCxSR_TEND(port) (((port)->type == PORT_SCI) ? SCI_TEND : SCIF_TEND)
256#define SCxSR_ERRORS(port) (((port)->type == PORT_SCI) ? SCI_ERRORS : SCIF_ERRORS)
257#define SCxSR_RDxF(port) (((port)->type == PORT_SCI) ? SCI_RDRF : SCIF_RDF)
258#define SCxSR_TDxE(port) (((port)->type == PORT_SCI) ? SCI_TDRE : SCIF_TDFE)
259#define SCxSR_FER(port) (((port)->type == PORT_SCI) ? SCI_FER : SCIF_FER)
260#define SCxSR_PER(port) (((port)->type == PORT_SCI) ? SCI_PER : SCIF_PER)
261#define SCxSR_BRK(port) (((port)->type == PORT_SCI) ? 0x00 : SCIF_BRK)
d830fa45 262#define SCxSR_ORER(port) (((port)->type == PORT_SCI) ? SCI_ORER : SCIF_ORER)
15c73aaa 263
3ea6bc3d 264#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
31a49c4b 265 defined(CONFIG_CPU_SUBTYPE_SH7720) || \
8a77b8d0
MD		 266 defined(CONFIG_CPU_SUBTYPE_SH7721) || \
267 defined(CONFIG_ARCH_SHMOBILE)
15c73aaa
PM		 268# define SCxSR_RDxF_CLEAR(port) (sci_in(port, SCxSR) & 0xfffc)
269# define SCxSR_ERROR_CLEAR(port) (sci_in(port, SCxSR) & 0xfd73)
270# define SCxSR_TDxE_CLEAR(port) (sci_in(port, SCxSR) & 0xffdf)
271# define SCxSR_BREAK_CLEAR(port) (sci_in(port, SCxSR) & 0xffe3)
1da177e4 272#else
1da177e4
LT		 273# define SCxSR_RDxF_CLEAR(port) (((port)->type == PORT_SCI) ? 0xbc : 0x00fc)
274# define SCxSR_ERROR_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x0073)
275# define SCxSR_TDxE_CLEAR(port) (((port)->type == PORT_SCI) ? 0x78 : 0x00df)
276# define SCxSR_BREAK_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x00e3)
277#endif
278
279/* SCFCR */
280#define SCFCR_RFRST 0x0002
281#define SCFCR_TFRST 0x0004
282#define SCFCR_TCRST 0x4000
283#define SCFCR_MCE 0x0008
284
285#define SCI_MAJOR 204
286#define SCI_MINOR_START 8
287
288/* Generic serial flags */
289#define SCI_RX_THROTTLE 0x0000001
290
291#define SCI_MAGIC 0xbabeface
292
293/*
294 * Events are used to schedule things to happen at timer-interrupt
295 * time, instead of at rs interrupt time.
296 */
297#define SCI_EVENT_WRITE_WAKEUP 0
298
1da177e4 299#define SCI_IN(size, offset) \
b7a76e4b 300 if ((size) == 8) { \
7ff731ae 301 return ioread8(port->membase + (offset)); \
b7a76e4b 302 } else { \
7ff731ae 303 return ioread16(port->membase + (offset)); \
1da177e4
LT		 304 }
305#define SCI_OUT(size, offset, value) \
b7a76e4b 306 if ((size) == 8) { \
7ff731ae 307 iowrite8(value, port->membase + (offset)); \
3d2c2f3e 308 } else if ((size) == 16) { \
7ff731ae 309 iowrite16(value, port->membase + (offset)); \
1da177e4
LT		 310 }
311
312#define CPU_SCIx_FNS(name, sci_offset, sci_size, scif_offset, scif_size)\
313 static inline unsigned int sci_##name##_in(struct uart_port *port) \
314 { \
1a22f08d
YS		 315 if (port->type == PORT_SCIF) { \
316 SCI_IN(scif_size, scif_offset) \
317 } else { /* PORT_SCI or PORT_SCIFA */ \
318 SCI_IN(sci_size, sci_offset); \
1da177e4
LT		 319 } \
320 } \
321 static inline void sci_##name##_out(struct uart_port *port, unsigned int value) \
322 { \
1a22f08d
YS		 323 if (port->type == PORT_SCIF) { \
324 SCI_OUT(scif_size, scif_offset, value) \
325 } else { /* PORT_SCI or PORT_SCIFA */ \
326 SCI_OUT(sci_size, sci_offset, value); \
1da177e4
LT		 327 } \
328 }
329
168f3623
YS		 330#ifdef CONFIG_H8300
331/* h8300 don't have SCIF */
332#define CPU_SCIF_FNS(name) \
333 static inline unsigned int sci_##name##_in(struct uart_port *port) \
334 { \
335 return 0; \
336 } \
337 static inline void sci_##name##_out(struct uart_port *port, unsigned int value) \
338 { \
339 }
340#else
341#define CPU_SCIF_FNS(name, scif_offset, scif_size) \
1da177e4
LT		 342 static inline unsigned int sci_##name##_in(struct uart_port *port) \
343 { \
b7a76e4b 344 SCI_IN(scif_size, scif_offset); \
1da177e4
LT		 345 } \
346 static inline void sci_##name##_out(struct uart_port *port, unsigned int value) \
347 { \
348 SCI_OUT(scif_size, scif_offset, value); \
349 }
168f3623 350#endif
1da177e4
LT		 351
352#define CPU_SCI_FNS(name, sci_offset, sci_size) \
353 static inline unsigned int sci_##name##_in(struct uart_port* port) \
354 { \
b7a76e4b 355 SCI_IN(sci_size, sci_offset); \
1da177e4
LT		 356 } \
357 static inline void sci_##name##_out(struct uart_port* port, unsigned int value) \
358 { \
359 SCI_OUT(sci_size, sci_offset, value); \
360 }
361
8a77b8d0 362#if defined(CONFIG_CPU_SH3) || defined(CONFIG_ARCH_SHMOBILE)
9465a54f
NI		 363#if defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
364#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
365 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
366 h8_sci_offset, h8_sci_size) \
367 CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size, sh4_scif_offset, sh4_scif_size)
368#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
369 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
3ea6bc3d 370#elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \
31a49c4b 371 defined(CONFIG_CPU_SUBTYPE_SH7720) || \
8a77b8d0
MD		 372 defined(CONFIG_CPU_SUBTYPE_SH7721) || \
373 defined(CONFIG_ARCH_SHMOBILE)
1da177e4
LT		 374#define SCIF_FNS(name, scif_offset, scif_size) \
375 CPU_SCIF_FNS(name, scif_offset, scif_size)
376#else
377#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
378 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
379 h8_sci_offset, h8_sci_size) \
380 CPU_SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh3_scif_offset, sh3_scif_size)
381#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
382 CPU_SCIF_FNS(name, sh3_scif_offset, sh3_scif_size)
383#endif
384#elif defined(__H8300H__) || defined(__H8300S__)
385#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
386 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
387 h8_sci_offset, h8_sci_size) \
388 CPU_SCI_FNS(name, h8_sci_offset, h8_sci_size)
168f3623
YS		 389#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
390 CPU_SCIF_FNS(name)
47948d2b
KM		 391#elif defined(CONFIG_CPU_SUBTYPE_SH7723) ||\
392 defined(CONFIG_CPU_SUBTYPE_SH7724)
178dd0cd
PM		 393 #define SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size, sh4_scif_offset, sh4_scif_size) \
394 CPU_SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size, sh4_scif_offset, sh4_scif_size)
395 #define SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) \
396 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
1da177e4
LT		 397#else
398#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
399 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
400 h8_sci_offset, h8_sci_size) \
401 CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size, sh4_scif_offset, sh4_scif_size)
402#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
403 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
404#endif
405
3ea6bc3d 406#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
31a49c4b 407 defined(CONFIG_CPU_SUBTYPE_SH7720) || \
8a77b8d0
MD		 408 defined(CONFIG_CPU_SUBTYPE_SH7721) || \
409 defined(CONFIG_ARCH_SHMOBILE)
9465a54f 410
1da177e4
LT		 411SCIF_FNS(SCSMR, 0x00, 16)
412SCIF_FNS(SCBRR, 0x04, 8)
413SCIF_FNS(SCSCR, 0x08, 16)
414SCIF_FNS(SCTDSR, 0x0c, 8)
415SCIF_FNS(SCFER, 0x10, 16)
416SCIF_FNS(SCxSR, 0x14, 16)
417SCIF_FNS(SCFCR, 0x18, 16)
418SCIF_FNS(SCFDR, 0x1c, 16)
419SCIF_FNS(SCxTDR, 0x20, 8)
420SCIF_FNS(SCxRDR, 0x24, 8)
8a77b8d0 421SCIF_FNS(SCLSR, 0x00, 0)
47948d2b
KM		 422#elif defined(CONFIG_CPU_SUBTYPE_SH7723) ||\
423 defined(CONFIG_CPU_SUBTYPE_SH7724)
178dd0cd
PM		 424SCIx_FNS(SCSMR, 0x00, 16, 0x00, 16)
425SCIx_FNS(SCBRR, 0x04, 8, 0x04, 8)
426SCIx_FNS(SCSCR, 0x08, 16, 0x08, 16)
427SCIx_FNS(SCxTDR, 0x20, 8, 0x0c, 8)
428SCIx_FNS(SCxSR, 0x14, 16, 0x10, 16)
429SCIx_FNS(SCxRDR, 0x24, 8, 0x14, 8)
f686359e 430SCIx_FNS(SCSPTR, 0, 0, 0, 0)
178dd0cd
PM		 431SCIF_FNS(SCTDSR, 0x0c, 8)
432SCIF_FNS(SCFER, 0x10, 16)
433SCIF_FNS(SCFCR, 0x18, 16)
434SCIF_FNS(SCFDR, 0x1c, 16)
435SCIF_FNS(SCLSR, 0x24, 16)
1da177e4
LT		 436#else
437/* reg SCI/SH3 SCI/SH4 SCIF/SH3 SCIF/SH4 SCI/H8*/
438/* name off sz off sz off sz off sz off sz*/
439SCIx_FNS(SCSMR, 0x00, 8, 0x00, 8, 0x00, 8, 0x00, 16, 0x00, 8)
440SCIx_FNS(SCBRR, 0x02, 8, 0x04, 8, 0x02, 8, 0x04, 8, 0x01, 8)
441SCIx_FNS(SCSCR, 0x04, 8, 0x08, 8, 0x04, 8, 0x08, 16, 0x02, 8)
442SCIx_FNS(SCxTDR, 0x06, 8, 0x0c, 8, 0x06, 8, 0x0C, 8, 0x03, 8)
443SCIx_FNS(SCxSR, 0x08, 8, 0x10, 8, 0x08, 16, 0x10, 16, 0x04, 8)
444SCIx_FNS(SCxRDR, 0x0a, 8, 0x14, 8, 0x0A, 8, 0x14, 8, 0x05, 8)
445SCIF_FNS(SCFCR, 0x0c, 8, 0x18, 16)
32351a28
PM		 446#if defined(CONFIG_CPU_SUBTYPE_SH7760) || \
447 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
55ba99eb
KM		 448 defined(CONFIG_CPU_SUBTYPE_SH7785) || \
449 defined(CONFIG_CPU_SUBTYPE_SH7786)
c2697968 450SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16)
b7a76e4b
PM		 451SCIF_FNS(SCTFDR, 0x0e, 16, 0x1C, 16)
452SCIF_FNS(SCRFDR, 0x0e, 16, 0x20, 16)
453SCIF_FNS(SCSPTR, 0, 0, 0x24, 16)
454SCIF_FNS(SCLSR, 0, 0, 0x28, 16)
c2697968 455#elif defined(CONFIG_CPU_SUBTYPE_SH7763)
c63847a3
NI		 456SCIF_FNS(SCFDR, 0, 0, 0x1C, 16)
457SCIF_FNS(SCSPTR2, 0, 0, 0x20, 16)
c2697968
PM		 458SCIF_FNS(SCLSR2, 0, 0, 0x24, 16)
459SCIF_FNS(SCTFDR, 0x0e, 16, 0x1C, 16)
460SCIF_FNS(SCRFDR, 0x0e, 16, 0x20, 16)
461SCIF_FNS(SCSPTR, 0, 0, 0x24, 16)
462SCIF_FNS(SCLSR, 0, 0, 0x28, 16)
b7a76e4b 463#else
1da177e4 464SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16)
9b4e466f
MD		 465#if defined(CONFIG_CPU_SUBTYPE_SH7722)
466SCIF_FNS(SCSPTR, 0, 0, 0, 0)
467#else
1da177e4 468SCIF_FNS(SCSPTR, 0, 0, 0x20, 16)
9b4e466f 469#endif
1da177e4
LT		 470SCIF_FNS(SCLSR, 0, 0, 0x24, 16)
471#endif
b7a76e4b 472#endif
1da177e4
LT		 473#define sci_in(port, reg) sci_##reg##_in(port)
474#define sci_out(port, reg, value) sci_##reg##_out(port, value)
475
476/* H8/300 series SCI pins assignment */
477#if defined(__H8300H__) || defined(__H8300S__)
478static const struct __attribute__((packed)) {
479 int port; /* GPIO port no */
480 unsigned short rx,tx; /* GPIO bit no */
481} h8300_sci_pins[] = {
482#if defined(CONFIG_H83007) || defined(CONFIG_H83068)
483 { /* SCI0 */
484 .port = H8300_GPIO_P9,
485 .rx = H8300_GPIO_B2,
486 .tx = H8300_GPIO_B0,
487 },
488 { /* SCI1 */
489 .port = H8300_GPIO_P9,
490 .rx = H8300_GPIO_B3,
491 .tx = H8300_GPIO_B1,
492 },
493 { /* SCI2 */
494 .port = H8300_GPIO_PB,
495 .rx = H8300_GPIO_B7,
496 .tx = H8300_GPIO_B6,
497 }
498#elif defined(CONFIG_H8S2678)
499 { /* SCI0 */
500 .port = H8300_GPIO_P3,
501 .rx = H8300_GPIO_B2,
502 .tx = H8300_GPIO_B0,
503 },
504 { /* SCI1 */
505 .port = H8300_GPIO_P3,
506 .rx = H8300_GPIO_B3,
507 .tx = H8300_GPIO_B1,
508 },
509 { /* SCI2 */
510 .port = H8300_GPIO_P5,
511 .rx = H8300_GPIO_B1,
512 .tx = H8300_GPIO_B0,
513 }
514#endif
515};
516#endif
517
0fbde950
MD		 518#if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
519 defined(CONFIG_CPU_SUBTYPE_SH7707) || \
520 defined(CONFIG_CPU_SUBTYPE_SH7708) || \
521 defined(CONFIG_CPU_SUBTYPE_SH7709)
1da177e4
LT		 522static inline int sci_rxd_in(struct uart_port *port)
523{
524 if (port->mapbase == 0xfffffe80)
32b53076 525 return __raw_readb(SCPDR)&0x01 ? 1 : 0; /* SCI */
3ea6bc3d
MB		 526 return 1;
527}
05627486
PM		 528#elif defined(CONFIG_CPU_SUBTYPE_SH7750) || \
529 defined(CONFIG_CPU_SUBTYPE_SH7751) || \
530 defined(CONFIG_CPU_SUBTYPE_SH7751R) || \
531 defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
532 defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
961e9ff9 533 defined(CONFIG_CPU_SUBTYPE_SH7091)
1da177e4
LT		 534static inline int sci_rxd_in(struct uart_port *port)
535{
1da177e4 536 if (port->mapbase == 0xffe00000)
32b53076 537 return __raw_readb(SCSPTR1)&0x01 ? 1 : 0; /* SCI */
47948d2b
KM		 538 return 1;
539}
1da177e4
LT		 540#elif defined(__H8300H__) || defined(__H8300S__)
541static inline int sci_rxd_in(struct uart_port *port)
542{
543 int ch = (port->mapbase - SMR0) >> 3;
544 return (H8300_SCI_DR(ch) & h8300_sci_pins[ch].rx) ? 1 : 0;
545}
9e9622d1 546#else /* default case for non-SCI processors */
2b1bd1ac
PM		 547static inline int sci_rxd_in(struct uart_port *port)
548{
1760b7d7 549 return 1;
2b1bd1ac 550}
1da177e4
LT		 551#endif
552
553/*
554 * Values for the BitRate Register (SCBRR)
555 *
556 * The values are actually divisors for a frequency which can
557 * be internal to the SH3 (14.7456MHz) or derived from an external
558 * clock source. This driver assumes the internal clock is used;
559 * to support using an external clock source, config options or
560 * possibly command-line options would need to be added.
561 *
562 * Also, to support speeds below 2400 (why?) the lower 2 bits of
563 * the SCSMR register would also need to be set to non-zero values.
564 *
565 * -- Greg Banks 27Feb2000
566 *
567 * Answer: The SCBRR register is only eight bits, and the value in
568 * it gets larger with lower baud rates. At around 2400 (depending on
569 * the peripherial module clock) you run out of bits. However the
570 * lower two bits of SCSMR allow the module clock to be divided down,
571 * scaling the value which is needed in SCBRR.
572 *
573 * -- Stuart Menefy - 23 May 2000
574 *
575 * I meant, why would anyone bother with bitrates below 2400.
576 *
577 * -- Greg Banks - 7Jul2000
578 *
579 * You "speedist"! How will I use my 110bps ASR-33 teletype with paper
580 * tape reader as a console!
581 *
582 * -- Mitch Davis - 15 Jul 2000
583 */
584
c63847a3 585#if defined(CONFIG_CPU_SUBTYPE_SH7780) || \
55ba99eb
KM		 586 defined(CONFIG_CPU_SUBTYPE_SH7785) || \
587 defined(CONFIG_CPU_SUBTYPE_SH7786)
b7a76e4b 588#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(16*bps)-1)
3ea6bc3d 589#elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \
31a49c4b 590 defined(CONFIG_CPU_SUBTYPE_SH7720) || \
8a77b8d0
MD		 591 defined(CONFIG_CPU_SUBTYPE_SH7721) || \
592 defined(CONFIG_ARCH_SHMOBILE)
b7a76e4b 593#define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1)
47948d2b
KM		 594#elif defined(CONFIG_CPU_SUBTYPE_SH7723) ||\
595 defined(CONFIG_CPU_SUBTYPE_SH7724)
ba1d2818
NI		 596static inline int scbrr_calc(struct uart_port *port, int bps, int clk)
597{
598 if (port->type == PORT_SCIF)
599 return (clk+16*bps)/(32*bps)-1;
600 else
601 return ((clk*2)+16*bps)/(16*bps)-1;
602}
603#define SCBRR_VALUE(bps, clk) scbrr_calc(port, bps, clk)
b7a76e4b 604#elif defined(__H8300H__) || defined(__H8300S__)
a2159b52 605#define SCBRR_VALUE(bps, clk) (((clk*1000/32)/bps)-1)
b7a76e4b
PM		 606#else /* Generic SH */
607#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1)
1da177e4 608#endif
Linux 6.x block layer and io_uring tree(s)