atmel_serial: use container_of instead of direct cast
[linux-2.6-block.git] / drivers / serial / atmel_serial.c
CommitLineData
1e6c9c28 1/*
c2f5ccfb 2 * linux/drivers/char/atmel_serial.c
1e6c9c28 3 *
7192f92c 4 * Driver for Atmel AT91 / AT32 Serial ports
1e6c9c28
AV
5 * Copyright (C) 2003 Rick Bronson
6 *
7 * Based on drivers/char/serial_sa1100.c, by Deep Blue Solutions Ltd.
8 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
9 *
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10 * DMA support added by Chip Coldwell.
11 *
1e6c9c28
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12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 *
26 */
1e6c9c28
AV
27#include <linux/module.h>
28#include <linux/tty.h>
29#include <linux/ioport.h>
30#include <linux/slab.h>
31#include <linux/init.h>
32#include <linux/serial.h>
afefc415 33#include <linux/clk.h>
1e6c9c28
AV
34#include <linux/console.h>
35#include <linux/sysrq.h>
36#include <linux/tty_flip.h>
afefc415 37#include <linux/platform_device.h>
a6670615 38#include <linux/dma-mapping.h>
93a3ddc2 39#include <linux/atmel_pdc.h>
fa3218d8 40#include <linux/atmel_serial.h>
1e6c9c28
AV
41
42#include <asm/io.h>
43
afefc415 44#include <asm/mach/serial_at91.h>
1e6c9c28 45#include <asm/arch/board.h>
93a3ddc2 46
acca9b83 47#ifdef CONFIG_ARM
c2f5ccfb 48#include <asm/arch/cpu.h>
20e65276 49#include <asm/arch/gpio.h>
acca9b83 50#endif
1e6c9c28 51
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52#define PDC_BUFFER_SIZE 512
53/* Revisit: We should calculate this based on the actual port settings */
54#define PDC_RX_TIMEOUT (3 * 10) /* 3 bytes */
55
749c4e60 56#if defined(CONFIG_SERIAL_ATMEL_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
1e6c9c28
AV
57#define SUPPORT_SYSRQ
58#endif
59
60#include <linux/serial_core.h>
61
749c4e60 62#ifdef CONFIG_SERIAL_ATMEL_TTYAT
1e6c9c28
AV
63
64/* Use device name ttyAT, major 204 and minor 154-169. This is necessary if we
65 * should coexist with the 8250 driver, such as if we have an external 16C550
66 * UART. */
7192f92c 67#define SERIAL_ATMEL_MAJOR 204
1e6c9c28 68#define MINOR_START 154
7192f92c 69#define ATMEL_DEVICENAME "ttyAT"
1e6c9c28
AV
70
71#else
72
73/* Use device name ttyS, major 4, minor 64-68. This is the usual serial port
74 * name, but it is legally reserved for the 8250 driver. */
7192f92c 75#define SERIAL_ATMEL_MAJOR TTY_MAJOR
1e6c9c28 76#define MINOR_START 64
7192f92c 77#define ATMEL_DEVICENAME "ttyS"
1e6c9c28
AV
78
79#endif
80
7192f92c 81#define ATMEL_ISR_PASS_LIMIT 256
1e6c9c28 82
b843aa21 83/* UART registers. CR is write-only, hence no GET macro */
544fc728
HS
84#define UART_PUT_CR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_CR)
85#define UART_GET_MR(port) __raw_readl((port)->membase + ATMEL_US_MR)
86#define UART_PUT_MR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_MR)
87#define UART_PUT_IER(port,v) __raw_writel(v, (port)->membase + ATMEL_US_IER)
88#define UART_PUT_IDR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_IDR)
89#define UART_GET_IMR(port) __raw_readl((port)->membase + ATMEL_US_IMR)
90#define UART_GET_CSR(port) __raw_readl((port)->membase + ATMEL_US_CSR)
91#define UART_GET_CHAR(port) __raw_readl((port)->membase + ATMEL_US_RHR)
92#define UART_PUT_CHAR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_THR)
93#define UART_GET_BRGR(port) __raw_readl((port)->membase + ATMEL_US_BRGR)
94#define UART_PUT_BRGR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_BRGR)
95#define UART_PUT_RTOR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_RTOR)
96
1e6c9c28 97 /* PDC registers */
544fc728
HS
98#define UART_PUT_PTCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_PTCR)
99#define UART_GET_PTSR(port) __raw_readl((port)->membase + ATMEL_PDC_PTSR)
100
101#define UART_PUT_RPR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RPR)
102#define UART_GET_RPR(port) __raw_readl((port)->membase + ATMEL_PDC_RPR)
103#define UART_PUT_RCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RCR)
104#define UART_PUT_RNPR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RNPR)
105#define UART_PUT_RNCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RNCR)
106
107#define UART_PUT_TPR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_TPR)
108#define UART_PUT_TCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_TCR)
1e6c9c28 109
71f2e2b8
HS
110static int (*atmel_open_hook)(struct uart_port *);
111static void (*atmel_close_hook)(struct uart_port *);
1e6c9c28 112
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113struct atmel_dma_buffer {
114 unsigned char *buf;
115 dma_addr_t dma_addr;
116 unsigned int dma_size;
117 unsigned int ofs;
118};
119
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120struct atmel_uart_char {
121 u16 status;
122 u16 ch;
123};
124
125#define ATMEL_SERIAL_RINGSIZE 1024
126
afefc415
AV
127/*
128 * We wrap our port structure around the generic uart_port.
129 */
7192f92c 130struct atmel_uart_port {
afefc415
AV
131 struct uart_port uart; /* uart */
132 struct clk *clk; /* uart clock */
133 unsigned short suspended; /* is port suspended? */
9e6077bd 134 int break_active; /* break being received */
1ecc26bd 135
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136 short use_dma_rx; /* enable PDC receiver */
137 short pdc_rx_idx; /* current PDC RX buffer */
138 struct atmel_dma_buffer pdc_rx[2]; /* PDC receier */
139
140 short use_dma_tx; /* enable PDC transmitter */
141 struct atmel_dma_buffer pdc_tx; /* PDC transmitter */
142
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143 struct tasklet_struct tasklet;
144 unsigned int irq_status;
145 unsigned int irq_status_prev;
146
147 struct circ_buf rx_ring;
afefc415
AV
148};
149
7192f92c 150static struct atmel_uart_port atmel_ports[ATMEL_MAX_UART];
afefc415 151
1e6c9c28 152#ifdef SUPPORT_SYSRQ
7192f92c 153static struct console atmel_console;
1e6c9c28
AV
154#endif
155
c811ab8c
HS
156static inline struct atmel_uart_port *
157to_atmel_uart_port(struct uart_port *uart)
158{
159 return container_of(uart, struct atmel_uart_port, uart);
160}
161
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162#ifdef CONFIG_SERIAL_ATMEL_PDC
163static bool atmel_use_dma_rx(struct uart_port *port)
164{
c811ab8c 165 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
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166
167 return atmel_port->use_dma_rx;
168}
169
170static bool atmel_use_dma_tx(struct uart_port *port)
171{
c811ab8c 172 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
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173
174 return atmel_port->use_dma_tx;
175}
176#else
177static bool atmel_use_dma_rx(struct uart_port *port)
178{
179 return false;
180}
181
182static bool atmel_use_dma_tx(struct uart_port *port)
183{
184 return false;
185}
186#endif
187
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188/*
189 * Return TIOCSER_TEMT when transmitter FIFO and Shift register is empty.
190 */
7192f92c 191static u_int atmel_tx_empty(struct uart_port *port)
1e6c9c28 192{
7192f92c 193 return (UART_GET_CSR(port) & ATMEL_US_TXEMPTY) ? TIOCSER_TEMT : 0;
1e6c9c28
AV
194}
195
196/*
197 * Set state of the modem control output lines
198 */
7192f92c 199static void atmel_set_mctrl(struct uart_port *port, u_int mctrl)
1e6c9c28
AV
200{
201 unsigned int control = 0;
afefc415 202 unsigned int mode;
1e6c9c28 203
c2f5ccfb 204#ifdef CONFIG_ARCH_AT91RM9200
79da7a61 205 if (cpu_is_at91rm9200()) {
afefc415 206 /*
b843aa21
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207 * AT91RM9200 Errata #39: RTS0 is not internally connected
208 * to PA21. We need to drive the pin manually.
afefc415 209 */
72729910 210 if (port->mapbase == AT91RM9200_BASE_US0) {
afefc415 211 if (mctrl & TIOCM_RTS)
20e65276 212 at91_set_gpio_value(AT91_PIN_PA21, 0);
afefc415 213 else
20e65276 214 at91_set_gpio_value(AT91_PIN_PA21, 1);
afefc415 215 }
1e6c9c28 216 }
acca9b83 217#endif
1e6c9c28
AV
218
219 if (mctrl & TIOCM_RTS)
7192f92c 220 control |= ATMEL_US_RTSEN;
1e6c9c28 221 else
7192f92c 222 control |= ATMEL_US_RTSDIS;
1e6c9c28
AV
223
224 if (mctrl & TIOCM_DTR)
7192f92c 225 control |= ATMEL_US_DTREN;
1e6c9c28 226 else
7192f92c 227 control |= ATMEL_US_DTRDIS;
1e6c9c28 228
afefc415
AV
229 UART_PUT_CR(port, control);
230
231 /* Local loopback mode? */
7192f92c 232 mode = UART_GET_MR(port) & ~ATMEL_US_CHMODE;
afefc415 233 if (mctrl & TIOCM_LOOP)
7192f92c 234 mode |= ATMEL_US_CHMODE_LOC_LOOP;
afefc415 235 else
7192f92c 236 mode |= ATMEL_US_CHMODE_NORMAL;
afefc415 237 UART_PUT_MR(port, mode);
1e6c9c28
AV
238}
239
240/*
241 * Get state of the modem control input lines
242 */
7192f92c 243static u_int atmel_get_mctrl(struct uart_port *port)
1e6c9c28
AV
244{
245 unsigned int status, ret = 0;
246
247 status = UART_GET_CSR(port);
248
249 /*
250 * The control signals are active low.
251 */
7192f92c 252 if (!(status & ATMEL_US_DCD))
1e6c9c28 253 ret |= TIOCM_CD;
7192f92c 254 if (!(status & ATMEL_US_CTS))
1e6c9c28 255 ret |= TIOCM_CTS;
7192f92c 256 if (!(status & ATMEL_US_DSR))
1e6c9c28 257 ret |= TIOCM_DSR;
7192f92c 258 if (!(status & ATMEL_US_RI))
1e6c9c28
AV
259 ret |= TIOCM_RI;
260
261 return ret;
262}
263
264/*
265 * Stop transmitting.
266 */
7192f92c 267static void atmel_stop_tx(struct uart_port *port)
1e6c9c28 268{
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269 if (atmel_use_dma_tx(port)) {
270 /* disable PDC transmit */
271 UART_PUT_PTCR(port, ATMEL_PDC_TXTDIS);
272 UART_PUT_IDR(port, ATMEL_US_ENDTX | ATMEL_US_TXBUFE);
273 } else
274 UART_PUT_IDR(port, ATMEL_US_TXRDY);
1e6c9c28
AV
275}
276
277/*
278 * Start transmitting.
279 */
7192f92c 280static void atmel_start_tx(struct uart_port *port)
1e6c9c28 281{
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282 if (atmel_use_dma_tx(port)) {
283 if (UART_GET_PTSR(port) & ATMEL_PDC_TXTEN)
284 /* The transmitter is already running. Yes, we
285 really need this.*/
286 return;
287
288 UART_PUT_IER(port, ATMEL_US_ENDTX | ATMEL_US_TXBUFE);
289 /* re-enable PDC transmit */
290 UART_PUT_PTCR(port, ATMEL_PDC_TXTEN);
291 } else
292 UART_PUT_IER(port, ATMEL_US_TXRDY);
1e6c9c28
AV
293}
294
295/*
296 * Stop receiving - port is in process of being closed.
297 */
7192f92c 298static void atmel_stop_rx(struct uart_port *port)
1e6c9c28 299{
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300 if (atmel_use_dma_rx(port)) {
301 /* disable PDC receive */
302 UART_PUT_PTCR(port, ATMEL_PDC_RXTDIS);
303 UART_PUT_IDR(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
304 } else
305 UART_PUT_IDR(port, ATMEL_US_RXRDY);
1e6c9c28
AV
306}
307
308/*
309 * Enable modem status interrupts
310 */
7192f92c 311static void atmel_enable_ms(struct uart_port *port)
1e6c9c28 312{
b843aa21
RB
313 UART_PUT_IER(port, ATMEL_US_RIIC | ATMEL_US_DSRIC
314 | ATMEL_US_DCDIC | ATMEL_US_CTSIC);
1e6c9c28
AV
315}
316
317/*
318 * Control the transmission of a break signal
319 */
7192f92c 320static void atmel_break_ctl(struct uart_port *port, int break_state)
1e6c9c28
AV
321{
322 if (break_state != 0)
7192f92c 323 UART_PUT_CR(port, ATMEL_US_STTBRK); /* start break */
1e6c9c28 324 else
7192f92c 325 UART_PUT_CR(port, ATMEL_US_STPBRK); /* stop break */
1e6c9c28
AV
326}
327
1ecc26bd
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328/*
329 * Stores the incoming character in the ring buffer
330 */
331static void
332atmel_buffer_rx_char(struct uart_port *port, unsigned int status,
333 unsigned int ch)
334{
c811ab8c 335 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1ecc26bd
RB
336 struct circ_buf *ring = &atmel_port->rx_ring;
337 struct atmel_uart_char *c;
338
339 if (!CIRC_SPACE(ring->head, ring->tail, ATMEL_SERIAL_RINGSIZE))
340 /* Buffer overflow, ignore char */
341 return;
342
343 c = &((struct atmel_uart_char *)ring->buf)[ring->head];
344 c->status = status;
345 c->ch = ch;
346
347 /* Make sure the character is stored before we update head. */
348 smp_wmb();
349
350 ring->head = (ring->head + 1) & (ATMEL_SERIAL_RINGSIZE - 1);
351}
352
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353/*
354 * Deal with parity, framing and overrun errors.
355 */
356static void atmel_pdc_rxerr(struct uart_port *port, unsigned int status)
357{
358 /* clear error */
359 UART_PUT_CR(port, ATMEL_US_RSTSTA);
360
361 if (status & ATMEL_US_RXBRK) {
362 /* ignore side-effect */
363 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME);
364 port->icount.brk++;
365 }
366 if (status & ATMEL_US_PARE)
367 port->icount.parity++;
368 if (status & ATMEL_US_FRAME)
369 port->icount.frame++;
370 if (status & ATMEL_US_OVRE)
371 port->icount.overrun++;
372}
373
1e6c9c28
AV
374/*
375 * Characters received (called from interrupt handler)
376 */
7d12e780 377static void atmel_rx_chars(struct uart_port *port)
1e6c9c28 378{
c811ab8c 379 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1ecc26bd 380 unsigned int status, ch;
1e6c9c28 381
afefc415 382 status = UART_GET_CSR(port);
7192f92c 383 while (status & ATMEL_US_RXRDY) {
1e6c9c28
AV
384 ch = UART_GET_CHAR(port);
385
1e6c9c28
AV
386 /*
387 * note that the error handling code is
388 * out of the main execution path
389 */
9e6077bd
HS
390 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME
391 | ATMEL_US_OVRE | ATMEL_US_RXBRK)
392 || atmel_port->break_active)) {
1ecc26bd 393
b843aa21
RB
394 /* clear error */
395 UART_PUT_CR(port, ATMEL_US_RSTSTA);
1ecc26bd 396
9e6077bd
HS
397 if (status & ATMEL_US_RXBRK
398 && !atmel_port->break_active) {
9e6077bd
HS
399 atmel_port->break_active = 1;
400 UART_PUT_IER(port, ATMEL_US_RXBRK);
9e6077bd
HS
401 } else {
402 /*
403 * This is either the end-of-break
404 * condition or we've received at
405 * least one character without RXBRK
406 * being set. In both cases, the next
407 * RXBRK will indicate start-of-break.
408 */
409 UART_PUT_IDR(port, ATMEL_US_RXBRK);
410 status &= ~ATMEL_US_RXBRK;
411 atmel_port->break_active = 0;
afefc415 412 }
1e6c9c28
AV
413 }
414
1ecc26bd 415 atmel_buffer_rx_char(port, status, ch);
afefc415 416 status = UART_GET_CSR(port);
1e6c9c28
AV
417 }
418
1ecc26bd 419 tasklet_schedule(&atmel_port->tasklet);
1e6c9c28
AV
420}
421
422/*
1ecc26bd
RB
423 * Transmit characters (called from tasklet with TXRDY interrupt
424 * disabled)
1e6c9c28 425 */
7192f92c 426static void atmel_tx_chars(struct uart_port *port)
1e6c9c28
AV
427{
428 struct circ_buf *xmit = &port->info->xmit;
429
1ecc26bd 430 if (port->x_char && UART_GET_CSR(port) & ATMEL_US_TXRDY) {
1e6c9c28
AV
431 UART_PUT_CHAR(port, port->x_char);
432 port->icount.tx++;
433 port->x_char = 0;
1e6c9c28 434 }
1ecc26bd 435 if (uart_circ_empty(xmit) || uart_tx_stopped(port))
1e6c9c28 436 return;
1e6c9c28 437
7192f92c 438 while (UART_GET_CSR(port) & ATMEL_US_TXRDY) {
1e6c9c28
AV
439 UART_PUT_CHAR(port, xmit->buf[xmit->tail]);
440 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
441 port->icount.tx++;
442 if (uart_circ_empty(xmit))
443 break;
444 }
445
446 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
447 uart_write_wakeup(port);
448
1ecc26bd
RB
449 if (!uart_circ_empty(xmit))
450 UART_PUT_IER(port, ATMEL_US_TXRDY);
1e6c9c28
AV
451}
452
b843aa21
RB
453/*
454 * receive interrupt handler.
455 */
456static void
457atmel_handle_receive(struct uart_port *port, unsigned int pending)
458{
c811ab8c 459 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
b843aa21 460
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461 if (atmel_use_dma_rx(port)) {
462 /*
463 * PDC receive. Just schedule the tasklet and let it
464 * figure out the details.
465 *
466 * TODO: We're not handling error flags correctly at
467 * the moment.
468 */
469 if (pending & (ATMEL_US_ENDRX | ATMEL_US_TIMEOUT)) {
470 UART_PUT_IDR(port, (ATMEL_US_ENDRX
471 | ATMEL_US_TIMEOUT));
472 tasklet_schedule(&atmel_port->tasklet);
473 }
474
475 if (pending & (ATMEL_US_RXBRK | ATMEL_US_OVRE |
476 ATMEL_US_FRAME | ATMEL_US_PARE))
477 atmel_pdc_rxerr(port, pending);
478 }
479
b843aa21
RB
480 /* Interrupt receive */
481 if (pending & ATMEL_US_RXRDY)
482 atmel_rx_chars(port);
483 else if (pending & ATMEL_US_RXBRK) {
484 /*
485 * End of break detected. If it came along with a
486 * character, atmel_rx_chars will handle it.
487 */
488 UART_PUT_CR(port, ATMEL_US_RSTSTA);
489 UART_PUT_IDR(port, ATMEL_US_RXBRK);
490 atmel_port->break_active = 0;
491 }
492}
493
494/*
1ecc26bd 495 * transmit interrupt handler. (Transmit is IRQF_NODELAY safe)
b843aa21
RB
496 */
497static void
498atmel_handle_transmit(struct uart_port *port, unsigned int pending)
499{
c811ab8c 500 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1ecc26bd 501
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502 if (atmel_use_dma_tx(port)) {
503 /* PDC transmit */
504 if (pending & (ATMEL_US_ENDTX | ATMEL_US_TXBUFE)) {
505 UART_PUT_IDR(port, ATMEL_US_ENDTX | ATMEL_US_TXBUFE);
506 tasklet_schedule(&atmel_port->tasklet);
507 }
508 } else {
509 /* Interrupt transmit */
510 if (pending & ATMEL_US_TXRDY) {
511 UART_PUT_IDR(port, ATMEL_US_TXRDY);
512 tasklet_schedule(&atmel_port->tasklet);
513 }
1ecc26bd 514 }
b843aa21
RB
515}
516
517/*
518 * status flags interrupt handler.
519 */
520static void
521atmel_handle_status(struct uart_port *port, unsigned int pending,
522 unsigned int status)
523{
c811ab8c 524 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1ecc26bd 525
b843aa21 526 if (pending & (ATMEL_US_RIIC | ATMEL_US_DSRIC | ATMEL_US_DCDIC
1ecc26bd
RB
527 | ATMEL_US_CTSIC)) {
528 atmel_port->irq_status = status;
529 tasklet_schedule(&atmel_port->tasklet);
530 }
b843aa21
RB
531}
532
1e6c9c28
AV
533/*
534 * Interrupt handler
535 */
7d12e780 536static irqreturn_t atmel_interrupt(int irq, void *dev_id)
1e6c9c28
AV
537{
538 struct uart_port *port = dev_id;
539 unsigned int status, pending, pass_counter = 0;
540
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541 do {
542 status = UART_GET_CSR(port);
543 pending = status & UART_GET_IMR(port);
544 if (!pending)
545 break;
546
b843aa21
RB
547 atmel_handle_receive(port, pending);
548 atmel_handle_status(port, pending, status);
549 atmel_handle_transmit(port, pending);
a6670615 550 } while (pass_counter++ < ATMEL_ISR_PASS_LIMIT);
afefc415 551
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552 return IRQ_HANDLED;
553}
1e6c9c28 554
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CC
555/*
556 * Called from tasklet with ENDTX and TXBUFE interrupts disabled.
557 */
558static void atmel_tx_dma(struct uart_port *port)
559{
c811ab8c 560 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
a6670615
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561 struct circ_buf *xmit = &port->info->xmit;
562 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
563 int count;
564
565 xmit->tail += pdc->ofs;
566 xmit->tail &= UART_XMIT_SIZE - 1;
567
568 port->icount.tx += pdc->ofs;
569 pdc->ofs = 0;
570
571 if (!uart_circ_empty(xmit)) {
572 /* more to transmit - setup next transfer */
573
574 /* disable PDC transmit */
575 UART_PUT_PTCR(port, ATMEL_PDC_TXTDIS);
576 dma_sync_single_for_device(port->dev,
577 pdc->dma_addr,
578 pdc->dma_size,
579 DMA_TO_DEVICE);
580
581 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
582 pdc->ofs = count;
583
584 UART_PUT_TPR(port, pdc->dma_addr + xmit->tail);
585 UART_PUT_TCR(port, count);
586 /* re-enable PDC transmit and interrupts */
587 UART_PUT_PTCR(port, ATMEL_PDC_TXTEN);
588 UART_PUT_IER(port, ATMEL_US_ENDTX | ATMEL_US_TXBUFE);
589 } else {
590 /* nothing left to transmit - disable the transmitter */
591
592 /* disable PDC transmit */
593 UART_PUT_PTCR(port, ATMEL_PDC_TXTDIS);
1e6c9c28 594 }
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CC
595
596 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
597 uart_write_wakeup(port);
1e6c9c28
AV
598}
599
1ecc26bd
RB
600static void atmel_rx_from_ring(struct uart_port *port)
601{
c811ab8c 602 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1ecc26bd
RB
603 struct circ_buf *ring = &atmel_port->rx_ring;
604 unsigned int flg;
605 unsigned int status;
606
607 while (ring->head != ring->tail) {
608 struct atmel_uart_char c;
609
610 /* Make sure c is loaded after head. */
611 smp_rmb();
612
613 c = ((struct atmel_uart_char *)ring->buf)[ring->tail];
614
615 ring->tail = (ring->tail + 1) & (ATMEL_SERIAL_RINGSIZE - 1);
616
617 port->icount.rx++;
618 status = c.status;
619 flg = TTY_NORMAL;
620
621 /*
622 * note that the error handling code is
623 * out of the main execution path
624 */
625 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME
626 | ATMEL_US_OVRE | ATMEL_US_RXBRK))) {
627 if (status & ATMEL_US_RXBRK) {
628 /* ignore side-effect */
629 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME);
630
631 port->icount.brk++;
632 if (uart_handle_break(port))
633 continue;
634 }
635 if (status & ATMEL_US_PARE)
636 port->icount.parity++;
637 if (status & ATMEL_US_FRAME)
638 port->icount.frame++;
639 if (status & ATMEL_US_OVRE)
640 port->icount.overrun++;
641
642 status &= port->read_status_mask;
643
644 if (status & ATMEL_US_RXBRK)
645 flg = TTY_BREAK;
646 else if (status & ATMEL_US_PARE)
647 flg = TTY_PARITY;
648 else if (status & ATMEL_US_FRAME)
649 flg = TTY_FRAME;
650 }
651
652
653 if (uart_handle_sysrq_char(port, c.ch))
654 continue;
655
656 uart_insert_char(port, status, ATMEL_US_OVRE, c.ch, flg);
657 }
658
659 /*
660 * Drop the lock here since it might end up calling
661 * uart_start(), which takes the lock.
662 */
663 spin_unlock(&port->lock);
664 tty_flip_buffer_push(port->info->tty);
665 spin_lock(&port->lock);
666}
667
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CC
668static void atmel_rx_from_dma(struct uart_port *port)
669{
c811ab8c 670 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
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CC
671 struct tty_struct *tty = port->info->tty;
672 struct atmel_dma_buffer *pdc;
673 int rx_idx = atmel_port->pdc_rx_idx;
674 unsigned int head;
675 unsigned int tail;
676 unsigned int count;
677
678 do {
679 /* Reset the UART timeout early so that we don't miss one */
680 UART_PUT_CR(port, ATMEL_US_STTTO);
681
682 pdc = &atmel_port->pdc_rx[rx_idx];
683 head = UART_GET_RPR(port) - pdc->dma_addr;
684 tail = pdc->ofs;
685
686 /* If the PDC has switched buffers, RPR won't contain
687 * any address within the current buffer. Since head
688 * is unsigned, we just need a one-way comparison to
689 * find out.
690 *
691 * In this case, we just need to consume the entire
692 * buffer and resubmit it for DMA. This will clear the
693 * ENDRX bit as well, so that we can safely re-enable
694 * all interrupts below.
695 */
696 head = min(head, pdc->dma_size);
697
698 if (likely(head != tail)) {
699 dma_sync_single_for_cpu(port->dev, pdc->dma_addr,
700 pdc->dma_size, DMA_FROM_DEVICE);
701
702 /*
703 * head will only wrap around when we recycle
704 * the DMA buffer, and when that happens, we
705 * explicitly set tail to 0. So head will
706 * always be greater than tail.
707 */
708 count = head - tail;
709
710 tty_insert_flip_string(tty, pdc->buf + pdc->ofs, count);
711
712 dma_sync_single_for_device(port->dev, pdc->dma_addr,
713 pdc->dma_size, DMA_FROM_DEVICE);
714
715 port->icount.rx += count;
716 pdc->ofs = head;
717 }
718
719 /*
720 * If the current buffer is full, we need to check if
721 * the next one contains any additional data.
722 */
723 if (head >= pdc->dma_size) {
724 pdc->ofs = 0;
725 UART_PUT_RNPR(port, pdc->dma_addr);
726 UART_PUT_RNCR(port, pdc->dma_size);
727
728 rx_idx = !rx_idx;
729 atmel_port->pdc_rx_idx = rx_idx;
730 }
731 } while (head >= pdc->dma_size);
732
733 /*
734 * Drop the lock here since it might end up calling
735 * uart_start(), which takes the lock.
736 */
737 spin_unlock(&port->lock);
738 tty_flip_buffer_push(tty);
739 spin_lock(&port->lock);
740
741 UART_PUT_IER(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
742}
743
1ecc26bd
RB
744/*
745 * tasklet handling tty stuff outside the interrupt handler.
746 */
747static void atmel_tasklet_func(unsigned long data)
748{
749 struct uart_port *port = (struct uart_port *)data;
c811ab8c 750 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1ecc26bd
RB
751 unsigned int status;
752 unsigned int status_change;
753
754 /* The interrupt handler does not take the lock */
755 spin_lock(&port->lock);
756
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CC
757 if (atmel_use_dma_tx(port))
758 atmel_tx_dma(port);
759 else
760 atmel_tx_chars(port);
1ecc26bd
RB
761
762 status = atmel_port->irq_status;
763 status_change = status ^ atmel_port->irq_status_prev;
764
765 if (status_change & (ATMEL_US_RI | ATMEL_US_DSR
766 | ATMEL_US_DCD | ATMEL_US_CTS)) {
767 /* TODO: All reads to CSR will clear these interrupts! */
768 if (status_change & ATMEL_US_RI)
769 port->icount.rng++;
770 if (status_change & ATMEL_US_DSR)
771 port->icount.dsr++;
772 if (status_change & ATMEL_US_DCD)
773 uart_handle_dcd_change(port, !(status & ATMEL_US_DCD));
774 if (status_change & ATMEL_US_CTS)
775 uart_handle_cts_change(port, !(status & ATMEL_US_CTS));
776
777 wake_up_interruptible(&port->info->delta_msr_wait);
778
779 atmel_port->irq_status_prev = status;
780 }
781
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CC
782 if (atmel_use_dma_rx(port))
783 atmel_rx_from_dma(port);
784 else
785 atmel_rx_from_ring(port);
1ecc26bd
RB
786
787 spin_unlock(&port->lock);
788}
789
1e6c9c28
AV
790/*
791 * Perform initialization and enable port for reception
792 */
7192f92c 793static int atmel_startup(struct uart_port *port)
1e6c9c28 794{
c811ab8c 795 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1e6c9c28
AV
796 int retval;
797
798 /*
799 * Ensure that no interrupts are enabled otherwise when
800 * request_irq() is called we could get stuck trying to
801 * handle an unexpected interrupt
802 */
803 UART_PUT_IDR(port, -1);
804
805 /*
806 * Allocate the IRQ
807 */
b843aa21
RB
808 retval = request_irq(port->irq, atmel_interrupt, IRQF_SHARED,
809 "atmel_serial", port);
1e6c9c28 810 if (retval) {
7192f92c 811 printk("atmel_serial: atmel_startup - Can't get irq\n");
1e6c9c28
AV
812 return retval;
813 }
814
a6670615
CC
815 /*
816 * Initialize DMA (if necessary)
817 */
818 if (atmel_use_dma_rx(port)) {
819 int i;
820
821 for (i = 0; i < 2; i++) {
822 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i];
823
824 pdc->buf = kmalloc(PDC_BUFFER_SIZE, GFP_KERNEL);
825 if (pdc->buf == NULL) {
826 if (i != 0) {
827 dma_unmap_single(port->dev,
828 atmel_port->pdc_rx[0].dma_addr,
829 PDC_BUFFER_SIZE,
830 DMA_FROM_DEVICE);
831 kfree(atmel_port->pdc_rx[0].buf);
832 }
833 free_irq(port->irq, port);
834 return -ENOMEM;
835 }
836 pdc->dma_addr = dma_map_single(port->dev,
837 pdc->buf,
838 PDC_BUFFER_SIZE,
839 DMA_FROM_DEVICE);
840 pdc->dma_size = PDC_BUFFER_SIZE;
841 pdc->ofs = 0;
842 }
843
844 atmel_port->pdc_rx_idx = 0;
845
846 UART_PUT_RPR(port, atmel_port->pdc_rx[0].dma_addr);
847 UART_PUT_RCR(port, PDC_BUFFER_SIZE);
848
849 UART_PUT_RNPR(port, atmel_port->pdc_rx[1].dma_addr);
850 UART_PUT_RNCR(port, PDC_BUFFER_SIZE);
851 }
852 if (atmel_use_dma_tx(port)) {
853 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
854 struct circ_buf *xmit = &port->info->xmit;
855
856 pdc->buf = xmit->buf;
857 pdc->dma_addr = dma_map_single(port->dev,
858 pdc->buf,
859 UART_XMIT_SIZE,
860 DMA_TO_DEVICE);
861 pdc->dma_size = UART_XMIT_SIZE;
862 pdc->ofs = 0;
863 }
864
1e6c9c28
AV
865 /*
866 * If there is a specific "open" function (to register
867 * control line interrupts)
868 */
71f2e2b8
HS
869 if (atmel_open_hook) {
870 retval = atmel_open_hook(port);
1e6c9c28
AV
871 if (retval) {
872 free_irq(port->irq, port);
873 return retval;
874 }
875 }
876
1e6c9c28
AV
877 /*
878 * Finally, enable the serial port
879 */
7192f92c 880 UART_PUT_CR(port, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
b843aa21
RB
881 /* enable xmit & rcvr */
882 UART_PUT_CR(port, ATMEL_US_TXEN | ATMEL_US_RXEN);
afefc415 883
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CC
884 if (atmel_use_dma_rx(port)) {
885 /* set UART timeout */
886 UART_PUT_RTOR(port, PDC_RX_TIMEOUT);
887 UART_PUT_CR(port, ATMEL_US_STTTO);
888
889 UART_PUT_IER(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
890 /* enable PDC controller */
891 UART_PUT_PTCR(port, ATMEL_PDC_RXTEN);
892 } else {
893 /* enable receive only */
894 UART_PUT_IER(port, ATMEL_US_RXRDY);
895 }
afefc415 896
1e6c9c28
AV
897 return 0;
898}
899
900/*
901 * Disable the port
902 */
7192f92c 903static void atmel_shutdown(struct uart_port *port)
1e6c9c28 904{
c811ab8c 905 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
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CC
906 /*
907 * Ensure everything is stopped.
908 */
909 atmel_stop_rx(port);
910 atmel_stop_tx(port);
911
912 /*
913 * Shut-down the DMA.
914 */
915 if (atmel_use_dma_rx(port)) {
916 int i;
917
918 for (i = 0; i < 2; i++) {
919 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i];
920
921 dma_unmap_single(port->dev,
922 pdc->dma_addr,
923 pdc->dma_size,
924 DMA_FROM_DEVICE);
925 kfree(pdc->buf);
926 }
927 }
928 if (atmel_use_dma_tx(port)) {
929 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
930
931 dma_unmap_single(port->dev,
932 pdc->dma_addr,
933 pdc->dma_size,
934 DMA_TO_DEVICE);
935 }
936
1e6c9c28
AV
937 /*
938 * Disable all interrupts, port and break condition.
939 */
7192f92c 940 UART_PUT_CR(port, ATMEL_US_RSTSTA);
1e6c9c28
AV
941 UART_PUT_IDR(port, -1);
942
943 /*
944 * Free the interrupt
945 */
946 free_irq(port->irq, port);
947
948 /*
949 * If there is a specific "close" function (to unregister
950 * control line interrupts)
951 */
71f2e2b8
HS
952 if (atmel_close_hook)
953 atmel_close_hook(port);
1e6c9c28
AV
954}
955
956/*
957 * Power / Clock management.
958 */
b843aa21
RB
959static void atmel_serial_pm(struct uart_port *port, unsigned int state,
960 unsigned int oldstate)
1e6c9c28 961{
c811ab8c 962 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
afefc415 963
1e6c9c28 964 switch (state) {
b843aa21
RB
965 case 0:
966 /*
967 * Enable the peripheral clock for this serial port.
968 * This is called on uart_open() or a resume event.
969 */
970 clk_enable(atmel_port->clk);
971 break;
972 case 3:
973 /*
974 * Disable the peripheral clock for this serial port.
975 * This is called on uart_close() or a suspend event.
976 */
977 clk_disable(atmel_port->clk);
978 break;
979 default:
980 printk(KERN_ERR "atmel_serial: unknown pm %d\n", state);
1e6c9c28
AV
981 }
982}
983
984/*
985 * Change the port parameters
986 */
b843aa21
RB
987static void atmel_set_termios(struct uart_port *port, struct ktermios *termios,
988 struct ktermios *old)
1e6c9c28
AV
989{
990 unsigned long flags;
991 unsigned int mode, imr, quot, baud;
992
03abeac0 993 /* Get current mode register */
b843aa21
RB
994 mode = UART_GET_MR(port) & ~(ATMEL_US_USCLKS | ATMEL_US_CHRL
995 | ATMEL_US_NBSTOP | ATMEL_US_PAR);
03abeac0 996
b843aa21 997 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
1e6c9c28
AV
998 quot = uart_get_divisor(port, baud);
999
b843aa21 1000 if (quot > 65535) { /* BRGR is 16-bit, so switch to slower clock */
03abeac0
AV
1001 quot /= 8;
1002 mode |= ATMEL_US_USCLKS_MCK_DIV8;
1003 }
1e6c9c28
AV
1004
1005 /* byte size */
1006 switch (termios->c_cflag & CSIZE) {
1007 case CS5:
7192f92c 1008 mode |= ATMEL_US_CHRL_5;
1e6c9c28
AV
1009 break;
1010 case CS6:
7192f92c 1011 mode |= ATMEL_US_CHRL_6;
1e6c9c28
AV
1012 break;
1013 case CS7:
7192f92c 1014 mode |= ATMEL_US_CHRL_7;
1e6c9c28
AV
1015 break;
1016 default:
7192f92c 1017 mode |= ATMEL_US_CHRL_8;
1e6c9c28
AV
1018 break;
1019 }
1020
1021 /* stop bits */
1022 if (termios->c_cflag & CSTOPB)
7192f92c 1023 mode |= ATMEL_US_NBSTOP_2;
1e6c9c28
AV
1024
1025 /* parity */
1026 if (termios->c_cflag & PARENB) {
b843aa21
RB
1027 /* Mark or Space parity */
1028 if (termios->c_cflag & CMSPAR) {
1e6c9c28 1029 if (termios->c_cflag & PARODD)
7192f92c 1030 mode |= ATMEL_US_PAR_MARK;
1e6c9c28 1031 else
7192f92c 1032 mode |= ATMEL_US_PAR_SPACE;
b843aa21 1033 } else if (termios->c_cflag & PARODD)
7192f92c 1034 mode |= ATMEL_US_PAR_ODD;
1e6c9c28 1035 else
7192f92c 1036 mode |= ATMEL_US_PAR_EVEN;
b843aa21 1037 } else
7192f92c 1038 mode |= ATMEL_US_PAR_NONE;
1e6c9c28
AV
1039
1040 spin_lock_irqsave(&port->lock, flags);
1041
7192f92c 1042 port->read_status_mask = ATMEL_US_OVRE;
1e6c9c28 1043 if (termios->c_iflag & INPCK)
7192f92c 1044 port->read_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE);
1e6c9c28 1045 if (termios->c_iflag & (BRKINT | PARMRK))
7192f92c 1046 port->read_status_mask |= ATMEL_US_RXBRK;
1e6c9c28 1047
a6670615
CC
1048 if (atmel_use_dma_rx(port))
1049 /* need to enable error interrupts */
1050 UART_PUT_IER(port, port->read_status_mask);
1051
1e6c9c28
AV
1052 /*
1053 * Characters to ignore
1054 */
1055 port->ignore_status_mask = 0;
1056 if (termios->c_iflag & IGNPAR)
7192f92c 1057 port->ignore_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE);
1e6c9c28 1058 if (termios->c_iflag & IGNBRK) {
7192f92c 1059 port->ignore_status_mask |= ATMEL_US_RXBRK;
1e6c9c28
AV
1060 /*
1061 * If we're ignoring parity and break indicators,
1062 * ignore overruns too (for real raw support).
1063 */
1064 if (termios->c_iflag & IGNPAR)
7192f92c 1065 port->ignore_status_mask |= ATMEL_US_OVRE;
1e6c9c28 1066 }
b843aa21 1067 /* TODO: Ignore all characters if CREAD is set.*/
1e6c9c28
AV
1068
1069 /* update the per-port timeout */
1070 uart_update_timeout(port, termios->c_cflag, baud);
1071
b843aa21
RB
1072 /* save/disable interrupts and drain transmitter */
1073 imr = UART_GET_IMR(port);
1074 UART_PUT_IDR(port, -1);
1075 while (!(UART_GET_CSR(port) & ATMEL_US_TXEMPTY))
829dd811 1076 cpu_relax();
1e6c9c28
AV
1077
1078 /* disable receiver and transmitter */
7192f92c 1079 UART_PUT_CR(port, ATMEL_US_TXDIS | ATMEL_US_RXDIS);
1e6c9c28
AV
1080
1081 /* set the parity, stop bits and data size */
1082 UART_PUT_MR(port, mode);
1083
1084 /* set the baud rate */
1085 UART_PUT_BRGR(port, quot);
7192f92c
HS
1086 UART_PUT_CR(port, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
1087 UART_PUT_CR(port, ATMEL_US_TXEN | ATMEL_US_RXEN);
1e6c9c28
AV
1088
1089 /* restore interrupts */
1090 UART_PUT_IER(port, imr);
1091
1092 /* CTS flow-control and modem-status interrupts */
1093 if (UART_ENABLE_MS(port, termios->c_cflag))
1094 port->ops->enable_ms(port);
1095
1096 spin_unlock_irqrestore(&port->lock, flags);
1097}
1098
1099/*
1100 * Return string describing the specified port
1101 */
7192f92c 1102static const char *atmel_type(struct uart_port *port)
1e6c9c28 1103{
9ab4f88b 1104 return (port->type == PORT_ATMEL) ? "ATMEL_SERIAL" : NULL;
1e6c9c28
AV
1105}
1106
1107/*
1108 * Release the memory region(s) being used by 'port'.
1109 */
7192f92c 1110static void atmel_release_port(struct uart_port *port)
1e6c9c28 1111{
afefc415
AV
1112 struct platform_device *pdev = to_platform_device(port->dev);
1113 int size = pdev->resource[0].end - pdev->resource[0].start + 1;
1114
1115 release_mem_region(port->mapbase, size);
1116
1117 if (port->flags & UPF_IOREMAP) {
1118 iounmap(port->membase);
1119 port->membase = NULL;
1120 }
1e6c9c28
AV
1121}
1122
1123/*
1124 * Request the memory region(s) being used by 'port'.
1125 */
7192f92c 1126static int atmel_request_port(struct uart_port *port)
1e6c9c28 1127{
afefc415
AV
1128 struct platform_device *pdev = to_platform_device(port->dev);
1129 int size = pdev->resource[0].end - pdev->resource[0].start + 1;
1130
7192f92c 1131 if (!request_mem_region(port->mapbase, size, "atmel_serial"))
afefc415
AV
1132 return -EBUSY;
1133
1134 if (port->flags & UPF_IOREMAP) {
1135 port->membase = ioremap(port->mapbase, size);
1136 if (port->membase == NULL) {
1137 release_mem_region(port->mapbase, size);
1138 return -ENOMEM;
1139 }
1140 }
1e6c9c28 1141
afefc415 1142 return 0;
1e6c9c28
AV
1143}
1144
1145/*
1146 * Configure/autoconfigure the port.
1147 */
7192f92c 1148static void atmel_config_port(struct uart_port *port, int flags)
1e6c9c28
AV
1149{
1150 if (flags & UART_CONFIG_TYPE) {
9ab4f88b 1151 port->type = PORT_ATMEL;
7192f92c 1152 atmel_request_port(port);
1e6c9c28
AV
1153 }
1154}
1155
1156/*
1157 * Verify the new serial_struct (for TIOCSSERIAL).
1158 */
7192f92c 1159static int atmel_verify_port(struct uart_port *port, struct serial_struct *ser)
1e6c9c28
AV
1160{
1161 int ret = 0;
9ab4f88b 1162 if (ser->type != PORT_UNKNOWN && ser->type != PORT_ATMEL)
1e6c9c28
AV
1163 ret = -EINVAL;
1164 if (port->irq != ser->irq)
1165 ret = -EINVAL;
1166 if (ser->io_type != SERIAL_IO_MEM)
1167 ret = -EINVAL;
1168 if (port->uartclk / 16 != ser->baud_base)
1169 ret = -EINVAL;
1170 if ((void *)port->mapbase != ser->iomem_base)
1171 ret = -EINVAL;
1172 if (port->iobase != ser->port)
1173 ret = -EINVAL;
1174 if (ser->hub6 != 0)
1175 ret = -EINVAL;
1176 return ret;
1177}
1178
7192f92c
HS
1179static struct uart_ops atmel_pops = {
1180 .tx_empty = atmel_tx_empty,
1181 .set_mctrl = atmel_set_mctrl,
1182 .get_mctrl = atmel_get_mctrl,
1183 .stop_tx = atmel_stop_tx,
1184 .start_tx = atmel_start_tx,
1185 .stop_rx = atmel_stop_rx,
1186 .enable_ms = atmel_enable_ms,
1187 .break_ctl = atmel_break_ctl,
1188 .startup = atmel_startup,
1189 .shutdown = atmel_shutdown,
1190 .set_termios = atmel_set_termios,
1191 .type = atmel_type,
1192 .release_port = atmel_release_port,
1193 .request_port = atmel_request_port,
1194 .config_port = atmel_config_port,
1195 .verify_port = atmel_verify_port,
1196 .pm = atmel_serial_pm,
1e6c9c28
AV
1197};
1198
afefc415
AV
1199/*
1200 * Configure the port from the platform device resource info.
1201 */
b843aa21
RB
1202static void __devinit atmel_init_port(struct atmel_uart_port *atmel_port,
1203 struct platform_device *pdev)
1e6c9c28 1204{
7192f92c 1205 struct uart_port *port = &atmel_port->uart;
73e2798b 1206 struct atmel_uart_data *data = pdev->dev.platform_data;
afefc415
AV
1207
1208 port->iotype = UPIO_MEM;
a14d5273 1209 port->flags = UPF_BOOT_AUTOCONF;
7192f92c 1210 port->ops = &atmel_pops;
a14d5273 1211 port->fifosize = 1;
afefc415
AV
1212 port->line = pdev->id;
1213 port->dev = &pdev->dev;
1214
1215 port->mapbase = pdev->resource[0].start;
1216 port->irq = pdev->resource[1].start;
1217
1ecc26bd
RB
1218 tasklet_init(&atmel_port->tasklet, atmel_tasklet_func,
1219 (unsigned long)port);
1220
1221 memset(&atmel_port->rx_ring, 0, sizeof(atmel_port->rx_ring));
1222
75d35213
HS
1223 if (data->regs)
1224 /* Already mapped by setup code */
1225 port->membase = data->regs;
afefc415
AV
1226 else {
1227 port->flags |= UPF_IOREMAP;
1228 port->membase = NULL;
1229 }
1e6c9c28 1230
b843aa21
RB
1231 /* for console, the clock could already be configured */
1232 if (!atmel_port->clk) {
7192f92c
HS
1233 atmel_port->clk = clk_get(&pdev->dev, "usart");
1234 clk_enable(atmel_port->clk);
1235 port->uartclk = clk_get_rate(atmel_port->clk);
afefc415 1236 }
a6670615
CC
1237
1238 atmel_port->use_dma_rx = data->use_dma_rx;
1239 atmel_port->use_dma_tx = data->use_dma_tx;
1240 if (atmel_use_dma_tx(port))
1241 port->fifosize = PDC_BUFFER_SIZE;
1e6c9c28
AV
1242}
1243
afefc415
AV
1244/*
1245 * Register board-specific modem-control line handlers.
1246 */
71f2e2b8 1247void __init atmel_register_uart_fns(struct atmel_port_fns *fns)
1e6c9c28
AV
1248{
1249 if (fns->enable_ms)
7192f92c 1250 atmel_pops.enable_ms = fns->enable_ms;
1e6c9c28 1251 if (fns->get_mctrl)
7192f92c 1252 atmel_pops.get_mctrl = fns->get_mctrl;
1e6c9c28 1253 if (fns->set_mctrl)
7192f92c 1254 atmel_pops.set_mctrl = fns->set_mctrl;
71f2e2b8
HS
1255 atmel_open_hook = fns->open;
1256 atmel_close_hook = fns->close;
7192f92c
HS
1257 atmel_pops.pm = fns->pm;
1258 atmel_pops.set_wake = fns->set_wake;
1e6c9c28
AV
1259}
1260
749c4e60 1261#ifdef CONFIG_SERIAL_ATMEL_CONSOLE
7192f92c 1262static void atmel_console_putchar(struct uart_port *port, int ch)
d358788f 1263{
7192f92c 1264 while (!(UART_GET_CSR(port) & ATMEL_US_TXRDY))
829dd811 1265 cpu_relax();
d358788f
RK
1266 UART_PUT_CHAR(port, ch);
1267}
1e6c9c28
AV
1268
1269/*
1270 * Interrupts are disabled on entering
1271 */
7192f92c 1272static void atmel_console_write(struct console *co, const char *s, u_int count)
1e6c9c28 1273{
7192f92c 1274 struct uart_port *port = &atmel_ports[co->index].uart;
d358788f 1275 unsigned int status, imr;
1e6c9c28
AV
1276
1277 /*
b843aa21 1278 * First, save IMR and then disable interrupts
1e6c9c28 1279 */
b843aa21 1280 imr = UART_GET_IMR(port);
7192f92c 1281 UART_PUT_IDR(port, ATMEL_US_RXRDY | ATMEL_US_TXRDY);
1e6c9c28 1282
7192f92c 1283 uart_console_write(port, s, count, atmel_console_putchar);
1e6c9c28
AV
1284
1285 /*
b843aa21
RB
1286 * Finally, wait for transmitter to become empty
1287 * and restore IMR
1e6c9c28
AV
1288 */
1289 do {
1290 status = UART_GET_CSR(port);
7192f92c 1291 } while (!(status & ATMEL_US_TXRDY));
b843aa21
RB
1292 /* set interrupts back the way they were */
1293 UART_PUT_IER(port, imr);
1e6c9c28
AV
1294}
1295
1296/*
b843aa21
RB
1297 * If the port was already initialised (eg, by a boot loader),
1298 * try to determine the current setup.
1e6c9c28 1299 */
b843aa21
RB
1300static void __init atmel_console_get_options(struct uart_port *port, int *baud,
1301 int *parity, int *bits)
1e6c9c28
AV
1302{
1303 unsigned int mr, quot;
1304
1c0fd82f
HS
1305 /*
1306 * If the baud rate generator isn't running, the port wasn't
1307 * initialized by the boot loader.
1308 */
1309 quot = UART_GET_BRGR(port);
1310 if (!quot)
1311 return;
1e6c9c28 1312
7192f92c
HS
1313 mr = UART_GET_MR(port) & ATMEL_US_CHRL;
1314 if (mr == ATMEL_US_CHRL_8)
1e6c9c28
AV
1315 *bits = 8;
1316 else
1317 *bits = 7;
1318
7192f92c
HS
1319 mr = UART_GET_MR(port) & ATMEL_US_PAR;
1320 if (mr == ATMEL_US_PAR_EVEN)
1e6c9c28 1321 *parity = 'e';
7192f92c 1322 else if (mr == ATMEL_US_PAR_ODD)
1e6c9c28
AV
1323 *parity = 'o';
1324
4d5e392c
HS
1325 /*
1326 * The serial core only rounds down when matching this to a
1327 * supported baud rate. Make sure we don't end up slightly
1328 * lower than one of those, as it would make us fall through
1329 * to a much lower baud rate than we really want.
1330 */
4d5e392c 1331 *baud = port->uartclk / (16 * (quot - 1));
1e6c9c28
AV
1332}
1333
7192f92c 1334static int __init atmel_console_setup(struct console *co, char *options)
1e6c9c28 1335{
7192f92c 1336 struct uart_port *port = &atmel_ports[co->index].uart;
1e6c9c28
AV
1337 int baud = 115200;
1338 int bits = 8;
1339 int parity = 'n';
1340 int flow = 'n';
1341
b843aa21
RB
1342 if (port->membase == NULL) {
1343 /* Port not initialized yet - delay setup */
afefc415 1344 return -ENODEV;
b843aa21 1345 }
1e6c9c28 1346
b843aa21 1347 UART_PUT_IDR(port, -1);
7192f92c
HS
1348 UART_PUT_CR(port, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
1349 UART_PUT_CR(port, ATMEL_US_TXEN | ATMEL_US_RXEN);
1e6c9c28
AV
1350
1351 if (options)
1352 uart_parse_options(options, &baud, &parity, &bits, &flow);
1353 else
7192f92c 1354 atmel_console_get_options(port, &baud, &parity, &bits);
1e6c9c28
AV
1355
1356 return uart_set_options(port, co, baud, parity, bits, flow);
1357}
1358
7192f92c 1359static struct uart_driver atmel_uart;
1e6c9c28 1360
7192f92c
HS
1361static struct console atmel_console = {
1362 .name = ATMEL_DEVICENAME,
1363 .write = atmel_console_write,
1e6c9c28 1364 .device = uart_console_device,
7192f92c 1365 .setup = atmel_console_setup,
1e6c9c28
AV
1366 .flags = CON_PRINTBUFFER,
1367 .index = -1,
7192f92c 1368 .data = &atmel_uart,
1e6c9c28
AV
1369};
1370
7192f92c 1371#define ATMEL_CONSOLE_DEVICE &atmel_console
1e6c9c28 1372
afefc415
AV
1373/*
1374 * Early console initialization (before VM subsystem initialized).
1375 */
7192f92c 1376static int __init atmel_console_init(void)
1e6c9c28 1377{
73e2798b 1378 if (atmel_default_console_device) {
b843aa21
RB
1379 add_preferred_console(ATMEL_DEVICENAME,
1380 atmel_default_console_device->id, NULL);
1381 atmel_init_port(&atmel_ports[atmel_default_console_device->id],
1382 atmel_default_console_device);
7192f92c 1383 register_console(&atmel_console);
afefc415 1384 }
1e6c9c28 1385
1e6c9c28
AV
1386 return 0;
1387}
b843aa21 1388
7192f92c 1389console_initcall(atmel_console_init);
1e6c9c28 1390
afefc415
AV
1391/*
1392 * Late console initialization.
1393 */
7192f92c 1394static int __init atmel_late_console_init(void)
afefc415 1395{
b843aa21
RB
1396 if (atmel_default_console_device
1397 && !(atmel_console.flags & CON_ENABLED))
7192f92c 1398 register_console(&atmel_console);
afefc415
AV
1399
1400 return 0;
1401}
b843aa21 1402
7192f92c 1403core_initcall(atmel_late_console_init);
afefc415 1404
dfa7f343
HS
1405static inline bool atmel_is_console_port(struct uart_port *port)
1406{
1407 return port->cons && port->cons->index == port->line;
1408}
1409
1e6c9c28 1410#else
7192f92c 1411#define ATMEL_CONSOLE_DEVICE NULL
dfa7f343
HS
1412
1413static inline bool atmel_is_console_port(struct uart_port *port)
1414{
1415 return false;
1416}
1e6c9c28
AV
1417#endif
1418
7192f92c 1419static struct uart_driver atmel_uart = {
b843aa21
RB
1420 .owner = THIS_MODULE,
1421 .driver_name = "atmel_serial",
1422 .dev_name = ATMEL_DEVICENAME,
1423 .major = SERIAL_ATMEL_MAJOR,
1424 .minor = MINOR_START,
1425 .nr = ATMEL_MAX_UART,
1426 .cons = ATMEL_CONSOLE_DEVICE,
1e6c9c28
AV
1427};
1428
afefc415 1429#ifdef CONFIG_PM
b843aa21
RB
1430static int atmel_serial_suspend(struct platform_device *pdev,
1431 pm_message_t state)
1e6c9c28 1432{
afefc415 1433 struct uart_port *port = platform_get_drvdata(pdev);
c811ab8c 1434 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
afefc415 1435
b843aa21
RB
1436 if (device_may_wakeup(&pdev->dev)
1437 && !at91_suspend_entering_slow_clock())
afefc415
AV
1438 enable_irq_wake(port->irq);
1439 else {
7192f92c
HS
1440 uart_suspend_port(&atmel_uart, port);
1441 atmel_port->suspended = 1;
afefc415 1442 }
1e6c9c28 1443
afefc415
AV
1444 return 0;
1445}
1e6c9c28 1446
7192f92c 1447static int atmel_serial_resume(struct platform_device *pdev)
afefc415
AV
1448{
1449 struct uart_port *port = platform_get_drvdata(pdev);
c811ab8c 1450 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1e6c9c28 1451
7192f92c
HS
1452 if (atmel_port->suspended) {
1453 uart_resume_port(&atmel_uart, port);
1454 atmel_port->suspended = 0;
b843aa21 1455 } else
9b938166 1456 disable_irq_wake(port->irq);
1e6c9c28
AV
1457
1458 return 0;
1459}
afefc415 1460#else
7192f92c
HS
1461#define atmel_serial_suspend NULL
1462#define atmel_serial_resume NULL
afefc415 1463#endif
1e6c9c28 1464
7192f92c 1465static int __devinit atmel_serial_probe(struct platform_device *pdev)
1e6c9c28 1466{
7192f92c 1467 struct atmel_uart_port *port;
1ecc26bd 1468 void *data;
afefc415 1469 int ret;
1e6c9c28 1470
1ecc26bd
RB
1471 BUILD_BUG_ON(!is_power_of_2(ATMEL_SERIAL_RINGSIZE));
1472
7192f92c
HS
1473 port = &atmel_ports[pdev->id];
1474 atmel_init_port(port, pdev);
1e6c9c28 1475
a6670615
CC
1476 if (!atmel_use_dma_rx(&port->uart)) {
1477 ret = -ENOMEM;
6433471d
HS
1478 data = kmalloc(sizeof(struct atmel_uart_char)
1479 * ATMEL_SERIAL_RINGSIZE, GFP_KERNEL);
a6670615
CC
1480 if (!data)
1481 goto err_alloc_ring;
1482 port->rx_ring.buf = data;
1483 }
1ecc26bd 1484
7192f92c 1485 ret = uart_add_one_port(&atmel_uart, &port->uart);
dfa7f343
HS
1486 if (ret)
1487 goto err_add_port;
1488
1489 device_init_wakeup(&pdev->dev, 1);
1490 platform_set_drvdata(pdev, port);
1491
1492 return 0;
1493
1494err_add_port:
1ecc26bd
RB
1495 kfree(port->rx_ring.buf);
1496 port->rx_ring.buf = NULL;
1497err_alloc_ring:
dfa7f343
HS
1498 if (!atmel_is_console_port(&port->uart)) {
1499 clk_disable(port->clk);
1500 clk_put(port->clk);
1501 port->clk = NULL;
afefc415
AV
1502 }
1503
1504 return ret;
1505}
1506
7192f92c 1507static int __devexit atmel_serial_remove(struct platform_device *pdev)
afefc415
AV
1508{
1509 struct uart_port *port = platform_get_drvdata(pdev);
c811ab8c 1510 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
afefc415
AV
1511 int ret = 0;
1512
afefc415
AV
1513 device_init_wakeup(&pdev->dev, 0);
1514 platform_set_drvdata(pdev, NULL);
1515
dfa7f343
HS
1516 ret = uart_remove_one_port(&atmel_uart, port);
1517
1ecc26bd
RB
1518 tasklet_kill(&atmel_port->tasklet);
1519 kfree(atmel_port->rx_ring.buf);
1520
dfa7f343
HS
1521 /* "port" is allocated statically, so we shouldn't free it */
1522
1523 clk_disable(atmel_port->clk);
1524 clk_put(atmel_port->clk);
afefc415
AV
1525
1526 return ret;
1527}
1528
7192f92c
HS
1529static struct platform_driver atmel_serial_driver = {
1530 .probe = atmel_serial_probe,
1531 .remove = __devexit_p(atmel_serial_remove),
1532 .suspend = atmel_serial_suspend,
1533 .resume = atmel_serial_resume,
afefc415 1534 .driver = {
1e8ea802 1535 .name = "atmel_usart",
afefc415
AV
1536 .owner = THIS_MODULE,
1537 },
1538};
1539
7192f92c 1540static int __init atmel_serial_init(void)
afefc415
AV
1541{
1542 int ret;
1543
7192f92c 1544 ret = uart_register_driver(&atmel_uart);
afefc415
AV
1545 if (ret)
1546 return ret;
1547
7192f92c 1548 ret = platform_driver_register(&atmel_serial_driver);
afefc415 1549 if (ret)
7192f92c 1550 uart_unregister_driver(&atmel_uart);
afefc415
AV
1551
1552 return ret;
1553}
1554
7192f92c 1555static void __exit atmel_serial_exit(void)
afefc415 1556{
7192f92c
HS
1557 platform_driver_unregister(&atmel_serial_driver);
1558 uart_unregister_driver(&atmel_uart);
1e6c9c28
AV
1559}
1560
7192f92c
HS
1561module_init(atmel_serial_init);
1562module_exit(atmel_serial_exit);
1e6c9c28
AV
1563
1564MODULE_AUTHOR("Rick Bronson");
7192f92c 1565MODULE_DESCRIPTION("Atmel AT91 / AT32 serial port driver");
1e6c9c28 1566MODULE_LICENSE("GPL");