ARM: 6053/1: AT91: Save power by disabling the processor clock when CPU is idle
[linux-2.6-block.git] / drivers / serial / atmel_serial.c
CommitLineData
1e6c9c28 1/*
c2f5ccfb 2 * linux/drivers/char/atmel_serial.c
1e6c9c28 3 *
7192f92c 4 * Driver for Atmel AT91 / AT32 Serial ports
1e6c9c28
AV
5 * Copyright (C) 2003 Rick Bronson
6 *
7 * Based on drivers/char/serial_sa1100.c, by Deep Blue Solutions Ltd.
8 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
9 *
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10 * DMA support added by Chip Coldwell.
11 *
1e6c9c28
AV
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 *
26 */
1e6c9c28
AV
27#include <linux/module.h>
28#include <linux/tty.h>
29#include <linux/ioport.h>
30#include <linux/slab.h>
31#include <linux/init.h>
32#include <linux/serial.h>
afefc415 33#include <linux/clk.h>
1e6c9c28
AV
34#include <linux/console.h>
35#include <linux/sysrq.h>
36#include <linux/tty_flip.h>
afefc415 37#include <linux/platform_device.h>
a6670615 38#include <linux/dma-mapping.h>
93a3ddc2 39#include <linux/atmel_pdc.h>
fa3218d8 40#include <linux/atmel_serial.h>
1e6c9c28
AV
41
42#include <asm/io.h>
43
afefc415 44#include <asm/mach/serial_at91.h>
a09e64fb 45#include <mach/board.h>
93a3ddc2 46
acca9b83 47#ifdef CONFIG_ARM
a09e64fb
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48#include <mach/cpu.h>
49#include <mach/gpio.h>
acca9b83 50#endif
1e6c9c28 51
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52#define PDC_BUFFER_SIZE 512
53/* Revisit: We should calculate this based on the actual port settings */
54#define PDC_RX_TIMEOUT (3 * 10) /* 3 bytes */
55
749c4e60 56#if defined(CONFIG_SERIAL_ATMEL_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
1e6c9c28
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57#define SUPPORT_SYSRQ
58#endif
59
60#include <linux/serial_core.h>
61
749c4e60 62#ifdef CONFIG_SERIAL_ATMEL_TTYAT
1e6c9c28
AV
63
64/* Use device name ttyAT, major 204 and minor 154-169. This is necessary if we
65 * should coexist with the 8250 driver, such as if we have an external 16C550
66 * UART. */
7192f92c 67#define SERIAL_ATMEL_MAJOR 204
1e6c9c28 68#define MINOR_START 154
7192f92c 69#define ATMEL_DEVICENAME "ttyAT"
1e6c9c28
AV
70
71#else
72
73/* Use device name ttyS, major 4, minor 64-68. This is the usual serial port
74 * name, but it is legally reserved for the 8250 driver. */
7192f92c 75#define SERIAL_ATMEL_MAJOR TTY_MAJOR
1e6c9c28 76#define MINOR_START 64
7192f92c 77#define ATMEL_DEVICENAME "ttyS"
1e6c9c28
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78
79#endif
80
7192f92c 81#define ATMEL_ISR_PASS_LIMIT 256
1e6c9c28 82
b843aa21 83/* UART registers. CR is write-only, hence no GET macro */
544fc728
HS
84#define UART_PUT_CR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_CR)
85#define UART_GET_MR(port) __raw_readl((port)->membase + ATMEL_US_MR)
86#define UART_PUT_MR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_MR)
87#define UART_PUT_IER(port,v) __raw_writel(v, (port)->membase + ATMEL_US_IER)
88#define UART_PUT_IDR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_IDR)
89#define UART_GET_IMR(port) __raw_readl((port)->membase + ATMEL_US_IMR)
90#define UART_GET_CSR(port) __raw_readl((port)->membase + ATMEL_US_CSR)
91#define UART_GET_CHAR(port) __raw_readl((port)->membase + ATMEL_US_RHR)
92#define UART_PUT_CHAR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_THR)
93#define UART_GET_BRGR(port) __raw_readl((port)->membase + ATMEL_US_BRGR)
94#define UART_PUT_BRGR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_BRGR)
95#define UART_PUT_RTOR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_RTOR)
96
1e6c9c28 97 /* PDC registers */
544fc728
HS
98#define UART_PUT_PTCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_PTCR)
99#define UART_GET_PTSR(port) __raw_readl((port)->membase + ATMEL_PDC_PTSR)
100
101#define UART_PUT_RPR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RPR)
102#define UART_GET_RPR(port) __raw_readl((port)->membase + ATMEL_PDC_RPR)
103#define UART_PUT_RCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RCR)
104#define UART_PUT_RNPR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RNPR)
105#define UART_PUT_RNCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RNCR)
106
107#define UART_PUT_TPR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_TPR)
108#define UART_PUT_TCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_TCR)
39d4c922 109#define UART_GET_TCR(port) __raw_readl((port)->membase + ATMEL_PDC_TCR)
1e6c9c28 110
71f2e2b8
HS
111static int (*atmel_open_hook)(struct uart_port *);
112static void (*atmel_close_hook)(struct uart_port *);
1e6c9c28 113
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114struct atmel_dma_buffer {
115 unsigned char *buf;
116 dma_addr_t dma_addr;
117 unsigned int dma_size;
118 unsigned int ofs;
119};
120
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121struct atmel_uart_char {
122 u16 status;
123 u16 ch;
124};
125
126#define ATMEL_SERIAL_RINGSIZE 1024
127
afefc415
AV
128/*
129 * We wrap our port structure around the generic uart_port.
130 */
7192f92c 131struct atmel_uart_port {
afefc415
AV
132 struct uart_port uart; /* uart */
133 struct clk *clk; /* uart clock */
f05596db
AS
134 int may_wakeup; /* cached value of device_may_wakeup for times we need to disable it */
135 u32 backup_imr; /* IMR saved during suspend */
9e6077bd 136 int break_active; /* break being received */
1ecc26bd 137
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138 short use_dma_rx; /* enable PDC receiver */
139 short pdc_rx_idx; /* current PDC RX buffer */
140 struct atmel_dma_buffer pdc_rx[2]; /* PDC receier */
141
142 short use_dma_tx; /* enable PDC transmitter */
143 struct atmel_dma_buffer pdc_tx; /* PDC transmitter */
144
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145 struct tasklet_struct tasklet;
146 unsigned int irq_status;
147 unsigned int irq_status_prev;
148
149 struct circ_buf rx_ring;
afefc415
AV
150};
151
7192f92c 152static struct atmel_uart_port atmel_ports[ATMEL_MAX_UART];
afefc415 153
1e6c9c28 154#ifdef SUPPORT_SYSRQ
7192f92c 155static struct console atmel_console;
1e6c9c28
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156#endif
157
c811ab8c
HS
158static inline struct atmel_uart_port *
159to_atmel_uart_port(struct uart_port *uart)
160{
161 return container_of(uart, struct atmel_uart_port, uart);
162}
163
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164#ifdef CONFIG_SERIAL_ATMEL_PDC
165static bool atmel_use_dma_rx(struct uart_port *port)
166{
c811ab8c 167 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
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168
169 return atmel_port->use_dma_rx;
170}
171
172static bool atmel_use_dma_tx(struct uart_port *port)
173{
c811ab8c 174 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
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175
176 return atmel_port->use_dma_tx;
177}
178#else
179static bool atmel_use_dma_rx(struct uart_port *port)
180{
181 return false;
182}
183
184static bool atmel_use_dma_tx(struct uart_port *port)
185{
186 return false;
187}
188#endif
189
1e6c9c28
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190/*
191 * Return TIOCSER_TEMT when transmitter FIFO and Shift register is empty.
192 */
7192f92c 193static u_int atmel_tx_empty(struct uart_port *port)
1e6c9c28 194{
7192f92c 195 return (UART_GET_CSR(port) & ATMEL_US_TXEMPTY) ? TIOCSER_TEMT : 0;
1e6c9c28
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196}
197
198/*
199 * Set state of the modem control output lines
200 */
7192f92c 201static void atmel_set_mctrl(struct uart_port *port, u_int mctrl)
1e6c9c28
AV
202{
203 unsigned int control = 0;
afefc415 204 unsigned int mode;
1e6c9c28 205
c2f5ccfb 206#ifdef CONFIG_ARCH_AT91RM9200
79da7a61 207 if (cpu_is_at91rm9200()) {
afefc415 208 /*
b843aa21
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209 * AT91RM9200 Errata #39: RTS0 is not internally connected
210 * to PA21. We need to drive the pin manually.
afefc415 211 */
72729910 212 if (port->mapbase == AT91RM9200_BASE_US0) {
afefc415 213 if (mctrl & TIOCM_RTS)
20e65276 214 at91_set_gpio_value(AT91_PIN_PA21, 0);
afefc415 215 else
20e65276 216 at91_set_gpio_value(AT91_PIN_PA21, 1);
afefc415 217 }
1e6c9c28 218 }
acca9b83 219#endif
1e6c9c28
AV
220
221 if (mctrl & TIOCM_RTS)
7192f92c 222 control |= ATMEL_US_RTSEN;
1e6c9c28 223 else
7192f92c 224 control |= ATMEL_US_RTSDIS;
1e6c9c28
AV
225
226 if (mctrl & TIOCM_DTR)
7192f92c 227 control |= ATMEL_US_DTREN;
1e6c9c28 228 else
7192f92c 229 control |= ATMEL_US_DTRDIS;
1e6c9c28 230
afefc415
AV
231 UART_PUT_CR(port, control);
232
233 /* Local loopback mode? */
7192f92c 234 mode = UART_GET_MR(port) & ~ATMEL_US_CHMODE;
afefc415 235 if (mctrl & TIOCM_LOOP)
7192f92c 236 mode |= ATMEL_US_CHMODE_LOC_LOOP;
afefc415 237 else
7192f92c 238 mode |= ATMEL_US_CHMODE_NORMAL;
afefc415 239 UART_PUT_MR(port, mode);
1e6c9c28
AV
240}
241
242/*
243 * Get state of the modem control input lines
244 */
7192f92c 245static u_int atmel_get_mctrl(struct uart_port *port)
1e6c9c28
AV
246{
247 unsigned int status, ret = 0;
248
249 status = UART_GET_CSR(port);
250
251 /*
252 * The control signals are active low.
253 */
7192f92c 254 if (!(status & ATMEL_US_DCD))
1e6c9c28 255 ret |= TIOCM_CD;
7192f92c 256 if (!(status & ATMEL_US_CTS))
1e6c9c28 257 ret |= TIOCM_CTS;
7192f92c 258 if (!(status & ATMEL_US_DSR))
1e6c9c28 259 ret |= TIOCM_DSR;
7192f92c 260 if (!(status & ATMEL_US_RI))
1e6c9c28
AV
261 ret |= TIOCM_RI;
262
263 return ret;
264}
265
266/*
267 * Stop transmitting.
268 */
7192f92c 269static void atmel_stop_tx(struct uart_port *port)
1e6c9c28 270{
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271 if (atmel_use_dma_tx(port)) {
272 /* disable PDC transmit */
273 UART_PUT_PTCR(port, ATMEL_PDC_TXTDIS);
274 UART_PUT_IDR(port, ATMEL_US_ENDTX | ATMEL_US_TXBUFE);
275 } else
276 UART_PUT_IDR(port, ATMEL_US_TXRDY);
1e6c9c28
AV
277}
278
279/*
280 * Start transmitting.
281 */
7192f92c 282static void atmel_start_tx(struct uart_port *port)
1e6c9c28 283{
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284 if (atmel_use_dma_tx(port)) {
285 if (UART_GET_PTSR(port) & ATMEL_PDC_TXTEN)
286 /* The transmitter is already running. Yes, we
287 really need this.*/
288 return;
289
290 UART_PUT_IER(port, ATMEL_US_ENDTX | ATMEL_US_TXBUFE);
291 /* re-enable PDC transmit */
292 UART_PUT_PTCR(port, ATMEL_PDC_TXTEN);
293 } else
294 UART_PUT_IER(port, ATMEL_US_TXRDY);
1e6c9c28
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295}
296
297/*
298 * Stop receiving - port is in process of being closed.
299 */
7192f92c 300static void atmel_stop_rx(struct uart_port *port)
1e6c9c28 301{
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302 if (atmel_use_dma_rx(port)) {
303 /* disable PDC receive */
304 UART_PUT_PTCR(port, ATMEL_PDC_RXTDIS);
305 UART_PUT_IDR(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
306 } else
307 UART_PUT_IDR(port, ATMEL_US_RXRDY);
1e6c9c28
AV
308}
309
310/*
311 * Enable modem status interrupts
312 */
7192f92c 313static void atmel_enable_ms(struct uart_port *port)
1e6c9c28 314{
b843aa21
RB
315 UART_PUT_IER(port, ATMEL_US_RIIC | ATMEL_US_DSRIC
316 | ATMEL_US_DCDIC | ATMEL_US_CTSIC);
1e6c9c28
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317}
318
319/*
320 * Control the transmission of a break signal
321 */
7192f92c 322static void atmel_break_ctl(struct uart_port *port, int break_state)
1e6c9c28
AV
323{
324 if (break_state != 0)
7192f92c 325 UART_PUT_CR(port, ATMEL_US_STTBRK); /* start break */
1e6c9c28 326 else
7192f92c 327 UART_PUT_CR(port, ATMEL_US_STPBRK); /* stop break */
1e6c9c28
AV
328}
329
1ecc26bd
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330/*
331 * Stores the incoming character in the ring buffer
332 */
333static void
334atmel_buffer_rx_char(struct uart_port *port, unsigned int status,
335 unsigned int ch)
336{
c811ab8c 337 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1ecc26bd
RB
338 struct circ_buf *ring = &atmel_port->rx_ring;
339 struct atmel_uart_char *c;
340
341 if (!CIRC_SPACE(ring->head, ring->tail, ATMEL_SERIAL_RINGSIZE))
342 /* Buffer overflow, ignore char */
343 return;
344
345 c = &((struct atmel_uart_char *)ring->buf)[ring->head];
346 c->status = status;
347 c->ch = ch;
348
349 /* Make sure the character is stored before we update head. */
350 smp_wmb();
351
352 ring->head = (ring->head + 1) & (ATMEL_SERIAL_RINGSIZE - 1);
353}
354
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355/*
356 * Deal with parity, framing and overrun errors.
357 */
358static void atmel_pdc_rxerr(struct uart_port *port, unsigned int status)
359{
360 /* clear error */
361 UART_PUT_CR(port, ATMEL_US_RSTSTA);
362
363 if (status & ATMEL_US_RXBRK) {
364 /* ignore side-effect */
365 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME);
366 port->icount.brk++;
367 }
368 if (status & ATMEL_US_PARE)
369 port->icount.parity++;
370 if (status & ATMEL_US_FRAME)
371 port->icount.frame++;
372 if (status & ATMEL_US_OVRE)
373 port->icount.overrun++;
374}
375
1e6c9c28
AV
376/*
377 * Characters received (called from interrupt handler)
378 */
7d12e780 379static void atmel_rx_chars(struct uart_port *port)
1e6c9c28 380{
c811ab8c 381 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1ecc26bd 382 unsigned int status, ch;
1e6c9c28 383
afefc415 384 status = UART_GET_CSR(port);
7192f92c 385 while (status & ATMEL_US_RXRDY) {
1e6c9c28
AV
386 ch = UART_GET_CHAR(port);
387
1e6c9c28
AV
388 /*
389 * note that the error handling code is
390 * out of the main execution path
391 */
9e6077bd
HS
392 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME
393 | ATMEL_US_OVRE | ATMEL_US_RXBRK)
394 || atmel_port->break_active)) {
1ecc26bd 395
b843aa21
RB
396 /* clear error */
397 UART_PUT_CR(port, ATMEL_US_RSTSTA);
1ecc26bd 398
9e6077bd
HS
399 if (status & ATMEL_US_RXBRK
400 && !atmel_port->break_active) {
9e6077bd
HS
401 atmel_port->break_active = 1;
402 UART_PUT_IER(port, ATMEL_US_RXBRK);
9e6077bd
HS
403 } else {
404 /*
405 * This is either the end-of-break
406 * condition or we've received at
407 * least one character without RXBRK
408 * being set. In both cases, the next
409 * RXBRK will indicate start-of-break.
410 */
411 UART_PUT_IDR(port, ATMEL_US_RXBRK);
412 status &= ~ATMEL_US_RXBRK;
413 atmel_port->break_active = 0;
afefc415 414 }
1e6c9c28
AV
415 }
416
1ecc26bd 417 atmel_buffer_rx_char(port, status, ch);
afefc415 418 status = UART_GET_CSR(port);
1e6c9c28
AV
419 }
420
1ecc26bd 421 tasklet_schedule(&atmel_port->tasklet);
1e6c9c28
AV
422}
423
424/*
1ecc26bd
RB
425 * Transmit characters (called from tasklet with TXRDY interrupt
426 * disabled)
1e6c9c28 427 */
7192f92c 428static void atmel_tx_chars(struct uart_port *port)
1e6c9c28 429{
ebd2c8f6 430 struct circ_buf *xmit = &port->state->xmit;
1e6c9c28 431
1ecc26bd 432 if (port->x_char && UART_GET_CSR(port) & ATMEL_US_TXRDY) {
1e6c9c28
AV
433 UART_PUT_CHAR(port, port->x_char);
434 port->icount.tx++;
435 port->x_char = 0;
1e6c9c28 436 }
1ecc26bd 437 if (uart_circ_empty(xmit) || uart_tx_stopped(port))
1e6c9c28 438 return;
1e6c9c28 439
7192f92c 440 while (UART_GET_CSR(port) & ATMEL_US_TXRDY) {
1e6c9c28
AV
441 UART_PUT_CHAR(port, xmit->buf[xmit->tail]);
442 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
443 port->icount.tx++;
444 if (uart_circ_empty(xmit))
445 break;
446 }
447
448 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
449 uart_write_wakeup(port);
450
1ecc26bd
RB
451 if (!uart_circ_empty(xmit))
452 UART_PUT_IER(port, ATMEL_US_TXRDY);
1e6c9c28
AV
453}
454
b843aa21
RB
455/*
456 * receive interrupt handler.
457 */
458static void
459atmel_handle_receive(struct uart_port *port, unsigned int pending)
460{
c811ab8c 461 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
b843aa21 462
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463 if (atmel_use_dma_rx(port)) {
464 /*
465 * PDC receive. Just schedule the tasklet and let it
466 * figure out the details.
467 *
468 * TODO: We're not handling error flags correctly at
469 * the moment.
470 */
471 if (pending & (ATMEL_US_ENDRX | ATMEL_US_TIMEOUT)) {
472 UART_PUT_IDR(port, (ATMEL_US_ENDRX
473 | ATMEL_US_TIMEOUT));
474 tasklet_schedule(&atmel_port->tasklet);
475 }
476
477 if (pending & (ATMEL_US_RXBRK | ATMEL_US_OVRE |
478 ATMEL_US_FRAME | ATMEL_US_PARE))
479 atmel_pdc_rxerr(port, pending);
480 }
481
b843aa21
RB
482 /* Interrupt receive */
483 if (pending & ATMEL_US_RXRDY)
484 atmel_rx_chars(port);
485 else if (pending & ATMEL_US_RXBRK) {
486 /*
487 * End of break detected. If it came along with a
488 * character, atmel_rx_chars will handle it.
489 */
490 UART_PUT_CR(port, ATMEL_US_RSTSTA);
491 UART_PUT_IDR(port, ATMEL_US_RXBRK);
492 atmel_port->break_active = 0;
493 }
494}
495
496/*
1ecc26bd 497 * transmit interrupt handler. (Transmit is IRQF_NODELAY safe)
b843aa21
RB
498 */
499static void
500atmel_handle_transmit(struct uart_port *port, unsigned int pending)
501{
c811ab8c 502 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1ecc26bd 503
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504 if (atmel_use_dma_tx(port)) {
505 /* PDC transmit */
506 if (pending & (ATMEL_US_ENDTX | ATMEL_US_TXBUFE)) {
507 UART_PUT_IDR(port, ATMEL_US_ENDTX | ATMEL_US_TXBUFE);
508 tasklet_schedule(&atmel_port->tasklet);
509 }
510 } else {
511 /* Interrupt transmit */
512 if (pending & ATMEL_US_TXRDY) {
513 UART_PUT_IDR(port, ATMEL_US_TXRDY);
514 tasklet_schedule(&atmel_port->tasklet);
515 }
1ecc26bd 516 }
b843aa21
RB
517}
518
519/*
520 * status flags interrupt handler.
521 */
522static void
523atmel_handle_status(struct uart_port *port, unsigned int pending,
524 unsigned int status)
525{
c811ab8c 526 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1ecc26bd 527
b843aa21 528 if (pending & (ATMEL_US_RIIC | ATMEL_US_DSRIC | ATMEL_US_DCDIC
1ecc26bd
RB
529 | ATMEL_US_CTSIC)) {
530 atmel_port->irq_status = status;
531 tasklet_schedule(&atmel_port->tasklet);
532 }
b843aa21
RB
533}
534
1e6c9c28
AV
535/*
536 * Interrupt handler
537 */
7d12e780 538static irqreturn_t atmel_interrupt(int irq, void *dev_id)
1e6c9c28
AV
539{
540 struct uart_port *port = dev_id;
541 unsigned int status, pending, pass_counter = 0;
542
a6670615
CC
543 do {
544 status = UART_GET_CSR(port);
545 pending = status & UART_GET_IMR(port);
546 if (!pending)
547 break;
548
b843aa21
RB
549 atmel_handle_receive(port, pending);
550 atmel_handle_status(port, pending, status);
551 atmel_handle_transmit(port, pending);
a6670615 552 } while (pass_counter++ < ATMEL_ISR_PASS_LIMIT);
afefc415 553
0400b697 554 return pass_counter ? IRQ_HANDLED : IRQ_NONE;
a6670615 555}
1e6c9c28 556
a6670615
CC
557/*
558 * Called from tasklet with ENDTX and TXBUFE interrupts disabled.
559 */
560static void atmel_tx_dma(struct uart_port *port)
561{
c811ab8c 562 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
ebd2c8f6 563 struct circ_buf *xmit = &port->state->xmit;
a6670615
CC
564 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
565 int count;
566
ba0657ff
MT
567 /* nothing left to transmit? */
568 if (UART_GET_TCR(port))
569 return;
570
a6670615
CC
571 xmit->tail += pdc->ofs;
572 xmit->tail &= UART_XMIT_SIZE - 1;
573
574 port->icount.tx += pdc->ofs;
575 pdc->ofs = 0;
576
ba0657ff 577 /* more to transmit - setup next transfer */
a6670615 578
ba0657ff
MT
579 /* disable PDC transmit */
580 UART_PUT_PTCR(port, ATMEL_PDC_TXTDIS);
581
1f14081d 582 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) {
a6670615
CC
583 dma_sync_single_for_device(port->dev,
584 pdc->dma_addr,
585 pdc->dma_size,
586 DMA_TO_DEVICE);
587
588 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
589 pdc->ofs = count;
590
591 UART_PUT_TPR(port, pdc->dma_addr + xmit->tail);
592 UART_PUT_TCR(port, count);
593 /* re-enable PDC transmit and interrupts */
594 UART_PUT_PTCR(port, ATMEL_PDC_TXTEN);
595 UART_PUT_IER(port, ATMEL_US_ENDTX | ATMEL_US_TXBUFE);
1e6c9c28 596 }
a6670615
CC
597
598 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
599 uart_write_wakeup(port);
1e6c9c28
AV
600}
601
1ecc26bd
RB
602static void atmel_rx_from_ring(struct uart_port *port)
603{
c811ab8c 604 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1ecc26bd
RB
605 struct circ_buf *ring = &atmel_port->rx_ring;
606 unsigned int flg;
607 unsigned int status;
608
609 while (ring->head != ring->tail) {
610 struct atmel_uart_char c;
611
612 /* Make sure c is loaded after head. */
613 smp_rmb();
614
615 c = ((struct atmel_uart_char *)ring->buf)[ring->tail];
616
617 ring->tail = (ring->tail + 1) & (ATMEL_SERIAL_RINGSIZE - 1);
618
619 port->icount.rx++;
620 status = c.status;
621 flg = TTY_NORMAL;
622
623 /*
624 * note that the error handling code is
625 * out of the main execution path
626 */
627 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME
628 | ATMEL_US_OVRE | ATMEL_US_RXBRK))) {
629 if (status & ATMEL_US_RXBRK) {
630 /* ignore side-effect */
631 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME);
632
633 port->icount.brk++;
634 if (uart_handle_break(port))
635 continue;
636 }
637 if (status & ATMEL_US_PARE)
638 port->icount.parity++;
639 if (status & ATMEL_US_FRAME)
640 port->icount.frame++;
641 if (status & ATMEL_US_OVRE)
642 port->icount.overrun++;
643
644 status &= port->read_status_mask;
645
646 if (status & ATMEL_US_RXBRK)
647 flg = TTY_BREAK;
648 else if (status & ATMEL_US_PARE)
649 flg = TTY_PARITY;
650 else if (status & ATMEL_US_FRAME)
651 flg = TTY_FRAME;
652 }
653
654
655 if (uart_handle_sysrq_char(port, c.ch))
656 continue;
657
658 uart_insert_char(port, status, ATMEL_US_OVRE, c.ch, flg);
659 }
660
661 /*
662 * Drop the lock here since it might end up calling
663 * uart_start(), which takes the lock.
664 */
665 spin_unlock(&port->lock);
ebd2c8f6 666 tty_flip_buffer_push(port->state->port.tty);
1ecc26bd
RB
667 spin_lock(&port->lock);
668}
669
a6670615
CC
670static void atmel_rx_from_dma(struct uart_port *port)
671{
c811ab8c 672 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
ebd2c8f6 673 struct tty_struct *tty = port->state->port.tty;
a6670615
CC
674 struct atmel_dma_buffer *pdc;
675 int rx_idx = atmel_port->pdc_rx_idx;
676 unsigned int head;
677 unsigned int tail;
678 unsigned int count;
679
680 do {
681 /* Reset the UART timeout early so that we don't miss one */
682 UART_PUT_CR(port, ATMEL_US_STTTO);
683
684 pdc = &atmel_port->pdc_rx[rx_idx];
685 head = UART_GET_RPR(port) - pdc->dma_addr;
686 tail = pdc->ofs;
687
688 /* If the PDC has switched buffers, RPR won't contain
689 * any address within the current buffer. Since head
690 * is unsigned, we just need a one-way comparison to
691 * find out.
692 *
693 * In this case, we just need to consume the entire
694 * buffer and resubmit it for DMA. This will clear the
695 * ENDRX bit as well, so that we can safely re-enable
696 * all interrupts below.
697 */
698 head = min(head, pdc->dma_size);
699
700 if (likely(head != tail)) {
701 dma_sync_single_for_cpu(port->dev, pdc->dma_addr,
702 pdc->dma_size, DMA_FROM_DEVICE);
703
704 /*
705 * head will only wrap around when we recycle
706 * the DMA buffer, and when that happens, we
707 * explicitly set tail to 0. So head will
708 * always be greater than tail.
709 */
710 count = head - tail;
711
712 tty_insert_flip_string(tty, pdc->buf + pdc->ofs, count);
713
714 dma_sync_single_for_device(port->dev, pdc->dma_addr,
715 pdc->dma_size, DMA_FROM_DEVICE);
716
717 port->icount.rx += count;
718 pdc->ofs = head;
719 }
720
721 /*
722 * If the current buffer is full, we need to check if
723 * the next one contains any additional data.
724 */
725 if (head >= pdc->dma_size) {
726 pdc->ofs = 0;
727 UART_PUT_RNPR(port, pdc->dma_addr);
728 UART_PUT_RNCR(port, pdc->dma_size);
729
730 rx_idx = !rx_idx;
731 atmel_port->pdc_rx_idx = rx_idx;
732 }
733 } while (head >= pdc->dma_size);
734
735 /*
736 * Drop the lock here since it might end up calling
737 * uart_start(), which takes the lock.
738 */
739 spin_unlock(&port->lock);
740 tty_flip_buffer_push(tty);
741 spin_lock(&port->lock);
742
743 UART_PUT_IER(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
744}
745
1ecc26bd
RB
746/*
747 * tasklet handling tty stuff outside the interrupt handler.
748 */
749static void atmel_tasklet_func(unsigned long data)
750{
751 struct uart_port *port = (struct uart_port *)data;
c811ab8c 752 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1ecc26bd
RB
753 unsigned int status;
754 unsigned int status_change;
755
756 /* The interrupt handler does not take the lock */
757 spin_lock(&port->lock);
758
a6670615
CC
759 if (atmel_use_dma_tx(port))
760 atmel_tx_dma(port);
761 else
762 atmel_tx_chars(port);
1ecc26bd
RB
763
764 status = atmel_port->irq_status;
765 status_change = status ^ atmel_port->irq_status_prev;
766
767 if (status_change & (ATMEL_US_RI | ATMEL_US_DSR
768 | ATMEL_US_DCD | ATMEL_US_CTS)) {
769 /* TODO: All reads to CSR will clear these interrupts! */
770 if (status_change & ATMEL_US_RI)
771 port->icount.rng++;
772 if (status_change & ATMEL_US_DSR)
773 port->icount.dsr++;
774 if (status_change & ATMEL_US_DCD)
775 uart_handle_dcd_change(port, !(status & ATMEL_US_DCD));
776 if (status_change & ATMEL_US_CTS)
777 uart_handle_cts_change(port, !(status & ATMEL_US_CTS));
778
bdc04e31 779 wake_up_interruptible(&port->state->port.delta_msr_wait);
1ecc26bd
RB
780
781 atmel_port->irq_status_prev = status;
782 }
783
a6670615
CC
784 if (atmel_use_dma_rx(port))
785 atmel_rx_from_dma(port);
786 else
787 atmel_rx_from_ring(port);
1ecc26bd
RB
788
789 spin_unlock(&port->lock);
790}
791
1e6c9c28
AV
792/*
793 * Perform initialization and enable port for reception
794 */
7192f92c 795static int atmel_startup(struct uart_port *port)
1e6c9c28 796{
c811ab8c 797 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
ebd2c8f6 798 struct tty_struct *tty = port->state->port.tty;
1e6c9c28
AV
799 int retval;
800
801 /*
802 * Ensure that no interrupts are enabled otherwise when
803 * request_irq() is called we could get stuck trying to
804 * handle an unexpected interrupt
805 */
806 UART_PUT_IDR(port, -1);
807
808 /*
809 * Allocate the IRQ
810 */
b843aa21 811 retval = request_irq(port->irq, atmel_interrupt, IRQF_SHARED,
ae161068 812 tty ? tty->name : "atmel_serial", port);
1e6c9c28 813 if (retval) {
7192f92c 814 printk("atmel_serial: atmel_startup - Can't get irq\n");
1e6c9c28
AV
815 return retval;
816 }
817
a6670615
CC
818 /*
819 * Initialize DMA (if necessary)
820 */
821 if (atmel_use_dma_rx(port)) {
822 int i;
823
824 for (i = 0; i < 2; i++) {
825 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i];
826
827 pdc->buf = kmalloc(PDC_BUFFER_SIZE, GFP_KERNEL);
828 if (pdc->buf == NULL) {
829 if (i != 0) {
830 dma_unmap_single(port->dev,
831 atmel_port->pdc_rx[0].dma_addr,
832 PDC_BUFFER_SIZE,
833 DMA_FROM_DEVICE);
834 kfree(atmel_port->pdc_rx[0].buf);
835 }
836 free_irq(port->irq, port);
837 return -ENOMEM;
838 }
839 pdc->dma_addr = dma_map_single(port->dev,
840 pdc->buf,
841 PDC_BUFFER_SIZE,
842 DMA_FROM_DEVICE);
843 pdc->dma_size = PDC_BUFFER_SIZE;
844 pdc->ofs = 0;
845 }
846
847 atmel_port->pdc_rx_idx = 0;
848
849 UART_PUT_RPR(port, atmel_port->pdc_rx[0].dma_addr);
850 UART_PUT_RCR(port, PDC_BUFFER_SIZE);
851
852 UART_PUT_RNPR(port, atmel_port->pdc_rx[1].dma_addr);
853 UART_PUT_RNCR(port, PDC_BUFFER_SIZE);
854 }
855 if (atmel_use_dma_tx(port)) {
856 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
ebd2c8f6 857 struct circ_buf *xmit = &port->state->xmit;
a6670615
CC
858
859 pdc->buf = xmit->buf;
860 pdc->dma_addr = dma_map_single(port->dev,
861 pdc->buf,
862 UART_XMIT_SIZE,
863 DMA_TO_DEVICE);
864 pdc->dma_size = UART_XMIT_SIZE;
865 pdc->ofs = 0;
866 }
867
1e6c9c28
AV
868 /*
869 * If there is a specific "open" function (to register
870 * control line interrupts)
871 */
71f2e2b8
HS
872 if (atmel_open_hook) {
873 retval = atmel_open_hook(port);
1e6c9c28
AV
874 if (retval) {
875 free_irq(port->irq, port);
876 return retval;
877 }
878 }
879
27c0c8e5
AN
880 /* Save current CSR for comparison in atmel_tasklet_func() */
881 atmel_port->irq_status_prev = UART_GET_CSR(port);
882 atmel_port->irq_status = atmel_port->irq_status_prev;
883
1e6c9c28
AV
884 /*
885 * Finally, enable the serial port
886 */
7192f92c 887 UART_PUT_CR(port, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
b843aa21
RB
888 /* enable xmit & rcvr */
889 UART_PUT_CR(port, ATMEL_US_TXEN | ATMEL_US_RXEN);
afefc415 890
a6670615
CC
891 if (atmel_use_dma_rx(port)) {
892 /* set UART timeout */
893 UART_PUT_RTOR(port, PDC_RX_TIMEOUT);
894 UART_PUT_CR(port, ATMEL_US_STTTO);
895
896 UART_PUT_IER(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
897 /* enable PDC controller */
898 UART_PUT_PTCR(port, ATMEL_PDC_RXTEN);
899 } else {
900 /* enable receive only */
901 UART_PUT_IER(port, ATMEL_US_RXRDY);
902 }
afefc415 903
1e6c9c28
AV
904 return 0;
905}
906
907/*
908 * Disable the port
909 */
7192f92c 910static void atmel_shutdown(struct uart_port *port)
1e6c9c28 911{
c811ab8c 912 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
a6670615
CC
913 /*
914 * Ensure everything is stopped.
915 */
916 atmel_stop_rx(port);
917 atmel_stop_tx(port);
918
919 /*
920 * Shut-down the DMA.
921 */
922 if (atmel_use_dma_rx(port)) {
923 int i;
924
925 for (i = 0; i < 2; i++) {
926 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i];
927
928 dma_unmap_single(port->dev,
929 pdc->dma_addr,
930 pdc->dma_size,
931 DMA_FROM_DEVICE);
932 kfree(pdc->buf);
933 }
934 }
935 if (atmel_use_dma_tx(port)) {
936 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
937
938 dma_unmap_single(port->dev,
939 pdc->dma_addr,
940 pdc->dma_size,
941 DMA_TO_DEVICE);
942 }
943
1e6c9c28
AV
944 /*
945 * Disable all interrupts, port and break condition.
946 */
7192f92c 947 UART_PUT_CR(port, ATMEL_US_RSTSTA);
1e6c9c28
AV
948 UART_PUT_IDR(port, -1);
949
950 /*
951 * Free the interrupt
952 */
953 free_irq(port->irq, port);
954
955 /*
956 * If there is a specific "close" function (to unregister
957 * control line interrupts)
958 */
71f2e2b8
HS
959 if (atmel_close_hook)
960 atmel_close_hook(port);
1e6c9c28
AV
961}
962
9afd561a
HS
963/*
964 * Flush any TX data submitted for DMA. Called when the TX circular
965 * buffer is reset.
966 */
967static void atmel_flush_buffer(struct uart_port *port)
968{
969 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
970
971 if (atmel_use_dma_tx(port)) {
972 UART_PUT_TCR(port, 0);
973 atmel_port->pdc_tx.ofs = 0;
974 }
975}
976
1e6c9c28
AV
977/*
978 * Power / Clock management.
979 */
b843aa21
RB
980static void atmel_serial_pm(struct uart_port *port, unsigned int state,
981 unsigned int oldstate)
1e6c9c28 982{
c811ab8c 983 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
afefc415 984
1e6c9c28 985 switch (state) {
b843aa21
RB
986 case 0:
987 /*
988 * Enable the peripheral clock for this serial port.
989 * This is called on uart_open() or a resume event.
990 */
991 clk_enable(atmel_port->clk);
f05596db
AS
992
993 /* re-enable interrupts if we disabled some on suspend */
994 UART_PUT_IER(port, atmel_port->backup_imr);
b843aa21
RB
995 break;
996 case 3:
f05596db
AS
997 /* Back up the interrupt mask and disable all interrupts */
998 atmel_port->backup_imr = UART_GET_IMR(port);
999 UART_PUT_IDR(port, -1);
1000
b843aa21
RB
1001 /*
1002 * Disable the peripheral clock for this serial port.
1003 * This is called on uart_close() or a suspend event.
1004 */
1005 clk_disable(atmel_port->clk);
1006 break;
1007 default:
1008 printk(KERN_ERR "atmel_serial: unknown pm %d\n", state);
1e6c9c28
AV
1009 }
1010}
1011
1012/*
1013 * Change the port parameters
1014 */
b843aa21
RB
1015static void atmel_set_termios(struct uart_port *port, struct ktermios *termios,
1016 struct ktermios *old)
1e6c9c28
AV
1017{
1018 unsigned long flags;
1019 unsigned int mode, imr, quot, baud;
1020
03abeac0 1021 /* Get current mode register */
b843aa21 1022 mode = UART_GET_MR(port) & ~(ATMEL_US_USCLKS | ATMEL_US_CHRL
8e706c4d
PM
1023 | ATMEL_US_NBSTOP | ATMEL_US_PAR
1024 | ATMEL_US_USMODE);
03abeac0 1025
b843aa21 1026 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
1e6c9c28
AV
1027 quot = uart_get_divisor(port, baud);
1028
b843aa21 1029 if (quot > 65535) { /* BRGR is 16-bit, so switch to slower clock */
03abeac0
AV
1030 quot /= 8;
1031 mode |= ATMEL_US_USCLKS_MCK_DIV8;
1032 }
1e6c9c28
AV
1033
1034 /* byte size */
1035 switch (termios->c_cflag & CSIZE) {
1036 case CS5:
7192f92c 1037 mode |= ATMEL_US_CHRL_5;
1e6c9c28
AV
1038 break;
1039 case CS6:
7192f92c 1040 mode |= ATMEL_US_CHRL_6;
1e6c9c28
AV
1041 break;
1042 case CS7:
7192f92c 1043 mode |= ATMEL_US_CHRL_7;
1e6c9c28
AV
1044 break;
1045 default:
7192f92c 1046 mode |= ATMEL_US_CHRL_8;
1e6c9c28
AV
1047 break;
1048 }
1049
1050 /* stop bits */
1051 if (termios->c_cflag & CSTOPB)
7192f92c 1052 mode |= ATMEL_US_NBSTOP_2;
1e6c9c28
AV
1053
1054 /* parity */
1055 if (termios->c_cflag & PARENB) {
b843aa21
RB
1056 /* Mark or Space parity */
1057 if (termios->c_cflag & CMSPAR) {
1e6c9c28 1058 if (termios->c_cflag & PARODD)
7192f92c 1059 mode |= ATMEL_US_PAR_MARK;
1e6c9c28 1060 else
7192f92c 1061 mode |= ATMEL_US_PAR_SPACE;
b843aa21 1062 } else if (termios->c_cflag & PARODD)
7192f92c 1063 mode |= ATMEL_US_PAR_ODD;
1e6c9c28 1064 else
7192f92c 1065 mode |= ATMEL_US_PAR_EVEN;
b843aa21 1066 } else
7192f92c 1067 mode |= ATMEL_US_PAR_NONE;
1e6c9c28 1068
8e706c4d
PM
1069 /* hardware handshake (RTS/CTS) */
1070 if (termios->c_cflag & CRTSCTS)
1071 mode |= ATMEL_US_USMODE_HWHS;
1072 else
1073 mode |= ATMEL_US_USMODE_NORMAL;
1074
1e6c9c28
AV
1075 spin_lock_irqsave(&port->lock, flags);
1076
7192f92c 1077 port->read_status_mask = ATMEL_US_OVRE;
1e6c9c28 1078 if (termios->c_iflag & INPCK)
7192f92c 1079 port->read_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE);
1e6c9c28 1080 if (termios->c_iflag & (BRKINT | PARMRK))
7192f92c 1081 port->read_status_mask |= ATMEL_US_RXBRK;
1e6c9c28 1082
a6670615
CC
1083 if (atmel_use_dma_rx(port))
1084 /* need to enable error interrupts */
1085 UART_PUT_IER(port, port->read_status_mask);
1086
1e6c9c28
AV
1087 /*
1088 * Characters to ignore
1089 */
1090 port->ignore_status_mask = 0;
1091 if (termios->c_iflag & IGNPAR)
7192f92c 1092 port->ignore_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE);
1e6c9c28 1093 if (termios->c_iflag & IGNBRK) {
7192f92c 1094 port->ignore_status_mask |= ATMEL_US_RXBRK;
1e6c9c28
AV
1095 /*
1096 * If we're ignoring parity and break indicators,
1097 * ignore overruns too (for real raw support).
1098 */
1099 if (termios->c_iflag & IGNPAR)
7192f92c 1100 port->ignore_status_mask |= ATMEL_US_OVRE;
1e6c9c28 1101 }
b843aa21 1102 /* TODO: Ignore all characters if CREAD is set.*/
1e6c9c28
AV
1103
1104 /* update the per-port timeout */
1105 uart_update_timeout(port, termios->c_cflag, baud);
1106
0ccad870
HS
1107 /*
1108 * save/disable interrupts. The tty layer will ensure that the
1109 * transmitter is empty if requested by the caller, so there's
1110 * no need to wait for it here.
1111 */
b843aa21
RB
1112 imr = UART_GET_IMR(port);
1113 UART_PUT_IDR(port, -1);
1e6c9c28
AV
1114
1115 /* disable receiver and transmitter */
7192f92c 1116 UART_PUT_CR(port, ATMEL_US_TXDIS | ATMEL_US_RXDIS);
1e6c9c28
AV
1117
1118 /* set the parity, stop bits and data size */
1119 UART_PUT_MR(port, mode);
1120
1121 /* set the baud rate */
1122 UART_PUT_BRGR(port, quot);
7192f92c
HS
1123 UART_PUT_CR(port, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
1124 UART_PUT_CR(port, ATMEL_US_TXEN | ATMEL_US_RXEN);
1e6c9c28
AV
1125
1126 /* restore interrupts */
1127 UART_PUT_IER(port, imr);
1128
1129 /* CTS flow-control and modem-status interrupts */
1130 if (UART_ENABLE_MS(port, termios->c_cflag))
1131 port->ops->enable_ms(port);
1132
1133 spin_unlock_irqrestore(&port->lock, flags);
1134}
1135
1136/*
1137 * Return string describing the specified port
1138 */
7192f92c 1139static const char *atmel_type(struct uart_port *port)
1e6c9c28 1140{
9ab4f88b 1141 return (port->type == PORT_ATMEL) ? "ATMEL_SERIAL" : NULL;
1e6c9c28
AV
1142}
1143
1144/*
1145 * Release the memory region(s) being used by 'port'.
1146 */
7192f92c 1147static void atmel_release_port(struct uart_port *port)
1e6c9c28 1148{
afefc415
AV
1149 struct platform_device *pdev = to_platform_device(port->dev);
1150 int size = pdev->resource[0].end - pdev->resource[0].start + 1;
1151
1152 release_mem_region(port->mapbase, size);
1153
1154 if (port->flags & UPF_IOREMAP) {
1155 iounmap(port->membase);
1156 port->membase = NULL;
1157 }
1e6c9c28
AV
1158}
1159
1160/*
1161 * Request the memory region(s) being used by 'port'.
1162 */
7192f92c 1163static int atmel_request_port(struct uart_port *port)
1e6c9c28 1164{
afefc415
AV
1165 struct platform_device *pdev = to_platform_device(port->dev);
1166 int size = pdev->resource[0].end - pdev->resource[0].start + 1;
1167
7192f92c 1168 if (!request_mem_region(port->mapbase, size, "atmel_serial"))
afefc415
AV
1169 return -EBUSY;
1170
1171 if (port->flags & UPF_IOREMAP) {
1172 port->membase = ioremap(port->mapbase, size);
1173 if (port->membase == NULL) {
1174 release_mem_region(port->mapbase, size);
1175 return -ENOMEM;
1176 }
1177 }
1e6c9c28 1178
afefc415 1179 return 0;
1e6c9c28
AV
1180}
1181
1182/*
1183 * Configure/autoconfigure the port.
1184 */
7192f92c 1185static void atmel_config_port(struct uart_port *port, int flags)
1e6c9c28
AV
1186{
1187 if (flags & UART_CONFIG_TYPE) {
9ab4f88b 1188 port->type = PORT_ATMEL;
7192f92c 1189 atmel_request_port(port);
1e6c9c28
AV
1190 }
1191}
1192
1193/*
1194 * Verify the new serial_struct (for TIOCSSERIAL).
1195 */
7192f92c 1196static int atmel_verify_port(struct uart_port *port, struct serial_struct *ser)
1e6c9c28
AV
1197{
1198 int ret = 0;
9ab4f88b 1199 if (ser->type != PORT_UNKNOWN && ser->type != PORT_ATMEL)
1e6c9c28
AV
1200 ret = -EINVAL;
1201 if (port->irq != ser->irq)
1202 ret = -EINVAL;
1203 if (ser->io_type != SERIAL_IO_MEM)
1204 ret = -EINVAL;
1205 if (port->uartclk / 16 != ser->baud_base)
1206 ret = -EINVAL;
1207 if ((void *)port->mapbase != ser->iomem_base)
1208 ret = -EINVAL;
1209 if (port->iobase != ser->port)
1210 ret = -EINVAL;
1211 if (ser->hub6 != 0)
1212 ret = -EINVAL;
1213 return ret;
1214}
1215
8fe2d541
AT
1216#ifdef CONFIG_CONSOLE_POLL
1217static int atmel_poll_get_char(struct uart_port *port)
1218{
1219 while (!(UART_GET_CSR(port) & ATMEL_US_RXRDY))
1220 cpu_relax();
1221
1222 return UART_GET_CHAR(port);
1223}
1224
1225static void atmel_poll_put_char(struct uart_port *port, unsigned char ch)
1226{
1227 while (!(UART_GET_CSR(port) & ATMEL_US_TXRDY))
1228 cpu_relax();
1229
1230 UART_PUT_CHAR(port, ch);
1231}
1232#endif
1233
7192f92c
HS
1234static struct uart_ops atmel_pops = {
1235 .tx_empty = atmel_tx_empty,
1236 .set_mctrl = atmel_set_mctrl,
1237 .get_mctrl = atmel_get_mctrl,
1238 .stop_tx = atmel_stop_tx,
1239 .start_tx = atmel_start_tx,
1240 .stop_rx = atmel_stop_rx,
1241 .enable_ms = atmel_enable_ms,
1242 .break_ctl = atmel_break_ctl,
1243 .startup = atmel_startup,
1244 .shutdown = atmel_shutdown,
9afd561a 1245 .flush_buffer = atmel_flush_buffer,
7192f92c
HS
1246 .set_termios = atmel_set_termios,
1247 .type = atmel_type,
1248 .release_port = atmel_release_port,
1249 .request_port = atmel_request_port,
1250 .config_port = atmel_config_port,
1251 .verify_port = atmel_verify_port,
1252 .pm = atmel_serial_pm,
8fe2d541
AT
1253#ifdef CONFIG_CONSOLE_POLL
1254 .poll_get_char = atmel_poll_get_char,
1255 .poll_put_char = atmel_poll_put_char,
1256#endif
1e6c9c28
AV
1257};
1258
afefc415
AV
1259/*
1260 * Configure the port from the platform device resource info.
1261 */
b843aa21
RB
1262static void __devinit atmel_init_port(struct atmel_uart_port *atmel_port,
1263 struct platform_device *pdev)
1e6c9c28 1264{
7192f92c 1265 struct uart_port *port = &atmel_port->uart;
73e2798b 1266 struct atmel_uart_data *data = pdev->dev.platform_data;
afefc415
AV
1267
1268 port->iotype = UPIO_MEM;
a14d5273 1269 port->flags = UPF_BOOT_AUTOCONF;
7192f92c 1270 port->ops = &atmel_pops;
a14d5273 1271 port->fifosize = 1;
afefc415
AV
1272 port->line = pdev->id;
1273 port->dev = &pdev->dev;
1274
1275 port->mapbase = pdev->resource[0].start;
1276 port->irq = pdev->resource[1].start;
1277
1ecc26bd
RB
1278 tasklet_init(&atmel_port->tasklet, atmel_tasklet_func,
1279 (unsigned long)port);
1280
1281 memset(&atmel_port->rx_ring, 0, sizeof(atmel_port->rx_ring));
1282
75d35213
HS
1283 if (data->regs)
1284 /* Already mapped by setup code */
1285 port->membase = data->regs;
afefc415
AV
1286 else {
1287 port->flags |= UPF_IOREMAP;
1288 port->membase = NULL;
1289 }
1e6c9c28 1290
b843aa21
RB
1291 /* for console, the clock could already be configured */
1292 if (!atmel_port->clk) {
7192f92c
HS
1293 atmel_port->clk = clk_get(&pdev->dev, "usart");
1294 clk_enable(atmel_port->clk);
1295 port->uartclk = clk_get_rate(atmel_port->clk);
06a7f058
DB
1296 clk_disable(atmel_port->clk);
1297 /* only enable clock when USART is in use */
afefc415 1298 }
a6670615
CC
1299
1300 atmel_port->use_dma_rx = data->use_dma_rx;
1301 atmel_port->use_dma_tx = data->use_dma_tx;
1302 if (atmel_use_dma_tx(port))
1303 port->fifosize = PDC_BUFFER_SIZE;
1e6c9c28
AV
1304}
1305
afefc415
AV
1306/*
1307 * Register board-specific modem-control line handlers.
1308 */
71f2e2b8 1309void __init atmel_register_uart_fns(struct atmel_port_fns *fns)
1e6c9c28
AV
1310{
1311 if (fns->enable_ms)
7192f92c 1312 atmel_pops.enable_ms = fns->enable_ms;
1e6c9c28 1313 if (fns->get_mctrl)
7192f92c 1314 atmel_pops.get_mctrl = fns->get_mctrl;
1e6c9c28 1315 if (fns->set_mctrl)
7192f92c 1316 atmel_pops.set_mctrl = fns->set_mctrl;
71f2e2b8
HS
1317 atmel_open_hook = fns->open;
1318 atmel_close_hook = fns->close;
7192f92c
HS
1319 atmel_pops.pm = fns->pm;
1320 atmel_pops.set_wake = fns->set_wake;
1e6c9c28
AV
1321}
1322
749c4e60 1323#ifdef CONFIG_SERIAL_ATMEL_CONSOLE
7192f92c 1324static void atmel_console_putchar(struct uart_port *port, int ch)
d358788f 1325{
7192f92c 1326 while (!(UART_GET_CSR(port) & ATMEL_US_TXRDY))
829dd811 1327 cpu_relax();
d358788f
RK
1328 UART_PUT_CHAR(port, ch);
1329}
1e6c9c28
AV
1330
1331/*
1332 * Interrupts are disabled on entering
1333 */
7192f92c 1334static void atmel_console_write(struct console *co, const char *s, u_int count)
1e6c9c28 1335{
7192f92c 1336 struct uart_port *port = &atmel_ports[co->index].uart;
d358788f 1337 unsigned int status, imr;
39d4c922 1338 unsigned int pdc_tx;
1e6c9c28
AV
1339
1340 /*
b843aa21 1341 * First, save IMR and then disable interrupts
1e6c9c28 1342 */
b843aa21 1343 imr = UART_GET_IMR(port);
7192f92c 1344 UART_PUT_IDR(port, ATMEL_US_RXRDY | ATMEL_US_TXRDY);
1e6c9c28 1345
39d4c922
MP
1346 /* Store PDC transmit status and disable it */
1347 pdc_tx = UART_GET_PTSR(port) & ATMEL_PDC_TXTEN;
1348 UART_PUT_PTCR(port, ATMEL_PDC_TXTDIS);
1349
7192f92c 1350 uart_console_write(port, s, count, atmel_console_putchar);
1e6c9c28
AV
1351
1352 /*
b843aa21
RB
1353 * Finally, wait for transmitter to become empty
1354 * and restore IMR
1e6c9c28
AV
1355 */
1356 do {
1357 status = UART_GET_CSR(port);
7192f92c 1358 } while (!(status & ATMEL_US_TXRDY));
39d4c922
MP
1359
1360 /* Restore PDC transmit status */
1361 if (pdc_tx)
1362 UART_PUT_PTCR(port, ATMEL_PDC_TXTEN);
1363
b843aa21
RB
1364 /* set interrupts back the way they were */
1365 UART_PUT_IER(port, imr);
1e6c9c28
AV
1366}
1367
1368/*
b843aa21
RB
1369 * If the port was already initialised (eg, by a boot loader),
1370 * try to determine the current setup.
1e6c9c28 1371 */
b843aa21
RB
1372static void __init atmel_console_get_options(struct uart_port *port, int *baud,
1373 int *parity, int *bits)
1e6c9c28
AV
1374{
1375 unsigned int mr, quot;
1376
1c0fd82f
HS
1377 /*
1378 * If the baud rate generator isn't running, the port wasn't
1379 * initialized by the boot loader.
1380 */
9c81c5c9 1381 quot = UART_GET_BRGR(port) & ATMEL_US_CD;
1c0fd82f
HS
1382 if (!quot)
1383 return;
1e6c9c28 1384
7192f92c
HS
1385 mr = UART_GET_MR(port) & ATMEL_US_CHRL;
1386 if (mr == ATMEL_US_CHRL_8)
1e6c9c28
AV
1387 *bits = 8;
1388 else
1389 *bits = 7;
1390
7192f92c
HS
1391 mr = UART_GET_MR(port) & ATMEL_US_PAR;
1392 if (mr == ATMEL_US_PAR_EVEN)
1e6c9c28 1393 *parity = 'e';
7192f92c 1394 else if (mr == ATMEL_US_PAR_ODD)
1e6c9c28
AV
1395 *parity = 'o';
1396
4d5e392c
HS
1397 /*
1398 * The serial core only rounds down when matching this to a
1399 * supported baud rate. Make sure we don't end up slightly
1400 * lower than one of those, as it would make us fall through
1401 * to a much lower baud rate than we really want.
1402 */
4d5e392c 1403 *baud = port->uartclk / (16 * (quot - 1));
1e6c9c28
AV
1404}
1405
7192f92c 1406static int __init atmel_console_setup(struct console *co, char *options)
1e6c9c28 1407{
7192f92c 1408 struct uart_port *port = &atmel_ports[co->index].uart;
1e6c9c28
AV
1409 int baud = 115200;
1410 int bits = 8;
1411 int parity = 'n';
1412 int flow = 'n';
1413
b843aa21
RB
1414 if (port->membase == NULL) {
1415 /* Port not initialized yet - delay setup */
afefc415 1416 return -ENODEV;
b843aa21 1417 }
1e6c9c28 1418
06a7f058
DB
1419 clk_enable(atmel_ports[co->index].clk);
1420
b843aa21 1421 UART_PUT_IDR(port, -1);
7192f92c
HS
1422 UART_PUT_CR(port, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
1423 UART_PUT_CR(port, ATMEL_US_TXEN | ATMEL_US_RXEN);
1e6c9c28
AV
1424
1425 if (options)
1426 uart_parse_options(options, &baud, &parity, &bits, &flow);
1427 else
7192f92c 1428 atmel_console_get_options(port, &baud, &parity, &bits);
1e6c9c28
AV
1429
1430 return uart_set_options(port, co, baud, parity, bits, flow);
1431}
1432
7192f92c 1433static struct uart_driver atmel_uart;
1e6c9c28 1434
7192f92c
HS
1435static struct console atmel_console = {
1436 .name = ATMEL_DEVICENAME,
1437 .write = atmel_console_write,
1e6c9c28 1438 .device = uart_console_device,
7192f92c 1439 .setup = atmel_console_setup,
1e6c9c28
AV
1440 .flags = CON_PRINTBUFFER,
1441 .index = -1,
7192f92c 1442 .data = &atmel_uart,
1e6c9c28
AV
1443};
1444
06a7f058 1445#define ATMEL_CONSOLE_DEVICE (&atmel_console)
1e6c9c28 1446
afefc415
AV
1447/*
1448 * Early console initialization (before VM subsystem initialized).
1449 */
7192f92c 1450static int __init atmel_console_init(void)
1e6c9c28 1451{
73e2798b 1452 if (atmel_default_console_device) {
b843aa21
RB
1453 add_preferred_console(ATMEL_DEVICENAME,
1454 atmel_default_console_device->id, NULL);
1455 atmel_init_port(&atmel_ports[atmel_default_console_device->id],
1456 atmel_default_console_device);
7192f92c 1457 register_console(&atmel_console);
afefc415 1458 }
1e6c9c28 1459
1e6c9c28
AV
1460 return 0;
1461}
b843aa21 1462
7192f92c 1463console_initcall(atmel_console_init);
1e6c9c28 1464
afefc415
AV
1465/*
1466 * Late console initialization.
1467 */
7192f92c 1468static int __init atmel_late_console_init(void)
afefc415 1469{
b843aa21
RB
1470 if (atmel_default_console_device
1471 && !(atmel_console.flags & CON_ENABLED))
7192f92c 1472 register_console(&atmel_console);
afefc415
AV
1473
1474 return 0;
1475}
b843aa21 1476
7192f92c 1477core_initcall(atmel_late_console_init);
afefc415 1478
dfa7f343
HS
1479static inline bool atmel_is_console_port(struct uart_port *port)
1480{
1481 return port->cons && port->cons->index == port->line;
1482}
1483
1e6c9c28 1484#else
7192f92c 1485#define ATMEL_CONSOLE_DEVICE NULL
dfa7f343
HS
1486
1487static inline bool atmel_is_console_port(struct uart_port *port)
1488{
1489 return false;
1490}
1e6c9c28
AV
1491#endif
1492
7192f92c 1493static struct uart_driver atmel_uart = {
b843aa21
RB
1494 .owner = THIS_MODULE,
1495 .driver_name = "atmel_serial",
1496 .dev_name = ATMEL_DEVICENAME,
1497 .major = SERIAL_ATMEL_MAJOR,
1498 .minor = MINOR_START,
1499 .nr = ATMEL_MAX_UART,
1500 .cons = ATMEL_CONSOLE_DEVICE,
1e6c9c28
AV
1501};
1502
afefc415 1503#ifdef CONFIG_PM
f826caa4
HS
1504static bool atmel_serial_clk_will_stop(void)
1505{
1506#ifdef CONFIG_ARCH_AT91
1507 return at91_suspend_entering_slow_clock();
1508#else
1509 return false;
1510#endif
1511}
1512
b843aa21
RB
1513static int atmel_serial_suspend(struct platform_device *pdev,
1514 pm_message_t state)
1e6c9c28 1515{
afefc415 1516 struct uart_port *port = platform_get_drvdata(pdev);
c811ab8c 1517 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
afefc415 1518
e1c609ef
HS
1519 if (atmel_is_console_port(port) && console_suspend_enabled) {
1520 /* Drain the TX shifter */
1521 while (!(UART_GET_CSR(port) & ATMEL_US_TXEMPTY))
1522 cpu_relax();
1523 }
1524
f05596db
AS
1525 /* we can not wake up if we're running on slow clock */
1526 atmel_port->may_wakeup = device_may_wakeup(&pdev->dev);
1527 if (atmel_serial_clk_will_stop())
1528 device_set_wakeup_enable(&pdev->dev, 0);
1529
1530 uart_suspend_port(&atmel_uart, port);
1e6c9c28 1531
afefc415
AV
1532 return 0;
1533}
1e6c9c28 1534
7192f92c 1535static int atmel_serial_resume(struct platform_device *pdev)
afefc415
AV
1536{
1537 struct uart_port *port = platform_get_drvdata(pdev);
c811ab8c 1538 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1e6c9c28 1539
f05596db
AS
1540 uart_resume_port(&atmel_uart, port);
1541 device_set_wakeup_enable(&pdev->dev, atmel_port->may_wakeup);
1e6c9c28
AV
1542
1543 return 0;
1544}
afefc415 1545#else
7192f92c
HS
1546#define atmel_serial_suspend NULL
1547#define atmel_serial_resume NULL
afefc415 1548#endif
1e6c9c28 1549
7192f92c 1550static int __devinit atmel_serial_probe(struct platform_device *pdev)
1e6c9c28 1551{
7192f92c 1552 struct atmel_uart_port *port;
1ecc26bd 1553 void *data;
afefc415 1554 int ret;
1e6c9c28 1555
9d09daf8 1556 BUILD_BUG_ON(ATMEL_SERIAL_RINGSIZE & (ATMEL_SERIAL_RINGSIZE - 1));
1ecc26bd 1557
7192f92c 1558 port = &atmel_ports[pdev->id];
f05596db
AS
1559 port->backup_imr = 0;
1560
7192f92c 1561 atmel_init_port(port, pdev);
1e6c9c28 1562
a6670615
CC
1563 if (!atmel_use_dma_rx(&port->uart)) {
1564 ret = -ENOMEM;
6433471d
HS
1565 data = kmalloc(sizeof(struct atmel_uart_char)
1566 * ATMEL_SERIAL_RINGSIZE, GFP_KERNEL);
a6670615
CC
1567 if (!data)
1568 goto err_alloc_ring;
1569 port->rx_ring.buf = data;
1570 }
1ecc26bd 1571
7192f92c 1572 ret = uart_add_one_port(&atmel_uart, &port->uart);
dfa7f343
HS
1573 if (ret)
1574 goto err_add_port;
1575
8da14b5f 1576#ifdef CONFIG_SERIAL_ATMEL_CONSOLE
06a7f058
DB
1577 if (atmel_is_console_port(&port->uart)
1578 && ATMEL_CONSOLE_DEVICE->flags & CON_ENABLED) {
1579 /*
1580 * The serial core enabled the clock for us, so undo
1581 * the clk_enable() in atmel_console_setup()
1582 */
1583 clk_disable(port->clk);
1584 }
8da14b5f 1585#endif
06a7f058 1586
dfa7f343
HS
1587 device_init_wakeup(&pdev->dev, 1);
1588 platform_set_drvdata(pdev, port);
1589
1590 return 0;
1591
1592err_add_port:
1ecc26bd
RB
1593 kfree(port->rx_ring.buf);
1594 port->rx_ring.buf = NULL;
1595err_alloc_ring:
dfa7f343 1596 if (!atmel_is_console_port(&port->uart)) {
dfa7f343
HS
1597 clk_put(port->clk);
1598 port->clk = NULL;
afefc415
AV
1599 }
1600
1601 return ret;
1602}
1603
7192f92c 1604static int __devexit atmel_serial_remove(struct platform_device *pdev)
afefc415
AV
1605{
1606 struct uart_port *port = platform_get_drvdata(pdev);
c811ab8c 1607 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
afefc415
AV
1608 int ret = 0;
1609
afefc415
AV
1610 device_init_wakeup(&pdev->dev, 0);
1611 platform_set_drvdata(pdev, NULL);
1612
dfa7f343
HS
1613 ret = uart_remove_one_port(&atmel_uart, port);
1614
1ecc26bd
RB
1615 tasklet_kill(&atmel_port->tasklet);
1616 kfree(atmel_port->rx_ring.buf);
1617
dfa7f343
HS
1618 /* "port" is allocated statically, so we shouldn't free it */
1619
dfa7f343 1620 clk_put(atmel_port->clk);
afefc415
AV
1621
1622 return ret;
1623}
1624
7192f92c
HS
1625static struct platform_driver atmel_serial_driver = {
1626 .probe = atmel_serial_probe,
1627 .remove = __devexit_p(atmel_serial_remove),
1628 .suspend = atmel_serial_suspend,
1629 .resume = atmel_serial_resume,
afefc415 1630 .driver = {
1e8ea802 1631 .name = "atmel_usart",
afefc415
AV
1632 .owner = THIS_MODULE,
1633 },
1634};
1635
7192f92c 1636static int __init atmel_serial_init(void)
afefc415
AV
1637{
1638 int ret;
1639
7192f92c 1640 ret = uart_register_driver(&atmel_uart);
afefc415
AV
1641 if (ret)
1642 return ret;
1643
7192f92c 1644 ret = platform_driver_register(&atmel_serial_driver);
afefc415 1645 if (ret)
7192f92c 1646 uart_unregister_driver(&atmel_uart);
afefc415
AV
1647
1648 return ret;
1649}
1650
7192f92c 1651static void __exit atmel_serial_exit(void)
afefc415 1652{
7192f92c
HS
1653 platform_driver_unregister(&atmel_serial_driver);
1654 uart_unregister_driver(&atmel_uart);
1e6c9c28
AV
1655}
1656
7192f92c
HS
1657module_init(atmel_serial_init);
1658module_exit(atmel_serial_exit);
1e6c9c28
AV
1659
1660MODULE_AUTHOR("Rick Bronson");
7192f92c 1661MODULE_DESCRIPTION("Atmel AT91 / AT32 serial port driver");
1e6c9c28 1662MODULE_LICENSE("GPL");
e169c139 1663MODULE_ALIAS("platform:atmel_usart");