memcg: check under limit at shrink_usage
[linux-2.6-block.git] / drivers / serial / atmel_serial.c
CommitLineData
1e6c9c28 1/*
c2f5ccfb 2 * linux/drivers/char/atmel_serial.c
1e6c9c28 3 *
7192f92c 4 * Driver for Atmel AT91 / AT32 Serial ports
1e6c9c28
AV
5 * Copyright (C) 2003 Rick Bronson
6 *
7 * Based on drivers/char/serial_sa1100.c, by Deep Blue Solutions Ltd.
8 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
9 *
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10 * DMA support added by Chip Coldwell.
11 *
1e6c9c28
AV
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 *
26 */
1e6c9c28
AV
27#include <linux/module.h>
28#include <linux/tty.h>
29#include <linux/ioport.h>
30#include <linux/slab.h>
31#include <linux/init.h>
32#include <linux/serial.h>
afefc415 33#include <linux/clk.h>
1e6c9c28
AV
34#include <linux/console.h>
35#include <linux/sysrq.h>
36#include <linux/tty_flip.h>
afefc415 37#include <linux/platform_device.h>
a6670615 38#include <linux/dma-mapping.h>
93a3ddc2 39#include <linux/atmel_pdc.h>
fa3218d8 40#include <linux/atmel_serial.h>
1e6c9c28
AV
41
42#include <asm/io.h>
43
afefc415 44#include <asm/mach/serial_at91.h>
a09e64fb 45#include <mach/board.h>
93a3ddc2 46
acca9b83 47#ifdef CONFIG_ARM
a09e64fb
RK
48#include <mach/cpu.h>
49#include <mach/gpio.h>
acca9b83 50#endif
1e6c9c28 51
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52#define PDC_BUFFER_SIZE 512
53/* Revisit: We should calculate this based on the actual port settings */
54#define PDC_RX_TIMEOUT (3 * 10) /* 3 bytes */
55
749c4e60 56#if defined(CONFIG_SERIAL_ATMEL_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
1e6c9c28
AV
57#define SUPPORT_SYSRQ
58#endif
59
60#include <linux/serial_core.h>
61
749c4e60 62#ifdef CONFIG_SERIAL_ATMEL_TTYAT
1e6c9c28
AV
63
64/* Use device name ttyAT, major 204 and minor 154-169. This is necessary if we
65 * should coexist with the 8250 driver, such as if we have an external 16C550
66 * UART. */
7192f92c 67#define SERIAL_ATMEL_MAJOR 204
1e6c9c28 68#define MINOR_START 154
7192f92c 69#define ATMEL_DEVICENAME "ttyAT"
1e6c9c28
AV
70
71#else
72
73/* Use device name ttyS, major 4, minor 64-68. This is the usual serial port
74 * name, but it is legally reserved for the 8250 driver. */
7192f92c 75#define SERIAL_ATMEL_MAJOR TTY_MAJOR
1e6c9c28 76#define MINOR_START 64
7192f92c 77#define ATMEL_DEVICENAME "ttyS"
1e6c9c28
AV
78
79#endif
80
7192f92c 81#define ATMEL_ISR_PASS_LIMIT 256
1e6c9c28 82
b843aa21 83/* UART registers. CR is write-only, hence no GET macro */
544fc728
HS
84#define UART_PUT_CR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_CR)
85#define UART_GET_MR(port) __raw_readl((port)->membase + ATMEL_US_MR)
86#define UART_PUT_MR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_MR)
87#define UART_PUT_IER(port,v) __raw_writel(v, (port)->membase + ATMEL_US_IER)
88#define UART_PUT_IDR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_IDR)
89#define UART_GET_IMR(port) __raw_readl((port)->membase + ATMEL_US_IMR)
90#define UART_GET_CSR(port) __raw_readl((port)->membase + ATMEL_US_CSR)
91#define UART_GET_CHAR(port) __raw_readl((port)->membase + ATMEL_US_RHR)
92#define UART_PUT_CHAR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_THR)
93#define UART_GET_BRGR(port) __raw_readl((port)->membase + ATMEL_US_BRGR)
94#define UART_PUT_BRGR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_BRGR)
95#define UART_PUT_RTOR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_RTOR)
96
1e6c9c28 97 /* PDC registers */
544fc728
HS
98#define UART_PUT_PTCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_PTCR)
99#define UART_GET_PTSR(port) __raw_readl((port)->membase + ATMEL_PDC_PTSR)
100
101#define UART_PUT_RPR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RPR)
102#define UART_GET_RPR(port) __raw_readl((port)->membase + ATMEL_PDC_RPR)
103#define UART_PUT_RCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RCR)
104#define UART_PUT_RNPR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RNPR)
105#define UART_PUT_RNCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RNCR)
106
107#define UART_PUT_TPR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_TPR)
108#define UART_PUT_TCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_TCR)
39d4c922 109#define UART_GET_TCR(port) __raw_readl((port)->membase + ATMEL_PDC_TCR)
1e6c9c28 110
71f2e2b8
HS
111static int (*atmel_open_hook)(struct uart_port *);
112static void (*atmel_close_hook)(struct uart_port *);
1e6c9c28 113
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114struct atmel_dma_buffer {
115 unsigned char *buf;
116 dma_addr_t dma_addr;
117 unsigned int dma_size;
118 unsigned int ofs;
119};
120
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121struct atmel_uart_char {
122 u16 status;
123 u16 ch;
124};
125
126#define ATMEL_SERIAL_RINGSIZE 1024
127
afefc415
AV
128/*
129 * We wrap our port structure around the generic uart_port.
130 */
7192f92c 131struct atmel_uart_port {
afefc415
AV
132 struct uart_port uart; /* uart */
133 struct clk *clk; /* uart clock */
134 unsigned short suspended; /* is port suspended? */
9e6077bd 135 int break_active; /* break being received */
1ecc26bd 136
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137 short use_dma_rx; /* enable PDC receiver */
138 short pdc_rx_idx; /* current PDC RX buffer */
139 struct atmel_dma_buffer pdc_rx[2]; /* PDC receier */
140
141 short use_dma_tx; /* enable PDC transmitter */
142 struct atmel_dma_buffer pdc_tx; /* PDC transmitter */
143
1ecc26bd
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144 struct tasklet_struct tasklet;
145 unsigned int irq_status;
146 unsigned int irq_status_prev;
147
148 struct circ_buf rx_ring;
afefc415
AV
149};
150
7192f92c 151static struct atmel_uart_port atmel_ports[ATMEL_MAX_UART];
afefc415 152
1e6c9c28 153#ifdef SUPPORT_SYSRQ
7192f92c 154static struct console atmel_console;
1e6c9c28
AV
155#endif
156
c811ab8c
HS
157static inline struct atmel_uart_port *
158to_atmel_uart_port(struct uart_port *uart)
159{
160 return container_of(uart, struct atmel_uart_port, uart);
161}
162
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163#ifdef CONFIG_SERIAL_ATMEL_PDC
164static bool atmel_use_dma_rx(struct uart_port *port)
165{
c811ab8c 166 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
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167
168 return atmel_port->use_dma_rx;
169}
170
171static bool atmel_use_dma_tx(struct uart_port *port)
172{
c811ab8c 173 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
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174
175 return atmel_port->use_dma_tx;
176}
177#else
178static bool atmel_use_dma_rx(struct uart_port *port)
179{
180 return false;
181}
182
183static bool atmel_use_dma_tx(struct uart_port *port)
184{
185 return false;
186}
187#endif
188
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AV
189/*
190 * Return TIOCSER_TEMT when transmitter FIFO and Shift register is empty.
191 */
7192f92c 192static u_int atmel_tx_empty(struct uart_port *port)
1e6c9c28 193{
7192f92c 194 return (UART_GET_CSR(port) & ATMEL_US_TXEMPTY) ? TIOCSER_TEMT : 0;
1e6c9c28
AV
195}
196
197/*
198 * Set state of the modem control output lines
199 */
7192f92c 200static void atmel_set_mctrl(struct uart_port *port, u_int mctrl)
1e6c9c28
AV
201{
202 unsigned int control = 0;
afefc415 203 unsigned int mode;
1e6c9c28 204
c2f5ccfb 205#ifdef CONFIG_ARCH_AT91RM9200
79da7a61 206 if (cpu_is_at91rm9200()) {
afefc415 207 /*
b843aa21
RB
208 * AT91RM9200 Errata #39: RTS0 is not internally connected
209 * to PA21. We need to drive the pin manually.
afefc415 210 */
72729910 211 if (port->mapbase == AT91RM9200_BASE_US0) {
afefc415 212 if (mctrl & TIOCM_RTS)
20e65276 213 at91_set_gpio_value(AT91_PIN_PA21, 0);
afefc415 214 else
20e65276 215 at91_set_gpio_value(AT91_PIN_PA21, 1);
afefc415 216 }
1e6c9c28 217 }
acca9b83 218#endif
1e6c9c28
AV
219
220 if (mctrl & TIOCM_RTS)
7192f92c 221 control |= ATMEL_US_RTSEN;
1e6c9c28 222 else
7192f92c 223 control |= ATMEL_US_RTSDIS;
1e6c9c28
AV
224
225 if (mctrl & TIOCM_DTR)
7192f92c 226 control |= ATMEL_US_DTREN;
1e6c9c28 227 else
7192f92c 228 control |= ATMEL_US_DTRDIS;
1e6c9c28 229
afefc415
AV
230 UART_PUT_CR(port, control);
231
232 /* Local loopback mode? */
7192f92c 233 mode = UART_GET_MR(port) & ~ATMEL_US_CHMODE;
afefc415 234 if (mctrl & TIOCM_LOOP)
7192f92c 235 mode |= ATMEL_US_CHMODE_LOC_LOOP;
afefc415 236 else
7192f92c 237 mode |= ATMEL_US_CHMODE_NORMAL;
afefc415 238 UART_PUT_MR(port, mode);
1e6c9c28
AV
239}
240
241/*
242 * Get state of the modem control input lines
243 */
7192f92c 244static u_int atmel_get_mctrl(struct uart_port *port)
1e6c9c28
AV
245{
246 unsigned int status, ret = 0;
247
248 status = UART_GET_CSR(port);
249
250 /*
251 * The control signals are active low.
252 */
7192f92c 253 if (!(status & ATMEL_US_DCD))
1e6c9c28 254 ret |= TIOCM_CD;
7192f92c 255 if (!(status & ATMEL_US_CTS))
1e6c9c28 256 ret |= TIOCM_CTS;
7192f92c 257 if (!(status & ATMEL_US_DSR))
1e6c9c28 258 ret |= TIOCM_DSR;
7192f92c 259 if (!(status & ATMEL_US_RI))
1e6c9c28
AV
260 ret |= TIOCM_RI;
261
262 return ret;
263}
264
265/*
266 * Stop transmitting.
267 */
7192f92c 268static void atmel_stop_tx(struct uart_port *port)
1e6c9c28 269{
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270 if (atmel_use_dma_tx(port)) {
271 /* disable PDC transmit */
272 UART_PUT_PTCR(port, ATMEL_PDC_TXTDIS);
273 UART_PUT_IDR(port, ATMEL_US_ENDTX | ATMEL_US_TXBUFE);
274 } else
275 UART_PUT_IDR(port, ATMEL_US_TXRDY);
1e6c9c28
AV
276}
277
278/*
279 * Start transmitting.
280 */
7192f92c 281static void atmel_start_tx(struct uart_port *port)
1e6c9c28 282{
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283 if (atmel_use_dma_tx(port)) {
284 if (UART_GET_PTSR(port) & ATMEL_PDC_TXTEN)
285 /* The transmitter is already running. Yes, we
286 really need this.*/
287 return;
288
289 UART_PUT_IER(port, ATMEL_US_ENDTX | ATMEL_US_TXBUFE);
290 /* re-enable PDC transmit */
291 UART_PUT_PTCR(port, ATMEL_PDC_TXTEN);
292 } else
293 UART_PUT_IER(port, ATMEL_US_TXRDY);
1e6c9c28
AV
294}
295
296/*
297 * Stop receiving - port is in process of being closed.
298 */
7192f92c 299static void atmel_stop_rx(struct uart_port *port)
1e6c9c28 300{
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301 if (atmel_use_dma_rx(port)) {
302 /* disable PDC receive */
303 UART_PUT_PTCR(port, ATMEL_PDC_RXTDIS);
304 UART_PUT_IDR(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
305 } else
306 UART_PUT_IDR(port, ATMEL_US_RXRDY);
1e6c9c28
AV
307}
308
309/*
310 * Enable modem status interrupts
311 */
7192f92c 312static void atmel_enable_ms(struct uart_port *port)
1e6c9c28 313{
b843aa21
RB
314 UART_PUT_IER(port, ATMEL_US_RIIC | ATMEL_US_DSRIC
315 | ATMEL_US_DCDIC | ATMEL_US_CTSIC);
1e6c9c28
AV
316}
317
318/*
319 * Control the transmission of a break signal
320 */
7192f92c 321static void atmel_break_ctl(struct uart_port *port, int break_state)
1e6c9c28
AV
322{
323 if (break_state != 0)
7192f92c 324 UART_PUT_CR(port, ATMEL_US_STTBRK); /* start break */
1e6c9c28 325 else
7192f92c 326 UART_PUT_CR(port, ATMEL_US_STPBRK); /* stop break */
1e6c9c28
AV
327}
328
1ecc26bd
RB
329/*
330 * Stores the incoming character in the ring buffer
331 */
332static void
333atmel_buffer_rx_char(struct uart_port *port, unsigned int status,
334 unsigned int ch)
335{
c811ab8c 336 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1ecc26bd
RB
337 struct circ_buf *ring = &atmel_port->rx_ring;
338 struct atmel_uart_char *c;
339
340 if (!CIRC_SPACE(ring->head, ring->tail, ATMEL_SERIAL_RINGSIZE))
341 /* Buffer overflow, ignore char */
342 return;
343
344 c = &((struct atmel_uart_char *)ring->buf)[ring->head];
345 c->status = status;
346 c->ch = ch;
347
348 /* Make sure the character is stored before we update head. */
349 smp_wmb();
350
351 ring->head = (ring->head + 1) & (ATMEL_SERIAL_RINGSIZE - 1);
352}
353
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354/*
355 * Deal with parity, framing and overrun errors.
356 */
357static void atmel_pdc_rxerr(struct uart_port *port, unsigned int status)
358{
359 /* clear error */
360 UART_PUT_CR(port, ATMEL_US_RSTSTA);
361
362 if (status & ATMEL_US_RXBRK) {
363 /* ignore side-effect */
364 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME);
365 port->icount.brk++;
366 }
367 if (status & ATMEL_US_PARE)
368 port->icount.parity++;
369 if (status & ATMEL_US_FRAME)
370 port->icount.frame++;
371 if (status & ATMEL_US_OVRE)
372 port->icount.overrun++;
373}
374
1e6c9c28
AV
375/*
376 * Characters received (called from interrupt handler)
377 */
7d12e780 378static void atmel_rx_chars(struct uart_port *port)
1e6c9c28 379{
c811ab8c 380 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1ecc26bd 381 unsigned int status, ch;
1e6c9c28 382
afefc415 383 status = UART_GET_CSR(port);
7192f92c 384 while (status & ATMEL_US_RXRDY) {
1e6c9c28
AV
385 ch = UART_GET_CHAR(port);
386
1e6c9c28
AV
387 /*
388 * note that the error handling code is
389 * out of the main execution path
390 */
9e6077bd
HS
391 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME
392 | ATMEL_US_OVRE | ATMEL_US_RXBRK)
393 || atmel_port->break_active)) {
1ecc26bd 394
b843aa21
RB
395 /* clear error */
396 UART_PUT_CR(port, ATMEL_US_RSTSTA);
1ecc26bd 397
9e6077bd
HS
398 if (status & ATMEL_US_RXBRK
399 && !atmel_port->break_active) {
9e6077bd
HS
400 atmel_port->break_active = 1;
401 UART_PUT_IER(port, ATMEL_US_RXBRK);
9e6077bd
HS
402 } else {
403 /*
404 * This is either the end-of-break
405 * condition or we've received at
406 * least one character without RXBRK
407 * being set. In both cases, the next
408 * RXBRK will indicate start-of-break.
409 */
410 UART_PUT_IDR(port, ATMEL_US_RXBRK);
411 status &= ~ATMEL_US_RXBRK;
412 atmel_port->break_active = 0;
afefc415 413 }
1e6c9c28
AV
414 }
415
1ecc26bd 416 atmel_buffer_rx_char(port, status, ch);
afefc415 417 status = UART_GET_CSR(port);
1e6c9c28
AV
418 }
419
1ecc26bd 420 tasklet_schedule(&atmel_port->tasklet);
1e6c9c28
AV
421}
422
423/*
1ecc26bd
RB
424 * Transmit characters (called from tasklet with TXRDY interrupt
425 * disabled)
1e6c9c28 426 */
7192f92c 427static void atmel_tx_chars(struct uart_port *port)
1e6c9c28
AV
428{
429 struct circ_buf *xmit = &port->info->xmit;
430
1ecc26bd 431 if (port->x_char && UART_GET_CSR(port) & ATMEL_US_TXRDY) {
1e6c9c28
AV
432 UART_PUT_CHAR(port, port->x_char);
433 port->icount.tx++;
434 port->x_char = 0;
1e6c9c28 435 }
1ecc26bd 436 if (uart_circ_empty(xmit) || uart_tx_stopped(port))
1e6c9c28 437 return;
1e6c9c28 438
7192f92c 439 while (UART_GET_CSR(port) & ATMEL_US_TXRDY) {
1e6c9c28
AV
440 UART_PUT_CHAR(port, xmit->buf[xmit->tail]);
441 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
442 port->icount.tx++;
443 if (uart_circ_empty(xmit))
444 break;
445 }
446
447 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
448 uart_write_wakeup(port);
449
1ecc26bd
RB
450 if (!uart_circ_empty(xmit))
451 UART_PUT_IER(port, ATMEL_US_TXRDY);
1e6c9c28
AV
452}
453
b843aa21
RB
454/*
455 * receive interrupt handler.
456 */
457static void
458atmel_handle_receive(struct uart_port *port, unsigned int pending)
459{
c811ab8c 460 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
b843aa21 461
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CC
462 if (atmel_use_dma_rx(port)) {
463 /*
464 * PDC receive. Just schedule the tasklet and let it
465 * figure out the details.
466 *
467 * TODO: We're not handling error flags correctly at
468 * the moment.
469 */
470 if (pending & (ATMEL_US_ENDRX | ATMEL_US_TIMEOUT)) {
471 UART_PUT_IDR(port, (ATMEL_US_ENDRX
472 | ATMEL_US_TIMEOUT));
473 tasklet_schedule(&atmel_port->tasklet);
474 }
475
476 if (pending & (ATMEL_US_RXBRK | ATMEL_US_OVRE |
477 ATMEL_US_FRAME | ATMEL_US_PARE))
478 atmel_pdc_rxerr(port, pending);
479 }
480
b843aa21
RB
481 /* Interrupt receive */
482 if (pending & ATMEL_US_RXRDY)
483 atmel_rx_chars(port);
484 else if (pending & ATMEL_US_RXBRK) {
485 /*
486 * End of break detected. If it came along with a
487 * character, atmel_rx_chars will handle it.
488 */
489 UART_PUT_CR(port, ATMEL_US_RSTSTA);
490 UART_PUT_IDR(port, ATMEL_US_RXBRK);
491 atmel_port->break_active = 0;
492 }
493}
494
495/*
1ecc26bd 496 * transmit interrupt handler. (Transmit is IRQF_NODELAY safe)
b843aa21
RB
497 */
498static void
499atmel_handle_transmit(struct uart_port *port, unsigned int pending)
500{
c811ab8c 501 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1ecc26bd 502
a6670615
CC
503 if (atmel_use_dma_tx(port)) {
504 /* PDC transmit */
505 if (pending & (ATMEL_US_ENDTX | ATMEL_US_TXBUFE)) {
506 UART_PUT_IDR(port, ATMEL_US_ENDTX | ATMEL_US_TXBUFE);
507 tasklet_schedule(&atmel_port->tasklet);
508 }
509 } else {
510 /* Interrupt transmit */
511 if (pending & ATMEL_US_TXRDY) {
512 UART_PUT_IDR(port, ATMEL_US_TXRDY);
513 tasklet_schedule(&atmel_port->tasklet);
514 }
1ecc26bd 515 }
b843aa21
RB
516}
517
518/*
519 * status flags interrupt handler.
520 */
521static void
522atmel_handle_status(struct uart_port *port, unsigned int pending,
523 unsigned int status)
524{
c811ab8c 525 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1ecc26bd 526
b843aa21 527 if (pending & (ATMEL_US_RIIC | ATMEL_US_DSRIC | ATMEL_US_DCDIC
1ecc26bd
RB
528 | ATMEL_US_CTSIC)) {
529 atmel_port->irq_status = status;
530 tasklet_schedule(&atmel_port->tasklet);
531 }
b843aa21
RB
532}
533
1e6c9c28
AV
534/*
535 * Interrupt handler
536 */
7d12e780 537static irqreturn_t atmel_interrupt(int irq, void *dev_id)
1e6c9c28
AV
538{
539 struct uart_port *port = dev_id;
540 unsigned int status, pending, pass_counter = 0;
541
a6670615
CC
542 do {
543 status = UART_GET_CSR(port);
544 pending = status & UART_GET_IMR(port);
545 if (!pending)
546 break;
547
b843aa21
RB
548 atmel_handle_receive(port, pending);
549 atmel_handle_status(port, pending, status);
550 atmel_handle_transmit(port, pending);
a6670615 551 } while (pass_counter++ < ATMEL_ISR_PASS_LIMIT);
afefc415 552
0400b697 553 return pass_counter ? IRQ_HANDLED : IRQ_NONE;
a6670615 554}
1e6c9c28 555
a6670615
CC
556/*
557 * Called from tasklet with ENDTX and TXBUFE interrupts disabled.
558 */
559static void atmel_tx_dma(struct uart_port *port)
560{
c811ab8c 561 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
a6670615
CC
562 struct circ_buf *xmit = &port->info->xmit;
563 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
564 int count;
565
ba0657ff
MT
566 /* nothing left to transmit? */
567 if (UART_GET_TCR(port))
568 return;
569
a6670615
CC
570 xmit->tail += pdc->ofs;
571 xmit->tail &= UART_XMIT_SIZE - 1;
572
573 port->icount.tx += pdc->ofs;
574 pdc->ofs = 0;
575
ba0657ff 576 /* more to transmit - setup next transfer */
a6670615 577
ba0657ff
MT
578 /* disable PDC transmit */
579 UART_PUT_PTCR(port, ATMEL_PDC_TXTDIS);
580
581 if (!uart_circ_empty(xmit)) {
a6670615
CC
582 dma_sync_single_for_device(port->dev,
583 pdc->dma_addr,
584 pdc->dma_size,
585 DMA_TO_DEVICE);
586
587 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
588 pdc->ofs = count;
589
590 UART_PUT_TPR(port, pdc->dma_addr + xmit->tail);
591 UART_PUT_TCR(port, count);
592 /* re-enable PDC transmit and interrupts */
593 UART_PUT_PTCR(port, ATMEL_PDC_TXTEN);
594 UART_PUT_IER(port, ATMEL_US_ENDTX | ATMEL_US_TXBUFE);
1e6c9c28 595 }
a6670615
CC
596
597 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
598 uart_write_wakeup(port);
1e6c9c28
AV
599}
600
1ecc26bd
RB
601static void atmel_rx_from_ring(struct uart_port *port)
602{
c811ab8c 603 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1ecc26bd
RB
604 struct circ_buf *ring = &atmel_port->rx_ring;
605 unsigned int flg;
606 unsigned int status;
607
608 while (ring->head != ring->tail) {
609 struct atmel_uart_char c;
610
611 /* Make sure c is loaded after head. */
612 smp_rmb();
613
614 c = ((struct atmel_uart_char *)ring->buf)[ring->tail];
615
616 ring->tail = (ring->tail + 1) & (ATMEL_SERIAL_RINGSIZE - 1);
617
618 port->icount.rx++;
619 status = c.status;
620 flg = TTY_NORMAL;
621
622 /*
623 * note that the error handling code is
624 * out of the main execution path
625 */
626 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME
627 | ATMEL_US_OVRE | ATMEL_US_RXBRK))) {
628 if (status & ATMEL_US_RXBRK) {
629 /* ignore side-effect */
630 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME);
631
632 port->icount.brk++;
633 if (uart_handle_break(port))
634 continue;
635 }
636 if (status & ATMEL_US_PARE)
637 port->icount.parity++;
638 if (status & ATMEL_US_FRAME)
639 port->icount.frame++;
640 if (status & ATMEL_US_OVRE)
641 port->icount.overrun++;
642
643 status &= port->read_status_mask;
644
645 if (status & ATMEL_US_RXBRK)
646 flg = TTY_BREAK;
647 else if (status & ATMEL_US_PARE)
648 flg = TTY_PARITY;
649 else if (status & ATMEL_US_FRAME)
650 flg = TTY_FRAME;
651 }
652
653
654 if (uart_handle_sysrq_char(port, c.ch))
655 continue;
656
657 uart_insert_char(port, status, ATMEL_US_OVRE, c.ch, flg);
658 }
659
660 /*
661 * Drop the lock here since it might end up calling
662 * uart_start(), which takes the lock.
663 */
664 spin_unlock(&port->lock);
b1d1619b 665 tty_flip_buffer_push(port->info->port.tty);
1ecc26bd
RB
666 spin_lock(&port->lock);
667}
668
a6670615
CC
669static void atmel_rx_from_dma(struct uart_port *port)
670{
c811ab8c 671 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
b1d1619b 672 struct tty_struct *tty = port->info->port.tty;
a6670615
CC
673 struct atmel_dma_buffer *pdc;
674 int rx_idx = atmel_port->pdc_rx_idx;
675 unsigned int head;
676 unsigned int tail;
677 unsigned int count;
678
679 do {
680 /* Reset the UART timeout early so that we don't miss one */
681 UART_PUT_CR(port, ATMEL_US_STTTO);
682
683 pdc = &atmel_port->pdc_rx[rx_idx];
684 head = UART_GET_RPR(port) - pdc->dma_addr;
685 tail = pdc->ofs;
686
687 /* If the PDC has switched buffers, RPR won't contain
688 * any address within the current buffer. Since head
689 * is unsigned, we just need a one-way comparison to
690 * find out.
691 *
692 * In this case, we just need to consume the entire
693 * buffer and resubmit it for DMA. This will clear the
694 * ENDRX bit as well, so that we can safely re-enable
695 * all interrupts below.
696 */
697 head = min(head, pdc->dma_size);
698
699 if (likely(head != tail)) {
700 dma_sync_single_for_cpu(port->dev, pdc->dma_addr,
701 pdc->dma_size, DMA_FROM_DEVICE);
702
703 /*
704 * head will only wrap around when we recycle
705 * the DMA buffer, and when that happens, we
706 * explicitly set tail to 0. So head will
707 * always be greater than tail.
708 */
709 count = head - tail;
710
711 tty_insert_flip_string(tty, pdc->buf + pdc->ofs, count);
712
713 dma_sync_single_for_device(port->dev, pdc->dma_addr,
714 pdc->dma_size, DMA_FROM_DEVICE);
715
716 port->icount.rx += count;
717 pdc->ofs = head;
718 }
719
720 /*
721 * If the current buffer is full, we need to check if
722 * the next one contains any additional data.
723 */
724 if (head >= pdc->dma_size) {
725 pdc->ofs = 0;
726 UART_PUT_RNPR(port, pdc->dma_addr);
727 UART_PUT_RNCR(port, pdc->dma_size);
728
729 rx_idx = !rx_idx;
730 atmel_port->pdc_rx_idx = rx_idx;
731 }
732 } while (head >= pdc->dma_size);
733
734 /*
735 * Drop the lock here since it might end up calling
736 * uart_start(), which takes the lock.
737 */
738 spin_unlock(&port->lock);
739 tty_flip_buffer_push(tty);
740 spin_lock(&port->lock);
741
742 UART_PUT_IER(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
743}
744
1ecc26bd
RB
745/*
746 * tasklet handling tty stuff outside the interrupt handler.
747 */
748static void atmel_tasklet_func(unsigned long data)
749{
750 struct uart_port *port = (struct uart_port *)data;
c811ab8c 751 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1ecc26bd
RB
752 unsigned int status;
753 unsigned int status_change;
754
755 /* The interrupt handler does not take the lock */
756 spin_lock(&port->lock);
757
a6670615
CC
758 if (atmel_use_dma_tx(port))
759 atmel_tx_dma(port);
760 else
761 atmel_tx_chars(port);
1ecc26bd
RB
762
763 status = atmel_port->irq_status;
764 status_change = status ^ atmel_port->irq_status_prev;
765
766 if (status_change & (ATMEL_US_RI | ATMEL_US_DSR
767 | ATMEL_US_DCD | ATMEL_US_CTS)) {
768 /* TODO: All reads to CSR will clear these interrupts! */
769 if (status_change & ATMEL_US_RI)
770 port->icount.rng++;
771 if (status_change & ATMEL_US_DSR)
772 port->icount.dsr++;
773 if (status_change & ATMEL_US_DCD)
774 uart_handle_dcd_change(port, !(status & ATMEL_US_DCD));
775 if (status_change & ATMEL_US_CTS)
776 uart_handle_cts_change(port, !(status & ATMEL_US_CTS));
777
778 wake_up_interruptible(&port->info->delta_msr_wait);
779
780 atmel_port->irq_status_prev = status;
781 }
782
a6670615
CC
783 if (atmel_use_dma_rx(port))
784 atmel_rx_from_dma(port);
785 else
786 atmel_rx_from_ring(port);
1ecc26bd
RB
787
788 spin_unlock(&port->lock);
789}
790
1e6c9c28
AV
791/*
792 * Perform initialization and enable port for reception
793 */
7192f92c 794static int atmel_startup(struct uart_port *port)
1e6c9c28 795{
c811ab8c 796 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
b1d1619b 797 struct tty_struct *tty = port->info->port.tty;
1e6c9c28
AV
798 int retval;
799
800 /*
801 * Ensure that no interrupts are enabled otherwise when
802 * request_irq() is called we could get stuck trying to
803 * handle an unexpected interrupt
804 */
805 UART_PUT_IDR(port, -1);
806
807 /*
808 * Allocate the IRQ
809 */
b843aa21 810 retval = request_irq(port->irq, atmel_interrupt, IRQF_SHARED,
ae161068 811 tty ? tty->name : "atmel_serial", port);
1e6c9c28 812 if (retval) {
7192f92c 813 printk("atmel_serial: atmel_startup - Can't get irq\n");
1e6c9c28
AV
814 return retval;
815 }
816
a6670615
CC
817 /*
818 * Initialize DMA (if necessary)
819 */
820 if (atmel_use_dma_rx(port)) {
821 int i;
822
823 for (i = 0; i < 2; i++) {
824 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i];
825
826 pdc->buf = kmalloc(PDC_BUFFER_SIZE, GFP_KERNEL);
827 if (pdc->buf == NULL) {
828 if (i != 0) {
829 dma_unmap_single(port->dev,
830 atmel_port->pdc_rx[0].dma_addr,
831 PDC_BUFFER_SIZE,
832 DMA_FROM_DEVICE);
833 kfree(atmel_port->pdc_rx[0].buf);
834 }
835 free_irq(port->irq, port);
836 return -ENOMEM;
837 }
838 pdc->dma_addr = dma_map_single(port->dev,
839 pdc->buf,
840 PDC_BUFFER_SIZE,
841 DMA_FROM_DEVICE);
842 pdc->dma_size = PDC_BUFFER_SIZE;
843 pdc->ofs = 0;
844 }
845
846 atmel_port->pdc_rx_idx = 0;
847
848 UART_PUT_RPR(port, atmel_port->pdc_rx[0].dma_addr);
849 UART_PUT_RCR(port, PDC_BUFFER_SIZE);
850
851 UART_PUT_RNPR(port, atmel_port->pdc_rx[1].dma_addr);
852 UART_PUT_RNCR(port, PDC_BUFFER_SIZE);
853 }
854 if (atmel_use_dma_tx(port)) {
855 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
856 struct circ_buf *xmit = &port->info->xmit;
857
858 pdc->buf = xmit->buf;
859 pdc->dma_addr = dma_map_single(port->dev,
860 pdc->buf,
861 UART_XMIT_SIZE,
862 DMA_TO_DEVICE);
863 pdc->dma_size = UART_XMIT_SIZE;
864 pdc->ofs = 0;
865 }
866
1e6c9c28
AV
867 /*
868 * If there is a specific "open" function (to register
869 * control line interrupts)
870 */
71f2e2b8
HS
871 if (atmel_open_hook) {
872 retval = atmel_open_hook(port);
1e6c9c28
AV
873 if (retval) {
874 free_irq(port->irq, port);
875 return retval;
876 }
877 }
878
1e6c9c28
AV
879 /*
880 * Finally, enable the serial port
881 */
7192f92c 882 UART_PUT_CR(port, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
b843aa21
RB
883 /* enable xmit & rcvr */
884 UART_PUT_CR(port, ATMEL_US_TXEN | ATMEL_US_RXEN);
afefc415 885
a6670615
CC
886 if (atmel_use_dma_rx(port)) {
887 /* set UART timeout */
888 UART_PUT_RTOR(port, PDC_RX_TIMEOUT);
889 UART_PUT_CR(port, ATMEL_US_STTTO);
890
891 UART_PUT_IER(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
892 /* enable PDC controller */
893 UART_PUT_PTCR(port, ATMEL_PDC_RXTEN);
894 } else {
895 /* enable receive only */
896 UART_PUT_IER(port, ATMEL_US_RXRDY);
897 }
afefc415 898
1e6c9c28
AV
899 return 0;
900}
901
902/*
903 * Disable the port
904 */
7192f92c 905static void atmel_shutdown(struct uart_port *port)
1e6c9c28 906{
c811ab8c 907 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
a6670615
CC
908 /*
909 * Ensure everything is stopped.
910 */
911 atmel_stop_rx(port);
912 atmel_stop_tx(port);
913
914 /*
915 * Shut-down the DMA.
916 */
917 if (atmel_use_dma_rx(port)) {
918 int i;
919
920 for (i = 0; i < 2; i++) {
921 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i];
922
923 dma_unmap_single(port->dev,
924 pdc->dma_addr,
925 pdc->dma_size,
926 DMA_FROM_DEVICE);
927 kfree(pdc->buf);
928 }
929 }
930 if (atmel_use_dma_tx(port)) {
931 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
932
933 dma_unmap_single(port->dev,
934 pdc->dma_addr,
935 pdc->dma_size,
936 DMA_TO_DEVICE);
937 }
938
1e6c9c28
AV
939 /*
940 * Disable all interrupts, port and break condition.
941 */
7192f92c 942 UART_PUT_CR(port, ATMEL_US_RSTSTA);
1e6c9c28
AV
943 UART_PUT_IDR(port, -1);
944
945 /*
946 * Free the interrupt
947 */
948 free_irq(port->irq, port);
949
950 /*
951 * If there is a specific "close" function (to unregister
952 * control line interrupts)
953 */
71f2e2b8
HS
954 if (atmel_close_hook)
955 atmel_close_hook(port);
1e6c9c28
AV
956}
957
9afd561a
HS
958/*
959 * Flush any TX data submitted for DMA. Called when the TX circular
960 * buffer is reset.
961 */
962static void atmel_flush_buffer(struct uart_port *port)
963{
964 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
965
966 if (atmel_use_dma_tx(port)) {
967 UART_PUT_TCR(port, 0);
968 atmel_port->pdc_tx.ofs = 0;
969 }
970}
971
1e6c9c28
AV
972/*
973 * Power / Clock management.
974 */
b843aa21
RB
975static void atmel_serial_pm(struct uart_port *port, unsigned int state,
976 unsigned int oldstate)
1e6c9c28 977{
c811ab8c 978 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
afefc415 979
1e6c9c28 980 switch (state) {
b843aa21
RB
981 case 0:
982 /*
983 * Enable the peripheral clock for this serial port.
984 * This is called on uart_open() or a resume event.
985 */
986 clk_enable(atmel_port->clk);
987 break;
988 case 3:
989 /*
990 * Disable the peripheral clock for this serial port.
991 * This is called on uart_close() or a suspend event.
992 */
993 clk_disable(atmel_port->clk);
994 break;
995 default:
996 printk(KERN_ERR "atmel_serial: unknown pm %d\n", state);
1e6c9c28
AV
997 }
998}
999
1000/*
1001 * Change the port parameters
1002 */
b843aa21
RB
1003static void atmel_set_termios(struct uart_port *port, struct ktermios *termios,
1004 struct ktermios *old)
1e6c9c28
AV
1005{
1006 unsigned long flags;
1007 unsigned int mode, imr, quot, baud;
1008
03abeac0 1009 /* Get current mode register */
b843aa21
RB
1010 mode = UART_GET_MR(port) & ~(ATMEL_US_USCLKS | ATMEL_US_CHRL
1011 | ATMEL_US_NBSTOP | ATMEL_US_PAR);
03abeac0 1012
b843aa21 1013 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
1e6c9c28
AV
1014 quot = uart_get_divisor(port, baud);
1015
b843aa21 1016 if (quot > 65535) { /* BRGR is 16-bit, so switch to slower clock */
03abeac0
AV
1017 quot /= 8;
1018 mode |= ATMEL_US_USCLKS_MCK_DIV8;
1019 }
1e6c9c28
AV
1020
1021 /* byte size */
1022 switch (termios->c_cflag & CSIZE) {
1023 case CS5:
7192f92c 1024 mode |= ATMEL_US_CHRL_5;
1e6c9c28
AV
1025 break;
1026 case CS6:
7192f92c 1027 mode |= ATMEL_US_CHRL_6;
1e6c9c28
AV
1028 break;
1029 case CS7:
7192f92c 1030 mode |= ATMEL_US_CHRL_7;
1e6c9c28
AV
1031 break;
1032 default:
7192f92c 1033 mode |= ATMEL_US_CHRL_8;
1e6c9c28
AV
1034 break;
1035 }
1036
1037 /* stop bits */
1038 if (termios->c_cflag & CSTOPB)
7192f92c 1039 mode |= ATMEL_US_NBSTOP_2;
1e6c9c28
AV
1040
1041 /* parity */
1042 if (termios->c_cflag & PARENB) {
b843aa21
RB
1043 /* Mark or Space parity */
1044 if (termios->c_cflag & CMSPAR) {
1e6c9c28 1045 if (termios->c_cflag & PARODD)
7192f92c 1046 mode |= ATMEL_US_PAR_MARK;
1e6c9c28 1047 else
7192f92c 1048 mode |= ATMEL_US_PAR_SPACE;
b843aa21 1049 } else if (termios->c_cflag & PARODD)
7192f92c 1050 mode |= ATMEL_US_PAR_ODD;
1e6c9c28 1051 else
7192f92c 1052 mode |= ATMEL_US_PAR_EVEN;
b843aa21 1053 } else
7192f92c 1054 mode |= ATMEL_US_PAR_NONE;
1e6c9c28
AV
1055
1056 spin_lock_irqsave(&port->lock, flags);
1057
7192f92c 1058 port->read_status_mask = ATMEL_US_OVRE;
1e6c9c28 1059 if (termios->c_iflag & INPCK)
7192f92c 1060 port->read_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE);
1e6c9c28 1061 if (termios->c_iflag & (BRKINT | PARMRK))
7192f92c 1062 port->read_status_mask |= ATMEL_US_RXBRK;
1e6c9c28 1063
a6670615
CC
1064 if (atmel_use_dma_rx(port))
1065 /* need to enable error interrupts */
1066 UART_PUT_IER(port, port->read_status_mask);
1067
1e6c9c28
AV
1068 /*
1069 * Characters to ignore
1070 */
1071 port->ignore_status_mask = 0;
1072 if (termios->c_iflag & IGNPAR)
7192f92c 1073 port->ignore_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE);
1e6c9c28 1074 if (termios->c_iflag & IGNBRK) {
7192f92c 1075 port->ignore_status_mask |= ATMEL_US_RXBRK;
1e6c9c28
AV
1076 /*
1077 * If we're ignoring parity and break indicators,
1078 * ignore overruns too (for real raw support).
1079 */
1080 if (termios->c_iflag & IGNPAR)
7192f92c 1081 port->ignore_status_mask |= ATMEL_US_OVRE;
1e6c9c28 1082 }
b843aa21 1083 /* TODO: Ignore all characters if CREAD is set.*/
1e6c9c28
AV
1084
1085 /* update the per-port timeout */
1086 uart_update_timeout(port, termios->c_cflag, baud);
1087
b843aa21
RB
1088 /* save/disable interrupts and drain transmitter */
1089 imr = UART_GET_IMR(port);
1090 UART_PUT_IDR(port, -1);
1091 while (!(UART_GET_CSR(port) & ATMEL_US_TXEMPTY))
829dd811 1092 cpu_relax();
1e6c9c28
AV
1093
1094 /* disable receiver and transmitter */
7192f92c 1095 UART_PUT_CR(port, ATMEL_US_TXDIS | ATMEL_US_RXDIS);
1e6c9c28
AV
1096
1097 /* set the parity, stop bits and data size */
1098 UART_PUT_MR(port, mode);
1099
1100 /* set the baud rate */
1101 UART_PUT_BRGR(port, quot);
7192f92c
HS
1102 UART_PUT_CR(port, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
1103 UART_PUT_CR(port, ATMEL_US_TXEN | ATMEL_US_RXEN);
1e6c9c28
AV
1104
1105 /* restore interrupts */
1106 UART_PUT_IER(port, imr);
1107
1108 /* CTS flow-control and modem-status interrupts */
1109 if (UART_ENABLE_MS(port, termios->c_cflag))
1110 port->ops->enable_ms(port);
1111
1112 spin_unlock_irqrestore(&port->lock, flags);
1113}
1114
1115/*
1116 * Return string describing the specified port
1117 */
7192f92c 1118static const char *atmel_type(struct uart_port *port)
1e6c9c28 1119{
9ab4f88b 1120 return (port->type == PORT_ATMEL) ? "ATMEL_SERIAL" : NULL;
1e6c9c28
AV
1121}
1122
1123/*
1124 * Release the memory region(s) being used by 'port'.
1125 */
7192f92c 1126static void atmel_release_port(struct uart_port *port)
1e6c9c28 1127{
afefc415
AV
1128 struct platform_device *pdev = to_platform_device(port->dev);
1129 int size = pdev->resource[0].end - pdev->resource[0].start + 1;
1130
1131 release_mem_region(port->mapbase, size);
1132
1133 if (port->flags & UPF_IOREMAP) {
1134 iounmap(port->membase);
1135 port->membase = NULL;
1136 }
1e6c9c28
AV
1137}
1138
1139/*
1140 * Request the memory region(s) being used by 'port'.
1141 */
7192f92c 1142static int atmel_request_port(struct uart_port *port)
1e6c9c28 1143{
afefc415
AV
1144 struct platform_device *pdev = to_platform_device(port->dev);
1145 int size = pdev->resource[0].end - pdev->resource[0].start + 1;
1146
7192f92c 1147 if (!request_mem_region(port->mapbase, size, "atmel_serial"))
afefc415
AV
1148 return -EBUSY;
1149
1150 if (port->flags & UPF_IOREMAP) {
1151 port->membase = ioremap(port->mapbase, size);
1152 if (port->membase == NULL) {
1153 release_mem_region(port->mapbase, size);
1154 return -ENOMEM;
1155 }
1156 }
1e6c9c28 1157
afefc415 1158 return 0;
1e6c9c28
AV
1159}
1160
1161/*
1162 * Configure/autoconfigure the port.
1163 */
7192f92c 1164static void atmel_config_port(struct uart_port *port, int flags)
1e6c9c28
AV
1165{
1166 if (flags & UART_CONFIG_TYPE) {
9ab4f88b 1167 port->type = PORT_ATMEL;
7192f92c 1168 atmel_request_port(port);
1e6c9c28
AV
1169 }
1170}
1171
1172/*
1173 * Verify the new serial_struct (for TIOCSSERIAL).
1174 */
7192f92c 1175static int atmel_verify_port(struct uart_port *port, struct serial_struct *ser)
1e6c9c28
AV
1176{
1177 int ret = 0;
9ab4f88b 1178 if (ser->type != PORT_UNKNOWN && ser->type != PORT_ATMEL)
1e6c9c28
AV
1179 ret = -EINVAL;
1180 if (port->irq != ser->irq)
1181 ret = -EINVAL;
1182 if (ser->io_type != SERIAL_IO_MEM)
1183 ret = -EINVAL;
1184 if (port->uartclk / 16 != ser->baud_base)
1185 ret = -EINVAL;
1186 if ((void *)port->mapbase != ser->iomem_base)
1187 ret = -EINVAL;
1188 if (port->iobase != ser->port)
1189 ret = -EINVAL;
1190 if (ser->hub6 != 0)
1191 ret = -EINVAL;
1192 return ret;
1193}
1194
7192f92c
HS
1195static struct uart_ops atmel_pops = {
1196 .tx_empty = atmel_tx_empty,
1197 .set_mctrl = atmel_set_mctrl,
1198 .get_mctrl = atmel_get_mctrl,
1199 .stop_tx = atmel_stop_tx,
1200 .start_tx = atmel_start_tx,
1201 .stop_rx = atmel_stop_rx,
1202 .enable_ms = atmel_enable_ms,
1203 .break_ctl = atmel_break_ctl,
1204 .startup = atmel_startup,
1205 .shutdown = atmel_shutdown,
9afd561a 1206 .flush_buffer = atmel_flush_buffer,
7192f92c
HS
1207 .set_termios = atmel_set_termios,
1208 .type = atmel_type,
1209 .release_port = atmel_release_port,
1210 .request_port = atmel_request_port,
1211 .config_port = atmel_config_port,
1212 .verify_port = atmel_verify_port,
1213 .pm = atmel_serial_pm,
1e6c9c28
AV
1214};
1215
afefc415
AV
1216/*
1217 * Configure the port from the platform device resource info.
1218 */
b843aa21
RB
1219static void __devinit atmel_init_port(struct atmel_uart_port *atmel_port,
1220 struct platform_device *pdev)
1e6c9c28 1221{
7192f92c 1222 struct uart_port *port = &atmel_port->uart;
73e2798b 1223 struct atmel_uart_data *data = pdev->dev.platform_data;
afefc415
AV
1224
1225 port->iotype = UPIO_MEM;
a14d5273 1226 port->flags = UPF_BOOT_AUTOCONF;
7192f92c 1227 port->ops = &atmel_pops;
a14d5273 1228 port->fifosize = 1;
afefc415
AV
1229 port->line = pdev->id;
1230 port->dev = &pdev->dev;
1231
1232 port->mapbase = pdev->resource[0].start;
1233 port->irq = pdev->resource[1].start;
1234
1ecc26bd
RB
1235 tasklet_init(&atmel_port->tasklet, atmel_tasklet_func,
1236 (unsigned long)port);
1237
1238 memset(&atmel_port->rx_ring, 0, sizeof(atmel_port->rx_ring));
1239
75d35213
HS
1240 if (data->regs)
1241 /* Already mapped by setup code */
1242 port->membase = data->regs;
afefc415
AV
1243 else {
1244 port->flags |= UPF_IOREMAP;
1245 port->membase = NULL;
1246 }
1e6c9c28 1247
b843aa21
RB
1248 /* for console, the clock could already be configured */
1249 if (!atmel_port->clk) {
7192f92c
HS
1250 atmel_port->clk = clk_get(&pdev->dev, "usart");
1251 clk_enable(atmel_port->clk);
1252 port->uartclk = clk_get_rate(atmel_port->clk);
afefc415 1253 }
a6670615
CC
1254
1255 atmel_port->use_dma_rx = data->use_dma_rx;
1256 atmel_port->use_dma_tx = data->use_dma_tx;
1257 if (atmel_use_dma_tx(port))
1258 port->fifosize = PDC_BUFFER_SIZE;
1e6c9c28
AV
1259}
1260
afefc415
AV
1261/*
1262 * Register board-specific modem-control line handlers.
1263 */
71f2e2b8 1264void __init atmel_register_uart_fns(struct atmel_port_fns *fns)
1e6c9c28
AV
1265{
1266 if (fns->enable_ms)
7192f92c 1267 atmel_pops.enable_ms = fns->enable_ms;
1e6c9c28 1268 if (fns->get_mctrl)
7192f92c 1269 atmel_pops.get_mctrl = fns->get_mctrl;
1e6c9c28 1270 if (fns->set_mctrl)
7192f92c 1271 atmel_pops.set_mctrl = fns->set_mctrl;
71f2e2b8
HS
1272 atmel_open_hook = fns->open;
1273 atmel_close_hook = fns->close;
7192f92c
HS
1274 atmel_pops.pm = fns->pm;
1275 atmel_pops.set_wake = fns->set_wake;
1e6c9c28
AV
1276}
1277
749c4e60 1278#ifdef CONFIG_SERIAL_ATMEL_CONSOLE
7192f92c 1279static void atmel_console_putchar(struct uart_port *port, int ch)
d358788f 1280{
7192f92c 1281 while (!(UART_GET_CSR(port) & ATMEL_US_TXRDY))
829dd811 1282 cpu_relax();
d358788f
RK
1283 UART_PUT_CHAR(port, ch);
1284}
1e6c9c28
AV
1285
1286/*
1287 * Interrupts are disabled on entering
1288 */
7192f92c 1289static void atmel_console_write(struct console *co, const char *s, u_int count)
1e6c9c28 1290{
7192f92c 1291 struct uart_port *port = &atmel_ports[co->index].uart;
d358788f 1292 unsigned int status, imr;
39d4c922 1293 unsigned int pdc_tx;
1e6c9c28
AV
1294
1295 /*
b843aa21 1296 * First, save IMR and then disable interrupts
1e6c9c28 1297 */
b843aa21 1298 imr = UART_GET_IMR(port);
7192f92c 1299 UART_PUT_IDR(port, ATMEL_US_RXRDY | ATMEL_US_TXRDY);
1e6c9c28 1300
39d4c922
MP
1301 /* Store PDC transmit status and disable it */
1302 pdc_tx = UART_GET_PTSR(port) & ATMEL_PDC_TXTEN;
1303 UART_PUT_PTCR(port, ATMEL_PDC_TXTDIS);
1304
7192f92c 1305 uart_console_write(port, s, count, atmel_console_putchar);
1e6c9c28
AV
1306
1307 /*
b843aa21
RB
1308 * Finally, wait for transmitter to become empty
1309 * and restore IMR
1e6c9c28
AV
1310 */
1311 do {
1312 status = UART_GET_CSR(port);
7192f92c 1313 } while (!(status & ATMEL_US_TXRDY));
39d4c922
MP
1314
1315 /* Restore PDC transmit status */
1316 if (pdc_tx)
1317 UART_PUT_PTCR(port, ATMEL_PDC_TXTEN);
1318
b843aa21
RB
1319 /* set interrupts back the way they were */
1320 UART_PUT_IER(port, imr);
1e6c9c28
AV
1321}
1322
1323/*
b843aa21
RB
1324 * If the port was already initialised (eg, by a boot loader),
1325 * try to determine the current setup.
1e6c9c28 1326 */
b843aa21
RB
1327static void __init atmel_console_get_options(struct uart_port *port, int *baud,
1328 int *parity, int *bits)
1e6c9c28
AV
1329{
1330 unsigned int mr, quot;
1331
1c0fd82f
HS
1332 /*
1333 * If the baud rate generator isn't running, the port wasn't
1334 * initialized by the boot loader.
1335 */
9c81c5c9 1336 quot = UART_GET_BRGR(port) & ATMEL_US_CD;
1c0fd82f
HS
1337 if (!quot)
1338 return;
1e6c9c28 1339
7192f92c
HS
1340 mr = UART_GET_MR(port) & ATMEL_US_CHRL;
1341 if (mr == ATMEL_US_CHRL_8)
1e6c9c28
AV
1342 *bits = 8;
1343 else
1344 *bits = 7;
1345
7192f92c
HS
1346 mr = UART_GET_MR(port) & ATMEL_US_PAR;
1347 if (mr == ATMEL_US_PAR_EVEN)
1e6c9c28 1348 *parity = 'e';
7192f92c 1349 else if (mr == ATMEL_US_PAR_ODD)
1e6c9c28
AV
1350 *parity = 'o';
1351
4d5e392c
HS
1352 /*
1353 * The serial core only rounds down when matching this to a
1354 * supported baud rate. Make sure we don't end up slightly
1355 * lower than one of those, as it would make us fall through
1356 * to a much lower baud rate than we really want.
1357 */
4d5e392c 1358 *baud = port->uartclk / (16 * (quot - 1));
1e6c9c28
AV
1359}
1360
7192f92c 1361static int __init atmel_console_setup(struct console *co, char *options)
1e6c9c28 1362{
7192f92c 1363 struct uart_port *port = &atmel_ports[co->index].uart;
1e6c9c28
AV
1364 int baud = 115200;
1365 int bits = 8;
1366 int parity = 'n';
1367 int flow = 'n';
1368
b843aa21
RB
1369 if (port->membase == NULL) {
1370 /* Port not initialized yet - delay setup */
afefc415 1371 return -ENODEV;
b843aa21 1372 }
1e6c9c28 1373
b843aa21 1374 UART_PUT_IDR(port, -1);
7192f92c
HS
1375 UART_PUT_CR(port, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
1376 UART_PUT_CR(port, ATMEL_US_TXEN | ATMEL_US_RXEN);
1e6c9c28
AV
1377
1378 if (options)
1379 uart_parse_options(options, &baud, &parity, &bits, &flow);
1380 else
7192f92c 1381 atmel_console_get_options(port, &baud, &parity, &bits);
1e6c9c28
AV
1382
1383 return uart_set_options(port, co, baud, parity, bits, flow);
1384}
1385
7192f92c 1386static struct uart_driver atmel_uart;
1e6c9c28 1387
7192f92c
HS
1388static struct console atmel_console = {
1389 .name = ATMEL_DEVICENAME,
1390 .write = atmel_console_write,
1e6c9c28 1391 .device = uart_console_device,
7192f92c 1392 .setup = atmel_console_setup,
1e6c9c28
AV
1393 .flags = CON_PRINTBUFFER,
1394 .index = -1,
7192f92c 1395 .data = &atmel_uart,
1e6c9c28
AV
1396};
1397
7192f92c 1398#define ATMEL_CONSOLE_DEVICE &atmel_console
1e6c9c28 1399
afefc415
AV
1400/*
1401 * Early console initialization (before VM subsystem initialized).
1402 */
7192f92c 1403static int __init atmel_console_init(void)
1e6c9c28 1404{
73e2798b 1405 if (atmel_default_console_device) {
b843aa21
RB
1406 add_preferred_console(ATMEL_DEVICENAME,
1407 atmel_default_console_device->id, NULL);
1408 atmel_init_port(&atmel_ports[atmel_default_console_device->id],
1409 atmel_default_console_device);
7192f92c 1410 register_console(&atmel_console);
afefc415 1411 }
1e6c9c28 1412
1e6c9c28
AV
1413 return 0;
1414}
b843aa21 1415
7192f92c 1416console_initcall(atmel_console_init);
1e6c9c28 1417
afefc415
AV
1418/*
1419 * Late console initialization.
1420 */
7192f92c 1421static int __init atmel_late_console_init(void)
afefc415 1422{
b843aa21
RB
1423 if (atmel_default_console_device
1424 && !(atmel_console.flags & CON_ENABLED))
7192f92c 1425 register_console(&atmel_console);
afefc415
AV
1426
1427 return 0;
1428}
b843aa21 1429
7192f92c 1430core_initcall(atmel_late_console_init);
afefc415 1431
dfa7f343
HS
1432static inline bool atmel_is_console_port(struct uart_port *port)
1433{
1434 return port->cons && port->cons->index == port->line;
1435}
1436
1e6c9c28 1437#else
7192f92c 1438#define ATMEL_CONSOLE_DEVICE NULL
dfa7f343
HS
1439
1440static inline bool atmel_is_console_port(struct uart_port *port)
1441{
1442 return false;
1443}
1e6c9c28
AV
1444#endif
1445
7192f92c 1446static struct uart_driver atmel_uart = {
b843aa21
RB
1447 .owner = THIS_MODULE,
1448 .driver_name = "atmel_serial",
1449 .dev_name = ATMEL_DEVICENAME,
1450 .major = SERIAL_ATMEL_MAJOR,
1451 .minor = MINOR_START,
1452 .nr = ATMEL_MAX_UART,
1453 .cons = ATMEL_CONSOLE_DEVICE,
1e6c9c28
AV
1454};
1455
afefc415 1456#ifdef CONFIG_PM
f826caa4
HS
1457static bool atmel_serial_clk_will_stop(void)
1458{
1459#ifdef CONFIG_ARCH_AT91
1460 return at91_suspend_entering_slow_clock();
1461#else
1462 return false;
1463#endif
1464}
1465
b843aa21
RB
1466static int atmel_serial_suspend(struct platform_device *pdev,
1467 pm_message_t state)
1e6c9c28 1468{
afefc415 1469 struct uart_port *port = platform_get_drvdata(pdev);
c811ab8c 1470 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
afefc415 1471
e1c609ef
HS
1472 if (atmel_is_console_port(port) && console_suspend_enabled) {
1473 /* Drain the TX shifter */
1474 while (!(UART_GET_CSR(port) & ATMEL_US_TXEMPTY))
1475 cpu_relax();
1476 }
1477
b843aa21 1478 if (device_may_wakeup(&pdev->dev)
f826caa4 1479 && !atmel_serial_clk_will_stop())
afefc415
AV
1480 enable_irq_wake(port->irq);
1481 else {
7192f92c
HS
1482 uart_suspend_port(&atmel_uart, port);
1483 atmel_port->suspended = 1;
afefc415 1484 }
1e6c9c28 1485
afefc415
AV
1486 return 0;
1487}
1e6c9c28 1488
7192f92c 1489static int atmel_serial_resume(struct platform_device *pdev)
afefc415
AV
1490{
1491 struct uart_port *port = platform_get_drvdata(pdev);
c811ab8c 1492 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1e6c9c28 1493
7192f92c
HS
1494 if (atmel_port->suspended) {
1495 uart_resume_port(&atmel_uart, port);
1496 atmel_port->suspended = 0;
b843aa21 1497 } else
9b938166 1498 disable_irq_wake(port->irq);
1e6c9c28
AV
1499
1500 return 0;
1501}
afefc415 1502#else
7192f92c
HS
1503#define atmel_serial_suspend NULL
1504#define atmel_serial_resume NULL
afefc415 1505#endif
1e6c9c28 1506
7192f92c 1507static int __devinit atmel_serial_probe(struct platform_device *pdev)
1e6c9c28 1508{
7192f92c 1509 struct atmel_uart_port *port;
1ecc26bd 1510 void *data;
afefc415 1511 int ret;
1e6c9c28 1512
1ecc26bd
RB
1513 BUILD_BUG_ON(!is_power_of_2(ATMEL_SERIAL_RINGSIZE));
1514
7192f92c
HS
1515 port = &atmel_ports[pdev->id];
1516 atmel_init_port(port, pdev);
1e6c9c28 1517
a6670615
CC
1518 if (!atmel_use_dma_rx(&port->uart)) {
1519 ret = -ENOMEM;
6433471d
HS
1520 data = kmalloc(sizeof(struct atmel_uart_char)
1521 * ATMEL_SERIAL_RINGSIZE, GFP_KERNEL);
a6670615
CC
1522 if (!data)
1523 goto err_alloc_ring;
1524 port->rx_ring.buf = data;
1525 }
1ecc26bd 1526
7192f92c 1527 ret = uart_add_one_port(&atmel_uart, &port->uart);
dfa7f343
HS
1528 if (ret)
1529 goto err_add_port;
1530
1531 device_init_wakeup(&pdev->dev, 1);
1532 platform_set_drvdata(pdev, port);
1533
1534 return 0;
1535
1536err_add_port:
1ecc26bd
RB
1537 kfree(port->rx_ring.buf);
1538 port->rx_ring.buf = NULL;
1539err_alloc_ring:
dfa7f343
HS
1540 if (!atmel_is_console_port(&port->uart)) {
1541 clk_disable(port->clk);
1542 clk_put(port->clk);
1543 port->clk = NULL;
afefc415
AV
1544 }
1545
1546 return ret;
1547}
1548
7192f92c 1549static int __devexit atmel_serial_remove(struct platform_device *pdev)
afefc415
AV
1550{
1551 struct uart_port *port = platform_get_drvdata(pdev);
c811ab8c 1552 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
afefc415
AV
1553 int ret = 0;
1554
afefc415
AV
1555 device_init_wakeup(&pdev->dev, 0);
1556 platform_set_drvdata(pdev, NULL);
1557
dfa7f343
HS
1558 ret = uart_remove_one_port(&atmel_uart, port);
1559
1ecc26bd
RB
1560 tasklet_kill(&atmel_port->tasklet);
1561 kfree(atmel_port->rx_ring.buf);
1562
dfa7f343
HS
1563 /* "port" is allocated statically, so we shouldn't free it */
1564
1565 clk_disable(atmel_port->clk);
1566 clk_put(atmel_port->clk);
afefc415
AV
1567
1568 return ret;
1569}
1570
7192f92c
HS
1571static struct platform_driver atmel_serial_driver = {
1572 .probe = atmel_serial_probe,
1573 .remove = __devexit_p(atmel_serial_remove),
1574 .suspend = atmel_serial_suspend,
1575 .resume = atmel_serial_resume,
afefc415 1576 .driver = {
1e8ea802 1577 .name = "atmel_usart",
afefc415
AV
1578 .owner = THIS_MODULE,
1579 },
1580};
1581
7192f92c 1582static int __init atmel_serial_init(void)
afefc415
AV
1583{
1584 int ret;
1585
7192f92c 1586 ret = uart_register_driver(&atmel_uart);
afefc415
AV
1587 if (ret)
1588 return ret;
1589
7192f92c 1590 ret = platform_driver_register(&atmel_serial_driver);
afefc415 1591 if (ret)
7192f92c 1592 uart_unregister_driver(&atmel_uart);
afefc415
AV
1593
1594 return ret;
1595}
1596
7192f92c 1597static void __exit atmel_serial_exit(void)
afefc415 1598{
7192f92c
HS
1599 platform_driver_unregister(&atmel_serial_driver);
1600 uart_unregister_driver(&atmel_uart);
1e6c9c28
AV
1601}
1602
7192f92c
HS
1603module_init(atmel_serial_init);
1604module_exit(atmel_serial_exit);
1e6c9c28
AV
1605
1606MODULE_AUTHOR("Rick Bronson");
7192f92c 1607MODULE_DESCRIPTION("Atmel AT91 / AT32 serial port driver");
1e6c9c28 1608MODULE_LICENSE("GPL");
e169c139 1609MODULE_ALIAS("platform:atmel_usart");