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synclink_gt: fix transmit race and timeout
[linux-2.6-block.git] / drivers / serial / 8250_pci.c
CommitLineData
1da177e4
LT		 1/*
2 * linux/drivers/char/8250_pci.c
3 *
4 * Probe module for 8250/16550-type PCI serial ports.
5 *
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
7 *
8 * Copyright (C) 2001 Russell King, All Rights Reserved.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License.
1da177e4
LT		 13 */
14#include <linux/module.h>
15#include <linux/init.h>
16#include <linux/pci.h>
1da177e4
LT		 17#include <linux/string.h>
18#include <linux/kernel.h>
19#include <linux/slab.h>
20#include <linux/delay.h>
21#include <linux/tty.h>
22#include <linux/serial_core.h>
23#include <linux/8250_pci.h>
24#include <linux/bitops.h>
25
26#include <asm/byteorder.h>
27#include <asm/io.h>
28
29#include "8250.h"
30
31#undef SERIAL_DEBUG_PCI
32
1da177e4
LT		 33/*
34 * init function returns:
35 * > 0 - number of ports
36 * = 0 - use board->num_ports
37 * < 0 - error
38 */
39struct pci_serial_quirk {
40 u32 vendor;
41 u32 device;
42 u32 subvendor;
43 u32 subdevice;
44 int (*init)(struct pci_dev *dev);
975a1a7d
RK		 45 int (*setup)(struct serial_private *,
46 const struct pciserial_board *,
05caac58 47 struct uart_port *, int);
1da177e4
LT		 48 void (*exit)(struct pci_dev *dev);
49};
50
51#define PCI_NUM_BAR_RESOURCES 6
52
53struct serial_private {
70db3d91 54 struct pci_dev *dev;
1da177e4
LT		 55 unsigned int nr;
56 void __iomem *remapped_bar[PCI_NUM_BAR_RESOURCES];
57 struct pci_serial_quirk *quirk;
58 int line[0];
59};
60
61static void moan_device(const char *str, struct pci_dev *dev)
62{
63 printk(KERN_WARNING "%s: %s\n"
64 KERN_WARNING "Please send the output of lspci -vv, this\n"
65 KERN_WARNING "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
66 KERN_WARNING "manufacturer and name of serial board or\n"
67 KERN_WARNING "modem board to rmk+serial@arm.linux.org.uk.\n",
68 pci_name(dev), str, dev->vendor, dev->device,
69 dev->subsystem_vendor, dev->subsystem_device);
70}
71
72static int
70db3d91 73setup_port(struct serial_private *priv, struct uart_port *port,
1da177e4
LT		 74 int bar, int offset, int regshift)
75{
70db3d91 76 struct pci_dev *dev = priv->dev;
1da177e4
LT		 77 unsigned long base, len;
78
79 if (bar >= PCI_NUM_BAR_RESOURCES)
80 return -EINVAL;
81
72ce9a83
RK		 82 base = pci_resource_start(dev, bar);
83
1da177e4 84 if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
1da177e4
LT		 85 len = pci_resource_len(dev, bar);
86
87 if (!priv->remapped_bar[bar])
6f441fe9 88 priv->remapped_bar[bar] = ioremap_nocache(base, len);
1da177e4
LT		 89 if (!priv->remapped_bar[bar])
90 return -ENOMEM;
91
92 port->iotype = UPIO_MEM;
72ce9a83 93 port->iobase = 0;
1da177e4
LT		 94 port->mapbase = base + offset;
95 port->membase = priv->remapped_bar[bar] + offset;
96 port->regshift = regshift;
97 } else {
1da177e4 98 port->iotype = UPIO_PORT;
72ce9a83
RK		 99 port->iobase = base + offset;
100 port->mapbase = 0;
101 port->membase = NULL;
102 port->regshift = 0;
1da177e4
LT		 103 }
104 return 0;
105}
106
02c9b5cf
KJ		 107/*
108 * ADDI-DATA GmbH communication cards <info@addi-data.com>
109 */
110static int addidata_apci7800_setup(struct serial_private *priv,
975a1a7d 111 const struct pciserial_board *board,
02c9b5cf
KJ		 112 struct uart_port *port, int idx)
113{
114 unsigned int bar = 0, offset = board->first_offset;
115 bar = FL_GET_BASE(board->flags);
116
117 if (idx < 2) {
118 offset += idx * board->uart_offset;
119 } else if ((idx >= 2) && (idx < 4)) {
120 bar += 1;
121 offset += ((idx - 2) * board->uart_offset);
122 } else if ((idx >= 4) && (idx < 6)) {
123 bar += 2;
124 offset += ((idx - 4) * board->uart_offset);
125 } else if (idx >= 6) {
126 bar += 3;
127 offset += ((idx - 6) * board->uart_offset);
128 }
129
130 return setup_port(priv, port, bar, offset, board->reg_shift);
131}
132
1da177e4
LT		 133/*
134 * AFAVLAB uses a different mixture of BARs and offsets
135 * Not that ugly ;) -- HW
136 */
137static int
975a1a7d 138afavlab_setup(struct serial_private *priv, const struct pciserial_board *board,
1da177e4
LT		 139 struct uart_port *port, int idx)
140{
141 unsigned int bar, offset = board->first_offset;
5756ee99 142
1da177e4
LT		 143 bar = FL_GET_BASE(board->flags);
144 if (idx < 4)
145 bar += idx;
146 else {
147 bar = 4;
148 offset += (idx - 4) * board->uart_offset;
149 }
150
70db3d91 151 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 152}
153
154/*
155 * HP's Remote Management Console. The Diva chip came in several
156 * different versions. N-class, L2000 and A500 have two Diva chips, each
157 * with 3 UARTs (the third UART on the second chip is unused). Superdome
158 * and Keystone have one Diva chip with 3 UARTs. Some later machines have
159 * one Diva chip, but it has been expanded to 5 UARTs.
160 */
61a116ef 161static int pci_hp_diva_init(struct pci_dev *dev)
1da177e4
LT		 162{
163 int rc = 0;
164
165 switch (dev->subsystem_device) {
166 case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
167 case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
168 case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
169 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
170 rc = 3;
171 break;
172 case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
173 rc = 2;
174 break;
175 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
176 rc = 4;
177 break;
178 case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
551f8f0e 179 case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
1da177e4
LT		 180 rc = 1;
181 break;
182 }
183
184 return rc;
185}
186
187/*
188 * HP's Diva chip puts the 4th/5th serial port further out, and
189 * some serial ports are supposed to be hidden on certain models.
190 */
191static int
975a1a7d
RK		 192pci_hp_diva_setup(struct serial_private *priv,
193 const struct pciserial_board *board,
194 struct uart_port *port, int idx)
1da177e4
LT		 195{
196 unsigned int offset = board->first_offset;
197 unsigned int bar = FL_GET_BASE(board->flags);
198
70db3d91 199 switch (priv->dev->subsystem_device) {
1da177e4
LT		 200 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
201 if (idx == 3)
202 idx++;
203 break;
204 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
205 if (idx > 0)
206 idx++;
207 if (idx > 2)
208 idx++;
209 break;
210 }
211 if (idx > 2)
212 offset = 0x18;
213
214 offset += idx * board->uart_offset;
215
70db3d91 216 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 217}
218
219/*
220 * Added for EKF Intel i960 serial boards
221 */
61a116ef 222static int pci_inteli960ni_init(struct pci_dev *dev)
1da177e4
LT		 223{
224 unsigned long oldval;
225
226 if (!(dev->subsystem_device & 0x1000))
227 return -ENODEV;
228
229 /* is firmware started? */
5756ee99
AC		 230 pci_read_config_dword(dev, 0x44, (void *)&oldval);
231 if (oldval == 0x00001000L) { /* RESET value */
1da177e4
LT		 232 printk(KERN_DEBUG "Local i960 firmware missing");
233 return -ENODEV;
234 }
235 return 0;
236}
237
238/*
239 * Some PCI serial cards using the PLX 9050 PCI interface chip require
240 * that the card interrupt be explicitly enabled or disabled. This
241 * seems to be mainly needed on card using the PLX which also use I/O
242 * mapped memory.
243 */
61a116ef 244static int pci_plx9050_init(struct pci_dev *dev)
1da177e4
LT		 245{
246 u8 irq_config;
247 void __iomem *p;
248
249 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
250 moan_device("no memory in bar 0", dev);
251 return 0;
252 }
253
254 irq_config = 0x41;
add7b58e 255 if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
5756ee99 256 dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS)
1da177e4 257 irq_config = 0x43;
5756ee99 258
1da177e4 259 if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
5756ee99 260 (dev->device == PCI_DEVICE_ID_PLX_ROMULUS))
1da177e4
LT		 261 /*
262 * As the megawolf cards have the int pins active
263 * high, and have 2 UART chips, both ints must be
264 * enabled on the 9050. Also, the UARTS are set in
265 * 16450 mode by default, so we have to enable the
266 * 16C950 'enhanced' mode so that we can use the
267 * deep FIFOs
268 */
269 irq_config = 0x5b;
1da177e4
LT		 270 /*
271 * enable/disable interrupts
272 */
6f441fe9 273 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
1da177e4
LT		 274 if (p == NULL)
275 return -ENOMEM;
276 writel(irq_config, p + 0x4c);
277
278 /*
279 * Read the register back to ensure that it took effect.
280 */
281 readl(p + 0x4c);
282 iounmap(p);
283
284 return 0;
285}
286
287static void __devexit pci_plx9050_exit(struct pci_dev *dev)
288{
289 u8 __iomem *p;
290
291 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
292 return;
293
294 /*
295 * disable interrupts
296 */
6f441fe9 297 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
1da177e4
LT		 298 if (p != NULL) {
299 writel(0, p + 0x4c);
300
301 /*
302 * Read the register back to ensure that it took effect.
303 */
304 readl(p + 0x4c);
305 iounmap(p);
306 }
307}
308
04bf7e74
WP		 309#define NI8420_INT_ENABLE_REG 0x38
310#define NI8420_INT_ENABLE_BIT 0x2000
311
312static void __devexit pci_ni8420_exit(struct pci_dev *dev)
313{
314 void __iomem *p;
315 unsigned long base, len;
316 unsigned int bar = 0;
317
318 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
319 moan_device("no memory in bar", dev);
320 return;
321 }
322
323 base = pci_resource_start(dev, bar);
324 len = pci_resource_len(dev, bar);
325 p = ioremap_nocache(base, len);
326 if (p == NULL)
327 return;
328
329 /* Disable the CPU Interrupt */
330 writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT),
331 p + NI8420_INT_ENABLE_REG);
332 iounmap(p);
333}
334
335
46a0fac9
SB		 336/* MITE registers */
337#define MITE_IOWBSR1 0xc4
338#define MITE_IOWCR1 0xf4
339#define MITE_LCIMR1 0x08
340#define MITE_LCIMR2 0x10
341
342#define MITE_LCIMR2_CLR_CPU_IE (1 << 30)
343
344static void __devexit pci_ni8430_exit(struct pci_dev *dev)
345{
346 void __iomem *p;
347 unsigned long base, len;
348 unsigned int bar = 0;
349
350 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
351 moan_device("no memory in bar", dev);
352 return;
353 }
354
355 base = pci_resource_start(dev, bar);
356 len = pci_resource_len(dev, bar);
357 p = ioremap_nocache(base, len);
358 if (p == NULL)
359 return;
360
361 /* Disable the CPU Interrupt */
362 writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2);
363 iounmap(p);
364}
365
1da177e4
LT		 366/* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
367static int
975a1a7d 368sbs_setup(struct serial_private *priv, const struct pciserial_board *board,
1da177e4
LT		 369 struct uart_port *port, int idx)
370{
371 unsigned int bar, offset = board->first_offset;
372
373 bar = 0;
374
375 if (idx < 4) {
376 /* first four channels map to 0, 0x100, 0x200, 0x300 */
377 offset += idx * board->uart_offset;
378 } else if (idx < 8) {
379 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
380 offset += idx * board->uart_offset + 0xC00;
381 } else /* we have only 8 ports on PMC-OCTALPRO */
382 return 1;
383
70db3d91 384 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 385}
386
387/*
388* This does initialization for PMC OCTALPRO cards:
389* maps the device memory, resets the UARTs (needed, bc
390* if the module is removed and inserted again, the card
391* is in the sleep mode) and enables global interrupt.
392*/
393
394/* global control register offset for SBS PMC-OctalPro */
395#define OCT_REG_CR_OFF 0x500
396
61a116ef 397static int sbs_init(struct pci_dev *dev)
1da177e4
LT		 398{
399 u8 __iomem *p;
400
6f441fe9
AC		 401 p = ioremap_nocache(pci_resource_start(dev, 0),
402 pci_resource_len(dev, 0));
1da177e4
LT		 403
404 if (p == NULL)
405 return -ENOMEM;
406 /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
5756ee99 407 writeb(0x10, p + OCT_REG_CR_OFF);
1da177e4 408 udelay(50);
5756ee99 409 writeb(0x0, p + OCT_REG_CR_OFF);
1da177e4
LT		 410
411 /* Set bit-2 (INTENABLE) of Control Register */
412 writeb(0x4, p + OCT_REG_CR_OFF);
413 iounmap(p);
414
415 return 0;
416}
417
418/*
419 * Disables the global interrupt of PMC-OctalPro
420 */
421
422static void __devexit sbs_exit(struct pci_dev *dev)
423{
424 u8 __iomem *p;
425
6f441fe9
AC		 426 p = ioremap_nocache(pci_resource_start(dev, 0),
427 pci_resource_len(dev, 0));
5756ee99
AC		 428 /* FIXME: What if resource_len < OCT_REG_CR_OFF */
429 if (p != NULL)
1da177e4 430 writeb(0, p + OCT_REG_CR_OFF);
1da177e4
LT		 431 iounmap(p);
432}
433
434/*
435 * SIIG serial cards have an PCI interface chip which also controls
436 * the UART clocking frequency. Each UART can be clocked independently
437 * (except cards equiped with 4 UARTs) and initial clocking settings
438 * are stored in the EEPROM chip. It can cause problems because this
439 * version of serial driver doesn't support differently clocked UART's
440 * on single PCI card. To prevent this, initialization functions set
441 * high frequency clocking for all UART's on given card. It is safe (I
442 * hope) because it doesn't touch EEPROM settings to prevent conflicts
443 * with other OSes (like M$ DOS).
444 *
445 * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
5756ee99 446 *
1da177e4
LT		 447 * There is two family of SIIG serial cards with different PCI
448 * interface chip and different configuration methods:
449 * - 10x cards have control registers in IO and/or memory space;
450 * - 20x cards have control registers in standard PCI configuration space.
451 *
67d74b87
RK		 452 * Note: all 10x cards have PCI device ids 0x10..
453 * all 20x cards have PCI device ids 0x20..
454 *
fbc0dc0d
AP		 455 * There are also Quartet Serial cards which use Oxford Semiconductor
456 * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
457 *
1da177e4
LT		 458 * Note: some SIIG cards are probed by the parport_serial object.
459 */
460
461#define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
462#define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
463
464static int pci_siig10x_init(struct pci_dev *dev)
465{
466 u16 data;
467 void __iomem *p;
468
469 switch (dev->device & 0xfff8) {
470 case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
471 data = 0xffdf;
472 break;
473 case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
474 data = 0xf7ff;
475 break;
476 default: /* 1S1P, 4S */
477 data = 0xfffb;
478 break;
479 }
480
6f441fe9 481 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
1da177e4
LT		 482 if (p == NULL)
483 return -ENOMEM;
484
485 writew(readw(p + 0x28) & data, p + 0x28);
486 readw(p + 0x28);
487 iounmap(p);
488 return 0;
489}
490
491#define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
492#define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
493
494static int pci_siig20x_init(struct pci_dev *dev)
495{
496 u8 data;
497
498 /* Change clock frequency for the first UART. */
499 pci_read_config_byte(dev, 0x6f, &data);
500 pci_write_config_byte(dev, 0x6f, data & 0xef);
501
502 /* If this card has 2 UART, we have to do the same with second UART. */
503 if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
504 ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
505 pci_read_config_byte(dev, 0x73, &data);
506 pci_write_config_byte(dev, 0x73, data & 0xef);
507 }
508 return 0;
509}
510
67d74b87
RK		 511static int pci_siig_init(struct pci_dev *dev)
512{
513 unsigned int type = dev->device & 0xff00;
514
515 if (type == 0x1000)
516 return pci_siig10x_init(dev);
517 else if (type == 0x2000)
518 return pci_siig20x_init(dev);
519
520 moan_device("Unknown SIIG card", dev);
521 return -ENODEV;
522}
523
3ec9c594 524static int pci_siig_setup(struct serial_private *priv,
975a1a7d 525 const struct pciserial_board *board,
3ec9c594
AP		 526 struct uart_port *port, int idx)
527{
528 unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
529
530 if (idx > 3) {
531 bar = 4;
532 offset = (idx - 4) * 8;
533 }
534
535 return setup_port(priv, port, bar, offset, 0);
536}
537
1da177e4
LT		 538/*
539 * Timedia has an explosion of boards, and to avoid the PCI table from
540 * growing *huge*, we use this function to collapse some 70 entries
541 * in the PCI table into one, for sanity's and compactness's sake.
542 */
e9422e09 543static const unsigned short timedia_single_port[] = {
1da177e4
LT		 544 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
545};
546
e9422e09 547static const unsigned short timedia_dual_port[] = {
1da177e4 548 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
5756ee99
AC		 549 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
550 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
1da177e4
LT		 551 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
552 0xD079, 0
553};
554
e9422e09 555static const unsigned short timedia_quad_port[] = {
5756ee99
AC		 556 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
557 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
1da177e4
LT		 558 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
559 0xB157, 0
560};
561
e9422e09 562static const unsigned short timedia_eight_port[] = {
5756ee99 563 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
1da177e4
LT		 564 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
565};
566
cb3592be 567static const struct timedia_struct {
1da177e4 568 int num;
e9422e09 569 const unsigned short *ids;
1da177e4
LT		 570} timedia_data[] = {
571 { 1, timedia_single_port },
572 { 2, timedia_dual_port },
573 { 4, timedia_quad_port },
e9422e09 574 { 8, timedia_eight_port }
1da177e4
LT		 575};
576
61a116ef 577static int pci_timedia_init(struct pci_dev *dev)
1da177e4 578{
e9422e09 579 const unsigned short *ids;
1da177e4
LT		 580 int i, j;
581
e9422e09 582 for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
1da177e4
LT		 583 ids = timedia_data[i].ids;
584 for (j = 0; ids[j]; j++)
585 if (dev->subsystem_device == ids[j])
586 return timedia_data[i].num;
587 }
588 return 0;
589}
590
591/*
592 * Timedia/SUNIX uses a mixture of BARs and offsets
593 * Ugh, this is ugly as all hell --- TYT
594 */
595static int
975a1a7d
RK		 596pci_timedia_setup(struct serial_private *priv,
597 const struct pciserial_board *board,
1da177e4
LT		 598 struct uart_port *port, int idx)
599{
600 unsigned int bar = 0, offset = board->first_offset;
601
602 switch (idx) {
603 case 0:
604 bar = 0;
605 break;
606 case 1:
607 offset = board->uart_offset;
608 bar = 0;
609 break;
610 case 2:
611 bar = 1;
612 break;
613 case 3:
614 offset = board->uart_offset;
c2cd6d3c 615 /* FALLTHROUGH */
1da177e4
LT		 616 case 4: /* BAR 2 */
617 case 5: /* BAR 3 */
618 case 6: /* BAR 4 */
619 case 7: /* BAR 5 */
620 bar = idx - 2;
621 }
622
70db3d91 623 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 624}
625
626/*
627 * Some Titan cards are also a little weird
628 */
629static int
70db3d91 630titan_400l_800l_setup(struct serial_private *priv,
975a1a7d 631 const struct pciserial_board *board,
1da177e4
LT		 632 struct uart_port *port, int idx)
633{
634 unsigned int bar, offset = board->first_offset;
635
636 switch (idx) {
637 case 0:
638 bar = 1;
639 break;
640 case 1:
641 bar = 2;
642 break;
643 default:
644 bar = 4;
645 offset = (idx - 2) * board->uart_offset;
646 }
647
70db3d91 648 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 649}
650
61a116ef 651static int pci_xircom_init(struct pci_dev *dev)
1da177e4
LT		 652{
653 msleep(100);
654 return 0;
655}
656
04bf7e74
WP		 657static int pci_ni8420_init(struct pci_dev *dev)
658{
659 void __iomem *p;
660 unsigned long base, len;
661 unsigned int bar = 0;
662
663 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
664 moan_device("no memory in bar", dev);
665 return 0;
666 }
667
668 base = pci_resource_start(dev, bar);
669 len = pci_resource_len(dev, bar);
670 p = ioremap_nocache(base, len);
671 if (p == NULL)
672 return -ENOMEM;
673
674 /* Enable CPU Interrupt */
675 writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT,
676 p + NI8420_INT_ENABLE_REG);
677
678 iounmap(p);
679 return 0;
680}
681
46a0fac9
SB		 682#define MITE_IOWBSR1_WSIZE 0xa
683#define MITE_IOWBSR1_WIN_OFFSET 0x800
684#define MITE_IOWBSR1_WENAB (1 << 7)
685#define MITE_LCIMR1_IO_IE_0 (1 << 24)
686#define MITE_LCIMR2_SET_CPU_IE (1 << 31)
687#define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe
688
689static int pci_ni8430_init(struct pci_dev *dev)
690{
691 void __iomem *p;
692 unsigned long base, len;
693 u32 device_window;
694 unsigned int bar = 0;
695
696 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
697 moan_device("no memory in bar", dev);
698 return 0;
699 }
700
701 base = pci_resource_start(dev, bar);
702 len = pci_resource_len(dev, bar);
703 p = ioremap_nocache(base, len);
704 if (p == NULL)
705 return -ENOMEM;
706
707 /* Set device window address and size in BAR0 */
708 device_window = ((base + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00)
709 | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE;
710 writel(device_window, p + MITE_IOWBSR1);
711
712 /* Set window access to go to RAMSEL IO address space */
713 writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK),
714 p + MITE_IOWCR1);
715
716 /* Enable IO Bus Interrupt 0 */
717 writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1);
718
719 /* Enable CPU Interrupt */
720 writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2);
721
722 iounmap(p);
723 return 0;
724}
725
726/* UART Port Control Register */
727#define NI8430_PORTCON 0x0f
728#define NI8430_PORTCON_TXVR_ENABLE (1 << 3)
729
730static int
bf538fe4
AC		 731pci_ni8430_setup(struct serial_private *priv,
732 const struct pciserial_board *board,
46a0fac9
SB		 733 struct uart_port *port, int idx)
734{
735 void __iomem *p;
736 unsigned long base, len;
737 unsigned int bar, offset = board->first_offset;
738
739 if (idx >= board->num_ports)
740 return 1;
741
742 bar = FL_GET_BASE(board->flags);
743 offset += idx * board->uart_offset;
744
745 base = pci_resource_start(priv->dev, bar);
746 len = pci_resource_len(priv->dev, bar);
747 p = ioremap_nocache(base, len);
748
749 /* enable the transciever */
750 writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE,
751 p + offset + NI8430_PORTCON);
752
753 iounmap(p);
754
755 return setup_port(priv, port, bar, offset, board->reg_shift);
756}
757
758
61a116ef 759static int pci_netmos_init(struct pci_dev *dev)
1da177e4
LT		 760{
761 /* subdevice 0x00PS means <P> parallel, <S> serial */
762 unsigned int num_serial = dev->subsystem_device & 0xf;
763
25cf9bc1
JS		 764 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
765 dev->subsystem_device == 0x0299)
766 return 0;
767
1da177e4
LT		 768 if (num_serial == 0)
769 return -ENODEV;
770 return num_serial;
771}
772
84f8c6fc 773/*
84f8c6fc
NV		 774 * These chips are available with optionally one parallel port and up to
775 * two serial ports. Unfortunately they all have the same product id.
776 *
777 * Basic configuration is done over a region of 32 I/O ports. The base
778 * ioport is called INTA or INTC, depending on docs/other drivers.
779 *
780 * The region of the 32 I/O ports is configured in POSIO0R...
781 */
782
783/* registers */
784#define ITE_887x_MISCR 0x9c
785#define ITE_887x_INTCBAR 0x78
786#define ITE_887x_UARTBAR 0x7c
787#define ITE_887x_PS0BAR 0x10
788#define ITE_887x_POSIO0 0x60
789
790/* I/O space size */
791#define ITE_887x_IOSIZE 32
792/* I/O space size (bits 26-24; 8 bytes = 011b) */
793#define ITE_887x_POSIO_IOSIZE_8 (3 << 24)
794/* I/O space size (bits 26-24; 32 bytes = 101b) */
795#define ITE_887x_POSIO_IOSIZE_32 (5 << 24)
796/* Decoding speed (1 = slow, 2 = medium, 3 = fast) */
797#define ITE_887x_POSIO_SPEED (3 << 29)
798/* enable IO_Space bit */
799#define ITE_887x_POSIO_ENABLE (1 << 31)
800
f79abb82 801static int pci_ite887x_init(struct pci_dev *dev)
84f8c6fc
NV		 802{
803 /* inta_addr are the configuration addresses of the ITE */
804 static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0,
805 0x200, 0x280, 0 };
806 int ret, i, type;
807 struct resource *iobase = NULL;
808 u32 miscr, uartbar, ioport;
809
810 /* search for the base-ioport */
811 i = 0;
812 while (inta_addr[i] && iobase == NULL) {
813 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE,
814 "ite887x");
815 if (iobase != NULL) {
816 /* write POSIO0R - speed | size | ioport */
817 pci_write_config_dword(dev, ITE_887x_POSIO0,
818 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
819 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]);
820 /* write INTCBAR - ioport */
5756ee99
AC		 821 pci_write_config_dword(dev, ITE_887x_INTCBAR,
822 inta_addr[i]);
84f8c6fc
NV		 823 ret = inb(inta_addr[i]);
824 if (ret != 0xff) {
825 /* ioport connected */
826 break;
827 }
828 release_region(iobase->start, ITE_887x_IOSIZE);
829 iobase = NULL;
830 }
831 i++;
832 }
833
834 if (!inta_addr[i]) {
835 printk(KERN_ERR "ite887x: could not find iobase\n");
836 return -ENODEV;
837 }
838
839 /* start of undocumented type checking (see parport_pc.c) */
840 type = inb(iobase->start + 0x18) & 0x0f;
841
842 switch (type) {
843 case 0x2: /* ITE8871 (1P) */
844 case 0xa: /* ITE8875 (1P) */
845 ret = 0;
846 break;
847 case 0xe: /* ITE8872 (2S1P) */
848 ret = 2;
849 break;
850 case 0x6: /* ITE8873 (1S) */
851 ret = 1;
852 break;
853 case 0x8: /* ITE8874 (2S) */
854 ret = 2;
855 break;
856 default:
857 moan_device("Unknown ITE887x", dev);
858 ret = -ENODEV;
859 }
860
861 /* configure all serial ports */
862 for (i = 0; i < ret; i++) {
863 /* read the I/O port from the device */
864 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)),
865 &ioport);
866 ioport &= 0x0000FF00; /* the actual base address */
867 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)),
868 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
869 ITE_887x_POSIO_IOSIZE_8 | ioport);
870
871 /* write the ioport to the UARTBAR */
872 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar);
873 uartbar &= ~(0xffff << (16 * i)); /* clear half the reg */
874 uartbar |= (ioport << (16 * i)); /* set the ioport */
875 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar);
876
877 /* get current config */
878 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr);
879 /* disable interrupts (UARTx_Routing[3:0]) */
880 miscr &= ~(0xf << (12 - 4 * i));
881 /* activate the UART (UARTx_En) */
882 miscr |= 1 << (23 - i);
883 /* write new config with activated UART */
884 pci_write_config_dword(dev, ITE_887x_MISCR, miscr);
885 }
886
887 if (ret <= 0) {
888 /* the device has no UARTs if we get here */
889 release_region(iobase->start, ITE_887x_IOSIZE);
890 }
891
892 return ret;
893}
894
895static void __devexit pci_ite887x_exit(struct pci_dev *dev)
896{
897 u32 ioport;
898 /* the ioport is bit 0-15 in POSIO0R */
899 pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport);
900 ioport &= 0xffff;
901 release_region(ioport, ITE_887x_IOSIZE);
902}
903
9f2a036a
RK		 904/*
905 * Oxford Semiconductor Inc.
906 * Check that device is part of the Tornado range of devices, then determine
907 * the number of ports available on the device.
908 */
909static int pci_oxsemi_tornado_init(struct pci_dev *dev)
910{
911 u8 __iomem *p;
912 unsigned long deviceID;
913 unsigned int number_uarts = 0;
914
915 /* OxSemi Tornado devices are all 0xCxxx */
916 if (dev->vendor == PCI_VENDOR_ID_OXSEMI &&
917 (dev->device & 0xF000) != 0xC000)
918 return 0;
919
920 p = pci_iomap(dev, 0, 5);
921 if (p == NULL)
922 return -ENOMEM;
923
924 deviceID = ioread32(p);
925 /* Tornado device */
926 if (deviceID == 0x07000200) {
927 number_uarts = ioread8(p + 4);
928 printk(KERN_DEBUG
929 "%d ports detected on Oxford PCI Express device\n",
930 number_uarts);
931 }
932 pci_iounmap(dev, p);
933 return number_uarts;
934}
935
1da177e4 936static int
975a1a7d
RK		 937pci_default_setup(struct serial_private *priv,
938 const struct pciserial_board *board,
1da177e4
LT		 939 struct uart_port *port, int idx)
940{
941 unsigned int bar, offset = board->first_offset, maxnr;
942
943 bar = FL_GET_BASE(board->flags);
944 if (board->flags & FL_BASE_BARS)
945 bar += idx;
946 else
947 offset += idx * board->uart_offset;
948
2427ddd8
GKH		 949 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
950 (board->reg_shift + 3);
1da177e4
LT		 951
952 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
953 return 1;
5756ee99 954
70db3d91 955 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 956}
957
b6adea33
MCC		 958static int skip_tx_en_setup(struct serial_private *priv,
959 const struct pciserial_board *board,
960 struct uart_port *port, int idx)
961{
962 port->flags |= UPF_NO_TXEN_TEST;
963 printk(KERN_DEBUG "serial8250: skipping TxEn test for device "
964 "[%04x:%04x] subsystem [%04x:%04x]\n",
965 priv->dev->vendor,
966 priv->dev->device,
967 priv->dev->subsystem_vendor,
968 priv->dev->subsystem_device);
969
970 return pci_default_setup(priv, board, port, idx);
971}
972
1da177e4
LT		 973/* This should be in linux/pci_ids.h */
974#define PCI_VENDOR_ID_SBSMODULARIO 0x124B
975#define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B
976#define PCI_DEVICE_ID_OCTPRO 0x0001
977#define PCI_SUBDEVICE_ID_OCTPRO232 0x0108
978#define PCI_SUBDEVICE_ID_OCTPRO422 0x0208
979#define PCI_SUBDEVICE_ID_POCTAL232 0x0308
980#define PCI_SUBDEVICE_ID_POCTAL422 0x0408
78d70d48
MB		 981#define PCI_VENDOR_ID_ADVANTECH 0x13fe
982#define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620
1da177e4 983
b76c5a07
CB		 984/* Unknown vendors/cards - this should not be in linux/pci_ids.h */
985#define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584
986
1da177e4
LT		 987/*
988 * Master list of serial port init/setup/exit quirks.
989 * This does not describe the general nature of the port.
990 * (ie, baud base, number and location of ports, etc)
991 *
992 * This list is ordered alphabetically by vendor then device.
993 * Specific entries must come before more generic entries.
994 */
7a63ce5a 995static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
02c9b5cf
KJ		 996 /*
997 * ADDI-DATA GmbH communication cards <info@addi-data.com>
998 */
999 {
1000 .vendor = PCI_VENDOR_ID_ADDIDATA_OLD,
1001 .device = PCI_DEVICE_ID_ADDIDATA_APCI7800,
1002 .subvendor = PCI_ANY_ID,
1003 .subdevice = PCI_ANY_ID,
1004 .setup = addidata_apci7800_setup,
1005 },
1da177e4 1006 /*
61a116ef 1007 * AFAVLAB cards - these may be called via parport_serial
1da177e4
LT		 1008 * It is not clear whether this applies to all products.
1009 */
1010 {
1011 .vendor = PCI_VENDOR_ID_AFAVLAB,
1012 .device = PCI_ANY_ID,
1013 .subvendor = PCI_ANY_ID,
1014 .subdevice = PCI_ANY_ID,
1015 .setup = afavlab_setup,
1016 },
1017 /*
1018 * HP Diva
1019 */
1020 {
1021 .vendor = PCI_VENDOR_ID_HP,
1022 .device = PCI_DEVICE_ID_HP_DIVA,
1023 .subvendor = PCI_ANY_ID,
1024 .subdevice = PCI_ANY_ID,
1025 .init = pci_hp_diva_init,
1026 .setup = pci_hp_diva_setup,
1027 },
1028 /*
1029 * Intel
1030 */
1031 {
1032 .vendor = PCI_VENDOR_ID_INTEL,
1033 .device = PCI_DEVICE_ID_INTEL_80960_RP,
1034 .subvendor = 0xe4bf,
1035 .subdevice = PCI_ANY_ID,
1036 .init = pci_inteli960ni_init,
1037 .setup = pci_default_setup,
1038 },
b6adea33
MCC		 1039 {
1040 .vendor = PCI_VENDOR_ID_INTEL,
1041 .device = PCI_DEVICE_ID_INTEL_8257X_SOL,
1042 .subvendor = PCI_ANY_ID,
1043 .subdevice = PCI_ANY_ID,
1044 .setup = skip_tx_en_setup,
1045 },
1046 {
1047 .vendor = PCI_VENDOR_ID_INTEL,
1048 .device = PCI_DEVICE_ID_INTEL_82573L_SOL,
1049 .subvendor = PCI_ANY_ID,
1050 .subdevice = PCI_ANY_ID,
1051 .setup = skip_tx_en_setup,
1052 },
1053 {
1054 .vendor = PCI_VENDOR_ID_INTEL,
1055 .device = PCI_DEVICE_ID_INTEL_82573E_SOL,
1056 .subvendor = PCI_ANY_ID,
1057 .subdevice = PCI_ANY_ID,
1058 .setup = skip_tx_en_setup,
1059 },
84f8c6fc
NV		 1060 /*
1061 * ITE
1062 */
1063 {
1064 .vendor = PCI_VENDOR_ID_ITE,
1065 .device = PCI_DEVICE_ID_ITE_8872,
1066 .subvendor = PCI_ANY_ID,
1067 .subdevice = PCI_ANY_ID,
1068 .init = pci_ite887x_init,
1069 .setup = pci_default_setup,
1070 .exit = __devexit_p(pci_ite887x_exit),
1071 },
46a0fac9
SB		 1072 /*
1073 * National Instruments
1074 */
04bf7e74
WP		 1075 {
1076 .vendor = PCI_VENDOR_ID_NI,
1077 .device = PCI_DEVICE_ID_NI_PCI23216,
1078 .subvendor = PCI_ANY_ID,
1079 .subdevice = PCI_ANY_ID,
1080 .init = pci_ni8420_init,
1081 .setup = pci_default_setup,
1082 .exit = __devexit_p(pci_ni8420_exit),
1083 },
1084 {
1085 .vendor = PCI_VENDOR_ID_NI,
1086 .device = PCI_DEVICE_ID_NI_PCI2328,
1087 .subvendor = PCI_ANY_ID,
1088 .subdevice = PCI_ANY_ID,
1089 .init = pci_ni8420_init,
1090 .setup = pci_default_setup,
1091 .exit = __devexit_p(pci_ni8420_exit),
1092 },
1093 {
1094 .vendor = PCI_VENDOR_ID_NI,
1095 .device = PCI_DEVICE_ID_NI_PCI2324,
1096 .subvendor = PCI_ANY_ID,
1097 .subdevice = PCI_ANY_ID,
1098 .init = pci_ni8420_init,
1099 .setup = pci_default_setup,
1100 .exit = __devexit_p(pci_ni8420_exit),
1101 },
1102 {
1103 .vendor = PCI_VENDOR_ID_NI,
1104 .device = PCI_DEVICE_ID_NI_PCI2322,
1105 .subvendor = PCI_ANY_ID,
1106 .subdevice = PCI_ANY_ID,
1107 .init = pci_ni8420_init,
1108 .setup = pci_default_setup,
1109 .exit = __devexit_p(pci_ni8420_exit),
1110 },
1111 {
1112 .vendor = PCI_VENDOR_ID_NI,
1113 .device = PCI_DEVICE_ID_NI_PCI2324I,
1114 .subvendor = PCI_ANY_ID,
1115 .subdevice = PCI_ANY_ID,
1116 .init = pci_ni8420_init,
1117 .setup = pci_default_setup,
1118 .exit = __devexit_p(pci_ni8420_exit),
1119 },
1120 {
1121 .vendor = PCI_VENDOR_ID_NI,
1122 .device = PCI_DEVICE_ID_NI_PCI2322I,
1123 .subvendor = PCI_ANY_ID,
1124 .subdevice = PCI_ANY_ID,
1125 .init = pci_ni8420_init,
1126 .setup = pci_default_setup,
1127 .exit = __devexit_p(pci_ni8420_exit),
1128 },
1129 {
1130 .vendor = PCI_VENDOR_ID_NI,
1131 .device = PCI_DEVICE_ID_NI_PXI8420_23216,
1132 .subvendor = PCI_ANY_ID,
1133 .subdevice = PCI_ANY_ID,
1134 .init = pci_ni8420_init,
1135 .setup = pci_default_setup,
1136 .exit = __devexit_p(pci_ni8420_exit),
1137 },
1138 {
1139 .vendor = PCI_VENDOR_ID_NI,
1140 .device = PCI_DEVICE_ID_NI_PXI8420_2328,
1141 .subvendor = PCI_ANY_ID,
1142 .subdevice = PCI_ANY_ID,
1143 .init = pci_ni8420_init,
1144 .setup = pci_default_setup,
1145 .exit = __devexit_p(pci_ni8420_exit),
1146 },
1147 {
1148 .vendor = PCI_VENDOR_ID_NI,
1149 .device = PCI_DEVICE_ID_NI_PXI8420_2324,
1150 .subvendor = PCI_ANY_ID,
1151 .subdevice = PCI_ANY_ID,
1152 .init = pci_ni8420_init,
1153 .setup = pci_default_setup,
1154 .exit = __devexit_p(pci_ni8420_exit),
1155 },
1156 {
1157 .vendor = PCI_VENDOR_ID_NI,
1158 .device = PCI_DEVICE_ID_NI_PXI8420_2322,
1159 .subvendor = PCI_ANY_ID,
1160 .subdevice = PCI_ANY_ID,
1161 .init = pci_ni8420_init,
1162 .setup = pci_default_setup,
1163 .exit = __devexit_p(pci_ni8420_exit),
1164 },
1165 {
1166 .vendor = PCI_VENDOR_ID_NI,
1167 .device = PCI_DEVICE_ID_NI_PXI8422_2324,
1168 .subvendor = PCI_ANY_ID,
1169 .subdevice = PCI_ANY_ID,
1170 .init = pci_ni8420_init,
1171 .setup = pci_default_setup,
1172 .exit = __devexit_p(pci_ni8420_exit),
1173 },
1174 {
1175 .vendor = PCI_VENDOR_ID_NI,
1176 .device = PCI_DEVICE_ID_NI_PXI8422_2322,
1177 .subvendor = PCI_ANY_ID,
1178 .subdevice = PCI_ANY_ID,
1179 .init = pci_ni8420_init,
1180 .setup = pci_default_setup,
1181 .exit = __devexit_p(pci_ni8420_exit),
1182 },
46a0fac9
SB		 1183 {
1184 .vendor = PCI_VENDOR_ID_NI,
1185 .device = PCI_ANY_ID,
1186 .subvendor = PCI_ANY_ID,
1187 .subdevice = PCI_ANY_ID,
1188 .init = pci_ni8430_init,
1189 .setup = pci_ni8430_setup,
1190 .exit = __devexit_p(pci_ni8430_exit),
1191 },
1da177e4
LT		 1192 /*
1193 * Panacom
1194 */
1195 {
1196 .vendor = PCI_VENDOR_ID_PANACOM,
1197 .device = PCI_DEVICE_ID_PANACOM_QUADMODEM,
1198 .subvendor = PCI_ANY_ID,
1199 .subdevice = PCI_ANY_ID,
1200 .init = pci_plx9050_init,
1201 .setup = pci_default_setup,
1202 .exit = __devexit_p(pci_plx9050_exit),
5756ee99 1203 },
1da177e4
LT		 1204 {
1205 .vendor = PCI_VENDOR_ID_PANACOM,
1206 .device = PCI_DEVICE_ID_PANACOM_DUALMODEM,
1207 .subvendor = PCI_ANY_ID,
1208 .subdevice = PCI_ANY_ID,
1209 .init = pci_plx9050_init,
1210 .setup = pci_default_setup,
1211 .exit = __devexit_p(pci_plx9050_exit),
1212 },
1213 /*
1214 * PLX
1215 */
48212008
TH		 1216 {
1217 .vendor = PCI_VENDOR_ID_PLX,
1218 .device = PCI_DEVICE_ID_PLX_9030,
1219 .subvendor = PCI_SUBVENDOR_ID_PERLE,
1220 .subdevice = PCI_ANY_ID,
1221 .setup = pci_default_setup,
1222 },
add7b58e
BH		 1223 {
1224 .vendor = PCI_VENDOR_ID_PLX,
1225 .device = PCI_DEVICE_ID_PLX_9050,
1226 .subvendor = PCI_SUBVENDOR_ID_EXSYS,
1227 .subdevice = PCI_SUBDEVICE_ID_EXSYS_4055,
1228 .init = pci_plx9050_init,
1229 .setup = pci_default_setup,
1230 .exit = __devexit_p(pci_plx9050_exit),
1231 },
1da177e4
LT		 1232 {
1233 .vendor = PCI_VENDOR_ID_PLX,
1234 .device = PCI_DEVICE_ID_PLX_9050,
1235 .subvendor = PCI_SUBVENDOR_ID_KEYSPAN,
1236 .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
1237 .init = pci_plx9050_init,
1238 .setup = pci_default_setup,
1239 .exit = __devexit_p(pci_plx9050_exit),
1240 },
b76c5a07
CB		 1241 {
1242 .vendor = PCI_VENDOR_ID_PLX,
1243 .device = PCI_DEVICE_ID_PLX_9050,
1244 .subvendor = PCI_VENDOR_ID_PLX,
1245 .subdevice = PCI_SUBDEVICE_ID_UNKNOWN_0x1584,
1246 .init = pci_plx9050_init,
1247 .setup = pci_default_setup,
1248 .exit = __devexit_p(pci_plx9050_exit),
1249 },
1da177e4
LT		 1250 {
1251 .vendor = PCI_VENDOR_ID_PLX,
1252 .device = PCI_DEVICE_ID_PLX_ROMULUS,
1253 .subvendor = PCI_VENDOR_ID_PLX,
1254 .subdevice = PCI_DEVICE_ID_PLX_ROMULUS,
1255 .init = pci_plx9050_init,
1256 .setup = pci_default_setup,
1257 .exit = __devexit_p(pci_plx9050_exit),
1258 },
1259 /*
1260 * SBS Technologies, Inc., PMC-OCTALPRO 232
1261 */
1262 {
1263 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
1264 .device = PCI_DEVICE_ID_OCTPRO,
1265 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
1266 .subdevice = PCI_SUBDEVICE_ID_OCTPRO232,
1267 .init = sbs_init,
1268 .setup = sbs_setup,
1269 .exit = __devexit_p(sbs_exit),
1270 },
1271 /*
1272 * SBS Technologies, Inc., PMC-OCTALPRO 422
1273 */
1274 {
1275 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
1276 .device = PCI_DEVICE_ID_OCTPRO,
1277 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
1278 .subdevice = PCI_SUBDEVICE_ID_OCTPRO422,
1279 .init = sbs_init,
1280 .setup = sbs_setup,
1281 .exit = __devexit_p(sbs_exit),
1282 },
1283 /*
1284 * SBS Technologies, Inc., P-Octal 232
1285 */
1286 {
1287 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
1288 .device = PCI_DEVICE_ID_OCTPRO,
1289 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
1290 .subdevice = PCI_SUBDEVICE_ID_POCTAL232,
1291 .init = sbs_init,
1292 .setup = sbs_setup,
1293 .exit = __devexit_p(sbs_exit),
1294 },
1295 /*
1296 * SBS Technologies, Inc., P-Octal 422
1297 */
1298 {
1299 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
1300 .device = PCI_DEVICE_ID_OCTPRO,
1301 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
1302 .subdevice = PCI_SUBDEVICE_ID_POCTAL422,
1303 .init = sbs_init,
1304 .setup = sbs_setup,
1305 .exit = __devexit_p(sbs_exit),
1306 },
1da177e4 1307 /*
61a116ef 1308 * SIIG cards - these may be called via parport_serial
1da177e4
LT		 1309 */
1310 {
1311 .vendor = PCI_VENDOR_ID_SIIG,
67d74b87 1312 .device = PCI_ANY_ID,
1da177e4
LT		 1313 .subvendor = PCI_ANY_ID,
1314 .subdevice = PCI_ANY_ID,
67d74b87 1315 .init = pci_siig_init,
3ec9c594 1316 .setup = pci_siig_setup,
1da177e4
LT		 1317 },
1318 /*
1319 * Titan cards
1320 */
1321 {
1322 .vendor = PCI_VENDOR_ID_TITAN,
1323 .device = PCI_DEVICE_ID_TITAN_400L,
1324 .subvendor = PCI_ANY_ID,
1325 .subdevice = PCI_ANY_ID,
1326 .setup = titan_400l_800l_setup,
1327 },
1328 {
1329 .vendor = PCI_VENDOR_ID_TITAN,
1330 .device = PCI_DEVICE_ID_TITAN_800L,
1331 .subvendor = PCI_ANY_ID,
1332 .subdevice = PCI_ANY_ID,
1333 .setup = titan_400l_800l_setup,
1334 },
1335 /*
1336 * Timedia cards
1337 */
1338 {
1339 .vendor = PCI_VENDOR_ID_TIMEDIA,
1340 .device = PCI_DEVICE_ID_TIMEDIA_1889,
1341 .subvendor = PCI_VENDOR_ID_TIMEDIA,
1342 .subdevice = PCI_ANY_ID,
1343 .init = pci_timedia_init,
1344 .setup = pci_timedia_setup,
1345 },
1346 {
1347 .vendor = PCI_VENDOR_ID_TIMEDIA,
1348 .device = PCI_ANY_ID,
1349 .subvendor = PCI_ANY_ID,
1350 .subdevice = PCI_ANY_ID,
1351 .setup = pci_timedia_setup,
1352 },
1353 /*
1354 * Xircom cards
1355 */
1356 {
1357 .vendor = PCI_VENDOR_ID_XIRCOM,
1358 .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
1359 .subvendor = PCI_ANY_ID,
1360 .subdevice = PCI_ANY_ID,
1361 .init = pci_xircom_init,
1362 .setup = pci_default_setup,
1363 },
1364 /*
61a116ef 1365 * Netmos cards - these may be called via parport_serial
1da177e4
LT		 1366 */
1367 {
1368 .vendor = PCI_VENDOR_ID_NETMOS,
1369 .device = PCI_ANY_ID,
1370 .subvendor = PCI_ANY_ID,
1371 .subdevice = PCI_ANY_ID,
1372 .init = pci_netmos_init,
1373 .setup = pci_default_setup,
1374 },
9f2a036a
RK		 1375 /*
1376 * For Oxford Semiconductor and Mainpine
1377 */
1378 {
1379 .vendor = PCI_VENDOR_ID_OXSEMI,
1380 .device = PCI_ANY_ID,
1381 .subvendor = PCI_ANY_ID,
1382 .subdevice = PCI_ANY_ID,
1383 .init = pci_oxsemi_tornado_init,
1384 .setup = pci_default_setup,
1385 },
1386 {
1387 .vendor = PCI_VENDOR_ID_MAINPINE,
1388 .device = PCI_ANY_ID,
1389 .subvendor = PCI_ANY_ID,
1390 .subdevice = PCI_ANY_ID,
1391 .init = pci_oxsemi_tornado_init,
1392 .setup = pci_default_setup,
1393 },
1da177e4
LT		 1394 /*
1395 * Default "match everything" terminator entry
1396 */
1397 {
1398 .vendor = PCI_ANY_ID,
1399 .device = PCI_ANY_ID,
1400 .subvendor = PCI_ANY_ID,
1401 .subdevice = PCI_ANY_ID,
1402 .setup = pci_default_setup,
1403 }
1404};
1405
1406static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
1407{
1408 return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
1409}
1410
1411static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
1412{
1413 struct pci_serial_quirk *quirk;
1414
1415 for (quirk = pci_serial_quirks; ; quirk++)
1416 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
1417 quirk_id_matches(quirk->device, dev->device) &&
1418 quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
1419 quirk_id_matches(quirk->subdevice, dev->subsystem_device))
5756ee99 1420 break;
1da177e4
LT		 1421 return quirk;
1422}
1423
dd68e88c 1424static inline int get_pci_irq(struct pci_dev *dev,
975a1a7d 1425 const struct pciserial_board *board)
1da177e4
LT		 1426{
1427 if (board->flags & FL_NOIRQ)
1428 return 0;
1429 else
1430 return dev->irq;
1431}
1432
1433/*
1434 * This is the configuration table for all of the PCI serial boards
1435 * which we support. It is directly indexed by the pci_board_num_t enum
1436 * value, which is encoded in the pci_device_id PCI probe table's
1437 * driver_data member.
1438 *
1439 * The makeup of these names are:
26e92861 1440 * pbn_bn{_bt}_n_baud{_offsetinhex}
1da177e4 1441 *
26e92861
GH		 1442 * bn = PCI BAR number
1443 * bt = Index using PCI BARs
1444 * n = number of serial ports
1445 * baud = baud rate
1446 * offsetinhex = offset for each sequential port (in hex)
1da177e4 1447 *
26e92861 1448 * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
f1690f37 1449 *
1da177e4
LT		 1450 * Please note: in theory if n = 1, _bt infix should make no difference.
1451 * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
1452 */
1453enum pci_board_num_t {
1454 pbn_default = 0,
1455
1456 pbn_b0_1_115200,
1457 pbn_b0_2_115200,
1458 pbn_b0_4_115200,
1459 pbn_b0_5_115200,
bf0df636 1460 pbn_b0_8_115200,
1da177e4
LT		 1461
1462 pbn_b0_1_921600,
1463 pbn_b0_2_921600,
1464 pbn_b0_4_921600,
1465
db1de159
DR		 1466 pbn_b0_2_1130000,
1467
fbc0dc0d
AP		 1468 pbn_b0_4_1152000,
1469
26e92861
GH		 1470 pbn_b0_2_1843200,
1471 pbn_b0_4_1843200,
1472
1473 pbn_b0_2_1843200_200,
1474 pbn_b0_4_1843200_200,
1475 pbn_b0_8_1843200_200,
1476
7106b4e3
LH		 1477 pbn_b0_1_4000000,
1478
1da177e4
LT		 1479 pbn_b0_bt_1_115200,
1480 pbn_b0_bt_2_115200,
1481 pbn_b0_bt_8_115200,
1482
1483 pbn_b0_bt_1_460800,
1484 pbn_b0_bt_2_460800,
1485 pbn_b0_bt_4_460800,
1486
1487 pbn_b0_bt_1_921600,
1488 pbn_b0_bt_2_921600,
1489 pbn_b0_bt_4_921600,
1490 pbn_b0_bt_8_921600,
1491
1492 pbn_b1_1_115200,
1493 pbn_b1_2_115200,
1494 pbn_b1_4_115200,
1495 pbn_b1_8_115200,
04bf7e74 1496 pbn_b1_16_115200,
1da177e4
LT		 1497
1498 pbn_b1_1_921600,
1499 pbn_b1_2_921600,
1500 pbn_b1_4_921600,
1501 pbn_b1_8_921600,
1502
26e92861
GH		 1503 pbn_b1_2_1250000,
1504
84f8c6fc 1505 pbn_b1_bt_1_115200,
04bf7e74
WP		 1506 pbn_b1_bt_2_115200,
1507 pbn_b1_bt_4_115200,
1508
1da177e4
LT		 1509 pbn_b1_bt_2_921600,
1510
1511 pbn_b1_1_1382400,
1512 pbn_b1_2_1382400,
1513 pbn_b1_4_1382400,
1514 pbn_b1_8_1382400,
1515
1516 pbn_b2_1_115200,
737c1756 1517 pbn_b2_2_115200,
a9cccd34 1518 pbn_b2_4_115200,
1da177e4
LT		 1519 pbn_b2_8_115200,
1520
1521 pbn_b2_1_460800,
1522 pbn_b2_4_460800,
1523 pbn_b2_8_460800,
1524 pbn_b2_16_460800,
1525
1526 pbn_b2_1_921600,
1527 pbn_b2_4_921600,
1528 pbn_b2_8_921600,
1529
1530 pbn_b2_bt_1_115200,
1531 pbn_b2_bt_2_115200,
1532 pbn_b2_bt_4_115200,
1533
1534 pbn_b2_bt_2_921600,
1535 pbn_b2_bt_4_921600,
1536
d9004eb4 1537 pbn_b3_2_115200,
1da177e4
LT		 1538 pbn_b3_4_115200,
1539 pbn_b3_8_115200,
1540
1541 /*
1542 * Board-specific versions.
1543 */
1544 pbn_panacom,
1545 pbn_panacom2,
1546 pbn_panacom4,
add7b58e 1547 pbn_exsys_4055,
1da177e4
LT		 1548 pbn_plx_romulus,
1549 pbn_oxsemi,
7106b4e3
LH		 1550 pbn_oxsemi_1_4000000,
1551 pbn_oxsemi_2_4000000,
1552 pbn_oxsemi_4_4000000,
1553 pbn_oxsemi_8_4000000,
1da177e4
LT		 1554 pbn_intel_i960,
1555 pbn_sgi_ioc3,
1da177e4
LT		 1556 pbn_computone_4,
1557 pbn_computone_6,
1558 pbn_computone_8,
1559 pbn_sbsxrsio,
1560 pbn_exar_XR17C152,
1561 pbn_exar_XR17C154,
1562 pbn_exar_XR17C158,
aa798505 1563 pbn_pasemi_1682M,
46a0fac9
SB		 1564 pbn_ni8430_2,
1565 pbn_ni8430_4,
1566 pbn_ni8430_8,
1567 pbn_ni8430_16,
1da177e4
LT		 1568};
1569
1570/*
1571 * uart_offset - the space between channels
1572 * reg_shift - describes how the UART registers are mapped
1573 * to PCI memory by the card.
1574 * For example IER register on SBS, Inc. PMC-OctPro is located at
1575 * offset 0x10 from the UART base, while UART_IER is defined as 1
1576 * in include/linux/serial_reg.h,
1577 * see first lines of serial_in() and serial_out() in 8250.c
1578*/
1579
1c7c1fe5 1580static struct pciserial_board pci_boards[] __devinitdata = {
1da177e4
LT		 1581 [pbn_default] = {
1582 .flags = FL_BASE0,
1583 .num_ports = 1,
1584 .base_baud = 115200,
1585 .uart_offset = 8,
1586 },
1587 [pbn_b0_1_115200] = {
1588 .flags = FL_BASE0,
1589 .num_ports = 1,
1590 .base_baud = 115200,
1591 .uart_offset = 8,
1592 },
1593 [pbn_b0_2_115200] = {
1594 .flags = FL_BASE0,
1595 .num_ports = 2,
1596 .base_baud = 115200,
1597 .uart_offset = 8,
1598 },
1599 [pbn_b0_4_115200] = {
1600 .flags = FL_BASE0,
1601 .num_ports = 4,
1602 .base_baud = 115200,
1603 .uart_offset = 8,
1604 },
1605 [pbn_b0_5_115200] = {
1606 .flags = FL_BASE0,
1607 .num_ports = 5,
1608 .base_baud = 115200,
1609 .uart_offset = 8,
1610 },
bf0df636
AC		 1611 [pbn_b0_8_115200] = {
1612 .flags = FL_BASE0,
1613 .num_ports = 8,
1614 .base_baud = 115200,
1615 .uart_offset = 8,
1616 },
1da177e4
LT		 1617 [pbn_b0_1_921600] = {
1618 .flags = FL_BASE0,
1619 .num_ports = 1,
1620 .base_baud = 921600,
1621 .uart_offset = 8,
1622 },
1623 [pbn_b0_2_921600] = {
1624 .flags = FL_BASE0,
1625 .num_ports = 2,
1626 .base_baud = 921600,
1627 .uart_offset = 8,
1628 },
1629 [pbn_b0_4_921600] = {
1630 .flags = FL_BASE0,
1631 .num_ports = 4,
1632 .base_baud = 921600,
1633 .uart_offset = 8,
1634 },
db1de159
DR		 1635
1636 [pbn_b0_2_1130000] = {
1637 .flags = FL_BASE0,
1638 .num_ports = 2,
1639 .base_baud = 1130000,
1640 .uart_offset = 8,
1641 },
1642
fbc0dc0d
AP		 1643 [pbn_b0_4_1152000] = {
1644 .flags = FL_BASE0,
1645 .num_ports = 4,
1646 .base_baud = 1152000,
1647 .uart_offset = 8,
1648 },
1da177e4 1649
26e92861
GH		 1650 [pbn_b0_2_1843200] = {
1651 .flags = FL_BASE0,
1652 .num_ports = 2,
1653 .base_baud = 1843200,
1654 .uart_offset = 8,
1655 },
1656 [pbn_b0_4_1843200] = {
1657 .flags = FL_BASE0,
1658 .num_ports = 4,
1659 .base_baud = 1843200,
1660 .uart_offset = 8,
1661 },
1662
1663 [pbn_b0_2_1843200_200] = {
1664 .flags = FL_BASE0,
1665 .num_ports = 2,
1666 .base_baud = 1843200,
1667 .uart_offset = 0x200,
1668 },
1669 [pbn_b0_4_1843200_200] = {
1670 .flags = FL_BASE0,
1671 .num_ports = 4,
1672 .base_baud = 1843200,
1673 .uart_offset = 0x200,
1674 },
1675 [pbn_b0_8_1843200_200] = {
1676 .flags = FL_BASE0,
1677 .num_ports = 8,
1678 .base_baud = 1843200,
1679 .uart_offset = 0x200,
1680 },
7106b4e3
LH		 1681 [pbn_b0_1_4000000] = {
1682 .flags = FL_BASE0,
1683 .num_ports = 1,
1684 .base_baud = 4000000,
1685 .uart_offset = 8,
1686 },
26e92861 1687
1da177e4
LT		 1688 [pbn_b0_bt_1_115200] = {
1689 .flags = FL_BASE0|FL_BASE_BARS,
1690 .num_ports = 1,
1691 .base_baud = 115200,
1692 .uart_offset = 8,
1693 },
1694 [pbn_b0_bt_2_115200] = {
1695 .flags = FL_BASE0|FL_BASE_BARS,
1696 .num_ports = 2,
1697 .base_baud = 115200,
1698 .uart_offset = 8,
1699 },
1700 [pbn_b0_bt_8_115200] = {
1701 .flags = FL_BASE0|FL_BASE_BARS,
1702 .num_ports = 8,
1703 .base_baud = 115200,
1704 .uart_offset = 8,
1705 },
1706
1707 [pbn_b0_bt_1_460800] = {
1708 .flags = FL_BASE0|FL_BASE_BARS,
1709 .num_ports = 1,
1710 .base_baud = 460800,
1711 .uart_offset = 8,
1712 },
1713 [pbn_b0_bt_2_460800] = {
1714 .flags = FL_BASE0|FL_BASE_BARS,
1715 .num_ports = 2,
1716 .base_baud = 460800,
1717 .uart_offset = 8,
1718 },
1719 [pbn_b0_bt_4_460800] = {
1720 .flags = FL_BASE0|FL_BASE_BARS,
1721 .num_ports = 4,
1722 .base_baud = 460800,
1723 .uart_offset = 8,
1724 },
1725
1726 [pbn_b0_bt_1_921600] = {
1727 .flags = FL_BASE0|FL_BASE_BARS,
1728 .num_ports = 1,
1729 .base_baud = 921600,
1730 .uart_offset = 8,
1731 },
1732 [pbn_b0_bt_2_921600] = {
1733 .flags = FL_BASE0|FL_BASE_BARS,
1734 .num_ports = 2,
1735 .base_baud = 921600,
1736 .uart_offset = 8,
1737 },
1738 [pbn_b0_bt_4_921600] = {
1739 .flags = FL_BASE0|FL_BASE_BARS,
1740 .num_ports = 4,
1741 .base_baud = 921600,
1742 .uart_offset = 8,
1743 },
1744 [pbn_b0_bt_8_921600] = {
1745 .flags = FL_BASE0|FL_BASE_BARS,
1746 .num_ports = 8,
1747 .base_baud = 921600,
1748 .uart_offset = 8,
1749 },
1750
1751 [pbn_b1_1_115200] = {
1752 .flags = FL_BASE1,
1753 .num_ports = 1,
1754 .base_baud = 115200,
1755 .uart_offset = 8,
1756 },
1757 [pbn_b1_2_115200] = {
1758 .flags = FL_BASE1,
1759 .num_ports = 2,
1760 .base_baud = 115200,
1761 .uart_offset = 8,
1762 },
1763 [pbn_b1_4_115200] = {
1764 .flags = FL_BASE1,
1765 .num_ports = 4,
1766 .base_baud = 115200,
1767 .uart_offset = 8,
1768 },
1769 [pbn_b1_8_115200] = {
1770 .flags = FL_BASE1,
1771 .num_ports = 8,
1772 .base_baud = 115200,
1773 .uart_offset = 8,
1774 },
04bf7e74
WP		 1775 [pbn_b1_16_115200] = {
1776 .flags = FL_BASE1,
1777 .num_ports = 16,
1778 .base_baud = 115200,
1779 .uart_offset = 8,
1780 },
1da177e4
LT		 1781
1782 [pbn_b1_1_921600] = {
1783 .flags = FL_BASE1,
1784 .num_ports = 1,
1785 .base_baud = 921600,
1786 .uart_offset = 8,
1787 },
1788 [pbn_b1_2_921600] = {
1789 .flags = FL_BASE1,
1790 .num_ports = 2,
1791 .base_baud = 921600,
1792 .uart_offset = 8,
1793 },
1794 [pbn_b1_4_921600] = {
1795 .flags = FL_BASE1,
1796 .num_ports = 4,
1797 .base_baud = 921600,
1798 .uart_offset = 8,
1799 },
1800 [pbn_b1_8_921600] = {
1801 .flags = FL_BASE1,
1802 .num_ports = 8,
1803 .base_baud = 921600,
1804 .uart_offset = 8,
1805 },
26e92861
GH		 1806 [pbn_b1_2_1250000] = {
1807 .flags = FL_BASE1,
1808 .num_ports = 2,
1809 .base_baud = 1250000,
1810 .uart_offset = 8,
1811 },
1da177e4 1812
84f8c6fc
NV		 1813 [pbn_b1_bt_1_115200] = {
1814 .flags = FL_BASE1|FL_BASE_BARS,
1815 .num_ports = 1,
1816 .base_baud = 115200,
1817 .uart_offset = 8,
1818 },
04bf7e74
WP		 1819 [pbn_b1_bt_2_115200] = {
1820 .flags = FL_BASE1|FL_BASE_BARS,
1821 .num_ports = 2,
1822 .base_baud = 115200,
1823 .uart_offset = 8,
1824 },
1825 [pbn_b1_bt_4_115200] = {
1826 .flags = FL_BASE1|FL_BASE_BARS,
1827 .num_ports = 4,
1828 .base_baud = 115200,
1829 .uart_offset = 8,
1830 },
84f8c6fc 1831
1da177e4
LT		 1832 [pbn_b1_bt_2_921600] = {
1833 .flags = FL_BASE1|FL_BASE_BARS,
1834 .num_ports = 2,
1835 .base_baud = 921600,
1836 .uart_offset = 8,
1837 },
1838
1839 [pbn_b1_1_1382400] = {
1840 .flags = FL_BASE1,
1841 .num_ports = 1,
1842 .base_baud = 1382400,
1843 .uart_offset = 8,
1844 },
1845 [pbn_b1_2_1382400] = {
1846 .flags = FL_BASE1,
1847 .num_ports = 2,
1848 .base_baud = 1382400,
1849 .uart_offset = 8,
1850 },
1851 [pbn_b1_4_1382400] = {
1852 .flags = FL_BASE1,
1853 .num_ports = 4,
1854 .base_baud = 1382400,
1855 .uart_offset = 8,
1856 },
1857 [pbn_b1_8_1382400] = {
1858 .flags = FL_BASE1,
1859 .num_ports = 8,
1860 .base_baud = 1382400,
1861 .uart_offset = 8,
1862 },
1863
1864 [pbn_b2_1_115200] = {
1865 .flags = FL_BASE2,
1866 .num_ports = 1,
1867 .base_baud = 115200,
1868 .uart_offset = 8,
1869 },
737c1756
PH		 1870 [pbn_b2_2_115200] = {
1871 .flags = FL_BASE2,
1872 .num_ports = 2,
1873 .base_baud = 115200,
1874 .uart_offset = 8,
1875 },
a9cccd34
MF		 1876 [pbn_b2_4_115200] = {
1877 .flags = FL_BASE2,
1878 .num_ports = 4,
1879 .base_baud = 115200,
1880 .uart_offset = 8,
1881 },
1da177e4
LT		 1882 [pbn_b2_8_115200] = {
1883 .flags = FL_BASE2,
1884 .num_ports = 8,
1885 .base_baud = 115200,
1886 .uart_offset = 8,
1887 },
1888
1889 [pbn_b2_1_460800] = {
1890 .flags = FL_BASE2,
1891 .num_ports = 1,
1892 .base_baud = 460800,
1893 .uart_offset = 8,
1894 },
1895 [pbn_b2_4_460800] = {
1896 .flags = FL_BASE2,
1897 .num_ports = 4,
1898 .base_baud = 460800,
1899 .uart_offset = 8,
1900 },
1901 [pbn_b2_8_460800] = {
1902 .flags = FL_BASE2,
1903 .num_ports = 8,
1904 .base_baud = 460800,
1905 .uart_offset = 8,
1906 },
1907 [pbn_b2_16_460800] = {
1908 .flags = FL_BASE2,
1909 .num_ports = 16,
1910 .base_baud = 460800,
1911 .uart_offset = 8,
1912 },
1913
1914 [pbn_b2_1_921600] = {
1915 .flags = FL_BASE2,
1916 .num_ports = 1,
1917 .base_baud = 921600,
1918 .uart_offset = 8,
1919 },
1920 [pbn_b2_4_921600] = {
1921 .flags = FL_BASE2,
1922 .num_ports = 4,
1923 .base_baud = 921600,
1924 .uart_offset = 8,
1925 },
1926 [pbn_b2_8_921600] = {
1927 .flags = FL_BASE2,
1928 .num_ports = 8,
1929 .base_baud = 921600,
1930 .uart_offset = 8,
1931 },
1932
1933 [pbn_b2_bt_1_115200] = {
1934 .flags = FL_BASE2|FL_BASE_BARS,
1935 .num_ports = 1,
1936 .base_baud = 115200,
1937 .uart_offset = 8,
1938 },
1939 [pbn_b2_bt_2_115200] = {
1940 .flags = FL_BASE2|FL_BASE_BARS,
1941 .num_ports = 2,
1942 .base_baud = 115200,
1943 .uart_offset = 8,
1944 },
1945 [pbn_b2_bt_4_115200] = {
1946 .flags = FL_BASE2|FL_BASE_BARS,
1947 .num_ports = 4,
1948 .base_baud = 115200,
1949 .uart_offset = 8,
1950 },
1951
1952 [pbn_b2_bt_2_921600] = {
1953 .flags = FL_BASE2|FL_BASE_BARS,
1954 .num_ports = 2,
1955 .base_baud = 921600,
1956 .uart_offset = 8,
1957 },
1958 [pbn_b2_bt_4_921600] = {
1959 .flags = FL_BASE2|FL_BASE_BARS,
1960 .num_ports = 4,
1961 .base_baud = 921600,
1962 .uart_offset = 8,
1963 },
1964
d9004eb4
ABL		 1965 [pbn_b3_2_115200] = {
1966 .flags = FL_BASE3,
1967 .num_ports = 2,
1968 .base_baud = 115200,
1969 .uart_offset = 8,
1970 },
1da177e4
LT		 1971 [pbn_b3_4_115200] = {
1972 .flags = FL_BASE3,
1973 .num_ports = 4,
1974 .base_baud = 115200,
1975 .uart_offset = 8,
1976 },
1977 [pbn_b3_8_115200] = {
1978 .flags = FL_BASE3,
1979 .num_ports = 8,
1980 .base_baud = 115200,
1981 .uart_offset = 8,
1982 },
1983
1984 /*
1985 * Entries following this are board-specific.
1986 */
1987
1988 /*
1989 * Panacom - IOMEM
1990 */
1991 [pbn_panacom] = {
1992 .flags = FL_BASE2,
1993 .num_ports = 2,
1994 .base_baud = 921600,
1995 .uart_offset = 0x400,
1996 .reg_shift = 7,
1997 },
1998 [pbn_panacom2] = {
1999 .flags = FL_BASE2|FL_BASE_BARS,
2000 .num_ports = 2,
2001 .base_baud = 921600,
2002 .uart_offset = 0x400,
2003 .reg_shift = 7,
2004 },
2005 [pbn_panacom4] = {
2006 .flags = FL_BASE2|FL_BASE_BARS,
2007 .num_ports = 4,
2008 .base_baud = 921600,
2009 .uart_offset = 0x400,
2010 .reg_shift = 7,
2011 },
2012
add7b58e
BH		 2013 [pbn_exsys_4055] = {
2014 .flags = FL_BASE2,
2015 .num_ports = 4,
2016 .base_baud = 115200,
2017 .uart_offset = 8,
2018 },
2019
1da177e4
LT		 2020 /* I think this entry is broken - the first_offset looks wrong --rmk */
2021 [pbn_plx_romulus] = {
2022 .flags = FL_BASE2,
2023 .num_ports = 4,
2024 .base_baud = 921600,
2025 .uart_offset = 8 << 2,
2026 .reg_shift = 2,
2027 .first_offset = 0x03,
2028 },
2029
2030 /*
2031 * This board uses the size of PCI Base region 0 to
2032 * signal now many ports are available
2033 */
2034 [pbn_oxsemi] = {
2035 .flags = FL_BASE0|FL_REGION_SZ_CAP,
2036 .num_ports = 32,
2037 .base_baud = 115200,
2038 .uart_offset = 8,
2039 },
7106b4e3
LH		 2040 [pbn_oxsemi_1_4000000] = {
2041 .flags = FL_BASE0,
2042 .num_ports = 1,
2043 .base_baud = 4000000,
2044 .uart_offset = 0x200,
2045 .first_offset = 0x1000,
2046 },
2047 [pbn_oxsemi_2_4000000] = {
2048 .flags = FL_BASE0,
2049 .num_ports = 2,
2050 .base_baud = 4000000,
2051 .uart_offset = 0x200,
2052 .first_offset = 0x1000,
2053 },
2054 [pbn_oxsemi_4_4000000] = {
2055 .flags = FL_BASE0,
2056 .num_ports = 4,
2057 .base_baud = 4000000,
2058 .uart_offset = 0x200,
2059 .first_offset = 0x1000,
2060 },
2061 [pbn_oxsemi_8_4000000] = {
2062 .flags = FL_BASE0,
2063 .num_ports = 8,
2064 .base_baud = 4000000,
2065 .uart_offset = 0x200,
2066 .first_offset = 0x1000,
2067 },
2068
1da177e4
LT		 2069
2070 /*
2071 * EKF addition for i960 Boards form EKF with serial port.
2072 * Max 256 ports.
2073 */
2074 [pbn_intel_i960] = {
2075 .flags = FL_BASE0,
2076 .num_ports = 32,
2077 .base_baud = 921600,
2078 .uart_offset = 8 << 2,
2079 .reg_shift = 2,
2080 .first_offset = 0x10000,
2081 },
2082 [pbn_sgi_ioc3] = {
2083 .flags = FL_BASE0|FL_NOIRQ,
2084 .num_ports = 1,
2085 .base_baud = 458333,
2086 .uart_offset = 8,
2087 .reg_shift = 0,
2088 .first_offset = 0x20178,
2089 },
2090
1da177e4
LT		 2091 /*
2092 * Computone - uses IOMEM.
2093 */
2094 [pbn_computone_4] = {
2095 .flags = FL_BASE0,
2096 .num_ports = 4,
2097 .base_baud = 921600,
2098 .uart_offset = 0x40,
2099 .reg_shift = 2,
2100 .first_offset = 0x200,
2101 },
2102 [pbn_computone_6] = {
2103 .flags = FL_BASE0,
2104 .num_ports = 6,
2105 .base_baud = 921600,
2106 .uart_offset = 0x40,
2107 .reg_shift = 2,
2108 .first_offset = 0x200,
2109 },
2110 [pbn_computone_8] = {
2111 .flags = FL_BASE0,
2112 .num_ports = 8,
2113 .base_baud = 921600,
2114 .uart_offset = 0x40,
2115 .reg_shift = 2,
2116 .first_offset = 0x200,
2117 },
2118 [pbn_sbsxrsio] = {
2119 .flags = FL_BASE0,
2120 .num_ports = 8,
2121 .base_baud = 460800,
2122 .uart_offset = 256,
2123 .reg_shift = 4,
2124 },
2125 /*
2126 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
2127 * Only basic 16550A support.
2128 * XR17C15[24] are not tested, but they should work.
2129 */
2130 [pbn_exar_XR17C152] = {
2131 .flags = FL_BASE0,
2132 .num_ports = 2,
2133 .base_baud = 921600,
2134 .uart_offset = 0x200,
2135 },
2136 [pbn_exar_XR17C154] = {
2137 .flags = FL_BASE0,
2138 .num_ports = 4,
2139 .base_baud = 921600,
2140 .uart_offset = 0x200,
2141 },
2142 [pbn_exar_XR17C158] = {
2143 .flags = FL_BASE0,
2144 .num_ports = 8,
2145 .base_baud = 921600,
2146 .uart_offset = 0x200,
2147 },
aa798505
OJ		 2148 /*
2149 * PA Semi PWRficient PA6T-1682M on-chip UART
2150 */
2151 [pbn_pasemi_1682M] = {
2152 .flags = FL_BASE0,
2153 .num_ports = 1,
2154 .base_baud = 8333333,
2155 },
46a0fac9
SB		 2156 /*
2157 * National Instruments 843x
2158 */
2159 [pbn_ni8430_16] = {
2160 .flags = FL_BASE0,
2161 .num_ports = 16,
2162 .base_baud = 3686400,
2163 .uart_offset = 0x10,
2164 .first_offset = 0x800,
2165 },
2166 [pbn_ni8430_8] = {
2167 .flags = FL_BASE0,
2168 .num_ports = 8,
2169 .base_baud = 3686400,
2170 .uart_offset = 0x10,
2171 .first_offset = 0x800,
2172 },
2173 [pbn_ni8430_4] = {
2174 .flags = FL_BASE0,
2175 .num_ports = 4,
2176 .base_baud = 3686400,
2177 .uart_offset = 0x10,
2178 .first_offset = 0x800,
2179 },
2180 [pbn_ni8430_2] = {
2181 .flags = FL_BASE0,
2182 .num_ports = 2,
2183 .base_baud = 3686400,
2184 .uart_offset = 0x10,
2185 .first_offset = 0x800,
2186 },
1da177e4
LT		 2187};
2188
436bbd43 2189static const struct pci_device_id softmodem_blacklist[] = {
5756ee99 2190 { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */
436bbd43
CS		 2191};
2192
1da177e4
LT		 2193/*
2194 * Given a complete unknown PCI device, try to use some heuristics to
2195 * guess what the configuration might be, based on the pitiful PCI
2196 * serial specs. Returns 0 on success, 1 on failure.
2197 */
2198static int __devinit
1c7c1fe5 2199serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
1da177e4 2200{
436bbd43 2201 const struct pci_device_id *blacklist;
1da177e4 2202 int num_iomem, num_port, first_port = -1, i;
5756ee99 2203
1da177e4
LT		 2204 /*
2205 * If it is not a communications device or the programming
2206 * interface is greater than 6, give up.
2207 *
2208 * (Should we try to make guesses for multiport serial devices
5756ee99 2209 * later?)
1da177e4
LT		 2210 */
2211 if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
2212 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
2213 (dev->class & 0xff) > 6)
2214 return -ENODEV;
2215
436bbd43
CS		 2216 /*
2217 * Do not access blacklisted devices that are known not to
2218 * feature serial ports.
2219 */
2220 for (blacklist = softmodem_blacklist;
2221 blacklist < softmodem_blacklist + ARRAY_SIZE(softmodem_blacklist);
2222 blacklist++) {
2223 if (dev->vendor == blacklist->vendor &&
2224 dev->device == blacklist->device)
2225 return -ENODEV;
2226 }
2227
1da177e4
LT		 2228 num_iomem = num_port = 0;
2229 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
2230 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
2231 num_port++;
2232 if (first_port == -1)
2233 first_port = i;
2234 }
2235 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
2236 num_iomem++;
2237 }
2238
2239 /*
2240 * If there is 1 or 0 iomem regions, and exactly one port,
2241 * use it. We guess the number of ports based on the IO
2242 * region size.
2243 */
2244 if (num_iomem <= 1 && num_port == 1) {
2245 board->flags = first_port;
2246 board->num_ports = pci_resource_len(dev, first_port) / 8;
2247 return 0;
2248 }
2249
2250 /*
2251 * Now guess if we've got a board which indexes by BARs.
2252 * Each IO BAR should be 8 bytes, and they should follow
2253 * consecutively.
2254 */
2255 first_port = -1;
2256 num_port = 0;
2257 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
2258 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
2259 pci_resource_len(dev, i) == 8 &&
2260 (first_port == -1 || (first_port + num_port) == i)) {
2261 num_port++;
2262 if (first_port == -1)
2263 first_port = i;
2264 }
2265 }
2266
2267 if (num_port > 1) {
2268 board->flags = first_port | FL_BASE_BARS;
2269 board->num_ports = num_port;
2270 return 0;
2271 }
2272
2273 return -ENODEV;
2274}
2275
2276static inline int
975a1a7d
RK		 2277serial_pci_matches(const struct pciserial_board *board,
2278 const struct pciserial_board *guessed)
1da177e4
LT		 2279{
2280 return
2281 board->num_ports == guessed->num_ports &&
2282 board->base_baud == guessed->base_baud &&
2283 board->uart_offset == guessed->uart_offset &&
2284 board->reg_shift == guessed->reg_shift &&
2285 board->first_offset == guessed->first_offset;
2286}
2287
241fc436 2288struct serial_private *
975a1a7d 2289pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board)
1da177e4 2290{
72ce9a83 2291 struct uart_port serial_port;
1da177e4 2292 struct serial_private *priv;
1da177e4
LT		 2293 struct pci_serial_quirk *quirk;
2294 int rc, nr_ports, i;
2295
1da177e4
LT		 2296 nr_ports = board->num_ports;
2297
2298 /*
2299 * Find an init and setup quirks.
2300 */
2301 quirk = find_quirk(dev);
2302
2303 /*
2304 * Run the new-style initialization function.
2305 * The initialization function returns:
2306 * <0 - error
2307 * 0 - use board->num_ports
2308 * >0 - number of ports
2309 */
2310 if (quirk->init) {
2311 rc = quirk->init(dev);
241fc436
RK		 2312 if (rc < 0) {
2313 priv = ERR_PTR(rc);
2314 goto err_out;
2315 }
1da177e4
LT		 2316 if (rc)
2317 nr_ports = rc;
2318 }
2319
8f31bb39 2320 priv = kzalloc(sizeof(struct serial_private) +
1da177e4
LT		 2321 sizeof(unsigned int) * nr_ports,
2322 GFP_KERNEL);
2323 if (!priv) {
241fc436
RK		 2324 priv = ERR_PTR(-ENOMEM);
2325 goto err_deinit;
1da177e4
LT		 2326 }
2327
70db3d91 2328 priv->dev = dev;
1da177e4 2329 priv->quirk = quirk;
1da177e4 2330
72ce9a83
RK		 2331 memset(&serial_port, 0, sizeof(struct uart_port));
2332 serial_port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
2333 serial_port.uartclk = board->base_baud * 16;
2334 serial_port.irq = get_pci_irq(dev, board);
2335 serial_port.dev = &dev->dev;
2336
1da177e4 2337 for (i = 0; i < nr_ports; i++) {
70db3d91 2338 if (quirk->setup(priv, board, &serial_port, i))
1da177e4 2339 break;
72ce9a83 2340
1da177e4 2341#ifdef SERIAL_DEBUG_PCI
5756ee99 2342 printk(KERN_DEBUG "Setup PCI port: port %x, irq %d, type %d\n",
1da177e4
LT		 2343 serial_port.iobase, serial_port.irq, serial_port.iotype);
2344#endif
5756ee99 2345
1da177e4
LT		 2346 priv->line[i] = serial8250_register_port(&serial_port);
2347 if (priv->line[i] < 0) {
2348 printk(KERN_WARNING "Couldn't register serial port %s: %d\n", pci_name(dev), priv->line[i]);
2349 break;
2350 }
2351 }
1da177e4 2352 priv->nr = i;
241fc436 2353 return priv;
1da177e4 2354
5756ee99 2355err_deinit:
1da177e4
LT		 2356 if (quirk->exit)
2357 quirk->exit(dev);
5756ee99 2358err_out:
241fc436 2359 return priv;
1da177e4 2360}
241fc436 2361EXPORT_SYMBOL_GPL(pciserial_init_ports);
1da177e4 2362
241fc436 2363void pciserial_remove_ports(struct serial_private *priv)
1da177e4 2364{
056a8763
RK		 2365 struct pci_serial_quirk *quirk;
2366 int i;
1da177e4 2367
056a8763
RK		 2368 for (i = 0; i < priv->nr; i++)
2369 serial8250_unregister_port(priv->line[i]);
1da177e4 2370
056a8763
RK		 2371 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
2372 if (priv->remapped_bar[i])
2373 iounmap(priv->remapped_bar[i]);
2374 priv->remapped_bar[i] = NULL;
2375 }
1da177e4 2376
056a8763
RK		 2377 /*
2378 * Find the exit quirks.
2379 */
241fc436 2380 quirk = find_quirk(priv->dev);
056a8763 2381 if (quirk->exit)
241fc436
RK		 2382 quirk->exit(priv->dev);
2383
2384 kfree(priv);
2385}
2386EXPORT_SYMBOL_GPL(pciserial_remove_ports);
2387
2388void pciserial_suspend_ports(struct serial_private *priv)
2389{
2390 int i;
2391
2392 for (i = 0; i < priv->nr; i++)
2393 if (priv->line[i] >= 0)
2394 serial8250_suspend_port(priv->line[i]);
2395}
2396EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
2397
2398void pciserial_resume_ports(struct serial_private *priv)
2399{
2400 int i;
2401
2402 /*
2403 * Ensure that the board is correctly configured.
2404 */
2405 if (priv->quirk->init)
2406 priv->quirk->init(priv->dev);
2407
2408 for (i = 0; i < priv->nr; i++)
2409 if (priv->line[i] >= 0)
2410 serial8250_resume_port(priv->line[i]);
2411}
2412EXPORT_SYMBOL_GPL(pciserial_resume_ports);
2413
2414/*
2415 * Probe one serial board. Unfortunately, there is no rhyme nor reason
2416 * to the arrangement of serial ports on a PCI card.
2417 */
2418static int __devinit
2419pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
2420{
2421 struct serial_private *priv;
975a1a7d
RK		 2422 const struct pciserial_board *board;
2423 struct pciserial_board tmp;
241fc436
RK		 2424 int rc;
2425
2426 if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
2427 printk(KERN_ERR "pci_init_one: invalid driver_data: %ld\n",
2428 ent->driver_data);
2429 return -EINVAL;
2430 }
2431
2432 board = &pci_boards[ent->driver_data];
2433
2434 rc = pci_enable_device(dev);
2435 if (rc)
2436 return rc;
2437
2438 if (ent->driver_data == pbn_default) {
2439 /*
2440 * Use a copy of the pci_board entry for this;
2441 * avoid changing entries in the table.
2442 */
2443 memcpy(&tmp, board, sizeof(struct pciserial_board));
2444 board = &tmp;
2445
2446 /*
2447 * We matched one of our class entries. Try to
2448 * determine the parameters of this board.
2449 */
975a1a7d 2450 rc = serial_pci_guess_board(dev, &tmp);
241fc436
RK		 2451 if (rc)
2452 goto disable;
2453 } else {
2454 /*
2455 * We matched an explicit entry. If we are able to
2456 * detect this boards settings with our heuristic,
2457 * then we no longer need this entry.
2458 */
2459 memcpy(&tmp, &pci_boards[pbn_default],
2460 sizeof(struct pciserial_board));
2461 rc = serial_pci_guess_board(dev, &tmp);
2462 if (rc == 0 && serial_pci_matches(board, &tmp))
2463 moan_device("Redundant entry in serial pci_table.",
2464 dev);
2465 }
2466
2467 priv = pciserial_init_ports(dev, board);
2468 if (!IS_ERR(priv)) {
2469 pci_set_drvdata(dev, priv);
2470 return 0;
2471 }
2472
2473 rc = PTR_ERR(priv);
1da177e4 2474
241fc436 2475 disable:
056a8763 2476 pci_disable_device(dev);
241fc436
RK		 2477 return rc;
2478}
1da177e4 2479
241fc436
RK		 2480static void __devexit pciserial_remove_one(struct pci_dev *dev)
2481{
2482 struct serial_private *priv = pci_get_drvdata(dev);
2483
2484 pci_set_drvdata(dev, NULL);
2485
2486 pciserial_remove_ports(priv);
2487
2488 pci_disable_device(dev);
1da177e4
LT		 2489}
2490
1d5e7996 2491#ifdef CONFIG_PM
1da177e4
LT		 2492static int pciserial_suspend_one(struct pci_dev *dev, pm_message_t state)
2493{
2494 struct serial_private *priv = pci_get_drvdata(dev);
2495
241fc436
RK		 2496 if (priv)
2497 pciserial_suspend_ports(priv);
1da177e4 2498
1da177e4
LT		 2499 pci_save_state(dev);
2500 pci_set_power_state(dev, pci_choose_state(dev, state));
2501 return 0;
2502}
2503
2504static int pciserial_resume_one(struct pci_dev *dev)
2505{
ccb9d59e 2506 int err;
1da177e4
LT		 2507 struct serial_private *priv = pci_get_drvdata(dev);
2508
2509 pci_set_power_state(dev, PCI_D0);
2510 pci_restore_state(dev);
2511
2512 if (priv) {
1da177e4
LT		 2513 /*
2514 * The device may have been disabled. Re-enable it.
2515 */
ccb9d59e 2516 err = pci_enable_device(dev);
40836c48 2517 /* FIXME: We cannot simply error out here */
ccb9d59e 2518 if (err)
40836c48 2519 printk(KERN_ERR "pciserial: Unable to re-enable ports, trying to continue.\n");
241fc436 2520 pciserial_resume_ports(priv);
1da177e4
LT		 2521 }
2522 return 0;
2523}
1d5e7996 2524#endif
1da177e4
LT		 2525
2526static struct pci_device_id serial_pci_tbl[] = {
78d70d48
MB		 2527 /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */
2528 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620,
2529 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0,
2530 pbn_b2_8_921600 },
1da177e4
LT		 2531 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2532 PCI_SUBVENDOR_ID_CONNECT_TECH,
2533 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
2534 pbn_b1_8_1382400 },
2535 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2536 PCI_SUBVENDOR_ID_CONNECT_TECH,
2537 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
2538 pbn_b1_4_1382400 },
2539 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2540 PCI_SUBVENDOR_ID_CONNECT_TECH,
2541 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
2542 pbn_b1_2_1382400 },
2543 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2544 PCI_SUBVENDOR_ID_CONNECT_TECH,
2545 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
2546 pbn_b1_8_1382400 },
2547 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2548 PCI_SUBVENDOR_ID_CONNECT_TECH,
2549 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
2550 pbn_b1_4_1382400 },
2551 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2552 PCI_SUBVENDOR_ID_CONNECT_TECH,
2553 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
2554 pbn_b1_2_1382400 },
2555 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2556 PCI_SUBVENDOR_ID_CONNECT_TECH,
2557 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
2558 pbn_b1_8_921600 },
2559 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2560 PCI_SUBVENDOR_ID_CONNECT_TECH,
2561 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
2562 pbn_b1_8_921600 },
2563 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2564 PCI_SUBVENDOR_ID_CONNECT_TECH,
2565 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
2566 pbn_b1_4_921600 },
2567 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2568 PCI_SUBVENDOR_ID_CONNECT_TECH,
2569 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
2570 pbn_b1_4_921600 },
2571 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2572 PCI_SUBVENDOR_ID_CONNECT_TECH,
2573 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
2574 pbn_b1_2_921600 },
2575 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2576 PCI_SUBVENDOR_ID_CONNECT_TECH,
2577 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
2578 pbn_b1_8_921600 },
2579 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2580 PCI_SUBVENDOR_ID_CONNECT_TECH,
2581 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
2582 pbn_b1_8_921600 },
2583 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2584 PCI_SUBVENDOR_ID_CONNECT_TECH,
2585 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
2586 pbn_b1_4_921600 },
26e92861
GH		 2587 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2588 PCI_SUBVENDOR_ID_CONNECT_TECH,
2589 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
2590 pbn_b1_2_1250000 },
2591 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2592 PCI_SUBVENDOR_ID_CONNECT_TECH,
2593 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
2594 pbn_b0_2_1843200 },
2595 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2596 PCI_SUBVENDOR_ID_CONNECT_TECH,
2597 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
2598 pbn_b0_4_1843200 },
85d1494e
YY		 2599 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2600 PCI_VENDOR_ID_AFAVLAB,
2601 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
2602 pbn_b0_4_1152000 },
26e92861
GH		 2603 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2604 PCI_SUBVENDOR_ID_CONNECT_TECH,
2605 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232, 0, 0,
2606 pbn_b0_2_1843200_200 },
2607 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2608 PCI_SUBVENDOR_ID_CONNECT_TECH,
2609 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232, 0, 0,
2610 pbn_b0_4_1843200_200 },
2611 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2612 PCI_SUBVENDOR_ID_CONNECT_TECH,
2613 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232, 0, 0,
2614 pbn_b0_8_1843200_200 },
2615 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2616 PCI_SUBVENDOR_ID_CONNECT_TECH,
2617 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1, 0, 0,
2618 pbn_b0_2_1843200_200 },
2619 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2620 PCI_SUBVENDOR_ID_CONNECT_TECH,
2621 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2, 0, 0,
2622 pbn_b0_4_1843200_200 },
2623 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2624 PCI_SUBVENDOR_ID_CONNECT_TECH,
2625 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4, 0, 0,
2626 pbn_b0_8_1843200_200 },
2627 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2628 PCI_SUBVENDOR_ID_CONNECT_TECH,
2629 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2, 0, 0,
2630 pbn_b0_2_1843200_200 },
2631 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2632 PCI_SUBVENDOR_ID_CONNECT_TECH,
2633 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4, 0, 0,
2634 pbn_b0_4_1843200_200 },
2635 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2636 PCI_SUBVENDOR_ID_CONNECT_TECH,
2637 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8, 0, 0,
2638 pbn_b0_8_1843200_200 },
2639 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2640 PCI_SUBVENDOR_ID_CONNECT_TECH,
2641 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485, 0, 0,
2642 pbn_b0_2_1843200_200 },
2643 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2644 PCI_SUBVENDOR_ID_CONNECT_TECH,
2645 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485, 0, 0,
2646 pbn_b0_4_1843200_200 },
2647 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2648 PCI_SUBVENDOR_ID_CONNECT_TECH,
2649 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485, 0, 0,
2650 pbn_b0_8_1843200_200 },
1da177e4
LT		 2651
2652 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
5756ee99 2653 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 2654 pbn_b2_bt_1_115200 },
2655 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
5756ee99 2656 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 2657 pbn_b2_bt_2_115200 },
2658 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
5756ee99 2659 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 2660 pbn_b2_bt_4_115200 },
2661 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
5756ee99 2662 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 2663 pbn_b2_bt_2_115200 },
2664 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
5756ee99 2665 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 2666 pbn_b2_bt_4_115200 },
2667 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
5756ee99 2668 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4 2669 pbn_b2_8_115200 },
e65f0f82
FL		 2670 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803,
2671 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2672 pbn_b2_8_460800 },
1da177e4
LT		 2673 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
2674 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2675 pbn_b2_8_115200 },
2676
2677 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
2678 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2679 pbn_b2_bt_2_115200 },
2680 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
2681 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2682 pbn_b2_bt_2_921600 },
2683 /*
2684 * VScom SPCOM800, from sl@s.pl
2685 */
5756ee99
AC		 2686 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
2687 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 2688 pbn_b2_8_921600 },
2689 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
5756ee99 2690 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4 2691 pbn_b2_4_921600 },
b76c5a07
CB		 2692 /* Unknown card - subdevice 0x1584 */
2693 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2694 PCI_VENDOR_ID_PLX,
2695 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0,
2696 pbn_b0_4_115200 },
1da177e4
LT		 2697 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2698 PCI_SUBVENDOR_ID_KEYSPAN,
2699 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
2700 pbn_panacom },
2701 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
2702 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2703 pbn_panacom4 },
2704 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
2705 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2706 pbn_panacom2 },
a9cccd34
MF		 2707 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
2708 PCI_VENDOR_ID_ESDGMBH,
2709 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
2710 pbn_b2_4_115200 },
1da177e4
LT		 2711 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2712 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
5756ee99 2713 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
1da177e4
LT		 2714 pbn_b2_4_460800 },
2715 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2716 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
5756ee99 2717 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
1da177e4
LT		 2718 pbn_b2_8_460800 },
2719 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2720 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
5756ee99 2721 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
1da177e4
LT		 2722 pbn_b2_16_460800 },
2723 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2724 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
5756ee99 2725 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
1da177e4
LT		 2726 pbn_b2_16_460800 },
2727 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2728 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
5756ee99 2729 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
1da177e4
LT		 2730 pbn_b2_4_460800 },
2731 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2732 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
5756ee99 2733 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
1da177e4 2734 pbn_b2_8_460800 },
add7b58e
BH		 2735 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2736 PCI_SUBVENDOR_ID_EXSYS,
2737 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
2738 pbn_exsys_4055 },
1da177e4
LT		 2739 /*
2740 * Megawolf Romulus PCI Serial Card, from Mike Hudson
2741 * (Exoray@isys.ca)
2742 */
2743 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
2744 0x10b5, 0x106a, 0, 0,
2745 pbn_plx_romulus },
2746 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
2747 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2748 pbn_b1_4_115200 },
2749 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
2750 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2751 pbn_b1_2_115200 },
2752 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
2753 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2754 pbn_b1_8_115200 },
2755 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
2756 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2757 pbn_b1_8_115200 },
2758 { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
5756ee99
AC		 2759 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4,
2760 0, 0,
1da177e4 2761 pbn_b0_4_921600 },
fbc0dc0d 2762 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
5756ee99
AC		 2763 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL,
2764 0, 0,
fbc0dc0d 2765 pbn_b0_4_1152000 },
db1de159
DR		 2766
2767 /*
2768 * The below card is a little controversial since it is the
2769 * subject of a PCI vendor/device ID clash. (See
2770 * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
2771 * For now just used the hex ID 0x950a.
2772 */
39aced68
NV		 2773 { PCI_VENDOR_ID_OXSEMI, 0x950a,
2774 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_SERIAL, 0, 0,
2775 pbn_b0_2_115200 },
db1de159
DR		 2776 { PCI_VENDOR_ID_OXSEMI, 0x950a,
2777 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2778 pbn_b0_2_1130000 },
70fd8fde
AP		 2779 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950,
2780 PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0,
2781 pbn_b0_1_921600 },
1da177e4
LT		 2782 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2783 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2784 pbn_b0_4_115200 },
2785 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
2786 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2787 pbn_b0_bt_2_921600 },
2788
7106b4e3
LH		 2789 /*
2790 * Oxford Semiconductor Inc. Tornado PCI express device range.
2791 */
2792 { PCI_VENDOR_ID_OXSEMI, 0xc101, /* OXPCIe952 1 Legacy UART */
2793 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2794 pbn_b0_1_4000000 },
2795 { PCI_VENDOR_ID_OXSEMI, 0xc105, /* OXPCIe952 1 Legacy UART */
2796 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2797 pbn_b0_1_4000000 },
2798 { PCI_VENDOR_ID_OXSEMI, 0xc11b, /* OXPCIe952 1 Native UART */
2799 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2800 pbn_oxsemi_1_4000000 },
2801 { PCI_VENDOR_ID_OXSEMI, 0xc11f, /* OXPCIe952 1 Native UART */
2802 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2803 pbn_oxsemi_1_4000000 },
2804 { PCI_VENDOR_ID_OXSEMI, 0xc120, /* OXPCIe952 1 Legacy UART */
2805 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2806 pbn_b0_1_4000000 },
2807 { PCI_VENDOR_ID_OXSEMI, 0xc124, /* OXPCIe952 1 Legacy UART */
2808 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2809 pbn_b0_1_4000000 },
2810 { PCI_VENDOR_ID_OXSEMI, 0xc138, /* OXPCIe952 1 Native UART */
2811 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2812 pbn_oxsemi_1_4000000 },
2813 { PCI_VENDOR_ID_OXSEMI, 0xc13d, /* OXPCIe952 1 Native UART */
2814 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2815 pbn_oxsemi_1_4000000 },
2816 { PCI_VENDOR_ID_OXSEMI, 0xc140, /* OXPCIe952 1 Legacy UART */
2817 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2818 pbn_b0_1_4000000 },
2819 { PCI_VENDOR_ID_OXSEMI, 0xc141, /* OXPCIe952 1 Legacy UART */
2820 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2821 pbn_b0_1_4000000 },
2822 { PCI_VENDOR_ID_OXSEMI, 0xc144, /* OXPCIe952 1 Legacy UART */
2823 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2824 pbn_b0_1_4000000 },
2825 { PCI_VENDOR_ID_OXSEMI, 0xc145, /* OXPCIe952 1 Legacy UART */
2826 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2827 pbn_b0_1_4000000 },
2828 { PCI_VENDOR_ID_OXSEMI, 0xc158, /* OXPCIe952 2 Native UART */
2829 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2830 pbn_oxsemi_2_4000000 },
2831 { PCI_VENDOR_ID_OXSEMI, 0xc15d, /* OXPCIe952 2 Native UART */
2832 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2833 pbn_oxsemi_2_4000000 },
2834 { PCI_VENDOR_ID_OXSEMI, 0xc208, /* OXPCIe954 4 Native UART */
2835 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2836 pbn_oxsemi_4_4000000 },
2837 { PCI_VENDOR_ID_OXSEMI, 0xc20d, /* OXPCIe954 4 Native UART */
2838 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2839 pbn_oxsemi_4_4000000 },
2840 { PCI_VENDOR_ID_OXSEMI, 0xc308, /* OXPCIe958 8 Native UART */
2841 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2842 pbn_oxsemi_8_4000000 },
2843 { PCI_VENDOR_ID_OXSEMI, 0xc30d, /* OXPCIe958 8 Native UART */
2844 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2845 pbn_oxsemi_8_4000000 },
2846 { PCI_VENDOR_ID_OXSEMI, 0xc40b, /* OXPCIe200 1 Native UART */
2847 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2848 pbn_oxsemi_1_4000000 },
2849 { PCI_VENDOR_ID_OXSEMI, 0xc40f, /* OXPCIe200 1 Native UART */
2850 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2851 pbn_oxsemi_1_4000000 },
2852 { PCI_VENDOR_ID_OXSEMI, 0xc41b, /* OXPCIe200 1 Native UART */
2853 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2854 pbn_oxsemi_1_4000000 },
2855 { PCI_VENDOR_ID_OXSEMI, 0xc41f, /* OXPCIe200 1 Native UART */
2856 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2857 pbn_oxsemi_1_4000000 },
2858 { PCI_VENDOR_ID_OXSEMI, 0xc42b, /* OXPCIe200 1 Native UART */
2859 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2860 pbn_oxsemi_1_4000000 },
2861 { PCI_VENDOR_ID_OXSEMI, 0xc42f, /* OXPCIe200 1 Native UART */
2862 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2863 pbn_oxsemi_1_4000000 },
2864 { PCI_VENDOR_ID_OXSEMI, 0xc43b, /* OXPCIe200 1 Native UART */
2865 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2866 pbn_oxsemi_1_4000000 },
2867 { PCI_VENDOR_ID_OXSEMI, 0xc43f, /* OXPCIe200 1 Native UART */
2868 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2869 pbn_oxsemi_1_4000000 },
2870 { PCI_VENDOR_ID_OXSEMI, 0xc44b, /* OXPCIe200 1 Native UART */
2871 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2872 pbn_oxsemi_1_4000000 },
2873 { PCI_VENDOR_ID_OXSEMI, 0xc44f, /* OXPCIe200 1 Native UART */
2874 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2875 pbn_oxsemi_1_4000000 },
2876 { PCI_VENDOR_ID_OXSEMI, 0xc45b, /* OXPCIe200 1 Native UART */
2877 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2878 pbn_oxsemi_1_4000000 },
2879 { PCI_VENDOR_ID_OXSEMI, 0xc45f, /* OXPCIe200 1 Native UART */
2880 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2881 pbn_oxsemi_1_4000000 },
2882 { PCI_VENDOR_ID_OXSEMI, 0xc46b, /* OXPCIe200 1 Native UART */
2883 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2884 pbn_oxsemi_1_4000000 },
2885 { PCI_VENDOR_ID_OXSEMI, 0xc46f, /* OXPCIe200 1 Native UART */
2886 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2887 pbn_oxsemi_1_4000000 },
2888 { PCI_VENDOR_ID_OXSEMI, 0xc47b, /* OXPCIe200 1 Native UART */
2889 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2890 pbn_oxsemi_1_4000000 },
2891 { PCI_VENDOR_ID_OXSEMI, 0xc47f, /* OXPCIe200 1 Native UART */
2892 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2893 pbn_oxsemi_1_4000000 },
2894 { PCI_VENDOR_ID_OXSEMI, 0xc48b, /* OXPCIe200 1 Native UART */
2895 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2896 pbn_oxsemi_1_4000000 },
2897 { PCI_VENDOR_ID_OXSEMI, 0xc48f, /* OXPCIe200 1 Native UART */
2898 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2899 pbn_oxsemi_1_4000000 },
2900 { PCI_VENDOR_ID_OXSEMI, 0xc49b, /* OXPCIe200 1 Native UART */
2901 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2902 pbn_oxsemi_1_4000000 },
2903 { PCI_VENDOR_ID_OXSEMI, 0xc49f, /* OXPCIe200 1 Native UART */
2904 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2905 pbn_oxsemi_1_4000000 },
2906 { PCI_VENDOR_ID_OXSEMI, 0xc4ab, /* OXPCIe200 1 Native UART */
2907 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2908 pbn_oxsemi_1_4000000 },
2909 { PCI_VENDOR_ID_OXSEMI, 0xc4af, /* OXPCIe200 1 Native UART */
2910 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2911 pbn_oxsemi_1_4000000 },
2912 { PCI_VENDOR_ID_OXSEMI, 0xc4bb, /* OXPCIe200 1 Native UART */
2913 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2914 pbn_oxsemi_1_4000000 },
2915 { PCI_VENDOR_ID_OXSEMI, 0xc4bf, /* OXPCIe200 1 Native UART */
2916 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2917 pbn_oxsemi_1_4000000 },
2918 { PCI_VENDOR_ID_OXSEMI, 0xc4cb, /* OXPCIe200 1 Native UART */
2919 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2920 pbn_oxsemi_1_4000000 },
2921 { PCI_VENDOR_ID_OXSEMI, 0xc4cf, /* OXPCIe200 1 Native UART */
2922 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2923 pbn_oxsemi_1_4000000 },
b80de369
LH		 2924 /*
2925 * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado
2926 */
2927 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */
2928 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0,
2929 pbn_oxsemi_1_4000000 },
2930 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */
2931 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0,
2932 pbn_oxsemi_2_4000000 },
2933 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */
2934 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0,
2935 pbn_oxsemi_4_4000000 },
2936 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */
2937 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0,
2938 pbn_oxsemi_8_4000000 },
1da177e4
LT		 2939 /*
2940 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
2941 * from skokodyn@yahoo.com
2942 */
2943 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
2944 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
2945 pbn_sbsxrsio },
2946 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
2947 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
2948 pbn_sbsxrsio },
2949 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
2950 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
2951 pbn_sbsxrsio },
2952 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
2953 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
2954 pbn_sbsxrsio },
2955
2956 /*
2957 * Digitan DS560-558, from jimd@esoft.com
2958 */
2959 { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
5756ee99 2960 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 2961 pbn_b1_1_115200 },
2962
2963 /*
2964 * Titan Electronic cards
2965 * The 400L and 800L have a custom setup quirk.
2966 */
2967 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
5756ee99 2968 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 2969 pbn_b0_1_921600 },
2970 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
5756ee99 2971 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 2972 pbn_b0_2_921600 },
2973 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
5756ee99 2974 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 2975 pbn_b0_4_921600 },
2976 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
5756ee99 2977 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 2978 pbn_b0_4_921600 },
2979 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
2980 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2981 pbn_b1_1_921600 },
2982 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
2983 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2984 pbn_b1_bt_2_921600 },
2985 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
2986 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2987 pbn_b0_bt_4_921600 },
2988 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
2989 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2990 pbn_b0_bt_8_921600 },
2991
2992 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
2993 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2994 pbn_b2_1_460800 },
2995 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
2996 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2997 pbn_b2_1_460800 },
2998 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
2999 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3000 pbn_b2_1_460800 },
3001 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
3002 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3003 pbn_b2_bt_2_921600 },
3004 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
3005 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3006 pbn_b2_bt_2_921600 },
3007 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
3008 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3009 pbn_b2_bt_2_921600 },
3010 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
3011 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3012 pbn_b2_bt_4_921600 },
3013 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
3014 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3015 pbn_b2_bt_4_921600 },
3016 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
3017 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3018 pbn_b2_bt_4_921600 },
3019 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
3020 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3021 pbn_b0_1_921600 },
3022 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
3023 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3024 pbn_b0_1_921600 },
3025 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
3026 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3027 pbn_b0_1_921600 },
3028 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
3029 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3030 pbn_b0_bt_2_921600 },
3031 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
3032 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3033 pbn_b0_bt_2_921600 },
3034 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
3035 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3036 pbn_b0_bt_2_921600 },
3037 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
3038 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3039 pbn_b0_bt_4_921600 },
3040 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
3041 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3042 pbn_b0_bt_4_921600 },
3043 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
3044 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3045 pbn_b0_bt_4_921600 },
3ec9c594
AP		 3046 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
3047 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3048 pbn_b0_bt_8_921600 },
3049 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
3050 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3051 pbn_b0_bt_8_921600 },
3052 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
3053 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3054 pbn_b0_bt_8_921600 },
1da177e4
LT		 3055
3056 /*
3057 * Computone devices submitted by Doug McNash dmcnash@computone.com
3058 */
3059 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
3060 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
3061 0, 0, pbn_computone_4 },
3062 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
3063 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
3064 0, 0, pbn_computone_8 },
3065 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
3066 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
3067 0, 0, pbn_computone_6 },
3068
3069 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
3070 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3071 pbn_oxsemi },
3072 { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
3073 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
3074 pbn_b0_bt_1_921600 },
3075
3076 /*
3077 * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
3078 */
3079 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
3080 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3081 pbn_b0_bt_8_115200 },
3082 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
3083 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3084 pbn_b0_bt_8_115200 },
3085
3086 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
3087 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3088 pbn_b0_bt_2_115200 },
3089 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
3090 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3091 pbn_b0_bt_2_115200 },
3092 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
3093 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3094 pbn_b0_bt_2_115200 },
3095 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
3096 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3097 pbn_b0_bt_4_460800 },
3098 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
3099 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3100 pbn_b0_bt_4_460800 },
3101 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
3102 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3103 pbn_b0_bt_2_460800 },
3104 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
3105 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3106 pbn_b0_bt_2_460800 },
3107 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
3108 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3109 pbn_b0_bt_2_460800 },
3110 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
3111 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3112 pbn_b0_bt_1_115200 },
3113 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
3114 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3115 pbn_b0_bt_1_460800 },
3116
1fb8cacc
RK		 3117 /*
3118 * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408).
3119 * Cards are identified by their subsystem vendor IDs, which
3120 * (in hex) match the model number.
3121 *
3122 * Note that JC140x are RS422/485 cards which require ox950
3123 * ACR = 0x10, and as such are not currently fully supported.
3124 */
3125 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3126 0x1204, 0x0004, 0, 0,
3127 pbn_b0_4_921600 },
3128 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3129 0x1208, 0x0004, 0, 0,
3130 pbn_b0_4_921600 },
3131/* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3132 0x1402, 0x0002, 0, 0,
3133 pbn_b0_2_921600 }, */
3134/* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3135 0x1404, 0x0004, 0, 0,
3136 pbn_b0_4_921600 }, */
3137 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1,
3138 0x1208, 0x0004, 0, 0,
3139 pbn_b0_4_921600 },
3140
1da177e4
LT		 3141 /*
3142 * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
3143 */
3144 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
3145 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3146 pbn_b1_1_1382400 },
3147
3148 /*
3149 * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
3150 */
3151 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
3152 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3153 pbn_b1_1_1382400 },
3154
3155 /*
3156 * RAStel 2 port modem, gerg@moreton.com.au
3157 */
3158 { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
3159 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3160 pbn_b2_bt_2_115200 },
3161
3162 /*
3163 * EKF addition for i960 Boards form EKF with serial port
3164 */
3165 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
3166 0xE4BF, PCI_ANY_ID, 0, 0,
3167 pbn_intel_i960 },
3168
3169 /*
3170 * Xircom Cardbus/Ethernet combos
3171 */
3172 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
3173 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3174 pbn_b0_1_115200 },
3175 /*
3176 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
3177 */
3178 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
3179 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3180 pbn_b0_1_115200 },
3181
3182 /*
3183 * Untested PCI modems, sent in from various folks...
3184 */
3185
3186 /*
3187 * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
3188 */
3189 { PCI_VENDOR_ID_ROCKWELL, 0x1004,
3190 0x1048, 0x1500, 0, 0,
3191 pbn_b1_1_115200 },
3192
3193 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
3194 0xFF00, 0, 0, 0,
3195 pbn_sgi_ioc3 },
3196
3197 /*
3198 * HP Diva card
3199 */
3200 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
3201 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
3202 pbn_b1_1_115200 },
3203 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
3204 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3205 pbn_b0_5_115200 },
3206 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
3207 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3208 pbn_b2_1_115200 },
3209
d9004eb4
ABL		 3210 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
3211 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3212 pbn_b3_2_115200 },
1da177e4
LT		 3213 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
3214 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3215 pbn_b3_4_115200 },
3216 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
3217 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3218 pbn_b3_8_115200 },
3219
3220 /*
3221 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
3222 */
3223 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3224 PCI_ANY_ID, PCI_ANY_ID,
3225 0,
3226 0, pbn_exar_XR17C152 },
3227 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3228 PCI_ANY_ID, PCI_ANY_ID,
3229 0,
3230 0, pbn_exar_XR17C154 },
3231 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3232 PCI_ANY_ID, PCI_ANY_ID,
3233 0,
3234 0, pbn_exar_XR17C158 },
3235
3236 /*
3237 * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
3238 */
3239 { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
3240 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3241 pbn_b0_1_115200 },
84f8c6fc
NV		 3242 /*
3243 * ITE
3244 */
3245 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
3246 PCI_ANY_ID, PCI_ANY_ID,
3247 0, 0,
3248 pbn_b1_bt_1_115200 },
1da177e4 3249
737c1756
PH		 3250 /*
3251 * IntaShield IS-200
3252 */
3253 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
3254 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0811 */
3255 pbn_b2_2_115200 },
4b6f6ce9
IGP		 3256 /*
3257 * IntaShield IS-400
3258 */
3259 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400,
3260 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0dc0 */
3261 pbn_b2_4_115200 },
48212008
TH		 3262 /*
3263 * Perle PCI-RAS cards
3264 */
3265 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
3266 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4,
3267 0, 0, pbn_b2_4_921600 },
3268 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
3269 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8,
3270 0, 0, pbn_b2_8_921600 },
bf0df636
AC		 3271
3272 /*
3273 * Mainpine series cards: Fairly standard layout but fools
3274 * parts of the autodetect in some cases and uses otherwise
3275 * unmatched communications subclasses in the PCI Express case
3276 */
3277
3278 { /* RockForceDUO */
3279 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3280 PCI_VENDOR_ID_MAINPINE, 0x0200,
3281 0, 0, pbn_b0_2_115200 },
3282 { /* RockForceQUATRO */
3283 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3284 PCI_VENDOR_ID_MAINPINE, 0x0300,
3285 0, 0, pbn_b0_4_115200 },
3286 { /* RockForceDUO+ */
3287 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3288 PCI_VENDOR_ID_MAINPINE, 0x0400,
3289 0, 0, pbn_b0_2_115200 },
3290 { /* RockForceQUATRO+ */
3291 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3292 PCI_VENDOR_ID_MAINPINE, 0x0500,
3293 0, 0, pbn_b0_4_115200 },
3294 { /* RockForce+ */
3295 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3296 PCI_VENDOR_ID_MAINPINE, 0x0600,
3297 0, 0, pbn_b0_2_115200 },
3298 { /* RockForce+ */
3299 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3300 PCI_VENDOR_ID_MAINPINE, 0x0700,
3301 0, 0, pbn_b0_4_115200 },
3302 { /* RockForceOCTO+ */
3303 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3304 PCI_VENDOR_ID_MAINPINE, 0x0800,
3305 0, 0, pbn_b0_8_115200 },
3306 { /* RockForceDUO+ */
3307 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3308 PCI_VENDOR_ID_MAINPINE, 0x0C00,
3309 0, 0, pbn_b0_2_115200 },
3310 { /* RockForceQUARTRO+ */
3311 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3312 PCI_VENDOR_ID_MAINPINE, 0x0D00,
3313 0, 0, pbn_b0_4_115200 },
3314 { /* RockForceOCTO+ */
3315 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3316 PCI_VENDOR_ID_MAINPINE, 0x1D00,
3317 0, 0, pbn_b0_8_115200 },
3318 { /* RockForceD1 */
3319 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3320 PCI_VENDOR_ID_MAINPINE, 0x2000,
3321 0, 0, pbn_b0_1_115200 },
3322 { /* RockForceF1 */
3323 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3324 PCI_VENDOR_ID_MAINPINE, 0x2100,
3325 0, 0, pbn_b0_1_115200 },
3326 { /* RockForceD2 */
3327 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3328 PCI_VENDOR_ID_MAINPINE, 0x2200,
3329 0, 0, pbn_b0_2_115200 },
3330 { /* RockForceF2 */
3331 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3332 PCI_VENDOR_ID_MAINPINE, 0x2300,
3333 0, 0, pbn_b0_2_115200 },
3334 { /* RockForceD4 */
3335 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3336 PCI_VENDOR_ID_MAINPINE, 0x2400,
3337 0, 0, pbn_b0_4_115200 },
3338 { /* RockForceF4 */
3339 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3340 PCI_VENDOR_ID_MAINPINE, 0x2500,
3341 0, 0, pbn_b0_4_115200 },
3342 { /* RockForceD8 */
3343 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3344 PCI_VENDOR_ID_MAINPINE, 0x2600,
3345 0, 0, pbn_b0_8_115200 },
3346 { /* RockForceF8 */
3347 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3348 PCI_VENDOR_ID_MAINPINE, 0x2700,
3349 0, 0, pbn_b0_8_115200 },
3350 { /* IQ Express D1 */
3351 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3352 PCI_VENDOR_ID_MAINPINE, 0x3000,
3353 0, 0, pbn_b0_1_115200 },
3354 { /* IQ Express F1 */
3355 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3356 PCI_VENDOR_ID_MAINPINE, 0x3100,
3357 0, 0, pbn_b0_1_115200 },
3358 { /* IQ Express D2 */
3359 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3360 PCI_VENDOR_ID_MAINPINE, 0x3200,
3361 0, 0, pbn_b0_2_115200 },
3362 { /* IQ Express F2 */
3363 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3364 PCI_VENDOR_ID_MAINPINE, 0x3300,
3365 0, 0, pbn_b0_2_115200 },
3366 { /* IQ Express D4 */
3367 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3368 PCI_VENDOR_ID_MAINPINE, 0x3400,
3369 0, 0, pbn_b0_4_115200 },
3370 { /* IQ Express F4 */
3371 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3372 PCI_VENDOR_ID_MAINPINE, 0x3500,
3373 0, 0, pbn_b0_4_115200 },
3374 { /* IQ Express D8 */
3375 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3376 PCI_VENDOR_ID_MAINPINE, 0x3C00,
3377 0, 0, pbn_b0_8_115200 },
3378 { /* IQ Express F8 */
3379 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3380 PCI_VENDOR_ID_MAINPINE, 0x3D00,
3381 0, 0, pbn_b0_8_115200 },
3382
3383
aa798505
OJ		 3384 /*
3385 * PA Semi PA6T-1682M on-chip UART
3386 */
3387 { PCI_VENDOR_ID_PASEMI, 0xa004,
3388 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3389 pbn_pasemi_1682M },
3390
46a0fac9
SB		 3391 /*
3392 * National Instruments
3393 */
04bf7e74
WP		 3394 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216,
3395 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3396 pbn_b1_16_115200 },
3397 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328,
3398 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3399 pbn_b1_8_115200 },
3400 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324,
3401 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3402 pbn_b1_bt_4_115200 },
3403 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322,
3404 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3405 pbn_b1_bt_2_115200 },
3406 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I,
3407 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3408 pbn_b1_bt_4_115200 },
3409 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I,
3410 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3411 pbn_b1_bt_2_115200 },
3412 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216,
3413 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3414 pbn_b1_16_115200 },
3415 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328,
3416 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3417 pbn_b1_8_115200 },
3418 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324,
3419 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3420 pbn_b1_bt_4_115200 },
3421 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322,
3422 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3423 pbn_b1_bt_2_115200 },
3424 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324,
3425 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3426 pbn_b1_bt_4_115200 },
3427 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322,
3428 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3429 pbn_b1_bt_2_115200 },
46a0fac9
SB		 3430 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322,
3431 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3432 pbn_ni8430_2 },
3433 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322,
3434 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3435 pbn_ni8430_2 },
3436 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324,
3437 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3438 pbn_ni8430_4 },
3439 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324,
3440 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3441 pbn_ni8430_4 },
3442 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328,
3443 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3444 pbn_ni8430_8 },
3445 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328,
3446 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3447 pbn_ni8430_8 },
3448 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216,
3449 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3450 pbn_ni8430_16 },
3451 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216,
3452 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3453 pbn_ni8430_16 },
3454 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322,
3455 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3456 pbn_ni8430_2 },
3457 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322,
3458 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3459 pbn_ni8430_2 },
3460 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324,
3461 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3462 pbn_ni8430_4 },
3463 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324,
3464 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3465 pbn_ni8430_4 },
3466
02c9b5cf
KJ		 3467 /*
3468 * ADDI-DATA GmbH communication cards <info@addi-data.com>
3469 */
3470 { PCI_VENDOR_ID_ADDIDATA,
3471 PCI_DEVICE_ID_ADDIDATA_APCI7500,
3472 PCI_ANY_ID,
3473 PCI_ANY_ID,
3474 0,
3475 0,
3476 pbn_b0_4_115200 },
3477
3478 { PCI_VENDOR_ID_ADDIDATA,
3479 PCI_DEVICE_ID_ADDIDATA_APCI7420,
3480 PCI_ANY_ID,
3481 PCI_ANY_ID,
3482 0,
3483 0,
3484 pbn_b0_2_115200 },
3485
3486 { PCI_VENDOR_ID_ADDIDATA,
3487 PCI_DEVICE_ID_ADDIDATA_APCI7300,
3488 PCI_ANY_ID,
3489 PCI_ANY_ID,
3490 0,
3491 0,
3492 pbn_b0_1_115200 },
3493
3494 { PCI_VENDOR_ID_ADDIDATA_OLD,
3495 PCI_DEVICE_ID_ADDIDATA_APCI7800,
3496 PCI_ANY_ID,
3497 PCI_ANY_ID,
3498 0,
3499 0,
3500 pbn_b1_8_115200 },
3501
3502 { PCI_VENDOR_ID_ADDIDATA,
3503 PCI_DEVICE_ID_ADDIDATA_APCI7500_2,
3504 PCI_ANY_ID,
3505 PCI_ANY_ID,
3506 0,
3507 0,
3508 pbn_b0_4_115200 },
3509
3510 { PCI_VENDOR_ID_ADDIDATA,
3511 PCI_DEVICE_ID_ADDIDATA_APCI7420_2,
3512 PCI_ANY_ID,
3513 PCI_ANY_ID,
3514 0,
3515 0,
3516 pbn_b0_2_115200 },
3517
3518 { PCI_VENDOR_ID_ADDIDATA,
3519 PCI_DEVICE_ID_ADDIDATA_APCI7300_2,
3520 PCI_ANY_ID,
3521 PCI_ANY_ID,
3522 0,
3523 0,
3524 pbn_b0_1_115200 },
3525
3526 { PCI_VENDOR_ID_ADDIDATA,
3527 PCI_DEVICE_ID_ADDIDATA_APCI7500_3,
3528 PCI_ANY_ID,
3529 PCI_ANY_ID,
3530 0,
3531 0,
3532 pbn_b0_4_115200 },
3533
3534 { PCI_VENDOR_ID_ADDIDATA,
3535 PCI_DEVICE_ID_ADDIDATA_APCI7420_3,
3536 PCI_ANY_ID,
3537 PCI_ANY_ID,
3538 0,
3539 0,
3540 pbn_b0_2_115200 },
3541
3542 { PCI_VENDOR_ID_ADDIDATA,
3543 PCI_DEVICE_ID_ADDIDATA_APCI7300_3,
3544 PCI_ANY_ID,
3545 PCI_ANY_ID,
3546 0,
3547 0,
3548 pbn_b0_1_115200 },
3549
3550 { PCI_VENDOR_ID_ADDIDATA,
3551 PCI_DEVICE_ID_ADDIDATA_APCI7800_3,
3552 PCI_ANY_ID,
3553 PCI_ANY_ID,
3554 0,
3555 0,
3556 pbn_b0_8_115200 },
3557
25cf9bc1
JS		 3558 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835,
3559 PCI_VENDOR_ID_IBM, 0x0299,
3560 0, 0, pbn_b0_bt_2_115200 },
3561
1da177e4
LT		 3562 /*
3563 * These entries match devices with class COMMUNICATION_SERIAL,
3564 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
3565 */
3566 { PCI_ANY_ID, PCI_ANY_ID,
3567 PCI_ANY_ID, PCI_ANY_ID,
3568 PCI_CLASS_COMMUNICATION_SERIAL << 8,
3569 0xffff00, pbn_default },
3570 { PCI_ANY_ID, PCI_ANY_ID,
3571 PCI_ANY_ID, PCI_ANY_ID,
3572 PCI_CLASS_COMMUNICATION_MODEM << 8,
3573 0xffff00, pbn_default },
3574 { PCI_ANY_ID, PCI_ANY_ID,
3575 PCI_ANY_ID, PCI_ANY_ID,
3576 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
3577 0xffff00, pbn_default },
3578 { 0, }
3579};
3580
3581static struct pci_driver serial_pci_driver = {
3582 .name = "serial",
3583 .probe = pciserial_init_one,
3584 .remove = __devexit_p(pciserial_remove_one),
1d5e7996 3585#ifdef CONFIG_PM
1da177e4
LT		 3586 .suspend = pciserial_suspend_one,
3587 .resume = pciserial_resume_one,
1d5e7996 3588#endif
1da177e4
LT		 3589 .id_table = serial_pci_tbl,
3590};
3591
3592static int __init serial8250_pci_init(void)
3593{
3594 return pci_register_driver(&serial_pci_driver);
3595}
3596
3597static void __exit serial8250_pci_exit(void)
3598{
3599 pci_unregister_driver(&serial_pci_driver);
3600}
3601
3602module_init(serial8250_pci_init);
3603module_exit(serial8250_pci_exit);
3604
3605MODULE_LICENSE("GPL");
3606MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
3607MODULE_DEVICE_TABLE(pci, serial_pci_tbl);
Linux 6.x block layer and io_uring tree(s)