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scsi: qla2xxx: Complain if waiting for pending commands times out
[linux-2.6-block.git] / drivers / scsi / qla2xxx / qla_os.c
CommitLineData
1da177e4 1/*
fa90c54f 2 * QLogic Fibre Channel HBA Driver
bd21eaf9 3 * Copyright (c) 2003-2014 QLogic Corporation
1da177e4 4 *
fa90c54f 5 * See LICENSE.qla2xxx for copyright and licensing details.
1da177e4
LT		 6 */
7#include "qla_def.h"
8
9#include <linux/moduleparam.h>
10#include <linux/vmalloc.h>
1da177e4 11#include <linux/delay.h>
39a11240 12#include <linux/kthread.h>
e1e82b6f 13#include <linux/mutex.h>
3420d36c 14#include <linux/kobject.h>
5a0e3ad6 15#include <linux/slab.h>
5601236b 16#include <linux/blk-mq-pci.h>
585def9b
QT		 17#include <linux/refcount.h>
18
1da177e4
LT		 19#include <scsi/scsi_tcq.h>
20#include <scsi/scsicam.h>
21#include <scsi/scsi_transport.h>
22#include <scsi/scsi_transport_fc.h>
23
2d70c103
NB		 24#include "qla_target.h"
25
1da177e4
LT		 26/*
27 * Driver version
28 */
29char qla2x00_version_str[40];
30
6a03b4cd
HZ		 31static int apidev_major;
32
1da177e4
LT		 33/*
34 * SRB allocation cache
35 */
d7459527 36struct kmem_cache *srb_cachep;
1da177e4 37
a9083016
GM		 38/*
39 * CT6 CTX allocation cache
40 */
41static struct kmem_cache *ctx_cachep;
3ce8866c
SK		 42/*
43 * error level for logging
44 */
3f006ac3 45uint ql_errlev = 0x8001;
a9083016 46
fa492630 47static int ql2xenableclass2;
2d70c103
NB		 48module_param(ql2xenableclass2, int, S_IRUGO|S_IRUSR);
49MODULE_PARM_DESC(ql2xenableclass2,
50 "Specify if Class 2 operations are supported from the very "
51 "beginning. Default is 0 - class 2 not supported.");
52
8ae6d9c7 53
1da177e4 54int ql2xlogintimeout = 20;
f2019cb1 55module_param(ql2xlogintimeout, int, S_IRUGO);
1da177e4
LT		 56MODULE_PARM_DESC(ql2xlogintimeout,
57 "Login timeout value in seconds.");
58
a7b61842 59int qlport_down_retry;
f2019cb1 60module_param(qlport_down_retry, int, S_IRUGO);
1da177e4 61MODULE_PARM_DESC(qlport_down_retry,
900d9f98 62 "Maximum number of command retries to a port that returns "
1da177e4
LT		 63 "a PORT-DOWN status.");
64
1da177e4
LT		 65int ql2xplogiabsentdevice;
66module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR);
67MODULE_PARM_DESC(ql2xplogiabsentdevice,
68 "Option to enable PLOGI to devices that are not present after "
900d9f98 69 "a Fabric scan. This is needed for several broken switches. "
0d52e642 70 "Default is 0 - no PLOGI. 1 - perform PLOGI.");
1da177e4 71
c1c7178c 72int ql2xloginretrycount;
f2019cb1 73module_param(ql2xloginretrycount, int, S_IRUGO);
1da177e4
LT		 74MODULE_PARM_DESC(ql2xloginretrycount,
75 "Specify an alternate value for the NVRAM login retry count.");
76
a7a167bf 77int ql2xallocfwdump = 1;
f2019cb1 78module_param(ql2xallocfwdump, int, S_IRUGO);
a7a167bf
AV		 79MODULE_PARM_DESC(ql2xallocfwdump,
80 "Option to enable allocation of memory for a firmware dump "
81 "during HBA initialization. Memory allocation requirements "
82 "vary by ISP type. Default is 1 - allocate memory.");
83
11010fec 84int ql2xextended_error_logging;
27d94035 85module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
a2b3e01d 86module_param_named(logging, ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
11010fec 87MODULE_PARM_DESC(ql2xextended_error_logging,
3ce8866c
SK		 88 "Option to enable extended error logging,\n"
89 "\t\tDefault is 0 - no logging. 0x40000000 - Module Init & Probe.\n"
90 "\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n"
91 "\t\t0x08000000 - IO tracing. 0x04000000 - DPC Thread.\n"
92 "\t\t0x02000000 - Async events. 0x01000000 - Timer routines.\n"
93 "\t\t0x00800000 - User space. 0x00400000 - Task Management.\n"
94 "\t\t0x00200000 - AER/EEH. 0x00100000 - Multi Q.\n"
95 "\t\t0x00080000 - P3P Specific. 0x00040000 - Virtual Port.\n"
96 "\t\t0x00020000 - Buffer Dump. 0x00010000 - Misc.\n"
29f9f90c
CD		 97 "\t\t0x00008000 - Verbose. 0x00004000 - Target.\n"
98 "\t\t0x00002000 - Target Mgmt. 0x00001000 - Target TMF.\n"
3ce8866c 99 "\t\t0x7fffffff - For enabling all logs, can be too many logs.\n"
cfb0919c
CD		 100 "\t\t0x1e400000 - Preferred value for capturing essential "
101 "debug information (equivalent to old "
102 "ql2xextended_error_logging=1).\n"
3ce8866c 103 "\t\tDo LOGICAL OR of the value to enable more than one level");
0181944f 104
a9083016 105int ql2xshiftctondsd = 6;
f2019cb1 106module_param(ql2xshiftctondsd, int, S_IRUGO);
a9083016
GM		 107MODULE_PARM_DESC(ql2xshiftctondsd,
108 "Set to control shifting of command type processing "
109 "based on total number of SG elements.");
110
58e2753c 111int ql2xfdmienable = 1;
de187df8 112module_param(ql2xfdmienable, int, S_IRUGO|S_IWUSR);
a2b3e01d 113module_param_named(fdmi, ql2xfdmienable, int, S_IRUGO|S_IWUSR);
cca5335c 114MODULE_PARM_DESC(ql2xfdmienable,
7794a5af
FW		 115 "Enables FDMI registrations. "
116 "0 - no FDMI. Default is 1 - perform FDMI.");
cca5335c 117
d213a4b7 118#define MAX_Q_DEPTH 64
50280c01 119static int ql2xmaxqdepth = MAX_Q_DEPTH;
df7baa50
AV		 120module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR);
121MODULE_PARM_DESC(ql2xmaxqdepth,
e92e4a8f 122 "Maximum queue depth to set for each LUN. "
d213a4b7 123 "Default is 64.");
df7baa50 124
e84067d7
DG		 125#if (IS_ENABLED(CONFIG_NVME_FC))
126int ql2xenabledif;
127#else
9e522cd8 128int ql2xenabledif = 2;
e84067d7 129#endif
9e522cd8 130module_param(ql2xenabledif, int, S_IRUGO);
bad75002 131MODULE_PARM_DESC(ql2xenabledif,
b97f5d0b
SM		 132 " Enable T10-CRC-DIF:\n"
133 " Default is 2.\n"
134 " 0 -- No DIF Support\n"
135 " 1 -- Enable DIF for all types\n"
136 " 2 -- Enable DIF for all types, except Type 0.\n");
bad75002 137
e84067d7
DG		 138#if (IS_ENABLED(CONFIG_NVME_FC))
139int ql2xnvmeenable = 1;
140#else
141int ql2xnvmeenable;
142#endif
143module_param(ql2xnvmeenable, int, 0644);
144MODULE_PARM_DESC(ql2xnvmeenable,
145 "Enables NVME support. "
146 "0 - no NVMe. Default is Y");
147
8cb2049c 148int ql2xenablehba_err_chk = 2;
bad75002
AE		 149module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR);
150MODULE_PARM_DESC(ql2xenablehba_err_chk,
8cb2049c 151 " Enable T10-CRC-DIF Error isolation by HBA:\n"
b97f5d0b 152 " Default is 2.\n"
8cb2049c
AE		 153 " 0 -- Error isolation disabled\n"
154 " 1 -- Error isolation enabled only for DIX Type 0\n"
155 " 2 -- Error isolation enabled for all Types\n");
bad75002 156
58e2753c 157int ql2xiidmaenable = 1;
f2019cb1 158module_param(ql2xiidmaenable, int, S_IRUGO);
e5896bd5
AV		 159MODULE_PARM_DESC(ql2xiidmaenable,
160 "Enables iIDMA settings "
161 "Default is 1 - perform iIDMA. 0 - no iIDMA.");
162
d7459527
MH		 163int ql2xmqsupport = 1;
164module_param(ql2xmqsupport, int, S_IRUGO);
165MODULE_PARM_DESC(ql2xmqsupport,
166 "Enable on demand multiple queue pairs support "
167 "Default is 1 for supported. "
168 "Set it to 0 to turn off mq qpair support.");
e337d907
AV		 169
170int ql2xfwloadbin;
86e45bf6 171module_param(ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
a2b3e01d 172module_param_named(fwload, ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
e337d907 173MODULE_PARM_DESC(ql2xfwloadbin,
7c3df132
SK		 174 "Option to specify location from which to load ISP firmware:.\n"
175 " 2 -- load firmware via the request_firmware() (hotplug).\n"
e337d907
AV		 176 " interface.\n"
177 " 1 -- load firmware from flash.\n"
178 " 0 -- use default semantics.\n");
179
ae97c91e 180int ql2xetsenable;
f2019cb1 181module_param(ql2xetsenable, int, S_IRUGO);
ae97c91e
AV		 182MODULE_PARM_DESC(ql2xetsenable,
183 "Enables firmware ETS burst."
184 "Default is 0 - skip ETS enablement.");
185
6907869d 186int ql2xdbwr = 1;
86e45bf6 187module_param(ql2xdbwr, int, S_IRUGO|S_IWUSR);
a9083016 188MODULE_PARM_DESC(ql2xdbwr,
08de2844
GM		 189 "Option to specify scheme for request queue posting.\n"
190 " 0 -- Regular doorbell.\n"
191 " 1 -- CAMRAM doorbell (faster).\n");
a9083016 192
f4c496c1 193int ql2xtargetreset = 1;
f2019cb1 194module_param(ql2xtargetreset, int, S_IRUGO);
f4c496c1
GM		 195MODULE_PARM_DESC(ql2xtargetreset,
196 "Enable target reset."
197 "Default is 1 - use hw defaults.");
198
4da26e16 199int ql2xgffidenable;
f2019cb1 200module_param(ql2xgffidenable, int, S_IRUGO);
4da26e16
CD		 201MODULE_PARM_DESC(ql2xgffidenable,
202 "Enables GFF_ID checks of port type. "
203 "Default is 0 - Do not use GFF_ID information.");
a9083016 204
043dc1d7 205int ql2xasynctmfenable = 1;
f2019cb1 206module_param(ql2xasynctmfenable, int, S_IRUGO);
3822263e
MI		 207MODULE_PARM_DESC(ql2xasynctmfenable,
208 "Enables issue of TM IOCBs asynchronously via IOCB mechanism"
84e13c45 209 "Default is 1 - Issue TM IOCBs via mailbox mechanism.");
ed0de87c
GM		 210
211int ql2xdontresethba;
86e45bf6 212module_param(ql2xdontresethba, int, S_IRUGO|S_IWUSR);
ed0de87c 213MODULE_PARM_DESC(ql2xdontresethba,
08de2844
GM		 214 "Option to specify reset behaviour.\n"
215 " 0 (Default) -- Reset on failure.\n"
216 " 1 -- Do not reset on failure.\n");
ed0de87c 217
1abf635d
HR		 218uint64_t ql2xmaxlun = MAX_LUNS;
219module_param(ql2xmaxlun, ullong, S_IRUGO);
82515920
AV		 220MODULE_PARM_DESC(ql2xmaxlun,
221 "Defines the maximum LU number to register with the SCSI "
222 "midlayer. Default is 65535.");
223
08de2844
GM		 224int ql2xmdcapmask = 0x1F;
225module_param(ql2xmdcapmask, int, S_IRUGO);
226MODULE_PARM_DESC(ql2xmdcapmask,
227 "Set the Minidump driver capture mask level. "
6e96fa7b 228 "Default is 0x1F - Can be set to 0x3, 0x7, 0xF, 0x1F, 0x7F.");
08de2844 229
3aadff35 230int ql2xmdenable = 1;
08de2844
GM		 231module_param(ql2xmdenable, int, S_IRUGO);
232MODULE_PARM_DESC(ql2xmdenable,
233 "Enable/disable MiniDump. "
3aadff35
GM		 234 "0 - MiniDump disabled. "
235 "1 (Default) - MiniDump enabled.");
08de2844 236
c1c7178c 237int ql2xexlogins;
b0d6cabd
HM		 238module_param(ql2xexlogins, uint, S_IRUGO|S_IWUSR);
239MODULE_PARM_DESC(ql2xexlogins,
240 "Number of extended Logins. "
241 "0 (Default)- Disabled.");
242
99e1b683
QT		 243int ql2xexchoffld = 1024;
244module_param(ql2xexchoffld, uint, 0644);
2f56a7f1 245MODULE_PARM_DESC(ql2xexchoffld,
99e1b683
QT		 246 "Number of target exchanges.");
247
248int ql2xiniexchg = 1024;
249module_param(ql2xiniexchg, uint, 0644);
250MODULE_PARM_DESC(ql2xiniexchg,
251 "Number of initiator exchanges.");
2f56a7f1 252
c1c7178c 253int ql2xfwholdabts;
f198cafa
HM		 254module_param(ql2xfwholdabts, int, S_IRUGO);
255MODULE_PARM_DESC(ql2xfwholdabts,
256 "Allow FW to hold status IOCB until ABTS rsp received. "
257 "0 (Default) Do not set fw option. "
258 "1 - Set fw option to hold ABTS.");
259
41dc529a
QT		 260int ql2xmvasynctoatio = 1;
261module_param(ql2xmvasynctoatio, int, S_IRUGO|S_IWUSR);
262MODULE_PARM_DESC(ql2xmvasynctoatio,
263 "Move PUREX, ABTS RX and RIDA IOCBs to ATIOQ"
264 "0 (Default). Do not move IOCBs"
265 "1 - Move IOCBs.");
266
e4e3a2ce
QT		 267int ql2xautodetectsfp = 1;
268module_param(ql2xautodetectsfp, int, 0444);
269MODULE_PARM_DESC(ql2xautodetectsfp,
270 "Detect SFP range and set appropriate distance.\n"
271 "1 (Default): Enable\n");
272
e7240af5
HM		 273int ql2xenablemsix = 1;
274module_param(ql2xenablemsix, int, 0444);
275MODULE_PARM_DESC(ql2xenablemsix,
276 "Set to enable MSI or MSI-X interrupt mechanism.\n"
277 " Default is 1, enable MSI-X interrupt mechanism.\n"
278 " 0 -- enable traditional pin-based mechanism.\n"
279 " 1 -- enable MSI-X interrupt mechanism.\n"
280 " 2 -- enable MSI interrupt mechanism.\n");
281
9ecf0b0d
QT		 282int qla2xuseresexchforels;
283module_param(qla2xuseresexchforels, int, 0444);
284MODULE_PARM_DESC(qla2xuseresexchforels,
285 "Reserve 1/2 of emergency exchanges for ELS.\n"
286 " 0 (default): disabled");
287
b3ede8ea 288static int ql2xprotmask;
7855d2ba
MP		 289module_param(ql2xprotmask, int, 0644);
290MODULE_PARM_DESC(ql2xprotmask,
291 "Override DIF/DIX protection capabilities mask\n"
292 "Default is 0 which sets protection mask based on "
293 "capabilities reported by HBA firmware.\n");
294
b3ede8ea 295static int ql2xprotguard;
7855d2ba
MP		 296module_param(ql2xprotguard, int, 0644);
297MODULE_PARM_DESC(ql2xprotguard, "Override choice of DIX checksum\n"
298 " 0 -- Let HBA firmware decide\n"
299 " 1 -- Force T10 CRC\n"
300 " 2 -- Force IP checksum\n");
301
50b81275
GM		 302int ql2xdifbundlinginternalbuffers;
303module_param(ql2xdifbundlinginternalbuffers, int, 0644);
304MODULE_PARM_DESC(ql2xdifbundlinginternalbuffers,
305 "Force using internal buffers for DIF information\n"
306 "0 (Default). Based on check.\n"
307 "1 Force using internal buffers\n");
308
1a2fbf18 309static void qla2x00_clear_drv_active(struct qla_hw_data *);
3491255e 310static void qla2x00_free_device(scsi_qla_host_t *);
5601236b 311static int qla2xxx_map_queues(struct Scsi_Host *shost);
e84067d7 312static void qla2x00_destroy_deferred_work(struct qla_hw_data *);
ce7e4af7 313
45235022 314
1da177e4 315static struct scsi_transport_template *qla2xxx_transport_template = NULL;
2c3dfe3f 316struct scsi_transport_template *qla2xxx_transport_vport_template = NULL;
1da177e4 317
1da177e4
LT		 318/* TODO Convert to inlines
319 *
320 * Timer routines
321 */
1da177e4 322
2c3dfe3f 323__inline__ void
8e5f4ba0 324qla2x00_start_timer(scsi_qla_host_t *vha, unsigned long interval)
1da177e4 325{
8e5f4ba0 326 timer_setup(&vha->timer, qla2x00_timer, 0);
e315cd28 327 vha->timer.expires = jiffies + interval * HZ;
e315cd28
AC		 328 add_timer(&vha->timer);
329 vha->timer_active = 1;
1da177e4
LT		 330}
331
332static inline void
e315cd28 333qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval)
1da177e4 334{
a9083016 335 /* Currently used for 82XX only. */
7c3df132
SK		 336 if (vha->device_flags & DFLG_DEV_FAILED) {
337 ql_dbg(ql_dbg_timer, vha, 0x600d,
338 "Device in a failed state, returning.\n");
a9083016 339 return;
7c3df132 340 }
a9083016 341
e315cd28 342 mod_timer(&vha->timer, jiffies + interval * HZ);
1da177e4
LT		 343}
344
a824ebb3 345static __inline__ void
e315cd28 346qla2x00_stop_timer(scsi_qla_host_t *vha)
1da177e4 347{
e315cd28
AC		 348 del_timer_sync(&vha->timer);
349 vha->timer_active = 0;
1da177e4
LT		 350}
351
1da177e4
LT		 352static int qla2x00_do_dpc(void *data);
353
354static void qla2x00_rst_aen(scsi_qla_host_t *);
355
73208dfd
AC		 356static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t,
357 struct req_que **, struct rsp_que **);
e30d1756 358static void qla2x00_free_fw_dump(struct qla_hw_data *);
e315cd28 359static void qla2x00_mem_free(struct qla_hw_data *);
d7459527
MH		 360int qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd,
361 struct qla_qpair *qpair);
1da177e4 362
1da177e4 363/* -------------------------------------------------------------------------- */
8abfa9e2
QT		 364static void qla_init_base_qpair(struct scsi_qla_host *vha, struct req_que *req,
365 struct rsp_que *rsp)
366{
367 struct qla_hw_data *ha = vha->hw;
bd432bb5 368
8abfa9e2
QT		 369 rsp->qpair = ha->base_qpair;
370 rsp->req = req;
0691094f 371 ha->base_qpair->hw = ha;
8abfa9e2
QT		 372 ha->base_qpair->req = req;
373 ha->base_qpair->rsp = rsp;
374 ha->base_qpair->vha = vha;
375 ha->base_qpair->qp_lock_ptr = &ha->hardware_lock;
376 ha->base_qpair->use_shadow_reg = IS_SHADOW_REG_CAPABLE(ha) ? 1 : 0;
377 ha->base_qpair->msix = &ha->msix_entries[QLA_MSIX_RSP_Q];
6a629468 378 ha->base_qpair->srb_mempool = ha->srb_mempool;
8abfa9e2
QT		 379 INIT_LIST_HEAD(&ha->base_qpair->hints_list);
380 ha->base_qpair->enable_class_2 = ql2xenableclass2;
381 /* init qpair to this cpu. Will adjust at run time. */
86531887 382 qla_cpu_update(rsp->qpair, raw_smp_processor_id());
8abfa9e2
QT		 383 ha->base_qpair->pdev = ha->pdev;
384
ecc89f25 385 if (IS_QLA27XX(ha) || IS_QLA83XX(ha) || IS_QLA28XX(ha))
8abfa9e2
QT		 386 ha->base_qpair->reqq_start_iocbs = qla_83xx_start_iocbs;
387}
388
9a347ff4
CD		 389static int qla2x00_alloc_queues(struct qla_hw_data *ha, struct req_que *req,
390 struct rsp_que *rsp)
73208dfd 391{
7c3df132 392 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
bd432bb5 393
6396bb22 394 ha->req_q_map = kcalloc(ha->max_req_queues, sizeof(struct req_que *),
73208dfd
AC		 395 GFP_KERNEL);
396 if (!ha->req_q_map) {
7c3df132
SK		 397 ql_log(ql_log_fatal, vha, 0x003b,
398 "Unable to allocate memory for request queue ptrs.\n");
73208dfd
AC		 399 goto fail_req_map;
400 }
401
6396bb22 402 ha->rsp_q_map = kcalloc(ha->max_rsp_queues, sizeof(struct rsp_que *),
73208dfd
AC		 403 GFP_KERNEL);
404 if (!ha->rsp_q_map) {
7c3df132
SK		 405 ql_log(ql_log_fatal, vha, 0x003c,
406 "Unable to allocate memory for response queue ptrs.\n");
73208dfd
AC		 407 goto fail_rsp_map;
408 }
d7459527 409
e326d22a
QT		 410 ha->base_qpair = kzalloc(sizeof(struct qla_qpair), GFP_KERNEL);
411 if (ha->base_qpair == NULL) {
412 ql_log(ql_log_warn, vha, 0x00e0,
413 "Failed to allocate base queue pair memory.\n");
414 goto fail_base_qpair;
415 }
416
8abfa9e2 417 qla_init_base_qpair(vha, req, rsp);
e326d22a 418
c38d1baf 419 if ((ql2xmqsupport || ql2xnvmeenable) && ha->max_qpairs) {
d7459527
MH		 420 ha->queue_pair_map = kcalloc(ha->max_qpairs, sizeof(struct qla_qpair *),
421 GFP_KERNEL);
422 if (!ha->queue_pair_map) {
423 ql_log(ql_log_fatal, vha, 0x0180,
424 "Unable to allocate memory for queue pair ptrs.\n");
425 goto fail_qpair_map;
426 }
d7459527
MH		 427 }
428
9a347ff4
CD		 429 /*
430 * Make sure we record at least the request and response queue zero in
431 * case we need to free them if part of the probe fails.
432 */
433 ha->rsp_q_map[0] = rsp;
434 ha->req_q_map[0] = req;
73208dfd
AC		 435 set_bit(0, ha->rsp_qid_map);
436 set_bit(0, ha->req_qid_map);
6a2cf8d3 437 return 0;
73208dfd 438
d7459527 439fail_qpair_map:
82de802a
QT		 440 kfree(ha->base_qpair);
441 ha->base_qpair = NULL;
442fail_base_qpair:
d7459527
MH		 443 kfree(ha->rsp_q_map);
444 ha->rsp_q_map = NULL;
73208dfd
AC		 445fail_rsp_map:
446 kfree(ha->req_q_map);
447 ha->req_q_map = NULL;
448fail_req_map:
449 return -ENOMEM;
450}
451
2afa19a9 452static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req)
73208dfd 453{
8ae6d9c7
GM		 454 if (IS_QLAFX00(ha)) {
455 if (req && req->ring_fx00)
456 dma_free_coherent(&ha->pdev->dev,
457 (req->length_fx00 + 1) * sizeof(request_t),
458 req->ring_fx00, req->dma_fx00);
459 } else if (req && req->ring)
73208dfd
AC		 460 dma_free_coherent(&ha->pdev->dev,
461 (req->length + 1) * sizeof(request_t),
462 req->ring, req->dma);
463
6d634067 464 if (req)
8d93f550 465 kfree(req->outstanding_cmds);
6d634067
BK		 466
467 kfree(req);
73208dfd
AC		 468}
469
2afa19a9
AC		 470static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp)
471{
8ae6d9c7 472 if (IS_QLAFX00(ha)) {
3f6c9be2 473 if (rsp && rsp->ring_fx00)
8ae6d9c7
GM		 474 dma_free_coherent(&ha->pdev->dev,
475 (rsp->length_fx00 + 1) * sizeof(request_t),
476 rsp->ring_fx00, rsp->dma_fx00);
477 } else if (rsp && rsp->ring) {
2afa19a9
AC		 478 dma_free_coherent(&ha->pdev->dev,
479 (rsp->length + 1) * sizeof(response_t),
480 rsp->ring, rsp->dma);
8ae6d9c7 481 }
6d634067 482 kfree(rsp);
2afa19a9
AC		 483}
484
73208dfd
AC		 485static void qla2x00_free_queues(struct qla_hw_data *ha)
486{
487 struct req_que *req;
488 struct rsp_que *rsp;
489 int cnt;
093df737 490 unsigned long flags;
73208dfd 491
82de802a
QT		 492 if (ha->queue_pair_map) {
493 kfree(ha->queue_pair_map);
494 ha->queue_pair_map = NULL;
495 }
496 if (ha->base_qpair) {
497 kfree(ha->base_qpair);
498 ha->base_qpair = NULL;
499 }
500
093df737 501 spin_lock_irqsave(&ha->hardware_lock, flags);
2afa19a9 502 for (cnt = 0; cnt < ha->max_req_queues; cnt++) {
cb43285f
QT		 503 if (!test_bit(cnt, ha->req_qid_map))
504 continue;
505
73208dfd 506 req = ha->req_q_map[cnt];
093df737
QT		 507 clear_bit(cnt, ha->req_qid_map);
508 ha->req_q_map[cnt] = NULL;
509
510 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2afa19a9 511 qla2x00_free_req_que(ha, req);
093df737 512 spin_lock_irqsave(&ha->hardware_lock, flags);
73208dfd 513 }
093df737
QT		 514 spin_unlock_irqrestore(&ha->hardware_lock, flags);
515
73208dfd
AC		 516 kfree(ha->req_q_map);
517 ha->req_q_map = NULL;
2afa19a9 518
093df737
QT		 519
520 spin_lock_irqsave(&ha->hardware_lock, flags);
2afa19a9 521 for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) {
cb43285f
QT		 522 if (!test_bit(cnt, ha->rsp_qid_map))
523 continue;
524
2afa19a9 525 rsp = ha->rsp_q_map[cnt];
c3c42394 526 clear_bit(cnt, ha->rsp_qid_map);
093df737
QT		 527 ha->rsp_q_map[cnt] = NULL;
528 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2afa19a9 529 qla2x00_free_rsp_que(ha, rsp);
093df737 530 spin_lock_irqsave(&ha->hardware_lock, flags);
2afa19a9 531 }
093df737
QT		 532 spin_unlock_irqrestore(&ha->hardware_lock, flags);
533
2afa19a9
AC		 534 kfree(ha->rsp_q_map);
535 ha->rsp_q_map = NULL;
73208dfd
AC		 536}
537
1da177e4 538static char *
e315cd28 539qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str)
1da177e4 540{
e315cd28 541 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 542 static char *pci_bus_modes[] = {
543 "33", "66", "100", "133",
544 };
545 uint16_t pci_bus;
546
547 strcpy(str, "PCI");
548 pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9;
549 if (pci_bus) {
550 strcat(str, "-X (");
551 strcat(str, pci_bus_modes[pci_bus]);
552 } else {
553 pci_bus = (ha->pci_attr & BIT_8) >> 8;
554 strcat(str, " (");
555 strcat(str, pci_bus_modes[pci_bus]);
556 }
557 strcat(str, " MHz)");
558
559 return (str);
560}
561
fca29703 562static char *
e315cd28 563qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str)
fca29703
AV		 564{
565 static char *pci_bus_modes[] = { "33", "66", "100", "133", };
e315cd28 566 struct qla_hw_data *ha = vha->hw;
fca29703 567 uint32_t pci_bus;
fca29703 568
62a276f8 569 if (pci_is_pcie(ha->pdev)) {
fca29703 570 char lwstr[6];
62a276f8 571 uint32_t lstat, lspeed, lwidth;
fca29703 572
62a276f8
BH		 573 pcie_capability_read_dword(ha->pdev, PCI_EXP_LNKCAP, &lstat);
574 lspeed = lstat & PCI_EXP_LNKCAP_SLS;
575 lwidth = (lstat & PCI_EXP_LNKCAP_MLW) >> 4;
fca29703
AV		 576
577 strcpy(str, "PCIe (");
49300af7
SK		 578 switch (lspeed) {
579 case 1:
c87a0d8c 580 strcat(str, "2.5GT/s ");
49300af7
SK		 581 break;
582 case 2:
c87a0d8c 583 strcat(str, "5.0GT/s ");
49300af7
SK		 584 break;
585 case 3:
586 strcat(str, "8.0GT/s ");
587 break;
588 default:
fca29703 589 strcat(str, "<unknown> ");
49300af7
SK		 590 break;
591 }
fca29703
AV		 592 snprintf(lwstr, sizeof(lwstr), "x%d)", lwidth);
593 strcat(str, lwstr);
594
595 return str;
596 }
597
598 strcpy(str, "PCI");
599 pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8;
600 if (pci_bus == 0 || pci_bus == 8) {
601 strcat(str, " (");
602 strcat(str, pci_bus_modes[pci_bus >> 3]);
603 } else {
604 strcat(str, "-X ");
605 if (pci_bus & BIT_2)
606 strcat(str, "Mode 2");
607 else
608 strcat(str, "Mode 1");
609 strcat(str, " (");
610 strcat(str, pci_bus_modes[pci_bus & ~BIT_2]);
611 }
612 strcat(str, " MHz)");
613
614 return str;
615}
616
e5f82ab8 617static char *
df57caba 618qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
1da177e4
LT		 619{
620 char un_str[10];
e315cd28 621 struct qla_hw_data *ha = vha->hw;
fa2a1ce5 622
df57caba
HM		 623 snprintf(str, size, "%d.%02d.%02d ", ha->fw_major_version,
624 ha->fw_minor_version, ha->fw_subminor_version);
1da177e4
LT		 625
626 if (ha->fw_attributes & BIT_9) {
627 strcat(str, "FLX");
628 return (str);
629 }
630
631 switch (ha->fw_attributes & 0xFF) {
632 case 0x7:
633 strcat(str, "EF");
634 break;
635 case 0x17:
636 strcat(str, "TP");
637 break;
638 case 0x37:
639 strcat(str, "IP");
640 break;
641 case 0x77:
642 strcat(str, "VI");
643 break;
644 default:
645 sprintf(un_str, "(%x)", ha->fw_attributes);
646 strcat(str, un_str);
647 break;
648 }
649 if (ha->fw_attributes & 0x100)
650 strcat(str, "X");
651
652 return (str);
653}
654
e5f82ab8 655static char *
df57caba 656qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
fca29703 657{
e315cd28 658 struct qla_hw_data *ha = vha->hw;
f0883ac6 659
df57caba 660 snprintf(str, size, "%d.%02d.%02d (%x)", ha->fw_major_version,
3a03eb79 661 ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes);
fca29703 662 return str;
fca29703
AV		 663}
664
9ba56b95 665void
25ff6af1 666qla2x00_sp_free_dma(void *ptr)
fca29703 667{
25ff6af1
JC		 668 srb_t *sp = ptr;
669 struct qla_hw_data *ha = sp->vha->hw;
9ba56b95 670 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
9ba56b95 671 void *ctx = GET_CMD_CTX_SP(sp);
fca29703 672
9ba56b95
GM		 673 if (sp->flags & SRB_DMA_VALID) {
674 scsi_dma_unmap(cmd);
675 sp->flags &= ~SRB_DMA_VALID;
7c3df132 676 }
fca29703 677
9ba56b95
GM		 678 if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
679 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
680 scsi_prot_sg_count(cmd), cmd->sc_data_direction);
681 sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
682 }
683
d5ff0eed 684 if (!ctx)
711a08d7 685 return;
d5ff0eed 686
9ba56b95
GM		 687 if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
688 /* List assured to be having elements */
d5ff0eed 689 qla2x00_clean_dsd_pool(ha, ctx);
9ba56b95
GM		 690 sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
691 }
692
693 if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
d5ff0eed
JC		 694 struct crc_context *ctx0 = ctx;
695
696 dma_pool_free(ha->dl_dma_pool, ctx0, ctx0->crc_ctx_dma);
9ba56b95
GM		 697 sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
698 }
699
700 if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
d5ff0eed 701 struct ct6_dsd *ctx1 = ctx;
fca29703 702
9ba56b95 703 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd,
d5ff0eed 704 ctx1->fcp_cmnd_dma);
9ba56b95
GM		 705 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list);
706 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt;
707 ha->gbl_dsd_avail += ctx1->dsd_use_cnt;
708 mempool_free(ctx1, ha->ctx_mempool);
9ba56b95 709 }
9ba56b95
GM		 710}
711
d7459527 712void
25ff6af1 713qla2x00_sp_compl(void *ptr, int res)
9ba56b95 714{
25ff6af1 715 srb_t *sp = ptr;
9ba56b95 716 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
219d27d7 717 struct completion *comp = sp->comp;
9ba56b95 718
db4bf822 719 if (WARN_ON_ONCE(atomic_read(&sp->ref_count) == 0))
9ba56b95 720 return;
219d27d7
BVA		 721
722 atomic_dec(&sp->ref_count);
9ba56b95 723
f3caa990 724 sp->free(sp);
740e2935 725 cmd->result = res;
711a08d7 726 CMD_SP(cmd) = NULL;
9ba56b95 727 cmd->scsi_done(cmd);
219d27d7
BVA		 728 if (comp)
729 complete(comp);
711a08d7 730 qla2x00_rel_sp(sp);
fca29703
AV		 731}
732
d7459527 733void
25ff6af1 734qla2xxx_qpair_sp_free_dma(void *ptr)
d7459527
MH		 735{
736 srb_t *sp = (srb_t *)ptr;
737 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
738 struct qla_hw_data *ha = sp->fcport->vha->hw;
739 void *ctx = GET_CMD_CTX_SP(sp);
740
741 if (sp->flags & SRB_DMA_VALID) {
742 scsi_dma_unmap(cmd);
743 sp->flags &= ~SRB_DMA_VALID;
744 }
745
746 if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
747 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
748 scsi_prot_sg_count(cmd), cmd->sc_data_direction);
749 sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
750 }
751
d5ff0eed 752 if (!ctx)
711a08d7 753 return;
d5ff0eed 754
d7459527
MH		 755 if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
756 /* List assured to be having elements */
d5ff0eed 757 qla2x00_clean_dsd_pool(ha, ctx);
d7459527
MH		 758 sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
759 }
760
50b81275 761 if (sp->flags & SRB_DIF_BUNDL_DMA_VALID) {
d8f945bf 762 struct crc_context *difctx = ctx;
50b81275
GM		 763 struct dsd_dma *dif_dsd, *nxt_dsd;
764
765 list_for_each_entry_safe(dif_dsd, nxt_dsd,
766 &difctx->ldif_dma_hndl_list, list) {
767 list_del(&dif_dsd->list);
768 dma_pool_free(ha->dif_bundl_pool, dif_dsd->dsd_addr,
769 dif_dsd->dsd_list_dma);
770 kfree(dif_dsd);
771 difctx->no_dif_bundl--;
772 }
773
774 list_for_each_entry_safe(dif_dsd, nxt_dsd,
775 &difctx->ldif_dsd_list, list) {
776 list_del(&dif_dsd->list);
777 dma_pool_free(ha->dl_dma_pool, dif_dsd->dsd_addr,
778 dif_dsd->dsd_list_dma);
779 kfree(dif_dsd);
780 difctx->no_ldif_dsd--;
781 }
782
783 if (difctx->no_ldif_dsd) {
784 ql_dbg(ql_dbg_tgt+ql_dbg_verbose, sp->vha, 0xe022,
785 "%s: difctx->no_ldif_dsd=%x\n",
786 __func__, difctx->no_ldif_dsd);
787 }
788
789 if (difctx->no_dif_bundl) {
790 ql_dbg(ql_dbg_tgt+ql_dbg_verbose, sp->vha, 0xe022,
791 "%s: difctx->no_dif_bundl=%x\n",
792 __func__, difctx->no_dif_bundl);
793 }
794 sp->flags &= ~SRB_DIF_BUNDL_DMA_VALID;
d7459527 795 }
d8f945bf
BVA		 796
797 if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
798 struct ct6_dsd *ctx1 = ctx;
799
800 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd,
801 ctx1->fcp_cmnd_dma);
802 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list);
803 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt;
804 ha->gbl_dsd_avail += ctx1->dsd_use_cnt;
805 mempool_free(ctx1, ha->ctx_mempool);
806 sp->flags &= ~SRB_FCP_CMND_DMA_VALID;
807 }
808
809 if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
810 struct crc_context *ctx0 = ctx;
811
812 dma_pool_free(ha->dl_dma_pool, ctx, ctx0->crc_ctx_dma);
813 sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
814 }
d7459527
MH		 815}
816
817void
25ff6af1 818qla2xxx_qpair_sp_compl(void *ptr, int res)
d7459527 819{
25ff6af1 820 srb_t *sp = ptr;
d7459527 821 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
219d27d7 822 struct completion *comp = sp->comp;
d7459527 823
db4bf822 824 if (WARN_ON_ONCE(atomic_read(&sp->ref_count) == 0))
d7459527 825 return;
219d27d7
BVA		 826
827 atomic_dec(&sp->ref_count);
d7459527 828
f3caa990 829 sp->free(sp);
711a08d7
GM		 830 cmd->result = res;
831 CMD_SP(cmd) = NULL;
d7459527 832 cmd->scsi_done(cmd);
219d27d7
BVA		 833 if (comp)
834 complete(comp);
711a08d7 835 qla2xxx_rel_qpair_sp(sp->qpair, sp);
d7459527
MH		 836}
837
1da177e4 838static int
f5e3e40b 839qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
fca29703 840{
134ae078 841 scsi_qla_host_t *vha = shost_priv(host);
fca29703 842 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
19a7b4ae 843 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
e315cd28
AC		 844 struct qla_hw_data *ha = vha->hw;
845 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
fca29703
AV		 846 srb_t *sp;
847 int rval;
848
2dbb02fd
BVA		 849 if (unlikely(test_bit(UNLOADING, &base_vha->dpc_flags)) ||
850 WARN_ON_ONCE(!rport)) {
04dfaa53
MFO		 851 cmd->result = DID_NO_CONNECT << 16;
852 goto qc24_fail_command;
853 }
854
5601236b 855 if (ha->mqenable) {
6d58ef05
BVA		 856 uint32_t tag;
857 uint16_t hwq;
858 struct qla_qpair *qpair = NULL;
859
f664a3cc
JA		 860 tag = blk_mq_unique_tag(cmd->request);
861 hwq = blk_mq_unique_tag_to_hwq(tag);
862 qpair = ha->queue_pair_map[hwq];
5601236b
MH		 863
864 if (qpair)
865 return qla2xxx_mqueuecommand(host, cmd, qpair);
d7459527
MH		 866 }
867
85880801 868 if (ha->flags.eeh_busy) {
7c3df132 869 if (ha->flags.pci_channel_io_perm_failure) {
5f28d2d7 870 ql_dbg(ql_dbg_aer, vha, 0x9010,
7c3df132
SK		 871 "PCI Channel IO permanent failure, exiting "
872 "cmd=%p.\n", cmd);
b9b12f73 873 cmd->result = DID_NO_CONNECT << 16;
7c3df132 874 } else {
5f28d2d7 875 ql_dbg(ql_dbg_aer, vha, 0x9011,
7c3df132 876 "EEH_Busy, Requeuing the cmd=%p.\n", cmd);
85880801 877 cmd->result = DID_REQUEUE << 16;
7c3df132 878 }
14e660e6
SJ		 879 goto qc24_fail_command;
880 }
881
19a7b4ae
JSEC		 882 rval = fc_remote_port_chkready(rport);
883 if (rval) {
884 cmd->result = rval;
5f28d2d7 885 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3003,
7c3df132
SK		 886 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
887 cmd, rval);
fca29703
AV		 888 goto qc24_fail_command;
889 }
890
bad75002
AE		 891 if (!vha->flags.difdix_supported &&
892 scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) {
7c3df132
SK		 893 ql_dbg(ql_dbg_io, vha, 0x3004,
894 "DIF Cap not reg, fail DIF capable cmd's:%p.\n",
895 cmd);
bad75002
AE		 896 cmd->result = DID_NO_CONNECT << 16;
897 goto qc24_fail_command;
898 }
aa651be8
CD		 899
900 if (!fcport) {
901 cmd->result = DID_NO_CONNECT << 16;
902 goto qc24_fail_command;
903 }
904
fca29703
AV		 905 if (atomic_read(&fcport->state) != FCS_ONLINE) {
906 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
38170fa8 907 atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
7c3df132
SK		 908 ql_dbg(ql_dbg_io, vha, 0x3005,
909 "Returning DNC, fcport_state=%d loop_state=%d.\n",
910 atomic_read(&fcport->state),
911 atomic_read(&base_vha->loop_state));
fca29703
AV		 912 cmd->result = DID_NO_CONNECT << 16;
913 goto qc24_fail_command;
914 }
7b594131 915 goto qc24_target_busy;
fca29703
AV		 916 }
917
e05fe292
CD		 918 /*
919 * Return target busy if we've received a non-zero retry_delay_timer
920 * in a FCP_RSP.
921 */
975f7d46
BP		 922 if (fcport->retry_delay_timestamp == 0) {
923 /* retry delay not set */
924 } else if (time_after(jiffies, fcport->retry_delay_timestamp))
e05fe292
CD		 925 fcport->retry_delay_timestamp = 0;
926 else
927 goto qc24_target_busy;
928
b00ee7d7 929 sp = qla2x00_get_sp(vha, fcport, GFP_ATOMIC);
50280c01 930 if (!sp)
f5e3e40b 931 goto qc24_host_busy;
fca29703 932
9ba56b95
GM		 933 sp->u.scmd.cmd = cmd;
934 sp->type = SRB_SCSI_CMD;
935 atomic_set(&sp->ref_count, 1);
936 CMD_SP(cmd) = (void *)sp;
937 sp->free = qla2x00_sp_free_dma;
938 sp->done = qla2x00_sp_compl;
939
e315cd28 940 rval = ha->isp_ops->start_scsi(sp);
7c3df132 941 if (rval != QLA_SUCCESS) {
53016ed3 942 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3013,
7c3df132 943 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
fca29703 944 goto qc24_host_busy_free_sp;
7c3df132 945 }
fca29703 946
fca29703
AV		 947 return 0;
948
949qc24_host_busy_free_sp:
f3caa990 950 sp->free(sp);
fca29703 951
f5e3e40b 952qc24_host_busy:
fca29703
AV		 953 return SCSI_MLQUEUE_HOST_BUSY;
954
7b594131
MC		 955qc24_target_busy:
956 return SCSI_MLQUEUE_TARGET_BUSY;
957
fca29703 958qc24_fail_command:
f5e3e40b 959 cmd->scsi_done(cmd);
fca29703
AV		 960
961 return 0;
962}
963
d7459527
MH		 964/* For MQ supported I/O */
965int
966qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd,
967 struct qla_qpair *qpair)
968{
969 scsi_qla_host_t *vha = shost_priv(host);
970 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
971 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
972 struct qla_hw_data *ha = vha->hw;
973 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
974 srb_t *sp;
975 int rval;
976
2dbb02fd 977 rval = rport ? fc_remote_port_chkready(rport) : FC_PORTSTATE_OFFLINE;
d7459527
MH		 978 if (rval) {
979 cmd->result = rval;
980 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3076,
981 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
982 cmd, rval);
983 goto qc24_fail_command;
984 }
985
986 if (!fcport) {
987 cmd->result = DID_NO_CONNECT << 16;
988 goto qc24_fail_command;
989 }
990
991 if (atomic_read(&fcport->state) != FCS_ONLINE) {
992 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
993 atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
994 ql_dbg(ql_dbg_io, vha, 0x3077,
995 "Returning DNC, fcport_state=%d loop_state=%d.\n",
996 atomic_read(&fcport->state),
997 atomic_read(&base_vha->loop_state));
998 cmd->result = DID_NO_CONNECT << 16;
999 goto qc24_fail_command;
1000 }
1001 goto qc24_target_busy;
1002 }
1003
1004 /*
1005 * Return target busy if we've received a non-zero retry_delay_timer
1006 * in a FCP_RSP.
1007 */
1008 if (fcport->retry_delay_timestamp == 0) {
1009 /* retry delay not set */
1010 } else if (time_after(jiffies, fcport->retry_delay_timestamp))
1011 fcport->retry_delay_timestamp = 0;
1012 else
1013 goto qc24_target_busy;
1014
6a629468 1015 sp = qla2xxx_get_qpair_sp(vha, qpair, fcport, GFP_ATOMIC);
d7459527
MH		 1016 if (!sp)
1017 goto qc24_host_busy;
1018
1019 sp->u.scmd.cmd = cmd;
1020 sp->type = SRB_SCSI_CMD;
1021 atomic_set(&sp->ref_count, 1);
1022 CMD_SP(cmd) = (void *)sp;
1023 sp->free = qla2xxx_qpair_sp_free_dma;
1024 sp->done = qla2xxx_qpair_sp_compl;
1025 sp->qpair = qpair;
1026
1027 rval = ha->isp_ops->start_scsi_mq(sp);
1028 if (rval != QLA_SUCCESS) {
1029 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3078,
1030 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
1031 if (rval == QLA_INTERFACE_ERROR)
1032 goto qc24_fail_command;
1033 goto qc24_host_busy_free_sp;
1034 }
1035
1036 return 0;
1037
1038qc24_host_busy_free_sp:
f3caa990 1039 sp->free(sp);
d7459527
MH		 1040
1041qc24_host_busy:
1042 return SCSI_MLQUEUE_HOST_BUSY;
1043
1044qc24_target_busy:
1045 return SCSI_MLQUEUE_TARGET_BUSY;
1046
1047qc24_fail_command:
1048 cmd->scsi_done(cmd);
1049
1050 return 0;
1051}
1052
1da177e4
LT		 1053/*
1054 * qla2x00_eh_wait_on_command
1055 * Waits for the command to be returned by the Firmware for some
1056 * max time.
1057 *
1058 * Input:
1da177e4 1059 * cmd = Scsi Command to wait on.
1da177e4
LT		 1060 *
1061 * Return:
fcef0893
BVA		 1062 * Completed in time : QLA_SUCCESS
1063 * Did not complete in time : QLA_FUNCTION_FAILED
1da177e4
LT		 1064 */
1065static int
e315cd28 1066qla2x00_eh_wait_on_command(struct scsi_cmnd *cmd)
1da177e4 1067{
fe74c71f 1068#define ABORT_POLLING_PERIOD 1000
478c3b03 1069#define ABORT_WAIT_ITER ((2 * 1000) / (ABORT_POLLING_PERIOD))
f4f051eb 1070 unsigned long wait_iter = ABORT_WAIT_ITER;
85880801
AV		 1071 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1072 struct qla_hw_data *ha = vha->hw;
f4f051eb 1073 int ret = QLA_SUCCESS;
1da177e4 1074
85880801 1075 if (unlikely(pci_channel_offline(ha->pdev)) || ha->flags.eeh_busy) {
7c3df132
SK		 1076 ql_dbg(ql_dbg_taskm, vha, 0x8005,
1077 "Return:eh_wait.\n");
85880801
AV		 1078 return ret;
1079 }
1080
d970432c 1081 while (CMD_SP(cmd) && wait_iter--) {
fe74c71f 1082 msleep(ABORT_POLLING_PERIOD);
f4f051eb 1083 }
1084 if (CMD_SP(cmd))
1085 ret = QLA_FUNCTION_FAILED;
1da177e4 1086
f4f051eb 1087 return ret;
1da177e4
LT		 1088}
1089
1090/*
1091 * qla2x00_wait_for_hba_online
fa2a1ce5 1092 * Wait till the HBA is online after going through
1da177e4
LT		 1093 * <= MAX_RETRIES_OF_ISP_ABORT or
1094 * finally HBA is disabled ie marked offline
1095 *
1096 * Input:
1097 * ha - pointer to host adapter structure
fa2a1ce5
AV		 1098 *
1099 * Note:
1da177e4
LT		 1100 * Does context switching-Release SPIN_LOCK
1101 * (if any) before calling this routine.
1102 *
1103 * Return:
1104 * Success (Adapter is online) : 0
1105 * Failed (Adapter is offline/disabled) : 1
1106 */
854165f4 1107int
e315cd28 1108qla2x00_wait_for_hba_online(scsi_qla_host_t *vha)
1da177e4 1109{
fca29703
AV		 1110 int return_status;
1111 unsigned long wait_online;
e315cd28
AC		 1112 struct qla_hw_data *ha = vha->hw;
1113 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4 1114
fa2a1ce5 1115 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ);
e315cd28
AC		 1116 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
1117 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
1118 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
1119 ha->dpc_active) && time_before(jiffies, wait_online)) {
1da177e4
LT		 1120
1121 msleep(1000);
1122 }
e315cd28 1123 if (base_vha->flags.online)
fa2a1ce5 1124 return_status = QLA_SUCCESS;
1da177e4
LT		 1125 else
1126 return_status = QLA_FUNCTION_FAILED;
1127
1da177e4
LT		 1128 return (return_status);
1129}
1130
726b8548
QT		 1131static inline int test_fcport_count(scsi_qla_host_t *vha)
1132{
1133 struct qla_hw_data *ha = vha->hw;
1134 unsigned long flags;
1135 int res;
1136
1137 spin_lock_irqsave(&ha->tgt.sess_lock, flags);
83548fe2
QT		 1138 ql_dbg(ql_dbg_init, vha, 0x00ec,
1139 "tgt %p, fcport_count=%d\n",
1140 vha, vha->fcport_count);
726b8548
QT		 1141 res = (vha->fcport_count == 0);
1142 spin_unlock_irqrestore(&ha->tgt.sess_lock, flags);
1143
1144 return res;
1145}
1146
1147/*
1148 * qla2x00_wait_for_sess_deletion can only be called from remove_one.
1149 * it has dependency on UNLOADING flag to stop device discovery
1150 */
efa93f48 1151void
726b8548
QT		 1152qla2x00_wait_for_sess_deletion(scsi_qla_host_t *vha)
1153{
1154 qla2x00_mark_all_devices_lost(vha, 0);
1155
b85e0957 1156 wait_event_timeout(vha->fcport_waitQ, test_fcport_count(vha), 10*HZ);
726b8548
QT		 1157}
1158
86fbee86 1159/*
638a1a01
SC		 1160 * qla2x00_wait_for_hba_ready
1161 * Wait till the HBA is ready before doing driver unload
86fbee86
LC		 1162 *
1163 * Input:
1164 * ha - pointer to host adapter structure
1165 *
1166 * Note:
1167 * Does context switching-Release SPIN_LOCK
1168 * (if any) before calling this routine.
1169 *
86fbee86 1170 */
638a1a01
SC		 1171static void
1172qla2x00_wait_for_hba_ready(scsi_qla_host_t *vha)
86fbee86 1173{
86fbee86 1174 struct qla_hw_data *ha = vha->hw;
783e0dc4 1175 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
86fbee86 1176
1d483901
DC		 1177 while ((qla2x00_reset_active(vha) || ha->dpc_active ||
1178 ha->flags.mbox_busy) ||
1179 test_bit(FX00_RESET_RECOVERY, &vha->dpc_flags) ||
1180 test_bit(FX00_TARGET_SCAN, &vha->dpc_flags)) {
1181 if (test_bit(UNLOADING, &base_vha->dpc_flags))
1182 break;
86fbee86 1183 msleep(1000);
783e0dc4 1184 }
86fbee86
LC		 1185}
1186
2533cf67
LC		 1187int
1188qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha)
1189{
1190 int return_status;
1191 unsigned long wait_reset;
1192 struct qla_hw_data *ha = vha->hw;
1193 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1194
1195 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ);
1196 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
1197 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
1198 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
1199 ha->dpc_active) && time_before(jiffies, wait_reset)) {
1200
1201 msleep(1000);
1202
1203 if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) &&
1204 ha->flags.chip_reset_done)
1205 break;
1206 }
1207 if (ha->flags.chip_reset_done)
1208 return_status = QLA_SUCCESS;
1209 else
1210 return_status = QLA_FUNCTION_FAILED;
1211
1212 return return_status;
1213}
1214
585def9b 1215static int
083a469d
GM		 1216sp_get(struct srb *sp)
1217{
845bbb09 1218 if (!refcount_inc_not_zero((refcount_t *)&sp->ref_count))
585def9b
QT		 1219 /* kref get fail */
1220 return ENXIO;
1221 else
1222 return 0;
083a469d
GM		 1223}
1224
a465537a
SC		 1225#define ISP_REG_DISCONNECT 0xffffffffU
1226/**************************************************************************
1227* qla2x00_isp_reg_stat
1228*
1229* Description:
1230* Read the host status register of ISP before aborting the command.
1231*
1232* Input:
1233* ha = pointer to host adapter structure.
1234*
1235*
1236* Returns:
1237* Either true or false.
1238*
1239* Note: Return true if there is register disconnect.
1240**************************************************************************/
1241static inline
1242uint32_t qla2x00_isp_reg_stat(struct qla_hw_data *ha)
1243{
1244 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
bf6061b1 1245 struct device_reg_82xx __iomem *reg82 = &ha->iobase->isp82;
a465537a 1246
bf6061b1
SC		 1247 if (IS_P3P_TYPE(ha))
1248 return ((RD_REG_DWORD(&reg82->host_int)) == ISP_REG_DISCONNECT);
1249 else
1250 return ((RD_REG_DWORD(&reg->host_status)) ==
1251 ISP_REG_DISCONNECT);
a465537a
SC		 1252}
1253
1da177e4
LT		 1254/**************************************************************************
1255* qla2xxx_eh_abort
1256*
1257* Description:
1258* The abort function will abort the specified command.
1259*
1260* Input:
1261* cmd = Linux SCSI command packet to be aborted.
1262*
1263* Returns:
1264* Either SUCCESS or FAILED.
1265*
1266* Note:
2ea00202 1267* Only return FAILED if command not returned by firmware.
1da177e4 1268**************************************************************************/
e5f82ab8 1269static int
1da177e4
LT		 1270qla2xxx_eh_abort(struct scsi_cmnd *cmd)
1271{
e315cd28 1272 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
8dd9593c 1273 DECLARE_COMPLETION_ONSTACK(comp);
f4f051eb 1274 srb_t *sp;
4e98d3b8 1275 int ret;
9cb78c16
HR		 1276 unsigned int id;
1277 uint64_t lun;
18e144d3 1278 unsigned long flags;
219d27d7 1279 int rval;
e315cd28 1280 struct qla_hw_data *ha = vha->hw;
585def9b 1281 struct qla_qpair *qpair;
1da177e4 1282
a465537a
SC		 1283 if (qla2x00_isp_reg_stat(ha)) {
1284 ql_log(ql_log_info, vha, 0x8042,
1285 "PCI/Register disconnect, exiting.\n");
1286 return FAILED;
1287 }
1da177e4 1288
4e98d3b8
AV		 1289 ret = fc_block_scsi_eh(cmd);
1290 if (ret != 0)
1291 return ret;
4e98d3b8 1292
170babc3 1293 sp = (srb_t *) CMD_SP(cmd);
585def9b
QT		 1294 if (!sp)
1295 return SUCCESS;
1296
1297 qpair = sp->qpair;
1298 if (!qpair)
1299 return SUCCESS;
1300
7f4374e6
QT		 1301 if (sp->fcport && sp->fcport->deleted)
1302 return SUCCESS;
1303
585def9b 1304 spin_lock_irqsave(qpair->qp_lock_ptr, flags);
219d27d7 1305 if (sp->type != SRB_SCSI_CMD || GET_CMD_SP(sp) != cmd) {
585def9b
QT		 1306 /* there's a chance an interrupt could clear
1307 the ptr as part of done & free */
1308 spin_unlock_irqrestore(qpair->qp_lock_ptr, flags);
170babc3
MC		 1309 return SUCCESS;
1310 }
1da177e4 1311
8dd9593c 1312 /* Get a reference to the sp and drop the lock. */
585def9b
QT		 1313 if (sp_get(sp)){
1314 /* ref_count is already 0 */
1315 spin_unlock_irqrestore(qpair->qp_lock_ptr, flags);
170babc3
MC		 1316 return SUCCESS;
1317 }
585def9b
QT		 1318 spin_unlock_irqrestore(qpair->qp_lock_ptr, flags);
1319
1320 id = cmd->device->id;
1321 lun = cmd->device->lun;
1da177e4 1322
7c3df132 1323 ql_dbg(ql_dbg_taskm, vha, 0x8002,
c7bc4cae
CD		 1324 "Aborting from RISC nexus=%ld:%d:%llu sp=%p cmd=%p handle=%x\n",
1325 vha->host_no, id, lun, sp, cmd, sp->handle);
17d98630 1326
f934c9d0 1327 rval = ha->isp_ops->abort_command(sp);
219d27d7
BVA		 1328 ql_dbg(ql_dbg_taskm, vha, 0x8003,
1329 "Abort command mbx cmd=%p, rval=%x.\n", cmd, rval);
f934c9d0 1330
219d27d7
BVA		 1331 switch (rval) {
1332 case QLA_SUCCESS:
711a08d7 1333 /*
219d27d7
BVA		 1334 * The command has been aborted. That means that the firmware
1335 * won't report a completion.
711a08d7 1336 */
219d27d7
BVA		 1337 sp->done(sp, DID_ABORT << 16);
1338 ret = SUCCESS;
1339 break;
8dd9593c
BVA		 1340 case QLA_FUNCTION_PARAMETER_ERROR: {
1341 /* Wait for the command completion. */
1342 uint32_t ratov = ha->r_a_tov/10;
1343 uint32_t ratov_j = msecs_to_jiffies(4 * ratov * 1000);
1344
1345 WARN_ON_ONCE(sp->comp);
1346 sp->comp = &comp;
1347 if (!wait_for_completion_timeout(&comp, ratov_j)) {
1348 ql_dbg(ql_dbg_taskm, vha, 0xffff,
1349 "%s: Abort wait timer (4 * R_A_TOV[%d]) expired\n",
1350 __func__, ha->r_a_tov);
1351 ret = FAILED;
1352 } else {
1353 ret = SUCCESS;
1354 }
1355 break;
1356 }
219d27d7
BVA		 1357 default:
1358 /*
1359 * Either abort failed or abort and completion raced. Let
1360 * the SCSI core retry the abort in the former case.
1361 */
1362 ret = FAILED;
1363 break;
1da177e4 1364 }
219d27d7 1365
8dd9593c
BVA		 1366 sp->comp = NULL;
1367 atomic_dec(&sp->ref_count);
7c3df132 1368 ql_log(ql_log_info, vha, 0x801c,
219d27d7
BVA		 1369 "Abort command issued nexus=%ld:%d:%llu -- %x.\n",
1370 vha->host_no, id, lun, ret);
1da177e4 1371
f4f051eb 1372 return ret;
1373}
1da177e4 1374
fcef0893
BVA		 1375/*
1376 * Returns: QLA_SUCCESS or QLA_FUNCTION_FAILED.
1377 */
4d78c973 1378int
e315cd28 1379qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t,
9cb78c16 1380 uint64_t l, enum nexus_wait_type type)
f4f051eb 1381{
17d98630 1382 int cnt, match, status;
18e144d3 1383 unsigned long flags;
e315cd28 1384 struct qla_hw_data *ha = vha->hw;
73208dfd 1385 struct req_que *req;
4d78c973 1386 srb_t *sp;
9ba56b95 1387 struct scsi_cmnd *cmd;
1da177e4 1388
523ec773 1389 status = QLA_SUCCESS;
17d98630 1390
e315cd28 1391 spin_lock_irqsave(&ha->hardware_lock, flags);
67c2e93a 1392 req = vha->req;
17d98630 1393 for (cnt = 1; status == QLA_SUCCESS &&
8d93f550 1394 cnt < req->num_outstanding_cmds; cnt++) {
17d98630
AC		 1395 sp = req->outstanding_cmds[cnt];
1396 if (!sp)
523ec773 1397 continue;
9ba56b95 1398 if (sp->type != SRB_SCSI_CMD)
cf53b069 1399 continue;
25ff6af1 1400 if (vha->vp_idx != sp->vha->vp_idx)
17d98630
AC		 1401 continue;
1402 match = 0;
9ba56b95 1403 cmd = GET_CMD_SP(sp);
17d98630
AC		 1404 switch (type) {
1405 case WAIT_HOST:
1406 match = 1;
1407 break;
1408 case WAIT_TARGET:
9ba56b95 1409 match = cmd->device->id == t;
17d98630
AC		 1410 break;
1411 case WAIT_LUN:
9ba56b95
GM		 1412 match = (cmd->device->id == t &&
1413 cmd->device->lun == l);
17d98630 1414 break;
73208dfd 1415 }
17d98630
AC		 1416 if (!match)
1417 continue;
1418
1419 spin_unlock_irqrestore(&ha->hardware_lock, flags);
9ba56b95 1420 status = qla2x00_eh_wait_on_command(cmd);
17d98630 1421 spin_lock_irqsave(&ha->hardware_lock, flags);
1da177e4 1422 }
e315cd28 1423 spin_unlock_irqrestore(&ha->hardware_lock, flags);
523ec773
AV		 1424
1425 return status;
1da177e4
LT		 1426}
1427
523ec773
AV		 1428static char *reset_errors[] = {
1429 "HBA not online",
1430 "HBA not ready",
1431 "Task management failed",
1432 "Waiting for command completions",
1433};
1da177e4 1434
e5f82ab8 1435static int
523ec773 1436__qla2xxx_eh_generic_reset(char *name, enum nexus_wait_type type,
9cb78c16 1437 struct scsi_cmnd *cmd, int (*do_reset)(struct fc_port *, uint64_t, int))
1da177e4 1438{
e315cd28 1439 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
bdf79621 1440 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
523ec773 1441 int err;
1da177e4 1442
7c3df132 1443 if (!fcport) {
523ec773 1444 return FAILED;
7c3df132 1445 }
1da177e4 1446
4e98d3b8
AV		 1447 err = fc_block_scsi_eh(cmd);
1448 if (err != 0)
1449 return err;
1450
7f4374e6
QT		 1451 if (fcport->deleted)
1452 return SUCCESS;
1453
7c3df132 1454 ql_log(ql_log_info, vha, 0x8009,
9cb78c16 1455 "%s RESET ISSUED nexus=%ld:%d:%llu cmd=%p.\n", name, vha->host_no,
7c3df132 1456 cmd->device->id, cmd->device->lun, cmd);
1da177e4 1457
523ec773 1458 err = 0;
7c3df132
SK		 1459 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1460 ql_log(ql_log_warn, vha, 0x800a,
1461 "Wait for hba online failed for cmd=%p.\n", cmd);
523ec773 1462 goto eh_reset_failed;
7c3df132 1463 }
523ec773 1464 err = 2;
ac444b4f 1465 if (do_reset(fcport, cmd->device->lun, 1)
7c3df132
SK		 1466 != QLA_SUCCESS) {
1467 ql_log(ql_log_warn, vha, 0x800c,
1468 "do_reset failed for cmd=%p.\n", cmd);
523ec773 1469 goto eh_reset_failed;
7c3df132 1470 }
523ec773 1471 err = 3;
e315cd28 1472 if (qla2x00_eh_wait_for_pending_commands(vha, cmd->device->id,
7c3df132
SK		 1473 cmd->device->lun, type) != QLA_SUCCESS) {
1474 ql_log(ql_log_warn, vha, 0x800d,
d6a03581 1475 "wait for pending cmds failed for cmd=%p.\n", cmd);
523ec773 1476 goto eh_reset_failed;
7c3df132 1477 }
523ec773 1478
7c3df132 1479 ql_log(ql_log_info, vha, 0x800e,
9cb78c16 1480 "%s RESET SUCCEEDED nexus:%ld:%d:%llu cmd=%p.\n", name,
cfb0919c 1481 vha->host_no, cmd->device->id, cmd->device->lun, cmd);
523ec773
AV		 1482
1483 return SUCCESS;
1484
4d78c973 1485eh_reset_failed:
7c3df132 1486 ql_log(ql_log_info, vha, 0x800f,
9cb78c16 1487 "%s RESET FAILED: %s nexus=%ld:%d:%llu cmd=%p.\n", name,
cfb0919c
CD		 1488 reset_errors[err], vha->host_no, cmd->device->id, cmd->device->lun,
1489 cmd);
523ec773
AV		 1490 return FAILED;
1491}
1da177e4 1492
523ec773
AV		 1493static int
1494qla2xxx_eh_device_reset(struct scsi_cmnd *cmd)
1495{
e315cd28
AC		 1496 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1497 struct qla_hw_data *ha = vha->hw;
1da177e4 1498
a465537a
SC		 1499 if (qla2x00_isp_reg_stat(ha)) {
1500 ql_log(ql_log_info, vha, 0x803e,
1501 "PCI/Register disconnect, exiting.\n");
1502 return FAILED;
1503 }
1504
523ec773
AV		 1505 return __qla2xxx_eh_generic_reset("DEVICE", WAIT_LUN, cmd,
1506 ha->isp_ops->lun_reset);
1da177e4
LT		 1507}
1508
1da177e4 1509static int
523ec773 1510qla2xxx_eh_target_reset(struct scsi_cmnd *cmd)
1da177e4 1511{
e315cd28
AC		 1512 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1513 struct qla_hw_data *ha = vha->hw;
1da177e4 1514
a465537a
SC		 1515 if (qla2x00_isp_reg_stat(ha)) {
1516 ql_log(ql_log_info, vha, 0x803f,
1517 "PCI/Register disconnect, exiting.\n");
1518 return FAILED;
1519 }
1520
523ec773
AV		 1521 return __qla2xxx_eh_generic_reset("TARGET", WAIT_TARGET, cmd,
1522 ha->isp_ops->target_reset);
1da177e4
LT		 1523}
1524
1da177e4
LT		 1525/**************************************************************************
1526* qla2xxx_eh_bus_reset
1527*
1528* Description:
1529* The bus reset function will reset the bus and abort any executing
1530* commands.
1531*
1532* Input:
1533* cmd = Linux SCSI command packet of the command that cause the
1534* bus reset.
1535*
1536* Returns:
1537* SUCCESS/FAILURE (defined as macro in scsi.h).
1538*
1539**************************************************************************/
e5f82ab8 1540static int
1da177e4
LT		 1541qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd)
1542{
e315cd28 1543 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
bdf79621 1544 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
2c3dfe3f 1545 int ret = FAILED;
9cb78c16
HR		 1546 unsigned int id;
1547 uint64_t lun;
a465537a
SC		 1548 struct qla_hw_data *ha = vha->hw;
1549
1550 if (qla2x00_isp_reg_stat(ha)) {
1551 ql_log(ql_log_info, vha, 0x8040,
1552 "PCI/Register disconnect, exiting.\n");
1553 return FAILED;
1554 }
f4f051eb 1555
f4f051eb 1556 id = cmd->device->id;
1557 lun = cmd->device->lun;
1da177e4 1558
7c3df132 1559 if (!fcport) {
f4f051eb 1560 return ret;
7c3df132 1561 }
1da177e4 1562
4e98d3b8
AV		 1563 ret = fc_block_scsi_eh(cmd);
1564 if (ret != 0)
1565 return ret;
1566 ret = FAILED;
1567
7f4374e6
QT		 1568 if (qla2x00_chip_is_down(vha))
1569 return ret;
1570
7c3df132 1571 ql_log(ql_log_info, vha, 0x8012,
9cb78c16 1572 "BUS RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun);
1da177e4 1573
e315cd28 1574 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
7c3df132
SK		 1575 ql_log(ql_log_fatal, vha, 0x8013,
1576 "Wait for hba online failed board disabled.\n");
f4f051eb 1577 goto eh_bus_reset_done;
1da177e4
LT		 1578 }
1579
ad537689
SK		 1580 if (qla2x00_loop_reset(vha) == QLA_SUCCESS)
1581 ret = SUCCESS;
1582
f4f051eb 1583 if (ret == FAILED)
1584 goto eh_bus_reset_done;
1da177e4 1585
9a41a62b 1586 /* Flush outstanding commands. */
4d78c973 1587 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) !=
7c3df132
SK		 1588 QLA_SUCCESS) {
1589 ql_log(ql_log_warn, vha, 0x8014,
1590 "Wait for pending commands failed.\n");
9a41a62b 1591 ret = FAILED;
7c3df132 1592 }
1da177e4 1593
f4f051eb 1594eh_bus_reset_done:
7c3df132 1595 ql_log(ql_log_warn, vha, 0x802b,
9cb78c16 1596 "BUS RESET %s nexus=%ld:%d:%llu.\n",
d6a03581 1597 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1da177e4 1598
f4f051eb 1599 return ret;
1da177e4
LT		 1600}
1601
1602/**************************************************************************
1603* qla2xxx_eh_host_reset
1604*
1605* Description:
1606* The reset function will reset the Adapter.
1607*
1608* Input:
1609* cmd = Linux SCSI command packet of the command that cause the
1610* adapter reset.
1611*
1612* Returns:
1613* Either SUCCESS or FAILED.
1614*
1615* Note:
1616**************************************************************************/
e5f82ab8 1617static int
1da177e4
LT		 1618qla2xxx_eh_host_reset(struct scsi_cmnd *cmd)
1619{
e315cd28 1620 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
e315cd28 1621 struct qla_hw_data *ha = vha->hw;
2c3dfe3f 1622 int ret = FAILED;
9cb78c16
HR		 1623 unsigned int id;
1624 uint64_t lun;
e315cd28 1625 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4 1626
a465537a
SC		 1627 if (qla2x00_isp_reg_stat(ha)) {
1628 ql_log(ql_log_info, vha, 0x8041,
1629 "PCI/Register disconnect, exiting.\n");
1630 schedule_work(&ha->board_disable);
1631 return SUCCESS;
1632 }
1633
f4f051eb 1634 id = cmd->device->id;
1635 lun = cmd->device->lun;
f4f051eb 1636
7c3df132 1637 ql_log(ql_log_info, vha, 0x8018,
9cb78c16 1638 "ADAPTER RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun);
1da177e4 1639
63ee7072
CD		 1640 /*
1641 * No point in issuing another reset if one is active. Also do not
1642 * attempt a reset if we are updating flash.
1643 */
1644 if (qla2x00_reset_active(vha) || ha->optrom_state != QLA_SWAITING)
f4f051eb 1645 goto eh_host_reset_lock;
1da177e4 1646
e315cd28
AC		 1647 if (vha != base_vha) {
1648 if (qla2x00_vp_abort_isp(vha))
f4f051eb 1649 goto eh_host_reset_lock;
e315cd28 1650 } else {
7ec0effd 1651 if (IS_P3P_TYPE(vha->hw)) {
a9083016
GM		 1652 if (!qla82xx_fcoe_ctx_reset(vha)) {
1653 /* Ctx reset success */
1654 ret = SUCCESS;
1655 goto eh_host_reset_lock;
1656 }
1657 /* fall thru if ctx reset failed */
1658 }
68ca949c
AC		 1659 if (ha->wq)
1660 flush_workqueue(ha->wq);
1661
e315cd28 1662 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
a9083016 1663 if (ha->isp_ops->abort_isp(base_vha)) {
e315cd28
AC		 1664 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1665 /* failed. schedule dpc to try */
1666 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
1667
7c3df132
SK		 1668 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1669 ql_log(ql_log_warn, vha, 0x802a,
1670 "wait for hba online failed.\n");
e315cd28 1671 goto eh_host_reset_lock;
7c3df132 1672 }
e315cd28
AC		 1673 }
1674 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
fa2a1ce5 1675 }
1da177e4 1676
e315cd28 1677 /* Waiting for command to be returned to OS.*/
4d78c973 1678 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) ==
e315cd28 1679 QLA_SUCCESS)
f4f051eb 1680 ret = SUCCESS;
1da177e4 1681
f4f051eb 1682eh_host_reset_lock:
cfb0919c 1683 ql_log(ql_log_info, vha, 0x8017,
9cb78c16 1684 "ADAPTER RESET %s nexus=%ld:%d:%llu.\n",
cfb0919c 1685 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1da177e4 1686
f4f051eb 1687 return ret;
1688}
1da177e4
LT		 1689
1690/*
1691* qla2x00_loop_reset
1692* Issue loop reset.
1693*
1694* Input:
1695* ha = adapter block pointer.
1696*
1697* Returns:
1698* 0 = success
1699*/
a4722cf2 1700int
e315cd28 1701qla2x00_loop_reset(scsi_qla_host_t *vha)
1da177e4 1702{
0c8c39af 1703 int ret;
bdf79621 1704 struct fc_port *fcport;
e315cd28 1705 struct qla_hw_data *ha = vha->hw;
1da177e4 1706
5854771e
AB		 1707 if (IS_QLAFX00(ha)) {
1708 return qlafx00_loop_reset(vha);
1709 }
1710
f4c496c1 1711 if (ql2xtargetreset == 1 && ha->flags.enable_target_reset) {
55e5ed27
AV		 1712 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1713 if (fcport->port_type != FCT_TARGET)
1714 continue;
1715
1716 ret = ha->isp_ops->target_reset(fcport, 0, 0);
1717 if (ret != QLA_SUCCESS) {
7c3df132 1718 ql_dbg(ql_dbg_taskm, vha, 0x802c,
5854771e 1719 "Bus Reset failed: Reset=%d "
7c3df132 1720 "d_id=%x.\n", ret, fcport->d_id.b24);
55e5ed27
AV		 1721 }
1722 }
1723 }
1724
8ae6d9c7 1725
6246b8a1 1726 if (ha->flags.enable_lip_full_login && !IS_CNA_CAPABLE(ha)) {
0b7e7c53
AV		 1727 atomic_set(&vha->loop_state, LOOP_DOWN);
1728 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
1729 qla2x00_mark_all_devices_lost(vha, 0);
e315cd28 1730 ret = qla2x00_full_login_lip(vha);
0c8c39af 1731 if (ret != QLA_SUCCESS) {
7c3df132
SK		 1732 ql_dbg(ql_dbg_taskm, vha, 0x802d,
1733 "full_login_lip=%d.\n", ret);
749af3d5 1734 }
0c8c39af
AV		 1735 }
1736
0d6e61bc 1737 if (ha->flags.enable_lip_reset) {
e315cd28 1738 ret = qla2x00_lip_reset(vha);
ad537689 1739 if (ret != QLA_SUCCESS)
7c3df132
SK		 1740 ql_dbg(ql_dbg_taskm, vha, 0x802e,
1741 "lip_reset failed (%d).\n", ret);
1da177e4
LT		 1742 }
1743
1da177e4 1744 /* Issue marker command only when we are going to start the I/O */
e315cd28 1745 vha->marker_needed = 1;
1da177e4 1746
0c8c39af 1747 return QLA_SUCCESS;
1da177e4
LT		 1748}
1749
c4e521b6
BVA		 1750static void qla2x00_abort_srb(struct qla_qpair *qp, srb_t *sp, const int res,
1751 unsigned long *flags)
1752 __releases(qp->qp_lock_ptr)
1753 __acquires(qp->qp_lock_ptr)
1754{
219d27d7 1755 DECLARE_COMPLETION_ONSTACK(comp);
c4e521b6
BVA		 1756 scsi_qla_host_t *vha = qp->vha;
1757 struct qla_hw_data *ha = vha->hw;
219d27d7 1758 int rval;
c4e521b6 1759
219d27d7
BVA		 1760 if (sp_get(sp))
1761 return;
1762
1763 if (sp->type == SRB_NVME_CMD || sp->type == SRB_NVME_LS ||
1764 (sp->type == SRB_SCSI_CMD && !ha->flags.eeh_busy &&
1765 !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) &&
1766 !qla2x00_isp_reg_stat(ha))) {
1767 sp->comp = &comp;
219d27d7 1768 spin_unlock_irqrestore(qp->qp_lock_ptr, *flags);
5589b08e 1769 rval = ha->isp_ops->abort_command(sp);
219d27d7
BVA		 1770
1771 switch (rval) {
1772 case QLA_SUCCESS:
1773 sp->done(sp, res);
1774 break;
1775 case QLA_FUNCTION_PARAMETER_ERROR:
1776 wait_for_completion(&comp);
1777 break;
c4e521b6 1778 }
219d27d7
BVA		 1779
1780 spin_lock_irqsave(qp->qp_lock_ptr, *flags);
1781 sp->comp = NULL;
c4e521b6 1782 }
d2d2b5a5
BVA		 1783
1784 atomic_dec(&sp->ref_count);
c4e521b6
BVA		 1785}
1786
bbead493
QT		 1787static void
1788__qla2x00_abort_all_cmds(struct qla_qpair *qp, int res)
df4bf0bb 1789{
eb023220 1790 int cnt;
df4bf0bb
AV		 1791 unsigned long flags;
1792 srb_t *sp;
bbead493 1793 scsi_qla_host_t *vha = qp->vha;
e315cd28 1794 struct qla_hw_data *ha = vha->hw;
73208dfd 1795 struct req_que *req;
c5419e26
QT		 1796 struct qla_tgt *tgt = vha->vha_tgt.qla_tgt;
1797 struct qla_tgt_cmd *cmd;
c0cb4496 1798
6a2cf8d3
BK		 1799 if (!ha->req_q_map)
1800 return;
bbead493
QT		 1801 spin_lock_irqsave(qp->qp_lock_ptr, flags);
1802 req = qp->req;
1803 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) {
1804 sp = req->outstanding_cmds[cnt];
1805 if (sp) {
1806 req->outstanding_cmds[cnt] = NULL;
6b0431d6
QT		 1807 switch (sp->cmd_type) {
1808 case TYPE_SRB:
c4e521b6 1809 qla2x00_abort_srb(qp, sp, res, &flags);
585def9b
QT		 1810 break;
1811 case TYPE_TGT_CMD:
bbead493
QT		 1812 if (!vha->hw->tgt.tgt_ops || !tgt ||
1813 qla_ini_mode_enabled(vha)) {
585def9b
QT		 1814 ql_dbg(ql_dbg_tgt_mgt, vha, 0xf003,
1815 "HOST-ABORT-HNDLR: dpc_flags=%lx. Target mode disabled\n",
1816 vha->dpc_flags);
bbead493 1817 continue;
c733ab35 1818 }
bbead493 1819 cmd = (struct qla_tgt_cmd *)sp;
aefed3e5 1820 cmd->aborted = 1;
585def9b
QT		 1821 break;
1822 case TYPE_TGT_TMCMD:
aefed3e5 1823 /* Skip task management functions. */
585def9b
QT		 1824 break;
1825 default:
1826 break;
73208dfd 1827 }
df4bf0bb
AV		 1828 }
1829 }
bbead493
QT		 1830 spin_unlock_irqrestore(qp->qp_lock_ptr, flags);
1831}
1832
1833void
1834qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res)
1835{
1836 int que;
1837 struct qla_hw_data *ha = vha->hw;
1838
26a77799
AV		 1839 /* Continue only if initialization complete. */
1840 if (!ha->base_qpair)
1841 return;
bbead493
QT		 1842 __qla2x00_abort_all_cmds(ha->base_qpair, res);
1843
26a77799
AV		 1844 if (!ha->queue_pair_map)
1845 return;
bbead493
QT		 1846 for (que = 0; que < ha->max_qpairs; que++) {
1847 if (!ha->queue_pair_map[que])
1848 continue;
1849
1850 __qla2x00_abort_all_cmds(ha->queue_pair_map[que], res);
1851 }
df4bf0bb
AV		 1852}
1853
f4f051eb 1854static int
1855qla2xxx_slave_alloc(struct scsi_device *sdev)
1da177e4 1856{
bdf79621 1857 struct fc_rport *rport = starget_to_rport(scsi_target(sdev));
1da177e4 1858
19a7b4ae 1859 if (!rport || fc_remote_port_chkready(rport))
f4f051eb 1860 return -ENXIO;
bdf79621 1861
19a7b4ae 1862 sdev->hostdata = *(fc_port_t **)rport->dd_data;
1da177e4 1863
f4f051eb 1864 return 0;
1865}
1da177e4 1866
f4f051eb 1867static int
1868qla2xxx_slave_configure(struct scsi_device *sdev)
1869{
e315cd28 1870 scsi_qla_host_t *vha = shost_priv(sdev->host);
2afa19a9 1871 struct req_que *req = vha->req;
8482e118 1872
9e522cd8
AE		 1873 if (IS_T10_PI_CAPABLE(vha->hw))
1874 blk_queue_update_dma_alignment(sdev->request_queue, 0x7);
1875
db5ed4df 1876 scsi_change_queue_depth(sdev, req->max_q_depth);
f4f051eb 1877 return 0;
1878}
1da177e4 1879
f4f051eb 1880static void
1881qla2xxx_slave_destroy(struct scsi_device *sdev)
1882{
1883 sdev->hostdata = NULL;
1da177e4
LT		 1884}
1885
1886/**
1887 * qla2x00_config_dma_addressing() - Configure OS DMA addressing method.
1888 * @ha: HA context
1889 *
1890 * At exit, the @ha's flags.enable_64bit_addressing set to indicated
1891 * supported addressing method.
1892 */
1893static void
53303c42 1894qla2x00_config_dma_addressing(struct qla_hw_data *ha)
1da177e4 1895{
7524f9b9 1896 /* Assume a 32bit DMA mask. */
1da177e4 1897 ha->flags.enable_64bit_addressing = 0;
1da177e4 1898
6a35528a 1899 if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) {
7524f9b9
AV		 1900 /* Any upper-dword bits set? */
1901 if (MSD(dma_get_required_mask(&ha->pdev->dev)) &&
6a35528a 1902 !pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(64))) {
7524f9b9 1903 /* Ok, a 64bit DMA mask is applicable. */
1da177e4 1904 ha->flags.enable_64bit_addressing = 1;
fd34f556
AV		 1905 ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64;
1906 ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64;
7524f9b9 1907 return;
1da177e4 1908 }
1da177e4 1909 }
7524f9b9 1910
284901a9
YH		 1911 dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32));
1912 pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(32));
1da177e4
LT		 1913}
1914
fd34f556 1915static void
e315cd28 1916qla2x00_enable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1917{
1918 unsigned long flags = 0;
1919 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1920
1921 spin_lock_irqsave(&ha->hardware_lock, flags);
1922 ha->interrupts_on = 1;
1923 /* enable risc and host interrupts */
1924 WRT_REG_WORD(&reg->ictrl, ICR_EN_INT | ICR_EN_RISC);
1925 RD_REG_WORD(&reg->ictrl);
1926 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1927
1928}
1929
1930static void
e315cd28 1931qla2x00_disable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1932{
1933 unsigned long flags = 0;
1934 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1935
1936 spin_lock_irqsave(&ha->hardware_lock, flags);
1937 ha->interrupts_on = 0;
1938 /* disable risc and host interrupts */
1939 WRT_REG_WORD(&reg->ictrl, 0);
1940 RD_REG_WORD(&reg->ictrl);
1941 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1942}
1943
1944static void
e315cd28 1945qla24xx_enable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1946{
1947 unsigned long flags = 0;
1948 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1949
1950 spin_lock_irqsave(&ha->hardware_lock, flags);
1951 ha->interrupts_on = 1;
1952 WRT_REG_DWORD(&reg->ictrl, ICRX_EN_RISC_INT);
1953 RD_REG_DWORD(&reg->ictrl);
1954 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1955}
1956
1957static void
e315cd28 1958qla24xx_disable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1959{
1960 unsigned long flags = 0;
1961 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1962
124f85e6
AV		 1963 if (IS_NOPOLLING_TYPE(ha))
1964 return;
fd34f556
AV		 1965 spin_lock_irqsave(&ha->hardware_lock, flags);
1966 ha->interrupts_on = 0;
1967 WRT_REG_DWORD(&reg->ictrl, 0);
1968 RD_REG_DWORD(&reg->ictrl);
1969 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1970}
1971
706f457d
GM		 1972static int
1973qla2x00_iospace_config(struct qla_hw_data *ha)
1974{
1975 resource_size_t pio;
1976 uint16_t msix;
706f457d 1977
706f457d
GM		 1978 if (pci_request_selected_regions(ha->pdev, ha->bars,
1979 QLA2XXX_DRIVER_NAME)) {
1980 ql_log_pci(ql_log_fatal, ha->pdev, 0x0011,
1981 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
1982 pci_name(ha->pdev));
1983 goto iospace_error_exit;
1984 }
1985 if (!(ha->bars & 1))
1986 goto skip_pio;
1987
1988 /* We only need PIO for Flash operations on ISP2312 v2 chips. */
1989 pio = pci_resource_start(ha->pdev, 0);
1990 if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) {
1991 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
1992 ql_log_pci(ql_log_warn, ha->pdev, 0x0012,
1993 "Invalid pci I/O region size (%s).\n",
1994 pci_name(ha->pdev));
1995 pio = 0;
1996 }
1997 } else {
1998 ql_log_pci(ql_log_warn, ha->pdev, 0x0013,
1999 "Region #0 no a PIO resource (%s).\n",
2000 pci_name(ha->pdev));
2001 pio = 0;
2002 }
2003 ha->pio_address = pio;
2004 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014,
2005 "PIO address=%llu.\n",
2006 (unsigned long long)ha->pio_address);
2007
2008skip_pio:
2009 /* Use MMIO operations for all accesses. */
2010 if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) {
2011 ql_log_pci(ql_log_fatal, ha->pdev, 0x0015,
2012 "Region #1 not an MMIO resource (%s), aborting.\n",
2013 pci_name(ha->pdev));
2014 goto iospace_error_exit;
2015 }
2016 if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) {
2017 ql_log_pci(ql_log_fatal, ha->pdev, 0x0016,
2018 "Invalid PCI mem region size (%s), aborting.\n",
2019 pci_name(ha->pdev));
2020 goto iospace_error_exit;
2021 }
2022
2023 ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN);
2024 if (!ha->iobase) {
2025 ql_log_pci(ql_log_fatal, ha->pdev, 0x0017,
2026 "Cannot remap MMIO (%s), aborting.\n",
2027 pci_name(ha->pdev));
2028 goto iospace_error_exit;
2029 }
2030
2031 /* Determine queue resources */
2032 ha->max_req_queues = ha->max_rsp_queues = 1;
f54f2cb5 2033 ha->msix_count = QLA_BASE_VECTORS;
c38d1baf
HM		 2034 if (!ql2xmqsupport || !ql2xnvmeenable ||
2035 (!IS_QLA25XX(ha) && !IS_QLA81XX(ha)))
706f457d
GM		 2036 goto mqiobase_exit;
2037
2038 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3),
2039 pci_resource_len(ha->pdev, 3));
2040 if (ha->mqiobase) {
2041 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018,
2042 "MQIO Base=%p.\n", ha->mqiobase);
2043 /* Read MSIX vector size of the board */
2044 pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix);
d7459527 2045 ha->msix_count = msix + 1;
706f457d 2046 /* Max queues are bounded by available msix vectors */
d7459527
MH		 2047 /* MB interrupt uses 1 vector */
2048 ha->max_req_queues = ha->msix_count - 1;
2049 ha->max_rsp_queues = ha->max_req_queues;
2050 /* Queue pairs is the max value minus the base queue pair */
2051 ha->max_qpairs = ha->max_rsp_queues - 1;
2052 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0188,
2053 "Max no of queues pairs: %d.\n", ha->max_qpairs);
2054
706f457d 2055 ql_log_pci(ql_log_info, ha->pdev, 0x001a,
d7459527 2056 "MSI-X vector count: %d.\n", ha->msix_count);
706f457d
GM		 2057 } else
2058 ql_log_pci(ql_log_info, ha->pdev, 0x001b,
2059 "BAR 3 not enabled.\n");
2060
2061mqiobase_exit:
706f457d 2062 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c,
f54f2cb5 2063 "MSIX Count: %d.\n", ha->msix_count);
706f457d
GM		 2064 return (0);
2065
2066iospace_error_exit:
2067 return (-ENOMEM);
2068}
2069
2070
6246b8a1
GM		 2071static int
2072qla83xx_iospace_config(struct qla_hw_data *ha)
2073{
2074 uint16_t msix;
6246b8a1
GM		 2075
2076 if (pci_request_selected_regions(ha->pdev, ha->bars,
2077 QLA2XXX_DRIVER_NAME)) {
2078 ql_log_pci(ql_log_fatal, ha->pdev, 0x0117,
2079 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
2080 pci_name(ha->pdev));
2081
2082 goto iospace_error_exit;
2083 }
2084
2085 /* Use MMIO operations for all accesses. */
2086 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) {
2087 ql_log_pci(ql_log_warn, ha->pdev, 0x0118,
2088 "Invalid pci I/O region size (%s).\n",
2089 pci_name(ha->pdev));
2090 goto iospace_error_exit;
2091 }
2092 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
2093 ql_log_pci(ql_log_warn, ha->pdev, 0x0119,
2094 "Invalid PCI mem region size (%s), aborting\n",
2095 pci_name(ha->pdev));
2096 goto iospace_error_exit;
2097 }
2098
2099 ha->iobase = ioremap(pci_resource_start(ha->pdev, 0), MIN_IOBASE_LEN);
2100 if (!ha->iobase) {
2101 ql_log_pci(ql_log_fatal, ha->pdev, 0x011a,
2102 "Cannot remap MMIO (%s), aborting.\n",
2103 pci_name(ha->pdev));
2104 goto iospace_error_exit;
2105 }
2106
2107 /* 64bit PCI BAR - BAR2 will correspoond to region 4 */
2108 /* 83XX 26XX always use MQ type access for queues
2109 * - mbar 2, a.k.a region 4 */
2110 ha->max_req_queues = ha->max_rsp_queues = 1;
f54f2cb5 2111 ha->msix_count = QLA_BASE_VECTORS;
6246b8a1
GM		 2112 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 4),
2113 pci_resource_len(ha->pdev, 4));
2114
2115 if (!ha->mqiobase) {
2116 ql_log_pci(ql_log_fatal, ha->pdev, 0x011d,
2117 "BAR2/region4 not enabled\n");
2118 goto mqiobase_exit;
2119 }
2120
2121 ha->msixbase = ioremap(pci_resource_start(ha->pdev, 2),
2122 pci_resource_len(ha->pdev, 2));
2123 if (ha->msixbase) {
2124 /* Read MSIX vector size of the board */
2125 pci_read_config_word(ha->pdev,
2126 QLA_83XX_PCI_MSIX_CONTROL, &msix);
e326d22a 2127 ha->msix_count = (msix & PCI_MSIX_FLAGS_QSIZE) + 1;
093df737
QT		 2128 /*
2129 * By default, driver uses at least two msix vectors
2130 * (default & rspq)
2131 */
c38d1baf 2132 if (ql2xmqsupport || ql2xnvmeenable) {
d7459527
MH		 2133 /* MB interrupt uses 1 vector */
2134 ha->max_req_queues = ha->msix_count - 1;
093df737
QT		 2135
2136 /* ATIOQ needs 1 vector. That's 1 less QPair */
2137 if (QLA_TGT_MODE_ENABLED())
2138 ha->max_req_queues--;
2139
d0d2c68b
MH		 2140 ha->max_rsp_queues = ha->max_req_queues;
2141
d7459527
MH		 2142 /* Queue pairs is the max value minus
2143 * the base queue pair */
2144 ha->max_qpairs = ha->max_req_queues - 1;
83548fe2 2145 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x00e3,
d7459527 2146 "Max no of queues pairs: %d.\n", ha->max_qpairs);
6246b8a1
GM		 2147 }
2148 ql_log_pci(ql_log_info, ha->pdev, 0x011c,
d7459527 2149 "MSI-X vector count: %d.\n", ha->msix_count);
6246b8a1
GM		 2150 } else
2151 ql_log_pci(ql_log_info, ha->pdev, 0x011e,
2152 "BAR 1 not enabled.\n");
2153
2154mqiobase_exit:
6246b8a1 2155 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011f,
f54f2cb5 2156 "MSIX Count: %d.\n", ha->msix_count);
6246b8a1
GM		 2157 return 0;
2158
2159iospace_error_exit:
2160 return -ENOMEM;
2161}
2162
fd34f556
AV		 2163static struct isp_operations qla2100_isp_ops = {
2164 .pci_config = qla2100_pci_config,
2165 .reset_chip = qla2x00_reset_chip,
2166 .chip_diag = qla2x00_chip_diag,
2167 .config_rings = qla2x00_config_rings,
2168 .reset_adapter = qla2x00_reset_adapter,
2169 .nvram_config = qla2x00_nvram_config,
2170 .update_fw_options = qla2x00_update_fw_options,
2171 .load_risc = qla2x00_load_risc,
2172 .pci_info_str = qla2x00_pci_info_str,
2173 .fw_version_str = qla2x00_fw_version_str,
2174 .intr_handler = qla2100_intr_handler,
2175 .enable_intrs = qla2x00_enable_intrs,
2176 .disable_intrs = qla2x00_disable_intrs,
2177 .abort_command = qla2x00_abort_command,
523ec773
AV		 2178 .target_reset = qla2x00_abort_target,
2179 .lun_reset = qla2x00_lun_reset,
fd34f556
AV		 2180 .fabric_login = qla2x00_login_fabric,
2181 .fabric_logout = qla2x00_fabric_logout,
2182 .calc_req_entries = qla2x00_calc_iocbs_32,
2183 .build_iocbs = qla2x00_build_scsi_iocbs_32,
2184 .prep_ms_iocb = qla2x00_prep_ms_iocb,
2185 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
2186 .read_nvram = qla2x00_read_nvram_data,
2187 .write_nvram = qla2x00_write_nvram_data,
2188 .fw_dump = qla2100_fw_dump,
2189 .beacon_on = NULL,
2190 .beacon_off = NULL,
2191 .beacon_blink = NULL,
2192 .read_optrom = qla2x00_read_optrom_data,
2193 .write_optrom = qla2x00_write_optrom_data,
2194 .get_flash_version = qla2x00_get_flash_version,
e315cd28 2195 .start_scsi = qla2x00_start_scsi,
d7459527 2196 .start_scsi_mq = NULL,
a9083016 2197 .abort_isp = qla2x00_abort_isp,
706f457d 2198 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2199 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 2200};
2201
2202static struct isp_operations qla2300_isp_ops = {
2203 .pci_config = qla2300_pci_config,
2204 .reset_chip = qla2x00_reset_chip,
2205 .chip_diag = qla2x00_chip_diag,
2206 .config_rings = qla2x00_config_rings,
2207 .reset_adapter = qla2x00_reset_adapter,
2208 .nvram_config = qla2x00_nvram_config,
2209 .update_fw_options = qla2x00_update_fw_options,
2210 .load_risc = qla2x00_load_risc,
2211 .pci_info_str = qla2x00_pci_info_str,
2212 .fw_version_str = qla2x00_fw_version_str,
2213 .intr_handler = qla2300_intr_handler,
2214 .enable_intrs = qla2x00_enable_intrs,
2215 .disable_intrs = qla2x00_disable_intrs,
2216 .abort_command = qla2x00_abort_command,
523ec773
AV		 2217 .target_reset = qla2x00_abort_target,
2218 .lun_reset = qla2x00_lun_reset,
fd34f556
AV		 2219 .fabric_login = qla2x00_login_fabric,
2220 .fabric_logout = qla2x00_fabric_logout,
2221 .calc_req_entries = qla2x00_calc_iocbs_32,
2222 .build_iocbs = qla2x00_build_scsi_iocbs_32,
2223 .prep_ms_iocb = qla2x00_prep_ms_iocb,
2224 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
2225 .read_nvram = qla2x00_read_nvram_data,
2226 .write_nvram = qla2x00_write_nvram_data,
2227 .fw_dump = qla2300_fw_dump,
2228 .beacon_on = qla2x00_beacon_on,
2229 .beacon_off = qla2x00_beacon_off,
2230 .beacon_blink = qla2x00_beacon_blink,
2231 .read_optrom = qla2x00_read_optrom_data,
2232 .write_optrom = qla2x00_write_optrom_data,
2233 .get_flash_version = qla2x00_get_flash_version,
e315cd28 2234 .start_scsi = qla2x00_start_scsi,
d7459527 2235 .start_scsi_mq = NULL,
a9083016 2236 .abort_isp = qla2x00_abort_isp,
7ec0effd 2237 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2238 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 2239};
2240
2241static struct isp_operations qla24xx_isp_ops = {
2242 .pci_config = qla24xx_pci_config,
2243 .reset_chip = qla24xx_reset_chip,
2244 .chip_diag = qla24xx_chip_diag,
2245 .config_rings = qla24xx_config_rings,
2246 .reset_adapter = qla24xx_reset_adapter,
2247 .nvram_config = qla24xx_nvram_config,
2248 .update_fw_options = qla24xx_update_fw_options,
2249 .load_risc = qla24xx_load_risc,
2250 .pci_info_str = qla24xx_pci_info_str,
2251 .fw_version_str = qla24xx_fw_version_str,
2252 .intr_handler = qla24xx_intr_handler,
2253 .enable_intrs = qla24xx_enable_intrs,
2254 .disable_intrs = qla24xx_disable_intrs,
2255 .abort_command = qla24xx_abort_command,
523ec773
AV		 2256 .target_reset = qla24xx_abort_target,
2257 .lun_reset = qla24xx_lun_reset,
fd34f556
AV		 2258 .fabric_login = qla24xx_login_fabric,
2259 .fabric_logout = qla24xx_fabric_logout,
2260 .calc_req_entries = NULL,
2261 .build_iocbs = NULL,
2262 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2263 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2264 .read_nvram = qla24xx_read_nvram_data,
2265 .write_nvram = qla24xx_write_nvram_data,
2266 .fw_dump = qla24xx_fw_dump,
2267 .beacon_on = qla24xx_beacon_on,
2268 .beacon_off = qla24xx_beacon_off,
2269 .beacon_blink = qla24xx_beacon_blink,
2270 .read_optrom = qla24xx_read_optrom_data,
2271 .write_optrom = qla24xx_write_optrom_data,
2272 .get_flash_version = qla24xx_get_flash_version,
e315cd28 2273 .start_scsi = qla24xx_start_scsi,
d7459527 2274 .start_scsi_mq = NULL,
a9083016 2275 .abort_isp = qla2x00_abort_isp,
7ec0effd 2276 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2277 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 2278};
2279
c3a2f0df
AV		 2280static struct isp_operations qla25xx_isp_ops = {
2281 .pci_config = qla25xx_pci_config,
2282 .reset_chip = qla24xx_reset_chip,
2283 .chip_diag = qla24xx_chip_diag,
2284 .config_rings = qla24xx_config_rings,
2285 .reset_adapter = qla24xx_reset_adapter,
2286 .nvram_config = qla24xx_nvram_config,
2287 .update_fw_options = qla24xx_update_fw_options,
2288 .load_risc = qla24xx_load_risc,
2289 .pci_info_str = qla24xx_pci_info_str,
2290 .fw_version_str = qla24xx_fw_version_str,
2291 .intr_handler = qla24xx_intr_handler,
2292 .enable_intrs = qla24xx_enable_intrs,
2293 .disable_intrs = qla24xx_disable_intrs,
2294 .abort_command = qla24xx_abort_command,
523ec773
AV		 2295 .target_reset = qla24xx_abort_target,
2296 .lun_reset = qla24xx_lun_reset,
c3a2f0df
AV		 2297 .fabric_login = qla24xx_login_fabric,
2298 .fabric_logout = qla24xx_fabric_logout,
2299 .calc_req_entries = NULL,
2300 .build_iocbs = NULL,
2301 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2302 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2303 .read_nvram = qla25xx_read_nvram_data,
2304 .write_nvram = qla25xx_write_nvram_data,
2305 .fw_dump = qla25xx_fw_dump,
2306 .beacon_on = qla24xx_beacon_on,
2307 .beacon_off = qla24xx_beacon_off,
2308 .beacon_blink = qla24xx_beacon_blink,
338c9161 2309 .read_optrom = qla25xx_read_optrom_data,
c3a2f0df
AV		 2310 .write_optrom = qla24xx_write_optrom_data,
2311 .get_flash_version = qla24xx_get_flash_version,
bad75002 2312 .start_scsi = qla24xx_dif_start_scsi,
d7459527 2313 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
a9083016 2314 .abort_isp = qla2x00_abort_isp,
7ec0effd 2315 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2316 .initialize_adapter = qla2x00_initialize_adapter,
c3a2f0df
AV		 2317};
2318
3a03eb79
AV		 2319static struct isp_operations qla81xx_isp_ops = {
2320 .pci_config = qla25xx_pci_config,
2321 .reset_chip = qla24xx_reset_chip,
2322 .chip_diag = qla24xx_chip_diag,
2323 .config_rings = qla24xx_config_rings,
2324 .reset_adapter = qla24xx_reset_adapter,
2325 .nvram_config = qla81xx_nvram_config,
2326 .update_fw_options = qla81xx_update_fw_options,
eaac30be 2327 .load_risc = qla81xx_load_risc,
3a03eb79
AV		 2328 .pci_info_str = qla24xx_pci_info_str,
2329 .fw_version_str = qla24xx_fw_version_str,
2330 .intr_handler = qla24xx_intr_handler,
2331 .enable_intrs = qla24xx_enable_intrs,
2332 .disable_intrs = qla24xx_disable_intrs,
2333 .abort_command = qla24xx_abort_command,
2334 .target_reset = qla24xx_abort_target,
2335 .lun_reset = qla24xx_lun_reset,
2336 .fabric_login = qla24xx_login_fabric,
2337 .fabric_logout = qla24xx_fabric_logout,
2338 .calc_req_entries = NULL,
2339 .build_iocbs = NULL,
2340 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2341 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
3d79038f
AV		 2342 .read_nvram = NULL,
2343 .write_nvram = NULL,
3a03eb79
AV		 2344 .fw_dump = qla81xx_fw_dump,
2345 .beacon_on = qla24xx_beacon_on,
2346 .beacon_off = qla24xx_beacon_off,
6246b8a1 2347 .beacon_blink = qla83xx_beacon_blink,
3a03eb79
AV		 2348 .read_optrom = qla25xx_read_optrom_data,
2349 .write_optrom = qla24xx_write_optrom_data,
2350 .get_flash_version = qla24xx_get_flash_version,
ba77ef53 2351 .start_scsi = qla24xx_dif_start_scsi,
d7459527 2352 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
a9083016 2353 .abort_isp = qla2x00_abort_isp,
7ec0effd 2354 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2355 .initialize_adapter = qla2x00_initialize_adapter,
a9083016
GM		 2356};
2357
2358static struct isp_operations qla82xx_isp_ops = {
2359 .pci_config = qla82xx_pci_config,
2360 .reset_chip = qla82xx_reset_chip,
2361 .chip_diag = qla24xx_chip_diag,
2362 .config_rings = qla82xx_config_rings,
2363 .reset_adapter = qla24xx_reset_adapter,
2364 .nvram_config = qla81xx_nvram_config,
2365 .update_fw_options = qla24xx_update_fw_options,
2366 .load_risc = qla82xx_load_risc,
9d55ca66 2367 .pci_info_str = qla24xx_pci_info_str,
a9083016
GM		 2368 .fw_version_str = qla24xx_fw_version_str,
2369 .intr_handler = qla82xx_intr_handler,
2370 .enable_intrs = qla82xx_enable_intrs,
2371 .disable_intrs = qla82xx_disable_intrs,
2372 .abort_command = qla24xx_abort_command,
2373 .target_reset = qla24xx_abort_target,
2374 .lun_reset = qla24xx_lun_reset,
2375 .fabric_login = qla24xx_login_fabric,
2376 .fabric_logout = qla24xx_fabric_logout,
2377 .calc_req_entries = NULL,
2378 .build_iocbs = NULL,
2379 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2380 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2381 .read_nvram = qla24xx_read_nvram_data,
2382 .write_nvram = qla24xx_write_nvram_data,
a1b23c5a 2383 .fw_dump = qla82xx_fw_dump,
999916dc
SK		 2384 .beacon_on = qla82xx_beacon_on,
2385 .beacon_off = qla82xx_beacon_off,
2386 .beacon_blink = NULL,
a9083016
GM		 2387 .read_optrom = qla82xx_read_optrom_data,
2388 .write_optrom = qla82xx_write_optrom_data,
7ec0effd 2389 .get_flash_version = qla82xx_get_flash_version,
a9083016 2390 .start_scsi = qla82xx_start_scsi,
d7459527 2391 .start_scsi_mq = NULL,
a9083016 2392 .abort_isp = qla82xx_abort_isp,
706f457d 2393 .iospace_config = qla82xx_iospace_config,
8ae6d9c7 2394 .initialize_adapter = qla2x00_initialize_adapter,
3a03eb79
AV		 2395};
2396
7ec0effd
AD		 2397static struct isp_operations qla8044_isp_ops = {
2398 .pci_config = qla82xx_pci_config,
2399 .reset_chip = qla82xx_reset_chip,
2400 .chip_diag = qla24xx_chip_diag,
2401 .config_rings = qla82xx_config_rings,
2402 .reset_adapter = qla24xx_reset_adapter,
2403 .nvram_config = qla81xx_nvram_config,
2404 .update_fw_options = qla24xx_update_fw_options,
2405 .load_risc = qla82xx_load_risc,
2406 .pci_info_str = qla24xx_pci_info_str,
2407 .fw_version_str = qla24xx_fw_version_str,
2408 .intr_handler = qla8044_intr_handler,
2409 .enable_intrs = qla82xx_enable_intrs,
2410 .disable_intrs = qla82xx_disable_intrs,
2411 .abort_command = qla24xx_abort_command,
2412 .target_reset = qla24xx_abort_target,
2413 .lun_reset = qla24xx_lun_reset,
2414 .fabric_login = qla24xx_login_fabric,
2415 .fabric_logout = qla24xx_fabric_logout,
2416 .calc_req_entries = NULL,
2417 .build_iocbs = NULL,
2418 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2419 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2420 .read_nvram = NULL,
2421 .write_nvram = NULL,
a1b23c5a 2422 .fw_dump = qla8044_fw_dump,
7ec0effd
AD		 2423 .beacon_on = qla82xx_beacon_on,
2424 .beacon_off = qla82xx_beacon_off,
2425 .beacon_blink = NULL,
888e639d 2426 .read_optrom = qla8044_read_optrom_data,
7ec0effd
AD		 2427 .write_optrom = qla8044_write_optrom_data,
2428 .get_flash_version = qla82xx_get_flash_version,
2429 .start_scsi = qla82xx_start_scsi,
d7459527 2430 .start_scsi_mq = NULL,
7ec0effd
AD		 2431 .abort_isp = qla8044_abort_isp,
2432 .iospace_config = qla82xx_iospace_config,
2433 .initialize_adapter = qla2x00_initialize_adapter,
2434};
2435
6246b8a1
GM		 2436static struct isp_operations qla83xx_isp_ops = {
2437 .pci_config = qla25xx_pci_config,
2438 .reset_chip = qla24xx_reset_chip,
2439 .chip_diag = qla24xx_chip_diag,
2440 .config_rings = qla24xx_config_rings,
2441 .reset_adapter = qla24xx_reset_adapter,
2442 .nvram_config = qla81xx_nvram_config,
2443 .update_fw_options = qla81xx_update_fw_options,
2444 .load_risc = qla81xx_load_risc,
2445 .pci_info_str = qla24xx_pci_info_str,
2446 .fw_version_str = qla24xx_fw_version_str,
2447 .intr_handler = qla24xx_intr_handler,
2448 .enable_intrs = qla24xx_enable_intrs,
2449 .disable_intrs = qla24xx_disable_intrs,
2450 .abort_command = qla24xx_abort_command,
2451 .target_reset = qla24xx_abort_target,
2452 .lun_reset = qla24xx_lun_reset,
2453 .fabric_login = qla24xx_login_fabric,
2454 .fabric_logout = qla24xx_fabric_logout,
2455 .calc_req_entries = NULL,
2456 .build_iocbs = NULL,
2457 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2458 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2459 .read_nvram = NULL,
2460 .write_nvram = NULL,
2461 .fw_dump = qla83xx_fw_dump,
2462 .beacon_on = qla24xx_beacon_on,
2463 .beacon_off = qla24xx_beacon_off,
2464 .beacon_blink = qla83xx_beacon_blink,
2465 .read_optrom = qla25xx_read_optrom_data,
2466 .write_optrom = qla24xx_write_optrom_data,
2467 .get_flash_version = qla24xx_get_flash_version,
2468 .start_scsi = qla24xx_dif_start_scsi,
d7459527 2469 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
6246b8a1
GM		 2470 .abort_isp = qla2x00_abort_isp,
2471 .iospace_config = qla83xx_iospace_config,
8ae6d9c7
GM		 2472 .initialize_adapter = qla2x00_initialize_adapter,
2473};
2474
2475static struct isp_operations qlafx00_isp_ops = {
2476 .pci_config = qlafx00_pci_config,
2477 .reset_chip = qlafx00_soft_reset,
2478 .chip_diag = qlafx00_chip_diag,
2479 .config_rings = qlafx00_config_rings,
2480 .reset_adapter = qlafx00_soft_reset,
2481 .nvram_config = NULL,
2482 .update_fw_options = NULL,
2483 .load_risc = NULL,
2484 .pci_info_str = qlafx00_pci_info_str,
2485 .fw_version_str = qlafx00_fw_version_str,
2486 .intr_handler = qlafx00_intr_handler,
2487 .enable_intrs = qlafx00_enable_intrs,
2488 .disable_intrs = qlafx00_disable_intrs,
4440e46d 2489 .abort_command = qla24xx_async_abort_command,
8ae6d9c7
GM		 2490 .target_reset = qlafx00_abort_target,
2491 .lun_reset = qlafx00_lun_reset,
2492 .fabric_login = NULL,
2493 .fabric_logout = NULL,
2494 .calc_req_entries = NULL,
2495 .build_iocbs = NULL,
2496 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2497 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2498 .read_nvram = qla24xx_read_nvram_data,
2499 .write_nvram = qla24xx_write_nvram_data,
2500 .fw_dump = NULL,
2501 .beacon_on = qla24xx_beacon_on,
2502 .beacon_off = qla24xx_beacon_off,
2503 .beacon_blink = NULL,
2504 .read_optrom = qla24xx_read_optrom_data,
2505 .write_optrom = qla24xx_write_optrom_data,
2506 .get_flash_version = qla24xx_get_flash_version,
2507 .start_scsi = qlafx00_start_scsi,
d7459527 2508 .start_scsi_mq = NULL,
8ae6d9c7
GM		 2509 .abort_isp = qlafx00_abort_isp,
2510 .iospace_config = qlafx00_iospace_config,
2511 .initialize_adapter = qlafx00_initialize_adapter,
6246b8a1
GM		 2512};
2513
f73cb695
CD		 2514static struct isp_operations qla27xx_isp_ops = {
2515 .pci_config = qla25xx_pci_config,
2516 .reset_chip = qla24xx_reset_chip,
2517 .chip_diag = qla24xx_chip_diag,
2518 .config_rings = qla24xx_config_rings,
2519 .reset_adapter = qla24xx_reset_adapter,
2520 .nvram_config = qla81xx_nvram_config,
a36f1443 2521 .update_fw_options = qla24xx_update_fw_options,
f73cb695
CD		 2522 .load_risc = qla81xx_load_risc,
2523 .pci_info_str = qla24xx_pci_info_str,
2524 .fw_version_str = qla24xx_fw_version_str,
2525 .intr_handler = qla24xx_intr_handler,
2526 .enable_intrs = qla24xx_enable_intrs,
2527 .disable_intrs = qla24xx_disable_intrs,
2528 .abort_command = qla24xx_abort_command,
2529 .target_reset = qla24xx_abort_target,
2530 .lun_reset = qla24xx_lun_reset,
2531 .fabric_login = qla24xx_login_fabric,
2532 .fabric_logout = qla24xx_fabric_logout,
2533 .calc_req_entries = NULL,
2534 .build_iocbs = NULL,
2535 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2536 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2537 .read_nvram = NULL,
2538 .write_nvram = NULL,
2539 .fw_dump = qla27xx_fwdump,
2540 .beacon_on = qla24xx_beacon_on,
2541 .beacon_off = qla24xx_beacon_off,
2542 .beacon_blink = qla83xx_beacon_blink,
2543 .read_optrom = qla25xx_read_optrom_data,
2544 .write_optrom = qla24xx_write_optrom_data,
2545 .get_flash_version = qla24xx_get_flash_version,
2546 .start_scsi = qla24xx_dif_start_scsi,
d7459527 2547 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
f73cb695
CD		 2548 .abort_isp = qla2x00_abort_isp,
2549 .iospace_config = qla83xx_iospace_config,
2550 .initialize_adapter = qla2x00_initialize_adapter,
2551};
2552
ea5b6382 2553static inline void
e315cd28 2554qla2x00_set_isp_flags(struct qla_hw_data *ha)
ea5b6382 2555{
2556 ha->device_type = DT_EXTENDED_IDS;
2557 switch (ha->pdev->device) {
2558 case PCI_DEVICE_ID_QLOGIC_ISP2100:
9e052e2d 2559 ha->isp_type |= DT_ISP2100;
ea5b6382 2560 ha->device_type &= ~DT_EXTENDED_IDS;
441d1072 2561 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
ea5b6382 2562 break;
2563 case PCI_DEVICE_ID_QLOGIC_ISP2200:
9e052e2d 2564 ha->isp_type |= DT_ISP2200;
ea5b6382 2565 ha->device_type &= ~DT_EXTENDED_IDS;
441d1072 2566 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
ea5b6382 2567 break;
2568 case PCI_DEVICE_ID_QLOGIC_ISP2300:
9e052e2d 2569 ha->isp_type |= DT_ISP2300;
4a59f71d 2570 ha->device_type |= DT_ZIO_SUPPORTED;
441d1072 2571 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 2572 break;
2573 case PCI_DEVICE_ID_QLOGIC_ISP2312:
9e052e2d 2574 ha->isp_type |= DT_ISP2312;
4a59f71d 2575 ha->device_type |= DT_ZIO_SUPPORTED;
441d1072 2576 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 2577 break;
2578 case PCI_DEVICE_ID_QLOGIC_ISP2322:
9e052e2d 2579 ha->isp_type |= DT_ISP2322;
4a59f71d 2580 ha->device_type |= DT_ZIO_SUPPORTED;
ea5b6382 2581 if (ha->pdev->subsystem_vendor == 0x1028 &&
2582 ha->pdev->subsystem_device == 0x0170)
2583 ha->device_type |= DT_OEM_001;
441d1072 2584 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 2585 break;
2586 case PCI_DEVICE_ID_QLOGIC_ISP6312:
9e052e2d 2587 ha->isp_type |= DT_ISP6312;
441d1072 2588 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 2589 break;
2590 case PCI_DEVICE_ID_QLOGIC_ISP6322:
9e052e2d 2591 ha->isp_type |= DT_ISP6322;
441d1072 2592 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 2593 break;
2594 case PCI_DEVICE_ID_QLOGIC_ISP2422:
9e052e2d 2595 ha->isp_type |= DT_ISP2422;
4a59f71d 2596 ha->device_type |= DT_ZIO_SUPPORTED;
e428924c 2597 ha->device_type |= DT_FWI2;
c76f2c01 2598 ha->device_type |= DT_IIDMA;
441d1072 2599 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2600 break;
2601 case PCI_DEVICE_ID_QLOGIC_ISP2432:
9e052e2d 2602 ha->isp_type |= DT_ISP2432;
4a59f71d 2603 ha->device_type |= DT_ZIO_SUPPORTED;
e428924c 2604 ha->device_type |= DT_FWI2;
c76f2c01 2605 ha->device_type |= DT_IIDMA;
441d1072 2606 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2607 break;
4d4df193 2608 case PCI_DEVICE_ID_QLOGIC_ISP8432:
9e052e2d 2609 ha->isp_type |= DT_ISP8432;
4d4df193
HK		 2610 ha->device_type |= DT_ZIO_SUPPORTED;
2611 ha->device_type |= DT_FWI2;
2612 ha->device_type |= DT_IIDMA;
2613 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2614 break;
044cc6c8 2615 case PCI_DEVICE_ID_QLOGIC_ISP5422:
9e052e2d 2616 ha->isp_type |= DT_ISP5422;
e428924c 2617 ha->device_type |= DT_FWI2;
441d1072 2618 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2619 break;
044cc6c8 2620 case PCI_DEVICE_ID_QLOGIC_ISP5432:
9e052e2d 2621 ha->isp_type |= DT_ISP5432;
e428924c 2622 ha->device_type |= DT_FWI2;
441d1072 2623 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2624 break;
c3a2f0df 2625 case PCI_DEVICE_ID_QLOGIC_ISP2532:
9e052e2d 2626 ha->isp_type |= DT_ISP2532;
c3a2f0df
AV		 2627 ha->device_type |= DT_ZIO_SUPPORTED;
2628 ha->device_type |= DT_FWI2;
2629 ha->device_type |= DT_IIDMA;
441d1072 2630 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2631 break;
3a03eb79 2632 case PCI_DEVICE_ID_QLOGIC_ISP8001:
9e052e2d 2633 ha->isp_type |= DT_ISP8001;
3a03eb79
AV		 2634 ha->device_type |= DT_ZIO_SUPPORTED;
2635 ha->device_type |= DT_FWI2;
2636 ha->device_type |= DT_IIDMA;
2637 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2638 break;
a9083016 2639 case PCI_DEVICE_ID_QLOGIC_ISP8021:
9e052e2d 2640 ha->isp_type |= DT_ISP8021;
a9083016
GM		 2641 ha->device_type |= DT_ZIO_SUPPORTED;
2642 ha->device_type |= DT_FWI2;
2643 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2644 /* Initialize 82XX ISP flags */
2645 qla82xx_init_flags(ha);
2646 break;
7ec0effd 2647 case PCI_DEVICE_ID_QLOGIC_ISP8044:
9e052e2d 2648 ha->isp_type |= DT_ISP8044;
7ec0effd
AD		 2649 ha->device_type |= DT_ZIO_SUPPORTED;
2650 ha->device_type |= DT_FWI2;
2651 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2652 /* Initialize 82XX ISP flags */
2653 qla82xx_init_flags(ha);
2654 break;
6246b8a1 2655 case PCI_DEVICE_ID_QLOGIC_ISP2031:
9e052e2d 2656 ha->isp_type |= DT_ISP2031;
6246b8a1
GM		 2657 ha->device_type |= DT_ZIO_SUPPORTED;
2658 ha->device_type |= DT_FWI2;
2659 ha->device_type |= DT_IIDMA;
2660 ha->device_type |= DT_T10_PI;
2661 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2662 break;
2663 case PCI_DEVICE_ID_QLOGIC_ISP8031:
9e052e2d 2664 ha->isp_type |= DT_ISP8031;
6246b8a1
GM		 2665 ha->device_type |= DT_ZIO_SUPPORTED;
2666 ha->device_type |= DT_FWI2;
2667 ha->device_type |= DT_IIDMA;
2668 ha->device_type |= DT_T10_PI;
2669 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2670 break;
8ae6d9c7 2671 case PCI_DEVICE_ID_QLOGIC_ISPF001:
9e052e2d 2672 ha->isp_type |= DT_ISPFX00;
8ae6d9c7 2673 break;
f73cb695 2674 case PCI_DEVICE_ID_QLOGIC_ISP2071:
9e052e2d 2675 ha->isp_type |= DT_ISP2071;
f73cb695
CD		 2676 ha->device_type |= DT_ZIO_SUPPORTED;
2677 ha->device_type |= DT_FWI2;
2678 ha->device_type |= DT_IIDMA;
8ce3f570 2679 ha->device_type |= DT_T10_PI;
f73cb695
CD		 2680 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2681 break;
2c5bbbb2 2682 case PCI_DEVICE_ID_QLOGIC_ISP2271:
9e052e2d 2683 ha->isp_type |= DT_ISP2271;
2c5bbbb2
JC		 2684 ha->device_type |= DT_ZIO_SUPPORTED;
2685 ha->device_type |= DT_FWI2;
2686 ha->device_type |= DT_IIDMA;
8ce3f570 2687 ha->device_type |= DT_T10_PI;
2c5bbbb2
JC		 2688 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2689 break;
2b48992f 2690 case PCI_DEVICE_ID_QLOGIC_ISP2261:
9e052e2d 2691 ha->isp_type |= DT_ISP2261;
2b48992f
SC		 2692 ha->device_type |= DT_ZIO_SUPPORTED;
2693 ha->device_type |= DT_FWI2;
2694 ha->device_type |= DT_IIDMA;
8ce3f570 2695 ha->device_type |= DT_T10_PI;
2b48992f
SC		 2696 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2697 break;
ecc89f25
JC		 2698 case PCI_DEVICE_ID_QLOGIC_ISP2081:
2699 case PCI_DEVICE_ID_QLOGIC_ISP2089:
2700 ha->isp_type |= DT_ISP2081;
2701 ha->device_type |= DT_ZIO_SUPPORTED;
2702 ha->device_type |= DT_FWI2;
2703 ha->device_type |= DT_IIDMA;
2704 ha->device_type |= DT_T10_PI;
2705 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2706 break;
2707 case PCI_DEVICE_ID_QLOGIC_ISP2281:
2708 case PCI_DEVICE_ID_QLOGIC_ISP2289:
2709 ha->isp_type |= DT_ISP2281;
2710 ha->device_type |= DT_ZIO_SUPPORTED;
2711 ha->device_type |= DT_FWI2;
2712 ha->device_type |= DT_IIDMA;
2713 ha->device_type |= DT_T10_PI;
2714 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2715 break;
ea5b6382 2716 }
e5b68a61 2717
a9083016 2718 if (IS_QLA82XX(ha))
43a9c38b 2719 ha->port_no = ha->portnum & 1;
f73cb695 2720 else {
a9083016
GM		 2721 /* Get adapter physical port no from interrupt pin register. */
2722 pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no);
ecc89f25
JC		 2723 if (IS_QLA25XX(ha) || IS_QLA2031(ha) ||
2724 IS_QLA27XX(ha) || IS_QLA28XX(ha))
f73cb695
CD		 2725 ha->port_no--;
2726 else
2727 ha->port_no = !(ha->port_no & 1);
2728 }
a9083016 2729
7c3df132 2730 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b,
d8424f68 2731 "device_type=0x%x port=%d fw_srisc_address=0x%x.\n",
f73cb695 2732 ha->device_type, ha->port_no, ha->fw_srisc_address);
ea5b6382 2733}
2734
1e99e33a
AV		 2735static void
2736qla2xxx_scan_start(struct Scsi_Host *shost)
2737{
e315cd28 2738 scsi_qla_host_t *vha = shost_priv(shost);
1e99e33a 2739
cbc8eb67
AV		 2740 if (vha->hw->flags.running_gold_fw)
2741 return;
2742
e315cd28
AC		 2743 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
2744 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
2745 set_bit(RSCN_UPDATE, &vha->dpc_flags);
2746 set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags);
1e99e33a
AV		 2747}
2748
2749static int
2750qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time)
2751{
e315cd28 2752 scsi_qla_host_t *vha = shost_priv(shost);
1e99e33a 2753
a5dd506e
BK		 2754 if (test_bit(UNLOADING, &vha->dpc_flags))
2755 return 1;
e315cd28 2756 if (!vha->host)
1e99e33a 2757 return 1;
e315cd28 2758 if (time > vha->hw->loop_reset_delay * HZ)
1e99e33a
AV		 2759 return 1;
2760
e315cd28 2761 return atomic_read(&vha->loop_state) == LOOP_READY;
1e99e33a
AV		 2762}
2763
ec7193e2
QT		 2764static void qla2x00_iocb_work_fn(struct work_struct *work)
2765{
2766 struct scsi_qla_host *vha = container_of(work,
2767 struct scsi_qla_host, iocb_work);
9b3e0f4d
QT		 2768 struct qla_hw_data *ha = vha->hw;
2769 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
0aca7784 2770 int i = 2;
9b3e0f4d
QT		 2771 unsigned long flags;
2772
2773 if (test_bit(UNLOADING, &base_vha->dpc_flags))
2774 return;
ec7193e2 2775
9b3e0f4d 2776 while (!list_empty(&vha->work_list) && i > 0) {
ec7193e2 2777 qla2x00_do_work(vha);
9b3e0f4d 2778 i--;
ec7193e2 2779 }
9b3e0f4d
QT		 2780
2781 spin_lock_irqsave(&vha->work_lock, flags);
2782 clear_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags);
2783 spin_unlock_irqrestore(&vha->work_lock, flags);
ec7193e2
QT		 2784}
2785
1da177e4
LT		 2786/*
2787 * PCI driver interface
2788 */
6f039790 2789static int
7ee61397 2790qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
1da177e4 2791{
a1541d5a 2792 int ret = -ENODEV;
1da177e4 2793 struct Scsi_Host *host;
e315cd28
AC		 2794 scsi_qla_host_t *base_vha = NULL;
2795 struct qla_hw_data *ha;
29856e28 2796 char pci_info[30];
7d613ac6 2797 char fw_str[30], wq_name[30];
5433383e 2798 struct scsi_host_template *sht;
642ef983 2799 int bars, mem_only = 0;
e315cd28 2800 uint16_t req_length = 0, rsp_length = 0;
73208dfd
AC		 2801 struct req_que *req = NULL;
2802 struct rsp_que *rsp = NULL;
5601236b 2803 int i;
d7459527 2804
285d0321 2805 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO);
a5326f86 2806 sht = &qla2xxx_driver_template;
5433383e 2807 if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 ||
8bc69e7d 2808 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 ||
4d4df193 2809 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 ||
8bc69e7d 2810 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 ||
c3a2f0df 2811 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 ||
3a03eb79 2812 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 ||
a9083016 2813 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 ||
6246b8a1
GM		 2814 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021 ||
2815 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2031 ||
8ae6d9c7 2816 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8031 ||
7ec0effd 2817 pdev->device == PCI_DEVICE_ID_QLOGIC_ISPF001 ||
f73cb695 2818 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8044 ||
2c5bbbb2 2819 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2071 ||
2b48992f 2820 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2271 ||
ecc89f25
JC		 2821 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2261 ||
2822 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2081 ||
2823 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2281 ||
2824 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2089 ||
2825 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2289) {
285d0321 2826 bars = pci_select_bars(pdev, IORESOURCE_MEM);
09483916 2827 mem_only = 1;
7c3df132
SK		 2828 ql_dbg_pci(ql_dbg_init, pdev, 0x0007,
2829 "Mem only adapter.\n");
285d0321 2830 }
7c3df132
SK		 2831 ql_dbg_pci(ql_dbg_init, pdev, 0x0008,
2832 "Bars=%d.\n", bars);
285d0321 2833
09483916
BH		 2834 if (mem_only) {
2835 if (pci_enable_device_mem(pdev))
ddff7ed4 2836 return ret;
09483916
BH		 2837 } else {
2838 if (pci_enable_device(pdev))
ddff7ed4 2839 return ret;
09483916 2840 }
285d0321 2841
0927678f
JB		 2842 /* This may fail but that's ok */
2843 pci_enable_pcie_error_reporting(pdev);
285d0321 2844
5da05a26
GM		 2845 /* Turn off T10-DIF when FC-NVMe is enabled */
2846 if (ql2xnvmeenable)
2847 ql2xenabledif = 0;
2848
e315cd28
AC		 2849 ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL);
2850 if (!ha) {
7c3df132
SK		 2851 ql_log_pci(ql_log_fatal, pdev, 0x0009,
2852 "Unable to allocate memory for ha.\n");
ddff7ed4 2853 goto disable_device;
1da177e4 2854 }
7c3df132
SK		 2855 ql_dbg_pci(ql_dbg_init, pdev, 0x000a,
2856 "Memory allocated for ha=%p.\n", ha);
e315cd28 2857 ha->pdev = pdev;
33e79977
QT		 2858 INIT_LIST_HEAD(&ha->tgt.q_full_list);
2859 spin_lock_init(&ha->tgt.q_full_lock);
7560151b 2860 spin_lock_init(&ha->tgt.sess_lock);
2f424b9b
QT		 2861 spin_lock_init(&ha->tgt.atio_lock);
2862
deeae7a6 2863 atomic_set(&ha->nvme_active_aen_cnt, 0);
1da177e4
LT		 2864
2865 /* Clear our data area */
285d0321 2866 ha->bars = bars;
09483916 2867 ha->mem_only = mem_only;
df4bf0bb 2868 spin_lock_init(&ha->hardware_lock);
339aa70e 2869 spin_lock_init(&ha->vport_slock);
a9b6f722 2870 mutex_init(&ha->selflogin_lock);
7a8ab9c8 2871 mutex_init(&ha->optrom_mutex);
1da177e4 2872
ea5b6382 2873 /* Set ISP-type information. */
2874 qla2x00_set_isp_flags(ha);
ca79cf66
DG		 2875
2876 /* Set EEH reset type to fundamental if required by hba */
95676112 2877 if (IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha) ||
ecc89f25 2878 IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))
ca79cf66 2879 pdev->needs_freset = 1;
ca79cf66 2880
cba1e47f
CD		 2881 ha->prev_topology = 0;
2882 ha->init_cb_size = sizeof(init_cb_t);
2883 ha->link_data_rate = PORT_SPEED_UNKNOWN;
2884 ha->optrom_size = OPTROM_SIZE_2300;
d1e3635a 2885 ha->max_exchg = FW_MAX_EXCHANGES_CNT;
b2000805
QT		 2886 atomic_set(&ha->num_pend_mbx_stage1, 0);
2887 atomic_set(&ha->num_pend_mbx_stage2, 0);
2888 atomic_set(&ha->num_pend_mbx_stage3, 0);
8b4673ba
QT		 2889 atomic_set(&ha->zio_threshold, DEFAULT_ZIO_THRESHOLD);
2890 ha->last_zio_threshold = DEFAULT_ZIO_THRESHOLD;
cba1e47f 2891
abbd8870 2892 /* Assign ISP specific operations. */
1da177e4 2893 if (IS_QLA2100(ha)) {
642ef983 2894 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
1da177e4 2895 ha->mbx_count = MAILBOX_REGISTER_COUNT_2100;
e315cd28
AC		 2896 req_length = REQUEST_ENTRY_CNT_2100;
2897 rsp_length = RESPONSE_ENTRY_CNT_2100;
2898 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
abbd8870 2899 ha->gid_list_info_size = 4;
3a03eb79
AV		 2900 ha->flash_conf_off = ~0;
2901 ha->flash_data_off = ~0;
2902 ha->nvram_conf_off = ~0;
2903 ha->nvram_data_off = ~0;
fd34f556 2904 ha->isp_ops = &qla2100_isp_ops;
1da177e4 2905 } else if (IS_QLA2200(ha)) {
642ef983 2906 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
67ddda35 2907 ha->mbx_count = MAILBOX_REGISTER_COUNT_2200;
e315cd28
AC		 2908 req_length = REQUEST_ENTRY_CNT_2200;
2909 rsp_length = RESPONSE_ENTRY_CNT_2100;
2910 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
abbd8870 2911 ha->gid_list_info_size = 4;
3a03eb79
AV		 2912 ha->flash_conf_off = ~0;
2913 ha->flash_data_off = ~0;
2914 ha->nvram_conf_off = ~0;
2915 ha->nvram_data_off = ~0;
fd34f556 2916 ha->isp_ops = &qla2100_isp_ops;
fca29703 2917 } else if (IS_QLA23XX(ha)) {
642ef983 2918 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
1da177e4 2919 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2920 req_length = REQUEST_ENTRY_CNT_2200;
2921 rsp_length = RESPONSE_ENTRY_CNT_2300;
2922 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
abbd8870 2923 ha->gid_list_info_size = 6;
854165f4 2924 if (IS_QLA2322(ha) || IS_QLA6322(ha))
2925 ha->optrom_size = OPTROM_SIZE_2322;
3a03eb79
AV		 2926 ha->flash_conf_off = ~0;
2927 ha->flash_data_off = ~0;
2928 ha->nvram_conf_off = ~0;
2929 ha->nvram_data_off = ~0;
fd34f556 2930 ha->isp_ops = &qla2300_isp_ops;
4d4df193 2931 } else if (IS_QLA24XX_TYPE(ha)) {
642ef983 2932 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
fca29703 2933 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2934 req_length = REQUEST_ENTRY_CNT_24XX;
2935 rsp_length = RESPONSE_ENTRY_CNT_2300;
2d70c103 2936 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
e315cd28 2937 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2c3dfe3f 2938 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
fca29703 2939 ha->gid_list_info_size = 8;
854165f4 2940 ha->optrom_size = OPTROM_SIZE_24XX;
73208dfd 2941 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX;
fd34f556 2942 ha->isp_ops = &qla24xx_isp_ops;
3a03eb79
AV		 2943 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2944 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2945 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2946 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
c3a2f0df 2947 } else if (IS_QLA25XX(ha)) {
642ef983 2948 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
c3a2f0df 2949 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2950 req_length = REQUEST_ENTRY_CNT_24XX;
2951 rsp_length = RESPONSE_ENTRY_CNT_2300;
2d70c103 2952 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
e315cd28 2953 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
c3a2f0df 2954 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
c3a2f0df
AV		 2955 ha->gid_list_info_size = 8;
2956 ha->optrom_size = OPTROM_SIZE_25XX;
73208dfd 2957 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
c3a2f0df 2958 ha->isp_ops = &qla25xx_isp_ops;
3a03eb79
AV		 2959 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2960 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2961 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2962 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
2963 } else if (IS_QLA81XX(ha)) {
642ef983 2964 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3a03eb79
AV		 2965 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2966 req_length = REQUEST_ENTRY_CNT_24XX;
2967 rsp_length = RESPONSE_ENTRY_CNT_2300;
aa230bc5 2968 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
3a03eb79
AV		 2969 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2970 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2971 ha->gid_list_info_size = 8;
2972 ha->optrom_size = OPTROM_SIZE_81XX;
40859ae5 2973 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3a03eb79
AV		 2974 ha->isp_ops = &qla81xx_isp_ops;
2975 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2976 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2977 ha->nvram_conf_off = ~0;
2978 ha->nvram_data_off = ~0;
a9083016 2979 } else if (IS_QLA82XX(ha)) {
642ef983 2980 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
a9083016
GM		 2981 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2982 req_length = REQUEST_ENTRY_CNT_82XX;
2983 rsp_length = RESPONSE_ENTRY_CNT_82XX;
2984 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2985 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2986 ha->gid_list_info_size = 8;
2987 ha->optrom_size = OPTROM_SIZE_82XX;
087c621e 2988 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
a9083016
GM		 2989 ha->isp_ops = &qla82xx_isp_ops;
2990 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2991 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2992 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2993 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
7ec0effd
AD		 2994 } else if (IS_QLA8044(ha)) {
2995 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2996 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2997 req_length = REQUEST_ENTRY_CNT_82XX;
2998 rsp_length = RESPONSE_ENTRY_CNT_82XX;
2999 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
3000 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
3001 ha->gid_list_info_size = 8;
3002 ha->optrom_size = OPTROM_SIZE_83XX;
3003 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3004 ha->isp_ops = &qla8044_isp_ops;
3005 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
3006 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
3007 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
3008 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
6246b8a1 3009 } else if (IS_QLA83XX(ha)) {
7d613ac6 3010 ha->portnum = PCI_FUNC(ha->pdev->devfn);
642ef983 3011 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
6246b8a1 3012 ha->mbx_count = MAILBOX_REGISTER_COUNT;
f2ea653f 3013 req_length = REQUEST_ENTRY_CNT_83XX;
e7b42e33 3014 rsp_length = RESPONSE_ENTRY_CNT_83XX;
b8aa4bdf 3015 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
6246b8a1
GM		 3016 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
3017 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
3018 ha->gid_list_info_size = 8;
3019 ha->optrom_size = OPTROM_SIZE_83XX;
3020 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3021 ha->isp_ops = &qla83xx_isp_ops;
3022 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
3023 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
3024 ha->nvram_conf_off = ~0;
3025 ha->nvram_data_off = ~0;
8ae6d9c7
GM		 3026 } else if (IS_QLAFX00(ha)) {
3027 ha->max_fibre_devices = MAX_FIBRE_DEVICES_FX00;
3028 ha->mbx_count = MAILBOX_REGISTER_COUNT_FX00;
3029 ha->aen_mbx_count = AEN_MAILBOX_REGISTER_COUNT_FX00;
3030 req_length = REQUEST_ENTRY_CNT_FX00;
3031 rsp_length = RESPONSE_ENTRY_CNT_FX00;
8ae6d9c7
GM		 3032 ha->isp_ops = &qlafx00_isp_ops;
3033 ha->port_down_retry_count = 30; /* default value */
3034 ha->mr.fw_hbt_cnt = QLAFX00_HEARTBEAT_INTERVAL;
3035 ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL;
71e56003 3036 ha->mr.fw_critemp_timer_tick = QLAFX00_CRITEMP_INTERVAL;
8ae6d9c7 3037 ha->mr.fw_hbt_en = 1;
e8f5e95d
AB		 3038 ha->mr.host_info_resend = false;
3039 ha->mr.hinfo_resend_timer_tick = QLAFX00_HINFO_RESEND_INTERVAL;
f73cb695
CD		 3040 } else if (IS_QLA27XX(ha)) {
3041 ha->portnum = PCI_FUNC(ha->pdev->devfn);
3042 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3043 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e7b42e33
QT		 3044 req_length = REQUEST_ENTRY_CNT_83XX;
3045 rsp_length = RESPONSE_ENTRY_CNT_83XX;
b20f02e1 3046 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
f73cb695
CD		 3047 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
3048 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
3049 ha->gid_list_info_size = 8;
3050 ha->optrom_size = OPTROM_SIZE_83XX;
3051 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3052 ha->isp_ops = &qla27xx_isp_ops;
3053 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
3054 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
3055 ha->nvram_conf_off = ~0;
3056 ha->nvram_data_off = ~0;
ecc89f25
JC		 3057 } else if (IS_QLA28XX(ha)) {
3058 ha->portnum = PCI_FUNC(ha->pdev->devfn);
3059 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3060 ha->mbx_count = MAILBOX_REGISTER_COUNT;
3061 req_length = REQUEST_ENTRY_CNT_24XX;
3062 rsp_length = RESPONSE_ENTRY_CNT_2300;
3063 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
3064 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
3065 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
3066 ha->gid_list_info_size = 8;
3067 ha->optrom_size = OPTROM_SIZE_28XX;
3068 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3069 ha->isp_ops = &qla27xx_isp_ops;
3070 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_28XX;
3071 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_28XX;
3072 ha->nvram_conf_off = ~0;
3073 ha->nvram_data_off = ~0;
1da177e4 3074 }
6246b8a1 3075
7c3df132
SK		 3076 ql_dbg_pci(ql_dbg_init, pdev, 0x001e,
3077 "mbx_count=%d, req_length=%d, "
3078 "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, "
642ef983
CD		 3079 "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, "
3080 "max_fibre_devices=%d.\n",
7c3df132
SK		 3081 ha->mbx_count, req_length, rsp_length, ha->max_loop_id,
3082 ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size,
642ef983 3083 ha->nvram_npiv_size, ha->max_fibre_devices);
7c3df132
SK		 3084 ql_dbg_pci(ql_dbg_init, pdev, 0x001f,
3085 "isp_ops=%p, flash_conf_off=%d, "
3086 "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n",
3087 ha->isp_ops, ha->flash_conf_off, ha->flash_data_off,
3088 ha->nvram_conf_off, ha->nvram_data_off);
706f457d
GM		 3089
3090 /* Configure PCI I/O space */
3091 ret = ha->isp_ops->iospace_config(ha);
3092 if (ret)
0a63ad12 3093 goto iospace_config_failed;
706f457d
GM		 3094
3095 ql_log_pci(ql_log_info, pdev, 0x001d,
3096 "Found an ISP%04X irq %d iobase 0x%p.\n",
3097 pdev->device, pdev->irq, ha->iobase);
6c2f527c 3098 mutex_init(&ha->vport_lock);
d7459527 3099 mutex_init(&ha->mq_lock);
0b05a1f0
MB		 3100 init_completion(&ha->mbx_cmd_comp);
3101 complete(&ha->mbx_cmd_comp);
3102 init_completion(&ha->mbx_intr_comp);
23f2ebd1 3103 init_completion(&ha->dcbx_comp);
f356bef1 3104 init_completion(&ha->lb_portup_comp);
1da177e4 3105
2c3dfe3f 3106 set_bit(0, (unsigned long *) ha->vp_idx_map);
1da177e4 3107
53303c42 3108 qla2x00_config_dma_addressing(ha);
7c3df132
SK		 3109 ql_dbg_pci(ql_dbg_init, pdev, 0x0020,
3110 "64 Bit addressing is %s.\n",
3111 ha->flags.enable_64bit_addressing ? "enable" :
3112 "disable");
73208dfd 3113 ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp);
b2a72ec3 3114 if (ret) {
7c3df132
SK		 3115 ql_log_pci(ql_log_fatal, pdev, 0x0031,
3116 "Failed to allocate memory for adapter, aborting.\n");
1da177e4 3117
e315cd28
AC		 3118 goto probe_hw_failed;
3119 }
3120
73208dfd 3121 req->max_q_depth = MAX_Q_DEPTH;
e315cd28 3122 if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU)
73208dfd
AC		 3123 req->max_q_depth = ql2xmaxqdepth;
3124
e315cd28
AC		 3125
3126 base_vha = qla2x00_create_host(sht, ha);
3127 if (!base_vha) {
a1541d5a 3128 ret = -ENOMEM;
e315cd28 3129 goto probe_hw_failed;
1da177e4
LT		 3130 }
3131
e315cd28 3132 pci_set_drvdata(pdev, base_vha);
6b383979 3133 set_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags);
e315cd28 3134
e315cd28 3135 host = base_vha->host;
2afa19a9 3136 base_vha->req = req;
73208dfd 3137 if (IS_QLA2XXX_MIDTYPE(ha))
f6602f3b
QT		 3138 base_vha->mgmt_svr_loop_id =
3139 qla2x00_reserve_mgmt_server_loop_id(base_vha);
73208dfd 3140 else
e315cd28
AC		 3141 base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER +
3142 base_vha->vp_idx;
58548cb5 3143
8ae6d9c7
GM		 3144 /* Setup fcport template structure. */
3145 ha->mr.fcport.vha = base_vha;
3146 ha->mr.fcport.port_type = FCT_UNKNOWN;
3147 ha->mr.fcport.loop_id = FC_NO_LOOP_ID;
3148 qla2x00_set_fcport_state(&ha->mr.fcport, FCS_UNCONFIGURED);
3149 ha->mr.fcport.supported_classes = FC_COS_UNSPECIFIED;
3150 ha->mr.fcport.scan_state = 1;
3151
58548cb5
GM		 3152 /* Set the SG table size based on ISP type */
3153 if (!IS_FWI2_CAPABLE(ha)) {
3154 if (IS_QLA2100(ha))
3155 host->sg_tablesize = 32;
3156 } else {
3157 if (!IS_QLA82XX(ha))
3158 host->sg_tablesize = QLA_SG_ALL;
3159 }
642ef983 3160 host->max_id = ha->max_fibre_devices;
e315cd28
AC		 3161 host->cmd_per_lun = 3;
3162 host->unique_id = host->host_no;
e02587d7 3163 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif)
0c470874
AE		 3164 host->max_cmd_len = 32;
3165 else
3166 host->max_cmd_len = MAX_CMDSZ;
e315cd28 3167 host->max_channel = MAX_BUSES - 1;
755f516b
HR		 3168 /* Older HBAs support only 16-bit LUNs */
3169 if (!IS_QLAFX00(ha) && !IS_FWI2_CAPABLE(ha) &&
3170 ql2xmaxlun > 0xffff)
3171 host->max_lun = 0xffff;
3172 else
3173 host->max_lun = ql2xmaxlun;
e315cd28 3174 host->transportt = qla2xxx_transport_template;
9a069e19 3175 sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC);
e315cd28 3176
7c3df132
SK		 3177 ql_dbg(ql_dbg_init, base_vha, 0x0033,
3178 "max_id=%d this_id=%d "
3179 "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d "
1abf635d 3180 "max_lun=%llu transportt=%p, vendor_id=%llu.\n", host->max_id,
7c3df132
SK		 3181 host->this_id, host->cmd_per_lun, host->unique_id,
3182 host->max_cmd_len, host->max_channel, host->max_lun,
3183 host->transportt, sht->vendor_id);
3184
1010f21e
HM		 3185 INIT_WORK(&base_vha->iocb_work, qla2x00_iocb_work_fn);
3186
d7459527
MH		 3187 /* Set up the irqs */
3188 ret = qla2x00_request_irqs(ha, rsp);
3189 if (ret)
6a2cf8d3 3190 goto probe_failed;
d7459527 3191
9a347ff4 3192 /* Alloc arrays of request and response ring ptrs */
6d634067
BK		 3193 ret = qla2x00_alloc_queues(ha, req, rsp);
3194 if (ret) {
9a347ff4
CD		 3195 ql_log(ql_log_fatal, base_vha, 0x003d,
3196 "Failed to allocate memory for queue pointers..."
3197 "aborting.\n");
26a77799 3198 ret = -ENODEV;
6a2cf8d3 3199 goto probe_failed;
9a347ff4
CD		 3200 }
3201
f664a3cc 3202 if (ha->mqenable) {
5601236b
MH		 3203 /* number of hardware queues supported by blk/scsi-mq*/
3204 host->nr_hw_queues = ha->max_qpairs;
3205
3206 ql_dbg(ql_dbg_init, base_vha, 0x0192,
3207 "blk/scsi-mq enabled, HW queues = %d.\n", host->nr_hw_queues);
c38d1baf
HM		 3208 } else {
3209 if (ql2xnvmeenable) {
3210 host->nr_hw_queues = ha->max_qpairs;
3211 ql_dbg(ql_dbg_init, base_vha, 0x0194,
3212 "FC-NVMe support is enabled, HW queues=%d\n",
3213 host->nr_hw_queues);
3214 } else {
3215 ql_dbg(ql_dbg_init, base_vha, 0x0193,
3216 "blk/scsi-mq disabled.\n");
3217 }
3218 }
5601236b 3219
2d70c103 3220 qlt_probe_one_stage1(base_vha, ha);
9a347ff4 3221
90a86fc0
JC		 3222 pci_save_state(pdev);
3223
9a347ff4 3224 /* Assign back pointers */
2afa19a9
AC		 3225 rsp->req = req;
3226 req->rsp = rsp;
9a347ff4 3227
8ae6d9c7
GM		 3228 if (IS_QLAFX00(ha)) {
3229 ha->rsp_q_map[0] = rsp;
3230 ha->req_q_map[0] = req;
3231 set_bit(0, ha->req_qid_map);
3232 set_bit(0, ha->rsp_qid_map);
3233 }
3234
08029990
AV		 3235 /* FWI2-capable only. */
3236 req->req_q_in = &ha->iobase->isp24.req_q_in;
3237 req->req_q_out = &ha->iobase->isp24.req_q_out;
3238 rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in;
3239 rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out;
ecc89f25
JC		 3240 if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha) ||
3241 IS_QLA28XX(ha)) {
08029990
AV		 3242 req->req_q_in = &ha->mqiobase->isp25mq.req_q_in;
3243 req->req_q_out = &ha->mqiobase->isp25mq.req_q_out;
3244 rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in;
3245 rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out;
17d98630
AC		 3246 }
3247
8ae6d9c7
GM		 3248 if (IS_QLAFX00(ha)) {
3249 req->req_q_in = &ha->iobase->ispfx00.req_q_in;
3250 req->req_q_out = &ha->iobase->ispfx00.req_q_out;
3251 rsp->rsp_q_in = &ha->iobase->ispfx00.rsp_q_in;
3252 rsp->rsp_q_out = &ha->iobase->ispfx00.rsp_q_out;
3253 }
3254
7ec0effd 3255 if (IS_P3P_TYPE(ha)) {
a9083016
GM		 3256 req->req_q_out = &ha->iobase->isp82.req_q_out[0];
3257 rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0];
3258 rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0];
3259 }
3260
7c3df132
SK		 3261 ql_dbg(ql_dbg_multiq, base_vha, 0xc009,
3262 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
3263 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
3264 ql_dbg(ql_dbg_multiq, base_vha, 0xc00a,
3265 "req->req_q_in=%p req->req_q_out=%p "
3266 "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
3267 req->req_q_in, req->req_q_out,
3268 rsp->rsp_q_in, rsp->rsp_q_out);
3269 ql_dbg(ql_dbg_init, base_vha, 0x003e,
3270 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
3271 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
3272 ql_dbg(ql_dbg_init, base_vha, 0x003f,
3273 "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
3274 req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out);
1da177e4 3275
d48cc67c 3276 ha->wq = alloc_workqueue("qla2xxx_wq", 0, 0);
3277
8ae6d9c7 3278 if (ha->isp_ops->initialize_adapter(base_vha)) {
7c3df132
SK		 3279 ql_log(ql_log_fatal, base_vha, 0x00d6,
3280 "Failed to initialize adapter - Adapter flags %x.\n",
3281 base_vha->device_flags);
1da177e4 3282
a9083016
GM		 3283 if (IS_QLA82XX(ha)) {
3284 qla82xx_idc_lock(ha);
3285 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 3286 QLA8XXX_DEV_FAILED);
a9083016 3287 qla82xx_idc_unlock(ha);
7c3df132
SK		 3288 ql_log(ql_log_fatal, base_vha, 0x00d7,
3289 "HW State: FAILED.\n");
7ec0effd
AD		 3290 } else if (IS_QLA8044(ha)) {
3291 qla8044_idc_lock(ha);
3292 qla8044_wr_direct(base_vha,
3293 QLA8044_CRB_DEV_STATE_INDEX,
3294 QLA8XXX_DEV_FAILED);
3295 qla8044_idc_unlock(ha);
3296 ql_log(ql_log_fatal, base_vha, 0x0150,
3297 "HW State: FAILED.\n");
a9083016
GM		 3298 }
3299
a1541d5a 3300 ret = -ENODEV;
1da177e4
LT		 3301 goto probe_failed;
3302 }
3303
3b1bef64
CD		 3304 if (IS_QLAFX00(ha))
3305 host->can_queue = QLAFX00_MAX_CANQUEUE;
3306 else
3307 host->can_queue = req->num_outstanding_cmds - 10;
3308
3309 ql_dbg(ql_dbg_init, base_vha, 0x0032,
3310 "can_queue=%d, req=%p, mgmt_svr_loop_id=%d, sg_tablesize=%d.\n",
3311 host->can_queue, base_vha->req,
3312 base_vha->mgmt_svr_loop_id, host->sg_tablesize);
3313
e326d22a 3314 if (ha->mqenable) {
e326d22a 3315 bool startit = false;
e326d22a 3316
f664a3cc 3317 if (QLA_TGT_MODE_ENABLED())
e326d22a 3318 startit = false;
e326d22a 3319
f664a3cc 3320 if (ql2x_ini_mode == QLA2XXX_INI_MODE_ENABLED)
e326d22a 3321 startit = true;
e326d22a 3322
f664a3cc
JA		 3323 /* Create start of day qpairs for Block MQ */
3324 for (i = 0; i < ha->max_qpairs; i++)
3325 qla2xxx_create_qpair(base_vha, 5, 0, startit);
5601236b 3326 }
68ca949c 3327
cbc8eb67
AV		 3328 if (ha->flags.running_gold_fw)
3329 goto skip_dpc;
3330
1da177e4
LT		 3331 /*
3332 * Startup the kernel thread for this host adapter
3333 */
39a11240 3334 ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha,
7c3df132 3335 "%s_dpc", base_vha->host_str);
39a11240 3336 if (IS_ERR(ha->dpc_thread)) {
7c3df132
SK		 3337 ql_log(ql_log_fatal, base_vha, 0x00ed,
3338 "Failed to start DPC thread.\n");
39a11240 3339 ret = PTR_ERR(ha->dpc_thread);
e2532b4a 3340 ha->dpc_thread = NULL;
1da177e4
LT		 3341 goto probe_failed;
3342 }
7c3df132
SK		 3343 ql_dbg(ql_dbg_init, base_vha, 0x00ee,
3344 "DPC thread started successfully.\n");
1da177e4 3345
2d70c103
NB		 3346 /*
3347 * If we're not coming up in initiator mode, we might sit for
3348 * a while without waking up the dpc thread, which leads to a
3349 * stuck process warning. So just kick the dpc once here and
3350 * let the kthread start (and go back to sleep in qla2x00_do_dpc).
3351 */
3352 qla2xxx_wake_dpc(base_vha);
3353
f3ddac19
CD		 3354 INIT_WORK(&ha->board_disable, qla2x00_disable_board_on_pci_error);
3355
81178772
SK		 3356 if (IS_QLA8031(ha) || IS_MCTP_CAPABLE(ha)) {
3357 sprintf(wq_name, "qla2xxx_%lu_dpc_lp_wq", base_vha->host_no);
3358 ha->dpc_lp_wq = create_singlethread_workqueue(wq_name);
3359 INIT_WORK(&ha->idc_aen, qla83xx_service_idc_aen);
3360
3361 sprintf(wq_name, "qla2xxx_%lu_dpc_hp_wq", base_vha->host_no);
3362 ha->dpc_hp_wq = create_singlethread_workqueue(wq_name);
3363 INIT_WORK(&ha->nic_core_reset, qla83xx_nic_core_reset_work);
3364 INIT_WORK(&ha->idc_state_handler,
3365 qla83xx_idc_state_handler_work);
3366 INIT_WORK(&ha->nic_core_unrecoverable,
3367 qla83xx_nic_core_unrecoverable_work);
3368 }
3369
cbc8eb67 3370skip_dpc:
e315cd28
AC		 3371 list_add_tail(&base_vha->list, &ha->vp_list);
3372 base_vha->host->irq = ha->pdev->irq;
1da177e4
LT		 3373
3374 /* Initialized the timer */
8e5f4ba0 3375 qla2x00_start_timer(base_vha, WATCH_INTERVAL);
7c3df132
SK		 3376 ql_dbg(ql_dbg_init, base_vha, 0x00ef,
3377 "Started qla2x00_timer with "
3378 "interval=%d.\n", WATCH_INTERVAL);
3379 ql_dbg(ql_dbg_init, base_vha, 0x00f0,
3380 "Detected hba at address=%p.\n",
3381 ha);
d19044c3 3382
e02587d7 3383 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) {
bad75002 3384 if (ha->fw_attributes & BIT_4) {
9e522cd8 3385 int prot = 0, guard;
bd432bb5 3386
bad75002 3387 base_vha->flags.difdix_supported = 1;
7c3df132
SK		 3388 ql_dbg(ql_dbg_init, base_vha, 0x00f1,
3389 "Registering for DIF/DIX type 1 and 3 protection.\n");
8cb2049c
AE		 3390 if (ql2xenabledif == 1)
3391 prot = SHOST_DIX_TYPE0_PROTECTION;
7855d2ba
MP		 3392 if (ql2xprotmask)
3393 scsi_host_set_prot(host, ql2xprotmask);
3394 else
3395 scsi_host_set_prot(host,
3396 prot | SHOST_DIF_TYPE1_PROTECTION
3397 | SHOST_DIF_TYPE2_PROTECTION
3398 | SHOST_DIF_TYPE3_PROTECTION
3399 | SHOST_DIX_TYPE1_PROTECTION
3400 | SHOST_DIX_TYPE2_PROTECTION
3401 | SHOST_DIX_TYPE3_PROTECTION);
9e522cd8
AE		 3402
3403 guard = SHOST_DIX_GUARD_CRC;
3404
3405 if (IS_PI_IPGUARD_CAPABLE(ha) &&
3406 (ql2xenabledif > 1 || IS_PI_DIFB_DIX0_CAPABLE(ha)))
3407 guard |= SHOST_DIX_GUARD_IP;
3408
7855d2ba
MP		 3409 if (ql2xprotguard)
3410 scsi_host_set_guard(host, ql2xprotguard);
3411 else
3412 scsi_host_set_guard(host, guard);
bad75002
AE		 3413 } else
3414 base_vha->flags.difdix_supported = 0;
3415 }
3416
a9083016
GM		 3417 ha->isp_ops->enable_intrs(ha);
3418
1fe19ee4
AB		 3419 if (IS_QLAFX00(ha)) {
3420 ret = qlafx00_fx_disc(base_vha,
3421 &base_vha->hw->mr.fcport, FXDISC_GET_CONFIG_INFO);
3422 host->sg_tablesize = (ha->mr.extended_io_enabled) ?
3423 QLA_SG_ALL : 128;
3424 }
3425
a1541d5a
AV		 3426 ret = scsi_add_host(host, &pdev->dev);
3427 if (ret)
3428 goto probe_failed;
3429
1486400f
MR		 3430 base_vha->flags.init_done = 1;
3431 base_vha->flags.online = 1;
edaa5c74 3432 ha->prev_minidump_failed = 0;
1486400f 3433
7c3df132
SK		 3434 ql_dbg(ql_dbg_init, base_vha, 0x00f2,
3435 "Init done and hba is online.\n");
3436
726b8548
QT		 3437 if (qla_ini_mode_enabled(base_vha) ||
3438 qla_dual_mode_enabled(base_vha))
2d70c103
NB		 3439 scsi_scan_host(host);
3440 else
3441 ql_dbg(ql_dbg_init, base_vha, 0x0122,
3442 "skipping scsi_scan_host() for non-initiator port\n");
1e99e33a 3443
e315cd28 3444 qla2x00_alloc_sysfs_attr(base_vha);
a1541d5a 3445
8ae6d9c7 3446 if (IS_QLAFX00(ha)) {
8ae6d9c7
GM		 3447 ret = qlafx00_fx_disc(base_vha,
3448 &base_vha->hw->mr.fcport, FXDISC_GET_PORT_INFO);
3449
3450 /* Register system information */
3451 ret = qlafx00_fx_disc(base_vha,
3452 &base_vha->hw->mr.fcport, FXDISC_REG_HOST_INFO);
3453 }
3454
e315cd28 3455 qla2x00_init_host_attr(base_vha);
a1541d5a 3456
e315cd28 3457 qla2x00_dfs_setup(base_vha);
df613b96 3458
03eb912a
AB		 3459 ql_log(ql_log_info, base_vha, 0x00fb,
3460 "QLogic %s - %s.\n", ha->model_number, ha->model_desc);
7c3df132
SK		 3461 ql_log(ql_log_info, base_vha, 0x00fc,
3462 "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n",
3463 pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info),
3464 pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-',
3465 base_vha->host_no,
df57caba 3466 ha->isp_ops->fw_version_str(base_vha, fw_str, sizeof(fw_str)));
1da177e4 3467
2d70c103
NB		 3468 qlt_add_target(ha, base_vha);
3469
6b383979 3470 clear_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags);
a29b3dd7
JC		 3471
3472 if (test_bit(UNLOADING, &base_vha->dpc_flags))
3473 return -ENODEV;
3474
e4e3a2ce
QT		 3475 if (ha->flags.detected_lr_sfp) {
3476 ql_log(ql_log_info, base_vha, 0xffff,
3477 "Reset chip to pick up LR SFP setting\n");
3478 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
3479 qla2xxx_wake_dpc(base_vha);
3480 }
3481
1da177e4
LT		 3482 return 0;
3483
3484probe_failed:
b9978769
AV		 3485 if (base_vha->timer_active)
3486 qla2x00_stop_timer(base_vha);
3487 base_vha->flags.online = 0;
3488 if (ha->dpc_thread) {
3489 struct task_struct *t = ha->dpc_thread;
3490
3491 ha->dpc_thread = NULL;
3492 kthread_stop(t);
3493 }
3494
e315cd28 3495 qla2x00_free_device(base_vha);
e315cd28 3496 scsi_host_put(base_vha->host);
6d634067
BK		 3497 /*
3498 * Need to NULL out local req/rsp after
3499 * qla2x00_free_device => qla2x00_free_queues frees
3500 * what these are pointing to. Or else we'll
3501 * fall over below in qla2x00_free_req/rsp_que.
3502 */
3503 req = NULL;
3504 rsp = NULL;
1da177e4 3505
e315cd28 3506probe_hw_failed:
d64d6c56 3507 qla2x00_mem_free(ha);
3508 qla2x00_free_req_que(ha, req);
3509 qla2x00_free_rsp_que(ha, rsp);
1a2fbf18
JL		 3510 qla2x00_clear_drv_active(ha);
3511
0a63ad12 3512iospace_config_failed:
7ec0effd 3513 if (IS_P3P_TYPE(ha)) {
0a63ad12 3514 if (!ha->nx_pcibase)
f73cb695 3515 iounmap((device_reg_t *)ha->nx_pcibase);
a9083016 3516 if (!ql2xdbwr)
f73cb695 3517 iounmap((device_reg_t *)ha->nxdb_wr_ptr);
a9083016
GM		 3518 } else {
3519 if (ha->iobase)
3520 iounmap(ha->iobase);
8ae6d9c7
GM		 3521 if (ha->cregbase)
3522 iounmap(ha->cregbase);
a9083016 3523 }
e315cd28
AC		 3524 pci_release_selected_regions(ha->pdev, ha->bars);
3525 kfree(ha);
1da177e4 3526
ddff7ed4 3527disable_device:
e315cd28 3528 pci_disable_device(pdev);
a1541d5a 3529 return ret;
1da177e4 3530}
1da177e4 3531
e30d1756
MI		 3532static void
3533qla2x00_shutdown(struct pci_dev *pdev)
3534{
3535 scsi_qla_host_t *vha;
3536 struct qla_hw_data *ha;
3537
3538 vha = pci_get_drvdata(pdev);
3539 ha = vha->hw;
3540
efdb5760
SC		 3541 ql_log(ql_log_info, vha, 0xfffa,
3542 "Adapter shutdown\n");
3543
3544 /*
3545 * Prevent future board_disable and wait
3546 * until any pending board_disable has completed.
3547 */
3548 set_bit(PFLG_DRIVER_REMOVING, &vha->pci_flags);
3549 cancel_work_sync(&ha->board_disable);
3550
3551 if (!atomic_read(&pdev->enable_cnt))
3552 return;
3553
42479343
AB		 3554 /* Notify ISPFX00 firmware */
3555 if (IS_QLAFX00(ha))
3556 qlafx00_driver_shutdown(vha, 20);
3557
e30d1756
MI		 3558 /* Turn-off FCE trace */
3559 if (ha->flags.fce_enabled) {
3560 qla2x00_disable_fce_trace(vha, NULL, NULL);
3561 ha->flags.fce_enabled = 0;
3562 }
3563
3564 /* Turn-off EFT trace */
3565 if (ha->eft)
3566 qla2x00_disable_eft_trace(vha);
3567
ecc89f25
JC		 3568 if (IS_QLA25XX(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) ||
3569 IS_QLA28XX(ha)) {
3407fc37
QT		 3570 if (ha->flags.fw_started)
3571 qla2x00_abort_isp_cleanup(vha);
3572 } else {
3573 /* Stop currently executing firmware. */
3574 qla2x00_try_to_stop_firmware(vha);
3575 }
e30d1756
MI		 3576
3577 /* Turn adapter off line */
3578 vha->flags.online = 0;
3579
3580 /* turn-off interrupts on the card */
3581 if (ha->interrupts_on) {
3582 vha->flags.init_done = 0;
3583 ha->isp_ops->disable_intrs(ha);
3584 }
3585
3586 qla2x00_free_irqs(vha);
3587
3588 qla2x00_free_fw_dump(ha);
61d41f61 3589
61d41f61 3590 pci_disable_device(pdev);
efdb5760
SC		 3591 ql_log(ql_log_info, vha, 0xfffe,
3592 "Adapter shutdown successfully.\n");
e30d1756
MI		 3593}
3594
fe1b806f 3595/* Deletes all the virtual ports for a given ha */
4c993f76 3596static void
fe1b806f 3597qla2x00_delete_all_vps(struct qla_hw_data *ha, scsi_qla_host_t *base_vha)
1da177e4 3598{
fe1b806f 3599 scsi_qla_host_t *vha;
feafb7b1 3600 unsigned long flags;
e315cd28 3601
43ebf16d
AE		 3602 mutex_lock(&ha->vport_lock);
3603 while (ha->cur_vport_count) {
43ebf16d 3604 spin_lock_irqsave(&ha->vport_slock, flags);
feafb7b1 3605
43ebf16d
AE		 3606 BUG_ON(base_vha->list.next == &ha->vp_list);
3607 /* This assumes first entry in ha->vp_list is always base vha */
3608 vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list);
52c82823 3609 scsi_host_get(vha->host);
feafb7b1 3610
43ebf16d
AE		 3611 spin_unlock_irqrestore(&ha->vport_slock, flags);
3612 mutex_unlock(&ha->vport_lock);
3613
5e6803b4
HM		 3614 qla_nvme_delete(vha);
3615
43ebf16d
AE		 3616 fc_vport_terminate(vha->fc_vport);
3617 scsi_host_put(vha->host);
feafb7b1 3618
43ebf16d 3619 mutex_lock(&ha->vport_lock);
e315cd28 3620 }
43ebf16d 3621 mutex_unlock(&ha->vport_lock);
fe1b806f 3622}
1da177e4 3623
fe1b806f
CD		 3624/* Stops all deferred work threads */
3625static void
3626qla2x00_destroy_deferred_work(struct qla_hw_data *ha)
3627{
7d613ac6
SV		 3628 /* Cancel all work and destroy DPC workqueues */
3629 if (ha->dpc_lp_wq) {
3630 cancel_work_sync(&ha->idc_aen);
3631 destroy_workqueue(ha->dpc_lp_wq);
3632 ha->dpc_lp_wq = NULL;
3633 }
3634
3635 if (ha->dpc_hp_wq) {
3636 cancel_work_sync(&ha->nic_core_reset);
3637 cancel_work_sync(&ha->idc_state_handler);
3638 cancel_work_sync(&ha->nic_core_unrecoverable);
3639 destroy_workqueue(ha->dpc_hp_wq);
3640 ha->dpc_hp_wq = NULL;
3641 }
3642
b9978769
AV		 3643 /* Kill the kernel thread for this host */
3644 if (ha->dpc_thread) {
3645 struct task_struct *t = ha->dpc_thread;
3646
3647 /*
3648 * qla2xxx_wake_dpc checks for ->dpc_thread
3649 * so we need to zero it out.
3650 */
3651 ha->dpc_thread = NULL;
3652 kthread_stop(t);
3653 }
fe1b806f 3654}
1da177e4 3655
fe1b806f
CD		 3656static void
3657qla2x00_unmap_iobases(struct qla_hw_data *ha)
3658{
a9083016 3659 if (IS_QLA82XX(ha)) {
b963752f 3660
f73cb695 3661 iounmap((device_reg_t *)ha->nx_pcibase);
a9083016 3662 if (!ql2xdbwr)
f73cb695 3663 iounmap((device_reg_t *)ha->nxdb_wr_ptr);
a9083016
GM		 3664 } else {
3665 if (ha->iobase)
3666 iounmap(ha->iobase);
1da177e4 3667
8ae6d9c7
GM		 3668 if (ha->cregbase)
3669 iounmap(ha->cregbase);
3670
a9083016
GM		 3671 if (ha->mqiobase)
3672 iounmap(ha->mqiobase);
6246b8a1 3673
ecc89f25
JC		 3674 if ((IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) &&
3675 ha->msixbase)
6246b8a1 3676 iounmap(ha->msixbase);
a9083016 3677 }
fe1b806f
CD		 3678}
3679
3680static void
db7157d4 3681qla2x00_clear_drv_active(struct qla_hw_data *ha)
fe1b806f 3682{
fe1b806f
CD		 3683 if (IS_QLA8044(ha)) {
3684 qla8044_idc_lock(ha);
c41afc9a 3685 qla8044_clear_drv_active(ha);
fe1b806f
CD		 3686 qla8044_idc_unlock(ha);
3687 } else if (IS_QLA82XX(ha)) {
3688 qla82xx_idc_lock(ha);
3689 qla82xx_clear_drv_active(ha);
3690 qla82xx_idc_unlock(ha);
3691 }
3692}
3693
3694static void
3695qla2x00_remove_one(struct pci_dev *pdev)
3696{
3697 scsi_qla_host_t *base_vha;
3698 struct qla_hw_data *ha;
3699
beb9e315
JL		 3700 base_vha = pci_get_drvdata(pdev);
3701 ha = base_vha->hw;
45235022
QT		 3702 ql_log(ql_log_info, base_vha, 0xb079,
3703 "Removing driver\n");
beb9e315
JL		 3704
3705 /* Indicate device removal to prevent future board_disable and wait
3706 * until any pending board_disable has completed. */
3707 set_bit(PFLG_DRIVER_REMOVING, &base_vha->pci_flags);
3708 cancel_work_sync(&ha->board_disable);
3709
fe1b806f 3710 /*
beb9e315
JL		 3711 * If the PCI device is disabled then there was a PCI-disconnect and
3712 * qla2x00_disable_board_on_pci_error has taken care of most of the
3713 * resources.
fe1b806f 3714 */
beb9e315 3715 if (!atomic_read(&pdev->enable_cnt)) {
726b8548
QT		 3716 dma_free_coherent(&ha->pdev->dev, base_vha->gnl.size,
3717 base_vha->gnl.l, base_vha->gnl.ldma);
3718
beb9e315
JL		 3719 scsi_host_put(base_vha->host);
3720 kfree(ha);
3721 pci_set_drvdata(pdev, NULL);
fe1b806f 3722 return;
beb9e315 3723 }
638a1a01
SC		 3724 qla2x00_wait_for_hba_ready(base_vha);
3725
ecc89f25
JC		 3726 if (IS_QLA25XX(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) ||
3727 IS_QLA28XX(ha)) {
45235022
QT		 3728 if (ha->flags.fw_started)
3729 qla2x00_abort_isp_cleanup(base_vha);
3730 } else if (!IS_QLAFX00(ha)) {
3731 if (IS_QLA8031(ha)) {
3732 ql_dbg(ql_dbg_p3p, base_vha, 0xb07e,
3733 "Clearing fcoe driver presence.\n");
3734 if (qla83xx_clear_drv_presence(base_vha) != QLA_SUCCESS)
3735 ql_dbg(ql_dbg_p3p, base_vha, 0xb079,
3736 "Error while clearing DRV-Presence.\n");
3737 }
3738
3739 qla2x00_try_to_stop_firmware(base_vha);
3740 }
3741
2ce87cc5
QT		 3742 qla2x00_wait_for_sess_deletion(base_vha);
3743
726b8548
QT		 3744 /*
3745 * if UNLOAD flag is already set, then continue unload,
783e0dc4
SC		 3746 * where it was set first.
3747 */
3748 if (test_bit(UNLOADING, &base_vha->dpc_flags))
3749 return;
3750
fe1b806f 3751 set_bit(UNLOADING, &base_vha->dpc_flags);
e84067d7
DG		 3752
3753 qla_nvme_delete(base_vha);
3754
726b8548
QT		 3755 dma_free_coherent(&ha->pdev->dev,
3756 base_vha->gnl.size, base_vha->gnl.l, base_vha->gnl.ldma);
fe1b806f 3757
a4239945
QT		 3758 vfree(base_vha->scan.l);
3759
fe1b806f
CD		 3760 if (IS_QLAFX00(ha))
3761 qlafx00_driver_shutdown(base_vha, 20);
3762
3763 qla2x00_delete_all_vps(ha, base_vha);
3764
fe1b806f
CD		 3765 qla2x00_dfs_remove(base_vha);
3766
3767 qla84xx_put_chip(base_vha);
3768
3769 /* Disable timer */
3770 if (base_vha->timer_active)
3771 qla2x00_stop_timer(base_vha);
3772
3773 base_vha->flags.online = 0;
3774
b0d6cabd
HM		 3775 /* free DMA memory */
3776 if (ha->exlogin_buf)
3777 qla2x00_free_exlogin_buffer(ha);
3778
2f56a7f1
HM		 3779 /* free DMA memory */
3780 if (ha->exchoffld_buf)
3781 qla2x00_free_exchoffld_buffer(ha);
3782
fe1b806f
CD		 3783 qla2x00_destroy_deferred_work(ha);
3784
3785 qlt_remove_target(ha, base_vha);
3786
3787 qla2x00_free_sysfs_attr(base_vha, true);
3788
3789 fc_remove_host(base_vha->host);
482c9dc7 3790 qlt_remove_target_resources(ha);
fe1b806f
CD		 3791
3792 scsi_remove_host(base_vha->host);
3793
3794 qla2x00_free_device(base_vha);
3795
db7157d4 3796 qla2x00_clear_drv_active(ha);
fe1b806f 3797
d2749ffa
AE		 3798 scsi_host_put(base_vha->host);
3799
fe1b806f 3800 qla2x00_unmap_iobases(ha);
73208dfd 3801
e315cd28
AC		 3802 pci_release_selected_regions(ha->pdev, ha->bars);
3803 kfree(ha);
1da177e4 3804
90a86fc0
JC		 3805 pci_disable_pcie_error_reporting(pdev);
3806
665db93b 3807 pci_disable_device(pdev);
1da177e4 3808}
1da177e4
LT		 3809
3810static void
e315cd28 3811qla2x00_free_device(scsi_qla_host_t *vha)
1da177e4 3812{
e315cd28 3813 struct qla_hw_data *ha = vha->hw;
1da177e4 3814
85880801
AV		 3815 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
3816
3817 /* Disable timer */
3818 if (vha->timer_active)
3819 qla2x00_stop_timer(vha);
3820
2afa19a9 3821 qla25xx_delete_queues(vha);
85880801
AV		 3822 vha->flags.online = 0;
3823
f6ef3b18 3824 /* turn-off interrupts on the card */
a9083016
GM		 3825 if (ha->interrupts_on) {
3826 vha->flags.init_done = 0;
fd34f556 3827 ha->isp_ops->disable_intrs(ha);
a9083016 3828 }
f6ef3b18 3829
093df737
QT		 3830 qla2x00_free_fcports(vha);
3831
e315cd28 3832 qla2x00_free_irqs(vha);
1da177e4 3833
093df737
QT		 3834 /* Flush the work queue and remove it */
3835 if (ha->wq) {
3836 flush_workqueue(ha->wq);
3837 destroy_workqueue(ha->wq);
3838 ha->wq = NULL;
3839 }
3840
8867048b 3841
e315cd28 3842 qla2x00_mem_free(ha);
73208dfd 3843
08de2844
GM		 3844 qla82xx_md_free(vha);
3845
73208dfd 3846 qla2x00_free_queues(ha);
1da177e4
LT		 3847}
3848
8867048b
CD		 3849void qla2x00_free_fcports(struct scsi_qla_host *vha)
3850{
3851 fc_port_t *fcport, *tfcport;
3852
ffbc6476
QT		 3853 list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list)
3854 qla2x00_free_fcport(fcport);
8867048b
CD		 3855}
3856
d97994dc 3857static inline void
e315cd28 3858qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport,
d97994dc 3859 int defer)
3860{
d97994dc 3861 struct fc_rport *rport;
67becc00 3862 scsi_qla_host_t *base_vha;
044d78e1 3863 unsigned long flags;
d97994dc 3864
3865 if (!fcport->rport)
3866 return;
3867
3868 rport = fcport->rport;
3869 if (defer) {
67becc00 3870 base_vha = pci_get_drvdata(vha->hw->pdev);
044d78e1 3871 spin_lock_irqsave(vha->host->host_lock, flags);
d97994dc 3872 fcport->drport = rport;
044d78e1 3873 spin_unlock_irqrestore(vha->host->host_lock, flags);
df673274 3874 qlt_do_generation_tick(vha, &base_vha->total_fcport_update_gen);
67becc00
AV		 3875 set_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags);
3876 qla2xxx_wake_dpc(base_vha);
2d70c103 3877 } else {
df673274 3878 int now;
bd432bb5 3879
726b8548 3880 if (rport) {
83548fe2
QT		 3881 ql_dbg(ql_dbg_disc, fcport->vha, 0x2109,
3882 "%s %8phN. rport %p roles %x\n",
3883 __func__, fcport->port_name, rport,
3884 rport->roles);
d20ed91b 3885 fc_remote_port_delete(rport);
726b8548 3886 }
df673274 3887 qlt_do_generation_tick(vha, &now);
2d70c103 3888 }
d97994dc 3889}
3890
1da177e4
LT		 3891/*
3892 * qla2x00_mark_device_lost Updates fcport state when device goes offline.
3893 *
3894 * Input: ha = adapter block pointer. fcport = port structure pointer.
3895 *
3896 * Return: None.
3897 *
3898 * Context:
3899 */
e315cd28 3900void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport,
d97994dc 3901 int do_login, int defer)
1da177e4 3902{
8ae6d9c7
GM		 3903 if (IS_QLAFX00(vha->hw)) {
3904 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
3905 qla2x00_schedule_rport_del(vha, fcport, defer);
3906 return;
3907 }
3908
2c3dfe3f 3909 if (atomic_read(&fcport->state) == FCS_ONLINE &&
c6d39e23 3910 vha->vp_idx == fcport->vha->vp_idx) {
ec426e10 3911 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
e315cd28
AC		 3912 qla2x00_schedule_rport_del(vha, fcport, defer);
3913 }
fa2a1ce5 3914 /*
1da177e4
LT		 3915 * We may need to retry the login, so don't change the state of the
3916 * port but do the retries.
3917 */
3918 if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD)
ec426e10 3919 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
1da177e4
LT		 3920
3921 if (!do_login)
3922 return;
3923
a1d0285e 3924 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
1da177e4
LT		 3925}
3926
3927/*
3928 * qla2x00_mark_all_devices_lost
3929 * Updates fcport state when device goes offline.
3930 *
3931 * Input:
3932 * ha = adapter block pointer.
3933 * fcport = port structure pointer.
3934 *
3935 * Return:
3936 * None.
3937 *
3938 * Context:
3939 */
3940void
e315cd28 3941qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha, int defer)
1da177e4
LT		 3942{
3943 fc_port_t *fcport;
3944
83548fe2
QT		 3945 ql_dbg(ql_dbg_disc, vha, 0x20f1,
3946 "Mark all dev lost\n");
726b8548 3947
e315cd28 3948 list_for_each_entry(fcport, &vha->vp_fcports, list) {
726b8548 3949 fcport->scan_state = 0;
d8630bb9 3950 qlt_schedule_sess_for_deletion(fcport);
726b8548 3951
c6d39e23 3952 if (vha->vp_idx != 0 && vha->vp_idx != fcport->vha->vp_idx)
1da177e4 3953 continue;
0d6e61bc 3954
1da177e4
LT		 3955 /*
3956 * No point in marking the device as lost, if the device is
3957 * already DEAD.
3958 */
3959 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD)
3960 continue;
e315cd28 3961 if (atomic_read(&fcport->state) == FCS_ONLINE) {
ec426e10 3962 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
0d6e61bc
AV		 3963 if (defer)
3964 qla2x00_schedule_rport_del(vha, fcport, defer);
c6d39e23 3965 else if (vha->vp_idx == fcport->vha->vp_idx)
0d6e61bc
AV		 3966 qla2x00_schedule_rport_del(vha, fcport, defer);
3967 }
1da177e4
LT		 3968 }
3969}
3970
0e145a59
BVA		 3971static void qla2x00_set_reserved_loop_ids(struct qla_hw_data *ha)
3972{
3973 int i;
3974
3975 if (IS_FWI2_CAPABLE(ha))
3976 return;
3977
3978 for (i = 0; i < SNS_FIRST_LOOP_ID; i++)
3979 set_bit(i, ha->loop_id_map);
3980 set_bit(MANAGEMENT_SERVER, ha->loop_id_map);
3981 set_bit(BROADCAST, ha->loop_id_map);
3982}
3983
1da177e4
LT		 3984/*
3985* qla2x00_mem_alloc
3986* Allocates adapter memory.
3987*
3988* Returns:
3989* 0 = success.
e8711085 3990* !0 = failure.
1da177e4 3991*/
e8711085 3992static int
73208dfd
AC		 3993qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len,
3994 struct req_que **req, struct rsp_que **rsp)
1da177e4
LT		 3995{
3996 char name[16];
1da177e4 3997
e8711085 3998 ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size,
e315cd28 3999 &ha->init_cb_dma, GFP_KERNEL);
e8711085 4000 if (!ha->init_cb)
e315cd28 4001 goto fail;
e8711085 4002
2d70c103
NB		 4003 if (qlt_mem_alloc(ha) < 0)
4004 goto fail_free_init_cb;
4005
642ef983
CD		 4006 ha->gid_list = dma_alloc_coherent(&ha->pdev->dev,
4007 qla2x00_gid_list_size(ha), &ha->gid_list_dma, GFP_KERNEL);
e315cd28 4008 if (!ha->gid_list)
2d70c103 4009 goto fail_free_tgt_mem;
1da177e4 4010
e8711085
AV		 4011 ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep);
4012 if (!ha->srb_mempool)
e315cd28 4013 goto fail_free_gid_list;
e8711085 4014
7ec0effd 4015 if (IS_P3P_TYPE(ha)) {
a9083016
GM		 4016 /* Allocate cache for CT6 Ctx. */
4017 if (!ctx_cachep) {
4018 ctx_cachep = kmem_cache_create("qla2xxx_ctx",
4019 sizeof(struct ct6_dsd), 0,
4020 SLAB_HWCACHE_ALIGN, NULL);
4021 if (!ctx_cachep)
fc1ffd6c 4022 goto fail_free_srb_mempool;
a9083016
GM		 4023 }
4024 ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ,
4025 ctx_cachep);
4026 if (!ha->ctx_mempool)
4027 goto fail_free_srb_mempool;
7c3df132
SK		 4028 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021,
4029 "ctx_cachep=%p ctx_mempool=%p.\n",
4030 ctx_cachep, ha->ctx_mempool);
a9083016
GM		 4031 }
4032
e8711085
AV		 4033 /* Get memory for cached NVRAM */
4034 ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL);
4035 if (!ha->nvram)
a9083016 4036 goto fail_free_ctx_mempool;
e8711085 4037
e315cd28
AC		 4038 snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME,
4039 ha->pdev->device);
4040 ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev,
4041 DMA_POOL_SIZE, 8, 0);
4042 if (!ha->s_dma_pool)
4043 goto fail_free_nvram;
4044
7c3df132
SK		 4045 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022,
4046 "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n",
4047 ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool);
4048
7ec0effd 4049 if (IS_P3P_TYPE(ha) || ql2xenabledif) {
a9083016
GM		 4050 ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev,
4051 DSD_LIST_DMA_POOL_SIZE, 8, 0);
4052 if (!ha->dl_dma_pool) {
7c3df132
SK		 4053 ql_log_pci(ql_log_fatal, ha->pdev, 0x0023,
4054 "Failed to allocate memory for dl_dma_pool.\n");
a9083016
GM		 4055 goto fail_s_dma_pool;
4056 }
4057
4058 ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev,
4059 FCP_CMND_DMA_POOL_SIZE, 8, 0);
4060 if (!ha->fcp_cmnd_dma_pool) {
7c3df132
SK		 4061 ql_log_pci(ql_log_fatal, ha->pdev, 0x0024,
4062 "Failed to allocate memory for fcp_cmnd_dma_pool.\n");
a9083016
GM		 4063 goto fail_dl_dma_pool;
4064 }
50b81275
GM		 4065
4066 if (ql2xenabledif) {
4067 u64 bufsize = DIF_BUNDLING_DMA_POOL_SIZE;
4068 struct dsd_dma *dsd, *nxt;
4069 uint i;
4070 /* Creata a DMA pool of buffers for DIF bundling */
4071 ha->dif_bundl_pool = dma_pool_create(name,
4072 &ha->pdev->dev, DIF_BUNDLING_DMA_POOL_SIZE, 8, 0);
4073 if (!ha->dif_bundl_pool) {
4074 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0024,
4075 "%s: failed create dif_bundl_pool\n",
4076 __func__);
4077 goto fail_dif_bundl_dma_pool;
4078 }
4079
4080 INIT_LIST_HEAD(&ha->pool.good.head);
4081 INIT_LIST_HEAD(&ha->pool.unusable.head);
4082 ha->pool.good.count = 0;
4083 ha->pool.unusable.count = 0;
4084 for (i = 0; i < 128; i++) {
4085 dsd = kzalloc(sizeof(*dsd), GFP_ATOMIC);
4086 if (!dsd) {
4087 ql_dbg_pci(ql_dbg_init, ha->pdev,
4088 0xe0ee, "%s: failed alloc dsd\n",
4089 __func__);
4090 return 1;
4091 }
4092 ha->dif_bundle_kallocs++;
4093
4094 dsd->dsd_addr = dma_pool_alloc(
4095 ha->dif_bundl_pool, GFP_ATOMIC,
4096 &dsd->dsd_list_dma);
4097 if (!dsd->dsd_addr) {
4098 ql_dbg_pci(ql_dbg_init, ha->pdev,
4099 0xe0ee,
4100 "%s: failed alloc ->dsd_addr\n",
4101 __func__);
4102 kfree(dsd);
4103 ha->dif_bundle_kallocs--;
4104 continue;
4105 }
4106 ha->dif_bundle_dma_allocs++;
4107
4108 /*
4109 * if DMA buffer crosses 4G boundary,
4110 * put it on bad list
4111 */
4112 if (MSD(dsd->dsd_list_dma) ^
4113 MSD(dsd->dsd_list_dma + bufsize)) {
4114 list_add_tail(&dsd->list,
4115 &ha->pool.unusable.head);
4116 ha->pool.unusable.count++;
4117 } else {
4118 list_add_tail(&dsd->list,
4119 &ha->pool.good.head);
4120 ha->pool.good.count++;
4121 }
4122 }
4123
4124 /* return the good ones back to the pool */
4125 list_for_each_entry_safe(dsd, nxt,
4126 &ha->pool.good.head, list) {
4127 list_del(&dsd->list);
4128 dma_pool_free(ha->dif_bundl_pool,
4129 dsd->dsd_addr, dsd->dsd_list_dma);
4130 ha->dif_bundle_dma_allocs--;
4131 kfree(dsd);
4132 ha->dif_bundle_kallocs--;
4133 }
4134
4135 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0024,
4136 "%s: dif dma pool (good=%u unusable=%u)\n",
4137 __func__, ha->pool.good.count,
4138 ha->pool.unusable.count);
4139 }
4140
7c3df132 4141 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025,
50b81275
GM		 4142 "dl_dma_pool=%p fcp_cmnd_dma_pool=%p dif_bundl_pool=%p.\n",
4143 ha->dl_dma_pool, ha->fcp_cmnd_dma_pool,
4144 ha->dif_bundl_pool);
a9083016
GM		 4145 }
4146
e8711085
AV		 4147 /* Allocate memory for SNS commands */
4148 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
e315cd28 4149 /* Get consistent memory allocated for SNS commands */
e8711085 4150 ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev,
e315cd28 4151 sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL);
e8711085 4152 if (!ha->sns_cmd)
e315cd28 4153 goto fail_dma_pool;
7c3df132 4154 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026,
d8424f68 4155 "sns_cmd: %p.\n", ha->sns_cmd);
e8711085 4156 } else {
e315cd28 4157 /* Get consistent memory allocated for MS IOCB */
e8711085 4158 ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
e315cd28 4159 &ha->ms_iocb_dma);
e8711085 4160 if (!ha->ms_iocb)
e315cd28
AC		 4161 goto fail_dma_pool;
4162 /* Get consistent memory allocated for CT SNS commands */
e8711085 4163 ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev,
e315cd28 4164 sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL);
e8711085
AV		 4165 if (!ha->ct_sns)
4166 goto fail_free_ms_iocb;
7c3df132
SK		 4167 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027,
4168 "ms_iocb=%p ct_sns=%p.\n",
4169 ha->ms_iocb, ha->ct_sns);
1da177e4
LT		 4170 }
4171
e315cd28 4172 /* Allocate memory for request ring */
73208dfd
AC		 4173 *req = kzalloc(sizeof(struct req_que), GFP_KERNEL);
4174 if (!*req) {
7c3df132
SK		 4175 ql_log_pci(ql_log_fatal, ha->pdev, 0x0028,
4176 "Failed to allocate memory for req.\n");
e315cd28
AC		 4177 goto fail_req;
4178 }
73208dfd
AC		 4179 (*req)->length = req_len;
4180 (*req)->ring = dma_alloc_coherent(&ha->pdev->dev,
4181 ((*req)->length + 1) * sizeof(request_t),
4182 &(*req)->dma, GFP_KERNEL);
4183 if (!(*req)->ring) {
7c3df132
SK		 4184 ql_log_pci(ql_log_fatal, ha->pdev, 0x0029,
4185 "Failed to allocate memory for req_ring.\n");
e315cd28
AC		 4186 goto fail_req_ring;
4187 }
4188 /* Allocate memory for response ring */
73208dfd
AC		 4189 *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL);
4190 if (!*rsp) {
7c3df132
SK		 4191 ql_log_pci(ql_log_fatal, ha->pdev, 0x002a,
4192 "Failed to allocate memory for rsp.\n");
e315cd28
AC		 4193 goto fail_rsp;
4194 }
73208dfd
AC		 4195 (*rsp)->hw = ha;
4196 (*rsp)->length = rsp_len;
4197 (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev,
4198 ((*rsp)->length + 1) * sizeof(response_t),
4199 &(*rsp)->dma, GFP_KERNEL);
4200 if (!(*rsp)->ring) {
7c3df132
SK		 4201 ql_log_pci(ql_log_fatal, ha->pdev, 0x002b,
4202 "Failed to allocate memory for rsp_ring.\n");
e315cd28
AC		 4203 goto fail_rsp_ring;
4204 }
73208dfd
AC		 4205 (*req)->rsp = *rsp;
4206 (*rsp)->req = *req;
7c3df132
SK		 4207 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c,
4208 "req=%p req->length=%d req->ring=%p rsp=%p "
4209 "rsp->length=%d rsp->ring=%p.\n",
4210 *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length,
4211 (*rsp)->ring);
73208dfd
AC		 4212 /* Allocate memory for NVRAM data for vports */
4213 if (ha->nvram_npiv_size) {
6396bb22
KC		 4214 ha->npiv_info = kcalloc(ha->nvram_npiv_size,
4215 sizeof(struct qla_npiv_entry),
4216 GFP_KERNEL);
73208dfd 4217 if (!ha->npiv_info) {
7c3df132
SK		 4218 ql_log_pci(ql_log_fatal, ha->pdev, 0x002d,
4219 "Failed to allocate memory for npiv_info.\n");
73208dfd
AC		 4220 goto fail_npiv_info;
4221 }
4222 } else
4223 ha->npiv_info = NULL;
e8711085 4224
b64b0e8f 4225 /* Get consistent memory allocated for EX-INIT-CB. */
ecc89f25
JC		 4226 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) ||
4227 IS_QLA28XX(ha)) {
b64b0e8f
AV		 4228 ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
4229 &ha->ex_init_cb_dma);
4230 if (!ha->ex_init_cb)
4231 goto fail_ex_init_cb;
7c3df132
SK		 4232 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e,
4233 "ex_init_cb=%p.\n", ha->ex_init_cb);
b64b0e8f
AV		 4234 }
4235
a9083016
GM		 4236 INIT_LIST_HEAD(&ha->gbl_dsd_list);
4237
5ff1d584
AV		 4238 /* Get consistent memory allocated for Async Port-Database. */
4239 if (!IS_FWI2_CAPABLE(ha)) {
4240 ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
4241 &ha->async_pd_dma);
4242 if (!ha->async_pd)
4243 goto fail_async_pd;
7c3df132
SK		 4244 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f,
4245 "async_pd=%p.\n", ha->async_pd);
5ff1d584
AV		 4246 }
4247
e315cd28 4248 INIT_LIST_HEAD(&ha->vp_list);
5f16b331
CD		 4249
4250 /* Allocate memory for our loop_id bitmap */
6396bb22
KC		 4251 ha->loop_id_map = kcalloc(BITS_TO_LONGS(LOOPID_MAP_SIZE),
4252 sizeof(long),
4253 GFP_KERNEL);
5f16b331 4254 if (!ha->loop_id_map)
fc1ffd6c 4255 goto fail_loop_id_map;
5f16b331
CD		 4256 else {
4257 qla2x00_set_reserved_loop_ids(ha);
4258 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0123,
b2a72ec3 4259 "loop_id_map=%p.\n", ha->loop_id_map);
5f16b331
CD		 4260 }
4261
e4e3a2ce
QT		 4262 ha->sfp_data = dma_alloc_coherent(&ha->pdev->dev,
4263 SFP_DEV_SIZE, &ha->sfp_data_dma, GFP_KERNEL);
4264 if (!ha->sfp_data) {
4265 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b,
4266 "Unable to allocate memory for SFP read-data.\n");
4267 goto fail_sfp_data;
4268 }
4269
3f006ac3
MH		 4270 ha->flt = dma_alloc_coherent(&ha->pdev->dev,
4271 sizeof(struct qla_flt_header) + FLT_REGIONS_SIZE, &ha->flt_dma,
4272 GFP_KERNEL);
4273 if (!ha->flt) {
4274 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b,
4275 "Unable to allocate memory for FLT.\n");
4276 goto fail_flt_buffer;
4277 }
4278
b2a72ec3 4279 return 0;
e315cd28 4280
3f006ac3
MH		 4281fail_flt_buffer:
4282 dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE,
4283 ha->sfp_data, ha->sfp_data_dma);
e4e3a2ce
QT		 4284fail_sfp_data:
4285 kfree(ha->loop_id_map);
fc1ffd6c
QT		 4286fail_loop_id_map:
4287 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
5ff1d584
AV		 4288fail_async_pd:
4289 dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma);
b64b0e8f
AV		 4290fail_ex_init_cb:
4291 kfree(ha->npiv_info);
73208dfd
AC		 4292fail_npiv_info:
4293 dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) *
4294 sizeof(response_t), (*rsp)->ring, (*rsp)->dma);
4295 (*rsp)->ring = NULL;
4296 (*rsp)->dma = 0;
e315cd28 4297fail_rsp_ring:
73208dfd 4298 kfree(*rsp);
6d634067 4299 *rsp = NULL;
e315cd28 4300fail_rsp:
73208dfd
AC		 4301 dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) *
4302 sizeof(request_t), (*req)->ring, (*req)->dma);
4303 (*req)->ring = NULL;
4304 (*req)->dma = 0;
e315cd28 4305fail_req_ring:
73208dfd 4306 kfree(*req);
6d634067 4307 *req = NULL;
e315cd28
AC		 4308fail_req:
4309 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
4310 ha->ct_sns, ha->ct_sns_dma);
4311 ha->ct_sns = NULL;
4312 ha->ct_sns_dma = 0;
e8711085
AV		 4313fail_free_ms_iocb:
4314 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
4315 ha->ms_iocb = NULL;
4316 ha->ms_iocb_dma = 0;
fc1ffd6c
QT		 4317
4318 if (ha->sns_cmd)
4319 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
4320 ha->sns_cmd, ha->sns_cmd_dma);
e315cd28 4321fail_dma_pool:
50b81275
GM		 4322 if (ql2xenabledif) {
4323 struct dsd_dma *dsd, *nxt;
4324
4325 list_for_each_entry_safe(dsd, nxt, &ha->pool.unusable.head,
4326 list) {
4327 list_del(&dsd->list);
4328 dma_pool_free(ha->dif_bundl_pool, dsd->dsd_addr,
4329 dsd->dsd_list_dma);
4330 ha->dif_bundle_dma_allocs--;
4331 kfree(dsd);
4332 ha->dif_bundle_kallocs--;
4333 ha->pool.unusable.count--;
4334 }
4335 dma_pool_destroy(ha->dif_bundl_pool);
4336 ha->dif_bundl_pool = NULL;
4337 }
4338
4339fail_dif_bundl_dma_pool:
bad75002 4340 if (IS_QLA82XX(ha) || ql2xenabledif) {
a9083016
GM		 4341 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
4342 ha->fcp_cmnd_dma_pool = NULL;
4343 }
4344fail_dl_dma_pool:
bad75002 4345 if (IS_QLA82XX(ha) || ql2xenabledif) {
a9083016
GM		 4346 dma_pool_destroy(ha->dl_dma_pool);
4347 ha->dl_dma_pool = NULL;
4348 }
4349fail_s_dma_pool:
e315cd28
AC		 4350 dma_pool_destroy(ha->s_dma_pool);
4351 ha->s_dma_pool = NULL;
e8711085
AV		 4352fail_free_nvram:
4353 kfree(ha->nvram);
4354 ha->nvram = NULL;
a9083016 4355fail_free_ctx_mempool:
75c1d48a 4356 mempool_destroy(ha->ctx_mempool);
a9083016 4357 ha->ctx_mempool = NULL;
e8711085 4358fail_free_srb_mempool:
75c1d48a 4359 mempool_destroy(ha->srb_mempool);
e8711085 4360 ha->srb_mempool = NULL;
e8711085 4361fail_free_gid_list:
642ef983
CD		 4362 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
4363 ha->gid_list,
e315cd28 4364 ha->gid_list_dma);
e8711085
AV		 4365 ha->gid_list = NULL;
4366 ha->gid_list_dma = 0;
2d70c103
NB		 4367fail_free_tgt_mem:
4368 qlt_mem_free(ha);
e315cd28
AC		 4369fail_free_init_cb:
4370 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb,
4371 ha->init_cb_dma);
4372 ha->init_cb = NULL;
4373 ha->init_cb_dma = 0;
e8711085 4374fail:
7c3df132
SK		 4375 ql_log(ql_log_fatal, NULL, 0x0030,
4376 "Memory allocation failure.\n");
e8711085 4377 return -ENOMEM;
1da177e4
LT		 4378}
4379
b0d6cabd
HM		 4380int
4381qla2x00_set_exlogins_buffer(scsi_qla_host_t *vha)
4382{
4383 int rval;
4384 uint16_t size, max_cnt, temp;
4385 struct qla_hw_data *ha = vha->hw;
4386
4387 /* Return if we don't need to alloacate any extended logins */
4388 if (!ql2xexlogins)
4389 return QLA_SUCCESS;
4390
99e1b683
QT		 4391 if (!IS_EXLOGIN_OFFLD_CAPABLE(ha))
4392 return QLA_SUCCESS;
4393
b0d6cabd
HM		 4394 ql_log(ql_log_info, vha, 0xd021, "EXLOGIN count: %d.\n", ql2xexlogins);
4395 max_cnt = 0;
4396 rval = qla_get_exlogin_status(vha, &size, &max_cnt);
4397 if (rval != QLA_SUCCESS) {
4398 ql_log_pci(ql_log_fatal, ha->pdev, 0xd029,
4399 "Failed to get exlogin status.\n");
4400 return rval;
4401 }
4402
4403 temp = (ql2xexlogins > max_cnt) ? max_cnt : ql2xexlogins;
99e1b683
QT		 4404 temp *= size;
4405
4406 if (temp != ha->exlogin_size) {
4407 qla2x00_free_exlogin_buffer(ha);
4408 ha->exlogin_size = temp;
4409
4410 ql_log(ql_log_info, vha, 0xd024,
4411 "EXLOGIN: max_logins=%d, portdb=0x%x, total=%d.\n",
4412 max_cnt, size, temp);
4413
4414 ql_log(ql_log_info, vha, 0xd025,
4415 "EXLOGIN: requested size=0x%x\n", ha->exlogin_size);
4416
4417 /* Get consistent memory for extended logins */
4418 ha->exlogin_buf = dma_alloc_coherent(&ha->pdev->dev,
4419 ha->exlogin_size, &ha->exlogin_buf_dma, GFP_KERNEL);
4420 if (!ha->exlogin_buf) {
4421 ql_log_pci(ql_log_fatal, ha->pdev, 0xd02a,
b0d6cabd 4422 "Failed to allocate memory for exlogin_buf_dma.\n");
99e1b683
QT		 4423 return -ENOMEM;
4424 }
b0d6cabd
HM		 4425 }
4426
4427 /* Now configure the dma buffer */
4428 rval = qla_set_exlogin_mem_cfg(vha, ha->exlogin_buf_dma);
4429 if (rval) {
83548fe2 4430 ql_log(ql_log_fatal, vha, 0xd033,
b0d6cabd
HM		 4431 "Setup extended login buffer ****FAILED****.\n");
4432 qla2x00_free_exlogin_buffer(ha);
4433 }
4434
4435 return rval;
4436}
4437
4438/*
4439* qla2x00_free_exlogin_buffer
4440*
4441* Input:
4442* ha = adapter block pointer
4443*/
4444void
4445qla2x00_free_exlogin_buffer(struct qla_hw_data *ha)
4446{
4447 if (ha->exlogin_buf) {
4448 dma_free_coherent(&ha->pdev->dev, ha->exlogin_size,
4449 ha->exlogin_buf, ha->exlogin_buf_dma);
4450 ha->exlogin_buf = NULL;
4451 ha->exlogin_size = 0;
4452 }
4453}
4454
99e1b683
QT		 4455static void
4456qla2x00_number_of_exch(scsi_qla_host_t *vha, u32 *ret_cnt, u16 max_cnt)
4457{
4458 u32 temp;
0645cb83 4459 struct init_cb_81xx *icb = (struct init_cb_81xx *)&vha->hw->init_cb;
99e1b683
QT		 4460 *ret_cnt = FW_DEF_EXCHANGES_CNT;
4461
d1e3635a
QT		 4462 if (max_cnt > vha->hw->max_exchg)
4463 max_cnt = vha->hw->max_exchg;
4464
99e1b683 4465 if (qla_ini_mode_enabled(vha)) {
0645cb83
QT		 4466 if (vha->ql2xiniexchg > max_cnt)
4467 vha->ql2xiniexchg = max_cnt;
4468
4469 if (vha->ql2xiniexchg > FW_DEF_EXCHANGES_CNT)
4470 *ret_cnt = vha->ql2xiniexchg;
99e1b683 4471
99e1b683 4472 } else if (qla_tgt_mode_enabled(vha)) {
0645cb83
QT		 4473 if (vha->ql2xexchoffld > max_cnt) {
4474 vha->ql2xexchoffld = max_cnt;
4475 icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld);
4476 }
99e1b683 4477
0645cb83
QT		 4478 if (vha->ql2xexchoffld > FW_DEF_EXCHANGES_CNT)
4479 *ret_cnt = vha->ql2xexchoffld;
99e1b683 4480 } else if (qla_dual_mode_enabled(vha)) {
0645cb83 4481 temp = vha->ql2xiniexchg + vha->ql2xexchoffld;
99e1b683 4482 if (temp > max_cnt) {
0645cb83
QT		 4483 vha->ql2xiniexchg -= (temp - max_cnt)/2;
4484 vha->ql2xexchoffld -= (((temp - max_cnt)/2) + 1);
99e1b683 4485 temp = max_cnt;
0645cb83 4486 icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld);
99e1b683
QT		 4487 }
4488
4489 if (temp > FW_DEF_EXCHANGES_CNT)
4490 *ret_cnt = temp;
4491 }
4492}
4493
2f56a7f1
HM		 4494int
4495qla2x00_set_exchoffld_buffer(scsi_qla_host_t *vha)
4496{
4497 int rval;
d1e3635a
QT		 4498 u16 size, max_cnt;
4499 u32 actual_cnt, totsz;
2f56a7f1
HM		 4500 struct qla_hw_data *ha = vha->hw;
4501
99e1b683
QT		 4502 if (!ha->flags.exchoffld_enabled)
4503 return QLA_SUCCESS;
4504
4505 if (!IS_EXCHG_OFFLD_CAPABLE(ha))
2f56a7f1
HM		 4506 return QLA_SUCCESS;
4507
2f56a7f1
HM		 4508 max_cnt = 0;
4509 rval = qla_get_exchoffld_status(vha, &size, &max_cnt);
4510 if (rval != QLA_SUCCESS) {
4511 ql_log_pci(ql_log_fatal, ha->pdev, 0xd012,
4512 "Failed to get exlogin status.\n");
4513 return rval;
4514 }
4515
d1e3635a
QT		 4516 qla2x00_number_of_exch(vha, &actual_cnt, max_cnt);
4517 ql_log(ql_log_info, vha, 0xd014,
4518 "Actual exchange offload count: %d.\n", actual_cnt);
4519
4520 totsz = actual_cnt * size;
2f56a7f1 4521
d1e3635a 4522 if (totsz != ha->exchoffld_size) {
99e1b683 4523 qla2x00_free_exchoffld_buffer(ha);
0645cb83
QT		 4524 if (actual_cnt <= FW_DEF_EXCHANGES_CNT) {
4525 ha->exchoffld_size = 0;
4526 ha->flags.exchoffld_enabled = 0;
4527 return QLA_SUCCESS;
4528 }
4529
d1e3635a 4530 ha->exchoffld_size = totsz;
99e1b683
QT		 4531
4532 ql_log(ql_log_info, vha, 0xd016,
d1e3635a
QT		 4533 "Exchange offload: max_count=%d, actual count=%d entry sz=0x%x, total sz=0x%x\n",
4534 max_cnt, actual_cnt, size, totsz);
99e1b683
QT		 4535
4536 ql_log(ql_log_info, vha, 0xd017,
4537 "Exchange Buffers requested size = 0x%x\n",
4538 ha->exchoffld_size);
4539
4540 /* Get consistent memory for extended logins */
4541 ha->exchoffld_buf = dma_alloc_coherent(&ha->pdev->dev,
4542 ha->exchoffld_size, &ha->exchoffld_buf_dma, GFP_KERNEL);
4543 if (!ha->exchoffld_buf) {
4544 ql_log_pci(ql_log_fatal, ha->pdev, 0xd013,
d1e3635a
QT		 4545 "Failed to allocate memory for Exchange Offload.\n");
4546
4547 if (ha->max_exchg >
4548 (FW_DEF_EXCHANGES_CNT + REDUCE_EXCHANGES_CNT)) {
4549 ha->max_exchg -= REDUCE_EXCHANGES_CNT;
4550 } else if (ha->max_exchg >
4551 (FW_DEF_EXCHANGES_CNT + 512)) {
4552 ha->max_exchg -= 512;
4553 } else {
4554 ha->flags.exchoffld_enabled = 0;
4555 ql_log_pci(ql_log_fatal, ha->pdev, 0xd013,
4556 "Disabling Exchange offload due to lack of memory\n");
4557 }
4558 ha->exchoffld_size = 0;
4559
99e1b683
QT		 4560 return -ENOMEM;
4561 }
0645cb83
QT		 4562 } else if (!ha->exchoffld_buf || (actual_cnt <= FW_DEF_EXCHANGES_CNT)) {
4563 /* pathological case */
4564 qla2x00_free_exchoffld_buffer(ha);
4565 ha->exchoffld_size = 0;
4566 ha->flags.exchoffld_enabled = 0;
4567 ql_log(ql_log_info, vha, 0xd016,
4568 "Exchange offload not enable: offld size=%d, actual count=%d entry sz=0x%x, total sz=0x%x.\n",
4569 ha->exchoffld_size, actual_cnt, size, totsz);
4570 return 0;
2f56a7f1
HM		 4571 }
4572
4573 /* Now configure the dma buffer */
99e1b683 4574 rval = qla_set_exchoffld_mem_cfg(vha);
2f56a7f1
HM		 4575 if (rval) {
4576 ql_log(ql_log_fatal, vha, 0xd02e,
4577 "Setup exchange offload buffer ****FAILED****.\n");
4578 qla2x00_free_exchoffld_buffer(ha);
99e1b683
QT		 4579 } else {
4580 /* re-adjust number of target exchange */
4581 struct init_cb_81xx *icb = (struct init_cb_81xx *)ha->init_cb;
4582
4583 if (qla_ini_mode_enabled(vha))
4584 icb->exchange_count = 0;
4585 else
0645cb83 4586 icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld);
2f56a7f1
HM		 4587 }
4588
4589 return rval;
4590}
4591
4592/*
4593* qla2x00_free_exchoffld_buffer
4594*
4595* Input:
4596* ha = adapter block pointer
4597*/
4598void
4599qla2x00_free_exchoffld_buffer(struct qla_hw_data *ha)
4600{
4601 if (ha->exchoffld_buf) {
4602 dma_free_coherent(&ha->pdev->dev, ha->exchoffld_size,
4603 ha->exchoffld_buf, ha->exchoffld_buf_dma);
4604 ha->exchoffld_buf = NULL;
4605 ha->exchoffld_size = 0;
4606 }
4607}
4608
1da177e4 4609/*
e30d1756
MI		 4610* qla2x00_free_fw_dump
4611* Frees fw dump stuff.
1da177e4
LT		 4612*
4613* Input:
7ec0effd 4614* ha = adapter block pointer
1da177e4 4615*/
a824ebb3 4616static void
e30d1756 4617qla2x00_free_fw_dump(struct qla_hw_data *ha)
1da177e4 4618{
a28d9e4e
JC		 4619 struct fwdt *fwdt = ha->fwdt;
4620 uint j;
4621
df613b96 4622 if (ha->fce)
f73cb695
CD		 4623 dma_free_coherent(&ha->pdev->dev,
4624 FCE_SIZE, ha->fce, ha->fce_dma);
df613b96 4625
f73cb695
CD		 4626 if (ha->eft)
4627 dma_free_coherent(&ha->pdev->dev,
4628 EFT_SIZE, ha->eft, ha->eft_dma);
4629
4630 if (ha->fw_dump)
a7a167bf 4631 vfree(ha->fw_dump);
f73cb695 4632
e30d1756
MI		 4633 ha->fce = NULL;
4634 ha->fce_dma = 0;
4635 ha->eft = NULL;
4636 ha->eft_dma = 0;
e30d1756 4637 ha->fw_dumped = 0;
61f098dd 4638 ha->fw_dump_cap_flags = 0;
e30d1756 4639 ha->fw_dump_reading = 0;
f73cb695
CD		 4640 ha->fw_dump = NULL;
4641 ha->fw_dump_len = 0;
a28d9e4e
JC		 4642
4643 for (j = 0; j < 2; j++, fwdt++) {
4644 if (fwdt->template)
4645 vfree(fwdt->template);
4646 fwdt->template = NULL;
4647 fwdt->length = 0;
4648 }
e30d1756
MI		 4649}
4650
4651/*
4652* qla2x00_mem_free
4653* Frees all adapter allocated memory.
4654*
4655* Input:
4656* ha = adapter block pointer.
4657*/
4658static void
4659qla2x00_mem_free(struct qla_hw_data *ha)
4660{
4661 qla2x00_free_fw_dump(ha);
4662
81178772
SK		 4663 if (ha->mctp_dump)
4664 dma_free_coherent(&ha->pdev->dev, MCTP_DUMP_SIZE, ha->mctp_dump,
4665 ha->mctp_dump_dma);
5365bf99 4666 ha->mctp_dump = NULL;
81178772 4667
75c1d48a 4668 mempool_destroy(ha->srb_mempool);
5365bf99 4669 ha->srb_mempool = NULL;
a7a167bf 4670
11bbc1d8
AV		 4671 if (ha->dcbx_tlv)
4672 dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE,
4673 ha->dcbx_tlv, ha->dcbx_tlv_dma);
5365bf99 4674 ha->dcbx_tlv = NULL;
11bbc1d8 4675
ce0423f4
AV		 4676 if (ha->xgmac_data)
4677 dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE,
4678 ha->xgmac_data, ha->xgmac_data_dma);
5365bf99 4679 ha->xgmac_data = NULL;
ce0423f4 4680
1da177e4
LT		 4681 if (ha->sns_cmd)
4682 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
e315cd28 4683 ha->sns_cmd, ha->sns_cmd_dma);
5365bf99
BVA		 4684 ha->sns_cmd = NULL;
4685 ha->sns_cmd_dma = 0;
1da177e4
LT		 4686
4687 if (ha->ct_sns)
4688 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
e315cd28 4689 ha->ct_sns, ha->ct_sns_dma);
5365bf99
BVA		 4690 ha->ct_sns = NULL;
4691 ha->ct_sns_dma = 0;
1da177e4 4692
88729e53 4693 if (ha->sfp_data)
e4e3a2ce
QT		 4694 dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE, ha->sfp_data,
4695 ha->sfp_data_dma);
5365bf99 4696 ha->sfp_data = NULL;
88729e53 4697
3f006ac3
MH		 4698 if (ha->flt)
4699 dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE,
4700 ha->flt, ha->flt_dma);
dc035d4e
BVA		 4701 ha->flt = NULL;
4702 ha->flt_dma = 0;
3f006ac3 4703
1da177e4
LT		 4704 if (ha->ms_iocb)
4705 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
5365bf99
BVA		 4706 ha->ms_iocb = NULL;
4707 ha->ms_iocb_dma = 0;
1da177e4 4708
b64b0e8f 4709 if (ha->ex_init_cb)
a9083016
GM		 4710 dma_pool_free(ha->s_dma_pool,
4711 ha->ex_init_cb, ha->ex_init_cb_dma);
5365bf99
BVA		 4712 ha->ex_init_cb = NULL;
4713 ha->ex_init_cb_dma = 0;
b64b0e8f 4714
5ff1d584
AV		 4715 if (ha->async_pd)
4716 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
5365bf99
BVA		 4717 ha->async_pd = NULL;
4718 ha->async_pd_dma = 0;
5ff1d584 4719
75c1d48a 4720 dma_pool_destroy(ha->s_dma_pool);
5365bf99 4721 ha->s_dma_pool = NULL;
1da177e4 4722
1da177e4 4723 if (ha->gid_list)
642ef983
CD		 4724 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
4725 ha->gid_list, ha->gid_list_dma);
5365bf99
BVA		 4726 ha->gid_list = NULL;
4727 ha->gid_list_dma = 0;
1da177e4 4728
a9083016
GM		 4729 if (IS_QLA82XX(ha)) {
4730 if (!list_empty(&ha->gbl_dsd_list)) {
4731 struct dsd_dma *dsd_ptr, *tdsd_ptr;
4732
4733 /* clean up allocated prev pool */
4734 list_for_each_entry_safe(dsd_ptr,
4735 tdsd_ptr, &ha->gbl_dsd_list, list) {
4736 dma_pool_free(ha->dl_dma_pool,
4737 dsd_ptr->dsd_addr, dsd_ptr->dsd_list_dma);
4738 list_del(&dsd_ptr->list);
4739 kfree(dsd_ptr);
4740 }
4741 }
4742 }
4743
75c1d48a 4744 dma_pool_destroy(ha->dl_dma_pool);
5365bf99 4745 ha->dl_dma_pool = NULL;
a9083016 4746
75c1d48a 4747 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
5365bf99 4748 ha->fcp_cmnd_dma_pool = NULL;
a9083016 4749
75c1d48a 4750 mempool_destroy(ha->ctx_mempool);
5365bf99 4751 ha->ctx_mempool = NULL;
a9083016 4752
26a77799 4753 if (ql2xenabledif && ha->dif_bundl_pool) {
50b81275
GM		 4754 struct dsd_dma *dsd, *nxt;
4755
4756 list_for_each_entry_safe(dsd, nxt, &ha->pool.unusable.head,
4757 list) {
4758 list_del(&dsd->list);
4759 dma_pool_free(ha->dif_bundl_pool, dsd->dsd_addr,
4760 dsd->dsd_list_dma);
4761 ha->dif_bundle_dma_allocs--;
4762 kfree(dsd);
4763 ha->dif_bundle_kallocs--;
4764 ha->pool.unusable.count--;
4765 }
4766 list_for_each_entry_safe(dsd, nxt, &ha->pool.good.head, list) {
4767 list_del(&dsd->list);
4768 dma_pool_free(ha->dif_bundl_pool, dsd->dsd_addr,
4769 dsd->dsd_list_dma);
4770 ha->dif_bundle_dma_allocs--;
4771 kfree(dsd);
4772 ha->dif_bundle_kallocs--;
4773 }
4774 }
4775
0b3b6fe2 4776 dma_pool_destroy(ha->dif_bundl_pool);
dc035d4e 4777 ha->dif_bundl_pool = NULL;
50b81275 4778
2d70c103
NB		 4779 qlt_mem_free(ha);
4780
e315cd28
AC		 4781 if (ha->init_cb)
4782 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size,
a9083016 4783 ha->init_cb, ha->init_cb_dma);
5365bf99
BVA		 4784 ha->init_cb = NULL;
4785 ha->init_cb_dma = 0;
6a2cf8d3 4786
6d634067 4787 vfree(ha->optrom_buffer);
5365bf99 4788 ha->optrom_buffer = NULL;
6d634067 4789 kfree(ha->nvram);
5365bf99 4790 ha->nvram = NULL;
6d634067 4791 kfree(ha->npiv_info);
5365bf99 4792 ha->npiv_info = NULL;
6d634067 4793 kfree(ha->swl);
5365bf99 4794 ha->swl = NULL;
6d634067 4795 kfree(ha->loop_id_map);
6a2cf8d3 4796 ha->loop_id_map = NULL;
e315cd28 4797}
1da177e4 4798
e315cd28
AC		 4799struct scsi_qla_host *qla2x00_create_host(struct scsi_host_template *sht,
4800 struct qla_hw_data *ha)
4801{
4802 struct Scsi_Host *host;
4803 struct scsi_qla_host *vha = NULL;
854165f4 4804
e315cd28 4805 host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t));
41dc529a 4806 if (!host) {
7c3df132
SK		 4807 ql_log_pci(ql_log_fatal, ha->pdev, 0x0107,
4808 "Failed to allocate host from the scsi layer, aborting.\n");
41dc529a 4809 return NULL;
e315cd28
AC		 4810 }
4811
4812 /* Clear our data area */
4813 vha = shost_priv(host);
4814 memset(vha, 0, sizeof(scsi_qla_host_t));
4815
4816 vha->host = host;
4817 vha->host_no = host->host_no;
4818 vha->hw = ha;
4819
0645cb83
QT		 4820 vha->qlini_mode = ql2x_ini_mode;
4821 vha->ql2xexchoffld = ql2xexchoffld;
4822 vha->ql2xiniexchg = ql2xiniexchg;
4823
e315cd28
AC		 4824 INIT_LIST_HEAD(&vha->vp_fcports);
4825 INIT_LIST_HEAD(&vha->work_list);
4826 INIT_LIST_HEAD(&vha->list);
8b2f5ff3
SN		 4827 INIT_LIST_HEAD(&vha->qla_cmd_list);
4828 INIT_LIST_HEAD(&vha->qla_sess_op_cmd_list);
71cdc079 4829 INIT_LIST_HEAD(&vha->logo_list);
b7bd104e 4830 INIT_LIST_HEAD(&vha->plogi_ack_list);
d7459527 4831 INIT_LIST_HEAD(&vha->qp_list);
41dc529a 4832 INIT_LIST_HEAD(&vha->gnl.fcports);
2d73ac61 4833 INIT_LIST_HEAD(&vha->gpnid_list);
9b3e0f4d 4834 INIT_WORK(&vha->iocb_work, qla2x00_iocb_work_fn);
e315cd28 4835
f999f4c1 4836 spin_lock_init(&vha->work_lock);
8b2f5ff3 4837 spin_lock_init(&vha->cmd_list_lock);
726b8548 4838 init_waitqueue_head(&vha->fcport_waitQ);
c4a9b538 4839 init_waitqueue_head(&vha->vref_waitq);
f999f4c1 4840
2fdbc65e
BVA		 4841 vha->gnl.size = sizeof(struct get_name_list_extended) *
4842 (ha->max_loop_id + 1);
41dc529a
QT		 4843 vha->gnl.l = dma_alloc_coherent(&ha->pdev->dev,
4844 vha->gnl.size, &vha->gnl.ldma, GFP_KERNEL);
4845 if (!vha->gnl.l) {
83548fe2 4846 ql_log(ql_log_fatal, vha, 0xd04a,
41dc529a 4847 "Alloc failed for name list.\n");
26a77799 4848 scsi_host_put(vha->host);
41dc529a
QT		 4849 return NULL;
4850 }
f999f4c1 4851
a4239945
QT		 4852 /* todo: what about ext login? */
4853 vha->scan.size = ha->max_fibre_devices * sizeof(struct fab_scan_rp);
4854 vha->scan.l = vmalloc(vha->scan.size);
4855 if (!vha->scan.l) {
4856 ql_log(ql_log_fatal, vha, 0xd04a,
4857 "Alloc failed for scan database.\n");
4858 dma_free_coherent(&ha->pdev->dev, vha->gnl.size,
4859 vha->gnl.l, vha->gnl.ldma);
26a77799 4860 scsi_host_put(vha->host);
a4239945
QT		 4861 return NULL;
4862 }
f352eeb7 4863 INIT_DELAYED_WORK(&vha->scan.scan_work, qla_scan_work_fn);
a4239945 4864
e315cd28 4865 sprintf(vha->host_str, "%s_%ld", QLA2XXX_DRIVER_NAME, vha->host_no);
7c3df132
SK		 4866 ql_dbg(ql_dbg_init, vha, 0x0041,
4867 "Allocated the host=%p hw=%p vha=%p dev_name=%s",
4868 vha->host, vha->hw, vha,
4869 dev_name(&(ha->pdev->dev)));
4870
e315cd28 4871 return vha;
1da177e4
LT		 4872}
4873
726b8548 4874struct qla_work_evt *
f999f4c1 4875qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type)
0971de7f
AV		 4876{
4877 struct qla_work_evt *e;
feafb7b1
AE		 4878 uint8_t bail;
4879
4880 QLA_VHA_MARK_BUSY(vha, bail);
4881 if (bail)
4882 return NULL;
0971de7f 4883
f999f4c1 4884 e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC);
feafb7b1
AE		 4885 if (!e) {
4886 QLA_VHA_MARK_NOT_BUSY(vha);
0971de7f 4887 return NULL;
feafb7b1 4888 }
0971de7f
AV		 4889
4890 INIT_LIST_HEAD(&e->list);
4891 e->type = type;
4892 e->flags = QLA_EVT_FLAG_FREE;
4893 return e;
4894}
4895
726b8548 4896int
f999f4c1 4897qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e)
0971de7f 4898{
f999f4c1 4899 unsigned long flags;
9b3e0f4d 4900 bool q = false;
0971de7f 4901
f999f4c1 4902 spin_lock_irqsave(&vha->work_lock, flags);
e315cd28 4903 list_add_tail(&e->list, &vha->work_list);
9b3e0f4d
QT		 4904
4905 if (!test_and_set_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags))
4906 q = true;
4907
f999f4c1 4908 spin_unlock_irqrestore(&vha->work_lock, flags);
ec7193e2 4909
9b3e0f4d
QT		 4910 if (q)
4911 queue_work(vha->hw->wq, &vha->iocb_work);
f999f4c1 4912
0971de7f
AV		 4913 return QLA_SUCCESS;
4914}
4915
4916int
e315cd28 4917qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code,
0971de7f
AV		 4918 u32 data)
4919{
4920 struct qla_work_evt *e;
4921
f999f4c1 4922 e = qla2x00_alloc_work(vha, QLA_EVT_AEN);
0971de7f
AV		 4923 if (!e)
4924 return QLA_FUNCTION_FAILED;
4925
4926 e->u.aen.code = code;
4927 e->u.aen.data = data;
f999f4c1 4928 return qla2x00_post_work(vha, e);
0971de7f
AV		 4929}
4930
8a659571
AV		 4931int
4932qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb)
4933{
4934 struct qla_work_evt *e;
4935
f999f4c1 4936 e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK);
8a659571
AV		 4937 if (!e)
4938 return QLA_FUNCTION_FAILED;
4939
4940 memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t));
f999f4c1 4941 return qla2x00_post_work(vha, e);
8a659571
AV		 4942}
4943
ac280b67
AV		 4944#define qla2x00_post_async_work(name, type) \
4945int qla2x00_post_async_##name##_work( \
4946 struct scsi_qla_host *vha, \
4947 fc_port_t *fcport, uint16_t *data) \
4948{ \
4949 struct qla_work_evt *e; \
4950 \
4951 e = qla2x00_alloc_work(vha, type); \
4952 if (!e) \
4953 return QLA_FUNCTION_FAILED; \
4954 \
4955 e->u.logio.fcport = fcport; \
4956 if (data) { \
4957 e->u.logio.data[0] = data[0]; \
4958 e->u.logio.data[1] = data[1]; \
4959 } \
6d674927 4960 fcport->flags |= FCF_ASYNC_ACTIVE; \
ac280b67
AV		 4961 return qla2x00_post_work(vha, e); \
4962}
4963
4964qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN);
ac280b67
AV		 4965qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT);
4966qla2x00_post_async_work(logout_done, QLA_EVT_ASYNC_LOGOUT_DONE);
5ff1d584 4967qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC);
11aea16a
QT		 4968qla2x00_post_async_work(prlo, QLA_EVT_ASYNC_PRLO);
4969qla2x00_post_async_work(prlo_done, QLA_EVT_ASYNC_PRLO_DONE);
ac280b67 4970
3420d36c
AV		 4971int
4972qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code)
4973{
4974 struct qla_work_evt *e;
4975
4976 e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT);
4977 if (!e)
4978 return QLA_FUNCTION_FAILED;
4979
4980 e->u.uevent.code = code;
4981 return qla2x00_post_work(vha, e);
4982}
4983
4984static void
4985qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code)
4986{
4987 char event_string[40];
4988 char *envp[] = { event_string, NULL };
4989
4990 switch (code) {
4991 case QLA_UEVENT_CODE_FW_DUMP:
4992 snprintf(event_string, sizeof(event_string), "FW_DUMP=%ld",
4993 vha->host_no);
4994 break;
4995 default:
4996 /* do nothing */
4997 break;
4998 }
4999 kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp);
5000}
5001
8ae6d9c7
GM		 5002int
5003qlafx00_post_aenfx_work(struct scsi_qla_host *vha, uint32_t evtcode,
5004 uint32_t *data, int cnt)
5005{
5006 struct qla_work_evt *e;
5007
5008 e = qla2x00_alloc_work(vha, QLA_EVT_AENFX);
5009 if (!e)
5010 return QLA_FUNCTION_FAILED;
5011
5012 e->u.aenfx.evtcode = evtcode;
5013 e->u.aenfx.count = cnt;
5014 memcpy(e->u.aenfx.mbx, data, sizeof(*data) * cnt);
5015 return qla2x00_post_work(vha, e);
5016}
5017
cd4ed6b4 5018void qla24xx_sched_upd_fcport(fc_port_t *fcport)
726b8548 5019{
cd4ed6b4 5020 unsigned long flags;
726b8548 5021
cd4ed6b4
QT		 5022 if (IS_SW_RESV_ADDR(fcport->d_id))
5023 return;
726b8548 5024
cd4ed6b4
QT		 5025 spin_lock_irqsave(&fcport->vha->work_lock, flags);
5026 if (fcport->disc_state == DSC_UPD_FCPORT) {
5027 spin_unlock_irqrestore(&fcport->vha->work_lock, flags);
5028 return;
5029 }
5030 fcport->jiffies_at_registration = jiffies;
5031 fcport->sec_since_registration = 0;
5032 fcport->next_disc_state = DSC_DELETED;
5033 fcport->disc_state = DSC_UPD_FCPORT;
5034 spin_unlock_irqrestore(&fcport->vha->work_lock, flags);
5035
5036 queue_work(system_unbound_wq, &fcport->reg_work);
726b8548
QT		 5037}
5038
5039static
5040void qla24xx_create_new_sess(struct scsi_qla_host *vha, struct qla_work_evt *e)
5041{
5042 unsigned long flags;
b5d15312 5043 fc_port_t *fcport = NULL, *tfcp;
726b8548
QT		 5044 struct qlt_plogi_ack_t *pla =
5045 (struct qlt_plogi_ack_t *)e->u.new_sess.pla;
b5d15312 5046 uint8_t free_fcport = 0;
726b8548 5047
9cd883f0
QT		 5048 ql_dbg(ql_dbg_disc, vha, 0xffff,
5049 "%s %d %8phC enter\n",
5050 __func__, __LINE__, e->u.new_sess.port_name);
5051
726b8548
QT		 5052 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
5053 fcport = qla2x00_find_fcport_by_wwpn(vha, e->u.new_sess.port_name, 1);
5054 if (fcport) {
5055 fcport->d_id = e->u.new_sess.id;
5056 if (pla) {
5057 fcport->fw_login_state = DSC_LS_PLOGI_PEND;
9b3e0f4d
QT		 5058 memcpy(fcport->node_name,
5059 pla->iocb.u.isp24.u.plogi.node_name,
5060 WWN_SIZE);
726b8548
QT		 5061 qlt_plogi_ack_link(vha, pla, fcport, QLT_PLOGI_LINK_SAME_WWN);
5062 /* we took an extra ref_count to prevent PLOGI ACK when
5063 * fcport/sess has not been created.
5064 */
5065 pla->ref_count--;
5066 }
5067 } else {
b5d15312 5068 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
726b8548
QT		 5069 fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
5070 if (fcport) {
5071 fcport->d_id = e->u.new_sess.id;
726b8548
QT		 5072 fcport->flags |= FCF_FABRIC_DEVICE;
5073 fcport->fw_login_state = DSC_LS_PLOGI_PEND;
c64a87f9 5074 if (e->u.new_sess.fc4_type == FS_FC4TYPE_FCP)
a4239945 5075 fcport->fc4_type = FC4_TYPE_FCP_SCSI;
726b8548 5076
c64a87f9 5077 if (e->u.new_sess.fc4_type == FS_FC4TYPE_NVME) {
2b5b9647
DT		 5078 fcport->fc4_type = FC4_TYPE_OTHER;
5079 fcport->fc4f_nvme = FC4_TYPE_NVME;
5080 }
33b28357 5081
726b8548
QT		 5082 memcpy(fcport->port_name, e->u.new_sess.port_name,
5083 WWN_SIZE);
b5d15312
QT		 5084 } else {
5085 ql_dbg(ql_dbg_disc, vha, 0xffff,
5086 "%s %8phC mem alloc fail.\n",
5087 __func__, e->u.new_sess.port_name);
5088
1df627b4
BVA		 5089 if (pla) {
5090 list_del(&pla->list);
b5d15312 5091 kmem_cache_free(qla_tgt_plogi_cachep, pla);
1df627b4 5092 }
b5d15312
QT		 5093 return;
5094 }
5095
5096 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
a4239945 5097 /* search again to make sure no one else got ahead */
b5d15312
QT		 5098 tfcp = qla2x00_find_fcport_by_wwpn(vha,
5099 e->u.new_sess.port_name, 1);
5100 if (tfcp) {
5101 /* should rarily happen */
5102 ql_dbg(ql_dbg_disc, vha, 0xffff,
5103 "%s %8phC found existing fcport b4 add. DS %d LS %d\n",
5104 __func__, tfcp->port_name, tfcp->disc_state,
5105 tfcp->fw_login_state);
5106
5107 free_fcport = 1;
5108 } else {
726b8548
QT		 5109 list_add_tail(&fcport->list, &vha->vp_fcports);
5110
19759033
QT		 5111 }
5112 if (pla) {
5113 qlt_plogi_ack_link(vha, pla, fcport,
5114 QLT_PLOGI_LINK_SAME_WWN);
5115 pla->ref_count--;
726b8548
QT		 5116 }
5117 }
5118 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
5119
5120 if (fcport) {
a4239945
QT		 5121 fcport->id_changed = 1;
5122 fcport->scan_state = QLA_FCPORT_FOUND;
8b5292bc 5123 fcport->chip_reset = vha->hw->base_qpair->chip_reset;
a4239945
QT		 5124 memcpy(fcport->node_name, e->u.new_sess.node_name, WWN_SIZE);
5125
5ef696aa 5126 if (pla) {
9cd883f0
QT		 5127 if (pla->iocb.u.isp24.status_subcode == ELS_PRLI) {
5128 u16 wd3_lo;
5129
5130 fcport->fw_login_state = DSC_LS_PRLI_PEND;
5131 fcport->local = 0;
5132 fcport->loop_id =
5133 le16_to_cpu(
5134 pla->iocb.u.isp24.nport_handle);
5135 fcport->fw_login_state = DSC_LS_PRLI_PEND;
5136 wd3_lo =
5137 le16_to_cpu(
5138 pla->iocb.u.isp24.u.prli.wd3_lo);
5139
5140 if (wd3_lo & BIT_7)
5141 fcport->conf_compl_supported = 1;
5142
5143 if ((wd3_lo & BIT_4) == 0)
5144 fcport->port_type = FCT_INITIATOR;
5145 else
5146 fcport->port_type = FCT_TARGET;
5147 }
726b8548 5148 qlt_plogi_ack_unref(vha, pla);
5ef696aa 5149 } else {
1c6cacf4
HR		 5150 fc_port_t *dfcp = NULL;
5151
5ef696aa
QT		 5152 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
5153 tfcp = qla2x00_find_fcport_by_nportid(vha,
5154 &e->u.new_sess.id, 1);
5155 if (tfcp && (tfcp != fcport)) {
5156 /*
5157 * We have a conflict fcport with same NportID.
5158 */
5159 ql_dbg(ql_dbg_disc, vha, 0xffff,
5160 "%s %8phC found conflict b4 add. DS %d LS %d\n",
5161 __func__, tfcp->port_name, tfcp->disc_state,
5162 tfcp->fw_login_state);
5163
5164 switch (tfcp->disc_state) {
5165 case DSC_DELETED:
5166 break;
5167 case DSC_DELETE_PEND:
5168 fcport->login_pause = 1;
5169 tfcp->conflict = fcport;
5170 break;
5171 default:
5172 fcport->login_pause = 1;
5173 tfcp->conflict = fcport;
1c6cacf4 5174 dfcp = tfcp;
5ef696aa
QT		 5175 break;
5176 }
5177 }
5178 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
1c6cacf4
HR		 5179 if (dfcp)
5180 qlt_schedule_sess_for_deletion(tfcp);
a4239945 5181
a4239945 5182
8777e431
QT		 5183 if (N2N_TOPO(vha->hw))
5184 fcport->flags &= ~FCF_FABRIC_DEVICE;
5185
5186 if (N2N_TOPO(vha->hw)) {
5187 if (vha->flags.nvme_enabled) {
5188 fcport->fc4f_nvme = 1;
5189 fcport->n2n_flag = 1;
5190 }
5191 fcport->fw_login_state = 0;
5192 /*
5193 * wait link init done before sending login
5194 */
5195 } else {
5196 qla24xx_fcport_handle_login(vha, fcport);
5197 }
5ef696aa 5198 }
726b8548 5199 }
b5d15312
QT		 5200
5201 if (free_fcport) {
5202 qla2x00_free_fcport(fcport);
1df627b4
BVA		 5203 if (pla) {
5204 list_del(&pla->list);
b5d15312 5205 kmem_cache_free(qla_tgt_plogi_cachep, pla);
1df627b4 5206 }
b5d15312 5207 }
726b8548
QT		 5208}
5209
e374f9f5
QT		 5210static void qla_sp_retry(struct scsi_qla_host *vha, struct qla_work_evt *e)
5211{
5212 struct srb *sp = e->u.iosb.sp;
5213 int rval;
5214
5215 rval = qla2x00_start_sp(sp);
5216 if (rval != QLA_SUCCESS) {
5217 ql_dbg(ql_dbg_disc, vha, 0x2043,
5218 "%s: %s: Re-issue IOCB failed (%d).\n",
5219 __func__, sp->name, rval);
5220 qla24xx_sp_unmap(vha, sp);
5221 }
5222}
5223
ac280b67 5224void
e315cd28 5225qla2x00_do_work(struct scsi_qla_host *vha)
0971de7f 5226{
f999f4c1
AV		 5227 struct qla_work_evt *e, *tmp;
5228 unsigned long flags;
5229 LIST_HEAD(work);
80676d05 5230 int rc;
0971de7f 5231
f999f4c1
AV		 5232 spin_lock_irqsave(&vha->work_lock, flags);
5233 list_splice_init(&vha->work_list, &work);
5234 spin_unlock_irqrestore(&vha->work_lock, flags);
5235
5236 list_for_each_entry_safe(e, tmp, &work, list) {
80676d05 5237 rc = QLA_SUCCESS;
0971de7f
AV		 5238 switch (e->type) {
5239 case QLA_EVT_AEN:
e315cd28 5240 fc_host_post_event(vha->host, fc_get_event_number(),
0971de7f
AV		 5241 e->u.aen.code, e->u.aen.data);
5242 break;
8a659571
AV		 5243 case QLA_EVT_IDC_ACK:
5244 qla81xx_idc_ack(vha, e->u.idc_ack.mb);
5245 break;
ac280b67
AV		 5246 case QLA_EVT_ASYNC_LOGIN:
5247 qla2x00_async_login(vha, e->u.logio.fcport,
5248 e->u.logio.data);
5249 break;
ac280b67 5250 case QLA_EVT_ASYNC_LOGOUT:
80676d05 5251 rc = qla2x00_async_logout(vha, e->u.logio.fcport);
ac280b67
AV		 5252 break;
5253 case QLA_EVT_ASYNC_LOGOUT_DONE:
5254 qla2x00_async_logout_done(vha, e->u.logio.fcport,
5255 e->u.logio.data);
5256 break;
5ff1d584
AV		 5257 case QLA_EVT_ASYNC_ADISC:
5258 qla2x00_async_adisc(vha, e->u.logio.fcport,
5259 e->u.logio.data);
5260 break;
3420d36c
AV		 5261 case QLA_EVT_UEVENT:
5262 qla2x00_uevent_emit(vha, e->u.uevent.code);
5263 break;
8ae6d9c7
GM		 5264 case QLA_EVT_AENFX:
5265 qlafx00_process_aen(vha, e);
5266 break;
726b8548
QT		 5267 case QLA_EVT_GPNID:
5268 qla24xx_async_gpnid(vha, &e->u.gpnid.id);
5269 break;
e374f9f5
QT		 5270 case QLA_EVT_UNMAP:
5271 qla24xx_sp_unmap(vha, e->u.iosb.sp);
726b8548 5272 break;
9b3e0f4d
QT		 5273 case QLA_EVT_RELOGIN:
5274 qla2x00_relogin(vha);
5275 break;
726b8548
QT		 5276 case QLA_EVT_NEW_SESS:
5277 qla24xx_create_new_sess(vha, e);
5278 break;
5279 case QLA_EVT_GPDB:
5280 qla24xx_async_gpdb(vha, e->u.fcport.fcport,
5281 e->u.fcport.opt);
5282 break;
a5d42f4c
DG		 5283 case QLA_EVT_PRLI:
5284 qla24xx_async_prli(vha, e->u.fcport.fcport);
5285 break;
726b8548
QT		 5286 case QLA_EVT_GPSC:
5287 qla24xx_async_gpsc(vha, e->u.fcport.fcport);
5288 break;
726b8548
QT		 5289 case QLA_EVT_GNL:
5290 qla24xx_async_gnl(vha, e->u.fcport.fcport);
5291 break;
5292 case QLA_EVT_NACK:
5293 qla24xx_do_nack_work(vha, e);
5294 break;
11aea16a 5295 case QLA_EVT_ASYNC_PRLO:
80676d05 5296 rc = qla2x00_async_prlo(vha, e->u.logio.fcport);
11aea16a
QT		 5297 break;
5298 case QLA_EVT_ASYNC_PRLO_DONE:
5299 qla2x00_async_prlo_done(vha, e->u.logio.fcport,
5300 e->u.logio.data);
5301 break;
a4239945 5302 case QLA_EVT_GPNFT:
33b28357
QT		 5303 qla24xx_async_gpnft(vha, e->u.gpnft.fc4_type,
5304 e->u.gpnft.sp);
a4239945
QT		 5305 break;
5306 case QLA_EVT_GPNFT_DONE:
5307 qla24xx_async_gpnft_done(vha, e->u.iosb.sp);
5308 break;
5309 case QLA_EVT_GNNFT_DONE:
5310 qla24xx_async_gnnft_done(vha, e->u.iosb.sp);
5311 break;
5312 case QLA_EVT_GNNID:
5313 qla24xx_async_gnnid(vha, e->u.fcport.fcport);
5314 break;
5315 case QLA_EVT_GFPNID:
5316 qla24xx_async_gfpnid(vha, e->u.fcport.fcport);
5317 break;
e374f9f5
QT		 5318 case QLA_EVT_SP_RETRY:
5319 qla_sp_retry(vha, e);
cc28e0ac
QT		 5320 break;
5321 case QLA_EVT_IIDMA:
5322 qla_do_iidma_work(vha, e->u.fcport.fcport);
5323 break;
8777e431
QT		 5324 case QLA_EVT_ELS_PLOGI:
5325 qla24xx_els_dcmd2_iocb(vha, ELS_DCMD_PLOGI,
5326 e->u.fcport.fcport, false);
5327 break;
0971de7f 5328 }
80676d05
QT		 5329
5330 if (rc == EAGAIN) {
5331 /* put 'work' at head of 'vha->work_list' */
5332 spin_lock_irqsave(&vha->work_lock, flags);
5333 list_splice(&work, &vha->work_list);
5334 spin_unlock_irqrestore(&vha->work_lock, flags);
5335 break;
5336 }
5337 list_del_init(&e->list);
0971de7f
AV		 5338 if (e->flags & QLA_EVT_FLAG_FREE)
5339 kfree(e);
feafb7b1
AE		 5340
5341 /* For each work completed decrement vha ref count */
5342 QLA_VHA_MARK_NOT_BUSY(vha);
e315cd28 5343 }
e315cd28 5344}
f999f4c1 5345
9b3e0f4d
QT		 5346int qla24xx_post_relogin_work(struct scsi_qla_host *vha)
5347{
5348 struct qla_work_evt *e;
5349
5350 e = qla2x00_alloc_work(vha, QLA_EVT_RELOGIN);
5351
5352 if (!e) {
5353 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
5354 return QLA_FUNCTION_FAILED;
5355 }
5356
5357 return qla2x00_post_work(vha, e);
5358}
5359
e315cd28
AC		 5360/* Relogins all the fcports of a vport
5361 * Context: dpc thread
5362 */
5363void qla2x00_relogin(struct scsi_qla_host *vha)
5364{
5365 fc_port_t *fcport;
23dd98a6 5366 int status, relogin_needed = 0;
726b8548 5367 struct event_arg ea;
e315cd28
AC		 5368
5369 list_for_each_entry(fcport, &vha->vp_fcports, list) {
9cd883f0
QT		 5370 /*
5371 * If the port is not ONLINE then try to login
5372 * to it if we haven't run out of retries.
5373 */
5ff1d584 5374 if (atomic_read(&fcport->state) != FCS_ONLINE &&
23dd98a6
QT		 5375 fcport->login_retry) {
5376 if (fcport->scan_state != QLA_FCPORT_FOUND ||
5377 fcport->disc_state == DSC_LOGIN_COMPLETE)
5378 continue;
e315cd28 5379
23dd98a6
QT		 5380 if (fcport->flags & (FCF_ASYNC_SENT|FCF_ASYNC_ACTIVE) ||
5381 fcport->disc_state == DSC_DELETE_PEND) {
5382 relogin_needed = 1;
5383 } else {
5384 if (vha->hw->current_topology != ISP_CFG_NL) {
5385 memset(&ea, 0, sizeof(ea));
5386 ea.event = FCME_RELOGIN;
5387 ea.fcport = fcport;
5388 qla2x00_fcport_event_handler(vha, &ea);
5389 } else if (vha->hw->current_topology ==
5390 ISP_CFG_NL) {
5391 fcport->login_retry--;
5392 status =
5393 qla2x00_local_device_login(vha,
5394 fcport);
5395 if (status == QLA_SUCCESS) {
5396 fcport->old_loop_id =
5397 fcport->loop_id;
5398 ql_dbg(ql_dbg_disc, vha, 0x2003,
5399 "Port login OK: logged in ID 0x%x.\n",
5400 fcport->loop_id);
5401 qla2x00_update_fcport
5402 (vha, fcport);
5403 } else if (status == 1) {
5404 set_bit(RELOGIN_NEEDED,
5405 &vha->dpc_flags);
5406 /* retry the login again */
5407 ql_dbg(ql_dbg_disc, vha, 0x2007,
5408 "Retrying %d login again loop_id 0x%x.\n",
5409 fcport->login_retry,
5410 fcport->loop_id);
5411 } else {
5412 fcport->login_retry = 0;
5413 }
e315cd28 5414
23dd98a6
QT		 5415 if (fcport->login_retry == 0 &&
5416 status != QLA_SUCCESS)
5417 qla2x00_clear_loop_id(fcport);
5418 }
e315cd28 5419 }
e315cd28
AC		 5420 }
5421 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
5422 break;
0971de7f 5423 }
9b3e0f4d 5424
23dd98a6
QT		 5425 if (relogin_needed)
5426 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
5427
9b3e0f4d
QT		 5428 ql_dbg(ql_dbg_disc, vha, 0x400e,
5429 "Relogin end.\n");
0971de7f
AV		 5430}
5431
7d613ac6
SV		 5432/* Schedule work on any of the dpc-workqueues */
5433void
5434qla83xx_schedule_work(scsi_qla_host_t *base_vha, int work_code)
5435{
5436 struct qla_hw_data *ha = base_vha->hw;
5437
5438 switch (work_code) {
5439 case MBA_IDC_AEN: /* 0x8200 */
5440 if (ha->dpc_lp_wq)
5441 queue_work(ha->dpc_lp_wq, &ha->idc_aen);
5442 break;
5443
5444 case QLA83XX_NIC_CORE_RESET: /* 0x1 */
5445 if (!ha->flags.nic_core_reset_hdlr_active) {
5446 if (ha->dpc_hp_wq)
5447 queue_work(ha->dpc_hp_wq, &ha->nic_core_reset);
5448 } else
5449 ql_dbg(ql_dbg_p3p, base_vha, 0xb05e,
5450 "NIC Core reset is already active. Skip "
5451 "scheduling it again.\n");
5452 break;
5453 case QLA83XX_IDC_STATE_HANDLER: /* 0x2 */
5454 if (ha->dpc_hp_wq)
5455 queue_work(ha->dpc_hp_wq, &ha->idc_state_handler);
5456 break;
5457 case QLA83XX_NIC_CORE_UNRECOVERABLE: /* 0x3 */
5458 if (ha->dpc_hp_wq)
5459 queue_work(ha->dpc_hp_wq, &ha->nic_core_unrecoverable);
5460 break;
5461 default:
5462 ql_log(ql_log_warn, base_vha, 0xb05f,
d939be3a 5463 "Unknown work-code=0x%x.\n", work_code);
7d613ac6
SV		 5464 }
5465
5466 return;
5467}
5468
5469/* Work: Perform NIC Core Unrecoverable state handling */
5470void
5471qla83xx_nic_core_unrecoverable_work(struct work_struct *work)
5472{
5473 struct qla_hw_data *ha =
2ad1b67c 5474 container_of(work, struct qla_hw_data, nic_core_unrecoverable);
7d613ac6
SV		 5475 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5476 uint32_t dev_state = 0;
5477
5478 qla83xx_idc_lock(base_vha, 0);
5479 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
5480 qla83xx_reset_ownership(base_vha);
5481 if (ha->flags.nic_core_reset_owner) {
5482 ha->flags.nic_core_reset_owner = 0;
5483 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
5484 QLA8XXX_DEV_FAILED);
5485 ql_log(ql_log_info, base_vha, 0xb060, "HW State: FAILED.\n");
5486 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
5487 }
5488 qla83xx_idc_unlock(base_vha, 0);
5489}
5490
5491/* Work: Execute IDC state handler */
5492void
5493qla83xx_idc_state_handler_work(struct work_struct *work)
5494{
5495 struct qla_hw_data *ha =
2ad1b67c 5496 container_of(work, struct qla_hw_data, idc_state_handler);
7d613ac6
SV		 5497 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5498 uint32_t dev_state = 0;
5499
5500 qla83xx_idc_lock(base_vha, 0);
5501 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
5502 if (dev_state == QLA8XXX_DEV_FAILED ||
5503 dev_state == QLA8XXX_DEV_NEED_QUIESCENT)
5504 qla83xx_idc_state_handler(base_vha);
5505 qla83xx_idc_unlock(base_vha, 0);
5506}
5507
fa492630 5508static int
7d613ac6
SV		 5509qla83xx_check_nic_core_fw_alive(scsi_qla_host_t *base_vha)
5510{
5511 int rval = QLA_SUCCESS;
5512 unsigned long heart_beat_wait = jiffies + (1 * HZ);
5513 uint32_t heart_beat_counter1, heart_beat_counter2;
5514
5515 do {
5516 if (time_after(jiffies, heart_beat_wait)) {
5517 ql_dbg(ql_dbg_p3p, base_vha, 0xb07c,
5518 "Nic Core f/w is not alive.\n");
5519 rval = QLA_FUNCTION_FAILED;
5520 break;
5521 }
5522
5523 qla83xx_idc_lock(base_vha, 0);
5524 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
5525 &heart_beat_counter1);
5526 qla83xx_idc_unlock(base_vha, 0);
5527 msleep(100);
5528 qla83xx_idc_lock(base_vha, 0);
5529 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
5530 &heart_beat_counter2);
5531 qla83xx_idc_unlock(base_vha, 0);
5532 } while (heart_beat_counter1 == heart_beat_counter2);
5533
5534 return rval;
5535}
5536
5537/* Work: Perform NIC Core Reset handling */
5538void
5539qla83xx_nic_core_reset_work(struct work_struct *work)
5540{
5541 struct qla_hw_data *ha =
5542 container_of(work, struct qla_hw_data, nic_core_reset);
5543 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5544 uint32_t dev_state = 0;
5545
81178772
SK		 5546 if (IS_QLA2031(ha)) {
5547 if (qla2xxx_mctp_dump(base_vha) != QLA_SUCCESS)
5548 ql_log(ql_log_warn, base_vha, 0xb081,
5549 "Failed to dump mctp\n");
5550 return;
5551 }
5552
7d613ac6
SV		 5553 if (!ha->flags.nic_core_reset_hdlr_active) {
5554 if (qla83xx_check_nic_core_fw_alive(base_vha) == QLA_SUCCESS) {
5555 qla83xx_idc_lock(base_vha, 0);
5556 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE,
5557 &dev_state);
5558 qla83xx_idc_unlock(base_vha, 0);
5559 if (dev_state != QLA8XXX_DEV_NEED_RESET) {
5560 ql_dbg(ql_dbg_p3p, base_vha, 0xb07a,
5561 "Nic Core f/w is alive.\n");
5562 return;
5563 }
5564 }
5565
5566 ha->flags.nic_core_reset_hdlr_active = 1;
5567 if (qla83xx_nic_core_reset(base_vha)) {
5568 /* NIC Core reset failed. */
5569 ql_dbg(ql_dbg_p3p, base_vha, 0xb061,
5570 "NIC Core reset failed.\n");
5571 }
5572 ha->flags.nic_core_reset_hdlr_active = 0;
5573 }
5574}
5575
5576/* Work: Handle 8200 IDC aens */
5577void
5578qla83xx_service_idc_aen(struct work_struct *work)
5579{
5580 struct qla_hw_data *ha =
5581 container_of(work, struct qla_hw_data, idc_aen);
5582 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5583 uint32_t dev_state, idc_control;
5584
5585 qla83xx_idc_lock(base_vha, 0);
5586 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
5587 qla83xx_rd_reg(base_vha, QLA83XX_IDC_CONTROL, &idc_control);
5588 qla83xx_idc_unlock(base_vha, 0);
5589 if (dev_state == QLA8XXX_DEV_NEED_RESET) {
5590 if (idc_control & QLA83XX_IDC_GRACEFUL_RESET) {
5591 ql_dbg(ql_dbg_p3p, base_vha, 0xb062,
5592 "Application requested NIC Core Reset.\n");
5593 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
5594 } else if (qla83xx_check_nic_core_fw_alive(base_vha) ==
5595 QLA_SUCCESS) {
5596 ql_dbg(ql_dbg_p3p, base_vha, 0xb07b,
5597 "Other protocol driver requested NIC Core Reset.\n");
5598 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
5599 }
5600 } else if (dev_state == QLA8XXX_DEV_FAILED ||
5601 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) {
5602 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
5603 }
5604}
5605
5606static void
5607qla83xx_wait_logic(void)
5608{
5609 int i;
5610
5611 /* Yield CPU */
5612 if (!in_interrupt()) {
5613 /*
5614 * Wait about 200ms before retrying again.
5615 * This controls the number of retries for single
5616 * lock operation.
5617 */
5618 msleep(100);
5619 schedule();
5620 } else {
5621 for (i = 0; i < 20; i++)
5622 cpu_relax(); /* This a nop instr on i386 */
5623 }
5624}
5625
fa492630 5626static int
7d613ac6
SV		 5627qla83xx_force_lock_recovery(scsi_qla_host_t *base_vha)
5628{
5629 int rval;
5630 uint32_t data;
5631 uint32_t idc_lck_rcvry_stage_mask = 0x3;
5632 uint32_t idc_lck_rcvry_owner_mask = 0x3c;
5633 struct qla_hw_data *ha = base_vha->hw;
bd432bb5 5634
6c315553
SK		 5635 ql_dbg(ql_dbg_p3p, base_vha, 0xb086,
5636 "Trying force recovery of the IDC lock.\n");
7d613ac6
SV		 5637
5638 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, &data);
5639 if (rval)
5640 return rval;
5641
5642 if ((data & idc_lck_rcvry_stage_mask) > 0) {
5643 return QLA_SUCCESS;
5644 } else {
5645 data = (IDC_LOCK_RECOVERY_STAGE1) | (ha->portnum << 2);
5646 rval = qla83xx_wr_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
5647 data);
5648 if (rval)
5649 return rval;
5650
5651 msleep(200);
5652
5653 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
5654 &data);
5655 if (rval)
5656 return rval;
5657
5658 if (((data & idc_lck_rcvry_owner_mask) >> 2) == ha->portnum) {
5659 data &= (IDC_LOCK_RECOVERY_STAGE2 |
5660 ~(idc_lck_rcvry_stage_mask));
5661 rval = qla83xx_wr_reg(base_vha,
5662 QLA83XX_IDC_LOCK_RECOVERY, data);
5663 if (rval)
5664 return rval;
5665
5666 /* Forcefully perform IDC UnLock */
5667 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK,
5668 &data);
5669 if (rval)
5670 return rval;
5671 /* Clear lock-id by setting 0xff */
5672 rval = qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
5673 0xff);
5674 if (rval)
5675 return rval;
5676 /* Clear lock-recovery by setting 0x0 */
5677 rval = qla83xx_wr_reg(base_vha,
5678 QLA83XX_IDC_LOCK_RECOVERY, 0x0);
5679 if (rval)
5680 return rval;
5681 } else
5682 return QLA_SUCCESS;
5683 }
5684
5685 return rval;
5686}
5687
fa492630 5688static int
7d613ac6
SV		 5689qla83xx_idc_lock_recovery(scsi_qla_host_t *base_vha)
5690{
5691 int rval = QLA_SUCCESS;
5692 uint32_t o_drv_lockid, n_drv_lockid;
5693 unsigned long lock_recovery_timeout;
5694
5695 lock_recovery_timeout = jiffies + QLA83XX_MAX_LOCK_RECOVERY_WAIT;
5696retry_lockid:
5697 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &o_drv_lockid);
5698 if (rval)
5699 goto exit;
5700
5701 /* MAX wait time before forcing IDC Lock recovery = 2 secs */
5702 if (time_after_eq(jiffies, lock_recovery_timeout)) {
5703 if (qla83xx_force_lock_recovery(base_vha) == QLA_SUCCESS)
5704 return QLA_SUCCESS;
5705 else
5706 return QLA_FUNCTION_FAILED;
5707 }
5708
5709 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &n_drv_lockid);
5710 if (rval)
5711 goto exit;
5712
5713 if (o_drv_lockid == n_drv_lockid) {
5714 qla83xx_wait_logic();
5715 goto retry_lockid;
5716 } else
5717 return QLA_SUCCESS;
5718
5719exit:
5720 return rval;
5721}
5722
5723void
5724qla83xx_idc_lock(scsi_qla_host_t *base_vha, uint16_t requester_id)
5725{
7d613ac6 5726 uint32_t data;
6c315553 5727 uint32_t lock_owner;
7d613ac6
SV		 5728 struct qla_hw_data *ha = base_vha->hw;
5729
5730 /* IDC-lock implementation using driver-lock/lock-id remote registers */
5731retry_lock:
5732 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCK, &data)
5733 == QLA_SUCCESS) {
5734 if (data) {
5735 /* Setting lock-id to our function-number */
5736 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
5737 ha->portnum);
5738 } else {
6c315553
SK		 5739 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID,
5740 &lock_owner);
7d613ac6 5741 ql_dbg(ql_dbg_p3p, base_vha, 0xb063,
6c315553
SK		 5742 "Failed to acquire IDC lock, acquired by %d, "
5743 "retrying...\n", lock_owner);
7d613ac6
SV		 5744
5745 /* Retry/Perform IDC-Lock recovery */
5746 if (qla83xx_idc_lock_recovery(base_vha)
5747 == QLA_SUCCESS) {
5748 qla83xx_wait_logic();
5749 goto retry_lock;
5750 } else
5751 ql_log(ql_log_warn, base_vha, 0xb075,
5752 "IDC Lock recovery FAILED.\n");
5753 }
5754
5755 }
5756
5757 return;
7d613ac6
SV		 5758}
5759
5760void
5761qla83xx_idc_unlock(scsi_qla_host_t *base_vha, uint16_t requester_id)
5762{
5897cb2f
BVA		 5763#if 0
5764 uint16_t options = (requester_id << 15) | BIT_7;
5765#endif
5766 uint16_t retry;
7d613ac6
SV		 5767 uint32_t data;
5768 struct qla_hw_data *ha = base_vha->hw;
5769
5770 /* IDC-unlock implementation using driver-unlock/lock-id
5771 * remote registers
5772 */
5773 retry = 0;
5774retry_unlock:
5775 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &data)
5776 == QLA_SUCCESS) {
5777 if (data == ha->portnum) {
5778 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, &data);
5779 /* Clearing lock-id by setting 0xff */
5780 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 0xff);
5781 } else if (retry < 10) {
5782 /* SV: XXX: IDC unlock retrying needed here? */
5783
5784 /* Retry for IDC-unlock */
5785 qla83xx_wait_logic();
5786 retry++;
5787 ql_dbg(ql_dbg_p3p, base_vha, 0xb064,
ee6a8773 5788 "Failed to release IDC lock, retrying=%d\n", retry);
7d613ac6
SV		 5789 goto retry_unlock;
5790 }
5791 } else if (retry < 10) {
5792 /* Retry for IDC-unlock */
5793 qla83xx_wait_logic();
5794 retry++;
5795 ql_dbg(ql_dbg_p3p, base_vha, 0xb065,
ee6a8773 5796 "Failed to read drv-lockid, retrying=%d\n", retry);
7d613ac6
SV		 5797 goto retry_unlock;
5798 }
5799
5800 return;
5801
5897cb2f 5802#if 0
7d613ac6
SV		 5803 /* XXX: IDC-unlock implementation using access-control mbx */
5804 retry = 0;
5805retry_unlock2:
5806 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
5807 if (retry < 10) {
5808 /* Retry for IDC-unlock */
5809 qla83xx_wait_logic();
5810 retry++;
5811 ql_dbg(ql_dbg_p3p, base_vha, 0xb066,
ee6a8773 5812 "Failed to release IDC lock, retrying=%d\n", retry);
7d613ac6
SV		 5813 goto retry_unlock2;
5814 }
5815 }
5816
5817 return;
5897cb2f 5818#endif
7d613ac6
SV		 5819}
5820
5821int
5822__qla83xx_set_drv_presence(scsi_qla_host_t *vha)
5823{
5824 int rval = QLA_SUCCESS;
5825 struct qla_hw_data *ha = vha->hw;
5826 uint32_t drv_presence;
5827
5828 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
5829 if (rval == QLA_SUCCESS) {
5830 drv_presence |= (1 << ha->portnum);
5831 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
5832 drv_presence);
5833 }
5834
5835 return rval;
5836}
5837
5838int
5839qla83xx_set_drv_presence(scsi_qla_host_t *vha)
5840{
5841 int rval = QLA_SUCCESS;
5842
5843 qla83xx_idc_lock(vha, 0);
5844 rval = __qla83xx_set_drv_presence(vha);
5845 qla83xx_idc_unlock(vha, 0);
5846
5847 return rval;
5848}
5849
5850int
5851__qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
5852{
5853 int rval = QLA_SUCCESS;
5854 struct qla_hw_data *ha = vha->hw;
5855 uint32_t drv_presence;
5856
5857 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
5858 if (rval == QLA_SUCCESS) {
5859 drv_presence &= ~(1 << ha->portnum);
5860 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
5861 drv_presence);
5862 }
5863
5864 return rval;
5865}
5866
5867int
5868qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
5869{
5870 int rval = QLA_SUCCESS;
5871
5872 qla83xx_idc_lock(vha, 0);
5873 rval = __qla83xx_clear_drv_presence(vha);
5874 qla83xx_idc_unlock(vha, 0);
5875
5876 return rval;
5877}
5878
fa492630 5879static void
7d613ac6
SV		 5880qla83xx_need_reset_handler(scsi_qla_host_t *vha)
5881{
5882 struct qla_hw_data *ha = vha->hw;
5883 uint32_t drv_ack, drv_presence;
5884 unsigned long ack_timeout;
5885
5886 /* Wait for IDC ACK from all functions (DRV-ACK == DRV-PRESENCE) */
5887 ack_timeout = jiffies + (ha->fcoe_reset_timeout * HZ);
5888 while (1) {
5889 qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
5890 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
807fb6d8 5891 if ((drv_ack & drv_presence) == drv_presence)
7d613ac6
SV		 5892 break;
5893
5894 if (time_after_eq(jiffies, ack_timeout)) {
5895 ql_log(ql_log_warn, vha, 0xb067,
5896 "RESET ACK TIMEOUT! drv_presence=0x%x "
5897 "drv_ack=0x%x\n", drv_presence, drv_ack);
5898 /*
5899 * The function(s) which did not ack in time are forced
5900 * to withdraw any further participation in the IDC
5901 * reset.
5902 */
5903 if (drv_ack != drv_presence)
5904 qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
5905 drv_ack);
5906 break;
5907 }
5908
5909 qla83xx_idc_unlock(vha, 0);
5910 msleep(1000);
5911 qla83xx_idc_lock(vha, 0);
5912 }
5913
5914 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_COLD);
5915 ql_log(ql_log_info, vha, 0xb068, "HW State: COLD/RE-INIT.\n");
5916}
5917
fa492630 5918static int
7d613ac6
SV		 5919qla83xx_device_bootstrap(scsi_qla_host_t *vha)
5920{
5921 int rval = QLA_SUCCESS;
5922 uint32_t idc_control;
5923
5924 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_INITIALIZING);
5925 ql_log(ql_log_info, vha, 0xb069, "HW State: INITIALIZING.\n");
5926
5927 /* Clearing IDC-Control Graceful-Reset Bit before resetting f/w */
5928 __qla83xx_get_idc_control(vha, &idc_control);
5929 idc_control &= ~QLA83XX_IDC_GRACEFUL_RESET;
5930 __qla83xx_set_idc_control(vha, 0);
5931
5932 qla83xx_idc_unlock(vha, 0);
5933 rval = qla83xx_restart_nic_firmware(vha);
5934 qla83xx_idc_lock(vha, 0);
5935
5936 if (rval != QLA_SUCCESS) {
5937 ql_log(ql_log_fatal, vha, 0xb06a,
5938 "Failed to restart NIC f/w.\n");
5939 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_FAILED);
5940 ql_log(ql_log_info, vha, 0xb06b, "HW State: FAILED.\n");
5941 } else {
5942 ql_dbg(ql_dbg_p3p, vha, 0xb06c,
5943 "Success in restarting nic f/w.\n");
5944 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_READY);
5945 ql_log(ql_log_info, vha, 0xb06d, "HW State: READY.\n");
5946 }
5947
5948 return rval;
5949}
5950
5951/* Assumes idc_lock always held on entry */
5952int
5953qla83xx_idc_state_handler(scsi_qla_host_t *base_vha)
5954{
5955 struct qla_hw_data *ha = base_vha->hw;
5956 int rval = QLA_SUCCESS;
5957 unsigned long dev_init_timeout;
5958 uint32_t dev_state;
5959
5960 /* Wait for MAX-INIT-TIMEOUT for the device to go ready */
5961 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ);
5962
5963 while (1) {
5964
5965 if (time_after_eq(jiffies, dev_init_timeout)) {
5966 ql_log(ql_log_warn, base_vha, 0xb06e,
5967 "Initialization TIMEOUT!\n");
5968 /* Init timeout. Disable further NIC Core
5969 * communication.
5970 */
5971 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
5972 QLA8XXX_DEV_FAILED);
5973 ql_log(ql_log_info, base_vha, 0xb06f,
5974 "HW State: FAILED.\n");
5975 }
5976
5977 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
5978 switch (dev_state) {
5979 case QLA8XXX_DEV_READY:
5980 if (ha->flags.nic_core_reset_owner)
5981 qla83xx_idc_audit(base_vha,
5982 IDC_AUDIT_COMPLETION);
5983 ha->flags.nic_core_reset_owner = 0;
5984 ql_dbg(ql_dbg_p3p, base_vha, 0xb070,
5985 "Reset_owner reset by 0x%x.\n",
5986 ha->portnum);
5987 goto exit;
5988 case QLA8XXX_DEV_COLD:
5989 if (ha->flags.nic_core_reset_owner)
5990 rval = qla83xx_device_bootstrap(base_vha);
5991 else {
5992 /* Wait for AEN to change device-state */
5993 qla83xx_idc_unlock(base_vha, 0);
5994 msleep(1000);
5995 qla83xx_idc_lock(base_vha, 0);
5996 }
5997 break;
5998 case QLA8XXX_DEV_INITIALIZING:
5999 /* Wait for AEN to change device-state */
6000 qla83xx_idc_unlock(base_vha, 0);
6001 msleep(1000);
6002 qla83xx_idc_lock(base_vha, 0);
6003 break;
6004 case QLA8XXX_DEV_NEED_RESET:
6005 if (!ql2xdontresethba && ha->flags.nic_core_reset_owner)
6006 qla83xx_need_reset_handler(base_vha);
6007 else {
6008 /* Wait for AEN to change device-state */
6009 qla83xx_idc_unlock(base_vha, 0);
6010 msleep(1000);
6011 qla83xx_idc_lock(base_vha, 0);
6012 }
6013 /* reset timeout value after need reset handler */
6014 dev_init_timeout = jiffies +
6015 (ha->fcoe_dev_init_timeout * HZ);
6016 break;
6017 case QLA8XXX_DEV_NEED_QUIESCENT:
6018 /* XXX: DEBUG for now */
6019 qla83xx_idc_unlock(base_vha, 0);
6020 msleep(1000);
6021 qla83xx_idc_lock(base_vha, 0);
6022 break;
6023 case QLA8XXX_DEV_QUIESCENT:
6024 /* XXX: DEBUG for now */
6025 if (ha->flags.quiesce_owner)
6026 goto exit;
6027
6028 qla83xx_idc_unlock(base_vha, 0);
6029 msleep(1000);
6030 qla83xx_idc_lock(base_vha, 0);
6031 dev_init_timeout = jiffies +
6032 (ha->fcoe_dev_init_timeout * HZ);
6033 break;
6034 case QLA8XXX_DEV_FAILED:
6035 if (ha->flags.nic_core_reset_owner)
6036 qla83xx_idc_audit(base_vha,
6037 IDC_AUDIT_COMPLETION);
6038 ha->flags.nic_core_reset_owner = 0;
6039 __qla83xx_clear_drv_presence(base_vha);
6040 qla83xx_idc_unlock(base_vha, 0);
6041 qla8xxx_dev_failed_handler(base_vha);
6042 rval = QLA_FUNCTION_FAILED;
6043 qla83xx_idc_lock(base_vha, 0);
6044 goto exit;
6045 case QLA8XXX_BAD_VALUE:
6046 qla83xx_idc_unlock(base_vha, 0);
6047 msleep(1000);
6048 qla83xx_idc_lock(base_vha, 0);
6049 break;
6050 default:
6051 ql_log(ql_log_warn, base_vha, 0xb071,
d939be3a 6052 "Unknown Device State: %x.\n", dev_state);
7d613ac6
SV		 6053 qla83xx_idc_unlock(base_vha, 0);
6054 qla8xxx_dev_failed_handler(base_vha);
6055 rval = QLA_FUNCTION_FAILED;
6056 qla83xx_idc_lock(base_vha, 0);
6057 goto exit;
6058 }
6059 }
6060
6061exit:
6062 return rval;
6063}
6064
f3ddac19
CD		 6065void
6066qla2x00_disable_board_on_pci_error(struct work_struct *work)
6067{
6068 struct qla_hw_data *ha = container_of(work, struct qla_hw_data,
6069 board_disable);
6070 struct pci_dev *pdev = ha->pdev;
6071 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
6072
726b8548
QT		 6073 /*
6074 * if UNLOAD flag is already set, then continue unload,
783e0dc4
SC		 6075 * where it was set first.
6076 */
6077 if (test_bit(UNLOADING, &base_vha->dpc_flags))
6078 return;
6079
f3ddac19
CD		 6080 ql_log(ql_log_warn, base_vha, 0x015b,
6081 "Disabling adapter.\n");
6082
efdb5760
SC		 6083 if (!atomic_read(&pdev->enable_cnt)) {
6084 ql_log(ql_log_info, base_vha, 0xfffc,
6085 "PCI device disabled, no action req for PCI error=%lx\n",
6086 base_vha->pci_flags);
6087 return;
6088 }
6089
726b8548
QT		 6090 qla2x00_wait_for_sess_deletion(base_vha);
6091
f3ddac19
CD		 6092 set_bit(UNLOADING, &base_vha->dpc_flags);
6093
6094 qla2x00_delete_all_vps(ha, base_vha);
6095
6096 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
6097
6098 qla2x00_dfs_remove(base_vha);
6099
6100 qla84xx_put_chip(base_vha);
6101
6102 if (base_vha->timer_active)
6103 qla2x00_stop_timer(base_vha);
6104
6105 base_vha->flags.online = 0;
6106
6107 qla2x00_destroy_deferred_work(ha);
6108
6109 /*
6110 * Do not try to stop beacon blink as it will issue a mailbox
6111 * command.
6112 */
6113 qla2x00_free_sysfs_attr(base_vha, false);
6114
6115 fc_remove_host(base_vha->host);
6116
6117 scsi_remove_host(base_vha->host);
6118
6119 base_vha->flags.init_done = 0;
6120 qla25xx_delete_queues(base_vha);
f3ddac19 6121 qla2x00_free_fcports(base_vha);
093df737 6122 qla2x00_free_irqs(base_vha);
f3ddac19
CD		 6123 qla2x00_mem_free(ha);
6124 qla82xx_md_free(base_vha);
6125 qla2x00_free_queues(ha);
6126
f3ddac19
CD		 6127 qla2x00_unmap_iobases(ha);
6128
6129 pci_release_selected_regions(ha->pdev, ha->bars);
f3ddac19
CD		 6130 pci_disable_pcie_error_reporting(pdev);
6131 pci_disable_device(pdev);
f3ddac19 6132
beb9e315
JL		 6133 /*
6134 * Let qla2x00_remove_one cleanup qla_hw_data on device removal.
6135 */
f3ddac19
CD		 6136}
6137
1da177e4
LT		 6138/**************************************************************************
6139* qla2x00_do_dpc
6140* This kernel thread is a task that is schedule by the interrupt handler
6141* to perform the background processing for interrupts.
6142*
6143* Notes:
6144* This task always run in the context of a kernel thread. It
6145* is kick-off by the driver's detect code and starts up
6146* up one per adapter. It immediately goes to sleep and waits for
6147* some fibre event. When either the interrupt handler or
6148* the timer routine detects a event it will one of the task
6149* bits then wake us up.
6150**************************************************************************/
6151static int
6152qla2x00_do_dpc(void *data)
6153{
e315cd28
AC		 6154 scsi_qla_host_t *base_vha;
6155 struct qla_hw_data *ha;
d7459527
MH		 6156 uint32_t online;
6157 struct qla_qpair *qpair;
1da177e4 6158
e315cd28
AC		 6159 ha = (struct qla_hw_data *)data;
6160 base_vha = pci_get_drvdata(ha->pdev);
1da177e4 6161
8698a745 6162 set_user_nice(current, MIN_NICE);
1da177e4 6163
563585ec 6164 set_current_state(TASK_INTERRUPTIBLE);
39a11240 6165 while (!kthread_should_stop()) {
7c3df132
SK		 6166 ql_dbg(ql_dbg_dpc, base_vha, 0x4000,
6167 "DPC handler sleeping.\n");
1da177e4 6168
39a11240 6169 schedule();
1da177e4 6170
c142caf0
AV		 6171 if (!base_vha->flags.init_done || ha->flags.mbox_busy)
6172 goto end_loop;
1da177e4 6173
85880801 6174 if (ha->flags.eeh_busy) {
7c3df132
SK		 6175 ql_dbg(ql_dbg_dpc, base_vha, 0x4003,
6176 "eeh_busy=%d.\n", ha->flags.eeh_busy);
c142caf0 6177 goto end_loop;
85880801
AV		 6178 }
6179
1da177e4
LT		 6180 ha->dpc_active = 1;
6181
5f28d2d7
SK		 6182 ql_dbg(ql_dbg_dpc + ql_dbg_verbose, base_vha, 0x4001,
6183 "DPC handler waking up, dpc_flags=0x%lx.\n",
6184 base_vha->dpc_flags);
1da177e4 6185
a29b3dd7
JC		 6186 if (test_bit(UNLOADING, &base_vha->dpc_flags))
6187 break;
6188
7ec0effd
AD		 6189 if (IS_P3P_TYPE(ha)) {
6190 if (IS_QLA8044(ha)) {
6191 if (test_and_clear_bit(ISP_UNRECOVERABLE,
6192 &base_vha->dpc_flags)) {
6193 qla8044_idc_lock(ha);
6194 qla8044_wr_direct(base_vha,
6195 QLA8044_CRB_DEV_STATE_INDEX,
6196 QLA8XXX_DEV_FAILED);
6197 qla8044_idc_unlock(ha);
6198 ql_log(ql_log_info, base_vha, 0x4004,
6199 "HW State: FAILED.\n");
6200 qla8044_device_state_handler(base_vha);
6201 continue;
6202 }
6203
6204 } else {
6205 if (test_and_clear_bit(ISP_UNRECOVERABLE,
6206 &base_vha->dpc_flags)) {
6207 qla82xx_idc_lock(ha);
6208 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
6209 QLA8XXX_DEV_FAILED);
6210 qla82xx_idc_unlock(ha);
6211 ql_log(ql_log_info, base_vha, 0x0151,
6212 "HW State: FAILED.\n");
6213 qla82xx_device_state_handler(base_vha);
6214 continue;
6215 }
a9083016
GM		 6216 }
6217
6218 if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED,
6219 &base_vha->dpc_flags)) {
6220
7c3df132
SK		 6221 ql_dbg(ql_dbg_dpc, base_vha, 0x4005,
6222 "FCoE context reset scheduled.\n");
a9083016
GM		 6223 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
6224 &base_vha->dpc_flags))) {
6225 if (qla82xx_fcoe_ctx_reset(base_vha)) {
6226 /* FCoE-ctx reset failed.
6227 * Escalate to chip-reset
6228 */
6229 set_bit(ISP_ABORT_NEEDED,
6230 &base_vha->dpc_flags);
6231 }
6232 clear_bit(ABORT_ISP_ACTIVE,
6233 &base_vha->dpc_flags);
6234 }
6235
7c3df132
SK		 6236 ql_dbg(ql_dbg_dpc, base_vha, 0x4006,
6237 "FCoE context reset end.\n");
a9083016 6238 }
8ae6d9c7
GM		 6239 } else if (IS_QLAFX00(ha)) {
6240 if (test_and_clear_bit(ISP_UNRECOVERABLE,
6241 &base_vha->dpc_flags)) {
6242 ql_dbg(ql_dbg_dpc, base_vha, 0x4020,
6243 "Firmware Reset Recovery\n");
6244 if (qlafx00_reset_initialize(base_vha)) {
6245 /* Failed. Abort isp later. */
6246 if (!test_bit(UNLOADING,
f92f82d6 6247 &base_vha->dpc_flags)) {
8ae6d9c7
GM		 6248 set_bit(ISP_UNRECOVERABLE,
6249 &base_vha->dpc_flags);
6250 ql_dbg(ql_dbg_dpc, base_vha,
6251 0x4021,
6252 "Reset Recovery Failed\n");
f92f82d6 6253 }
8ae6d9c7
GM		 6254 }
6255 }
6256
6257 if (test_and_clear_bit(FX00_TARGET_SCAN,
6258 &base_vha->dpc_flags)) {
6259 ql_dbg(ql_dbg_dpc, base_vha, 0x4022,
6260 "ISPFx00 Target Scan scheduled\n");
6261 if (qlafx00_rescan_isp(base_vha)) {
6262 if (!test_bit(UNLOADING,
6263 &base_vha->dpc_flags))
6264 set_bit(ISP_UNRECOVERABLE,
6265 &base_vha->dpc_flags);
6266 ql_dbg(ql_dbg_dpc, base_vha, 0x401e,
6267 "ISPFx00 Target Scan Failed\n");
6268 }
6269 ql_dbg(ql_dbg_dpc, base_vha, 0x401f,
6270 "ISPFx00 Target Scan End\n");
6271 }
e8f5e95d
AB		 6272 if (test_and_clear_bit(FX00_HOST_INFO_RESEND,
6273 &base_vha->dpc_flags)) {
6274 ql_dbg(ql_dbg_dpc, base_vha, 0x4023,
6275 "ISPFx00 Host Info resend scheduled\n");
6276 qlafx00_fx_disc(base_vha,
6277 &base_vha->hw->mr.fcport,
6278 FXDISC_REG_HOST_INFO);
6279 }
a9083016
GM		 6280 }
6281
e4e3a2ce
QT		 6282 if (test_and_clear_bit(DETECT_SFP_CHANGE,
6283 &base_vha->dpc_flags) &&
6284 !test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) {
6285 qla24xx_detect_sfp(base_vha);
6286
6287 if (ha->flags.detected_lr_sfp !=
6288 ha->flags.using_lr_setting)
6289 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
6290 }
6291
b08abbd9
QT		 6292 if (test_and_clear_bit
6293 (ISP_ABORT_NEEDED, &base_vha->dpc_flags) &&
6294 !test_bit(UNLOADING, &base_vha->dpc_flags)) {
93eca613
QT		 6295 bool do_reset = true;
6296
0645cb83 6297 switch (base_vha->qlini_mode) {
93eca613
QT		 6298 case QLA2XXX_INI_MODE_ENABLED:
6299 break;
6300 case QLA2XXX_INI_MODE_DISABLED:
0645cb83
QT		 6301 if (!qla_tgt_mode_enabled(base_vha) &&
6302 !ha->flags.fw_started)
93eca613
QT		 6303 do_reset = false;
6304 break;
6305 case QLA2XXX_INI_MODE_DUAL:
0645cb83
QT		 6306 if (!qla_dual_mode_enabled(base_vha) &&
6307 !ha->flags.fw_started)
93eca613
QT		 6308 do_reset = false;
6309 break;
6310 default:
6311 break;
6312 }
1da177e4 6313
93eca613 6314 if (do_reset && !(test_and_set_bit(ABORT_ISP_ACTIVE,
e315cd28 6315 &base_vha->dpc_flags))) {
93eca613
QT		 6316 ql_dbg(ql_dbg_dpc, base_vha, 0x4007,
6317 "ISP abort scheduled.\n");
a9083016 6318 if (ha->isp_ops->abort_isp(base_vha)) {
1da177e4
LT		 6319 /* failed. retry later */
6320 set_bit(ISP_ABORT_NEEDED,
e315cd28 6321 &base_vha->dpc_flags);
99363ef8 6322 }
e315cd28
AC		 6323 clear_bit(ABORT_ISP_ACTIVE,
6324 &base_vha->dpc_flags);
93eca613
QT		 6325 ql_dbg(ql_dbg_dpc, base_vha, 0x4008,
6326 "ISP abort end.\n");
99363ef8 6327 }
1da177e4
LT		 6328 }
6329
a394aac8
DJ		 6330 if (test_and_clear_bit(FCPORT_UPDATE_NEEDED,
6331 &base_vha->dpc_flags)) {
e315cd28 6332 qla2x00_update_fcports(base_vha);
c9c5ced9 6333 }
d97994dc 6334
8ae6d9c7
GM		 6335 if (IS_QLAFX00(ha))
6336 goto loop_resync_check;
6337
579d12b5 6338 if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) {
7c3df132
SK		 6339 ql_dbg(ql_dbg_dpc, base_vha, 0x4009,
6340 "Quiescence mode scheduled.\n");
7ec0effd
AD		 6341 if (IS_P3P_TYPE(ha)) {
6342 if (IS_QLA82XX(ha))
6343 qla82xx_device_state_handler(base_vha);
6344 if (IS_QLA8044(ha))
6345 qla8044_device_state_handler(base_vha);
8fcd6b8b
CD		 6346 clear_bit(ISP_QUIESCE_NEEDED,
6347 &base_vha->dpc_flags);
6348 if (!ha->flags.quiesce_owner) {
6349 qla2x00_perform_loop_resync(base_vha);
7ec0effd
AD		 6350 if (IS_QLA82XX(ha)) {
6351 qla82xx_idc_lock(ha);
6352 qla82xx_clear_qsnt_ready(
6353 base_vha);
6354 qla82xx_idc_unlock(ha);
6355 } else if (IS_QLA8044(ha)) {
6356 qla8044_idc_lock(ha);
6357 qla8044_clear_qsnt_ready(
6358 base_vha);
6359 qla8044_idc_unlock(ha);
6360 }
8fcd6b8b
CD		 6361 }
6362 } else {
6363 clear_bit(ISP_QUIESCE_NEEDED,
6364 &base_vha->dpc_flags);
6365 qla2x00_quiesce_io(base_vha);
579d12b5 6366 }
7c3df132
SK		 6367 ql_dbg(ql_dbg_dpc, base_vha, 0x400a,
6368 "Quiescence mode end.\n");
579d12b5
SK		 6369 }
6370
e315cd28 6371 if (test_and_clear_bit(RESET_MARKER_NEEDED,
8ae6d9c7 6372 &base_vha->dpc_flags) &&
e315cd28 6373 (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) {
1da177e4 6374
7c3df132
SK		 6375 ql_dbg(ql_dbg_dpc, base_vha, 0x400b,
6376 "Reset marker scheduled.\n");
e315cd28
AC		 6377 qla2x00_rst_aen(base_vha);
6378 clear_bit(RESET_ACTIVE, &base_vha->dpc_flags);
7c3df132
SK		 6379 ql_dbg(ql_dbg_dpc, base_vha, 0x400c,
6380 "Reset marker end.\n");
1da177e4
LT		 6381 }
6382
6383 /* Retry each device up to login retry count */
4005a995 6384 if (test_bit(RELOGIN_NEEDED, &base_vha->dpc_flags) &&
e315cd28
AC		 6385 !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) &&
6386 atomic_read(&base_vha->loop_state) != LOOP_DOWN) {
1da177e4 6387
4005a995
QT		 6388 if (!base_vha->relogin_jif ||
6389 time_after_eq(jiffies, base_vha->relogin_jif)) {
6390 base_vha->relogin_jif = jiffies + HZ;
6391 clear_bit(RELOGIN_NEEDED, &base_vha->dpc_flags);
6392
9b3e0f4d 6393 ql_dbg(ql_dbg_disc, base_vha, 0x400d,
4005a995 6394 "Relogin scheduled.\n");
9b3e0f4d 6395 qla24xx_post_relogin_work(base_vha);
4005a995 6396 }
1da177e4 6397 }
8ae6d9c7 6398loop_resync_check:
e315cd28 6399 if (test_and_clear_bit(LOOP_RESYNC_NEEDED,
8ae6d9c7 6400 &base_vha->dpc_flags)) {
1da177e4 6401
7c3df132
SK		 6402 ql_dbg(ql_dbg_dpc, base_vha, 0x400f,
6403 "Loop resync scheduled.\n");
1da177e4
LT		 6404
6405 if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE,
e315cd28 6406 &base_vha->dpc_flags))) {
1da177e4 6407
52c82823 6408 qla2x00_loop_resync(base_vha);
1da177e4 6409
e315cd28
AC		 6410 clear_bit(LOOP_RESYNC_ACTIVE,
6411 &base_vha->dpc_flags);
1da177e4
LT		 6412 }
6413
7c3df132
SK		 6414 ql_dbg(ql_dbg_dpc, base_vha, 0x4010,
6415 "Loop resync end.\n");
1da177e4
LT		 6416 }
6417
8ae6d9c7
GM		 6418 if (IS_QLAFX00(ha))
6419 goto intr_on_check;
6420
e315cd28
AC		 6421 if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) &&
6422 atomic_read(&base_vha->loop_state) == LOOP_READY) {
6423 clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags);
6424 qla2xxx_flash_npiv_conf(base_vha);
272976ca
AV		 6425 }
6426
8ae6d9c7 6427intr_on_check:
1da177e4 6428 if (!ha->interrupts_on)
fd34f556 6429 ha->isp_ops->enable_intrs(ha);
1da177e4 6430
e315cd28 6431 if (test_and_clear_bit(BEACON_BLINK_NEEDED,
90b604f2
HM		 6432 &base_vha->dpc_flags)) {
6433 if (ha->beacon_blink_led == 1)
6434 ha->isp_ops->beacon_blink(base_vha);
6435 }
f6df144c 6436
d7459527
MH		 6437 /* qpair online check */
6438 if (test_and_clear_bit(QPAIR_ONLINE_CHECK_NEEDED,
6439 &base_vha->dpc_flags)) {
6440 if (ha->flags.eeh_busy ||
6441 ha->flags.pci_channel_io_perm_failure)
6442 online = 0;
6443 else
6444 online = 1;
6445
6446 mutex_lock(&ha->mq_lock);
6447 list_for_each_entry(qpair, &base_vha->qp_list,
6448 qp_list_elem)
6449 qpair->online = online;
6450 mutex_unlock(&ha->mq_lock);
6451 }
6452
8b4673ba
QT		 6453 if (test_and_clear_bit(SET_NVME_ZIO_THRESHOLD_NEEDED,
6454 &base_vha->dpc_flags)) {
deeae7a6
DG		 6455 ql_log(ql_log_info, base_vha, 0xffffff,
6456 "nvme: SET ZIO Activity exchange threshold to %d.\n",
6457 ha->nvme_last_rptd_aen);
8b4673ba
QT		 6458 if (qla27xx_set_zio_threshold(base_vha,
6459 ha->nvme_last_rptd_aen)) {
deeae7a6 6460 ql_log(ql_log_info, base_vha, 0xffffff,
8b4673ba
QT		 6461 "nvme: Unable to SET ZIO Activity exchange threshold to %d.\n",
6462 ha->nvme_last_rptd_aen);
deeae7a6
DG		 6463 }
6464 }
6465
8b4673ba
QT		 6466 if (test_and_clear_bit(SET_ZIO_THRESHOLD_NEEDED,
6467 &base_vha->dpc_flags)) {
6468 ql_log(ql_log_info, base_vha, 0xffffff,
6469 "SET ZIO Activity exchange threshold to %d.\n",
6470 ha->last_zio_threshold);
6471 qla27xx_set_zio_threshold(base_vha,
6472 ha->last_zio_threshold);
6473 }
6474
8ae6d9c7
GM		 6475 if (!IS_QLAFX00(ha))
6476 qla2x00_do_dpc_all_vps(base_vha);
2c3dfe3f 6477
48acad09
QT		 6478 if (test_and_clear_bit(N2N_LINK_RESET,
6479 &base_vha->dpc_flags)) {
6480 qla2x00_lip_reset(base_vha);
6481 }
6482
1da177e4 6483 ha->dpc_active = 0;
c142caf0 6484end_loop:
563585ec 6485 set_current_state(TASK_INTERRUPTIBLE);
1da177e4 6486 } /* End of while(1) */
563585ec 6487 __set_current_state(TASK_RUNNING);
1da177e4 6488
7c3df132
SK		 6489 ql_dbg(ql_dbg_dpc, base_vha, 0x4011,
6490 "DPC handler exiting.\n");
1da177e4
LT		 6491
6492 /*
6493 * Make sure that nobody tries to wake us up again.
6494 */
1da177e4
LT		 6495 ha->dpc_active = 0;
6496
ac280b67
AV		 6497 /* Cleanup any residual CTX SRBs. */
6498 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
6499
39a11240
CH		 6500 return 0;
6501}
6502
6503void
e315cd28 6504qla2xxx_wake_dpc(struct scsi_qla_host *vha)
39a11240 6505{
e315cd28 6506 struct qla_hw_data *ha = vha->hw;
c795c1e4
AV		 6507 struct task_struct *t = ha->dpc_thread;
6508
e315cd28 6509 if (!test_bit(UNLOADING, &vha->dpc_flags) && t)
c795c1e4 6510 wake_up_process(t);
1da177e4
LT		 6511}
6512
1da177e4
LT		 6513/*
6514* qla2x00_rst_aen
6515* Processes asynchronous reset.
6516*
6517* Input:
6518* ha = adapter block pointer.
6519*/
6520static void
e315cd28 6521qla2x00_rst_aen(scsi_qla_host_t *vha)
1da177e4 6522{
e315cd28
AC		 6523 if (vha->flags.online && !vha->flags.reset_active &&
6524 !atomic_read(&vha->loop_down_timer) &&
6525 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) {
1da177e4 6526 do {
e315cd28 6527 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
1da177e4
LT		 6528
6529 /*
6530 * Issue marker command only when we are going to start
6531 * the I/O.
6532 */
e315cd28
AC		 6533 vha->marker_needed = 1;
6534 } while (!atomic_read(&vha->loop_down_timer) &&
6535 (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)));
1da177e4
LT		 6536 }
6537}
6538
1da177e4
LT		 6539/**************************************************************************
6540* qla2x00_timer
6541*
6542* Description:
6543* One second timer
6544*
6545* Context: Interrupt
6546***************************************************************************/
2c3dfe3f 6547void
8e5f4ba0 6548qla2x00_timer(struct timer_list *t)
1da177e4 6549{
8e5f4ba0 6550 scsi_qla_host_t *vha = from_timer(vha, t, timer);
1da177e4 6551 unsigned long cpu_flags = 0;
1da177e4
LT		 6552 int start_dpc = 0;
6553 int index;
6554 srb_t *sp;
85880801 6555 uint16_t w;
e315cd28 6556 struct qla_hw_data *ha = vha->hw;
73208dfd 6557 struct req_que *req;
85880801 6558
a5b36321 6559 if (ha->flags.eeh_busy) {
7c3df132
SK		 6560 ql_dbg(ql_dbg_timer, vha, 0x6000,
6561 "EEH = %d, restarting timer.\n",
6562 ha->flags.eeh_busy);
a5b36321
LC		 6563 qla2x00_restart_timer(vha, WATCH_INTERVAL);
6564 return;
6565 }
6566
f3ddac19
CD		 6567 /*
6568 * Hardware read to raise pending EEH errors during mailbox waits. If
6569 * the read returns -1 then disable the board.
6570 */
6571 if (!pci_channel_offline(ha->pdev)) {
85880801 6572 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w);
c821e0d5 6573 qla2x00_check_reg16_for_disconnect(vha, w);
f3ddac19 6574 }
1da177e4 6575
cefcaba6 6576 /* Make sure qla82xx_watchdog is run only for physical port */
7ec0effd 6577 if (!vha->vp_idx && IS_P3P_TYPE(ha)) {
579d12b5
SK		 6578 if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags))
6579 start_dpc++;
7ec0effd
AD		 6580 if (IS_QLA82XX(ha))
6581 qla82xx_watchdog(vha);
6582 else if (IS_QLA8044(ha))
6583 qla8044_watchdog(vha);
579d12b5
SK		 6584 }
6585
8ae6d9c7
GM		 6586 if (!vha->vp_idx && IS_QLAFX00(ha))
6587 qlafx00_timer_routine(vha);
6588
1da177e4 6589 /* Loop down handler. */
e315cd28 6590 if (atomic_read(&vha->loop_down_timer) > 0 &&
8f7daead
GM		 6591 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) &&
6592 !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags))
e315cd28 6593 && vha->flags.online) {
1da177e4 6594
e315cd28
AC		 6595 if (atomic_read(&vha->loop_down_timer) ==
6596 vha->loop_down_abort_time) {
1da177e4 6597
7c3df132
SK		 6598 ql_log(ql_log_info, vha, 0x6008,
6599 "Loop down - aborting the queues before time expires.\n");
1da177e4 6600
e315cd28
AC		 6601 if (!IS_QLA2100(ha) && vha->link_down_timeout)
6602 atomic_set(&vha->loop_state, LOOP_DEAD);
1da177e4 6603
f08b7251
AV		 6604 /*
6605 * Schedule an ISP abort to return any FCP2-device
6606 * commands.
6607 */
2c3dfe3f 6608 /* NPIV - scan physical port only */
e315cd28 6609 if (!vha->vp_idx) {
2c3dfe3f
SJ		 6610 spin_lock_irqsave(&ha->hardware_lock,
6611 cpu_flags);
73208dfd 6612 req = ha->req_q_map[0];
2c3dfe3f 6613 for (index = 1;
8d93f550 6614 index < req->num_outstanding_cmds;
2c3dfe3f
SJ		 6615 index++) {
6616 fc_port_t *sfcp;
6617
e315cd28 6618 sp = req->outstanding_cmds[index];
2c3dfe3f
SJ		 6619 if (!sp)
6620 continue;
c5419e26
QT		 6621 if (sp->cmd_type != TYPE_SRB)
6622 continue;
9ba56b95 6623 if (sp->type != SRB_SCSI_CMD)
cf53b069 6624 continue;
2c3dfe3f 6625 sfcp = sp->fcport;
f08b7251 6626 if (!(sfcp->flags & FCF_FCP2_DEVICE))
2c3dfe3f 6627 continue;
bdf79621 6628
8f7daead
GM		 6629 if (IS_QLA82XX(ha))
6630 set_bit(FCOE_CTX_RESET_NEEDED,
6631 &vha->dpc_flags);
6632 else
6633 set_bit(ISP_ABORT_NEEDED,
e315cd28 6634 &vha->dpc_flags);
2c3dfe3f
SJ		 6635 break;
6636 }
6637 spin_unlock_irqrestore(&ha->hardware_lock,
e315cd28 6638 cpu_flags);
1da177e4 6639 }
1da177e4
LT		 6640 start_dpc++;
6641 }
6642
6643 /* if the loop has been down for 4 minutes, reinit adapter */
e315cd28 6644 if (atomic_dec_and_test(&vha->loop_down_timer) != 0) {
0d6e61bc 6645 if (!(vha->device_flags & DFLG_NO_CABLE)) {
7c3df132 6646 ql_log(ql_log_warn, vha, 0x6009,
1da177e4
LT		 6647 "Loop down - aborting ISP.\n");
6648
8f7daead
GM		 6649 if (IS_QLA82XX(ha))
6650 set_bit(FCOE_CTX_RESET_NEEDED,
6651 &vha->dpc_flags);
6652 else
6653 set_bit(ISP_ABORT_NEEDED,
6654 &vha->dpc_flags);
1da177e4
LT		 6655 }
6656 }
7c3df132
SK		 6657 ql_dbg(ql_dbg_timer, vha, 0x600a,
6658 "Loop down - seconds remaining %d.\n",
6659 atomic_read(&vha->loop_down_timer));
1da177e4 6660 }
cefcaba6
SK		 6661 /* Check if beacon LED needs to be blinked for physical host only */
6662 if (!vha->vp_idx && (ha->beacon_blink_led == 1)) {
999916dc 6663 /* There is no beacon_blink function for ISP82xx */
7ec0effd 6664 if (!IS_P3P_TYPE(ha)) {
999916dc
SK		 6665 set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags);
6666 start_dpc++;
6667 }
f6df144c 6668 }
6669
550bf57d 6670 /* Process any deferred work. */
9b3e0f4d
QT		 6671 if (!list_empty(&vha->work_list)) {
6672 unsigned long flags;
6673 bool q = false;
6674
6675 spin_lock_irqsave(&vha->work_lock, flags);
6676 if (!test_and_set_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags))
6677 q = true;
6678 spin_unlock_irqrestore(&vha->work_lock, flags);
6679 if (q)
6680 queue_work(vha->hw->wq, &vha->iocb_work);
6681 }
550bf57d 6682
7401bc18
DG		 6683 /*
6684 * FC-NVME
6685 * see if the active AEN count has changed from what was last reported.
6686 */
b2d1453a
GM		 6687 if (!vha->vp_idx &&
6688 (atomic_read(&ha->nvme_active_aen_cnt) != ha->nvme_last_rptd_aen) &&
6689 ha->zio_mode == QLA_ZIO_MODE_6 &&
6690 !ha->flags.host_shutting_down) {
7401bc18 6691 ql_log(ql_log_info, vha, 0x3002,
8b4673ba
QT		 6692 "nvme: Sched: Set ZIO exchange threshold to %d.\n",
6693 ha->nvme_last_rptd_aen);
deeae7a6 6694 ha->nvme_last_rptd_aen = atomic_read(&ha->nvme_active_aen_cnt);
8b4673ba
QT		 6695 set_bit(SET_NVME_ZIO_THRESHOLD_NEEDED, &vha->dpc_flags);
6696 start_dpc++;
6697 }
6698
6699 if (!vha->vp_idx &&
6700 (atomic_read(&ha->zio_threshold) != ha->last_zio_threshold) &&
6701 (ha->zio_mode == QLA_ZIO_MODE_6) &&
ecc89f25 6702 (IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))) {
8b4673ba
QT		 6703 ql_log(ql_log_info, vha, 0x3002,
6704 "Sched: Set ZIO exchange threshold to %d.\n",
6705 ha->last_zio_threshold);
6706 ha->last_zio_threshold = atomic_read(&ha->zio_threshold);
deeae7a6
DG		 6707 set_bit(SET_ZIO_THRESHOLD_NEEDED, &vha->dpc_flags);
6708 start_dpc++;
7401bc18
DG		 6709 }
6710
1da177e4 6711 /* Schedule the DPC routine if needed */
e315cd28
AC		 6712 if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) ||
6713 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) ||
6714 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags) ||
1da177e4 6715 start_dpc ||
e315cd28
AC		 6716 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) ||
6717 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) ||
a9083016
GM		 6718 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) ||
6719 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) ||
e315cd28 6720 test_bit(VP_DPC_NEEDED, &vha->dpc_flags) ||
50280c01 6721 test_bit(RELOGIN_NEEDED, &vha->dpc_flags))) {
7c3df132
SK		 6722 ql_dbg(ql_dbg_timer, vha, 0x600b,
6723 "isp_abort_needed=%d loop_resync_needed=%d "
6724 "fcport_update_needed=%d start_dpc=%d "
6725 "reset_marker_needed=%d",
6726 test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags),
6727 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags),
6728 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags),
6729 start_dpc,
6730 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags));
6731 ql_dbg(ql_dbg_timer, vha, 0x600c,
6732 "beacon_blink_needed=%d isp_unrecoverable=%d "
6733 "fcoe_ctx_reset_needed=%d vp_dpc_needed=%d "
50280c01 6734 "relogin_needed=%d.\n",
7c3df132
SK		 6735 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags),
6736 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags),
6737 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags),
6738 test_bit(VP_DPC_NEEDED, &vha->dpc_flags),
50280c01 6739 test_bit(RELOGIN_NEEDED, &vha->dpc_flags));
e315cd28 6740 qla2xxx_wake_dpc(vha);
7c3df132 6741 }
1da177e4 6742
e315cd28 6743 qla2x00_restart_timer(vha, WATCH_INTERVAL);
1da177e4
LT		 6744}
6745
5433383e
AV		 6746/* Firmware interface routines. */
6747
5433383e
AV		 6748#define FW_ISP21XX 0
6749#define FW_ISP22XX 1
6750#define FW_ISP2300 2
6751#define FW_ISP2322 3
48c02fde 6752#define FW_ISP24XX 4
c3a2f0df 6753#define FW_ISP25XX 5
3a03eb79 6754#define FW_ISP81XX 6
a9083016 6755#define FW_ISP82XX 7
6246b8a1
GM		 6756#define FW_ISP2031 8
6757#define FW_ISP8031 9
2c5bbbb2 6758#define FW_ISP27XX 10
ecc89f25 6759#define FW_ISP28XX 11
5433383e 6760
bb8ee499
AV		 6761#define FW_FILE_ISP21XX "ql2100_fw.bin"
6762#define FW_FILE_ISP22XX "ql2200_fw.bin"
6763#define FW_FILE_ISP2300 "ql2300_fw.bin"
6764#define FW_FILE_ISP2322 "ql2322_fw.bin"
6765#define FW_FILE_ISP24XX "ql2400_fw.bin"
c3a2f0df 6766#define FW_FILE_ISP25XX "ql2500_fw.bin"
3a03eb79 6767#define FW_FILE_ISP81XX "ql8100_fw.bin"
a9083016 6768#define FW_FILE_ISP82XX "ql8200_fw.bin"
6246b8a1
GM		 6769#define FW_FILE_ISP2031 "ql2600_fw.bin"
6770#define FW_FILE_ISP8031 "ql8300_fw.bin"
2c5bbbb2 6771#define FW_FILE_ISP27XX "ql2700_fw.bin"
ecc89f25 6772#define FW_FILE_ISP28XX "ql2800_fw.bin"
f73cb695 6773
bb8ee499 6774
e1e82b6f 6775static DEFINE_MUTEX(qla_fw_lock);
5433383e 6776
ecc89f25 6777static struct fw_blob qla_fw_blobs[] = {
bb8ee499
AV		 6778 { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, },
6779 { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, },
6780 { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, },
6781 { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, },
6782 { .name = FW_FILE_ISP24XX, },
c3a2f0df 6783 { .name = FW_FILE_ISP25XX, },
3a03eb79 6784 { .name = FW_FILE_ISP81XX, },
a9083016 6785 { .name = FW_FILE_ISP82XX, },
6246b8a1
GM		 6786 { .name = FW_FILE_ISP2031, },
6787 { .name = FW_FILE_ISP8031, },
2c5bbbb2 6788 { .name = FW_FILE_ISP27XX, },
ecc89f25
JC		 6789 { .name = FW_FILE_ISP28XX, },
6790 { .name = NULL, },
5433383e
AV		 6791};
6792
6793struct fw_blob *
e315cd28 6794qla2x00_request_firmware(scsi_qla_host_t *vha)
5433383e 6795{
e315cd28 6796 struct qla_hw_data *ha = vha->hw;
5433383e
AV		 6797 struct fw_blob *blob;
6798
5433383e
AV		 6799 if (IS_QLA2100(ha)) {
6800 blob = &qla_fw_blobs[FW_ISP21XX];
6801 } else if (IS_QLA2200(ha)) {
6802 blob = &qla_fw_blobs[FW_ISP22XX];
48c02fde 6803 } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
5433383e 6804 blob = &qla_fw_blobs[FW_ISP2300];
48c02fde 6805 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
5433383e 6806 blob = &qla_fw_blobs[FW_ISP2322];
4d4df193 6807 } else if (IS_QLA24XX_TYPE(ha)) {
5433383e 6808 blob = &qla_fw_blobs[FW_ISP24XX];
c3a2f0df
AV		 6809 } else if (IS_QLA25XX(ha)) {
6810 blob = &qla_fw_blobs[FW_ISP25XX];
3a03eb79
AV		 6811 } else if (IS_QLA81XX(ha)) {
6812 blob = &qla_fw_blobs[FW_ISP81XX];
a9083016
GM		 6813 } else if (IS_QLA82XX(ha)) {
6814 blob = &qla_fw_blobs[FW_ISP82XX];
6246b8a1
GM		 6815 } else if (IS_QLA2031(ha)) {
6816 blob = &qla_fw_blobs[FW_ISP2031];
6817 } else if (IS_QLA8031(ha)) {
6818 blob = &qla_fw_blobs[FW_ISP8031];
2c5bbbb2
JC		 6819 } else if (IS_QLA27XX(ha)) {
6820 blob = &qla_fw_blobs[FW_ISP27XX];
ecc89f25
JC		 6821 } else if (IS_QLA28XX(ha)) {
6822 blob = &qla_fw_blobs[FW_ISP28XX];
8a655229
DC		 6823 } else {
6824 return NULL;
5433383e
AV		 6825 }
6826
ecc89f25
JC		 6827 if (!blob->name)
6828 return NULL;
6829
e1e82b6f 6830 mutex_lock(&qla_fw_lock);
5433383e
AV		 6831 if (blob->fw)
6832 goto out;
6833
6834 if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) {
7c3df132
SK		 6835 ql_log(ql_log_warn, vha, 0x0063,
6836 "Failed to load firmware image (%s).\n", blob->name);
5433383e
AV		 6837 blob->fw = NULL;
6838 blob = NULL;
5433383e
AV		 6839 }
6840
6841out:
e1e82b6f 6842 mutex_unlock(&qla_fw_lock);
5433383e
AV		 6843 return blob;
6844}
6845
6846static void
6847qla2x00_release_firmware(void)
6848{
ecc89f25 6849 struct fw_blob *blob;
5433383e 6850
e1e82b6f 6851 mutex_lock(&qla_fw_lock);
ecc89f25
JC		 6852 for (blob = qla_fw_blobs; blob->name; blob++)
6853 release_firmware(blob->fw);
e1e82b6f 6854 mutex_unlock(&qla_fw_lock);
5433383e
AV		 6855}
6856
5386a4e6
QT		 6857static void qla_pci_error_cleanup(scsi_qla_host_t *vha)
6858{
6859 struct qla_hw_data *ha = vha->hw;
6860 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
6861 struct qla_qpair *qpair = NULL;
6862 struct scsi_qla_host *vp;
6863 fc_port_t *fcport;
6864 int i;
6865 unsigned long flags;
6866
6867 ha->chip_reset++;
6868
6869 ha->base_qpair->chip_reset = ha->chip_reset;
6870 for (i = 0; i < ha->max_qpairs; i++) {
6871 if (ha->queue_pair_map[i])
6872 ha->queue_pair_map[i]->chip_reset =
6873 ha->base_qpair->chip_reset;
6874 }
6875
6876 /* purge MBox commands */
6877 if (atomic_read(&ha->num_pend_mbx_stage3)) {
6878 clear_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags);
6879 complete(&ha->mbx_intr_comp);
6880 }
6881
6882 i = 0;
6883
6884 while (atomic_read(&ha->num_pend_mbx_stage3) ||
6885 atomic_read(&ha->num_pend_mbx_stage2) ||
6886 atomic_read(&ha->num_pend_mbx_stage1)) {
6887 msleep(20);
6888 i++;
6889 if (i > 50)
6890 break;
6891 }
6892
6893 ha->flags.purge_mbox = 0;
6894
6895 mutex_lock(&ha->mq_lock);
6896 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem)
6897 qpair->online = 0;
6898 mutex_unlock(&ha->mq_lock);
6899
6900 qla2x00_mark_all_devices_lost(vha, 0);
6901
6902 spin_lock_irqsave(&ha->vport_slock, flags);
6903 list_for_each_entry(vp, &ha->vp_list, list) {
6904 atomic_inc(&vp->vref_count);
6905 spin_unlock_irqrestore(&ha->vport_slock, flags);
6906 qla2x00_mark_all_devices_lost(vp, 0);
6907 spin_lock_irqsave(&ha->vport_slock, flags);
6908 atomic_dec(&vp->vref_count);
6909 }
6910 spin_unlock_irqrestore(&ha->vport_slock, flags);
6911
6912 /* Clear all async request states across all VPs. */
6913 list_for_each_entry(fcport, &vha->vp_fcports, list)
6914 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
6915
6916 spin_lock_irqsave(&ha->vport_slock, flags);
6917 list_for_each_entry(vp, &ha->vp_list, list) {
6918 atomic_inc(&vp->vref_count);
6919 spin_unlock_irqrestore(&ha->vport_slock, flags);
6920 list_for_each_entry(fcport, &vp->vp_fcports, list)
6921 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
6922 spin_lock_irqsave(&ha->vport_slock, flags);
6923 atomic_dec(&vp->vref_count);
6924 }
6925 spin_unlock_irqrestore(&ha->vport_slock, flags);
6926}
6927
6928
14e660e6
SJ		 6929static pci_ers_result_t
6930qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
6931{
85880801
AV		 6932 scsi_qla_host_t *vha = pci_get_drvdata(pdev);
6933 struct qla_hw_data *ha = vha->hw;
6934
7c3df132
SK		 6935 ql_dbg(ql_dbg_aer, vha, 0x9000,
6936 "PCI error detected, state %x.\n", state);
b9b12f73 6937
efdb5760
SC		 6938 if (!atomic_read(&pdev->enable_cnt)) {
6939 ql_log(ql_log_info, vha, 0xffff,
6940 "PCI device is disabled,state %x\n", state);
6941 return PCI_ERS_RESULT_NEED_RESET;
6942 }
6943
14e660e6
SJ		 6944 switch (state) {
6945 case pci_channel_io_normal:
85880801 6946 ha->flags.eeh_busy = 0;
c38d1baf 6947 if (ql2xmqsupport || ql2xnvmeenable) {
d7459527
MH		 6948 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags);
6949 qla2xxx_wake_dpc(vha);
6950 }
14e660e6
SJ		 6951 return PCI_ERS_RESULT_CAN_RECOVER;
6952 case pci_channel_io_frozen:
85880801 6953 ha->flags.eeh_busy = 1;
5386a4e6 6954 qla_pci_error_cleanup(vha);
14e660e6
SJ		 6955 return PCI_ERS_RESULT_NEED_RESET;
6956 case pci_channel_io_perm_failure:
85880801
AV		 6957 ha->flags.pci_channel_io_perm_failure = 1;
6958 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
c38d1baf 6959 if (ql2xmqsupport || ql2xnvmeenable) {
d7459527
MH		 6960 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags);
6961 qla2xxx_wake_dpc(vha);
6962 }
14e660e6
SJ		 6963 return PCI_ERS_RESULT_DISCONNECT;
6964 }
6965 return PCI_ERS_RESULT_NEED_RESET;
6966}
6967
6968static pci_ers_result_t
6969qla2xxx_pci_mmio_enabled(struct pci_dev *pdev)
6970{
6971 int risc_paused = 0;
6972 uint32_t stat;
6973 unsigned long flags;
e315cd28
AC		 6974 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
6975 struct qla_hw_data *ha = base_vha->hw;
14e660e6
SJ		 6976 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
6977 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
6978
bcc5b6d3
SK		 6979 if (IS_QLA82XX(ha))
6980 return PCI_ERS_RESULT_RECOVERED;
6981
14e660e6
SJ		 6982 spin_lock_irqsave(&ha->hardware_lock, flags);
6983 if (IS_QLA2100(ha) || IS_QLA2200(ha)){
6984 stat = RD_REG_DWORD(&reg->hccr);
6985 if (stat & HCCR_RISC_PAUSE)
6986 risc_paused = 1;
6987 } else if (IS_QLA23XX(ha)) {
6988 stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
6989 if (stat & HSR_RISC_PAUSED)
6990 risc_paused = 1;
6991 } else if (IS_FWI2_CAPABLE(ha)) {
6992 stat = RD_REG_DWORD(&reg24->host_status);
6993 if (stat & HSRX_RISC_PAUSED)
6994 risc_paused = 1;
6995 }
6996 spin_unlock_irqrestore(&ha->hardware_lock, flags);
6997
6998 if (risc_paused) {
7c3df132
SK		 6999 ql_log(ql_log_info, base_vha, 0x9003,
7000 "RISC paused -- mmio_enabled, Dumping firmware.\n");
e315cd28 7001 ha->isp_ops->fw_dump(base_vha, 0);
14e660e6
SJ		 7002
7003 return PCI_ERS_RESULT_NEED_RESET;
7004 } else
7005 return PCI_ERS_RESULT_RECOVERED;
7006}
7007
7008static pci_ers_result_t
7009qla2xxx_pci_slot_reset(struct pci_dev *pdev)
7010{
7011 pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT;
e315cd28
AC		 7012 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
7013 struct qla_hw_data *ha = base_vha->hw;
5386a4e6
QT		 7014 int rc;
7015 struct qla_qpair *qpair = NULL;
09483916 7016
7c3df132
SK		 7017 ql_dbg(ql_dbg_aer, base_vha, 0x9004,
7018 "Slot Reset.\n");
85880801 7019
90a86fc0
JC		 7020 /* Workaround: qla2xxx driver which access hardware earlier
7021 * needs error state to be pci_channel_io_online.
7022 * Otherwise mailbox command timesout.
7023 */
7024 pdev->error_state = pci_channel_io_normal;
7025
7026 pci_restore_state(pdev);
7027
8c1496bd
RL		 7028 /* pci_restore_state() clears the saved_state flag of the device
7029 * save restored state which resets saved_state flag
7030 */
7031 pci_save_state(pdev);
7032
09483916
BH		 7033 if (ha->mem_only)
7034 rc = pci_enable_device_mem(pdev);
7035 else
7036 rc = pci_enable_device(pdev);
14e660e6 7037
09483916 7038 if (rc) {
7c3df132 7039 ql_log(ql_log_warn, base_vha, 0x9005,
14e660e6 7040 "Can't re-enable PCI device after reset.\n");
a5b36321 7041 goto exit_slot_reset;
14e660e6 7042 }
14e660e6 7043
90a86fc0 7044
e315cd28 7045 if (ha->isp_ops->pci_config(base_vha))
a5b36321
LC		 7046 goto exit_slot_reset;
7047
5386a4e6
QT		 7048 mutex_lock(&ha->mq_lock);
7049 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem)
7050 qpair->online = 1;
7051 mutex_unlock(&ha->mq_lock);
85880801 7052
5386a4e6 7053 base_vha->flags.online = 1;
e315cd28 7054 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
a9083016 7055 if (ha->isp_ops->abort_isp(base_vha) == QLA_SUCCESS)
14e660e6 7056 ret = PCI_ERS_RESULT_RECOVERED;
e315cd28 7057 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
14e660e6 7058
90a86fc0 7059
a5b36321 7060exit_slot_reset:
7c3df132
SK		 7061 ql_dbg(ql_dbg_aer, base_vha, 0x900e,
7062 "slot_reset return %x.\n", ret);
85880801 7063
14e660e6
SJ		 7064 return ret;
7065}
7066
7067static void
7068qla2xxx_pci_resume(struct pci_dev *pdev)
7069{
e315cd28
AC		 7070 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
7071 struct qla_hw_data *ha = base_vha->hw;
14e660e6
SJ		 7072 int ret;
7073
7c3df132
SK		 7074 ql_dbg(ql_dbg_aer, base_vha, 0x900f,
7075 "pci_resume.\n");
85880801 7076
5386a4e6
QT		 7077 ha->flags.eeh_busy = 0;
7078
e315cd28 7079 ret = qla2x00_wait_for_hba_online(base_vha);
14e660e6 7080 if (ret != QLA_SUCCESS) {
7c3df132
SK		 7081 ql_log(ql_log_fatal, base_vha, 0x9002,
7082 "The device failed to resume I/O from slot/link_reset.\n");
14e660e6 7083 }
14e660e6
SJ		 7084}
7085
590f806d
QT		 7086static void
7087qla_pci_reset_prepare(struct pci_dev *pdev)
7088{
7089 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
7090 struct qla_hw_data *ha = base_vha->hw;
7091 struct qla_qpair *qpair;
7092
7093 ql_log(ql_log_warn, base_vha, 0xffff,
7094 "%s.\n", __func__);
7095
7096 /*
7097 * PCI FLR/function reset is about to reset the
7098 * slot. Stop the chip to stop all DMA access.
7099 * It is assumed that pci_reset_done will be called
7100 * after FLR to resume Chip operation.
7101 */
7102 ha->flags.eeh_busy = 1;
7103 mutex_lock(&ha->mq_lock);
7104 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem)
7105 qpair->online = 0;
7106 mutex_unlock(&ha->mq_lock);
7107
7108 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
7109 qla2x00_abort_isp_cleanup(base_vha);
7110 qla2x00_abort_all_cmds(base_vha, DID_RESET << 16);
7111}
7112
7113static void
7114qla_pci_reset_done(struct pci_dev *pdev)
7115{
7116 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
7117 struct qla_hw_data *ha = base_vha->hw;
7118 struct qla_qpair *qpair;
7119
7120 ql_log(ql_log_warn, base_vha, 0xffff,
7121 "%s.\n", __func__);
7122
7123 /*
7124 * FLR just completed by PCI layer. Resume adapter
7125 */
7126 ha->flags.eeh_busy = 0;
7127 mutex_lock(&ha->mq_lock);
7128 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem)
7129 qpair->online = 1;
7130 mutex_unlock(&ha->mq_lock);
7131
7132 base_vha->flags.online = 1;
7133 ha->isp_ops->abort_isp(base_vha);
7134 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
7135}
7136
5601236b
MH		 7137static int qla2xxx_map_queues(struct Scsi_Host *shost)
7138{
d68b850e 7139 int rc;
5601236b 7140 scsi_qla_host_t *vha = (scsi_qla_host_t *)shost->hostdata;
485b0eca 7141 struct blk_mq_queue_map *qmap = &shost->tag_set.map[HCTX_TYPE_DEFAULT];
5601236b 7142
f3e02695 7143 if (USER_CTRL_IRQ(vha->hw) || !vha->hw->mqiobase)
ed76e329 7144 rc = blk_mq_map_queues(qmap);
d68b850e 7145 else
f0783d43 7146 rc = blk_mq_pci_map_queues(qmap, vha->hw->pdev, vha->irq_offset);
d68b850e 7147 return rc;
5601236b
MH		 7148}
7149
6515ad71
BVA		 7150struct scsi_host_template qla2xxx_driver_template = {
7151 .module = THIS_MODULE,
7152 .name = QLA2XXX_DRIVER_NAME,
7153 .queuecommand = qla2xxx_queuecommand,
7154
7155 .eh_timed_out = fc_eh_timed_out,
7156 .eh_abort_handler = qla2xxx_eh_abort,
7157 .eh_device_reset_handler = qla2xxx_eh_device_reset,
7158 .eh_target_reset_handler = qla2xxx_eh_target_reset,
7159 .eh_bus_reset_handler = qla2xxx_eh_bus_reset,
7160 .eh_host_reset_handler = qla2xxx_eh_host_reset,
7161
7162 .slave_configure = qla2xxx_slave_configure,
7163
7164 .slave_alloc = qla2xxx_slave_alloc,
7165 .slave_destroy = qla2xxx_slave_destroy,
7166 .scan_finished = qla2xxx_scan_finished,
7167 .scan_start = qla2xxx_scan_start,
7168 .change_queue_depth = scsi_change_queue_depth,
7169 .map_queues = qla2xxx_map_queues,
7170 .this_id = -1,
7171 .cmd_per_lun = 3,
7172 .sg_tablesize = SG_ALL,
7173
7174 .max_sectors = 0xFFFF,
7175 .shost_attrs = qla2x00_host_attrs,
7176
7177 .supported_mode = MODE_INITIATOR,
7178 .track_queue_depth = 1,
7179};
7180
a55b2d21 7181static const struct pci_error_handlers qla2xxx_err_handler = {
14e660e6
SJ		 7182 .error_detected = qla2xxx_pci_error_detected,
7183 .mmio_enabled = qla2xxx_pci_mmio_enabled,
7184 .slot_reset = qla2xxx_pci_slot_reset,
7185 .resume = qla2xxx_pci_resume,
590f806d
QT		 7186 .reset_prepare = qla_pci_reset_prepare,
7187 .reset_done = qla_pci_reset_done,
14e660e6
SJ		 7188};
7189
5433383e 7190static struct pci_device_id qla2xxx_pci_tbl[] = {
47f5e069
AV		 7191 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) },
7192 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) },
7193 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) },
7194 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) },
7195 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) },
7196 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) },
7197 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) },
7198 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) },
7199 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) },
4d4df193 7200 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) },
47f5e069
AV		 7201 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) },
7202 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) },
c3a2f0df 7203 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) },
6246b8a1 7204 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2031) },
3a03eb79 7205 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) },
a9083016 7206 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) },
650f528f 7207 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8031) },
8ae6d9c7 7208 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISPF001) },
7ec0effd 7209 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8044) },
f73cb695 7210 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2071) },
2c5bbbb2 7211 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2271) },
2b48992f 7212 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2261) },
ecc89f25
JC		 7213 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2061) },
7214 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2081) },
7215 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2281) },
7216 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2089) },
7217 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2289) },
5433383e
AV		 7218 { 0 },
7219};
7220MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl);
7221
fca29703 7222static struct pci_driver qla2xxx_pci_driver = {
cb63067a 7223 .name = QLA2XXX_DRIVER_NAME,
0a21ef1e
JB		 7224 .driver = {
7225 .owner = THIS_MODULE,
7226 },
fca29703 7227 .id_table = qla2xxx_pci_tbl,
7ee61397 7228 .probe = qla2x00_probe_one,
4c993f76 7229 .remove = qla2x00_remove_one,
e30d1756 7230 .shutdown = qla2x00_shutdown,
14e660e6 7231 .err_handler = &qla2xxx_err_handler,
fca29703
AV		 7232};
7233
75ef9de1 7234static const struct file_operations apidev_fops = {
6a03b4cd 7235 .owner = THIS_MODULE,
6038f373 7236 .llseek = noop_llseek,
6a03b4cd
HZ		 7237};
7238
1da177e4
LT		 7239/**
7240 * qla2x00_module_init - Module initialization.
7241 **/
7242static int __init
7243qla2x00_module_init(void)
7244{
fca29703
AV		 7245 int ret = 0;
7246
bc04459c
BVA		 7247 BUILD_BUG_ON(sizeof(cmd_entry_t) != 64);
7248 BUILD_BUG_ON(sizeof(cont_a64_entry_t) != 64);
7249 BUILD_BUG_ON(sizeof(cont_entry_t) != 64);
7250 BUILD_BUG_ON(sizeof(init_cb_t) != 96);
7251 BUILD_BUG_ON(sizeof(ms_iocb_entry_t) != 64);
7252 BUILD_BUG_ON(sizeof(request_t) != 64);
7253 BUILD_BUG_ON(sizeof(struct access_chip_84xx) != 64);
7254 BUILD_BUG_ON(sizeof(struct cmd_bidir) != 64);
7255 BUILD_BUG_ON(sizeof(struct cmd_nvme) != 64);
7256 BUILD_BUG_ON(sizeof(struct cmd_type_6) != 64);
7257 BUILD_BUG_ON(sizeof(struct cmd_type_7) != 64);
7258 BUILD_BUG_ON(sizeof(struct cmd_type_7_fx00) != 64);
7259 BUILD_BUG_ON(sizeof(struct cmd_type_crc_2) != 64);
7260 BUILD_BUG_ON(sizeof(struct ct_entry_24xx) != 64);
7261 BUILD_BUG_ON(sizeof(struct ctio_crc2_to_fw) != 64);
7262 BUILD_BUG_ON(sizeof(struct els_entry_24xx) != 64);
7263 BUILD_BUG_ON(sizeof(struct fxdisc_entry_fx00) != 64);
7264 BUILD_BUG_ON(sizeof(struct init_cb_24xx) != 128);
7265 BUILD_BUG_ON(sizeof(struct init_cb_81xx) != 128);
7266 BUILD_BUG_ON(sizeof(struct pt_ls4_request) != 64);
7267 BUILD_BUG_ON(sizeof(struct sns_cmd_pkt) != 2064);
7268 BUILD_BUG_ON(sizeof(struct verify_chip_entry_84xx) != 64);
7269 BUILD_BUG_ON(sizeof(struct vf_evfp_entry_24xx) != 56);
7270
1da177e4 7271 /* Allocate cache for SRBs. */
354d6b21 7272 srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0,
20c2df83 7273 SLAB_HWCACHE_ALIGN, NULL);
1da177e4 7274 if (srb_cachep == NULL) {
7c3df132
SK		 7275 ql_log(ql_log_fatal, NULL, 0x0001,
7276 "Unable to allocate SRB cache...Failing load!.\n");
1da177e4
LT		 7277 return -ENOMEM;
7278 }
7279
2d70c103
NB		 7280 /* Initialize target kmem_cache and mem_pools */
7281 ret = qlt_init();
7282 if (ret < 0) {
c794d24e 7283 goto destroy_cache;
2d70c103
NB		 7284 } else if (ret > 0) {
7285 /*
7286 * If initiator mode is explictly disabled by qlt_init(),
7287 * prevent scsi_transport_fc.c:fc_scsi_scan_rport() from
7288 * performing scsi_scan_target() during LOOP UP event.
7289 */
7290 qla2xxx_transport_functions.disable_target_scan = 1;
7291 qla2xxx_transport_vport_functions.disable_target_scan = 1;
7292 }
7293
1da177e4
LT		 7294 /* Derive version string. */
7295 strcpy(qla2x00_version_str, QLA2XXX_VERSION);
11010fec 7296 if (ql2xextended_error_logging)
0181944f 7297 strcat(qla2x00_version_str, "-debug");
fed0f68a
JC		 7298 if (ql2xextended_error_logging == 1)
7299 ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK;
0181944f 7300
0645cb83
QT		 7301 if (ql2x_ini_mode == QLA2XXX_INI_MODE_DUAL)
7302 qla_insert_tgt_attrs();
7303
1c97a12a
AV		 7304 qla2xxx_transport_template =
7305 fc_attach_transport(&qla2xxx_transport_functions);
2c3dfe3f 7306 if (!qla2xxx_transport_template) {
7c3df132
SK		 7307 ql_log(ql_log_fatal, NULL, 0x0002,
7308 "fc_attach_transport failed...Failing load!.\n");
c794d24e
BVA		 7309 ret = -ENODEV;
7310 goto qlt_exit;
2c3dfe3f 7311 }
6a03b4cd
HZ		 7312
7313 apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops);
7314 if (apidev_major < 0) {
7c3df132
SK		 7315 ql_log(ql_log_fatal, NULL, 0x0003,
7316 "Unable to register char device %s.\n", QLA2XXX_APIDEV);
6a03b4cd
HZ		 7317 }
7318
2c3dfe3f
SJ		 7319 qla2xxx_transport_vport_template =
7320 fc_attach_transport(&qla2xxx_transport_vport_functions);
7321 if (!qla2xxx_transport_vport_template) {
7c3df132
SK		 7322 ql_log(ql_log_fatal, NULL, 0x0004,
7323 "fc_attach_transport vport failed...Failing load!.\n");
c794d24e
BVA		 7324 ret = -ENODEV;
7325 goto unreg_chrdev;
2c3dfe3f 7326 }
7c3df132
SK		 7327 ql_log(ql_log_info, NULL, 0x0005,
7328 "QLogic Fibre Channel HBA Driver: %s.\n",
fd9a29f0 7329 qla2x00_version_str);
7ee61397 7330 ret = pci_register_driver(&qla2xxx_pci_driver);
fca29703 7331 if (ret) {
7c3df132
SK		 7332 ql_log(ql_log_fatal, NULL, 0x0006,
7333 "pci_register_driver failed...ret=%d Failing load!.\n",
7334 ret);
c794d24e 7335 goto release_vport_transport;
fca29703
AV		 7336 }
7337 return ret;
c794d24e
BVA		 7338
7339release_vport_transport:
7340 fc_release_transport(qla2xxx_transport_vport_template);
7341
7342unreg_chrdev:
7343 if (apidev_major >= 0)
7344 unregister_chrdev(apidev_major, QLA2XXX_APIDEV);
7345 fc_release_transport(qla2xxx_transport_template);
7346
7347qlt_exit:
7348 qlt_exit();
7349
7350destroy_cache:
7351 kmem_cache_destroy(srb_cachep);
7352 return ret;
1da177e4
LT		 7353}
7354
7355/**
7356 * qla2x00_module_exit - Module cleanup.
7357 **/
7358static void __exit
7359qla2x00_module_exit(void)
7360{
7ee61397 7361 pci_unregister_driver(&qla2xxx_pci_driver);
5433383e 7362 qla2x00_release_firmware();
75c1d48a 7363 kmem_cache_destroy(ctx_cachep);
2c3dfe3f 7364 fc_release_transport(qla2xxx_transport_vport_template);
59c209a6
BVA		 7365 if (apidev_major >= 0)
7366 unregister_chrdev(apidev_major, QLA2XXX_APIDEV);
7367 fc_release_transport(qla2xxx_transport_template);
7368 qlt_exit();
7369 kmem_cache_destroy(srb_cachep);
1da177e4
LT		 7370}
7371
7372module_init(qla2x00_module_init);
7373module_exit(qla2x00_module_exit);
7374
7375MODULE_AUTHOR("QLogic Corporation");
7376MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver");
7377MODULE_LICENSE("GPL");
7378MODULE_VERSION(QLA2XXX_VERSION);
bb8ee499
AV		 7379MODULE_FIRMWARE(FW_FILE_ISP21XX);
7380MODULE_FIRMWARE(FW_FILE_ISP22XX);
7381MODULE_FIRMWARE(FW_FILE_ISP2300);
7382MODULE_FIRMWARE(FW_FILE_ISP2322);
7383MODULE_FIRMWARE(FW_FILE_ISP24XX);
61623fc3 7384MODULE_FIRMWARE(FW_FILE_ISP25XX);
Linux 6.x block layer and io_uring tree(s)