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qla2xxx: Add selective command queuing
[linux-2.6-block.git] / drivers / scsi / qla2xxx / qla_os.c
CommitLineData
1da177e4 1/*
fa90c54f 2 * QLogic Fibre Channel HBA Driver
bd21eaf9 3 * Copyright (c) 2003-2014 QLogic Corporation
1da177e4 4 *
fa90c54f 5 * See LICENSE.qla2xxx for copyright and licensing details.
1da177e4
LT		 6 */
7#include "qla_def.h"
8
9#include <linux/moduleparam.h>
10#include <linux/vmalloc.h>
1da177e4 11#include <linux/delay.h>
39a11240 12#include <linux/kthread.h>
e1e82b6f 13#include <linux/mutex.h>
3420d36c 14#include <linux/kobject.h>
5a0e3ad6 15#include <linux/slab.h>
1da177e4
LT		 16#include <scsi/scsi_tcq.h>
17#include <scsi/scsicam.h>
18#include <scsi/scsi_transport.h>
19#include <scsi/scsi_transport_fc.h>
20
2d70c103
NB		 21#include "qla_target.h"
22
1da177e4
LT		 23/*
24 * Driver version
25 */
26char qla2x00_version_str[40];
27
6a03b4cd
HZ		 28static int apidev_major;
29
1da177e4
LT		 30/*
31 * SRB allocation cache
32 */
e18b890b 33static struct kmem_cache *srb_cachep;
1da177e4 34
a9083016
GM		 35/*
36 * CT6 CTX allocation cache
37 */
38static struct kmem_cache *ctx_cachep;
3ce8866c
SK		 39/*
40 * error level for logging
41 */
42int ql_errlev = ql_log_all;
a9083016 43
fa492630 44static int ql2xenableclass2;
2d70c103
NB		 45module_param(ql2xenableclass2, int, S_IRUGO|S_IRUSR);
46MODULE_PARM_DESC(ql2xenableclass2,
47 "Specify if Class 2 operations are supported from the very "
48 "beginning. Default is 0 - class 2 not supported.");
49
8ae6d9c7 50
1da177e4 51int ql2xlogintimeout = 20;
f2019cb1 52module_param(ql2xlogintimeout, int, S_IRUGO);
1da177e4
LT		 53MODULE_PARM_DESC(ql2xlogintimeout,
54 "Login timeout value in seconds.");
55
a7b61842 56int qlport_down_retry;
f2019cb1 57module_param(qlport_down_retry, int, S_IRUGO);
1da177e4 58MODULE_PARM_DESC(qlport_down_retry,
900d9f98 59 "Maximum number of command retries to a port that returns "
1da177e4
LT		 60 "a PORT-DOWN status.");
61
1da177e4
LT		 62int ql2xplogiabsentdevice;
63module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR);
64MODULE_PARM_DESC(ql2xplogiabsentdevice,
65 "Option to enable PLOGI to devices that are not present after "
900d9f98 66 "a Fabric scan. This is needed for several broken switches. "
1da177e4
LT		 67 "Default is 0 - no PLOGI. 1 - perfom PLOGI.");
68
1da177e4 69int ql2xloginretrycount = 0;
f2019cb1 70module_param(ql2xloginretrycount, int, S_IRUGO);
1da177e4
LT		 71MODULE_PARM_DESC(ql2xloginretrycount,
72 "Specify an alternate value for the NVRAM login retry count.");
73
a7a167bf 74int ql2xallocfwdump = 1;
f2019cb1 75module_param(ql2xallocfwdump, int, S_IRUGO);
a7a167bf
AV		 76MODULE_PARM_DESC(ql2xallocfwdump,
77 "Option to enable allocation of memory for a firmware dump "
78 "during HBA initialization. Memory allocation requirements "
79 "vary by ISP type. Default is 1 - allocate memory.");
80
11010fec 81int ql2xextended_error_logging;
27d94035 82module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
11010fec 83MODULE_PARM_DESC(ql2xextended_error_logging,
3ce8866c
SK		 84 "Option to enable extended error logging,\n"
85 "\t\tDefault is 0 - no logging. 0x40000000 - Module Init & Probe.\n"
86 "\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n"
87 "\t\t0x08000000 - IO tracing. 0x04000000 - DPC Thread.\n"
88 "\t\t0x02000000 - Async events. 0x01000000 - Timer routines.\n"
89 "\t\t0x00800000 - User space. 0x00400000 - Task Management.\n"
90 "\t\t0x00200000 - AER/EEH. 0x00100000 - Multi Q.\n"
91 "\t\t0x00080000 - P3P Specific. 0x00040000 - Virtual Port.\n"
92 "\t\t0x00020000 - Buffer Dump. 0x00010000 - Misc.\n"
29f9f90c
CD		 93 "\t\t0x00008000 - Verbose. 0x00004000 - Target.\n"
94 "\t\t0x00002000 - Target Mgmt. 0x00001000 - Target TMF.\n"
3ce8866c 95 "\t\t0x7fffffff - For enabling all logs, can be too many logs.\n"
cfb0919c
CD		 96 "\t\t0x1e400000 - Preferred value for capturing essential "
97 "debug information (equivalent to old "
98 "ql2xextended_error_logging=1).\n"
3ce8866c 99 "\t\tDo LOGICAL OR of the value to enable more than one level");
0181944f 100
a9083016 101int ql2xshiftctondsd = 6;
f2019cb1 102module_param(ql2xshiftctondsd, int, S_IRUGO);
a9083016
GM		 103MODULE_PARM_DESC(ql2xshiftctondsd,
104 "Set to control shifting of command type processing "
105 "based on total number of SG elements.");
106
7e47e5ca 107int ql2xfdmienable=1;
de187df8 108module_param(ql2xfdmienable, int, S_IRUGO|S_IWUSR);
cca5335c 109MODULE_PARM_DESC(ql2xfdmienable,
7794a5af
FW		 110 "Enables FDMI registrations. "
111 "0 - no FDMI. Default is 1 - perform FDMI.");
cca5335c 112
50280c01
CD		 113#define MAX_Q_DEPTH 32
114static int ql2xmaxqdepth = MAX_Q_DEPTH;
df7baa50
AV		 115module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR);
116MODULE_PARM_DESC(ql2xmaxqdepth,
e92e4a8f
CD		 117 "Maximum queue depth to set for each LUN. "
118 "Default is 32.");
df7baa50 119
9e522cd8
AE		 120int ql2xenabledif = 2;
121module_param(ql2xenabledif, int, S_IRUGO);
bad75002 122MODULE_PARM_DESC(ql2xenabledif,
b97f5d0b
SM		 123 " Enable T10-CRC-DIF:\n"
124 " Default is 2.\n"
125 " 0 -- No DIF Support\n"
126 " 1 -- Enable DIF for all types\n"
127 " 2 -- Enable DIF for all types, except Type 0.\n");
bad75002 128
8cb2049c 129int ql2xenablehba_err_chk = 2;
bad75002
AE		 130module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR);
131MODULE_PARM_DESC(ql2xenablehba_err_chk,
8cb2049c 132 " Enable T10-CRC-DIF Error isolation by HBA:\n"
b97f5d0b 133 " Default is 2.\n"
8cb2049c
AE		 134 " 0 -- Error isolation disabled\n"
135 " 1 -- Error isolation enabled only for DIX Type 0\n"
136 " 2 -- Error isolation enabled for all Types\n");
bad75002 137
e5896bd5 138int ql2xiidmaenable=1;
f2019cb1 139module_param(ql2xiidmaenable, int, S_IRUGO);
e5896bd5
AV		 140MODULE_PARM_DESC(ql2xiidmaenable,
141 "Enables iIDMA settings "
142 "Default is 1 - perform iIDMA. 0 - no iIDMA.");
143
73208dfd 144int ql2xmaxqueues = 1;
f2019cb1 145module_param(ql2xmaxqueues, int, S_IRUGO);
73208dfd
AC		 146MODULE_PARM_DESC(ql2xmaxqueues,
147 "Enables MQ settings "
ae68230c
JP		 148 "Default is 1 for single queue. Set it to number "
149 "of queues in MQ mode.");
68ca949c
AC		 150
151int ql2xmultique_tag;
f2019cb1 152module_param(ql2xmultique_tag, int, S_IRUGO);
68ca949c
AC		 153MODULE_PARM_DESC(ql2xmultique_tag,
154 "Enables CPU affinity settings for the driver "
155 "Default is 0 for no affinity of request and response IO. "
156 "Set it to 1 to turn on the cpu affinity.");
e337d907
AV		 157
158int ql2xfwloadbin;
86e45bf6 159module_param(ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
e337d907 160MODULE_PARM_DESC(ql2xfwloadbin,
7c3df132
SK		 161 "Option to specify location from which to load ISP firmware:.\n"
162 " 2 -- load firmware via the request_firmware() (hotplug).\n"
e337d907
AV		 163 " interface.\n"
164 " 1 -- load firmware from flash.\n"
165 " 0 -- use default semantics.\n");
166
ae97c91e 167int ql2xetsenable;
f2019cb1 168module_param(ql2xetsenable, int, S_IRUGO);
ae97c91e
AV		 169MODULE_PARM_DESC(ql2xetsenable,
170 "Enables firmware ETS burst."
171 "Default is 0 - skip ETS enablement.");
172
6907869d 173int ql2xdbwr = 1;
86e45bf6 174module_param(ql2xdbwr, int, S_IRUGO|S_IWUSR);
a9083016 175MODULE_PARM_DESC(ql2xdbwr,
08de2844
GM		 176 "Option to specify scheme for request queue posting.\n"
177 " 0 -- Regular doorbell.\n"
178 " 1 -- CAMRAM doorbell (faster).\n");
a9083016 179
f4c496c1 180int ql2xtargetreset = 1;
f2019cb1 181module_param(ql2xtargetreset, int, S_IRUGO);
f4c496c1
GM		 182MODULE_PARM_DESC(ql2xtargetreset,
183 "Enable target reset."
184 "Default is 1 - use hw defaults.");
185
4da26e16 186int ql2xgffidenable;
f2019cb1 187module_param(ql2xgffidenable, int, S_IRUGO);
4da26e16
CD		 188MODULE_PARM_DESC(ql2xgffidenable,
189 "Enables GFF_ID checks of port type. "
190 "Default is 0 - Do not use GFF_ID information.");
a9083016 191
3822263e 192int ql2xasynctmfenable;
f2019cb1 193module_param(ql2xasynctmfenable, int, S_IRUGO);
3822263e
MI		 194MODULE_PARM_DESC(ql2xasynctmfenable,
195 "Enables issue of TM IOCBs asynchronously via IOCB mechanism"
196 "Default is 0 - Issue TM IOCBs via mailbox mechanism.");
ed0de87c
GM		 197
198int ql2xdontresethba;
86e45bf6 199module_param(ql2xdontresethba, int, S_IRUGO|S_IWUSR);
ed0de87c 200MODULE_PARM_DESC(ql2xdontresethba,
08de2844
GM		 201 "Option to specify reset behaviour.\n"
202 " 0 (Default) -- Reset on failure.\n"
203 " 1 -- Do not reset on failure.\n");
ed0de87c 204
1abf635d
HR		 205uint64_t ql2xmaxlun = MAX_LUNS;
206module_param(ql2xmaxlun, ullong, S_IRUGO);
82515920
AV		 207MODULE_PARM_DESC(ql2xmaxlun,
208 "Defines the maximum LU number to register with the SCSI "
209 "midlayer. Default is 65535.");
210
08de2844
GM		 211int ql2xmdcapmask = 0x1F;
212module_param(ql2xmdcapmask, int, S_IRUGO);
213MODULE_PARM_DESC(ql2xmdcapmask,
214 "Set the Minidump driver capture mask level. "
6e96fa7b 215 "Default is 0x1F - Can be set to 0x3, 0x7, 0xF, 0x1F, 0x7F.");
08de2844 216
3aadff35 217int ql2xmdenable = 1;
08de2844
GM		 218module_param(ql2xmdenable, int, S_IRUGO);
219MODULE_PARM_DESC(ql2xmdenable,
220 "Enable/disable MiniDump. "
3aadff35
GM		 221 "0 - MiniDump disabled. "
222 "1 (Default) - MiniDump enabled.");
08de2844 223
b0d6cabd
HM		 224int ql2xexlogins = 0;
225module_param(ql2xexlogins, uint, S_IRUGO|S_IWUSR);
226MODULE_PARM_DESC(ql2xexlogins,
227 "Number of extended Logins. "
228 "0 (Default)- Disabled.");
229
2f56a7f1
HM		 230int ql2xexchoffld = 0;
231module_param(ql2xexchoffld, uint, S_IRUGO|S_IWUSR);
232MODULE_PARM_DESC(ql2xexchoffld,
233 "Number of exchanges to offload. "
234 "0 (Default)- Disabled.");
235
1da177e4 236/*
fa2a1ce5 237 * SCSI host template entry points
1da177e4
LT		 238 */
239static int qla2xxx_slave_configure(struct scsi_device * device);
f4f051eb 240static int qla2xxx_slave_alloc(struct scsi_device *);
1e99e33a
AV		 241static int qla2xxx_scan_finished(struct Scsi_Host *, unsigned long time);
242static void qla2xxx_scan_start(struct Scsi_Host *);
f4f051eb 243static void qla2xxx_slave_destroy(struct scsi_device *);
f281233d 244static int qla2xxx_queuecommand(struct Scsi_Host *h, struct scsi_cmnd *cmd);
1da177e4
LT		 245static int qla2xxx_eh_abort(struct scsi_cmnd *);
246static int qla2xxx_eh_device_reset(struct scsi_cmnd *);
523ec773 247static int qla2xxx_eh_target_reset(struct scsi_cmnd *);
1da177e4
LT		 248static int qla2xxx_eh_bus_reset(struct scsi_cmnd *);
249static int qla2xxx_eh_host_reset(struct scsi_cmnd *);
1da177e4 250
1a2fbf18 251static void qla2x00_clear_drv_active(struct qla_hw_data *);
3491255e 252static void qla2x00_free_device(scsi_qla_host_t *);
2d5a4c34 253static void qla83xx_disable_laser(scsi_qla_host_t *vha);
ce7e4af7 254
a5326f86 255struct scsi_host_template qla2xxx_driver_template = {
1da177e4 256 .module = THIS_MODULE,
cb63067a 257 .name = QLA2XXX_DRIVER_NAME,
a5326f86 258 .queuecommand = qla2xxx_queuecommand,
fca29703
AV		 259
260 .eh_abort_handler = qla2xxx_eh_abort,
261 .eh_device_reset_handler = qla2xxx_eh_device_reset,
523ec773 262 .eh_target_reset_handler = qla2xxx_eh_target_reset,
fca29703
AV		 263 .eh_bus_reset_handler = qla2xxx_eh_bus_reset,
264 .eh_host_reset_handler = qla2xxx_eh_host_reset,
265
266 .slave_configure = qla2xxx_slave_configure,
267
268 .slave_alloc = qla2xxx_slave_alloc,
269 .slave_destroy = qla2xxx_slave_destroy,
ed677086
AV		 270 .scan_finished = qla2xxx_scan_finished,
271 .scan_start = qla2xxx_scan_start,
db5ed4df 272 .change_queue_depth = scsi_change_queue_depth,
fca29703
AV		 273 .this_id = -1,
274 .cmd_per_lun = 3,
275 .use_clustering = ENABLE_CLUSTERING,
276 .sg_tablesize = SG_ALL,
277
278 .max_sectors = 0xFFFF,
afb046e2 279 .shost_attrs = qla2x00_host_attrs,
2d70c103
NB		 280
281 .supported_mode = MODE_INITIATOR,
c40ecc12 282 .track_queue_depth = 1,
fca29703
AV		 283};
284
1da177e4 285static struct scsi_transport_template *qla2xxx_transport_template = NULL;
2c3dfe3f 286struct scsi_transport_template *qla2xxx_transport_vport_template = NULL;
1da177e4 287
1da177e4
LT		 288/* TODO Convert to inlines
289 *
290 * Timer routines
291 */
1da177e4 292
2c3dfe3f 293__inline__ void
e315cd28 294qla2x00_start_timer(scsi_qla_host_t *vha, void *func, unsigned long interval)
1da177e4 295{
e315cd28
AC		 296 init_timer(&vha->timer);
297 vha->timer.expires = jiffies + interval * HZ;
298 vha->timer.data = (unsigned long)vha;
299 vha->timer.function = (void (*)(unsigned long))func;
300 add_timer(&vha->timer);
301 vha->timer_active = 1;
1da177e4
LT		 302}
303
304static inline void
e315cd28 305qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval)
1da177e4 306{
a9083016 307 /* Currently used for 82XX only. */
7c3df132
SK		 308 if (vha->device_flags & DFLG_DEV_FAILED) {
309 ql_dbg(ql_dbg_timer, vha, 0x600d,
310 "Device in a failed state, returning.\n");
a9083016 311 return;
7c3df132 312 }
a9083016 313
e315cd28 314 mod_timer(&vha->timer, jiffies + interval * HZ);
1da177e4
LT		 315}
316
a824ebb3 317static __inline__ void
e315cd28 318qla2x00_stop_timer(scsi_qla_host_t *vha)
1da177e4 319{
e315cd28
AC		 320 del_timer_sync(&vha->timer);
321 vha->timer_active = 0;
1da177e4
LT		 322}
323
1da177e4
LT		 324static int qla2x00_do_dpc(void *data);
325
326static void qla2x00_rst_aen(scsi_qla_host_t *);
327
73208dfd
AC		 328static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t,
329 struct req_que **, struct rsp_que **);
e30d1756 330static void qla2x00_free_fw_dump(struct qla_hw_data *);
e315cd28 331static void qla2x00_mem_free(struct qla_hw_data *);
1da177e4 332
1da177e4 333/* -------------------------------------------------------------------------- */
9a347ff4
CD		 334static int qla2x00_alloc_queues(struct qla_hw_data *ha, struct req_que *req,
335 struct rsp_que *rsp)
73208dfd 336{
7c3df132 337 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2afa19a9 338 ha->req_q_map = kzalloc(sizeof(struct req_que *) * ha->max_req_queues,
73208dfd
AC		 339 GFP_KERNEL);
340 if (!ha->req_q_map) {
7c3df132
SK		 341 ql_log(ql_log_fatal, vha, 0x003b,
342 "Unable to allocate memory for request queue ptrs.\n");
73208dfd
AC		 343 goto fail_req_map;
344 }
345
2afa19a9 346 ha->rsp_q_map = kzalloc(sizeof(struct rsp_que *) * ha->max_rsp_queues,
73208dfd
AC		 347 GFP_KERNEL);
348 if (!ha->rsp_q_map) {
7c3df132
SK		 349 ql_log(ql_log_fatal, vha, 0x003c,
350 "Unable to allocate memory for response queue ptrs.\n");
73208dfd
AC		 351 goto fail_rsp_map;
352 }
9a347ff4
CD		 353 /*
354 * Make sure we record at least the request and response queue zero in
355 * case we need to free them if part of the probe fails.
356 */
357 ha->rsp_q_map[0] = rsp;
358 ha->req_q_map[0] = req;
73208dfd
AC		 359 set_bit(0, ha->rsp_qid_map);
360 set_bit(0, ha->req_qid_map);
361 return 1;
362
363fail_rsp_map:
364 kfree(ha->req_q_map);
365 ha->req_q_map = NULL;
366fail_req_map:
367 return -ENOMEM;
368}
369
2afa19a9 370static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req)
73208dfd 371{
8ae6d9c7
GM		 372 if (IS_QLAFX00(ha)) {
373 if (req && req->ring_fx00)
374 dma_free_coherent(&ha->pdev->dev,
375 (req->length_fx00 + 1) * sizeof(request_t),
376 req->ring_fx00, req->dma_fx00);
377 } else if (req && req->ring)
73208dfd
AC		 378 dma_free_coherent(&ha->pdev->dev,
379 (req->length + 1) * sizeof(request_t),
380 req->ring, req->dma);
381
8d93f550
CD		 382 if (req)
383 kfree(req->outstanding_cmds);
384
73208dfd
AC		 385 kfree(req);
386 req = NULL;
387}
388
2afa19a9
AC		 389static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp)
390{
8ae6d9c7
GM		 391 if (IS_QLAFX00(ha)) {
392 if (rsp && rsp->ring)
393 dma_free_coherent(&ha->pdev->dev,
394 (rsp->length_fx00 + 1) * sizeof(request_t),
395 rsp->ring_fx00, rsp->dma_fx00);
396 } else if (rsp && rsp->ring) {
2afa19a9
AC		 397 dma_free_coherent(&ha->pdev->dev,
398 (rsp->length + 1) * sizeof(response_t),
399 rsp->ring, rsp->dma);
8ae6d9c7 400 }
2afa19a9
AC		 401 kfree(rsp);
402 rsp = NULL;
403}
404
73208dfd
AC		 405static void qla2x00_free_queues(struct qla_hw_data *ha)
406{
407 struct req_que *req;
408 struct rsp_que *rsp;
409 int cnt;
410
2afa19a9 411 for (cnt = 0; cnt < ha->max_req_queues; cnt++) {
73208dfd 412 req = ha->req_q_map[cnt];
2afa19a9 413 qla2x00_free_req_que(ha, req);
73208dfd 414 }
73208dfd
AC		 415 kfree(ha->req_q_map);
416 ha->req_q_map = NULL;
2afa19a9
AC		 417
418 for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) {
419 rsp = ha->rsp_q_map[cnt];
420 qla2x00_free_rsp_que(ha, rsp);
421 }
422 kfree(ha->rsp_q_map);
423 ha->rsp_q_map = NULL;
73208dfd
AC		 424}
425
68ca949c
AC		 426static int qla25xx_setup_mode(struct scsi_qla_host *vha)
427{
428 uint16_t options = 0;
429 int ques, req, ret;
430 struct qla_hw_data *ha = vha->hw;
431
7163ea81 432 if (!(ha->fw_attributes & BIT_6)) {
7c3df132
SK		 433 ql_log(ql_log_warn, vha, 0x00d8,
434 "Firmware is not multi-queue capable.\n");
7163ea81
AC		 435 goto fail;
436 }
68ca949c 437 if (ql2xmultique_tag) {
68ca949c
AC		 438 /* create a request queue for IO */
439 options |= BIT_7;
440 req = qla25xx_create_req_que(ha, options, 0, 0, -1,
441 QLA_DEFAULT_QUE_QOS);
442 if (!req) {
7c3df132
SK		 443 ql_log(ql_log_warn, vha, 0x00e0,
444 "Failed to create request queue.\n");
68ca949c
AC		 445 goto fail;
446 }
278274d5 447 ha->wq = alloc_workqueue("qla2xxx_wq", WQ_MEM_RECLAIM, 1);
68ca949c
AC		 448 vha->req = ha->req_q_map[req];
449 options |= BIT_1;
450 for (ques = 1; ques < ha->max_rsp_queues; ques++) {
451 ret = qla25xx_create_rsp_que(ha, options, 0, 0, req);
452 if (!ret) {
7c3df132
SK		 453 ql_log(ql_log_warn, vha, 0x00e8,
454 "Failed to create response queue.\n");
68ca949c
AC		 455 goto fail2;
456 }
457 }
7163ea81 458 ha->flags.cpu_affinity_enabled = 1;
7c3df132 459 ql_dbg(ql_dbg_multiq, vha, 0xc007,
6ef68da7 460 "CPU affinity mode enabled, "
7c3df132
SK		 461 "no. of response queues:%d no. of request queues:%d.\n",
462 ha->max_rsp_queues, ha->max_req_queues);
463 ql_dbg(ql_dbg_init, vha, 0x00e9,
6ef68da7 464 "CPU affinity mode enabled, "
7c3df132
SK		 465 "no. of response queues:%d no. of request queues:%d.\n",
466 ha->max_rsp_queues, ha->max_req_queues);
68ca949c
AC		 467 }
468 return 0;
469fail2:
470 qla25xx_delete_queues(vha);
7163ea81
AC		 471 destroy_workqueue(ha->wq);
472 ha->wq = NULL;
0cd33fcf 473 vha->req = ha->req_q_map[0];
68ca949c
AC		 474fail:
475 ha->mqenable = 0;
7163ea81
AC		 476 kfree(ha->req_q_map);
477 kfree(ha->rsp_q_map);
478 ha->max_req_queues = ha->max_rsp_queues = 1;
68ca949c
AC		 479 return 1;
480}
481
1da177e4 482static char *
e315cd28 483qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str)
1da177e4 484{
e315cd28 485 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 486 static char *pci_bus_modes[] = {
487 "33", "66", "100", "133",
488 };
489 uint16_t pci_bus;
490
491 strcpy(str, "PCI");
492 pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9;
493 if (pci_bus) {
494 strcat(str, "-X (");
495 strcat(str, pci_bus_modes[pci_bus]);
496 } else {
497 pci_bus = (ha->pci_attr & BIT_8) >> 8;
498 strcat(str, " (");
499 strcat(str, pci_bus_modes[pci_bus]);
500 }
501 strcat(str, " MHz)");
502
503 return (str);
504}
505
fca29703 506static char *
e315cd28 507qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str)
fca29703
AV		 508{
509 static char *pci_bus_modes[] = { "33", "66", "100", "133", };
e315cd28 510 struct qla_hw_data *ha = vha->hw;
fca29703 511 uint32_t pci_bus;
fca29703 512
62a276f8 513 if (pci_is_pcie(ha->pdev)) {
fca29703 514 char lwstr[6];
62a276f8 515 uint32_t lstat, lspeed, lwidth;
fca29703 516
62a276f8
BH		 517 pcie_capability_read_dword(ha->pdev, PCI_EXP_LNKCAP, &lstat);
518 lspeed = lstat & PCI_EXP_LNKCAP_SLS;
519 lwidth = (lstat & PCI_EXP_LNKCAP_MLW) >> 4;
fca29703
AV		 520
521 strcpy(str, "PCIe (");
49300af7
SK		 522 switch (lspeed) {
523 case 1:
c87a0d8c 524 strcat(str, "2.5GT/s ");
49300af7
SK		 525 break;
526 case 2:
c87a0d8c 527 strcat(str, "5.0GT/s ");
49300af7
SK		 528 break;
529 case 3:
530 strcat(str, "8.0GT/s ");
531 break;
532 default:
fca29703 533 strcat(str, "<unknown> ");
49300af7
SK		 534 break;
535 }
fca29703
AV		 536 snprintf(lwstr, sizeof(lwstr), "x%d)", lwidth);
537 strcat(str, lwstr);
538
539 return str;
540 }
541
542 strcpy(str, "PCI");
543 pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8;
544 if (pci_bus == 0 || pci_bus == 8) {
545 strcat(str, " (");
546 strcat(str, pci_bus_modes[pci_bus >> 3]);
547 } else {
548 strcat(str, "-X ");
549 if (pci_bus & BIT_2)
550 strcat(str, "Mode 2");
551 else
552 strcat(str, "Mode 1");
553 strcat(str, " (");
554 strcat(str, pci_bus_modes[pci_bus & ~BIT_2]);
555 }
556 strcat(str, " MHz)");
557
558 return str;
559}
560
e5f82ab8 561static char *
df57caba 562qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
1da177e4
LT		 563{
564 char un_str[10];
e315cd28 565 struct qla_hw_data *ha = vha->hw;
fa2a1ce5 566
df57caba
HM		 567 snprintf(str, size, "%d.%02d.%02d ", ha->fw_major_version,
568 ha->fw_minor_version, ha->fw_subminor_version);
1da177e4
LT		 569
570 if (ha->fw_attributes & BIT_9) {
571 strcat(str, "FLX");
572 return (str);
573 }
574
575 switch (ha->fw_attributes & 0xFF) {
576 case 0x7:
577 strcat(str, "EF");
578 break;
579 case 0x17:
580 strcat(str, "TP");
581 break;
582 case 0x37:
583 strcat(str, "IP");
584 break;
585 case 0x77:
586 strcat(str, "VI");
587 break;
588 default:
589 sprintf(un_str, "(%x)", ha->fw_attributes);
590 strcat(str, un_str);
591 break;
592 }
593 if (ha->fw_attributes & 0x100)
594 strcat(str, "X");
595
596 return (str);
597}
598
e5f82ab8 599static char *
df57caba 600qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
fca29703 601{
e315cd28 602 struct qla_hw_data *ha = vha->hw;
f0883ac6 603
df57caba 604 snprintf(str, size, "%d.%02d.%02d (%x)", ha->fw_major_version,
3a03eb79 605 ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes);
fca29703 606 return str;
fca29703
AV		 607}
608
9ba56b95
GM		 609void
610qla2x00_sp_free_dma(void *vha, void *ptr)
fca29703 611{
9ba56b95
GM		 612 srb_t *sp = (srb_t *)ptr;
613 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
614 struct qla_hw_data *ha = sp->fcport->vha->hw;
615 void *ctx = GET_CMD_CTX_SP(sp);
fca29703 616
9ba56b95
GM		 617 if (sp->flags & SRB_DMA_VALID) {
618 scsi_dma_unmap(cmd);
619 sp->flags &= ~SRB_DMA_VALID;
7c3df132 620 }
fca29703 621
9ba56b95
GM		 622 if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
623 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
624 scsi_prot_sg_count(cmd), cmd->sc_data_direction);
625 sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
626 }
627
628 if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
629 /* List assured to be having elements */
f83adb61 630 qla2x00_clean_dsd_pool(ha, sp, NULL);
9ba56b95
GM		 631 sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
632 }
633
634 if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
635 dma_pool_free(ha->dl_dma_pool, ctx,
636 ((struct crc_context *)ctx)->crc_ctx_dma);
637 sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
638 }
639
640 if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
641 struct ct6_dsd *ctx1 = (struct ct6_dsd *)ctx;
fca29703 642
9ba56b95
GM		 643 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd,
644 ctx1->fcp_cmnd_dma);
645 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list);
646 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt;
647 ha->gbl_dsd_avail += ctx1->dsd_use_cnt;
648 mempool_free(ctx1, ha->ctx_mempool);
649 ctx1 = NULL;
650 }
651
652 CMD_SP(cmd) = NULL;
b00ee7d7 653 qla2x00_rel_sp(sp->fcport->vha, sp);
9ba56b95
GM		 654}
655
14b06808 656static void
9ba56b95
GM		 657qla2x00_sp_compl(void *data, void *ptr, int res)
658{
659 struct qla_hw_data *ha = (struct qla_hw_data *)data;
660 srb_t *sp = (srb_t *)ptr;
661 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
662
663 cmd->result = res;
664
665 if (atomic_read(&sp->ref_count) == 0) {
666 ql_dbg(ql_dbg_io, sp->fcport->vha, 0x3015,
667 "SP reference-count to ZERO -- sp=%p cmd=%p.\n",
668 sp, GET_CMD_SP(sp));
669 if (ql2xextended_error_logging & ql_dbg_io)
8fbdac8c 670 WARN_ON(atomic_read(&sp->ref_count) == 0);
9ba56b95
GM		 671 return;
672 }
673 if (!atomic_dec_and_test(&sp->ref_count))
674 return;
675
676 qla2x00_sp_free_dma(ha, sp);
677 cmd->scsi_done(cmd);
fca29703
AV		 678}
679
8ae6d9c7
GM		 680/* If we are SP1 here, we need to still take and release the host_lock as SP1
681 * does not have the changes necessary to avoid taking host->host_lock.
682 */
1da177e4 683static int
f5e3e40b 684qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
fca29703 685{
134ae078 686 scsi_qla_host_t *vha = shost_priv(host);
fca29703 687 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
19a7b4ae 688 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
e315cd28
AC		 689 struct qla_hw_data *ha = vha->hw;
690 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
fca29703
AV		 691 srb_t *sp;
692 int rval;
693
85880801 694 if (ha->flags.eeh_busy) {
7c3df132 695 if (ha->flags.pci_channel_io_perm_failure) {
5f28d2d7 696 ql_dbg(ql_dbg_aer, vha, 0x9010,
7c3df132
SK		 697 "PCI Channel IO permanent failure, exiting "
698 "cmd=%p.\n", cmd);
b9b12f73 699 cmd->result = DID_NO_CONNECT << 16;
7c3df132 700 } else {
5f28d2d7 701 ql_dbg(ql_dbg_aer, vha, 0x9011,
7c3df132 702 "EEH_Busy, Requeuing the cmd=%p.\n", cmd);
85880801 703 cmd->result = DID_REQUEUE << 16;
7c3df132 704 }
14e660e6
SJ		 705 goto qc24_fail_command;
706 }
707
19a7b4ae
JSEC		 708 rval = fc_remote_port_chkready(rport);
709 if (rval) {
710 cmd->result = rval;
5f28d2d7 711 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3003,
7c3df132
SK		 712 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
713 cmd, rval);
fca29703
AV		 714 goto qc24_fail_command;
715 }
716
bad75002
AE		 717 if (!vha->flags.difdix_supported &&
718 scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) {
7c3df132
SK		 719 ql_dbg(ql_dbg_io, vha, 0x3004,
720 "DIF Cap not reg, fail DIF capable cmd's:%p.\n",
721 cmd);
bad75002
AE		 722 cmd->result = DID_NO_CONNECT << 16;
723 goto qc24_fail_command;
724 }
aa651be8
CD		 725
726 if (!fcport) {
727 cmd->result = DID_NO_CONNECT << 16;
728 goto qc24_fail_command;
729 }
730
fca29703
AV		 731 if (atomic_read(&fcport->state) != FCS_ONLINE) {
732 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
38170fa8 733 atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
7c3df132
SK		 734 ql_dbg(ql_dbg_io, vha, 0x3005,
735 "Returning DNC, fcport_state=%d loop_state=%d.\n",
736 atomic_read(&fcport->state),
737 atomic_read(&base_vha->loop_state));
fca29703
AV		 738 cmd->result = DID_NO_CONNECT << 16;
739 goto qc24_fail_command;
740 }
7b594131 741 goto qc24_target_busy;
fca29703
AV		 742 }
743
e05fe292
CD		 744 /*
745 * Return target busy if we've received a non-zero retry_delay_timer
746 * in a FCP_RSP.
747 */
975f7d46
BP		 748 if (fcport->retry_delay_timestamp == 0) {
749 /* retry delay not set */
750 } else if (time_after(jiffies, fcport->retry_delay_timestamp))
e05fe292
CD		 751 fcport->retry_delay_timestamp = 0;
752 else
753 goto qc24_target_busy;
754
b00ee7d7 755 sp = qla2x00_get_sp(vha, fcport, GFP_ATOMIC);
50280c01 756 if (!sp)
f5e3e40b 757 goto qc24_host_busy;
fca29703 758
9ba56b95
GM		 759 sp->u.scmd.cmd = cmd;
760 sp->type = SRB_SCSI_CMD;
761 atomic_set(&sp->ref_count, 1);
762 CMD_SP(cmd) = (void *)sp;
763 sp->free = qla2x00_sp_free_dma;
764 sp->done = qla2x00_sp_compl;
765
e315cd28 766 rval = ha->isp_ops->start_scsi(sp);
7c3df132 767 if (rval != QLA_SUCCESS) {
53016ed3 768 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3013,
7c3df132 769 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
fca29703 770 goto qc24_host_busy_free_sp;
7c3df132 771 }
fca29703 772
fca29703
AV		 773 return 0;
774
775qc24_host_busy_free_sp:
9ba56b95 776 qla2x00_sp_free_dma(ha, sp);
fca29703 777
f5e3e40b 778qc24_host_busy:
fca29703
AV		 779 return SCSI_MLQUEUE_HOST_BUSY;
780
7b594131
MC		 781qc24_target_busy:
782 return SCSI_MLQUEUE_TARGET_BUSY;
783
fca29703 784qc24_fail_command:
f5e3e40b 785 cmd->scsi_done(cmd);
fca29703
AV		 786
787 return 0;
788}
789
1da177e4
LT		 790/*
791 * qla2x00_eh_wait_on_command
792 * Waits for the command to be returned by the Firmware for some
793 * max time.
794 *
795 * Input:
1da177e4 796 * cmd = Scsi Command to wait on.
1da177e4
LT		 797 *
798 * Return:
799 * Not Found : 0
800 * Found : 1
801 */
802static int
e315cd28 803qla2x00_eh_wait_on_command(struct scsi_cmnd *cmd)
1da177e4 804{
fe74c71f 805#define ABORT_POLLING_PERIOD 1000
478c3b03 806#define ABORT_WAIT_ITER ((2 * 1000) / (ABORT_POLLING_PERIOD))
f4f051eb 807 unsigned long wait_iter = ABORT_WAIT_ITER;
85880801
AV		 808 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
809 struct qla_hw_data *ha = vha->hw;
f4f051eb 810 int ret = QLA_SUCCESS;
1da177e4 811
85880801 812 if (unlikely(pci_channel_offline(ha->pdev)) || ha->flags.eeh_busy) {
7c3df132
SK		 813 ql_dbg(ql_dbg_taskm, vha, 0x8005,
814 "Return:eh_wait.\n");
85880801
AV		 815 return ret;
816 }
817
d970432c 818 while (CMD_SP(cmd) && wait_iter--) {
fe74c71f 819 msleep(ABORT_POLLING_PERIOD);
f4f051eb 820 }
821 if (CMD_SP(cmd))
822 ret = QLA_FUNCTION_FAILED;
1da177e4 823
f4f051eb 824 return ret;
1da177e4
LT		 825}
826
827/*
828 * qla2x00_wait_for_hba_online
fa2a1ce5 829 * Wait till the HBA is online after going through
1da177e4
LT		 830 * <= MAX_RETRIES_OF_ISP_ABORT or
831 * finally HBA is disabled ie marked offline
832 *
833 * Input:
834 * ha - pointer to host adapter structure
fa2a1ce5
AV		 835 *
836 * Note:
1da177e4
LT		 837 * Does context switching-Release SPIN_LOCK
838 * (if any) before calling this routine.
839 *
840 * Return:
841 * Success (Adapter is online) : 0
842 * Failed (Adapter is offline/disabled) : 1
843 */
854165f4 844int
e315cd28 845qla2x00_wait_for_hba_online(scsi_qla_host_t *vha)
1da177e4 846{
fca29703
AV		 847 int return_status;
848 unsigned long wait_online;
e315cd28
AC		 849 struct qla_hw_data *ha = vha->hw;
850 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4 851
fa2a1ce5 852 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ);
e315cd28
AC		 853 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
854 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
855 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
856 ha->dpc_active) && time_before(jiffies, wait_online)) {
1da177e4
LT		 857
858 msleep(1000);
859 }
e315cd28 860 if (base_vha->flags.online)
fa2a1ce5 861 return_status = QLA_SUCCESS;
1da177e4
LT		 862 else
863 return_status = QLA_FUNCTION_FAILED;
864
1da177e4
LT		 865 return (return_status);
866}
867
86fbee86 868/*
638a1a01
SC		 869 * qla2x00_wait_for_hba_ready
870 * Wait till the HBA is ready before doing driver unload
86fbee86
LC		 871 *
872 * Input:
873 * ha - pointer to host adapter structure
874 *
875 * Note:
876 * Does context switching-Release SPIN_LOCK
877 * (if any) before calling this routine.
878 *
86fbee86 879 */
638a1a01
SC		 880static void
881qla2x00_wait_for_hba_ready(scsi_qla_host_t *vha)
86fbee86 882{
86fbee86 883 struct qla_hw_data *ha = vha->hw;
86fbee86 884
9d35894d
SC		 885 while (((qla2x00_reset_active(vha)) || ha->dpc_active ||
886 ha->flags.mbox_busy) ||
887 test_bit(FX00_RESET_RECOVERY, &vha->dpc_flags) ||
888 test_bit(FX00_TARGET_SCAN, &vha->dpc_flags))
86fbee86 889 msleep(1000);
86fbee86
LC		 890}
891
2533cf67
LC		 892int
893qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha)
894{
895 int return_status;
896 unsigned long wait_reset;
897 struct qla_hw_data *ha = vha->hw;
898 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
899
900 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ);
901 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
902 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
903 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
904 ha->dpc_active) && time_before(jiffies, wait_reset)) {
905
906 msleep(1000);
907
908 if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) &&
909 ha->flags.chip_reset_done)
910 break;
911 }
912 if (ha->flags.chip_reset_done)
913 return_status = QLA_SUCCESS;
914 else
915 return_status = QLA_FUNCTION_FAILED;
916
917 return return_status;
918}
919
083a469d
GM		 920static void
921sp_get(struct srb *sp)
922{
923 atomic_inc(&sp->ref_count);
924}
925
1da177e4
LT		 926/**************************************************************************
927* qla2xxx_eh_abort
928*
929* Description:
930* The abort function will abort the specified command.
931*
932* Input:
933* cmd = Linux SCSI command packet to be aborted.
934*
935* Returns:
936* Either SUCCESS or FAILED.
937*
938* Note:
2ea00202 939* Only return FAILED if command not returned by firmware.
1da177e4 940**************************************************************************/
e5f82ab8 941static int
1da177e4
LT		 942qla2xxx_eh_abort(struct scsi_cmnd *cmd)
943{
e315cd28 944 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
f4f051eb 945 srb_t *sp;
4e98d3b8 946 int ret;
9cb78c16
HR		 947 unsigned int id;
948 uint64_t lun;
18e144d3 949 unsigned long flags;
f934c9d0 950 int rval, wait = 0;
e315cd28 951 struct qla_hw_data *ha = vha->hw;
1da177e4 952
f4f051eb 953 if (!CMD_SP(cmd))
2ea00202 954 return SUCCESS;
1da177e4 955
4e98d3b8
AV		 956 ret = fc_block_scsi_eh(cmd);
957 if (ret != 0)
958 return ret;
959 ret = SUCCESS;
960
f4f051eb 961 id = cmd->device->id;
962 lun = cmd->device->lun;
1da177e4 963
e315cd28 964 spin_lock_irqsave(&ha->hardware_lock, flags);
170babc3
MC		 965 sp = (srb_t *) CMD_SP(cmd);
966 if (!sp) {
967 spin_unlock_irqrestore(&ha->hardware_lock, flags);
968 return SUCCESS;
969 }
1da177e4 970
7c3df132 971 ql_dbg(ql_dbg_taskm, vha, 0x8002,
c7bc4cae
CD		 972 "Aborting from RISC nexus=%ld:%d:%llu sp=%p cmd=%p handle=%x\n",
973 vha->host_no, id, lun, sp, cmd, sp->handle);
17d98630 974
170babc3
MC		 975 /* Get a reference to the sp and drop the lock.*/
976 sp_get(sp);
083a469d 977
e315cd28 978 spin_unlock_irqrestore(&ha->hardware_lock, flags);
f934c9d0
CD		 979 rval = ha->isp_ops->abort_command(sp);
980 if (rval) {
96219424 981 if (rval == QLA_FUNCTION_PARAMETER_ERROR)
f934c9d0 982 ret = SUCCESS;
96219424 983 else
f934c9d0
CD		 984 ret = FAILED;
985
7c3df132 986 ql_dbg(ql_dbg_taskm, vha, 0x8003,
f934c9d0 987 "Abort command mbx failed cmd=%p, rval=%x.\n", cmd, rval);
170babc3 988 } else {
7c3df132 989 ql_dbg(ql_dbg_taskm, vha, 0x8004,
cfb0919c 990 "Abort command mbx success cmd=%p.\n", cmd);
170babc3
MC		 991 wait = 1;
992 }
75942064
SK		 993
994 spin_lock_irqsave(&ha->hardware_lock, flags);
9ba56b95 995 sp->done(ha, sp, 0);
75942064 996 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1da177e4 997
bc91ade9
CD		 998 /* Did the command return during mailbox execution? */
999 if (ret == FAILED && !CMD_SP(cmd))
1000 ret = SUCCESS;
1001
f4f051eb 1002 /* Wait for the command to be returned. */
2ea00202 1003 if (wait) {
e315cd28 1004 if (qla2x00_eh_wait_on_command(cmd) != QLA_SUCCESS) {
7c3df132 1005 ql_log(ql_log_warn, vha, 0x8006,
cfb0919c 1006 "Abort handler timed out cmd=%p.\n", cmd);
2ea00202 1007 ret = FAILED;
f4f051eb 1008 }
1da177e4 1009 }
1da177e4 1010
7c3df132 1011 ql_log(ql_log_info, vha, 0x801c,
9cb78c16 1012 "Abort command issued nexus=%ld:%d:%llu -- %d %x.\n",
cfb0919c 1013 vha->host_no, id, lun, wait, ret);
1da177e4 1014
f4f051eb 1015 return ret;
1016}
1da177e4 1017
4d78c973 1018int
e315cd28 1019qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t,
9cb78c16 1020 uint64_t l, enum nexus_wait_type type)
f4f051eb 1021{
17d98630 1022 int cnt, match, status;
18e144d3 1023 unsigned long flags;
e315cd28 1024 struct qla_hw_data *ha = vha->hw;
73208dfd 1025 struct req_que *req;
4d78c973 1026 srb_t *sp;
9ba56b95 1027 struct scsi_cmnd *cmd;
1da177e4 1028
523ec773 1029 status = QLA_SUCCESS;
17d98630 1030
e315cd28 1031 spin_lock_irqsave(&ha->hardware_lock, flags);
67c2e93a 1032 req = vha->req;
17d98630 1033 for (cnt = 1; status == QLA_SUCCESS &&
8d93f550 1034 cnt < req->num_outstanding_cmds; cnt++) {
17d98630
AC		 1035 sp = req->outstanding_cmds[cnt];
1036 if (!sp)
523ec773 1037 continue;
9ba56b95 1038 if (sp->type != SRB_SCSI_CMD)
cf53b069 1039 continue;
17d98630
AC		 1040 if (vha->vp_idx != sp->fcport->vha->vp_idx)
1041 continue;
1042 match = 0;
9ba56b95 1043 cmd = GET_CMD_SP(sp);
17d98630
AC		 1044 switch (type) {
1045 case WAIT_HOST:
1046 match = 1;
1047 break;
1048 case WAIT_TARGET:
9ba56b95 1049 match = cmd->device->id == t;
17d98630
AC		 1050 break;
1051 case WAIT_LUN:
9ba56b95
GM		 1052 match = (cmd->device->id == t &&
1053 cmd->device->lun == l);
17d98630 1054 break;
73208dfd 1055 }
17d98630
AC		 1056 if (!match)
1057 continue;
1058
1059 spin_unlock_irqrestore(&ha->hardware_lock, flags);
9ba56b95 1060 status = qla2x00_eh_wait_on_command(cmd);
17d98630 1061 spin_lock_irqsave(&ha->hardware_lock, flags);
1da177e4 1062 }
e315cd28 1063 spin_unlock_irqrestore(&ha->hardware_lock, flags);
523ec773
AV		 1064
1065 return status;
1da177e4
LT		 1066}
1067
523ec773
AV		 1068static char *reset_errors[] = {
1069 "HBA not online",
1070 "HBA not ready",
1071 "Task management failed",
1072 "Waiting for command completions",
1073};
1da177e4 1074
e5f82ab8 1075static int
523ec773 1076__qla2xxx_eh_generic_reset(char *name, enum nexus_wait_type type,
9cb78c16 1077 struct scsi_cmnd *cmd, int (*do_reset)(struct fc_port *, uint64_t, int))
1da177e4 1078{
e315cd28 1079 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
bdf79621 1080 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
523ec773 1081 int err;
1da177e4 1082
7c3df132 1083 if (!fcport) {
523ec773 1084 return FAILED;
7c3df132 1085 }
1da177e4 1086
4e98d3b8
AV		 1087 err = fc_block_scsi_eh(cmd);
1088 if (err != 0)
1089 return err;
1090
7c3df132 1091 ql_log(ql_log_info, vha, 0x8009,
9cb78c16 1092 "%s RESET ISSUED nexus=%ld:%d:%llu cmd=%p.\n", name, vha->host_no,
7c3df132 1093 cmd->device->id, cmd->device->lun, cmd);
1da177e4 1094
523ec773 1095 err = 0;
7c3df132
SK		 1096 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1097 ql_log(ql_log_warn, vha, 0x800a,
1098 "Wait for hba online failed for cmd=%p.\n", cmd);
523ec773 1099 goto eh_reset_failed;
7c3df132 1100 }
523ec773 1101 err = 2;
2afa19a9 1102 if (do_reset(fcport, cmd->device->lun, cmd->request->cpu + 1)
7c3df132
SK		 1103 != QLA_SUCCESS) {
1104 ql_log(ql_log_warn, vha, 0x800c,
1105 "do_reset failed for cmd=%p.\n", cmd);
523ec773 1106 goto eh_reset_failed;
7c3df132 1107 }
523ec773 1108 err = 3;
e315cd28 1109 if (qla2x00_eh_wait_for_pending_commands(vha, cmd->device->id,
7c3df132
SK		 1110 cmd->device->lun, type) != QLA_SUCCESS) {
1111 ql_log(ql_log_warn, vha, 0x800d,
d6a03581 1112 "wait for pending cmds failed for cmd=%p.\n", cmd);
523ec773 1113 goto eh_reset_failed;
7c3df132 1114 }
523ec773 1115
7c3df132 1116 ql_log(ql_log_info, vha, 0x800e,
9cb78c16 1117 "%s RESET SUCCEEDED nexus:%ld:%d:%llu cmd=%p.\n", name,
cfb0919c 1118 vha->host_no, cmd->device->id, cmd->device->lun, cmd);
523ec773
AV		 1119
1120 return SUCCESS;
1121
4d78c973 1122eh_reset_failed:
7c3df132 1123 ql_log(ql_log_info, vha, 0x800f,
9cb78c16 1124 "%s RESET FAILED: %s nexus=%ld:%d:%llu cmd=%p.\n", name,
cfb0919c
CD		 1125 reset_errors[err], vha->host_no, cmd->device->id, cmd->device->lun,
1126 cmd);
523ec773
AV		 1127 return FAILED;
1128}
1da177e4 1129
523ec773
AV		 1130static int
1131qla2xxx_eh_device_reset(struct scsi_cmnd *cmd)
1132{
e315cd28
AC		 1133 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1134 struct qla_hw_data *ha = vha->hw;
1da177e4 1135
523ec773
AV		 1136 return __qla2xxx_eh_generic_reset("DEVICE", WAIT_LUN, cmd,
1137 ha->isp_ops->lun_reset);
1da177e4
LT		 1138}
1139
1da177e4 1140static int
523ec773 1141qla2xxx_eh_target_reset(struct scsi_cmnd *cmd)
1da177e4 1142{
e315cd28
AC		 1143 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1144 struct qla_hw_data *ha = vha->hw;
1da177e4 1145
523ec773
AV		 1146 return __qla2xxx_eh_generic_reset("TARGET", WAIT_TARGET, cmd,
1147 ha->isp_ops->target_reset);
1da177e4
LT		 1148}
1149
1da177e4
LT		 1150/**************************************************************************
1151* qla2xxx_eh_bus_reset
1152*
1153* Description:
1154* The bus reset function will reset the bus and abort any executing
1155* commands.
1156*
1157* Input:
1158* cmd = Linux SCSI command packet of the command that cause the
1159* bus reset.
1160*
1161* Returns:
1162* SUCCESS/FAILURE (defined as macro in scsi.h).
1163*
1164**************************************************************************/
e5f82ab8 1165static int
1da177e4
LT		 1166qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd)
1167{
e315cd28 1168 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
bdf79621 1169 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
2c3dfe3f 1170 int ret = FAILED;
9cb78c16
HR		 1171 unsigned int id;
1172 uint64_t lun;
f4f051eb 1173
f4f051eb 1174 id = cmd->device->id;
1175 lun = cmd->device->lun;
1da177e4 1176
7c3df132 1177 if (!fcport) {
f4f051eb 1178 return ret;
7c3df132 1179 }
1da177e4 1180
4e98d3b8
AV		 1181 ret = fc_block_scsi_eh(cmd);
1182 if (ret != 0)
1183 return ret;
1184 ret = FAILED;
1185
7c3df132 1186 ql_log(ql_log_info, vha, 0x8012,
9cb78c16 1187 "BUS RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun);
1da177e4 1188
e315cd28 1189 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
7c3df132
SK		 1190 ql_log(ql_log_fatal, vha, 0x8013,
1191 "Wait for hba online failed board disabled.\n");
f4f051eb 1192 goto eh_bus_reset_done;
1da177e4
LT		 1193 }
1194
ad537689
SK		 1195 if (qla2x00_loop_reset(vha) == QLA_SUCCESS)
1196 ret = SUCCESS;
1197
f4f051eb 1198 if (ret == FAILED)
1199 goto eh_bus_reset_done;
1da177e4 1200
9a41a62b 1201 /* Flush outstanding commands. */
4d78c973 1202 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) !=
7c3df132
SK		 1203 QLA_SUCCESS) {
1204 ql_log(ql_log_warn, vha, 0x8014,
1205 "Wait for pending commands failed.\n");
9a41a62b 1206 ret = FAILED;
7c3df132 1207 }
1da177e4 1208
f4f051eb 1209eh_bus_reset_done:
7c3df132 1210 ql_log(ql_log_warn, vha, 0x802b,
9cb78c16 1211 "BUS RESET %s nexus=%ld:%d:%llu.\n",
d6a03581 1212 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1da177e4 1213
f4f051eb 1214 return ret;
1da177e4
LT		 1215}
1216
1217/**************************************************************************
1218* qla2xxx_eh_host_reset
1219*
1220* Description:
1221* The reset function will reset the Adapter.
1222*
1223* Input:
1224* cmd = Linux SCSI command packet of the command that cause the
1225* adapter reset.
1226*
1227* Returns:
1228* Either SUCCESS or FAILED.
1229*
1230* Note:
1231**************************************************************************/
e5f82ab8 1232static int
1da177e4
LT		 1233qla2xxx_eh_host_reset(struct scsi_cmnd *cmd)
1234{
e315cd28 1235 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
e315cd28 1236 struct qla_hw_data *ha = vha->hw;
2c3dfe3f 1237 int ret = FAILED;
9cb78c16
HR		 1238 unsigned int id;
1239 uint64_t lun;
e315cd28 1240 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4 1241
f4f051eb 1242 id = cmd->device->id;
1243 lun = cmd->device->lun;
f4f051eb 1244
7c3df132 1245 ql_log(ql_log_info, vha, 0x8018,
9cb78c16 1246 "ADAPTER RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun);
1da177e4 1247
63ee7072
CD		 1248 /*
1249 * No point in issuing another reset if one is active. Also do not
1250 * attempt a reset if we are updating flash.
1251 */
1252 if (qla2x00_reset_active(vha) || ha->optrom_state != QLA_SWAITING)
f4f051eb 1253 goto eh_host_reset_lock;
1da177e4 1254
e315cd28
AC		 1255 if (vha != base_vha) {
1256 if (qla2x00_vp_abort_isp(vha))
f4f051eb 1257 goto eh_host_reset_lock;
e315cd28 1258 } else {
7ec0effd 1259 if (IS_P3P_TYPE(vha->hw)) {
a9083016
GM		 1260 if (!qla82xx_fcoe_ctx_reset(vha)) {
1261 /* Ctx reset success */
1262 ret = SUCCESS;
1263 goto eh_host_reset_lock;
1264 }
1265 /* fall thru if ctx reset failed */
1266 }
68ca949c
AC		 1267 if (ha->wq)
1268 flush_workqueue(ha->wq);
1269
e315cd28 1270 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
a9083016 1271 if (ha->isp_ops->abort_isp(base_vha)) {
e315cd28
AC		 1272 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1273 /* failed. schedule dpc to try */
1274 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
1275
7c3df132
SK		 1276 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1277 ql_log(ql_log_warn, vha, 0x802a,
1278 "wait for hba online failed.\n");
e315cd28 1279 goto eh_host_reset_lock;
7c3df132 1280 }
e315cd28
AC		 1281 }
1282 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
fa2a1ce5 1283 }
1da177e4 1284
e315cd28 1285 /* Waiting for command to be returned to OS.*/
4d78c973 1286 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) ==
e315cd28 1287 QLA_SUCCESS)
f4f051eb 1288 ret = SUCCESS;
1da177e4 1289
f4f051eb 1290eh_host_reset_lock:
cfb0919c 1291 ql_log(ql_log_info, vha, 0x8017,
9cb78c16 1292 "ADAPTER RESET %s nexus=%ld:%d:%llu.\n",
cfb0919c 1293 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1da177e4 1294
f4f051eb 1295 return ret;
1296}
1da177e4
LT		 1297
1298/*
1299* qla2x00_loop_reset
1300* Issue loop reset.
1301*
1302* Input:
1303* ha = adapter block pointer.
1304*
1305* Returns:
1306* 0 = success
1307*/
a4722cf2 1308int
e315cd28 1309qla2x00_loop_reset(scsi_qla_host_t *vha)
1da177e4 1310{
0c8c39af 1311 int ret;
bdf79621 1312 struct fc_port *fcport;
e315cd28 1313 struct qla_hw_data *ha = vha->hw;
1da177e4 1314
5854771e
AB		 1315 if (IS_QLAFX00(ha)) {
1316 return qlafx00_loop_reset(vha);
1317 }
1318
f4c496c1 1319 if (ql2xtargetreset == 1 && ha->flags.enable_target_reset) {
55e5ed27
AV		 1320 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1321 if (fcport->port_type != FCT_TARGET)
1322 continue;
1323
1324 ret = ha->isp_ops->target_reset(fcport, 0, 0);
1325 if (ret != QLA_SUCCESS) {
7c3df132 1326 ql_dbg(ql_dbg_taskm, vha, 0x802c,
5854771e 1327 "Bus Reset failed: Reset=%d "
7c3df132 1328 "d_id=%x.\n", ret, fcport->d_id.b24);
55e5ed27
AV		 1329 }
1330 }
1331 }
1332
8ae6d9c7 1333
6246b8a1 1334 if (ha->flags.enable_lip_full_login && !IS_CNA_CAPABLE(ha)) {
0b7e7c53
AV		 1335 atomic_set(&vha->loop_state, LOOP_DOWN);
1336 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
1337 qla2x00_mark_all_devices_lost(vha, 0);
e315cd28 1338 ret = qla2x00_full_login_lip(vha);
0c8c39af 1339 if (ret != QLA_SUCCESS) {
7c3df132
SK		 1340 ql_dbg(ql_dbg_taskm, vha, 0x802d,
1341 "full_login_lip=%d.\n", ret);
749af3d5 1342 }
0c8c39af
AV		 1343 }
1344
0d6e61bc 1345 if (ha->flags.enable_lip_reset) {
e315cd28 1346 ret = qla2x00_lip_reset(vha);
ad537689 1347 if (ret != QLA_SUCCESS)
7c3df132
SK		 1348 ql_dbg(ql_dbg_taskm, vha, 0x802e,
1349 "lip_reset failed (%d).\n", ret);
1da177e4
LT		 1350 }
1351
1da177e4 1352 /* Issue marker command only when we are going to start the I/O */
e315cd28 1353 vha->marker_needed = 1;
1da177e4 1354
0c8c39af 1355 return QLA_SUCCESS;
1da177e4
LT		 1356}
1357
df4bf0bb 1358void
e315cd28 1359qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res)
df4bf0bb 1360{
73208dfd 1361 int que, cnt;
df4bf0bb
AV		 1362 unsigned long flags;
1363 srb_t *sp;
e315cd28 1364 struct qla_hw_data *ha = vha->hw;
73208dfd 1365 struct req_que *req;
df4bf0bb 1366
c0cb4496
AE		 1367 qlt_host_reset_handler(ha);
1368
df4bf0bb 1369 spin_lock_irqsave(&ha->hardware_lock, flags);
2afa19a9 1370 for (que = 0; que < ha->max_req_queues; que++) {
29bdccbe 1371 req = ha->req_q_map[que];
73208dfd
AC		 1372 if (!req)
1373 continue;
8d93f550
CD		 1374 if (!req->outstanding_cmds)
1375 continue;
1376 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) {
73208dfd 1377 sp = req->outstanding_cmds[cnt];
e612d465 1378 if (sp) {
73208dfd 1379 req->outstanding_cmds[cnt] = NULL;
9ba56b95 1380 sp->done(vha, sp, res);
73208dfd 1381 }
df4bf0bb
AV		 1382 }
1383 }
1384 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1385}
1386
f4f051eb 1387static int
1388qla2xxx_slave_alloc(struct scsi_device *sdev)
1da177e4 1389{
bdf79621 1390 struct fc_rport *rport = starget_to_rport(scsi_target(sdev));
1da177e4 1391
19a7b4ae 1392 if (!rport || fc_remote_port_chkready(rport))
f4f051eb 1393 return -ENXIO;
bdf79621 1394
19a7b4ae 1395 sdev->hostdata = *(fc_port_t **)rport->dd_data;
1da177e4 1396
f4f051eb 1397 return 0;
1398}
1da177e4 1399
f4f051eb 1400static int
1401qla2xxx_slave_configure(struct scsi_device *sdev)
1402{
e315cd28 1403 scsi_qla_host_t *vha = shost_priv(sdev->host);
2afa19a9 1404 struct req_que *req = vha->req;
8482e118 1405
9e522cd8
AE		 1406 if (IS_T10_PI_CAPABLE(vha->hw))
1407 blk_queue_update_dma_alignment(sdev->request_queue, 0x7);
1408
db5ed4df 1409 scsi_change_queue_depth(sdev, req->max_q_depth);
f4f051eb 1410 return 0;
1411}
1da177e4 1412
f4f051eb 1413static void
1414qla2xxx_slave_destroy(struct scsi_device *sdev)
1415{
1416 sdev->hostdata = NULL;
1da177e4
LT		 1417}
1418
1419/**
1420 * qla2x00_config_dma_addressing() - Configure OS DMA addressing method.
1421 * @ha: HA context
1422 *
1423 * At exit, the @ha's flags.enable_64bit_addressing set to indicated
1424 * supported addressing method.
1425 */
1426static void
53303c42 1427qla2x00_config_dma_addressing(struct qla_hw_data *ha)
1da177e4 1428{
7524f9b9 1429 /* Assume a 32bit DMA mask. */
1da177e4 1430 ha->flags.enable_64bit_addressing = 0;
1da177e4 1431
6a35528a 1432 if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) {
7524f9b9
AV		 1433 /* Any upper-dword bits set? */
1434 if (MSD(dma_get_required_mask(&ha->pdev->dev)) &&
6a35528a 1435 !pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(64))) {
7524f9b9 1436 /* Ok, a 64bit DMA mask is applicable. */
1da177e4 1437 ha->flags.enable_64bit_addressing = 1;
fd34f556
AV		 1438 ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64;
1439 ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64;
7524f9b9 1440 return;
1da177e4 1441 }
1da177e4 1442 }
7524f9b9 1443
284901a9
YH		 1444 dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32));
1445 pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(32));
1da177e4
LT		 1446}
1447
fd34f556 1448static void
e315cd28 1449qla2x00_enable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1450{
1451 unsigned long flags = 0;
1452 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1453
1454 spin_lock_irqsave(&ha->hardware_lock, flags);
1455 ha->interrupts_on = 1;
1456 /* enable risc and host interrupts */
1457 WRT_REG_WORD(&reg->ictrl, ICR_EN_INT | ICR_EN_RISC);
1458 RD_REG_WORD(&reg->ictrl);
1459 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1460
1461}
1462
1463static void
e315cd28 1464qla2x00_disable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1465{
1466 unsigned long flags = 0;
1467 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1468
1469 spin_lock_irqsave(&ha->hardware_lock, flags);
1470 ha->interrupts_on = 0;
1471 /* disable risc and host interrupts */
1472 WRT_REG_WORD(&reg->ictrl, 0);
1473 RD_REG_WORD(&reg->ictrl);
1474 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1475}
1476
1477static void
e315cd28 1478qla24xx_enable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1479{
1480 unsigned long flags = 0;
1481 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1482
1483 spin_lock_irqsave(&ha->hardware_lock, flags);
1484 ha->interrupts_on = 1;
1485 WRT_REG_DWORD(&reg->ictrl, ICRX_EN_RISC_INT);
1486 RD_REG_DWORD(&reg->ictrl);
1487 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1488}
1489
1490static void
e315cd28 1491qla24xx_disable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1492{
1493 unsigned long flags = 0;
1494 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1495
124f85e6
AV		 1496 if (IS_NOPOLLING_TYPE(ha))
1497 return;
fd34f556
AV		 1498 spin_lock_irqsave(&ha->hardware_lock, flags);
1499 ha->interrupts_on = 0;
1500 WRT_REG_DWORD(&reg->ictrl, 0);
1501 RD_REG_DWORD(&reg->ictrl);
1502 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1503}
1504
706f457d
GM		 1505static int
1506qla2x00_iospace_config(struct qla_hw_data *ha)
1507{
1508 resource_size_t pio;
1509 uint16_t msix;
1510 int cpus;
1511
706f457d
GM		 1512 if (pci_request_selected_regions(ha->pdev, ha->bars,
1513 QLA2XXX_DRIVER_NAME)) {
1514 ql_log_pci(ql_log_fatal, ha->pdev, 0x0011,
1515 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
1516 pci_name(ha->pdev));
1517 goto iospace_error_exit;
1518 }
1519 if (!(ha->bars & 1))
1520 goto skip_pio;
1521
1522 /* We only need PIO for Flash operations on ISP2312 v2 chips. */
1523 pio = pci_resource_start(ha->pdev, 0);
1524 if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) {
1525 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
1526 ql_log_pci(ql_log_warn, ha->pdev, 0x0012,
1527 "Invalid pci I/O region size (%s).\n",
1528 pci_name(ha->pdev));
1529 pio = 0;
1530 }
1531 } else {
1532 ql_log_pci(ql_log_warn, ha->pdev, 0x0013,
1533 "Region #0 no a PIO resource (%s).\n",
1534 pci_name(ha->pdev));
1535 pio = 0;
1536 }
1537 ha->pio_address = pio;
1538 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014,
1539 "PIO address=%llu.\n",
1540 (unsigned long long)ha->pio_address);
1541
1542skip_pio:
1543 /* Use MMIO operations for all accesses. */
1544 if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) {
1545 ql_log_pci(ql_log_fatal, ha->pdev, 0x0015,
1546 "Region #1 not an MMIO resource (%s), aborting.\n",
1547 pci_name(ha->pdev));
1548 goto iospace_error_exit;
1549 }
1550 if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) {
1551 ql_log_pci(ql_log_fatal, ha->pdev, 0x0016,
1552 "Invalid PCI mem region size (%s), aborting.\n",
1553 pci_name(ha->pdev));
1554 goto iospace_error_exit;
1555 }
1556
1557 ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN);
1558 if (!ha->iobase) {
1559 ql_log_pci(ql_log_fatal, ha->pdev, 0x0017,
1560 "Cannot remap MMIO (%s), aborting.\n",
1561 pci_name(ha->pdev));
1562 goto iospace_error_exit;
1563 }
1564
1565 /* Determine queue resources */
1566 ha->max_req_queues = ha->max_rsp_queues = 1;
1567 if ((ql2xmaxqueues <= 1 && !ql2xmultique_tag) ||
1568 (ql2xmaxqueues > 1 && ql2xmultique_tag) ||
1569 (!IS_QLA25XX(ha) && !IS_QLA81XX(ha)))
1570 goto mqiobase_exit;
1571
1572 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3),
1573 pci_resource_len(ha->pdev, 3));
1574 if (ha->mqiobase) {
1575 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018,
1576 "MQIO Base=%p.\n", ha->mqiobase);
1577 /* Read MSIX vector size of the board */
1578 pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix);
1579 ha->msix_count = msix;
1580 /* Max queues are bounded by available msix vectors */
1581 /* queue 0 uses two msix vectors */
1582 if (ql2xmultique_tag) {
1583 cpus = num_online_cpus();
1584 ha->max_rsp_queues = (ha->msix_count - 1 > cpus) ?
1585 (cpus + 1) : (ha->msix_count - 1);
1586 ha->max_req_queues = 2;
1587 } else if (ql2xmaxqueues > 1) {
1588 ha->max_req_queues = ql2xmaxqueues > QLA_MQ_SIZE ?
1589 QLA_MQ_SIZE : ql2xmaxqueues;
1590 ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc008,
1591 "QoS mode set, max no of request queues:%d.\n",
1592 ha->max_req_queues);
1593 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0019,
1594 "QoS mode set, max no of request queues:%d.\n",
1595 ha->max_req_queues);
1596 }
1597 ql_log_pci(ql_log_info, ha->pdev, 0x001a,
1598 "MSI-X vector count: %d.\n", msix);
1599 } else
1600 ql_log_pci(ql_log_info, ha->pdev, 0x001b,
1601 "BAR 3 not enabled.\n");
1602
1603mqiobase_exit:
1604 ha->msix_count = ha->max_rsp_queues + 1;
1605 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c,
1606 "MSIX Count:%d.\n", ha->msix_count);
1607 return (0);
1608
1609iospace_error_exit:
1610 return (-ENOMEM);
1611}
1612
1613
6246b8a1
GM		 1614static int
1615qla83xx_iospace_config(struct qla_hw_data *ha)
1616{
1617 uint16_t msix;
1618 int cpus;
1619
1620 if (pci_request_selected_regions(ha->pdev, ha->bars,
1621 QLA2XXX_DRIVER_NAME)) {
1622 ql_log_pci(ql_log_fatal, ha->pdev, 0x0117,
1623 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
1624 pci_name(ha->pdev));
1625
1626 goto iospace_error_exit;
1627 }
1628
1629 /* Use MMIO operations for all accesses. */
1630 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) {
1631 ql_log_pci(ql_log_warn, ha->pdev, 0x0118,
1632 "Invalid pci I/O region size (%s).\n",
1633 pci_name(ha->pdev));
1634 goto iospace_error_exit;
1635 }
1636 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
1637 ql_log_pci(ql_log_warn, ha->pdev, 0x0119,
1638 "Invalid PCI mem region size (%s), aborting\n",
1639 pci_name(ha->pdev));
1640 goto iospace_error_exit;
1641 }
1642
1643 ha->iobase = ioremap(pci_resource_start(ha->pdev, 0), MIN_IOBASE_LEN);
1644 if (!ha->iobase) {
1645 ql_log_pci(ql_log_fatal, ha->pdev, 0x011a,
1646 "Cannot remap MMIO (%s), aborting.\n",
1647 pci_name(ha->pdev));
1648 goto iospace_error_exit;
1649 }
1650
1651 /* 64bit PCI BAR - BAR2 will correspoond to region 4 */
1652 /* 83XX 26XX always use MQ type access for queues
1653 * - mbar 2, a.k.a region 4 */
1654 ha->max_req_queues = ha->max_rsp_queues = 1;
1655 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 4),
1656 pci_resource_len(ha->pdev, 4));
1657
1658 if (!ha->mqiobase) {
1659 ql_log_pci(ql_log_fatal, ha->pdev, 0x011d,
1660 "BAR2/region4 not enabled\n");
1661 goto mqiobase_exit;
1662 }
1663
1664 ha->msixbase = ioremap(pci_resource_start(ha->pdev, 2),
1665 pci_resource_len(ha->pdev, 2));
1666 if (ha->msixbase) {
1667 /* Read MSIX vector size of the board */
1668 pci_read_config_word(ha->pdev,
1669 QLA_83XX_PCI_MSIX_CONTROL, &msix);
1670 ha->msix_count = msix;
1671 /* Max queues are bounded by available msix vectors */
1672 /* queue 0 uses two msix vectors */
1673 if (ql2xmultique_tag) {
1674 cpus = num_online_cpus();
1675 ha->max_rsp_queues = (ha->msix_count - 1 > cpus) ?
1676 (cpus + 1) : (ha->msix_count - 1);
1677 ha->max_req_queues = 2;
1678 } else if (ql2xmaxqueues > 1) {
1679 ha->max_req_queues = ql2xmaxqueues > QLA_MQ_SIZE ?
1680 QLA_MQ_SIZE : ql2xmaxqueues;
1681 ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc00c,
1682 "QoS mode set, max no of request queues:%d.\n",
1683 ha->max_req_queues);
1684 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b,
1685 "QoS mode set, max no of request queues:%d.\n",
1686 ha->max_req_queues);
1687 }
1688 ql_log_pci(ql_log_info, ha->pdev, 0x011c,
1689 "MSI-X vector count: %d.\n", msix);
1690 } else
1691 ql_log_pci(ql_log_info, ha->pdev, 0x011e,
1692 "BAR 1 not enabled.\n");
1693
1694mqiobase_exit:
1695 ha->msix_count = ha->max_rsp_queues + 1;
aa230bc5
AE		 1696
1697 qlt_83xx_iospace_config(ha);
1698
6246b8a1
GM		 1699 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011f,
1700 "MSIX Count:%d.\n", ha->msix_count);
1701 return 0;
1702
1703iospace_error_exit:
1704 return -ENOMEM;
1705}
1706
fd34f556
AV		 1707static struct isp_operations qla2100_isp_ops = {
1708 .pci_config = qla2100_pci_config,
1709 .reset_chip = qla2x00_reset_chip,
1710 .chip_diag = qla2x00_chip_diag,
1711 .config_rings = qla2x00_config_rings,
1712 .reset_adapter = qla2x00_reset_adapter,
1713 .nvram_config = qla2x00_nvram_config,
1714 .update_fw_options = qla2x00_update_fw_options,
1715 .load_risc = qla2x00_load_risc,
1716 .pci_info_str = qla2x00_pci_info_str,
1717 .fw_version_str = qla2x00_fw_version_str,
1718 .intr_handler = qla2100_intr_handler,
1719 .enable_intrs = qla2x00_enable_intrs,
1720 .disable_intrs = qla2x00_disable_intrs,
1721 .abort_command = qla2x00_abort_command,
523ec773
AV		 1722 .target_reset = qla2x00_abort_target,
1723 .lun_reset = qla2x00_lun_reset,
fd34f556
AV		 1724 .fabric_login = qla2x00_login_fabric,
1725 .fabric_logout = qla2x00_fabric_logout,
1726 .calc_req_entries = qla2x00_calc_iocbs_32,
1727 .build_iocbs = qla2x00_build_scsi_iocbs_32,
1728 .prep_ms_iocb = qla2x00_prep_ms_iocb,
1729 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
1730 .read_nvram = qla2x00_read_nvram_data,
1731 .write_nvram = qla2x00_write_nvram_data,
1732 .fw_dump = qla2100_fw_dump,
1733 .beacon_on = NULL,
1734 .beacon_off = NULL,
1735 .beacon_blink = NULL,
1736 .read_optrom = qla2x00_read_optrom_data,
1737 .write_optrom = qla2x00_write_optrom_data,
1738 .get_flash_version = qla2x00_get_flash_version,
e315cd28 1739 .start_scsi = qla2x00_start_scsi,
a9083016 1740 .abort_isp = qla2x00_abort_isp,
706f457d 1741 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 1742 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 1743};
1744
1745static struct isp_operations qla2300_isp_ops = {
1746 .pci_config = qla2300_pci_config,
1747 .reset_chip = qla2x00_reset_chip,
1748 .chip_diag = qla2x00_chip_diag,
1749 .config_rings = qla2x00_config_rings,
1750 .reset_adapter = qla2x00_reset_adapter,
1751 .nvram_config = qla2x00_nvram_config,
1752 .update_fw_options = qla2x00_update_fw_options,
1753 .load_risc = qla2x00_load_risc,
1754 .pci_info_str = qla2x00_pci_info_str,
1755 .fw_version_str = qla2x00_fw_version_str,
1756 .intr_handler = qla2300_intr_handler,
1757 .enable_intrs = qla2x00_enable_intrs,
1758 .disable_intrs = qla2x00_disable_intrs,
1759 .abort_command = qla2x00_abort_command,
523ec773
AV		 1760 .target_reset = qla2x00_abort_target,
1761 .lun_reset = qla2x00_lun_reset,
fd34f556
AV		 1762 .fabric_login = qla2x00_login_fabric,
1763 .fabric_logout = qla2x00_fabric_logout,
1764 .calc_req_entries = qla2x00_calc_iocbs_32,
1765 .build_iocbs = qla2x00_build_scsi_iocbs_32,
1766 .prep_ms_iocb = qla2x00_prep_ms_iocb,
1767 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
1768 .read_nvram = qla2x00_read_nvram_data,
1769 .write_nvram = qla2x00_write_nvram_data,
1770 .fw_dump = qla2300_fw_dump,
1771 .beacon_on = qla2x00_beacon_on,
1772 .beacon_off = qla2x00_beacon_off,
1773 .beacon_blink = qla2x00_beacon_blink,
1774 .read_optrom = qla2x00_read_optrom_data,
1775 .write_optrom = qla2x00_write_optrom_data,
1776 .get_flash_version = qla2x00_get_flash_version,
e315cd28 1777 .start_scsi = qla2x00_start_scsi,
a9083016 1778 .abort_isp = qla2x00_abort_isp,
7ec0effd 1779 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 1780 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 1781};
1782
1783static struct isp_operations qla24xx_isp_ops = {
1784 .pci_config = qla24xx_pci_config,
1785 .reset_chip = qla24xx_reset_chip,
1786 .chip_diag = qla24xx_chip_diag,
1787 .config_rings = qla24xx_config_rings,
1788 .reset_adapter = qla24xx_reset_adapter,
1789 .nvram_config = qla24xx_nvram_config,
1790 .update_fw_options = qla24xx_update_fw_options,
1791 .load_risc = qla24xx_load_risc,
1792 .pci_info_str = qla24xx_pci_info_str,
1793 .fw_version_str = qla24xx_fw_version_str,
1794 .intr_handler = qla24xx_intr_handler,
1795 .enable_intrs = qla24xx_enable_intrs,
1796 .disable_intrs = qla24xx_disable_intrs,
1797 .abort_command = qla24xx_abort_command,
523ec773
AV		 1798 .target_reset = qla24xx_abort_target,
1799 .lun_reset = qla24xx_lun_reset,
fd34f556
AV		 1800 .fabric_login = qla24xx_login_fabric,
1801 .fabric_logout = qla24xx_fabric_logout,
1802 .calc_req_entries = NULL,
1803 .build_iocbs = NULL,
1804 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1805 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1806 .read_nvram = qla24xx_read_nvram_data,
1807 .write_nvram = qla24xx_write_nvram_data,
1808 .fw_dump = qla24xx_fw_dump,
1809 .beacon_on = qla24xx_beacon_on,
1810 .beacon_off = qla24xx_beacon_off,
1811 .beacon_blink = qla24xx_beacon_blink,
1812 .read_optrom = qla24xx_read_optrom_data,
1813 .write_optrom = qla24xx_write_optrom_data,
1814 .get_flash_version = qla24xx_get_flash_version,
e315cd28 1815 .start_scsi = qla24xx_start_scsi,
a9083016 1816 .abort_isp = qla2x00_abort_isp,
7ec0effd 1817 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 1818 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 1819};
1820
c3a2f0df
AV		 1821static struct isp_operations qla25xx_isp_ops = {
1822 .pci_config = qla25xx_pci_config,
1823 .reset_chip = qla24xx_reset_chip,
1824 .chip_diag = qla24xx_chip_diag,
1825 .config_rings = qla24xx_config_rings,
1826 .reset_adapter = qla24xx_reset_adapter,
1827 .nvram_config = qla24xx_nvram_config,
1828 .update_fw_options = qla24xx_update_fw_options,
1829 .load_risc = qla24xx_load_risc,
1830 .pci_info_str = qla24xx_pci_info_str,
1831 .fw_version_str = qla24xx_fw_version_str,
1832 .intr_handler = qla24xx_intr_handler,
1833 .enable_intrs = qla24xx_enable_intrs,
1834 .disable_intrs = qla24xx_disable_intrs,
1835 .abort_command = qla24xx_abort_command,
523ec773
AV		 1836 .target_reset = qla24xx_abort_target,
1837 .lun_reset = qla24xx_lun_reset,
c3a2f0df
AV		 1838 .fabric_login = qla24xx_login_fabric,
1839 .fabric_logout = qla24xx_fabric_logout,
1840 .calc_req_entries = NULL,
1841 .build_iocbs = NULL,
1842 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1843 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1844 .read_nvram = qla25xx_read_nvram_data,
1845 .write_nvram = qla25xx_write_nvram_data,
1846 .fw_dump = qla25xx_fw_dump,
1847 .beacon_on = qla24xx_beacon_on,
1848 .beacon_off = qla24xx_beacon_off,
1849 .beacon_blink = qla24xx_beacon_blink,
338c9161 1850 .read_optrom = qla25xx_read_optrom_data,
c3a2f0df
AV		 1851 .write_optrom = qla24xx_write_optrom_data,
1852 .get_flash_version = qla24xx_get_flash_version,
bad75002 1853 .start_scsi = qla24xx_dif_start_scsi,
a9083016 1854 .abort_isp = qla2x00_abort_isp,
7ec0effd 1855 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 1856 .initialize_adapter = qla2x00_initialize_adapter,
c3a2f0df
AV		 1857};
1858
3a03eb79
AV		 1859static struct isp_operations qla81xx_isp_ops = {
1860 .pci_config = qla25xx_pci_config,
1861 .reset_chip = qla24xx_reset_chip,
1862 .chip_diag = qla24xx_chip_diag,
1863 .config_rings = qla24xx_config_rings,
1864 .reset_adapter = qla24xx_reset_adapter,
1865 .nvram_config = qla81xx_nvram_config,
1866 .update_fw_options = qla81xx_update_fw_options,
eaac30be 1867 .load_risc = qla81xx_load_risc,
3a03eb79
AV		 1868 .pci_info_str = qla24xx_pci_info_str,
1869 .fw_version_str = qla24xx_fw_version_str,
1870 .intr_handler = qla24xx_intr_handler,
1871 .enable_intrs = qla24xx_enable_intrs,
1872 .disable_intrs = qla24xx_disable_intrs,
1873 .abort_command = qla24xx_abort_command,
1874 .target_reset = qla24xx_abort_target,
1875 .lun_reset = qla24xx_lun_reset,
1876 .fabric_login = qla24xx_login_fabric,
1877 .fabric_logout = qla24xx_fabric_logout,
1878 .calc_req_entries = NULL,
1879 .build_iocbs = NULL,
1880 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1881 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
3d79038f
AV		 1882 .read_nvram = NULL,
1883 .write_nvram = NULL,
3a03eb79
AV		 1884 .fw_dump = qla81xx_fw_dump,
1885 .beacon_on = qla24xx_beacon_on,
1886 .beacon_off = qla24xx_beacon_off,
6246b8a1 1887 .beacon_blink = qla83xx_beacon_blink,
3a03eb79
AV		 1888 .read_optrom = qla25xx_read_optrom_data,
1889 .write_optrom = qla24xx_write_optrom_data,
1890 .get_flash_version = qla24xx_get_flash_version,
ba77ef53 1891 .start_scsi = qla24xx_dif_start_scsi,
a9083016 1892 .abort_isp = qla2x00_abort_isp,
7ec0effd 1893 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 1894 .initialize_adapter = qla2x00_initialize_adapter,
a9083016
GM		 1895};
1896
1897static struct isp_operations qla82xx_isp_ops = {
1898 .pci_config = qla82xx_pci_config,
1899 .reset_chip = qla82xx_reset_chip,
1900 .chip_diag = qla24xx_chip_diag,
1901 .config_rings = qla82xx_config_rings,
1902 .reset_adapter = qla24xx_reset_adapter,
1903 .nvram_config = qla81xx_nvram_config,
1904 .update_fw_options = qla24xx_update_fw_options,
1905 .load_risc = qla82xx_load_risc,
9d55ca66 1906 .pci_info_str = qla24xx_pci_info_str,
a9083016
GM		 1907 .fw_version_str = qla24xx_fw_version_str,
1908 .intr_handler = qla82xx_intr_handler,
1909 .enable_intrs = qla82xx_enable_intrs,
1910 .disable_intrs = qla82xx_disable_intrs,
1911 .abort_command = qla24xx_abort_command,
1912 .target_reset = qla24xx_abort_target,
1913 .lun_reset = qla24xx_lun_reset,
1914 .fabric_login = qla24xx_login_fabric,
1915 .fabric_logout = qla24xx_fabric_logout,
1916 .calc_req_entries = NULL,
1917 .build_iocbs = NULL,
1918 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1919 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1920 .read_nvram = qla24xx_read_nvram_data,
1921 .write_nvram = qla24xx_write_nvram_data,
a1b23c5a 1922 .fw_dump = qla82xx_fw_dump,
999916dc
SK		 1923 .beacon_on = qla82xx_beacon_on,
1924 .beacon_off = qla82xx_beacon_off,
1925 .beacon_blink = NULL,
a9083016
GM		 1926 .read_optrom = qla82xx_read_optrom_data,
1927 .write_optrom = qla82xx_write_optrom_data,
7ec0effd 1928 .get_flash_version = qla82xx_get_flash_version,
a9083016
GM		 1929 .start_scsi = qla82xx_start_scsi,
1930 .abort_isp = qla82xx_abort_isp,
706f457d 1931 .iospace_config = qla82xx_iospace_config,
8ae6d9c7 1932 .initialize_adapter = qla2x00_initialize_adapter,
3a03eb79
AV		 1933};
1934
7ec0effd
AD		 1935static struct isp_operations qla8044_isp_ops = {
1936 .pci_config = qla82xx_pci_config,
1937 .reset_chip = qla82xx_reset_chip,
1938 .chip_diag = qla24xx_chip_diag,
1939 .config_rings = qla82xx_config_rings,
1940 .reset_adapter = qla24xx_reset_adapter,
1941 .nvram_config = qla81xx_nvram_config,
1942 .update_fw_options = qla24xx_update_fw_options,
1943 .load_risc = qla82xx_load_risc,
1944 .pci_info_str = qla24xx_pci_info_str,
1945 .fw_version_str = qla24xx_fw_version_str,
1946 .intr_handler = qla8044_intr_handler,
1947 .enable_intrs = qla82xx_enable_intrs,
1948 .disable_intrs = qla82xx_disable_intrs,
1949 .abort_command = qla24xx_abort_command,
1950 .target_reset = qla24xx_abort_target,
1951 .lun_reset = qla24xx_lun_reset,
1952 .fabric_login = qla24xx_login_fabric,
1953 .fabric_logout = qla24xx_fabric_logout,
1954 .calc_req_entries = NULL,
1955 .build_iocbs = NULL,
1956 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1957 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1958 .read_nvram = NULL,
1959 .write_nvram = NULL,
a1b23c5a 1960 .fw_dump = qla8044_fw_dump,
7ec0effd
AD		 1961 .beacon_on = qla82xx_beacon_on,
1962 .beacon_off = qla82xx_beacon_off,
1963 .beacon_blink = NULL,
888e639d 1964 .read_optrom = qla8044_read_optrom_data,
7ec0effd
AD		 1965 .write_optrom = qla8044_write_optrom_data,
1966 .get_flash_version = qla82xx_get_flash_version,
1967 .start_scsi = qla82xx_start_scsi,
1968 .abort_isp = qla8044_abort_isp,
1969 .iospace_config = qla82xx_iospace_config,
1970 .initialize_adapter = qla2x00_initialize_adapter,
1971};
1972
6246b8a1
GM		 1973static struct isp_operations qla83xx_isp_ops = {
1974 .pci_config = qla25xx_pci_config,
1975 .reset_chip = qla24xx_reset_chip,
1976 .chip_diag = qla24xx_chip_diag,
1977 .config_rings = qla24xx_config_rings,
1978 .reset_adapter = qla24xx_reset_adapter,
1979 .nvram_config = qla81xx_nvram_config,
1980 .update_fw_options = qla81xx_update_fw_options,
1981 .load_risc = qla81xx_load_risc,
1982 .pci_info_str = qla24xx_pci_info_str,
1983 .fw_version_str = qla24xx_fw_version_str,
1984 .intr_handler = qla24xx_intr_handler,
1985 .enable_intrs = qla24xx_enable_intrs,
1986 .disable_intrs = qla24xx_disable_intrs,
1987 .abort_command = qla24xx_abort_command,
1988 .target_reset = qla24xx_abort_target,
1989 .lun_reset = qla24xx_lun_reset,
1990 .fabric_login = qla24xx_login_fabric,
1991 .fabric_logout = qla24xx_fabric_logout,
1992 .calc_req_entries = NULL,
1993 .build_iocbs = NULL,
1994 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1995 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1996 .read_nvram = NULL,
1997 .write_nvram = NULL,
1998 .fw_dump = qla83xx_fw_dump,
1999 .beacon_on = qla24xx_beacon_on,
2000 .beacon_off = qla24xx_beacon_off,
2001 .beacon_blink = qla83xx_beacon_blink,
2002 .read_optrom = qla25xx_read_optrom_data,
2003 .write_optrom = qla24xx_write_optrom_data,
2004 .get_flash_version = qla24xx_get_flash_version,
2005 .start_scsi = qla24xx_dif_start_scsi,
2006 .abort_isp = qla2x00_abort_isp,
2007 .iospace_config = qla83xx_iospace_config,
8ae6d9c7
GM		 2008 .initialize_adapter = qla2x00_initialize_adapter,
2009};
2010
2011static struct isp_operations qlafx00_isp_ops = {
2012 .pci_config = qlafx00_pci_config,
2013 .reset_chip = qlafx00_soft_reset,
2014 .chip_diag = qlafx00_chip_diag,
2015 .config_rings = qlafx00_config_rings,
2016 .reset_adapter = qlafx00_soft_reset,
2017 .nvram_config = NULL,
2018 .update_fw_options = NULL,
2019 .load_risc = NULL,
2020 .pci_info_str = qlafx00_pci_info_str,
2021 .fw_version_str = qlafx00_fw_version_str,
2022 .intr_handler = qlafx00_intr_handler,
2023 .enable_intrs = qlafx00_enable_intrs,
2024 .disable_intrs = qlafx00_disable_intrs,
4440e46d 2025 .abort_command = qla24xx_async_abort_command,
8ae6d9c7
GM		 2026 .target_reset = qlafx00_abort_target,
2027 .lun_reset = qlafx00_lun_reset,
2028 .fabric_login = NULL,
2029 .fabric_logout = NULL,
2030 .calc_req_entries = NULL,
2031 .build_iocbs = NULL,
2032 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2033 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2034 .read_nvram = qla24xx_read_nvram_data,
2035 .write_nvram = qla24xx_write_nvram_data,
2036 .fw_dump = NULL,
2037 .beacon_on = qla24xx_beacon_on,
2038 .beacon_off = qla24xx_beacon_off,
2039 .beacon_blink = NULL,
2040 .read_optrom = qla24xx_read_optrom_data,
2041 .write_optrom = qla24xx_write_optrom_data,
2042 .get_flash_version = qla24xx_get_flash_version,
2043 .start_scsi = qlafx00_start_scsi,
2044 .abort_isp = qlafx00_abort_isp,
2045 .iospace_config = qlafx00_iospace_config,
2046 .initialize_adapter = qlafx00_initialize_adapter,
6246b8a1
GM		 2047};
2048
f73cb695
CD		 2049static struct isp_operations qla27xx_isp_ops = {
2050 .pci_config = qla25xx_pci_config,
2051 .reset_chip = qla24xx_reset_chip,
2052 .chip_diag = qla24xx_chip_diag,
2053 .config_rings = qla24xx_config_rings,
2054 .reset_adapter = qla24xx_reset_adapter,
2055 .nvram_config = qla81xx_nvram_config,
2056 .update_fw_options = qla81xx_update_fw_options,
2057 .load_risc = qla81xx_load_risc,
2058 .pci_info_str = qla24xx_pci_info_str,
2059 .fw_version_str = qla24xx_fw_version_str,
2060 .intr_handler = qla24xx_intr_handler,
2061 .enable_intrs = qla24xx_enable_intrs,
2062 .disable_intrs = qla24xx_disable_intrs,
2063 .abort_command = qla24xx_abort_command,
2064 .target_reset = qla24xx_abort_target,
2065 .lun_reset = qla24xx_lun_reset,
2066 .fabric_login = qla24xx_login_fabric,
2067 .fabric_logout = qla24xx_fabric_logout,
2068 .calc_req_entries = NULL,
2069 .build_iocbs = NULL,
2070 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2071 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2072 .read_nvram = NULL,
2073 .write_nvram = NULL,
2074 .fw_dump = qla27xx_fwdump,
2075 .beacon_on = qla24xx_beacon_on,
2076 .beacon_off = qla24xx_beacon_off,
2077 .beacon_blink = qla83xx_beacon_blink,
2078 .read_optrom = qla25xx_read_optrom_data,
2079 .write_optrom = qla24xx_write_optrom_data,
2080 .get_flash_version = qla24xx_get_flash_version,
2081 .start_scsi = qla24xx_dif_start_scsi,
2082 .abort_isp = qla2x00_abort_isp,
2083 .iospace_config = qla83xx_iospace_config,
2084 .initialize_adapter = qla2x00_initialize_adapter,
2085};
2086
ea5b6382 2087static inline void
e315cd28 2088qla2x00_set_isp_flags(struct qla_hw_data *ha)
ea5b6382 2089{
2090 ha->device_type = DT_EXTENDED_IDS;
2091 switch (ha->pdev->device) {
2092 case PCI_DEVICE_ID_QLOGIC_ISP2100:
2093 ha->device_type |= DT_ISP2100;
2094 ha->device_type &= ~DT_EXTENDED_IDS;
441d1072 2095 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
ea5b6382 2096 break;
2097 case PCI_DEVICE_ID_QLOGIC_ISP2200:
2098 ha->device_type |= DT_ISP2200;
2099 ha->device_type &= ~DT_EXTENDED_IDS;
441d1072 2100 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
ea5b6382 2101 break;
2102 case PCI_DEVICE_ID_QLOGIC_ISP2300:
2103 ha->device_type |= DT_ISP2300;
4a59f71d 2104 ha->device_type |= DT_ZIO_SUPPORTED;
441d1072 2105 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 2106 break;
2107 case PCI_DEVICE_ID_QLOGIC_ISP2312:
2108 ha->device_type |= DT_ISP2312;
4a59f71d 2109 ha->device_type |= DT_ZIO_SUPPORTED;
441d1072 2110 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 2111 break;
2112 case PCI_DEVICE_ID_QLOGIC_ISP2322:
2113 ha->device_type |= DT_ISP2322;
4a59f71d 2114 ha->device_type |= DT_ZIO_SUPPORTED;
ea5b6382 2115 if (ha->pdev->subsystem_vendor == 0x1028 &&
2116 ha->pdev->subsystem_device == 0x0170)
2117 ha->device_type |= DT_OEM_001;
441d1072 2118 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 2119 break;
2120 case PCI_DEVICE_ID_QLOGIC_ISP6312:
2121 ha->device_type |= DT_ISP6312;
441d1072 2122 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 2123 break;
2124 case PCI_DEVICE_ID_QLOGIC_ISP6322:
2125 ha->device_type |= DT_ISP6322;
441d1072 2126 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 2127 break;
2128 case PCI_DEVICE_ID_QLOGIC_ISP2422:
2129 ha->device_type |= DT_ISP2422;
4a59f71d 2130 ha->device_type |= DT_ZIO_SUPPORTED;
e428924c 2131 ha->device_type |= DT_FWI2;
c76f2c01 2132 ha->device_type |= DT_IIDMA;
441d1072 2133 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2134 break;
2135 case PCI_DEVICE_ID_QLOGIC_ISP2432:
2136 ha->device_type |= DT_ISP2432;
4a59f71d 2137 ha->device_type |= DT_ZIO_SUPPORTED;
e428924c 2138 ha->device_type |= DT_FWI2;
c76f2c01 2139 ha->device_type |= DT_IIDMA;
441d1072 2140 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2141 break;
4d4df193
HK		 2142 case PCI_DEVICE_ID_QLOGIC_ISP8432:
2143 ha->device_type |= DT_ISP8432;
2144 ha->device_type |= DT_ZIO_SUPPORTED;
2145 ha->device_type |= DT_FWI2;
2146 ha->device_type |= DT_IIDMA;
2147 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2148 break;
044cc6c8 2149 case PCI_DEVICE_ID_QLOGIC_ISP5422:
2150 ha->device_type |= DT_ISP5422;
e428924c 2151 ha->device_type |= DT_FWI2;
441d1072 2152 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2153 break;
044cc6c8 2154 case PCI_DEVICE_ID_QLOGIC_ISP5432:
2155 ha->device_type |= DT_ISP5432;
e428924c 2156 ha->device_type |= DT_FWI2;
441d1072 2157 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2158 break;
c3a2f0df
AV		 2159 case PCI_DEVICE_ID_QLOGIC_ISP2532:
2160 ha->device_type |= DT_ISP2532;
2161 ha->device_type |= DT_ZIO_SUPPORTED;
2162 ha->device_type |= DT_FWI2;
2163 ha->device_type |= DT_IIDMA;
441d1072 2164 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2165 break;
3a03eb79
AV		 2166 case PCI_DEVICE_ID_QLOGIC_ISP8001:
2167 ha->device_type |= DT_ISP8001;
2168 ha->device_type |= DT_ZIO_SUPPORTED;
2169 ha->device_type |= DT_FWI2;
2170 ha->device_type |= DT_IIDMA;
2171 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2172 break;
a9083016
GM		 2173 case PCI_DEVICE_ID_QLOGIC_ISP8021:
2174 ha->device_type |= DT_ISP8021;
2175 ha->device_type |= DT_ZIO_SUPPORTED;
2176 ha->device_type |= DT_FWI2;
2177 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2178 /* Initialize 82XX ISP flags */
2179 qla82xx_init_flags(ha);
2180 break;
7ec0effd
AD		 2181 case PCI_DEVICE_ID_QLOGIC_ISP8044:
2182 ha->device_type |= DT_ISP8044;
2183 ha->device_type |= DT_ZIO_SUPPORTED;
2184 ha->device_type |= DT_FWI2;
2185 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2186 /* Initialize 82XX ISP flags */
2187 qla82xx_init_flags(ha);
2188 break;
6246b8a1
GM		 2189 case PCI_DEVICE_ID_QLOGIC_ISP2031:
2190 ha->device_type |= DT_ISP2031;
2191 ha->device_type |= DT_ZIO_SUPPORTED;
2192 ha->device_type |= DT_FWI2;
2193 ha->device_type |= DT_IIDMA;
2194 ha->device_type |= DT_T10_PI;
2195 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2196 break;
2197 case PCI_DEVICE_ID_QLOGIC_ISP8031:
2198 ha->device_type |= DT_ISP8031;
2199 ha->device_type |= DT_ZIO_SUPPORTED;
2200 ha->device_type |= DT_FWI2;
2201 ha->device_type |= DT_IIDMA;
2202 ha->device_type |= DT_T10_PI;
2203 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2204 break;
8ae6d9c7
GM		 2205 case PCI_DEVICE_ID_QLOGIC_ISPF001:
2206 ha->device_type |= DT_ISPFX00;
2207 break;
f73cb695
CD		 2208 case PCI_DEVICE_ID_QLOGIC_ISP2071:
2209 ha->device_type |= DT_ISP2071;
2210 ha->device_type |= DT_ZIO_SUPPORTED;
2211 ha->device_type |= DT_FWI2;
2212 ha->device_type |= DT_IIDMA;
2213 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2214 break;
2c5bbbb2
JC		 2215 case PCI_DEVICE_ID_QLOGIC_ISP2271:
2216 ha->device_type |= DT_ISP2271;
2217 ha->device_type |= DT_ZIO_SUPPORTED;
2218 ha->device_type |= DT_FWI2;
2219 ha->device_type |= DT_IIDMA;
2220 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2221 break;
2b48992f
SC		 2222 case PCI_DEVICE_ID_QLOGIC_ISP2261:
2223 ha->device_type |= DT_ISP2261;
2224 ha->device_type |= DT_ZIO_SUPPORTED;
2225 ha->device_type |= DT_FWI2;
2226 ha->device_type |= DT_IIDMA;
2227 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2228 break;
ea5b6382 2229 }
e5b68a61 2230
a9083016 2231 if (IS_QLA82XX(ha))
43a9c38b 2232 ha->port_no = ha->portnum & 1;
f73cb695 2233 else {
a9083016
GM		 2234 /* Get adapter physical port no from interrupt pin register. */
2235 pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no);
f73cb695
CD		 2236 if (IS_QLA27XX(ha))
2237 ha->port_no--;
2238 else
2239 ha->port_no = !(ha->port_no & 1);
2240 }
a9083016 2241
7c3df132 2242 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b,
d8424f68 2243 "device_type=0x%x port=%d fw_srisc_address=0x%x.\n",
f73cb695 2244 ha->device_type, ha->port_no, ha->fw_srisc_address);
ea5b6382 2245}
2246
1e99e33a
AV		 2247static void
2248qla2xxx_scan_start(struct Scsi_Host *shost)
2249{
e315cd28 2250 scsi_qla_host_t *vha = shost_priv(shost);
1e99e33a 2251
cbc8eb67
AV		 2252 if (vha->hw->flags.running_gold_fw)
2253 return;
2254
e315cd28
AC		 2255 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
2256 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
2257 set_bit(RSCN_UPDATE, &vha->dpc_flags);
2258 set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags);
1e99e33a
AV		 2259}
2260
2261static int
2262qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time)
2263{
e315cd28 2264 scsi_qla_host_t *vha = shost_priv(shost);
1e99e33a 2265
e315cd28 2266 if (!vha->host)
1e99e33a 2267 return 1;
e315cd28 2268 if (time > vha->hw->loop_reset_delay * HZ)
1e99e33a
AV		 2269 return 1;
2270
e315cd28 2271 return atomic_read(&vha->loop_state) == LOOP_READY;
1e99e33a
AV		 2272}
2273
1da177e4
LT		 2274/*
2275 * PCI driver interface
2276 */
6f039790 2277static int
7ee61397 2278qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
1da177e4 2279{
a1541d5a 2280 int ret = -ENODEV;
1da177e4 2281 struct Scsi_Host *host;
e315cd28
AC		 2282 scsi_qla_host_t *base_vha = NULL;
2283 struct qla_hw_data *ha;
29856e28 2284 char pci_info[30];
7d613ac6 2285 char fw_str[30], wq_name[30];
5433383e 2286 struct scsi_host_template *sht;
642ef983 2287 int bars, mem_only = 0;
e315cd28 2288 uint16_t req_length = 0, rsp_length = 0;
73208dfd
AC		 2289 struct req_que *req = NULL;
2290 struct rsp_que *rsp = NULL;
285d0321 2291 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO);
a5326f86 2292 sht = &qla2xxx_driver_template;
5433383e 2293 if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 ||
8bc69e7d 2294 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 ||
4d4df193 2295 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 ||
8bc69e7d 2296 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 ||
c3a2f0df 2297 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 ||
3a03eb79 2298 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 ||
a9083016 2299 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 ||
6246b8a1
GM		 2300 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021 ||
2301 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2031 ||
8ae6d9c7 2302 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8031 ||
7ec0effd 2303 pdev->device == PCI_DEVICE_ID_QLOGIC_ISPF001 ||
f73cb695 2304 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8044 ||
2c5bbbb2 2305 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2071 ||
2b48992f
SC		 2306 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2271 ||
2307 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2261) {
285d0321 2308 bars = pci_select_bars(pdev, IORESOURCE_MEM);
09483916 2309 mem_only = 1;
7c3df132
SK		 2310 ql_dbg_pci(ql_dbg_init, pdev, 0x0007,
2311 "Mem only adapter.\n");
285d0321 2312 }
7c3df132
SK		 2313 ql_dbg_pci(ql_dbg_init, pdev, 0x0008,
2314 "Bars=%d.\n", bars);
285d0321 2315
09483916
BH		 2316 if (mem_only) {
2317 if (pci_enable_device_mem(pdev))
2318 goto probe_out;
2319 } else {
2320 if (pci_enable_device(pdev))
2321 goto probe_out;
2322 }
285d0321 2323
0927678f
JB		 2324 /* This may fail but that's ok */
2325 pci_enable_pcie_error_reporting(pdev);
285d0321 2326
e315cd28
AC		 2327 ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL);
2328 if (!ha) {
7c3df132
SK		 2329 ql_log_pci(ql_log_fatal, pdev, 0x0009,
2330 "Unable to allocate memory for ha.\n");
e315cd28 2331 goto probe_out;
1da177e4 2332 }
7c3df132
SK		 2333 ql_dbg_pci(ql_dbg_init, pdev, 0x000a,
2334 "Memory allocated for ha=%p.\n", ha);
e315cd28 2335 ha->pdev = pdev;
2d70c103 2336 ha->tgt.enable_class_2 = ql2xenableclass2;
33e79977
QT		 2337 INIT_LIST_HEAD(&ha->tgt.q_full_list);
2338 spin_lock_init(&ha->tgt.q_full_lock);
7560151b 2339 spin_lock_init(&ha->tgt.sess_lock);
1da177e4
LT		 2340
2341 /* Clear our data area */
285d0321 2342 ha->bars = bars;
09483916 2343 ha->mem_only = mem_only;
df4bf0bb 2344 spin_lock_init(&ha->hardware_lock);
339aa70e 2345 spin_lock_init(&ha->vport_slock);
a9b6f722 2346 mutex_init(&ha->selflogin_lock);
7a8ab9c8 2347 mutex_init(&ha->optrom_mutex);
1da177e4 2348
ea5b6382 2349 /* Set ISP-type information. */
2350 qla2x00_set_isp_flags(ha);
ca79cf66
DG		 2351
2352 /* Set EEH reset type to fundamental if required by hba */
95676112 2353 if (IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha) ||
f73cb695 2354 IS_QLA83XX(ha) || IS_QLA27XX(ha))
ca79cf66 2355 pdev->needs_freset = 1;
ca79cf66 2356
cba1e47f
CD		 2357 ha->prev_topology = 0;
2358 ha->init_cb_size = sizeof(init_cb_t);
2359 ha->link_data_rate = PORT_SPEED_UNKNOWN;
2360 ha->optrom_size = OPTROM_SIZE_2300;
2361
abbd8870 2362 /* Assign ISP specific operations. */
1da177e4 2363 if (IS_QLA2100(ha)) {
642ef983 2364 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
1da177e4 2365 ha->mbx_count = MAILBOX_REGISTER_COUNT_2100;
e315cd28
AC		 2366 req_length = REQUEST_ENTRY_CNT_2100;
2367 rsp_length = RESPONSE_ENTRY_CNT_2100;
2368 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
abbd8870 2369 ha->gid_list_info_size = 4;
3a03eb79
AV		 2370 ha->flash_conf_off = ~0;
2371 ha->flash_data_off = ~0;
2372 ha->nvram_conf_off = ~0;
2373 ha->nvram_data_off = ~0;
fd34f556 2374 ha->isp_ops = &qla2100_isp_ops;
1da177e4 2375 } else if (IS_QLA2200(ha)) {
642ef983 2376 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
67ddda35 2377 ha->mbx_count = MAILBOX_REGISTER_COUNT_2200;
e315cd28
AC		 2378 req_length = REQUEST_ENTRY_CNT_2200;
2379 rsp_length = RESPONSE_ENTRY_CNT_2100;
2380 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
abbd8870 2381 ha->gid_list_info_size = 4;
3a03eb79
AV		 2382 ha->flash_conf_off = ~0;
2383 ha->flash_data_off = ~0;
2384 ha->nvram_conf_off = ~0;
2385 ha->nvram_data_off = ~0;
fd34f556 2386 ha->isp_ops = &qla2100_isp_ops;
fca29703 2387 } else if (IS_QLA23XX(ha)) {
642ef983 2388 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
1da177e4 2389 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2390 req_length = REQUEST_ENTRY_CNT_2200;
2391 rsp_length = RESPONSE_ENTRY_CNT_2300;
2392 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
abbd8870 2393 ha->gid_list_info_size = 6;
854165f4 2394 if (IS_QLA2322(ha) || IS_QLA6322(ha))
2395 ha->optrom_size = OPTROM_SIZE_2322;
3a03eb79
AV		 2396 ha->flash_conf_off = ~0;
2397 ha->flash_data_off = ~0;
2398 ha->nvram_conf_off = ~0;
2399 ha->nvram_data_off = ~0;
fd34f556 2400 ha->isp_ops = &qla2300_isp_ops;
4d4df193 2401 } else if (IS_QLA24XX_TYPE(ha)) {
642ef983 2402 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
fca29703 2403 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2404 req_length = REQUEST_ENTRY_CNT_24XX;
2405 rsp_length = RESPONSE_ENTRY_CNT_2300;
2d70c103 2406 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
e315cd28 2407 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2c3dfe3f 2408 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
fca29703 2409 ha->gid_list_info_size = 8;
854165f4 2410 ha->optrom_size = OPTROM_SIZE_24XX;
73208dfd 2411 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX;
fd34f556 2412 ha->isp_ops = &qla24xx_isp_ops;
3a03eb79
AV		 2413 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2414 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2415 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2416 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
c3a2f0df 2417 } else if (IS_QLA25XX(ha)) {
642ef983 2418 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
c3a2f0df 2419 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2420 req_length = REQUEST_ENTRY_CNT_24XX;
2421 rsp_length = RESPONSE_ENTRY_CNT_2300;
2d70c103 2422 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
e315cd28 2423 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
c3a2f0df 2424 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
c3a2f0df
AV		 2425 ha->gid_list_info_size = 8;
2426 ha->optrom_size = OPTROM_SIZE_25XX;
73208dfd 2427 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
c3a2f0df 2428 ha->isp_ops = &qla25xx_isp_ops;
3a03eb79
AV		 2429 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2430 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2431 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2432 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
2433 } else if (IS_QLA81XX(ha)) {
642ef983 2434 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3a03eb79
AV		 2435 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2436 req_length = REQUEST_ENTRY_CNT_24XX;
2437 rsp_length = RESPONSE_ENTRY_CNT_2300;
aa230bc5 2438 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
3a03eb79
AV		 2439 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2440 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2441 ha->gid_list_info_size = 8;
2442 ha->optrom_size = OPTROM_SIZE_81XX;
40859ae5 2443 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3a03eb79
AV		 2444 ha->isp_ops = &qla81xx_isp_ops;
2445 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2446 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2447 ha->nvram_conf_off = ~0;
2448 ha->nvram_data_off = ~0;
a9083016 2449 } else if (IS_QLA82XX(ha)) {
642ef983 2450 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
a9083016
GM		 2451 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2452 req_length = REQUEST_ENTRY_CNT_82XX;
2453 rsp_length = RESPONSE_ENTRY_CNT_82XX;
2454 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2455 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2456 ha->gid_list_info_size = 8;
2457 ha->optrom_size = OPTROM_SIZE_82XX;
087c621e 2458 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
a9083016
GM		 2459 ha->isp_ops = &qla82xx_isp_ops;
2460 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2461 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2462 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2463 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
7ec0effd
AD		 2464 } else if (IS_QLA8044(ha)) {
2465 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2466 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2467 req_length = REQUEST_ENTRY_CNT_82XX;
2468 rsp_length = RESPONSE_ENTRY_CNT_82XX;
2469 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2470 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2471 ha->gid_list_info_size = 8;
2472 ha->optrom_size = OPTROM_SIZE_83XX;
2473 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2474 ha->isp_ops = &qla8044_isp_ops;
2475 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2476 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2477 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2478 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
6246b8a1 2479 } else if (IS_QLA83XX(ha)) {
7d613ac6 2480 ha->portnum = PCI_FUNC(ha->pdev->devfn);
642ef983 2481 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
6246b8a1 2482 ha->mbx_count = MAILBOX_REGISTER_COUNT;
f2ea653f 2483 req_length = REQUEST_ENTRY_CNT_83XX;
6246b8a1 2484 rsp_length = RESPONSE_ENTRY_CNT_2300;
b8aa4bdf 2485 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
6246b8a1
GM		 2486 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2487 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2488 ha->gid_list_info_size = 8;
2489 ha->optrom_size = OPTROM_SIZE_83XX;
2490 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2491 ha->isp_ops = &qla83xx_isp_ops;
2492 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2493 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2494 ha->nvram_conf_off = ~0;
2495 ha->nvram_data_off = ~0;
8ae6d9c7
GM		 2496 } else if (IS_QLAFX00(ha)) {
2497 ha->max_fibre_devices = MAX_FIBRE_DEVICES_FX00;
2498 ha->mbx_count = MAILBOX_REGISTER_COUNT_FX00;
2499 ha->aen_mbx_count = AEN_MAILBOX_REGISTER_COUNT_FX00;
2500 req_length = REQUEST_ENTRY_CNT_FX00;
2501 rsp_length = RESPONSE_ENTRY_CNT_FX00;
8ae6d9c7
GM		 2502 ha->isp_ops = &qlafx00_isp_ops;
2503 ha->port_down_retry_count = 30; /* default value */
2504 ha->mr.fw_hbt_cnt = QLAFX00_HEARTBEAT_INTERVAL;
2505 ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL;
71e56003 2506 ha->mr.fw_critemp_timer_tick = QLAFX00_CRITEMP_INTERVAL;
8ae6d9c7 2507 ha->mr.fw_hbt_en = 1;
e8f5e95d
AB		 2508 ha->mr.host_info_resend = false;
2509 ha->mr.hinfo_resend_timer_tick = QLAFX00_HINFO_RESEND_INTERVAL;
f73cb695
CD		 2510 } else if (IS_QLA27XX(ha)) {
2511 ha->portnum = PCI_FUNC(ha->pdev->devfn);
2512 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2513 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2514 req_length = REQUEST_ENTRY_CNT_24XX;
2515 rsp_length = RESPONSE_ENTRY_CNT_2300;
b20f02e1 2516 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
f73cb695
CD		 2517 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2518 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2519 ha->gid_list_info_size = 8;
2520 ha->optrom_size = OPTROM_SIZE_83XX;
2521 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2522 ha->isp_ops = &qla27xx_isp_ops;
2523 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2524 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2525 ha->nvram_conf_off = ~0;
2526 ha->nvram_data_off = ~0;
1da177e4 2527 }
6246b8a1 2528
7c3df132
SK		 2529 ql_dbg_pci(ql_dbg_init, pdev, 0x001e,
2530 "mbx_count=%d, req_length=%d, "
2531 "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, "
642ef983
CD		 2532 "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, "
2533 "max_fibre_devices=%d.\n",
7c3df132
SK		 2534 ha->mbx_count, req_length, rsp_length, ha->max_loop_id,
2535 ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size,
642ef983 2536 ha->nvram_npiv_size, ha->max_fibre_devices);
7c3df132
SK		 2537 ql_dbg_pci(ql_dbg_init, pdev, 0x001f,
2538 "isp_ops=%p, flash_conf_off=%d, "
2539 "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n",
2540 ha->isp_ops, ha->flash_conf_off, ha->flash_data_off,
2541 ha->nvram_conf_off, ha->nvram_data_off);
706f457d
GM		 2542
2543 /* Configure PCI I/O space */
2544 ret = ha->isp_ops->iospace_config(ha);
2545 if (ret)
0a63ad12 2546 goto iospace_config_failed;
706f457d
GM		 2547
2548 ql_log_pci(ql_log_info, pdev, 0x001d,
2549 "Found an ISP%04X irq %d iobase 0x%p.\n",
2550 pdev->device, pdev->irq, ha->iobase);
6c2f527c 2551 mutex_init(&ha->vport_lock);
0b05a1f0
MB		 2552 init_completion(&ha->mbx_cmd_comp);
2553 complete(&ha->mbx_cmd_comp);
2554 init_completion(&ha->mbx_intr_comp);
23f2ebd1 2555 init_completion(&ha->dcbx_comp);
f356bef1 2556 init_completion(&ha->lb_portup_comp);
1da177e4 2557
2c3dfe3f 2558 set_bit(0, (unsigned long *) ha->vp_idx_map);
1da177e4 2559
53303c42 2560 qla2x00_config_dma_addressing(ha);
7c3df132
SK		 2561 ql_dbg_pci(ql_dbg_init, pdev, 0x0020,
2562 "64 Bit addressing is %s.\n",
2563 ha->flags.enable_64bit_addressing ? "enable" :
2564 "disable");
73208dfd 2565 ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp);
b2a72ec3 2566 if (ret) {
7c3df132
SK		 2567 ql_log_pci(ql_log_fatal, pdev, 0x0031,
2568 "Failed to allocate memory for adapter, aborting.\n");
1da177e4 2569
e315cd28
AC		 2570 goto probe_hw_failed;
2571 }
2572
73208dfd 2573 req->max_q_depth = MAX_Q_DEPTH;
e315cd28 2574 if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU)
73208dfd
AC		 2575 req->max_q_depth = ql2xmaxqdepth;
2576
e315cd28
AC		 2577
2578 base_vha = qla2x00_create_host(sht, ha);
2579 if (!base_vha) {
a1541d5a 2580 ret = -ENOMEM;
6e9f21f3 2581 qla2x00_mem_free(ha);
2afa19a9
AC		 2582 qla2x00_free_req_que(ha, req);
2583 qla2x00_free_rsp_que(ha, rsp);
e315cd28 2584 goto probe_hw_failed;
1da177e4
LT		 2585 }
2586
e315cd28 2587 pci_set_drvdata(pdev, base_vha);
6b383979 2588 set_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags);
e315cd28 2589
e315cd28 2590 host = base_vha->host;
2afa19a9 2591 base_vha->req = req;
73208dfd 2592 if (IS_QLA2XXX_MIDTYPE(ha))
e315cd28 2593 base_vha->mgmt_svr_loop_id = 10 + base_vha->vp_idx;
73208dfd 2594 else
e315cd28
AC		 2595 base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER +
2596 base_vha->vp_idx;
58548cb5 2597
8ae6d9c7
GM		 2598 /* Setup fcport template structure. */
2599 ha->mr.fcport.vha = base_vha;
2600 ha->mr.fcport.port_type = FCT_UNKNOWN;
2601 ha->mr.fcport.loop_id = FC_NO_LOOP_ID;
2602 qla2x00_set_fcport_state(&ha->mr.fcport, FCS_UNCONFIGURED);
2603 ha->mr.fcport.supported_classes = FC_COS_UNSPECIFIED;
2604 ha->mr.fcport.scan_state = 1;
2605
58548cb5
GM		 2606 /* Set the SG table size based on ISP type */
2607 if (!IS_FWI2_CAPABLE(ha)) {
2608 if (IS_QLA2100(ha))
2609 host->sg_tablesize = 32;
2610 } else {
2611 if (!IS_QLA82XX(ha))
2612 host->sg_tablesize = QLA_SG_ALL;
2613 }
642ef983 2614 host->max_id = ha->max_fibre_devices;
e315cd28
AC		 2615 host->cmd_per_lun = 3;
2616 host->unique_id = host->host_no;
e02587d7 2617 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif)
0c470874
AE		 2618 host->max_cmd_len = 32;
2619 else
2620 host->max_cmd_len = MAX_CMDSZ;
e315cd28 2621 host->max_channel = MAX_BUSES - 1;
755f516b
HR		 2622 /* Older HBAs support only 16-bit LUNs */
2623 if (!IS_QLAFX00(ha) && !IS_FWI2_CAPABLE(ha) &&
2624 ql2xmaxlun > 0xffff)
2625 host->max_lun = 0xffff;
2626 else
2627 host->max_lun = ql2xmaxlun;
e315cd28 2628 host->transportt = qla2xxx_transport_template;
9a069e19 2629 sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC);
e315cd28 2630
7c3df132
SK		 2631 ql_dbg(ql_dbg_init, base_vha, 0x0033,
2632 "max_id=%d this_id=%d "
2633 "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d "
1abf635d 2634 "max_lun=%llu transportt=%p, vendor_id=%llu.\n", host->max_id,
7c3df132
SK		 2635 host->this_id, host->cmd_per_lun, host->unique_id,
2636 host->max_cmd_len, host->max_channel, host->max_lun,
2637 host->transportt, sht->vendor_id);
2638
9a347ff4
CD		 2639que_init:
2640 /* Alloc arrays of request and response ring ptrs */
2641 if (!qla2x00_alloc_queues(ha, req, rsp)) {
2642 ql_log(ql_log_fatal, base_vha, 0x003d,
2643 "Failed to allocate memory for queue pointers..."
2644 "aborting.\n");
2645 goto probe_init_failed;
2646 }
2647
2d70c103 2648 qlt_probe_one_stage1(base_vha, ha);
9a347ff4 2649
73208dfd
AC		 2650 /* Set up the irqs */
2651 ret = qla2x00_request_irqs(ha, rsp);
2652 if (ret)
6e9f21f3 2653 goto probe_init_failed;
90a86fc0
JC		 2654
2655 pci_save_state(pdev);
2656
9a347ff4 2657 /* Assign back pointers */
2afa19a9
AC		 2658 rsp->req = req;
2659 req->rsp = rsp;
9a347ff4 2660
8ae6d9c7
GM		 2661 if (IS_QLAFX00(ha)) {
2662 ha->rsp_q_map[0] = rsp;
2663 ha->req_q_map[0] = req;
2664 set_bit(0, ha->req_qid_map);
2665 set_bit(0, ha->rsp_qid_map);
2666 }
2667
08029990
AV		 2668 /* FWI2-capable only. */
2669 req->req_q_in = &ha->iobase->isp24.req_q_in;
2670 req->req_q_out = &ha->iobase->isp24.req_q_out;
2671 rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in;
2672 rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out;
f73cb695 2673 if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
08029990
AV		 2674 req->req_q_in = &ha->mqiobase->isp25mq.req_q_in;
2675 req->req_q_out = &ha->mqiobase->isp25mq.req_q_out;
2676 rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in;
2677 rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out;
17d98630
AC		 2678 }
2679
8ae6d9c7
GM		 2680 if (IS_QLAFX00(ha)) {
2681 req->req_q_in = &ha->iobase->ispfx00.req_q_in;
2682 req->req_q_out = &ha->iobase->ispfx00.req_q_out;
2683 rsp->rsp_q_in = &ha->iobase->ispfx00.rsp_q_in;
2684 rsp->rsp_q_out = &ha->iobase->ispfx00.rsp_q_out;
2685 }
2686
7ec0effd 2687 if (IS_P3P_TYPE(ha)) {
a9083016
GM		 2688 req->req_q_out = &ha->iobase->isp82.req_q_out[0];
2689 rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0];
2690 rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0];
2691 }
2692
7c3df132
SK		 2693 ql_dbg(ql_dbg_multiq, base_vha, 0xc009,
2694 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
2695 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
2696 ql_dbg(ql_dbg_multiq, base_vha, 0xc00a,
2697 "req->req_q_in=%p req->req_q_out=%p "
2698 "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
2699 req->req_q_in, req->req_q_out,
2700 rsp->rsp_q_in, rsp->rsp_q_out);
2701 ql_dbg(ql_dbg_init, base_vha, 0x003e,
2702 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
2703 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
2704 ql_dbg(ql_dbg_init, base_vha, 0x003f,
2705 "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
2706 req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out);
1da177e4 2707
8ae6d9c7 2708 if (ha->isp_ops->initialize_adapter(base_vha)) {
7c3df132
SK		 2709 ql_log(ql_log_fatal, base_vha, 0x00d6,
2710 "Failed to initialize adapter - Adapter flags %x.\n",
2711 base_vha->device_flags);
1da177e4 2712
a9083016
GM		 2713 if (IS_QLA82XX(ha)) {
2714 qla82xx_idc_lock(ha);
2715 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 2716 QLA8XXX_DEV_FAILED);
a9083016 2717 qla82xx_idc_unlock(ha);
7c3df132
SK		 2718 ql_log(ql_log_fatal, base_vha, 0x00d7,
2719 "HW State: FAILED.\n");
7ec0effd
AD		 2720 } else if (IS_QLA8044(ha)) {
2721 qla8044_idc_lock(ha);
2722 qla8044_wr_direct(base_vha,
2723 QLA8044_CRB_DEV_STATE_INDEX,
2724 QLA8XXX_DEV_FAILED);
2725 qla8044_idc_unlock(ha);
2726 ql_log(ql_log_fatal, base_vha, 0x0150,
2727 "HW State: FAILED.\n");
a9083016
GM		 2728 }
2729
a1541d5a 2730 ret = -ENODEV;
1da177e4
LT		 2731 goto probe_failed;
2732 }
2733
3b1bef64
CD		 2734 if (IS_QLAFX00(ha))
2735 host->can_queue = QLAFX00_MAX_CANQUEUE;
2736 else
2737 host->can_queue = req->num_outstanding_cmds - 10;
2738
2739 ql_dbg(ql_dbg_init, base_vha, 0x0032,
2740 "can_queue=%d, req=%p, mgmt_svr_loop_id=%d, sg_tablesize=%d.\n",
2741 host->can_queue, base_vha->req,
2742 base_vha->mgmt_svr_loop_id, host->sg_tablesize);
2743
7163ea81
AC		 2744 if (ha->mqenable) {
2745 if (qla25xx_setup_mode(base_vha)) {
7c3df132
SK		 2746 ql_log(ql_log_warn, base_vha, 0x00ec,
2747 "Failed to create queues, falling back to single queue mode.\n");
7163ea81
AC		 2748 goto que_init;
2749 }
2750 }
68ca949c 2751
cbc8eb67
AV		 2752 if (ha->flags.running_gold_fw)
2753 goto skip_dpc;
2754
1da177e4
LT		 2755 /*
2756 * Startup the kernel thread for this host adapter
2757 */
39a11240 2758 ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha,
7c3df132 2759 "%s_dpc", base_vha->host_str);
39a11240 2760 if (IS_ERR(ha->dpc_thread)) {
7c3df132
SK		 2761 ql_log(ql_log_fatal, base_vha, 0x00ed,
2762 "Failed to start DPC thread.\n");
39a11240 2763 ret = PTR_ERR(ha->dpc_thread);
1da177e4
LT		 2764 goto probe_failed;
2765 }
7c3df132
SK		 2766 ql_dbg(ql_dbg_init, base_vha, 0x00ee,
2767 "DPC thread started successfully.\n");
1da177e4 2768
2d70c103
NB		 2769 /*
2770 * If we're not coming up in initiator mode, we might sit for
2771 * a while without waking up the dpc thread, which leads to a
2772 * stuck process warning. So just kick the dpc once here and
2773 * let the kthread start (and go back to sleep in qla2x00_do_dpc).
2774 */
2775 qla2xxx_wake_dpc(base_vha);
2776
f3ddac19
CD		 2777 INIT_WORK(&ha->board_disable, qla2x00_disable_board_on_pci_error);
2778
81178772
SK		 2779 if (IS_QLA8031(ha) || IS_MCTP_CAPABLE(ha)) {
2780 sprintf(wq_name, "qla2xxx_%lu_dpc_lp_wq", base_vha->host_no);
2781 ha->dpc_lp_wq = create_singlethread_workqueue(wq_name);
2782 INIT_WORK(&ha->idc_aen, qla83xx_service_idc_aen);
2783
2784 sprintf(wq_name, "qla2xxx_%lu_dpc_hp_wq", base_vha->host_no);
2785 ha->dpc_hp_wq = create_singlethread_workqueue(wq_name);
2786 INIT_WORK(&ha->nic_core_reset, qla83xx_nic_core_reset_work);
2787 INIT_WORK(&ha->idc_state_handler,
2788 qla83xx_idc_state_handler_work);
2789 INIT_WORK(&ha->nic_core_unrecoverable,
2790 qla83xx_nic_core_unrecoverable_work);
2791 }
2792
cbc8eb67 2793skip_dpc:
e315cd28
AC		 2794 list_add_tail(&base_vha->list, &ha->vp_list);
2795 base_vha->host->irq = ha->pdev->irq;
1da177e4
LT		 2796
2797 /* Initialized the timer */
e315cd28 2798 qla2x00_start_timer(base_vha, qla2x00_timer, WATCH_INTERVAL);
7c3df132
SK		 2799 ql_dbg(ql_dbg_init, base_vha, 0x00ef,
2800 "Started qla2x00_timer with "
2801 "interval=%d.\n", WATCH_INTERVAL);
2802 ql_dbg(ql_dbg_init, base_vha, 0x00f0,
2803 "Detected hba at address=%p.\n",
2804 ha);
d19044c3 2805
e02587d7 2806 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) {
bad75002 2807 if (ha->fw_attributes & BIT_4) {
9e522cd8 2808 int prot = 0, guard;
bad75002 2809 base_vha->flags.difdix_supported = 1;
7c3df132
SK		 2810 ql_dbg(ql_dbg_init, base_vha, 0x00f1,
2811 "Registering for DIF/DIX type 1 and 3 protection.\n");
8cb2049c
AE		 2812 if (ql2xenabledif == 1)
2813 prot = SHOST_DIX_TYPE0_PROTECTION;
bad75002 2814 scsi_host_set_prot(host,
8cb2049c 2815 prot | SHOST_DIF_TYPE1_PROTECTION
0c470874 2816 | SHOST_DIF_TYPE2_PROTECTION
bad75002
AE		 2817 | SHOST_DIF_TYPE3_PROTECTION
2818 | SHOST_DIX_TYPE1_PROTECTION
0c470874 2819 | SHOST_DIX_TYPE2_PROTECTION
bad75002 2820 | SHOST_DIX_TYPE3_PROTECTION);
9e522cd8
AE		 2821
2822 guard = SHOST_DIX_GUARD_CRC;
2823
2824 if (IS_PI_IPGUARD_CAPABLE(ha) &&
2825 (ql2xenabledif > 1 || IS_PI_DIFB_DIX0_CAPABLE(ha)))
2826 guard |= SHOST_DIX_GUARD_IP;
2827
2828 scsi_host_set_guard(host, guard);
bad75002
AE		 2829 } else
2830 base_vha->flags.difdix_supported = 0;
2831 }
2832
a9083016
GM		 2833 ha->isp_ops->enable_intrs(ha);
2834
1fe19ee4
AB		 2835 if (IS_QLAFX00(ha)) {
2836 ret = qlafx00_fx_disc(base_vha,
2837 &base_vha->hw->mr.fcport, FXDISC_GET_CONFIG_INFO);
2838 host->sg_tablesize = (ha->mr.extended_io_enabled) ?
2839 QLA_SG_ALL : 128;
2840 }
2841
a1541d5a
AV		 2842 ret = scsi_add_host(host, &pdev->dev);
2843 if (ret)
2844 goto probe_failed;
2845
1486400f
MR		 2846 base_vha->flags.init_done = 1;
2847 base_vha->flags.online = 1;
edaa5c74 2848 ha->prev_minidump_failed = 0;
1486400f 2849
7c3df132
SK		 2850 ql_dbg(ql_dbg_init, base_vha, 0x00f2,
2851 "Init done and hba is online.\n");
2852
2d70c103
NB		 2853 if (qla_ini_mode_enabled(base_vha))
2854 scsi_scan_host(host);
2855 else
2856 ql_dbg(ql_dbg_init, base_vha, 0x0122,
2857 "skipping scsi_scan_host() for non-initiator port\n");
1e99e33a 2858
e315cd28 2859 qla2x00_alloc_sysfs_attr(base_vha);
a1541d5a 2860
8ae6d9c7 2861 if (IS_QLAFX00(ha)) {
8ae6d9c7
GM		 2862 ret = qlafx00_fx_disc(base_vha,
2863 &base_vha->hw->mr.fcport, FXDISC_GET_PORT_INFO);
2864
2865 /* Register system information */
2866 ret = qlafx00_fx_disc(base_vha,
2867 &base_vha->hw->mr.fcport, FXDISC_REG_HOST_INFO);
2868 }
2869
e315cd28 2870 qla2x00_init_host_attr(base_vha);
a1541d5a 2871
e315cd28 2872 qla2x00_dfs_setup(base_vha);
df613b96 2873
03eb912a
AB		 2874 ql_log(ql_log_info, base_vha, 0x00fb,
2875 "QLogic %s - %s.\n", ha->model_number, ha->model_desc);
7c3df132
SK		 2876 ql_log(ql_log_info, base_vha, 0x00fc,
2877 "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n",
2878 pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info),
2879 pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-',
2880 base_vha->host_no,
df57caba 2881 ha->isp_ops->fw_version_str(base_vha, fw_str, sizeof(fw_str)));
1da177e4 2882
2d70c103
NB		 2883 qlt_add_target(ha, base_vha);
2884
6b383979 2885 clear_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags);
1da177e4
LT		 2886 return 0;
2887
6e9f21f3 2888probe_init_failed:
2afa19a9 2889 qla2x00_free_req_que(ha, req);
9a347ff4
CD		 2890 ha->req_q_map[0] = NULL;
2891 clear_bit(0, ha->req_qid_map);
2afa19a9 2892 qla2x00_free_rsp_que(ha, rsp);
9a347ff4
CD		 2893 ha->rsp_q_map[0] = NULL;
2894 clear_bit(0, ha->rsp_qid_map);
2afa19a9 2895 ha->max_req_queues = ha->max_rsp_queues = 0;
6e9f21f3 2896
1da177e4 2897probe_failed:
b9978769
AV		 2898 if (base_vha->timer_active)
2899 qla2x00_stop_timer(base_vha);
2900 base_vha->flags.online = 0;
2901 if (ha->dpc_thread) {
2902 struct task_struct *t = ha->dpc_thread;
2903
2904 ha->dpc_thread = NULL;
2905 kthread_stop(t);
2906 }
2907
e315cd28 2908 qla2x00_free_device(base_vha);
1da177e4 2909
e315cd28 2910 scsi_host_put(base_vha->host);
1da177e4 2911
e315cd28 2912probe_hw_failed:
1a2fbf18
JL		 2913 qla2x00_clear_drv_active(ha);
2914
0a63ad12 2915iospace_config_failed:
7ec0effd 2916 if (IS_P3P_TYPE(ha)) {
0a63ad12 2917 if (!ha->nx_pcibase)
f73cb695 2918 iounmap((device_reg_t *)ha->nx_pcibase);
a9083016 2919 if (!ql2xdbwr)
f73cb695 2920 iounmap((device_reg_t *)ha->nxdb_wr_ptr);
a9083016
GM		 2921 } else {
2922 if (ha->iobase)
2923 iounmap(ha->iobase);
8ae6d9c7
GM		 2924 if (ha->cregbase)
2925 iounmap(ha->cregbase);
a9083016 2926 }
e315cd28
AC		 2927 pci_release_selected_regions(ha->pdev, ha->bars);
2928 kfree(ha);
2929 ha = NULL;
1da177e4 2930
a1541d5a 2931probe_out:
e315cd28 2932 pci_disable_device(pdev);
a1541d5a 2933 return ret;
1da177e4 2934}
1da177e4 2935
e30d1756
MI		 2936static void
2937qla2x00_shutdown(struct pci_dev *pdev)
2938{
2939 scsi_qla_host_t *vha;
2940 struct qla_hw_data *ha;
2941
552f3f9a
MI		 2942 if (!atomic_read(&pdev->enable_cnt))
2943 return;
2944
e30d1756
MI		 2945 vha = pci_get_drvdata(pdev);
2946 ha = vha->hw;
2947
42479343
AB		 2948 /* Notify ISPFX00 firmware */
2949 if (IS_QLAFX00(ha))
2950 qlafx00_driver_shutdown(vha, 20);
2951
e30d1756
MI		 2952 /* Turn-off FCE trace */
2953 if (ha->flags.fce_enabled) {
2954 qla2x00_disable_fce_trace(vha, NULL, NULL);
2955 ha->flags.fce_enabled = 0;
2956 }
2957
2958 /* Turn-off EFT trace */
2959 if (ha->eft)
2960 qla2x00_disable_eft_trace(vha);
2961
2962 /* Stop currently executing firmware. */
2963 qla2x00_try_to_stop_firmware(vha);
2964
2965 /* Turn adapter off line */
2966 vha->flags.online = 0;
2967
2968 /* turn-off interrupts on the card */
2969 if (ha->interrupts_on) {
2970 vha->flags.init_done = 0;
2971 ha->isp_ops->disable_intrs(ha);
2972 }
2973
2974 qla2x00_free_irqs(vha);
2975
2976 qla2x00_free_fw_dump(ha);
61d41f61
CD		 2977
2978 pci_disable_pcie_error_reporting(pdev);
2979 pci_disable_device(pdev);
e30d1756
MI		 2980}
2981
fe1b806f 2982/* Deletes all the virtual ports for a given ha */
4c993f76 2983static void
fe1b806f 2984qla2x00_delete_all_vps(struct qla_hw_data *ha, scsi_qla_host_t *base_vha)
1da177e4 2985{
fe1b806f 2986 scsi_qla_host_t *vha;
feafb7b1 2987 unsigned long flags;
e315cd28 2988
43ebf16d
AE		 2989 mutex_lock(&ha->vport_lock);
2990 while (ha->cur_vport_count) {
43ebf16d 2991 spin_lock_irqsave(&ha->vport_slock, flags);
feafb7b1 2992
43ebf16d
AE		 2993 BUG_ON(base_vha->list.next == &ha->vp_list);
2994 /* This assumes first entry in ha->vp_list is always base vha */
2995 vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list);
52c82823 2996 scsi_host_get(vha->host);
feafb7b1 2997
43ebf16d
AE		 2998 spin_unlock_irqrestore(&ha->vport_slock, flags);
2999 mutex_unlock(&ha->vport_lock);
3000
3001 fc_vport_terminate(vha->fc_vport);
3002 scsi_host_put(vha->host);
feafb7b1 3003
43ebf16d 3004 mutex_lock(&ha->vport_lock);
e315cd28 3005 }
43ebf16d 3006 mutex_unlock(&ha->vport_lock);
fe1b806f 3007}
1da177e4 3008
fe1b806f
CD		 3009/* Stops all deferred work threads */
3010static void
3011qla2x00_destroy_deferred_work(struct qla_hw_data *ha)
3012{
68ca949c
AC		 3013 /* Flush the work queue and remove it */
3014 if (ha->wq) {
3015 flush_workqueue(ha->wq);
3016 destroy_workqueue(ha->wq);
3017 ha->wq = NULL;
3018 }
3019
7d613ac6
SV		 3020 /* Cancel all work and destroy DPC workqueues */
3021 if (ha->dpc_lp_wq) {
3022 cancel_work_sync(&ha->idc_aen);
3023 destroy_workqueue(ha->dpc_lp_wq);
3024 ha->dpc_lp_wq = NULL;
3025 }
3026
3027 if (ha->dpc_hp_wq) {
3028 cancel_work_sync(&ha->nic_core_reset);
3029 cancel_work_sync(&ha->idc_state_handler);
3030 cancel_work_sync(&ha->nic_core_unrecoverable);
3031 destroy_workqueue(ha->dpc_hp_wq);
3032 ha->dpc_hp_wq = NULL;
3033 }
3034
b9978769
AV		 3035 /* Kill the kernel thread for this host */
3036 if (ha->dpc_thread) {
3037 struct task_struct *t = ha->dpc_thread;
3038
3039 /*
3040 * qla2xxx_wake_dpc checks for ->dpc_thread
3041 * so we need to zero it out.
3042 */
3043 ha->dpc_thread = NULL;
3044 kthread_stop(t);
3045 }
fe1b806f 3046}
1da177e4 3047
fe1b806f
CD		 3048static void
3049qla2x00_unmap_iobases(struct qla_hw_data *ha)
3050{
a9083016 3051 if (IS_QLA82XX(ha)) {
b963752f 3052
f73cb695 3053 iounmap((device_reg_t *)ha->nx_pcibase);
a9083016 3054 if (!ql2xdbwr)
f73cb695 3055 iounmap((device_reg_t *)ha->nxdb_wr_ptr);
a9083016
GM		 3056 } else {
3057 if (ha->iobase)
3058 iounmap(ha->iobase);
1da177e4 3059
8ae6d9c7
GM		 3060 if (ha->cregbase)
3061 iounmap(ha->cregbase);
3062
a9083016
GM		 3063 if (ha->mqiobase)
3064 iounmap(ha->mqiobase);
6246b8a1 3065
f73cb695 3066 if ((IS_QLA83XX(ha) || IS_QLA27XX(ha)) && ha->msixbase)
6246b8a1 3067 iounmap(ha->msixbase);
a9083016 3068 }
fe1b806f
CD		 3069}
3070
3071static void
db7157d4 3072qla2x00_clear_drv_active(struct qla_hw_data *ha)
fe1b806f 3073{
fe1b806f
CD		 3074 if (IS_QLA8044(ha)) {
3075 qla8044_idc_lock(ha);
c41afc9a 3076 qla8044_clear_drv_active(ha);
fe1b806f
CD		 3077 qla8044_idc_unlock(ha);
3078 } else if (IS_QLA82XX(ha)) {
3079 qla82xx_idc_lock(ha);
3080 qla82xx_clear_drv_active(ha);
3081 qla82xx_idc_unlock(ha);
3082 }
3083}
3084
3085static void
3086qla2x00_remove_one(struct pci_dev *pdev)
3087{
3088 scsi_qla_host_t *base_vha;
3089 struct qla_hw_data *ha;
3090
beb9e315
JL		 3091 base_vha = pci_get_drvdata(pdev);
3092 ha = base_vha->hw;
3093
3094 /* Indicate device removal to prevent future board_disable and wait
3095 * until any pending board_disable has completed. */
3096 set_bit(PFLG_DRIVER_REMOVING, &base_vha->pci_flags);
3097 cancel_work_sync(&ha->board_disable);
3098
fe1b806f 3099 /*
beb9e315
JL		 3100 * If the PCI device is disabled then there was a PCI-disconnect and
3101 * qla2x00_disable_board_on_pci_error has taken care of most of the
3102 * resources.
fe1b806f 3103 */
beb9e315
JL		 3104 if (!atomic_read(&pdev->enable_cnt)) {
3105 scsi_host_put(base_vha->host);
3106 kfree(ha);
3107 pci_set_drvdata(pdev, NULL);
fe1b806f 3108 return;
beb9e315 3109 }
fe1b806f 3110
638a1a01
SC		 3111 qla2x00_wait_for_hba_ready(base_vha);
3112
fe1b806f
CD		 3113 set_bit(UNLOADING, &base_vha->dpc_flags);
3114
3115 if (IS_QLAFX00(ha))
3116 qlafx00_driver_shutdown(base_vha, 20);
3117
3118 qla2x00_delete_all_vps(ha, base_vha);
3119
3120 if (IS_QLA8031(ha)) {
3121 ql_dbg(ql_dbg_p3p, base_vha, 0xb07e,
3122 "Clearing fcoe driver presence.\n");
3123 if (qla83xx_clear_drv_presence(base_vha) != QLA_SUCCESS)
3124 ql_dbg(ql_dbg_p3p, base_vha, 0xb079,
3125 "Error while clearing DRV-Presence.\n");
3126 }
3127
3128 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
3129
3130 qla2x00_dfs_remove(base_vha);
3131
3132 qla84xx_put_chip(base_vha);
3133
2d5a4c34
HM		 3134 /* Laser should be disabled only for ISP2031 */
3135 if (IS_QLA2031(ha))
3136 qla83xx_disable_laser(base_vha);
3137
fe1b806f
CD		 3138 /* Disable timer */
3139 if (base_vha->timer_active)
3140 qla2x00_stop_timer(base_vha);
3141
3142 base_vha->flags.online = 0;
3143
b0d6cabd
HM		 3144 /* free DMA memory */
3145 if (ha->exlogin_buf)
3146 qla2x00_free_exlogin_buffer(ha);
3147
2f56a7f1
HM		 3148 /* free DMA memory */
3149 if (ha->exchoffld_buf)
3150 qla2x00_free_exchoffld_buffer(ha);
3151
fe1b806f
CD		 3152 qla2x00_destroy_deferred_work(ha);
3153
3154 qlt_remove_target(ha, base_vha);
3155
3156 qla2x00_free_sysfs_attr(base_vha, true);
3157
3158 fc_remove_host(base_vha->host);
3159
3160 scsi_remove_host(base_vha->host);
3161
3162 qla2x00_free_device(base_vha);
3163
db7157d4 3164 qla2x00_clear_drv_active(ha);
fe1b806f 3165
d2749ffa
AE		 3166 scsi_host_put(base_vha->host);
3167
fe1b806f 3168 qla2x00_unmap_iobases(ha);
73208dfd 3169
e315cd28
AC		 3170 pci_release_selected_regions(ha->pdev, ha->bars);
3171 kfree(ha);
3172 ha = NULL;
1da177e4 3173
90a86fc0
JC		 3174 pci_disable_pcie_error_reporting(pdev);
3175
665db93b 3176 pci_disable_device(pdev);
1da177e4 3177}
1da177e4
LT		 3178
3179static void
e315cd28 3180qla2x00_free_device(scsi_qla_host_t *vha)
1da177e4 3181{
e315cd28 3182 struct qla_hw_data *ha = vha->hw;
1da177e4 3183
85880801
AV		 3184 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
3185
3186 /* Disable timer */
3187 if (vha->timer_active)
3188 qla2x00_stop_timer(vha);
3189
2afa19a9 3190 qla25xx_delete_queues(vha);
fe1b806f 3191
df613b96 3192 if (ha->flags.fce_enabled)
e315cd28 3193 qla2x00_disable_fce_trace(vha, NULL, NULL);
df613b96 3194
a7a167bf 3195 if (ha->eft)
e315cd28 3196 qla2x00_disable_eft_trace(vha);
a7a167bf 3197
f6ef3b18 3198 /* Stop currently executing firmware. */
e315cd28 3199 qla2x00_try_to_stop_firmware(vha);
1da177e4 3200
85880801
AV		 3201 vha->flags.online = 0;
3202
f6ef3b18 3203 /* turn-off interrupts on the card */
a9083016
GM		 3204 if (ha->interrupts_on) {
3205 vha->flags.init_done = 0;
fd34f556 3206 ha->isp_ops->disable_intrs(ha);
a9083016 3207 }
f6ef3b18 3208
e315cd28 3209 qla2x00_free_irqs(vha);
1da177e4 3210
8867048b
CD		 3211 qla2x00_free_fcports(vha);
3212
e315cd28 3213 qla2x00_mem_free(ha);
73208dfd 3214
08de2844
GM		 3215 qla82xx_md_free(vha);
3216
73208dfd 3217 qla2x00_free_queues(ha);
1da177e4
LT		 3218}
3219
8867048b
CD		 3220void qla2x00_free_fcports(struct scsi_qla_host *vha)
3221{
3222 fc_port_t *fcport, *tfcport;
3223
3224 list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list) {
3225 list_del(&fcport->list);
5f16b331 3226 qla2x00_clear_loop_id(fcport);
8867048b
CD		 3227 kfree(fcport);
3228 fcport = NULL;
3229 }
3230}
3231
d97994dc 3232static inline void
e315cd28 3233qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport,
d97994dc 3234 int defer)
3235{
d97994dc 3236 struct fc_rport *rport;
67becc00 3237 scsi_qla_host_t *base_vha;
044d78e1 3238 unsigned long flags;
d97994dc 3239
3240 if (!fcport->rport)
3241 return;
3242
3243 rport = fcport->rport;
3244 if (defer) {
67becc00 3245 base_vha = pci_get_drvdata(vha->hw->pdev);
044d78e1 3246 spin_lock_irqsave(vha->host->host_lock, flags);
d97994dc 3247 fcport->drport = rport;
044d78e1 3248 spin_unlock_irqrestore(vha->host->host_lock, flags);
df673274 3249 qlt_do_generation_tick(vha, &base_vha->total_fcport_update_gen);
67becc00
AV		 3250 set_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags);
3251 qla2xxx_wake_dpc(base_vha);
2d70c103 3252 } else {
df673274 3253 int now;
d20ed91b
AP		 3254 if (rport)
3255 fc_remote_port_delete(rport);
df673274
AP		 3256 qlt_do_generation_tick(vha, &now);
3257 qlt_fc_port_deleted(vha, fcport, now);
2d70c103 3258 }
d97994dc 3259}
3260
1da177e4
LT		 3261/*
3262 * qla2x00_mark_device_lost Updates fcport state when device goes offline.
3263 *
3264 * Input: ha = adapter block pointer. fcport = port structure pointer.
3265 *
3266 * Return: None.
3267 *
3268 * Context:
3269 */
e315cd28 3270void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport,
d97994dc 3271 int do_login, int defer)
1da177e4 3272{
8ae6d9c7
GM		 3273 if (IS_QLAFX00(vha->hw)) {
3274 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
3275 qla2x00_schedule_rport_del(vha, fcport, defer);
3276 return;
3277 }
3278
2c3dfe3f 3279 if (atomic_read(&fcport->state) == FCS_ONLINE &&
c6d39e23 3280 vha->vp_idx == fcport->vha->vp_idx) {
ec426e10 3281 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
e315cd28
AC		 3282 qla2x00_schedule_rport_del(vha, fcport, defer);
3283 }
fa2a1ce5 3284 /*
1da177e4
LT		 3285 * We may need to retry the login, so don't change the state of the
3286 * port but do the retries.
3287 */
3288 if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD)
ec426e10 3289 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
1da177e4
LT		 3290
3291 if (!do_login)
3292 return;
3293
a1d0285e
AE		 3294 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
3295
1da177e4 3296 if (fcport->login_retry == 0) {
e315cd28 3297 fcport->login_retry = vha->hw->login_retry_count;
1da177e4 3298
7c3df132 3299 ql_dbg(ql_dbg_disc, vha, 0x2067,
7b833558
OK		 3300 "Port login retry %8phN, id = 0x%04x retry cnt=%d.\n",
3301 fcport->port_name, fcport->loop_id, fcport->login_retry);
1da177e4
LT		 3302 }
3303}
3304
3305/*
3306 * qla2x00_mark_all_devices_lost
3307 * Updates fcport state when device goes offline.
3308 *
3309 * Input:
3310 * ha = adapter block pointer.
3311 * fcport = port structure pointer.
3312 *
3313 * Return:
3314 * None.
3315 *
3316 * Context:
3317 */
3318void
e315cd28 3319qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha, int defer)
1da177e4
LT		 3320{
3321 fc_port_t *fcport;
3322
e315cd28 3323 list_for_each_entry(fcport, &vha->vp_fcports, list) {
c6d39e23 3324 if (vha->vp_idx != 0 && vha->vp_idx != fcport->vha->vp_idx)
1da177e4 3325 continue;
0d6e61bc 3326
1da177e4
LT		 3327 /*
3328 * No point in marking the device as lost, if the device is
3329 * already DEAD.
3330 */
3331 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD)
3332 continue;
e315cd28 3333 if (atomic_read(&fcport->state) == FCS_ONLINE) {
ec426e10 3334 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
0d6e61bc
AV		 3335 if (defer)
3336 qla2x00_schedule_rport_del(vha, fcport, defer);
c6d39e23 3337 else if (vha->vp_idx == fcport->vha->vp_idx)
0d6e61bc
AV		 3338 qla2x00_schedule_rport_del(vha, fcport, defer);
3339 }
1da177e4
LT		 3340 }
3341}
3342
3343/*
3344* qla2x00_mem_alloc
3345* Allocates adapter memory.
3346*
3347* Returns:
3348* 0 = success.
e8711085 3349* !0 = failure.
1da177e4 3350*/
e8711085 3351static int
73208dfd
AC		 3352qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len,
3353 struct req_que **req, struct rsp_que **rsp)
1da177e4
LT		 3354{
3355 char name[16];
1da177e4 3356
e8711085 3357 ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size,
e315cd28 3358 &ha->init_cb_dma, GFP_KERNEL);
e8711085 3359 if (!ha->init_cb)
e315cd28 3360 goto fail;
e8711085 3361
2d70c103
NB		 3362 if (qlt_mem_alloc(ha) < 0)
3363 goto fail_free_init_cb;
3364
642ef983
CD		 3365 ha->gid_list = dma_alloc_coherent(&ha->pdev->dev,
3366 qla2x00_gid_list_size(ha), &ha->gid_list_dma, GFP_KERNEL);
e315cd28 3367 if (!ha->gid_list)
2d70c103 3368 goto fail_free_tgt_mem;
1da177e4 3369
e8711085
AV		 3370 ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep);
3371 if (!ha->srb_mempool)
e315cd28 3372 goto fail_free_gid_list;
e8711085 3373
7ec0effd 3374 if (IS_P3P_TYPE(ha)) {
a9083016
GM		 3375 /* Allocate cache for CT6 Ctx. */
3376 if (!ctx_cachep) {
3377 ctx_cachep = kmem_cache_create("qla2xxx_ctx",
3378 sizeof(struct ct6_dsd), 0,
3379 SLAB_HWCACHE_ALIGN, NULL);
3380 if (!ctx_cachep)
3381 goto fail_free_gid_list;
3382 }
3383 ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ,
3384 ctx_cachep);
3385 if (!ha->ctx_mempool)
3386 goto fail_free_srb_mempool;
7c3df132
SK		 3387 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021,
3388 "ctx_cachep=%p ctx_mempool=%p.\n",
3389 ctx_cachep, ha->ctx_mempool);
a9083016
GM		 3390 }
3391
e8711085
AV		 3392 /* Get memory for cached NVRAM */
3393 ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL);
3394 if (!ha->nvram)
a9083016 3395 goto fail_free_ctx_mempool;
e8711085 3396
e315cd28
AC		 3397 snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME,
3398 ha->pdev->device);
3399 ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3400 DMA_POOL_SIZE, 8, 0);
3401 if (!ha->s_dma_pool)
3402 goto fail_free_nvram;
3403
7c3df132
SK		 3404 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022,
3405 "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n",
3406 ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool);
3407
7ec0effd 3408 if (IS_P3P_TYPE(ha) || ql2xenabledif) {
a9083016
GM		 3409 ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3410 DSD_LIST_DMA_POOL_SIZE, 8, 0);
3411 if (!ha->dl_dma_pool) {
7c3df132
SK		 3412 ql_log_pci(ql_log_fatal, ha->pdev, 0x0023,
3413 "Failed to allocate memory for dl_dma_pool.\n");
a9083016
GM		 3414 goto fail_s_dma_pool;
3415 }
3416
3417 ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3418 FCP_CMND_DMA_POOL_SIZE, 8, 0);
3419 if (!ha->fcp_cmnd_dma_pool) {
7c3df132
SK		 3420 ql_log_pci(ql_log_fatal, ha->pdev, 0x0024,
3421 "Failed to allocate memory for fcp_cmnd_dma_pool.\n");
a9083016
GM		 3422 goto fail_dl_dma_pool;
3423 }
7c3df132
SK		 3424 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025,
3425 "dl_dma_pool=%p fcp_cmnd_dma_pool=%p.\n",
3426 ha->dl_dma_pool, ha->fcp_cmnd_dma_pool);
a9083016
GM		 3427 }
3428
e8711085
AV		 3429 /* Allocate memory for SNS commands */
3430 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
e315cd28 3431 /* Get consistent memory allocated for SNS commands */
e8711085 3432 ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev,
e315cd28 3433 sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL);
e8711085 3434 if (!ha->sns_cmd)
e315cd28 3435 goto fail_dma_pool;
7c3df132 3436 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026,
d8424f68 3437 "sns_cmd: %p.\n", ha->sns_cmd);
e8711085 3438 } else {
e315cd28 3439 /* Get consistent memory allocated for MS IOCB */
e8711085 3440 ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
e315cd28 3441 &ha->ms_iocb_dma);
e8711085 3442 if (!ha->ms_iocb)
e315cd28
AC		 3443 goto fail_dma_pool;
3444 /* Get consistent memory allocated for CT SNS commands */
e8711085 3445 ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev,
e315cd28 3446 sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL);
e8711085
AV		 3447 if (!ha->ct_sns)
3448 goto fail_free_ms_iocb;
7c3df132
SK		 3449 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027,
3450 "ms_iocb=%p ct_sns=%p.\n",
3451 ha->ms_iocb, ha->ct_sns);
1da177e4
LT		 3452 }
3453
e315cd28 3454 /* Allocate memory for request ring */
73208dfd
AC		 3455 *req = kzalloc(sizeof(struct req_que), GFP_KERNEL);
3456 if (!*req) {
7c3df132
SK		 3457 ql_log_pci(ql_log_fatal, ha->pdev, 0x0028,
3458 "Failed to allocate memory for req.\n");
e315cd28
AC		 3459 goto fail_req;
3460 }
73208dfd
AC		 3461 (*req)->length = req_len;
3462 (*req)->ring = dma_alloc_coherent(&ha->pdev->dev,
3463 ((*req)->length + 1) * sizeof(request_t),
3464 &(*req)->dma, GFP_KERNEL);
3465 if (!(*req)->ring) {
7c3df132
SK		 3466 ql_log_pci(ql_log_fatal, ha->pdev, 0x0029,
3467 "Failed to allocate memory for req_ring.\n");
e315cd28
AC		 3468 goto fail_req_ring;
3469 }
3470 /* Allocate memory for response ring */
73208dfd
AC		 3471 *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL);
3472 if (!*rsp) {
7c3df132
SK		 3473 ql_log_pci(ql_log_fatal, ha->pdev, 0x002a,
3474 "Failed to allocate memory for rsp.\n");
e315cd28
AC		 3475 goto fail_rsp;
3476 }
73208dfd
AC		 3477 (*rsp)->hw = ha;
3478 (*rsp)->length = rsp_len;
3479 (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev,
3480 ((*rsp)->length + 1) * sizeof(response_t),
3481 &(*rsp)->dma, GFP_KERNEL);
3482 if (!(*rsp)->ring) {
7c3df132
SK		 3483 ql_log_pci(ql_log_fatal, ha->pdev, 0x002b,
3484 "Failed to allocate memory for rsp_ring.\n");
e315cd28
AC		 3485 goto fail_rsp_ring;
3486 }
73208dfd
AC		 3487 (*req)->rsp = *rsp;
3488 (*rsp)->req = *req;
7c3df132
SK		 3489 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c,
3490 "req=%p req->length=%d req->ring=%p rsp=%p "
3491 "rsp->length=%d rsp->ring=%p.\n",
3492 *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length,
3493 (*rsp)->ring);
73208dfd
AC		 3494 /* Allocate memory for NVRAM data for vports */
3495 if (ha->nvram_npiv_size) {
3496 ha->npiv_info = kzalloc(sizeof(struct qla_npiv_entry) *
7c3df132 3497 ha->nvram_npiv_size, GFP_KERNEL);
73208dfd 3498 if (!ha->npiv_info) {
7c3df132
SK		 3499 ql_log_pci(ql_log_fatal, ha->pdev, 0x002d,
3500 "Failed to allocate memory for npiv_info.\n");
73208dfd
AC		 3501 goto fail_npiv_info;
3502 }
3503 } else
3504 ha->npiv_info = NULL;
e8711085 3505
b64b0e8f 3506 /* Get consistent memory allocated for EX-INIT-CB. */
f73cb695 3507 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha)) {
b64b0e8f
AV		 3508 ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
3509 &ha->ex_init_cb_dma);
3510 if (!ha->ex_init_cb)
3511 goto fail_ex_init_cb;
7c3df132
SK		 3512 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e,
3513 "ex_init_cb=%p.\n", ha->ex_init_cb);
b64b0e8f
AV		 3514 }
3515
a9083016
GM		 3516 INIT_LIST_HEAD(&ha->gbl_dsd_list);
3517
5ff1d584
AV		 3518 /* Get consistent memory allocated for Async Port-Database. */
3519 if (!IS_FWI2_CAPABLE(ha)) {
3520 ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
3521 &ha->async_pd_dma);
3522 if (!ha->async_pd)
3523 goto fail_async_pd;
7c3df132
SK		 3524 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f,
3525 "async_pd=%p.\n", ha->async_pd);
5ff1d584
AV		 3526 }
3527
e315cd28 3528 INIT_LIST_HEAD(&ha->vp_list);
5f16b331
CD		 3529
3530 /* Allocate memory for our loop_id bitmap */
3531 ha->loop_id_map = kzalloc(BITS_TO_LONGS(LOOPID_MAP_SIZE) * sizeof(long),
3532 GFP_KERNEL);
3533 if (!ha->loop_id_map)
3534 goto fail_async_pd;
3535 else {
3536 qla2x00_set_reserved_loop_ids(ha);
3537 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0123,
b2a72ec3 3538 "loop_id_map=%p.\n", ha->loop_id_map);
5f16b331
CD		 3539 }
3540
b2a72ec3 3541 return 0;
e315cd28 3542
5ff1d584
AV		 3543fail_async_pd:
3544 dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma);
b64b0e8f
AV		 3545fail_ex_init_cb:
3546 kfree(ha->npiv_info);
73208dfd
AC		 3547fail_npiv_info:
3548 dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) *
3549 sizeof(response_t), (*rsp)->ring, (*rsp)->dma);
3550 (*rsp)->ring = NULL;
3551 (*rsp)->dma = 0;
e315cd28 3552fail_rsp_ring:
73208dfd 3553 kfree(*rsp);
e315cd28 3554fail_rsp:
73208dfd
AC		 3555 dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) *
3556 sizeof(request_t), (*req)->ring, (*req)->dma);
3557 (*req)->ring = NULL;
3558 (*req)->dma = 0;
e315cd28 3559fail_req_ring:
73208dfd 3560 kfree(*req);
e315cd28
AC		 3561fail_req:
3562 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
3563 ha->ct_sns, ha->ct_sns_dma);
3564 ha->ct_sns = NULL;
3565 ha->ct_sns_dma = 0;
e8711085
AV		 3566fail_free_ms_iocb:
3567 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
3568 ha->ms_iocb = NULL;
3569 ha->ms_iocb_dma = 0;
e315cd28 3570fail_dma_pool:
bad75002 3571 if (IS_QLA82XX(ha) || ql2xenabledif) {
a9083016
GM		 3572 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
3573 ha->fcp_cmnd_dma_pool = NULL;
3574 }
3575fail_dl_dma_pool:
bad75002 3576 if (IS_QLA82XX(ha) || ql2xenabledif) {
a9083016
GM		 3577 dma_pool_destroy(ha->dl_dma_pool);
3578 ha->dl_dma_pool = NULL;
3579 }
3580fail_s_dma_pool:
e315cd28
AC		 3581 dma_pool_destroy(ha->s_dma_pool);
3582 ha->s_dma_pool = NULL;
e8711085
AV		 3583fail_free_nvram:
3584 kfree(ha->nvram);
3585 ha->nvram = NULL;
a9083016
GM		 3586fail_free_ctx_mempool:
3587 mempool_destroy(ha->ctx_mempool);
3588 ha->ctx_mempool = NULL;
e8711085
AV		 3589fail_free_srb_mempool:
3590 mempool_destroy(ha->srb_mempool);
3591 ha->srb_mempool = NULL;
e8711085 3592fail_free_gid_list:
642ef983
CD		 3593 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
3594 ha->gid_list,
e315cd28 3595 ha->gid_list_dma);
e8711085
AV		 3596 ha->gid_list = NULL;
3597 ha->gid_list_dma = 0;
2d70c103
NB		 3598fail_free_tgt_mem:
3599 qlt_mem_free(ha);
e315cd28
AC		 3600fail_free_init_cb:
3601 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb,
3602 ha->init_cb_dma);
3603 ha->init_cb = NULL;
3604 ha->init_cb_dma = 0;
e8711085 3605fail:
7c3df132
SK		 3606 ql_log(ql_log_fatal, NULL, 0x0030,
3607 "Memory allocation failure.\n");
e8711085 3608 return -ENOMEM;
1da177e4
LT		 3609}
3610
b0d6cabd
HM		 3611int
3612qla2x00_set_exlogins_buffer(scsi_qla_host_t *vha)
3613{
3614 int rval;
3615 uint16_t size, max_cnt, temp;
3616 struct qla_hw_data *ha = vha->hw;
3617
3618 /* Return if we don't need to alloacate any extended logins */
3619 if (!ql2xexlogins)
3620 return QLA_SUCCESS;
3621
3622 ql_log(ql_log_info, vha, 0xd021, "EXLOGIN count: %d.\n", ql2xexlogins);
3623 max_cnt = 0;
3624 rval = qla_get_exlogin_status(vha, &size, &max_cnt);
3625 if (rval != QLA_SUCCESS) {
3626 ql_log_pci(ql_log_fatal, ha->pdev, 0xd029,
3627 "Failed to get exlogin status.\n");
3628 return rval;
3629 }
3630
3631 temp = (ql2xexlogins > max_cnt) ? max_cnt : ql2xexlogins;
3632 ha->exlogin_size = (size * temp);
3633 ql_log(ql_log_info, vha, 0xd024,
3634 "EXLOGIN: max_logins=%d, portdb=0x%x, total=%d.\n",
3635 max_cnt, size, temp);
3636
3637 ql_log(ql_log_info, vha, 0xd025, "EXLOGIN: requested size=0x%x\n",
3638 ha->exlogin_size);
3639
3640 /* Get consistent memory for extended logins */
3641 ha->exlogin_buf = dma_alloc_coherent(&ha->pdev->dev,
3642 ha->exlogin_size, &ha->exlogin_buf_dma, GFP_KERNEL);
3643 if (!ha->exlogin_buf) {
3644 ql_log_pci(ql_log_fatal, ha->pdev, 0xd02a,
3645 "Failed to allocate memory for exlogin_buf_dma.\n");
3646 return -ENOMEM;
3647 }
3648
3649 /* Now configure the dma buffer */
3650 rval = qla_set_exlogin_mem_cfg(vha, ha->exlogin_buf_dma);
3651 if (rval) {
3652 ql_log(ql_log_fatal, vha, 0x00cf,
3653 "Setup extended login buffer ****FAILED****.\n");
3654 qla2x00_free_exlogin_buffer(ha);
3655 }
3656
3657 return rval;
3658}
3659
3660/*
3661* qla2x00_free_exlogin_buffer
3662*
3663* Input:
3664* ha = adapter block pointer
3665*/
3666void
3667qla2x00_free_exlogin_buffer(struct qla_hw_data *ha)
3668{
3669 if (ha->exlogin_buf) {
3670 dma_free_coherent(&ha->pdev->dev, ha->exlogin_size,
3671 ha->exlogin_buf, ha->exlogin_buf_dma);
3672 ha->exlogin_buf = NULL;
3673 ha->exlogin_size = 0;
3674 }
3675}
3676
2f56a7f1
HM		 3677int
3678qla2x00_set_exchoffld_buffer(scsi_qla_host_t *vha)
3679{
3680 int rval;
3681 uint16_t size, max_cnt, temp;
3682 struct qla_hw_data *ha = vha->hw;
3683
3684 /* Return if we don't need to alloacate any extended logins */
3685 if (!ql2xexchoffld)
3686 return QLA_SUCCESS;
3687
3688 ql_log(ql_log_info, vha, 0xd014,
3689 "Exchange offload count: %d.\n", ql2xexlogins);
3690
3691 max_cnt = 0;
3692 rval = qla_get_exchoffld_status(vha, &size, &max_cnt);
3693 if (rval != QLA_SUCCESS) {
3694 ql_log_pci(ql_log_fatal, ha->pdev, 0xd012,
3695 "Failed to get exlogin status.\n");
3696 return rval;
3697 }
3698
3699 temp = (ql2xexchoffld > max_cnt) ? max_cnt : ql2xexchoffld;
3700 ha->exchoffld_size = (size * temp);
3701 ql_log(ql_log_info, vha, 0xd016,
3702 "Exchange offload: max_count=%d, buffers=0x%x, total=%d.\n",
3703 max_cnt, size, temp);
3704
3705 ql_log(ql_log_info, vha, 0xd017,
3706 "Exchange Buffers requested size = 0x%x\n", ha->exchoffld_size);
3707
3708 /* Get consistent memory for extended logins */
3709 ha->exchoffld_buf = dma_alloc_coherent(&ha->pdev->dev,
3710 ha->exchoffld_size, &ha->exchoffld_buf_dma, GFP_KERNEL);
3711 if (!ha->exchoffld_buf) {
3712 ql_log_pci(ql_log_fatal, ha->pdev, 0xd013,
3713 "Failed to allocate memory for exchoffld_buf_dma.\n");
3714 return -ENOMEM;
3715 }
3716
3717 /* Now configure the dma buffer */
3718 rval = qla_set_exchoffld_mem_cfg(vha, ha->exchoffld_buf_dma);
3719 if (rval) {
3720 ql_log(ql_log_fatal, vha, 0xd02e,
3721 "Setup exchange offload buffer ****FAILED****.\n");
3722 qla2x00_free_exchoffld_buffer(ha);
3723 }
3724
3725 return rval;
3726}
3727
3728/*
3729* qla2x00_free_exchoffld_buffer
3730*
3731* Input:
3732* ha = adapter block pointer
3733*/
3734void
3735qla2x00_free_exchoffld_buffer(struct qla_hw_data *ha)
3736{
3737 if (ha->exchoffld_buf) {
3738 dma_free_coherent(&ha->pdev->dev, ha->exchoffld_size,
3739 ha->exchoffld_buf, ha->exchoffld_buf_dma);
3740 ha->exchoffld_buf = NULL;
3741 ha->exchoffld_size = 0;
3742 }
3743}
3744
1da177e4 3745/*
e30d1756
MI		 3746* qla2x00_free_fw_dump
3747* Frees fw dump stuff.
1da177e4
LT		 3748*
3749* Input:
7ec0effd 3750* ha = adapter block pointer
1da177e4 3751*/
a824ebb3 3752static void
e30d1756 3753qla2x00_free_fw_dump(struct qla_hw_data *ha)
1da177e4 3754{
df613b96 3755 if (ha->fce)
f73cb695
CD		 3756 dma_free_coherent(&ha->pdev->dev,
3757 FCE_SIZE, ha->fce, ha->fce_dma);
df613b96 3758
f73cb695
CD		 3759 if (ha->eft)
3760 dma_free_coherent(&ha->pdev->dev,
3761 EFT_SIZE, ha->eft, ha->eft_dma);
3762
3763 if (ha->fw_dump)
a7a167bf 3764 vfree(ha->fw_dump);
f73cb695
CD		 3765 if (ha->fw_dump_template)
3766 vfree(ha->fw_dump_template);
3767
e30d1756
MI		 3768 ha->fce = NULL;
3769 ha->fce_dma = 0;
3770 ha->eft = NULL;
3771 ha->eft_dma = 0;
e30d1756 3772 ha->fw_dumped = 0;
61f098dd 3773 ha->fw_dump_cap_flags = 0;
e30d1756 3774 ha->fw_dump_reading = 0;
f73cb695
CD		 3775 ha->fw_dump = NULL;
3776 ha->fw_dump_len = 0;
3777 ha->fw_dump_template = NULL;
3778 ha->fw_dump_template_len = 0;
e30d1756
MI		 3779}
3780
3781/*
3782* qla2x00_mem_free
3783* Frees all adapter allocated memory.
3784*
3785* Input:
3786* ha = adapter block pointer.
3787*/
3788static void
3789qla2x00_mem_free(struct qla_hw_data *ha)
3790{
3791 qla2x00_free_fw_dump(ha);
3792
81178772
SK		 3793 if (ha->mctp_dump)
3794 dma_free_coherent(&ha->pdev->dev, MCTP_DUMP_SIZE, ha->mctp_dump,
3795 ha->mctp_dump_dma);
3796
e30d1756
MI		 3797 if (ha->srb_mempool)
3798 mempool_destroy(ha->srb_mempool);
a7a167bf 3799
11bbc1d8
AV		 3800 if (ha->dcbx_tlv)
3801 dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE,
3802 ha->dcbx_tlv, ha->dcbx_tlv_dma);
3803
ce0423f4
AV		 3804 if (ha->xgmac_data)
3805 dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE,
3806 ha->xgmac_data, ha->xgmac_data_dma);
3807
1da177e4
LT		 3808 if (ha->sns_cmd)
3809 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
e315cd28 3810 ha->sns_cmd, ha->sns_cmd_dma);
1da177e4
LT		 3811
3812 if (ha->ct_sns)
3813 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
e315cd28 3814 ha->ct_sns, ha->ct_sns_dma);
1da177e4 3815
88729e53
AV		 3816 if (ha->sfp_data)
3817 dma_pool_free(ha->s_dma_pool, ha->sfp_data, ha->sfp_data_dma);
3818
1da177e4
LT		 3819 if (ha->ms_iocb)
3820 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
3821
b64b0e8f 3822 if (ha->ex_init_cb)
a9083016
GM		 3823 dma_pool_free(ha->s_dma_pool,
3824 ha->ex_init_cb, ha->ex_init_cb_dma);
b64b0e8f 3825
5ff1d584
AV		 3826 if (ha->async_pd)
3827 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
3828
1da177e4
LT		 3829 if (ha->s_dma_pool)
3830 dma_pool_destroy(ha->s_dma_pool);
3831
1da177e4 3832 if (ha->gid_list)
642ef983
CD		 3833 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
3834 ha->gid_list, ha->gid_list_dma);
1da177e4 3835
a9083016
GM		 3836 if (IS_QLA82XX(ha)) {
3837 if (!list_empty(&ha->gbl_dsd_list)) {
3838 struct dsd_dma *dsd_ptr, *tdsd_ptr;
3839
3840 /* clean up allocated prev pool */
3841 list_for_each_entry_safe(dsd_ptr,
3842 tdsd_ptr, &ha->gbl_dsd_list, list) {
3843 dma_pool_free(ha->dl_dma_pool,
3844 dsd_ptr->dsd_addr, dsd_ptr->dsd_list_dma);
3845 list_del(&dsd_ptr->list);
3846 kfree(dsd_ptr);
3847 }
3848 }
3849 }
3850
3851 if (ha->dl_dma_pool)
3852 dma_pool_destroy(ha->dl_dma_pool);
3853
3854 if (ha->fcp_cmnd_dma_pool)
3855 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
3856
3857 if (ha->ctx_mempool)
3858 mempool_destroy(ha->ctx_mempool);
3859
2d70c103
NB		 3860 qlt_mem_free(ha);
3861
e315cd28
AC		 3862 if (ha->init_cb)
3863 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size,
a9083016 3864 ha->init_cb, ha->init_cb_dma);
e315cd28
AC		 3865 vfree(ha->optrom_buffer);
3866 kfree(ha->nvram);
73208dfd 3867 kfree(ha->npiv_info);
7a67735b 3868 kfree(ha->swl);
5f16b331 3869 kfree(ha->loop_id_map);
1da177e4 3870
e8711085 3871 ha->srb_mempool = NULL;
a9083016 3872 ha->ctx_mempool = NULL;
1da177e4
LT		 3873 ha->sns_cmd = NULL;
3874 ha->sns_cmd_dma = 0;
3875 ha->ct_sns = NULL;
3876 ha->ct_sns_dma = 0;
3877 ha->ms_iocb = NULL;
3878 ha->ms_iocb_dma = 0;
1da177e4
LT		 3879 ha->init_cb = NULL;
3880 ha->init_cb_dma = 0;
b64b0e8f
AV		 3881 ha->ex_init_cb = NULL;
3882 ha->ex_init_cb_dma = 0;
5ff1d584
AV		 3883 ha->async_pd = NULL;
3884 ha->async_pd_dma = 0;
1da177e4
LT		 3885
3886 ha->s_dma_pool = NULL;
a9083016
GM		 3887 ha->dl_dma_pool = NULL;
3888 ha->fcp_cmnd_dma_pool = NULL;
1da177e4 3889
1da177e4
LT		 3890 ha->gid_list = NULL;
3891 ha->gid_list_dma = 0;
2d70c103
NB		 3892
3893 ha->tgt.atio_ring = NULL;
3894 ha->tgt.atio_dma = 0;
3895 ha->tgt.tgt_vp_map = NULL;
e315cd28 3896}
1da177e4 3897
e315cd28
AC		 3898struct scsi_qla_host *qla2x00_create_host(struct scsi_host_template *sht,
3899 struct qla_hw_data *ha)
3900{
3901 struct Scsi_Host *host;
3902 struct scsi_qla_host *vha = NULL;
854165f4 3903
e315cd28
AC		 3904 host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t));
3905 if (host == NULL) {
7c3df132
SK		 3906 ql_log_pci(ql_log_fatal, ha->pdev, 0x0107,
3907 "Failed to allocate host from the scsi layer, aborting.\n");
e315cd28
AC		 3908 goto fail;
3909 }
3910
3911 /* Clear our data area */
3912 vha = shost_priv(host);
3913 memset(vha, 0, sizeof(scsi_qla_host_t));
3914
3915 vha->host = host;
3916 vha->host_no = host->host_no;
3917 vha->hw = ha;
3918
3919 INIT_LIST_HEAD(&vha->vp_fcports);
3920 INIT_LIST_HEAD(&vha->work_list);
3921 INIT_LIST_HEAD(&vha->list);
8b2f5ff3
SN		 3922 INIT_LIST_HEAD(&vha->qla_cmd_list);
3923 INIT_LIST_HEAD(&vha->qla_sess_op_cmd_list);
71cdc079 3924 INIT_LIST_HEAD(&vha->logo_list);
b7bd104e 3925 INIT_LIST_HEAD(&vha->plogi_ack_list);
e315cd28 3926
f999f4c1 3927 spin_lock_init(&vha->work_lock);
8b2f5ff3 3928 spin_lock_init(&vha->cmd_list_lock);
f999f4c1 3929
e315cd28 3930 sprintf(vha->host_str, "%s_%ld", QLA2XXX_DRIVER_NAME, vha->host_no);
7c3df132
SK		 3931 ql_dbg(ql_dbg_init, vha, 0x0041,
3932 "Allocated the host=%p hw=%p vha=%p dev_name=%s",
3933 vha->host, vha->hw, vha,
3934 dev_name(&(ha->pdev->dev)));
3935
e315cd28
AC		 3936 return vha;
3937
3938fail:
3939 return vha;
1da177e4
LT		 3940}
3941
01ef66bb 3942static struct qla_work_evt *
f999f4c1 3943qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type)
0971de7f
AV		 3944{
3945 struct qla_work_evt *e;
feafb7b1
AE		 3946 uint8_t bail;
3947
3948 QLA_VHA_MARK_BUSY(vha, bail);
3949 if (bail)
3950 return NULL;
0971de7f 3951
f999f4c1 3952 e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC);
feafb7b1
AE		 3953 if (!e) {
3954 QLA_VHA_MARK_NOT_BUSY(vha);
0971de7f 3955 return NULL;
feafb7b1 3956 }
0971de7f
AV		 3957
3958 INIT_LIST_HEAD(&e->list);
3959 e->type = type;
3960 e->flags = QLA_EVT_FLAG_FREE;
3961 return e;
3962}
3963
01ef66bb 3964static int
f999f4c1 3965qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e)
0971de7f 3966{
f999f4c1 3967 unsigned long flags;
0971de7f 3968
f999f4c1 3969 spin_lock_irqsave(&vha->work_lock, flags);
e315cd28 3970 list_add_tail(&e->list, &vha->work_list);
f999f4c1 3971 spin_unlock_irqrestore(&vha->work_lock, flags);
e315cd28 3972 qla2xxx_wake_dpc(vha);
f999f4c1 3973
0971de7f
AV		 3974 return QLA_SUCCESS;
3975}
3976
3977int
e315cd28 3978qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code,
0971de7f
AV		 3979 u32 data)
3980{
3981 struct qla_work_evt *e;
3982
f999f4c1 3983 e = qla2x00_alloc_work(vha, QLA_EVT_AEN);
0971de7f
AV		 3984 if (!e)
3985 return QLA_FUNCTION_FAILED;
3986
3987 e->u.aen.code = code;
3988 e->u.aen.data = data;
f999f4c1 3989 return qla2x00_post_work(vha, e);
0971de7f
AV		 3990}
3991
8a659571
AV		 3992int
3993qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb)
3994{
3995 struct qla_work_evt *e;
3996
f999f4c1 3997 e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK);
8a659571
AV		 3998 if (!e)
3999 return QLA_FUNCTION_FAILED;
4000
4001 memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t));
f999f4c1 4002 return qla2x00_post_work(vha, e);
8a659571
AV		 4003}
4004
ac280b67
AV		 4005#define qla2x00_post_async_work(name, type) \
4006int qla2x00_post_async_##name##_work( \
4007 struct scsi_qla_host *vha, \
4008 fc_port_t *fcport, uint16_t *data) \
4009{ \
4010 struct qla_work_evt *e; \
4011 \
4012 e = qla2x00_alloc_work(vha, type); \
4013 if (!e) \
4014 return QLA_FUNCTION_FAILED; \
4015 \
4016 e->u.logio.fcport = fcport; \
4017 if (data) { \
4018 e->u.logio.data[0] = data[0]; \
4019 e->u.logio.data[1] = data[1]; \
4020 } \
4021 return qla2x00_post_work(vha, e); \
4022}
4023
4024qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN);
4025qla2x00_post_async_work(login_done, QLA_EVT_ASYNC_LOGIN_DONE);
4026qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT);
4027qla2x00_post_async_work(logout_done, QLA_EVT_ASYNC_LOGOUT_DONE);
5ff1d584
AV		 4028qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC);
4029qla2x00_post_async_work(adisc_done, QLA_EVT_ASYNC_ADISC_DONE);
ac280b67 4030
3420d36c
AV		 4031int
4032qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code)
4033{
4034 struct qla_work_evt *e;
4035
4036 e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT);
4037 if (!e)
4038 return QLA_FUNCTION_FAILED;
4039
4040 e->u.uevent.code = code;
4041 return qla2x00_post_work(vha, e);
4042}
4043
4044static void
4045qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code)
4046{
4047 char event_string[40];
4048 char *envp[] = { event_string, NULL };
4049
4050 switch (code) {
4051 case QLA_UEVENT_CODE_FW_DUMP:
4052 snprintf(event_string, sizeof(event_string), "FW_DUMP=%ld",
4053 vha->host_no);
4054 break;
4055 default:
4056 /* do nothing */
4057 break;
4058 }
4059 kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp);
4060}
4061
8ae6d9c7
GM		 4062int
4063qlafx00_post_aenfx_work(struct scsi_qla_host *vha, uint32_t evtcode,
4064 uint32_t *data, int cnt)
4065{
4066 struct qla_work_evt *e;
4067
4068 e = qla2x00_alloc_work(vha, QLA_EVT_AENFX);
4069 if (!e)
4070 return QLA_FUNCTION_FAILED;
4071
4072 e->u.aenfx.evtcode = evtcode;
4073 e->u.aenfx.count = cnt;
4074 memcpy(e->u.aenfx.mbx, data, sizeof(*data) * cnt);
4075 return qla2x00_post_work(vha, e);
4076}
4077
ac280b67 4078void
e315cd28 4079qla2x00_do_work(struct scsi_qla_host *vha)
0971de7f 4080{
f999f4c1
AV		 4081 struct qla_work_evt *e, *tmp;
4082 unsigned long flags;
4083 LIST_HEAD(work);
0971de7f 4084
f999f4c1
AV		 4085 spin_lock_irqsave(&vha->work_lock, flags);
4086 list_splice_init(&vha->work_list, &work);
4087 spin_unlock_irqrestore(&vha->work_lock, flags);
4088
4089 list_for_each_entry_safe(e, tmp, &work, list) {
0971de7f 4090 list_del_init(&e->list);
0971de7f
AV		 4091
4092 switch (e->type) {
4093 case QLA_EVT_AEN:
e315cd28 4094 fc_host_post_event(vha->host, fc_get_event_number(),
0971de7f
AV		 4095 e->u.aen.code, e->u.aen.data);
4096 break;
8a659571
AV		 4097 case QLA_EVT_IDC_ACK:
4098 qla81xx_idc_ack(vha, e->u.idc_ack.mb);
4099 break;
ac280b67
AV		 4100 case QLA_EVT_ASYNC_LOGIN:
4101 qla2x00_async_login(vha, e->u.logio.fcport,
4102 e->u.logio.data);
4103 break;
4104 case QLA_EVT_ASYNC_LOGIN_DONE:
4105 qla2x00_async_login_done(vha, e->u.logio.fcport,
4106 e->u.logio.data);
4107 break;
4108 case QLA_EVT_ASYNC_LOGOUT:
4109 qla2x00_async_logout(vha, e->u.logio.fcport);
4110 break;
4111 case QLA_EVT_ASYNC_LOGOUT_DONE:
4112 qla2x00_async_logout_done(vha, e->u.logio.fcport,
4113 e->u.logio.data);
4114 break;
5ff1d584
AV		 4115 case QLA_EVT_ASYNC_ADISC:
4116 qla2x00_async_adisc(vha, e->u.logio.fcport,
4117 e->u.logio.data);
4118 break;
4119 case QLA_EVT_ASYNC_ADISC_DONE:
4120 qla2x00_async_adisc_done(vha, e->u.logio.fcport,
4121 e->u.logio.data);
4122 break;
3420d36c
AV		 4123 case QLA_EVT_UEVENT:
4124 qla2x00_uevent_emit(vha, e->u.uevent.code);
4125 break;
8ae6d9c7
GM		 4126 case QLA_EVT_AENFX:
4127 qlafx00_process_aen(vha, e);
4128 break;
0971de7f
AV		 4129 }
4130 if (e->flags & QLA_EVT_FLAG_FREE)
4131 kfree(e);
feafb7b1
AE		 4132
4133 /* For each work completed decrement vha ref count */
4134 QLA_VHA_MARK_NOT_BUSY(vha);
e315cd28 4135 }
e315cd28 4136}
f999f4c1 4137
e315cd28
AC		 4138/* Relogins all the fcports of a vport
4139 * Context: dpc thread
4140 */
4141void qla2x00_relogin(struct scsi_qla_host *vha)
4142{
4143 fc_port_t *fcport;
c6b2fca8 4144 int status;
e315cd28
AC		 4145 uint16_t next_loopid = 0;
4146 struct qla_hw_data *ha = vha->hw;
ac280b67 4147 uint16_t data[2];
e315cd28
AC		 4148
4149 list_for_each_entry(fcport, &vha->vp_fcports, list) {
4150 /*
4151 * If the port is not ONLINE then try to login
4152 * to it if we haven't run out of retries.
4153 */
5ff1d584
AV		 4154 if (atomic_read(&fcport->state) != FCS_ONLINE &&
4155 fcport->login_retry && !(fcport->flags & FCF_ASYNC_SENT)) {
ac280b67 4156 fcport->login_retry--;
e315cd28 4157 if (fcport->flags & FCF_FABRIC_DEVICE) {
f08b7251 4158 if (fcport->flags & FCF_FCP2_DEVICE)
e315cd28
AC		 4159 ha->isp_ops->fabric_logout(vha,
4160 fcport->loop_id,
4161 fcport->d_id.b.domain,
4162 fcport->d_id.b.area,
4163 fcport->d_id.b.al_pa);
4164
03bcfb57
JC		 4165 if (fcport->loop_id == FC_NO_LOOP_ID) {
4166 fcport->loop_id = next_loopid =
4167 ha->min_external_loopid;
4168 status = qla2x00_find_new_loop_id(
4169 vha, fcport);
4170 if (status != QLA_SUCCESS) {
4171 /* Ran out of IDs to use */
4172 break;
4173 }
4174 }
4175
ac280b67 4176 if (IS_ALOGIO_CAPABLE(ha)) {
5ff1d584 4177 fcport->flags |= FCF_ASYNC_SENT;
ac280b67
AV		 4178 data[0] = 0;
4179 data[1] = QLA_LOGIO_LOGIN_RETRIED;
4180 status = qla2x00_post_async_login_work(
4181 vha, fcport, data);
4182 if (status == QLA_SUCCESS)
4183 continue;
4184 /* Attempt a retry. */
4185 status = 1;
aaf4d3e2 4186 } else {
ac280b67
AV		 4187 status = qla2x00_fabric_login(vha,
4188 fcport, &next_loopid);
aaf4d3e2
SK		 4189 if (status == QLA_SUCCESS) {
4190 int status2;
4191 uint8_t opts;
4192
4193 opts = 0;
4194 if (fcport->flags &
4195 FCF_FCP2_DEVICE)
4196 opts |= BIT_1;
03003960
SK		 4197 status2 =
4198 qla2x00_get_port_database(
4199 vha, fcport, opts);
aaf4d3e2
SK		 4200 if (status2 != QLA_SUCCESS)
4201 status = 1;
4202 }
4203 }
e315cd28
AC		 4204 } else
4205 status = qla2x00_local_device_login(vha,
4206 fcport);
4207
e315cd28
AC		 4208 if (status == QLA_SUCCESS) {
4209 fcport->old_loop_id = fcport->loop_id;
4210
7c3df132
SK		 4211 ql_dbg(ql_dbg_disc, vha, 0x2003,
4212 "Port login OK: logged in ID 0x%x.\n",
4213 fcport->loop_id);
e315cd28
AC		 4214
4215 qla2x00_update_fcport(vha, fcport);
4216
4217 } else if (status == 1) {
4218 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
4219 /* retry the login again */
7c3df132
SK		 4220 ql_dbg(ql_dbg_disc, vha, 0x2007,
4221 "Retrying %d login again loop_id 0x%x.\n",
4222 fcport->login_retry, fcport->loop_id);
e315cd28
AC		 4223 } else {
4224 fcport->login_retry = 0;
4225 }
4226
4227 if (fcport->login_retry == 0 && status != QLA_SUCCESS)
5f16b331 4228 qla2x00_clear_loop_id(fcport);
e315cd28
AC		 4229 }
4230 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
4231 break;
0971de7f 4232 }
0971de7f
AV		 4233}
4234
7d613ac6
SV		 4235/* Schedule work on any of the dpc-workqueues */
4236void
4237qla83xx_schedule_work(scsi_qla_host_t *base_vha, int work_code)
4238{
4239 struct qla_hw_data *ha = base_vha->hw;
4240
4241 switch (work_code) {
4242 case MBA_IDC_AEN: /* 0x8200 */
4243 if (ha->dpc_lp_wq)
4244 queue_work(ha->dpc_lp_wq, &ha->idc_aen);
4245 break;
4246
4247 case QLA83XX_NIC_CORE_RESET: /* 0x1 */
4248 if (!ha->flags.nic_core_reset_hdlr_active) {
4249 if (ha->dpc_hp_wq)
4250 queue_work(ha->dpc_hp_wq, &ha->nic_core_reset);
4251 } else
4252 ql_dbg(ql_dbg_p3p, base_vha, 0xb05e,
4253 "NIC Core reset is already active. Skip "
4254 "scheduling it again.\n");
4255 break;
4256 case QLA83XX_IDC_STATE_HANDLER: /* 0x2 */
4257 if (ha->dpc_hp_wq)
4258 queue_work(ha->dpc_hp_wq, &ha->idc_state_handler);
4259 break;
4260 case QLA83XX_NIC_CORE_UNRECOVERABLE: /* 0x3 */
4261 if (ha->dpc_hp_wq)
4262 queue_work(ha->dpc_hp_wq, &ha->nic_core_unrecoverable);
4263 break;
4264 default:
4265 ql_log(ql_log_warn, base_vha, 0xb05f,
d939be3a 4266 "Unknown work-code=0x%x.\n", work_code);
7d613ac6
SV		 4267 }
4268
4269 return;
4270}
4271
4272/* Work: Perform NIC Core Unrecoverable state handling */
4273void
4274qla83xx_nic_core_unrecoverable_work(struct work_struct *work)
4275{
4276 struct qla_hw_data *ha =
2ad1b67c 4277 container_of(work, struct qla_hw_data, nic_core_unrecoverable);
7d613ac6
SV		 4278 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4279 uint32_t dev_state = 0;
4280
4281 qla83xx_idc_lock(base_vha, 0);
4282 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4283 qla83xx_reset_ownership(base_vha);
4284 if (ha->flags.nic_core_reset_owner) {
4285 ha->flags.nic_core_reset_owner = 0;
4286 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
4287 QLA8XXX_DEV_FAILED);
4288 ql_log(ql_log_info, base_vha, 0xb060, "HW State: FAILED.\n");
4289 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
4290 }
4291 qla83xx_idc_unlock(base_vha, 0);
4292}
4293
4294/* Work: Execute IDC state handler */
4295void
4296qla83xx_idc_state_handler_work(struct work_struct *work)
4297{
4298 struct qla_hw_data *ha =
2ad1b67c 4299 container_of(work, struct qla_hw_data, idc_state_handler);
7d613ac6
SV		 4300 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4301 uint32_t dev_state = 0;
4302
4303 qla83xx_idc_lock(base_vha, 0);
4304 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4305 if (dev_state == QLA8XXX_DEV_FAILED ||
4306 dev_state == QLA8XXX_DEV_NEED_QUIESCENT)
4307 qla83xx_idc_state_handler(base_vha);
4308 qla83xx_idc_unlock(base_vha, 0);
4309}
4310
fa492630 4311static int
7d613ac6
SV		 4312qla83xx_check_nic_core_fw_alive(scsi_qla_host_t *base_vha)
4313{
4314 int rval = QLA_SUCCESS;
4315 unsigned long heart_beat_wait = jiffies + (1 * HZ);
4316 uint32_t heart_beat_counter1, heart_beat_counter2;
4317
4318 do {
4319 if (time_after(jiffies, heart_beat_wait)) {
4320 ql_dbg(ql_dbg_p3p, base_vha, 0xb07c,
4321 "Nic Core f/w is not alive.\n");
4322 rval = QLA_FUNCTION_FAILED;
4323 break;
4324 }
4325
4326 qla83xx_idc_lock(base_vha, 0);
4327 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
4328 &heart_beat_counter1);
4329 qla83xx_idc_unlock(base_vha, 0);
4330 msleep(100);
4331 qla83xx_idc_lock(base_vha, 0);
4332 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
4333 &heart_beat_counter2);
4334 qla83xx_idc_unlock(base_vha, 0);
4335 } while (heart_beat_counter1 == heart_beat_counter2);
4336
4337 return rval;
4338}
4339
4340/* Work: Perform NIC Core Reset handling */
4341void
4342qla83xx_nic_core_reset_work(struct work_struct *work)
4343{
4344 struct qla_hw_data *ha =
4345 container_of(work, struct qla_hw_data, nic_core_reset);
4346 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4347 uint32_t dev_state = 0;
4348
81178772
SK		 4349 if (IS_QLA2031(ha)) {
4350 if (qla2xxx_mctp_dump(base_vha) != QLA_SUCCESS)
4351 ql_log(ql_log_warn, base_vha, 0xb081,
4352 "Failed to dump mctp\n");
4353 return;
4354 }
4355
7d613ac6
SV		 4356 if (!ha->flags.nic_core_reset_hdlr_active) {
4357 if (qla83xx_check_nic_core_fw_alive(base_vha) == QLA_SUCCESS) {
4358 qla83xx_idc_lock(base_vha, 0);
4359 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE,
4360 &dev_state);
4361 qla83xx_idc_unlock(base_vha, 0);
4362 if (dev_state != QLA8XXX_DEV_NEED_RESET) {
4363 ql_dbg(ql_dbg_p3p, base_vha, 0xb07a,
4364 "Nic Core f/w is alive.\n");
4365 return;
4366 }
4367 }
4368
4369 ha->flags.nic_core_reset_hdlr_active = 1;
4370 if (qla83xx_nic_core_reset(base_vha)) {
4371 /* NIC Core reset failed. */
4372 ql_dbg(ql_dbg_p3p, base_vha, 0xb061,
4373 "NIC Core reset failed.\n");
4374 }
4375 ha->flags.nic_core_reset_hdlr_active = 0;
4376 }
4377}
4378
4379/* Work: Handle 8200 IDC aens */
4380void
4381qla83xx_service_idc_aen(struct work_struct *work)
4382{
4383 struct qla_hw_data *ha =
4384 container_of(work, struct qla_hw_data, idc_aen);
4385 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4386 uint32_t dev_state, idc_control;
4387
4388 qla83xx_idc_lock(base_vha, 0);
4389 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4390 qla83xx_rd_reg(base_vha, QLA83XX_IDC_CONTROL, &idc_control);
4391 qla83xx_idc_unlock(base_vha, 0);
4392 if (dev_state == QLA8XXX_DEV_NEED_RESET) {
4393 if (idc_control & QLA83XX_IDC_GRACEFUL_RESET) {
4394 ql_dbg(ql_dbg_p3p, base_vha, 0xb062,
4395 "Application requested NIC Core Reset.\n");
4396 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
4397 } else if (qla83xx_check_nic_core_fw_alive(base_vha) ==
4398 QLA_SUCCESS) {
4399 ql_dbg(ql_dbg_p3p, base_vha, 0xb07b,
4400 "Other protocol driver requested NIC Core Reset.\n");
4401 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
4402 }
4403 } else if (dev_state == QLA8XXX_DEV_FAILED ||
4404 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) {
4405 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
4406 }
4407}
4408
4409static void
4410qla83xx_wait_logic(void)
4411{
4412 int i;
4413
4414 /* Yield CPU */
4415 if (!in_interrupt()) {
4416 /*
4417 * Wait about 200ms before retrying again.
4418 * This controls the number of retries for single
4419 * lock operation.
4420 */
4421 msleep(100);
4422 schedule();
4423 } else {
4424 for (i = 0; i < 20; i++)
4425 cpu_relax(); /* This a nop instr on i386 */
4426 }
4427}
4428
fa492630 4429static int
7d613ac6
SV		 4430qla83xx_force_lock_recovery(scsi_qla_host_t *base_vha)
4431{
4432 int rval;
4433 uint32_t data;
4434 uint32_t idc_lck_rcvry_stage_mask = 0x3;
4435 uint32_t idc_lck_rcvry_owner_mask = 0x3c;
4436 struct qla_hw_data *ha = base_vha->hw;
6c315553
SK		 4437 ql_dbg(ql_dbg_p3p, base_vha, 0xb086,
4438 "Trying force recovery of the IDC lock.\n");
7d613ac6
SV		 4439
4440 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, &data);
4441 if (rval)
4442 return rval;
4443
4444 if ((data & idc_lck_rcvry_stage_mask) > 0) {
4445 return QLA_SUCCESS;
4446 } else {
4447 data = (IDC_LOCK_RECOVERY_STAGE1) | (ha->portnum << 2);
4448 rval = qla83xx_wr_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
4449 data);
4450 if (rval)
4451 return rval;
4452
4453 msleep(200);
4454
4455 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
4456 &data);
4457 if (rval)
4458 return rval;
4459
4460 if (((data & idc_lck_rcvry_owner_mask) >> 2) == ha->portnum) {
4461 data &= (IDC_LOCK_RECOVERY_STAGE2 |
4462 ~(idc_lck_rcvry_stage_mask));
4463 rval = qla83xx_wr_reg(base_vha,
4464 QLA83XX_IDC_LOCK_RECOVERY, data);
4465 if (rval)
4466 return rval;
4467
4468 /* Forcefully perform IDC UnLock */
4469 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK,
4470 &data);
4471 if (rval)
4472 return rval;
4473 /* Clear lock-id by setting 0xff */
4474 rval = qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
4475 0xff);
4476 if (rval)
4477 return rval;
4478 /* Clear lock-recovery by setting 0x0 */
4479 rval = qla83xx_wr_reg(base_vha,
4480 QLA83XX_IDC_LOCK_RECOVERY, 0x0);
4481 if (rval)
4482 return rval;
4483 } else
4484 return QLA_SUCCESS;
4485 }
4486
4487 return rval;
4488}
4489
fa492630 4490static int
7d613ac6
SV		 4491qla83xx_idc_lock_recovery(scsi_qla_host_t *base_vha)
4492{
4493 int rval = QLA_SUCCESS;
4494 uint32_t o_drv_lockid, n_drv_lockid;
4495 unsigned long lock_recovery_timeout;
4496
4497 lock_recovery_timeout = jiffies + QLA83XX_MAX_LOCK_RECOVERY_WAIT;
4498retry_lockid:
4499 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &o_drv_lockid);
4500 if (rval)
4501 goto exit;
4502
4503 /* MAX wait time before forcing IDC Lock recovery = 2 secs */
4504 if (time_after_eq(jiffies, lock_recovery_timeout)) {
4505 if (qla83xx_force_lock_recovery(base_vha) == QLA_SUCCESS)
4506 return QLA_SUCCESS;
4507 else
4508 return QLA_FUNCTION_FAILED;
4509 }
4510
4511 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &n_drv_lockid);
4512 if (rval)
4513 goto exit;
4514
4515 if (o_drv_lockid == n_drv_lockid) {
4516 qla83xx_wait_logic();
4517 goto retry_lockid;
4518 } else
4519 return QLA_SUCCESS;
4520
4521exit:
4522 return rval;
4523}
4524
4525void
4526qla83xx_idc_lock(scsi_qla_host_t *base_vha, uint16_t requester_id)
4527{
4528 uint16_t options = (requester_id << 15) | BIT_6;
4529 uint32_t data;
6c315553 4530 uint32_t lock_owner;
7d613ac6
SV		 4531 struct qla_hw_data *ha = base_vha->hw;
4532
4533 /* IDC-lock implementation using driver-lock/lock-id remote registers */
4534retry_lock:
4535 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCK, &data)
4536 == QLA_SUCCESS) {
4537 if (data) {
4538 /* Setting lock-id to our function-number */
4539 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
4540 ha->portnum);
4541 } else {
6c315553
SK		 4542 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID,
4543 &lock_owner);
7d613ac6 4544 ql_dbg(ql_dbg_p3p, base_vha, 0xb063,
6c315553
SK		 4545 "Failed to acquire IDC lock, acquired by %d, "
4546 "retrying...\n", lock_owner);
7d613ac6
SV		 4547
4548 /* Retry/Perform IDC-Lock recovery */
4549 if (qla83xx_idc_lock_recovery(base_vha)
4550 == QLA_SUCCESS) {
4551 qla83xx_wait_logic();
4552 goto retry_lock;
4553 } else
4554 ql_log(ql_log_warn, base_vha, 0xb075,
4555 "IDC Lock recovery FAILED.\n");
4556 }
4557
4558 }
4559
4560 return;
4561
4562 /* XXX: IDC-lock implementation using access-control mbx */
4563retry_lock2:
4564 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
4565 ql_dbg(ql_dbg_p3p, base_vha, 0xb072,
4566 "Failed to acquire IDC lock. retrying...\n");
4567 /* Retry/Perform IDC-Lock recovery */
4568 if (qla83xx_idc_lock_recovery(base_vha) == QLA_SUCCESS) {
4569 qla83xx_wait_logic();
4570 goto retry_lock2;
4571 } else
4572 ql_log(ql_log_warn, base_vha, 0xb076,
4573 "IDC Lock recovery FAILED.\n");
4574 }
4575
4576 return;
4577}
4578
4579void
4580qla83xx_idc_unlock(scsi_qla_host_t *base_vha, uint16_t requester_id)
4581{
5897cb2f
BVA		 4582#if 0
4583 uint16_t options = (requester_id << 15) | BIT_7;
4584#endif
4585 uint16_t retry;
7d613ac6
SV		 4586 uint32_t data;
4587 struct qla_hw_data *ha = base_vha->hw;
4588
4589 /* IDC-unlock implementation using driver-unlock/lock-id
4590 * remote registers
4591 */
4592 retry = 0;
4593retry_unlock:
4594 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &data)
4595 == QLA_SUCCESS) {
4596 if (data == ha->portnum) {
4597 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, &data);
4598 /* Clearing lock-id by setting 0xff */
4599 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 0xff);
4600 } else if (retry < 10) {
4601 /* SV: XXX: IDC unlock retrying needed here? */
4602
4603 /* Retry for IDC-unlock */
4604 qla83xx_wait_logic();
4605 retry++;
4606 ql_dbg(ql_dbg_p3p, base_vha, 0xb064,
4607 "Failed to release IDC lock, retyring=%d\n", retry);
4608 goto retry_unlock;
4609 }
4610 } else if (retry < 10) {
4611 /* Retry for IDC-unlock */
4612 qla83xx_wait_logic();
4613 retry++;
4614 ql_dbg(ql_dbg_p3p, base_vha, 0xb065,
4615 "Failed to read drv-lockid, retyring=%d\n", retry);
4616 goto retry_unlock;
4617 }
4618
4619 return;
4620
5897cb2f 4621#if 0
7d613ac6
SV		 4622 /* XXX: IDC-unlock implementation using access-control mbx */
4623 retry = 0;
4624retry_unlock2:
4625 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
4626 if (retry < 10) {
4627 /* Retry for IDC-unlock */
4628 qla83xx_wait_logic();
4629 retry++;
4630 ql_dbg(ql_dbg_p3p, base_vha, 0xb066,
4631 "Failed to release IDC lock, retyring=%d\n", retry);
4632 goto retry_unlock2;
4633 }
4634 }
4635
4636 return;
5897cb2f 4637#endif
7d613ac6
SV		 4638}
4639
4640int
4641__qla83xx_set_drv_presence(scsi_qla_host_t *vha)
4642{
4643 int rval = QLA_SUCCESS;
4644 struct qla_hw_data *ha = vha->hw;
4645 uint32_t drv_presence;
4646
4647 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
4648 if (rval == QLA_SUCCESS) {
4649 drv_presence |= (1 << ha->portnum);
4650 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
4651 drv_presence);
4652 }
4653
4654 return rval;
4655}
4656
4657int
4658qla83xx_set_drv_presence(scsi_qla_host_t *vha)
4659{
4660 int rval = QLA_SUCCESS;
4661
4662 qla83xx_idc_lock(vha, 0);
4663 rval = __qla83xx_set_drv_presence(vha);
4664 qla83xx_idc_unlock(vha, 0);
4665
4666 return rval;
4667}
4668
4669int
4670__qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
4671{
4672 int rval = QLA_SUCCESS;
4673 struct qla_hw_data *ha = vha->hw;
4674 uint32_t drv_presence;
4675
4676 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
4677 if (rval == QLA_SUCCESS) {
4678 drv_presence &= ~(1 << ha->portnum);
4679 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
4680 drv_presence);
4681 }
4682
4683 return rval;
4684}
4685
4686int
4687qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
4688{
4689 int rval = QLA_SUCCESS;
4690
4691 qla83xx_idc_lock(vha, 0);
4692 rval = __qla83xx_clear_drv_presence(vha);
4693 qla83xx_idc_unlock(vha, 0);
4694
4695 return rval;
4696}
4697
fa492630 4698static void
7d613ac6
SV		 4699qla83xx_need_reset_handler(scsi_qla_host_t *vha)
4700{
4701 struct qla_hw_data *ha = vha->hw;
4702 uint32_t drv_ack, drv_presence;
4703 unsigned long ack_timeout;
4704
4705 /* Wait for IDC ACK from all functions (DRV-ACK == DRV-PRESENCE) */
4706 ack_timeout = jiffies + (ha->fcoe_reset_timeout * HZ);
4707 while (1) {
4708 qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
4709 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
807fb6d8 4710 if ((drv_ack & drv_presence) == drv_presence)
7d613ac6
SV		 4711 break;
4712
4713 if (time_after_eq(jiffies, ack_timeout)) {
4714 ql_log(ql_log_warn, vha, 0xb067,
4715 "RESET ACK TIMEOUT! drv_presence=0x%x "
4716 "drv_ack=0x%x\n", drv_presence, drv_ack);
4717 /*
4718 * The function(s) which did not ack in time are forced
4719 * to withdraw any further participation in the IDC
4720 * reset.
4721 */
4722 if (drv_ack != drv_presence)
4723 qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
4724 drv_ack);
4725 break;
4726 }
4727
4728 qla83xx_idc_unlock(vha, 0);
4729 msleep(1000);
4730 qla83xx_idc_lock(vha, 0);
4731 }
4732
4733 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_COLD);
4734 ql_log(ql_log_info, vha, 0xb068, "HW State: COLD/RE-INIT.\n");
4735}
4736
fa492630 4737static int
7d613ac6
SV		 4738qla83xx_device_bootstrap(scsi_qla_host_t *vha)
4739{
4740 int rval = QLA_SUCCESS;
4741 uint32_t idc_control;
4742
4743 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_INITIALIZING);
4744 ql_log(ql_log_info, vha, 0xb069, "HW State: INITIALIZING.\n");
4745
4746 /* Clearing IDC-Control Graceful-Reset Bit before resetting f/w */
4747 __qla83xx_get_idc_control(vha, &idc_control);
4748 idc_control &= ~QLA83XX_IDC_GRACEFUL_RESET;
4749 __qla83xx_set_idc_control(vha, 0);
4750
4751 qla83xx_idc_unlock(vha, 0);
4752 rval = qla83xx_restart_nic_firmware(vha);
4753 qla83xx_idc_lock(vha, 0);
4754
4755 if (rval != QLA_SUCCESS) {
4756 ql_log(ql_log_fatal, vha, 0xb06a,
4757 "Failed to restart NIC f/w.\n");
4758 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_FAILED);
4759 ql_log(ql_log_info, vha, 0xb06b, "HW State: FAILED.\n");
4760 } else {
4761 ql_dbg(ql_dbg_p3p, vha, 0xb06c,
4762 "Success in restarting nic f/w.\n");
4763 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_READY);
4764 ql_log(ql_log_info, vha, 0xb06d, "HW State: READY.\n");
4765 }
4766
4767 return rval;
4768}
4769
4770/* Assumes idc_lock always held on entry */
4771int
4772qla83xx_idc_state_handler(scsi_qla_host_t *base_vha)
4773{
4774 struct qla_hw_data *ha = base_vha->hw;
4775 int rval = QLA_SUCCESS;
4776 unsigned long dev_init_timeout;
4777 uint32_t dev_state;
4778
4779 /* Wait for MAX-INIT-TIMEOUT for the device to go ready */
4780 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ);
4781
4782 while (1) {
4783
4784 if (time_after_eq(jiffies, dev_init_timeout)) {
4785 ql_log(ql_log_warn, base_vha, 0xb06e,
4786 "Initialization TIMEOUT!\n");
4787 /* Init timeout. Disable further NIC Core
4788 * communication.
4789 */
4790 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
4791 QLA8XXX_DEV_FAILED);
4792 ql_log(ql_log_info, base_vha, 0xb06f,
4793 "HW State: FAILED.\n");
4794 }
4795
4796 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4797 switch (dev_state) {
4798 case QLA8XXX_DEV_READY:
4799 if (ha->flags.nic_core_reset_owner)
4800 qla83xx_idc_audit(base_vha,
4801 IDC_AUDIT_COMPLETION);
4802 ha->flags.nic_core_reset_owner = 0;
4803 ql_dbg(ql_dbg_p3p, base_vha, 0xb070,
4804 "Reset_owner reset by 0x%x.\n",
4805 ha->portnum);
4806 goto exit;
4807 case QLA8XXX_DEV_COLD:
4808 if (ha->flags.nic_core_reset_owner)
4809 rval = qla83xx_device_bootstrap(base_vha);
4810 else {
4811 /* Wait for AEN to change device-state */
4812 qla83xx_idc_unlock(base_vha, 0);
4813 msleep(1000);
4814 qla83xx_idc_lock(base_vha, 0);
4815 }
4816 break;
4817 case QLA8XXX_DEV_INITIALIZING:
4818 /* Wait for AEN to change device-state */
4819 qla83xx_idc_unlock(base_vha, 0);
4820 msleep(1000);
4821 qla83xx_idc_lock(base_vha, 0);
4822 break;
4823 case QLA8XXX_DEV_NEED_RESET:
4824 if (!ql2xdontresethba && ha->flags.nic_core_reset_owner)
4825 qla83xx_need_reset_handler(base_vha);
4826 else {
4827 /* Wait for AEN to change device-state */
4828 qla83xx_idc_unlock(base_vha, 0);
4829 msleep(1000);
4830 qla83xx_idc_lock(base_vha, 0);
4831 }
4832 /* reset timeout value after need reset handler */
4833 dev_init_timeout = jiffies +
4834 (ha->fcoe_dev_init_timeout * HZ);
4835 break;
4836 case QLA8XXX_DEV_NEED_QUIESCENT:
4837 /* XXX: DEBUG for now */
4838 qla83xx_idc_unlock(base_vha, 0);
4839 msleep(1000);
4840 qla83xx_idc_lock(base_vha, 0);
4841 break;
4842 case QLA8XXX_DEV_QUIESCENT:
4843 /* XXX: DEBUG for now */
4844 if (ha->flags.quiesce_owner)
4845 goto exit;
4846
4847 qla83xx_idc_unlock(base_vha, 0);
4848 msleep(1000);
4849 qla83xx_idc_lock(base_vha, 0);
4850 dev_init_timeout = jiffies +
4851 (ha->fcoe_dev_init_timeout * HZ);
4852 break;
4853 case QLA8XXX_DEV_FAILED:
4854 if (ha->flags.nic_core_reset_owner)
4855 qla83xx_idc_audit(base_vha,
4856 IDC_AUDIT_COMPLETION);
4857 ha->flags.nic_core_reset_owner = 0;
4858 __qla83xx_clear_drv_presence(base_vha);
4859 qla83xx_idc_unlock(base_vha, 0);
4860 qla8xxx_dev_failed_handler(base_vha);
4861 rval = QLA_FUNCTION_FAILED;
4862 qla83xx_idc_lock(base_vha, 0);
4863 goto exit;
4864 case QLA8XXX_BAD_VALUE:
4865 qla83xx_idc_unlock(base_vha, 0);
4866 msleep(1000);
4867 qla83xx_idc_lock(base_vha, 0);
4868 break;
4869 default:
4870 ql_log(ql_log_warn, base_vha, 0xb071,
d939be3a 4871 "Unknown Device State: %x.\n", dev_state);
7d613ac6
SV		 4872 qla83xx_idc_unlock(base_vha, 0);
4873 qla8xxx_dev_failed_handler(base_vha);
4874 rval = QLA_FUNCTION_FAILED;
4875 qla83xx_idc_lock(base_vha, 0);
4876 goto exit;
4877 }
4878 }
4879
4880exit:
4881 return rval;
4882}
4883
f3ddac19
CD		 4884void
4885qla2x00_disable_board_on_pci_error(struct work_struct *work)
4886{
4887 struct qla_hw_data *ha = container_of(work, struct qla_hw_data,
4888 board_disable);
4889 struct pci_dev *pdev = ha->pdev;
4890 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4891
4892 ql_log(ql_log_warn, base_vha, 0x015b,
4893 "Disabling adapter.\n");
4894
4895 set_bit(UNLOADING, &base_vha->dpc_flags);
4896
4897 qla2x00_delete_all_vps(ha, base_vha);
4898
4899 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
4900
4901 qla2x00_dfs_remove(base_vha);
4902
4903 qla84xx_put_chip(base_vha);
4904
4905 if (base_vha->timer_active)
4906 qla2x00_stop_timer(base_vha);
4907
4908 base_vha->flags.online = 0;
4909
4910 qla2x00_destroy_deferred_work(ha);
4911
4912 /*
4913 * Do not try to stop beacon blink as it will issue a mailbox
4914 * command.
4915 */
4916 qla2x00_free_sysfs_attr(base_vha, false);
4917
4918 fc_remove_host(base_vha->host);
4919
4920 scsi_remove_host(base_vha->host);
4921
4922 base_vha->flags.init_done = 0;
4923 qla25xx_delete_queues(base_vha);
4924 qla2x00_free_irqs(base_vha);
4925 qla2x00_free_fcports(base_vha);
4926 qla2x00_mem_free(ha);
4927 qla82xx_md_free(base_vha);
4928 qla2x00_free_queues(ha);
4929
f3ddac19
CD		 4930 qla2x00_unmap_iobases(ha);
4931
4932 pci_release_selected_regions(ha->pdev, ha->bars);
f3ddac19
CD		 4933 pci_disable_pcie_error_reporting(pdev);
4934 pci_disable_device(pdev);
f3ddac19 4935
beb9e315
JL		 4936 /*
4937 * Let qla2x00_remove_one cleanup qla_hw_data on device removal.
4938 */
f3ddac19
CD		 4939}
4940
1da177e4
LT		 4941/**************************************************************************
4942* qla2x00_do_dpc
4943* This kernel thread is a task that is schedule by the interrupt handler
4944* to perform the background processing for interrupts.
4945*
4946* Notes:
4947* This task always run in the context of a kernel thread. It
4948* is kick-off by the driver's detect code and starts up
4949* up one per adapter. It immediately goes to sleep and waits for
4950* some fibre event. When either the interrupt handler or
4951* the timer routine detects a event it will one of the task
4952* bits then wake us up.
4953**************************************************************************/
4954static int
4955qla2x00_do_dpc(void *data)
4956{
e315cd28
AC		 4957 scsi_qla_host_t *base_vha;
4958 struct qla_hw_data *ha;
1da177e4 4959
e315cd28
AC		 4960 ha = (struct qla_hw_data *)data;
4961 base_vha = pci_get_drvdata(ha->pdev);
1da177e4 4962
8698a745 4963 set_user_nice(current, MIN_NICE);
1da177e4 4964
563585ec 4965 set_current_state(TASK_INTERRUPTIBLE);
39a11240 4966 while (!kthread_should_stop()) {
7c3df132
SK		 4967 ql_dbg(ql_dbg_dpc, base_vha, 0x4000,
4968 "DPC handler sleeping.\n");
1da177e4 4969
39a11240 4970 schedule();
1da177e4 4971
c142caf0
AV		 4972 if (!base_vha->flags.init_done || ha->flags.mbox_busy)
4973 goto end_loop;
1da177e4 4974
85880801 4975 if (ha->flags.eeh_busy) {
7c3df132
SK		 4976 ql_dbg(ql_dbg_dpc, base_vha, 0x4003,
4977 "eeh_busy=%d.\n", ha->flags.eeh_busy);
c142caf0 4978 goto end_loop;
85880801
AV		 4979 }
4980
1da177e4
LT		 4981 ha->dpc_active = 1;
4982
5f28d2d7
SK		 4983 ql_dbg(ql_dbg_dpc + ql_dbg_verbose, base_vha, 0x4001,
4984 "DPC handler waking up, dpc_flags=0x%lx.\n",
4985 base_vha->dpc_flags);
1da177e4 4986
e315cd28 4987 qla2x00_do_work(base_vha);
0971de7f 4988
7ec0effd
AD		 4989 if (IS_P3P_TYPE(ha)) {
4990 if (IS_QLA8044(ha)) {
4991 if (test_and_clear_bit(ISP_UNRECOVERABLE,
4992 &base_vha->dpc_flags)) {
4993 qla8044_idc_lock(ha);
4994 qla8044_wr_direct(base_vha,
4995 QLA8044_CRB_DEV_STATE_INDEX,
4996 QLA8XXX_DEV_FAILED);
4997 qla8044_idc_unlock(ha);
4998 ql_log(ql_log_info, base_vha, 0x4004,
4999 "HW State: FAILED.\n");
5000 qla8044_device_state_handler(base_vha);
5001 continue;
5002 }
5003
5004 } else {
5005 if (test_and_clear_bit(ISP_UNRECOVERABLE,
5006 &base_vha->dpc_flags)) {
5007 qla82xx_idc_lock(ha);
5008 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
5009 QLA8XXX_DEV_FAILED);
5010 qla82xx_idc_unlock(ha);
5011 ql_log(ql_log_info, base_vha, 0x0151,
5012 "HW State: FAILED.\n");
5013 qla82xx_device_state_handler(base_vha);
5014 continue;
5015 }
a9083016
GM		 5016 }
5017
5018 if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED,
5019 &base_vha->dpc_flags)) {
5020
7c3df132
SK		 5021 ql_dbg(ql_dbg_dpc, base_vha, 0x4005,
5022 "FCoE context reset scheduled.\n");
a9083016
GM		 5023 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
5024 &base_vha->dpc_flags))) {
5025 if (qla82xx_fcoe_ctx_reset(base_vha)) {
5026 /* FCoE-ctx reset failed.
5027 * Escalate to chip-reset
5028 */
5029 set_bit(ISP_ABORT_NEEDED,
5030 &base_vha->dpc_flags);
5031 }
5032 clear_bit(ABORT_ISP_ACTIVE,
5033 &base_vha->dpc_flags);
5034 }
5035
7c3df132
SK		 5036 ql_dbg(ql_dbg_dpc, base_vha, 0x4006,
5037 "FCoE context reset end.\n");
a9083016 5038 }
8ae6d9c7
GM		 5039 } else if (IS_QLAFX00(ha)) {
5040 if (test_and_clear_bit(ISP_UNRECOVERABLE,
5041 &base_vha->dpc_flags)) {
5042 ql_dbg(ql_dbg_dpc, base_vha, 0x4020,
5043 "Firmware Reset Recovery\n");
5044 if (qlafx00_reset_initialize(base_vha)) {
5045 /* Failed. Abort isp later. */
5046 if (!test_bit(UNLOADING,
f92f82d6 5047 &base_vha->dpc_flags)) {
8ae6d9c7
GM		 5048 set_bit(ISP_UNRECOVERABLE,
5049 &base_vha->dpc_flags);
5050 ql_dbg(ql_dbg_dpc, base_vha,
5051 0x4021,
5052 "Reset Recovery Failed\n");
f92f82d6 5053 }
8ae6d9c7
GM		 5054 }
5055 }
5056
5057 if (test_and_clear_bit(FX00_TARGET_SCAN,
5058 &base_vha->dpc_flags)) {
5059 ql_dbg(ql_dbg_dpc, base_vha, 0x4022,
5060 "ISPFx00 Target Scan scheduled\n");
5061 if (qlafx00_rescan_isp(base_vha)) {
5062 if (!test_bit(UNLOADING,
5063 &base_vha->dpc_flags))
5064 set_bit(ISP_UNRECOVERABLE,
5065 &base_vha->dpc_flags);
5066 ql_dbg(ql_dbg_dpc, base_vha, 0x401e,
5067 "ISPFx00 Target Scan Failed\n");
5068 }
5069 ql_dbg(ql_dbg_dpc, base_vha, 0x401f,
5070 "ISPFx00 Target Scan End\n");
5071 }
e8f5e95d
AB		 5072 if (test_and_clear_bit(FX00_HOST_INFO_RESEND,
5073 &base_vha->dpc_flags)) {
5074 ql_dbg(ql_dbg_dpc, base_vha, 0x4023,
5075 "ISPFx00 Host Info resend scheduled\n");
5076 qlafx00_fx_disc(base_vha,
5077 &base_vha->hw->mr.fcport,
5078 FXDISC_REG_HOST_INFO);
5079 }
a9083016
GM		 5080 }
5081
e315cd28
AC		 5082 if (test_and_clear_bit(ISP_ABORT_NEEDED,
5083 &base_vha->dpc_flags)) {
1da177e4 5084
7c3df132
SK		 5085 ql_dbg(ql_dbg_dpc, base_vha, 0x4007,
5086 "ISP abort scheduled.\n");
1da177e4 5087 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
e315cd28 5088 &base_vha->dpc_flags))) {
1da177e4 5089
a9083016 5090 if (ha->isp_ops->abort_isp(base_vha)) {
1da177e4
LT		 5091 /* failed. retry later */
5092 set_bit(ISP_ABORT_NEEDED,
e315cd28 5093 &base_vha->dpc_flags);
99363ef8 5094 }
e315cd28
AC		 5095 clear_bit(ABORT_ISP_ACTIVE,
5096 &base_vha->dpc_flags);
99363ef8
SJ		 5097 }
5098
7c3df132
SK		 5099 ql_dbg(ql_dbg_dpc, base_vha, 0x4008,
5100 "ISP abort end.\n");
1da177e4
LT		 5101 }
5102
a394aac8
DJ		 5103 if (test_and_clear_bit(FCPORT_UPDATE_NEEDED,
5104 &base_vha->dpc_flags)) {
e315cd28 5105 qla2x00_update_fcports(base_vha);
c9c5ced9 5106 }
d97994dc 5107
2d70c103
NB		 5108 if (test_bit(SCR_PENDING, &base_vha->dpc_flags)) {
5109 int ret;
5110 ret = qla2x00_send_change_request(base_vha, 0x3, 0);
5111 if (ret != QLA_SUCCESS)
5112 ql_log(ql_log_warn, base_vha, 0x121,
5113 "Failed to enable receiving of RSCN "
5114 "requests: 0x%x.\n", ret);
5115 clear_bit(SCR_PENDING, &base_vha->dpc_flags);
5116 }
5117
8ae6d9c7
GM		 5118 if (IS_QLAFX00(ha))
5119 goto loop_resync_check;
5120
579d12b5 5121 if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) {
7c3df132
SK		 5122 ql_dbg(ql_dbg_dpc, base_vha, 0x4009,
5123 "Quiescence mode scheduled.\n");
7ec0effd
AD		 5124 if (IS_P3P_TYPE(ha)) {
5125 if (IS_QLA82XX(ha))
5126 qla82xx_device_state_handler(base_vha);
5127 if (IS_QLA8044(ha))
5128 qla8044_device_state_handler(base_vha);
8fcd6b8b
CD		 5129 clear_bit(ISP_QUIESCE_NEEDED,
5130 &base_vha->dpc_flags);
5131 if (!ha->flags.quiesce_owner) {
5132 qla2x00_perform_loop_resync(base_vha);
7ec0effd
AD		 5133 if (IS_QLA82XX(ha)) {
5134 qla82xx_idc_lock(ha);
5135 qla82xx_clear_qsnt_ready(
5136 base_vha);
5137 qla82xx_idc_unlock(ha);
5138 } else if (IS_QLA8044(ha)) {
5139 qla8044_idc_lock(ha);
5140 qla8044_clear_qsnt_ready(
5141 base_vha);
5142 qla8044_idc_unlock(ha);
5143 }
8fcd6b8b
CD		 5144 }
5145 } else {
5146 clear_bit(ISP_QUIESCE_NEEDED,
5147 &base_vha->dpc_flags);
5148 qla2x00_quiesce_io(base_vha);
579d12b5 5149 }
7c3df132
SK		 5150 ql_dbg(ql_dbg_dpc, base_vha, 0x400a,
5151 "Quiescence mode end.\n");
579d12b5
SK		 5152 }
5153
e315cd28 5154 if (test_and_clear_bit(RESET_MARKER_NEEDED,
8ae6d9c7 5155 &base_vha->dpc_flags) &&
e315cd28 5156 (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) {
1da177e4 5157
7c3df132
SK		 5158 ql_dbg(ql_dbg_dpc, base_vha, 0x400b,
5159 "Reset marker scheduled.\n");
e315cd28
AC		 5160 qla2x00_rst_aen(base_vha);
5161 clear_bit(RESET_ACTIVE, &base_vha->dpc_flags);
7c3df132
SK		 5162 ql_dbg(ql_dbg_dpc, base_vha, 0x400c,
5163 "Reset marker end.\n");
1da177e4
LT		 5164 }
5165
5166 /* Retry each device up to login retry count */
e315cd28
AC		 5167 if ((test_and_clear_bit(RELOGIN_NEEDED,
5168 &base_vha->dpc_flags)) &&
5169 !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) &&
5170 atomic_read(&base_vha->loop_state) != LOOP_DOWN) {
1da177e4 5171
7c3df132
SK		 5172 ql_dbg(ql_dbg_dpc, base_vha, 0x400d,
5173 "Relogin scheduled.\n");
e315cd28 5174 qla2x00_relogin(base_vha);
7c3df132
SK		 5175 ql_dbg(ql_dbg_dpc, base_vha, 0x400e,
5176 "Relogin end.\n");
1da177e4 5177 }
8ae6d9c7 5178loop_resync_check:
e315cd28 5179 if (test_and_clear_bit(LOOP_RESYNC_NEEDED,
8ae6d9c7 5180 &base_vha->dpc_flags)) {
1da177e4 5181
7c3df132
SK		 5182 ql_dbg(ql_dbg_dpc, base_vha, 0x400f,
5183 "Loop resync scheduled.\n");
1da177e4
LT		 5184
5185 if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE,
e315cd28 5186 &base_vha->dpc_flags))) {
1da177e4 5187
52c82823 5188 qla2x00_loop_resync(base_vha);
1da177e4 5189
e315cd28
AC		 5190 clear_bit(LOOP_RESYNC_ACTIVE,
5191 &base_vha->dpc_flags);
1da177e4
LT		 5192 }
5193
7c3df132
SK		 5194 ql_dbg(ql_dbg_dpc, base_vha, 0x4010,
5195 "Loop resync end.\n");
1da177e4
LT		 5196 }
5197
8ae6d9c7
GM		 5198 if (IS_QLAFX00(ha))
5199 goto intr_on_check;
5200
e315cd28
AC		 5201 if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) &&
5202 atomic_read(&base_vha->loop_state) == LOOP_READY) {
5203 clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags);
5204 qla2xxx_flash_npiv_conf(base_vha);
272976ca
AV		 5205 }
5206
8ae6d9c7 5207intr_on_check:
1da177e4 5208 if (!ha->interrupts_on)
fd34f556 5209 ha->isp_ops->enable_intrs(ha);
1da177e4 5210
e315cd28 5211 if (test_and_clear_bit(BEACON_BLINK_NEEDED,
90b604f2
HM		 5212 &base_vha->dpc_flags)) {
5213 if (ha->beacon_blink_led == 1)
5214 ha->isp_ops->beacon_blink(base_vha);
5215 }
f6df144c 5216
8ae6d9c7
GM		 5217 if (!IS_QLAFX00(ha))
5218 qla2x00_do_dpc_all_vps(base_vha);
2c3dfe3f 5219
1da177e4 5220 ha->dpc_active = 0;
c142caf0 5221end_loop:
563585ec 5222 set_current_state(TASK_INTERRUPTIBLE);
1da177e4 5223 } /* End of while(1) */
563585ec 5224 __set_current_state(TASK_RUNNING);
1da177e4 5225
7c3df132
SK		 5226 ql_dbg(ql_dbg_dpc, base_vha, 0x4011,
5227 "DPC handler exiting.\n");
1da177e4
LT		 5228
5229 /*
5230 * Make sure that nobody tries to wake us up again.
5231 */
1da177e4
LT		 5232 ha->dpc_active = 0;
5233
ac280b67
AV		 5234 /* Cleanup any residual CTX SRBs. */
5235 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
5236
39a11240
CH		 5237 return 0;
5238}
5239
5240void
e315cd28 5241qla2xxx_wake_dpc(struct scsi_qla_host *vha)
39a11240 5242{
e315cd28 5243 struct qla_hw_data *ha = vha->hw;
c795c1e4
AV		 5244 struct task_struct *t = ha->dpc_thread;
5245
e315cd28 5246 if (!test_bit(UNLOADING, &vha->dpc_flags) && t)
c795c1e4 5247 wake_up_process(t);
1da177e4
LT		 5248}
5249
1da177e4
LT		 5250/*
5251* qla2x00_rst_aen
5252* Processes asynchronous reset.
5253*
5254* Input:
5255* ha = adapter block pointer.
5256*/
5257static void
e315cd28 5258qla2x00_rst_aen(scsi_qla_host_t *vha)
1da177e4 5259{
e315cd28
AC		 5260 if (vha->flags.online && !vha->flags.reset_active &&
5261 !atomic_read(&vha->loop_down_timer) &&
5262 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) {
1da177e4 5263 do {
e315cd28 5264 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
1da177e4
LT		 5265
5266 /*
5267 * Issue marker command only when we are going to start
5268 * the I/O.
5269 */
e315cd28
AC		 5270 vha->marker_needed = 1;
5271 } while (!atomic_read(&vha->loop_down_timer) &&
5272 (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)));
1da177e4
LT		 5273 }
5274}
5275
1da177e4
LT		 5276/**************************************************************************
5277* qla2x00_timer
5278*
5279* Description:
5280* One second timer
5281*
5282* Context: Interrupt
5283***************************************************************************/
2c3dfe3f 5284void
e315cd28 5285qla2x00_timer(scsi_qla_host_t *vha)
1da177e4 5286{
1da177e4 5287 unsigned long cpu_flags = 0;
1da177e4
LT		 5288 int start_dpc = 0;
5289 int index;
5290 srb_t *sp;
85880801 5291 uint16_t w;
e315cd28 5292 struct qla_hw_data *ha = vha->hw;
73208dfd 5293 struct req_que *req;
85880801 5294
a5b36321 5295 if (ha->flags.eeh_busy) {
7c3df132
SK		 5296 ql_dbg(ql_dbg_timer, vha, 0x6000,
5297 "EEH = %d, restarting timer.\n",
5298 ha->flags.eeh_busy);
a5b36321
LC		 5299 qla2x00_restart_timer(vha, WATCH_INTERVAL);
5300 return;
5301 }
5302
f3ddac19
CD		 5303 /*
5304 * Hardware read to raise pending EEH errors during mailbox waits. If
5305 * the read returns -1 then disable the board.
5306 */
5307 if (!pci_channel_offline(ha->pdev)) {
85880801 5308 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w);
c821e0d5 5309 qla2x00_check_reg16_for_disconnect(vha, w);
f3ddac19 5310 }
1da177e4 5311
cefcaba6 5312 /* Make sure qla82xx_watchdog is run only for physical port */
7ec0effd 5313 if (!vha->vp_idx && IS_P3P_TYPE(ha)) {
579d12b5
SK		 5314 if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags))
5315 start_dpc++;
7ec0effd
AD		 5316 if (IS_QLA82XX(ha))
5317 qla82xx_watchdog(vha);
5318 else if (IS_QLA8044(ha))
5319 qla8044_watchdog(vha);
579d12b5
SK		 5320 }
5321
8ae6d9c7
GM		 5322 if (!vha->vp_idx && IS_QLAFX00(ha))
5323 qlafx00_timer_routine(vha);
5324
1da177e4 5325 /* Loop down handler. */
e315cd28 5326 if (atomic_read(&vha->loop_down_timer) > 0 &&
8f7daead
GM		 5327 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) &&
5328 !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags))
e315cd28 5329 && vha->flags.online) {
1da177e4 5330
e315cd28
AC		 5331 if (atomic_read(&vha->loop_down_timer) ==
5332 vha->loop_down_abort_time) {
1da177e4 5333
7c3df132
SK		 5334 ql_log(ql_log_info, vha, 0x6008,
5335 "Loop down - aborting the queues before time expires.\n");
1da177e4 5336
e315cd28
AC		 5337 if (!IS_QLA2100(ha) && vha->link_down_timeout)
5338 atomic_set(&vha->loop_state, LOOP_DEAD);
1da177e4 5339
f08b7251
AV		 5340 /*
5341 * Schedule an ISP abort to return any FCP2-device
5342 * commands.
5343 */
2c3dfe3f 5344 /* NPIV - scan physical port only */
e315cd28 5345 if (!vha->vp_idx) {
2c3dfe3f
SJ		 5346 spin_lock_irqsave(&ha->hardware_lock,
5347 cpu_flags);
73208dfd 5348 req = ha->req_q_map[0];
2c3dfe3f 5349 for (index = 1;
8d93f550 5350 index < req->num_outstanding_cmds;
2c3dfe3f
SJ		 5351 index++) {
5352 fc_port_t *sfcp;
5353
e315cd28 5354 sp = req->outstanding_cmds[index];
2c3dfe3f
SJ		 5355 if (!sp)
5356 continue;
9ba56b95 5357 if (sp->type != SRB_SCSI_CMD)
cf53b069 5358 continue;
2c3dfe3f 5359 sfcp = sp->fcport;
f08b7251 5360 if (!(sfcp->flags & FCF_FCP2_DEVICE))
2c3dfe3f 5361 continue;
bdf79621 5362
8f7daead
GM		 5363 if (IS_QLA82XX(ha))
5364 set_bit(FCOE_CTX_RESET_NEEDED,
5365 &vha->dpc_flags);
5366 else
5367 set_bit(ISP_ABORT_NEEDED,
e315cd28 5368 &vha->dpc_flags);
2c3dfe3f
SJ		 5369 break;
5370 }
5371 spin_unlock_irqrestore(&ha->hardware_lock,
e315cd28 5372 cpu_flags);
1da177e4 5373 }
1da177e4
LT		 5374 start_dpc++;
5375 }
5376
5377 /* if the loop has been down for 4 minutes, reinit adapter */
e315cd28 5378 if (atomic_dec_and_test(&vha->loop_down_timer) != 0) {
0d6e61bc 5379 if (!(vha->device_flags & DFLG_NO_CABLE)) {
7c3df132 5380 ql_log(ql_log_warn, vha, 0x6009,
1da177e4
LT		 5381 "Loop down - aborting ISP.\n");
5382
8f7daead
GM		 5383 if (IS_QLA82XX(ha))
5384 set_bit(FCOE_CTX_RESET_NEEDED,
5385 &vha->dpc_flags);
5386 else
5387 set_bit(ISP_ABORT_NEEDED,
5388 &vha->dpc_flags);
1da177e4
LT		 5389 }
5390 }
7c3df132
SK		 5391 ql_dbg(ql_dbg_timer, vha, 0x600a,
5392 "Loop down - seconds remaining %d.\n",
5393 atomic_read(&vha->loop_down_timer));
1da177e4 5394 }
cefcaba6
SK		 5395 /* Check if beacon LED needs to be blinked for physical host only */
5396 if (!vha->vp_idx && (ha->beacon_blink_led == 1)) {
999916dc 5397 /* There is no beacon_blink function for ISP82xx */
7ec0effd 5398 if (!IS_P3P_TYPE(ha)) {
999916dc
SK		 5399 set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags);
5400 start_dpc++;
5401 }
f6df144c 5402 }
5403
550bf57d 5404 /* Process any deferred work. */
e315cd28 5405 if (!list_empty(&vha->work_list))
550bf57d
AV		 5406 start_dpc++;
5407
1da177e4 5408 /* Schedule the DPC routine if needed */
e315cd28
AC		 5409 if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) ||
5410 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) ||
5411 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags) ||
1da177e4 5412 start_dpc ||
e315cd28
AC		 5413 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) ||
5414 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) ||
a9083016
GM		 5415 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) ||
5416 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) ||
e315cd28 5417 test_bit(VP_DPC_NEEDED, &vha->dpc_flags) ||
50280c01 5418 test_bit(RELOGIN_NEEDED, &vha->dpc_flags))) {
7c3df132
SK		 5419 ql_dbg(ql_dbg_timer, vha, 0x600b,
5420 "isp_abort_needed=%d loop_resync_needed=%d "
5421 "fcport_update_needed=%d start_dpc=%d "
5422 "reset_marker_needed=%d",
5423 test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags),
5424 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags),
5425 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags),
5426 start_dpc,
5427 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags));
5428 ql_dbg(ql_dbg_timer, vha, 0x600c,
5429 "beacon_blink_needed=%d isp_unrecoverable=%d "
5430 "fcoe_ctx_reset_needed=%d vp_dpc_needed=%d "
50280c01 5431 "relogin_needed=%d.\n",
7c3df132
SK		 5432 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags),
5433 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags),
5434 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags),
5435 test_bit(VP_DPC_NEEDED, &vha->dpc_flags),
50280c01 5436 test_bit(RELOGIN_NEEDED, &vha->dpc_flags));
e315cd28 5437 qla2xxx_wake_dpc(vha);
7c3df132 5438 }
1da177e4 5439
e315cd28 5440 qla2x00_restart_timer(vha, WATCH_INTERVAL);
1da177e4
LT		 5441}
5442
5433383e
AV		 5443/* Firmware interface routines. */
5444
f73cb695 5445#define FW_BLOBS 11
5433383e
AV		 5446#define FW_ISP21XX 0
5447#define FW_ISP22XX 1
5448#define FW_ISP2300 2
5449#define FW_ISP2322 3
48c02fde 5450#define FW_ISP24XX 4
c3a2f0df 5451#define FW_ISP25XX 5
3a03eb79 5452#define FW_ISP81XX 6
a9083016 5453#define FW_ISP82XX 7
6246b8a1
GM		 5454#define FW_ISP2031 8
5455#define FW_ISP8031 9
2c5bbbb2 5456#define FW_ISP27XX 10
5433383e 5457
bb8ee499
AV		 5458#define FW_FILE_ISP21XX "ql2100_fw.bin"
5459#define FW_FILE_ISP22XX "ql2200_fw.bin"
5460#define FW_FILE_ISP2300 "ql2300_fw.bin"
5461#define FW_FILE_ISP2322 "ql2322_fw.bin"
5462#define FW_FILE_ISP24XX "ql2400_fw.bin"
c3a2f0df 5463#define FW_FILE_ISP25XX "ql2500_fw.bin"
3a03eb79 5464#define FW_FILE_ISP81XX "ql8100_fw.bin"
a9083016 5465#define FW_FILE_ISP82XX "ql8200_fw.bin"
6246b8a1
GM		 5466#define FW_FILE_ISP2031 "ql2600_fw.bin"
5467#define FW_FILE_ISP8031 "ql8300_fw.bin"
2c5bbbb2 5468#define FW_FILE_ISP27XX "ql2700_fw.bin"
f73cb695 5469
bb8ee499 5470
e1e82b6f 5471static DEFINE_MUTEX(qla_fw_lock);
5433383e
AV		 5472
5473static struct fw_blob qla_fw_blobs[FW_BLOBS] = {
bb8ee499
AV		 5474 { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, },
5475 { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, },
5476 { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, },
5477 { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, },
5478 { .name = FW_FILE_ISP24XX, },
c3a2f0df 5479 { .name = FW_FILE_ISP25XX, },
3a03eb79 5480 { .name = FW_FILE_ISP81XX, },
a9083016 5481 { .name = FW_FILE_ISP82XX, },
6246b8a1
GM		 5482 { .name = FW_FILE_ISP2031, },
5483 { .name = FW_FILE_ISP8031, },
2c5bbbb2 5484 { .name = FW_FILE_ISP27XX, },
5433383e
AV		 5485};
5486
5487struct fw_blob *
e315cd28 5488qla2x00_request_firmware(scsi_qla_host_t *vha)
5433383e 5489{
e315cd28 5490 struct qla_hw_data *ha = vha->hw;
5433383e
AV		 5491 struct fw_blob *blob;
5492
5433383e
AV		 5493 if (IS_QLA2100(ha)) {
5494 blob = &qla_fw_blobs[FW_ISP21XX];
5495 } else if (IS_QLA2200(ha)) {
5496 blob = &qla_fw_blobs[FW_ISP22XX];
48c02fde 5497 } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
5433383e 5498 blob = &qla_fw_blobs[FW_ISP2300];
48c02fde 5499 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
5433383e 5500 blob = &qla_fw_blobs[FW_ISP2322];
4d4df193 5501 } else if (IS_QLA24XX_TYPE(ha)) {
5433383e 5502 blob = &qla_fw_blobs[FW_ISP24XX];
c3a2f0df
AV		 5503 } else if (IS_QLA25XX(ha)) {
5504 blob = &qla_fw_blobs[FW_ISP25XX];
3a03eb79
AV		 5505 } else if (IS_QLA81XX(ha)) {
5506 blob = &qla_fw_blobs[FW_ISP81XX];
a9083016
GM		 5507 } else if (IS_QLA82XX(ha)) {
5508 blob = &qla_fw_blobs[FW_ISP82XX];
6246b8a1
GM		 5509 } else if (IS_QLA2031(ha)) {
5510 blob = &qla_fw_blobs[FW_ISP2031];
5511 } else if (IS_QLA8031(ha)) {
5512 blob = &qla_fw_blobs[FW_ISP8031];
2c5bbbb2
JC		 5513 } else if (IS_QLA27XX(ha)) {
5514 blob = &qla_fw_blobs[FW_ISP27XX];
8a655229
DC		 5515 } else {
5516 return NULL;
5433383e
AV		 5517 }
5518
e1e82b6f 5519 mutex_lock(&qla_fw_lock);
5433383e
AV		 5520 if (blob->fw)
5521 goto out;
5522
5523 if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) {
7c3df132
SK		 5524 ql_log(ql_log_warn, vha, 0x0063,
5525 "Failed to load firmware image (%s).\n", blob->name);
5433383e
AV		 5526 blob->fw = NULL;
5527 blob = NULL;
5528 goto out;
5529 }
5530
5531out:
e1e82b6f 5532 mutex_unlock(&qla_fw_lock);
5433383e
AV		 5533 return blob;
5534}
5535
5536static void
5537qla2x00_release_firmware(void)
5538{
5539 int idx;
5540
e1e82b6f 5541 mutex_lock(&qla_fw_lock);
5433383e 5542 for (idx = 0; idx < FW_BLOBS; idx++)
cf92549f 5543 release_firmware(qla_fw_blobs[idx].fw);
e1e82b6f 5544 mutex_unlock(&qla_fw_lock);
5433383e
AV		 5545}
5546
14e660e6
SJ		 5547static pci_ers_result_t
5548qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
5549{
85880801
AV		 5550 scsi_qla_host_t *vha = pci_get_drvdata(pdev);
5551 struct qla_hw_data *ha = vha->hw;
5552
7c3df132
SK		 5553 ql_dbg(ql_dbg_aer, vha, 0x9000,
5554 "PCI error detected, state %x.\n", state);
b9b12f73 5555
14e660e6
SJ		 5556 switch (state) {
5557 case pci_channel_io_normal:
85880801 5558 ha->flags.eeh_busy = 0;
14e660e6
SJ		 5559 return PCI_ERS_RESULT_CAN_RECOVER;
5560 case pci_channel_io_frozen:
85880801 5561 ha->flags.eeh_busy = 1;
a5b36321
LC		 5562 /* For ISP82XX complete any pending mailbox cmd */
5563 if (IS_QLA82XX(ha)) {
7190575f 5564 ha->flags.isp82xx_fw_hung = 1;
c8f6544e
CD		 5565 ql_dbg(ql_dbg_aer, vha, 0x9001, "Pci channel io frozen\n");
5566 qla82xx_clear_pending_mbx(vha);
a5b36321 5567 }
90a86fc0 5568 qla2x00_free_irqs(vha);
14e660e6 5569 pci_disable_device(pdev);
bddd2d65
LC		 5570 /* Return back all IOs */
5571 qla2x00_abort_all_cmds(vha, DID_RESET << 16);
14e660e6
SJ		 5572 return PCI_ERS_RESULT_NEED_RESET;
5573 case pci_channel_io_perm_failure:
85880801
AV		 5574 ha->flags.pci_channel_io_perm_failure = 1;
5575 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
14e660e6
SJ		 5576 return PCI_ERS_RESULT_DISCONNECT;
5577 }
5578 return PCI_ERS_RESULT_NEED_RESET;
5579}
5580
5581static pci_ers_result_t
5582qla2xxx_pci_mmio_enabled(struct pci_dev *pdev)
5583{
5584 int risc_paused = 0;
5585 uint32_t stat;
5586 unsigned long flags;
e315cd28
AC		 5587 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
5588 struct qla_hw_data *ha = base_vha->hw;
14e660e6
SJ		 5589 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
5590 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
5591
bcc5b6d3
SK		 5592 if (IS_QLA82XX(ha))
5593 return PCI_ERS_RESULT_RECOVERED;
5594
14e660e6
SJ		 5595 spin_lock_irqsave(&ha->hardware_lock, flags);
5596 if (IS_QLA2100(ha) || IS_QLA2200(ha)){
5597 stat = RD_REG_DWORD(&reg->hccr);
5598 if (stat & HCCR_RISC_PAUSE)
5599 risc_paused = 1;
5600 } else if (IS_QLA23XX(ha)) {
5601 stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
5602 if (stat & HSR_RISC_PAUSED)
5603 risc_paused = 1;
5604 } else if (IS_FWI2_CAPABLE(ha)) {
5605 stat = RD_REG_DWORD(&reg24->host_status);
5606 if (stat & HSRX_RISC_PAUSED)
5607 risc_paused = 1;
5608 }
5609 spin_unlock_irqrestore(&ha->hardware_lock, flags);
5610
5611 if (risc_paused) {
7c3df132
SK		 5612 ql_log(ql_log_info, base_vha, 0x9003,
5613 "RISC paused -- mmio_enabled, Dumping firmware.\n");
e315cd28 5614 ha->isp_ops->fw_dump(base_vha, 0);
14e660e6
SJ		 5615
5616 return PCI_ERS_RESULT_NEED_RESET;
5617 } else
5618 return PCI_ERS_RESULT_RECOVERED;
5619}
5620
fa492630
SK		 5621static uint32_t
5622qla82xx_error_recovery(scsi_qla_host_t *base_vha)
a5b36321
LC		 5623{
5624 uint32_t rval = QLA_FUNCTION_FAILED;
5625 uint32_t drv_active = 0;
5626 struct qla_hw_data *ha = base_vha->hw;
5627 int fn;
5628 struct pci_dev *other_pdev = NULL;
5629
7c3df132
SK		 5630 ql_dbg(ql_dbg_aer, base_vha, 0x9006,
5631 "Entered %s.\n", __func__);
a5b36321
LC		 5632
5633 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
5634
5635 if (base_vha->flags.online) {
5636 /* Abort all outstanding commands,
5637 * so as to be requeued later */
5638 qla2x00_abort_isp_cleanup(base_vha);
5639 }
5640
5641
5642 fn = PCI_FUNC(ha->pdev->devfn);
5643 while (fn > 0) {
5644 fn--;
7c3df132
SK		 5645 ql_dbg(ql_dbg_aer, base_vha, 0x9007,
5646 "Finding pci device at function = 0x%x.\n", fn);
a5b36321
LC		 5647 other_pdev =
5648 pci_get_domain_bus_and_slot(pci_domain_nr(ha->pdev->bus),
5649 ha->pdev->bus->number, PCI_DEVFN(PCI_SLOT(ha->pdev->devfn),
5650 fn));
5651
5652 if (!other_pdev)
5653 continue;
5654 if (atomic_read(&other_pdev->enable_cnt)) {
7c3df132
SK		 5655 ql_dbg(ql_dbg_aer, base_vha, 0x9008,
5656 "Found PCI func available and enable at 0x%x.\n",
5657 fn);
a5b36321
LC		 5658 pci_dev_put(other_pdev);
5659 break;
5660 }
5661 pci_dev_put(other_pdev);
5662 }
5663
5664 if (!fn) {
5665 /* Reset owner */
7c3df132
SK		 5666 ql_dbg(ql_dbg_aer, base_vha, 0x9009,
5667 "This devfn is reset owner = 0x%x.\n",
5668 ha->pdev->devfn);
a5b36321
LC		 5669 qla82xx_idc_lock(ha);
5670
5671 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 5672 QLA8XXX_DEV_INITIALIZING);
a5b36321
LC		 5673
5674 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION,
5675 QLA82XX_IDC_VERSION);
5676
5677 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
7c3df132
SK		 5678 ql_dbg(ql_dbg_aer, base_vha, 0x900a,
5679 "drv_active = 0x%x.\n", drv_active);
a5b36321
LC		 5680
5681 qla82xx_idc_unlock(ha);
5682 /* Reset if device is not already reset
5683 * drv_active would be 0 if a reset has already been done
5684 */
5685 if (drv_active)
5686 rval = qla82xx_start_firmware(base_vha);
5687 else
5688 rval = QLA_SUCCESS;
5689 qla82xx_idc_lock(ha);
5690
5691 if (rval != QLA_SUCCESS) {
7c3df132
SK		 5692 ql_log(ql_log_info, base_vha, 0x900b,
5693 "HW State: FAILED.\n");
a5b36321
LC		 5694 qla82xx_clear_drv_active(ha);
5695 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 5696 QLA8XXX_DEV_FAILED);
a5b36321 5697 } else {
7c3df132
SK		 5698 ql_log(ql_log_info, base_vha, 0x900c,
5699 "HW State: READY.\n");
a5b36321 5700 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 5701 QLA8XXX_DEV_READY);
a5b36321 5702 qla82xx_idc_unlock(ha);
7190575f 5703 ha->flags.isp82xx_fw_hung = 0;
a5b36321
LC		 5704 rval = qla82xx_restart_isp(base_vha);
5705 qla82xx_idc_lock(ha);
5706 /* Clear driver state register */
5707 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, 0);
5708 qla82xx_set_drv_active(base_vha);
5709 }
5710 qla82xx_idc_unlock(ha);
5711 } else {
7c3df132
SK		 5712 ql_dbg(ql_dbg_aer, base_vha, 0x900d,
5713 "This devfn is not reset owner = 0x%x.\n",
5714 ha->pdev->devfn);
a5b36321 5715 if ((qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE) ==
7d613ac6 5716 QLA8XXX_DEV_READY)) {
7190575f 5717 ha->flags.isp82xx_fw_hung = 0;
a5b36321
LC		 5718 rval = qla82xx_restart_isp(base_vha);
5719 qla82xx_idc_lock(ha);
5720 qla82xx_set_drv_active(base_vha);
5721 qla82xx_idc_unlock(ha);
5722 }
5723 }
5724 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
5725
5726 return rval;
5727}
5728
14e660e6
SJ		 5729static pci_ers_result_t
5730qla2xxx_pci_slot_reset(struct pci_dev *pdev)
5731{
5732 pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT;
e315cd28
AC		 5733 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
5734 struct qla_hw_data *ha = base_vha->hw;
90a86fc0
JC		 5735 struct rsp_que *rsp;
5736 int rc, retries = 10;
09483916 5737
7c3df132
SK		 5738 ql_dbg(ql_dbg_aer, base_vha, 0x9004,
5739 "Slot Reset.\n");
85880801 5740
90a86fc0
JC		 5741 /* Workaround: qla2xxx driver which access hardware earlier
5742 * needs error state to be pci_channel_io_online.
5743 * Otherwise mailbox command timesout.
5744 */
5745 pdev->error_state = pci_channel_io_normal;
5746
5747 pci_restore_state(pdev);
5748
8c1496bd
RL		 5749 /* pci_restore_state() clears the saved_state flag of the device
5750 * save restored state which resets saved_state flag
5751 */
5752 pci_save_state(pdev);
5753
09483916
BH		 5754 if (ha->mem_only)
5755 rc = pci_enable_device_mem(pdev);
5756 else
5757 rc = pci_enable_device(pdev);
14e660e6 5758
09483916 5759 if (rc) {
7c3df132 5760 ql_log(ql_log_warn, base_vha, 0x9005,
14e660e6 5761 "Can't re-enable PCI device after reset.\n");
a5b36321 5762 goto exit_slot_reset;
14e660e6 5763 }
14e660e6 5764
90a86fc0
JC		 5765 rsp = ha->rsp_q_map[0];
5766 if (qla2x00_request_irqs(ha, rsp))
a5b36321 5767 goto exit_slot_reset;
90a86fc0 5768
e315cd28 5769 if (ha->isp_ops->pci_config(base_vha))
a5b36321
LC		 5770 goto exit_slot_reset;
5771
5772 if (IS_QLA82XX(ha)) {
5773 if (qla82xx_error_recovery(base_vha) == QLA_SUCCESS) {
5774 ret = PCI_ERS_RESULT_RECOVERED;
5775 goto exit_slot_reset;
5776 } else
5777 goto exit_slot_reset;
5778 }
14e660e6 5779
90a86fc0
JC		 5780 while (ha->flags.mbox_busy && retries--)
5781 msleep(1000);
85880801 5782
e315cd28 5783 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
a9083016 5784 if (ha->isp_ops->abort_isp(base_vha) == QLA_SUCCESS)
14e660e6 5785 ret = PCI_ERS_RESULT_RECOVERED;
e315cd28 5786 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
14e660e6 5787
90a86fc0 5788
a5b36321 5789exit_slot_reset:
7c3df132
SK		 5790 ql_dbg(ql_dbg_aer, base_vha, 0x900e,
5791 "slot_reset return %x.\n", ret);
85880801 5792
14e660e6
SJ		 5793 return ret;
5794}
5795
5796static void
5797qla2xxx_pci_resume(struct pci_dev *pdev)
5798{
e315cd28
AC		 5799 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
5800 struct qla_hw_data *ha = base_vha->hw;
14e660e6
SJ		 5801 int ret;
5802
7c3df132
SK		 5803 ql_dbg(ql_dbg_aer, base_vha, 0x900f,
5804 "pci_resume.\n");
85880801 5805
e315cd28 5806 ret = qla2x00_wait_for_hba_online(base_vha);
14e660e6 5807 if (ret != QLA_SUCCESS) {
7c3df132
SK		 5808 ql_log(ql_log_fatal, base_vha, 0x9002,
5809 "The device failed to resume I/O from slot/link_reset.\n");
14e660e6 5810 }
85880801 5811
3e46f031
LC		 5812 pci_cleanup_aer_uncorrect_error_status(pdev);
5813
85880801 5814 ha->flags.eeh_busy = 0;
14e660e6
SJ		 5815}
5816
2d5a4c34
HM		 5817static void
5818qla83xx_disable_laser(scsi_qla_host_t *vha)
5819{
5820 uint32_t reg, data, fn;
5821 struct qla_hw_data *ha = vha->hw;
5822 struct device_reg_24xx __iomem *isp_reg = &ha->iobase->isp24;
5823
5824 /* pci func #/port # */
5825 ql_dbg(ql_dbg_init, vha, 0x004b,
5826 "Disabling Laser for hba: %p\n", vha);
5827
5828 fn = (RD_REG_DWORD(&isp_reg->ctrl_status) &
5829 (BIT_15|BIT_14|BIT_13|BIT_12));
5830
5831 fn = (fn >> 12);
5832
5833 if (fn & 1)
5834 reg = PORT_1_2031;
5835 else
5836 reg = PORT_0_2031;
5837
5838 data = LASER_OFF_2031;
5839
5840 qla83xx_wr_reg(vha, reg, data);
5841}
5842
a55b2d21 5843static const struct pci_error_handlers qla2xxx_err_handler = {
14e660e6
SJ		 5844 .error_detected = qla2xxx_pci_error_detected,
5845 .mmio_enabled = qla2xxx_pci_mmio_enabled,
5846 .slot_reset = qla2xxx_pci_slot_reset,
5847 .resume = qla2xxx_pci_resume,
5848};
5849
5433383e 5850static struct pci_device_id qla2xxx_pci_tbl[] = {
47f5e069
AV		 5851 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) },
5852 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) },
5853 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) },
5854 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) },
5855 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) },
5856 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) },
5857 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) },
5858 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) },
5859 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) },
4d4df193 5860 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) },
47f5e069
AV		 5861 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) },
5862 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) },
c3a2f0df 5863 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) },
6246b8a1 5864 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2031) },
3a03eb79 5865 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) },
a9083016 5866 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) },
650f528f 5867 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8031) },
8ae6d9c7 5868 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISPF001) },
7ec0effd 5869 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8044) },
f73cb695 5870 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2071) },
2c5bbbb2 5871 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2271) },
2b48992f 5872 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2261) },
5433383e
AV		 5873 { 0 },
5874};
5875MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl);
5876
fca29703 5877static struct pci_driver qla2xxx_pci_driver = {
cb63067a 5878 .name = QLA2XXX_DRIVER_NAME,
0a21ef1e
JB		 5879 .driver = {
5880 .owner = THIS_MODULE,
5881 },
fca29703 5882 .id_table = qla2xxx_pci_tbl,
7ee61397 5883 .probe = qla2x00_probe_one,
4c993f76 5884 .remove = qla2x00_remove_one,
e30d1756 5885 .shutdown = qla2x00_shutdown,
14e660e6 5886 .err_handler = &qla2xxx_err_handler,
fca29703
AV		 5887};
5888
75ef9de1 5889static const struct file_operations apidev_fops = {
6a03b4cd 5890 .owner = THIS_MODULE,
6038f373 5891 .llseek = noop_llseek,
6a03b4cd
HZ		 5892};
5893
1da177e4
LT		 5894/**
5895 * qla2x00_module_init - Module initialization.
5896 **/
5897static int __init
5898qla2x00_module_init(void)
5899{
fca29703
AV		 5900 int ret = 0;
5901
1da177e4 5902 /* Allocate cache for SRBs. */
354d6b21 5903 srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0,
20c2df83 5904 SLAB_HWCACHE_ALIGN, NULL);
1da177e4 5905 if (srb_cachep == NULL) {
7c3df132
SK		 5906 ql_log(ql_log_fatal, NULL, 0x0001,
5907 "Unable to allocate SRB cache...Failing load!.\n");
1da177e4
LT		 5908 return -ENOMEM;
5909 }
5910
2d70c103
NB		 5911 /* Initialize target kmem_cache and mem_pools */
5912 ret = qlt_init();
5913 if (ret < 0) {
5914 kmem_cache_destroy(srb_cachep);
5915 return ret;
5916 } else if (ret > 0) {
5917 /*
5918 * If initiator mode is explictly disabled by qlt_init(),
5919 * prevent scsi_transport_fc.c:fc_scsi_scan_rport() from
5920 * performing scsi_scan_target() during LOOP UP event.
5921 */
5922 qla2xxx_transport_functions.disable_target_scan = 1;
5923 qla2xxx_transport_vport_functions.disable_target_scan = 1;
5924 }
5925
1da177e4
LT		 5926 /* Derive version string. */
5927 strcpy(qla2x00_version_str, QLA2XXX_VERSION);
11010fec 5928 if (ql2xextended_error_logging)
0181944f
AV		 5929 strcat(qla2x00_version_str, "-debug");
5930
1c97a12a
AV		 5931 qla2xxx_transport_template =
5932 fc_attach_transport(&qla2xxx_transport_functions);
2c3dfe3f
SJ		 5933 if (!qla2xxx_transport_template) {
5934 kmem_cache_destroy(srb_cachep);
7c3df132
SK		 5935 ql_log(ql_log_fatal, NULL, 0x0002,
5936 "fc_attach_transport failed...Failing load!.\n");
2d70c103 5937 qlt_exit();
1da177e4 5938 return -ENODEV;
2c3dfe3f 5939 }
6a03b4cd
HZ		 5940
5941 apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops);
5942 if (apidev_major < 0) {
7c3df132
SK		 5943 ql_log(ql_log_fatal, NULL, 0x0003,
5944 "Unable to register char device %s.\n", QLA2XXX_APIDEV);
6a03b4cd
HZ		 5945 }
5946
2c3dfe3f
SJ		 5947 qla2xxx_transport_vport_template =
5948 fc_attach_transport(&qla2xxx_transport_vport_functions);
5949 if (!qla2xxx_transport_vport_template) {
5950 kmem_cache_destroy(srb_cachep);
2d70c103 5951 qlt_exit();
2c3dfe3f 5952 fc_release_transport(qla2xxx_transport_template);
7c3df132
SK		 5953 ql_log(ql_log_fatal, NULL, 0x0004,
5954 "fc_attach_transport vport failed...Failing load!.\n");
1da177e4 5955 return -ENODEV;
2c3dfe3f 5956 }
7c3df132
SK		 5957 ql_log(ql_log_info, NULL, 0x0005,
5958 "QLogic Fibre Channel HBA Driver: %s.\n",
fd9a29f0 5959 qla2x00_version_str);
7ee61397 5960 ret = pci_register_driver(&qla2xxx_pci_driver);
fca29703
AV		 5961 if (ret) {
5962 kmem_cache_destroy(srb_cachep);
2d70c103 5963 qlt_exit();
fca29703 5964 fc_release_transport(qla2xxx_transport_template);
2c3dfe3f 5965 fc_release_transport(qla2xxx_transport_vport_template);
7c3df132
SK		 5966 ql_log(ql_log_fatal, NULL, 0x0006,
5967 "pci_register_driver failed...ret=%d Failing load!.\n",
5968 ret);
fca29703
AV		 5969 }
5970 return ret;
1da177e4
LT		 5971}
5972
5973/**
5974 * qla2x00_module_exit - Module cleanup.
5975 **/
5976static void __exit
5977qla2x00_module_exit(void)
5978{
6a03b4cd 5979 unregister_chrdev(apidev_major, QLA2XXX_APIDEV);
7ee61397 5980 pci_unregister_driver(&qla2xxx_pci_driver);
5433383e 5981 qla2x00_release_firmware();
354d6b21 5982 kmem_cache_destroy(srb_cachep);
2d70c103 5983 qlt_exit();
a9083016
GM		 5984 if (ctx_cachep)
5985 kmem_cache_destroy(ctx_cachep);
1da177e4 5986 fc_release_transport(qla2xxx_transport_template);
2c3dfe3f 5987 fc_release_transport(qla2xxx_transport_vport_template);
1da177e4
LT		 5988}
5989
5990module_init(qla2x00_module_init);
5991module_exit(qla2x00_module_exit);
5992
5993MODULE_AUTHOR("QLogic Corporation");
5994MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver");
5995MODULE_LICENSE("GPL");
5996MODULE_VERSION(QLA2XXX_VERSION);
bb8ee499
AV		 5997MODULE_FIRMWARE(FW_FILE_ISP21XX);
5998MODULE_FIRMWARE(FW_FILE_ISP22XX);
5999MODULE_FIRMWARE(FW_FILE_ISP2300);
6000MODULE_FIRMWARE(FW_FILE_ISP2322);
6001MODULE_FIRMWARE(FW_FILE_ISP24XX);
61623fc3 6002MODULE_FIRMWARE(FW_FILE_ISP25XX);
f1458cda
SC		 6003MODULE_FIRMWARE(FW_FILE_ISP2031);
6004MODULE_FIRMWARE(FW_FILE_ISP8031);
6005MODULE_FIRMWARE(FW_FILE_ISP27XX);
Linux 6.x block layer and io_uring tree(s)