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qla2xxx: Increase the request queue size to 8K for ISP2031
[linux-2.6-block.git] / drivers / scsi / qla2xxx / qla_os.c
CommitLineData
1da177e4 1/*
fa90c54f 2 * QLogic Fibre Channel HBA Driver
bd21eaf9 3 * Copyright (c) 2003-2014 QLogic Corporation
1da177e4 4 *
fa90c54f 5 * See LICENSE.qla2xxx for copyright and licensing details.
1da177e4
LT		 6 */
7#include "qla_def.h"
8
9#include <linux/moduleparam.h>
10#include <linux/vmalloc.h>
1da177e4 11#include <linux/delay.h>
39a11240 12#include <linux/kthread.h>
e1e82b6f 13#include <linux/mutex.h>
3420d36c 14#include <linux/kobject.h>
5a0e3ad6 15#include <linux/slab.h>
1da177e4
LT		 16#include <scsi/scsi_tcq.h>
17#include <scsi/scsicam.h>
18#include <scsi/scsi_transport.h>
19#include <scsi/scsi_transport_fc.h>
20
2d70c103
NB		 21#include "qla_target.h"
22
1da177e4
LT		 23/*
24 * Driver version
25 */
26char qla2x00_version_str[40];
27
6a03b4cd
HZ		 28static int apidev_major;
29
1da177e4
LT		 30/*
31 * SRB allocation cache
32 */
e18b890b 33static struct kmem_cache *srb_cachep;
1da177e4 34
a9083016
GM		 35/*
36 * CT6 CTX allocation cache
37 */
38static struct kmem_cache *ctx_cachep;
3ce8866c
SK		 39/*
40 * error level for logging
41 */
42int ql_errlev = ql_log_all;
a9083016 43
fa492630 44static int ql2xenableclass2;
2d70c103
NB		 45module_param(ql2xenableclass2, int, S_IRUGO|S_IRUSR);
46MODULE_PARM_DESC(ql2xenableclass2,
47 "Specify if Class 2 operations are supported from the very "
48 "beginning. Default is 0 - class 2 not supported.");
49
8ae6d9c7 50
1da177e4 51int ql2xlogintimeout = 20;
f2019cb1 52module_param(ql2xlogintimeout, int, S_IRUGO);
1da177e4
LT		 53MODULE_PARM_DESC(ql2xlogintimeout,
54 "Login timeout value in seconds.");
55
a7b61842 56int qlport_down_retry;
f2019cb1 57module_param(qlport_down_retry, int, S_IRUGO);
1da177e4 58MODULE_PARM_DESC(qlport_down_retry,
900d9f98 59 "Maximum number of command retries to a port that returns "
1da177e4
LT		 60 "a PORT-DOWN status.");
61
1da177e4
LT		 62int ql2xplogiabsentdevice;
63module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR);
64MODULE_PARM_DESC(ql2xplogiabsentdevice,
65 "Option to enable PLOGI to devices that are not present after "
900d9f98 66 "a Fabric scan. This is needed for several broken switches. "
1da177e4
LT		 67 "Default is 0 - no PLOGI. 1 - perfom PLOGI.");
68
1da177e4 69int ql2xloginretrycount = 0;
f2019cb1 70module_param(ql2xloginretrycount, int, S_IRUGO);
1da177e4
LT		 71MODULE_PARM_DESC(ql2xloginretrycount,
72 "Specify an alternate value for the NVRAM login retry count.");
73
a7a167bf 74int ql2xallocfwdump = 1;
f2019cb1 75module_param(ql2xallocfwdump, int, S_IRUGO);
a7a167bf
AV		 76MODULE_PARM_DESC(ql2xallocfwdump,
77 "Option to enable allocation of memory for a firmware dump "
78 "during HBA initialization. Memory allocation requirements "
79 "vary by ISP type. Default is 1 - allocate memory.");
80
11010fec 81int ql2xextended_error_logging;
27d94035 82module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
11010fec 83MODULE_PARM_DESC(ql2xextended_error_logging,
3ce8866c
SK		 84 "Option to enable extended error logging,\n"
85 "\t\tDefault is 0 - no logging. 0x40000000 - Module Init & Probe.\n"
86 "\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n"
87 "\t\t0x08000000 - IO tracing. 0x04000000 - DPC Thread.\n"
88 "\t\t0x02000000 - Async events. 0x01000000 - Timer routines.\n"
89 "\t\t0x00800000 - User space. 0x00400000 - Task Management.\n"
90 "\t\t0x00200000 - AER/EEH. 0x00100000 - Multi Q.\n"
91 "\t\t0x00080000 - P3P Specific. 0x00040000 - Virtual Port.\n"
92 "\t\t0x00020000 - Buffer Dump. 0x00010000 - Misc.\n"
29f9f90c
CD		 93 "\t\t0x00008000 - Verbose. 0x00004000 - Target.\n"
94 "\t\t0x00002000 - Target Mgmt. 0x00001000 - Target TMF.\n"
3ce8866c 95 "\t\t0x7fffffff - For enabling all logs, can be too many logs.\n"
cfb0919c
CD		 96 "\t\t0x1e400000 - Preferred value for capturing essential "
97 "debug information (equivalent to old "
98 "ql2xextended_error_logging=1).\n"
3ce8866c 99 "\t\tDo LOGICAL OR of the value to enable more than one level");
0181944f 100
a9083016 101int ql2xshiftctondsd = 6;
f2019cb1 102module_param(ql2xshiftctondsd, int, S_IRUGO);
a9083016
GM		 103MODULE_PARM_DESC(ql2xshiftctondsd,
104 "Set to control shifting of command type processing "
105 "based on total number of SG elements.");
106
7e47e5ca 107int ql2xfdmienable=1;
de187df8 108module_param(ql2xfdmienable, int, S_IRUGO|S_IWUSR);
cca5335c 109MODULE_PARM_DESC(ql2xfdmienable,
7794a5af
FW		 110 "Enables FDMI registrations. "
111 "0 - no FDMI. Default is 1 - perform FDMI.");
cca5335c 112
50280c01
CD		 113#define MAX_Q_DEPTH 32
114static int ql2xmaxqdepth = MAX_Q_DEPTH;
df7baa50
AV		 115module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR);
116MODULE_PARM_DESC(ql2xmaxqdepth,
e92e4a8f
CD		 117 "Maximum queue depth to set for each LUN. "
118 "Default is 32.");
df7baa50 119
9e522cd8
AE		 120int ql2xenabledif = 2;
121module_param(ql2xenabledif, int, S_IRUGO);
bad75002 122MODULE_PARM_DESC(ql2xenabledif,
b97f5d0b
SM		 123 " Enable T10-CRC-DIF:\n"
124 " Default is 2.\n"
125 " 0 -- No DIF Support\n"
126 " 1 -- Enable DIF for all types\n"
127 " 2 -- Enable DIF for all types, except Type 0.\n");
bad75002 128
8cb2049c 129int ql2xenablehba_err_chk = 2;
bad75002
AE		 130module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR);
131MODULE_PARM_DESC(ql2xenablehba_err_chk,
8cb2049c 132 " Enable T10-CRC-DIF Error isolation by HBA:\n"
b97f5d0b 133 " Default is 2.\n"
8cb2049c
AE		 134 " 0 -- Error isolation disabled\n"
135 " 1 -- Error isolation enabled only for DIX Type 0\n"
136 " 2 -- Error isolation enabled for all Types\n");
bad75002 137
e5896bd5 138int ql2xiidmaenable=1;
f2019cb1 139module_param(ql2xiidmaenable, int, S_IRUGO);
e5896bd5
AV		 140MODULE_PARM_DESC(ql2xiidmaenable,
141 "Enables iIDMA settings "
142 "Default is 1 - perform iIDMA. 0 - no iIDMA.");
143
73208dfd 144int ql2xmaxqueues = 1;
f2019cb1 145module_param(ql2xmaxqueues, int, S_IRUGO);
73208dfd
AC		 146MODULE_PARM_DESC(ql2xmaxqueues,
147 "Enables MQ settings "
ae68230c
JP		 148 "Default is 1 for single queue. Set it to number "
149 "of queues in MQ mode.");
68ca949c
AC		 150
151int ql2xmultique_tag;
f2019cb1 152module_param(ql2xmultique_tag, int, S_IRUGO);
68ca949c
AC		 153MODULE_PARM_DESC(ql2xmultique_tag,
154 "Enables CPU affinity settings for the driver "
155 "Default is 0 for no affinity of request and response IO. "
156 "Set it to 1 to turn on the cpu affinity.");
e337d907
AV		 157
158int ql2xfwloadbin;
86e45bf6 159module_param(ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
e337d907 160MODULE_PARM_DESC(ql2xfwloadbin,
7c3df132
SK		 161 "Option to specify location from which to load ISP firmware:.\n"
162 " 2 -- load firmware via the request_firmware() (hotplug).\n"
e337d907
AV		 163 " interface.\n"
164 " 1 -- load firmware from flash.\n"
165 " 0 -- use default semantics.\n");
166
ae97c91e 167int ql2xetsenable;
f2019cb1 168module_param(ql2xetsenable, int, S_IRUGO);
ae97c91e
AV		 169MODULE_PARM_DESC(ql2xetsenable,
170 "Enables firmware ETS burst."
171 "Default is 0 - skip ETS enablement.");
172
6907869d 173int ql2xdbwr = 1;
86e45bf6 174module_param(ql2xdbwr, int, S_IRUGO|S_IWUSR);
a9083016 175MODULE_PARM_DESC(ql2xdbwr,
08de2844
GM		 176 "Option to specify scheme for request queue posting.\n"
177 " 0 -- Regular doorbell.\n"
178 " 1 -- CAMRAM doorbell (faster).\n");
a9083016 179
f4c496c1 180int ql2xtargetreset = 1;
f2019cb1 181module_param(ql2xtargetreset, int, S_IRUGO);
f4c496c1
GM		 182MODULE_PARM_DESC(ql2xtargetreset,
183 "Enable target reset."
184 "Default is 1 - use hw defaults.");
185
4da26e16 186int ql2xgffidenable;
f2019cb1 187module_param(ql2xgffidenable, int, S_IRUGO);
4da26e16
CD		 188MODULE_PARM_DESC(ql2xgffidenable,
189 "Enables GFF_ID checks of port type. "
190 "Default is 0 - Do not use GFF_ID information.");
a9083016 191
3822263e 192int ql2xasynctmfenable;
f2019cb1 193module_param(ql2xasynctmfenable, int, S_IRUGO);
3822263e
MI		 194MODULE_PARM_DESC(ql2xasynctmfenable,
195 "Enables issue of TM IOCBs asynchronously via IOCB mechanism"
196 "Default is 0 - Issue TM IOCBs via mailbox mechanism.");
ed0de87c
GM		 197
198int ql2xdontresethba;
86e45bf6 199module_param(ql2xdontresethba, int, S_IRUGO|S_IWUSR);
ed0de87c 200MODULE_PARM_DESC(ql2xdontresethba,
08de2844
GM		 201 "Option to specify reset behaviour.\n"
202 " 0 (Default) -- Reset on failure.\n"
203 " 1 -- Do not reset on failure.\n");
ed0de87c 204
1abf635d
HR		 205uint64_t ql2xmaxlun = MAX_LUNS;
206module_param(ql2xmaxlun, ullong, S_IRUGO);
82515920
AV		 207MODULE_PARM_DESC(ql2xmaxlun,
208 "Defines the maximum LU number to register with the SCSI "
209 "midlayer. Default is 65535.");
210
08de2844
GM		 211int ql2xmdcapmask = 0x1F;
212module_param(ql2xmdcapmask, int, S_IRUGO);
213MODULE_PARM_DESC(ql2xmdcapmask,
214 "Set the Minidump driver capture mask level. "
6e96fa7b 215 "Default is 0x1F - Can be set to 0x3, 0x7, 0xF, 0x1F, 0x7F.");
08de2844 216
3aadff35 217int ql2xmdenable = 1;
08de2844
GM		 218module_param(ql2xmdenable, int, S_IRUGO);
219MODULE_PARM_DESC(ql2xmdenable,
220 "Enable/disable MiniDump. "
3aadff35
GM		 221 "0 - MiniDump disabled. "
222 "1 (Default) - MiniDump enabled.");
08de2844 223
1da177e4 224/*
fa2a1ce5 225 * SCSI host template entry points
1da177e4
LT		 226 */
227static int qla2xxx_slave_configure(struct scsi_device * device);
f4f051eb 228static int qla2xxx_slave_alloc(struct scsi_device *);
1e99e33a
AV		 229static int qla2xxx_scan_finished(struct Scsi_Host *, unsigned long time);
230static void qla2xxx_scan_start(struct Scsi_Host *);
f4f051eb 231static void qla2xxx_slave_destroy(struct scsi_device *);
f281233d 232static int qla2xxx_queuecommand(struct Scsi_Host *h, struct scsi_cmnd *cmd);
1da177e4
LT		 233static int qla2xxx_eh_abort(struct scsi_cmnd *);
234static int qla2xxx_eh_device_reset(struct scsi_cmnd *);
523ec773 235static int qla2xxx_eh_target_reset(struct scsi_cmnd *);
1da177e4
LT		 236static int qla2xxx_eh_bus_reset(struct scsi_cmnd *);
237static int qla2xxx_eh_host_reset(struct scsi_cmnd *);
1da177e4 238
e881a172 239static int qla2x00_change_queue_depth(struct scsi_device *, int, int);
ce7e4af7 240static int qla2x00_change_queue_type(struct scsi_device *, int);
1a2fbf18 241static void qla2x00_clear_drv_active(struct qla_hw_data *);
3491255e 242static void qla2x00_free_device(scsi_qla_host_t *);
2d5a4c34 243static void qla83xx_disable_laser(scsi_qla_host_t *vha);
ce7e4af7 244
a5326f86 245struct scsi_host_template qla2xxx_driver_template = {
1da177e4 246 .module = THIS_MODULE,
cb63067a 247 .name = QLA2XXX_DRIVER_NAME,
a5326f86 248 .queuecommand = qla2xxx_queuecommand,
fca29703
AV		 249
250 .eh_abort_handler = qla2xxx_eh_abort,
251 .eh_device_reset_handler = qla2xxx_eh_device_reset,
523ec773 252 .eh_target_reset_handler = qla2xxx_eh_target_reset,
fca29703
AV		 253 .eh_bus_reset_handler = qla2xxx_eh_bus_reset,
254 .eh_host_reset_handler = qla2xxx_eh_host_reset,
255
256 .slave_configure = qla2xxx_slave_configure,
257
258 .slave_alloc = qla2xxx_slave_alloc,
259 .slave_destroy = qla2xxx_slave_destroy,
ed677086
AV		 260 .scan_finished = qla2xxx_scan_finished,
261 .scan_start = qla2xxx_scan_start,
ce7e4af7
AV		 262 .change_queue_depth = qla2x00_change_queue_depth,
263 .change_queue_type = qla2x00_change_queue_type,
fca29703
AV		 264 .this_id = -1,
265 .cmd_per_lun = 3,
266 .use_clustering = ENABLE_CLUSTERING,
267 .sg_tablesize = SG_ALL,
268
269 .max_sectors = 0xFFFF,
afb046e2 270 .shost_attrs = qla2x00_host_attrs,
2d70c103
NB		 271
272 .supported_mode = MODE_INITIATOR,
fca29703
AV		 273};
274
1da177e4 275static struct scsi_transport_template *qla2xxx_transport_template = NULL;
2c3dfe3f 276struct scsi_transport_template *qla2xxx_transport_vport_template = NULL;
1da177e4 277
1da177e4
LT		 278/* TODO Convert to inlines
279 *
280 * Timer routines
281 */
1da177e4 282
2c3dfe3f 283__inline__ void
e315cd28 284qla2x00_start_timer(scsi_qla_host_t *vha, void *func, unsigned long interval)
1da177e4 285{
e315cd28
AC		 286 init_timer(&vha->timer);
287 vha->timer.expires = jiffies + interval * HZ;
288 vha->timer.data = (unsigned long)vha;
289 vha->timer.function = (void (*)(unsigned long))func;
290 add_timer(&vha->timer);
291 vha->timer_active = 1;
1da177e4
LT		 292}
293
294static inline void
e315cd28 295qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval)
1da177e4 296{
a9083016 297 /* Currently used for 82XX only. */
7c3df132
SK		 298 if (vha->device_flags & DFLG_DEV_FAILED) {
299 ql_dbg(ql_dbg_timer, vha, 0x600d,
300 "Device in a failed state, returning.\n");
a9083016 301 return;
7c3df132 302 }
a9083016 303
e315cd28 304 mod_timer(&vha->timer, jiffies + interval * HZ);
1da177e4
LT		 305}
306
a824ebb3 307static __inline__ void
e315cd28 308qla2x00_stop_timer(scsi_qla_host_t *vha)
1da177e4 309{
e315cd28
AC		 310 del_timer_sync(&vha->timer);
311 vha->timer_active = 0;
1da177e4
LT		 312}
313
1da177e4
LT		 314static int qla2x00_do_dpc(void *data);
315
316static void qla2x00_rst_aen(scsi_qla_host_t *);
317
73208dfd
AC		 318static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t,
319 struct req_que **, struct rsp_que **);
e30d1756 320static void qla2x00_free_fw_dump(struct qla_hw_data *);
e315cd28 321static void qla2x00_mem_free(struct qla_hw_data *);
1da177e4 322
1da177e4 323/* -------------------------------------------------------------------------- */
9a347ff4
CD		 324static int qla2x00_alloc_queues(struct qla_hw_data *ha, struct req_que *req,
325 struct rsp_que *rsp)
73208dfd 326{
7c3df132 327 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2afa19a9 328 ha->req_q_map = kzalloc(sizeof(struct req_que *) * ha->max_req_queues,
73208dfd
AC		 329 GFP_KERNEL);
330 if (!ha->req_q_map) {
7c3df132
SK		 331 ql_log(ql_log_fatal, vha, 0x003b,
332 "Unable to allocate memory for request queue ptrs.\n");
73208dfd
AC		 333 goto fail_req_map;
334 }
335
2afa19a9 336 ha->rsp_q_map = kzalloc(sizeof(struct rsp_que *) * ha->max_rsp_queues,
73208dfd
AC		 337 GFP_KERNEL);
338 if (!ha->rsp_q_map) {
7c3df132
SK		 339 ql_log(ql_log_fatal, vha, 0x003c,
340 "Unable to allocate memory for response queue ptrs.\n");
73208dfd
AC		 341 goto fail_rsp_map;
342 }
9a347ff4
CD		 343 /*
344 * Make sure we record at least the request and response queue zero in
345 * case we need to free them if part of the probe fails.
346 */
347 ha->rsp_q_map[0] = rsp;
348 ha->req_q_map[0] = req;
73208dfd
AC		 349 set_bit(0, ha->rsp_qid_map);
350 set_bit(0, ha->req_qid_map);
351 return 1;
352
353fail_rsp_map:
354 kfree(ha->req_q_map);
355 ha->req_q_map = NULL;
356fail_req_map:
357 return -ENOMEM;
358}
359
2afa19a9 360static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req)
73208dfd 361{
8ae6d9c7
GM		 362 if (IS_QLAFX00(ha)) {
363 if (req && req->ring_fx00)
364 dma_free_coherent(&ha->pdev->dev,
365 (req->length_fx00 + 1) * sizeof(request_t),
366 req->ring_fx00, req->dma_fx00);
367 } else if (req && req->ring)
73208dfd
AC		 368 dma_free_coherent(&ha->pdev->dev,
369 (req->length + 1) * sizeof(request_t),
370 req->ring, req->dma);
371
8d93f550
CD		 372 if (req)
373 kfree(req->outstanding_cmds);
374
73208dfd
AC		 375 kfree(req);
376 req = NULL;
377}
378
2afa19a9
AC		 379static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp)
380{
8ae6d9c7
GM		 381 if (IS_QLAFX00(ha)) {
382 if (rsp && rsp->ring)
383 dma_free_coherent(&ha->pdev->dev,
384 (rsp->length_fx00 + 1) * sizeof(request_t),
385 rsp->ring_fx00, rsp->dma_fx00);
386 } else if (rsp && rsp->ring) {
2afa19a9
AC		 387 dma_free_coherent(&ha->pdev->dev,
388 (rsp->length + 1) * sizeof(response_t),
389 rsp->ring, rsp->dma);
8ae6d9c7 390 }
2afa19a9
AC		 391 kfree(rsp);
392 rsp = NULL;
393}
394
73208dfd
AC		 395static void qla2x00_free_queues(struct qla_hw_data *ha)
396{
397 struct req_que *req;
398 struct rsp_que *rsp;
399 int cnt;
400
2afa19a9 401 for (cnt = 0; cnt < ha->max_req_queues; cnt++) {
73208dfd 402 req = ha->req_q_map[cnt];
2afa19a9 403 qla2x00_free_req_que(ha, req);
73208dfd 404 }
73208dfd
AC		 405 kfree(ha->req_q_map);
406 ha->req_q_map = NULL;
2afa19a9
AC		 407
408 for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) {
409 rsp = ha->rsp_q_map[cnt];
410 qla2x00_free_rsp_que(ha, rsp);
411 }
412 kfree(ha->rsp_q_map);
413 ha->rsp_q_map = NULL;
73208dfd
AC		 414}
415
68ca949c
AC		 416static int qla25xx_setup_mode(struct scsi_qla_host *vha)
417{
418 uint16_t options = 0;
419 int ques, req, ret;
420 struct qla_hw_data *ha = vha->hw;
421
7163ea81 422 if (!(ha->fw_attributes & BIT_6)) {
7c3df132
SK		 423 ql_log(ql_log_warn, vha, 0x00d8,
424 "Firmware is not multi-queue capable.\n");
7163ea81
AC		 425 goto fail;
426 }
68ca949c 427 if (ql2xmultique_tag) {
68ca949c
AC		 428 /* create a request queue for IO */
429 options |= BIT_7;
430 req = qla25xx_create_req_que(ha, options, 0, 0, -1,
431 QLA_DEFAULT_QUE_QOS);
432 if (!req) {
7c3df132
SK		 433 ql_log(ql_log_warn, vha, 0x00e0,
434 "Failed to create request queue.\n");
68ca949c
AC		 435 goto fail;
436 }
278274d5 437 ha->wq = alloc_workqueue("qla2xxx_wq", WQ_MEM_RECLAIM, 1);
68ca949c
AC		 438 vha->req = ha->req_q_map[req];
439 options |= BIT_1;
440 for (ques = 1; ques < ha->max_rsp_queues; ques++) {
441 ret = qla25xx_create_rsp_que(ha, options, 0, 0, req);
442 if (!ret) {
7c3df132
SK		 443 ql_log(ql_log_warn, vha, 0x00e8,
444 "Failed to create response queue.\n");
68ca949c
AC		 445 goto fail2;
446 }
447 }
7163ea81 448 ha->flags.cpu_affinity_enabled = 1;
7c3df132
SK		 449 ql_dbg(ql_dbg_multiq, vha, 0xc007,
450 "CPU affinity mode enalbed, "
451 "no. of response queues:%d no. of request queues:%d.\n",
452 ha->max_rsp_queues, ha->max_req_queues);
453 ql_dbg(ql_dbg_init, vha, 0x00e9,
454 "CPU affinity mode enalbed, "
455 "no. of response queues:%d no. of request queues:%d.\n",
456 ha->max_rsp_queues, ha->max_req_queues);
68ca949c
AC		 457 }
458 return 0;
459fail2:
460 qla25xx_delete_queues(vha);
7163ea81
AC		 461 destroy_workqueue(ha->wq);
462 ha->wq = NULL;
0cd33fcf 463 vha->req = ha->req_q_map[0];
68ca949c
AC		 464fail:
465 ha->mqenable = 0;
7163ea81
AC		 466 kfree(ha->req_q_map);
467 kfree(ha->rsp_q_map);
468 ha->max_req_queues = ha->max_rsp_queues = 1;
68ca949c
AC		 469 return 1;
470}
471
1da177e4 472static char *
e315cd28 473qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str)
1da177e4 474{
e315cd28 475 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 476 static char *pci_bus_modes[] = {
477 "33", "66", "100", "133",
478 };
479 uint16_t pci_bus;
480
481 strcpy(str, "PCI");
482 pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9;
483 if (pci_bus) {
484 strcat(str, "-X (");
485 strcat(str, pci_bus_modes[pci_bus]);
486 } else {
487 pci_bus = (ha->pci_attr & BIT_8) >> 8;
488 strcat(str, " (");
489 strcat(str, pci_bus_modes[pci_bus]);
490 }
491 strcat(str, " MHz)");
492
493 return (str);
494}
495
fca29703 496static char *
e315cd28 497qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str)
fca29703
AV		 498{
499 static char *pci_bus_modes[] = { "33", "66", "100", "133", };
e315cd28 500 struct qla_hw_data *ha = vha->hw;
fca29703 501 uint32_t pci_bus;
fca29703 502
62a276f8 503 if (pci_is_pcie(ha->pdev)) {
fca29703 504 char lwstr[6];
62a276f8 505 uint32_t lstat, lspeed, lwidth;
fca29703 506
62a276f8
BH		 507 pcie_capability_read_dword(ha->pdev, PCI_EXP_LNKCAP, &lstat);
508 lspeed = lstat & PCI_EXP_LNKCAP_SLS;
509 lwidth = (lstat & PCI_EXP_LNKCAP_MLW) >> 4;
fca29703
AV		 510
511 strcpy(str, "PCIe (");
49300af7
SK		 512 switch (lspeed) {
513 case 1:
c87a0d8c 514 strcat(str, "2.5GT/s ");
49300af7
SK		 515 break;
516 case 2:
c87a0d8c 517 strcat(str, "5.0GT/s ");
49300af7
SK		 518 break;
519 case 3:
520 strcat(str, "8.0GT/s ");
521 break;
522 default:
fca29703 523 strcat(str, "<unknown> ");
49300af7
SK		 524 break;
525 }
fca29703
AV		 526 snprintf(lwstr, sizeof(lwstr), "x%d)", lwidth);
527 strcat(str, lwstr);
528
529 return str;
530 }
531
532 strcpy(str, "PCI");
533 pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8;
534 if (pci_bus == 0 || pci_bus == 8) {
535 strcat(str, " (");
536 strcat(str, pci_bus_modes[pci_bus >> 3]);
537 } else {
538 strcat(str, "-X ");
539 if (pci_bus & BIT_2)
540 strcat(str, "Mode 2");
541 else
542 strcat(str, "Mode 1");
543 strcat(str, " (");
544 strcat(str, pci_bus_modes[pci_bus & ~BIT_2]);
545 }
546 strcat(str, " MHz)");
547
548 return str;
549}
550
e5f82ab8 551static char *
df57caba 552qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
1da177e4
LT		 553{
554 char un_str[10];
e315cd28 555 struct qla_hw_data *ha = vha->hw;
fa2a1ce5 556
df57caba
HM		 557 snprintf(str, size, "%d.%02d.%02d ", ha->fw_major_version,
558 ha->fw_minor_version, ha->fw_subminor_version);
1da177e4
LT		 559
560 if (ha->fw_attributes & BIT_9) {
561 strcat(str, "FLX");
562 return (str);
563 }
564
565 switch (ha->fw_attributes & 0xFF) {
566 case 0x7:
567 strcat(str, "EF");
568 break;
569 case 0x17:
570 strcat(str, "TP");
571 break;
572 case 0x37:
573 strcat(str, "IP");
574 break;
575 case 0x77:
576 strcat(str, "VI");
577 break;
578 default:
579 sprintf(un_str, "(%x)", ha->fw_attributes);
580 strcat(str, un_str);
581 break;
582 }
583 if (ha->fw_attributes & 0x100)
584 strcat(str, "X");
585
586 return (str);
587}
588
e5f82ab8 589static char *
df57caba 590qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
fca29703 591{
e315cd28 592 struct qla_hw_data *ha = vha->hw;
f0883ac6 593
df57caba 594 snprintf(str, size, "%d.%02d.%02d (%x)", ha->fw_major_version,
3a03eb79 595 ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes);
fca29703 596 return str;
fca29703
AV		 597}
598
9ba56b95
GM		 599void
600qla2x00_sp_free_dma(void *vha, void *ptr)
fca29703 601{
9ba56b95
GM		 602 srb_t *sp = (srb_t *)ptr;
603 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
604 struct qla_hw_data *ha = sp->fcport->vha->hw;
605 void *ctx = GET_CMD_CTX_SP(sp);
fca29703 606
9ba56b95
GM		 607 if (sp->flags & SRB_DMA_VALID) {
608 scsi_dma_unmap(cmd);
609 sp->flags &= ~SRB_DMA_VALID;
7c3df132 610 }
fca29703 611
9ba56b95
GM		 612 if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
613 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
614 scsi_prot_sg_count(cmd), cmd->sc_data_direction);
615 sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
616 }
617
618 if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
619 /* List assured to be having elements */
f83adb61 620 qla2x00_clean_dsd_pool(ha, sp, NULL);
9ba56b95
GM		 621 sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
622 }
623
624 if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
625 dma_pool_free(ha->dl_dma_pool, ctx,
626 ((struct crc_context *)ctx)->crc_ctx_dma);
627 sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
628 }
629
630 if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
631 struct ct6_dsd *ctx1 = (struct ct6_dsd *)ctx;
fca29703 632
9ba56b95
GM		 633 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd,
634 ctx1->fcp_cmnd_dma);
635 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list);
636 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt;
637 ha->gbl_dsd_avail += ctx1->dsd_use_cnt;
638 mempool_free(ctx1, ha->ctx_mempool);
639 ctx1 = NULL;
640 }
641
642 CMD_SP(cmd) = NULL;
b00ee7d7 643 qla2x00_rel_sp(sp->fcport->vha, sp);
9ba56b95
GM		 644}
645
14b06808 646static void
9ba56b95
GM		 647qla2x00_sp_compl(void *data, void *ptr, int res)
648{
649 struct qla_hw_data *ha = (struct qla_hw_data *)data;
650 srb_t *sp = (srb_t *)ptr;
651 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
652
653 cmd->result = res;
654
655 if (atomic_read(&sp->ref_count) == 0) {
656 ql_dbg(ql_dbg_io, sp->fcport->vha, 0x3015,
657 "SP reference-count to ZERO -- sp=%p cmd=%p.\n",
658 sp, GET_CMD_SP(sp));
659 if (ql2xextended_error_logging & ql_dbg_io)
660 BUG();
661 return;
662 }
663 if (!atomic_dec_and_test(&sp->ref_count))
664 return;
665
666 qla2x00_sp_free_dma(ha, sp);
667 cmd->scsi_done(cmd);
fca29703
AV		 668}
669
8ae6d9c7
GM		 670/* If we are SP1 here, we need to still take and release the host_lock as SP1
671 * does not have the changes necessary to avoid taking host->host_lock.
672 */
1da177e4 673static int
f5e3e40b 674qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
fca29703 675{
134ae078 676 scsi_qla_host_t *vha = shost_priv(host);
fca29703 677 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
19a7b4ae 678 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
e315cd28
AC		 679 struct qla_hw_data *ha = vha->hw;
680 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
fca29703
AV		 681 srb_t *sp;
682 int rval;
683
85880801 684 if (ha->flags.eeh_busy) {
7c3df132 685 if (ha->flags.pci_channel_io_perm_failure) {
5f28d2d7 686 ql_dbg(ql_dbg_aer, vha, 0x9010,
7c3df132
SK		 687 "PCI Channel IO permanent failure, exiting "
688 "cmd=%p.\n", cmd);
b9b12f73 689 cmd->result = DID_NO_CONNECT << 16;
7c3df132 690 } else {
5f28d2d7 691 ql_dbg(ql_dbg_aer, vha, 0x9011,
7c3df132 692 "EEH_Busy, Requeuing the cmd=%p.\n", cmd);
85880801 693 cmd->result = DID_REQUEUE << 16;
7c3df132 694 }
14e660e6
SJ		 695 goto qc24_fail_command;
696 }
697
19a7b4ae
JSEC		 698 rval = fc_remote_port_chkready(rport);
699 if (rval) {
700 cmd->result = rval;
5f28d2d7 701 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3003,
7c3df132
SK		 702 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
703 cmd, rval);
fca29703
AV		 704 goto qc24_fail_command;
705 }
706
bad75002
AE		 707 if (!vha->flags.difdix_supported &&
708 scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) {
7c3df132
SK		 709 ql_dbg(ql_dbg_io, vha, 0x3004,
710 "DIF Cap not reg, fail DIF capable cmd's:%p.\n",
711 cmd);
bad75002
AE		 712 cmd->result = DID_NO_CONNECT << 16;
713 goto qc24_fail_command;
714 }
aa651be8
CD		 715
716 if (!fcport) {
717 cmd->result = DID_NO_CONNECT << 16;
718 goto qc24_fail_command;
719 }
720
fca29703
AV		 721 if (atomic_read(&fcport->state) != FCS_ONLINE) {
722 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
38170fa8 723 atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
7c3df132
SK		 724 ql_dbg(ql_dbg_io, vha, 0x3005,
725 "Returning DNC, fcport_state=%d loop_state=%d.\n",
726 atomic_read(&fcport->state),
727 atomic_read(&base_vha->loop_state));
fca29703
AV		 728 cmd->result = DID_NO_CONNECT << 16;
729 goto qc24_fail_command;
730 }
7b594131 731 goto qc24_target_busy;
fca29703
AV		 732 }
733
e05fe292
CD		 734 /*
735 * Return target busy if we've received a non-zero retry_delay_timer
736 * in a FCP_RSP.
737 */
738 if (time_after(jiffies, fcport->retry_delay_timestamp))
739 fcport->retry_delay_timestamp = 0;
740 else
741 goto qc24_target_busy;
742
b00ee7d7 743 sp = qla2x00_get_sp(vha, fcport, GFP_ATOMIC);
50280c01 744 if (!sp)
f5e3e40b 745 goto qc24_host_busy;
fca29703 746
9ba56b95
GM		 747 sp->u.scmd.cmd = cmd;
748 sp->type = SRB_SCSI_CMD;
749 atomic_set(&sp->ref_count, 1);
750 CMD_SP(cmd) = (void *)sp;
751 sp->free = qla2x00_sp_free_dma;
752 sp->done = qla2x00_sp_compl;
753
e315cd28 754 rval = ha->isp_ops->start_scsi(sp);
7c3df132 755 if (rval != QLA_SUCCESS) {
53016ed3 756 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3013,
7c3df132 757 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
fca29703 758 goto qc24_host_busy_free_sp;
7c3df132 759 }
fca29703 760
fca29703
AV		 761 return 0;
762
763qc24_host_busy_free_sp:
9ba56b95 764 qla2x00_sp_free_dma(ha, sp);
fca29703 765
f5e3e40b 766qc24_host_busy:
fca29703
AV		 767 return SCSI_MLQUEUE_HOST_BUSY;
768
7b594131
MC		 769qc24_target_busy:
770 return SCSI_MLQUEUE_TARGET_BUSY;
771
fca29703 772qc24_fail_command:
f5e3e40b 773 cmd->scsi_done(cmd);
fca29703
AV		 774
775 return 0;
776}
777
1da177e4
LT		 778/*
779 * qla2x00_eh_wait_on_command
780 * Waits for the command to be returned by the Firmware for some
781 * max time.
782 *
783 * Input:
1da177e4 784 * cmd = Scsi Command to wait on.
1da177e4
LT		 785 *
786 * Return:
787 * Not Found : 0
788 * Found : 1
789 */
790static int
e315cd28 791qla2x00_eh_wait_on_command(struct scsi_cmnd *cmd)
1da177e4 792{
fe74c71f 793#define ABORT_POLLING_PERIOD 1000
478c3b03 794#define ABORT_WAIT_ITER ((2 * 1000) / (ABORT_POLLING_PERIOD))
f4f051eb 795 unsigned long wait_iter = ABORT_WAIT_ITER;
85880801
AV		 796 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
797 struct qla_hw_data *ha = vha->hw;
f4f051eb 798 int ret = QLA_SUCCESS;
1da177e4 799
85880801 800 if (unlikely(pci_channel_offline(ha->pdev)) || ha->flags.eeh_busy) {
7c3df132
SK		 801 ql_dbg(ql_dbg_taskm, vha, 0x8005,
802 "Return:eh_wait.\n");
85880801
AV		 803 return ret;
804 }
805
d970432c 806 while (CMD_SP(cmd) && wait_iter--) {
fe74c71f 807 msleep(ABORT_POLLING_PERIOD);
f4f051eb 808 }
809 if (CMD_SP(cmd))
810 ret = QLA_FUNCTION_FAILED;
1da177e4 811
f4f051eb 812 return ret;
1da177e4
LT		 813}
814
815/*
816 * qla2x00_wait_for_hba_online
fa2a1ce5 817 * Wait till the HBA is online after going through
1da177e4
LT		 818 * <= MAX_RETRIES_OF_ISP_ABORT or
819 * finally HBA is disabled ie marked offline
820 *
821 * Input:
822 * ha - pointer to host adapter structure
fa2a1ce5
AV		 823 *
824 * Note:
1da177e4
LT		 825 * Does context switching-Release SPIN_LOCK
826 * (if any) before calling this routine.
827 *
828 * Return:
829 * Success (Adapter is online) : 0
830 * Failed (Adapter is offline/disabled) : 1
831 */
854165f4 832int
e315cd28 833qla2x00_wait_for_hba_online(scsi_qla_host_t *vha)
1da177e4 834{
fca29703
AV		 835 int return_status;
836 unsigned long wait_online;
e315cd28
AC		 837 struct qla_hw_data *ha = vha->hw;
838 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4 839
fa2a1ce5 840 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ);
e315cd28
AC		 841 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
842 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
843 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
844 ha->dpc_active) && time_before(jiffies, wait_online)) {
1da177e4
LT		 845
846 msleep(1000);
847 }
e315cd28 848 if (base_vha->flags.online)
fa2a1ce5 849 return_status = QLA_SUCCESS;
1da177e4
LT		 850 else
851 return_status = QLA_FUNCTION_FAILED;
852
1da177e4
LT		 853 return (return_status);
854}
855
86fbee86 856/*
638a1a01
SC		 857 * qla2x00_wait_for_hba_ready
858 * Wait till the HBA is ready before doing driver unload
86fbee86
LC		 859 *
860 * Input:
861 * ha - pointer to host adapter structure
862 *
863 * Note:
864 * Does context switching-Release SPIN_LOCK
865 * (if any) before calling this routine.
866 *
86fbee86 867 */
638a1a01
SC		 868static void
869qla2x00_wait_for_hba_ready(scsi_qla_host_t *vha)
86fbee86 870{
86fbee86 871 struct qla_hw_data *ha = vha->hw;
86fbee86 872
9d35894d
SC		 873 while (((qla2x00_reset_active(vha)) || ha->dpc_active ||
874 ha->flags.mbox_busy) ||
875 test_bit(FX00_RESET_RECOVERY, &vha->dpc_flags) ||
876 test_bit(FX00_TARGET_SCAN, &vha->dpc_flags))
86fbee86 877 msleep(1000);
86fbee86
LC		 878}
879
2533cf67
LC		 880int
881qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha)
882{
883 int return_status;
884 unsigned long wait_reset;
885 struct qla_hw_data *ha = vha->hw;
886 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
887
888 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ);
889 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
890 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
891 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
892 ha->dpc_active) && time_before(jiffies, wait_reset)) {
893
894 msleep(1000);
895
896 if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) &&
897 ha->flags.chip_reset_done)
898 break;
899 }
900 if (ha->flags.chip_reset_done)
901 return_status = QLA_SUCCESS;
902 else
903 return_status = QLA_FUNCTION_FAILED;
904
905 return return_status;
906}
907
083a469d
GM		 908static void
909sp_get(struct srb *sp)
910{
911 atomic_inc(&sp->ref_count);
912}
913
1da177e4
LT		 914/**************************************************************************
915* qla2xxx_eh_abort
916*
917* Description:
918* The abort function will abort the specified command.
919*
920* Input:
921* cmd = Linux SCSI command packet to be aborted.
922*
923* Returns:
924* Either SUCCESS or FAILED.
925*
926* Note:
2ea00202 927* Only return FAILED if command not returned by firmware.
1da177e4 928**************************************************************************/
e5f82ab8 929static int
1da177e4
LT		 930qla2xxx_eh_abort(struct scsi_cmnd *cmd)
931{
e315cd28 932 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
f4f051eb 933 srb_t *sp;
4e98d3b8 934 int ret;
9cb78c16
HR		 935 unsigned int id;
936 uint64_t lun;
18e144d3 937 unsigned long flags;
f934c9d0 938 int rval, wait = 0;
e315cd28 939 struct qla_hw_data *ha = vha->hw;
1da177e4 940
f4f051eb 941 if (!CMD_SP(cmd))
2ea00202 942 return SUCCESS;
1da177e4 943
4e98d3b8
AV		 944 ret = fc_block_scsi_eh(cmd);
945 if (ret != 0)
946 return ret;
947 ret = SUCCESS;
948
f4f051eb 949 id = cmd->device->id;
950 lun = cmd->device->lun;
1da177e4 951
e315cd28 952 spin_lock_irqsave(&ha->hardware_lock, flags);
170babc3
MC		 953 sp = (srb_t *) CMD_SP(cmd);
954 if (!sp) {
955 spin_unlock_irqrestore(&ha->hardware_lock, flags);
956 return SUCCESS;
957 }
1da177e4 958
7c3df132 959 ql_dbg(ql_dbg_taskm, vha, 0x8002,
9cb78c16 960 "Aborting from RISC nexus=%ld:%d:%llu sp=%p cmd=%p\n",
cfb0919c 961 vha->host_no, id, lun, sp, cmd);
17d98630 962
170babc3
MC		 963 /* Get a reference to the sp and drop the lock.*/
964 sp_get(sp);
083a469d 965
e315cd28 966 spin_unlock_irqrestore(&ha->hardware_lock, flags);
f934c9d0
CD		 967 rval = ha->isp_ops->abort_command(sp);
968 if (rval) {
969 if (rval == QLA_FUNCTION_PARAMETER_ERROR) {
970 /*
971 * Decrement the ref_count since we can't find the
972 * command
973 */
974 atomic_dec(&sp->ref_count);
975 ret = SUCCESS;
976 } else
977 ret = FAILED;
978
7c3df132 979 ql_dbg(ql_dbg_taskm, vha, 0x8003,
f934c9d0 980 "Abort command mbx failed cmd=%p, rval=%x.\n", cmd, rval);
170babc3 981 } else {
7c3df132 982 ql_dbg(ql_dbg_taskm, vha, 0x8004,
cfb0919c 983 "Abort command mbx success cmd=%p.\n", cmd);
170babc3
MC		 984 wait = 1;
985 }
75942064
SK		 986
987 spin_lock_irqsave(&ha->hardware_lock, flags);
f934c9d0
CD		 988 /*
989 * Clear the slot in the oustanding_cmds array if we can't find the
990 * command to reclaim the resources.
991 */
992 if (rval == QLA_FUNCTION_PARAMETER_ERROR)
993 vha->req->outstanding_cmds[sp->handle] = NULL;
9ba56b95 994 sp->done(ha, sp, 0);
75942064 995 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1da177e4 996
bc91ade9
CD		 997 /* Did the command return during mailbox execution? */
998 if (ret == FAILED && !CMD_SP(cmd))
999 ret = SUCCESS;
1000
f4f051eb 1001 /* Wait for the command to be returned. */
2ea00202 1002 if (wait) {
e315cd28 1003 if (qla2x00_eh_wait_on_command(cmd) != QLA_SUCCESS) {
7c3df132 1004 ql_log(ql_log_warn, vha, 0x8006,
cfb0919c 1005 "Abort handler timed out cmd=%p.\n", cmd);
2ea00202 1006 ret = FAILED;
f4f051eb 1007 }
1da177e4 1008 }
1da177e4 1009
7c3df132 1010 ql_log(ql_log_info, vha, 0x801c,
9cb78c16 1011 "Abort command issued nexus=%ld:%d:%llu -- %d %x.\n",
cfb0919c 1012 vha->host_no, id, lun, wait, ret);
1da177e4 1013
f4f051eb 1014 return ret;
1015}
1da177e4 1016
4d78c973 1017int
e315cd28 1018qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t,
9cb78c16 1019 uint64_t l, enum nexus_wait_type type)
f4f051eb 1020{
17d98630 1021 int cnt, match, status;
18e144d3 1022 unsigned long flags;
e315cd28 1023 struct qla_hw_data *ha = vha->hw;
73208dfd 1024 struct req_que *req;
4d78c973 1025 srb_t *sp;
9ba56b95 1026 struct scsi_cmnd *cmd;
1da177e4 1027
523ec773 1028 status = QLA_SUCCESS;
17d98630 1029
e315cd28 1030 spin_lock_irqsave(&ha->hardware_lock, flags);
67c2e93a 1031 req = vha->req;
17d98630 1032 for (cnt = 1; status == QLA_SUCCESS &&
8d93f550 1033 cnt < req->num_outstanding_cmds; cnt++) {
17d98630
AC		 1034 sp = req->outstanding_cmds[cnt];
1035 if (!sp)
523ec773 1036 continue;
9ba56b95 1037 if (sp->type != SRB_SCSI_CMD)
cf53b069 1038 continue;
17d98630
AC		 1039 if (vha->vp_idx != sp->fcport->vha->vp_idx)
1040 continue;
1041 match = 0;
9ba56b95 1042 cmd = GET_CMD_SP(sp);
17d98630
AC		 1043 switch (type) {
1044 case WAIT_HOST:
1045 match = 1;
1046 break;
1047 case WAIT_TARGET:
9ba56b95 1048 match = cmd->device->id == t;
17d98630
AC		 1049 break;
1050 case WAIT_LUN:
9ba56b95
GM		 1051 match = (cmd->device->id == t &&
1052 cmd->device->lun == l);
17d98630 1053 break;
73208dfd 1054 }
17d98630
AC		 1055 if (!match)
1056 continue;
1057
1058 spin_unlock_irqrestore(&ha->hardware_lock, flags);
9ba56b95 1059 status = qla2x00_eh_wait_on_command(cmd);
17d98630 1060 spin_lock_irqsave(&ha->hardware_lock, flags);
1da177e4 1061 }
e315cd28 1062 spin_unlock_irqrestore(&ha->hardware_lock, flags);
523ec773
AV		 1063
1064 return status;
1da177e4
LT		 1065}
1066
523ec773
AV		 1067static char *reset_errors[] = {
1068 "HBA not online",
1069 "HBA not ready",
1070 "Task management failed",
1071 "Waiting for command completions",
1072};
1da177e4 1073
e5f82ab8 1074static int
523ec773 1075__qla2xxx_eh_generic_reset(char *name, enum nexus_wait_type type,
9cb78c16 1076 struct scsi_cmnd *cmd, int (*do_reset)(struct fc_port *, uint64_t, int))
1da177e4 1077{
e315cd28 1078 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
bdf79621 1079 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
523ec773 1080 int err;
1da177e4 1081
7c3df132 1082 if (!fcport) {
523ec773 1083 return FAILED;
7c3df132 1084 }
1da177e4 1085
4e98d3b8
AV		 1086 err = fc_block_scsi_eh(cmd);
1087 if (err != 0)
1088 return err;
1089
7c3df132 1090 ql_log(ql_log_info, vha, 0x8009,
9cb78c16 1091 "%s RESET ISSUED nexus=%ld:%d:%llu cmd=%p.\n", name, vha->host_no,
7c3df132 1092 cmd->device->id, cmd->device->lun, cmd);
1da177e4 1093
523ec773 1094 err = 0;
7c3df132
SK		 1095 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1096 ql_log(ql_log_warn, vha, 0x800a,
1097 "Wait for hba online failed for cmd=%p.\n", cmd);
523ec773 1098 goto eh_reset_failed;
7c3df132 1099 }
523ec773 1100 err = 2;
2afa19a9 1101 if (do_reset(fcport, cmd->device->lun, cmd->request->cpu + 1)
7c3df132
SK		 1102 != QLA_SUCCESS) {
1103 ql_log(ql_log_warn, vha, 0x800c,
1104 "do_reset failed for cmd=%p.\n", cmd);
523ec773 1105 goto eh_reset_failed;
7c3df132 1106 }
523ec773 1107 err = 3;
e315cd28 1108 if (qla2x00_eh_wait_for_pending_commands(vha, cmd->device->id,
7c3df132
SK		 1109 cmd->device->lun, type) != QLA_SUCCESS) {
1110 ql_log(ql_log_warn, vha, 0x800d,
d6a03581 1111 "wait for pending cmds failed for cmd=%p.\n", cmd);
523ec773 1112 goto eh_reset_failed;
7c3df132 1113 }
523ec773 1114
7c3df132 1115 ql_log(ql_log_info, vha, 0x800e,
9cb78c16 1116 "%s RESET SUCCEEDED nexus:%ld:%d:%llu cmd=%p.\n", name,
cfb0919c 1117 vha->host_no, cmd->device->id, cmd->device->lun, cmd);
523ec773
AV		 1118
1119 return SUCCESS;
1120
4d78c973 1121eh_reset_failed:
7c3df132 1122 ql_log(ql_log_info, vha, 0x800f,
9cb78c16 1123 "%s RESET FAILED: %s nexus=%ld:%d:%llu cmd=%p.\n", name,
cfb0919c
CD		 1124 reset_errors[err], vha->host_no, cmd->device->id, cmd->device->lun,
1125 cmd);
523ec773
AV		 1126 return FAILED;
1127}
1da177e4 1128
523ec773
AV		 1129static int
1130qla2xxx_eh_device_reset(struct scsi_cmnd *cmd)
1131{
e315cd28
AC		 1132 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1133 struct qla_hw_data *ha = vha->hw;
1da177e4 1134
523ec773
AV		 1135 return __qla2xxx_eh_generic_reset("DEVICE", WAIT_LUN, cmd,
1136 ha->isp_ops->lun_reset);
1da177e4
LT		 1137}
1138
1da177e4 1139static int
523ec773 1140qla2xxx_eh_target_reset(struct scsi_cmnd *cmd)
1da177e4 1141{
e315cd28
AC		 1142 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1143 struct qla_hw_data *ha = vha->hw;
1da177e4 1144
523ec773
AV		 1145 return __qla2xxx_eh_generic_reset("TARGET", WAIT_TARGET, cmd,
1146 ha->isp_ops->target_reset);
1da177e4
LT		 1147}
1148
1da177e4
LT		 1149/**************************************************************************
1150* qla2xxx_eh_bus_reset
1151*
1152* Description:
1153* The bus reset function will reset the bus and abort any executing
1154* commands.
1155*
1156* Input:
1157* cmd = Linux SCSI command packet of the command that cause the
1158* bus reset.
1159*
1160* Returns:
1161* SUCCESS/FAILURE (defined as macro in scsi.h).
1162*
1163**************************************************************************/
e5f82ab8 1164static int
1da177e4
LT		 1165qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd)
1166{
e315cd28 1167 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
bdf79621 1168 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
2c3dfe3f 1169 int ret = FAILED;
9cb78c16
HR		 1170 unsigned int id;
1171 uint64_t lun;
f4f051eb 1172
f4f051eb 1173 id = cmd->device->id;
1174 lun = cmd->device->lun;
1da177e4 1175
7c3df132 1176 if (!fcport) {
f4f051eb 1177 return ret;
7c3df132 1178 }
1da177e4 1179
4e98d3b8
AV		 1180 ret = fc_block_scsi_eh(cmd);
1181 if (ret != 0)
1182 return ret;
1183 ret = FAILED;
1184
7c3df132 1185 ql_log(ql_log_info, vha, 0x8012,
9cb78c16 1186 "BUS RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun);
1da177e4 1187
e315cd28 1188 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
7c3df132
SK		 1189 ql_log(ql_log_fatal, vha, 0x8013,
1190 "Wait for hba online failed board disabled.\n");
f4f051eb 1191 goto eh_bus_reset_done;
1da177e4
LT		 1192 }
1193
ad537689
SK		 1194 if (qla2x00_loop_reset(vha) == QLA_SUCCESS)
1195 ret = SUCCESS;
1196
f4f051eb 1197 if (ret == FAILED)
1198 goto eh_bus_reset_done;
1da177e4 1199
9a41a62b 1200 /* Flush outstanding commands. */
4d78c973 1201 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) !=
7c3df132
SK		 1202 QLA_SUCCESS) {
1203 ql_log(ql_log_warn, vha, 0x8014,
1204 "Wait for pending commands failed.\n");
9a41a62b 1205 ret = FAILED;
7c3df132 1206 }
1da177e4 1207
f4f051eb 1208eh_bus_reset_done:
7c3df132 1209 ql_log(ql_log_warn, vha, 0x802b,
9cb78c16 1210 "BUS RESET %s nexus=%ld:%d:%llu.\n",
d6a03581 1211 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1da177e4 1212
f4f051eb 1213 return ret;
1da177e4
LT		 1214}
1215
1216/**************************************************************************
1217* qla2xxx_eh_host_reset
1218*
1219* Description:
1220* The reset function will reset the Adapter.
1221*
1222* Input:
1223* cmd = Linux SCSI command packet of the command that cause the
1224* adapter reset.
1225*
1226* Returns:
1227* Either SUCCESS or FAILED.
1228*
1229* Note:
1230**************************************************************************/
e5f82ab8 1231static int
1da177e4
LT		 1232qla2xxx_eh_host_reset(struct scsi_cmnd *cmd)
1233{
e315cd28 1234 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
e315cd28 1235 struct qla_hw_data *ha = vha->hw;
2c3dfe3f 1236 int ret = FAILED;
9cb78c16
HR		 1237 unsigned int id;
1238 uint64_t lun;
e315cd28 1239 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4 1240
f4f051eb 1241 id = cmd->device->id;
1242 lun = cmd->device->lun;
f4f051eb 1243
7c3df132 1244 ql_log(ql_log_info, vha, 0x8018,
9cb78c16 1245 "ADAPTER RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun);
1da177e4 1246
63ee7072
CD		 1247 /*
1248 * No point in issuing another reset if one is active. Also do not
1249 * attempt a reset if we are updating flash.
1250 */
1251 if (qla2x00_reset_active(vha) || ha->optrom_state != QLA_SWAITING)
f4f051eb 1252 goto eh_host_reset_lock;
1da177e4 1253
e315cd28
AC		 1254 if (vha != base_vha) {
1255 if (qla2x00_vp_abort_isp(vha))
f4f051eb 1256 goto eh_host_reset_lock;
e315cd28 1257 } else {
7ec0effd 1258 if (IS_P3P_TYPE(vha->hw)) {
a9083016
GM		 1259 if (!qla82xx_fcoe_ctx_reset(vha)) {
1260 /* Ctx reset success */
1261 ret = SUCCESS;
1262 goto eh_host_reset_lock;
1263 }
1264 /* fall thru if ctx reset failed */
1265 }
68ca949c
AC		 1266 if (ha->wq)
1267 flush_workqueue(ha->wq);
1268
e315cd28 1269 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
a9083016 1270 if (ha->isp_ops->abort_isp(base_vha)) {
e315cd28
AC		 1271 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1272 /* failed. schedule dpc to try */
1273 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
1274
7c3df132
SK		 1275 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1276 ql_log(ql_log_warn, vha, 0x802a,
1277 "wait for hba online failed.\n");
e315cd28 1278 goto eh_host_reset_lock;
7c3df132 1279 }
e315cd28
AC		 1280 }
1281 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
fa2a1ce5 1282 }
1da177e4 1283
e315cd28 1284 /* Waiting for command to be returned to OS.*/
4d78c973 1285 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) ==
e315cd28 1286 QLA_SUCCESS)
f4f051eb 1287 ret = SUCCESS;
1da177e4 1288
f4f051eb 1289eh_host_reset_lock:
cfb0919c 1290 ql_log(ql_log_info, vha, 0x8017,
9cb78c16 1291 "ADAPTER RESET %s nexus=%ld:%d:%llu.\n",
cfb0919c 1292 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1da177e4 1293
f4f051eb 1294 return ret;
1295}
1da177e4
LT		 1296
1297/*
1298* qla2x00_loop_reset
1299* Issue loop reset.
1300*
1301* Input:
1302* ha = adapter block pointer.
1303*
1304* Returns:
1305* 0 = success
1306*/
a4722cf2 1307int
e315cd28 1308qla2x00_loop_reset(scsi_qla_host_t *vha)
1da177e4 1309{
0c8c39af 1310 int ret;
bdf79621 1311 struct fc_port *fcport;
e315cd28 1312 struct qla_hw_data *ha = vha->hw;
1da177e4 1313
5854771e
AB		 1314 if (IS_QLAFX00(ha)) {
1315 return qlafx00_loop_reset(vha);
1316 }
1317
f4c496c1 1318 if (ql2xtargetreset == 1 && ha->flags.enable_target_reset) {
55e5ed27
AV		 1319 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1320 if (fcport->port_type != FCT_TARGET)
1321 continue;
1322
1323 ret = ha->isp_ops->target_reset(fcport, 0, 0);
1324 if (ret != QLA_SUCCESS) {
7c3df132 1325 ql_dbg(ql_dbg_taskm, vha, 0x802c,
5854771e 1326 "Bus Reset failed: Reset=%d "
7c3df132 1327 "d_id=%x.\n", ret, fcport->d_id.b24);
55e5ed27
AV		 1328 }
1329 }
1330 }
1331
8ae6d9c7 1332
6246b8a1 1333 if (ha->flags.enable_lip_full_login && !IS_CNA_CAPABLE(ha)) {
0b7e7c53
AV		 1334 atomic_set(&vha->loop_state, LOOP_DOWN);
1335 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
1336 qla2x00_mark_all_devices_lost(vha, 0);
e315cd28 1337 ret = qla2x00_full_login_lip(vha);
0c8c39af 1338 if (ret != QLA_SUCCESS) {
7c3df132
SK		 1339 ql_dbg(ql_dbg_taskm, vha, 0x802d,
1340 "full_login_lip=%d.\n", ret);
749af3d5 1341 }
0c8c39af
AV		 1342 }
1343
0d6e61bc 1344 if (ha->flags.enable_lip_reset) {
e315cd28 1345 ret = qla2x00_lip_reset(vha);
ad537689 1346 if (ret != QLA_SUCCESS)
7c3df132
SK		 1347 ql_dbg(ql_dbg_taskm, vha, 0x802e,
1348 "lip_reset failed (%d).\n", ret);
1da177e4
LT		 1349 }
1350
1da177e4 1351 /* Issue marker command only when we are going to start the I/O */
e315cd28 1352 vha->marker_needed = 1;
1da177e4 1353
0c8c39af 1354 return QLA_SUCCESS;
1da177e4
LT		 1355}
1356
df4bf0bb 1357void
e315cd28 1358qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res)
df4bf0bb 1359{
73208dfd 1360 int que, cnt;
df4bf0bb
AV		 1361 unsigned long flags;
1362 srb_t *sp;
e315cd28 1363 struct qla_hw_data *ha = vha->hw;
73208dfd 1364 struct req_que *req;
df4bf0bb 1365
c0cb4496
AE		 1366 qlt_host_reset_handler(ha);
1367
df4bf0bb 1368 spin_lock_irqsave(&ha->hardware_lock, flags);
2afa19a9 1369 for (que = 0; que < ha->max_req_queues; que++) {
29bdccbe 1370 req = ha->req_q_map[que];
73208dfd
AC		 1371 if (!req)
1372 continue;
8d93f550
CD		 1373 if (!req->outstanding_cmds)
1374 continue;
1375 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) {
73208dfd 1376 sp = req->outstanding_cmds[cnt];
e612d465 1377 if (sp) {
73208dfd 1378 req->outstanding_cmds[cnt] = NULL;
9ba56b95 1379 sp->done(vha, sp, res);
73208dfd 1380 }
df4bf0bb
AV		 1381 }
1382 }
1383 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1384}
1385
f4f051eb 1386static int
1387qla2xxx_slave_alloc(struct scsi_device *sdev)
1da177e4 1388{
bdf79621 1389 struct fc_rport *rport = starget_to_rport(scsi_target(sdev));
1da177e4 1390
19a7b4ae 1391 if (!rport || fc_remote_port_chkready(rport))
f4f051eb 1392 return -ENXIO;
bdf79621 1393
19a7b4ae 1394 sdev->hostdata = *(fc_port_t **)rport->dd_data;
1da177e4 1395
f4f051eb 1396 return 0;
1397}
1da177e4 1398
f4f051eb 1399static int
1400qla2xxx_slave_configure(struct scsi_device *sdev)
1401{
e315cd28 1402 scsi_qla_host_t *vha = shost_priv(sdev->host);
2afa19a9 1403 struct req_que *req = vha->req;
8482e118 1404
9e522cd8
AE		 1405 if (IS_T10_PI_CAPABLE(vha->hw))
1406 blk_queue_update_dma_alignment(sdev->request_queue, 0x7);
1407
f4f051eb 1408 if (sdev->tagged_supported)
73208dfd 1409 scsi_activate_tcq(sdev, req->max_q_depth);
f4f051eb 1410 else
73208dfd 1411 scsi_deactivate_tcq(sdev, req->max_q_depth);
f4f051eb 1412 return 0;
1413}
1da177e4 1414
f4f051eb 1415static void
1416qla2xxx_slave_destroy(struct scsi_device *sdev)
1417{
1418 sdev->hostdata = NULL;
1da177e4
LT		 1419}
1420
c45dd305
GM		 1421static void qla2x00_handle_queue_full(struct scsi_device *sdev, int qdepth)
1422{
1423 fc_port_t *fcport = (struct fc_port *) sdev->hostdata;
1424
1425 if (!scsi_track_queue_full(sdev, qdepth))
1426 return;
1427
7c3df132 1428 ql_dbg(ql_dbg_io, fcport->vha, 0x3029,
9cb78c16 1429 "Queue depth adjusted-down to %d for nexus=%ld:%d:%llu.\n",
cfb0919c 1430 sdev->queue_depth, fcport->vha->host_no, sdev->id, sdev->lun);
c45dd305
GM		 1431}
1432
1433static void qla2x00_adjust_sdev_qdepth_up(struct scsi_device *sdev, int qdepth)
1434{
1435 fc_port_t *fcport = sdev->hostdata;
1436 struct scsi_qla_host *vha = fcport->vha;
c45dd305
GM		 1437 struct req_que *req = NULL;
1438
1439 req = vha->req;
1440 if (!req)
1441 return;
1442
1443 if (req->max_q_depth <= sdev->queue_depth || req->max_q_depth < qdepth)
1444 return;
1445
1446 if (sdev->ordered_tags)
1447 scsi_adjust_queue_depth(sdev, MSG_ORDERED_TAG, qdepth);
1448 else
1449 scsi_adjust_queue_depth(sdev, MSG_SIMPLE_TAG, qdepth);
1450
7c3df132 1451 ql_dbg(ql_dbg_io, vha, 0x302a,
9cb78c16 1452 "Queue depth adjusted-up to %d for nexus=%ld:%d:%llu.\n",
cfb0919c 1453 sdev->queue_depth, fcport->vha->host_no, sdev->id, sdev->lun);
c45dd305
GM		 1454}
1455
ce7e4af7 1456static int
e881a172 1457qla2x00_change_queue_depth(struct scsi_device *sdev, int qdepth, int reason)
ce7e4af7 1458{
c45dd305
GM		 1459 switch (reason) {
1460 case SCSI_QDEPTH_DEFAULT:
1461 scsi_adjust_queue_depth(sdev, scsi_get_tag_type(sdev), qdepth);
1462 break;
1463 case SCSI_QDEPTH_QFULL:
1464 qla2x00_handle_queue_full(sdev, qdepth);
1465 break;
1466 case SCSI_QDEPTH_RAMP_UP:
1467 qla2x00_adjust_sdev_qdepth_up(sdev, qdepth);
1468 break;
1469 default:
08002af2 1470 return -EOPNOTSUPP;
c45dd305 1471 }
e881a172 1472
ce7e4af7
AV		 1473 return sdev->queue_depth;
1474}
1475
1476static int
1477qla2x00_change_queue_type(struct scsi_device *sdev, int tag_type)
1478{
1479 if (sdev->tagged_supported) {
1480 scsi_set_tag_type(sdev, tag_type);
1481 if (tag_type)
1482 scsi_activate_tcq(sdev, sdev->queue_depth);
1483 else
1484 scsi_deactivate_tcq(sdev, sdev->queue_depth);
1485 } else
1486 tag_type = 0;
1487
1488 return tag_type;
1489}
1490
1da177e4
LT		 1491/**
1492 * qla2x00_config_dma_addressing() - Configure OS DMA addressing method.
1493 * @ha: HA context
1494 *
1495 * At exit, the @ha's flags.enable_64bit_addressing set to indicated
1496 * supported addressing method.
1497 */
1498static void
53303c42 1499qla2x00_config_dma_addressing(struct qla_hw_data *ha)
1da177e4 1500{
7524f9b9 1501 /* Assume a 32bit DMA mask. */
1da177e4 1502 ha->flags.enable_64bit_addressing = 0;
1da177e4 1503
6a35528a 1504 if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) {
7524f9b9
AV		 1505 /* Any upper-dword bits set? */
1506 if (MSD(dma_get_required_mask(&ha->pdev->dev)) &&
6a35528a 1507 !pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(64))) {
7524f9b9 1508 /* Ok, a 64bit DMA mask is applicable. */
1da177e4 1509 ha->flags.enable_64bit_addressing = 1;
fd34f556
AV		 1510 ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64;
1511 ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64;
7524f9b9 1512 return;
1da177e4 1513 }
1da177e4 1514 }
7524f9b9 1515
284901a9
YH		 1516 dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32));
1517 pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(32));
1da177e4
LT		 1518}
1519
fd34f556 1520static void
e315cd28 1521qla2x00_enable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1522{
1523 unsigned long flags = 0;
1524 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1525
1526 spin_lock_irqsave(&ha->hardware_lock, flags);
1527 ha->interrupts_on = 1;
1528 /* enable risc and host interrupts */
1529 WRT_REG_WORD(&reg->ictrl, ICR_EN_INT | ICR_EN_RISC);
1530 RD_REG_WORD(&reg->ictrl);
1531 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1532
1533}
1534
1535static void
e315cd28 1536qla2x00_disable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1537{
1538 unsigned long flags = 0;
1539 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1540
1541 spin_lock_irqsave(&ha->hardware_lock, flags);
1542 ha->interrupts_on = 0;
1543 /* disable risc and host interrupts */
1544 WRT_REG_WORD(&reg->ictrl, 0);
1545 RD_REG_WORD(&reg->ictrl);
1546 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1547}
1548
1549static void
e315cd28 1550qla24xx_enable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1551{
1552 unsigned long flags = 0;
1553 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1554
1555 spin_lock_irqsave(&ha->hardware_lock, flags);
1556 ha->interrupts_on = 1;
1557 WRT_REG_DWORD(&reg->ictrl, ICRX_EN_RISC_INT);
1558 RD_REG_DWORD(&reg->ictrl);
1559 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1560}
1561
1562static void
e315cd28 1563qla24xx_disable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1564{
1565 unsigned long flags = 0;
1566 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1567
124f85e6
AV		 1568 if (IS_NOPOLLING_TYPE(ha))
1569 return;
fd34f556
AV		 1570 spin_lock_irqsave(&ha->hardware_lock, flags);
1571 ha->interrupts_on = 0;
1572 WRT_REG_DWORD(&reg->ictrl, 0);
1573 RD_REG_DWORD(&reg->ictrl);
1574 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1575}
1576
706f457d
GM		 1577static int
1578qla2x00_iospace_config(struct qla_hw_data *ha)
1579{
1580 resource_size_t pio;
1581 uint16_t msix;
1582 int cpus;
1583
706f457d
GM		 1584 if (pci_request_selected_regions(ha->pdev, ha->bars,
1585 QLA2XXX_DRIVER_NAME)) {
1586 ql_log_pci(ql_log_fatal, ha->pdev, 0x0011,
1587 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
1588 pci_name(ha->pdev));
1589 goto iospace_error_exit;
1590 }
1591 if (!(ha->bars & 1))
1592 goto skip_pio;
1593
1594 /* We only need PIO for Flash operations on ISP2312 v2 chips. */
1595 pio = pci_resource_start(ha->pdev, 0);
1596 if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) {
1597 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
1598 ql_log_pci(ql_log_warn, ha->pdev, 0x0012,
1599 "Invalid pci I/O region size (%s).\n",
1600 pci_name(ha->pdev));
1601 pio = 0;
1602 }
1603 } else {
1604 ql_log_pci(ql_log_warn, ha->pdev, 0x0013,
1605 "Region #0 no a PIO resource (%s).\n",
1606 pci_name(ha->pdev));
1607 pio = 0;
1608 }
1609 ha->pio_address = pio;
1610 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014,
1611 "PIO address=%llu.\n",
1612 (unsigned long long)ha->pio_address);
1613
1614skip_pio:
1615 /* Use MMIO operations for all accesses. */
1616 if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) {
1617 ql_log_pci(ql_log_fatal, ha->pdev, 0x0015,
1618 "Region #1 not an MMIO resource (%s), aborting.\n",
1619 pci_name(ha->pdev));
1620 goto iospace_error_exit;
1621 }
1622 if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) {
1623 ql_log_pci(ql_log_fatal, ha->pdev, 0x0016,
1624 "Invalid PCI mem region size (%s), aborting.\n",
1625 pci_name(ha->pdev));
1626 goto iospace_error_exit;
1627 }
1628
1629 ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN);
1630 if (!ha->iobase) {
1631 ql_log_pci(ql_log_fatal, ha->pdev, 0x0017,
1632 "Cannot remap MMIO (%s), aborting.\n",
1633 pci_name(ha->pdev));
1634 goto iospace_error_exit;
1635 }
1636
1637 /* Determine queue resources */
1638 ha->max_req_queues = ha->max_rsp_queues = 1;
1639 if ((ql2xmaxqueues <= 1 && !ql2xmultique_tag) ||
1640 (ql2xmaxqueues > 1 && ql2xmultique_tag) ||
1641 (!IS_QLA25XX(ha) && !IS_QLA81XX(ha)))
1642 goto mqiobase_exit;
1643
1644 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3),
1645 pci_resource_len(ha->pdev, 3));
1646 if (ha->mqiobase) {
1647 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018,
1648 "MQIO Base=%p.\n", ha->mqiobase);
1649 /* Read MSIX vector size of the board */
1650 pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix);
1651 ha->msix_count = msix;
1652 /* Max queues are bounded by available msix vectors */
1653 /* queue 0 uses two msix vectors */
1654 if (ql2xmultique_tag) {
1655 cpus = num_online_cpus();
1656 ha->max_rsp_queues = (ha->msix_count - 1 > cpus) ?
1657 (cpus + 1) : (ha->msix_count - 1);
1658 ha->max_req_queues = 2;
1659 } else if (ql2xmaxqueues > 1) {
1660 ha->max_req_queues = ql2xmaxqueues > QLA_MQ_SIZE ?
1661 QLA_MQ_SIZE : ql2xmaxqueues;
1662 ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc008,
1663 "QoS mode set, max no of request queues:%d.\n",
1664 ha->max_req_queues);
1665 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0019,
1666 "QoS mode set, max no of request queues:%d.\n",
1667 ha->max_req_queues);
1668 }
1669 ql_log_pci(ql_log_info, ha->pdev, 0x001a,
1670 "MSI-X vector count: %d.\n", msix);
1671 } else
1672 ql_log_pci(ql_log_info, ha->pdev, 0x001b,
1673 "BAR 3 not enabled.\n");
1674
1675mqiobase_exit:
1676 ha->msix_count = ha->max_rsp_queues + 1;
1677 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c,
1678 "MSIX Count:%d.\n", ha->msix_count);
1679 return (0);
1680
1681iospace_error_exit:
1682 return (-ENOMEM);
1683}
1684
1685
6246b8a1
GM		 1686static int
1687qla83xx_iospace_config(struct qla_hw_data *ha)
1688{
1689 uint16_t msix;
1690 int cpus;
1691
1692 if (pci_request_selected_regions(ha->pdev, ha->bars,
1693 QLA2XXX_DRIVER_NAME)) {
1694 ql_log_pci(ql_log_fatal, ha->pdev, 0x0117,
1695 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
1696 pci_name(ha->pdev));
1697
1698 goto iospace_error_exit;
1699 }
1700
1701 /* Use MMIO operations for all accesses. */
1702 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) {
1703 ql_log_pci(ql_log_warn, ha->pdev, 0x0118,
1704 "Invalid pci I/O region size (%s).\n",
1705 pci_name(ha->pdev));
1706 goto iospace_error_exit;
1707 }
1708 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
1709 ql_log_pci(ql_log_warn, ha->pdev, 0x0119,
1710 "Invalid PCI mem region size (%s), aborting\n",
1711 pci_name(ha->pdev));
1712 goto iospace_error_exit;
1713 }
1714
1715 ha->iobase = ioremap(pci_resource_start(ha->pdev, 0), MIN_IOBASE_LEN);
1716 if (!ha->iobase) {
1717 ql_log_pci(ql_log_fatal, ha->pdev, 0x011a,
1718 "Cannot remap MMIO (%s), aborting.\n",
1719 pci_name(ha->pdev));
1720 goto iospace_error_exit;
1721 }
1722
1723 /* 64bit PCI BAR - BAR2 will correspoond to region 4 */
1724 /* 83XX 26XX always use MQ type access for queues
1725 * - mbar 2, a.k.a region 4 */
1726 ha->max_req_queues = ha->max_rsp_queues = 1;
1727 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 4),
1728 pci_resource_len(ha->pdev, 4));
1729
1730 if (!ha->mqiobase) {
1731 ql_log_pci(ql_log_fatal, ha->pdev, 0x011d,
1732 "BAR2/region4 not enabled\n");
1733 goto mqiobase_exit;
1734 }
1735
1736 ha->msixbase = ioremap(pci_resource_start(ha->pdev, 2),
1737 pci_resource_len(ha->pdev, 2));
1738 if (ha->msixbase) {
1739 /* Read MSIX vector size of the board */
1740 pci_read_config_word(ha->pdev,
1741 QLA_83XX_PCI_MSIX_CONTROL, &msix);
1742 ha->msix_count = msix;
1743 /* Max queues are bounded by available msix vectors */
1744 /* queue 0 uses two msix vectors */
1745 if (ql2xmultique_tag) {
1746 cpus = num_online_cpus();
1747 ha->max_rsp_queues = (ha->msix_count - 1 > cpus) ?
1748 (cpus + 1) : (ha->msix_count - 1);
1749 ha->max_req_queues = 2;
1750 } else if (ql2xmaxqueues > 1) {
1751 ha->max_req_queues = ql2xmaxqueues > QLA_MQ_SIZE ?
1752 QLA_MQ_SIZE : ql2xmaxqueues;
1753 ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc00c,
1754 "QoS mode set, max no of request queues:%d.\n",
1755 ha->max_req_queues);
1756 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b,
1757 "QoS mode set, max no of request queues:%d.\n",
1758 ha->max_req_queues);
1759 }
1760 ql_log_pci(ql_log_info, ha->pdev, 0x011c,
1761 "MSI-X vector count: %d.\n", msix);
1762 } else
1763 ql_log_pci(ql_log_info, ha->pdev, 0x011e,
1764 "BAR 1 not enabled.\n");
1765
1766mqiobase_exit:
1767 ha->msix_count = ha->max_rsp_queues + 1;
aa230bc5
AE		 1768
1769 qlt_83xx_iospace_config(ha);
1770
6246b8a1
GM		 1771 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011f,
1772 "MSIX Count:%d.\n", ha->msix_count);
1773 return 0;
1774
1775iospace_error_exit:
1776 return -ENOMEM;
1777}
1778
fd34f556
AV		 1779static struct isp_operations qla2100_isp_ops = {
1780 .pci_config = qla2100_pci_config,
1781 .reset_chip = qla2x00_reset_chip,
1782 .chip_diag = qla2x00_chip_diag,
1783 .config_rings = qla2x00_config_rings,
1784 .reset_adapter = qla2x00_reset_adapter,
1785 .nvram_config = qla2x00_nvram_config,
1786 .update_fw_options = qla2x00_update_fw_options,
1787 .load_risc = qla2x00_load_risc,
1788 .pci_info_str = qla2x00_pci_info_str,
1789 .fw_version_str = qla2x00_fw_version_str,
1790 .intr_handler = qla2100_intr_handler,
1791 .enable_intrs = qla2x00_enable_intrs,
1792 .disable_intrs = qla2x00_disable_intrs,
1793 .abort_command = qla2x00_abort_command,
523ec773
AV		 1794 .target_reset = qla2x00_abort_target,
1795 .lun_reset = qla2x00_lun_reset,
fd34f556
AV		 1796 .fabric_login = qla2x00_login_fabric,
1797 .fabric_logout = qla2x00_fabric_logout,
1798 .calc_req_entries = qla2x00_calc_iocbs_32,
1799 .build_iocbs = qla2x00_build_scsi_iocbs_32,
1800 .prep_ms_iocb = qla2x00_prep_ms_iocb,
1801 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
1802 .read_nvram = qla2x00_read_nvram_data,
1803 .write_nvram = qla2x00_write_nvram_data,
1804 .fw_dump = qla2100_fw_dump,
1805 .beacon_on = NULL,
1806 .beacon_off = NULL,
1807 .beacon_blink = NULL,
1808 .read_optrom = qla2x00_read_optrom_data,
1809 .write_optrom = qla2x00_write_optrom_data,
1810 .get_flash_version = qla2x00_get_flash_version,
e315cd28 1811 .start_scsi = qla2x00_start_scsi,
a9083016 1812 .abort_isp = qla2x00_abort_isp,
706f457d 1813 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 1814 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 1815};
1816
1817static struct isp_operations qla2300_isp_ops = {
1818 .pci_config = qla2300_pci_config,
1819 .reset_chip = qla2x00_reset_chip,
1820 .chip_diag = qla2x00_chip_diag,
1821 .config_rings = qla2x00_config_rings,
1822 .reset_adapter = qla2x00_reset_adapter,
1823 .nvram_config = qla2x00_nvram_config,
1824 .update_fw_options = qla2x00_update_fw_options,
1825 .load_risc = qla2x00_load_risc,
1826 .pci_info_str = qla2x00_pci_info_str,
1827 .fw_version_str = qla2x00_fw_version_str,
1828 .intr_handler = qla2300_intr_handler,
1829 .enable_intrs = qla2x00_enable_intrs,
1830 .disable_intrs = qla2x00_disable_intrs,
1831 .abort_command = qla2x00_abort_command,
523ec773
AV		 1832 .target_reset = qla2x00_abort_target,
1833 .lun_reset = qla2x00_lun_reset,
fd34f556
AV		 1834 .fabric_login = qla2x00_login_fabric,
1835 .fabric_logout = qla2x00_fabric_logout,
1836 .calc_req_entries = qla2x00_calc_iocbs_32,
1837 .build_iocbs = qla2x00_build_scsi_iocbs_32,
1838 .prep_ms_iocb = qla2x00_prep_ms_iocb,
1839 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
1840 .read_nvram = qla2x00_read_nvram_data,
1841 .write_nvram = qla2x00_write_nvram_data,
1842 .fw_dump = qla2300_fw_dump,
1843 .beacon_on = qla2x00_beacon_on,
1844 .beacon_off = qla2x00_beacon_off,
1845 .beacon_blink = qla2x00_beacon_blink,
1846 .read_optrom = qla2x00_read_optrom_data,
1847 .write_optrom = qla2x00_write_optrom_data,
1848 .get_flash_version = qla2x00_get_flash_version,
e315cd28 1849 .start_scsi = qla2x00_start_scsi,
a9083016 1850 .abort_isp = qla2x00_abort_isp,
7ec0effd 1851 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 1852 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 1853};
1854
1855static struct isp_operations qla24xx_isp_ops = {
1856 .pci_config = qla24xx_pci_config,
1857 .reset_chip = qla24xx_reset_chip,
1858 .chip_diag = qla24xx_chip_diag,
1859 .config_rings = qla24xx_config_rings,
1860 .reset_adapter = qla24xx_reset_adapter,
1861 .nvram_config = qla24xx_nvram_config,
1862 .update_fw_options = qla24xx_update_fw_options,
1863 .load_risc = qla24xx_load_risc,
1864 .pci_info_str = qla24xx_pci_info_str,
1865 .fw_version_str = qla24xx_fw_version_str,
1866 .intr_handler = qla24xx_intr_handler,
1867 .enable_intrs = qla24xx_enable_intrs,
1868 .disable_intrs = qla24xx_disable_intrs,
1869 .abort_command = qla24xx_abort_command,
523ec773
AV		 1870 .target_reset = qla24xx_abort_target,
1871 .lun_reset = qla24xx_lun_reset,
fd34f556
AV		 1872 .fabric_login = qla24xx_login_fabric,
1873 .fabric_logout = qla24xx_fabric_logout,
1874 .calc_req_entries = NULL,
1875 .build_iocbs = NULL,
1876 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1877 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1878 .read_nvram = qla24xx_read_nvram_data,
1879 .write_nvram = qla24xx_write_nvram_data,
1880 .fw_dump = qla24xx_fw_dump,
1881 .beacon_on = qla24xx_beacon_on,
1882 .beacon_off = qla24xx_beacon_off,
1883 .beacon_blink = qla24xx_beacon_blink,
1884 .read_optrom = qla24xx_read_optrom_data,
1885 .write_optrom = qla24xx_write_optrom_data,
1886 .get_flash_version = qla24xx_get_flash_version,
e315cd28 1887 .start_scsi = qla24xx_start_scsi,
a9083016 1888 .abort_isp = qla2x00_abort_isp,
7ec0effd 1889 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 1890 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 1891};
1892
c3a2f0df
AV		 1893static struct isp_operations qla25xx_isp_ops = {
1894 .pci_config = qla25xx_pci_config,
1895 .reset_chip = qla24xx_reset_chip,
1896 .chip_diag = qla24xx_chip_diag,
1897 .config_rings = qla24xx_config_rings,
1898 .reset_adapter = qla24xx_reset_adapter,
1899 .nvram_config = qla24xx_nvram_config,
1900 .update_fw_options = qla24xx_update_fw_options,
1901 .load_risc = qla24xx_load_risc,
1902 .pci_info_str = qla24xx_pci_info_str,
1903 .fw_version_str = qla24xx_fw_version_str,
1904 .intr_handler = qla24xx_intr_handler,
1905 .enable_intrs = qla24xx_enable_intrs,
1906 .disable_intrs = qla24xx_disable_intrs,
1907 .abort_command = qla24xx_abort_command,
523ec773
AV		 1908 .target_reset = qla24xx_abort_target,
1909 .lun_reset = qla24xx_lun_reset,
c3a2f0df
AV		 1910 .fabric_login = qla24xx_login_fabric,
1911 .fabric_logout = qla24xx_fabric_logout,
1912 .calc_req_entries = NULL,
1913 .build_iocbs = NULL,
1914 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1915 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1916 .read_nvram = qla25xx_read_nvram_data,
1917 .write_nvram = qla25xx_write_nvram_data,
1918 .fw_dump = qla25xx_fw_dump,
1919 .beacon_on = qla24xx_beacon_on,
1920 .beacon_off = qla24xx_beacon_off,
1921 .beacon_blink = qla24xx_beacon_blink,
338c9161 1922 .read_optrom = qla25xx_read_optrom_data,
c3a2f0df
AV		 1923 .write_optrom = qla24xx_write_optrom_data,
1924 .get_flash_version = qla24xx_get_flash_version,
bad75002 1925 .start_scsi = qla24xx_dif_start_scsi,
a9083016 1926 .abort_isp = qla2x00_abort_isp,
7ec0effd 1927 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 1928 .initialize_adapter = qla2x00_initialize_adapter,
c3a2f0df
AV		 1929};
1930
3a03eb79
AV		 1931static struct isp_operations qla81xx_isp_ops = {
1932 .pci_config = qla25xx_pci_config,
1933 .reset_chip = qla24xx_reset_chip,
1934 .chip_diag = qla24xx_chip_diag,
1935 .config_rings = qla24xx_config_rings,
1936 .reset_adapter = qla24xx_reset_adapter,
1937 .nvram_config = qla81xx_nvram_config,
1938 .update_fw_options = qla81xx_update_fw_options,
eaac30be 1939 .load_risc = qla81xx_load_risc,
3a03eb79
AV		 1940 .pci_info_str = qla24xx_pci_info_str,
1941 .fw_version_str = qla24xx_fw_version_str,
1942 .intr_handler = qla24xx_intr_handler,
1943 .enable_intrs = qla24xx_enable_intrs,
1944 .disable_intrs = qla24xx_disable_intrs,
1945 .abort_command = qla24xx_abort_command,
1946 .target_reset = qla24xx_abort_target,
1947 .lun_reset = qla24xx_lun_reset,
1948 .fabric_login = qla24xx_login_fabric,
1949 .fabric_logout = qla24xx_fabric_logout,
1950 .calc_req_entries = NULL,
1951 .build_iocbs = NULL,
1952 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1953 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
3d79038f
AV		 1954 .read_nvram = NULL,
1955 .write_nvram = NULL,
3a03eb79
AV		 1956 .fw_dump = qla81xx_fw_dump,
1957 .beacon_on = qla24xx_beacon_on,
1958 .beacon_off = qla24xx_beacon_off,
6246b8a1 1959 .beacon_blink = qla83xx_beacon_blink,
3a03eb79
AV		 1960 .read_optrom = qla25xx_read_optrom_data,
1961 .write_optrom = qla24xx_write_optrom_data,
1962 .get_flash_version = qla24xx_get_flash_version,
ba77ef53 1963 .start_scsi = qla24xx_dif_start_scsi,
a9083016 1964 .abort_isp = qla2x00_abort_isp,
7ec0effd 1965 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 1966 .initialize_adapter = qla2x00_initialize_adapter,
a9083016
GM		 1967};
1968
1969static struct isp_operations qla82xx_isp_ops = {
1970 .pci_config = qla82xx_pci_config,
1971 .reset_chip = qla82xx_reset_chip,
1972 .chip_diag = qla24xx_chip_diag,
1973 .config_rings = qla82xx_config_rings,
1974 .reset_adapter = qla24xx_reset_adapter,
1975 .nvram_config = qla81xx_nvram_config,
1976 .update_fw_options = qla24xx_update_fw_options,
1977 .load_risc = qla82xx_load_risc,
9d55ca66 1978 .pci_info_str = qla24xx_pci_info_str,
a9083016
GM		 1979 .fw_version_str = qla24xx_fw_version_str,
1980 .intr_handler = qla82xx_intr_handler,
1981 .enable_intrs = qla82xx_enable_intrs,
1982 .disable_intrs = qla82xx_disable_intrs,
1983 .abort_command = qla24xx_abort_command,
1984 .target_reset = qla24xx_abort_target,
1985 .lun_reset = qla24xx_lun_reset,
1986 .fabric_login = qla24xx_login_fabric,
1987 .fabric_logout = qla24xx_fabric_logout,
1988 .calc_req_entries = NULL,
1989 .build_iocbs = NULL,
1990 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1991 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1992 .read_nvram = qla24xx_read_nvram_data,
1993 .write_nvram = qla24xx_write_nvram_data,
a1b23c5a 1994 .fw_dump = qla82xx_fw_dump,
999916dc
SK		 1995 .beacon_on = qla82xx_beacon_on,
1996 .beacon_off = qla82xx_beacon_off,
1997 .beacon_blink = NULL,
a9083016
GM		 1998 .read_optrom = qla82xx_read_optrom_data,
1999 .write_optrom = qla82xx_write_optrom_data,
7ec0effd 2000 .get_flash_version = qla82xx_get_flash_version,
a9083016
GM		 2001 .start_scsi = qla82xx_start_scsi,
2002 .abort_isp = qla82xx_abort_isp,
706f457d 2003 .iospace_config = qla82xx_iospace_config,
8ae6d9c7 2004 .initialize_adapter = qla2x00_initialize_adapter,
3a03eb79
AV		 2005};
2006
7ec0effd
AD		 2007static struct isp_operations qla8044_isp_ops = {
2008 .pci_config = qla82xx_pci_config,
2009 .reset_chip = qla82xx_reset_chip,
2010 .chip_diag = qla24xx_chip_diag,
2011 .config_rings = qla82xx_config_rings,
2012 .reset_adapter = qla24xx_reset_adapter,
2013 .nvram_config = qla81xx_nvram_config,
2014 .update_fw_options = qla24xx_update_fw_options,
2015 .load_risc = qla82xx_load_risc,
2016 .pci_info_str = qla24xx_pci_info_str,
2017 .fw_version_str = qla24xx_fw_version_str,
2018 .intr_handler = qla8044_intr_handler,
2019 .enable_intrs = qla82xx_enable_intrs,
2020 .disable_intrs = qla82xx_disable_intrs,
2021 .abort_command = qla24xx_abort_command,
2022 .target_reset = qla24xx_abort_target,
2023 .lun_reset = qla24xx_lun_reset,
2024 .fabric_login = qla24xx_login_fabric,
2025 .fabric_logout = qla24xx_fabric_logout,
2026 .calc_req_entries = NULL,
2027 .build_iocbs = NULL,
2028 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2029 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2030 .read_nvram = NULL,
2031 .write_nvram = NULL,
a1b23c5a 2032 .fw_dump = qla8044_fw_dump,
7ec0effd
AD		 2033 .beacon_on = qla82xx_beacon_on,
2034 .beacon_off = qla82xx_beacon_off,
2035 .beacon_blink = NULL,
888e639d 2036 .read_optrom = qla8044_read_optrom_data,
7ec0effd
AD		 2037 .write_optrom = qla8044_write_optrom_data,
2038 .get_flash_version = qla82xx_get_flash_version,
2039 .start_scsi = qla82xx_start_scsi,
2040 .abort_isp = qla8044_abort_isp,
2041 .iospace_config = qla82xx_iospace_config,
2042 .initialize_adapter = qla2x00_initialize_adapter,
2043};
2044
6246b8a1
GM		 2045static struct isp_operations qla83xx_isp_ops = {
2046 .pci_config = qla25xx_pci_config,
2047 .reset_chip = qla24xx_reset_chip,
2048 .chip_diag = qla24xx_chip_diag,
2049 .config_rings = qla24xx_config_rings,
2050 .reset_adapter = qla24xx_reset_adapter,
2051 .nvram_config = qla81xx_nvram_config,
2052 .update_fw_options = qla81xx_update_fw_options,
2053 .load_risc = qla81xx_load_risc,
2054 .pci_info_str = qla24xx_pci_info_str,
2055 .fw_version_str = qla24xx_fw_version_str,
2056 .intr_handler = qla24xx_intr_handler,
2057 .enable_intrs = qla24xx_enable_intrs,
2058 .disable_intrs = qla24xx_disable_intrs,
2059 .abort_command = qla24xx_abort_command,
2060 .target_reset = qla24xx_abort_target,
2061 .lun_reset = qla24xx_lun_reset,
2062 .fabric_login = qla24xx_login_fabric,
2063 .fabric_logout = qla24xx_fabric_logout,
2064 .calc_req_entries = NULL,
2065 .build_iocbs = NULL,
2066 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2067 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2068 .read_nvram = NULL,
2069 .write_nvram = NULL,
2070 .fw_dump = qla83xx_fw_dump,
2071 .beacon_on = qla24xx_beacon_on,
2072 .beacon_off = qla24xx_beacon_off,
2073 .beacon_blink = qla83xx_beacon_blink,
2074 .read_optrom = qla25xx_read_optrom_data,
2075 .write_optrom = qla24xx_write_optrom_data,
2076 .get_flash_version = qla24xx_get_flash_version,
2077 .start_scsi = qla24xx_dif_start_scsi,
2078 .abort_isp = qla2x00_abort_isp,
2079 .iospace_config = qla83xx_iospace_config,
8ae6d9c7
GM		 2080 .initialize_adapter = qla2x00_initialize_adapter,
2081};
2082
2083static struct isp_operations qlafx00_isp_ops = {
2084 .pci_config = qlafx00_pci_config,
2085 .reset_chip = qlafx00_soft_reset,
2086 .chip_diag = qlafx00_chip_diag,
2087 .config_rings = qlafx00_config_rings,
2088 .reset_adapter = qlafx00_soft_reset,
2089 .nvram_config = NULL,
2090 .update_fw_options = NULL,
2091 .load_risc = NULL,
2092 .pci_info_str = qlafx00_pci_info_str,
2093 .fw_version_str = qlafx00_fw_version_str,
2094 .intr_handler = qlafx00_intr_handler,
2095 .enable_intrs = qlafx00_enable_intrs,
2096 .disable_intrs = qlafx00_disable_intrs,
4440e46d 2097 .abort_command = qla24xx_async_abort_command,
8ae6d9c7
GM		 2098 .target_reset = qlafx00_abort_target,
2099 .lun_reset = qlafx00_lun_reset,
2100 .fabric_login = NULL,
2101 .fabric_logout = NULL,
2102 .calc_req_entries = NULL,
2103 .build_iocbs = NULL,
2104 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2105 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2106 .read_nvram = qla24xx_read_nvram_data,
2107 .write_nvram = qla24xx_write_nvram_data,
2108 .fw_dump = NULL,
2109 .beacon_on = qla24xx_beacon_on,
2110 .beacon_off = qla24xx_beacon_off,
2111 .beacon_blink = NULL,
2112 .read_optrom = qla24xx_read_optrom_data,
2113 .write_optrom = qla24xx_write_optrom_data,
2114 .get_flash_version = qla24xx_get_flash_version,
2115 .start_scsi = qlafx00_start_scsi,
2116 .abort_isp = qlafx00_abort_isp,
2117 .iospace_config = qlafx00_iospace_config,
2118 .initialize_adapter = qlafx00_initialize_adapter,
6246b8a1
GM		 2119};
2120
f73cb695
CD		 2121static struct isp_operations qla27xx_isp_ops = {
2122 .pci_config = qla25xx_pci_config,
2123 .reset_chip = qla24xx_reset_chip,
2124 .chip_diag = qla24xx_chip_diag,
2125 .config_rings = qla24xx_config_rings,
2126 .reset_adapter = qla24xx_reset_adapter,
2127 .nvram_config = qla81xx_nvram_config,
2128 .update_fw_options = qla81xx_update_fw_options,
2129 .load_risc = qla81xx_load_risc,
2130 .pci_info_str = qla24xx_pci_info_str,
2131 .fw_version_str = qla24xx_fw_version_str,
2132 .intr_handler = qla24xx_intr_handler,
2133 .enable_intrs = qla24xx_enable_intrs,
2134 .disable_intrs = qla24xx_disable_intrs,
2135 .abort_command = qla24xx_abort_command,
2136 .target_reset = qla24xx_abort_target,
2137 .lun_reset = qla24xx_lun_reset,
2138 .fabric_login = qla24xx_login_fabric,
2139 .fabric_logout = qla24xx_fabric_logout,
2140 .calc_req_entries = NULL,
2141 .build_iocbs = NULL,
2142 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2143 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2144 .read_nvram = NULL,
2145 .write_nvram = NULL,
2146 .fw_dump = qla27xx_fwdump,
2147 .beacon_on = qla24xx_beacon_on,
2148 .beacon_off = qla24xx_beacon_off,
2149 .beacon_blink = qla83xx_beacon_blink,
2150 .read_optrom = qla25xx_read_optrom_data,
2151 .write_optrom = qla24xx_write_optrom_data,
2152 .get_flash_version = qla24xx_get_flash_version,
2153 .start_scsi = qla24xx_dif_start_scsi,
2154 .abort_isp = qla2x00_abort_isp,
2155 .iospace_config = qla83xx_iospace_config,
2156 .initialize_adapter = qla2x00_initialize_adapter,
2157};
2158
ea5b6382 2159static inline void
e315cd28 2160qla2x00_set_isp_flags(struct qla_hw_data *ha)
ea5b6382 2161{
2162 ha->device_type = DT_EXTENDED_IDS;
2163 switch (ha->pdev->device) {
2164 case PCI_DEVICE_ID_QLOGIC_ISP2100:
2165 ha->device_type |= DT_ISP2100;
2166 ha->device_type &= ~DT_EXTENDED_IDS;
441d1072 2167 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
ea5b6382 2168 break;
2169 case PCI_DEVICE_ID_QLOGIC_ISP2200:
2170 ha->device_type |= DT_ISP2200;
2171 ha->device_type &= ~DT_EXTENDED_IDS;
441d1072 2172 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
ea5b6382 2173 break;
2174 case PCI_DEVICE_ID_QLOGIC_ISP2300:
2175 ha->device_type |= DT_ISP2300;
4a59f71d 2176 ha->device_type |= DT_ZIO_SUPPORTED;
441d1072 2177 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 2178 break;
2179 case PCI_DEVICE_ID_QLOGIC_ISP2312:
2180 ha->device_type |= DT_ISP2312;
4a59f71d 2181 ha->device_type |= DT_ZIO_SUPPORTED;
441d1072 2182 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 2183 break;
2184 case PCI_DEVICE_ID_QLOGIC_ISP2322:
2185 ha->device_type |= DT_ISP2322;
4a59f71d 2186 ha->device_type |= DT_ZIO_SUPPORTED;
ea5b6382 2187 if (ha->pdev->subsystem_vendor == 0x1028 &&
2188 ha->pdev->subsystem_device == 0x0170)
2189 ha->device_type |= DT_OEM_001;
441d1072 2190 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 2191 break;
2192 case PCI_DEVICE_ID_QLOGIC_ISP6312:
2193 ha->device_type |= DT_ISP6312;
441d1072 2194 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 2195 break;
2196 case PCI_DEVICE_ID_QLOGIC_ISP6322:
2197 ha->device_type |= DT_ISP6322;
441d1072 2198 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 2199 break;
2200 case PCI_DEVICE_ID_QLOGIC_ISP2422:
2201 ha->device_type |= DT_ISP2422;
4a59f71d 2202 ha->device_type |= DT_ZIO_SUPPORTED;
e428924c 2203 ha->device_type |= DT_FWI2;
c76f2c01 2204 ha->device_type |= DT_IIDMA;
441d1072 2205 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2206 break;
2207 case PCI_DEVICE_ID_QLOGIC_ISP2432:
2208 ha->device_type |= DT_ISP2432;
4a59f71d 2209 ha->device_type |= DT_ZIO_SUPPORTED;
e428924c 2210 ha->device_type |= DT_FWI2;
c76f2c01 2211 ha->device_type |= DT_IIDMA;
441d1072 2212 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2213 break;
4d4df193
HK		 2214 case PCI_DEVICE_ID_QLOGIC_ISP8432:
2215 ha->device_type |= DT_ISP8432;
2216 ha->device_type |= DT_ZIO_SUPPORTED;
2217 ha->device_type |= DT_FWI2;
2218 ha->device_type |= DT_IIDMA;
2219 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2220 break;
044cc6c8 2221 case PCI_DEVICE_ID_QLOGIC_ISP5422:
2222 ha->device_type |= DT_ISP5422;
e428924c 2223 ha->device_type |= DT_FWI2;
441d1072 2224 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2225 break;
044cc6c8 2226 case PCI_DEVICE_ID_QLOGIC_ISP5432:
2227 ha->device_type |= DT_ISP5432;
e428924c 2228 ha->device_type |= DT_FWI2;
441d1072 2229 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2230 break;
c3a2f0df
AV		 2231 case PCI_DEVICE_ID_QLOGIC_ISP2532:
2232 ha->device_type |= DT_ISP2532;
2233 ha->device_type |= DT_ZIO_SUPPORTED;
2234 ha->device_type |= DT_FWI2;
2235 ha->device_type |= DT_IIDMA;
441d1072 2236 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2237 break;
3a03eb79
AV		 2238 case PCI_DEVICE_ID_QLOGIC_ISP8001:
2239 ha->device_type |= DT_ISP8001;
2240 ha->device_type |= DT_ZIO_SUPPORTED;
2241 ha->device_type |= DT_FWI2;
2242 ha->device_type |= DT_IIDMA;
2243 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2244 break;
a9083016
GM		 2245 case PCI_DEVICE_ID_QLOGIC_ISP8021:
2246 ha->device_type |= DT_ISP8021;
2247 ha->device_type |= DT_ZIO_SUPPORTED;
2248 ha->device_type |= DT_FWI2;
2249 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2250 /* Initialize 82XX ISP flags */
2251 qla82xx_init_flags(ha);
2252 break;
7ec0effd
AD		 2253 case PCI_DEVICE_ID_QLOGIC_ISP8044:
2254 ha->device_type |= DT_ISP8044;
2255 ha->device_type |= DT_ZIO_SUPPORTED;
2256 ha->device_type |= DT_FWI2;
2257 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2258 /* Initialize 82XX ISP flags */
2259 qla82xx_init_flags(ha);
2260 break;
6246b8a1
GM		 2261 case PCI_DEVICE_ID_QLOGIC_ISP2031:
2262 ha->device_type |= DT_ISP2031;
2263 ha->device_type |= DT_ZIO_SUPPORTED;
2264 ha->device_type |= DT_FWI2;
2265 ha->device_type |= DT_IIDMA;
2266 ha->device_type |= DT_T10_PI;
2267 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2268 break;
2269 case PCI_DEVICE_ID_QLOGIC_ISP8031:
2270 ha->device_type |= DT_ISP8031;
2271 ha->device_type |= DT_ZIO_SUPPORTED;
2272 ha->device_type |= DT_FWI2;
2273 ha->device_type |= DT_IIDMA;
2274 ha->device_type |= DT_T10_PI;
2275 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2276 break;
8ae6d9c7
GM		 2277 case PCI_DEVICE_ID_QLOGIC_ISPF001:
2278 ha->device_type |= DT_ISPFX00;
2279 break;
f73cb695
CD		 2280 case PCI_DEVICE_ID_QLOGIC_ISP2071:
2281 ha->device_type |= DT_ISP2071;
2282 ha->device_type |= DT_ZIO_SUPPORTED;
2283 ha->device_type |= DT_FWI2;
2284 ha->device_type |= DT_IIDMA;
2285 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2286 break;
2c5bbbb2
JC		 2287 case PCI_DEVICE_ID_QLOGIC_ISP2271:
2288 ha->device_type |= DT_ISP2271;
2289 ha->device_type |= DT_ZIO_SUPPORTED;
2290 ha->device_type |= DT_FWI2;
2291 ha->device_type |= DT_IIDMA;
2292 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2293 break;
ea5b6382 2294 }
e5b68a61 2295
a9083016 2296 if (IS_QLA82XX(ha))
43a9c38b 2297 ha->port_no = ha->portnum & 1;
f73cb695 2298 else {
a9083016
GM		 2299 /* Get adapter physical port no from interrupt pin register. */
2300 pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no);
f73cb695
CD		 2301 if (IS_QLA27XX(ha))
2302 ha->port_no--;
2303 else
2304 ha->port_no = !(ha->port_no & 1);
2305 }
a9083016 2306
7c3df132 2307 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b,
d8424f68 2308 "device_type=0x%x port=%d fw_srisc_address=0x%x.\n",
f73cb695 2309 ha->device_type, ha->port_no, ha->fw_srisc_address);
ea5b6382 2310}
2311
1e99e33a
AV		 2312static void
2313qla2xxx_scan_start(struct Scsi_Host *shost)
2314{
e315cd28 2315 scsi_qla_host_t *vha = shost_priv(shost);
1e99e33a 2316
cbc8eb67
AV		 2317 if (vha->hw->flags.running_gold_fw)
2318 return;
2319
e315cd28
AC		 2320 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
2321 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
2322 set_bit(RSCN_UPDATE, &vha->dpc_flags);
2323 set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags);
1e99e33a
AV		 2324}
2325
2326static int
2327qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time)
2328{
e315cd28 2329 scsi_qla_host_t *vha = shost_priv(shost);
1e99e33a 2330
e315cd28 2331 if (!vha->host)
1e99e33a 2332 return 1;
e315cd28 2333 if (time > vha->hw->loop_reset_delay * HZ)
1e99e33a
AV		 2334 return 1;
2335
e315cd28 2336 return atomic_read(&vha->loop_state) == LOOP_READY;
1e99e33a
AV		 2337}
2338
1da177e4
LT		 2339/*
2340 * PCI driver interface
2341 */
6f039790 2342static int
7ee61397 2343qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
1da177e4 2344{
a1541d5a 2345 int ret = -ENODEV;
1da177e4 2346 struct Scsi_Host *host;
e315cd28
AC		 2347 scsi_qla_host_t *base_vha = NULL;
2348 struct qla_hw_data *ha;
29856e28 2349 char pci_info[30];
7d613ac6 2350 char fw_str[30], wq_name[30];
5433383e 2351 struct scsi_host_template *sht;
642ef983 2352 int bars, mem_only = 0;
e315cd28 2353 uint16_t req_length = 0, rsp_length = 0;
73208dfd
AC		 2354 struct req_que *req = NULL;
2355 struct rsp_que *rsp = NULL;
285d0321 2356 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO);
a5326f86 2357 sht = &qla2xxx_driver_template;
5433383e 2358 if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 ||
8bc69e7d 2359 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 ||
4d4df193 2360 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 ||
8bc69e7d 2361 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 ||
c3a2f0df 2362 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 ||
3a03eb79 2363 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 ||
a9083016 2364 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 ||
6246b8a1
GM		 2365 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021 ||
2366 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2031 ||
8ae6d9c7 2367 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8031 ||
7ec0effd 2368 pdev->device == PCI_DEVICE_ID_QLOGIC_ISPF001 ||
f73cb695 2369 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8044 ||
2c5bbbb2
JC		 2370 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2071 ||
2371 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2271) {
285d0321 2372 bars = pci_select_bars(pdev, IORESOURCE_MEM);
09483916 2373 mem_only = 1;
7c3df132
SK		 2374 ql_dbg_pci(ql_dbg_init, pdev, 0x0007,
2375 "Mem only adapter.\n");
285d0321 2376 }
7c3df132
SK		 2377 ql_dbg_pci(ql_dbg_init, pdev, 0x0008,
2378 "Bars=%d.\n", bars);
285d0321 2379
09483916
BH		 2380 if (mem_only) {
2381 if (pci_enable_device_mem(pdev))
2382 goto probe_out;
2383 } else {
2384 if (pci_enable_device(pdev))
2385 goto probe_out;
2386 }
285d0321 2387
0927678f
JB		 2388 /* This may fail but that's ok */
2389 pci_enable_pcie_error_reporting(pdev);
285d0321 2390
e315cd28
AC		 2391 ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL);
2392 if (!ha) {
7c3df132
SK		 2393 ql_log_pci(ql_log_fatal, pdev, 0x0009,
2394 "Unable to allocate memory for ha.\n");
e315cd28 2395 goto probe_out;
1da177e4 2396 }
7c3df132
SK		 2397 ql_dbg_pci(ql_dbg_init, pdev, 0x000a,
2398 "Memory allocated for ha=%p.\n", ha);
e315cd28 2399 ha->pdev = pdev;
2d70c103 2400 ha->tgt.enable_class_2 = ql2xenableclass2;
1da177e4
LT		 2401
2402 /* Clear our data area */
285d0321 2403 ha->bars = bars;
09483916 2404 ha->mem_only = mem_only;
df4bf0bb 2405 spin_lock_init(&ha->hardware_lock);
339aa70e 2406 spin_lock_init(&ha->vport_slock);
a9b6f722 2407 mutex_init(&ha->selflogin_lock);
7a8ab9c8 2408 mutex_init(&ha->optrom_mutex);
1da177e4 2409
ea5b6382 2410 /* Set ISP-type information. */
2411 qla2x00_set_isp_flags(ha);
ca79cf66
DG		 2412
2413 /* Set EEH reset type to fundamental if required by hba */
95676112 2414 if (IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha) ||
f73cb695 2415 IS_QLA83XX(ha) || IS_QLA27XX(ha))
ca79cf66 2416 pdev->needs_freset = 1;
ca79cf66 2417
cba1e47f
CD		 2418 ha->prev_topology = 0;
2419 ha->init_cb_size = sizeof(init_cb_t);
2420 ha->link_data_rate = PORT_SPEED_UNKNOWN;
2421 ha->optrom_size = OPTROM_SIZE_2300;
2422
abbd8870 2423 /* Assign ISP specific operations. */
1da177e4 2424 if (IS_QLA2100(ha)) {
642ef983 2425 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
1da177e4 2426 ha->mbx_count = MAILBOX_REGISTER_COUNT_2100;
e315cd28
AC		 2427 req_length = REQUEST_ENTRY_CNT_2100;
2428 rsp_length = RESPONSE_ENTRY_CNT_2100;
2429 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
abbd8870 2430 ha->gid_list_info_size = 4;
3a03eb79
AV		 2431 ha->flash_conf_off = ~0;
2432 ha->flash_data_off = ~0;
2433 ha->nvram_conf_off = ~0;
2434 ha->nvram_data_off = ~0;
fd34f556 2435 ha->isp_ops = &qla2100_isp_ops;
1da177e4 2436 } else if (IS_QLA2200(ha)) {
642ef983 2437 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
67ddda35 2438 ha->mbx_count = MAILBOX_REGISTER_COUNT_2200;
e315cd28
AC		 2439 req_length = REQUEST_ENTRY_CNT_2200;
2440 rsp_length = RESPONSE_ENTRY_CNT_2100;
2441 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
abbd8870 2442 ha->gid_list_info_size = 4;
3a03eb79
AV		 2443 ha->flash_conf_off = ~0;
2444 ha->flash_data_off = ~0;
2445 ha->nvram_conf_off = ~0;
2446 ha->nvram_data_off = ~0;
fd34f556 2447 ha->isp_ops = &qla2100_isp_ops;
fca29703 2448 } else if (IS_QLA23XX(ha)) {
642ef983 2449 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
1da177e4 2450 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2451 req_length = REQUEST_ENTRY_CNT_2200;
2452 rsp_length = RESPONSE_ENTRY_CNT_2300;
2453 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
abbd8870 2454 ha->gid_list_info_size = 6;
854165f4 2455 if (IS_QLA2322(ha) || IS_QLA6322(ha))
2456 ha->optrom_size = OPTROM_SIZE_2322;
3a03eb79
AV		 2457 ha->flash_conf_off = ~0;
2458 ha->flash_data_off = ~0;
2459 ha->nvram_conf_off = ~0;
2460 ha->nvram_data_off = ~0;
fd34f556 2461 ha->isp_ops = &qla2300_isp_ops;
4d4df193 2462 } else if (IS_QLA24XX_TYPE(ha)) {
642ef983 2463 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
fca29703 2464 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2465 req_length = REQUEST_ENTRY_CNT_24XX;
2466 rsp_length = RESPONSE_ENTRY_CNT_2300;
2d70c103 2467 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
e315cd28 2468 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2c3dfe3f 2469 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
fca29703 2470 ha->gid_list_info_size = 8;
854165f4 2471 ha->optrom_size = OPTROM_SIZE_24XX;
73208dfd 2472 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX;
fd34f556 2473 ha->isp_ops = &qla24xx_isp_ops;
3a03eb79
AV		 2474 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2475 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2476 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2477 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
c3a2f0df 2478 } else if (IS_QLA25XX(ha)) {
642ef983 2479 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
c3a2f0df 2480 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2481 req_length = REQUEST_ENTRY_CNT_24XX;
2482 rsp_length = RESPONSE_ENTRY_CNT_2300;
2d70c103 2483 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
e315cd28 2484 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
c3a2f0df 2485 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
c3a2f0df
AV		 2486 ha->gid_list_info_size = 8;
2487 ha->optrom_size = OPTROM_SIZE_25XX;
73208dfd 2488 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
c3a2f0df 2489 ha->isp_ops = &qla25xx_isp_ops;
3a03eb79
AV		 2490 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2491 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2492 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2493 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
2494 } else if (IS_QLA81XX(ha)) {
642ef983 2495 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3a03eb79
AV		 2496 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2497 req_length = REQUEST_ENTRY_CNT_24XX;
2498 rsp_length = RESPONSE_ENTRY_CNT_2300;
aa230bc5 2499 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
3a03eb79
AV		 2500 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2501 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2502 ha->gid_list_info_size = 8;
2503 ha->optrom_size = OPTROM_SIZE_81XX;
40859ae5 2504 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3a03eb79
AV		 2505 ha->isp_ops = &qla81xx_isp_ops;
2506 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2507 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2508 ha->nvram_conf_off = ~0;
2509 ha->nvram_data_off = ~0;
a9083016 2510 } else if (IS_QLA82XX(ha)) {
642ef983 2511 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
a9083016
GM		 2512 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2513 req_length = REQUEST_ENTRY_CNT_82XX;
2514 rsp_length = RESPONSE_ENTRY_CNT_82XX;
2515 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2516 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2517 ha->gid_list_info_size = 8;
2518 ha->optrom_size = OPTROM_SIZE_82XX;
087c621e 2519 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
a9083016
GM		 2520 ha->isp_ops = &qla82xx_isp_ops;
2521 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2522 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2523 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2524 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
7ec0effd
AD		 2525 } else if (IS_QLA8044(ha)) {
2526 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2527 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2528 req_length = REQUEST_ENTRY_CNT_82XX;
2529 rsp_length = RESPONSE_ENTRY_CNT_82XX;
2530 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2531 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2532 ha->gid_list_info_size = 8;
2533 ha->optrom_size = OPTROM_SIZE_83XX;
2534 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2535 ha->isp_ops = &qla8044_isp_ops;
2536 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2537 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2538 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2539 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
6246b8a1 2540 } else if (IS_QLA83XX(ha)) {
7d613ac6 2541 ha->portnum = PCI_FUNC(ha->pdev->devfn);
642ef983 2542 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
6246b8a1 2543 ha->mbx_count = MAILBOX_REGISTER_COUNT;
f2ea653f 2544 req_length = REQUEST_ENTRY_CNT_83XX;
6246b8a1 2545 rsp_length = RESPONSE_ENTRY_CNT_2300;
b8aa4bdf 2546 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
6246b8a1
GM		 2547 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2548 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2549 ha->gid_list_info_size = 8;
2550 ha->optrom_size = OPTROM_SIZE_83XX;
2551 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2552 ha->isp_ops = &qla83xx_isp_ops;
2553 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2554 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2555 ha->nvram_conf_off = ~0;
2556 ha->nvram_data_off = ~0;
8ae6d9c7
GM		 2557 } else if (IS_QLAFX00(ha)) {
2558 ha->max_fibre_devices = MAX_FIBRE_DEVICES_FX00;
2559 ha->mbx_count = MAILBOX_REGISTER_COUNT_FX00;
2560 ha->aen_mbx_count = AEN_MAILBOX_REGISTER_COUNT_FX00;
2561 req_length = REQUEST_ENTRY_CNT_FX00;
2562 rsp_length = RESPONSE_ENTRY_CNT_FX00;
8ae6d9c7
GM		 2563 ha->isp_ops = &qlafx00_isp_ops;
2564 ha->port_down_retry_count = 30; /* default value */
2565 ha->mr.fw_hbt_cnt = QLAFX00_HEARTBEAT_INTERVAL;
2566 ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL;
71e56003 2567 ha->mr.fw_critemp_timer_tick = QLAFX00_CRITEMP_INTERVAL;
8ae6d9c7 2568 ha->mr.fw_hbt_en = 1;
e8f5e95d
AB		 2569 ha->mr.host_info_resend = false;
2570 ha->mr.hinfo_resend_timer_tick = QLAFX00_HINFO_RESEND_INTERVAL;
f73cb695
CD		 2571 } else if (IS_QLA27XX(ha)) {
2572 ha->portnum = PCI_FUNC(ha->pdev->devfn);
2573 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2574 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2575 req_length = REQUEST_ENTRY_CNT_24XX;
2576 rsp_length = RESPONSE_ENTRY_CNT_2300;
2577 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2578 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2579 ha->gid_list_info_size = 8;
2580 ha->optrom_size = OPTROM_SIZE_83XX;
2581 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2582 ha->isp_ops = &qla27xx_isp_ops;
2583 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2584 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2585 ha->nvram_conf_off = ~0;
2586 ha->nvram_data_off = ~0;
1da177e4 2587 }
6246b8a1 2588
7c3df132
SK		 2589 ql_dbg_pci(ql_dbg_init, pdev, 0x001e,
2590 "mbx_count=%d, req_length=%d, "
2591 "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, "
642ef983
CD		 2592 "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, "
2593 "max_fibre_devices=%d.\n",
7c3df132
SK		 2594 ha->mbx_count, req_length, rsp_length, ha->max_loop_id,
2595 ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size,
642ef983 2596 ha->nvram_npiv_size, ha->max_fibre_devices);
7c3df132
SK		 2597 ql_dbg_pci(ql_dbg_init, pdev, 0x001f,
2598 "isp_ops=%p, flash_conf_off=%d, "
2599 "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n",
2600 ha->isp_ops, ha->flash_conf_off, ha->flash_data_off,
2601 ha->nvram_conf_off, ha->nvram_data_off);
706f457d
GM		 2602
2603 /* Configure PCI I/O space */
2604 ret = ha->isp_ops->iospace_config(ha);
2605 if (ret)
0a63ad12 2606 goto iospace_config_failed;
706f457d
GM		 2607
2608 ql_log_pci(ql_log_info, pdev, 0x001d,
2609 "Found an ISP%04X irq %d iobase 0x%p.\n",
2610 pdev->device, pdev->irq, ha->iobase);
6c2f527c 2611 mutex_init(&ha->vport_lock);
0b05a1f0
MB		 2612 init_completion(&ha->mbx_cmd_comp);
2613 complete(&ha->mbx_cmd_comp);
2614 init_completion(&ha->mbx_intr_comp);
23f2ebd1 2615 init_completion(&ha->dcbx_comp);
f356bef1 2616 init_completion(&ha->lb_portup_comp);
1da177e4 2617
2c3dfe3f 2618 set_bit(0, (unsigned long *) ha->vp_idx_map);
1da177e4 2619
53303c42 2620 qla2x00_config_dma_addressing(ha);
7c3df132
SK		 2621 ql_dbg_pci(ql_dbg_init, pdev, 0x0020,
2622 "64 Bit addressing is %s.\n",
2623 ha->flags.enable_64bit_addressing ? "enable" :
2624 "disable");
73208dfd 2625 ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp);
b2a72ec3 2626 if (ret) {
7c3df132
SK		 2627 ql_log_pci(ql_log_fatal, pdev, 0x0031,
2628 "Failed to allocate memory for adapter, aborting.\n");
1da177e4 2629
e315cd28
AC		 2630 goto probe_hw_failed;
2631 }
2632
73208dfd 2633 req->max_q_depth = MAX_Q_DEPTH;
e315cd28 2634 if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU)
73208dfd
AC		 2635 req->max_q_depth = ql2xmaxqdepth;
2636
e315cd28
AC		 2637
2638 base_vha = qla2x00_create_host(sht, ha);
2639 if (!base_vha) {
a1541d5a 2640 ret = -ENOMEM;
6e9f21f3 2641 qla2x00_mem_free(ha);
2afa19a9
AC		 2642 qla2x00_free_req_que(ha, req);
2643 qla2x00_free_rsp_que(ha, rsp);
e315cd28 2644 goto probe_hw_failed;
1da177e4
LT		 2645 }
2646
e315cd28 2647 pci_set_drvdata(pdev, base_vha);
6b383979 2648 set_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags);
e315cd28 2649
e315cd28 2650 host = base_vha->host;
2afa19a9 2651 base_vha->req = req;
73208dfd 2652 if (IS_QLA2XXX_MIDTYPE(ha))
e315cd28 2653 base_vha->mgmt_svr_loop_id = 10 + base_vha->vp_idx;
73208dfd 2654 else
e315cd28
AC		 2655 base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER +
2656 base_vha->vp_idx;
58548cb5 2657
8ae6d9c7
GM		 2658 /* Setup fcport template structure. */
2659 ha->mr.fcport.vha = base_vha;
2660 ha->mr.fcport.port_type = FCT_UNKNOWN;
2661 ha->mr.fcport.loop_id = FC_NO_LOOP_ID;
2662 qla2x00_set_fcport_state(&ha->mr.fcport, FCS_UNCONFIGURED);
2663 ha->mr.fcport.supported_classes = FC_COS_UNSPECIFIED;
2664 ha->mr.fcport.scan_state = 1;
2665
58548cb5
GM		 2666 /* Set the SG table size based on ISP type */
2667 if (!IS_FWI2_CAPABLE(ha)) {
2668 if (IS_QLA2100(ha))
2669 host->sg_tablesize = 32;
2670 } else {
2671 if (!IS_QLA82XX(ha))
2672 host->sg_tablesize = QLA_SG_ALL;
2673 }
642ef983 2674 host->max_id = ha->max_fibre_devices;
e315cd28
AC		 2675 host->cmd_per_lun = 3;
2676 host->unique_id = host->host_no;
e02587d7 2677 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif)
0c470874
AE		 2678 host->max_cmd_len = 32;
2679 else
2680 host->max_cmd_len = MAX_CMDSZ;
e315cd28 2681 host->max_channel = MAX_BUSES - 1;
755f516b
HR		 2682 /* Older HBAs support only 16-bit LUNs */
2683 if (!IS_QLAFX00(ha) && !IS_FWI2_CAPABLE(ha) &&
2684 ql2xmaxlun > 0xffff)
2685 host->max_lun = 0xffff;
2686 else
2687 host->max_lun = ql2xmaxlun;
e315cd28 2688 host->transportt = qla2xxx_transport_template;
9a069e19 2689 sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC);
e315cd28 2690
7c3df132
SK		 2691 ql_dbg(ql_dbg_init, base_vha, 0x0033,
2692 "max_id=%d this_id=%d "
2693 "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d "
1abf635d 2694 "max_lun=%llu transportt=%p, vendor_id=%llu.\n", host->max_id,
7c3df132
SK		 2695 host->this_id, host->cmd_per_lun, host->unique_id,
2696 host->max_cmd_len, host->max_channel, host->max_lun,
2697 host->transportt, sht->vendor_id);
2698
9a347ff4
CD		 2699que_init:
2700 /* Alloc arrays of request and response ring ptrs */
2701 if (!qla2x00_alloc_queues(ha, req, rsp)) {
2702 ql_log(ql_log_fatal, base_vha, 0x003d,
2703 "Failed to allocate memory for queue pointers..."
2704 "aborting.\n");
2705 goto probe_init_failed;
2706 }
2707
2d70c103 2708 qlt_probe_one_stage1(base_vha, ha);
9a347ff4 2709
73208dfd
AC		 2710 /* Set up the irqs */
2711 ret = qla2x00_request_irqs(ha, rsp);
2712 if (ret)
6e9f21f3 2713 goto probe_init_failed;
90a86fc0
JC		 2714
2715 pci_save_state(pdev);
2716
9a347ff4 2717 /* Assign back pointers */
2afa19a9
AC		 2718 rsp->req = req;
2719 req->rsp = rsp;
9a347ff4 2720
8ae6d9c7
GM		 2721 if (IS_QLAFX00(ha)) {
2722 ha->rsp_q_map[0] = rsp;
2723 ha->req_q_map[0] = req;
2724 set_bit(0, ha->req_qid_map);
2725 set_bit(0, ha->rsp_qid_map);
2726 }
2727
08029990
AV		 2728 /* FWI2-capable only. */
2729 req->req_q_in = &ha->iobase->isp24.req_q_in;
2730 req->req_q_out = &ha->iobase->isp24.req_q_out;
2731 rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in;
2732 rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out;
f73cb695 2733 if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
08029990
AV		 2734 req->req_q_in = &ha->mqiobase->isp25mq.req_q_in;
2735 req->req_q_out = &ha->mqiobase->isp25mq.req_q_out;
2736 rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in;
2737 rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out;
17d98630
AC		 2738 }
2739
8ae6d9c7
GM		 2740 if (IS_QLAFX00(ha)) {
2741 req->req_q_in = &ha->iobase->ispfx00.req_q_in;
2742 req->req_q_out = &ha->iobase->ispfx00.req_q_out;
2743 rsp->rsp_q_in = &ha->iobase->ispfx00.rsp_q_in;
2744 rsp->rsp_q_out = &ha->iobase->ispfx00.rsp_q_out;
2745 }
2746
7ec0effd 2747 if (IS_P3P_TYPE(ha)) {
a9083016
GM		 2748 req->req_q_out = &ha->iobase->isp82.req_q_out[0];
2749 rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0];
2750 rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0];
2751 }
2752
7c3df132
SK		 2753 ql_dbg(ql_dbg_multiq, base_vha, 0xc009,
2754 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
2755 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
2756 ql_dbg(ql_dbg_multiq, base_vha, 0xc00a,
2757 "req->req_q_in=%p req->req_q_out=%p "
2758 "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
2759 req->req_q_in, req->req_q_out,
2760 rsp->rsp_q_in, rsp->rsp_q_out);
2761 ql_dbg(ql_dbg_init, base_vha, 0x003e,
2762 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
2763 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
2764 ql_dbg(ql_dbg_init, base_vha, 0x003f,
2765 "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
2766 req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out);
1da177e4 2767
8ae6d9c7 2768 if (ha->isp_ops->initialize_adapter(base_vha)) {
7c3df132
SK		 2769 ql_log(ql_log_fatal, base_vha, 0x00d6,
2770 "Failed to initialize adapter - Adapter flags %x.\n",
2771 base_vha->device_flags);
1da177e4 2772
a9083016
GM		 2773 if (IS_QLA82XX(ha)) {
2774 qla82xx_idc_lock(ha);
2775 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 2776 QLA8XXX_DEV_FAILED);
a9083016 2777 qla82xx_idc_unlock(ha);
7c3df132
SK		 2778 ql_log(ql_log_fatal, base_vha, 0x00d7,
2779 "HW State: FAILED.\n");
7ec0effd
AD		 2780 } else if (IS_QLA8044(ha)) {
2781 qla8044_idc_lock(ha);
2782 qla8044_wr_direct(base_vha,
2783 QLA8044_CRB_DEV_STATE_INDEX,
2784 QLA8XXX_DEV_FAILED);
2785 qla8044_idc_unlock(ha);
2786 ql_log(ql_log_fatal, base_vha, 0x0150,
2787 "HW State: FAILED.\n");
a9083016
GM		 2788 }
2789
a1541d5a 2790 ret = -ENODEV;
1da177e4
LT		 2791 goto probe_failed;
2792 }
2793
3b1bef64
CD		 2794 if (IS_QLAFX00(ha))
2795 host->can_queue = QLAFX00_MAX_CANQUEUE;
2796 else
2797 host->can_queue = req->num_outstanding_cmds - 10;
2798
2799 ql_dbg(ql_dbg_init, base_vha, 0x0032,
2800 "can_queue=%d, req=%p, mgmt_svr_loop_id=%d, sg_tablesize=%d.\n",
2801 host->can_queue, base_vha->req,
2802 base_vha->mgmt_svr_loop_id, host->sg_tablesize);
2803
7163ea81
AC		 2804 if (ha->mqenable) {
2805 if (qla25xx_setup_mode(base_vha)) {
7c3df132
SK		 2806 ql_log(ql_log_warn, base_vha, 0x00ec,
2807 "Failed to create queues, falling back to single queue mode.\n");
7163ea81
AC		 2808 goto que_init;
2809 }
2810 }
68ca949c 2811
cbc8eb67
AV		 2812 if (ha->flags.running_gold_fw)
2813 goto skip_dpc;
2814
1da177e4
LT		 2815 /*
2816 * Startup the kernel thread for this host adapter
2817 */
39a11240 2818 ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha,
7c3df132 2819 "%s_dpc", base_vha->host_str);
39a11240 2820 if (IS_ERR(ha->dpc_thread)) {
7c3df132
SK		 2821 ql_log(ql_log_fatal, base_vha, 0x00ed,
2822 "Failed to start DPC thread.\n");
39a11240 2823 ret = PTR_ERR(ha->dpc_thread);
1da177e4
LT		 2824 goto probe_failed;
2825 }
7c3df132
SK		 2826 ql_dbg(ql_dbg_init, base_vha, 0x00ee,
2827 "DPC thread started successfully.\n");
1da177e4 2828
2d70c103
NB		 2829 /*
2830 * If we're not coming up in initiator mode, we might sit for
2831 * a while without waking up the dpc thread, which leads to a
2832 * stuck process warning. So just kick the dpc once here and
2833 * let the kthread start (and go back to sleep in qla2x00_do_dpc).
2834 */
2835 qla2xxx_wake_dpc(base_vha);
2836
f3ddac19
CD		 2837 INIT_WORK(&ha->board_disable, qla2x00_disable_board_on_pci_error);
2838
81178772
SK		 2839 if (IS_QLA8031(ha) || IS_MCTP_CAPABLE(ha)) {
2840 sprintf(wq_name, "qla2xxx_%lu_dpc_lp_wq", base_vha->host_no);
2841 ha->dpc_lp_wq = create_singlethread_workqueue(wq_name);
2842 INIT_WORK(&ha->idc_aen, qla83xx_service_idc_aen);
2843
2844 sprintf(wq_name, "qla2xxx_%lu_dpc_hp_wq", base_vha->host_no);
2845 ha->dpc_hp_wq = create_singlethread_workqueue(wq_name);
2846 INIT_WORK(&ha->nic_core_reset, qla83xx_nic_core_reset_work);
2847 INIT_WORK(&ha->idc_state_handler,
2848 qla83xx_idc_state_handler_work);
2849 INIT_WORK(&ha->nic_core_unrecoverable,
2850 qla83xx_nic_core_unrecoverable_work);
2851 }
2852
cbc8eb67 2853skip_dpc:
e315cd28
AC		 2854 list_add_tail(&base_vha->list, &ha->vp_list);
2855 base_vha->host->irq = ha->pdev->irq;
1da177e4
LT		 2856
2857 /* Initialized the timer */
e315cd28 2858 qla2x00_start_timer(base_vha, qla2x00_timer, WATCH_INTERVAL);
7c3df132
SK		 2859 ql_dbg(ql_dbg_init, base_vha, 0x00ef,
2860 "Started qla2x00_timer with "
2861 "interval=%d.\n", WATCH_INTERVAL);
2862 ql_dbg(ql_dbg_init, base_vha, 0x00f0,
2863 "Detected hba at address=%p.\n",
2864 ha);
d19044c3 2865
e02587d7 2866 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) {
bad75002 2867 if (ha->fw_attributes & BIT_4) {
9e522cd8 2868 int prot = 0, guard;
bad75002 2869 base_vha->flags.difdix_supported = 1;
7c3df132
SK		 2870 ql_dbg(ql_dbg_init, base_vha, 0x00f1,
2871 "Registering for DIF/DIX type 1 and 3 protection.\n");
8cb2049c
AE		 2872 if (ql2xenabledif == 1)
2873 prot = SHOST_DIX_TYPE0_PROTECTION;
bad75002 2874 scsi_host_set_prot(host,
8cb2049c 2875 prot | SHOST_DIF_TYPE1_PROTECTION
0c470874 2876 | SHOST_DIF_TYPE2_PROTECTION
bad75002
AE		 2877 | SHOST_DIF_TYPE3_PROTECTION
2878 | SHOST_DIX_TYPE1_PROTECTION
0c470874 2879 | SHOST_DIX_TYPE2_PROTECTION
bad75002 2880 | SHOST_DIX_TYPE3_PROTECTION);
9e522cd8
AE		 2881
2882 guard = SHOST_DIX_GUARD_CRC;
2883
2884 if (IS_PI_IPGUARD_CAPABLE(ha) &&
2885 (ql2xenabledif > 1 || IS_PI_DIFB_DIX0_CAPABLE(ha)))
2886 guard |= SHOST_DIX_GUARD_IP;
2887
2888 scsi_host_set_guard(host, guard);
bad75002
AE		 2889 } else
2890 base_vha->flags.difdix_supported = 0;
2891 }
2892
a9083016
GM		 2893 ha->isp_ops->enable_intrs(ha);
2894
1fe19ee4
AB		 2895 if (IS_QLAFX00(ha)) {
2896 ret = qlafx00_fx_disc(base_vha,
2897 &base_vha->hw->mr.fcport, FXDISC_GET_CONFIG_INFO);
2898 host->sg_tablesize = (ha->mr.extended_io_enabled) ?
2899 QLA_SG_ALL : 128;
2900 }
2901
a1541d5a
AV		 2902 ret = scsi_add_host(host, &pdev->dev);
2903 if (ret)
2904 goto probe_failed;
2905
1486400f
MR		 2906 base_vha->flags.init_done = 1;
2907 base_vha->flags.online = 1;
edaa5c74 2908 ha->prev_minidump_failed = 0;
1486400f 2909
7c3df132
SK		 2910 ql_dbg(ql_dbg_init, base_vha, 0x00f2,
2911 "Init done and hba is online.\n");
2912
2d70c103
NB		 2913 if (qla_ini_mode_enabled(base_vha))
2914 scsi_scan_host(host);
2915 else
2916 ql_dbg(ql_dbg_init, base_vha, 0x0122,
2917 "skipping scsi_scan_host() for non-initiator port\n");
1e99e33a 2918
e315cd28 2919 qla2x00_alloc_sysfs_attr(base_vha);
a1541d5a 2920
8ae6d9c7 2921 if (IS_QLAFX00(ha)) {
8ae6d9c7
GM		 2922 ret = qlafx00_fx_disc(base_vha,
2923 &base_vha->hw->mr.fcport, FXDISC_GET_PORT_INFO);
2924
2925 /* Register system information */
2926 ret = qlafx00_fx_disc(base_vha,
2927 &base_vha->hw->mr.fcport, FXDISC_REG_HOST_INFO);
2928 }
2929
e315cd28 2930 qla2x00_init_host_attr(base_vha);
a1541d5a 2931
e315cd28 2932 qla2x00_dfs_setup(base_vha);
df613b96 2933
03eb912a
AB		 2934 ql_log(ql_log_info, base_vha, 0x00fb,
2935 "QLogic %s - %s.\n", ha->model_number, ha->model_desc);
7c3df132
SK		 2936 ql_log(ql_log_info, base_vha, 0x00fc,
2937 "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n",
2938 pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info),
2939 pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-',
2940 base_vha->host_no,
df57caba 2941 ha->isp_ops->fw_version_str(base_vha, fw_str, sizeof(fw_str)));
1da177e4 2942
2d70c103
NB		 2943 qlt_add_target(ha, base_vha);
2944
6b383979 2945 clear_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags);
1da177e4
LT		 2946 return 0;
2947
6e9f21f3 2948probe_init_failed:
2afa19a9 2949 qla2x00_free_req_que(ha, req);
9a347ff4
CD		 2950 ha->req_q_map[0] = NULL;
2951 clear_bit(0, ha->req_qid_map);
2afa19a9 2952 qla2x00_free_rsp_que(ha, rsp);
9a347ff4
CD		 2953 ha->rsp_q_map[0] = NULL;
2954 clear_bit(0, ha->rsp_qid_map);
2afa19a9 2955 ha->max_req_queues = ha->max_rsp_queues = 0;
6e9f21f3 2956
1da177e4 2957probe_failed:
b9978769
AV		 2958 if (base_vha->timer_active)
2959 qla2x00_stop_timer(base_vha);
2960 base_vha->flags.online = 0;
2961 if (ha->dpc_thread) {
2962 struct task_struct *t = ha->dpc_thread;
2963
2964 ha->dpc_thread = NULL;
2965 kthread_stop(t);
2966 }
2967
e315cd28 2968 qla2x00_free_device(base_vha);
1da177e4 2969
e315cd28 2970 scsi_host_put(base_vha->host);
1da177e4 2971
e315cd28 2972probe_hw_failed:
1a2fbf18
JL		 2973 qla2x00_clear_drv_active(ha);
2974
0a63ad12 2975iospace_config_failed:
7ec0effd 2976 if (IS_P3P_TYPE(ha)) {
0a63ad12 2977 if (!ha->nx_pcibase)
f73cb695 2978 iounmap((device_reg_t *)ha->nx_pcibase);
a9083016 2979 if (!ql2xdbwr)
f73cb695 2980 iounmap((device_reg_t *)ha->nxdb_wr_ptr);
a9083016
GM		 2981 } else {
2982 if (ha->iobase)
2983 iounmap(ha->iobase);
8ae6d9c7
GM		 2984 if (ha->cregbase)
2985 iounmap(ha->cregbase);
a9083016 2986 }
e315cd28
AC		 2987 pci_release_selected_regions(ha->pdev, ha->bars);
2988 kfree(ha);
2989 ha = NULL;
1da177e4 2990
a1541d5a 2991probe_out:
e315cd28 2992 pci_disable_device(pdev);
a1541d5a 2993 return ret;
1da177e4 2994}
1da177e4 2995
e30d1756
MI		 2996static void
2997qla2x00_shutdown(struct pci_dev *pdev)
2998{
2999 scsi_qla_host_t *vha;
3000 struct qla_hw_data *ha;
3001
552f3f9a
MI		 3002 if (!atomic_read(&pdev->enable_cnt))
3003 return;
3004
e30d1756
MI		 3005 vha = pci_get_drvdata(pdev);
3006 ha = vha->hw;
3007
42479343
AB		 3008 /* Notify ISPFX00 firmware */
3009 if (IS_QLAFX00(ha))
3010 qlafx00_driver_shutdown(vha, 20);
3011
e30d1756
MI		 3012 /* Turn-off FCE trace */
3013 if (ha->flags.fce_enabled) {
3014 qla2x00_disable_fce_trace(vha, NULL, NULL);
3015 ha->flags.fce_enabled = 0;
3016 }
3017
3018 /* Turn-off EFT trace */
3019 if (ha->eft)
3020 qla2x00_disable_eft_trace(vha);
3021
3022 /* Stop currently executing firmware. */
3023 qla2x00_try_to_stop_firmware(vha);
3024
3025 /* Turn adapter off line */
3026 vha->flags.online = 0;
3027
3028 /* turn-off interrupts on the card */
3029 if (ha->interrupts_on) {
3030 vha->flags.init_done = 0;
3031 ha->isp_ops->disable_intrs(ha);
3032 }
3033
3034 qla2x00_free_irqs(vha);
3035
3036 qla2x00_free_fw_dump(ha);
61d41f61
CD		 3037
3038 pci_disable_pcie_error_reporting(pdev);
3039 pci_disable_device(pdev);
e30d1756
MI		 3040}
3041
fe1b806f 3042/* Deletes all the virtual ports for a given ha */
4c993f76 3043static void
fe1b806f 3044qla2x00_delete_all_vps(struct qla_hw_data *ha, scsi_qla_host_t *base_vha)
1da177e4 3045{
fe1b806f
CD		 3046 struct Scsi_Host *scsi_host;
3047 scsi_qla_host_t *vha;
feafb7b1 3048 unsigned long flags;
e315cd28 3049
43ebf16d
AE		 3050 mutex_lock(&ha->vport_lock);
3051 while (ha->cur_vport_count) {
43ebf16d 3052 spin_lock_irqsave(&ha->vport_slock, flags);
feafb7b1 3053
43ebf16d
AE		 3054 BUG_ON(base_vha->list.next == &ha->vp_list);
3055 /* This assumes first entry in ha->vp_list is always base vha */
3056 vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list);
fe1b806f 3057 scsi_host = scsi_host_get(vha->host);
feafb7b1 3058
43ebf16d
AE		 3059 spin_unlock_irqrestore(&ha->vport_slock, flags);
3060 mutex_unlock(&ha->vport_lock);
3061
3062 fc_vport_terminate(vha->fc_vport);
3063 scsi_host_put(vha->host);
feafb7b1 3064
43ebf16d 3065 mutex_lock(&ha->vport_lock);
e315cd28 3066 }
43ebf16d 3067 mutex_unlock(&ha->vport_lock);
fe1b806f 3068}
1da177e4 3069
fe1b806f
CD		 3070/* Stops all deferred work threads */
3071static void
3072qla2x00_destroy_deferred_work(struct qla_hw_data *ha)
3073{
68ca949c
AC		 3074 /* Flush the work queue and remove it */
3075 if (ha->wq) {
3076 flush_workqueue(ha->wq);
3077 destroy_workqueue(ha->wq);
3078 ha->wq = NULL;
3079 }
3080
7d613ac6
SV		 3081 /* Cancel all work and destroy DPC workqueues */
3082 if (ha->dpc_lp_wq) {
3083 cancel_work_sync(&ha->idc_aen);
3084 destroy_workqueue(ha->dpc_lp_wq);
3085 ha->dpc_lp_wq = NULL;
3086 }
3087
3088 if (ha->dpc_hp_wq) {
3089 cancel_work_sync(&ha->nic_core_reset);
3090 cancel_work_sync(&ha->idc_state_handler);
3091 cancel_work_sync(&ha->nic_core_unrecoverable);
3092 destroy_workqueue(ha->dpc_hp_wq);
3093 ha->dpc_hp_wq = NULL;
3094 }
3095
b9978769
AV		 3096 /* Kill the kernel thread for this host */
3097 if (ha->dpc_thread) {
3098 struct task_struct *t = ha->dpc_thread;
3099
3100 /*
3101 * qla2xxx_wake_dpc checks for ->dpc_thread
3102 * so we need to zero it out.
3103 */
3104 ha->dpc_thread = NULL;
3105 kthread_stop(t);
3106 }
fe1b806f 3107}
1da177e4 3108
fe1b806f
CD		 3109static void
3110qla2x00_unmap_iobases(struct qla_hw_data *ha)
3111{
a9083016 3112 if (IS_QLA82XX(ha)) {
b963752f 3113
f73cb695 3114 iounmap((device_reg_t *)ha->nx_pcibase);
a9083016 3115 if (!ql2xdbwr)
f73cb695 3116 iounmap((device_reg_t *)ha->nxdb_wr_ptr);
a9083016
GM		 3117 } else {
3118 if (ha->iobase)
3119 iounmap(ha->iobase);
1da177e4 3120
8ae6d9c7
GM		 3121 if (ha->cregbase)
3122 iounmap(ha->cregbase);
3123
a9083016
GM		 3124 if (ha->mqiobase)
3125 iounmap(ha->mqiobase);
6246b8a1 3126
f73cb695 3127 if ((IS_QLA83XX(ha) || IS_QLA27XX(ha)) && ha->msixbase)
6246b8a1 3128 iounmap(ha->msixbase);
a9083016 3129 }
fe1b806f
CD		 3130}
3131
3132static void
db7157d4 3133qla2x00_clear_drv_active(struct qla_hw_data *ha)
fe1b806f 3134{
fe1b806f
CD		 3135 if (IS_QLA8044(ha)) {
3136 qla8044_idc_lock(ha);
c41afc9a 3137 qla8044_clear_drv_active(ha);
fe1b806f
CD		 3138 qla8044_idc_unlock(ha);
3139 } else if (IS_QLA82XX(ha)) {
3140 qla82xx_idc_lock(ha);
3141 qla82xx_clear_drv_active(ha);
3142 qla82xx_idc_unlock(ha);
3143 }
3144}
3145
3146static void
3147qla2x00_remove_one(struct pci_dev *pdev)
3148{
3149 scsi_qla_host_t *base_vha;
3150 struct qla_hw_data *ha;
3151
beb9e315
JL		 3152 base_vha = pci_get_drvdata(pdev);
3153 ha = base_vha->hw;
3154
3155 /* Indicate device removal to prevent future board_disable and wait
3156 * until any pending board_disable has completed. */
3157 set_bit(PFLG_DRIVER_REMOVING, &base_vha->pci_flags);
3158 cancel_work_sync(&ha->board_disable);
3159
fe1b806f 3160 /*
beb9e315
JL		 3161 * If the PCI device is disabled then there was a PCI-disconnect and
3162 * qla2x00_disable_board_on_pci_error has taken care of most of the
3163 * resources.
fe1b806f 3164 */
beb9e315
JL		 3165 if (!atomic_read(&pdev->enable_cnt)) {
3166 scsi_host_put(base_vha->host);
3167 kfree(ha);
3168 pci_set_drvdata(pdev, NULL);
fe1b806f 3169 return;
beb9e315 3170 }
fe1b806f 3171
638a1a01
SC		 3172 qla2x00_wait_for_hba_ready(base_vha);
3173
fe1b806f
CD		 3174 set_bit(UNLOADING, &base_vha->dpc_flags);
3175
3176 if (IS_QLAFX00(ha))
3177 qlafx00_driver_shutdown(base_vha, 20);
3178
3179 qla2x00_delete_all_vps(ha, base_vha);
3180
3181 if (IS_QLA8031(ha)) {
3182 ql_dbg(ql_dbg_p3p, base_vha, 0xb07e,
3183 "Clearing fcoe driver presence.\n");
3184 if (qla83xx_clear_drv_presence(base_vha) != QLA_SUCCESS)
3185 ql_dbg(ql_dbg_p3p, base_vha, 0xb079,
3186 "Error while clearing DRV-Presence.\n");
3187 }
3188
3189 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
3190
3191 qla2x00_dfs_remove(base_vha);
3192
3193 qla84xx_put_chip(base_vha);
3194
2d5a4c34
HM		 3195 /* Laser should be disabled only for ISP2031 */
3196 if (IS_QLA2031(ha))
3197 qla83xx_disable_laser(base_vha);
3198
fe1b806f
CD		 3199 /* Disable timer */
3200 if (base_vha->timer_active)
3201 qla2x00_stop_timer(base_vha);
3202
3203 base_vha->flags.online = 0;
3204
3205 qla2x00_destroy_deferred_work(ha);
3206
3207 qlt_remove_target(ha, base_vha);
3208
3209 qla2x00_free_sysfs_attr(base_vha, true);
3210
3211 fc_remove_host(base_vha->host);
3212
3213 scsi_remove_host(base_vha->host);
3214
3215 qla2x00_free_device(base_vha);
3216
db7157d4 3217 qla2x00_clear_drv_active(ha);
fe1b806f 3218
d2749ffa
AE		 3219 scsi_host_put(base_vha->host);
3220
fe1b806f 3221 qla2x00_unmap_iobases(ha);
73208dfd 3222
e315cd28
AC		 3223 pci_release_selected_regions(ha->pdev, ha->bars);
3224 kfree(ha);
3225 ha = NULL;
1da177e4 3226
90a86fc0
JC		 3227 pci_disable_pcie_error_reporting(pdev);
3228
665db93b 3229 pci_disable_device(pdev);
1da177e4 3230}
1da177e4
LT		 3231
3232static void
e315cd28 3233qla2x00_free_device(scsi_qla_host_t *vha)
1da177e4 3234{
e315cd28 3235 struct qla_hw_data *ha = vha->hw;
1da177e4 3236
85880801
AV		 3237 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
3238
3239 /* Disable timer */
3240 if (vha->timer_active)
3241 qla2x00_stop_timer(vha);
3242
2afa19a9 3243 qla25xx_delete_queues(vha);
fe1b806f 3244
df613b96 3245 if (ha->flags.fce_enabled)
e315cd28 3246 qla2x00_disable_fce_trace(vha, NULL, NULL);
df613b96 3247
a7a167bf 3248 if (ha->eft)
e315cd28 3249 qla2x00_disable_eft_trace(vha);
a7a167bf 3250
f6ef3b18 3251 /* Stop currently executing firmware. */
e315cd28 3252 qla2x00_try_to_stop_firmware(vha);
1da177e4 3253
85880801
AV		 3254 vha->flags.online = 0;
3255
f6ef3b18 3256 /* turn-off interrupts on the card */
a9083016
GM		 3257 if (ha->interrupts_on) {
3258 vha->flags.init_done = 0;
fd34f556 3259 ha->isp_ops->disable_intrs(ha);
a9083016 3260 }
f6ef3b18 3261
e315cd28 3262 qla2x00_free_irqs(vha);
1da177e4 3263
8867048b
CD		 3264 qla2x00_free_fcports(vha);
3265
e315cd28 3266 qla2x00_mem_free(ha);
73208dfd 3267
08de2844
GM		 3268 qla82xx_md_free(vha);
3269
73208dfd 3270 qla2x00_free_queues(ha);
1da177e4
LT		 3271}
3272
8867048b
CD		 3273void qla2x00_free_fcports(struct scsi_qla_host *vha)
3274{
3275 fc_port_t *fcport, *tfcport;
3276
3277 list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list) {
3278 list_del(&fcport->list);
5f16b331 3279 qla2x00_clear_loop_id(fcport);
8867048b
CD		 3280 kfree(fcport);
3281 fcport = NULL;
3282 }
3283}
3284
d97994dc 3285static inline void
e315cd28 3286qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport,
d97994dc 3287 int defer)
3288{
d97994dc 3289 struct fc_rport *rport;
67becc00 3290 scsi_qla_host_t *base_vha;
044d78e1 3291 unsigned long flags;
d97994dc 3292
3293 if (!fcport->rport)
3294 return;
3295
3296 rport = fcport->rport;
3297 if (defer) {
67becc00 3298 base_vha = pci_get_drvdata(vha->hw->pdev);
044d78e1 3299 spin_lock_irqsave(vha->host->host_lock, flags);
d97994dc 3300 fcport->drport = rport;
044d78e1 3301 spin_unlock_irqrestore(vha->host->host_lock, flags);
67becc00
AV		 3302 set_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags);
3303 qla2xxx_wake_dpc(base_vha);
2d70c103 3304 } else {
d97994dc 3305 fc_remote_port_delete(rport);
2d70c103
NB		 3306 qlt_fc_port_deleted(vha, fcport);
3307 }
d97994dc 3308}
3309
1da177e4
LT		 3310/*
3311 * qla2x00_mark_device_lost Updates fcport state when device goes offline.
3312 *
3313 * Input: ha = adapter block pointer. fcport = port structure pointer.
3314 *
3315 * Return: None.
3316 *
3317 * Context:
3318 */
e315cd28 3319void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport,
d97994dc 3320 int do_login, int defer)
1da177e4 3321{
8ae6d9c7
GM		 3322 if (IS_QLAFX00(vha->hw)) {
3323 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
3324 qla2x00_schedule_rport_del(vha, fcport, defer);
3325 return;
3326 }
3327
2c3dfe3f 3328 if (atomic_read(&fcport->state) == FCS_ONLINE &&
c6d39e23 3329 vha->vp_idx == fcport->vha->vp_idx) {
ec426e10 3330 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
e315cd28
AC		 3331 qla2x00_schedule_rport_del(vha, fcport, defer);
3332 }
fa2a1ce5 3333 /*
1da177e4
LT		 3334 * We may need to retry the login, so don't change the state of the
3335 * port but do the retries.
3336 */
3337 if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD)
ec426e10 3338 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
1da177e4
LT		 3339
3340 if (!do_login)
3341 return;
3342
3343 if (fcport->login_retry == 0) {
e315cd28
AC		 3344 fcport->login_retry = vha->hw->login_retry_count;
3345 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
1da177e4 3346
7c3df132 3347 ql_dbg(ql_dbg_disc, vha, 0x2067,
7b833558
OK		 3348 "Port login retry %8phN, id = 0x%04x retry cnt=%d.\n",
3349 fcport->port_name, fcport->loop_id, fcport->login_retry);
1da177e4
LT		 3350 }
3351}
3352
3353/*
3354 * qla2x00_mark_all_devices_lost
3355 * Updates fcport state when device goes offline.
3356 *
3357 * Input:
3358 * ha = adapter block pointer.
3359 * fcport = port structure pointer.
3360 *
3361 * Return:
3362 * None.
3363 *
3364 * Context:
3365 */
3366void
e315cd28 3367qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha, int defer)
1da177e4
LT		 3368{
3369 fc_port_t *fcport;
3370
e315cd28 3371 list_for_each_entry(fcport, &vha->vp_fcports, list) {
c6d39e23 3372 if (vha->vp_idx != 0 && vha->vp_idx != fcport->vha->vp_idx)
1da177e4 3373 continue;
0d6e61bc 3374
1da177e4
LT		 3375 /*
3376 * No point in marking the device as lost, if the device is
3377 * already DEAD.
3378 */
3379 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD)
3380 continue;
e315cd28 3381 if (atomic_read(&fcport->state) == FCS_ONLINE) {
ec426e10 3382 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
0d6e61bc
AV		 3383 if (defer)
3384 qla2x00_schedule_rport_del(vha, fcport, defer);
c6d39e23 3385 else if (vha->vp_idx == fcport->vha->vp_idx)
0d6e61bc
AV		 3386 qla2x00_schedule_rport_del(vha, fcport, defer);
3387 }
1da177e4
LT		 3388 }
3389}
3390
3391/*
3392* qla2x00_mem_alloc
3393* Allocates adapter memory.
3394*
3395* Returns:
3396* 0 = success.
e8711085 3397* !0 = failure.
1da177e4 3398*/
e8711085 3399static int
73208dfd
AC		 3400qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len,
3401 struct req_que **req, struct rsp_que **rsp)
1da177e4
LT		 3402{
3403 char name[16];
1da177e4 3404
e8711085 3405 ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size,
e315cd28 3406 &ha->init_cb_dma, GFP_KERNEL);
e8711085 3407 if (!ha->init_cb)
e315cd28 3408 goto fail;
e8711085 3409
2d70c103
NB		 3410 if (qlt_mem_alloc(ha) < 0)
3411 goto fail_free_init_cb;
3412
642ef983
CD		 3413 ha->gid_list = dma_alloc_coherent(&ha->pdev->dev,
3414 qla2x00_gid_list_size(ha), &ha->gid_list_dma, GFP_KERNEL);
e315cd28 3415 if (!ha->gid_list)
2d70c103 3416 goto fail_free_tgt_mem;
1da177e4 3417
e8711085
AV		 3418 ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep);
3419 if (!ha->srb_mempool)
e315cd28 3420 goto fail_free_gid_list;
e8711085 3421
7ec0effd 3422 if (IS_P3P_TYPE(ha)) {
a9083016
GM		 3423 /* Allocate cache for CT6 Ctx. */
3424 if (!ctx_cachep) {
3425 ctx_cachep = kmem_cache_create("qla2xxx_ctx",
3426 sizeof(struct ct6_dsd), 0,
3427 SLAB_HWCACHE_ALIGN, NULL);
3428 if (!ctx_cachep)
3429 goto fail_free_gid_list;
3430 }
3431 ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ,
3432 ctx_cachep);
3433 if (!ha->ctx_mempool)
3434 goto fail_free_srb_mempool;
7c3df132
SK		 3435 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021,
3436 "ctx_cachep=%p ctx_mempool=%p.\n",
3437 ctx_cachep, ha->ctx_mempool);
a9083016
GM		 3438 }
3439
e8711085
AV		 3440 /* Get memory for cached NVRAM */
3441 ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL);
3442 if (!ha->nvram)
a9083016 3443 goto fail_free_ctx_mempool;
e8711085 3444
e315cd28
AC		 3445 snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME,
3446 ha->pdev->device);
3447 ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3448 DMA_POOL_SIZE, 8, 0);
3449 if (!ha->s_dma_pool)
3450 goto fail_free_nvram;
3451
7c3df132
SK		 3452 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022,
3453 "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n",
3454 ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool);
3455
7ec0effd 3456 if (IS_P3P_TYPE(ha) || ql2xenabledif) {
a9083016
GM		 3457 ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3458 DSD_LIST_DMA_POOL_SIZE, 8, 0);
3459 if (!ha->dl_dma_pool) {
7c3df132
SK		 3460 ql_log_pci(ql_log_fatal, ha->pdev, 0x0023,
3461 "Failed to allocate memory for dl_dma_pool.\n");
a9083016
GM		 3462 goto fail_s_dma_pool;
3463 }
3464
3465 ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3466 FCP_CMND_DMA_POOL_SIZE, 8, 0);
3467 if (!ha->fcp_cmnd_dma_pool) {
7c3df132
SK		 3468 ql_log_pci(ql_log_fatal, ha->pdev, 0x0024,
3469 "Failed to allocate memory for fcp_cmnd_dma_pool.\n");
a9083016
GM		 3470 goto fail_dl_dma_pool;
3471 }
7c3df132
SK		 3472 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025,
3473 "dl_dma_pool=%p fcp_cmnd_dma_pool=%p.\n",
3474 ha->dl_dma_pool, ha->fcp_cmnd_dma_pool);
a9083016
GM		 3475 }
3476
e8711085
AV		 3477 /* Allocate memory for SNS commands */
3478 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
e315cd28 3479 /* Get consistent memory allocated for SNS commands */
e8711085 3480 ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev,
e315cd28 3481 sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL);
e8711085 3482 if (!ha->sns_cmd)
e315cd28 3483 goto fail_dma_pool;
7c3df132 3484 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026,
d8424f68 3485 "sns_cmd: %p.\n", ha->sns_cmd);
e8711085 3486 } else {
e315cd28 3487 /* Get consistent memory allocated for MS IOCB */
e8711085 3488 ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
e315cd28 3489 &ha->ms_iocb_dma);
e8711085 3490 if (!ha->ms_iocb)
e315cd28
AC		 3491 goto fail_dma_pool;
3492 /* Get consistent memory allocated for CT SNS commands */
e8711085 3493 ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev,
e315cd28 3494 sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL);
e8711085
AV		 3495 if (!ha->ct_sns)
3496 goto fail_free_ms_iocb;
7c3df132
SK		 3497 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027,
3498 "ms_iocb=%p ct_sns=%p.\n",
3499 ha->ms_iocb, ha->ct_sns);
1da177e4
LT		 3500 }
3501
e315cd28 3502 /* Allocate memory for request ring */
73208dfd
AC		 3503 *req = kzalloc(sizeof(struct req_que), GFP_KERNEL);
3504 if (!*req) {
7c3df132
SK		 3505 ql_log_pci(ql_log_fatal, ha->pdev, 0x0028,
3506 "Failed to allocate memory for req.\n");
e315cd28
AC		 3507 goto fail_req;
3508 }
73208dfd
AC		 3509 (*req)->length = req_len;
3510 (*req)->ring = dma_alloc_coherent(&ha->pdev->dev,
3511 ((*req)->length + 1) * sizeof(request_t),
3512 &(*req)->dma, GFP_KERNEL);
3513 if (!(*req)->ring) {
7c3df132
SK		 3514 ql_log_pci(ql_log_fatal, ha->pdev, 0x0029,
3515 "Failed to allocate memory for req_ring.\n");
e315cd28
AC		 3516 goto fail_req_ring;
3517 }
3518 /* Allocate memory for response ring */
73208dfd
AC		 3519 *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL);
3520 if (!*rsp) {
7c3df132
SK		 3521 ql_log_pci(ql_log_fatal, ha->pdev, 0x002a,
3522 "Failed to allocate memory for rsp.\n");
e315cd28
AC		 3523 goto fail_rsp;
3524 }
73208dfd
AC		 3525 (*rsp)->hw = ha;
3526 (*rsp)->length = rsp_len;
3527 (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev,
3528 ((*rsp)->length + 1) * sizeof(response_t),
3529 &(*rsp)->dma, GFP_KERNEL);
3530 if (!(*rsp)->ring) {
7c3df132
SK		 3531 ql_log_pci(ql_log_fatal, ha->pdev, 0x002b,
3532 "Failed to allocate memory for rsp_ring.\n");
e315cd28
AC		 3533 goto fail_rsp_ring;
3534 }
73208dfd
AC		 3535 (*req)->rsp = *rsp;
3536 (*rsp)->req = *req;
7c3df132
SK		 3537 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c,
3538 "req=%p req->length=%d req->ring=%p rsp=%p "
3539 "rsp->length=%d rsp->ring=%p.\n",
3540 *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length,
3541 (*rsp)->ring);
73208dfd
AC		 3542 /* Allocate memory for NVRAM data for vports */
3543 if (ha->nvram_npiv_size) {
3544 ha->npiv_info = kzalloc(sizeof(struct qla_npiv_entry) *
7c3df132 3545 ha->nvram_npiv_size, GFP_KERNEL);
73208dfd 3546 if (!ha->npiv_info) {
7c3df132
SK		 3547 ql_log_pci(ql_log_fatal, ha->pdev, 0x002d,
3548 "Failed to allocate memory for npiv_info.\n");
73208dfd
AC		 3549 goto fail_npiv_info;
3550 }
3551 } else
3552 ha->npiv_info = NULL;
e8711085 3553
b64b0e8f 3554 /* Get consistent memory allocated for EX-INIT-CB. */
f73cb695 3555 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha)) {
b64b0e8f
AV		 3556 ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
3557 &ha->ex_init_cb_dma);
3558 if (!ha->ex_init_cb)
3559 goto fail_ex_init_cb;
7c3df132
SK		 3560 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e,
3561 "ex_init_cb=%p.\n", ha->ex_init_cb);
b64b0e8f
AV		 3562 }
3563
a9083016
GM		 3564 INIT_LIST_HEAD(&ha->gbl_dsd_list);
3565
5ff1d584
AV		 3566 /* Get consistent memory allocated for Async Port-Database. */
3567 if (!IS_FWI2_CAPABLE(ha)) {
3568 ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
3569 &ha->async_pd_dma);
3570 if (!ha->async_pd)
3571 goto fail_async_pd;
7c3df132
SK		 3572 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f,
3573 "async_pd=%p.\n", ha->async_pd);
5ff1d584
AV		 3574 }
3575
e315cd28 3576 INIT_LIST_HEAD(&ha->vp_list);
5f16b331
CD		 3577
3578 /* Allocate memory for our loop_id bitmap */
3579 ha->loop_id_map = kzalloc(BITS_TO_LONGS(LOOPID_MAP_SIZE) * sizeof(long),
3580 GFP_KERNEL);
3581 if (!ha->loop_id_map)
3582 goto fail_async_pd;
3583 else {
3584 qla2x00_set_reserved_loop_ids(ha);
3585 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0123,
b2a72ec3 3586 "loop_id_map=%p.\n", ha->loop_id_map);
5f16b331
CD		 3587 }
3588
b2a72ec3 3589 return 0;
e315cd28 3590
5ff1d584
AV		 3591fail_async_pd:
3592 dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma);
b64b0e8f
AV		 3593fail_ex_init_cb:
3594 kfree(ha->npiv_info);
73208dfd
AC		 3595fail_npiv_info:
3596 dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) *
3597 sizeof(response_t), (*rsp)->ring, (*rsp)->dma);
3598 (*rsp)->ring = NULL;
3599 (*rsp)->dma = 0;
e315cd28 3600fail_rsp_ring:
73208dfd 3601 kfree(*rsp);
e315cd28 3602fail_rsp:
73208dfd
AC		 3603 dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) *
3604 sizeof(request_t), (*req)->ring, (*req)->dma);
3605 (*req)->ring = NULL;
3606 (*req)->dma = 0;
e315cd28 3607fail_req_ring:
73208dfd 3608 kfree(*req);
e315cd28
AC		 3609fail_req:
3610 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
3611 ha->ct_sns, ha->ct_sns_dma);
3612 ha->ct_sns = NULL;
3613 ha->ct_sns_dma = 0;
e8711085
AV		 3614fail_free_ms_iocb:
3615 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
3616 ha->ms_iocb = NULL;
3617 ha->ms_iocb_dma = 0;
e315cd28 3618fail_dma_pool:
bad75002 3619 if (IS_QLA82XX(ha) || ql2xenabledif) {
a9083016
GM		 3620 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
3621 ha->fcp_cmnd_dma_pool = NULL;
3622 }
3623fail_dl_dma_pool:
bad75002 3624 if (IS_QLA82XX(ha) || ql2xenabledif) {
a9083016
GM		 3625 dma_pool_destroy(ha->dl_dma_pool);
3626 ha->dl_dma_pool = NULL;
3627 }
3628fail_s_dma_pool:
e315cd28
AC		 3629 dma_pool_destroy(ha->s_dma_pool);
3630 ha->s_dma_pool = NULL;
e8711085
AV		 3631fail_free_nvram:
3632 kfree(ha->nvram);
3633 ha->nvram = NULL;
a9083016
GM		 3634fail_free_ctx_mempool:
3635 mempool_destroy(ha->ctx_mempool);
3636 ha->ctx_mempool = NULL;
e8711085
AV		 3637fail_free_srb_mempool:
3638 mempool_destroy(ha->srb_mempool);
3639 ha->srb_mempool = NULL;
e8711085 3640fail_free_gid_list:
642ef983
CD		 3641 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
3642 ha->gid_list,
e315cd28 3643 ha->gid_list_dma);
e8711085
AV		 3644 ha->gid_list = NULL;
3645 ha->gid_list_dma = 0;
2d70c103
NB		 3646fail_free_tgt_mem:
3647 qlt_mem_free(ha);
e315cd28
AC		 3648fail_free_init_cb:
3649 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb,
3650 ha->init_cb_dma);
3651 ha->init_cb = NULL;
3652 ha->init_cb_dma = 0;
e8711085 3653fail:
7c3df132
SK		 3654 ql_log(ql_log_fatal, NULL, 0x0030,
3655 "Memory allocation failure.\n");
e8711085 3656 return -ENOMEM;
1da177e4
LT		 3657}
3658
3659/*
e30d1756
MI		 3660* qla2x00_free_fw_dump
3661* Frees fw dump stuff.
1da177e4
LT		 3662*
3663* Input:
7ec0effd 3664* ha = adapter block pointer
1da177e4 3665*/
a824ebb3 3666static void
e30d1756 3667qla2x00_free_fw_dump(struct qla_hw_data *ha)
1da177e4 3668{
df613b96 3669 if (ha->fce)
f73cb695
CD		 3670 dma_free_coherent(&ha->pdev->dev,
3671 FCE_SIZE, ha->fce, ha->fce_dma);
df613b96 3672
f73cb695
CD		 3673 if (ha->eft)
3674 dma_free_coherent(&ha->pdev->dev,
3675 EFT_SIZE, ha->eft, ha->eft_dma);
3676
3677 if (ha->fw_dump)
a7a167bf 3678 vfree(ha->fw_dump);
f73cb695
CD		 3679 if (ha->fw_dump_template)
3680 vfree(ha->fw_dump_template);
3681
e30d1756
MI		 3682 ha->fce = NULL;
3683 ha->fce_dma = 0;
3684 ha->eft = NULL;
3685 ha->eft_dma = 0;
e30d1756 3686 ha->fw_dumped = 0;
61f098dd 3687 ha->fw_dump_cap_flags = 0;
e30d1756 3688 ha->fw_dump_reading = 0;
f73cb695
CD		 3689 ha->fw_dump = NULL;
3690 ha->fw_dump_len = 0;
3691 ha->fw_dump_template = NULL;
3692 ha->fw_dump_template_len = 0;
e30d1756
MI		 3693}
3694
3695/*
3696* qla2x00_mem_free
3697* Frees all adapter allocated memory.
3698*
3699* Input:
3700* ha = adapter block pointer.
3701*/
3702static void
3703qla2x00_mem_free(struct qla_hw_data *ha)
3704{
3705 qla2x00_free_fw_dump(ha);
3706
81178772
SK		 3707 if (ha->mctp_dump)
3708 dma_free_coherent(&ha->pdev->dev, MCTP_DUMP_SIZE, ha->mctp_dump,
3709 ha->mctp_dump_dma);
3710
e30d1756
MI		 3711 if (ha->srb_mempool)
3712 mempool_destroy(ha->srb_mempool);
a7a167bf 3713
11bbc1d8
AV		 3714 if (ha->dcbx_tlv)
3715 dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE,
3716 ha->dcbx_tlv, ha->dcbx_tlv_dma);
3717
ce0423f4
AV		 3718 if (ha->xgmac_data)
3719 dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE,
3720 ha->xgmac_data, ha->xgmac_data_dma);
3721
1da177e4
LT		 3722 if (ha->sns_cmd)
3723 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
e315cd28 3724 ha->sns_cmd, ha->sns_cmd_dma);
1da177e4
LT		 3725
3726 if (ha->ct_sns)
3727 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
e315cd28 3728 ha->ct_sns, ha->ct_sns_dma);
1da177e4 3729
88729e53
AV		 3730 if (ha->sfp_data)
3731 dma_pool_free(ha->s_dma_pool, ha->sfp_data, ha->sfp_data_dma);
3732
1da177e4
LT		 3733 if (ha->ms_iocb)
3734 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
3735
b64b0e8f 3736 if (ha->ex_init_cb)
a9083016
GM		 3737 dma_pool_free(ha->s_dma_pool,
3738 ha->ex_init_cb, ha->ex_init_cb_dma);
b64b0e8f 3739
5ff1d584
AV		 3740 if (ha->async_pd)
3741 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
3742
1da177e4
LT		 3743 if (ha->s_dma_pool)
3744 dma_pool_destroy(ha->s_dma_pool);
3745
1da177e4 3746 if (ha->gid_list)
642ef983
CD		 3747 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
3748 ha->gid_list, ha->gid_list_dma);
1da177e4 3749
a9083016
GM		 3750 if (IS_QLA82XX(ha)) {
3751 if (!list_empty(&ha->gbl_dsd_list)) {
3752 struct dsd_dma *dsd_ptr, *tdsd_ptr;
3753
3754 /* clean up allocated prev pool */
3755 list_for_each_entry_safe(dsd_ptr,
3756 tdsd_ptr, &ha->gbl_dsd_list, list) {
3757 dma_pool_free(ha->dl_dma_pool,
3758 dsd_ptr->dsd_addr, dsd_ptr->dsd_list_dma);
3759 list_del(&dsd_ptr->list);
3760 kfree(dsd_ptr);
3761 }
3762 }
3763 }
3764
3765 if (ha->dl_dma_pool)
3766 dma_pool_destroy(ha->dl_dma_pool);
3767
3768 if (ha->fcp_cmnd_dma_pool)
3769 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
3770
3771 if (ha->ctx_mempool)
3772 mempool_destroy(ha->ctx_mempool);
3773
2d70c103
NB		 3774 qlt_mem_free(ha);
3775
e315cd28
AC		 3776 if (ha->init_cb)
3777 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size,
a9083016 3778 ha->init_cb, ha->init_cb_dma);
e315cd28
AC		 3779 vfree(ha->optrom_buffer);
3780 kfree(ha->nvram);
73208dfd 3781 kfree(ha->npiv_info);
7a67735b 3782 kfree(ha->swl);
5f16b331 3783 kfree(ha->loop_id_map);
1da177e4 3784
e8711085 3785 ha->srb_mempool = NULL;
a9083016 3786 ha->ctx_mempool = NULL;
1da177e4
LT		 3787 ha->sns_cmd = NULL;
3788 ha->sns_cmd_dma = 0;
3789 ha->ct_sns = NULL;
3790 ha->ct_sns_dma = 0;
3791 ha->ms_iocb = NULL;
3792 ha->ms_iocb_dma = 0;
1da177e4
LT		 3793 ha->init_cb = NULL;
3794 ha->init_cb_dma = 0;
b64b0e8f
AV		 3795 ha->ex_init_cb = NULL;
3796 ha->ex_init_cb_dma = 0;
5ff1d584
AV		 3797 ha->async_pd = NULL;
3798 ha->async_pd_dma = 0;
1da177e4
LT		 3799
3800 ha->s_dma_pool = NULL;
a9083016
GM		 3801 ha->dl_dma_pool = NULL;
3802 ha->fcp_cmnd_dma_pool = NULL;
1da177e4 3803
1da177e4
LT		 3804 ha->gid_list = NULL;
3805 ha->gid_list_dma = 0;
2d70c103
NB		 3806
3807 ha->tgt.atio_ring = NULL;
3808 ha->tgt.atio_dma = 0;
3809 ha->tgt.tgt_vp_map = NULL;
e315cd28 3810}
1da177e4 3811
e315cd28
AC		 3812struct scsi_qla_host *qla2x00_create_host(struct scsi_host_template *sht,
3813 struct qla_hw_data *ha)
3814{
3815 struct Scsi_Host *host;
3816 struct scsi_qla_host *vha = NULL;
854165f4 3817
e315cd28
AC		 3818 host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t));
3819 if (host == NULL) {
7c3df132
SK		 3820 ql_log_pci(ql_log_fatal, ha->pdev, 0x0107,
3821 "Failed to allocate host from the scsi layer, aborting.\n");
e315cd28
AC		 3822 goto fail;
3823 }
3824
3825 /* Clear our data area */
3826 vha = shost_priv(host);
3827 memset(vha, 0, sizeof(scsi_qla_host_t));
3828
3829 vha->host = host;
3830 vha->host_no = host->host_no;
3831 vha->hw = ha;
3832
3833 INIT_LIST_HEAD(&vha->vp_fcports);
3834 INIT_LIST_HEAD(&vha->work_list);
3835 INIT_LIST_HEAD(&vha->list);
3836
f999f4c1
AV		 3837 spin_lock_init(&vha->work_lock);
3838
e315cd28 3839 sprintf(vha->host_str, "%s_%ld", QLA2XXX_DRIVER_NAME, vha->host_no);
7c3df132
SK		 3840 ql_dbg(ql_dbg_init, vha, 0x0041,
3841 "Allocated the host=%p hw=%p vha=%p dev_name=%s",
3842 vha->host, vha->hw, vha,
3843 dev_name(&(ha->pdev->dev)));
3844
e315cd28
AC		 3845 return vha;
3846
3847fail:
3848 return vha;
1da177e4
LT		 3849}
3850
01ef66bb 3851static struct qla_work_evt *
f999f4c1 3852qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type)
0971de7f
AV		 3853{
3854 struct qla_work_evt *e;
feafb7b1
AE		 3855 uint8_t bail;
3856
3857 QLA_VHA_MARK_BUSY(vha, bail);
3858 if (bail)
3859 return NULL;
0971de7f 3860
f999f4c1 3861 e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC);
feafb7b1
AE		 3862 if (!e) {
3863 QLA_VHA_MARK_NOT_BUSY(vha);
0971de7f 3864 return NULL;
feafb7b1 3865 }
0971de7f
AV		 3866
3867 INIT_LIST_HEAD(&e->list);
3868 e->type = type;
3869 e->flags = QLA_EVT_FLAG_FREE;
3870 return e;
3871}
3872
01ef66bb 3873static int
f999f4c1 3874qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e)
0971de7f 3875{
f999f4c1 3876 unsigned long flags;
0971de7f 3877
f999f4c1 3878 spin_lock_irqsave(&vha->work_lock, flags);
e315cd28 3879 list_add_tail(&e->list, &vha->work_list);
f999f4c1 3880 spin_unlock_irqrestore(&vha->work_lock, flags);
e315cd28 3881 qla2xxx_wake_dpc(vha);
f999f4c1 3882
0971de7f
AV		 3883 return QLA_SUCCESS;
3884}
3885
3886int
e315cd28 3887qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code,
0971de7f
AV		 3888 u32 data)
3889{
3890 struct qla_work_evt *e;
3891
f999f4c1 3892 e = qla2x00_alloc_work(vha, QLA_EVT_AEN);
0971de7f
AV		 3893 if (!e)
3894 return QLA_FUNCTION_FAILED;
3895
3896 e->u.aen.code = code;
3897 e->u.aen.data = data;
f999f4c1 3898 return qla2x00_post_work(vha, e);
0971de7f
AV		 3899}
3900
8a659571
AV		 3901int
3902qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb)
3903{
3904 struct qla_work_evt *e;
3905
f999f4c1 3906 e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK);
8a659571
AV		 3907 if (!e)
3908 return QLA_FUNCTION_FAILED;
3909
3910 memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t));
f999f4c1 3911 return qla2x00_post_work(vha, e);
8a659571
AV		 3912}
3913
ac280b67
AV		 3914#define qla2x00_post_async_work(name, type) \
3915int qla2x00_post_async_##name##_work( \
3916 struct scsi_qla_host *vha, \
3917 fc_port_t *fcport, uint16_t *data) \
3918{ \
3919 struct qla_work_evt *e; \
3920 \
3921 e = qla2x00_alloc_work(vha, type); \
3922 if (!e) \
3923 return QLA_FUNCTION_FAILED; \
3924 \
3925 e->u.logio.fcport = fcport; \
3926 if (data) { \
3927 e->u.logio.data[0] = data[0]; \
3928 e->u.logio.data[1] = data[1]; \
3929 } \
3930 return qla2x00_post_work(vha, e); \
3931}
3932
3933qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN);
3934qla2x00_post_async_work(login_done, QLA_EVT_ASYNC_LOGIN_DONE);
3935qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT);
3936qla2x00_post_async_work(logout_done, QLA_EVT_ASYNC_LOGOUT_DONE);
5ff1d584
AV		 3937qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC);
3938qla2x00_post_async_work(adisc_done, QLA_EVT_ASYNC_ADISC_DONE);
ac280b67 3939
3420d36c
AV		 3940int
3941qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code)
3942{
3943 struct qla_work_evt *e;
3944
3945 e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT);
3946 if (!e)
3947 return QLA_FUNCTION_FAILED;
3948
3949 e->u.uevent.code = code;
3950 return qla2x00_post_work(vha, e);
3951}
3952
3953static void
3954qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code)
3955{
3956 char event_string[40];
3957 char *envp[] = { event_string, NULL };
3958
3959 switch (code) {
3960 case QLA_UEVENT_CODE_FW_DUMP:
3961 snprintf(event_string, sizeof(event_string), "FW_DUMP=%ld",
3962 vha->host_no);
3963 break;
3964 default:
3965 /* do nothing */
3966 break;
3967 }
3968 kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp);
3969}
3970
8ae6d9c7
GM		 3971int
3972qlafx00_post_aenfx_work(struct scsi_qla_host *vha, uint32_t evtcode,
3973 uint32_t *data, int cnt)
3974{
3975 struct qla_work_evt *e;
3976
3977 e = qla2x00_alloc_work(vha, QLA_EVT_AENFX);
3978 if (!e)
3979 return QLA_FUNCTION_FAILED;
3980
3981 e->u.aenfx.evtcode = evtcode;
3982 e->u.aenfx.count = cnt;
3983 memcpy(e->u.aenfx.mbx, data, sizeof(*data) * cnt);
3984 return qla2x00_post_work(vha, e);
3985}
3986
ac280b67 3987void
e315cd28 3988qla2x00_do_work(struct scsi_qla_host *vha)
0971de7f 3989{
f999f4c1
AV		 3990 struct qla_work_evt *e, *tmp;
3991 unsigned long flags;
3992 LIST_HEAD(work);
0971de7f 3993
f999f4c1
AV		 3994 spin_lock_irqsave(&vha->work_lock, flags);
3995 list_splice_init(&vha->work_list, &work);
3996 spin_unlock_irqrestore(&vha->work_lock, flags);
3997
3998 list_for_each_entry_safe(e, tmp, &work, list) {
0971de7f 3999 list_del_init(&e->list);
0971de7f
AV		 4000
4001 switch (e->type) {
4002 case QLA_EVT_AEN:
e315cd28 4003 fc_host_post_event(vha->host, fc_get_event_number(),
0971de7f
AV		 4004 e->u.aen.code, e->u.aen.data);
4005 break;
8a659571
AV		 4006 case QLA_EVT_IDC_ACK:
4007 qla81xx_idc_ack(vha, e->u.idc_ack.mb);
4008 break;
ac280b67
AV		 4009 case QLA_EVT_ASYNC_LOGIN:
4010 qla2x00_async_login(vha, e->u.logio.fcport,
4011 e->u.logio.data);
4012 break;
4013 case QLA_EVT_ASYNC_LOGIN_DONE:
4014 qla2x00_async_login_done(vha, e->u.logio.fcport,
4015 e->u.logio.data);
4016 break;
4017 case QLA_EVT_ASYNC_LOGOUT:
4018 qla2x00_async_logout(vha, e->u.logio.fcport);
4019 break;
4020 case QLA_EVT_ASYNC_LOGOUT_DONE:
4021 qla2x00_async_logout_done(vha, e->u.logio.fcport,
4022 e->u.logio.data);
4023 break;
5ff1d584
AV		 4024 case QLA_EVT_ASYNC_ADISC:
4025 qla2x00_async_adisc(vha, e->u.logio.fcport,
4026 e->u.logio.data);
4027 break;
4028 case QLA_EVT_ASYNC_ADISC_DONE:
4029 qla2x00_async_adisc_done(vha, e->u.logio.fcport,
4030 e->u.logio.data);
4031 break;
3420d36c
AV		 4032 case QLA_EVT_UEVENT:
4033 qla2x00_uevent_emit(vha, e->u.uevent.code);
4034 break;
8ae6d9c7
GM		 4035 case QLA_EVT_AENFX:
4036 qlafx00_process_aen(vha, e);
4037 break;
0971de7f
AV		 4038 }
4039 if (e->flags & QLA_EVT_FLAG_FREE)
4040 kfree(e);
feafb7b1
AE		 4041
4042 /* For each work completed decrement vha ref count */
4043 QLA_VHA_MARK_NOT_BUSY(vha);
e315cd28 4044 }
e315cd28 4045}
f999f4c1 4046
e315cd28
AC		 4047/* Relogins all the fcports of a vport
4048 * Context: dpc thread
4049 */
4050void qla2x00_relogin(struct scsi_qla_host *vha)
4051{
4052 fc_port_t *fcport;
c6b2fca8 4053 int status;
e315cd28
AC		 4054 uint16_t next_loopid = 0;
4055 struct qla_hw_data *ha = vha->hw;
ac280b67 4056 uint16_t data[2];
e315cd28
AC		 4057
4058 list_for_each_entry(fcport, &vha->vp_fcports, list) {
4059 /*
4060 * If the port is not ONLINE then try to login
4061 * to it if we haven't run out of retries.
4062 */
5ff1d584
AV		 4063 if (atomic_read(&fcport->state) != FCS_ONLINE &&
4064 fcport->login_retry && !(fcport->flags & FCF_ASYNC_SENT)) {
ac280b67 4065 fcport->login_retry--;
e315cd28 4066 if (fcport->flags & FCF_FABRIC_DEVICE) {
f08b7251 4067 if (fcport->flags & FCF_FCP2_DEVICE)
e315cd28
AC		 4068 ha->isp_ops->fabric_logout(vha,
4069 fcport->loop_id,
4070 fcport->d_id.b.domain,
4071 fcport->d_id.b.area,
4072 fcport->d_id.b.al_pa);
4073
03bcfb57
JC		 4074 if (fcport->loop_id == FC_NO_LOOP_ID) {
4075 fcport->loop_id = next_loopid =
4076 ha->min_external_loopid;
4077 status = qla2x00_find_new_loop_id(
4078 vha, fcport);
4079 if (status != QLA_SUCCESS) {
4080 /* Ran out of IDs to use */
4081 break;
4082 }
4083 }
4084
ac280b67 4085 if (IS_ALOGIO_CAPABLE(ha)) {
5ff1d584 4086 fcport->flags |= FCF_ASYNC_SENT;
ac280b67
AV		 4087 data[0] = 0;
4088 data[1] = QLA_LOGIO_LOGIN_RETRIED;
4089 status = qla2x00_post_async_login_work(
4090 vha, fcport, data);
4091 if (status == QLA_SUCCESS)
4092 continue;
4093 /* Attempt a retry. */
4094 status = 1;
aaf4d3e2 4095 } else {
ac280b67
AV		 4096 status = qla2x00_fabric_login(vha,
4097 fcport, &next_loopid);
aaf4d3e2
SK		 4098 if (status == QLA_SUCCESS) {
4099 int status2;
4100 uint8_t opts;
4101
4102 opts = 0;
4103 if (fcport->flags &
4104 FCF_FCP2_DEVICE)
4105 opts |= BIT_1;
03003960
SK		 4106 status2 =
4107 qla2x00_get_port_database(
4108 vha, fcport, opts);
aaf4d3e2
SK		 4109 if (status2 != QLA_SUCCESS)
4110 status = 1;
4111 }
4112 }
e315cd28
AC		 4113 } else
4114 status = qla2x00_local_device_login(vha,
4115 fcport);
4116
e315cd28
AC		 4117 if (status == QLA_SUCCESS) {
4118 fcport->old_loop_id = fcport->loop_id;
4119
7c3df132
SK		 4120 ql_dbg(ql_dbg_disc, vha, 0x2003,
4121 "Port login OK: logged in ID 0x%x.\n",
4122 fcport->loop_id);
e315cd28
AC		 4123
4124 qla2x00_update_fcport(vha, fcport);
4125
4126 } else if (status == 1) {
4127 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
4128 /* retry the login again */
7c3df132
SK		 4129 ql_dbg(ql_dbg_disc, vha, 0x2007,
4130 "Retrying %d login again loop_id 0x%x.\n",
4131 fcport->login_retry, fcport->loop_id);
e315cd28
AC		 4132 } else {
4133 fcport->login_retry = 0;
4134 }
4135
4136 if (fcport->login_retry == 0 && status != QLA_SUCCESS)
5f16b331 4137 qla2x00_clear_loop_id(fcport);
e315cd28
AC		 4138 }
4139 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
4140 break;
0971de7f 4141 }
0971de7f
AV		 4142}
4143
7d613ac6
SV		 4144/* Schedule work on any of the dpc-workqueues */
4145void
4146qla83xx_schedule_work(scsi_qla_host_t *base_vha, int work_code)
4147{
4148 struct qla_hw_data *ha = base_vha->hw;
4149
4150 switch (work_code) {
4151 case MBA_IDC_AEN: /* 0x8200 */
4152 if (ha->dpc_lp_wq)
4153 queue_work(ha->dpc_lp_wq, &ha->idc_aen);
4154 break;
4155
4156 case QLA83XX_NIC_CORE_RESET: /* 0x1 */
4157 if (!ha->flags.nic_core_reset_hdlr_active) {
4158 if (ha->dpc_hp_wq)
4159 queue_work(ha->dpc_hp_wq, &ha->nic_core_reset);
4160 } else
4161 ql_dbg(ql_dbg_p3p, base_vha, 0xb05e,
4162 "NIC Core reset is already active. Skip "
4163 "scheduling it again.\n");
4164 break;
4165 case QLA83XX_IDC_STATE_HANDLER: /* 0x2 */
4166 if (ha->dpc_hp_wq)
4167 queue_work(ha->dpc_hp_wq, &ha->idc_state_handler);
4168 break;
4169 case QLA83XX_NIC_CORE_UNRECOVERABLE: /* 0x3 */
4170 if (ha->dpc_hp_wq)
4171 queue_work(ha->dpc_hp_wq, &ha->nic_core_unrecoverable);
4172 break;
4173 default:
4174 ql_log(ql_log_warn, base_vha, 0xb05f,
4175 "Unknow work-code=0x%x.\n", work_code);
4176 }
4177
4178 return;
4179}
4180
4181/* Work: Perform NIC Core Unrecoverable state handling */
4182void
4183qla83xx_nic_core_unrecoverable_work(struct work_struct *work)
4184{
4185 struct qla_hw_data *ha =
2ad1b67c 4186 container_of(work, struct qla_hw_data, nic_core_unrecoverable);
7d613ac6
SV		 4187 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4188 uint32_t dev_state = 0;
4189
4190 qla83xx_idc_lock(base_vha, 0);
4191 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4192 qla83xx_reset_ownership(base_vha);
4193 if (ha->flags.nic_core_reset_owner) {
4194 ha->flags.nic_core_reset_owner = 0;
4195 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
4196 QLA8XXX_DEV_FAILED);
4197 ql_log(ql_log_info, base_vha, 0xb060, "HW State: FAILED.\n");
4198 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
4199 }
4200 qla83xx_idc_unlock(base_vha, 0);
4201}
4202
4203/* Work: Execute IDC state handler */
4204void
4205qla83xx_idc_state_handler_work(struct work_struct *work)
4206{
4207 struct qla_hw_data *ha =
2ad1b67c 4208 container_of(work, struct qla_hw_data, idc_state_handler);
7d613ac6
SV		 4209 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4210 uint32_t dev_state = 0;
4211
4212 qla83xx_idc_lock(base_vha, 0);
4213 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4214 if (dev_state == QLA8XXX_DEV_FAILED ||
4215 dev_state == QLA8XXX_DEV_NEED_QUIESCENT)
4216 qla83xx_idc_state_handler(base_vha);
4217 qla83xx_idc_unlock(base_vha, 0);
4218}
4219
fa492630 4220static int
7d613ac6
SV		 4221qla83xx_check_nic_core_fw_alive(scsi_qla_host_t *base_vha)
4222{
4223 int rval = QLA_SUCCESS;
4224 unsigned long heart_beat_wait = jiffies + (1 * HZ);
4225 uint32_t heart_beat_counter1, heart_beat_counter2;
4226
4227 do {
4228 if (time_after(jiffies, heart_beat_wait)) {
4229 ql_dbg(ql_dbg_p3p, base_vha, 0xb07c,
4230 "Nic Core f/w is not alive.\n");
4231 rval = QLA_FUNCTION_FAILED;
4232 break;
4233 }
4234
4235 qla83xx_idc_lock(base_vha, 0);
4236 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
4237 &heart_beat_counter1);
4238 qla83xx_idc_unlock(base_vha, 0);
4239 msleep(100);
4240 qla83xx_idc_lock(base_vha, 0);
4241 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
4242 &heart_beat_counter2);
4243 qla83xx_idc_unlock(base_vha, 0);
4244 } while (heart_beat_counter1 == heart_beat_counter2);
4245
4246 return rval;
4247}
4248
4249/* Work: Perform NIC Core Reset handling */
4250void
4251qla83xx_nic_core_reset_work(struct work_struct *work)
4252{
4253 struct qla_hw_data *ha =
4254 container_of(work, struct qla_hw_data, nic_core_reset);
4255 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4256 uint32_t dev_state = 0;
4257
81178772
SK		 4258 if (IS_QLA2031(ha)) {
4259 if (qla2xxx_mctp_dump(base_vha) != QLA_SUCCESS)
4260 ql_log(ql_log_warn, base_vha, 0xb081,
4261 "Failed to dump mctp\n");
4262 return;
4263 }
4264
7d613ac6
SV		 4265 if (!ha->flags.nic_core_reset_hdlr_active) {
4266 if (qla83xx_check_nic_core_fw_alive(base_vha) == QLA_SUCCESS) {
4267 qla83xx_idc_lock(base_vha, 0);
4268 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE,
4269 &dev_state);
4270 qla83xx_idc_unlock(base_vha, 0);
4271 if (dev_state != QLA8XXX_DEV_NEED_RESET) {
4272 ql_dbg(ql_dbg_p3p, base_vha, 0xb07a,
4273 "Nic Core f/w is alive.\n");
4274 return;
4275 }
4276 }
4277
4278 ha->flags.nic_core_reset_hdlr_active = 1;
4279 if (qla83xx_nic_core_reset(base_vha)) {
4280 /* NIC Core reset failed. */
4281 ql_dbg(ql_dbg_p3p, base_vha, 0xb061,
4282 "NIC Core reset failed.\n");
4283 }
4284 ha->flags.nic_core_reset_hdlr_active = 0;
4285 }
4286}
4287
4288/* Work: Handle 8200 IDC aens */
4289void
4290qla83xx_service_idc_aen(struct work_struct *work)
4291{
4292 struct qla_hw_data *ha =
4293 container_of(work, struct qla_hw_data, idc_aen);
4294 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4295 uint32_t dev_state, idc_control;
4296
4297 qla83xx_idc_lock(base_vha, 0);
4298 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4299 qla83xx_rd_reg(base_vha, QLA83XX_IDC_CONTROL, &idc_control);
4300 qla83xx_idc_unlock(base_vha, 0);
4301 if (dev_state == QLA8XXX_DEV_NEED_RESET) {
4302 if (idc_control & QLA83XX_IDC_GRACEFUL_RESET) {
4303 ql_dbg(ql_dbg_p3p, base_vha, 0xb062,
4304 "Application requested NIC Core Reset.\n");
4305 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
4306 } else if (qla83xx_check_nic_core_fw_alive(base_vha) ==
4307 QLA_SUCCESS) {
4308 ql_dbg(ql_dbg_p3p, base_vha, 0xb07b,
4309 "Other protocol driver requested NIC Core Reset.\n");
4310 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
4311 }
4312 } else if (dev_state == QLA8XXX_DEV_FAILED ||
4313 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) {
4314 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
4315 }
4316}
4317
4318static void
4319qla83xx_wait_logic(void)
4320{
4321 int i;
4322
4323 /* Yield CPU */
4324 if (!in_interrupt()) {
4325 /*
4326 * Wait about 200ms before retrying again.
4327 * This controls the number of retries for single
4328 * lock operation.
4329 */
4330 msleep(100);
4331 schedule();
4332 } else {
4333 for (i = 0; i < 20; i++)
4334 cpu_relax(); /* This a nop instr on i386 */
4335 }
4336}
4337
fa492630 4338static int
7d613ac6
SV		 4339qla83xx_force_lock_recovery(scsi_qla_host_t *base_vha)
4340{
4341 int rval;
4342 uint32_t data;
4343 uint32_t idc_lck_rcvry_stage_mask = 0x3;
4344 uint32_t idc_lck_rcvry_owner_mask = 0x3c;
4345 struct qla_hw_data *ha = base_vha->hw;
6c315553
SK		 4346 ql_dbg(ql_dbg_p3p, base_vha, 0xb086,
4347 "Trying force recovery of the IDC lock.\n");
7d613ac6
SV		 4348
4349 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, &data);
4350 if (rval)
4351 return rval;
4352
4353 if ((data & idc_lck_rcvry_stage_mask) > 0) {
4354 return QLA_SUCCESS;
4355 } else {
4356 data = (IDC_LOCK_RECOVERY_STAGE1) | (ha->portnum << 2);
4357 rval = qla83xx_wr_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
4358 data);
4359 if (rval)
4360 return rval;
4361
4362 msleep(200);
4363
4364 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
4365 &data);
4366 if (rval)
4367 return rval;
4368
4369 if (((data & idc_lck_rcvry_owner_mask) >> 2) == ha->portnum) {
4370 data &= (IDC_LOCK_RECOVERY_STAGE2 |
4371 ~(idc_lck_rcvry_stage_mask));
4372 rval = qla83xx_wr_reg(base_vha,
4373 QLA83XX_IDC_LOCK_RECOVERY, data);
4374 if (rval)
4375 return rval;
4376
4377 /* Forcefully perform IDC UnLock */
4378 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK,
4379 &data);
4380 if (rval)
4381 return rval;
4382 /* Clear lock-id by setting 0xff */
4383 rval = qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
4384 0xff);
4385 if (rval)
4386 return rval;
4387 /* Clear lock-recovery by setting 0x0 */
4388 rval = qla83xx_wr_reg(base_vha,
4389 QLA83XX_IDC_LOCK_RECOVERY, 0x0);
4390 if (rval)
4391 return rval;
4392 } else
4393 return QLA_SUCCESS;
4394 }
4395
4396 return rval;
4397}
4398
fa492630 4399static int
7d613ac6
SV		 4400qla83xx_idc_lock_recovery(scsi_qla_host_t *base_vha)
4401{
4402 int rval = QLA_SUCCESS;
4403 uint32_t o_drv_lockid, n_drv_lockid;
4404 unsigned long lock_recovery_timeout;
4405
4406 lock_recovery_timeout = jiffies + QLA83XX_MAX_LOCK_RECOVERY_WAIT;
4407retry_lockid:
4408 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &o_drv_lockid);
4409 if (rval)
4410 goto exit;
4411
4412 /* MAX wait time before forcing IDC Lock recovery = 2 secs */
4413 if (time_after_eq(jiffies, lock_recovery_timeout)) {
4414 if (qla83xx_force_lock_recovery(base_vha) == QLA_SUCCESS)
4415 return QLA_SUCCESS;
4416 else
4417 return QLA_FUNCTION_FAILED;
4418 }
4419
4420 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &n_drv_lockid);
4421 if (rval)
4422 goto exit;
4423
4424 if (o_drv_lockid == n_drv_lockid) {
4425 qla83xx_wait_logic();
4426 goto retry_lockid;
4427 } else
4428 return QLA_SUCCESS;
4429
4430exit:
4431 return rval;
4432}
4433
4434void
4435qla83xx_idc_lock(scsi_qla_host_t *base_vha, uint16_t requester_id)
4436{
4437 uint16_t options = (requester_id << 15) | BIT_6;
4438 uint32_t data;
6c315553 4439 uint32_t lock_owner;
7d613ac6
SV		 4440 struct qla_hw_data *ha = base_vha->hw;
4441
4442 /* IDC-lock implementation using driver-lock/lock-id remote registers */
4443retry_lock:
4444 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCK, &data)
4445 == QLA_SUCCESS) {
4446 if (data) {
4447 /* Setting lock-id to our function-number */
4448 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
4449 ha->portnum);
4450 } else {
6c315553
SK		 4451 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID,
4452 &lock_owner);
7d613ac6 4453 ql_dbg(ql_dbg_p3p, base_vha, 0xb063,
6c315553
SK		 4454 "Failed to acquire IDC lock, acquired by %d, "
4455 "retrying...\n", lock_owner);
7d613ac6
SV		 4456
4457 /* Retry/Perform IDC-Lock recovery */
4458 if (qla83xx_idc_lock_recovery(base_vha)
4459 == QLA_SUCCESS) {
4460 qla83xx_wait_logic();
4461 goto retry_lock;
4462 } else
4463 ql_log(ql_log_warn, base_vha, 0xb075,
4464 "IDC Lock recovery FAILED.\n");
4465 }
4466
4467 }
4468
4469 return;
4470
4471 /* XXX: IDC-lock implementation using access-control mbx */
4472retry_lock2:
4473 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
4474 ql_dbg(ql_dbg_p3p, base_vha, 0xb072,
4475 "Failed to acquire IDC lock. retrying...\n");
4476 /* Retry/Perform IDC-Lock recovery */
4477 if (qla83xx_idc_lock_recovery(base_vha) == QLA_SUCCESS) {
4478 qla83xx_wait_logic();
4479 goto retry_lock2;
4480 } else
4481 ql_log(ql_log_warn, base_vha, 0xb076,
4482 "IDC Lock recovery FAILED.\n");
4483 }
4484
4485 return;
4486}
4487
4488void
4489qla83xx_idc_unlock(scsi_qla_host_t *base_vha, uint16_t requester_id)
4490{
4491 uint16_t options = (requester_id << 15) | BIT_7, retry;
4492 uint32_t data;
4493 struct qla_hw_data *ha = base_vha->hw;
4494
4495 /* IDC-unlock implementation using driver-unlock/lock-id
4496 * remote registers
4497 */
4498 retry = 0;
4499retry_unlock:
4500 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &data)
4501 == QLA_SUCCESS) {
4502 if (data == ha->portnum) {
4503 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, &data);
4504 /* Clearing lock-id by setting 0xff */
4505 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 0xff);
4506 } else if (retry < 10) {
4507 /* SV: XXX: IDC unlock retrying needed here? */
4508
4509 /* Retry for IDC-unlock */
4510 qla83xx_wait_logic();
4511 retry++;
4512 ql_dbg(ql_dbg_p3p, base_vha, 0xb064,
4513 "Failed to release IDC lock, retyring=%d\n", retry);
4514 goto retry_unlock;
4515 }
4516 } else if (retry < 10) {
4517 /* Retry for IDC-unlock */
4518 qla83xx_wait_logic();
4519 retry++;
4520 ql_dbg(ql_dbg_p3p, base_vha, 0xb065,
4521 "Failed to read drv-lockid, retyring=%d\n", retry);
4522 goto retry_unlock;
4523 }
4524
4525 return;
4526
4527 /* XXX: IDC-unlock implementation using access-control mbx */
4528 retry = 0;
4529retry_unlock2:
4530 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
4531 if (retry < 10) {
4532 /* Retry for IDC-unlock */
4533 qla83xx_wait_logic();
4534 retry++;
4535 ql_dbg(ql_dbg_p3p, base_vha, 0xb066,
4536 "Failed to release IDC lock, retyring=%d\n", retry);
4537 goto retry_unlock2;
4538 }
4539 }
4540
4541 return;
4542}
4543
4544int
4545__qla83xx_set_drv_presence(scsi_qla_host_t *vha)
4546{
4547 int rval = QLA_SUCCESS;
4548 struct qla_hw_data *ha = vha->hw;
4549 uint32_t drv_presence;
4550
4551 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
4552 if (rval == QLA_SUCCESS) {
4553 drv_presence |= (1 << ha->portnum);
4554 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
4555 drv_presence);
4556 }
4557
4558 return rval;
4559}
4560
4561int
4562qla83xx_set_drv_presence(scsi_qla_host_t *vha)
4563{
4564 int rval = QLA_SUCCESS;
4565
4566 qla83xx_idc_lock(vha, 0);
4567 rval = __qla83xx_set_drv_presence(vha);
4568 qla83xx_idc_unlock(vha, 0);
4569
4570 return rval;
4571}
4572
4573int
4574__qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
4575{
4576 int rval = QLA_SUCCESS;
4577 struct qla_hw_data *ha = vha->hw;
4578 uint32_t drv_presence;
4579
4580 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
4581 if (rval == QLA_SUCCESS) {
4582 drv_presence &= ~(1 << ha->portnum);
4583 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
4584 drv_presence);
4585 }
4586
4587 return rval;
4588}
4589
4590int
4591qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
4592{
4593 int rval = QLA_SUCCESS;
4594
4595 qla83xx_idc_lock(vha, 0);
4596 rval = __qla83xx_clear_drv_presence(vha);
4597 qla83xx_idc_unlock(vha, 0);
4598
4599 return rval;
4600}
4601
fa492630 4602static void
7d613ac6
SV		 4603qla83xx_need_reset_handler(scsi_qla_host_t *vha)
4604{
4605 struct qla_hw_data *ha = vha->hw;
4606 uint32_t drv_ack, drv_presence;
4607 unsigned long ack_timeout;
4608
4609 /* Wait for IDC ACK from all functions (DRV-ACK == DRV-PRESENCE) */
4610 ack_timeout = jiffies + (ha->fcoe_reset_timeout * HZ);
4611 while (1) {
4612 qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
4613 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
807fb6d8 4614 if ((drv_ack & drv_presence) == drv_presence)
7d613ac6
SV		 4615 break;
4616
4617 if (time_after_eq(jiffies, ack_timeout)) {
4618 ql_log(ql_log_warn, vha, 0xb067,
4619 "RESET ACK TIMEOUT! drv_presence=0x%x "
4620 "drv_ack=0x%x\n", drv_presence, drv_ack);
4621 /*
4622 * The function(s) which did not ack in time are forced
4623 * to withdraw any further participation in the IDC
4624 * reset.
4625 */
4626 if (drv_ack != drv_presence)
4627 qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
4628 drv_ack);
4629 break;
4630 }
4631
4632 qla83xx_idc_unlock(vha, 0);
4633 msleep(1000);
4634 qla83xx_idc_lock(vha, 0);
4635 }
4636
4637 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_COLD);
4638 ql_log(ql_log_info, vha, 0xb068, "HW State: COLD/RE-INIT.\n");
4639}
4640
fa492630 4641static int
7d613ac6
SV		 4642qla83xx_device_bootstrap(scsi_qla_host_t *vha)
4643{
4644 int rval = QLA_SUCCESS;
4645 uint32_t idc_control;
4646
4647 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_INITIALIZING);
4648 ql_log(ql_log_info, vha, 0xb069, "HW State: INITIALIZING.\n");
4649
4650 /* Clearing IDC-Control Graceful-Reset Bit before resetting f/w */
4651 __qla83xx_get_idc_control(vha, &idc_control);
4652 idc_control &= ~QLA83XX_IDC_GRACEFUL_RESET;
4653 __qla83xx_set_idc_control(vha, 0);
4654
4655 qla83xx_idc_unlock(vha, 0);
4656 rval = qla83xx_restart_nic_firmware(vha);
4657 qla83xx_idc_lock(vha, 0);
4658
4659 if (rval != QLA_SUCCESS) {
4660 ql_log(ql_log_fatal, vha, 0xb06a,
4661 "Failed to restart NIC f/w.\n");
4662 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_FAILED);
4663 ql_log(ql_log_info, vha, 0xb06b, "HW State: FAILED.\n");
4664 } else {
4665 ql_dbg(ql_dbg_p3p, vha, 0xb06c,
4666 "Success in restarting nic f/w.\n");
4667 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_READY);
4668 ql_log(ql_log_info, vha, 0xb06d, "HW State: READY.\n");
4669 }
4670
4671 return rval;
4672}
4673
4674/* Assumes idc_lock always held on entry */
4675int
4676qla83xx_idc_state_handler(scsi_qla_host_t *base_vha)
4677{
4678 struct qla_hw_data *ha = base_vha->hw;
4679 int rval = QLA_SUCCESS;
4680 unsigned long dev_init_timeout;
4681 uint32_t dev_state;
4682
4683 /* Wait for MAX-INIT-TIMEOUT for the device to go ready */
4684 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ);
4685
4686 while (1) {
4687
4688 if (time_after_eq(jiffies, dev_init_timeout)) {
4689 ql_log(ql_log_warn, base_vha, 0xb06e,
4690 "Initialization TIMEOUT!\n");
4691 /* Init timeout. Disable further NIC Core
4692 * communication.
4693 */
4694 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
4695 QLA8XXX_DEV_FAILED);
4696 ql_log(ql_log_info, base_vha, 0xb06f,
4697 "HW State: FAILED.\n");
4698 }
4699
4700 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4701 switch (dev_state) {
4702 case QLA8XXX_DEV_READY:
4703 if (ha->flags.nic_core_reset_owner)
4704 qla83xx_idc_audit(base_vha,
4705 IDC_AUDIT_COMPLETION);
4706 ha->flags.nic_core_reset_owner = 0;
4707 ql_dbg(ql_dbg_p3p, base_vha, 0xb070,
4708 "Reset_owner reset by 0x%x.\n",
4709 ha->portnum);
4710 goto exit;
4711 case QLA8XXX_DEV_COLD:
4712 if (ha->flags.nic_core_reset_owner)
4713 rval = qla83xx_device_bootstrap(base_vha);
4714 else {
4715 /* Wait for AEN to change device-state */
4716 qla83xx_idc_unlock(base_vha, 0);
4717 msleep(1000);
4718 qla83xx_idc_lock(base_vha, 0);
4719 }
4720 break;
4721 case QLA8XXX_DEV_INITIALIZING:
4722 /* Wait for AEN to change device-state */
4723 qla83xx_idc_unlock(base_vha, 0);
4724 msleep(1000);
4725 qla83xx_idc_lock(base_vha, 0);
4726 break;
4727 case QLA8XXX_DEV_NEED_RESET:
4728 if (!ql2xdontresethba && ha->flags.nic_core_reset_owner)
4729 qla83xx_need_reset_handler(base_vha);
4730 else {
4731 /* Wait for AEN to change device-state */
4732 qla83xx_idc_unlock(base_vha, 0);
4733 msleep(1000);
4734 qla83xx_idc_lock(base_vha, 0);
4735 }
4736 /* reset timeout value after need reset handler */
4737 dev_init_timeout = jiffies +
4738 (ha->fcoe_dev_init_timeout * HZ);
4739 break;
4740 case QLA8XXX_DEV_NEED_QUIESCENT:
4741 /* XXX: DEBUG for now */
4742 qla83xx_idc_unlock(base_vha, 0);
4743 msleep(1000);
4744 qla83xx_idc_lock(base_vha, 0);
4745 break;
4746 case QLA8XXX_DEV_QUIESCENT:
4747 /* XXX: DEBUG for now */
4748 if (ha->flags.quiesce_owner)
4749 goto exit;
4750
4751 qla83xx_idc_unlock(base_vha, 0);
4752 msleep(1000);
4753 qla83xx_idc_lock(base_vha, 0);
4754 dev_init_timeout = jiffies +
4755 (ha->fcoe_dev_init_timeout * HZ);
4756 break;
4757 case QLA8XXX_DEV_FAILED:
4758 if (ha->flags.nic_core_reset_owner)
4759 qla83xx_idc_audit(base_vha,
4760 IDC_AUDIT_COMPLETION);
4761 ha->flags.nic_core_reset_owner = 0;
4762 __qla83xx_clear_drv_presence(base_vha);
4763 qla83xx_idc_unlock(base_vha, 0);
4764 qla8xxx_dev_failed_handler(base_vha);
4765 rval = QLA_FUNCTION_FAILED;
4766 qla83xx_idc_lock(base_vha, 0);
4767 goto exit;
4768 case QLA8XXX_BAD_VALUE:
4769 qla83xx_idc_unlock(base_vha, 0);
4770 msleep(1000);
4771 qla83xx_idc_lock(base_vha, 0);
4772 break;
4773 default:
4774 ql_log(ql_log_warn, base_vha, 0xb071,
4775 "Unknow Device State: %x.\n", dev_state);
4776 qla83xx_idc_unlock(base_vha, 0);
4777 qla8xxx_dev_failed_handler(base_vha);
4778 rval = QLA_FUNCTION_FAILED;
4779 qla83xx_idc_lock(base_vha, 0);
4780 goto exit;
4781 }
4782 }
4783
4784exit:
4785 return rval;
4786}
4787
f3ddac19
CD		 4788void
4789qla2x00_disable_board_on_pci_error(struct work_struct *work)
4790{
4791 struct qla_hw_data *ha = container_of(work, struct qla_hw_data,
4792 board_disable);
4793 struct pci_dev *pdev = ha->pdev;
4794 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4795
4796 ql_log(ql_log_warn, base_vha, 0x015b,
4797 "Disabling adapter.\n");
4798
4799 set_bit(UNLOADING, &base_vha->dpc_flags);
4800
4801 qla2x00_delete_all_vps(ha, base_vha);
4802
4803 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
4804
4805 qla2x00_dfs_remove(base_vha);
4806
4807 qla84xx_put_chip(base_vha);
4808
4809 if (base_vha->timer_active)
4810 qla2x00_stop_timer(base_vha);
4811
4812 base_vha->flags.online = 0;
4813
4814 qla2x00_destroy_deferred_work(ha);
4815
4816 /*
4817 * Do not try to stop beacon blink as it will issue a mailbox
4818 * command.
4819 */
4820 qla2x00_free_sysfs_attr(base_vha, false);
4821
4822 fc_remove_host(base_vha->host);
4823
4824 scsi_remove_host(base_vha->host);
4825
4826 base_vha->flags.init_done = 0;
4827 qla25xx_delete_queues(base_vha);
4828 qla2x00_free_irqs(base_vha);
4829 qla2x00_free_fcports(base_vha);
4830 qla2x00_mem_free(ha);
4831 qla82xx_md_free(base_vha);
4832 qla2x00_free_queues(ha);
4833
f3ddac19
CD		 4834 qla2x00_unmap_iobases(ha);
4835
4836 pci_release_selected_regions(ha->pdev, ha->bars);
f3ddac19
CD		 4837 pci_disable_pcie_error_reporting(pdev);
4838 pci_disable_device(pdev);
f3ddac19 4839
beb9e315
JL		 4840 /*
4841 * Let qla2x00_remove_one cleanup qla_hw_data on device removal.
4842 */
f3ddac19
CD		 4843}
4844
1da177e4
LT		 4845/**************************************************************************
4846* qla2x00_do_dpc
4847* This kernel thread is a task that is schedule by the interrupt handler
4848* to perform the background processing for interrupts.
4849*
4850* Notes:
4851* This task always run in the context of a kernel thread. It
4852* is kick-off by the driver's detect code and starts up
4853* up one per adapter. It immediately goes to sleep and waits for
4854* some fibre event. When either the interrupt handler or
4855* the timer routine detects a event it will one of the task
4856* bits then wake us up.
4857**************************************************************************/
4858static int
4859qla2x00_do_dpc(void *data)
4860{
2c3dfe3f 4861 int rval;
e315cd28
AC		 4862 scsi_qla_host_t *base_vha;
4863 struct qla_hw_data *ha;
1da177e4 4864
e315cd28
AC		 4865 ha = (struct qla_hw_data *)data;
4866 base_vha = pci_get_drvdata(ha->pdev);
1da177e4 4867
8698a745 4868 set_user_nice(current, MIN_NICE);
1da177e4 4869
563585ec 4870 set_current_state(TASK_INTERRUPTIBLE);
39a11240 4871 while (!kthread_should_stop()) {
7c3df132
SK		 4872 ql_dbg(ql_dbg_dpc, base_vha, 0x4000,
4873 "DPC handler sleeping.\n");
1da177e4 4874
39a11240
CH		 4875 schedule();
4876 __set_current_state(TASK_RUNNING);
1da177e4 4877
c142caf0
AV		 4878 if (!base_vha->flags.init_done || ha->flags.mbox_busy)
4879 goto end_loop;
1da177e4 4880
85880801 4881 if (ha->flags.eeh_busy) {
7c3df132
SK		 4882 ql_dbg(ql_dbg_dpc, base_vha, 0x4003,
4883 "eeh_busy=%d.\n", ha->flags.eeh_busy);
c142caf0 4884 goto end_loop;
85880801
AV		 4885 }
4886
1da177e4
LT		 4887 ha->dpc_active = 1;
4888
5f28d2d7
SK		 4889 ql_dbg(ql_dbg_dpc + ql_dbg_verbose, base_vha, 0x4001,
4890 "DPC handler waking up, dpc_flags=0x%lx.\n",
4891 base_vha->dpc_flags);
1da177e4 4892
e315cd28 4893 qla2x00_do_work(base_vha);
0971de7f 4894
7ec0effd
AD		 4895 if (IS_P3P_TYPE(ha)) {
4896 if (IS_QLA8044(ha)) {
4897 if (test_and_clear_bit(ISP_UNRECOVERABLE,
4898 &base_vha->dpc_flags)) {
4899 qla8044_idc_lock(ha);
4900 qla8044_wr_direct(base_vha,
4901 QLA8044_CRB_DEV_STATE_INDEX,
4902 QLA8XXX_DEV_FAILED);
4903 qla8044_idc_unlock(ha);
4904 ql_log(ql_log_info, base_vha, 0x4004,
4905 "HW State: FAILED.\n");
4906 qla8044_device_state_handler(base_vha);
4907 continue;
4908 }
4909
4910 } else {
4911 if (test_and_clear_bit(ISP_UNRECOVERABLE,
4912 &base_vha->dpc_flags)) {
4913 qla82xx_idc_lock(ha);
4914 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
4915 QLA8XXX_DEV_FAILED);
4916 qla82xx_idc_unlock(ha);
4917 ql_log(ql_log_info, base_vha, 0x0151,
4918 "HW State: FAILED.\n");
4919 qla82xx_device_state_handler(base_vha);
4920 continue;
4921 }
a9083016
GM		 4922 }
4923
4924 if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED,
4925 &base_vha->dpc_flags)) {
4926
7c3df132
SK		 4927 ql_dbg(ql_dbg_dpc, base_vha, 0x4005,
4928 "FCoE context reset scheduled.\n");
a9083016
GM		 4929 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
4930 &base_vha->dpc_flags))) {
4931 if (qla82xx_fcoe_ctx_reset(base_vha)) {
4932 /* FCoE-ctx reset failed.
4933 * Escalate to chip-reset
4934 */
4935 set_bit(ISP_ABORT_NEEDED,
4936 &base_vha->dpc_flags);
4937 }
4938 clear_bit(ABORT_ISP_ACTIVE,
4939 &base_vha->dpc_flags);
4940 }
4941
7c3df132
SK		 4942 ql_dbg(ql_dbg_dpc, base_vha, 0x4006,
4943 "FCoE context reset end.\n");
a9083016 4944 }
8ae6d9c7
GM		 4945 } else if (IS_QLAFX00(ha)) {
4946 if (test_and_clear_bit(ISP_UNRECOVERABLE,
4947 &base_vha->dpc_flags)) {
4948 ql_dbg(ql_dbg_dpc, base_vha, 0x4020,
4949 "Firmware Reset Recovery\n");
4950 if (qlafx00_reset_initialize(base_vha)) {
4951 /* Failed. Abort isp later. */
4952 if (!test_bit(UNLOADING,
f92f82d6 4953 &base_vha->dpc_flags)) {
8ae6d9c7
GM		 4954 set_bit(ISP_UNRECOVERABLE,
4955 &base_vha->dpc_flags);
4956 ql_dbg(ql_dbg_dpc, base_vha,
4957 0x4021,
4958 "Reset Recovery Failed\n");
f92f82d6 4959 }
8ae6d9c7
GM		 4960 }
4961 }
4962
4963 if (test_and_clear_bit(FX00_TARGET_SCAN,
4964 &base_vha->dpc_flags)) {
4965 ql_dbg(ql_dbg_dpc, base_vha, 0x4022,
4966 "ISPFx00 Target Scan scheduled\n");
4967 if (qlafx00_rescan_isp(base_vha)) {
4968 if (!test_bit(UNLOADING,
4969 &base_vha->dpc_flags))
4970 set_bit(ISP_UNRECOVERABLE,
4971 &base_vha->dpc_flags);
4972 ql_dbg(ql_dbg_dpc, base_vha, 0x401e,
4973 "ISPFx00 Target Scan Failed\n");
4974 }
4975 ql_dbg(ql_dbg_dpc, base_vha, 0x401f,
4976 "ISPFx00 Target Scan End\n");
4977 }
e8f5e95d
AB		 4978 if (test_and_clear_bit(FX00_HOST_INFO_RESEND,
4979 &base_vha->dpc_flags)) {
4980 ql_dbg(ql_dbg_dpc, base_vha, 0x4023,
4981 "ISPFx00 Host Info resend scheduled\n");
4982 qlafx00_fx_disc(base_vha,
4983 &base_vha->hw->mr.fcport,
4984 FXDISC_REG_HOST_INFO);
4985 }
a9083016
GM		 4986 }
4987
e315cd28
AC		 4988 if (test_and_clear_bit(ISP_ABORT_NEEDED,
4989 &base_vha->dpc_flags)) {
1da177e4 4990
7c3df132
SK		 4991 ql_dbg(ql_dbg_dpc, base_vha, 0x4007,
4992 "ISP abort scheduled.\n");
1da177e4 4993 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
e315cd28 4994 &base_vha->dpc_flags))) {
1da177e4 4995
a9083016 4996 if (ha->isp_ops->abort_isp(base_vha)) {
1da177e4
LT		 4997 /* failed. retry later */
4998 set_bit(ISP_ABORT_NEEDED,
e315cd28 4999 &base_vha->dpc_flags);
99363ef8 5000 }
e315cd28
AC		 5001 clear_bit(ABORT_ISP_ACTIVE,
5002 &base_vha->dpc_flags);
99363ef8
SJ		 5003 }
5004
7c3df132
SK		 5005 ql_dbg(ql_dbg_dpc, base_vha, 0x4008,
5006 "ISP abort end.\n");
1da177e4
LT		 5007 }
5008
a394aac8
DJ		 5009 if (test_and_clear_bit(FCPORT_UPDATE_NEEDED,
5010 &base_vha->dpc_flags)) {
e315cd28 5011 qla2x00_update_fcports(base_vha);
c9c5ced9 5012 }
d97994dc 5013
2d70c103
NB		 5014 if (test_bit(SCR_PENDING, &base_vha->dpc_flags)) {
5015 int ret;
5016 ret = qla2x00_send_change_request(base_vha, 0x3, 0);
5017 if (ret != QLA_SUCCESS)
5018 ql_log(ql_log_warn, base_vha, 0x121,
5019 "Failed to enable receiving of RSCN "
5020 "requests: 0x%x.\n", ret);
5021 clear_bit(SCR_PENDING, &base_vha->dpc_flags);
5022 }
5023
8ae6d9c7
GM		 5024 if (IS_QLAFX00(ha))
5025 goto loop_resync_check;
5026
579d12b5 5027 if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) {
7c3df132
SK		 5028 ql_dbg(ql_dbg_dpc, base_vha, 0x4009,
5029 "Quiescence mode scheduled.\n");
7ec0effd
AD		 5030 if (IS_P3P_TYPE(ha)) {
5031 if (IS_QLA82XX(ha))
5032 qla82xx_device_state_handler(base_vha);
5033 if (IS_QLA8044(ha))
5034 qla8044_device_state_handler(base_vha);
8fcd6b8b
CD		 5035 clear_bit(ISP_QUIESCE_NEEDED,
5036 &base_vha->dpc_flags);
5037 if (!ha->flags.quiesce_owner) {
5038 qla2x00_perform_loop_resync(base_vha);
7ec0effd
AD		 5039 if (IS_QLA82XX(ha)) {
5040 qla82xx_idc_lock(ha);
5041 qla82xx_clear_qsnt_ready(
5042 base_vha);
5043 qla82xx_idc_unlock(ha);
5044 } else if (IS_QLA8044(ha)) {
5045 qla8044_idc_lock(ha);
5046 qla8044_clear_qsnt_ready(
5047 base_vha);
5048 qla8044_idc_unlock(ha);
5049 }
8fcd6b8b
CD		 5050 }
5051 } else {
5052 clear_bit(ISP_QUIESCE_NEEDED,
5053 &base_vha->dpc_flags);
5054 qla2x00_quiesce_io(base_vha);
579d12b5 5055 }
7c3df132
SK		 5056 ql_dbg(ql_dbg_dpc, base_vha, 0x400a,
5057 "Quiescence mode end.\n");
579d12b5
SK		 5058 }
5059
e315cd28 5060 if (test_and_clear_bit(RESET_MARKER_NEEDED,
8ae6d9c7 5061 &base_vha->dpc_flags) &&
e315cd28 5062 (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) {
1da177e4 5063
7c3df132
SK		 5064 ql_dbg(ql_dbg_dpc, base_vha, 0x400b,
5065 "Reset marker scheduled.\n");
e315cd28
AC		 5066 qla2x00_rst_aen(base_vha);
5067 clear_bit(RESET_ACTIVE, &base_vha->dpc_flags);
7c3df132
SK		 5068 ql_dbg(ql_dbg_dpc, base_vha, 0x400c,
5069 "Reset marker end.\n");
1da177e4
LT		 5070 }
5071
5072 /* Retry each device up to login retry count */
e315cd28
AC		 5073 if ((test_and_clear_bit(RELOGIN_NEEDED,
5074 &base_vha->dpc_flags)) &&
5075 !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) &&
5076 atomic_read(&base_vha->loop_state) != LOOP_DOWN) {
1da177e4 5077
7c3df132
SK		 5078 ql_dbg(ql_dbg_dpc, base_vha, 0x400d,
5079 "Relogin scheduled.\n");
e315cd28 5080 qla2x00_relogin(base_vha);
7c3df132
SK		 5081 ql_dbg(ql_dbg_dpc, base_vha, 0x400e,
5082 "Relogin end.\n");
1da177e4 5083 }
8ae6d9c7 5084loop_resync_check:
e315cd28 5085 if (test_and_clear_bit(LOOP_RESYNC_NEEDED,
8ae6d9c7 5086 &base_vha->dpc_flags)) {
1da177e4 5087
7c3df132
SK		 5088 ql_dbg(ql_dbg_dpc, base_vha, 0x400f,
5089 "Loop resync scheduled.\n");
1da177e4
LT		 5090
5091 if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE,
e315cd28 5092 &base_vha->dpc_flags))) {
1da177e4 5093
e315cd28 5094 rval = qla2x00_loop_resync(base_vha);
1da177e4 5095
e315cd28
AC		 5096 clear_bit(LOOP_RESYNC_ACTIVE,
5097 &base_vha->dpc_flags);
1da177e4
LT		 5098 }
5099
7c3df132
SK		 5100 ql_dbg(ql_dbg_dpc, base_vha, 0x4010,
5101 "Loop resync end.\n");
1da177e4
LT		 5102 }
5103
8ae6d9c7
GM		 5104 if (IS_QLAFX00(ha))
5105 goto intr_on_check;
5106
e315cd28
AC		 5107 if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) &&
5108 atomic_read(&base_vha->loop_state) == LOOP_READY) {
5109 clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags);
5110 qla2xxx_flash_npiv_conf(base_vha);
272976ca
AV		 5111 }
5112
8ae6d9c7 5113intr_on_check:
1da177e4 5114 if (!ha->interrupts_on)
fd34f556 5115 ha->isp_ops->enable_intrs(ha);
1da177e4 5116
e315cd28 5117 if (test_and_clear_bit(BEACON_BLINK_NEEDED,
90b604f2
HM		 5118 &base_vha->dpc_flags)) {
5119 if (ha->beacon_blink_led == 1)
5120 ha->isp_ops->beacon_blink(base_vha);
5121 }
f6df144c 5122
8ae6d9c7
GM		 5123 if (!IS_QLAFX00(ha))
5124 qla2x00_do_dpc_all_vps(base_vha);
2c3dfe3f 5125
1da177e4 5126 ha->dpc_active = 0;
c142caf0 5127end_loop:
563585ec 5128 set_current_state(TASK_INTERRUPTIBLE);
1da177e4 5129 } /* End of while(1) */
563585ec 5130 __set_current_state(TASK_RUNNING);
1da177e4 5131
7c3df132
SK		 5132 ql_dbg(ql_dbg_dpc, base_vha, 0x4011,
5133 "DPC handler exiting.\n");
1da177e4
LT		 5134
5135 /*
5136 * Make sure that nobody tries to wake us up again.
5137 */
1da177e4
LT		 5138 ha->dpc_active = 0;
5139
ac280b67
AV		 5140 /* Cleanup any residual CTX SRBs. */
5141 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
5142
39a11240
CH		 5143 return 0;
5144}
5145
5146void
e315cd28 5147qla2xxx_wake_dpc(struct scsi_qla_host *vha)
39a11240 5148{
e315cd28 5149 struct qla_hw_data *ha = vha->hw;
c795c1e4
AV		 5150 struct task_struct *t = ha->dpc_thread;
5151
e315cd28 5152 if (!test_bit(UNLOADING, &vha->dpc_flags) && t)
c795c1e4 5153 wake_up_process(t);
1da177e4
LT		 5154}
5155
1da177e4
LT		 5156/*
5157* qla2x00_rst_aen
5158* Processes asynchronous reset.
5159*
5160* Input:
5161* ha = adapter block pointer.
5162*/
5163static void
e315cd28 5164qla2x00_rst_aen(scsi_qla_host_t *vha)
1da177e4 5165{
e315cd28
AC		 5166 if (vha->flags.online && !vha->flags.reset_active &&
5167 !atomic_read(&vha->loop_down_timer) &&
5168 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) {
1da177e4 5169 do {
e315cd28 5170 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
1da177e4
LT		 5171
5172 /*
5173 * Issue marker command only when we are going to start
5174 * the I/O.
5175 */
e315cd28
AC		 5176 vha->marker_needed = 1;
5177 } while (!atomic_read(&vha->loop_down_timer) &&
5178 (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)));
1da177e4
LT		 5179 }
5180}
5181
1da177e4
LT		 5182/**************************************************************************
5183* qla2x00_timer
5184*
5185* Description:
5186* One second timer
5187*
5188* Context: Interrupt
5189***************************************************************************/
2c3dfe3f 5190void
e315cd28 5191qla2x00_timer(scsi_qla_host_t *vha)
1da177e4 5192{
1da177e4 5193 unsigned long cpu_flags = 0;
1da177e4
LT		 5194 int start_dpc = 0;
5195 int index;
5196 srb_t *sp;
85880801 5197 uint16_t w;
e315cd28 5198 struct qla_hw_data *ha = vha->hw;
73208dfd 5199 struct req_que *req;
85880801 5200
a5b36321 5201 if (ha->flags.eeh_busy) {
7c3df132
SK		 5202 ql_dbg(ql_dbg_timer, vha, 0x6000,
5203 "EEH = %d, restarting timer.\n",
5204 ha->flags.eeh_busy);
a5b36321
LC		 5205 qla2x00_restart_timer(vha, WATCH_INTERVAL);
5206 return;
5207 }
5208
f3ddac19
CD		 5209 /*
5210 * Hardware read to raise pending EEH errors during mailbox waits. If
5211 * the read returns -1 then disable the board.
5212 */
5213 if (!pci_channel_offline(ha->pdev)) {
85880801 5214 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w);
c821e0d5 5215 qla2x00_check_reg16_for_disconnect(vha, w);
f3ddac19 5216 }
1da177e4 5217
cefcaba6 5218 /* Make sure qla82xx_watchdog is run only for physical port */
7ec0effd 5219 if (!vha->vp_idx && IS_P3P_TYPE(ha)) {
579d12b5
SK		 5220 if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags))
5221 start_dpc++;
7ec0effd
AD		 5222 if (IS_QLA82XX(ha))
5223 qla82xx_watchdog(vha);
5224 else if (IS_QLA8044(ha))
5225 qla8044_watchdog(vha);
579d12b5
SK		 5226 }
5227
8ae6d9c7
GM		 5228 if (!vha->vp_idx && IS_QLAFX00(ha))
5229 qlafx00_timer_routine(vha);
5230
1da177e4 5231 /* Loop down handler. */
e315cd28 5232 if (atomic_read(&vha->loop_down_timer) > 0 &&
8f7daead
GM		 5233 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) &&
5234 !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags))
e315cd28 5235 && vha->flags.online) {
1da177e4 5236
e315cd28
AC		 5237 if (atomic_read(&vha->loop_down_timer) ==
5238 vha->loop_down_abort_time) {
1da177e4 5239
7c3df132
SK		 5240 ql_log(ql_log_info, vha, 0x6008,
5241 "Loop down - aborting the queues before time expires.\n");
1da177e4 5242
e315cd28
AC		 5243 if (!IS_QLA2100(ha) && vha->link_down_timeout)
5244 atomic_set(&vha->loop_state, LOOP_DEAD);
1da177e4 5245
f08b7251
AV		 5246 /*
5247 * Schedule an ISP abort to return any FCP2-device
5248 * commands.
5249 */
2c3dfe3f 5250 /* NPIV - scan physical port only */
e315cd28 5251 if (!vha->vp_idx) {
2c3dfe3f
SJ		 5252 spin_lock_irqsave(&ha->hardware_lock,
5253 cpu_flags);
73208dfd 5254 req = ha->req_q_map[0];
2c3dfe3f 5255 for (index = 1;
8d93f550 5256 index < req->num_outstanding_cmds;
2c3dfe3f
SJ		 5257 index++) {
5258 fc_port_t *sfcp;
5259
e315cd28 5260 sp = req->outstanding_cmds[index];
2c3dfe3f
SJ		 5261 if (!sp)
5262 continue;
9ba56b95 5263 if (sp->type != SRB_SCSI_CMD)
cf53b069 5264 continue;
2c3dfe3f 5265 sfcp = sp->fcport;
f08b7251 5266 if (!(sfcp->flags & FCF_FCP2_DEVICE))
2c3dfe3f 5267 continue;
bdf79621 5268
8f7daead
GM		 5269 if (IS_QLA82XX(ha))
5270 set_bit(FCOE_CTX_RESET_NEEDED,
5271 &vha->dpc_flags);
5272 else
5273 set_bit(ISP_ABORT_NEEDED,
e315cd28 5274 &vha->dpc_flags);
2c3dfe3f
SJ		 5275 break;
5276 }
5277 spin_unlock_irqrestore(&ha->hardware_lock,
e315cd28 5278 cpu_flags);
1da177e4 5279 }
1da177e4
LT		 5280 start_dpc++;
5281 }
5282
5283 /* if the loop has been down for 4 minutes, reinit adapter */
e315cd28 5284 if (atomic_dec_and_test(&vha->loop_down_timer) != 0) {
0d6e61bc 5285 if (!(vha->device_flags & DFLG_NO_CABLE)) {
7c3df132 5286 ql_log(ql_log_warn, vha, 0x6009,
1da177e4
LT		 5287 "Loop down - aborting ISP.\n");
5288
8f7daead
GM		 5289 if (IS_QLA82XX(ha))
5290 set_bit(FCOE_CTX_RESET_NEEDED,
5291 &vha->dpc_flags);
5292 else
5293 set_bit(ISP_ABORT_NEEDED,
5294 &vha->dpc_flags);
1da177e4
LT		 5295 }
5296 }
7c3df132
SK		 5297 ql_dbg(ql_dbg_timer, vha, 0x600a,
5298 "Loop down - seconds remaining %d.\n",
5299 atomic_read(&vha->loop_down_timer));
1da177e4 5300 }
cefcaba6
SK		 5301 /* Check if beacon LED needs to be blinked for physical host only */
5302 if (!vha->vp_idx && (ha->beacon_blink_led == 1)) {
999916dc 5303 /* There is no beacon_blink function for ISP82xx */
7ec0effd 5304 if (!IS_P3P_TYPE(ha)) {
999916dc
SK		 5305 set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags);
5306 start_dpc++;
5307 }
f6df144c 5308 }
5309
550bf57d 5310 /* Process any deferred work. */
e315cd28 5311 if (!list_empty(&vha->work_list))
550bf57d
AV		 5312 start_dpc++;
5313
1da177e4 5314 /* Schedule the DPC routine if needed */
e315cd28
AC		 5315 if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) ||
5316 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) ||
5317 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags) ||
1da177e4 5318 start_dpc ||
e315cd28
AC		 5319 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) ||
5320 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) ||
a9083016
GM		 5321 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) ||
5322 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) ||
e315cd28 5323 test_bit(VP_DPC_NEEDED, &vha->dpc_flags) ||
50280c01 5324 test_bit(RELOGIN_NEEDED, &vha->dpc_flags))) {
7c3df132
SK		 5325 ql_dbg(ql_dbg_timer, vha, 0x600b,
5326 "isp_abort_needed=%d loop_resync_needed=%d "
5327 "fcport_update_needed=%d start_dpc=%d "
5328 "reset_marker_needed=%d",
5329 test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags),
5330 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags),
5331 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags),
5332 start_dpc,
5333 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags));
5334 ql_dbg(ql_dbg_timer, vha, 0x600c,
5335 "beacon_blink_needed=%d isp_unrecoverable=%d "
5336 "fcoe_ctx_reset_needed=%d vp_dpc_needed=%d "
50280c01 5337 "relogin_needed=%d.\n",
7c3df132
SK		 5338 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags),
5339 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags),
5340 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags),
5341 test_bit(VP_DPC_NEEDED, &vha->dpc_flags),
50280c01 5342 test_bit(RELOGIN_NEEDED, &vha->dpc_flags));
e315cd28 5343 qla2xxx_wake_dpc(vha);
7c3df132 5344 }
1da177e4 5345
e315cd28 5346 qla2x00_restart_timer(vha, WATCH_INTERVAL);
1da177e4
LT		 5347}
5348
5433383e
AV		 5349/* Firmware interface routines. */
5350
f73cb695 5351#define FW_BLOBS 11
5433383e
AV		 5352#define FW_ISP21XX 0
5353#define FW_ISP22XX 1
5354#define FW_ISP2300 2
5355#define FW_ISP2322 3
48c02fde 5356#define FW_ISP24XX 4
c3a2f0df 5357#define FW_ISP25XX 5
3a03eb79 5358#define FW_ISP81XX 6
a9083016 5359#define FW_ISP82XX 7
6246b8a1
GM		 5360#define FW_ISP2031 8
5361#define FW_ISP8031 9
2c5bbbb2 5362#define FW_ISP27XX 10
5433383e 5363
bb8ee499
AV		 5364#define FW_FILE_ISP21XX "ql2100_fw.bin"
5365#define FW_FILE_ISP22XX "ql2200_fw.bin"
5366#define FW_FILE_ISP2300 "ql2300_fw.bin"
5367#define FW_FILE_ISP2322 "ql2322_fw.bin"
5368#define FW_FILE_ISP24XX "ql2400_fw.bin"
c3a2f0df 5369#define FW_FILE_ISP25XX "ql2500_fw.bin"
3a03eb79 5370#define FW_FILE_ISP81XX "ql8100_fw.bin"
a9083016 5371#define FW_FILE_ISP82XX "ql8200_fw.bin"
6246b8a1
GM		 5372#define FW_FILE_ISP2031 "ql2600_fw.bin"
5373#define FW_FILE_ISP8031 "ql8300_fw.bin"
2c5bbbb2 5374#define FW_FILE_ISP27XX "ql2700_fw.bin"
f73cb695 5375
bb8ee499 5376
e1e82b6f 5377static DEFINE_MUTEX(qla_fw_lock);
5433383e
AV		 5378
5379static struct fw_blob qla_fw_blobs[FW_BLOBS] = {
bb8ee499
AV		 5380 { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, },
5381 { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, },
5382 { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, },
5383 { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, },
5384 { .name = FW_FILE_ISP24XX, },
c3a2f0df 5385 { .name = FW_FILE_ISP25XX, },
3a03eb79 5386 { .name = FW_FILE_ISP81XX, },
a9083016 5387 { .name = FW_FILE_ISP82XX, },
6246b8a1
GM		 5388 { .name = FW_FILE_ISP2031, },
5389 { .name = FW_FILE_ISP8031, },
2c5bbbb2 5390 { .name = FW_FILE_ISP27XX, },
5433383e
AV		 5391};
5392
5393struct fw_blob *
e315cd28 5394qla2x00_request_firmware(scsi_qla_host_t *vha)
5433383e 5395{
e315cd28 5396 struct qla_hw_data *ha = vha->hw;
5433383e
AV		 5397 struct fw_blob *blob;
5398
5433383e
AV		 5399 if (IS_QLA2100(ha)) {
5400 blob = &qla_fw_blobs[FW_ISP21XX];
5401 } else if (IS_QLA2200(ha)) {
5402 blob = &qla_fw_blobs[FW_ISP22XX];
48c02fde 5403 } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
5433383e 5404 blob = &qla_fw_blobs[FW_ISP2300];
48c02fde 5405 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
5433383e 5406 blob = &qla_fw_blobs[FW_ISP2322];
4d4df193 5407 } else if (IS_QLA24XX_TYPE(ha)) {
5433383e 5408 blob = &qla_fw_blobs[FW_ISP24XX];
c3a2f0df
AV		 5409 } else if (IS_QLA25XX(ha)) {
5410 blob = &qla_fw_blobs[FW_ISP25XX];
3a03eb79
AV		 5411 } else if (IS_QLA81XX(ha)) {
5412 blob = &qla_fw_blobs[FW_ISP81XX];
a9083016
GM		 5413 } else if (IS_QLA82XX(ha)) {
5414 blob = &qla_fw_blobs[FW_ISP82XX];
6246b8a1
GM		 5415 } else if (IS_QLA2031(ha)) {
5416 blob = &qla_fw_blobs[FW_ISP2031];
5417 } else if (IS_QLA8031(ha)) {
5418 blob = &qla_fw_blobs[FW_ISP8031];
2c5bbbb2
JC		 5419 } else if (IS_QLA27XX(ha)) {
5420 blob = &qla_fw_blobs[FW_ISP27XX];
8a655229
DC		 5421 } else {
5422 return NULL;
5433383e
AV		 5423 }
5424
e1e82b6f 5425 mutex_lock(&qla_fw_lock);
5433383e
AV		 5426 if (blob->fw)
5427 goto out;
5428
5429 if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) {
7c3df132
SK		 5430 ql_log(ql_log_warn, vha, 0x0063,
5431 "Failed to load firmware image (%s).\n", blob->name);
5433383e
AV		 5432 blob->fw = NULL;
5433 blob = NULL;
5434 goto out;
5435 }
5436
5437out:
e1e82b6f 5438 mutex_unlock(&qla_fw_lock);
5433383e
AV		 5439 return blob;
5440}
5441
5442static void
5443qla2x00_release_firmware(void)
5444{
5445 int idx;
5446
e1e82b6f 5447 mutex_lock(&qla_fw_lock);
5433383e 5448 for (idx = 0; idx < FW_BLOBS; idx++)
cf92549f 5449 release_firmware(qla_fw_blobs[idx].fw);
e1e82b6f 5450 mutex_unlock(&qla_fw_lock);
5433383e
AV		 5451}
5452
14e660e6
SJ		 5453static pci_ers_result_t
5454qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
5455{
85880801
AV		 5456 scsi_qla_host_t *vha = pci_get_drvdata(pdev);
5457 struct qla_hw_data *ha = vha->hw;
5458
7c3df132
SK		 5459 ql_dbg(ql_dbg_aer, vha, 0x9000,
5460 "PCI error detected, state %x.\n", state);
b9b12f73 5461
14e660e6
SJ		 5462 switch (state) {
5463 case pci_channel_io_normal:
85880801 5464 ha->flags.eeh_busy = 0;
14e660e6
SJ		 5465 return PCI_ERS_RESULT_CAN_RECOVER;
5466 case pci_channel_io_frozen:
85880801 5467 ha->flags.eeh_busy = 1;
a5b36321
LC		 5468 /* For ISP82XX complete any pending mailbox cmd */
5469 if (IS_QLA82XX(ha)) {
7190575f 5470 ha->flags.isp82xx_fw_hung = 1;
c8f6544e
CD		 5471 ql_dbg(ql_dbg_aer, vha, 0x9001, "Pci channel io frozen\n");
5472 qla82xx_clear_pending_mbx(vha);
a5b36321 5473 }
90a86fc0 5474 qla2x00_free_irqs(vha);
14e660e6 5475 pci_disable_device(pdev);
bddd2d65
LC		 5476 /* Return back all IOs */
5477 qla2x00_abort_all_cmds(vha, DID_RESET << 16);
14e660e6
SJ		 5478 return PCI_ERS_RESULT_NEED_RESET;
5479 case pci_channel_io_perm_failure:
85880801
AV		 5480 ha->flags.pci_channel_io_perm_failure = 1;
5481 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
14e660e6
SJ		 5482 return PCI_ERS_RESULT_DISCONNECT;
5483 }
5484 return PCI_ERS_RESULT_NEED_RESET;
5485}
5486
5487static pci_ers_result_t
5488qla2xxx_pci_mmio_enabled(struct pci_dev *pdev)
5489{
5490 int risc_paused = 0;
5491 uint32_t stat;
5492 unsigned long flags;
e315cd28
AC		 5493 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
5494 struct qla_hw_data *ha = base_vha->hw;
14e660e6
SJ		 5495 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
5496 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
5497
bcc5b6d3
SK		 5498 if (IS_QLA82XX(ha))
5499 return PCI_ERS_RESULT_RECOVERED;
5500
14e660e6
SJ		 5501 spin_lock_irqsave(&ha->hardware_lock, flags);
5502 if (IS_QLA2100(ha) || IS_QLA2200(ha)){
5503 stat = RD_REG_DWORD(&reg->hccr);
5504 if (stat & HCCR_RISC_PAUSE)
5505 risc_paused = 1;
5506 } else if (IS_QLA23XX(ha)) {
5507 stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
5508 if (stat & HSR_RISC_PAUSED)
5509 risc_paused = 1;
5510 } else if (IS_FWI2_CAPABLE(ha)) {
5511 stat = RD_REG_DWORD(&reg24->host_status);
5512 if (stat & HSRX_RISC_PAUSED)
5513 risc_paused = 1;
5514 }
5515 spin_unlock_irqrestore(&ha->hardware_lock, flags);
5516
5517 if (risc_paused) {
7c3df132
SK		 5518 ql_log(ql_log_info, base_vha, 0x9003,
5519 "RISC paused -- mmio_enabled, Dumping firmware.\n");
e315cd28 5520 ha->isp_ops->fw_dump(base_vha, 0);
14e660e6
SJ		 5521
5522 return PCI_ERS_RESULT_NEED_RESET;
5523 } else
5524 return PCI_ERS_RESULT_RECOVERED;
5525}
5526
fa492630
SK		 5527static uint32_t
5528qla82xx_error_recovery(scsi_qla_host_t *base_vha)
a5b36321
LC		 5529{
5530 uint32_t rval = QLA_FUNCTION_FAILED;
5531 uint32_t drv_active = 0;
5532 struct qla_hw_data *ha = base_vha->hw;
5533 int fn;
5534 struct pci_dev *other_pdev = NULL;
5535
7c3df132
SK		 5536 ql_dbg(ql_dbg_aer, base_vha, 0x9006,
5537 "Entered %s.\n", __func__);
a5b36321
LC		 5538
5539 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
5540
5541 if (base_vha->flags.online) {
5542 /* Abort all outstanding commands,
5543 * so as to be requeued later */
5544 qla2x00_abort_isp_cleanup(base_vha);
5545 }
5546
5547
5548 fn = PCI_FUNC(ha->pdev->devfn);
5549 while (fn > 0) {
5550 fn--;
7c3df132
SK		 5551 ql_dbg(ql_dbg_aer, base_vha, 0x9007,
5552 "Finding pci device at function = 0x%x.\n", fn);
a5b36321
LC		 5553 other_pdev =
5554 pci_get_domain_bus_and_slot(pci_domain_nr(ha->pdev->bus),
5555 ha->pdev->bus->number, PCI_DEVFN(PCI_SLOT(ha->pdev->devfn),
5556 fn));
5557
5558 if (!other_pdev)
5559 continue;
5560 if (atomic_read(&other_pdev->enable_cnt)) {
7c3df132
SK		 5561 ql_dbg(ql_dbg_aer, base_vha, 0x9008,
5562 "Found PCI func available and enable at 0x%x.\n",
5563 fn);
a5b36321
LC		 5564 pci_dev_put(other_pdev);
5565 break;
5566 }
5567 pci_dev_put(other_pdev);
5568 }
5569
5570 if (!fn) {
5571 /* Reset owner */
7c3df132
SK		 5572 ql_dbg(ql_dbg_aer, base_vha, 0x9009,
5573 "This devfn is reset owner = 0x%x.\n",
5574 ha->pdev->devfn);
a5b36321
LC		 5575 qla82xx_idc_lock(ha);
5576
5577 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 5578 QLA8XXX_DEV_INITIALIZING);
a5b36321
LC		 5579
5580 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION,
5581 QLA82XX_IDC_VERSION);
5582
5583 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
7c3df132
SK		 5584 ql_dbg(ql_dbg_aer, base_vha, 0x900a,
5585 "drv_active = 0x%x.\n", drv_active);
a5b36321
LC		 5586
5587 qla82xx_idc_unlock(ha);
5588 /* Reset if device is not already reset
5589 * drv_active would be 0 if a reset has already been done
5590 */
5591 if (drv_active)
5592 rval = qla82xx_start_firmware(base_vha);
5593 else
5594 rval = QLA_SUCCESS;
5595 qla82xx_idc_lock(ha);
5596
5597 if (rval != QLA_SUCCESS) {
7c3df132
SK		 5598 ql_log(ql_log_info, base_vha, 0x900b,
5599 "HW State: FAILED.\n");
a5b36321
LC		 5600 qla82xx_clear_drv_active(ha);
5601 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 5602 QLA8XXX_DEV_FAILED);
a5b36321 5603 } else {
7c3df132
SK		 5604 ql_log(ql_log_info, base_vha, 0x900c,
5605 "HW State: READY.\n");
a5b36321 5606 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 5607 QLA8XXX_DEV_READY);
a5b36321 5608 qla82xx_idc_unlock(ha);
7190575f 5609 ha->flags.isp82xx_fw_hung = 0;
a5b36321
LC		 5610 rval = qla82xx_restart_isp(base_vha);
5611 qla82xx_idc_lock(ha);
5612 /* Clear driver state register */
5613 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, 0);
5614 qla82xx_set_drv_active(base_vha);
5615 }
5616 qla82xx_idc_unlock(ha);
5617 } else {
7c3df132
SK		 5618 ql_dbg(ql_dbg_aer, base_vha, 0x900d,
5619 "This devfn is not reset owner = 0x%x.\n",
5620 ha->pdev->devfn);
a5b36321 5621 if ((qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE) ==
7d613ac6 5622 QLA8XXX_DEV_READY)) {
7190575f 5623 ha->flags.isp82xx_fw_hung = 0;
a5b36321
LC		 5624 rval = qla82xx_restart_isp(base_vha);
5625 qla82xx_idc_lock(ha);
5626 qla82xx_set_drv_active(base_vha);
5627 qla82xx_idc_unlock(ha);
5628 }
5629 }
5630 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
5631
5632 return rval;
5633}
5634
14e660e6
SJ		 5635static pci_ers_result_t
5636qla2xxx_pci_slot_reset(struct pci_dev *pdev)
5637{
5638 pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT;
e315cd28
AC		 5639 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
5640 struct qla_hw_data *ha = base_vha->hw;
90a86fc0
JC		 5641 struct rsp_que *rsp;
5642 int rc, retries = 10;
09483916 5643
7c3df132
SK		 5644 ql_dbg(ql_dbg_aer, base_vha, 0x9004,
5645 "Slot Reset.\n");
85880801 5646
90a86fc0
JC		 5647 /* Workaround: qla2xxx driver which access hardware earlier
5648 * needs error state to be pci_channel_io_online.
5649 * Otherwise mailbox command timesout.
5650 */
5651 pdev->error_state = pci_channel_io_normal;
5652
5653 pci_restore_state(pdev);
5654
8c1496bd
RL		 5655 /* pci_restore_state() clears the saved_state flag of the device
5656 * save restored state which resets saved_state flag
5657 */
5658 pci_save_state(pdev);
5659
09483916
BH		 5660 if (ha->mem_only)
5661 rc = pci_enable_device_mem(pdev);
5662 else
5663 rc = pci_enable_device(pdev);
14e660e6 5664
09483916 5665 if (rc) {
7c3df132 5666 ql_log(ql_log_warn, base_vha, 0x9005,
14e660e6 5667 "Can't re-enable PCI device after reset.\n");
a5b36321 5668 goto exit_slot_reset;
14e660e6 5669 }
14e660e6 5670
90a86fc0
JC		 5671 rsp = ha->rsp_q_map[0];
5672 if (qla2x00_request_irqs(ha, rsp))
a5b36321 5673 goto exit_slot_reset;
90a86fc0 5674
e315cd28 5675 if (ha->isp_ops->pci_config(base_vha))
a5b36321
LC		 5676 goto exit_slot_reset;
5677
5678 if (IS_QLA82XX(ha)) {
5679 if (qla82xx_error_recovery(base_vha) == QLA_SUCCESS) {
5680 ret = PCI_ERS_RESULT_RECOVERED;
5681 goto exit_slot_reset;
5682 } else
5683 goto exit_slot_reset;
5684 }
14e660e6 5685
90a86fc0
JC		 5686 while (ha->flags.mbox_busy && retries--)
5687 msleep(1000);
85880801 5688
e315cd28 5689 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
a9083016 5690 if (ha->isp_ops->abort_isp(base_vha) == QLA_SUCCESS)
14e660e6 5691 ret = PCI_ERS_RESULT_RECOVERED;
e315cd28 5692 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
14e660e6 5693
90a86fc0 5694
a5b36321 5695exit_slot_reset:
7c3df132
SK		 5696 ql_dbg(ql_dbg_aer, base_vha, 0x900e,
5697 "slot_reset return %x.\n", ret);
85880801 5698
14e660e6
SJ		 5699 return ret;
5700}
5701
5702static void
5703qla2xxx_pci_resume(struct pci_dev *pdev)
5704{
e315cd28
AC		 5705 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
5706 struct qla_hw_data *ha = base_vha->hw;
14e660e6
SJ		 5707 int ret;
5708
7c3df132
SK		 5709 ql_dbg(ql_dbg_aer, base_vha, 0x900f,
5710 "pci_resume.\n");
85880801 5711
e315cd28 5712 ret = qla2x00_wait_for_hba_online(base_vha);
14e660e6 5713 if (ret != QLA_SUCCESS) {
7c3df132
SK		 5714 ql_log(ql_log_fatal, base_vha, 0x9002,
5715 "The device failed to resume I/O from slot/link_reset.\n");
14e660e6 5716 }
85880801 5717
3e46f031
LC		 5718 pci_cleanup_aer_uncorrect_error_status(pdev);
5719
85880801 5720 ha->flags.eeh_busy = 0;
14e660e6
SJ		 5721}
5722
2d5a4c34
HM		 5723static void
5724qla83xx_disable_laser(scsi_qla_host_t *vha)
5725{
5726 uint32_t reg, data, fn;
5727 struct qla_hw_data *ha = vha->hw;
5728 struct device_reg_24xx __iomem *isp_reg = &ha->iobase->isp24;
5729
5730 /* pci func #/port # */
5731 ql_dbg(ql_dbg_init, vha, 0x004b,
5732 "Disabling Laser for hba: %p\n", vha);
5733
5734 fn = (RD_REG_DWORD(&isp_reg->ctrl_status) &
5735 (BIT_15|BIT_14|BIT_13|BIT_12));
5736
5737 fn = (fn >> 12);
5738
5739 if (fn & 1)
5740 reg = PORT_1_2031;
5741 else
5742 reg = PORT_0_2031;
5743
5744 data = LASER_OFF_2031;
5745
5746 qla83xx_wr_reg(vha, reg, data);
5747}
5748
a55b2d21 5749static const struct pci_error_handlers qla2xxx_err_handler = {
14e660e6
SJ		 5750 .error_detected = qla2xxx_pci_error_detected,
5751 .mmio_enabled = qla2xxx_pci_mmio_enabled,
5752 .slot_reset = qla2xxx_pci_slot_reset,
5753 .resume = qla2xxx_pci_resume,
5754};
5755
5433383e 5756static struct pci_device_id qla2xxx_pci_tbl[] = {
47f5e069
AV		 5757 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) },
5758 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) },
5759 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) },
5760 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) },
5761 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) },
5762 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) },
5763 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) },
5764 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) },
5765 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) },
4d4df193 5766 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) },
47f5e069
AV		 5767 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) },
5768 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) },
c3a2f0df 5769 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) },
6246b8a1 5770 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2031) },
3a03eb79 5771 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) },
a9083016 5772 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) },
650f528f 5773 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8031) },
8ae6d9c7 5774 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISPF001) },
7ec0effd 5775 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8044) },
f73cb695 5776 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2071) },
2c5bbbb2 5777 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2271) },
5433383e
AV		 5778 { 0 },
5779};
5780MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl);
5781
fca29703 5782static struct pci_driver qla2xxx_pci_driver = {
cb63067a 5783 .name = QLA2XXX_DRIVER_NAME,
0a21ef1e
JB		 5784 .driver = {
5785 .owner = THIS_MODULE,
5786 },
fca29703 5787 .id_table = qla2xxx_pci_tbl,
7ee61397 5788 .probe = qla2x00_probe_one,
4c993f76 5789 .remove = qla2x00_remove_one,
e30d1756 5790 .shutdown = qla2x00_shutdown,
14e660e6 5791 .err_handler = &qla2xxx_err_handler,
fca29703
AV		 5792};
5793
75ef9de1 5794static const struct file_operations apidev_fops = {
6a03b4cd 5795 .owner = THIS_MODULE,
6038f373 5796 .llseek = noop_llseek,
6a03b4cd
HZ		 5797};
5798
1da177e4
LT		 5799/**
5800 * qla2x00_module_init - Module initialization.
5801 **/
5802static int __init
5803qla2x00_module_init(void)
5804{
fca29703
AV		 5805 int ret = 0;
5806
1da177e4 5807 /* Allocate cache for SRBs. */
354d6b21 5808 srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0,
20c2df83 5809 SLAB_HWCACHE_ALIGN, NULL);
1da177e4 5810 if (srb_cachep == NULL) {
7c3df132
SK		 5811 ql_log(ql_log_fatal, NULL, 0x0001,
5812 "Unable to allocate SRB cache...Failing load!.\n");
1da177e4
LT		 5813 return -ENOMEM;
5814 }
5815
2d70c103
NB		 5816 /* Initialize target kmem_cache and mem_pools */
5817 ret = qlt_init();
5818 if (ret < 0) {
5819 kmem_cache_destroy(srb_cachep);
5820 return ret;
5821 } else if (ret > 0) {
5822 /*
5823 * If initiator mode is explictly disabled by qlt_init(),
5824 * prevent scsi_transport_fc.c:fc_scsi_scan_rport() from
5825 * performing scsi_scan_target() during LOOP UP event.
5826 */
5827 qla2xxx_transport_functions.disable_target_scan = 1;
5828 qla2xxx_transport_vport_functions.disable_target_scan = 1;
5829 }
5830
1da177e4
LT		 5831 /* Derive version string. */
5832 strcpy(qla2x00_version_str, QLA2XXX_VERSION);
11010fec 5833 if (ql2xextended_error_logging)
0181944f
AV		 5834 strcat(qla2x00_version_str, "-debug");
5835
1c97a12a
AV		 5836 qla2xxx_transport_template =
5837 fc_attach_transport(&qla2xxx_transport_functions);
2c3dfe3f
SJ		 5838 if (!qla2xxx_transport_template) {
5839 kmem_cache_destroy(srb_cachep);
7c3df132
SK		 5840 ql_log(ql_log_fatal, NULL, 0x0002,
5841 "fc_attach_transport failed...Failing load!.\n");
2d70c103 5842 qlt_exit();
1da177e4 5843 return -ENODEV;
2c3dfe3f 5844 }
6a03b4cd
HZ		 5845
5846 apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops);
5847 if (apidev_major < 0) {
7c3df132
SK		 5848 ql_log(ql_log_fatal, NULL, 0x0003,
5849 "Unable to register char device %s.\n", QLA2XXX_APIDEV);
6a03b4cd
HZ		 5850 }
5851
2c3dfe3f
SJ		 5852 qla2xxx_transport_vport_template =
5853 fc_attach_transport(&qla2xxx_transport_vport_functions);
5854 if (!qla2xxx_transport_vport_template) {
5855 kmem_cache_destroy(srb_cachep);
2d70c103 5856 qlt_exit();
2c3dfe3f 5857 fc_release_transport(qla2xxx_transport_template);
7c3df132
SK		 5858 ql_log(ql_log_fatal, NULL, 0x0004,
5859 "fc_attach_transport vport failed...Failing load!.\n");
1da177e4 5860 return -ENODEV;
2c3dfe3f 5861 }
7c3df132
SK		 5862 ql_log(ql_log_info, NULL, 0x0005,
5863 "QLogic Fibre Channel HBA Driver: %s.\n",
fd9a29f0 5864 qla2x00_version_str);
7ee61397 5865 ret = pci_register_driver(&qla2xxx_pci_driver);
fca29703
AV		 5866 if (ret) {
5867 kmem_cache_destroy(srb_cachep);
2d70c103 5868 qlt_exit();
fca29703 5869 fc_release_transport(qla2xxx_transport_template);
2c3dfe3f 5870 fc_release_transport(qla2xxx_transport_vport_template);
7c3df132
SK		 5871 ql_log(ql_log_fatal, NULL, 0x0006,
5872 "pci_register_driver failed...ret=%d Failing load!.\n",
5873 ret);
fca29703
AV		 5874 }
5875 return ret;
1da177e4
LT		 5876}
5877
5878/**
5879 * qla2x00_module_exit - Module cleanup.
5880 **/
5881static void __exit
5882qla2x00_module_exit(void)
5883{
6a03b4cd 5884 unregister_chrdev(apidev_major, QLA2XXX_APIDEV);
7ee61397 5885 pci_unregister_driver(&qla2xxx_pci_driver);
5433383e 5886 qla2x00_release_firmware();
354d6b21 5887 kmem_cache_destroy(srb_cachep);
2d70c103 5888 qlt_exit();
a9083016
GM		 5889 if (ctx_cachep)
5890 kmem_cache_destroy(ctx_cachep);
1da177e4 5891 fc_release_transport(qla2xxx_transport_template);
2c3dfe3f 5892 fc_release_transport(qla2xxx_transport_vport_template);
1da177e4
LT		 5893}
5894
5895module_init(qla2x00_module_init);
5896module_exit(qla2x00_module_exit);
5897
5898MODULE_AUTHOR("QLogic Corporation");
5899MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver");
5900MODULE_LICENSE("GPL");
5901MODULE_VERSION(QLA2XXX_VERSION);
bb8ee499
AV		 5902MODULE_FIRMWARE(FW_FILE_ISP21XX);
5903MODULE_FIRMWARE(FW_FILE_ISP22XX);
5904MODULE_FIRMWARE(FW_FILE_ISP2300);
5905MODULE_FIRMWARE(FW_FILE_ISP2322);
5906MODULE_FIRMWARE(FW_FILE_ISP24XX);
61623fc3 5907MODULE_FIRMWARE(FW_FILE_ISP25XX);
Linux 6.x block layer and io_uring tree(s)