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qla2xxx: fix crash due to task mgmt cmd type
[linux-2.6-block.git] / drivers / scsi / qla2xxx / qla_os.c
CommitLineData
1da177e4 1/*
fa90c54f 2 * QLogic Fibre Channel HBA Driver
bd21eaf9 3 * Copyright (c) 2003-2014 QLogic Corporation
1da177e4 4 *
fa90c54f 5 * See LICENSE.qla2xxx for copyright and licensing details.
1da177e4
LT		 6 */
7#include "qla_def.h"
8
9#include <linux/moduleparam.h>
10#include <linux/vmalloc.h>
1da177e4 11#include <linux/delay.h>
39a11240 12#include <linux/kthread.h>
e1e82b6f 13#include <linux/mutex.h>
3420d36c 14#include <linux/kobject.h>
5a0e3ad6 15#include <linux/slab.h>
1da177e4
LT		 16#include <scsi/scsi_tcq.h>
17#include <scsi/scsicam.h>
18#include <scsi/scsi_transport.h>
19#include <scsi/scsi_transport_fc.h>
20
2d70c103
NB		 21#include "qla_target.h"
22
1da177e4
LT		 23/*
24 * Driver version
25 */
26char qla2x00_version_str[40];
27
6a03b4cd
HZ		 28static int apidev_major;
29
1da177e4
LT		 30/*
31 * SRB allocation cache
32 */
e18b890b 33static struct kmem_cache *srb_cachep;
1da177e4 34
a9083016
GM		 35/*
36 * CT6 CTX allocation cache
37 */
38static struct kmem_cache *ctx_cachep;
3ce8866c
SK		 39/*
40 * error level for logging
41 */
42int ql_errlev = ql_log_all;
a9083016 43
fa492630 44static int ql2xenableclass2;
2d70c103
NB		 45module_param(ql2xenableclass2, int, S_IRUGO|S_IRUSR);
46MODULE_PARM_DESC(ql2xenableclass2,
47 "Specify if Class 2 operations are supported from the very "
48 "beginning. Default is 0 - class 2 not supported.");
49
8ae6d9c7 50
1da177e4 51int ql2xlogintimeout = 20;
f2019cb1 52module_param(ql2xlogintimeout, int, S_IRUGO);
1da177e4
LT		 53MODULE_PARM_DESC(ql2xlogintimeout,
54 "Login timeout value in seconds.");
55
a7b61842 56int qlport_down_retry;
f2019cb1 57module_param(qlport_down_retry, int, S_IRUGO);
1da177e4 58MODULE_PARM_DESC(qlport_down_retry,
900d9f98 59 "Maximum number of command retries to a port that returns "
1da177e4
LT		 60 "a PORT-DOWN status.");
61
1da177e4
LT		 62int ql2xplogiabsentdevice;
63module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR);
64MODULE_PARM_DESC(ql2xplogiabsentdevice,
65 "Option to enable PLOGI to devices that are not present after "
900d9f98 66 "a Fabric scan. This is needed for several broken switches. "
1da177e4
LT		 67 "Default is 0 - no PLOGI. 1 - perfom PLOGI.");
68
1da177e4 69int ql2xloginretrycount = 0;
f2019cb1 70module_param(ql2xloginretrycount, int, S_IRUGO);
1da177e4
LT		 71MODULE_PARM_DESC(ql2xloginretrycount,
72 "Specify an alternate value for the NVRAM login retry count.");
73
a7a167bf 74int ql2xallocfwdump = 1;
f2019cb1 75module_param(ql2xallocfwdump, int, S_IRUGO);
a7a167bf
AV		 76MODULE_PARM_DESC(ql2xallocfwdump,
77 "Option to enable allocation of memory for a firmware dump "
78 "during HBA initialization. Memory allocation requirements "
79 "vary by ISP type. Default is 1 - allocate memory.");
80
11010fec 81int ql2xextended_error_logging;
27d94035 82module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
11010fec 83MODULE_PARM_DESC(ql2xextended_error_logging,
3ce8866c
SK		 84 "Option to enable extended error logging,\n"
85 "\t\tDefault is 0 - no logging. 0x40000000 - Module Init & Probe.\n"
86 "\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n"
87 "\t\t0x08000000 - IO tracing. 0x04000000 - DPC Thread.\n"
88 "\t\t0x02000000 - Async events. 0x01000000 - Timer routines.\n"
89 "\t\t0x00800000 - User space. 0x00400000 - Task Management.\n"
90 "\t\t0x00200000 - AER/EEH. 0x00100000 - Multi Q.\n"
91 "\t\t0x00080000 - P3P Specific. 0x00040000 - Virtual Port.\n"
92 "\t\t0x00020000 - Buffer Dump. 0x00010000 - Misc.\n"
29f9f90c
CD		 93 "\t\t0x00008000 - Verbose. 0x00004000 - Target.\n"
94 "\t\t0x00002000 - Target Mgmt. 0x00001000 - Target TMF.\n"
3ce8866c 95 "\t\t0x7fffffff - For enabling all logs, can be too many logs.\n"
cfb0919c
CD		 96 "\t\t0x1e400000 - Preferred value for capturing essential "
97 "debug information (equivalent to old "
98 "ql2xextended_error_logging=1).\n"
3ce8866c 99 "\t\tDo LOGICAL OR of the value to enable more than one level");
0181944f 100
a9083016 101int ql2xshiftctondsd = 6;
f2019cb1 102module_param(ql2xshiftctondsd, int, S_IRUGO);
a9083016
GM		 103MODULE_PARM_DESC(ql2xshiftctondsd,
104 "Set to control shifting of command type processing "
105 "based on total number of SG elements.");
106
7e47e5ca 107int ql2xfdmienable=1;
de187df8 108module_param(ql2xfdmienable, int, S_IRUGO|S_IWUSR);
cca5335c 109MODULE_PARM_DESC(ql2xfdmienable,
7794a5af
FW		 110 "Enables FDMI registrations. "
111 "0 - no FDMI. Default is 1 - perform FDMI.");
cca5335c 112
50280c01
CD		 113#define MAX_Q_DEPTH 32
114static int ql2xmaxqdepth = MAX_Q_DEPTH;
df7baa50
AV		 115module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR);
116MODULE_PARM_DESC(ql2xmaxqdepth,
e92e4a8f
CD		 117 "Maximum queue depth to set for each LUN. "
118 "Default is 32.");
df7baa50 119
9e522cd8
AE		 120int ql2xenabledif = 2;
121module_param(ql2xenabledif, int, S_IRUGO);
bad75002 122MODULE_PARM_DESC(ql2xenabledif,
b97f5d0b
SM		 123 " Enable T10-CRC-DIF:\n"
124 " Default is 2.\n"
125 " 0 -- No DIF Support\n"
126 " 1 -- Enable DIF for all types\n"
127 " 2 -- Enable DIF for all types, except Type 0.\n");
bad75002 128
8cb2049c 129int ql2xenablehba_err_chk = 2;
bad75002
AE		 130module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR);
131MODULE_PARM_DESC(ql2xenablehba_err_chk,
8cb2049c 132 " Enable T10-CRC-DIF Error isolation by HBA:\n"
b97f5d0b 133 " Default is 2.\n"
8cb2049c
AE		 134 " 0 -- Error isolation disabled\n"
135 " 1 -- Error isolation enabled only for DIX Type 0\n"
136 " 2 -- Error isolation enabled for all Types\n");
bad75002 137
e5896bd5 138int ql2xiidmaenable=1;
f2019cb1 139module_param(ql2xiidmaenable, int, S_IRUGO);
e5896bd5
AV		 140MODULE_PARM_DESC(ql2xiidmaenable,
141 "Enables iIDMA settings "
142 "Default is 1 - perform iIDMA. 0 - no iIDMA.");
143
73208dfd 144int ql2xmaxqueues = 1;
f2019cb1 145module_param(ql2xmaxqueues, int, S_IRUGO);
73208dfd
AC		 146MODULE_PARM_DESC(ql2xmaxqueues,
147 "Enables MQ settings "
ae68230c
JP		 148 "Default is 1 for single queue. Set it to number "
149 "of queues in MQ mode.");
68ca949c
AC		 150
151int ql2xmultique_tag;
f2019cb1 152module_param(ql2xmultique_tag, int, S_IRUGO);
68ca949c
AC		 153MODULE_PARM_DESC(ql2xmultique_tag,
154 "Enables CPU affinity settings for the driver "
155 "Default is 0 for no affinity of request and response IO. "
156 "Set it to 1 to turn on the cpu affinity.");
e337d907
AV		 157
158int ql2xfwloadbin;
86e45bf6 159module_param(ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
e337d907 160MODULE_PARM_DESC(ql2xfwloadbin,
7c3df132
SK		 161 "Option to specify location from which to load ISP firmware:.\n"
162 " 2 -- load firmware via the request_firmware() (hotplug).\n"
e337d907
AV		 163 " interface.\n"
164 " 1 -- load firmware from flash.\n"
165 " 0 -- use default semantics.\n");
166
ae97c91e 167int ql2xetsenable;
f2019cb1 168module_param(ql2xetsenable, int, S_IRUGO);
ae97c91e
AV		 169MODULE_PARM_DESC(ql2xetsenable,
170 "Enables firmware ETS burst."
171 "Default is 0 - skip ETS enablement.");
172
6907869d 173int ql2xdbwr = 1;
86e45bf6 174module_param(ql2xdbwr, int, S_IRUGO|S_IWUSR);
a9083016 175MODULE_PARM_DESC(ql2xdbwr,
08de2844
GM		 176 "Option to specify scheme for request queue posting.\n"
177 " 0 -- Regular doorbell.\n"
178 " 1 -- CAMRAM doorbell (faster).\n");
a9083016 179
f4c496c1 180int ql2xtargetreset = 1;
f2019cb1 181module_param(ql2xtargetreset, int, S_IRUGO);
f4c496c1
GM		 182MODULE_PARM_DESC(ql2xtargetreset,
183 "Enable target reset."
184 "Default is 1 - use hw defaults.");
185
4da26e16 186int ql2xgffidenable;
f2019cb1 187module_param(ql2xgffidenable, int, S_IRUGO);
4da26e16
CD		 188MODULE_PARM_DESC(ql2xgffidenable,
189 "Enables GFF_ID checks of port type. "
190 "Default is 0 - Do not use GFF_ID information.");
a9083016 191
3822263e 192int ql2xasynctmfenable;
f2019cb1 193module_param(ql2xasynctmfenable, int, S_IRUGO);
3822263e
MI		 194MODULE_PARM_DESC(ql2xasynctmfenable,
195 "Enables issue of TM IOCBs asynchronously via IOCB mechanism"
196 "Default is 0 - Issue TM IOCBs via mailbox mechanism.");
ed0de87c
GM		 197
198int ql2xdontresethba;
86e45bf6 199module_param(ql2xdontresethba, int, S_IRUGO|S_IWUSR);
ed0de87c 200MODULE_PARM_DESC(ql2xdontresethba,
08de2844
GM		 201 "Option to specify reset behaviour.\n"
202 " 0 (Default) -- Reset on failure.\n"
203 " 1 -- Do not reset on failure.\n");
ed0de87c 204
1abf635d
HR		 205uint64_t ql2xmaxlun = MAX_LUNS;
206module_param(ql2xmaxlun, ullong, S_IRUGO);
82515920
AV		 207MODULE_PARM_DESC(ql2xmaxlun,
208 "Defines the maximum LU number to register with the SCSI "
209 "midlayer. Default is 65535.");
210
08de2844
GM		 211int ql2xmdcapmask = 0x1F;
212module_param(ql2xmdcapmask, int, S_IRUGO);
213MODULE_PARM_DESC(ql2xmdcapmask,
214 "Set the Minidump driver capture mask level. "
6e96fa7b 215 "Default is 0x1F - Can be set to 0x3, 0x7, 0xF, 0x1F, 0x7F.");
08de2844 216
3aadff35 217int ql2xmdenable = 1;
08de2844
GM		 218module_param(ql2xmdenable, int, S_IRUGO);
219MODULE_PARM_DESC(ql2xmdenable,
220 "Enable/disable MiniDump. "
3aadff35
GM		 221 "0 - MiniDump disabled. "
222 "1 (Default) - MiniDump enabled.");
08de2844 223
1da177e4 224/*
fa2a1ce5 225 * SCSI host template entry points
1da177e4
LT		 226 */
227static int qla2xxx_slave_configure(struct scsi_device * device);
f4f051eb 228static int qla2xxx_slave_alloc(struct scsi_device *);
1e99e33a
AV		 229static int qla2xxx_scan_finished(struct Scsi_Host *, unsigned long time);
230static void qla2xxx_scan_start(struct Scsi_Host *);
f4f051eb 231static void qla2xxx_slave_destroy(struct scsi_device *);
f281233d 232static int qla2xxx_queuecommand(struct Scsi_Host *h, struct scsi_cmnd *cmd);
1da177e4
LT		 233static int qla2xxx_eh_abort(struct scsi_cmnd *);
234static int qla2xxx_eh_device_reset(struct scsi_cmnd *);
523ec773 235static int qla2xxx_eh_target_reset(struct scsi_cmnd *);
1da177e4
LT		 236static int qla2xxx_eh_bus_reset(struct scsi_cmnd *);
237static int qla2xxx_eh_host_reset(struct scsi_cmnd *);
1da177e4 238
e881a172 239static int qla2x00_change_queue_depth(struct scsi_device *, int, int);
ce7e4af7 240static int qla2x00_change_queue_type(struct scsi_device *, int);
1a2fbf18 241static void qla2x00_clear_drv_active(struct qla_hw_data *);
3491255e 242static void qla2x00_free_device(scsi_qla_host_t *);
2d5a4c34 243static void qla83xx_disable_laser(scsi_qla_host_t *vha);
ce7e4af7 244
a5326f86 245struct scsi_host_template qla2xxx_driver_template = {
1da177e4 246 .module = THIS_MODULE,
cb63067a 247 .name = QLA2XXX_DRIVER_NAME,
a5326f86 248 .queuecommand = qla2xxx_queuecommand,
fca29703
AV		 249
250 .eh_abort_handler = qla2xxx_eh_abort,
251 .eh_device_reset_handler = qla2xxx_eh_device_reset,
523ec773 252 .eh_target_reset_handler = qla2xxx_eh_target_reset,
fca29703
AV		 253 .eh_bus_reset_handler = qla2xxx_eh_bus_reset,
254 .eh_host_reset_handler = qla2xxx_eh_host_reset,
255
256 .slave_configure = qla2xxx_slave_configure,
257
258 .slave_alloc = qla2xxx_slave_alloc,
259 .slave_destroy = qla2xxx_slave_destroy,
ed677086
AV		 260 .scan_finished = qla2xxx_scan_finished,
261 .scan_start = qla2xxx_scan_start,
ce7e4af7
AV		 262 .change_queue_depth = qla2x00_change_queue_depth,
263 .change_queue_type = qla2x00_change_queue_type,
fca29703
AV		 264 .this_id = -1,
265 .cmd_per_lun = 3,
266 .use_clustering = ENABLE_CLUSTERING,
267 .sg_tablesize = SG_ALL,
268
269 .max_sectors = 0xFFFF,
afb046e2 270 .shost_attrs = qla2x00_host_attrs,
2d70c103
NB		 271
272 .supported_mode = MODE_INITIATOR,
fca29703
AV		 273};
274
1da177e4 275static struct scsi_transport_template *qla2xxx_transport_template = NULL;
2c3dfe3f 276struct scsi_transport_template *qla2xxx_transport_vport_template = NULL;
1da177e4 277
1da177e4
LT		 278/* TODO Convert to inlines
279 *
280 * Timer routines
281 */
1da177e4 282
2c3dfe3f 283__inline__ void
e315cd28 284qla2x00_start_timer(scsi_qla_host_t *vha, void *func, unsigned long interval)
1da177e4 285{
e315cd28
AC		 286 init_timer(&vha->timer);
287 vha->timer.expires = jiffies + interval * HZ;
288 vha->timer.data = (unsigned long)vha;
289 vha->timer.function = (void (*)(unsigned long))func;
290 add_timer(&vha->timer);
291 vha->timer_active = 1;
1da177e4
LT		 292}
293
294static inline void
e315cd28 295qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval)
1da177e4 296{
a9083016 297 /* Currently used for 82XX only. */
7c3df132
SK		 298 if (vha->device_flags & DFLG_DEV_FAILED) {
299 ql_dbg(ql_dbg_timer, vha, 0x600d,
300 "Device in a failed state, returning.\n");
a9083016 301 return;
7c3df132 302 }
a9083016 303
e315cd28 304 mod_timer(&vha->timer, jiffies + interval * HZ);
1da177e4
LT		 305}
306
a824ebb3 307static __inline__ void
e315cd28 308qla2x00_stop_timer(scsi_qla_host_t *vha)
1da177e4 309{
e315cd28
AC		 310 del_timer_sync(&vha->timer);
311 vha->timer_active = 0;
1da177e4
LT		 312}
313
1da177e4
LT		 314static int qla2x00_do_dpc(void *data);
315
316static void qla2x00_rst_aen(scsi_qla_host_t *);
317
73208dfd
AC		 318static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t,
319 struct req_que **, struct rsp_que **);
e30d1756 320static void qla2x00_free_fw_dump(struct qla_hw_data *);
e315cd28 321static void qla2x00_mem_free(struct qla_hw_data *);
1da177e4 322
1da177e4 323/* -------------------------------------------------------------------------- */
9a347ff4
CD		 324static int qla2x00_alloc_queues(struct qla_hw_data *ha, struct req_que *req,
325 struct rsp_que *rsp)
73208dfd 326{
7c3df132 327 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2afa19a9 328 ha->req_q_map = kzalloc(sizeof(struct req_que *) * ha->max_req_queues,
73208dfd
AC		 329 GFP_KERNEL);
330 if (!ha->req_q_map) {
7c3df132
SK		 331 ql_log(ql_log_fatal, vha, 0x003b,
332 "Unable to allocate memory for request queue ptrs.\n");
73208dfd
AC		 333 goto fail_req_map;
334 }
335
2afa19a9 336 ha->rsp_q_map = kzalloc(sizeof(struct rsp_que *) * ha->max_rsp_queues,
73208dfd
AC		 337 GFP_KERNEL);
338 if (!ha->rsp_q_map) {
7c3df132
SK		 339 ql_log(ql_log_fatal, vha, 0x003c,
340 "Unable to allocate memory for response queue ptrs.\n");
73208dfd
AC		 341 goto fail_rsp_map;
342 }
9a347ff4
CD		 343 /*
344 * Make sure we record at least the request and response queue zero in
345 * case we need to free them if part of the probe fails.
346 */
347 ha->rsp_q_map[0] = rsp;
348 ha->req_q_map[0] = req;
73208dfd
AC		 349 set_bit(0, ha->rsp_qid_map);
350 set_bit(0, ha->req_qid_map);
351 return 1;
352
353fail_rsp_map:
354 kfree(ha->req_q_map);
355 ha->req_q_map = NULL;
356fail_req_map:
357 return -ENOMEM;
358}
359
2afa19a9 360static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req)
73208dfd 361{
8ae6d9c7
GM		 362 if (IS_QLAFX00(ha)) {
363 if (req && req->ring_fx00)
364 dma_free_coherent(&ha->pdev->dev,
365 (req->length_fx00 + 1) * sizeof(request_t),
366 req->ring_fx00, req->dma_fx00);
367 } else if (req && req->ring)
73208dfd
AC		 368 dma_free_coherent(&ha->pdev->dev,
369 (req->length + 1) * sizeof(request_t),
370 req->ring, req->dma);
371
8d93f550
CD		 372 if (req)
373 kfree(req->outstanding_cmds);
374
73208dfd
AC		 375 kfree(req);
376 req = NULL;
377}
378
2afa19a9
AC		 379static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp)
380{
8ae6d9c7
GM		 381 if (IS_QLAFX00(ha)) {
382 if (rsp && rsp->ring)
383 dma_free_coherent(&ha->pdev->dev,
384 (rsp->length_fx00 + 1) * sizeof(request_t),
385 rsp->ring_fx00, rsp->dma_fx00);
386 } else if (rsp && rsp->ring) {
2afa19a9
AC		 387 dma_free_coherent(&ha->pdev->dev,
388 (rsp->length + 1) * sizeof(response_t),
389 rsp->ring, rsp->dma);
8ae6d9c7 390 }
2afa19a9
AC		 391 kfree(rsp);
392 rsp = NULL;
393}
394
73208dfd
AC		 395static void qla2x00_free_queues(struct qla_hw_data *ha)
396{
397 struct req_que *req;
398 struct rsp_que *rsp;
399 int cnt;
400
2afa19a9 401 for (cnt = 0; cnt < ha->max_req_queues; cnt++) {
73208dfd 402 req = ha->req_q_map[cnt];
2afa19a9 403 qla2x00_free_req_que(ha, req);
73208dfd 404 }
73208dfd
AC		 405 kfree(ha->req_q_map);
406 ha->req_q_map = NULL;
2afa19a9
AC		 407
408 for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) {
409 rsp = ha->rsp_q_map[cnt];
410 qla2x00_free_rsp_que(ha, rsp);
411 }
412 kfree(ha->rsp_q_map);
413 ha->rsp_q_map = NULL;
73208dfd
AC		 414}
415
68ca949c
AC		 416static int qla25xx_setup_mode(struct scsi_qla_host *vha)
417{
418 uint16_t options = 0;
419 int ques, req, ret;
420 struct qla_hw_data *ha = vha->hw;
421
7163ea81 422 if (!(ha->fw_attributes & BIT_6)) {
7c3df132
SK		 423 ql_log(ql_log_warn, vha, 0x00d8,
424 "Firmware is not multi-queue capable.\n");
7163ea81
AC		 425 goto fail;
426 }
68ca949c 427 if (ql2xmultique_tag) {
68ca949c
AC		 428 /* create a request queue for IO */
429 options |= BIT_7;
430 req = qla25xx_create_req_que(ha, options, 0, 0, -1,
431 QLA_DEFAULT_QUE_QOS);
432 if (!req) {
7c3df132
SK		 433 ql_log(ql_log_warn, vha, 0x00e0,
434 "Failed to create request queue.\n");
68ca949c
AC		 435 goto fail;
436 }
278274d5 437 ha->wq = alloc_workqueue("qla2xxx_wq", WQ_MEM_RECLAIM, 1);
68ca949c
AC		 438 vha->req = ha->req_q_map[req];
439 options |= BIT_1;
440 for (ques = 1; ques < ha->max_rsp_queues; ques++) {
441 ret = qla25xx_create_rsp_que(ha, options, 0, 0, req);
442 if (!ret) {
7c3df132
SK		 443 ql_log(ql_log_warn, vha, 0x00e8,
444 "Failed to create response queue.\n");
68ca949c
AC		 445 goto fail2;
446 }
447 }
7163ea81 448 ha->flags.cpu_affinity_enabled = 1;
7c3df132
SK		 449 ql_dbg(ql_dbg_multiq, vha, 0xc007,
450 "CPU affinity mode enalbed, "
451 "no. of response queues:%d no. of request queues:%d.\n",
452 ha->max_rsp_queues, ha->max_req_queues);
453 ql_dbg(ql_dbg_init, vha, 0x00e9,
454 "CPU affinity mode enalbed, "
455 "no. of response queues:%d no. of request queues:%d.\n",
456 ha->max_rsp_queues, ha->max_req_queues);
68ca949c
AC		 457 }
458 return 0;
459fail2:
460 qla25xx_delete_queues(vha);
7163ea81
AC		 461 destroy_workqueue(ha->wq);
462 ha->wq = NULL;
0cd33fcf 463 vha->req = ha->req_q_map[0];
68ca949c
AC		 464fail:
465 ha->mqenable = 0;
7163ea81
AC		 466 kfree(ha->req_q_map);
467 kfree(ha->rsp_q_map);
468 ha->max_req_queues = ha->max_rsp_queues = 1;
68ca949c
AC		 469 return 1;
470}
471
1da177e4 472static char *
e315cd28 473qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str)
1da177e4 474{
e315cd28 475 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 476 static char *pci_bus_modes[] = {
477 "33", "66", "100", "133",
478 };
479 uint16_t pci_bus;
480
481 strcpy(str, "PCI");
482 pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9;
483 if (pci_bus) {
484 strcat(str, "-X (");
485 strcat(str, pci_bus_modes[pci_bus]);
486 } else {
487 pci_bus = (ha->pci_attr & BIT_8) >> 8;
488 strcat(str, " (");
489 strcat(str, pci_bus_modes[pci_bus]);
490 }
491 strcat(str, " MHz)");
492
493 return (str);
494}
495
fca29703 496static char *
e315cd28 497qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str)
fca29703
AV		 498{
499 static char *pci_bus_modes[] = { "33", "66", "100", "133", };
e315cd28 500 struct qla_hw_data *ha = vha->hw;
fca29703 501 uint32_t pci_bus;
fca29703 502
62a276f8 503 if (pci_is_pcie(ha->pdev)) {
fca29703 504 char lwstr[6];
62a276f8 505 uint32_t lstat, lspeed, lwidth;
fca29703 506
62a276f8
BH		 507 pcie_capability_read_dword(ha->pdev, PCI_EXP_LNKCAP, &lstat);
508 lspeed = lstat & PCI_EXP_LNKCAP_SLS;
509 lwidth = (lstat & PCI_EXP_LNKCAP_MLW) >> 4;
fca29703
AV		 510
511 strcpy(str, "PCIe (");
49300af7
SK		 512 switch (lspeed) {
513 case 1:
c87a0d8c 514 strcat(str, "2.5GT/s ");
49300af7
SK		 515 break;
516 case 2:
c87a0d8c 517 strcat(str, "5.0GT/s ");
49300af7
SK		 518 break;
519 case 3:
520 strcat(str, "8.0GT/s ");
521 break;
522 default:
fca29703 523 strcat(str, "<unknown> ");
49300af7
SK		 524 break;
525 }
fca29703
AV		 526 snprintf(lwstr, sizeof(lwstr), "x%d)", lwidth);
527 strcat(str, lwstr);
528
529 return str;
530 }
531
532 strcpy(str, "PCI");
533 pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8;
534 if (pci_bus == 0 || pci_bus == 8) {
535 strcat(str, " (");
536 strcat(str, pci_bus_modes[pci_bus >> 3]);
537 } else {
538 strcat(str, "-X ");
539 if (pci_bus & BIT_2)
540 strcat(str, "Mode 2");
541 else
542 strcat(str, "Mode 1");
543 strcat(str, " (");
544 strcat(str, pci_bus_modes[pci_bus & ~BIT_2]);
545 }
546 strcat(str, " MHz)");
547
548 return str;
549}
550
e5f82ab8 551static char *
df57caba 552qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
1da177e4
LT		 553{
554 char un_str[10];
e315cd28 555 struct qla_hw_data *ha = vha->hw;
fa2a1ce5 556
df57caba
HM		 557 snprintf(str, size, "%d.%02d.%02d ", ha->fw_major_version,
558 ha->fw_minor_version, ha->fw_subminor_version);
1da177e4
LT		 559
560 if (ha->fw_attributes & BIT_9) {
561 strcat(str, "FLX");
562 return (str);
563 }
564
565 switch (ha->fw_attributes & 0xFF) {
566 case 0x7:
567 strcat(str, "EF");
568 break;
569 case 0x17:
570 strcat(str, "TP");
571 break;
572 case 0x37:
573 strcat(str, "IP");
574 break;
575 case 0x77:
576 strcat(str, "VI");
577 break;
578 default:
579 sprintf(un_str, "(%x)", ha->fw_attributes);
580 strcat(str, un_str);
581 break;
582 }
583 if (ha->fw_attributes & 0x100)
584 strcat(str, "X");
585
586 return (str);
587}
588
e5f82ab8 589static char *
df57caba 590qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
fca29703 591{
e315cd28 592 struct qla_hw_data *ha = vha->hw;
f0883ac6 593
df57caba 594 snprintf(str, size, "%d.%02d.%02d (%x)", ha->fw_major_version,
3a03eb79 595 ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes);
fca29703 596 return str;
fca29703
AV		 597}
598
9ba56b95
GM		 599void
600qla2x00_sp_free_dma(void *vha, void *ptr)
fca29703 601{
9ba56b95
GM		 602 srb_t *sp = (srb_t *)ptr;
603 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
604 struct qla_hw_data *ha = sp->fcport->vha->hw;
605 void *ctx = GET_CMD_CTX_SP(sp);
fca29703 606
9ba56b95
GM		 607 if (sp->flags & SRB_DMA_VALID) {
608 scsi_dma_unmap(cmd);
609 sp->flags &= ~SRB_DMA_VALID;
7c3df132 610 }
fca29703 611
9ba56b95
GM		 612 if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
613 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
614 scsi_prot_sg_count(cmd), cmd->sc_data_direction);
615 sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
616 }
617
618 if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
619 /* List assured to be having elements */
f83adb61 620 qla2x00_clean_dsd_pool(ha, sp, NULL);
9ba56b95
GM		 621 sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
622 }
623
624 if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
625 dma_pool_free(ha->dl_dma_pool, ctx,
626 ((struct crc_context *)ctx)->crc_ctx_dma);
627 sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
628 }
629
630 if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
631 struct ct6_dsd *ctx1 = (struct ct6_dsd *)ctx;
fca29703 632
9ba56b95
GM		 633 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd,
634 ctx1->fcp_cmnd_dma);
635 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list);
636 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt;
637 ha->gbl_dsd_avail += ctx1->dsd_use_cnt;
638 mempool_free(ctx1, ha->ctx_mempool);
639 ctx1 = NULL;
640 }
641
642 CMD_SP(cmd) = NULL;
b00ee7d7 643 qla2x00_rel_sp(sp->fcport->vha, sp);
9ba56b95
GM		 644}
645
14b06808 646static void
9ba56b95
GM		 647qla2x00_sp_compl(void *data, void *ptr, int res)
648{
649 struct qla_hw_data *ha = (struct qla_hw_data *)data;
650 srb_t *sp = (srb_t *)ptr;
651 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
652
653 cmd->result = res;
654
655 if (atomic_read(&sp->ref_count) == 0) {
656 ql_dbg(ql_dbg_io, sp->fcport->vha, 0x3015,
657 "SP reference-count to ZERO -- sp=%p cmd=%p.\n",
658 sp, GET_CMD_SP(sp));
659 if (ql2xextended_error_logging & ql_dbg_io)
660 BUG();
661 return;
662 }
663 if (!atomic_dec_and_test(&sp->ref_count))
664 return;
665
666 qla2x00_sp_free_dma(ha, sp);
667 cmd->scsi_done(cmd);
fca29703
AV		 668}
669
8ae6d9c7
GM		 670/* If we are SP1 here, we need to still take and release the host_lock as SP1
671 * does not have the changes necessary to avoid taking host->host_lock.
672 */
1da177e4 673static int
f5e3e40b 674qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
fca29703 675{
134ae078 676 scsi_qla_host_t *vha = shost_priv(host);
fca29703 677 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
19a7b4ae 678 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
e315cd28
AC		 679 struct qla_hw_data *ha = vha->hw;
680 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
fca29703
AV		 681 srb_t *sp;
682 int rval;
683
85880801 684 if (ha->flags.eeh_busy) {
7c3df132 685 if (ha->flags.pci_channel_io_perm_failure) {
5f28d2d7 686 ql_dbg(ql_dbg_aer, vha, 0x9010,
7c3df132
SK		 687 "PCI Channel IO permanent failure, exiting "
688 "cmd=%p.\n", cmd);
b9b12f73 689 cmd->result = DID_NO_CONNECT << 16;
7c3df132 690 } else {
5f28d2d7 691 ql_dbg(ql_dbg_aer, vha, 0x9011,
7c3df132 692 "EEH_Busy, Requeuing the cmd=%p.\n", cmd);
85880801 693 cmd->result = DID_REQUEUE << 16;
7c3df132 694 }
14e660e6
SJ		 695 goto qc24_fail_command;
696 }
697
19a7b4ae
JSEC		 698 rval = fc_remote_port_chkready(rport);
699 if (rval) {
700 cmd->result = rval;
5f28d2d7 701 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3003,
7c3df132
SK		 702 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
703 cmd, rval);
fca29703
AV		 704 goto qc24_fail_command;
705 }
706
bad75002
AE		 707 if (!vha->flags.difdix_supported &&
708 scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) {
7c3df132
SK		 709 ql_dbg(ql_dbg_io, vha, 0x3004,
710 "DIF Cap not reg, fail DIF capable cmd's:%p.\n",
711 cmd);
bad75002
AE		 712 cmd->result = DID_NO_CONNECT << 16;
713 goto qc24_fail_command;
714 }
aa651be8
CD		 715
716 if (!fcport) {
717 cmd->result = DID_NO_CONNECT << 16;
718 goto qc24_fail_command;
719 }
720
fca29703
AV		 721 if (atomic_read(&fcport->state) != FCS_ONLINE) {
722 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
38170fa8 723 atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
7c3df132
SK		 724 ql_dbg(ql_dbg_io, vha, 0x3005,
725 "Returning DNC, fcport_state=%d loop_state=%d.\n",
726 atomic_read(&fcport->state),
727 atomic_read(&base_vha->loop_state));
fca29703
AV		 728 cmd->result = DID_NO_CONNECT << 16;
729 goto qc24_fail_command;
730 }
7b594131 731 goto qc24_target_busy;
fca29703
AV		 732 }
733
e05fe292
CD		 734 /*
735 * Return target busy if we've received a non-zero retry_delay_timer
736 * in a FCP_RSP.
737 */
738 if (time_after(jiffies, fcport->retry_delay_timestamp))
739 fcport->retry_delay_timestamp = 0;
740 else
741 goto qc24_target_busy;
742
b00ee7d7 743 sp = qla2x00_get_sp(vha, fcport, GFP_ATOMIC);
50280c01 744 if (!sp)
f5e3e40b 745 goto qc24_host_busy;
fca29703 746
9ba56b95
GM		 747 sp->u.scmd.cmd = cmd;
748 sp->type = SRB_SCSI_CMD;
749 atomic_set(&sp->ref_count, 1);
750 CMD_SP(cmd) = (void *)sp;
751 sp->free = qla2x00_sp_free_dma;
752 sp->done = qla2x00_sp_compl;
753
e315cd28 754 rval = ha->isp_ops->start_scsi(sp);
7c3df132 755 if (rval != QLA_SUCCESS) {
53016ed3 756 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3013,
7c3df132 757 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
fca29703 758 goto qc24_host_busy_free_sp;
7c3df132 759 }
fca29703 760
fca29703
AV		 761 return 0;
762
763qc24_host_busy_free_sp:
9ba56b95 764 qla2x00_sp_free_dma(ha, sp);
fca29703 765
f5e3e40b 766qc24_host_busy:
fca29703
AV		 767 return SCSI_MLQUEUE_HOST_BUSY;
768
7b594131
MC		 769qc24_target_busy:
770 return SCSI_MLQUEUE_TARGET_BUSY;
771
fca29703 772qc24_fail_command:
f5e3e40b 773 cmd->scsi_done(cmd);
fca29703
AV		 774
775 return 0;
776}
777
1da177e4
LT		 778/*
779 * qla2x00_eh_wait_on_command
780 * Waits for the command to be returned by the Firmware for some
781 * max time.
782 *
783 * Input:
1da177e4 784 * cmd = Scsi Command to wait on.
1da177e4
LT		 785 *
786 * Return:
787 * Not Found : 0
788 * Found : 1
789 */
790static int
e315cd28 791qla2x00_eh_wait_on_command(struct scsi_cmnd *cmd)
1da177e4 792{
fe74c71f 793#define ABORT_POLLING_PERIOD 1000
478c3b03 794#define ABORT_WAIT_ITER ((2 * 1000) / (ABORT_POLLING_PERIOD))
f4f051eb 795 unsigned long wait_iter = ABORT_WAIT_ITER;
85880801
AV		 796 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
797 struct qla_hw_data *ha = vha->hw;
f4f051eb 798 int ret = QLA_SUCCESS;
1da177e4 799
85880801 800 if (unlikely(pci_channel_offline(ha->pdev)) || ha->flags.eeh_busy) {
7c3df132
SK		 801 ql_dbg(ql_dbg_taskm, vha, 0x8005,
802 "Return:eh_wait.\n");
85880801
AV		 803 return ret;
804 }
805
d970432c 806 while (CMD_SP(cmd) && wait_iter--) {
fe74c71f 807 msleep(ABORT_POLLING_PERIOD);
f4f051eb 808 }
809 if (CMD_SP(cmd))
810 ret = QLA_FUNCTION_FAILED;
1da177e4 811
f4f051eb 812 return ret;
1da177e4
LT		 813}
814
815/*
816 * qla2x00_wait_for_hba_online
fa2a1ce5 817 * Wait till the HBA is online after going through
1da177e4
LT		 818 * <= MAX_RETRIES_OF_ISP_ABORT or
819 * finally HBA is disabled ie marked offline
820 *
821 * Input:
822 * ha - pointer to host adapter structure
fa2a1ce5
AV		 823 *
824 * Note:
1da177e4
LT		 825 * Does context switching-Release SPIN_LOCK
826 * (if any) before calling this routine.
827 *
828 * Return:
829 * Success (Adapter is online) : 0
830 * Failed (Adapter is offline/disabled) : 1
831 */
854165f4 832int
e315cd28 833qla2x00_wait_for_hba_online(scsi_qla_host_t *vha)
1da177e4 834{
fca29703
AV		 835 int return_status;
836 unsigned long wait_online;
e315cd28
AC		 837 struct qla_hw_data *ha = vha->hw;
838 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4 839
fa2a1ce5 840 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ);
e315cd28
AC		 841 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
842 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
843 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
844 ha->dpc_active) && time_before(jiffies, wait_online)) {
1da177e4
LT		 845
846 msleep(1000);
847 }
e315cd28 848 if (base_vha->flags.online)
fa2a1ce5 849 return_status = QLA_SUCCESS;
1da177e4
LT		 850 else
851 return_status = QLA_FUNCTION_FAILED;
852
1da177e4
LT		 853 return (return_status);
854}
855
86fbee86 856/*
638a1a01
SC		 857 * qla2x00_wait_for_hba_ready
858 * Wait till the HBA is ready before doing driver unload
86fbee86
LC		 859 *
860 * Input:
861 * ha - pointer to host adapter structure
862 *
863 * Note:
864 * Does context switching-Release SPIN_LOCK
865 * (if any) before calling this routine.
866 *
86fbee86 867 */
638a1a01
SC		 868static void
869qla2x00_wait_for_hba_ready(scsi_qla_host_t *vha)
86fbee86 870{
86fbee86 871 struct qla_hw_data *ha = vha->hw;
86fbee86 872
9d35894d
SC		 873 while (((qla2x00_reset_active(vha)) || ha->dpc_active ||
874 ha->flags.mbox_busy) ||
875 test_bit(FX00_RESET_RECOVERY, &vha->dpc_flags) ||
876 test_bit(FX00_TARGET_SCAN, &vha->dpc_flags))
86fbee86 877 msleep(1000);
86fbee86
LC		 878}
879
2533cf67
LC		 880int
881qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha)
882{
883 int return_status;
884 unsigned long wait_reset;
885 struct qla_hw_data *ha = vha->hw;
886 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
887
888 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ);
889 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
890 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
891 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
892 ha->dpc_active) && time_before(jiffies, wait_reset)) {
893
894 msleep(1000);
895
896 if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) &&
897 ha->flags.chip_reset_done)
898 break;
899 }
900 if (ha->flags.chip_reset_done)
901 return_status = QLA_SUCCESS;
902 else
903 return_status = QLA_FUNCTION_FAILED;
904
905 return return_status;
906}
907
083a469d
GM		 908static void
909sp_get(struct srb *sp)
910{
911 atomic_inc(&sp->ref_count);
912}
913
1da177e4
LT		 914/**************************************************************************
915* qla2xxx_eh_abort
916*
917* Description:
918* The abort function will abort the specified command.
919*
920* Input:
921* cmd = Linux SCSI command packet to be aborted.
922*
923* Returns:
924* Either SUCCESS or FAILED.
925*
926* Note:
2ea00202 927* Only return FAILED if command not returned by firmware.
1da177e4 928**************************************************************************/
e5f82ab8 929static int
1da177e4
LT		 930qla2xxx_eh_abort(struct scsi_cmnd *cmd)
931{
e315cd28 932 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
f4f051eb 933 srb_t *sp;
4e98d3b8 934 int ret;
9cb78c16
HR		 935 unsigned int id;
936 uint64_t lun;
18e144d3 937 unsigned long flags;
f934c9d0 938 int rval, wait = 0;
e315cd28 939 struct qla_hw_data *ha = vha->hw;
1da177e4 940
f4f051eb 941 if (!CMD_SP(cmd))
2ea00202 942 return SUCCESS;
1da177e4 943
4e98d3b8
AV		 944 ret = fc_block_scsi_eh(cmd);
945 if (ret != 0)
946 return ret;
947 ret = SUCCESS;
948
f4f051eb 949 id = cmd->device->id;
950 lun = cmd->device->lun;
1da177e4 951
e315cd28 952 spin_lock_irqsave(&ha->hardware_lock, flags);
170babc3
MC		 953 sp = (srb_t *) CMD_SP(cmd);
954 if (!sp) {
955 spin_unlock_irqrestore(&ha->hardware_lock, flags);
956 return SUCCESS;
957 }
1da177e4 958
7c3df132 959 ql_dbg(ql_dbg_taskm, vha, 0x8002,
9cb78c16 960 "Aborting from RISC nexus=%ld:%d:%llu sp=%p cmd=%p\n",
cfb0919c 961 vha->host_no, id, lun, sp, cmd);
17d98630 962
170babc3
MC		 963 /* Get a reference to the sp and drop the lock.*/
964 sp_get(sp);
083a469d 965
e315cd28 966 spin_unlock_irqrestore(&ha->hardware_lock, flags);
f934c9d0
CD		 967 rval = ha->isp_ops->abort_command(sp);
968 if (rval) {
969 if (rval == QLA_FUNCTION_PARAMETER_ERROR) {
970 /*
971 * Decrement the ref_count since we can't find the
972 * command
973 */
974 atomic_dec(&sp->ref_count);
975 ret = SUCCESS;
976 } else
977 ret = FAILED;
978
7c3df132 979 ql_dbg(ql_dbg_taskm, vha, 0x8003,
f934c9d0 980 "Abort command mbx failed cmd=%p, rval=%x.\n", cmd, rval);
170babc3 981 } else {
7c3df132 982 ql_dbg(ql_dbg_taskm, vha, 0x8004,
cfb0919c 983 "Abort command mbx success cmd=%p.\n", cmd);
170babc3
MC		 984 wait = 1;
985 }
75942064
SK		 986
987 spin_lock_irqsave(&ha->hardware_lock, flags);
f934c9d0
CD		 988 /*
989 * Clear the slot in the oustanding_cmds array if we can't find the
990 * command to reclaim the resources.
991 */
992 if (rval == QLA_FUNCTION_PARAMETER_ERROR)
993 vha->req->outstanding_cmds[sp->handle] = NULL;
9ba56b95 994 sp->done(ha, sp, 0);
75942064 995 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1da177e4 996
bc91ade9
CD		 997 /* Did the command return during mailbox execution? */
998 if (ret == FAILED && !CMD_SP(cmd))
999 ret = SUCCESS;
1000
f4f051eb 1001 /* Wait for the command to be returned. */
2ea00202 1002 if (wait) {
e315cd28 1003 if (qla2x00_eh_wait_on_command(cmd) != QLA_SUCCESS) {
7c3df132 1004 ql_log(ql_log_warn, vha, 0x8006,
cfb0919c 1005 "Abort handler timed out cmd=%p.\n", cmd);
2ea00202 1006 ret = FAILED;
f4f051eb 1007 }
1da177e4 1008 }
1da177e4 1009
7c3df132 1010 ql_log(ql_log_info, vha, 0x801c,
9cb78c16 1011 "Abort command issued nexus=%ld:%d:%llu -- %d %x.\n",
cfb0919c 1012 vha->host_no, id, lun, wait, ret);
1da177e4 1013
f4f051eb 1014 return ret;
1015}
1da177e4 1016
4d78c973 1017int
e315cd28 1018qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t,
9cb78c16 1019 uint64_t l, enum nexus_wait_type type)
f4f051eb 1020{
17d98630 1021 int cnt, match, status;
18e144d3 1022 unsigned long flags;
e315cd28 1023 struct qla_hw_data *ha = vha->hw;
73208dfd 1024 struct req_que *req;
4d78c973 1025 srb_t *sp;
9ba56b95 1026 struct scsi_cmnd *cmd;
1da177e4 1027
523ec773 1028 status = QLA_SUCCESS;
17d98630 1029
e315cd28 1030 spin_lock_irqsave(&ha->hardware_lock, flags);
67c2e93a 1031 req = vha->req;
17d98630 1032 for (cnt = 1; status == QLA_SUCCESS &&
8d93f550 1033 cnt < req->num_outstanding_cmds; cnt++) {
17d98630
AC		 1034 sp = req->outstanding_cmds[cnt];
1035 if (!sp)
523ec773 1036 continue;
9ba56b95 1037 if (sp->type != SRB_SCSI_CMD)
cf53b069 1038 continue;
17d98630
AC		 1039 if (vha->vp_idx != sp->fcport->vha->vp_idx)
1040 continue;
1041 match = 0;
9ba56b95 1042 cmd = GET_CMD_SP(sp);
17d98630
AC		 1043 switch (type) {
1044 case WAIT_HOST:
1045 match = 1;
1046 break;
1047 case WAIT_TARGET:
9ba56b95 1048 match = cmd->device->id == t;
17d98630
AC		 1049 break;
1050 case WAIT_LUN:
9ba56b95
GM		 1051 match = (cmd->device->id == t &&
1052 cmd->device->lun == l);
17d98630 1053 break;
73208dfd 1054 }
17d98630
AC		 1055 if (!match)
1056 continue;
1057
1058 spin_unlock_irqrestore(&ha->hardware_lock, flags);
9ba56b95 1059 status = qla2x00_eh_wait_on_command(cmd);
17d98630 1060 spin_lock_irqsave(&ha->hardware_lock, flags);
1da177e4 1061 }
e315cd28 1062 spin_unlock_irqrestore(&ha->hardware_lock, flags);
523ec773
AV		 1063
1064 return status;
1da177e4
LT		 1065}
1066
523ec773
AV		 1067static char *reset_errors[] = {
1068 "HBA not online",
1069 "HBA not ready",
1070 "Task management failed",
1071 "Waiting for command completions",
1072};
1da177e4 1073
e5f82ab8 1074static int
523ec773 1075__qla2xxx_eh_generic_reset(char *name, enum nexus_wait_type type,
9cb78c16 1076 struct scsi_cmnd *cmd, int (*do_reset)(struct fc_port *, uint64_t, int))
1da177e4 1077{
e315cd28 1078 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
bdf79621 1079 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
523ec773 1080 int err;
1da177e4 1081
7c3df132 1082 if (!fcport) {
523ec773 1083 return FAILED;
7c3df132 1084 }
1da177e4 1085
4e98d3b8
AV		 1086 err = fc_block_scsi_eh(cmd);
1087 if (err != 0)
1088 return err;
1089
7c3df132 1090 ql_log(ql_log_info, vha, 0x8009,
9cb78c16 1091 "%s RESET ISSUED nexus=%ld:%d:%llu cmd=%p.\n", name, vha->host_no,
7c3df132 1092 cmd->device->id, cmd->device->lun, cmd);
1da177e4 1093
523ec773 1094 err = 0;
7c3df132
SK		 1095 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1096 ql_log(ql_log_warn, vha, 0x800a,
1097 "Wait for hba online failed for cmd=%p.\n", cmd);
523ec773 1098 goto eh_reset_failed;
7c3df132 1099 }
523ec773 1100 err = 2;
2afa19a9 1101 if (do_reset(fcport, cmd->device->lun, cmd->request->cpu + 1)
7c3df132
SK		 1102 != QLA_SUCCESS) {
1103 ql_log(ql_log_warn, vha, 0x800c,
1104 "do_reset failed for cmd=%p.\n", cmd);
523ec773 1105 goto eh_reset_failed;
7c3df132 1106 }
523ec773 1107 err = 3;
e315cd28 1108 if (qla2x00_eh_wait_for_pending_commands(vha, cmd->device->id,
7c3df132
SK		 1109 cmd->device->lun, type) != QLA_SUCCESS) {
1110 ql_log(ql_log_warn, vha, 0x800d,
d6a03581 1111 "wait for pending cmds failed for cmd=%p.\n", cmd);
523ec773 1112 goto eh_reset_failed;
7c3df132 1113 }
523ec773 1114
7c3df132 1115 ql_log(ql_log_info, vha, 0x800e,
9cb78c16 1116 "%s RESET SUCCEEDED nexus:%ld:%d:%llu cmd=%p.\n", name,
cfb0919c 1117 vha->host_no, cmd->device->id, cmd->device->lun, cmd);
523ec773
AV		 1118
1119 return SUCCESS;
1120
4d78c973 1121eh_reset_failed:
7c3df132 1122 ql_log(ql_log_info, vha, 0x800f,
9cb78c16 1123 "%s RESET FAILED: %s nexus=%ld:%d:%llu cmd=%p.\n", name,
cfb0919c
CD		 1124 reset_errors[err], vha->host_no, cmd->device->id, cmd->device->lun,
1125 cmd);
523ec773
AV		 1126 return FAILED;
1127}
1da177e4 1128
523ec773
AV		 1129static int
1130qla2xxx_eh_device_reset(struct scsi_cmnd *cmd)
1131{
e315cd28
AC		 1132 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1133 struct qla_hw_data *ha = vha->hw;
1da177e4 1134
523ec773
AV		 1135 return __qla2xxx_eh_generic_reset("DEVICE", WAIT_LUN, cmd,
1136 ha->isp_ops->lun_reset);
1da177e4
LT		 1137}
1138
1da177e4 1139static int
523ec773 1140qla2xxx_eh_target_reset(struct scsi_cmnd *cmd)
1da177e4 1141{
e315cd28
AC		 1142 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1143 struct qla_hw_data *ha = vha->hw;
1da177e4 1144
523ec773
AV		 1145 return __qla2xxx_eh_generic_reset("TARGET", WAIT_TARGET, cmd,
1146 ha->isp_ops->target_reset);
1da177e4
LT		 1147}
1148
1da177e4
LT		 1149/**************************************************************************
1150* qla2xxx_eh_bus_reset
1151*
1152* Description:
1153* The bus reset function will reset the bus and abort any executing
1154* commands.
1155*
1156* Input:
1157* cmd = Linux SCSI command packet of the command that cause the
1158* bus reset.
1159*
1160* Returns:
1161* SUCCESS/FAILURE (defined as macro in scsi.h).
1162*
1163**************************************************************************/
e5f82ab8 1164static int
1da177e4
LT		 1165qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd)
1166{
e315cd28 1167 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
bdf79621 1168 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
2c3dfe3f 1169 int ret = FAILED;
9cb78c16
HR		 1170 unsigned int id;
1171 uint64_t lun;
f4f051eb 1172
f4f051eb 1173 id = cmd->device->id;
1174 lun = cmd->device->lun;
1da177e4 1175
7c3df132 1176 if (!fcport) {
f4f051eb 1177 return ret;
7c3df132 1178 }
1da177e4 1179
4e98d3b8
AV		 1180 ret = fc_block_scsi_eh(cmd);
1181 if (ret != 0)
1182 return ret;
1183 ret = FAILED;
1184
7c3df132 1185 ql_log(ql_log_info, vha, 0x8012,
9cb78c16 1186 "BUS RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun);
1da177e4 1187
e315cd28 1188 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
7c3df132
SK		 1189 ql_log(ql_log_fatal, vha, 0x8013,
1190 "Wait for hba online failed board disabled.\n");
f4f051eb 1191 goto eh_bus_reset_done;
1da177e4
LT		 1192 }
1193
ad537689
SK		 1194 if (qla2x00_loop_reset(vha) == QLA_SUCCESS)
1195 ret = SUCCESS;
1196
f4f051eb 1197 if (ret == FAILED)
1198 goto eh_bus_reset_done;
1da177e4 1199
9a41a62b 1200 /* Flush outstanding commands. */
4d78c973 1201 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) !=
7c3df132
SK		 1202 QLA_SUCCESS) {
1203 ql_log(ql_log_warn, vha, 0x8014,
1204 "Wait for pending commands failed.\n");
9a41a62b 1205 ret = FAILED;
7c3df132 1206 }
1da177e4 1207
f4f051eb 1208eh_bus_reset_done:
7c3df132 1209 ql_log(ql_log_warn, vha, 0x802b,
9cb78c16 1210 "BUS RESET %s nexus=%ld:%d:%llu.\n",
d6a03581 1211 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1da177e4 1212
f4f051eb 1213 return ret;
1da177e4
LT		 1214}
1215
1216/**************************************************************************
1217* qla2xxx_eh_host_reset
1218*
1219* Description:
1220* The reset function will reset the Adapter.
1221*
1222* Input:
1223* cmd = Linux SCSI command packet of the command that cause the
1224* adapter reset.
1225*
1226* Returns:
1227* Either SUCCESS or FAILED.
1228*
1229* Note:
1230**************************************************************************/
e5f82ab8 1231static int
1da177e4
LT		 1232qla2xxx_eh_host_reset(struct scsi_cmnd *cmd)
1233{
e315cd28 1234 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
e315cd28 1235 struct qla_hw_data *ha = vha->hw;
2c3dfe3f 1236 int ret = FAILED;
9cb78c16
HR		 1237 unsigned int id;
1238 uint64_t lun;
e315cd28 1239 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4 1240
f4f051eb 1241 id = cmd->device->id;
1242 lun = cmd->device->lun;
f4f051eb 1243
7c3df132 1244 ql_log(ql_log_info, vha, 0x8018,
9cb78c16 1245 "ADAPTER RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun);
1da177e4 1246
63ee7072
CD		 1247 /*
1248 * No point in issuing another reset if one is active. Also do not
1249 * attempt a reset if we are updating flash.
1250 */
1251 if (qla2x00_reset_active(vha) || ha->optrom_state != QLA_SWAITING)
f4f051eb 1252 goto eh_host_reset_lock;
1da177e4 1253
e315cd28
AC		 1254 if (vha != base_vha) {
1255 if (qla2x00_vp_abort_isp(vha))
f4f051eb 1256 goto eh_host_reset_lock;
e315cd28 1257 } else {
7ec0effd 1258 if (IS_P3P_TYPE(vha->hw)) {
a9083016
GM		 1259 if (!qla82xx_fcoe_ctx_reset(vha)) {
1260 /* Ctx reset success */
1261 ret = SUCCESS;
1262 goto eh_host_reset_lock;
1263 }
1264 /* fall thru if ctx reset failed */
1265 }
68ca949c
AC		 1266 if (ha->wq)
1267 flush_workqueue(ha->wq);
1268
e315cd28 1269 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
a9083016 1270 if (ha->isp_ops->abort_isp(base_vha)) {
e315cd28
AC		 1271 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1272 /* failed. schedule dpc to try */
1273 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
1274
7c3df132
SK		 1275 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1276 ql_log(ql_log_warn, vha, 0x802a,
1277 "wait for hba online failed.\n");
e315cd28 1278 goto eh_host_reset_lock;
7c3df132 1279 }
e315cd28
AC		 1280 }
1281 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
fa2a1ce5 1282 }
1da177e4 1283
e315cd28 1284 /* Waiting for command to be returned to OS.*/
4d78c973 1285 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) ==
e315cd28 1286 QLA_SUCCESS)
f4f051eb 1287 ret = SUCCESS;
1da177e4 1288
f4f051eb 1289eh_host_reset_lock:
cfb0919c 1290 ql_log(ql_log_info, vha, 0x8017,
9cb78c16 1291 "ADAPTER RESET %s nexus=%ld:%d:%llu.\n",
cfb0919c 1292 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1da177e4 1293
f4f051eb 1294 return ret;
1295}
1da177e4
LT		 1296
1297/*
1298* qla2x00_loop_reset
1299* Issue loop reset.
1300*
1301* Input:
1302* ha = adapter block pointer.
1303*
1304* Returns:
1305* 0 = success
1306*/
a4722cf2 1307int
e315cd28 1308qla2x00_loop_reset(scsi_qla_host_t *vha)
1da177e4 1309{
0c8c39af 1310 int ret;
bdf79621 1311 struct fc_port *fcport;
e315cd28 1312 struct qla_hw_data *ha = vha->hw;
1da177e4 1313
5854771e
AB		 1314 if (IS_QLAFX00(ha)) {
1315 return qlafx00_loop_reset(vha);
1316 }
1317
f4c496c1 1318 if (ql2xtargetreset == 1 && ha->flags.enable_target_reset) {
55e5ed27
AV		 1319 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1320 if (fcport->port_type != FCT_TARGET)
1321 continue;
1322
1323 ret = ha->isp_ops->target_reset(fcport, 0, 0);
1324 if (ret != QLA_SUCCESS) {
7c3df132 1325 ql_dbg(ql_dbg_taskm, vha, 0x802c,
5854771e 1326 "Bus Reset failed: Reset=%d "
7c3df132 1327 "d_id=%x.\n", ret, fcport->d_id.b24);
55e5ed27
AV		 1328 }
1329 }
1330 }
1331
8ae6d9c7 1332
6246b8a1 1333 if (ha->flags.enable_lip_full_login && !IS_CNA_CAPABLE(ha)) {
0b7e7c53
AV		 1334 atomic_set(&vha->loop_state, LOOP_DOWN);
1335 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
1336 qla2x00_mark_all_devices_lost(vha, 0);
e315cd28 1337 ret = qla2x00_full_login_lip(vha);
0c8c39af 1338 if (ret != QLA_SUCCESS) {
7c3df132
SK		 1339 ql_dbg(ql_dbg_taskm, vha, 0x802d,
1340 "full_login_lip=%d.\n", ret);
749af3d5 1341 }
0c8c39af
AV		 1342 }
1343
0d6e61bc 1344 if (ha->flags.enable_lip_reset) {
e315cd28 1345 ret = qla2x00_lip_reset(vha);
ad537689 1346 if (ret != QLA_SUCCESS)
7c3df132
SK		 1347 ql_dbg(ql_dbg_taskm, vha, 0x802e,
1348 "lip_reset failed (%d).\n", ret);
1da177e4
LT		 1349 }
1350
1da177e4 1351 /* Issue marker command only when we are going to start the I/O */
e315cd28 1352 vha->marker_needed = 1;
1da177e4 1353
0c8c39af 1354 return QLA_SUCCESS;
1da177e4
LT		 1355}
1356
df4bf0bb 1357void
e315cd28 1358qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res)
df4bf0bb 1359{
73208dfd 1360 int que, cnt;
df4bf0bb
AV		 1361 unsigned long flags;
1362 srb_t *sp;
e315cd28 1363 struct qla_hw_data *ha = vha->hw;
73208dfd 1364 struct req_que *req;
df4bf0bb
AV		 1365
1366 spin_lock_irqsave(&ha->hardware_lock, flags);
2afa19a9 1367 for (que = 0; que < ha->max_req_queues; que++) {
29bdccbe 1368 req = ha->req_q_map[que];
73208dfd
AC		 1369 if (!req)
1370 continue;
8d93f550
CD		 1371 if (!req->outstanding_cmds)
1372 continue;
1373 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) {
73208dfd 1374 sp = req->outstanding_cmds[cnt];
e612d465 1375 if (sp) {
73208dfd 1376 req->outstanding_cmds[cnt] = NULL;
9ba56b95 1377 sp->done(vha, sp, res);
73208dfd 1378 }
df4bf0bb
AV		 1379 }
1380 }
1381 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1382}
1383
f4f051eb 1384static int
1385qla2xxx_slave_alloc(struct scsi_device *sdev)
1da177e4 1386{
bdf79621 1387 struct fc_rport *rport = starget_to_rport(scsi_target(sdev));
1da177e4 1388
19a7b4ae 1389 if (!rport || fc_remote_port_chkready(rport))
f4f051eb 1390 return -ENXIO;
bdf79621 1391
19a7b4ae 1392 sdev->hostdata = *(fc_port_t **)rport->dd_data;
1da177e4 1393
f4f051eb 1394 return 0;
1395}
1da177e4 1396
f4f051eb 1397static int
1398qla2xxx_slave_configure(struct scsi_device *sdev)
1399{
e315cd28 1400 scsi_qla_host_t *vha = shost_priv(sdev->host);
2afa19a9 1401 struct req_que *req = vha->req;
8482e118 1402
9e522cd8
AE		 1403 if (IS_T10_PI_CAPABLE(vha->hw))
1404 blk_queue_update_dma_alignment(sdev->request_queue, 0x7);
1405
f4f051eb 1406 if (sdev->tagged_supported)
73208dfd 1407 scsi_activate_tcq(sdev, req->max_q_depth);
f4f051eb 1408 else
73208dfd 1409 scsi_deactivate_tcq(sdev, req->max_q_depth);
f4f051eb 1410 return 0;
1411}
1da177e4 1412
f4f051eb 1413static void
1414qla2xxx_slave_destroy(struct scsi_device *sdev)
1415{
1416 sdev->hostdata = NULL;
1da177e4
LT		 1417}
1418
c45dd305
GM		 1419static void qla2x00_handle_queue_full(struct scsi_device *sdev, int qdepth)
1420{
1421 fc_port_t *fcport = (struct fc_port *) sdev->hostdata;
1422
1423 if (!scsi_track_queue_full(sdev, qdepth))
1424 return;
1425
7c3df132 1426 ql_dbg(ql_dbg_io, fcport->vha, 0x3029,
9cb78c16 1427 "Queue depth adjusted-down to %d for nexus=%ld:%d:%llu.\n",
cfb0919c 1428 sdev->queue_depth, fcport->vha->host_no, sdev->id, sdev->lun);
c45dd305
GM		 1429}
1430
1431static void qla2x00_adjust_sdev_qdepth_up(struct scsi_device *sdev, int qdepth)
1432{
1433 fc_port_t *fcport = sdev->hostdata;
1434 struct scsi_qla_host *vha = fcport->vha;
c45dd305
GM		 1435 struct req_que *req = NULL;
1436
1437 req = vha->req;
1438 if (!req)
1439 return;
1440
1441 if (req->max_q_depth <= sdev->queue_depth || req->max_q_depth < qdepth)
1442 return;
1443
1444 if (sdev->ordered_tags)
1445 scsi_adjust_queue_depth(sdev, MSG_ORDERED_TAG, qdepth);
1446 else
1447 scsi_adjust_queue_depth(sdev, MSG_SIMPLE_TAG, qdepth);
1448
7c3df132 1449 ql_dbg(ql_dbg_io, vha, 0x302a,
9cb78c16 1450 "Queue depth adjusted-up to %d for nexus=%ld:%d:%llu.\n",
cfb0919c 1451 sdev->queue_depth, fcport->vha->host_no, sdev->id, sdev->lun);
c45dd305
GM		 1452}
1453
ce7e4af7 1454static int
e881a172 1455qla2x00_change_queue_depth(struct scsi_device *sdev, int qdepth, int reason)
ce7e4af7 1456{
c45dd305
GM		 1457 switch (reason) {
1458 case SCSI_QDEPTH_DEFAULT:
1459 scsi_adjust_queue_depth(sdev, scsi_get_tag_type(sdev), qdepth);
1460 break;
1461 case SCSI_QDEPTH_QFULL:
1462 qla2x00_handle_queue_full(sdev, qdepth);
1463 break;
1464 case SCSI_QDEPTH_RAMP_UP:
1465 qla2x00_adjust_sdev_qdepth_up(sdev, qdepth);
1466 break;
1467 default:
08002af2 1468 return -EOPNOTSUPP;
c45dd305 1469 }
e881a172 1470
ce7e4af7
AV		 1471 return sdev->queue_depth;
1472}
1473
1474static int
1475qla2x00_change_queue_type(struct scsi_device *sdev, int tag_type)
1476{
1477 if (sdev->tagged_supported) {
1478 scsi_set_tag_type(sdev, tag_type);
1479 if (tag_type)
1480 scsi_activate_tcq(sdev, sdev->queue_depth);
1481 else
1482 scsi_deactivate_tcq(sdev, sdev->queue_depth);
1483 } else
1484 tag_type = 0;
1485
1486 return tag_type;
1487}
1488
1da177e4
LT		 1489/**
1490 * qla2x00_config_dma_addressing() - Configure OS DMA addressing method.
1491 * @ha: HA context
1492 *
1493 * At exit, the @ha's flags.enable_64bit_addressing set to indicated
1494 * supported addressing method.
1495 */
1496static void
53303c42 1497qla2x00_config_dma_addressing(struct qla_hw_data *ha)
1da177e4 1498{
7524f9b9 1499 /* Assume a 32bit DMA mask. */
1da177e4 1500 ha->flags.enable_64bit_addressing = 0;
1da177e4 1501
6a35528a 1502 if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) {
7524f9b9
AV		 1503 /* Any upper-dword bits set? */
1504 if (MSD(dma_get_required_mask(&ha->pdev->dev)) &&
6a35528a 1505 !pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(64))) {
7524f9b9 1506 /* Ok, a 64bit DMA mask is applicable. */
1da177e4 1507 ha->flags.enable_64bit_addressing = 1;
fd34f556
AV		 1508 ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64;
1509 ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64;
7524f9b9 1510 return;
1da177e4 1511 }
1da177e4 1512 }
7524f9b9 1513
284901a9
YH		 1514 dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32));
1515 pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(32));
1da177e4
LT		 1516}
1517
fd34f556 1518static void
e315cd28 1519qla2x00_enable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1520{
1521 unsigned long flags = 0;
1522 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1523
1524 spin_lock_irqsave(&ha->hardware_lock, flags);
1525 ha->interrupts_on = 1;
1526 /* enable risc and host interrupts */
1527 WRT_REG_WORD(&reg->ictrl, ICR_EN_INT | ICR_EN_RISC);
1528 RD_REG_WORD(&reg->ictrl);
1529 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1530
1531}
1532
1533static void
e315cd28 1534qla2x00_disable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1535{
1536 unsigned long flags = 0;
1537 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1538
1539 spin_lock_irqsave(&ha->hardware_lock, flags);
1540 ha->interrupts_on = 0;
1541 /* disable risc and host interrupts */
1542 WRT_REG_WORD(&reg->ictrl, 0);
1543 RD_REG_WORD(&reg->ictrl);
1544 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1545}
1546
1547static void
e315cd28 1548qla24xx_enable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1549{
1550 unsigned long flags = 0;
1551 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1552
1553 spin_lock_irqsave(&ha->hardware_lock, flags);
1554 ha->interrupts_on = 1;
1555 WRT_REG_DWORD(&reg->ictrl, ICRX_EN_RISC_INT);
1556 RD_REG_DWORD(&reg->ictrl);
1557 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1558}
1559
1560static void
e315cd28 1561qla24xx_disable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1562{
1563 unsigned long flags = 0;
1564 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1565
124f85e6
AV		 1566 if (IS_NOPOLLING_TYPE(ha))
1567 return;
fd34f556
AV		 1568 spin_lock_irqsave(&ha->hardware_lock, flags);
1569 ha->interrupts_on = 0;
1570 WRT_REG_DWORD(&reg->ictrl, 0);
1571 RD_REG_DWORD(&reg->ictrl);
1572 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1573}
1574
706f457d
GM		 1575static int
1576qla2x00_iospace_config(struct qla_hw_data *ha)
1577{
1578 resource_size_t pio;
1579 uint16_t msix;
1580 int cpus;
1581
706f457d
GM		 1582 if (pci_request_selected_regions(ha->pdev, ha->bars,
1583 QLA2XXX_DRIVER_NAME)) {
1584 ql_log_pci(ql_log_fatal, ha->pdev, 0x0011,
1585 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
1586 pci_name(ha->pdev));
1587 goto iospace_error_exit;
1588 }
1589 if (!(ha->bars & 1))
1590 goto skip_pio;
1591
1592 /* We only need PIO for Flash operations on ISP2312 v2 chips. */
1593 pio = pci_resource_start(ha->pdev, 0);
1594 if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) {
1595 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
1596 ql_log_pci(ql_log_warn, ha->pdev, 0x0012,
1597 "Invalid pci I/O region size (%s).\n",
1598 pci_name(ha->pdev));
1599 pio = 0;
1600 }
1601 } else {
1602 ql_log_pci(ql_log_warn, ha->pdev, 0x0013,
1603 "Region #0 no a PIO resource (%s).\n",
1604 pci_name(ha->pdev));
1605 pio = 0;
1606 }
1607 ha->pio_address = pio;
1608 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014,
1609 "PIO address=%llu.\n",
1610 (unsigned long long)ha->pio_address);
1611
1612skip_pio:
1613 /* Use MMIO operations for all accesses. */
1614 if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) {
1615 ql_log_pci(ql_log_fatal, ha->pdev, 0x0015,
1616 "Region #1 not an MMIO resource (%s), aborting.\n",
1617 pci_name(ha->pdev));
1618 goto iospace_error_exit;
1619 }
1620 if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) {
1621 ql_log_pci(ql_log_fatal, ha->pdev, 0x0016,
1622 "Invalid PCI mem region size (%s), aborting.\n",
1623 pci_name(ha->pdev));
1624 goto iospace_error_exit;
1625 }
1626
1627 ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN);
1628 if (!ha->iobase) {
1629 ql_log_pci(ql_log_fatal, ha->pdev, 0x0017,
1630 "Cannot remap MMIO (%s), aborting.\n",
1631 pci_name(ha->pdev));
1632 goto iospace_error_exit;
1633 }
1634
1635 /* Determine queue resources */
1636 ha->max_req_queues = ha->max_rsp_queues = 1;
1637 if ((ql2xmaxqueues <= 1 && !ql2xmultique_tag) ||
1638 (ql2xmaxqueues > 1 && ql2xmultique_tag) ||
1639 (!IS_QLA25XX(ha) && !IS_QLA81XX(ha)))
1640 goto mqiobase_exit;
1641
1642 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3),
1643 pci_resource_len(ha->pdev, 3));
1644 if (ha->mqiobase) {
1645 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018,
1646 "MQIO Base=%p.\n", ha->mqiobase);
1647 /* Read MSIX vector size of the board */
1648 pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix);
1649 ha->msix_count = msix;
1650 /* Max queues are bounded by available msix vectors */
1651 /* queue 0 uses two msix vectors */
1652 if (ql2xmultique_tag) {
1653 cpus = num_online_cpus();
1654 ha->max_rsp_queues = (ha->msix_count - 1 > cpus) ?
1655 (cpus + 1) : (ha->msix_count - 1);
1656 ha->max_req_queues = 2;
1657 } else if (ql2xmaxqueues > 1) {
1658 ha->max_req_queues = ql2xmaxqueues > QLA_MQ_SIZE ?
1659 QLA_MQ_SIZE : ql2xmaxqueues;
1660 ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc008,
1661 "QoS mode set, max no of request queues:%d.\n",
1662 ha->max_req_queues);
1663 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0019,
1664 "QoS mode set, max no of request queues:%d.\n",
1665 ha->max_req_queues);
1666 }
1667 ql_log_pci(ql_log_info, ha->pdev, 0x001a,
1668 "MSI-X vector count: %d.\n", msix);
1669 } else
1670 ql_log_pci(ql_log_info, ha->pdev, 0x001b,
1671 "BAR 3 not enabled.\n");
1672
1673mqiobase_exit:
1674 ha->msix_count = ha->max_rsp_queues + 1;
1675 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c,
1676 "MSIX Count:%d.\n", ha->msix_count);
1677 return (0);
1678
1679iospace_error_exit:
1680 return (-ENOMEM);
1681}
1682
1683
6246b8a1
GM		 1684static int
1685qla83xx_iospace_config(struct qla_hw_data *ha)
1686{
1687 uint16_t msix;
1688 int cpus;
1689
1690 if (pci_request_selected_regions(ha->pdev, ha->bars,
1691 QLA2XXX_DRIVER_NAME)) {
1692 ql_log_pci(ql_log_fatal, ha->pdev, 0x0117,
1693 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
1694 pci_name(ha->pdev));
1695
1696 goto iospace_error_exit;
1697 }
1698
1699 /* Use MMIO operations for all accesses. */
1700 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) {
1701 ql_log_pci(ql_log_warn, ha->pdev, 0x0118,
1702 "Invalid pci I/O region size (%s).\n",
1703 pci_name(ha->pdev));
1704 goto iospace_error_exit;
1705 }
1706 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
1707 ql_log_pci(ql_log_warn, ha->pdev, 0x0119,
1708 "Invalid PCI mem region size (%s), aborting\n",
1709 pci_name(ha->pdev));
1710 goto iospace_error_exit;
1711 }
1712
1713 ha->iobase = ioremap(pci_resource_start(ha->pdev, 0), MIN_IOBASE_LEN);
1714 if (!ha->iobase) {
1715 ql_log_pci(ql_log_fatal, ha->pdev, 0x011a,
1716 "Cannot remap MMIO (%s), aborting.\n",
1717 pci_name(ha->pdev));
1718 goto iospace_error_exit;
1719 }
1720
1721 /* 64bit PCI BAR - BAR2 will correspoond to region 4 */
1722 /* 83XX 26XX always use MQ type access for queues
1723 * - mbar 2, a.k.a region 4 */
1724 ha->max_req_queues = ha->max_rsp_queues = 1;
1725 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 4),
1726 pci_resource_len(ha->pdev, 4));
1727
1728 if (!ha->mqiobase) {
1729 ql_log_pci(ql_log_fatal, ha->pdev, 0x011d,
1730 "BAR2/region4 not enabled\n");
1731 goto mqiobase_exit;
1732 }
1733
1734 ha->msixbase = ioremap(pci_resource_start(ha->pdev, 2),
1735 pci_resource_len(ha->pdev, 2));
1736 if (ha->msixbase) {
1737 /* Read MSIX vector size of the board */
1738 pci_read_config_word(ha->pdev,
1739 QLA_83XX_PCI_MSIX_CONTROL, &msix);
1740 ha->msix_count = msix;
1741 /* Max queues are bounded by available msix vectors */
1742 /* queue 0 uses two msix vectors */
1743 if (ql2xmultique_tag) {
1744 cpus = num_online_cpus();
1745 ha->max_rsp_queues = (ha->msix_count - 1 > cpus) ?
1746 (cpus + 1) : (ha->msix_count - 1);
1747 ha->max_req_queues = 2;
1748 } else if (ql2xmaxqueues > 1) {
1749 ha->max_req_queues = ql2xmaxqueues > QLA_MQ_SIZE ?
1750 QLA_MQ_SIZE : ql2xmaxqueues;
1751 ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc00c,
1752 "QoS mode set, max no of request queues:%d.\n",
1753 ha->max_req_queues);
1754 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b,
1755 "QoS mode set, max no of request queues:%d.\n",
1756 ha->max_req_queues);
1757 }
1758 ql_log_pci(ql_log_info, ha->pdev, 0x011c,
1759 "MSI-X vector count: %d.\n", msix);
1760 } else
1761 ql_log_pci(ql_log_info, ha->pdev, 0x011e,
1762 "BAR 1 not enabled.\n");
1763
1764mqiobase_exit:
1765 ha->msix_count = ha->max_rsp_queues + 1;
aa230bc5
AE		 1766
1767 qlt_83xx_iospace_config(ha);
1768
6246b8a1
GM		 1769 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011f,
1770 "MSIX Count:%d.\n", ha->msix_count);
1771 return 0;
1772
1773iospace_error_exit:
1774 return -ENOMEM;
1775}
1776
fd34f556
AV		 1777static struct isp_operations qla2100_isp_ops = {
1778 .pci_config = qla2100_pci_config,
1779 .reset_chip = qla2x00_reset_chip,
1780 .chip_diag = qla2x00_chip_diag,
1781 .config_rings = qla2x00_config_rings,
1782 .reset_adapter = qla2x00_reset_adapter,
1783 .nvram_config = qla2x00_nvram_config,
1784 .update_fw_options = qla2x00_update_fw_options,
1785 .load_risc = qla2x00_load_risc,
1786 .pci_info_str = qla2x00_pci_info_str,
1787 .fw_version_str = qla2x00_fw_version_str,
1788 .intr_handler = qla2100_intr_handler,
1789 .enable_intrs = qla2x00_enable_intrs,
1790 .disable_intrs = qla2x00_disable_intrs,
1791 .abort_command = qla2x00_abort_command,
523ec773
AV		 1792 .target_reset = qla2x00_abort_target,
1793 .lun_reset = qla2x00_lun_reset,
fd34f556
AV		 1794 .fabric_login = qla2x00_login_fabric,
1795 .fabric_logout = qla2x00_fabric_logout,
1796 .calc_req_entries = qla2x00_calc_iocbs_32,
1797 .build_iocbs = qla2x00_build_scsi_iocbs_32,
1798 .prep_ms_iocb = qla2x00_prep_ms_iocb,
1799 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
1800 .read_nvram = qla2x00_read_nvram_data,
1801 .write_nvram = qla2x00_write_nvram_data,
1802 .fw_dump = qla2100_fw_dump,
1803 .beacon_on = NULL,
1804 .beacon_off = NULL,
1805 .beacon_blink = NULL,
1806 .read_optrom = qla2x00_read_optrom_data,
1807 .write_optrom = qla2x00_write_optrom_data,
1808 .get_flash_version = qla2x00_get_flash_version,
e315cd28 1809 .start_scsi = qla2x00_start_scsi,
a9083016 1810 .abort_isp = qla2x00_abort_isp,
706f457d 1811 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 1812 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 1813};
1814
1815static struct isp_operations qla2300_isp_ops = {
1816 .pci_config = qla2300_pci_config,
1817 .reset_chip = qla2x00_reset_chip,
1818 .chip_diag = qla2x00_chip_diag,
1819 .config_rings = qla2x00_config_rings,
1820 .reset_adapter = qla2x00_reset_adapter,
1821 .nvram_config = qla2x00_nvram_config,
1822 .update_fw_options = qla2x00_update_fw_options,
1823 .load_risc = qla2x00_load_risc,
1824 .pci_info_str = qla2x00_pci_info_str,
1825 .fw_version_str = qla2x00_fw_version_str,
1826 .intr_handler = qla2300_intr_handler,
1827 .enable_intrs = qla2x00_enable_intrs,
1828 .disable_intrs = qla2x00_disable_intrs,
1829 .abort_command = qla2x00_abort_command,
523ec773
AV		 1830 .target_reset = qla2x00_abort_target,
1831 .lun_reset = qla2x00_lun_reset,
fd34f556
AV		 1832 .fabric_login = qla2x00_login_fabric,
1833 .fabric_logout = qla2x00_fabric_logout,
1834 .calc_req_entries = qla2x00_calc_iocbs_32,
1835 .build_iocbs = qla2x00_build_scsi_iocbs_32,
1836 .prep_ms_iocb = qla2x00_prep_ms_iocb,
1837 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
1838 .read_nvram = qla2x00_read_nvram_data,
1839 .write_nvram = qla2x00_write_nvram_data,
1840 .fw_dump = qla2300_fw_dump,
1841 .beacon_on = qla2x00_beacon_on,
1842 .beacon_off = qla2x00_beacon_off,
1843 .beacon_blink = qla2x00_beacon_blink,
1844 .read_optrom = qla2x00_read_optrom_data,
1845 .write_optrom = qla2x00_write_optrom_data,
1846 .get_flash_version = qla2x00_get_flash_version,
e315cd28 1847 .start_scsi = qla2x00_start_scsi,
a9083016 1848 .abort_isp = qla2x00_abort_isp,
7ec0effd 1849 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 1850 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 1851};
1852
1853static struct isp_operations qla24xx_isp_ops = {
1854 .pci_config = qla24xx_pci_config,
1855 .reset_chip = qla24xx_reset_chip,
1856 .chip_diag = qla24xx_chip_diag,
1857 .config_rings = qla24xx_config_rings,
1858 .reset_adapter = qla24xx_reset_adapter,
1859 .nvram_config = qla24xx_nvram_config,
1860 .update_fw_options = qla24xx_update_fw_options,
1861 .load_risc = qla24xx_load_risc,
1862 .pci_info_str = qla24xx_pci_info_str,
1863 .fw_version_str = qla24xx_fw_version_str,
1864 .intr_handler = qla24xx_intr_handler,
1865 .enable_intrs = qla24xx_enable_intrs,
1866 .disable_intrs = qla24xx_disable_intrs,
1867 .abort_command = qla24xx_abort_command,
523ec773
AV		 1868 .target_reset = qla24xx_abort_target,
1869 .lun_reset = qla24xx_lun_reset,
fd34f556
AV		 1870 .fabric_login = qla24xx_login_fabric,
1871 .fabric_logout = qla24xx_fabric_logout,
1872 .calc_req_entries = NULL,
1873 .build_iocbs = NULL,
1874 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1875 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1876 .read_nvram = qla24xx_read_nvram_data,
1877 .write_nvram = qla24xx_write_nvram_data,
1878 .fw_dump = qla24xx_fw_dump,
1879 .beacon_on = qla24xx_beacon_on,
1880 .beacon_off = qla24xx_beacon_off,
1881 .beacon_blink = qla24xx_beacon_blink,
1882 .read_optrom = qla24xx_read_optrom_data,
1883 .write_optrom = qla24xx_write_optrom_data,
1884 .get_flash_version = qla24xx_get_flash_version,
e315cd28 1885 .start_scsi = qla24xx_start_scsi,
a9083016 1886 .abort_isp = qla2x00_abort_isp,
7ec0effd 1887 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 1888 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 1889};
1890
c3a2f0df
AV		 1891static struct isp_operations qla25xx_isp_ops = {
1892 .pci_config = qla25xx_pci_config,
1893 .reset_chip = qla24xx_reset_chip,
1894 .chip_diag = qla24xx_chip_diag,
1895 .config_rings = qla24xx_config_rings,
1896 .reset_adapter = qla24xx_reset_adapter,
1897 .nvram_config = qla24xx_nvram_config,
1898 .update_fw_options = qla24xx_update_fw_options,
1899 .load_risc = qla24xx_load_risc,
1900 .pci_info_str = qla24xx_pci_info_str,
1901 .fw_version_str = qla24xx_fw_version_str,
1902 .intr_handler = qla24xx_intr_handler,
1903 .enable_intrs = qla24xx_enable_intrs,
1904 .disable_intrs = qla24xx_disable_intrs,
1905 .abort_command = qla24xx_abort_command,
523ec773
AV		 1906 .target_reset = qla24xx_abort_target,
1907 .lun_reset = qla24xx_lun_reset,
c3a2f0df
AV		 1908 .fabric_login = qla24xx_login_fabric,
1909 .fabric_logout = qla24xx_fabric_logout,
1910 .calc_req_entries = NULL,
1911 .build_iocbs = NULL,
1912 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1913 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1914 .read_nvram = qla25xx_read_nvram_data,
1915 .write_nvram = qla25xx_write_nvram_data,
1916 .fw_dump = qla25xx_fw_dump,
1917 .beacon_on = qla24xx_beacon_on,
1918 .beacon_off = qla24xx_beacon_off,
1919 .beacon_blink = qla24xx_beacon_blink,
338c9161 1920 .read_optrom = qla25xx_read_optrom_data,
c3a2f0df
AV		 1921 .write_optrom = qla24xx_write_optrom_data,
1922 .get_flash_version = qla24xx_get_flash_version,
bad75002 1923 .start_scsi = qla24xx_dif_start_scsi,
a9083016 1924 .abort_isp = qla2x00_abort_isp,
7ec0effd 1925 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 1926 .initialize_adapter = qla2x00_initialize_adapter,
c3a2f0df
AV		 1927};
1928
3a03eb79
AV		 1929static struct isp_operations qla81xx_isp_ops = {
1930 .pci_config = qla25xx_pci_config,
1931 .reset_chip = qla24xx_reset_chip,
1932 .chip_diag = qla24xx_chip_diag,
1933 .config_rings = qla24xx_config_rings,
1934 .reset_adapter = qla24xx_reset_adapter,
1935 .nvram_config = qla81xx_nvram_config,
1936 .update_fw_options = qla81xx_update_fw_options,
eaac30be 1937 .load_risc = qla81xx_load_risc,
3a03eb79
AV		 1938 .pci_info_str = qla24xx_pci_info_str,
1939 .fw_version_str = qla24xx_fw_version_str,
1940 .intr_handler = qla24xx_intr_handler,
1941 .enable_intrs = qla24xx_enable_intrs,
1942 .disable_intrs = qla24xx_disable_intrs,
1943 .abort_command = qla24xx_abort_command,
1944 .target_reset = qla24xx_abort_target,
1945 .lun_reset = qla24xx_lun_reset,
1946 .fabric_login = qla24xx_login_fabric,
1947 .fabric_logout = qla24xx_fabric_logout,
1948 .calc_req_entries = NULL,
1949 .build_iocbs = NULL,
1950 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1951 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
3d79038f
AV		 1952 .read_nvram = NULL,
1953 .write_nvram = NULL,
3a03eb79
AV		 1954 .fw_dump = qla81xx_fw_dump,
1955 .beacon_on = qla24xx_beacon_on,
1956 .beacon_off = qla24xx_beacon_off,
6246b8a1 1957 .beacon_blink = qla83xx_beacon_blink,
3a03eb79
AV		 1958 .read_optrom = qla25xx_read_optrom_data,
1959 .write_optrom = qla24xx_write_optrom_data,
1960 .get_flash_version = qla24xx_get_flash_version,
ba77ef53 1961 .start_scsi = qla24xx_dif_start_scsi,
a9083016 1962 .abort_isp = qla2x00_abort_isp,
7ec0effd 1963 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 1964 .initialize_adapter = qla2x00_initialize_adapter,
a9083016
GM		 1965};
1966
1967static struct isp_operations qla82xx_isp_ops = {
1968 .pci_config = qla82xx_pci_config,
1969 .reset_chip = qla82xx_reset_chip,
1970 .chip_diag = qla24xx_chip_diag,
1971 .config_rings = qla82xx_config_rings,
1972 .reset_adapter = qla24xx_reset_adapter,
1973 .nvram_config = qla81xx_nvram_config,
1974 .update_fw_options = qla24xx_update_fw_options,
1975 .load_risc = qla82xx_load_risc,
9d55ca66 1976 .pci_info_str = qla24xx_pci_info_str,
a9083016
GM		 1977 .fw_version_str = qla24xx_fw_version_str,
1978 .intr_handler = qla82xx_intr_handler,
1979 .enable_intrs = qla82xx_enable_intrs,
1980 .disable_intrs = qla82xx_disable_intrs,
1981 .abort_command = qla24xx_abort_command,
1982 .target_reset = qla24xx_abort_target,
1983 .lun_reset = qla24xx_lun_reset,
1984 .fabric_login = qla24xx_login_fabric,
1985 .fabric_logout = qla24xx_fabric_logout,
1986 .calc_req_entries = NULL,
1987 .build_iocbs = NULL,
1988 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1989 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1990 .read_nvram = qla24xx_read_nvram_data,
1991 .write_nvram = qla24xx_write_nvram_data,
a1b23c5a 1992 .fw_dump = qla82xx_fw_dump,
999916dc
SK		 1993 .beacon_on = qla82xx_beacon_on,
1994 .beacon_off = qla82xx_beacon_off,
1995 .beacon_blink = NULL,
a9083016
GM		 1996 .read_optrom = qla82xx_read_optrom_data,
1997 .write_optrom = qla82xx_write_optrom_data,
7ec0effd 1998 .get_flash_version = qla82xx_get_flash_version,
a9083016
GM		 1999 .start_scsi = qla82xx_start_scsi,
2000 .abort_isp = qla82xx_abort_isp,
706f457d 2001 .iospace_config = qla82xx_iospace_config,
8ae6d9c7 2002 .initialize_adapter = qla2x00_initialize_adapter,
3a03eb79
AV		 2003};
2004
7ec0effd
AD		 2005static struct isp_operations qla8044_isp_ops = {
2006 .pci_config = qla82xx_pci_config,
2007 .reset_chip = qla82xx_reset_chip,
2008 .chip_diag = qla24xx_chip_diag,
2009 .config_rings = qla82xx_config_rings,
2010 .reset_adapter = qla24xx_reset_adapter,
2011 .nvram_config = qla81xx_nvram_config,
2012 .update_fw_options = qla24xx_update_fw_options,
2013 .load_risc = qla82xx_load_risc,
2014 .pci_info_str = qla24xx_pci_info_str,
2015 .fw_version_str = qla24xx_fw_version_str,
2016 .intr_handler = qla8044_intr_handler,
2017 .enable_intrs = qla82xx_enable_intrs,
2018 .disable_intrs = qla82xx_disable_intrs,
2019 .abort_command = qla24xx_abort_command,
2020 .target_reset = qla24xx_abort_target,
2021 .lun_reset = qla24xx_lun_reset,
2022 .fabric_login = qla24xx_login_fabric,
2023 .fabric_logout = qla24xx_fabric_logout,
2024 .calc_req_entries = NULL,
2025 .build_iocbs = NULL,
2026 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2027 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2028 .read_nvram = NULL,
2029 .write_nvram = NULL,
a1b23c5a 2030 .fw_dump = qla8044_fw_dump,
7ec0effd
AD		 2031 .beacon_on = qla82xx_beacon_on,
2032 .beacon_off = qla82xx_beacon_off,
2033 .beacon_blink = NULL,
888e639d 2034 .read_optrom = qla8044_read_optrom_data,
7ec0effd
AD		 2035 .write_optrom = qla8044_write_optrom_data,
2036 .get_flash_version = qla82xx_get_flash_version,
2037 .start_scsi = qla82xx_start_scsi,
2038 .abort_isp = qla8044_abort_isp,
2039 .iospace_config = qla82xx_iospace_config,
2040 .initialize_adapter = qla2x00_initialize_adapter,
2041};
2042
6246b8a1
GM		 2043static struct isp_operations qla83xx_isp_ops = {
2044 .pci_config = qla25xx_pci_config,
2045 .reset_chip = qla24xx_reset_chip,
2046 .chip_diag = qla24xx_chip_diag,
2047 .config_rings = qla24xx_config_rings,
2048 .reset_adapter = qla24xx_reset_adapter,
2049 .nvram_config = qla81xx_nvram_config,
2050 .update_fw_options = qla81xx_update_fw_options,
2051 .load_risc = qla81xx_load_risc,
2052 .pci_info_str = qla24xx_pci_info_str,
2053 .fw_version_str = qla24xx_fw_version_str,
2054 .intr_handler = qla24xx_intr_handler,
2055 .enable_intrs = qla24xx_enable_intrs,
2056 .disable_intrs = qla24xx_disable_intrs,
2057 .abort_command = qla24xx_abort_command,
2058 .target_reset = qla24xx_abort_target,
2059 .lun_reset = qla24xx_lun_reset,
2060 .fabric_login = qla24xx_login_fabric,
2061 .fabric_logout = qla24xx_fabric_logout,
2062 .calc_req_entries = NULL,
2063 .build_iocbs = NULL,
2064 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2065 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2066 .read_nvram = NULL,
2067 .write_nvram = NULL,
2068 .fw_dump = qla83xx_fw_dump,
2069 .beacon_on = qla24xx_beacon_on,
2070 .beacon_off = qla24xx_beacon_off,
2071 .beacon_blink = qla83xx_beacon_blink,
2072 .read_optrom = qla25xx_read_optrom_data,
2073 .write_optrom = qla24xx_write_optrom_data,
2074 .get_flash_version = qla24xx_get_flash_version,
2075 .start_scsi = qla24xx_dif_start_scsi,
2076 .abort_isp = qla2x00_abort_isp,
2077 .iospace_config = qla83xx_iospace_config,
8ae6d9c7
GM		 2078 .initialize_adapter = qla2x00_initialize_adapter,
2079};
2080
2081static struct isp_operations qlafx00_isp_ops = {
2082 .pci_config = qlafx00_pci_config,
2083 .reset_chip = qlafx00_soft_reset,
2084 .chip_diag = qlafx00_chip_diag,
2085 .config_rings = qlafx00_config_rings,
2086 .reset_adapter = qlafx00_soft_reset,
2087 .nvram_config = NULL,
2088 .update_fw_options = NULL,
2089 .load_risc = NULL,
2090 .pci_info_str = qlafx00_pci_info_str,
2091 .fw_version_str = qlafx00_fw_version_str,
2092 .intr_handler = qlafx00_intr_handler,
2093 .enable_intrs = qlafx00_enable_intrs,
2094 .disable_intrs = qlafx00_disable_intrs,
4440e46d 2095 .abort_command = qla24xx_async_abort_command,
8ae6d9c7
GM		 2096 .target_reset = qlafx00_abort_target,
2097 .lun_reset = qlafx00_lun_reset,
2098 .fabric_login = NULL,
2099 .fabric_logout = NULL,
2100 .calc_req_entries = NULL,
2101 .build_iocbs = NULL,
2102 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2103 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2104 .read_nvram = qla24xx_read_nvram_data,
2105 .write_nvram = qla24xx_write_nvram_data,
2106 .fw_dump = NULL,
2107 .beacon_on = qla24xx_beacon_on,
2108 .beacon_off = qla24xx_beacon_off,
2109 .beacon_blink = NULL,
2110 .read_optrom = qla24xx_read_optrom_data,
2111 .write_optrom = qla24xx_write_optrom_data,
2112 .get_flash_version = qla24xx_get_flash_version,
2113 .start_scsi = qlafx00_start_scsi,
2114 .abort_isp = qlafx00_abort_isp,
2115 .iospace_config = qlafx00_iospace_config,
2116 .initialize_adapter = qlafx00_initialize_adapter,
6246b8a1
GM		 2117};
2118
f73cb695
CD		 2119static struct isp_operations qla27xx_isp_ops = {
2120 .pci_config = qla25xx_pci_config,
2121 .reset_chip = qla24xx_reset_chip,
2122 .chip_diag = qla24xx_chip_diag,
2123 .config_rings = qla24xx_config_rings,
2124 .reset_adapter = qla24xx_reset_adapter,
2125 .nvram_config = qla81xx_nvram_config,
2126 .update_fw_options = qla81xx_update_fw_options,
2127 .load_risc = qla81xx_load_risc,
2128 .pci_info_str = qla24xx_pci_info_str,
2129 .fw_version_str = qla24xx_fw_version_str,
2130 .intr_handler = qla24xx_intr_handler,
2131 .enable_intrs = qla24xx_enable_intrs,
2132 .disable_intrs = qla24xx_disable_intrs,
2133 .abort_command = qla24xx_abort_command,
2134 .target_reset = qla24xx_abort_target,
2135 .lun_reset = qla24xx_lun_reset,
2136 .fabric_login = qla24xx_login_fabric,
2137 .fabric_logout = qla24xx_fabric_logout,
2138 .calc_req_entries = NULL,
2139 .build_iocbs = NULL,
2140 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2141 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2142 .read_nvram = NULL,
2143 .write_nvram = NULL,
2144 .fw_dump = qla27xx_fwdump,
2145 .beacon_on = qla24xx_beacon_on,
2146 .beacon_off = qla24xx_beacon_off,
2147 .beacon_blink = qla83xx_beacon_blink,
2148 .read_optrom = qla25xx_read_optrom_data,
2149 .write_optrom = qla24xx_write_optrom_data,
2150 .get_flash_version = qla24xx_get_flash_version,
2151 .start_scsi = qla24xx_dif_start_scsi,
2152 .abort_isp = qla2x00_abort_isp,
2153 .iospace_config = qla83xx_iospace_config,
2154 .initialize_adapter = qla2x00_initialize_adapter,
2155};
2156
ea5b6382 2157static inline void
e315cd28 2158qla2x00_set_isp_flags(struct qla_hw_data *ha)
ea5b6382 2159{
2160 ha->device_type = DT_EXTENDED_IDS;
2161 switch (ha->pdev->device) {
2162 case PCI_DEVICE_ID_QLOGIC_ISP2100:
2163 ha->device_type |= DT_ISP2100;
2164 ha->device_type &= ~DT_EXTENDED_IDS;
441d1072 2165 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
ea5b6382 2166 break;
2167 case PCI_DEVICE_ID_QLOGIC_ISP2200:
2168 ha->device_type |= DT_ISP2200;
2169 ha->device_type &= ~DT_EXTENDED_IDS;
441d1072 2170 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
ea5b6382 2171 break;
2172 case PCI_DEVICE_ID_QLOGIC_ISP2300:
2173 ha->device_type |= DT_ISP2300;
4a59f71d 2174 ha->device_type |= DT_ZIO_SUPPORTED;
441d1072 2175 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 2176 break;
2177 case PCI_DEVICE_ID_QLOGIC_ISP2312:
2178 ha->device_type |= DT_ISP2312;
4a59f71d 2179 ha->device_type |= DT_ZIO_SUPPORTED;
441d1072 2180 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 2181 break;
2182 case PCI_DEVICE_ID_QLOGIC_ISP2322:
2183 ha->device_type |= DT_ISP2322;
4a59f71d 2184 ha->device_type |= DT_ZIO_SUPPORTED;
ea5b6382 2185 if (ha->pdev->subsystem_vendor == 0x1028 &&
2186 ha->pdev->subsystem_device == 0x0170)
2187 ha->device_type |= DT_OEM_001;
441d1072 2188 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 2189 break;
2190 case PCI_DEVICE_ID_QLOGIC_ISP6312:
2191 ha->device_type |= DT_ISP6312;
441d1072 2192 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 2193 break;
2194 case PCI_DEVICE_ID_QLOGIC_ISP6322:
2195 ha->device_type |= DT_ISP6322;
441d1072 2196 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 2197 break;
2198 case PCI_DEVICE_ID_QLOGIC_ISP2422:
2199 ha->device_type |= DT_ISP2422;
4a59f71d 2200 ha->device_type |= DT_ZIO_SUPPORTED;
e428924c 2201 ha->device_type |= DT_FWI2;
c76f2c01 2202 ha->device_type |= DT_IIDMA;
441d1072 2203 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2204 break;
2205 case PCI_DEVICE_ID_QLOGIC_ISP2432:
2206 ha->device_type |= DT_ISP2432;
4a59f71d 2207 ha->device_type |= DT_ZIO_SUPPORTED;
e428924c 2208 ha->device_type |= DT_FWI2;
c76f2c01 2209 ha->device_type |= DT_IIDMA;
441d1072 2210 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2211 break;
4d4df193
HK		 2212 case PCI_DEVICE_ID_QLOGIC_ISP8432:
2213 ha->device_type |= DT_ISP8432;
2214 ha->device_type |= DT_ZIO_SUPPORTED;
2215 ha->device_type |= DT_FWI2;
2216 ha->device_type |= DT_IIDMA;
2217 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2218 break;
044cc6c8 2219 case PCI_DEVICE_ID_QLOGIC_ISP5422:
2220 ha->device_type |= DT_ISP5422;
e428924c 2221 ha->device_type |= DT_FWI2;
441d1072 2222 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2223 break;
044cc6c8 2224 case PCI_DEVICE_ID_QLOGIC_ISP5432:
2225 ha->device_type |= DT_ISP5432;
e428924c 2226 ha->device_type |= DT_FWI2;
441d1072 2227 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2228 break;
c3a2f0df
AV		 2229 case PCI_DEVICE_ID_QLOGIC_ISP2532:
2230 ha->device_type |= DT_ISP2532;
2231 ha->device_type |= DT_ZIO_SUPPORTED;
2232 ha->device_type |= DT_FWI2;
2233 ha->device_type |= DT_IIDMA;
441d1072 2234 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2235 break;
3a03eb79
AV		 2236 case PCI_DEVICE_ID_QLOGIC_ISP8001:
2237 ha->device_type |= DT_ISP8001;
2238 ha->device_type |= DT_ZIO_SUPPORTED;
2239 ha->device_type |= DT_FWI2;
2240 ha->device_type |= DT_IIDMA;
2241 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2242 break;
a9083016
GM		 2243 case PCI_DEVICE_ID_QLOGIC_ISP8021:
2244 ha->device_type |= DT_ISP8021;
2245 ha->device_type |= DT_ZIO_SUPPORTED;
2246 ha->device_type |= DT_FWI2;
2247 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2248 /* Initialize 82XX ISP flags */
2249 qla82xx_init_flags(ha);
2250 break;
7ec0effd
AD		 2251 case PCI_DEVICE_ID_QLOGIC_ISP8044:
2252 ha->device_type |= DT_ISP8044;
2253 ha->device_type |= DT_ZIO_SUPPORTED;
2254 ha->device_type |= DT_FWI2;
2255 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2256 /* Initialize 82XX ISP flags */
2257 qla82xx_init_flags(ha);
2258 break;
6246b8a1
GM		 2259 case PCI_DEVICE_ID_QLOGIC_ISP2031:
2260 ha->device_type |= DT_ISP2031;
2261 ha->device_type |= DT_ZIO_SUPPORTED;
2262 ha->device_type |= DT_FWI2;
2263 ha->device_type |= DT_IIDMA;
2264 ha->device_type |= DT_T10_PI;
2265 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2266 break;
2267 case PCI_DEVICE_ID_QLOGIC_ISP8031:
2268 ha->device_type |= DT_ISP8031;
2269 ha->device_type |= DT_ZIO_SUPPORTED;
2270 ha->device_type |= DT_FWI2;
2271 ha->device_type |= DT_IIDMA;
2272 ha->device_type |= DT_T10_PI;
2273 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2274 break;
8ae6d9c7
GM		 2275 case PCI_DEVICE_ID_QLOGIC_ISPF001:
2276 ha->device_type |= DT_ISPFX00;
2277 break;
f73cb695
CD		 2278 case PCI_DEVICE_ID_QLOGIC_ISP2071:
2279 ha->device_type |= DT_ISP2071;
2280 ha->device_type |= DT_ZIO_SUPPORTED;
2281 ha->device_type |= DT_FWI2;
2282 ha->device_type |= DT_IIDMA;
2283 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2284 break;
2c5bbbb2
JC		 2285 case PCI_DEVICE_ID_QLOGIC_ISP2271:
2286 ha->device_type |= DT_ISP2271;
2287 ha->device_type |= DT_ZIO_SUPPORTED;
2288 ha->device_type |= DT_FWI2;
2289 ha->device_type |= DT_IIDMA;
2290 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2291 break;
ea5b6382 2292 }
e5b68a61 2293
a9083016 2294 if (IS_QLA82XX(ha))
43a9c38b 2295 ha->port_no = ha->portnum & 1;
f73cb695 2296 else {
a9083016
GM		 2297 /* Get adapter physical port no from interrupt pin register. */
2298 pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no);
f73cb695
CD		 2299 if (IS_QLA27XX(ha))
2300 ha->port_no--;
2301 else
2302 ha->port_no = !(ha->port_no & 1);
2303 }
a9083016 2304
7c3df132 2305 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b,
d8424f68 2306 "device_type=0x%x port=%d fw_srisc_address=0x%x.\n",
f73cb695 2307 ha->device_type, ha->port_no, ha->fw_srisc_address);
ea5b6382 2308}
2309
1e99e33a
AV		 2310static void
2311qla2xxx_scan_start(struct Scsi_Host *shost)
2312{
e315cd28 2313 scsi_qla_host_t *vha = shost_priv(shost);
1e99e33a 2314
cbc8eb67
AV		 2315 if (vha->hw->flags.running_gold_fw)
2316 return;
2317
e315cd28
AC		 2318 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
2319 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
2320 set_bit(RSCN_UPDATE, &vha->dpc_flags);
2321 set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags);
1e99e33a
AV		 2322}
2323
2324static int
2325qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time)
2326{
e315cd28 2327 scsi_qla_host_t *vha = shost_priv(shost);
1e99e33a 2328
e315cd28 2329 if (!vha->host)
1e99e33a 2330 return 1;
e315cd28 2331 if (time > vha->hw->loop_reset_delay * HZ)
1e99e33a
AV		 2332 return 1;
2333
e315cd28 2334 return atomic_read(&vha->loop_state) == LOOP_READY;
1e99e33a
AV		 2335}
2336
1da177e4
LT		 2337/*
2338 * PCI driver interface
2339 */
6f039790 2340static int
7ee61397 2341qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
1da177e4 2342{
a1541d5a 2343 int ret = -ENODEV;
1da177e4 2344 struct Scsi_Host *host;
e315cd28
AC		 2345 scsi_qla_host_t *base_vha = NULL;
2346 struct qla_hw_data *ha;
29856e28 2347 char pci_info[30];
7d613ac6 2348 char fw_str[30], wq_name[30];
5433383e 2349 struct scsi_host_template *sht;
642ef983 2350 int bars, mem_only = 0;
e315cd28 2351 uint16_t req_length = 0, rsp_length = 0;
73208dfd
AC		 2352 struct req_que *req = NULL;
2353 struct rsp_que *rsp = NULL;
285d0321 2354 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO);
a5326f86 2355 sht = &qla2xxx_driver_template;
5433383e 2356 if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 ||
8bc69e7d 2357 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 ||
4d4df193 2358 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 ||
8bc69e7d 2359 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 ||
c3a2f0df 2360 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 ||
3a03eb79 2361 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 ||
a9083016 2362 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 ||
6246b8a1
GM		 2363 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021 ||
2364 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2031 ||
8ae6d9c7 2365 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8031 ||
7ec0effd 2366 pdev->device == PCI_DEVICE_ID_QLOGIC_ISPF001 ||
f73cb695 2367 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8044 ||
2c5bbbb2
JC		 2368 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2071 ||
2369 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2271) {
285d0321 2370 bars = pci_select_bars(pdev, IORESOURCE_MEM);
09483916 2371 mem_only = 1;
7c3df132
SK		 2372 ql_dbg_pci(ql_dbg_init, pdev, 0x0007,
2373 "Mem only adapter.\n");
285d0321 2374 }
7c3df132
SK		 2375 ql_dbg_pci(ql_dbg_init, pdev, 0x0008,
2376 "Bars=%d.\n", bars);
285d0321 2377
09483916
BH		 2378 if (mem_only) {
2379 if (pci_enable_device_mem(pdev))
2380 goto probe_out;
2381 } else {
2382 if (pci_enable_device(pdev))
2383 goto probe_out;
2384 }
285d0321 2385
0927678f
JB		 2386 /* This may fail but that's ok */
2387 pci_enable_pcie_error_reporting(pdev);
285d0321 2388
e315cd28
AC		 2389 ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL);
2390 if (!ha) {
7c3df132
SK		 2391 ql_log_pci(ql_log_fatal, pdev, 0x0009,
2392 "Unable to allocate memory for ha.\n");
e315cd28 2393 goto probe_out;
1da177e4 2394 }
7c3df132
SK		 2395 ql_dbg_pci(ql_dbg_init, pdev, 0x000a,
2396 "Memory allocated for ha=%p.\n", ha);
e315cd28 2397 ha->pdev = pdev;
2d70c103 2398 ha->tgt.enable_class_2 = ql2xenableclass2;
1da177e4
LT		 2399
2400 /* Clear our data area */
285d0321 2401 ha->bars = bars;
09483916 2402 ha->mem_only = mem_only;
df4bf0bb 2403 spin_lock_init(&ha->hardware_lock);
339aa70e 2404 spin_lock_init(&ha->vport_slock);
a9b6f722 2405 mutex_init(&ha->selflogin_lock);
7a8ab9c8 2406 mutex_init(&ha->optrom_mutex);
1da177e4 2407
ea5b6382 2408 /* Set ISP-type information. */
2409 qla2x00_set_isp_flags(ha);
ca79cf66
DG		 2410
2411 /* Set EEH reset type to fundamental if required by hba */
95676112 2412 if (IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha) ||
f73cb695 2413 IS_QLA83XX(ha) || IS_QLA27XX(ha))
ca79cf66 2414 pdev->needs_freset = 1;
ca79cf66 2415
cba1e47f
CD		 2416 ha->prev_topology = 0;
2417 ha->init_cb_size = sizeof(init_cb_t);
2418 ha->link_data_rate = PORT_SPEED_UNKNOWN;
2419 ha->optrom_size = OPTROM_SIZE_2300;
2420
abbd8870 2421 /* Assign ISP specific operations. */
1da177e4 2422 if (IS_QLA2100(ha)) {
642ef983 2423 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
1da177e4 2424 ha->mbx_count = MAILBOX_REGISTER_COUNT_2100;
e315cd28
AC		 2425 req_length = REQUEST_ENTRY_CNT_2100;
2426 rsp_length = RESPONSE_ENTRY_CNT_2100;
2427 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
abbd8870 2428 ha->gid_list_info_size = 4;
3a03eb79
AV		 2429 ha->flash_conf_off = ~0;
2430 ha->flash_data_off = ~0;
2431 ha->nvram_conf_off = ~0;
2432 ha->nvram_data_off = ~0;
fd34f556 2433 ha->isp_ops = &qla2100_isp_ops;
1da177e4 2434 } else if (IS_QLA2200(ha)) {
642ef983 2435 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
67ddda35 2436 ha->mbx_count = MAILBOX_REGISTER_COUNT_2200;
e315cd28
AC		 2437 req_length = REQUEST_ENTRY_CNT_2200;
2438 rsp_length = RESPONSE_ENTRY_CNT_2100;
2439 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
abbd8870 2440 ha->gid_list_info_size = 4;
3a03eb79
AV		 2441 ha->flash_conf_off = ~0;
2442 ha->flash_data_off = ~0;
2443 ha->nvram_conf_off = ~0;
2444 ha->nvram_data_off = ~0;
fd34f556 2445 ha->isp_ops = &qla2100_isp_ops;
fca29703 2446 } else if (IS_QLA23XX(ha)) {
642ef983 2447 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
1da177e4 2448 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2449 req_length = REQUEST_ENTRY_CNT_2200;
2450 rsp_length = RESPONSE_ENTRY_CNT_2300;
2451 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
abbd8870 2452 ha->gid_list_info_size = 6;
854165f4 2453 if (IS_QLA2322(ha) || IS_QLA6322(ha))
2454 ha->optrom_size = OPTROM_SIZE_2322;
3a03eb79
AV		 2455 ha->flash_conf_off = ~0;
2456 ha->flash_data_off = ~0;
2457 ha->nvram_conf_off = ~0;
2458 ha->nvram_data_off = ~0;
fd34f556 2459 ha->isp_ops = &qla2300_isp_ops;
4d4df193 2460 } else if (IS_QLA24XX_TYPE(ha)) {
642ef983 2461 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
fca29703 2462 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2463 req_length = REQUEST_ENTRY_CNT_24XX;
2464 rsp_length = RESPONSE_ENTRY_CNT_2300;
2d70c103 2465 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
e315cd28 2466 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2c3dfe3f 2467 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
fca29703 2468 ha->gid_list_info_size = 8;
854165f4 2469 ha->optrom_size = OPTROM_SIZE_24XX;
73208dfd 2470 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX;
fd34f556 2471 ha->isp_ops = &qla24xx_isp_ops;
3a03eb79
AV		 2472 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2473 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2474 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2475 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
c3a2f0df 2476 } else if (IS_QLA25XX(ha)) {
642ef983 2477 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
c3a2f0df 2478 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2479 req_length = REQUEST_ENTRY_CNT_24XX;
2480 rsp_length = RESPONSE_ENTRY_CNT_2300;
2d70c103 2481 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
e315cd28 2482 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
c3a2f0df 2483 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
c3a2f0df
AV		 2484 ha->gid_list_info_size = 8;
2485 ha->optrom_size = OPTROM_SIZE_25XX;
73208dfd 2486 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
c3a2f0df 2487 ha->isp_ops = &qla25xx_isp_ops;
3a03eb79
AV		 2488 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2489 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2490 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2491 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
2492 } else if (IS_QLA81XX(ha)) {
642ef983 2493 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3a03eb79
AV		 2494 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2495 req_length = REQUEST_ENTRY_CNT_24XX;
2496 rsp_length = RESPONSE_ENTRY_CNT_2300;
aa230bc5 2497 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
3a03eb79
AV		 2498 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2499 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2500 ha->gid_list_info_size = 8;
2501 ha->optrom_size = OPTROM_SIZE_81XX;
40859ae5 2502 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3a03eb79
AV		 2503 ha->isp_ops = &qla81xx_isp_ops;
2504 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2505 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2506 ha->nvram_conf_off = ~0;
2507 ha->nvram_data_off = ~0;
a9083016 2508 } else if (IS_QLA82XX(ha)) {
642ef983 2509 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
a9083016
GM		 2510 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2511 req_length = REQUEST_ENTRY_CNT_82XX;
2512 rsp_length = RESPONSE_ENTRY_CNT_82XX;
2513 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2514 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2515 ha->gid_list_info_size = 8;
2516 ha->optrom_size = OPTROM_SIZE_82XX;
087c621e 2517 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
a9083016
GM		 2518 ha->isp_ops = &qla82xx_isp_ops;
2519 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2520 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2521 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2522 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
7ec0effd
AD		 2523 } else if (IS_QLA8044(ha)) {
2524 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2525 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2526 req_length = REQUEST_ENTRY_CNT_82XX;
2527 rsp_length = RESPONSE_ENTRY_CNT_82XX;
2528 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2529 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2530 ha->gid_list_info_size = 8;
2531 ha->optrom_size = OPTROM_SIZE_83XX;
2532 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2533 ha->isp_ops = &qla8044_isp_ops;
2534 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2535 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2536 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2537 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
6246b8a1 2538 } else if (IS_QLA83XX(ha)) {
7d613ac6 2539 ha->portnum = PCI_FUNC(ha->pdev->devfn);
642ef983 2540 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
6246b8a1
GM		 2541 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2542 req_length = REQUEST_ENTRY_CNT_24XX;
2543 rsp_length = RESPONSE_ENTRY_CNT_2300;
b8aa4bdf 2544 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
6246b8a1
GM		 2545 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2546 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2547 ha->gid_list_info_size = 8;
2548 ha->optrom_size = OPTROM_SIZE_83XX;
2549 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2550 ha->isp_ops = &qla83xx_isp_ops;
2551 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2552 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2553 ha->nvram_conf_off = ~0;
2554 ha->nvram_data_off = ~0;
8ae6d9c7
GM		 2555 } else if (IS_QLAFX00(ha)) {
2556 ha->max_fibre_devices = MAX_FIBRE_DEVICES_FX00;
2557 ha->mbx_count = MAILBOX_REGISTER_COUNT_FX00;
2558 ha->aen_mbx_count = AEN_MAILBOX_REGISTER_COUNT_FX00;
2559 req_length = REQUEST_ENTRY_CNT_FX00;
2560 rsp_length = RESPONSE_ENTRY_CNT_FX00;
8ae6d9c7
GM		 2561 ha->isp_ops = &qlafx00_isp_ops;
2562 ha->port_down_retry_count = 30; /* default value */
2563 ha->mr.fw_hbt_cnt = QLAFX00_HEARTBEAT_INTERVAL;
2564 ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL;
71e56003 2565 ha->mr.fw_critemp_timer_tick = QLAFX00_CRITEMP_INTERVAL;
8ae6d9c7 2566 ha->mr.fw_hbt_en = 1;
e8f5e95d
AB		 2567 ha->mr.host_info_resend = false;
2568 ha->mr.hinfo_resend_timer_tick = QLAFX00_HINFO_RESEND_INTERVAL;
f73cb695
CD		 2569 } else if (IS_QLA27XX(ha)) {
2570 ha->portnum = PCI_FUNC(ha->pdev->devfn);
2571 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2572 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2573 req_length = REQUEST_ENTRY_CNT_24XX;
2574 rsp_length = RESPONSE_ENTRY_CNT_2300;
2575 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2576 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2577 ha->gid_list_info_size = 8;
2578 ha->optrom_size = OPTROM_SIZE_83XX;
2579 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2580 ha->isp_ops = &qla27xx_isp_ops;
2581 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2582 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2583 ha->nvram_conf_off = ~0;
2584 ha->nvram_data_off = ~0;
1da177e4 2585 }
6246b8a1 2586
7c3df132
SK		 2587 ql_dbg_pci(ql_dbg_init, pdev, 0x001e,
2588 "mbx_count=%d, req_length=%d, "
2589 "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, "
642ef983
CD		 2590 "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, "
2591 "max_fibre_devices=%d.\n",
7c3df132
SK		 2592 ha->mbx_count, req_length, rsp_length, ha->max_loop_id,
2593 ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size,
642ef983 2594 ha->nvram_npiv_size, ha->max_fibre_devices);
7c3df132
SK		 2595 ql_dbg_pci(ql_dbg_init, pdev, 0x001f,
2596 "isp_ops=%p, flash_conf_off=%d, "
2597 "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n",
2598 ha->isp_ops, ha->flash_conf_off, ha->flash_data_off,
2599 ha->nvram_conf_off, ha->nvram_data_off);
706f457d
GM		 2600
2601 /* Configure PCI I/O space */
2602 ret = ha->isp_ops->iospace_config(ha);
2603 if (ret)
0a63ad12 2604 goto iospace_config_failed;
706f457d
GM		 2605
2606 ql_log_pci(ql_log_info, pdev, 0x001d,
2607 "Found an ISP%04X irq %d iobase 0x%p.\n",
2608 pdev->device, pdev->irq, ha->iobase);
6c2f527c 2609 mutex_init(&ha->vport_lock);
0b05a1f0
MB		 2610 init_completion(&ha->mbx_cmd_comp);
2611 complete(&ha->mbx_cmd_comp);
2612 init_completion(&ha->mbx_intr_comp);
23f2ebd1 2613 init_completion(&ha->dcbx_comp);
f356bef1 2614 init_completion(&ha->lb_portup_comp);
1da177e4 2615
2c3dfe3f 2616 set_bit(0, (unsigned long *) ha->vp_idx_map);
1da177e4 2617
53303c42 2618 qla2x00_config_dma_addressing(ha);
7c3df132
SK		 2619 ql_dbg_pci(ql_dbg_init, pdev, 0x0020,
2620 "64 Bit addressing is %s.\n",
2621 ha->flags.enable_64bit_addressing ? "enable" :
2622 "disable");
73208dfd 2623 ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp);
b2a72ec3 2624 if (ret) {
7c3df132
SK		 2625 ql_log_pci(ql_log_fatal, pdev, 0x0031,
2626 "Failed to allocate memory for adapter, aborting.\n");
1da177e4 2627
e315cd28
AC		 2628 goto probe_hw_failed;
2629 }
2630
73208dfd 2631 req->max_q_depth = MAX_Q_DEPTH;
e315cd28 2632 if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU)
73208dfd
AC		 2633 req->max_q_depth = ql2xmaxqdepth;
2634
e315cd28
AC		 2635
2636 base_vha = qla2x00_create_host(sht, ha);
2637 if (!base_vha) {
a1541d5a 2638 ret = -ENOMEM;
6e9f21f3 2639 qla2x00_mem_free(ha);
2afa19a9
AC		 2640 qla2x00_free_req_que(ha, req);
2641 qla2x00_free_rsp_que(ha, rsp);
e315cd28 2642 goto probe_hw_failed;
1da177e4
LT		 2643 }
2644
e315cd28 2645 pci_set_drvdata(pdev, base_vha);
6b383979 2646 set_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags);
e315cd28 2647
e315cd28 2648 host = base_vha->host;
2afa19a9 2649 base_vha->req = req;
73208dfd 2650 if (IS_QLA2XXX_MIDTYPE(ha))
e315cd28 2651 base_vha->mgmt_svr_loop_id = 10 + base_vha->vp_idx;
73208dfd 2652 else
e315cd28
AC		 2653 base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER +
2654 base_vha->vp_idx;
58548cb5 2655
8ae6d9c7
GM		 2656 /* Setup fcport template structure. */
2657 ha->mr.fcport.vha = base_vha;
2658 ha->mr.fcport.port_type = FCT_UNKNOWN;
2659 ha->mr.fcport.loop_id = FC_NO_LOOP_ID;
2660 qla2x00_set_fcport_state(&ha->mr.fcport, FCS_UNCONFIGURED);
2661 ha->mr.fcport.supported_classes = FC_COS_UNSPECIFIED;
2662 ha->mr.fcport.scan_state = 1;
2663
58548cb5
GM		 2664 /* Set the SG table size based on ISP type */
2665 if (!IS_FWI2_CAPABLE(ha)) {
2666 if (IS_QLA2100(ha))
2667 host->sg_tablesize = 32;
2668 } else {
2669 if (!IS_QLA82XX(ha))
2670 host->sg_tablesize = QLA_SG_ALL;
2671 }
642ef983 2672 host->max_id = ha->max_fibre_devices;
e315cd28
AC		 2673 host->cmd_per_lun = 3;
2674 host->unique_id = host->host_no;
e02587d7 2675 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif)
0c470874
AE		 2676 host->max_cmd_len = 32;
2677 else
2678 host->max_cmd_len = MAX_CMDSZ;
e315cd28 2679 host->max_channel = MAX_BUSES - 1;
755f516b
HR		 2680 /* Older HBAs support only 16-bit LUNs */
2681 if (!IS_QLAFX00(ha) && !IS_FWI2_CAPABLE(ha) &&
2682 ql2xmaxlun > 0xffff)
2683 host->max_lun = 0xffff;
2684 else
2685 host->max_lun = ql2xmaxlun;
e315cd28 2686 host->transportt = qla2xxx_transport_template;
9a069e19 2687 sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC);
e315cd28 2688
7c3df132
SK		 2689 ql_dbg(ql_dbg_init, base_vha, 0x0033,
2690 "max_id=%d this_id=%d "
2691 "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d "
1abf635d 2692 "max_lun=%llu transportt=%p, vendor_id=%llu.\n", host->max_id,
7c3df132
SK		 2693 host->this_id, host->cmd_per_lun, host->unique_id,
2694 host->max_cmd_len, host->max_channel, host->max_lun,
2695 host->transportt, sht->vendor_id);
2696
9a347ff4
CD		 2697que_init:
2698 /* Alloc arrays of request and response ring ptrs */
2699 if (!qla2x00_alloc_queues(ha, req, rsp)) {
2700 ql_log(ql_log_fatal, base_vha, 0x003d,
2701 "Failed to allocate memory for queue pointers..."
2702 "aborting.\n");
2703 goto probe_init_failed;
2704 }
2705
2d70c103 2706 qlt_probe_one_stage1(base_vha, ha);
9a347ff4 2707
73208dfd
AC		 2708 /* Set up the irqs */
2709 ret = qla2x00_request_irqs(ha, rsp);
2710 if (ret)
6e9f21f3 2711 goto probe_init_failed;
90a86fc0
JC		 2712
2713 pci_save_state(pdev);
2714
9a347ff4 2715 /* Assign back pointers */
2afa19a9
AC		 2716 rsp->req = req;
2717 req->rsp = rsp;
9a347ff4 2718
8ae6d9c7
GM		 2719 if (IS_QLAFX00(ha)) {
2720 ha->rsp_q_map[0] = rsp;
2721 ha->req_q_map[0] = req;
2722 set_bit(0, ha->req_qid_map);
2723 set_bit(0, ha->rsp_qid_map);
2724 }
2725
08029990
AV		 2726 /* FWI2-capable only. */
2727 req->req_q_in = &ha->iobase->isp24.req_q_in;
2728 req->req_q_out = &ha->iobase->isp24.req_q_out;
2729 rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in;
2730 rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out;
f73cb695 2731 if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
08029990
AV		 2732 req->req_q_in = &ha->mqiobase->isp25mq.req_q_in;
2733 req->req_q_out = &ha->mqiobase->isp25mq.req_q_out;
2734 rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in;
2735 rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out;
17d98630
AC		 2736 }
2737
8ae6d9c7
GM		 2738 if (IS_QLAFX00(ha)) {
2739 req->req_q_in = &ha->iobase->ispfx00.req_q_in;
2740 req->req_q_out = &ha->iobase->ispfx00.req_q_out;
2741 rsp->rsp_q_in = &ha->iobase->ispfx00.rsp_q_in;
2742 rsp->rsp_q_out = &ha->iobase->ispfx00.rsp_q_out;
2743 }
2744
7ec0effd 2745 if (IS_P3P_TYPE(ha)) {
a9083016
GM		 2746 req->req_q_out = &ha->iobase->isp82.req_q_out[0];
2747 rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0];
2748 rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0];
2749 }
2750
7c3df132
SK		 2751 ql_dbg(ql_dbg_multiq, base_vha, 0xc009,
2752 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
2753 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
2754 ql_dbg(ql_dbg_multiq, base_vha, 0xc00a,
2755 "req->req_q_in=%p req->req_q_out=%p "
2756 "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
2757 req->req_q_in, req->req_q_out,
2758 rsp->rsp_q_in, rsp->rsp_q_out);
2759 ql_dbg(ql_dbg_init, base_vha, 0x003e,
2760 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
2761 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
2762 ql_dbg(ql_dbg_init, base_vha, 0x003f,
2763 "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
2764 req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out);
1da177e4 2765
8ae6d9c7 2766 if (ha->isp_ops->initialize_adapter(base_vha)) {
7c3df132
SK		 2767 ql_log(ql_log_fatal, base_vha, 0x00d6,
2768 "Failed to initialize adapter - Adapter flags %x.\n",
2769 base_vha->device_flags);
1da177e4 2770
a9083016
GM		 2771 if (IS_QLA82XX(ha)) {
2772 qla82xx_idc_lock(ha);
2773 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 2774 QLA8XXX_DEV_FAILED);
a9083016 2775 qla82xx_idc_unlock(ha);
7c3df132
SK		 2776 ql_log(ql_log_fatal, base_vha, 0x00d7,
2777 "HW State: FAILED.\n");
7ec0effd
AD		 2778 } else if (IS_QLA8044(ha)) {
2779 qla8044_idc_lock(ha);
2780 qla8044_wr_direct(base_vha,
2781 QLA8044_CRB_DEV_STATE_INDEX,
2782 QLA8XXX_DEV_FAILED);
2783 qla8044_idc_unlock(ha);
2784 ql_log(ql_log_fatal, base_vha, 0x0150,
2785 "HW State: FAILED.\n");
a9083016
GM		 2786 }
2787
a1541d5a 2788 ret = -ENODEV;
1da177e4
LT		 2789 goto probe_failed;
2790 }
2791
3b1bef64
CD		 2792 if (IS_QLAFX00(ha))
2793 host->can_queue = QLAFX00_MAX_CANQUEUE;
2794 else
2795 host->can_queue = req->num_outstanding_cmds - 10;
2796
2797 ql_dbg(ql_dbg_init, base_vha, 0x0032,
2798 "can_queue=%d, req=%p, mgmt_svr_loop_id=%d, sg_tablesize=%d.\n",
2799 host->can_queue, base_vha->req,
2800 base_vha->mgmt_svr_loop_id, host->sg_tablesize);
2801
7163ea81
AC		 2802 if (ha->mqenable) {
2803 if (qla25xx_setup_mode(base_vha)) {
7c3df132
SK		 2804 ql_log(ql_log_warn, base_vha, 0x00ec,
2805 "Failed to create queues, falling back to single queue mode.\n");
7163ea81
AC		 2806 goto que_init;
2807 }
2808 }
68ca949c 2809
cbc8eb67
AV		 2810 if (ha->flags.running_gold_fw)
2811 goto skip_dpc;
2812
1da177e4
LT		 2813 /*
2814 * Startup the kernel thread for this host adapter
2815 */
39a11240 2816 ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha,
7c3df132 2817 "%s_dpc", base_vha->host_str);
39a11240 2818 if (IS_ERR(ha->dpc_thread)) {
7c3df132
SK		 2819 ql_log(ql_log_fatal, base_vha, 0x00ed,
2820 "Failed to start DPC thread.\n");
39a11240 2821 ret = PTR_ERR(ha->dpc_thread);
1da177e4
LT		 2822 goto probe_failed;
2823 }
7c3df132
SK		 2824 ql_dbg(ql_dbg_init, base_vha, 0x00ee,
2825 "DPC thread started successfully.\n");
1da177e4 2826
2d70c103
NB		 2827 /*
2828 * If we're not coming up in initiator mode, we might sit for
2829 * a while without waking up the dpc thread, which leads to a
2830 * stuck process warning. So just kick the dpc once here and
2831 * let the kthread start (and go back to sleep in qla2x00_do_dpc).
2832 */
2833 qla2xxx_wake_dpc(base_vha);
2834
f3ddac19
CD		 2835 INIT_WORK(&ha->board_disable, qla2x00_disable_board_on_pci_error);
2836
81178772
SK		 2837 if (IS_QLA8031(ha) || IS_MCTP_CAPABLE(ha)) {
2838 sprintf(wq_name, "qla2xxx_%lu_dpc_lp_wq", base_vha->host_no);
2839 ha->dpc_lp_wq = create_singlethread_workqueue(wq_name);
2840 INIT_WORK(&ha->idc_aen, qla83xx_service_idc_aen);
2841
2842 sprintf(wq_name, "qla2xxx_%lu_dpc_hp_wq", base_vha->host_no);
2843 ha->dpc_hp_wq = create_singlethread_workqueue(wq_name);
2844 INIT_WORK(&ha->nic_core_reset, qla83xx_nic_core_reset_work);
2845 INIT_WORK(&ha->idc_state_handler,
2846 qla83xx_idc_state_handler_work);
2847 INIT_WORK(&ha->nic_core_unrecoverable,
2848 qla83xx_nic_core_unrecoverable_work);
2849 }
2850
cbc8eb67 2851skip_dpc:
e315cd28
AC		 2852 list_add_tail(&base_vha->list, &ha->vp_list);
2853 base_vha->host->irq = ha->pdev->irq;
1da177e4
LT		 2854
2855 /* Initialized the timer */
e315cd28 2856 qla2x00_start_timer(base_vha, qla2x00_timer, WATCH_INTERVAL);
7c3df132
SK		 2857 ql_dbg(ql_dbg_init, base_vha, 0x00ef,
2858 "Started qla2x00_timer with "
2859 "interval=%d.\n", WATCH_INTERVAL);
2860 ql_dbg(ql_dbg_init, base_vha, 0x00f0,
2861 "Detected hba at address=%p.\n",
2862 ha);
d19044c3 2863
e02587d7 2864 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) {
bad75002 2865 if (ha->fw_attributes & BIT_4) {
9e522cd8 2866 int prot = 0, guard;
bad75002 2867 base_vha->flags.difdix_supported = 1;
7c3df132
SK		 2868 ql_dbg(ql_dbg_init, base_vha, 0x00f1,
2869 "Registering for DIF/DIX type 1 and 3 protection.\n");
8cb2049c
AE		 2870 if (ql2xenabledif == 1)
2871 prot = SHOST_DIX_TYPE0_PROTECTION;
bad75002 2872 scsi_host_set_prot(host,
8cb2049c 2873 prot | SHOST_DIF_TYPE1_PROTECTION
0c470874 2874 | SHOST_DIF_TYPE2_PROTECTION
bad75002
AE		 2875 | SHOST_DIF_TYPE3_PROTECTION
2876 | SHOST_DIX_TYPE1_PROTECTION
0c470874 2877 | SHOST_DIX_TYPE2_PROTECTION
bad75002 2878 | SHOST_DIX_TYPE3_PROTECTION);
9e522cd8
AE		 2879
2880 guard = SHOST_DIX_GUARD_CRC;
2881
2882 if (IS_PI_IPGUARD_CAPABLE(ha) &&
2883 (ql2xenabledif > 1 || IS_PI_DIFB_DIX0_CAPABLE(ha)))
2884 guard |= SHOST_DIX_GUARD_IP;
2885
2886 scsi_host_set_guard(host, guard);
bad75002
AE		 2887 } else
2888 base_vha->flags.difdix_supported = 0;
2889 }
2890
a9083016
GM		 2891 ha->isp_ops->enable_intrs(ha);
2892
1fe19ee4
AB		 2893 if (IS_QLAFX00(ha)) {
2894 ret = qlafx00_fx_disc(base_vha,
2895 &base_vha->hw->mr.fcport, FXDISC_GET_CONFIG_INFO);
2896 host->sg_tablesize = (ha->mr.extended_io_enabled) ?
2897 QLA_SG_ALL : 128;
2898 }
2899
a1541d5a
AV		 2900 ret = scsi_add_host(host, &pdev->dev);
2901 if (ret)
2902 goto probe_failed;
2903
1486400f
MR		 2904 base_vha->flags.init_done = 1;
2905 base_vha->flags.online = 1;
edaa5c74 2906 ha->prev_minidump_failed = 0;
1486400f 2907
7c3df132
SK		 2908 ql_dbg(ql_dbg_init, base_vha, 0x00f2,
2909 "Init done and hba is online.\n");
2910
2d70c103
NB		 2911 if (qla_ini_mode_enabled(base_vha))
2912 scsi_scan_host(host);
2913 else
2914 ql_dbg(ql_dbg_init, base_vha, 0x0122,
2915 "skipping scsi_scan_host() for non-initiator port\n");
1e99e33a 2916
e315cd28 2917 qla2x00_alloc_sysfs_attr(base_vha);
a1541d5a 2918
8ae6d9c7 2919 if (IS_QLAFX00(ha)) {
8ae6d9c7
GM		 2920 ret = qlafx00_fx_disc(base_vha,
2921 &base_vha->hw->mr.fcport, FXDISC_GET_PORT_INFO);
2922
2923 /* Register system information */
2924 ret = qlafx00_fx_disc(base_vha,
2925 &base_vha->hw->mr.fcport, FXDISC_REG_HOST_INFO);
2926 }
2927
e315cd28 2928 qla2x00_init_host_attr(base_vha);
a1541d5a 2929
e315cd28 2930 qla2x00_dfs_setup(base_vha);
df613b96 2931
03eb912a
AB		 2932 ql_log(ql_log_info, base_vha, 0x00fb,
2933 "QLogic %s - %s.\n", ha->model_number, ha->model_desc);
7c3df132
SK		 2934 ql_log(ql_log_info, base_vha, 0x00fc,
2935 "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n",
2936 pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info),
2937 pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-',
2938 base_vha->host_no,
df57caba 2939 ha->isp_ops->fw_version_str(base_vha, fw_str, sizeof(fw_str)));
1da177e4 2940
2d70c103
NB		 2941 qlt_add_target(ha, base_vha);
2942
6b383979 2943 clear_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags);
1da177e4
LT		 2944 return 0;
2945
6e9f21f3 2946probe_init_failed:
2afa19a9 2947 qla2x00_free_req_que(ha, req);
9a347ff4
CD		 2948 ha->req_q_map[0] = NULL;
2949 clear_bit(0, ha->req_qid_map);
2afa19a9 2950 qla2x00_free_rsp_que(ha, rsp);
9a347ff4
CD		 2951 ha->rsp_q_map[0] = NULL;
2952 clear_bit(0, ha->rsp_qid_map);
2afa19a9 2953 ha->max_req_queues = ha->max_rsp_queues = 0;
6e9f21f3 2954
1da177e4 2955probe_failed:
b9978769
AV		 2956 if (base_vha->timer_active)
2957 qla2x00_stop_timer(base_vha);
2958 base_vha->flags.online = 0;
2959 if (ha->dpc_thread) {
2960 struct task_struct *t = ha->dpc_thread;
2961
2962 ha->dpc_thread = NULL;
2963 kthread_stop(t);
2964 }
2965
e315cd28 2966 qla2x00_free_device(base_vha);
1da177e4 2967
e315cd28 2968 scsi_host_put(base_vha->host);
1da177e4 2969
e315cd28 2970probe_hw_failed:
1a2fbf18
JL		 2971 qla2x00_clear_drv_active(ha);
2972
0a63ad12 2973iospace_config_failed:
7ec0effd 2974 if (IS_P3P_TYPE(ha)) {
0a63ad12 2975 if (!ha->nx_pcibase)
f73cb695 2976 iounmap((device_reg_t *)ha->nx_pcibase);
a9083016 2977 if (!ql2xdbwr)
f73cb695 2978 iounmap((device_reg_t *)ha->nxdb_wr_ptr);
a9083016
GM		 2979 } else {
2980 if (ha->iobase)
2981 iounmap(ha->iobase);
8ae6d9c7
GM		 2982 if (ha->cregbase)
2983 iounmap(ha->cregbase);
a9083016 2984 }
e315cd28
AC		 2985 pci_release_selected_regions(ha->pdev, ha->bars);
2986 kfree(ha);
2987 ha = NULL;
1da177e4 2988
a1541d5a 2989probe_out:
e315cd28 2990 pci_disable_device(pdev);
a1541d5a 2991 return ret;
1da177e4 2992}
1da177e4 2993
e30d1756
MI		 2994static void
2995qla2x00_shutdown(struct pci_dev *pdev)
2996{
2997 scsi_qla_host_t *vha;
2998 struct qla_hw_data *ha;
2999
552f3f9a
MI		 3000 if (!atomic_read(&pdev->enable_cnt))
3001 return;
3002
e30d1756
MI		 3003 vha = pci_get_drvdata(pdev);
3004 ha = vha->hw;
3005
42479343
AB		 3006 /* Notify ISPFX00 firmware */
3007 if (IS_QLAFX00(ha))
3008 qlafx00_driver_shutdown(vha, 20);
3009
e30d1756
MI		 3010 /* Turn-off FCE trace */
3011 if (ha->flags.fce_enabled) {
3012 qla2x00_disable_fce_trace(vha, NULL, NULL);
3013 ha->flags.fce_enabled = 0;
3014 }
3015
3016 /* Turn-off EFT trace */
3017 if (ha->eft)
3018 qla2x00_disable_eft_trace(vha);
3019
3020 /* Stop currently executing firmware. */
3021 qla2x00_try_to_stop_firmware(vha);
3022
3023 /* Turn adapter off line */
3024 vha->flags.online = 0;
3025
3026 /* turn-off interrupts on the card */
3027 if (ha->interrupts_on) {
3028 vha->flags.init_done = 0;
3029 ha->isp_ops->disable_intrs(ha);
3030 }
3031
3032 qla2x00_free_irqs(vha);
3033
3034 qla2x00_free_fw_dump(ha);
61d41f61
CD		 3035
3036 pci_disable_pcie_error_reporting(pdev);
3037 pci_disable_device(pdev);
e30d1756
MI		 3038}
3039
fe1b806f 3040/* Deletes all the virtual ports for a given ha */
4c993f76 3041static void
fe1b806f 3042qla2x00_delete_all_vps(struct qla_hw_data *ha, scsi_qla_host_t *base_vha)
1da177e4 3043{
fe1b806f
CD		 3044 struct Scsi_Host *scsi_host;
3045 scsi_qla_host_t *vha;
feafb7b1 3046 unsigned long flags;
e315cd28 3047
43ebf16d
AE		 3048 mutex_lock(&ha->vport_lock);
3049 while (ha->cur_vport_count) {
43ebf16d 3050 spin_lock_irqsave(&ha->vport_slock, flags);
feafb7b1 3051
43ebf16d
AE		 3052 BUG_ON(base_vha->list.next == &ha->vp_list);
3053 /* This assumes first entry in ha->vp_list is always base vha */
3054 vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list);
fe1b806f 3055 scsi_host = scsi_host_get(vha->host);
feafb7b1 3056
43ebf16d
AE		 3057 spin_unlock_irqrestore(&ha->vport_slock, flags);
3058 mutex_unlock(&ha->vport_lock);
3059
3060 fc_vport_terminate(vha->fc_vport);
3061 scsi_host_put(vha->host);
feafb7b1 3062
43ebf16d 3063 mutex_lock(&ha->vport_lock);
e315cd28 3064 }
43ebf16d 3065 mutex_unlock(&ha->vport_lock);
fe1b806f 3066}
1da177e4 3067
fe1b806f
CD		 3068/* Stops all deferred work threads */
3069static void
3070qla2x00_destroy_deferred_work(struct qla_hw_data *ha)
3071{
68ca949c
AC		 3072 /* Flush the work queue and remove it */
3073 if (ha->wq) {
3074 flush_workqueue(ha->wq);
3075 destroy_workqueue(ha->wq);
3076 ha->wq = NULL;
3077 }
3078
7d613ac6
SV		 3079 /* Cancel all work and destroy DPC workqueues */
3080 if (ha->dpc_lp_wq) {
3081 cancel_work_sync(&ha->idc_aen);
3082 destroy_workqueue(ha->dpc_lp_wq);
3083 ha->dpc_lp_wq = NULL;
3084 }
3085
3086 if (ha->dpc_hp_wq) {
3087 cancel_work_sync(&ha->nic_core_reset);
3088 cancel_work_sync(&ha->idc_state_handler);
3089 cancel_work_sync(&ha->nic_core_unrecoverable);
3090 destroy_workqueue(ha->dpc_hp_wq);
3091 ha->dpc_hp_wq = NULL;
3092 }
3093
b9978769
AV		 3094 /* Kill the kernel thread for this host */
3095 if (ha->dpc_thread) {
3096 struct task_struct *t = ha->dpc_thread;
3097
3098 /*
3099 * qla2xxx_wake_dpc checks for ->dpc_thread
3100 * so we need to zero it out.
3101 */
3102 ha->dpc_thread = NULL;
3103 kthread_stop(t);
3104 }
fe1b806f 3105}
1da177e4 3106
fe1b806f
CD		 3107static void
3108qla2x00_unmap_iobases(struct qla_hw_data *ha)
3109{
a9083016 3110 if (IS_QLA82XX(ha)) {
b963752f 3111
f73cb695 3112 iounmap((device_reg_t *)ha->nx_pcibase);
a9083016 3113 if (!ql2xdbwr)
f73cb695 3114 iounmap((device_reg_t *)ha->nxdb_wr_ptr);
a9083016
GM		 3115 } else {
3116 if (ha->iobase)
3117 iounmap(ha->iobase);
1da177e4 3118
8ae6d9c7
GM		 3119 if (ha->cregbase)
3120 iounmap(ha->cregbase);
3121
a9083016
GM		 3122 if (ha->mqiobase)
3123 iounmap(ha->mqiobase);
6246b8a1 3124
f73cb695 3125 if ((IS_QLA83XX(ha) || IS_QLA27XX(ha)) && ha->msixbase)
6246b8a1 3126 iounmap(ha->msixbase);
a9083016 3127 }
fe1b806f
CD		 3128}
3129
3130static void
db7157d4 3131qla2x00_clear_drv_active(struct qla_hw_data *ha)
fe1b806f 3132{
fe1b806f
CD		 3133 if (IS_QLA8044(ha)) {
3134 qla8044_idc_lock(ha);
c41afc9a 3135 qla8044_clear_drv_active(ha);
fe1b806f
CD		 3136 qla8044_idc_unlock(ha);
3137 } else if (IS_QLA82XX(ha)) {
3138 qla82xx_idc_lock(ha);
3139 qla82xx_clear_drv_active(ha);
3140 qla82xx_idc_unlock(ha);
3141 }
3142}
3143
3144static void
3145qla2x00_remove_one(struct pci_dev *pdev)
3146{
3147 scsi_qla_host_t *base_vha;
3148 struct qla_hw_data *ha;
3149
beb9e315
JL		 3150 base_vha = pci_get_drvdata(pdev);
3151 ha = base_vha->hw;
3152
3153 /* Indicate device removal to prevent future board_disable and wait
3154 * until any pending board_disable has completed. */
3155 set_bit(PFLG_DRIVER_REMOVING, &base_vha->pci_flags);
3156 cancel_work_sync(&ha->board_disable);
3157
fe1b806f 3158 /*
beb9e315
JL		 3159 * If the PCI device is disabled then there was a PCI-disconnect and
3160 * qla2x00_disable_board_on_pci_error has taken care of most of the
3161 * resources.
fe1b806f 3162 */
beb9e315
JL		 3163 if (!atomic_read(&pdev->enable_cnt)) {
3164 scsi_host_put(base_vha->host);
3165 kfree(ha);
3166 pci_set_drvdata(pdev, NULL);
fe1b806f 3167 return;
beb9e315 3168 }
fe1b806f 3169
638a1a01
SC		 3170 qla2x00_wait_for_hba_ready(base_vha);
3171
fe1b806f
CD		 3172 set_bit(UNLOADING, &base_vha->dpc_flags);
3173
3174 if (IS_QLAFX00(ha))
3175 qlafx00_driver_shutdown(base_vha, 20);
3176
3177 qla2x00_delete_all_vps(ha, base_vha);
3178
3179 if (IS_QLA8031(ha)) {
3180 ql_dbg(ql_dbg_p3p, base_vha, 0xb07e,
3181 "Clearing fcoe driver presence.\n");
3182 if (qla83xx_clear_drv_presence(base_vha) != QLA_SUCCESS)
3183 ql_dbg(ql_dbg_p3p, base_vha, 0xb079,
3184 "Error while clearing DRV-Presence.\n");
3185 }
3186
3187 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
3188
3189 qla2x00_dfs_remove(base_vha);
3190
3191 qla84xx_put_chip(base_vha);
3192
2d5a4c34
HM		 3193 /* Laser should be disabled only for ISP2031 */
3194 if (IS_QLA2031(ha))
3195 qla83xx_disable_laser(base_vha);
3196
fe1b806f
CD		 3197 /* Disable timer */
3198 if (base_vha->timer_active)
3199 qla2x00_stop_timer(base_vha);
3200
3201 base_vha->flags.online = 0;
3202
3203 qla2x00_destroy_deferred_work(ha);
3204
3205 qlt_remove_target(ha, base_vha);
3206
3207 qla2x00_free_sysfs_attr(base_vha, true);
3208
3209 fc_remove_host(base_vha->host);
3210
3211 scsi_remove_host(base_vha->host);
3212
3213 qla2x00_free_device(base_vha);
3214
db7157d4 3215 qla2x00_clear_drv_active(ha);
fe1b806f 3216
d2749ffa
AE		 3217 scsi_host_put(base_vha->host);
3218
fe1b806f 3219 qla2x00_unmap_iobases(ha);
73208dfd 3220
e315cd28
AC		 3221 pci_release_selected_regions(ha->pdev, ha->bars);
3222 kfree(ha);
3223 ha = NULL;
1da177e4 3224
90a86fc0
JC		 3225 pci_disable_pcie_error_reporting(pdev);
3226
665db93b 3227 pci_disable_device(pdev);
1da177e4 3228}
1da177e4
LT		 3229
3230static void
e315cd28 3231qla2x00_free_device(scsi_qla_host_t *vha)
1da177e4 3232{
e315cd28 3233 struct qla_hw_data *ha = vha->hw;
1da177e4 3234
85880801
AV		 3235 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
3236
3237 /* Disable timer */
3238 if (vha->timer_active)
3239 qla2x00_stop_timer(vha);
3240
2afa19a9 3241 qla25xx_delete_queues(vha);
fe1b806f 3242
df613b96 3243 if (ha->flags.fce_enabled)
e315cd28 3244 qla2x00_disable_fce_trace(vha, NULL, NULL);
df613b96 3245
a7a167bf 3246 if (ha->eft)
e315cd28 3247 qla2x00_disable_eft_trace(vha);
a7a167bf 3248
f6ef3b18 3249 /* Stop currently executing firmware. */
e315cd28 3250 qla2x00_try_to_stop_firmware(vha);
1da177e4 3251
85880801
AV		 3252 vha->flags.online = 0;
3253
f6ef3b18 3254 /* turn-off interrupts on the card */
a9083016
GM		 3255 if (ha->interrupts_on) {
3256 vha->flags.init_done = 0;
fd34f556 3257 ha->isp_ops->disable_intrs(ha);
a9083016 3258 }
f6ef3b18 3259
e315cd28 3260 qla2x00_free_irqs(vha);
1da177e4 3261
8867048b
CD		 3262 qla2x00_free_fcports(vha);
3263
e315cd28 3264 qla2x00_mem_free(ha);
73208dfd 3265
08de2844
GM		 3266 qla82xx_md_free(vha);
3267
73208dfd 3268 qla2x00_free_queues(ha);
1da177e4
LT		 3269}
3270
8867048b
CD		 3271void qla2x00_free_fcports(struct scsi_qla_host *vha)
3272{
3273 fc_port_t *fcport, *tfcport;
3274
3275 list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list) {
3276 list_del(&fcport->list);
5f16b331 3277 qla2x00_clear_loop_id(fcport);
8867048b
CD		 3278 kfree(fcport);
3279 fcport = NULL;
3280 }
3281}
3282
d97994dc 3283static inline void
e315cd28 3284qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport,
d97994dc 3285 int defer)
3286{
d97994dc 3287 struct fc_rport *rport;
67becc00 3288 scsi_qla_host_t *base_vha;
044d78e1 3289 unsigned long flags;
d97994dc 3290
3291 if (!fcport->rport)
3292 return;
3293
3294 rport = fcport->rport;
3295 if (defer) {
67becc00 3296 base_vha = pci_get_drvdata(vha->hw->pdev);
044d78e1 3297 spin_lock_irqsave(vha->host->host_lock, flags);
d97994dc 3298 fcport->drport = rport;
044d78e1 3299 spin_unlock_irqrestore(vha->host->host_lock, flags);
67becc00
AV		 3300 set_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags);
3301 qla2xxx_wake_dpc(base_vha);
2d70c103 3302 } else {
d97994dc 3303 fc_remote_port_delete(rport);
2d70c103
NB		 3304 qlt_fc_port_deleted(vha, fcport);
3305 }
d97994dc 3306}
3307
1da177e4
LT		 3308/*
3309 * qla2x00_mark_device_lost Updates fcport state when device goes offline.
3310 *
3311 * Input: ha = adapter block pointer. fcport = port structure pointer.
3312 *
3313 * Return: None.
3314 *
3315 * Context:
3316 */
e315cd28 3317void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport,
d97994dc 3318 int do_login, int defer)
1da177e4 3319{
8ae6d9c7
GM		 3320 if (IS_QLAFX00(vha->hw)) {
3321 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
3322 qla2x00_schedule_rport_del(vha, fcport, defer);
3323 return;
3324 }
3325
2c3dfe3f 3326 if (atomic_read(&fcport->state) == FCS_ONLINE &&
c6d39e23 3327 vha->vp_idx == fcport->vha->vp_idx) {
ec426e10 3328 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
e315cd28
AC		 3329 qla2x00_schedule_rport_del(vha, fcport, defer);
3330 }
fa2a1ce5 3331 /*
1da177e4
LT		 3332 * We may need to retry the login, so don't change the state of the
3333 * port but do the retries.
3334 */
3335 if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD)
ec426e10 3336 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
1da177e4
LT		 3337
3338 if (!do_login)
3339 return;
3340
3341 if (fcport->login_retry == 0) {
e315cd28
AC		 3342 fcport->login_retry = vha->hw->login_retry_count;
3343 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
1da177e4 3344
7c3df132 3345 ql_dbg(ql_dbg_disc, vha, 0x2067,
7b833558
OK		 3346 "Port login retry %8phN, id = 0x%04x retry cnt=%d.\n",
3347 fcport->port_name, fcport->loop_id, fcport->login_retry);
1da177e4
LT		 3348 }
3349}
3350
3351/*
3352 * qla2x00_mark_all_devices_lost
3353 * Updates fcport state when device goes offline.
3354 *
3355 * Input:
3356 * ha = adapter block pointer.
3357 * fcport = port structure pointer.
3358 *
3359 * Return:
3360 * None.
3361 *
3362 * Context:
3363 */
3364void
e315cd28 3365qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha, int defer)
1da177e4
LT		 3366{
3367 fc_port_t *fcport;
3368
e315cd28 3369 list_for_each_entry(fcport, &vha->vp_fcports, list) {
c6d39e23 3370 if (vha->vp_idx != 0 && vha->vp_idx != fcport->vha->vp_idx)
1da177e4 3371 continue;
0d6e61bc 3372
1da177e4
LT		 3373 /*
3374 * No point in marking the device as lost, if the device is
3375 * already DEAD.
3376 */
3377 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD)
3378 continue;
e315cd28 3379 if (atomic_read(&fcport->state) == FCS_ONLINE) {
ec426e10 3380 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
0d6e61bc
AV		 3381 if (defer)
3382 qla2x00_schedule_rport_del(vha, fcport, defer);
c6d39e23 3383 else if (vha->vp_idx == fcport->vha->vp_idx)
0d6e61bc
AV		 3384 qla2x00_schedule_rport_del(vha, fcport, defer);
3385 }
1da177e4
LT		 3386 }
3387}
3388
3389/*
3390* qla2x00_mem_alloc
3391* Allocates adapter memory.
3392*
3393* Returns:
3394* 0 = success.
e8711085 3395* !0 = failure.
1da177e4 3396*/
e8711085 3397static int
73208dfd
AC		 3398qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len,
3399 struct req_que **req, struct rsp_que **rsp)
1da177e4
LT		 3400{
3401 char name[16];
1da177e4 3402
e8711085 3403 ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size,
e315cd28 3404 &ha->init_cb_dma, GFP_KERNEL);
e8711085 3405 if (!ha->init_cb)
e315cd28 3406 goto fail;
e8711085 3407
2d70c103
NB		 3408 if (qlt_mem_alloc(ha) < 0)
3409 goto fail_free_init_cb;
3410
642ef983
CD		 3411 ha->gid_list = dma_alloc_coherent(&ha->pdev->dev,
3412 qla2x00_gid_list_size(ha), &ha->gid_list_dma, GFP_KERNEL);
e315cd28 3413 if (!ha->gid_list)
2d70c103 3414 goto fail_free_tgt_mem;
1da177e4 3415
e8711085
AV		 3416 ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep);
3417 if (!ha->srb_mempool)
e315cd28 3418 goto fail_free_gid_list;
e8711085 3419
7ec0effd 3420 if (IS_P3P_TYPE(ha)) {
a9083016
GM		 3421 /* Allocate cache for CT6 Ctx. */
3422 if (!ctx_cachep) {
3423 ctx_cachep = kmem_cache_create("qla2xxx_ctx",
3424 sizeof(struct ct6_dsd), 0,
3425 SLAB_HWCACHE_ALIGN, NULL);
3426 if (!ctx_cachep)
3427 goto fail_free_gid_list;
3428 }
3429 ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ,
3430 ctx_cachep);
3431 if (!ha->ctx_mempool)
3432 goto fail_free_srb_mempool;
7c3df132
SK		 3433 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021,
3434 "ctx_cachep=%p ctx_mempool=%p.\n",
3435 ctx_cachep, ha->ctx_mempool);
a9083016
GM		 3436 }
3437
e8711085
AV		 3438 /* Get memory for cached NVRAM */
3439 ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL);
3440 if (!ha->nvram)
a9083016 3441 goto fail_free_ctx_mempool;
e8711085 3442
e315cd28
AC		 3443 snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME,
3444 ha->pdev->device);
3445 ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3446 DMA_POOL_SIZE, 8, 0);
3447 if (!ha->s_dma_pool)
3448 goto fail_free_nvram;
3449
7c3df132
SK		 3450 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022,
3451 "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n",
3452 ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool);
3453
7ec0effd 3454 if (IS_P3P_TYPE(ha) || ql2xenabledif) {
a9083016
GM		 3455 ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3456 DSD_LIST_DMA_POOL_SIZE, 8, 0);
3457 if (!ha->dl_dma_pool) {
7c3df132
SK		 3458 ql_log_pci(ql_log_fatal, ha->pdev, 0x0023,
3459 "Failed to allocate memory for dl_dma_pool.\n");
a9083016
GM		 3460 goto fail_s_dma_pool;
3461 }
3462
3463 ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3464 FCP_CMND_DMA_POOL_SIZE, 8, 0);
3465 if (!ha->fcp_cmnd_dma_pool) {
7c3df132
SK		 3466 ql_log_pci(ql_log_fatal, ha->pdev, 0x0024,
3467 "Failed to allocate memory for fcp_cmnd_dma_pool.\n");
a9083016
GM		 3468 goto fail_dl_dma_pool;
3469 }
7c3df132
SK		 3470 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025,
3471 "dl_dma_pool=%p fcp_cmnd_dma_pool=%p.\n",
3472 ha->dl_dma_pool, ha->fcp_cmnd_dma_pool);
a9083016
GM		 3473 }
3474
e8711085
AV		 3475 /* Allocate memory for SNS commands */
3476 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
e315cd28 3477 /* Get consistent memory allocated for SNS commands */
e8711085 3478 ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev,
e315cd28 3479 sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL);
e8711085 3480 if (!ha->sns_cmd)
e315cd28 3481 goto fail_dma_pool;
7c3df132 3482 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026,
d8424f68 3483 "sns_cmd: %p.\n", ha->sns_cmd);
e8711085 3484 } else {
e315cd28 3485 /* Get consistent memory allocated for MS IOCB */
e8711085 3486 ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
e315cd28 3487 &ha->ms_iocb_dma);
e8711085 3488 if (!ha->ms_iocb)
e315cd28
AC		 3489 goto fail_dma_pool;
3490 /* Get consistent memory allocated for CT SNS commands */
e8711085 3491 ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev,
e315cd28 3492 sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL);
e8711085
AV		 3493 if (!ha->ct_sns)
3494 goto fail_free_ms_iocb;
7c3df132
SK		 3495 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027,
3496 "ms_iocb=%p ct_sns=%p.\n",
3497 ha->ms_iocb, ha->ct_sns);
1da177e4
LT		 3498 }
3499
e315cd28 3500 /* Allocate memory for request ring */
73208dfd
AC		 3501 *req = kzalloc(sizeof(struct req_que), GFP_KERNEL);
3502 if (!*req) {
7c3df132
SK		 3503 ql_log_pci(ql_log_fatal, ha->pdev, 0x0028,
3504 "Failed to allocate memory for req.\n");
e315cd28
AC		 3505 goto fail_req;
3506 }
73208dfd
AC		 3507 (*req)->length = req_len;
3508 (*req)->ring = dma_alloc_coherent(&ha->pdev->dev,
3509 ((*req)->length + 1) * sizeof(request_t),
3510 &(*req)->dma, GFP_KERNEL);
3511 if (!(*req)->ring) {
7c3df132
SK		 3512 ql_log_pci(ql_log_fatal, ha->pdev, 0x0029,
3513 "Failed to allocate memory for req_ring.\n");
e315cd28
AC		 3514 goto fail_req_ring;
3515 }
3516 /* Allocate memory for response ring */
73208dfd
AC		 3517 *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL);
3518 if (!*rsp) {
7c3df132
SK		 3519 ql_log_pci(ql_log_fatal, ha->pdev, 0x002a,
3520 "Failed to allocate memory for rsp.\n");
e315cd28
AC		 3521 goto fail_rsp;
3522 }
73208dfd
AC		 3523 (*rsp)->hw = ha;
3524 (*rsp)->length = rsp_len;
3525 (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev,
3526 ((*rsp)->length + 1) * sizeof(response_t),
3527 &(*rsp)->dma, GFP_KERNEL);
3528 if (!(*rsp)->ring) {
7c3df132
SK		 3529 ql_log_pci(ql_log_fatal, ha->pdev, 0x002b,
3530 "Failed to allocate memory for rsp_ring.\n");
e315cd28
AC		 3531 goto fail_rsp_ring;
3532 }
73208dfd
AC		 3533 (*req)->rsp = *rsp;
3534 (*rsp)->req = *req;
7c3df132
SK		 3535 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c,
3536 "req=%p req->length=%d req->ring=%p rsp=%p "
3537 "rsp->length=%d rsp->ring=%p.\n",
3538 *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length,
3539 (*rsp)->ring);
73208dfd
AC		 3540 /* Allocate memory for NVRAM data for vports */
3541 if (ha->nvram_npiv_size) {
3542 ha->npiv_info = kzalloc(sizeof(struct qla_npiv_entry) *
7c3df132 3543 ha->nvram_npiv_size, GFP_KERNEL);
73208dfd 3544 if (!ha->npiv_info) {
7c3df132
SK		 3545 ql_log_pci(ql_log_fatal, ha->pdev, 0x002d,
3546 "Failed to allocate memory for npiv_info.\n");
73208dfd
AC		 3547 goto fail_npiv_info;
3548 }
3549 } else
3550 ha->npiv_info = NULL;
e8711085 3551
b64b0e8f 3552 /* Get consistent memory allocated for EX-INIT-CB. */
f73cb695 3553 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha)) {
b64b0e8f
AV		 3554 ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
3555 &ha->ex_init_cb_dma);
3556 if (!ha->ex_init_cb)
3557 goto fail_ex_init_cb;
7c3df132
SK		 3558 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e,
3559 "ex_init_cb=%p.\n", ha->ex_init_cb);
b64b0e8f
AV		 3560 }
3561
a9083016
GM		 3562 INIT_LIST_HEAD(&ha->gbl_dsd_list);
3563
5ff1d584
AV		 3564 /* Get consistent memory allocated for Async Port-Database. */
3565 if (!IS_FWI2_CAPABLE(ha)) {
3566 ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
3567 &ha->async_pd_dma);
3568 if (!ha->async_pd)
3569 goto fail_async_pd;
7c3df132
SK		 3570 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f,
3571 "async_pd=%p.\n", ha->async_pd);
5ff1d584
AV		 3572 }
3573
e315cd28 3574 INIT_LIST_HEAD(&ha->vp_list);
5f16b331
CD		 3575
3576 /* Allocate memory for our loop_id bitmap */
3577 ha->loop_id_map = kzalloc(BITS_TO_LONGS(LOOPID_MAP_SIZE) * sizeof(long),
3578 GFP_KERNEL);
3579 if (!ha->loop_id_map)
3580 goto fail_async_pd;
3581 else {
3582 qla2x00_set_reserved_loop_ids(ha);
3583 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0123,
b2a72ec3 3584 "loop_id_map=%p.\n", ha->loop_id_map);
5f16b331
CD		 3585 }
3586
b2a72ec3 3587 return 0;
e315cd28 3588
5ff1d584
AV		 3589fail_async_pd:
3590 dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma);
b64b0e8f
AV		 3591fail_ex_init_cb:
3592 kfree(ha->npiv_info);
73208dfd
AC		 3593fail_npiv_info:
3594 dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) *
3595 sizeof(response_t), (*rsp)->ring, (*rsp)->dma);
3596 (*rsp)->ring = NULL;
3597 (*rsp)->dma = 0;
e315cd28 3598fail_rsp_ring:
73208dfd 3599 kfree(*rsp);
e315cd28 3600fail_rsp:
73208dfd
AC		 3601 dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) *
3602 sizeof(request_t), (*req)->ring, (*req)->dma);
3603 (*req)->ring = NULL;
3604 (*req)->dma = 0;
e315cd28 3605fail_req_ring:
73208dfd 3606 kfree(*req);
e315cd28
AC		 3607fail_req:
3608 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
3609 ha->ct_sns, ha->ct_sns_dma);
3610 ha->ct_sns = NULL;
3611 ha->ct_sns_dma = 0;
e8711085
AV		 3612fail_free_ms_iocb:
3613 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
3614 ha->ms_iocb = NULL;
3615 ha->ms_iocb_dma = 0;
e315cd28 3616fail_dma_pool:
bad75002 3617 if (IS_QLA82XX(ha) || ql2xenabledif) {
a9083016
GM		 3618 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
3619 ha->fcp_cmnd_dma_pool = NULL;
3620 }
3621fail_dl_dma_pool:
bad75002 3622 if (IS_QLA82XX(ha) || ql2xenabledif) {
a9083016
GM		 3623 dma_pool_destroy(ha->dl_dma_pool);
3624 ha->dl_dma_pool = NULL;
3625 }
3626fail_s_dma_pool:
e315cd28
AC		 3627 dma_pool_destroy(ha->s_dma_pool);
3628 ha->s_dma_pool = NULL;
e8711085
AV		 3629fail_free_nvram:
3630 kfree(ha->nvram);
3631 ha->nvram = NULL;
a9083016
GM		 3632fail_free_ctx_mempool:
3633 mempool_destroy(ha->ctx_mempool);
3634 ha->ctx_mempool = NULL;
e8711085
AV		 3635fail_free_srb_mempool:
3636 mempool_destroy(ha->srb_mempool);
3637 ha->srb_mempool = NULL;
e8711085 3638fail_free_gid_list:
642ef983
CD		 3639 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
3640 ha->gid_list,
e315cd28 3641 ha->gid_list_dma);
e8711085
AV		 3642 ha->gid_list = NULL;
3643 ha->gid_list_dma = 0;
2d70c103
NB		 3644fail_free_tgt_mem:
3645 qlt_mem_free(ha);
e315cd28
AC		 3646fail_free_init_cb:
3647 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb,
3648 ha->init_cb_dma);
3649 ha->init_cb = NULL;
3650 ha->init_cb_dma = 0;
e8711085 3651fail:
7c3df132
SK		 3652 ql_log(ql_log_fatal, NULL, 0x0030,
3653 "Memory allocation failure.\n");
e8711085 3654 return -ENOMEM;
1da177e4
LT		 3655}
3656
3657/*
e30d1756
MI		 3658* qla2x00_free_fw_dump
3659* Frees fw dump stuff.
1da177e4
LT		 3660*
3661* Input:
7ec0effd 3662* ha = adapter block pointer
1da177e4 3663*/
a824ebb3 3664static void
e30d1756 3665qla2x00_free_fw_dump(struct qla_hw_data *ha)
1da177e4 3666{
df613b96 3667 if (ha->fce)
f73cb695
CD		 3668 dma_free_coherent(&ha->pdev->dev,
3669 FCE_SIZE, ha->fce, ha->fce_dma);
df613b96 3670
f73cb695
CD		 3671 if (ha->eft)
3672 dma_free_coherent(&ha->pdev->dev,
3673 EFT_SIZE, ha->eft, ha->eft_dma);
3674
3675 if (ha->fw_dump)
a7a167bf 3676 vfree(ha->fw_dump);
f73cb695
CD		 3677 if (ha->fw_dump_template)
3678 vfree(ha->fw_dump_template);
3679
e30d1756
MI		 3680 ha->fce = NULL;
3681 ha->fce_dma = 0;
3682 ha->eft = NULL;
3683 ha->eft_dma = 0;
e30d1756 3684 ha->fw_dumped = 0;
61f098dd 3685 ha->fw_dump_cap_flags = 0;
e30d1756 3686 ha->fw_dump_reading = 0;
f73cb695
CD		 3687 ha->fw_dump = NULL;
3688 ha->fw_dump_len = 0;
3689 ha->fw_dump_template = NULL;
3690 ha->fw_dump_template_len = 0;
e30d1756
MI		 3691}
3692
3693/*
3694* qla2x00_mem_free
3695* Frees all adapter allocated memory.
3696*
3697* Input:
3698* ha = adapter block pointer.
3699*/
3700static void
3701qla2x00_mem_free(struct qla_hw_data *ha)
3702{
3703 qla2x00_free_fw_dump(ha);
3704
81178772
SK		 3705 if (ha->mctp_dump)
3706 dma_free_coherent(&ha->pdev->dev, MCTP_DUMP_SIZE, ha->mctp_dump,
3707 ha->mctp_dump_dma);
3708
e30d1756
MI		 3709 if (ha->srb_mempool)
3710 mempool_destroy(ha->srb_mempool);
a7a167bf 3711
11bbc1d8
AV		 3712 if (ha->dcbx_tlv)
3713 dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE,
3714 ha->dcbx_tlv, ha->dcbx_tlv_dma);
3715
ce0423f4
AV		 3716 if (ha->xgmac_data)
3717 dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE,
3718 ha->xgmac_data, ha->xgmac_data_dma);
3719
1da177e4
LT		 3720 if (ha->sns_cmd)
3721 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
e315cd28 3722 ha->sns_cmd, ha->sns_cmd_dma);
1da177e4
LT		 3723
3724 if (ha->ct_sns)
3725 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
e315cd28 3726 ha->ct_sns, ha->ct_sns_dma);
1da177e4 3727
88729e53
AV		 3728 if (ha->sfp_data)
3729 dma_pool_free(ha->s_dma_pool, ha->sfp_data, ha->sfp_data_dma);
3730
1da177e4
LT		 3731 if (ha->ms_iocb)
3732 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
3733
b64b0e8f 3734 if (ha->ex_init_cb)
a9083016
GM		 3735 dma_pool_free(ha->s_dma_pool,
3736 ha->ex_init_cb, ha->ex_init_cb_dma);
b64b0e8f 3737
5ff1d584
AV		 3738 if (ha->async_pd)
3739 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
3740
1da177e4
LT		 3741 if (ha->s_dma_pool)
3742 dma_pool_destroy(ha->s_dma_pool);
3743
1da177e4 3744 if (ha->gid_list)
642ef983
CD		 3745 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
3746 ha->gid_list, ha->gid_list_dma);
1da177e4 3747
a9083016
GM		 3748 if (IS_QLA82XX(ha)) {
3749 if (!list_empty(&ha->gbl_dsd_list)) {
3750 struct dsd_dma *dsd_ptr, *tdsd_ptr;
3751
3752 /* clean up allocated prev pool */
3753 list_for_each_entry_safe(dsd_ptr,
3754 tdsd_ptr, &ha->gbl_dsd_list, list) {
3755 dma_pool_free(ha->dl_dma_pool,
3756 dsd_ptr->dsd_addr, dsd_ptr->dsd_list_dma);
3757 list_del(&dsd_ptr->list);
3758 kfree(dsd_ptr);
3759 }
3760 }
3761 }
3762
3763 if (ha->dl_dma_pool)
3764 dma_pool_destroy(ha->dl_dma_pool);
3765
3766 if (ha->fcp_cmnd_dma_pool)
3767 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
3768
3769 if (ha->ctx_mempool)
3770 mempool_destroy(ha->ctx_mempool);
3771
2d70c103
NB		 3772 qlt_mem_free(ha);
3773
e315cd28
AC		 3774 if (ha->init_cb)
3775 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size,
a9083016 3776 ha->init_cb, ha->init_cb_dma);
e315cd28
AC		 3777 vfree(ha->optrom_buffer);
3778 kfree(ha->nvram);
73208dfd 3779 kfree(ha->npiv_info);
7a67735b 3780 kfree(ha->swl);
5f16b331 3781 kfree(ha->loop_id_map);
1da177e4 3782
e8711085 3783 ha->srb_mempool = NULL;
a9083016 3784 ha->ctx_mempool = NULL;
1da177e4
LT		 3785 ha->sns_cmd = NULL;
3786 ha->sns_cmd_dma = 0;
3787 ha->ct_sns = NULL;
3788 ha->ct_sns_dma = 0;
3789 ha->ms_iocb = NULL;
3790 ha->ms_iocb_dma = 0;
1da177e4
LT		 3791 ha->init_cb = NULL;
3792 ha->init_cb_dma = 0;
b64b0e8f
AV		 3793 ha->ex_init_cb = NULL;
3794 ha->ex_init_cb_dma = 0;
5ff1d584
AV		 3795 ha->async_pd = NULL;
3796 ha->async_pd_dma = 0;
1da177e4
LT		 3797
3798 ha->s_dma_pool = NULL;
a9083016
GM		 3799 ha->dl_dma_pool = NULL;
3800 ha->fcp_cmnd_dma_pool = NULL;
1da177e4 3801
1da177e4
LT		 3802 ha->gid_list = NULL;
3803 ha->gid_list_dma = 0;
2d70c103
NB		 3804
3805 ha->tgt.atio_ring = NULL;
3806 ha->tgt.atio_dma = 0;
3807 ha->tgt.tgt_vp_map = NULL;
e315cd28 3808}
1da177e4 3809
e315cd28
AC		 3810struct scsi_qla_host *qla2x00_create_host(struct scsi_host_template *sht,
3811 struct qla_hw_data *ha)
3812{
3813 struct Scsi_Host *host;
3814 struct scsi_qla_host *vha = NULL;
854165f4 3815
e315cd28
AC		 3816 host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t));
3817 if (host == NULL) {
7c3df132
SK		 3818 ql_log_pci(ql_log_fatal, ha->pdev, 0x0107,
3819 "Failed to allocate host from the scsi layer, aborting.\n");
e315cd28
AC		 3820 goto fail;
3821 }
3822
3823 /* Clear our data area */
3824 vha = shost_priv(host);
3825 memset(vha, 0, sizeof(scsi_qla_host_t));
3826
3827 vha->host = host;
3828 vha->host_no = host->host_no;
3829 vha->hw = ha;
3830
3831 INIT_LIST_HEAD(&vha->vp_fcports);
3832 INIT_LIST_HEAD(&vha->work_list);
3833 INIT_LIST_HEAD(&vha->list);
3834
f999f4c1
AV		 3835 spin_lock_init(&vha->work_lock);
3836
e315cd28 3837 sprintf(vha->host_str, "%s_%ld", QLA2XXX_DRIVER_NAME, vha->host_no);
7c3df132
SK		 3838 ql_dbg(ql_dbg_init, vha, 0x0041,
3839 "Allocated the host=%p hw=%p vha=%p dev_name=%s",
3840 vha->host, vha->hw, vha,
3841 dev_name(&(ha->pdev->dev)));
3842
e315cd28
AC		 3843 return vha;
3844
3845fail:
3846 return vha;
1da177e4
LT		 3847}
3848
01ef66bb 3849static struct qla_work_evt *
f999f4c1 3850qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type)
0971de7f
AV		 3851{
3852 struct qla_work_evt *e;
feafb7b1
AE		 3853 uint8_t bail;
3854
3855 QLA_VHA_MARK_BUSY(vha, bail);
3856 if (bail)
3857 return NULL;
0971de7f 3858
f999f4c1 3859 e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC);
feafb7b1
AE		 3860 if (!e) {
3861 QLA_VHA_MARK_NOT_BUSY(vha);
0971de7f 3862 return NULL;
feafb7b1 3863 }
0971de7f
AV		 3864
3865 INIT_LIST_HEAD(&e->list);
3866 e->type = type;
3867 e->flags = QLA_EVT_FLAG_FREE;
3868 return e;
3869}
3870
01ef66bb 3871static int
f999f4c1 3872qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e)
0971de7f 3873{
f999f4c1 3874 unsigned long flags;
0971de7f 3875
f999f4c1 3876 spin_lock_irqsave(&vha->work_lock, flags);
e315cd28 3877 list_add_tail(&e->list, &vha->work_list);
f999f4c1 3878 spin_unlock_irqrestore(&vha->work_lock, flags);
e315cd28 3879 qla2xxx_wake_dpc(vha);
f999f4c1 3880
0971de7f
AV		 3881 return QLA_SUCCESS;
3882}
3883
3884int
e315cd28 3885qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code,
0971de7f
AV		 3886 u32 data)
3887{
3888 struct qla_work_evt *e;
3889
f999f4c1 3890 e = qla2x00_alloc_work(vha, QLA_EVT_AEN);
0971de7f
AV		 3891 if (!e)
3892 return QLA_FUNCTION_FAILED;
3893
3894 e->u.aen.code = code;
3895 e->u.aen.data = data;
f999f4c1 3896 return qla2x00_post_work(vha, e);
0971de7f
AV		 3897}
3898
8a659571
AV		 3899int
3900qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb)
3901{
3902 struct qla_work_evt *e;
3903
f999f4c1 3904 e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK);
8a659571
AV		 3905 if (!e)
3906 return QLA_FUNCTION_FAILED;
3907
3908 memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t));
f999f4c1 3909 return qla2x00_post_work(vha, e);
8a659571
AV		 3910}
3911
ac280b67
AV		 3912#define qla2x00_post_async_work(name, type) \
3913int qla2x00_post_async_##name##_work( \
3914 struct scsi_qla_host *vha, \
3915 fc_port_t *fcport, uint16_t *data) \
3916{ \
3917 struct qla_work_evt *e; \
3918 \
3919 e = qla2x00_alloc_work(vha, type); \
3920 if (!e) \
3921 return QLA_FUNCTION_FAILED; \
3922 \
3923 e->u.logio.fcport = fcport; \
3924 if (data) { \
3925 e->u.logio.data[0] = data[0]; \
3926 e->u.logio.data[1] = data[1]; \
3927 } \
3928 return qla2x00_post_work(vha, e); \
3929}
3930
3931qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN);
3932qla2x00_post_async_work(login_done, QLA_EVT_ASYNC_LOGIN_DONE);
3933qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT);
3934qla2x00_post_async_work(logout_done, QLA_EVT_ASYNC_LOGOUT_DONE);
5ff1d584
AV		 3935qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC);
3936qla2x00_post_async_work(adisc_done, QLA_EVT_ASYNC_ADISC_DONE);
ac280b67 3937
3420d36c
AV		 3938int
3939qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code)
3940{
3941 struct qla_work_evt *e;
3942
3943 e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT);
3944 if (!e)
3945 return QLA_FUNCTION_FAILED;
3946
3947 e->u.uevent.code = code;
3948 return qla2x00_post_work(vha, e);
3949}
3950
3951static void
3952qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code)
3953{
3954 char event_string[40];
3955 char *envp[] = { event_string, NULL };
3956
3957 switch (code) {
3958 case QLA_UEVENT_CODE_FW_DUMP:
3959 snprintf(event_string, sizeof(event_string), "FW_DUMP=%ld",
3960 vha->host_no);
3961 break;
3962 default:
3963 /* do nothing */
3964 break;
3965 }
3966 kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp);
3967}
3968
8ae6d9c7
GM		 3969int
3970qlafx00_post_aenfx_work(struct scsi_qla_host *vha, uint32_t evtcode,
3971 uint32_t *data, int cnt)
3972{
3973 struct qla_work_evt *e;
3974
3975 e = qla2x00_alloc_work(vha, QLA_EVT_AENFX);
3976 if (!e)
3977 return QLA_FUNCTION_FAILED;
3978
3979 e->u.aenfx.evtcode = evtcode;
3980 e->u.aenfx.count = cnt;
3981 memcpy(e->u.aenfx.mbx, data, sizeof(*data) * cnt);
3982 return qla2x00_post_work(vha, e);
3983}
3984
ac280b67 3985void
e315cd28 3986qla2x00_do_work(struct scsi_qla_host *vha)
0971de7f 3987{
f999f4c1
AV		 3988 struct qla_work_evt *e, *tmp;
3989 unsigned long flags;
3990 LIST_HEAD(work);
0971de7f 3991
f999f4c1
AV		 3992 spin_lock_irqsave(&vha->work_lock, flags);
3993 list_splice_init(&vha->work_list, &work);
3994 spin_unlock_irqrestore(&vha->work_lock, flags);
3995
3996 list_for_each_entry_safe(e, tmp, &work, list) {
0971de7f 3997 list_del_init(&e->list);
0971de7f
AV		 3998
3999 switch (e->type) {
4000 case QLA_EVT_AEN:
e315cd28 4001 fc_host_post_event(vha->host, fc_get_event_number(),
0971de7f
AV		 4002 e->u.aen.code, e->u.aen.data);
4003 break;
8a659571
AV		 4004 case QLA_EVT_IDC_ACK:
4005 qla81xx_idc_ack(vha, e->u.idc_ack.mb);
4006 break;
ac280b67
AV		 4007 case QLA_EVT_ASYNC_LOGIN:
4008 qla2x00_async_login(vha, e->u.logio.fcport,
4009 e->u.logio.data);
4010 break;
4011 case QLA_EVT_ASYNC_LOGIN_DONE:
4012 qla2x00_async_login_done(vha, e->u.logio.fcport,
4013 e->u.logio.data);
4014 break;
4015 case QLA_EVT_ASYNC_LOGOUT:
4016 qla2x00_async_logout(vha, e->u.logio.fcport);
4017 break;
4018 case QLA_EVT_ASYNC_LOGOUT_DONE:
4019 qla2x00_async_logout_done(vha, e->u.logio.fcport,
4020 e->u.logio.data);
4021 break;
5ff1d584
AV		 4022 case QLA_EVT_ASYNC_ADISC:
4023 qla2x00_async_adisc(vha, e->u.logio.fcport,
4024 e->u.logio.data);
4025 break;
4026 case QLA_EVT_ASYNC_ADISC_DONE:
4027 qla2x00_async_adisc_done(vha, e->u.logio.fcport,
4028 e->u.logio.data);
4029 break;
3420d36c
AV		 4030 case QLA_EVT_UEVENT:
4031 qla2x00_uevent_emit(vha, e->u.uevent.code);
4032 break;
8ae6d9c7
GM		 4033 case QLA_EVT_AENFX:
4034 qlafx00_process_aen(vha, e);
4035 break;
0971de7f
AV		 4036 }
4037 if (e->flags & QLA_EVT_FLAG_FREE)
4038 kfree(e);
feafb7b1
AE		 4039
4040 /* For each work completed decrement vha ref count */
4041 QLA_VHA_MARK_NOT_BUSY(vha);
e315cd28 4042 }
e315cd28 4043}
f999f4c1 4044
e315cd28
AC		 4045/* Relogins all the fcports of a vport
4046 * Context: dpc thread
4047 */
4048void qla2x00_relogin(struct scsi_qla_host *vha)
4049{
4050 fc_port_t *fcport;
c6b2fca8 4051 int status;
e315cd28
AC		 4052 uint16_t next_loopid = 0;
4053 struct qla_hw_data *ha = vha->hw;
ac280b67 4054 uint16_t data[2];
e315cd28
AC		 4055
4056 list_for_each_entry(fcport, &vha->vp_fcports, list) {
4057 /*
4058 * If the port is not ONLINE then try to login
4059 * to it if we haven't run out of retries.
4060 */
5ff1d584
AV		 4061 if (atomic_read(&fcport->state) != FCS_ONLINE &&
4062 fcport->login_retry && !(fcport->flags & FCF_ASYNC_SENT)) {
ac280b67 4063 fcport->login_retry--;
e315cd28 4064 if (fcport->flags & FCF_FABRIC_DEVICE) {
f08b7251 4065 if (fcport->flags & FCF_FCP2_DEVICE)
e315cd28
AC		 4066 ha->isp_ops->fabric_logout(vha,
4067 fcport->loop_id,
4068 fcport->d_id.b.domain,
4069 fcport->d_id.b.area,
4070 fcport->d_id.b.al_pa);
4071
03bcfb57
JC		 4072 if (fcport->loop_id == FC_NO_LOOP_ID) {
4073 fcport->loop_id = next_loopid =
4074 ha->min_external_loopid;
4075 status = qla2x00_find_new_loop_id(
4076 vha, fcport);
4077 if (status != QLA_SUCCESS) {
4078 /* Ran out of IDs to use */
4079 break;
4080 }
4081 }
4082
ac280b67 4083 if (IS_ALOGIO_CAPABLE(ha)) {
5ff1d584 4084 fcport->flags |= FCF_ASYNC_SENT;
ac280b67
AV		 4085 data[0] = 0;
4086 data[1] = QLA_LOGIO_LOGIN_RETRIED;
4087 status = qla2x00_post_async_login_work(
4088 vha, fcport, data);
4089 if (status == QLA_SUCCESS)
4090 continue;
4091 /* Attempt a retry. */
4092 status = 1;
aaf4d3e2 4093 } else {
ac280b67
AV		 4094 status = qla2x00_fabric_login(vha,
4095 fcport, &next_loopid);
aaf4d3e2
SK		 4096 if (status == QLA_SUCCESS) {
4097 int status2;
4098 uint8_t opts;
4099
4100 opts = 0;
4101 if (fcport->flags &
4102 FCF_FCP2_DEVICE)
4103 opts |= BIT_1;
03003960
SK		 4104 status2 =
4105 qla2x00_get_port_database(
4106 vha, fcport, opts);
aaf4d3e2
SK		 4107 if (status2 != QLA_SUCCESS)
4108 status = 1;
4109 }
4110 }
e315cd28
AC		 4111 } else
4112 status = qla2x00_local_device_login(vha,
4113 fcport);
4114
e315cd28
AC		 4115 if (status == QLA_SUCCESS) {
4116 fcport->old_loop_id = fcport->loop_id;
4117
7c3df132
SK		 4118 ql_dbg(ql_dbg_disc, vha, 0x2003,
4119 "Port login OK: logged in ID 0x%x.\n",
4120 fcport->loop_id);
e315cd28
AC		 4121
4122 qla2x00_update_fcport(vha, fcport);
4123
4124 } else if (status == 1) {
4125 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
4126 /* retry the login again */
7c3df132
SK		 4127 ql_dbg(ql_dbg_disc, vha, 0x2007,
4128 "Retrying %d login again loop_id 0x%x.\n",
4129 fcport->login_retry, fcport->loop_id);
e315cd28
AC		 4130 } else {
4131 fcport->login_retry = 0;
4132 }
4133
4134 if (fcport->login_retry == 0 && status != QLA_SUCCESS)
5f16b331 4135 qla2x00_clear_loop_id(fcport);
e315cd28
AC		 4136 }
4137 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
4138 break;
0971de7f 4139 }
0971de7f
AV		 4140}
4141
7d613ac6
SV		 4142/* Schedule work on any of the dpc-workqueues */
4143void
4144qla83xx_schedule_work(scsi_qla_host_t *base_vha, int work_code)
4145{
4146 struct qla_hw_data *ha = base_vha->hw;
4147
4148 switch (work_code) {
4149 case MBA_IDC_AEN: /* 0x8200 */
4150 if (ha->dpc_lp_wq)
4151 queue_work(ha->dpc_lp_wq, &ha->idc_aen);
4152 break;
4153
4154 case QLA83XX_NIC_CORE_RESET: /* 0x1 */
4155 if (!ha->flags.nic_core_reset_hdlr_active) {
4156 if (ha->dpc_hp_wq)
4157 queue_work(ha->dpc_hp_wq, &ha->nic_core_reset);
4158 } else
4159 ql_dbg(ql_dbg_p3p, base_vha, 0xb05e,
4160 "NIC Core reset is already active. Skip "
4161 "scheduling it again.\n");
4162 break;
4163 case QLA83XX_IDC_STATE_HANDLER: /* 0x2 */
4164 if (ha->dpc_hp_wq)
4165 queue_work(ha->dpc_hp_wq, &ha->idc_state_handler);
4166 break;
4167 case QLA83XX_NIC_CORE_UNRECOVERABLE: /* 0x3 */
4168 if (ha->dpc_hp_wq)
4169 queue_work(ha->dpc_hp_wq, &ha->nic_core_unrecoverable);
4170 break;
4171 default:
4172 ql_log(ql_log_warn, base_vha, 0xb05f,
4173 "Unknow work-code=0x%x.\n", work_code);
4174 }
4175
4176 return;
4177}
4178
4179/* Work: Perform NIC Core Unrecoverable state handling */
4180void
4181qla83xx_nic_core_unrecoverable_work(struct work_struct *work)
4182{
4183 struct qla_hw_data *ha =
2ad1b67c 4184 container_of(work, struct qla_hw_data, nic_core_unrecoverable);
7d613ac6
SV		 4185 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4186 uint32_t dev_state = 0;
4187
4188 qla83xx_idc_lock(base_vha, 0);
4189 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4190 qla83xx_reset_ownership(base_vha);
4191 if (ha->flags.nic_core_reset_owner) {
4192 ha->flags.nic_core_reset_owner = 0;
4193 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
4194 QLA8XXX_DEV_FAILED);
4195 ql_log(ql_log_info, base_vha, 0xb060, "HW State: FAILED.\n");
4196 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
4197 }
4198 qla83xx_idc_unlock(base_vha, 0);
4199}
4200
4201/* Work: Execute IDC state handler */
4202void
4203qla83xx_idc_state_handler_work(struct work_struct *work)
4204{
4205 struct qla_hw_data *ha =
2ad1b67c 4206 container_of(work, struct qla_hw_data, idc_state_handler);
7d613ac6
SV		 4207 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4208 uint32_t dev_state = 0;
4209
4210 qla83xx_idc_lock(base_vha, 0);
4211 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4212 if (dev_state == QLA8XXX_DEV_FAILED ||
4213 dev_state == QLA8XXX_DEV_NEED_QUIESCENT)
4214 qla83xx_idc_state_handler(base_vha);
4215 qla83xx_idc_unlock(base_vha, 0);
4216}
4217
fa492630 4218static int
7d613ac6
SV		 4219qla83xx_check_nic_core_fw_alive(scsi_qla_host_t *base_vha)
4220{
4221 int rval = QLA_SUCCESS;
4222 unsigned long heart_beat_wait = jiffies + (1 * HZ);
4223 uint32_t heart_beat_counter1, heart_beat_counter2;
4224
4225 do {
4226 if (time_after(jiffies, heart_beat_wait)) {
4227 ql_dbg(ql_dbg_p3p, base_vha, 0xb07c,
4228 "Nic Core f/w is not alive.\n");
4229 rval = QLA_FUNCTION_FAILED;
4230 break;
4231 }
4232
4233 qla83xx_idc_lock(base_vha, 0);
4234 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
4235 &heart_beat_counter1);
4236 qla83xx_idc_unlock(base_vha, 0);
4237 msleep(100);
4238 qla83xx_idc_lock(base_vha, 0);
4239 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
4240 &heart_beat_counter2);
4241 qla83xx_idc_unlock(base_vha, 0);
4242 } while (heart_beat_counter1 == heart_beat_counter2);
4243
4244 return rval;
4245}
4246
4247/* Work: Perform NIC Core Reset handling */
4248void
4249qla83xx_nic_core_reset_work(struct work_struct *work)
4250{
4251 struct qla_hw_data *ha =
4252 container_of(work, struct qla_hw_data, nic_core_reset);
4253 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4254 uint32_t dev_state = 0;
4255
81178772
SK		 4256 if (IS_QLA2031(ha)) {
4257 if (qla2xxx_mctp_dump(base_vha) != QLA_SUCCESS)
4258 ql_log(ql_log_warn, base_vha, 0xb081,
4259 "Failed to dump mctp\n");
4260 return;
4261 }
4262
7d613ac6
SV		 4263 if (!ha->flags.nic_core_reset_hdlr_active) {
4264 if (qla83xx_check_nic_core_fw_alive(base_vha) == QLA_SUCCESS) {
4265 qla83xx_idc_lock(base_vha, 0);
4266 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE,
4267 &dev_state);
4268 qla83xx_idc_unlock(base_vha, 0);
4269 if (dev_state != QLA8XXX_DEV_NEED_RESET) {
4270 ql_dbg(ql_dbg_p3p, base_vha, 0xb07a,
4271 "Nic Core f/w is alive.\n");
4272 return;
4273 }
4274 }
4275
4276 ha->flags.nic_core_reset_hdlr_active = 1;
4277 if (qla83xx_nic_core_reset(base_vha)) {
4278 /* NIC Core reset failed. */
4279 ql_dbg(ql_dbg_p3p, base_vha, 0xb061,
4280 "NIC Core reset failed.\n");
4281 }
4282 ha->flags.nic_core_reset_hdlr_active = 0;
4283 }
4284}
4285
4286/* Work: Handle 8200 IDC aens */
4287void
4288qla83xx_service_idc_aen(struct work_struct *work)
4289{
4290 struct qla_hw_data *ha =
4291 container_of(work, struct qla_hw_data, idc_aen);
4292 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4293 uint32_t dev_state, idc_control;
4294
4295 qla83xx_idc_lock(base_vha, 0);
4296 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4297 qla83xx_rd_reg(base_vha, QLA83XX_IDC_CONTROL, &idc_control);
4298 qla83xx_idc_unlock(base_vha, 0);
4299 if (dev_state == QLA8XXX_DEV_NEED_RESET) {
4300 if (idc_control & QLA83XX_IDC_GRACEFUL_RESET) {
4301 ql_dbg(ql_dbg_p3p, base_vha, 0xb062,
4302 "Application requested NIC Core Reset.\n");
4303 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
4304 } else if (qla83xx_check_nic_core_fw_alive(base_vha) ==
4305 QLA_SUCCESS) {
4306 ql_dbg(ql_dbg_p3p, base_vha, 0xb07b,
4307 "Other protocol driver requested NIC Core Reset.\n");
4308 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
4309 }
4310 } else if (dev_state == QLA8XXX_DEV_FAILED ||
4311 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) {
4312 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
4313 }
4314}
4315
4316static void
4317qla83xx_wait_logic(void)
4318{
4319 int i;
4320
4321 /* Yield CPU */
4322 if (!in_interrupt()) {
4323 /*
4324 * Wait about 200ms before retrying again.
4325 * This controls the number of retries for single
4326 * lock operation.
4327 */
4328 msleep(100);
4329 schedule();
4330 } else {
4331 for (i = 0; i < 20; i++)
4332 cpu_relax(); /* This a nop instr on i386 */
4333 }
4334}
4335
fa492630 4336static int
7d613ac6
SV		 4337qla83xx_force_lock_recovery(scsi_qla_host_t *base_vha)
4338{
4339 int rval;
4340 uint32_t data;
4341 uint32_t idc_lck_rcvry_stage_mask = 0x3;
4342 uint32_t idc_lck_rcvry_owner_mask = 0x3c;
4343 struct qla_hw_data *ha = base_vha->hw;
6c315553
SK		 4344 ql_dbg(ql_dbg_p3p, base_vha, 0xb086,
4345 "Trying force recovery of the IDC lock.\n");
7d613ac6
SV		 4346
4347 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, &data);
4348 if (rval)
4349 return rval;
4350
4351 if ((data & idc_lck_rcvry_stage_mask) > 0) {
4352 return QLA_SUCCESS;
4353 } else {
4354 data = (IDC_LOCK_RECOVERY_STAGE1) | (ha->portnum << 2);
4355 rval = qla83xx_wr_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
4356 data);
4357 if (rval)
4358 return rval;
4359
4360 msleep(200);
4361
4362 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
4363 &data);
4364 if (rval)
4365 return rval;
4366
4367 if (((data & idc_lck_rcvry_owner_mask) >> 2) == ha->portnum) {
4368 data &= (IDC_LOCK_RECOVERY_STAGE2 |
4369 ~(idc_lck_rcvry_stage_mask));
4370 rval = qla83xx_wr_reg(base_vha,
4371 QLA83XX_IDC_LOCK_RECOVERY, data);
4372 if (rval)
4373 return rval;
4374
4375 /* Forcefully perform IDC UnLock */
4376 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK,
4377 &data);
4378 if (rval)
4379 return rval;
4380 /* Clear lock-id by setting 0xff */
4381 rval = qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
4382 0xff);
4383 if (rval)
4384 return rval;
4385 /* Clear lock-recovery by setting 0x0 */
4386 rval = qla83xx_wr_reg(base_vha,
4387 QLA83XX_IDC_LOCK_RECOVERY, 0x0);
4388 if (rval)
4389 return rval;
4390 } else
4391 return QLA_SUCCESS;
4392 }
4393
4394 return rval;
4395}
4396
fa492630 4397static int
7d613ac6
SV		 4398qla83xx_idc_lock_recovery(scsi_qla_host_t *base_vha)
4399{
4400 int rval = QLA_SUCCESS;
4401 uint32_t o_drv_lockid, n_drv_lockid;
4402 unsigned long lock_recovery_timeout;
4403
4404 lock_recovery_timeout = jiffies + QLA83XX_MAX_LOCK_RECOVERY_WAIT;
4405retry_lockid:
4406 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &o_drv_lockid);
4407 if (rval)
4408 goto exit;
4409
4410 /* MAX wait time before forcing IDC Lock recovery = 2 secs */
4411 if (time_after_eq(jiffies, lock_recovery_timeout)) {
4412 if (qla83xx_force_lock_recovery(base_vha) == QLA_SUCCESS)
4413 return QLA_SUCCESS;
4414 else
4415 return QLA_FUNCTION_FAILED;
4416 }
4417
4418 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &n_drv_lockid);
4419 if (rval)
4420 goto exit;
4421
4422 if (o_drv_lockid == n_drv_lockid) {
4423 qla83xx_wait_logic();
4424 goto retry_lockid;
4425 } else
4426 return QLA_SUCCESS;
4427
4428exit:
4429 return rval;
4430}
4431
4432void
4433qla83xx_idc_lock(scsi_qla_host_t *base_vha, uint16_t requester_id)
4434{
4435 uint16_t options = (requester_id << 15) | BIT_6;
4436 uint32_t data;
6c315553 4437 uint32_t lock_owner;
7d613ac6
SV		 4438 struct qla_hw_data *ha = base_vha->hw;
4439
4440 /* IDC-lock implementation using driver-lock/lock-id remote registers */
4441retry_lock:
4442 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCK, &data)
4443 == QLA_SUCCESS) {
4444 if (data) {
4445 /* Setting lock-id to our function-number */
4446 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
4447 ha->portnum);
4448 } else {
6c315553
SK		 4449 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID,
4450 &lock_owner);
7d613ac6 4451 ql_dbg(ql_dbg_p3p, base_vha, 0xb063,
6c315553
SK		 4452 "Failed to acquire IDC lock, acquired by %d, "
4453 "retrying...\n", lock_owner);
7d613ac6
SV		 4454
4455 /* Retry/Perform IDC-Lock recovery */
4456 if (qla83xx_idc_lock_recovery(base_vha)
4457 == QLA_SUCCESS) {
4458 qla83xx_wait_logic();
4459 goto retry_lock;
4460 } else
4461 ql_log(ql_log_warn, base_vha, 0xb075,
4462 "IDC Lock recovery FAILED.\n");
4463 }
4464
4465 }
4466
4467 return;
4468
4469 /* XXX: IDC-lock implementation using access-control mbx */
4470retry_lock2:
4471 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
4472 ql_dbg(ql_dbg_p3p, base_vha, 0xb072,
4473 "Failed to acquire IDC lock. retrying...\n");
4474 /* Retry/Perform IDC-Lock recovery */
4475 if (qla83xx_idc_lock_recovery(base_vha) == QLA_SUCCESS) {
4476 qla83xx_wait_logic();
4477 goto retry_lock2;
4478 } else
4479 ql_log(ql_log_warn, base_vha, 0xb076,
4480 "IDC Lock recovery FAILED.\n");
4481 }
4482
4483 return;
4484}
4485
4486void
4487qla83xx_idc_unlock(scsi_qla_host_t *base_vha, uint16_t requester_id)
4488{
4489 uint16_t options = (requester_id << 15) | BIT_7, retry;
4490 uint32_t data;
4491 struct qla_hw_data *ha = base_vha->hw;
4492
4493 /* IDC-unlock implementation using driver-unlock/lock-id
4494 * remote registers
4495 */
4496 retry = 0;
4497retry_unlock:
4498 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &data)
4499 == QLA_SUCCESS) {
4500 if (data == ha->portnum) {
4501 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, &data);
4502 /* Clearing lock-id by setting 0xff */
4503 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 0xff);
4504 } else if (retry < 10) {
4505 /* SV: XXX: IDC unlock retrying needed here? */
4506
4507 /* Retry for IDC-unlock */
4508 qla83xx_wait_logic();
4509 retry++;
4510 ql_dbg(ql_dbg_p3p, base_vha, 0xb064,
4511 "Failed to release IDC lock, retyring=%d\n", retry);
4512 goto retry_unlock;
4513 }
4514 } else if (retry < 10) {
4515 /* Retry for IDC-unlock */
4516 qla83xx_wait_logic();
4517 retry++;
4518 ql_dbg(ql_dbg_p3p, base_vha, 0xb065,
4519 "Failed to read drv-lockid, retyring=%d\n", retry);
4520 goto retry_unlock;
4521 }
4522
4523 return;
4524
4525 /* XXX: IDC-unlock implementation using access-control mbx */
4526 retry = 0;
4527retry_unlock2:
4528 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
4529 if (retry < 10) {
4530 /* Retry for IDC-unlock */
4531 qla83xx_wait_logic();
4532 retry++;
4533 ql_dbg(ql_dbg_p3p, base_vha, 0xb066,
4534 "Failed to release IDC lock, retyring=%d\n", retry);
4535 goto retry_unlock2;
4536 }
4537 }
4538
4539 return;
4540}
4541
4542int
4543__qla83xx_set_drv_presence(scsi_qla_host_t *vha)
4544{
4545 int rval = QLA_SUCCESS;
4546 struct qla_hw_data *ha = vha->hw;
4547 uint32_t drv_presence;
4548
4549 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
4550 if (rval == QLA_SUCCESS) {
4551 drv_presence |= (1 << ha->portnum);
4552 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
4553 drv_presence);
4554 }
4555
4556 return rval;
4557}
4558
4559int
4560qla83xx_set_drv_presence(scsi_qla_host_t *vha)
4561{
4562 int rval = QLA_SUCCESS;
4563
4564 qla83xx_idc_lock(vha, 0);
4565 rval = __qla83xx_set_drv_presence(vha);
4566 qla83xx_idc_unlock(vha, 0);
4567
4568 return rval;
4569}
4570
4571int
4572__qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
4573{
4574 int rval = QLA_SUCCESS;
4575 struct qla_hw_data *ha = vha->hw;
4576 uint32_t drv_presence;
4577
4578 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
4579 if (rval == QLA_SUCCESS) {
4580 drv_presence &= ~(1 << ha->portnum);
4581 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
4582 drv_presence);
4583 }
4584
4585 return rval;
4586}
4587
4588int
4589qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
4590{
4591 int rval = QLA_SUCCESS;
4592
4593 qla83xx_idc_lock(vha, 0);
4594 rval = __qla83xx_clear_drv_presence(vha);
4595 qla83xx_idc_unlock(vha, 0);
4596
4597 return rval;
4598}
4599
fa492630 4600static void
7d613ac6
SV		 4601qla83xx_need_reset_handler(scsi_qla_host_t *vha)
4602{
4603 struct qla_hw_data *ha = vha->hw;
4604 uint32_t drv_ack, drv_presence;
4605 unsigned long ack_timeout;
4606
4607 /* Wait for IDC ACK from all functions (DRV-ACK == DRV-PRESENCE) */
4608 ack_timeout = jiffies + (ha->fcoe_reset_timeout * HZ);
4609 while (1) {
4610 qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
4611 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
807fb6d8 4612 if ((drv_ack & drv_presence) == drv_presence)
7d613ac6
SV		 4613 break;
4614
4615 if (time_after_eq(jiffies, ack_timeout)) {
4616 ql_log(ql_log_warn, vha, 0xb067,
4617 "RESET ACK TIMEOUT! drv_presence=0x%x "
4618 "drv_ack=0x%x\n", drv_presence, drv_ack);
4619 /*
4620 * The function(s) which did not ack in time are forced
4621 * to withdraw any further participation in the IDC
4622 * reset.
4623 */
4624 if (drv_ack != drv_presence)
4625 qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
4626 drv_ack);
4627 break;
4628 }
4629
4630 qla83xx_idc_unlock(vha, 0);
4631 msleep(1000);
4632 qla83xx_idc_lock(vha, 0);
4633 }
4634
4635 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_COLD);
4636 ql_log(ql_log_info, vha, 0xb068, "HW State: COLD/RE-INIT.\n");
4637}
4638
fa492630 4639static int
7d613ac6
SV		 4640qla83xx_device_bootstrap(scsi_qla_host_t *vha)
4641{
4642 int rval = QLA_SUCCESS;
4643 uint32_t idc_control;
4644
4645 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_INITIALIZING);
4646 ql_log(ql_log_info, vha, 0xb069, "HW State: INITIALIZING.\n");
4647
4648 /* Clearing IDC-Control Graceful-Reset Bit before resetting f/w */
4649 __qla83xx_get_idc_control(vha, &idc_control);
4650 idc_control &= ~QLA83XX_IDC_GRACEFUL_RESET;
4651 __qla83xx_set_idc_control(vha, 0);
4652
4653 qla83xx_idc_unlock(vha, 0);
4654 rval = qla83xx_restart_nic_firmware(vha);
4655 qla83xx_idc_lock(vha, 0);
4656
4657 if (rval != QLA_SUCCESS) {
4658 ql_log(ql_log_fatal, vha, 0xb06a,
4659 "Failed to restart NIC f/w.\n");
4660 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_FAILED);
4661 ql_log(ql_log_info, vha, 0xb06b, "HW State: FAILED.\n");
4662 } else {
4663 ql_dbg(ql_dbg_p3p, vha, 0xb06c,
4664 "Success in restarting nic f/w.\n");
4665 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_READY);
4666 ql_log(ql_log_info, vha, 0xb06d, "HW State: READY.\n");
4667 }
4668
4669 return rval;
4670}
4671
4672/* Assumes idc_lock always held on entry */
4673int
4674qla83xx_idc_state_handler(scsi_qla_host_t *base_vha)
4675{
4676 struct qla_hw_data *ha = base_vha->hw;
4677 int rval = QLA_SUCCESS;
4678 unsigned long dev_init_timeout;
4679 uint32_t dev_state;
4680
4681 /* Wait for MAX-INIT-TIMEOUT for the device to go ready */
4682 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ);
4683
4684 while (1) {
4685
4686 if (time_after_eq(jiffies, dev_init_timeout)) {
4687 ql_log(ql_log_warn, base_vha, 0xb06e,
4688 "Initialization TIMEOUT!\n");
4689 /* Init timeout. Disable further NIC Core
4690 * communication.
4691 */
4692 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
4693 QLA8XXX_DEV_FAILED);
4694 ql_log(ql_log_info, base_vha, 0xb06f,
4695 "HW State: FAILED.\n");
4696 }
4697
4698 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4699 switch (dev_state) {
4700 case QLA8XXX_DEV_READY:
4701 if (ha->flags.nic_core_reset_owner)
4702 qla83xx_idc_audit(base_vha,
4703 IDC_AUDIT_COMPLETION);
4704 ha->flags.nic_core_reset_owner = 0;
4705 ql_dbg(ql_dbg_p3p, base_vha, 0xb070,
4706 "Reset_owner reset by 0x%x.\n",
4707 ha->portnum);
4708 goto exit;
4709 case QLA8XXX_DEV_COLD:
4710 if (ha->flags.nic_core_reset_owner)
4711 rval = qla83xx_device_bootstrap(base_vha);
4712 else {
4713 /* Wait for AEN to change device-state */
4714 qla83xx_idc_unlock(base_vha, 0);
4715 msleep(1000);
4716 qla83xx_idc_lock(base_vha, 0);
4717 }
4718 break;
4719 case QLA8XXX_DEV_INITIALIZING:
4720 /* Wait for AEN to change device-state */
4721 qla83xx_idc_unlock(base_vha, 0);
4722 msleep(1000);
4723 qla83xx_idc_lock(base_vha, 0);
4724 break;
4725 case QLA8XXX_DEV_NEED_RESET:
4726 if (!ql2xdontresethba && ha->flags.nic_core_reset_owner)
4727 qla83xx_need_reset_handler(base_vha);
4728 else {
4729 /* Wait for AEN to change device-state */
4730 qla83xx_idc_unlock(base_vha, 0);
4731 msleep(1000);
4732 qla83xx_idc_lock(base_vha, 0);
4733 }
4734 /* reset timeout value after need reset handler */
4735 dev_init_timeout = jiffies +
4736 (ha->fcoe_dev_init_timeout * HZ);
4737 break;
4738 case QLA8XXX_DEV_NEED_QUIESCENT:
4739 /* XXX: DEBUG for now */
4740 qla83xx_idc_unlock(base_vha, 0);
4741 msleep(1000);
4742 qla83xx_idc_lock(base_vha, 0);
4743 break;
4744 case QLA8XXX_DEV_QUIESCENT:
4745 /* XXX: DEBUG for now */
4746 if (ha->flags.quiesce_owner)
4747 goto exit;
4748
4749 qla83xx_idc_unlock(base_vha, 0);
4750 msleep(1000);
4751 qla83xx_idc_lock(base_vha, 0);
4752 dev_init_timeout = jiffies +
4753 (ha->fcoe_dev_init_timeout * HZ);
4754 break;
4755 case QLA8XXX_DEV_FAILED:
4756 if (ha->flags.nic_core_reset_owner)
4757 qla83xx_idc_audit(base_vha,
4758 IDC_AUDIT_COMPLETION);
4759 ha->flags.nic_core_reset_owner = 0;
4760 __qla83xx_clear_drv_presence(base_vha);
4761 qla83xx_idc_unlock(base_vha, 0);
4762 qla8xxx_dev_failed_handler(base_vha);
4763 rval = QLA_FUNCTION_FAILED;
4764 qla83xx_idc_lock(base_vha, 0);
4765 goto exit;
4766 case QLA8XXX_BAD_VALUE:
4767 qla83xx_idc_unlock(base_vha, 0);
4768 msleep(1000);
4769 qla83xx_idc_lock(base_vha, 0);
4770 break;
4771 default:
4772 ql_log(ql_log_warn, base_vha, 0xb071,
4773 "Unknow Device State: %x.\n", dev_state);
4774 qla83xx_idc_unlock(base_vha, 0);
4775 qla8xxx_dev_failed_handler(base_vha);
4776 rval = QLA_FUNCTION_FAILED;
4777 qla83xx_idc_lock(base_vha, 0);
4778 goto exit;
4779 }
4780 }
4781
4782exit:
4783 return rval;
4784}
4785
f3ddac19
CD		 4786void
4787qla2x00_disable_board_on_pci_error(struct work_struct *work)
4788{
4789 struct qla_hw_data *ha = container_of(work, struct qla_hw_data,
4790 board_disable);
4791 struct pci_dev *pdev = ha->pdev;
4792 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4793
4794 ql_log(ql_log_warn, base_vha, 0x015b,
4795 "Disabling adapter.\n");
4796
4797 set_bit(UNLOADING, &base_vha->dpc_flags);
4798
4799 qla2x00_delete_all_vps(ha, base_vha);
4800
4801 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
4802
4803 qla2x00_dfs_remove(base_vha);
4804
4805 qla84xx_put_chip(base_vha);
4806
4807 if (base_vha->timer_active)
4808 qla2x00_stop_timer(base_vha);
4809
4810 base_vha->flags.online = 0;
4811
4812 qla2x00_destroy_deferred_work(ha);
4813
4814 /*
4815 * Do not try to stop beacon blink as it will issue a mailbox
4816 * command.
4817 */
4818 qla2x00_free_sysfs_attr(base_vha, false);
4819
4820 fc_remove_host(base_vha->host);
4821
4822 scsi_remove_host(base_vha->host);
4823
4824 base_vha->flags.init_done = 0;
4825 qla25xx_delete_queues(base_vha);
4826 qla2x00_free_irqs(base_vha);
4827 qla2x00_free_fcports(base_vha);
4828 qla2x00_mem_free(ha);
4829 qla82xx_md_free(base_vha);
4830 qla2x00_free_queues(ha);
4831
f3ddac19
CD		 4832 qla2x00_unmap_iobases(ha);
4833
4834 pci_release_selected_regions(ha->pdev, ha->bars);
f3ddac19
CD		 4835 pci_disable_pcie_error_reporting(pdev);
4836 pci_disable_device(pdev);
f3ddac19 4837
beb9e315
JL		 4838 /*
4839 * Let qla2x00_remove_one cleanup qla_hw_data on device removal.
4840 */
f3ddac19
CD		 4841}
4842
1da177e4
LT		 4843/**************************************************************************
4844* qla2x00_do_dpc
4845* This kernel thread is a task that is schedule by the interrupt handler
4846* to perform the background processing for interrupts.
4847*
4848* Notes:
4849* This task always run in the context of a kernel thread. It
4850* is kick-off by the driver's detect code and starts up
4851* up one per adapter. It immediately goes to sleep and waits for
4852* some fibre event. When either the interrupt handler or
4853* the timer routine detects a event it will one of the task
4854* bits then wake us up.
4855**************************************************************************/
4856static int
4857qla2x00_do_dpc(void *data)
4858{
2c3dfe3f 4859 int rval;
e315cd28
AC		 4860 scsi_qla_host_t *base_vha;
4861 struct qla_hw_data *ha;
1da177e4 4862
e315cd28
AC		 4863 ha = (struct qla_hw_data *)data;
4864 base_vha = pci_get_drvdata(ha->pdev);
1da177e4 4865
8698a745 4866 set_user_nice(current, MIN_NICE);
1da177e4 4867
563585ec 4868 set_current_state(TASK_INTERRUPTIBLE);
39a11240 4869 while (!kthread_should_stop()) {
7c3df132
SK		 4870 ql_dbg(ql_dbg_dpc, base_vha, 0x4000,
4871 "DPC handler sleeping.\n");
1da177e4 4872
39a11240
CH		 4873 schedule();
4874 __set_current_state(TASK_RUNNING);
1da177e4 4875
c142caf0
AV		 4876 if (!base_vha->flags.init_done || ha->flags.mbox_busy)
4877 goto end_loop;
1da177e4 4878
85880801 4879 if (ha->flags.eeh_busy) {
7c3df132
SK		 4880 ql_dbg(ql_dbg_dpc, base_vha, 0x4003,
4881 "eeh_busy=%d.\n", ha->flags.eeh_busy);
c142caf0 4882 goto end_loop;
85880801
AV		 4883 }
4884
1da177e4
LT		 4885 ha->dpc_active = 1;
4886
5f28d2d7
SK		 4887 ql_dbg(ql_dbg_dpc + ql_dbg_verbose, base_vha, 0x4001,
4888 "DPC handler waking up, dpc_flags=0x%lx.\n",
4889 base_vha->dpc_flags);
1da177e4 4890
e315cd28 4891 qla2x00_do_work(base_vha);
0971de7f 4892
7ec0effd
AD		 4893 if (IS_P3P_TYPE(ha)) {
4894 if (IS_QLA8044(ha)) {
4895 if (test_and_clear_bit(ISP_UNRECOVERABLE,
4896 &base_vha->dpc_flags)) {
4897 qla8044_idc_lock(ha);
4898 qla8044_wr_direct(base_vha,
4899 QLA8044_CRB_DEV_STATE_INDEX,
4900 QLA8XXX_DEV_FAILED);
4901 qla8044_idc_unlock(ha);
4902 ql_log(ql_log_info, base_vha, 0x4004,
4903 "HW State: FAILED.\n");
4904 qla8044_device_state_handler(base_vha);
4905 continue;
4906 }
4907
4908 } else {
4909 if (test_and_clear_bit(ISP_UNRECOVERABLE,
4910 &base_vha->dpc_flags)) {
4911 qla82xx_idc_lock(ha);
4912 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
4913 QLA8XXX_DEV_FAILED);
4914 qla82xx_idc_unlock(ha);
4915 ql_log(ql_log_info, base_vha, 0x0151,
4916 "HW State: FAILED.\n");
4917 qla82xx_device_state_handler(base_vha);
4918 continue;
4919 }
a9083016
GM		 4920 }
4921
4922 if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED,
4923 &base_vha->dpc_flags)) {
4924
7c3df132
SK		 4925 ql_dbg(ql_dbg_dpc, base_vha, 0x4005,
4926 "FCoE context reset scheduled.\n");
a9083016
GM		 4927 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
4928 &base_vha->dpc_flags))) {
4929 if (qla82xx_fcoe_ctx_reset(base_vha)) {
4930 /* FCoE-ctx reset failed.
4931 * Escalate to chip-reset
4932 */
4933 set_bit(ISP_ABORT_NEEDED,
4934 &base_vha->dpc_flags);
4935 }
4936 clear_bit(ABORT_ISP_ACTIVE,
4937 &base_vha->dpc_flags);
4938 }
4939
7c3df132
SK		 4940 ql_dbg(ql_dbg_dpc, base_vha, 0x4006,
4941 "FCoE context reset end.\n");
a9083016 4942 }
8ae6d9c7
GM		 4943 } else if (IS_QLAFX00(ha)) {
4944 if (test_and_clear_bit(ISP_UNRECOVERABLE,
4945 &base_vha->dpc_flags)) {
4946 ql_dbg(ql_dbg_dpc, base_vha, 0x4020,
4947 "Firmware Reset Recovery\n");
4948 if (qlafx00_reset_initialize(base_vha)) {
4949 /* Failed. Abort isp later. */
4950 if (!test_bit(UNLOADING,
f92f82d6 4951 &base_vha->dpc_flags)) {
8ae6d9c7
GM		 4952 set_bit(ISP_UNRECOVERABLE,
4953 &base_vha->dpc_flags);
4954 ql_dbg(ql_dbg_dpc, base_vha,
4955 0x4021,
4956 "Reset Recovery Failed\n");
f92f82d6 4957 }
8ae6d9c7
GM		 4958 }
4959 }
4960
4961 if (test_and_clear_bit(FX00_TARGET_SCAN,
4962 &base_vha->dpc_flags)) {
4963 ql_dbg(ql_dbg_dpc, base_vha, 0x4022,
4964 "ISPFx00 Target Scan scheduled\n");
4965 if (qlafx00_rescan_isp(base_vha)) {
4966 if (!test_bit(UNLOADING,
4967 &base_vha->dpc_flags))
4968 set_bit(ISP_UNRECOVERABLE,
4969 &base_vha->dpc_flags);
4970 ql_dbg(ql_dbg_dpc, base_vha, 0x401e,
4971 "ISPFx00 Target Scan Failed\n");
4972 }
4973 ql_dbg(ql_dbg_dpc, base_vha, 0x401f,
4974 "ISPFx00 Target Scan End\n");
4975 }
e8f5e95d
AB		 4976 if (test_and_clear_bit(FX00_HOST_INFO_RESEND,
4977 &base_vha->dpc_flags)) {
4978 ql_dbg(ql_dbg_dpc, base_vha, 0x4023,
4979 "ISPFx00 Host Info resend scheduled\n");
4980 qlafx00_fx_disc(base_vha,
4981 &base_vha->hw->mr.fcport,
4982 FXDISC_REG_HOST_INFO);
4983 }
a9083016
GM		 4984 }
4985
e315cd28
AC		 4986 if (test_and_clear_bit(ISP_ABORT_NEEDED,
4987 &base_vha->dpc_flags)) {
1da177e4 4988
7c3df132
SK		 4989 ql_dbg(ql_dbg_dpc, base_vha, 0x4007,
4990 "ISP abort scheduled.\n");
1da177e4 4991 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
e315cd28 4992 &base_vha->dpc_flags))) {
1da177e4 4993
a9083016 4994 if (ha->isp_ops->abort_isp(base_vha)) {
1da177e4
LT		 4995 /* failed. retry later */
4996 set_bit(ISP_ABORT_NEEDED,
e315cd28 4997 &base_vha->dpc_flags);
99363ef8 4998 }
e315cd28
AC		 4999 clear_bit(ABORT_ISP_ACTIVE,
5000 &base_vha->dpc_flags);
99363ef8
SJ		 5001 }
5002
7c3df132
SK		 5003 ql_dbg(ql_dbg_dpc, base_vha, 0x4008,
5004 "ISP abort end.\n");
1da177e4
LT		 5005 }
5006
a394aac8
DJ		 5007 if (test_and_clear_bit(FCPORT_UPDATE_NEEDED,
5008 &base_vha->dpc_flags)) {
e315cd28 5009 qla2x00_update_fcports(base_vha);
c9c5ced9 5010 }
d97994dc 5011
2d70c103
NB		 5012 if (test_bit(SCR_PENDING, &base_vha->dpc_flags)) {
5013 int ret;
5014 ret = qla2x00_send_change_request(base_vha, 0x3, 0);
5015 if (ret != QLA_SUCCESS)
5016 ql_log(ql_log_warn, base_vha, 0x121,
5017 "Failed to enable receiving of RSCN "
5018 "requests: 0x%x.\n", ret);
5019 clear_bit(SCR_PENDING, &base_vha->dpc_flags);
5020 }
5021
8ae6d9c7
GM		 5022 if (IS_QLAFX00(ha))
5023 goto loop_resync_check;
5024
579d12b5 5025 if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) {
7c3df132
SK		 5026 ql_dbg(ql_dbg_dpc, base_vha, 0x4009,
5027 "Quiescence mode scheduled.\n");
7ec0effd
AD		 5028 if (IS_P3P_TYPE(ha)) {
5029 if (IS_QLA82XX(ha))
5030 qla82xx_device_state_handler(base_vha);
5031 if (IS_QLA8044(ha))
5032 qla8044_device_state_handler(base_vha);
8fcd6b8b
CD		 5033 clear_bit(ISP_QUIESCE_NEEDED,
5034 &base_vha->dpc_flags);
5035 if (!ha->flags.quiesce_owner) {
5036 qla2x00_perform_loop_resync(base_vha);
7ec0effd
AD		 5037 if (IS_QLA82XX(ha)) {
5038 qla82xx_idc_lock(ha);
5039 qla82xx_clear_qsnt_ready(
5040 base_vha);
5041 qla82xx_idc_unlock(ha);
5042 } else if (IS_QLA8044(ha)) {
5043 qla8044_idc_lock(ha);
5044 qla8044_clear_qsnt_ready(
5045 base_vha);
5046 qla8044_idc_unlock(ha);
5047 }
8fcd6b8b
CD		 5048 }
5049 } else {
5050 clear_bit(ISP_QUIESCE_NEEDED,
5051 &base_vha->dpc_flags);
5052 qla2x00_quiesce_io(base_vha);
579d12b5 5053 }
7c3df132
SK		 5054 ql_dbg(ql_dbg_dpc, base_vha, 0x400a,
5055 "Quiescence mode end.\n");
579d12b5
SK		 5056 }
5057
e315cd28 5058 if (test_and_clear_bit(RESET_MARKER_NEEDED,
8ae6d9c7 5059 &base_vha->dpc_flags) &&
e315cd28 5060 (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) {
1da177e4 5061
7c3df132
SK		 5062 ql_dbg(ql_dbg_dpc, base_vha, 0x400b,
5063 "Reset marker scheduled.\n");
e315cd28
AC		 5064 qla2x00_rst_aen(base_vha);
5065 clear_bit(RESET_ACTIVE, &base_vha->dpc_flags);
7c3df132
SK		 5066 ql_dbg(ql_dbg_dpc, base_vha, 0x400c,
5067 "Reset marker end.\n");
1da177e4
LT		 5068 }
5069
5070 /* Retry each device up to login retry count */
e315cd28
AC		 5071 if ((test_and_clear_bit(RELOGIN_NEEDED,
5072 &base_vha->dpc_flags)) &&
5073 !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) &&
5074 atomic_read(&base_vha->loop_state) != LOOP_DOWN) {
1da177e4 5075
7c3df132
SK		 5076 ql_dbg(ql_dbg_dpc, base_vha, 0x400d,
5077 "Relogin scheduled.\n");
e315cd28 5078 qla2x00_relogin(base_vha);
7c3df132
SK		 5079 ql_dbg(ql_dbg_dpc, base_vha, 0x400e,
5080 "Relogin end.\n");
1da177e4 5081 }
8ae6d9c7 5082loop_resync_check:
e315cd28 5083 if (test_and_clear_bit(LOOP_RESYNC_NEEDED,
8ae6d9c7 5084 &base_vha->dpc_flags)) {
1da177e4 5085
7c3df132
SK		 5086 ql_dbg(ql_dbg_dpc, base_vha, 0x400f,
5087 "Loop resync scheduled.\n");
1da177e4
LT		 5088
5089 if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE,
e315cd28 5090 &base_vha->dpc_flags))) {
1da177e4 5091
e315cd28 5092 rval = qla2x00_loop_resync(base_vha);
1da177e4 5093
e315cd28
AC		 5094 clear_bit(LOOP_RESYNC_ACTIVE,
5095 &base_vha->dpc_flags);
1da177e4
LT		 5096 }
5097
7c3df132
SK		 5098 ql_dbg(ql_dbg_dpc, base_vha, 0x4010,
5099 "Loop resync end.\n");
1da177e4
LT		 5100 }
5101
8ae6d9c7
GM		 5102 if (IS_QLAFX00(ha))
5103 goto intr_on_check;
5104
e315cd28
AC		 5105 if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) &&
5106 atomic_read(&base_vha->loop_state) == LOOP_READY) {
5107 clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags);
5108 qla2xxx_flash_npiv_conf(base_vha);
272976ca
AV		 5109 }
5110
8ae6d9c7 5111intr_on_check:
1da177e4 5112 if (!ha->interrupts_on)
fd34f556 5113 ha->isp_ops->enable_intrs(ha);
1da177e4 5114
e315cd28 5115 if (test_and_clear_bit(BEACON_BLINK_NEEDED,
90b604f2
HM		 5116 &base_vha->dpc_flags)) {
5117 if (ha->beacon_blink_led == 1)
5118 ha->isp_ops->beacon_blink(base_vha);
5119 }
f6df144c 5120
8ae6d9c7
GM		 5121 if (!IS_QLAFX00(ha))
5122 qla2x00_do_dpc_all_vps(base_vha);
2c3dfe3f 5123
1da177e4 5124 ha->dpc_active = 0;
c142caf0 5125end_loop:
563585ec 5126 set_current_state(TASK_INTERRUPTIBLE);
1da177e4 5127 } /* End of while(1) */
563585ec 5128 __set_current_state(TASK_RUNNING);
1da177e4 5129
7c3df132
SK		 5130 ql_dbg(ql_dbg_dpc, base_vha, 0x4011,
5131 "DPC handler exiting.\n");
1da177e4
LT		 5132
5133 /*
5134 * Make sure that nobody tries to wake us up again.
5135 */
1da177e4
LT		 5136 ha->dpc_active = 0;
5137
ac280b67
AV		 5138 /* Cleanup any residual CTX SRBs. */
5139 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
5140
39a11240
CH		 5141 return 0;
5142}
5143
5144void
e315cd28 5145qla2xxx_wake_dpc(struct scsi_qla_host *vha)
39a11240 5146{
e315cd28 5147 struct qla_hw_data *ha = vha->hw;
c795c1e4
AV		 5148 struct task_struct *t = ha->dpc_thread;
5149
e315cd28 5150 if (!test_bit(UNLOADING, &vha->dpc_flags) && t)
c795c1e4 5151 wake_up_process(t);
1da177e4
LT		 5152}
5153
1da177e4
LT		 5154/*
5155* qla2x00_rst_aen
5156* Processes asynchronous reset.
5157*
5158* Input:
5159* ha = adapter block pointer.
5160*/
5161static void
e315cd28 5162qla2x00_rst_aen(scsi_qla_host_t *vha)
1da177e4 5163{
e315cd28
AC		 5164 if (vha->flags.online && !vha->flags.reset_active &&
5165 !atomic_read(&vha->loop_down_timer) &&
5166 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) {
1da177e4 5167 do {
e315cd28 5168 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
1da177e4
LT		 5169
5170 /*
5171 * Issue marker command only when we are going to start
5172 * the I/O.
5173 */
e315cd28
AC		 5174 vha->marker_needed = 1;
5175 } while (!atomic_read(&vha->loop_down_timer) &&
5176 (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)));
1da177e4
LT		 5177 }
5178}
5179
1da177e4
LT		 5180/**************************************************************************
5181* qla2x00_timer
5182*
5183* Description:
5184* One second timer
5185*
5186* Context: Interrupt
5187***************************************************************************/
2c3dfe3f 5188void
e315cd28 5189qla2x00_timer(scsi_qla_host_t *vha)
1da177e4 5190{
1da177e4 5191 unsigned long cpu_flags = 0;
1da177e4
LT		 5192 int start_dpc = 0;
5193 int index;
5194 srb_t *sp;
85880801 5195 uint16_t w;
e315cd28 5196 struct qla_hw_data *ha = vha->hw;
73208dfd 5197 struct req_que *req;
85880801 5198
a5b36321 5199 if (ha->flags.eeh_busy) {
7c3df132
SK		 5200 ql_dbg(ql_dbg_timer, vha, 0x6000,
5201 "EEH = %d, restarting timer.\n",
5202 ha->flags.eeh_busy);
a5b36321
LC		 5203 qla2x00_restart_timer(vha, WATCH_INTERVAL);
5204 return;
5205 }
5206
f3ddac19
CD		 5207 /*
5208 * Hardware read to raise pending EEH errors during mailbox waits. If
5209 * the read returns -1 then disable the board.
5210 */
5211 if (!pci_channel_offline(ha->pdev)) {
85880801 5212 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w);
c821e0d5 5213 qla2x00_check_reg16_for_disconnect(vha, w);
f3ddac19 5214 }
1da177e4 5215
cefcaba6 5216 /* Make sure qla82xx_watchdog is run only for physical port */
7ec0effd 5217 if (!vha->vp_idx && IS_P3P_TYPE(ha)) {
579d12b5
SK		 5218 if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags))
5219 start_dpc++;
7ec0effd
AD		 5220 if (IS_QLA82XX(ha))
5221 qla82xx_watchdog(vha);
5222 else if (IS_QLA8044(ha))
5223 qla8044_watchdog(vha);
579d12b5
SK		 5224 }
5225
8ae6d9c7
GM		 5226 if (!vha->vp_idx && IS_QLAFX00(ha))
5227 qlafx00_timer_routine(vha);
5228
1da177e4 5229 /* Loop down handler. */
e315cd28 5230 if (atomic_read(&vha->loop_down_timer) > 0 &&
8f7daead
GM		 5231 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) &&
5232 !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags))
e315cd28 5233 && vha->flags.online) {
1da177e4 5234
e315cd28
AC		 5235 if (atomic_read(&vha->loop_down_timer) ==
5236 vha->loop_down_abort_time) {
1da177e4 5237
7c3df132
SK		 5238 ql_log(ql_log_info, vha, 0x6008,
5239 "Loop down - aborting the queues before time expires.\n");
1da177e4 5240
e315cd28
AC		 5241 if (!IS_QLA2100(ha) && vha->link_down_timeout)
5242 atomic_set(&vha->loop_state, LOOP_DEAD);
1da177e4 5243
f08b7251
AV		 5244 /*
5245 * Schedule an ISP abort to return any FCP2-device
5246 * commands.
5247 */
2c3dfe3f 5248 /* NPIV - scan physical port only */
e315cd28 5249 if (!vha->vp_idx) {
2c3dfe3f
SJ		 5250 spin_lock_irqsave(&ha->hardware_lock,
5251 cpu_flags);
73208dfd 5252 req = ha->req_q_map[0];
2c3dfe3f 5253 for (index = 1;
8d93f550 5254 index < req->num_outstanding_cmds;
2c3dfe3f
SJ		 5255 index++) {
5256 fc_port_t *sfcp;
5257
e315cd28 5258 sp = req->outstanding_cmds[index];
2c3dfe3f
SJ		 5259 if (!sp)
5260 continue;
9ba56b95 5261 if (sp->type != SRB_SCSI_CMD)
cf53b069 5262 continue;
2c3dfe3f 5263 sfcp = sp->fcport;
f08b7251 5264 if (!(sfcp->flags & FCF_FCP2_DEVICE))
2c3dfe3f 5265 continue;
bdf79621 5266
8f7daead
GM		 5267 if (IS_QLA82XX(ha))
5268 set_bit(FCOE_CTX_RESET_NEEDED,
5269 &vha->dpc_flags);
5270 else
5271 set_bit(ISP_ABORT_NEEDED,
e315cd28 5272 &vha->dpc_flags);
2c3dfe3f
SJ		 5273 break;
5274 }
5275 spin_unlock_irqrestore(&ha->hardware_lock,
e315cd28 5276 cpu_flags);
1da177e4 5277 }
1da177e4
LT		 5278 start_dpc++;
5279 }
5280
5281 /* if the loop has been down for 4 minutes, reinit adapter */
e315cd28 5282 if (atomic_dec_and_test(&vha->loop_down_timer) != 0) {
0d6e61bc 5283 if (!(vha->device_flags & DFLG_NO_CABLE)) {
7c3df132 5284 ql_log(ql_log_warn, vha, 0x6009,
1da177e4
LT		 5285 "Loop down - aborting ISP.\n");
5286
8f7daead
GM		 5287 if (IS_QLA82XX(ha))
5288 set_bit(FCOE_CTX_RESET_NEEDED,
5289 &vha->dpc_flags);
5290 else
5291 set_bit(ISP_ABORT_NEEDED,
5292 &vha->dpc_flags);
1da177e4
LT		 5293 }
5294 }
7c3df132
SK		 5295 ql_dbg(ql_dbg_timer, vha, 0x600a,
5296 "Loop down - seconds remaining %d.\n",
5297 atomic_read(&vha->loop_down_timer));
1da177e4 5298 }
cefcaba6
SK		 5299 /* Check if beacon LED needs to be blinked for physical host only */
5300 if (!vha->vp_idx && (ha->beacon_blink_led == 1)) {
999916dc 5301 /* There is no beacon_blink function for ISP82xx */
7ec0effd 5302 if (!IS_P3P_TYPE(ha)) {
999916dc
SK		 5303 set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags);
5304 start_dpc++;
5305 }
f6df144c 5306 }
5307
550bf57d 5308 /* Process any deferred work. */
e315cd28 5309 if (!list_empty(&vha->work_list))
550bf57d
AV		 5310 start_dpc++;
5311
1da177e4 5312 /* Schedule the DPC routine if needed */
e315cd28
AC		 5313 if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) ||
5314 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) ||
5315 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags) ||
1da177e4 5316 start_dpc ||
e315cd28
AC		 5317 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) ||
5318 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) ||
a9083016
GM		 5319 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) ||
5320 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) ||
e315cd28 5321 test_bit(VP_DPC_NEEDED, &vha->dpc_flags) ||
50280c01 5322 test_bit(RELOGIN_NEEDED, &vha->dpc_flags))) {
7c3df132
SK		 5323 ql_dbg(ql_dbg_timer, vha, 0x600b,
5324 "isp_abort_needed=%d loop_resync_needed=%d "
5325 "fcport_update_needed=%d start_dpc=%d "
5326 "reset_marker_needed=%d",
5327 test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags),
5328 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags),
5329 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags),
5330 start_dpc,
5331 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags));
5332 ql_dbg(ql_dbg_timer, vha, 0x600c,
5333 "beacon_blink_needed=%d isp_unrecoverable=%d "
5334 "fcoe_ctx_reset_needed=%d vp_dpc_needed=%d "
50280c01 5335 "relogin_needed=%d.\n",
7c3df132
SK		 5336 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags),
5337 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags),
5338 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags),
5339 test_bit(VP_DPC_NEEDED, &vha->dpc_flags),
50280c01 5340 test_bit(RELOGIN_NEEDED, &vha->dpc_flags));
e315cd28 5341 qla2xxx_wake_dpc(vha);
7c3df132 5342 }
1da177e4 5343
e315cd28 5344 qla2x00_restart_timer(vha, WATCH_INTERVAL);
1da177e4
LT		 5345}
5346
5433383e
AV		 5347/* Firmware interface routines. */
5348
f73cb695 5349#define FW_BLOBS 11
5433383e
AV		 5350#define FW_ISP21XX 0
5351#define FW_ISP22XX 1
5352#define FW_ISP2300 2
5353#define FW_ISP2322 3
48c02fde 5354#define FW_ISP24XX 4
c3a2f0df 5355#define FW_ISP25XX 5
3a03eb79 5356#define FW_ISP81XX 6
a9083016 5357#define FW_ISP82XX 7
6246b8a1
GM		 5358#define FW_ISP2031 8
5359#define FW_ISP8031 9
2c5bbbb2 5360#define FW_ISP27XX 10
5433383e 5361
bb8ee499
AV		 5362#define FW_FILE_ISP21XX "ql2100_fw.bin"
5363#define FW_FILE_ISP22XX "ql2200_fw.bin"
5364#define FW_FILE_ISP2300 "ql2300_fw.bin"
5365#define FW_FILE_ISP2322 "ql2322_fw.bin"
5366#define FW_FILE_ISP24XX "ql2400_fw.bin"
c3a2f0df 5367#define FW_FILE_ISP25XX "ql2500_fw.bin"
3a03eb79 5368#define FW_FILE_ISP81XX "ql8100_fw.bin"
a9083016 5369#define FW_FILE_ISP82XX "ql8200_fw.bin"
6246b8a1
GM		 5370#define FW_FILE_ISP2031 "ql2600_fw.bin"
5371#define FW_FILE_ISP8031 "ql8300_fw.bin"
2c5bbbb2 5372#define FW_FILE_ISP27XX "ql2700_fw.bin"
f73cb695 5373
bb8ee499 5374
e1e82b6f 5375static DEFINE_MUTEX(qla_fw_lock);
5433383e
AV		 5376
5377static struct fw_blob qla_fw_blobs[FW_BLOBS] = {
bb8ee499
AV		 5378 { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, },
5379 { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, },
5380 { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, },
5381 { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, },
5382 { .name = FW_FILE_ISP24XX, },
c3a2f0df 5383 { .name = FW_FILE_ISP25XX, },
3a03eb79 5384 { .name = FW_FILE_ISP81XX, },
a9083016 5385 { .name = FW_FILE_ISP82XX, },
6246b8a1
GM		 5386 { .name = FW_FILE_ISP2031, },
5387 { .name = FW_FILE_ISP8031, },
2c5bbbb2 5388 { .name = FW_FILE_ISP27XX, },
5433383e
AV		 5389};
5390
5391struct fw_blob *
e315cd28 5392qla2x00_request_firmware(scsi_qla_host_t *vha)
5433383e 5393{
e315cd28 5394 struct qla_hw_data *ha = vha->hw;
5433383e
AV		 5395 struct fw_blob *blob;
5396
5433383e
AV		 5397 if (IS_QLA2100(ha)) {
5398 blob = &qla_fw_blobs[FW_ISP21XX];
5399 } else if (IS_QLA2200(ha)) {
5400 blob = &qla_fw_blobs[FW_ISP22XX];
48c02fde 5401 } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
5433383e 5402 blob = &qla_fw_blobs[FW_ISP2300];
48c02fde 5403 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
5433383e 5404 blob = &qla_fw_blobs[FW_ISP2322];
4d4df193 5405 } else if (IS_QLA24XX_TYPE(ha)) {
5433383e 5406 blob = &qla_fw_blobs[FW_ISP24XX];
c3a2f0df
AV		 5407 } else if (IS_QLA25XX(ha)) {
5408 blob = &qla_fw_blobs[FW_ISP25XX];
3a03eb79
AV		 5409 } else if (IS_QLA81XX(ha)) {
5410 blob = &qla_fw_blobs[FW_ISP81XX];
a9083016
GM		 5411 } else if (IS_QLA82XX(ha)) {
5412 blob = &qla_fw_blobs[FW_ISP82XX];
6246b8a1
GM		 5413 } else if (IS_QLA2031(ha)) {
5414 blob = &qla_fw_blobs[FW_ISP2031];
5415 } else if (IS_QLA8031(ha)) {
5416 blob = &qla_fw_blobs[FW_ISP8031];
2c5bbbb2
JC		 5417 } else if (IS_QLA27XX(ha)) {
5418 blob = &qla_fw_blobs[FW_ISP27XX];
8a655229
DC		 5419 } else {
5420 return NULL;
5433383e
AV		 5421 }
5422
e1e82b6f 5423 mutex_lock(&qla_fw_lock);
5433383e
AV		 5424 if (blob->fw)
5425 goto out;
5426
5427 if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) {
7c3df132
SK		 5428 ql_log(ql_log_warn, vha, 0x0063,
5429 "Failed to load firmware image (%s).\n", blob->name);
5433383e
AV		 5430 blob->fw = NULL;
5431 blob = NULL;
5432 goto out;
5433 }
5434
5435out:
e1e82b6f 5436 mutex_unlock(&qla_fw_lock);
5433383e
AV		 5437 return blob;
5438}
5439
5440static void
5441qla2x00_release_firmware(void)
5442{
5443 int idx;
5444
e1e82b6f 5445 mutex_lock(&qla_fw_lock);
5433383e 5446 for (idx = 0; idx < FW_BLOBS; idx++)
cf92549f 5447 release_firmware(qla_fw_blobs[idx].fw);
e1e82b6f 5448 mutex_unlock(&qla_fw_lock);
5433383e
AV		 5449}
5450
14e660e6
SJ		 5451static pci_ers_result_t
5452qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
5453{
85880801
AV		 5454 scsi_qla_host_t *vha = pci_get_drvdata(pdev);
5455 struct qla_hw_data *ha = vha->hw;
5456
7c3df132
SK		 5457 ql_dbg(ql_dbg_aer, vha, 0x9000,
5458 "PCI error detected, state %x.\n", state);
b9b12f73 5459
14e660e6
SJ		 5460 switch (state) {
5461 case pci_channel_io_normal:
85880801 5462 ha->flags.eeh_busy = 0;
14e660e6
SJ		 5463 return PCI_ERS_RESULT_CAN_RECOVER;
5464 case pci_channel_io_frozen:
85880801 5465 ha->flags.eeh_busy = 1;
a5b36321
LC		 5466 /* For ISP82XX complete any pending mailbox cmd */
5467 if (IS_QLA82XX(ha)) {
7190575f 5468 ha->flags.isp82xx_fw_hung = 1;
c8f6544e
CD		 5469 ql_dbg(ql_dbg_aer, vha, 0x9001, "Pci channel io frozen\n");
5470 qla82xx_clear_pending_mbx(vha);
a5b36321 5471 }
90a86fc0 5472 qla2x00_free_irqs(vha);
14e660e6 5473 pci_disable_device(pdev);
bddd2d65
LC		 5474 /* Return back all IOs */
5475 qla2x00_abort_all_cmds(vha, DID_RESET << 16);
14e660e6
SJ		 5476 return PCI_ERS_RESULT_NEED_RESET;
5477 case pci_channel_io_perm_failure:
85880801
AV		 5478 ha->flags.pci_channel_io_perm_failure = 1;
5479 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
14e660e6
SJ		 5480 return PCI_ERS_RESULT_DISCONNECT;
5481 }
5482 return PCI_ERS_RESULT_NEED_RESET;
5483}
5484
5485static pci_ers_result_t
5486qla2xxx_pci_mmio_enabled(struct pci_dev *pdev)
5487{
5488 int risc_paused = 0;
5489 uint32_t stat;
5490 unsigned long flags;
e315cd28
AC		 5491 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
5492 struct qla_hw_data *ha = base_vha->hw;
14e660e6
SJ		 5493 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
5494 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
5495
bcc5b6d3
SK		 5496 if (IS_QLA82XX(ha))
5497 return PCI_ERS_RESULT_RECOVERED;
5498
14e660e6
SJ		 5499 spin_lock_irqsave(&ha->hardware_lock, flags);
5500 if (IS_QLA2100(ha) || IS_QLA2200(ha)){
5501 stat = RD_REG_DWORD(&reg->hccr);
5502 if (stat & HCCR_RISC_PAUSE)
5503 risc_paused = 1;
5504 } else if (IS_QLA23XX(ha)) {
5505 stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
5506 if (stat & HSR_RISC_PAUSED)
5507 risc_paused = 1;
5508 } else if (IS_FWI2_CAPABLE(ha)) {
5509 stat = RD_REG_DWORD(&reg24->host_status);
5510 if (stat & HSRX_RISC_PAUSED)
5511 risc_paused = 1;
5512 }
5513 spin_unlock_irqrestore(&ha->hardware_lock, flags);
5514
5515 if (risc_paused) {
7c3df132
SK		 5516 ql_log(ql_log_info, base_vha, 0x9003,
5517 "RISC paused -- mmio_enabled, Dumping firmware.\n");
e315cd28 5518 ha->isp_ops->fw_dump(base_vha, 0);
14e660e6
SJ		 5519
5520 return PCI_ERS_RESULT_NEED_RESET;
5521 } else
5522 return PCI_ERS_RESULT_RECOVERED;
5523}
5524
fa492630
SK		 5525static uint32_t
5526qla82xx_error_recovery(scsi_qla_host_t *base_vha)
a5b36321
LC		 5527{
5528 uint32_t rval = QLA_FUNCTION_FAILED;
5529 uint32_t drv_active = 0;
5530 struct qla_hw_data *ha = base_vha->hw;
5531 int fn;
5532 struct pci_dev *other_pdev = NULL;
5533
7c3df132
SK		 5534 ql_dbg(ql_dbg_aer, base_vha, 0x9006,
5535 "Entered %s.\n", __func__);
a5b36321
LC		 5536
5537 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
5538
5539 if (base_vha->flags.online) {
5540 /* Abort all outstanding commands,
5541 * so as to be requeued later */
5542 qla2x00_abort_isp_cleanup(base_vha);
5543 }
5544
5545
5546 fn = PCI_FUNC(ha->pdev->devfn);
5547 while (fn > 0) {
5548 fn--;
7c3df132
SK		 5549 ql_dbg(ql_dbg_aer, base_vha, 0x9007,
5550 "Finding pci device at function = 0x%x.\n", fn);
a5b36321
LC		 5551 other_pdev =
5552 pci_get_domain_bus_and_slot(pci_domain_nr(ha->pdev->bus),
5553 ha->pdev->bus->number, PCI_DEVFN(PCI_SLOT(ha->pdev->devfn),
5554 fn));
5555
5556 if (!other_pdev)
5557 continue;
5558 if (atomic_read(&other_pdev->enable_cnt)) {
7c3df132
SK		 5559 ql_dbg(ql_dbg_aer, base_vha, 0x9008,
5560 "Found PCI func available and enable at 0x%x.\n",
5561 fn);
a5b36321
LC		 5562 pci_dev_put(other_pdev);
5563 break;
5564 }
5565 pci_dev_put(other_pdev);
5566 }
5567
5568 if (!fn) {
5569 /* Reset owner */
7c3df132
SK		 5570 ql_dbg(ql_dbg_aer, base_vha, 0x9009,
5571 "This devfn is reset owner = 0x%x.\n",
5572 ha->pdev->devfn);
a5b36321
LC		 5573 qla82xx_idc_lock(ha);
5574
5575 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 5576 QLA8XXX_DEV_INITIALIZING);
a5b36321
LC		 5577
5578 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION,
5579 QLA82XX_IDC_VERSION);
5580
5581 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
7c3df132
SK		 5582 ql_dbg(ql_dbg_aer, base_vha, 0x900a,
5583 "drv_active = 0x%x.\n", drv_active);
a5b36321
LC		 5584
5585 qla82xx_idc_unlock(ha);
5586 /* Reset if device is not already reset
5587 * drv_active would be 0 if a reset has already been done
5588 */
5589 if (drv_active)
5590 rval = qla82xx_start_firmware(base_vha);
5591 else
5592 rval = QLA_SUCCESS;
5593 qla82xx_idc_lock(ha);
5594
5595 if (rval != QLA_SUCCESS) {
7c3df132
SK		 5596 ql_log(ql_log_info, base_vha, 0x900b,
5597 "HW State: FAILED.\n");
a5b36321
LC		 5598 qla82xx_clear_drv_active(ha);
5599 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 5600 QLA8XXX_DEV_FAILED);
a5b36321 5601 } else {
7c3df132
SK		 5602 ql_log(ql_log_info, base_vha, 0x900c,
5603 "HW State: READY.\n");
a5b36321 5604 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 5605 QLA8XXX_DEV_READY);
a5b36321 5606 qla82xx_idc_unlock(ha);
7190575f 5607 ha->flags.isp82xx_fw_hung = 0;
a5b36321
LC		 5608 rval = qla82xx_restart_isp(base_vha);
5609 qla82xx_idc_lock(ha);
5610 /* Clear driver state register */
5611 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, 0);
5612 qla82xx_set_drv_active(base_vha);
5613 }
5614 qla82xx_idc_unlock(ha);
5615 } else {
7c3df132
SK		 5616 ql_dbg(ql_dbg_aer, base_vha, 0x900d,
5617 "This devfn is not reset owner = 0x%x.\n",
5618 ha->pdev->devfn);
a5b36321 5619 if ((qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE) ==
7d613ac6 5620 QLA8XXX_DEV_READY)) {
7190575f 5621 ha->flags.isp82xx_fw_hung = 0;
a5b36321
LC		 5622 rval = qla82xx_restart_isp(base_vha);
5623 qla82xx_idc_lock(ha);
5624 qla82xx_set_drv_active(base_vha);
5625 qla82xx_idc_unlock(ha);
5626 }
5627 }
5628 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
5629
5630 return rval;
5631}
5632
14e660e6
SJ		 5633static pci_ers_result_t
5634qla2xxx_pci_slot_reset(struct pci_dev *pdev)
5635{
5636 pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT;
e315cd28
AC		 5637 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
5638 struct qla_hw_data *ha = base_vha->hw;
90a86fc0
JC		 5639 struct rsp_que *rsp;
5640 int rc, retries = 10;
09483916 5641
7c3df132
SK		 5642 ql_dbg(ql_dbg_aer, base_vha, 0x9004,
5643 "Slot Reset.\n");
85880801 5644
90a86fc0
JC		 5645 /* Workaround: qla2xxx driver which access hardware earlier
5646 * needs error state to be pci_channel_io_online.
5647 * Otherwise mailbox command timesout.
5648 */
5649 pdev->error_state = pci_channel_io_normal;
5650
5651 pci_restore_state(pdev);
5652
8c1496bd
RL		 5653 /* pci_restore_state() clears the saved_state flag of the device
5654 * save restored state which resets saved_state flag
5655 */
5656 pci_save_state(pdev);
5657
09483916
BH		 5658 if (ha->mem_only)
5659 rc = pci_enable_device_mem(pdev);
5660 else
5661 rc = pci_enable_device(pdev);
14e660e6 5662
09483916 5663 if (rc) {
7c3df132 5664 ql_log(ql_log_warn, base_vha, 0x9005,
14e660e6 5665 "Can't re-enable PCI device after reset.\n");
a5b36321 5666 goto exit_slot_reset;
14e660e6 5667 }
14e660e6 5668
90a86fc0
JC		 5669 rsp = ha->rsp_q_map[0];
5670 if (qla2x00_request_irqs(ha, rsp))
a5b36321 5671 goto exit_slot_reset;
90a86fc0 5672
e315cd28 5673 if (ha->isp_ops->pci_config(base_vha))
a5b36321
LC		 5674 goto exit_slot_reset;
5675
5676 if (IS_QLA82XX(ha)) {
5677 if (qla82xx_error_recovery(base_vha) == QLA_SUCCESS) {
5678 ret = PCI_ERS_RESULT_RECOVERED;
5679 goto exit_slot_reset;
5680 } else
5681 goto exit_slot_reset;
5682 }
14e660e6 5683
90a86fc0
JC		 5684 while (ha->flags.mbox_busy && retries--)
5685 msleep(1000);
85880801 5686
e315cd28 5687 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
a9083016 5688 if (ha->isp_ops->abort_isp(base_vha) == QLA_SUCCESS)
14e660e6 5689 ret = PCI_ERS_RESULT_RECOVERED;
e315cd28 5690 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
14e660e6 5691
90a86fc0 5692
a5b36321 5693exit_slot_reset:
7c3df132
SK		 5694 ql_dbg(ql_dbg_aer, base_vha, 0x900e,
5695 "slot_reset return %x.\n", ret);
85880801 5696
14e660e6
SJ		 5697 return ret;
5698}
5699
5700static void
5701qla2xxx_pci_resume(struct pci_dev *pdev)
5702{
e315cd28
AC		 5703 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
5704 struct qla_hw_data *ha = base_vha->hw;
14e660e6
SJ		 5705 int ret;
5706
7c3df132
SK		 5707 ql_dbg(ql_dbg_aer, base_vha, 0x900f,
5708 "pci_resume.\n");
85880801 5709
e315cd28 5710 ret = qla2x00_wait_for_hba_online(base_vha);
14e660e6 5711 if (ret != QLA_SUCCESS) {
7c3df132
SK		 5712 ql_log(ql_log_fatal, base_vha, 0x9002,
5713 "The device failed to resume I/O from slot/link_reset.\n");
14e660e6 5714 }
85880801 5715
3e46f031
LC		 5716 pci_cleanup_aer_uncorrect_error_status(pdev);
5717
85880801 5718 ha->flags.eeh_busy = 0;
14e660e6
SJ		 5719}
5720
2d5a4c34
HM		 5721static void
5722qla83xx_disable_laser(scsi_qla_host_t *vha)
5723{
5724 uint32_t reg, data, fn;
5725 struct qla_hw_data *ha = vha->hw;
5726 struct device_reg_24xx __iomem *isp_reg = &ha->iobase->isp24;
5727
5728 /* pci func #/port # */
5729 ql_dbg(ql_dbg_init, vha, 0x004b,
5730 "Disabling Laser for hba: %p\n", vha);
5731
5732 fn = (RD_REG_DWORD(&isp_reg->ctrl_status) &
5733 (BIT_15|BIT_14|BIT_13|BIT_12));
5734
5735 fn = (fn >> 12);
5736
5737 if (fn & 1)
5738 reg = PORT_1_2031;
5739 else
5740 reg = PORT_0_2031;
5741
5742 data = LASER_OFF_2031;
5743
5744 qla83xx_wr_reg(vha, reg, data);
5745}
5746
a55b2d21 5747static const struct pci_error_handlers qla2xxx_err_handler = {
14e660e6
SJ		 5748 .error_detected = qla2xxx_pci_error_detected,
5749 .mmio_enabled = qla2xxx_pci_mmio_enabled,
5750 .slot_reset = qla2xxx_pci_slot_reset,
5751 .resume = qla2xxx_pci_resume,
5752};
5753
5433383e 5754static struct pci_device_id qla2xxx_pci_tbl[] = {
47f5e069
AV		 5755 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) },
5756 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) },
5757 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) },
5758 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) },
5759 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) },
5760 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) },
5761 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) },
5762 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) },
5763 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) },
4d4df193 5764 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) },
47f5e069
AV		 5765 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) },
5766 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) },
c3a2f0df 5767 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) },
6246b8a1 5768 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2031) },
3a03eb79 5769 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) },
a9083016 5770 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) },
650f528f 5771 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8031) },
8ae6d9c7 5772 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISPF001) },
7ec0effd 5773 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8044) },
f73cb695 5774 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2071) },
2c5bbbb2 5775 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2271) },
5433383e
AV		 5776 { 0 },
5777};
5778MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl);
5779
fca29703 5780static struct pci_driver qla2xxx_pci_driver = {
cb63067a 5781 .name = QLA2XXX_DRIVER_NAME,
0a21ef1e
JB		 5782 .driver = {
5783 .owner = THIS_MODULE,
5784 },
fca29703 5785 .id_table = qla2xxx_pci_tbl,
7ee61397 5786 .probe = qla2x00_probe_one,
4c993f76 5787 .remove = qla2x00_remove_one,
e30d1756 5788 .shutdown = qla2x00_shutdown,
14e660e6 5789 .err_handler = &qla2xxx_err_handler,
fca29703
AV		 5790};
5791
75ef9de1 5792static const struct file_operations apidev_fops = {
6a03b4cd 5793 .owner = THIS_MODULE,
6038f373 5794 .llseek = noop_llseek,
6a03b4cd
HZ		 5795};
5796
1da177e4
LT		 5797/**
5798 * qla2x00_module_init - Module initialization.
5799 **/
5800static int __init
5801qla2x00_module_init(void)
5802{
fca29703
AV		 5803 int ret = 0;
5804
1da177e4 5805 /* Allocate cache for SRBs. */
354d6b21 5806 srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0,
20c2df83 5807 SLAB_HWCACHE_ALIGN, NULL);
1da177e4 5808 if (srb_cachep == NULL) {
7c3df132
SK		 5809 ql_log(ql_log_fatal, NULL, 0x0001,
5810 "Unable to allocate SRB cache...Failing load!.\n");
1da177e4
LT		 5811 return -ENOMEM;
5812 }
5813
2d70c103
NB		 5814 /* Initialize target kmem_cache and mem_pools */
5815 ret = qlt_init();
5816 if (ret < 0) {
5817 kmem_cache_destroy(srb_cachep);
5818 return ret;
5819 } else if (ret > 0) {
5820 /*
5821 * If initiator mode is explictly disabled by qlt_init(),
5822 * prevent scsi_transport_fc.c:fc_scsi_scan_rport() from
5823 * performing scsi_scan_target() during LOOP UP event.
5824 */
5825 qla2xxx_transport_functions.disable_target_scan = 1;
5826 qla2xxx_transport_vport_functions.disable_target_scan = 1;
5827 }
5828
1da177e4
LT		 5829 /* Derive version string. */
5830 strcpy(qla2x00_version_str, QLA2XXX_VERSION);
11010fec 5831 if (ql2xextended_error_logging)
0181944f
AV		 5832 strcat(qla2x00_version_str, "-debug");
5833
1c97a12a
AV		 5834 qla2xxx_transport_template =
5835 fc_attach_transport(&qla2xxx_transport_functions);
2c3dfe3f
SJ		 5836 if (!qla2xxx_transport_template) {
5837 kmem_cache_destroy(srb_cachep);
7c3df132
SK		 5838 ql_log(ql_log_fatal, NULL, 0x0002,
5839 "fc_attach_transport failed...Failing load!.\n");
2d70c103 5840 qlt_exit();
1da177e4 5841 return -ENODEV;
2c3dfe3f 5842 }
6a03b4cd
HZ		 5843
5844 apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops);
5845 if (apidev_major < 0) {
7c3df132
SK		 5846 ql_log(ql_log_fatal, NULL, 0x0003,
5847 "Unable to register char device %s.\n", QLA2XXX_APIDEV);
6a03b4cd
HZ		 5848 }
5849
2c3dfe3f
SJ		 5850 qla2xxx_transport_vport_template =
5851 fc_attach_transport(&qla2xxx_transport_vport_functions);
5852 if (!qla2xxx_transport_vport_template) {
5853 kmem_cache_destroy(srb_cachep);
2d70c103 5854 qlt_exit();
2c3dfe3f 5855 fc_release_transport(qla2xxx_transport_template);
7c3df132
SK		 5856 ql_log(ql_log_fatal, NULL, 0x0004,
5857 "fc_attach_transport vport failed...Failing load!.\n");
1da177e4 5858 return -ENODEV;
2c3dfe3f 5859 }
7c3df132
SK		 5860 ql_log(ql_log_info, NULL, 0x0005,
5861 "QLogic Fibre Channel HBA Driver: %s.\n",
fd9a29f0 5862 qla2x00_version_str);
7ee61397 5863 ret = pci_register_driver(&qla2xxx_pci_driver);
fca29703
AV		 5864 if (ret) {
5865 kmem_cache_destroy(srb_cachep);
2d70c103 5866 qlt_exit();
fca29703 5867 fc_release_transport(qla2xxx_transport_template);
2c3dfe3f 5868 fc_release_transport(qla2xxx_transport_vport_template);
7c3df132
SK		 5869 ql_log(ql_log_fatal, NULL, 0x0006,
5870 "pci_register_driver failed...ret=%d Failing load!.\n",
5871 ret);
fca29703
AV		 5872 }
5873 return ret;
1da177e4
LT		 5874}
5875
5876/**
5877 * qla2x00_module_exit - Module cleanup.
5878 **/
5879static void __exit
5880qla2x00_module_exit(void)
5881{
6a03b4cd 5882 unregister_chrdev(apidev_major, QLA2XXX_APIDEV);
7ee61397 5883 pci_unregister_driver(&qla2xxx_pci_driver);
5433383e 5884 qla2x00_release_firmware();
354d6b21 5885 kmem_cache_destroy(srb_cachep);
2d70c103 5886 qlt_exit();
a9083016
GM		 5887 if (ctx_cachep)
5888 kmem_cache_destroy(ctx_cachep);
1da177e4 5889 fc_release_transport(qla2xxx_transport_template);
2c3dfe3f 5890 fc_release_transport(qla2xxx_transport_vport_template);
1da177e4
LT		 5891}
5892
5893module_init(qla2x00_module_init);
5894module_exit(qla2x00_module_exit);
5895
5896MODULE_AUTHOR("QLogic Corporation");
5897MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver");
5898MODULE_LICENSE("GPL");
5899MODULE_VERSION(QLA2XXX_VERSION);
bb8ee499
AV		 5900MODULE_FIRMWARE(FW_FILE_ISP21XX);
5901MODULE_FIRMWARE(FW_FILE_ISP22XX);
5902MODULE_FIRMWARE(FW_FILE_ISP2300);
5903MODULE_FIRMWARE(FW_FILE_ISP2322);
5904MODULE_FIRMWARE(FW_FILE_ISP24XX);
61623fc3 5905MODULE_FIRMWARE(FW_FILE_ISP25XX);
Linux 6.x block layer and io_uring tree(s)