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qla2xxx: Abort stale cmds on qla_tgt_wq when plogi arrives
[linux-2.6-block.git] / drivers / scsi / qla2xxx / qla_os.c
CommitLineData
1da177e4 1/*
fa90c54f 2 * QLogic Fibre Channel HBA Driver
bd21eaf9 3 * Copyright (c) 2003-2014 QLogic Corporation
1da177e4 4 *
fa90c54f 5 * See LICENSE.qla2xxx for copyright and licensing details.
1da177e4
LT		 6 */
7#include "qla_def.h"
8
9#include <linux/moduleparam.h>
10#include <linux/vmalloc.h>
1da177e4 11#include <linux/delay.h>
39a11240 12#include <linux/kthread.h>
e1e82b6f 13#include <linux/mutex.h>
3420d36c 14#include <linux/kobject.h>
5a0e3ad6 15#include <linux/slab.h>
1da177e4
LT		 16#include <scsi/scsi_tcq.h>
17#include <scsi/scsicam.h>
18#include <scsi/scsi_transport.h>
19#include <scsi/scsi_transport_fc.h>
20
2d70c103
NB		 21#include "qla_target.h"
22
1da177e4
LT		 23/*
24 * Driver version
25 */
26char qla2x00_version_str[40];
27
6a03b4cd
HZ		 28static int apidev_major;
29
1da177e4
LT		 30/*
31 * SRB allocation cache
32 */
e18b890b 33static struct kmem_cache *srb_cachep;
1da177e4 34
a9083016
GM		 35/*
36 * CT6 CTX allocation cache
37 */
38static struct kmem_cache *ctx_cachep;
3ce8866c
SK		 39/*
40 * error level for logging
41 */
42int ql_errlev = ql_log_all;
a9083016 43
fa492630 44static int ql2xenableclass2;
2d70c103
NB		 45module_param(ql2xenableclass2, int, S_IRUGO|S_IRUSR);
46MODULE_PARM_DESC(ql2xenableclass2,
47 "Specify if Class 2 operations are supported from the very "
48 "beginning. Default is 0 - class 2 not supported.");
49
8ae6d9c7 50
1da177e4 51int ql2xlogintimeout = 20;
f2019cb1 52module_param(ql2xlogintimeout, int, S_IRUGO);
1da177e4
LT		 53MODULE_PARM_DESC(ql2xlogintimeout,
54 "Login timeout value in seconds.");
55
a7b61842 56int qlport_down_retry;
f2019cb1 57module_param(qlport_down_retry, int, S_IRUGO);
1da177e4 58MODULE_PARM_DESC(qlport_down_retry,
900d9f98 59 "Maximum number of command retries to a port that returns "
1da177e4
LT		 60 "a PORT-DOWN status.");
61
1da177e4
LT		 62int ql2xplogiabsentdevice;
63module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR);
64MODULE_PARM_DESC(ql2xplogiabsentdevice,
65 "Option to enable PLOGI to devices that are not present after "
900d9f98 66 "a Fabric scan. This is needed for several broken switches. "
1da177e4
LT		 67 "Default is 0 - no PLOGI. 1 - perfom PLOGI.");
68
1da177e4 69int ql2xloginretrycount = 0;
f2019cb1 70module_param(ql2xloginretrycount, int, S_IRUGO);
1da177e4
LT		 71MODULE_PARM_DESC(ql2xloginretrycount,
72 "Specify an alternate value for the NVRAM login retry count.");
73
a7a167bf 74int ql2xallocfwdump = 1;
f2019cb1 75module_param(ql2xallocfwdump, int, S_IRUGO);
a7a167bf
AV		 76MODULE_PARM_DESC(ql2xallocfwdump,
77 "Option to enable allocation of memory for a firmware dump "
78 "during HBA initialization. Memory allocation requirements "
79 "vary by ISP type. Default is 1 - allocate memory.");
80
11010fec 81int ql2xextended_error_logging;
27d94035 82module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
11010fec 83MODULE_PARM_DESC(ql2xextended_error_logging,
3ce8866c
SK		 84 "Option to enable extended error logging,\n"
85 "\t\tDefault is 0 - no logging. 0x40000000 - Module Init & Probe.\n"
86 "\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n"
87 "\t\t0x08000000 - IO tracing. 0x04000000 - DPC Thread.\n"
88 "\t\t0x02000000 - Async events. 0x01000000 - Timer routines.\n"
89 "\t\t0x00800000 - User space. 0x00400000 - Task Management.\n"
90 "\t\t0x00200000 - AER/EEH. 0x00100000 - Multi Q.\n"
91 "\t\t0x00080000 - P3P Specific. 0x00040000 - Virtual Port.\n"
92 "\t\t0x00020000 - Buffer Dump. 0x00010000 - Misc.\n"
29f9f90c
CD		 93 "\t\t0x00008000 - Verbose. 0x00004000 - Target.\n"
94 "\t\t0x00002000 - Target Mgmt. 0x00001000 - Target TMF.\n"
3ce8866c 95 "\t\t0x7fffffff - For enabling all logs, can be too many logs.\n"
cfb0919c
CD		 96 "\t\t0x1e400000 - Preferred value for capturing essential "
97 "debug information (equivalent to old "
98 "ql2xextended_error_logging=1).\n"
3ce8866c 99 "\t\tDo LOGICAL OR of the value to enable more than one level");
0181944f 100
a9083016 101int ql2xshiftctondsd = 6;
f2019cb1 102module_param(ql2xshiftctondsd, int, S_IRUGO);
a9083016
GM		 103MODULE_PARM_DESC(ql2xshiftctondsd,
104 "Set to control shifting of command type processing "
105 "based on total number of SG elements.");
106
7e47e5ca 107int ql2xfdmienable=1;
de187df8 108module_param(ql2xfdmienable, int, S_IRUGO|S_IWUSR);
cca5335c 109MODULE_PARM_DESC(ql2xfdmienable,
7794a5af
FW		 110 "Enables FDMI registrations. "
111 "0 - no FDMI. Default is 1 - perform FDMI.");
cca5335c 112
50280c01
CD		 113#define MAX_Q_DEPTH 32
114static int ql2xmaxqdepth = MAX_Q_DEPTH;
df7baa50
AV		 115module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR);
116MODULE_PARM_DESC(ql2xmaxqdepth,
e92e4a8f
CD		 117 "Maximum queue depth to set for each LUN. "
118 "Default is 32.");
df7baa50 119
9e522cd8
AE		 120int ql2xenabledif = 2;
121module_param(ql2xenabledif, int, S_IRUGO);
bad75002 122MODULE_PARM_DESC(ql2xenabledif,
b97f5d0b
SM		 123 " Enable T10-CRC-DIF:\n"
124 " Default is 2.\n"
125 " 0 -- No DIF Support\n"
126 " 1 -- Enable DIF for all types\n"
127 " 2 -- Enable DIF for all types, except Type 0.\n");
bad75002 128
8cb2049c 129int ql2xenablehba_err_chk = 2;
bad75002
AE		 130module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR);
131MODULE_PARM_DESC(ql2xenablehba_err_chk,
8cb2049c 132 " Enable T10-CRC-DIF Error isolation by HBA:\n"
b97f5d0b 133 " Default is 2.\n"
8cb2049c
AE		 134 " 0 -- Error isolation disabled\n"
135 " 1 -- Error isolation enabled only for DIX Type 0\n"
136 " 2 -- Error isolation enabled for all Types\n");
bad75002 137
e5896bd5 138int ql2xiidmaenable=1;
f2019cb1 139module_param(ql2xiidmaenable, int, S_IRUGO);
e5896bd5
AV		 140MODULE_PARM_DESC(ql2xiidmaenable,
141 "Enables iIDMA settings "
142 "Default is 1 - perform iIDMA. 0 - no iIDMA.");
143
73208dfd 144int ql2xmaxqueues = 1;
f2019cb1 145module_param(ql2xmaxqueues, int, S_IRUGO);
73208dfd
AC		 146MODULE_PARM_DESC(ql2xmaxqueues,
147 "Enables MQ settings "
ae68230c
JP		 148 "Default is 1 for single queue. Set it to number "
149 "of queues in MQ mode.");
68ca949c
AC		 150
151int ql2xmultique_tag;
f2019cb1 152module_param(ql2xmultique_tag, int, S_IRUGO);
68ca949c
AC		 153MODULE_PARM_DESC(ql2xmultique_tag,
154 "Enables CPU affinity settings for the driver "
155 "Default is 0 for no affinity of request and response IO. "
156 "Set it to 1 to turn on the cpu affinity.");
e337d907
AV		 157
158int ql2xfwloadbin;
86e45bf6 159module_param(ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
e337d907 160MODULE_PARM_DESC(ql2xfwloadbin,
7c3df132
SK		 161 "Option to specify location from which to load ISP firmware:.\n"
162 " 2 -- load firmware via the request_firmware() (hotplug).\n"
e337d907
AV		 163 " interface.\n"
164 " 1 -- load firmware from flash.\n"
165 " 0 -- use default semantics.\n");
166
ae97c91e 167int ql2xetsenable;
f2019cb1 168module_param(ql2xetsenable, int, S_IRUGO);
ae97c91e
AV		 169MODULE_PARM_DESC(ql2xetsenable,
170 "Enables firmware ETS burst."
171 "Default is 0 - skip ETS enablement.");
172
6907869d 173int ql2xdbwr = 1;
86e45bf6 174module_param(ql2xdbwr, int, S_IRUGO|S_IWUSR);
a9083016 175MODULE_PARM_DESC(ql2xdbwr,
08de2844
GM		 176 "Option to specify scheme for request queue posting.\n"
177 " 0 -- Regular doorbell.\n"
178 " 1 -- CAMRAM doorbell (faster).\n");
a9083016 179
f4c496c1 180int ql2xtargetreset = 1;
f2019cb1 181module_param(ql2xtargetreset, int, S_IRUGO);
f4c496c1
GM		 182MODULE_PARM_DESC(ql2xtargetreset,
183 "Enable target reset."
184 "Default is 1 - use hw defaults.");
185
4da26e16 186int ql2xgffidenable;
f2019cb1 187module_param(ql2xgffidenable, int, S_IRUGO);
4da26e16
CD		 188MODULE_PARM_DESC(ql2xgffidenable,
189 "Enables GFF_ID checks of port type. "
190 "Default is 0 - Do not use GFF_ID information.");
a9083016 191
3822263e 192int ql2xasynctmfenable;
f2019cb1 193module_param(ql2xasynctmfenable, int, S_IRUGO);
3822263e
MI		 194MODULE_PARM_DESC(ql2xasynctmfenable,
195 "Enables issue of TM IOCBs asynchronously via IOCB mechanism"
196 "Default is 0 - Issue TM IOCBs via mailbox mechanism.");
ed0de87c
GM		 197
198int ql2xdontresethba;
86e45bf6 199module_param(ql2xdontresethba, int, S_IRUGO|S_IWUSR);
ed0de87c 200MODULE_PARM_DESC(ql2xdontresethba,
08de2844
GM		 201 "Option to specify reset behaviour.\n"
202 " 0 (Default) -- Reset on failure.\n"
203 " 1 -- Do not reset on failure.\n");
ed0de87c 204
1abf635d
HR		 205uint64_t ql2xmaxlun = MAX_LUNS;
206module_param(ql2xmaxlun, ullong, S_IRUGO);
82515920
AV		 207MODULE_PARM_DESC(ql2xmaxlun,
208 "Defines the maximum LU number to register with the SCSI "
209 "midlayer. Default is 65535.");
210
08de2844
GM		 211int ql2xmdcapmask = 0x1F;
212module_param(ql2xmdcapmask, int, S_IRUGO);
213MODULE_PARM_DESC(ql2xmdcapmask,
214 "Set the Minidump driver capture mask level. "
6e96fa7b 215 "Default is 0x1F - Can be set to 0x3, 0x7, 0xF, 0x1F, 0x7F.");
08de2844 216
3aadff35 217int ql2xmdenable = 1;
08de2844
GM		 218module_param(ql2xmdenable, int, S_IRUGO);
219MODULE_PARM_DESC(ql2xmdenable,
220 "Enable/disable MiniDump. "
3aadff35
GM		 221 "0 - MiniDump disabled. "
222 "1 (Default) - MiniDump enabled.");
08de2844 223
1da177e4 224/*
fa2a1ce5 225 * SCSI host template entry points
1da177e4
LT		 226 */
227static int qla2xxx_slave_configure(struct scsi_device * device);
f4f051eb 228static int qla2xxx_slave_alloc(struct scsi_device *);
1e99e33a
AV		 229static int qla2xxx_scan_finished(struct Scsi_Host *, unsigned long time);
230static void qla2xxx_scan_start(struct Scsi_Host *);
f4f051eb 231static void qla2xxx_slave_destroy(struct scsi_device *);
f281233d 232static int qla2xxx_queuecommand(struct Scsi_Host *h, struct scsi_cmnd *cmd);
1da177e4
LT		 233static int qla2xxx_eh_abort(struct scsi_cmnd *);
234static int qla2xxx_eh_device_reset(struct scsi_cmnd *);
523ec773 235static int qla2xxx_eh_target_reset(struct scsi_cmnd *);
1da177e4
LT		 236static int qla2xxx_eh_bus_reset(struct scsi_cmnd *);
237static int qla2xxx_eh_host_reset(struct scsi_cmnd *);
1da177e4 238
1a2fbf18 239static void qla2x00_clear_drv_active(struct qla_hw_data *);
3491255e 240static void qla2x00_free_device(scsi_qla_host_t *);
2d5a4c34 241static void qla83xx_disable_laser(scsi_qla_host_t *vha);
ce7e4af7 242
a5326f86 243struct scsi_host_template qla2xxx_driver_template = {
1da177e4 244 .module = THIS_MODULE,
cb63067a 245 .name = QLA2XXX_DRIVER_NAME,
a5326f86 246 .queuecommand = qla2xxx_queuecommand,
fca29703
AV		 247
248 .eh_abort_handler = qla2xxx_eh_abort,
249 .eh_device_reset_handler = qla2xxx_eh_device_reset,
523ec773 250 .eh_target_reset_handler = qla2xxx_eh_target_reset,
fca29703
AV		 251 .eh_bus_reset_handler = qla2xxx_eh_bus_reset,
252 .eh_host_reset_handler = qla2xxx_eh_host_reset,
253
254 .slave_configure = qla2xxx_slave_configure,
255
256 .slave_alloc = qla2xxx_slave_alloc,
257 .slave_destroy = qla2xxx_slave_destroy,
ed677086
AV		 258 .scan_finished = qla2xxx_scan_finished,
259 .scan_start = qla2xxx_scan_start,
db5ed4df 260 .change_queue_depth = scsi_change_queue_depth,
fca29703
AV		 261 .this_id = -1,
262 .cmd_per_lun = 3,
263 .use_clustering = ENABLE_CLUSTERING,
264 .sg_tablesize = SG_ALL,
265
266 .max_sectors = 0xFFFF,
afb046e2 267 .shost_attrs = qla2x00_host_attrs,
2d70c103
NB		 268
269 .supported_mode = MODE_INITIATOR,
2ecb204d 270 .use_blk_tags = 1,
c40ecc12 271 .track_queue_depth = 1,
fca29703
AV		 272};
273
1da177e4 274static struct scsi_transport_template *qla2xxx_transport_template = NULL;
2c3dfe3f 275struct scsi_transport_template *qla2xxx_transport_vport_template = NULL;
1da177e4 276
1da177e4
LT		 277/* TODO Convert to inlines
278 *
279 * Timer routines
280 */
1da177e4 281
2c3dfe3f 282__inline__ void
e315cd28 283qla2x00_start_timer(scsi_qla_host_t *vha, void *func, unsigned long interval)
1da177e4 284{
e315cd28
AC		 285 init_timer(&vha->timer);
286 vha->timer.expires = jiffies + interval * HZ;
287 vha->timer.data = (unsigned long)vha;
288 vha->timer.function = (void (*)(unsigned long))func;
289 add_timer(&vha->timer);
290 vha->timer_active = 1;
1da177e4
LT		 291}
292
293static inline void
e315cd28 294qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval)
1da177e4 295{
a9083016 296 /* Currently used for 82XX only. */
7c3df132
SK		 297 if (vha->device_flags & DFLG_DEV_FAILED) {
298 ql_dbg(ql_dbg_timer, vha, 0x600d,
299 "Device in a failed state, returning.\n");
a9083016 300 return;
7c3df132 301 }
a9083016 302
e315cd28 303 mod_timer(&vha->timer, jiffies + interval * HZ);
1da177e4
LT		 304}
305
a824ebb3 306static __inline__ void
e315cd28 307qla2x00_stop_timer(scsi_qla_host_t *vha)
1da177e4 308{
e315cd28
AC		 309 del_timer_sync(&vha->timer);
310 vha->timer_active = 0;
1da177e4
LT		 311}
312
1da177e4
LT		 313static int qla2x00_do_dpc(void *data);
314
315static void qla2x00_rst_aen(scsi_qla_host_t *);
316
73208dfd
AC		 317static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t,
318 struct req_que **, struct rsp_que **);
e30d1756 319static void qla2x00_free_fw_dump(struct qla_hw_data *);
e315cd28 320static void qla2x00_mem_free(struct qla_hw_data *);
1da177e4 321
1da177e4 322/* -------------------------------------------------------------------------- */
9a347ff4
CD		 323static int qla2x00_alloc_queues(struct qla_hw_data *ha, struct req_que *req,
324 struct rsp_que *rsp)
73208dfd 325{
7c3df132 326 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2afa19a9 327 ha->req_q_map = kzalloc(sizeof(struct req_que *) * ha->max_req_queues,
73208dfd
AC		 328 GFP_KERNEL);
329 if (!ha->req_q_map) {
7c3df132
SK		 330 ql_log(ql_log_fatal, vha, 0x003b,
331 "Unable to allocate memory for request queue ptrs.\n");
73208dfd
AC		 332 goto fail_req_map;
333 }
334
2afa19a9 335 ha->rsp_q_map = kzalloc(sizeof(struct rsp_que *) * ha->max_rsp_queues,
73208dfd
AC		 336 GFP_KERNEL);
337 if (!ha->rsp_q_map) {
7c3df132
SK		 338 ql_log(ql_log_fatal, vha, 0x003c,
339 "Unable to allocate memory for response queue ptrs.\n");
73208dfd
AC		 340 goto fail_rsp_map;
341 }
9a347ff4
CD		 342 /*
343 * Make sure we record at least the request and response queue zero in
344 * case we need to free them if part of the probe fails.
345 */
346 ha->rsp_q_map[0] = rsp;
347 ha->req_q_map[0] = req;
73208dfd
AC		 348 set_bit(0, ha->rsp_qid_map);
349 set_bit(0, ha->req_qid_map);
350 return 1;
351
352fail_rsp_map:
353 kfree(ha->req_q_map);
354 ha->req_q_map = NULL;
355fail_req_map:
356 return -ENOMEM;
357}
358
2afa19a9 359static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req)
73208dfd 360{
8ae6d9c7
GM		 361 if (IS_QLAFX00(ha)) {
362 if (req && req->ring_fx00)
363 dma_free_coherent(&ha->pdev->dev,
364 (req->length_fx00 + 1) * sizeof(request_t),
365 req->ring_fx00, req->dma_fx00);
366 } else if (req && req->ring)
73208dfd
AC		 367 dma_free_coherent(&ha->pdev->dev,
368 (req->length + 1) * sizeof(request_t),
369 req->ring, req->dma);
370
8d93f550
CD		 371 if (req)
372 kfree(req->outstanding_cmds);
373
73208dfd
AC		 374 kfree(req);
375 req = NULL;
376}
377
2afa19a9
AC		 378static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp)
379{
8ae6d9c7
GM		 380 if (IS_QLAFX00(ha)) {
381 if (rsp && rsp->ring)
382 dma_free_coherent(&ha->pdev->dev,
383 (rsp->length_fx00 + 1) * sizeof(request_t),
384 rsp->ring_fx00, rsp->dma_fx00);
385 } else if (rsp && rsp->ring) {
2afa19a9
AC		 386 dma_free_coherent(&ha->pdev->dev,
387 (rsp->length + 1) * sizeof(response_t),
388 rsp->ring, rsp->dma);
8ae6d9c7 389 }
2afa19a9
AC		 390 kfree(rsp);
391 rsp = NULL;
392}
393
73208dfd
AC		 394static void qla2x00_free_queues(struct qla_hw_data *ha)
395{
396 struct req_que *req;
397 struct rsp_que *rsp;
398 int cnt;
399
2afa19a9 400 for (cnt = 0; cnt < ha->max_req_queues; cnt++) {
73208dfd 401 req = ha->req_q_map[cnt];
2afa19a9 402 qla2x00_free_req_que(ha, req);
73208dfd 403 }
73208dfd
AC		 404 kfree(ha->req_q_map);
405 ha->req_q_map = NULL;
2afa19a9
AC		 406
407 for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) {
408 rsp = ha->rsp_q_map[cnt];
409 qla2x00_free_rsp_que(ha, rsp);
410 }
411 kfree(ha->rsp_q_map);
412 ha->rsp_q_map = NULL;
73208dfd
AC		 413}
414
68ca949c
AC		 415static int qla25xx_setup_mode(struct scsi_qla_host *vha)
416{
417 uint16_t options = 0;
418 int ques, req, ret;
419 struct qla_hw_data *ha = vha->hw;
420
7163ea81 421 if (!(ha->fw_attributes & BIT_6)) {
7c3df132
SK		 422 ql_log(ql_log_warn, vha, 0x00d8,
423 "Firmware is not multi-queue capable.\n");
7163ea81
AC		 424 goto fail;
425 }
68ca949c 426 if (ql2xmultique_tag) {
68ca949c
AC		 427 /* create a request queue for IO */
428 options |= BIT_7;
429 req = qla25xx_create_req_que(ha, options, 0, 0, -1,
430 QLA_DEFAULT_QUE_QOS);
431 if (!req) {
7c3df132
SK		 432 ql_log(ql_log_warn, vha, 0x00e0,
433 "Failed to create request queue.\n");
68ca949c
AC		 434 goto fail;
435 }
278274d5 436 ha->wq = alloc_workqueue("qla2xxx_wq", WQ_MEM_RECLAIM, 1);
68ca949c
AC		 437 vha->req = ha->req_q_map[req];
438 options |= BIT_1;
439 for (ques = 1; ques < ha->max_rsp_queues; ques++) {
440 ret = qla25xx_create_rsp_que(ha, options, 0, 0, req);
441 if (!ret) {
7c3df132
SK		 442 ql_log(ql_log_warn, vha, 0x00e8,
443 "Failed to create response queue.\n");
68ca949c
AC		 444 goto fail2;
445 }
446 }
7163ea81 447 ha->flags.cpu_affinity_enabled = 1;
7c3df132 448 ql_dbg(ql_dbg_multiq, vha, 0xc007,
6ef68da7 449 "CPU affinity mode enabled, "
7c3df132
SK		 450 "no. of response queues:%d no. of request queues:%d.\n",
451 ha->max_rsp_queues, ha->max_req_queues);
452 ql_dbg(ql_dbg_init, vha, 0x00e9,
6ef68da7 453 "CPU affinity mode enabled, "
7c3df132
SK		 454 "no. of response queues:%d no. of request queues:%d.\n",
455 ha->max_rsp_queues, ha->max_req_queues);
68ca949c
AC		 456 }
457 return 0;
458fail2:
459 qla25xx_delete_queues(vha);
7163ea81
AC		 460 destroy_workqueue(ha->wq);
461 ha->wq = NULL;
0cd33fcf 462 vha->req = ha->req_q_map[0];
68ca949c
AC		 463fail:
464 ha->mqenable = 0;
7163ea81
AC		 465 kfree(ha->req_q_map);
466 kfree(ha->rsp_q_map);
467 ha->max_req_queues = ha->max_rsp_queues = 1;
68ca949c
AC		 468 return 1;
469}
470
1da177e4 471static char *
e315cd28 472qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str)
1da177e4 473{
e315cd28 474 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 475 static char *pci_bus_modes[] = {
476 "33", "66", "100", "133",
477 };
478 uint16_t pci_bus;
479
480 strcpy(str, "PCI");
481 pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9;
482 if (pci_bus) {
483 strcat(str, "-X (");
484 strcat(str, pci_bus_modes[pci_bus]);
485 } else {
486 pci_bus = (ha->pci_attr & BIT_8) >> 8;
487 strcat(str, " (");
488 strcat(str, pci_bus_modes[pci_bus]);
489 }
490 strcat(str, " MHz)");
491
492 return (str);
493}
494
fca29703 495static char *
e315cd28 496qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str)
fca29703
AV		 497{
498 static char *pci_bus_modes[] = { "33", "66", "100", "133", };
e315cd28 499 struct qla_hw_data *ha = vha->hw;
fca29703 500 uint32_t pci_bus;
fca29703 501
62a276f8 502 if (pci_is_pcie(ha->pdev)) {
fca29703 503 char lwstr[6];
62a276f8 504 uint32_t lstat, lspeed, lwidth;
fca29703 505
62a276f8
BH		 506 pcie_capability_read_dword(ha->pdev, PCI_EXP_LNKCAP, &lstat);
507 lspeed = lstat & PCI_EXP_LNKCAP_SLS;
508 lwidth = (lstat & PCI_EXP_LNKCAP_MLW) >> 4;
fca29703
AV		 509
510 strcpy(str, "PCIe (");
49300af7
SK		 511 switch (lspeed) {
512 case 1:
c87a0d8c 513 strcat(str, "2.5GT/s ");
49300af7
SK		 514 break;
515 case 2:
c87a0d8c 516 strcat(str, "5.0GT/s ");
49300af7
SK		 517 break;
518 case 3:
519 strcat(str, "8.0GT/s ");
520 break;
521 default:
fca29703 522 strcat(str, "<unknown> ");
49300af7
SK		 523 break;
524 }
fca29703
AV		 525 snprintf(lwstr, sizeof(lwstr), "x%d)", lwidth);
526 strcat(str, lwstr);
527
528 return str;
529 }
530
531 strcpy(str, "PCI");
532 pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8;
533 if (pci_bus == 0 || pci_bus == 8) {
534 strcat(str, " (");
535 strcat(str, pci_bus_modes[pci_bus >> 3]);
536 } else {
537 strcat(str, "-X ");
538 if (pci_bus & BIT_2)
539 strcat(str, "Mode 2");
540 else
541 strcat(str, "Mode 1");
542 strcat(str, " (");
543 strcat(str, pci_bus_modes[pci_bus & ~BIT_2]);
544 }
545 strcat(str, " MHz)");
546
547 return str;
548}
549
e5f82ab8 550static char *
df57caba 551qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
1da177e4
LT		 552{
553 char un_str[10];
e315cd28 554 struct qla_hw_data *ha = vha->hw;
fa2a1ce5 555
df57caba
HM		 556 snprintf(str, size, "%d.%02d.%02d ", ha->fw_major_version,
557 ha->fw_minor_version, ha->fw_subminor_version);
1da177e4
LT		 558
559 if (ha->fw_attributes & BIT_9) {
560 strcat(str, "FLX");
561 return (str);
562 }
563
564 switch (ha->fw_attributes & 0xFF) {
565 case 0x7:
566 strcat(str, "EF");
567 break;
568 case 0x17:
569 strcat(str, "TP");
570 break;
571 case 0x37:
572 strcat(str, "IP");
573 break;
574 case 0x77:
575 strcat(str, "VI");
576 break;
577 default:
578 sprintf(un_str, "(%x)", ha->fw_attributes);
579 strcat(str, un_str);
580 break;
581 }
582 if (ha->fw_attributes & 0x100)
583 strcat(str, "X");
584
585 return (str);
586}
587
e5f82ab8 588static char *
df57caba 589qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
fca29703 590{
e315cd28 591 struct qla_hw_data *ha = vha->hw;
f0883ac6 592
df57caba 593 snprintf(str, size, "%d.%02d.%02d (%x)", ha->fw_major_version,
3a03eb79 594 ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes);
fca29703 595 return str;
fca29703
AV		 596}
597
9ba56b95
GM		 598void
599qla2x00_sp_free_dma(void *vha, void *ptr)
fca29703 600{
9ba56b95
GM		 601 srb_t *sp = (srb_t *)ptr;
602 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
603 struct qla_hw_data *ha = sp->fcport->vha->hw;
604 void *ctx = GET_CMD_CTX_SP(sp);
fca29703 605
9ba56b95
GM		 606 if (sp->flags & SRB_DMA_VALID) {
607 scsi_dma_unmap(cmd);
608 sp->flags &= ~SRB_DMA_VALID;
7c3df132 609 }
fca29703 610
9ba56b95
GM		 611 if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
612 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
613 scsi_prot_sg_count(cmd), cmd->sc_data_direction);
614 sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
615 }
616
617 if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
618 /* List assured to be having elements */
f83adb61 619 qla2x00_clean_dsd_pool(ha, sp, NULL);
9ba56b95
GM		 620 sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
621 }
622
623 if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
624 dma_pool_free(ha->dl_dma_pool, ctx,
625 ((struct crc_context *)ctx)->crc_ctx_dma);
626 sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
627 }
628
629 if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
630 struct ct6_dsd *ctx1 = (struct ct6_dsd *)ctx;
fca29703 631
9ba56b95
GM		 632 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd,
633 ctx1->fcp_cmnd_dma);
634 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list);
635 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt;
636 ha->gbl_dsd_avail += ctx1->dsd_use_cnt;
637 mempool_free(ctx1, ha->ctx_mempool);
638 ctx1 = NULL;
639 }
640
641 CMD_SP(cmd) = NULL;
b00ee7d7 642 qla2x00_rel_sp(sp->fcport->vha, sp);
9ba56b95
GM		 643}
644
14b06808 645static void
9ba56b95
GM		 646qla2x00_sp_compl(void *data, void *ptr, int res)
647{
648 struct qla_hw_data *ha = (struct qla_hw_data *)data;
649 srb_t *sp = (srb_t *)ptr;
650 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
651
652 cmd->result = res;
653
654 if (atomic_read(&sp->ref_count) == 0) {
655 ql_dbg(ql_dbg_io, sp->fcport->vha, 0x3015,
656 "SP reference-count to ZERO -- sp=%p cmd=%p.\n",
657 sp, GET_CMD_SP(sp));
658 if (ql2xextended_error_logging & ql_dbg_io)
659 BUG();
660 return;
661 }
662 if (!atomic_dec_and_test(&sp->ref_count))
663 return;
664
665 qla2x00_sp_free_dma(ha, sp);
666 cmd->scsi_done(cmd);
fca29703
AV		 667}
668
8ae6d9c7
GM		 669/* If we are SP1 here, we need to still take and release the host_lock as SP1
670 * does not have the changes necessary to avoid taking host->host_lock.
671 */
1da177e4 672static int
f5e3e40b 673qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
fca29703 674{
134ae078 675 scsi_qla_host_t *vha = shost_priv(host);
fca29703 676 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
19a7b4ae 677 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
e315cd28
AC		 678 struct qla_hw_data *ha = vha->hw;
679 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
fca29703
AV		 680 srb_t *sp;
681 int rval;
682
85880801 683 if (ha->flags.eeh_busy) {
7c3df132 684 if (ha->flags.pci_channel_io_perm_failure) {
5f28d2d7 685 ql_dbg(ql_dbg_aer, vha, 0x9010,
7c3df132
SK		 686 "PCI Channel IO permanent failure, exiting "
687 "cmd=%p.\n", cmd);
b9b12f73 688 cmd->result = DID_NO_CONNECT << 16;
7c3df132 689 } else {
5f28d2d7 690 ql_dbg(ql_dbg_aer, vha, 0x9011,
7c3df132 691 "EEH_Busy, Requeuing the cmd=%p.\n", cmd);
85880801 692 cmd->result = DID_REQUEUE << 16;
7c3df132 693 }
14e660e6
SJ		 694 goto qc24_fail_command;
695 }
696
19a7b4ae
JSEC		 697 rval = fc_remote_port_chkready(rport);
698 if (rval) {
699 cmd->result = rval;
5f28d2d7 700 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3003,
7c3df132
SK		 701 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
702 cmd, rval);
fca29703
AV		 703 goto qc24_fail_command;
704 }
705
bad75002
AE		 706 if (!vha->flags.difdix_supported &&
707 scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) {
7c3df132
SK		 708 ql_dbg(ql_dbg_io, vha, 0x3004,
709 "DIF Cap not reg, fail DIF capable cmd's:%p.\n",
710 cmd);
bad75002
AE		 711 cmd->result = DID_NO_CONNECT << 16;
712 goto qc24_fail_command;
713 }
aa651be8
CD		 714
715 if (!fcport) {
716 cmd->result = DID_NO_CONNECT << 16;
717 goto qc24_fail_command;
718 }
719
fca29703
AV		 720 if (atomic_read(&fcport->state) != FCS_ONLINE) {
721 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
38170fa8 722 atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
7c3df132
SK		 723 ql_dbg(ql_dbg_io, vha, 0x3005,
724 "Returning DNC, fcport_state=%d loop_state=%d.\n",
725 atomic_read(&fcport->state),
726 atomic_read(&base_vha->loop_state));
fca29703
AV		 727 cmd->result = DID_NO_CONNECT << 16;
728 goto qc24_fail_command;
729 }
7b594131 730 goto qc24_target_busy;
fca29703
AV		 731 }
732
e05fe292
CD		 733 /*
734 * Return target busy if we've received a non-zero retry_delay_timer
735 * in a FCP_RSP.
736 */
975f7d46
BP		 737 if (fcport->retry_delay_timestamp == 0) {
738 /* retry delay not set */
739 } else if (time_after(jiffies, fcport->retry_delay_timestamp))
e05fe292
CD		 740 fcport->retry_delay_timestamp = 0;
741 else
742 goto qc24_target_busy;
743
b00ee7d7 744 sp = qla2x00_get_sp(vha, fcport, GFP_ATOMIC);
50280c01 745 if (!sp)
f5e3e40b 746 goto qc24_host_busy;
fca29703 747
9ba56b95
GM		 748 sp->u.scmd.cmd = cmd;
749 sp->type = SRB_SCSI_CMD;
750 atomic_set(&sp->ref_count, 1);
751 CMD_SP(cmd) = (void *)sp;
752 sp->free = qla2x00_sp_free_dma;
753 sp->done = qla2x00_sp_compl;
754
e315cd28 755 rval = ha->isp_ops->start_scsi(sp);
7c3df132 756 if (rval != QLA_SUCCESS) {
53016ed3 757 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3013,
7c3df132 758 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
fca29703 759 goto qc24_host_busy_free_sp;
7c3df132 760 }
fca29703 761
fca29703
AV		 762 return 0;
763
764qc24_host_busy_free_sp:
9ba56b95 765 qla2x00_sp_free_dma(ha, sp);
fca29703 766
f5e3e40b 767qc24_host_busy:
fca29703
AV		 768 return SCSI_MLQUEUE_HOST_BUSY;
769
7b594131
MC		 770qc24_target_busy:
771 return SCSI_MLQUEUE_TARGET_BUSY;
772
fca29703 773qc24_fail_command:
f5e3e40b 774 cmd->scsi_done(cmd);
fca29703
AV		 775
776 return 0;
777}
778
1da177e4
LT		 779/*
780 * qla2x00_eh_wait_on_command
781 * Waits for the command to be returned by the Firmware for some
782 * max time.
783 *
784 * Input:
1da177e4 785 * cmd = Scsi Command to wait on.
1da177e4
LT		 786 *
787 * Return:
788 * Not Found : 0
789 * Found : 1
790 */
791static int
e315cd28 792qla2x00_eh_wait_on_command(struct scsi_cmnd *cmd)
1da177e4 793{
fe74c71f 794#define ABORT_POLLING_PERIOD 1000
478c3b03 795#define ABORT_WAIT_ITER ((2 * 1000) / (ABORT_POLLING_PERIOD))
f4f051eb 796 unsigned long wait_iter = ABORT_WAIT_ITER;
85880801
AV		 797 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
798 struct qla_hw_data *ha = vha->hw;
f4f051eb 799 int ret = QLA_SUCCESS;
1da177e4 800
85880801 801 if (unlikely(pci_channel_offline(ha->pdev)) || ha->flags.eeh_busy) {
7c3df132
SK		 802 ql_dbg(ql_dbg_taskm, vha, 0x8005,
803 "Return:eh_wait.\n");
85880801
AV		 804 return ret;
805 }
806
d970432c 807 while (CMD_SP(cmd) && wait_iter--) {
fe74c71f 808 msleep(ABORT_POLLING_PERIOD);
f4f051eb 809 }
810 if (CMD_SP(cmd))
811 ret = QLA_FUNCTION_FAILED;
1da177e4 812
f4f051eb 813 return ret;
1da177e4
LT		 814}
815
816/*
817 * qla2x00_wait_for_hba_online
fa2a1ce5 818 * Wait till the HBA is online after going through
1da177e4
LT		 819 * <= MAX_RETRIES_OF_ISP_ABORT or
820 * finally HBA is disabled ie marked offline
821 *
822 * Input:
823 * ha - pointer to host adapter structure
fa2a1ce5
AV		 824 *
825 * Note:
1da177e4
LT		 826 * Does context switching-Release SPIN_LOCK
827 * (if any) before calling this routine.
828 *
829 * Return:
830 * Success (Adapter is online) : 0
831 * Failed (Adapter is offline/disabled) : 1
832 */
854165f4 833int
e315cd28 834qla2x00_wait_for_hba_online(scsi_qla_host_t *vha)
1da177e4 835{
fca29703
AV		 836 int return_status;
837 unsigned long wait_online;
e315cd28
AC		 838 struct qla_hw_data *ha = vha->hw;
839 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4 840
fa2a1ce5 841 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ);
e315cd28
AC		 842 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
843 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
844 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
845 ha->dpc_active) && time_before(jiffies, wait_online)) {
1da177e4
LT		 846
847 msleep(1000);
848 }
e315cd28 849 if (base_vha->flags.online)
fa2a1ce5 850 return_status = QLA_SUCCESS;
1da177e4
LT		 851 else
852 return_status = QLA_FUNCTION_FAILED;
853
1da177e4
LT		 854 return (return_status);
855}
856
86fbee86 857/*
638a1a01
SC		 858 * qla2x00_wait_for_hba_ready
859 * Wait till the HBA is ready before doing driver unload
86fbee86
LC		 860 *
861 * Input:
862 * ha - pointer to host adapter structure
863 *
864 * Note:
865 * Does context switching-Release SPIN_LOCK
866 * (if any) before calling this routine.
867 *
86fbee86 868 */
638a1a01
SC		 869static void
870qla2x00_wait_for_hba_ready(scsi_qla_host_t *vha)
86fbee86 871{
86fbee86 872 struct qla_hw_data *ha = vha->hw;
86fbee86 873
9d35894d
SC		 874 while (((qla2x00_reset_active(vha)) || ha->dpc_active ||
875 ha->flags.mbox_busy) ||
876 test_bit(FX00_RESET_RECOVERY, &vha->dpc_flags) ||
877 test_bit(FX00_TARGET_SCAN, &vha->dpc_flags))
86fbee86 878 msleep(1000);
86fbee86
LC		 879}
880
2533cf67
LC		 881int
882qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha)
883{
884 int return_status;
885 unsigned long wait_reset;
886 struct qla_hw_data *ha = vha->hw;
887 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
888
889 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ);
890 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
891 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
892 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
893 ha->dpc_active) && time_before(jiffies, wait_reset)) {
894
895 msleep(1000);
896
897 if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) &&
898 ha->flags.chip_reset_done)
899 break;
900 }
901 if (ha->flags.chip_reset_done)
902 return_status = QLA_SUCCESS;
903 else
904 return_status = QLA_FUNCTION_FAILED;
905
906 return return_status;
907}
908
083a469d
GM		 909static void
910sp_get(struct srb *sp)
911{
912 atomic_inc(&sp->ref_count);
913}
914
1da177e4
LT		 915/**************************************************************************
916* qla2xxx_eh_abort
917*
918* Description:
919* The abort function will abort the specified command.
920*
921* Input:
922* cmd = Linux SCSI command packet to be aborted.
923*
924* Returns:
925* Either SUCCESS or FAILED.
926*
927* Note:
2ea00202 928* Only return FAILED if command not returned by firmware.
1da177e4 929**************************************************************************/
e5f82ab8 930static int
1da177e4
LT		 931qla2xxx_eh_abort(struct scsi_cmnd *cmd)
932{
e315cd28 933 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
f4f051eb 934 srb_t *sp;
4e98d3b8 935 int ret;
9cb78c16
HR		 936 unsigned int id;
937 uint64_t lun;
18e144d3 938 unsigned long flags;
f934c9d0 939 int rval, wait = 0;
e315cd28 940 struct qla_hw_data *ha = vha->hw;
1da177e4 941
f4f051eb 942 if (!CMD_SP(cmd))
2ea00202 943 return SUCCESS;
1da177e4 944
4e98d3b8
AV		 945 ret = fc_block_scsi_eh(cmd);
946 if (ret != 0)
947 return ret;
948 ret = SUCCESS;
949
f4f051eb 950 id = cmd->device->id;
951 lun = cmd->device->lun;
1da177e4 952
e315cd28 953 spin_lock_irqsave(&ha->hardware_lock, flags);
170babc3
MC		 954 sp = (srb_t *) CMD_SP(cmd);
955 if (!sp) {
956 spin_unlock_irqrestore(&ha->hardware_lock, flags);
957 return SUCCESS;
958 }
1da177e4 959
7c3df132 960 ql_dbg(ql_dbg_taskm, vha, 0x8002,
9cb78c16 961 "Aborting from RISC nexus=%ld:%d:%llu sp=%p cmd=%p\n",
cfb0919c 962 vha->host_no, id, lun, sp, cmd);
17d98630 963
170babc3
MC		 964 /* Get a reference to the sp and drop the lock.*/
965 sp_get(sp);
083a469d 966
e315cd28 967 spin_unlock_irqrestore(&ha->hardware_lock, flags);
f934c9d0
CD		 968 rval = ha->isp_ops->abort_command(sp);
969 if (rval) {
970 if (rval == QLA_FUNCTION_PARAMETER_ERROR) {
971 /*
972 * Decrement the ref_count since we can't find the
973 * command
974 */
975 atomic_dec(&sp->ref_count);
976 ret = SUCCESS;
977 } else
978 ret = FAILED;
979
7c3df132 980 ql_dbg(ql_dbg_taskm, vha, 0x8003,
f934c9d0 981 "Abort command mbx failed cmd=%p, rval=%x.\n", cmd, rval);
170babc3 982 } else {
7c3df132 983 ql_dbg(ql_dbg_taskm, vha, 0x8004,
cfb0919c 984 "Abort command mbx success cmd=%p.\n", cmd);
170babc3
MC		 985 wait = 1;
986 }
75942064
SK		 987
988 spin_lock_irqsave(&ha->hardware_lock, flags);
f934c9d0
CD		 989 /*
990 * Clear the slot in the oustanding_cmds array if we can't find the
991 * command to reclaim the resources.
992 */
993 if (rval == QLA_FUNCTION_PARAMETER_ERROR)
994 vha->req->outstanding_cmds[sp->handle] = NULL;
9ba56b95 995 sp->done(ha, sp, 0);
75942064 996 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1da177e4 997
bc91ade9
CD		 998 /* Did the command return during mailbox execution? */
999 if (ret == FAILED && !CMD_SP(cmd))
1000 ret = SUCCESS;
1001
f4f051eb 1002 /* Wait for the command to be returned. */
2ea00202 1003 if (wait) {
e315cd28 1004 if (qla2x00_eh_wait_on_command(cmd) != QLA_SUCCESS) {
7c3df132 1005 ql_log(ql_log_warn, vha, 0x8006,
cfb0919c 1006 "Abort handler timed out cmd=%p.\n", cmd);
2ea00202 1007 ret = FAILED;
f4f051eb 1008 }
1da177e4 1009 }
1da177e4 1010
7c3df132 1011 ql_log(ql_log_info, vha, 0x801c,
9cb78c16 1012 "Abort command issued nexus=%ld:%d:%llu -- %d %x.\n",
cfb0919c 1013 vha->host_no, id, lun, wait, ret);
1da177e4 1014
f4f051eb 1015 return ret;
1016}
1da177e4 1017
4d78c973 1018int
e315cd28 1019qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t,
9cb78c16 1020 uint64_t l, enum nexus_wait_type type)
f4f051eb 1021{
17d98630 1022 int cnt, match, status;
18e144d3 1023 unsigned long flags;
e315cd28 1024 struct qla_hw_data *ha = vha->hw;
73208dfd 1025 struct req_que *req;
4d78c973 1026 srb_t *sp;
9ba56b95 1027 struct scsi_cmnd *cmd;
1da177e4 1028
523ec773 1029 status = QLA_SUCCESS;
17d98630 1030
e315cd28 1031 spin_lock_irqsave(&ha->hardware_lock, flags);
67c2e93a 1032 req = vha->req;
17d98630 1033 for (cnt = 1; status == QLA_SUCCESS &&
8d93f550 1034 cnt < req->num_outstanding_cmds; cnt++) {
17d98630
AC		 1035 sp = req->outstanding_cmds[cnt];
1036 if (!sp)
523ec773 1037 continue;
9ba56b95 1038 if (sp->type != SRB_SCSI_CMD)
cf53b069 1039 continue;
17d98630
AC		 1040 if (vha->vp_idx != sp->fcport->vha->vp_idx)
1041 continue;
1042 match = 0;
9ba56b95 1043 cmd = GET_CMD_SP(sp);
17d98630
AC		 1044 switch (type) {
1045 case WAIT_HOST:
1046 match = 1;
1047 break;
1048 case WAIT_TARGET:
9ba56b95 1049 match = cmd->device->id == t;
17d98630
AC		 1050 break;
1051 case WAIT_LUN:
9ba56b95
GM		 1052 match = (cmd->device->id == t &&
1053 cmd->device->lun == l);
17d98630 1054 break;
73208dfd 1055 }
17d98630
AC		 1056 if (!match)
1057 continue;
1058
1059 spin_unlock_irqrestore(&ha->hardware_lock, flags);
9ba56b95 1060 status = qla2x00_eh_wait_on_command(cmd);
17d98630 1061 spin_lock_irqsave(&ha->hardware_lock, flags);
1da177e4 1062 }
e315cd28 1063 spin_unlock_irqrestore(&ha->hardware_lock, flags);
523ec773
AV		 1064
1065 return status;
1da177e4
LT		 1066}
1067
523ec773
AV		 1068static char *reset_errors[] = {
1069 "HBA not online",
1070 "HBA not ready",
1071 "Task management failed",
1072 "Waiting for command completions",
1073};
1da177e4 1074
e5f82ab8 1075static int
523ec773 1076__qla2xxx_eh_generic_reset(char *name, enum nexus_wait_type type,
9cb78c16 1077 struct scsi_cmnd *cmd, int (*do_reset)(struct fc_port *, uint64_t, int))
1da177e4 1078{
e315cd28 1079 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
bdf79621 1080 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
523ec773 1081 int err;
1da177e4 1082
7c3df132 1083 if (!fcport) {
523ec773 1084 return FAILED;
7c3df132 1085 }
1da177e4 1086
4e98d3b8
AV		 1087 err = fc_block_scsi_eh(cmd);
1088 if (err != 0)
1089 return err;
1090
7c3df132 1091 ql_log(ql_log_info, vha, 0x8009,
9cb78c16 1092 "%s RESET ISSUED nexus=%ld:%d:%llu cmd=%p.\n", name, vha->host_no,
7c3df132 1093 cmd->device->id, cmd->device->lun, cmd);
1da177e4 1094
523ec773 1095 err = 0;
7c3df132
SK		 1096 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1097 ql_log(ql_log_warn, vha, 0x800a,
1098 "Wait for hba online failed for cmd=%p.\n", cmd);
523ec773 1099 goto eh_reset_failed;
7c3df132 1100 }
523ec773 1101 err = 2;
2afa19a9 1102 if (do_reset(fcport, cmd->device->lun, cmd->request->cpu + 1)
7c3df132
SK		 1103 != QLA_SUCCESS) {
1104 ql_log(ql_log_warn, vha, 0x800c,
1105 "do_reset failed for cmd=%p.\n", cmd);
523ec773 1106 goto eh_reset_failed;
7c3df132 1107 }
523ec773 1108 err = 3;
e315cd28 1109 if (qla2x00_eh_wait_for_pending_commands(vha, cmd->device->id,
7c3df132
SK		 1110 cmd->device->lun, type) != QLA_SUCCESS) {
1111 ql_log(ql_log_warn, vha, 0x800d,
d6a03581 1112 "wait for pending cmds failed for cmd=%p.\n", cmd);
523ec773 1113 goto eh_reset_failed;
7c3df132 1114 }
523ec773 1115
7c3df132 1116 ql_log(ql_log_info, vha, 0x800e,
9cb78c16 1117 "%s RESET SUCCEEDED nexus:%ld:%d:%llu cmd=%p.\n", name,
cfb0919c 1118 vha->host_no, cmd->device->id, cmd->device->lun, cmd);
523ec773
AV		 1119
1120 return SUCCESS;
1121
4d78c973 1122eh_reset_failed:
7c3df132 1123 ql_log(ql_log_info, vha, 0x800f,
9cb78c16 1124 "%s RESET FAILED: %s nexus=%ld:%d:%llu cmd=%p.\n", name,
cfb0919c
CD		 1125 reset_errors[err], vha->host_no, cmd->device->id, cmd->device->lun,
1126 cmd);
523ec773
AV		 1127 return FAILED;
1128}
1da177e4 1129
523ec773
AV		 1130static int
1131qla2xxx_eh_device_reset(struct scsi_cmnd *cmd)
1132{
e315cd28
AC		 1133 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1134 struct qla_hw_data *ha = vha->hw;
1da177e4 1135
523ec773
AV		 1136 return __qla2xxx_eh_generic_reset("DEVICE", WAIT_LUN, cmd,
1137 ha->isp_ops->lun_reset);
1da177e4
LT		 1138}
1139
1da177e4 1140static int
523ec773 1141qla2xxx_eh_target_reset(struct scsi_cmnd *cmd)
1da177e4 1142{
e315cd28
AC		 1143 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1144 struct qla_hw_data *ha = vha->hw;
1da177e4 1145
523ec773
AV		 1146 return __qla2xxx_eh_generic_reset("TARGET", WAIT_TARGET, cmd,
1147 ha->isp_ops->target_reset);
1da177e4
LT		 1148}
1149
1da177e4
LT		 1150/**************************************************************************
1151* qla2xxx_eh_bus_reset
1152*
1153* Description:
1154* The bus reset function will reset the bus and abort any executing
1155* commands.
1156*
1157* Input:
1158* cmd = Linux SCSI command packet of the command that cause the
1159* bus reset.
1160*
1161* Returns:
1162* SUCCESS/FAILURE (defined as macro in scsi.h).
1163*
1164**************************************************************************/
e5f82ab8 1165static int
1da177e4
LT		 1166qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd)
1167{
e315cd28 1168 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
bdf79621 1169 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
2c3dfe3f 1170 int ret = FAILED;
9cb78c16
HR		 1171 unsigned int id;
1172 uint64_t lun;
f4f051eb 1173
f4f051eb 1174 id = cmd->device->id;
1175 lun = cmd->device->lun;
1da177e4 1176
7c3df132 1177 if (!fcport) {
f4f051eb 1178 return ret;
7c3df132 1179 }
1da177e4 1180
4e98d3b8
AV		 1181 ret = fc_block_scsi_eh(cmd);
1182 if (ret != 0)
1183 return ret;
1184 ret = FAILED;
1185
7c3df132 1186 ql_log(ql_log_info, vha, 0x8012,
9cb78c16 1187 "BUS RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun);
1da177e4 1188
e315cd28 1189 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
7c3df132
SK		 1190 ql_log(ql_log_fatal, vha, 0x8013,
1191 "Wait for hba online failed board disabled.\n");
f4f051eb 1192 goto eh_bus_reset_done;
1da177e4
LT		 1193 }
1194
ad537689
SK		 1195 if (qla2x00_loop_reset(vha) == QLA_SUCCESS)
1196 ret = SUCCESS;
1197
f4f051eb 1198 if (ret == FAILED)
1199 goto eh_bus_reset_done;
1da177e4 1200
9a41a62b 1201 /* Flush outstanding commands. */
4d78c973 1202 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) !=
7c3df132
SK		 1203 QLA_SUCCESS) {
1204 ql_log(ql_log_warn, vha, 0x8014,
1205 "Wait for pending commands failed.\n");
9a41a62b 1206 ret = FAILED;
7c3df132 1207 }
1da177e4 1208
f4f051eb 1209eh_bus_reset_done:
7c3df132 1210 ql_log(ql_log_warn, vha, 0x802b,
9cb78c16 1211 "BUS RESET %s nexus=%ld:%d:%llu.\n",
d6a03581 1212 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1da177e4 1213
f4f051eb 1214 return ret;
1da177e4
LT		 1215}
1216
1217/**************************************************************************
1218* qla2xxx_eh_host_reset
1219*
1220* Description:
1221* The reset function will reset the Adapter.
1222*
1223* Input:
1224* cmd = Linux SCSI command packet of the command that cause the
1225* adapter reset.
1226*
1227* Returns:
1228* Either SUCCESS or FAILED.
1229*
1230* Note:
1231**************************************************************************/
e5f82ab8 1232static int
1da177e4
LT		 1233qla2xxx_eh_host_reset(struct scsi_cmnd *cmd)
1234{
e315cd28 1235 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
e315cd28 1236 struct qla_hw_data *ha = vha->hw;
2c3dfe3f 1237 int ret = FAILED;
9cb78c16
HR		 1238 unsigned int id;
1239 uint64_t lun;
e315cd28 1240 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4 1241
f4f051eb 1242 id = cmd->device->id;
1243 lun = cmd->device->lun;
f4f051eb 1244
7c3df132 1245 ql_log(ql_log_info, vha, 0x8018,
9cb78c16 1246 "ADAPTER RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun);
1da177e4 1247
63ee7072
CD		 1248 /*
1249 * No point in issuing another reset if one is active. Also do not
1250 * attempt a reset if we are updating flash.
1251 */
1252 if (qla2x00_reset_active(vha) || ha->optrom_state != QLA_SWAITING)
f4f051eb 1253 goto eh_host_reset_lock;
1da177e4 1254
e315cd28
AC		 1255 if (vha != base_vha) {
1256 if (qla2x00_vp_abort_isp(vha))
f4f051eb 1257 goto eh_host_reset_lock;
e315cd28 1258 } else {
7ec0effd 1259 if (IS_P3P_TYPE(vha->hw)) {
a9083016
GM		 1260 if (!qla82xx_fcoe_ctx_reset(vha)) {
1261 /* Ctx reset success */
1262 ret = SUCCESS;
1263 goto eh_host_reset_lock;
1264 }
1265 /* fall thru if ctx reset failed */
1266 }
68ca949c
AC		 1267 if (ha->wq)
1268 flush_workqueue(ha->wq);
1269
e315cd28 1270 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
a9083016 1271 if (ha->isp_ops->abort_isp(base_vha)) {
e315cd28
AC		 1272 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1273 /* failed. schedule dpc to try */
1274 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
1275
7c3df132
SK		 1276 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1277 ql_log(ql_log_warn, vha, 0x802a,
1278 "wait for hba online failed.\n");
e315cd28 1279 goto eh_host_reset_lock;
7c3df132 1280 }
e315cd28
AC		 1281 }
1282 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
fa2a1ce5 1283 }
1da177e4 1284
e315cd28 1285 /* Waiting for command to be returned to OS.*/
4d78c973 1286 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) ==
e315cd28 1287 QLA_SUCCESS)
f4f051eb 1288 ret = SUCCESS;
1da177e4 1289
f4f051eb 1290eh_host_reset_lock:
cfb0919c 1291 ql_log(ql_log_info, vha, 0x8017,
9cb78c16 1292 "ADAPTER RESET %s nexus=%ld:%d:%llu.\n",
cfb0919c 1293 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1da177e4 1294
f4f051eb 1295 return ret;
1296}
1da177e4
LT		 1297
1298/*
1299* qla2x00_loop_reset
1300* Issue loop reset.
1301*
1302* Input:
1303* ha = adapter block pointer.
1304*
1305* Returns:
1306* 0 = success
1307*/
a4722cf2 1308int
e315cd28 1309qla2x00_loop_reset(scsi_qla_host_t *vha)
1da177e4 1310{
0c8c39af 1311 int ret;
bdf79621 1312 struct fc_port *fcport;
e315cd28 1313 struct qla_hw_data *ha = vha->hw;
1da177e4 1314
5854771e
AB		 1315 if (IS_QLAFX00(ha)) {
1316 return qlafx00_loop_reset(vha);
1317 }
1318
f4c496c1 1319 if (ql2xtargetreset == 1 && ha->flags.enable_target_reset) {
55e5ed27
AV		 1320 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1321 if (fcport->port_type != FCT_TARGET)
1322 continue;
1323
1324 ret = ha->isp_ops->target_reset(fcport, 0, 0);
1325 if (ret != QLA_SUCCESS) {
7c3df132 1326 ql_dbg(ql_dbg_taskm, vha, 0x802c,
5854771e 1327 "Bus Reset failed: Reset=%d "
7c3df132 1328 "d_id=%x.\n", ret, fcport->d_id.b24);
55e5ed27
AV		 1329 }
1330 }
1331 }
1332
8ae6d9c7 1333
6246b8a1 1334 if (ha->flags.enable_lip_full_login && !IS_CNA_CAPABLE(ha)) {
0b7e7c53
AV		 1335 atomic_set(&vha->loop_state, LOOP_DOWN);
1336 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
1337 qla2x00_mark_all_devices_lost(vha, 0);
e315cd28 1338 ret = qla2x00_full_login_lip(vha);
0c8c39af 1339 if (ret != QLA_SUCCESS) {
7c3df132
SK		 1340 ql_dbg(ql_dbg_taskm, vha, 0x802d,
1341 "full_login_lip=%d.\n", ret);
749af3d5 1342 }
0c8c39af
AV		 1343 }
1344
0d6e61bc 1345 if (ha->flags.enable_lip_reset) {
e315cd28 1346 ret = qla2x00_lip_reset(vha);
ad537689 1347 if (ret != QLA_SUCCESS)
7c3df132
SK		 1348 ql_dbg(ql_dbg_taskm, vha, 0x802e,
1349 "lip_reset failed (%d).\n", ret);
1da177e4
LT		 1350 }
1351
1da177e4 1352 /* Issue marker command only when we are going to start the I/O */
e315cd28 1353 vha->marker_needed = 1;
1da177e4 1354
0c8c39af 1355 return QLA_SUCCESS;
1da177e4
LT		 1356}
1357
df4bf0bb 1358void
e315cd28 1359qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res)
df4bf0bb 1360{
73208dfd 1361 int que, cnt;
df4bf0bb
AV		 1362 unsigned long flags;
1363 srb_t *sp;
e315cd28 1364 struct qla_hw_data *ha = vha->hw;
73208dfd 1365 struct req_que *req;
df4bf0bb 1366
c0cb4496
AE		 1367 qlt_host_reset_handler(ha);
1368
df4bf0bb 1369 spin_lock_irqsave(&ha->hardware_lock, flags);
2afa19a9 1370 for (que = 0; que < ha->max_req_queues; que++) {
29bdccbe 1371 req = ha->req_q_map[que];
73208dfd
AC		 1372 if (!req)
1373 continue;
8d93f550
CD		 1374 if (!req->outstanding_cmds)
1375 continue;
1376 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) {
73208dfd 1377 sp = req->outstanding_cmds[cnt];
e612d465 1378 if (sp) {
73208dfd 1379 req->outstanding_cmds[cnt] = NULL;
9ba56b95 1380 sp->done(vha, sp, res);
73208dfd 1381 }
df4bf0bb
AV		 1382 }
1383 }
1384 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1385}
1386
f4f051eb 1387static int
1388qla2xxx_slave_alloc(struct scsi_device *sdev)
1da177e4 1389{
bdf79621 1390 struct fc_rport *rport = starget_to_rport(scsi_target(sdev));
1da177e4 1391
19a7b4ae 1392 if (!rport || fc_remote_port_chkready(rport))
f4f051eb 1393 return -ENXIO;
bdf79621 1394
19a7b4ae 1395 sdev->hostdata = *(fc_port_t **)rport->dd_data;
1da177e4 1396
f4f051eb 1397 return 0;
1398}
1da177e4 1399
f4f051eb 1400static int
1401qla2xxx_slave_configure(struct scsi_device *sdev)
1402{
e315cd28 1403 scsi_qla_host_t *vha = shost_priv(sdev->host);
2afa19a9 1404 struct req_que *req = vha->req;
8482e118 1405
9e522cd8
AE		 1406 if (IS_T10_PI_CAPABLE(vha->hw))
1407 blk_queue_update_dma_alignment(sdev->request_queue, 0x7);
1408
db5ed4df 1409 scsi_change_queue_depth(sdev, req->max_q_depth);
f4f051eb 1410 return 0;
1411}
1da177e4 1412
f4f051eb 1413static void
1414qla2xxx_slave_destroy(struct scsi_device *sdev)
1415{
1416 sdev->hostdata = NULL;
1da177e4
LT		 1417}
1418
1419/**
1420 * qla2x00_config_dma_addressing() - Configure OS DMA addressing method.
1421 * @ha: HA context
1422 *
1423 * At exit, the @ha's flags.enable_64bit_addressing set to indicated
1424 * supported addressing method.
1425 */
1426static void
53303c42 1427qla2x00_config_dma_addressing(struct qla_hw_data *ha)
1da177e4 1428{
7524f9b9 1429 /* Assume a 32bit DMA mask. */
1da177e4 1430 ha->flags.enable_64bit_addressing = 0;
1da177e4 1431
6a35528a 1432 if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) {
7524f9b9
AV		 1433 /* Any upper-dword bits set? */
1434 if (MSD(dma_get_required_mask(&ha->pdev->dev)) &&
6a35528a 1435 !pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(64))) {
7524f9b9 1436 /* Ok, a 64bit DMA mask is applicable. */
1da177e4 1437 ha->flags.enable_64bit_addressing = 1;
fd34f556
AV		 1438 ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64;
1439 ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64;
7524f9b9 1440 return;
1da177e4 1441 }
1da177e4 1442 }
7524f9b9 1443
284901a9
YH		 1444 dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32));
1445 pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(32));
1da177e4
LT		 1446}
1447
fd34f556 1448static void
e315cd28 1449qla2x00_enable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1450{
1451 unsigned long flags = 0;
1452 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1453
1454 spin_lock_irqsave(&ha->hardware_lock, flags);
1455 ha->interrupts_on = 1;
1456 /* enable risc and host interrupts */
1457 WRT_REG_WORD(&reg->ictrl, ICR_EN_INT | ICR_EN_RISC);
1458 RD_REG_WORD(&reg->ictrl);
1459 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1460
1461}
1462
1463static void
e315cd28 1464qla2x00_disable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1465{
1466 unsigned long flags = 0;
1467 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1468
1469 spin_lock_irqsave(&ha->hardware_lock, flags);
1470 ha->interrupts_on = 0;
1471 /* disable risc and host interrupts */
1472 WRT_REG_WORD(&reg->ictrl, 0);
1473 RD_REG_WORD(&reg->ictrl);
1474 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1475}
1476
1477static void
e315cd28 1478qla24xx_enable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1479{
1480 unsigned long flags = 0;
1481 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1482
1483 spin_lock_irqsave(&ha->hardware_lock, flags);
1484 ha->interrupts_on = 1;
1485 WRT_REG_DWORD(&reg->ictrl, ICRX_EN_RISC_INT);
1486 RD_REG_DWORD(&reg->ictrl);
1487 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1488}
1489
1490static void
e315cd28 1491qla24xx_disable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1492{
1493 unsigned long flags = 0;
1494 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1495
124f85e6
AV		 1496 if (IS_NOPOLLING_TYPE(ha))
1497 return;
fd34f556
AV		 1498 spin_lock_irqsave(&ha->hardware_lock, flags);
1499 ha->interrupts_on = 0;
1500 WRT_REG_DWORD(&reg->ictrl, 0);
1501 RD_REG_DWORD(&reg->ictrl);
1502 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1503}
1504
706f457d
GM		 1505static int
1506qla2x00_iospace_config(struct qla_hw_data *ha)
1507{
1508 resource_size_t pio;
1509 uint16_t msix;
1510 int cpus;
1511
706f457d
GM		 1512 if (pci_request_selected_regions(ha->pdev, ha->bars,
1513 QLA2XXX_DRIVER_NAME)) {
1514 ql_log_pci(ql_log_fatal, ha->pdev, 0x0011,
1515 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
1516 pci_name(ha->pdev));
1517 goto iospace_error_exit;
1518 }
1519 if (!(ha->bars & 1))
1520 goto skip_pio;
1521
1522 /* We only need PIO for Flash operations on ISP2312 v2 chips. */
1523 pio = pci_resource_start(ha->pdev, 0);
1524 if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) {
1525 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
1526 ql_log_pci(ql_log_warn, ha->pdev, 0x0012,
1527 "Invalid pci I/O region size (%s).\n",
1528 pci_name(ha->pdev));
1529 pio = 0;
1530 }
1531 } else {
1532 ql_log_pci(ql_log_warn, ha->pdev, 0x0013,
1533 "Region #0 no a PIO resource (%s).\n",
1534 pci_name(ha->pdev));
1535 pio = 0;
1536 }
1537 ha->pio_address = pio;
1538 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014,
1539 "PIO address=%llu.\n",
1540 (unsigned long long)ha->pio_address);
1541
1542skip_pio:
1543 /* Use MMIO operations for all accesses. */
1544 if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) {
1545 ql_log_pci(ql_log_fatal, ha->pdev, 0x0015,
1546 "Region #1 not an MMIO resource (%s), aborting.\n",
1547 pci_name(ha->pdev));
1548 goto iospace_error_exit;
1549 }
1550 if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) {
1551 ql_log_pci(ql_log_fatal, ha->pdev, 0x0016,
1552 "Invalid PCI mem region size (%s), aborting.\n",
1553 pci_name(ha->pdev));
1554 goto iospace_error_exit;
1555 }
1556
1557 ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN);
1558 if (!ha->iobase) {
1559 ql_log_pci(ql_log_fatal, ha->pdev, 0x0017,
1560 "Cannot remap MMIO (%s), aborting.\n",
1561 pci_name(ha->pdev));
1562 goto iospace_error_exit;
1563 }
1564
1565 /* Determine queue resources */
1566 ha->max_req_queues = ha->max_rsp_queues = 1;
1567 if ((ql2xmaxqueues <= 1 && !ql2xmultique_tag) ||
1568 (ql2xmaxqueues > 1 && ql2xmultique_tag) ||
1569 (!IS_QLA25XX(ha) && !IS_QLA81XX(ha)))
1570 goto mqiobase_exit;
1571
1572 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3),
1573 pci_resource_len(ha->pdev, 3));
1574 if (ha->mqiobase) {
1575 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018,
1576 "MQIO Base=%p.\n", ha->mqiobase);
1577 /* Read MSIX vector size of the board */
1578 pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix);
1579 ha->msix_count = msix;
1580 /* Max queues are bounded by available msix vectors */
1581 /* queue 0 uses two msix vectors */
1582 if (ql2xmultique_tag) {
1583 cpus = num_online_cpus();
1584 ha->max_rsp_queues = (ha->msix_count - 1 > cpus) ?
1585 (cpus + 1) : (ha->msix_count - 1);
1586 ha->max_req_queues = 2;
1587 } else if (ql2xmaxqueues > 1) {
1588 ha->max_req_queues = ql2xmaxqueues > QLA_MQ_SIZE ?
1589 QLA_MQ_SIZE : ql2xmaxqueues;
1590 ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc008,
1591 "QoS mode set, max no of request queues:%d.\n",
1592 ha->max_req_queues);
1593 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0019,
1594 "QoS mode set, max no of request queues:%d.\n",
1595 ha->max_req_queues);
1596 }
1597 ql_log_pci(ql_log_info, ha->pdev, 0x001a,
1598 "MSI-X vector count: %d.\n", msix);
1599 } else
1600 ql_log_pci(ql_log_info, ha->pdev, 0x001b,
1601 "BAR 3 not enabled.\n");
1602
1603mqiobase_exit:
1604 ha->msix_count = ha->max_rsp_queues + 1;
1605 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c,
1606 "MSIX Count:%d.\n", ha->msix_count);
1607 return (0);
1608
1609iospace_error_exit:
1610 return (-ENOMEM);
1611}
1612
1613
6246b8a1
GM		 1614static int
1615qla83xx_iospace_config(struct qla_hw_data *ha)
1616{
1617 uint16_t msix;
1618 int cpus;
1619
1620 if (pci_request_selected_regions(ha->pdev, ha->bars,
1621 QLA2XXX_DRIVER_NAME)) {
1622 ql_log_pci(ql_log_fatal, ha->pdev, 0x0117,
1623 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
1624 pci_name(ha->pdev));
1625
1626 goto iospace_error_exit;
1627 }
1628
1629 /* Use MMIO operations for all accesses. */
1630 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) {
1631 ql_log_pci(ql_log_warn, ha->pdev, 0x0118,
1632 "Invalid pci I/O region size (%s).\n",
1633 pci_name(ha->pdev));
1634 goto iospace_error_exit;
1635 }
1636 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
1637 ql_log_pci(ql_log_warn, ha->pdev, 0x0119,
1638 "Invalid PCI mem region size (%s), aborting\n",
1639 pci_name(ha->pdev));
1640 goto iospace_error_exit;
1641 }
1642
1643 ha->iobase = ioremap(pci_resource_start(ha->pdev, 0), MIN_IOBASE_LEN);
1644 if (!ha->iobase) {
1645 ql_log_pci(ql_log_fatal, ha->pdev, 0x011a,
1646 "Cannot remap MMIO (%s), aborting.\n",
1647 pci_name(ha->pdev));
1648 goto iospace_error_exit;
1649 }
1650
1651 /* 64bit PCI BAR - BAR2 will correspoond to region 4 */
1652 /* 83XX 26XX always use MQ type access for queues
1653 * - mbar 2, a.k.a region 4 */
1654 ha->max_req_queues = ha->max_rsp_queues = 1;
1655 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 4),
1656 pci_resource_len(ha->pdev, 4));
1657
1658 if (!ha->mqiobase) {
1659 ql_log_pci(ql_log_fatal, ha->pdev, 0x011d,
1660 "BAR2/region4 not enabled\n");
1661 goto mqiobase_exit;
1662 }
1663
1664 ha->msixbase = ioremap(pci_resource_start(ha->pdev, 2),
1665 pci_resource_len(ha->pdev, 2));
1666 if (ha->msixbase) {
1667 /* Read MSIX vector size of the board */
1668 pci_read_config_word(ha->pdev,
1669 QLA_83XX_PCI_MSIX_CONTROL, &msix);
1670 ha->msix_count = msix;
1671 /* Max queues are bounded by available msix vectors */
1672 /* queue 0 uses two msix vectors */
1673 if (ql2xmultique_tag) {
1674 cpus = num_online_cpus();
1675 ha->max_rsp_queues = (ha->msix_count - 1 > cpus) ?
1676 (cpus + 1) : (ha->msix_count - 1);
1677 ha->max_req_queues = 2;
1678 } else if (ql2xmaxqueues > 1) {
1679 ha->max_req_queues = ql2xmaxqueues > QLA_MQ_SIZE ?
1680 QLA_MQ_SIZE : ql2xmaxqueues;
1681 ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc00c,
1682 "QoS mode set, max no of request queues:%d.\n",
1683 ha->max_req_queues);
1684 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b,
1685 "QoS mode set, max no of request queues:%d.\n",
1686 ha->max_req_queues);
1687 }
1688 ql_log_pci(ql_log_info, ha->pdev, 0x011c,
1689 "MSI-X vector count: %d.\n", msix);
1690 } else
1691 ql_log_pci(ql_log_info, ha->pdev, 0x011e,
1692 "BAR 1 not enabled.\n");
1693
1694mqiobase_exit:
1695 ha->msix_count = ha->max_rsp_queues + 1;
aa230bc5
AE		 1696
1697 qlt_83xx_iospace_config(ha);
1698
6246b8a1
GM		 1699 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011f,
1700 "MSIX Count:%d.\n", ha->msix_count);
1701 return 0;
1702
1703iospace_error_exit:
1704 return -ENOMEM;
1705}
1706
fd34f556
AV		 1707static struct isp_operations qla2100_isp_ops = {
1708 .pci_config = qla2100_pci_config,
1709 .reset_chip = qla2x00_reset_chip,
1710 .chip_diag = qla2x00_chip_diag,
1711 .config_rings = qla2x00_config_rings,
1712 .reset_adapter = qla2x00_reset_adapter,
1713 .nvram_config = qla2x00_nvram_config,
1714 .update_fw_options = qla2x00_update_fw_options,
1715 .load_risc = qla2x00_load_risc,
1716 .pci_info_str = qla2x00_pci_info_str,
1717 .fw_version_str = qla2x00_fw_version_str,
1718 .intr_handler = qla2100_intr_handler,
1719 .enable_intrs = qla2x00_enable_intrs,
1720 .disable_intrs = qla2x00_disable_intrs,
1721 .abort_command = qla2x00_abort_command,
523ec773
AV		 1722 .target_reset = qla2x00_abort_target,
1723 .lun_reset = qla2x00_lun_reset,
fd34f556
AV		 1724 .fabric_login = qla2x00_login_fabric,
1725 .fabric_logout = qla2x00_fabric_logout,
1726 .calc_req_entries = qla2x00_calc_iocbs_32,
1727 .build_iocbs = qla2x00_build_scsi_iocbs_32,
1728 .prep_ms_iocb = qla2x00_prep_ms_iocb,
1729 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
1730 .read_nvram = qla2x00_read_nvram_data,
1731 .write_nvram = qla2x00_write_nvram_data,
1732 .fw_dump = qla2100_fw_dump,
1733 .beacon_on = NULL,
1734 .beacon_off = NULL,
1735 .beacon_blink = NULL,
1736 .read_optrom = qla2x00_read_optrom_data,
1737 .write_optrom = qla2x00_write_optrom_data,
1738 .get_flash_version = qla2x00_get_flash_version,
e315cd28 1739 .start_scsi = qla2x00_start_scsi,
a9083016 1740 .abort_isp = qla2x00_abort_isp,
706f457d 1741 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 1742 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 1743};
1744
1745static struct isp_operations qla2300_isp_ops = {
1746 .pci_config = qla2300_pci_config,
1747 .reset_chip = qla2x00_reset_chip,
1748 .chip_diag = qla2x00_chip_diag,
1749 .config_rings = qla2x00_config_rings,
1750 .reset_adapter = qla2x00_reset_adapter,
1751 .nvram_config = qla2x00_nvram_config,
1752 .update_fw_options = qla2x00_update_fw_options,
1753 .load_risc = qla2x00_load_risc,
1754 .pci_info_str = qla2x00_pci_info_str,
1755 .fw_version_str = qla2x00_fw_version_str,
1756 .intr_handler = qla2300_intr_handler,
1757 .enable_intrs = qla2x00_enable_intrs,
1758 .disable_intrs = qla2x00_disable_intrs,
1759 .abort_command = qla2x00_abort_command,
523ec773
AV		 1760 .target_reset = qla2x00_abort_target,
1761 .lun_reset = qla2x00_lun_reset,
fd34f556
AV		 1762 .fabric_login = qla2x00_login_fabric,
1763 .fabric_logout = qla2x00_fabric_logout,
1764 .calc_req_entries = qla2x00_calc_iocbs_32,
1765 .build_iocbs = qla2x00_build_scsi_iocbs_32,
1766 .prep_ms_iocb = qla2x00_prep_ms_iocb,
1767 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
1768 .read_nvram = qla2x00_read_nvram_data,
1769 .write_nvram = qla2x00_write_nvram_data,
1770 .fw_dump = qla2300_fw_dump,
1771 .beacon_on = qla2x00_beacon_on,
1772 .beacon_off = qla2x00_beacon_off,
1773 .beacon_blink = qla2x00_beacon_blink,
1774 .read_optrom = qla2x00_read_optrom_data,
1775 .write_optrom = qla2x00_write_optrom_data,
1776 .get_flash_version = qla2x00_get_flash_version,
e315cd28 1777 .start_scsi = qla2x00_start_scsi,
a9083016 1778 .abort_isp = qla2x00_abort_isp,
7ec0effd 1779 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 1780 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 1781};
1782
1783static struct isp_operations qla24xx_isp_ops = {
1784 .pci_config = qla24xx_pci_config,
1785 .reset_chip = qla24xx_reset_chip,
1786 .chip_diag = qla24xx_chip_diag,
1787 .config_rings = qla24xx_config_rings,
1788 .reset_adapter = qla24xx_reset_adapter,
1789 .nvram_config = qla24xx_nvram_config,
1790 .update_fw_options = qla24xx_update_fw_options,
1791 .load_risc = qla24xx_load_risc,
1792 .pci_info_str = qla24xx_pci_info_str,
1793 .fw_version_str = qla24xx_fw_version_str,
1794 .intr_handler = qla24xx_intr_handler,
1795 .enable_intrs = qla24xx_enable_intrs,
1796 .disable_intrs = qla24xx_disable_intrs,
1797 .abort_command = qla24xx_abort_command,
523ec773
AV		 1798 .target_reset = qla24xx_abort_target,
1799 .lun_reset = qla24xx_lun_reset,
fd34f556
AV		 1800 .fabric_login = qla24xx_login_fabric,
1801 .fabric_logout = qla24xx_fabric_logout,
1802 .calc_req_entries = NULL,
1803 .build_iocbs = NULL,
1804 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1805 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1806 .read_nvram = qla24xx_read_nvram_data,
1807 .write_nvram = qla24xx_write_nvram_data,
1808 .fw_dump = qla24xx_fw_dump,
1809 .beacon_on = qla24xx_beacon_on,
1810 .beacon_off = qla24xx_beacon_off,
1811 .beacon_blink = qla24xx_beacon_blink,
1812 .read_optrom = qla24xx_read_optrom_data,
1813 .write_optrom = qla24xx_write_optrom_data,
1814 .get_flash_version = qla24xx_get_flash_version,
e315cd28 1815 .start_scsi = qla24xx_start_scsi,
a9083016 1816 .abort_isp = qla2x00_abort_isp,
7ec0effd 1817 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 1818 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 1819};
1820
c3a2f0df
AV		 1821static struct isp_operations qla25xx_isp_ops = {
1822 .pci_config = qla25xx_pci_config,
1823 .reset_chip = qla24xx_reset_chip,
1824 .chip_diag = qla24xx_chip_diag,
1825 .config_rings = qla24xx_config_rings,
1826 .reset_adapter = qla24xx_reset_adapter,
1827 .nvram_config = qla24xx_nvram_config,
1828 .update_fw_options = qla24xx_update_fw_options,
1829 .load_risc = qla24xx_load_risc,
1830 .pci_info_str = qla24xx_pci_info_str,
1831 .fw_version_str = qla24xx_fw_version_str,
1832 .intr_handler = qla24xx_intr_handler,
1833 .enable_intrs = qla24xx_enable_intrs,
1834 .disable_intrs = qla24xx_disable_intrs,
1835 .abort_command = qla24xx_abort_command,
523ec773
AV		 1836 .target_reset = qla24xx_abort_target,
1837 .lun_reset = qla24xx_lun_reset,
c3a2f0df
AV		 1838 .fabric_login = qla24xx_login_fabric,
1839 .fabric_logout = qla24xx_fabric_logout,
1840 .calc_req_entries = NULL,
1841 .build_iocbs = NULL,
1842 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1843 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1844 .read_nvram = qla25xx_read_nvram_data,
1845 .write_nvram = qla25xx_write_nvram_data,
1846 .fw_dump = qla25xx_fw_dump,
1847 .beacon_on = qla24xx_beacon_on,
1848 .beacon_off = qla24xx_beacon_off,
1849 .beacon_blink = qla24xx_beacon_blink,
338c9161 1850 .read_optrom = qla25xx_read_optrom_data,
c3a2f0df
AV		 1851 .write_optrom = qla24xx_write_optrom_data,
1852 .get_flash_version = qla24xx_get_flash_version,
bad75002 1853 .start_scsi = qla24xx_dif_start_scsi,
a9083016 1854 .abort_isp = qla2x00_abort_isp,
7ec0effd 1855 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 1856 .initialize_adapter = qla2x00_initialize_adapter,
c3a2f0df
AV		 1857};
1858
3a03eb79
AV		 1859static struct isp_operations qla81xx_isp_ops = {
1860 .pci_config = qla25xx_pci_config,
1861 .reset_chip = qla24xx_reset_chip,
1862 .chip_diag = qla24xx_chip_diag,
1863 .config_rings = qla24xx_config_rings,
1864 .reset_adapter = qla24xx_reset_adapter,
1865 .nvram_config = qla81xx_nvram_config,
1866 .update_fw_options = qla81xx_update_fw_options,
eaac30be 1867 .load_risc = qla81xx_load_risc,
3a03eb79
AV		 1868 .pci_info_str = qla24xx_pci_info_str,
1869 .fw_version_str = qla24xx_fw_version_str,
1870 .intr_handler = qla24xx_intr_handler,
1871 .enable_intrs = qla24xx_enable_intrs,
1872 .disable_intrs = qla24xx_disable_intrs,
1873 .abort_command = qla24xx_abort_command,
1874 .target_reset = qla24xx_abort_target,
1875 .lun_reset = qla24xx_lun_reset,
1876 .fabric_login = qla24xx_login_fabric,
1877 .fabric_logout = qla24xx_fabric_logout,
1878 .calc_req_entries = NULL,
1879 .build_iocbs = NULL,
1880 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1881 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
3d79038f
AV		 1882 .read_nvram = NULL,
1883 .write_nvram = NULL,
3a03eb79
AV		 1884 .fw_dump = qla81xx_fw_dump,
1885 .beacon_on = qla24xx_beacon_on,
1886 .beacon_off = qla24xx_beacon_off,
6246b8a1 1887 .beacon_blink = qla83xx_beacon_blink,
3a03eb79
AV		 1888 .read_optrom = qla25xx_read_optrom_data,
1889 .write_optrom = qla24xx_write_optrom_data,
1890 .get_flash_version = qla24xx_get_flash_version,
ba77ef53 1891 .start_scsi = qla24xx_dif_start_scsi,
a9083016 1892 .abort_isp = qla2x00_abort_isp,
7ec0effd 1893 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 1894 .initialize_adapter = qla2x00_initialize_adapter,
a9083016
GM		 1895};
1896
1897static struct isp_operations qla82xx_isp_ops = {
1898 .pci_config = qla82xx_pci_config,
1899 .reset_chip = qla82xx_reset_chip,
1900 .chip_diag = qla24xx_chip_diag,
1901 .config_rings = qla82xx_config_rings,
1902 .reset_adapter = qla24xx_reset_adapter,
1903 .nvram_config = qla81xx_nvram_config,
1904 .update_fw_options = qla24xx_update_fw_options,
1905 .load_risc = qla82xx_load_risc,
9d55ca66 1906 .pci_info_str = qla24xx_pci_info_str,
a9083016
GM		 1907 .fw_version_str = qla24xx_fw_version_str,
1908 .intr_handler = qla82xx_intr_handler,
1909 .enable_intrs = qla82xx_enable_intrs,
1910 .disable_intrs = qla82xx_disable_intrs,
1911 .abort_command = qla24xx_abort_command,
1912 .target_reset = qla24xx_abort_target,
1913 .lun_reset = qla24xx_lun_reset,
1914 .fabric_login = qla24xx_login_fabric,
1915 .fabric_logout = qla24xx_fabric_logout,
1916 .calc_req_entries = NULL,
1917 .build_iocbs = NULL,
1918 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1919 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1920 .read_nvram = qla24xx_read_nvram_data,
1921 .write_nvram = qla24xx_write_nvram_data,
a1b23c5a 1922 .fw_dump = qla82xx_fw_dump,
999916dc
SK		 1923 .beacon_on = qla82xx_beacon_on,
1924 .beacon_off = qla82xx_beacon_off,
1925 .beacon_blink = NULL,
a9083016
GM		 1926 .read_optrom = qla82xx_read_optrom_data,
1927 .write_optrom = qla82xx_write_optrom_data,
7ec0effd 1928 .get_flash_version = qla82xx_get_flash_version,
a9083016
GM		 1929 .start_scsi = qla82xx_start_scsi,
1930 .abort_isp = qla82xx_abort_isp,
706f457d 1931 .iospace_config = qla82xx_iospace_config,
8ae6d9c7 1932 .initialize_adapter = qla2x00_initialize_adapter,
3a03eb79
AV		 1933};
1934
7ec0effd
AD		 1935static struct isp_operations qla8044_isp_ops = {
1936 .pci_config = qla82xx_pci_config,
1937 .reset_chip = qla82xx_reset_chip,
1938 .chip_diag = qla24xx_chip_diag,
1939 .config_rings = qla82xx_config_rings,
1940 .reset_adapter = qla24xx_reset_adapter,
1941 .nvram_config = qla81xx_nvram_config,
1942 .update_fw_options = qla24xx_update_fw_options,
1943 .load_risc = qla82xx_load_risc,
1944 .pci_info_str = qla24xx_pci_info_str,
1945 .fw_version_str = qla24xx_fw_version_str,
1946 .intr_handler = qla8044_intr_handler,
1947 .enable_intrs = qla82xx_enable_intrs,
1948 .disable_intrs = qla82xx_disable_intrs,
1949 .abort_command = qla24xx_abort_command,
1950 .target_reset = qla24xx_abort_target,
1951 .lun_reset = qla24xx_lun_reset,
1952 .fabric_login = qla24xx_login_fabric,
1953 .fabric_logout = qla24xx_fabric_logout,
1954 .calc_req_entries = NULL,
1955 .build_iocbs = NULL,
1956 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1957 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1958 .read_nvram = NULL,
1959 .write_nvram = NULL,
a1b23c5a 1960 .fw_dump = qla8044_fw_dump,
7ec0effd
AD		 1961 .beacon_on = qla82xx_beacon_on,
1962 .beacon_off = qla82xx_beacon_off,
1963 .beacon_blink = NULL,
888e639d 1964 .read_optrom = qla8044_read_optrom_data,
7ec0effd
AD		 1965 .write_optrom = qla8044_write_optrom_data,
1966 .get_flash_version = qla82xx_get_flash_version,
1967 .start_scsi = qla82xx_start_scsi,
1968 .abort_isp = qla8044_abort_isp,
1969 .iospace_config = qla82xx_iospace_config,
1970 .initialize_adapter = qla2x00_initialize_adapter,
1971};
1972
6246b8a1
GM		 1973static struct isp_operations qla83xx_isp_ops = {
1974 .pci_config = qla25xx_pci_config,
1975 .reset_chip = qla24xx_reset_chip,
1976 .chip_diag = qla24xx_chip_diag,
1977 .config_rings = qla24xx_config_rings,
1978 .reset_adapter = qla24xx_reset_adapter,
1979 .nvram_config = qla81xx_nvram_config,
1980 .update_fw_options = qla81xx_update_fw_options,
1981 .load_risc = qla81xx_load_risc,
1982 .pci_info_str = qla24xx_pci_info_str,
1983 .fw_version_str = qla24xx_fw_version_str,
1984 .intr_handler = qla24xx_intr_handler,
1985 .enable_intrs = qla24xx_enable_intrs,
1986 .disable_intrs = qla24xx_disable_intrs,
1987 .abort_command = qla24xx_abort_command,
1988 .target_reset = qla24xx_abort_target,
1989 .lun_reset = qla24xx_lun_reset,
1990 .fabric_login = qla24xx_login_fabric,
1991 .fabric_logout = qla24xx_fabric_logout,
1992 .calc_req_entries = NULL,
1993 .build_iocbs = NULL,
1994 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1995 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1996 .read_nvram = NULL,
1997 .write_nvram = NULL,
1998 .fw_dump = qla83xx_fw_dump,
1999 .beacon_on = qla24xx_beacon_on,
2000 .beacon_off = qla24xx_beacon_off,
2001 .beacon_blink = qla83xx_beacon_blink,
2002 .read_optrom = qla25xx_read_optrom_data,
2003 .write_optrom = qla24xx_write_optrom_data,
2004 .get_flash_version = qla24xx_get_flash_version,
2005 .start_scsi = qla24xx_dif_start_scsi,
2006 .abort_isp = qla2x00_abort_isp,
2007 .iospace_config = qla83xx_iospace_config,
8ae6d9c7
GM		 2008 .initialize_adapter = qla2x00_initialize_adapter,
2009};
2010
2011static struct isp_operations qlafx00_isp_ops = {
2012 .pci_config = qlafx00_pci_config,
2013 .reset_chip = qlafx00_soft_reset,
2014 .chip_diag = qlafx00_chip_diag,
2015 .config_rings = qlafx00_config_rings,
2016 .reset_adapter = qlafx00_soft_reset,
2017 .nvram_config = NULL,
2018 .update_fw_options = NULL,
2019 .load_risc = NULL,
2020 .pci_info_str = qlafx00_pci_info_str,
2021 .fw_version_str = qlafx00_fw_version_str,
2022 .intr_handler = qlafx00_intr_handler,
2023 .enable_intrs = qlafx00_enable_intrs,
2024 .disable_intrs = qlafx00_disable_intrs,
4440e46d 2025 .abort_command = qla24xx_async_abort_command,
8ae6d9c7
GM		 2026 .target_reset = qlafx00_abort_target,
2027 .lun_reset = qlafx00_lun_reset,
2028 .fabric_login = NULL,
2029 .fabric_logout = NULL,
2030 .calc_req_entries = NULL,
2031 .build_iocbs = NULL,
2032 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2033 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2034 .read_nvram = qla24xx_read_nvram_data,
2035 .write_nvram = qla24xx_write_nvram_data,
2036 .fw_dump = NULL,
2037 .beacon_on = qla24xx_beacon_on,
2038 .beacon_off = qla24xx_beacon_off,
2039 .beacon_blink = NULL,
2040 .read_optrom = qla24xx_read_optrom_data,
2041 .write_optrom = qla24xx_write_optrom_data,
2042 .get_flash_version = qla24xx_get_flash_version,
2043 .start_scsi = qlafx00_start_scsi,
2044 .abort_isp = qlafx00_abort_isp,
2045 .iospace_config = qlafx00_iospace_config,
2046 .initialize_adapter = qlafx00_initialize_adapter,
6246b8a1
GM		 2047};
2048
f73cb695
CD		 2049static struct isp_operations qla27xx_isp_ops = {
2050 .pci_config = qla25xx_pci_config,
2051 .reset_chip = qla24xx_reset_chip,
2052 .chip_diag = qla24xx_chip_diag,
2053 .config_rings = qla24xx_config_rings,
2054 .reset_adapter = qla24xx_reset_adapter,
2055 .nvram_config = qla81xx_nvram_config,
2056 .update_fw_options = qla81xx_update_fw_options,
2057 .load_risc = qla81xx_load_risc,
2058 .pci_info_str = qla24xx_pci_info_str,
2059 .fw_version_str = qla24xx_fw_version_str,
2060 .intr_handler = qla24xx_intr_handler,
2061 .enable_intrs = qla24xx_enable_intrs,
2062 .disable_intrs = qla24xx_disable_intrs,
2063 .abort_command = qla24xx_abort_command,
2064 .target_reset = qla24xx_abort_target,
2065 .lun_reset = qla24xx_lun_reset,
2066 .fabric_login = qla24xx_login_fabric,
2067 .fabric_logout = qla24xx_fabric_logout,
2068 .calc_req_entries = NULL,
2069 .build_iocbs = NULL,
2070 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2071 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2072 .read_nvram = NULL,
2073 .write_nvram = NULL,
2074 .fw_dump = qla27xx_fwdump,
2075 .beacon_on = qla24xx_beacon_on,
2076 .beacon_off = qla24xx_beacon_off,
2077 .beacon_blink = qla83xx_beacon_blink,
2078 .read_optrom = qla25xx_read_optrom_data,
2079 .write_optrom = qla24xx_write_optrom_data,
2080 .get_flash_version = qla24xx_get_flash_version,
2081 .start_scsi = qla24xx_dif_start_scsi,
2082 .abort_isp = qla2x00_abort_isp,
2083 .iospace_config = qla83xx_iospace_config,
2084 .initialize_adapter = qla2x00_initialize_adapter,
2085};
2086
ea5b6382 2087static inline void
e315cd28 2088qla2x00_set_isp_flags(struct qla_hw_data *ha)
ea5b6382 2089{
2090 ha->device_type = DT_EXTENDED_IDS;
2091 switch (ha->pdev->device) {
2092 case PCI_DEVICE_ID_QLOGIC_ISP2100:
2093 ha->device_type |= DT_ISP2100;
2094 ha->device_type &= ~DT_EXTENDED_IDS;
441d1072 2095 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
ea5b6382 2096 break;
2097 case PCI_DEVICE_ID_QLOGIC_ISP2200:
2098 ha->device_type |= DT_ISP2200;
2099 ha->device_type &= ~DT_EXTENDED_IDS;
441d1072 2100 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
ea5b6382 2101 break;
2102 case PCI_DEVICE_ID_QLOGIC_ISP2300:
2103 ha->device_type |= DT_ISP2300;
4a59f71d 2104 ha->device_type |= DT_ZIO_SUPPORTED;
441d1072 2105 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 2106 break;
2107 case PCI_DEVICE_ID_QLOGIC_ISP2312:
2108 ha->device_type |= DT_ISP2312;
4a59f71d 2109 ha->device_type |= DT_ZIO_SUPPORTED;
441d1072 2110 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 2111 break;
2112 case PCI_DEVICE_ID_QLOGIC_ISP2322:
2113 ha->device_type |= DT_ISP2322;
4a59f71d 2114 ha->device_type |= DT_ZIO_SUPPORTED;
ea5b6382 2115 if (ha->pdev->subsystem_vendor == 0x1028 &&
2116 ha->pdev->subsystem_device == 0x0170)
2117 ha->device_type |= DT_OEM_001;
441d1072 2118 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 2119 break;
2120 case PCI_DEVICE_ID_QLOGIC_ISP6312:
2121 ha->device_type |= DT_ISP6312;
441d1072 2122 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 2123 break;
2124 case PCI_DEVICE_ID_QLOGIC_ISP6322:
2125 ha->device_type |= DT_ISP6322;
441d1072 2126 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 2127 break;
2128 case PCI_DEVICE_ID_QLOGIC_ISP2422:
2129 ha->device_type |= DT_ISP2422;
4a59f71d 2130 ha->device_type |= DT_ZIO_SUPPORTED;
e428924c 2131 ha->device_type |= DT_FWI2;
c76f2c01 2132 ha->device_type |= DT_IIDMA;
441d1072 2133 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2134 break;
2135 case PCI_DEVICE_ID_QLOGIC_ISP2432:
2136 ha->device_type |= DT_ISP2432;
4a59f71d 2137 ha->device_type |= DT_ZIO_SUPPORTED;
e428924c 2138 ha->device_type |= DT_FWI2;
c76f2c01 2139 ha->device_type |= DT_IIDMA;
441d1072 2140 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2141 break;
4d4df193
HK		 2142 case PCI_DEVICE_ID_QLOGIC_ISP8432:
2143 ha->device_type |= DT_ISP8432;
2144 ha->device_type |= DT_ZIO_SUPPORTED;
2145 ha->device_type |= DT_FWI2;
2146 ha->device_type |= DT_IIDMA;
2147 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2148 break;
044cc6c8 2149 case PCI_DEVICE_ID_QLOGIC_ISP5422:
2150 ha->device_type |= DT_ISP5422;
e428924c 2151 ha->device_type |= DT_FWI2;
441d1072 2152 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2153 break;
044cc6c8 2154 case PCI_DEVICE_ID_QLOGIC_ISP5432:
2155 ha->device_type |= DT_ISP5432;
e428924c 2156 ha->device_type |= DT_FWI2;
441d1072 2157 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2158 break;
c3a2f0df
AV		 2159 case PCI_DEVICE_ID_QLOGIC_ISP2532:
2160 ha->device_type |= DT_ISP2532;
2161 ha->device_type |= DT_ZIO_SUPPORTED;
2162 ha->device_type |= DT_FWI2;
2163 ha->device_type |= DT_IIDMA;
441d1072 2164 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2165 break;
3a03eb79
AV		 2166 case PCI_DEVICE_ID_QLOGIC_ISP8001:
2167 ha->device_type |= DT_ISP8001;
2168 ha->device_type |= DT_ZIO_SUPPORTED;
2169 ha->device_type |= DT_FWI2;
2170 ha->device_type |= DT_IIDMA;
2171 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2172 break;
a9083016
GM		 2173 case PCI_DEVICE_ID_QLOGIC_ISP8021:
2174 ha->device_type |= DT_ISP8021;
2175 ha->device_type |= DT_ZIO_SUPPORTED;
2176 ha->device_type |= DT_FWI2;
2177 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2178 /* Initialize 82XX ISP flags */
2179 qla82xx_init_flags(ha);
2180 break;
7ec0effd
AD		 2181 case PCI_DEVICE_ID_QLOGIC_ISP8044:
2182 ha->device_type |= DT_ISP8044;
2183 ha->device_type |= DT_ZIO_SUPPORTED;
2184 ha->device_type |= DT_FWI2;
2185 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2186 /* Initialize 82XX ISP flags */
2187 qla82xx_init_flags(ha);
2188 break;
6246b8a1
GM		 2189 case PCI_DEVICE_ID_QLOGIC_ISP2031:
2190 ha->device_type |= DT_ISP2031;
2191 ha->device_type |= DT_ZIO_SUPPORTED;
2192 ha->device_type |= DT_FWI2;
2193 ha->device_type |= DT_IIDMA;
2194 ha->device_type |= DT_T10_PI;
2195 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2196 break;
2197 case PCI_DEVICE_ID_QLOGIC_ISP8031:
2198 ha->device_type |= DT_ISP8031;
2199 ha->device_type |= DT_ZIO_SUPPORTED;
2200 ha->device_type |= DT_FWI2;
2201 ha->device_type |= DT_IIDMA;
2202 ha->device_type |= DT_T10_PI;
2203 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2204 break;
8ae6d9c7
GM		 2205 case PCI_DEVICE_ID_QLOGIC_ISPF001:
2206 ha->device_type |= DT_ISPFX00;
2207 break;
f73cb695
CD		 2208 case PCI_DEVICE_ID_QLOGIC_ISP2071:
2209 ha->device_type |= DT_ISP2071;
2210 ha->device_type |= DT_ZIO_SUPPORTED;
2211 ha->device_type |= DT_FWI2;
2212 ha->device_type |= DT_IIDMA;
2213 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2214 break;
2c5bbbb2
JC		 2215 case PCI_DEVICE_ID_QLOGIC_ISP2271:
2216 ha->device_type |= DT_ISP2271;
2217 ha->device_type |= DT_ZIO_SUPPORTED;
2218 ha->device_type |= DT_FWI2;
2219 ha->device_type |= DT_IIDMA;
2220 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2221 break;
ea5b6382 2222 }
e5b68a61 2223
a9083016 2224 if (IS_QLA82XX(ha))
43a9c38b 2225 ha->port_no = ha->portnum & 1;
f73cb695 2226 else {
a9083016
GM		 2227 /* Get adapter physical port no from interrupt pin register. */
2228 pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no);
f73cb695
CD		 2229 if (IS_QLA27XX(ha))
2230 ha->port_no--;
2231 else
2232 ha->port_no = !(ha->port_no & 1);
2233 }
a9083016 2234
7c3df132 2235 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b,
d8424f68 2236 "device_type=0x%x port=%d fw_srisc_address=0x%x.\n",
f73cb695 2237 ha->device_type, ha->port_no, ha->fw_srisc_address);
ea5b6382 2238}
2239
1e99e33a
AV		 2240static void
2241qla2xxx_scan_start(struct Scsi_Host *shost)
2242{
e315cd28 2243 scsi_qla_host_t *vha = shost_priv(shost);
1e99e33a 2244
cbc8eb67
AV		 2245 if (vha->hw->flags.running_gold_fw)
2246 return;
2247
e315cd28
AC		 2248 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
2249 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
2250 set_bit(RSCN_UPDATE, &vha->dpc_flags);
2251 set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags);
1e99e33a
AV		 2252}
2253
2254static int
2255qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time)
2256{
e315cd28 2257 scsi_qla_host_t *vha = shost_priv(shost);
1e99e33a 2258
e315cd28 2259 if (!vha->host)
1e99e33a 2260 return 1;
e315cd28 2261 if (time > vha->hw->loop_reset_delay * HZ)
1e99e33a
AV		 2262 return 1;
2263
e315cd28 2264 return atomic_read(&vha->loop_state) == LOOP_READY;
1e99e33a
AV		 2265}
2266
1da177e4
LT		 2267/*
2268 * PCI driver interface
2269 */
6f039790 2270static int
7ee61397 2271qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
1da177e4 2272{
a1541d5a 2273 int ret = -ENODEV;
1da177e4 2274 struct Scsi_Host *host;
e315cd28
AC		 2275 scsi_qla_host_t *base_vha = NULL;
2276 struct qla_hw_data *ha;
29856e28 2277 char pci_info[30];
7d613ac6 2278 char fw_str[30], wq_name[30];
5433383e 2279 struct scsi_host_template *sht;
642ef983 2280 int bars, mem_only = 0;
e315cd28 2281 uint16_t req_length = 0, rsp_length = 0;
73208dfd
AC		 2282 struct req_que *req = NULL;
2283 struct rsp_que *rsp = NULL;
285d0321 2284 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO);
a5326f86 2285 sht = &qla2xxx_driver_template;
5433383e 2286 if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 ||
8bc69e7d 2287 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 ||
4d4df193 2288 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 ||
8bc69e7d 2289 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 ||
c3a2f0df 2290 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 ||
3a03eb79 2291 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 ||
a9083016 2292 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 ||
6246b8a1
GM		 2293 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021 ||
2294 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2031 ||
8ae6d9c7 2295 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8031 ||
7ec0effd 2296 pdev->device == PCI_DEVICE_ID_QLOGIC_ISPF001 ||
f73cb695 2297 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8044 ||
2c5bbbb2
JC		 2298 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2071 ||
2299 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2271) {
285d0321 2300 bars = pci_select_bars(pdev, IORESOURCE_MEM);
09483916 2301 mem_only = 1;
7c3df132
SK		 2302 ql_dbg_pci(ql_dbg_init, pdev, 0x0007,
2303 "Mem only adapter.\n");
285d0321 2304 }
7c3df132
SK		 2305 ql_dbg_pci(ql_dbg_init, pdev, 0x0008,
2306 "Bars=%d.\n", bars);
285d0321 2307
09483916
BH		 2308 if (mem_only) {
2309 if (pci_enable_device_mem(pdev))
2310 goto probe_out;
2311 } else {
2312 if (pci_enable_device(pdev))
2313 goto probe_out;
2314 }
285d0321 2315
0927678f
JB		 2316 /* This may fail but that's ok */
2317 pci_enable_pcie_error_reporting(pdev);
285d0321 2318
e315cd28
AC		 2319 ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL);
2320 if (!ha) {
7c3df132
SK		 2321 ql_log_pci(ql_log_fatal, pdev, 0x0009,
2322 "Unable to allocate memory for ha.\n");
e315cd28 2323 goto probe_out;
1da177e4 2324 }
7c3df132
SK		 2325 ql_dbg_pci(ql_dbg_init, pdev, 0x000a,
2326 "Memory allocated for ha=%p.\n", ha);
e315cd28 2327 ha->pdev = pdev;
2d70c103 2328 ha->tgt.enable_class_2 = ql2xenableclass2;
33e79977
QT		 2329 INIT_LIST_HEAD(&ha->tgt.q_full_list);
2330 spin_lock_init(&ha->tgt.q_full_lock);
1da177e4
LT		 2331
2332 /* Clear our data area */
285d0321 2333 ha->bars = bars;
09483916 2334 ha->mem_only = mem_only;
df4bf0bb 2335 spin_lock_init(&ha->hardware_lock);
339aa70e 2336 spin_lock_init(&ha->vport_slock);
a9b6f722 2337 mutex_init(&ha->selflogin_lock);
7a8ab9c8 2338 mutex_init(&ha->optrom_mutex);
1da177e4 2339
ea5b6382 2340 /* Set ISP-type information. */
2341 qla2x00_set_isp_flags(ha);
ca79cf66
DG		 2342
2343 /* Set EEH reset type to fundamental if required by hba */
95676112 2344 if (IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha) ||
f73cb695 2345 IS_QLA83XX(ha) || IS_QLA27XX(ha))
ca79cf66 2346 pdev->needs_freset = 1;
ca79cf66 2347
cba1e47f
CD		 2348 ha->prev_topology = 0;
2349 ha->init_cb_size = sizeof(init_cb_t);
2350 ha->link_data_rate = PORT_SPEED_UNKNOWN;
2351 ha->optrom_size = OPTROM_SIZE_2300;
2352
abbd8870 2353 /* Assign ISP specific operations. */
1da177e4 2354 if (IS_QLA2100(ha)) {
642ef983 2355 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
1da177e4 2356 ha->mbx_count = MAILBOX_REGISTER_COUNT_2100;
e315cd28
AC		 2357 req_length = REQUEST_ENTRY_CNT_2100;
2358 rsp_length = RESPONSE_ENTRY_CNT_2100;
2359 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
abbd8870 2360 ha->gid_list_info_size = 4;
3a03eb79
AV		 2361 ha->flash_conf_off = ~0;
2362 ha->flash_data_off = ~0;
2363 ha->nvram_conf_off = ~0;
2364 ha->nvram_data_off = ~0;
fd34f556 2365 ha->isp_ops = &qla2100_isp_ops;
1da177e4 2366 } else if (IS_QLA2200(ha)) {
642ef983 2367 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
67ddda35 2368 ha->mbx_count = MAILBOX_REGISTER_COUNT_2200;
e315cd28
AC		 2369 req_length = REQUEST_ENTRY_CNT_2200;
2370 rsp_length = RESPONSE_ENTRY_CNT_2100;
2371 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
abbd8870 2372 ha->gid_list_info_size = 4;
3a03eb79
AV		 2373 ha->flash_conf_off = ~0;
2374 ha->flash_data_off = ~0;
2375 ha->nvram_conf_off = ~0;
2376 ha->nvram_data_off = ~0;
fd34f556 2377 ha->isp_ops = &qla2100_isp_ops;
fca29703 2378 } else if (IS_QLA23XX(ha)) {
642ef983 2379 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
1da177e4 2380 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2381 req_length = REQUEST_ENTRY_CNT_2200;
2382 rsp_length = RESPONSE_ENTRY_CNT_2300;
2383 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
abbd8870 2384 ha->gid_list_info_size = 6;
854165f4 2385 if (IS_QLA2322(ha) || IS_QLA6322(ha))
2386 ha->optrom_size = OPTROM_SIZE_2322;
3a03eb79
AV		 2387 ha->flash_conf_off = ~0;
2388 ha->flash_data_off = ~0;
2389 ha->nvram_conf_off = ~0;
2390 ha->nvram_data_off = ~0;
fd34f556 2391 ha->isp_ops = &qla2300_isp_ops;
4d4df193 2392 } else if (IS_QLA24XX_TYPE(ha)) {
642ef983 2393 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
fca29703 2394 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2395 req_length = REQUEST_ENTRY_CNT_24XX;
2396 rsp_length = RESPONSE_ENTRY_CNT_2300;
2d70c103 2397 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
e315cd28 2398 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2c3dfe3f 2399 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
fca29703 2400 ha->gid_list_info_size = 8;
854165f4 2401 ha->optrom_size = OPTROM_SIZE_24XX;
73208dfd 2402 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX;
fd34f556 2403 ha->isp_ops = &qla24xx_isp_ops;
3a03eb79
AV		 2404 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2405 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2406 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2407 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
c3a2f0df 2408 } else if (IS_QLA25XX(ha)) {
642ef983 2409 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
c3a2f0df 2410 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2411 req_length = REQUEST_ENTRY_CNT_24XX;
2412 rsp_length = RESPONSE_ENTRY_CNT_2300;
2d70c103 2413 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
e315cd28 2414 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
c3a2f0df 2415 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
c3a2f0df
AV		 2416 ha->gid_list_info_size = 8;
2417 ha->optrom_size = OPTROM_SIZE_25XX;
73208dfd 2418 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
c3a2f0df 2419 ha->isp_ops = &qla25xx_isp_ops;
3a03eb79
AV		 2420 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2421 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2422 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2423 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
2424 } else if (IS_QLA81XX(ha)) {
642ef983 2425 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3a03eb79
AV		 2426 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2427 req_length = REQUEST_ENTRY_CNT_24XX;
2428 rsp_length = RESPONSE_ENTRY_CNT_2300;
aa230bc5 2429 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
3a03eb79
AV		 2430 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2431 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2432 ha->gid_list_info_size = 8;
2433 ha->optrom_size = OPTROM_SIZE_81XX;
40859ae5 2434 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3a03eb79
AV		 2435 ha->isp_ops = &qla81xx_isp_ops;
2436 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2437 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2438 ha->nvram_conf_off = ~0;
2439 ha->nvram_data_off = ~0;
a9083016 2440 } else if (IS_QLA82XX(ha)) {
642ef983 2441 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
a9083016
GM		 2442 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2443 req_length = REQUEST_ENTRY_CNT_82XX;
2444 rsp_length = RESPONSE_ENTRY_CNT_82XX;
2445 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2446 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2447 ha->gid_list_info_size = 8;
2448 ha->optrom_size = OPTROM_SIZE_82XX;
087c621e 2449 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
a9083016
GM		 2450 ha->isp_ops = &qla82xx_isp_ops;
2451 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2452 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2453 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2454 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
7ec0effd
AD		 2455 } else if (IS_QLA8044(ha)) {
2456 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2457 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2458 req_length = REQUEST_ENTRY_CNT_82XX;
2459 rsp_length = RESPONSE_ENTRY_CNT_82XX;
2460 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2461 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2462 ha->gid_list_info_size = 8;
2463 ha->optrom_size = OPTROM_SIZE_83XX;
2464 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2465 ha->isp_ops = &qla8044_isp_ops;
2466 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2467 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2468 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2469 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
6246b8a1 2470 } else if (IS_QLA83XX(ha)) {
7d613ac6 2471 ha->portnum = PCI_FUNC(ha->pdev->devfn);
642ef983 2472 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
6246b8a1 2473 ha->mbx_count = MAILBOX_REGISTER_COUNT;
f2ea653f 2474 req_length = REQUEST_ENTRY_CNT_83XX;
6246b8a1 2475 rsp_length = RESPONSE_ENTRY_CNT_2300;
b8aa4bdf 2476 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
6246b8a1
GM		 2477 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2478 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2479 ha->gid_list_info_size = 8;
2480 ha->optrom_size = OPTROM_SIZE_83XX;
2481 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2482 ha->isp_ops = &qla83xx_isp_ops;
2483 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2484 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2485 ha->nvram_conf_off = ~0;
2486 ha->nvram_data_off = ~0;
8ae6d9c7
GM		 2487 } else if (IS_QLAFX00(ha)) {
2488 ha->max_fibre_devices = MAX_FIBRE_DEVICES_FX00;
2489 ha->mbx_count = MAILBOX_REGISTER_COUNT_FX00;
2490 ha->aen_mbx_count = AEN_MAILBOX_REGISTER_COUNT_FX00;
2491 req_length = REQUEST_ENTRY_CNT_FX00;
2492 rsp_length = RESPONSE_ENTRY_CNT_FX00;
8ae6d9c7
GM		 2493 ha->isp_ops = &qlafx00_isp_ops;
2494 ha->port_down_retry_count = 30; /* default value */
2495 ha->mr.fw_hbt_cnt = QLAFX00_HEARTBEAT_INTERVAL;
2496 ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL;
71e56003 2497 ha->mr.fw_critemp_timer_tick = QLAFX00_CRITEMP_INTERVAL;
8ae6d9c7 2498 ha->mr.fw_hbt_en = 1;
e8f5e95d
AB		 2499 ha->mr.host_info_resend = false;
2500 ha->mr.hinfo_resend_timer_tick = QLAFX00_HINFO_RESEND_INTERVAL;
f73cb695
CD		 2501 } else if (IS_QLA27XX(ha)) {
2502 ha->portnum = PCI_FUNC(ha->pdev->devfn);
2503 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2504 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2505 req_length = REQUEST_ENTRY_CNT_24XX;
2506 rsp_length = RESPONSE_ENTRY_CNT_2300;
b20f02e1 2507 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
f73cb695
CD		 2508 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2509 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2510 ha->gid_list_info_size = 8;
2511 ha->optrom_size = OPTROM_SIZE_83XX;
2512 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2513 ha->isp_ops = &qla27xx_isp_ops;
2514 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2515 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2516 ha->nvram_conf_off = ~0;
2517 ha->nvram_data_off = ~0;
1da177e4 2518 }
6246b8a1 2519
7c3df132
SK		 2520 ql_dbg_pci(ql_dbg_init, pdev, 0x001e,
2521 "mbx_count=%d, req_length=%d, "
2522 "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, "
642ef983
CD		 2523 "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, "
2524 "max_fibre_devices=%d.\n",
7c3df132
SK		 2525 ha->mbx_count, req_length, rsp_length, ha->max_loop_id,
2526 ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size,
642ef983 2527 ha->nvram_npiv_size, ha->max_fibre_devices);
7c3df132
SK		 2528 ql_dbg_pci(ql_dbg_init, pdev, 0x001f,
2529 "isp_ops=%p, flash_conf_off=%d, "
2530 "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n",
2531 ha->isp_ops, ha->flash_conf_off, ha->flash_data_off,
2532 ha->nvram_conf_off, ha->nvram_data_off);
706f457d
GM		 2533
2534 /* Configure PCI I/O space */
2535 ret = ha->isp_ops->iospace_config(ha);
2536 if (ret)
0a63ad12 2537 goto iospace_config_failed;
706f457d
GM		 2538
2539 ql_log_pci(ql_log_info, pdev, 0x001d,
2540 "Found an ISP%04X irq %d iobase 0x%p.\n",
2541 pdev->device, pdev->irq, ha->iobase);
6c2f527c 2542 mutex_init(&ha->vport_lock);
0b05a1f0
MB		 2543 init_completion(&ha->mbx_cmd_comp);
2544 complete(&ha->mbx_cmd_comp);
2545 init_completion(&ha->mbx_intr_comp);
23f2ebd1 2546 init_completion(&ha->dcbx_comp);
f356bef1 2547 init_completion(&ha->lb_portup_comp);
1da177e4 2548
2c3dfe3f 2549 set_bit(0, (unsigned long *) ha->vp_idx_map);
1da177e4 2550
53303c42 2551 qla2x00_config_dma_addressing(ha);
7c3df132
SK		 2552 ql_dbg_pci(ql_dbg_init, pdev, 0x0020,
2553 "64 Bit addressing is %s.\n",
2554 ha->flags.enable_64bit_addressing ? "enable" :
2555 "disable");
73208dfd 2556 ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp);
b2a72ec3 2557 if (ret) {
7c3df132
SK		 2558 ql_log_pci(ql_log_fatal, pdev, 0x0031,
2559 "Failed to allocate memory for adapter, aborting.\n");
1da177e4 2560
e315cd28
AC		 2561 goto probe_hw_failed;
2562 }
2563
73208dfd 2564 req->max_q_depth = MAX_Q_DEPTH;
e315cd28 2565 if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU)
73208dfd
AC		 2566 req->max_q_depth = ql2xmaxqdepth;
2567
e315cd28
AC		 2568
2569 base_vha = qla2x00_create_host(sht, ha);
2570 if (!base_vha) {
a1541d5a 2571 ret = -ENOMEM;
6e9f21f3 2572 qla2x00_mem_free(ha);
2afa19a9
AC		 2573 qla2x00_free_req_que(ha, req);
2574 qla2x00_free_rsp_que(ha, rsp);
e315cd28 2575 goto probe_hw_failed;
1da177e4
LT		 2576 }
2577
e315cd28 2578 pci_set_drvdata(pdev, base_vha);
6b383979 2579 set_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags);
e315cd28 2580
e315cd28 2581 host = base_vha->host;
2afa19a9 2582 base_vha->req = req;
73208dfd 2583 if (IS_QLA2XXX_MIDTYPE(ha))
e315cd28 2584 base_vha->mgmt_svr_loop_id = 10 + base_vha->vp_idx;
73208dfd 2585 else
e315cd28
AC		 2586 base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER +
2587 base_vha->vp_idx;
58548cb5 2588
8ae6d9c7
GM		 2589 /* Setup fcport template structure. */
2590 ha->mr.fcport.vha = base_vha;
2591 ha->mr.fcport.port_type = FCT_UNKNOWN;
2592 ha->mr.fcport.loop_id = FC_NO_LOOP_ID;
2593 qla2x00_set_fcport_state(&ha->mr.fcport, FCS_UNCONFIGURED);
2594 ha->mr.fcport.supported_classes = FC_COS_UNSPECIFIED;
2595 ha->mr.fcport.scan_state = 1;
2596
58548cb5
GM		 2597 /* Set the SG table size based on ISP type */
2598 if (!IS_FWI2_CAPABLE(ha)) {
2599 if (IS_QLA2100(ha))
2600 host->sg_tablesize = 32;
2601 } else {
2602 if (!IS_QLA82XX(ha))
2603 host->sg_tablesize = QLA_SG_ALL;
2604 }
642ef983 2605 host->max_id = ha->max_fibre_devices;
e315cd28
AC		 2606 host->cmd_per_lun = 3;
2607 host->unique_id = host->host_no;
e02587d7 2608 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif)
0c470874
AE		 2609 host->max_cmd_len = 32;
2610 else
2611 host->max_cmd_len = MAX_CMDSZ;
e315cd28 2612 host->max_channel = MAX_BUSES - 1;
755f516b
HR		 2613 /* Older HBAs support only 16-bit LUNs */
2614 if (!IS_QLAFX00(ha) && !IS_FWI2_CAPABLE(ha) &&
2615 ql2xmaxlun > 0xffff)
2616 host->max_lun = 0xffff;
2617 else
2618 host->max_lun = ql2xmaxlun;
e315cd28 2619 host->transportt = qla2xxx_transport_template;
9a069e19 2620 sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC);
e315cd28 2621
7c3df132
SK		 2622 ql_dbg(ql_dbg_init, base_vha, 0x0033,
2623 "max_id=%d this_id=%d "
2624 "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d "
1abf635d 2625 "max_lun=%llu transportt=%p, vendor_id=%llu.\n", host->max_id,
7c3df132
SK		 2626 host->this_id, host->cmd_per_lun, host->unique_id,
2627 host->max_cmd_len, host->max_channel, host->max_lun,
2628 host->transportt, sht->vendor_id);
2629
9a347ff4
CD		 2630que_init:
2631 /* Alloc arrays of request and response ring ptrs */
2632 if (!qla2x00_alloc_queues(ha, req, rsp)) {
2633 ql_log(ql_log_fatal, base_vha, 0x003d,
2634 "Failed to allocate memory for queue pointers..."
2635 "aborting.\n");
2636 goto probe_init_failed;
2637 }
2638
2d70c103 2639 qlt_probe_one_stage1(base_vha, ha);
9a347ff4 2640
73208dfd
AC		 2641 /* Set up the irqs */
2642 ret = qla2x00_request_irqs(ha, rsp);
2643 if (ret)
6e9f21f3 2644 goto probe_init_failed;
90a86fc0
JC		 2645
2646 pci_save_state(pdev);
2647
9a347ff4 2648 /* Assign back pointers */
2afa19a9
AC		 2649 rsp->req = req;
2650 req->rsp = rsp;
9a347ff4 2651
8ae6d9c7
GM		 2652 if (IS_QLAFX00(ha)) {
2653 ha->rsp_q_map[0] = rsp;
2654 ha->req_q_map[0] = req;
2655 set_bit(0, ha->req_qid_map);
2656 set_bit(0, ha->rsp_qid_map);
2657 }
2658
08029990
AV		 2659 /* FWI2-capable only. */
2660 req->req_q_in = &ha->iobase->isp24.req_q_in;
2661 req->req_q_out = &ha->iobase->isp24.req_q_out;
2662 rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in;
2663 rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out;
f73cb695 2664 if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
08029990
AV		 2665 req->req_q_in = &ha->mqiobase->isp25mq.req_q_in;
2666 req->req_q_out = &ha->mqiobase->isp25mq.req_q_out;
2667 rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in;
2668 rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out;
17d98630
AC		 2669 }
2670
8ae6d9c7
GM		 2671 if (IS_QLAFX00(ha)) {
2672 req->req_q_in = &ha->iobase->ispfx00.req_q_in;
2673 req->req_q_out = &ha->iobase->ispfx00.req_q_out;
2674 rsp->rsp_q_in = &ha->iobase->ispfx00.rsp_q_in;
2675 rsp->rsp_q_out = &ha->iobase->ispfx00.rsp_q_out;
2676 }
2677
7ec0effd 2678 if (IS_P3P_TYPE(ha)) {
a9083016
GM		 2679 req->req_q_out = &ha->iobase->isp82.req_q_out[0];
2680 rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0];
2681 rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0];
2682 }
2683
7c3df132
SK		 2684 ql_dbg(ql_dbg_multiq, base_vha, 0xc009,
2685 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
2686 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
2687 ql_dbg(ql_dbg_multiq, base_vha, 0xc00a,
2688 "req->req_q_in=%p req->req_q_out=%p "
2689 "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
2690 req->req_q_in, req->req_q_out,
2691 rsp->rsp_q_in, rsp->rsp_q_out);
2692 ql_dbg(ql_dbg_init, base_vha, 0x003e,
2693 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
2694 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
2695 ql_dbg(ql_dbg_init, base_vha, 0x003f,
2696 "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
2697 req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out);
1da177e4 2698
8ae6d9c7 2699 if (ha->isp_ops->initialize_adapter(base_vha)) {
7c3df132
SK		 2700 ql_log(ql_log_fatal, base_vha, 0x00d6,
2701 "Failed to initialize adapter - Adapter flags %x.\n",
2702 base_vha->device_flags);
1da177e4 2703
a9083016
GM		 2704 if (IS_QLA82XX(ha)) {
2705 qla82xx_idc_lock(ha);
2706 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 2707 QLA8XXX_DEV_FAILED);
a9083016 2708 qla82xx_idc_unlock(ha);
7c3df132
SK		 2709 ql_log(ql_log_fatal, base_vha, 0x00d7,
2710 "HW State: FAILED.\n");
7ec0effd
AD		 2711 } else if (IS_QLA8044(ha)) {
2712 qla8044_idc_lock(ha);
2713 qla8044_wr_direct(base_vha,
2714 QLA8044_CRB_DEV_STATE_INDEX,
2715 QLA8XXX_DEV_FAILED);
2716 qla8044_idc_unlock(ha);
2717 ql_log(ql_log_fatal, base_vha, 0x0150,
2718 "HW State: FAILED.\n");
a9083016
GM		 2719 }
2720
a1541d5a 2721 ret = -ENODEV;
1da177e4
LT		 2722 goto probe_failed;
2723 }
2724
3b1bef64
CD		 2725 if (IS_QLAFX00(ha))
2726 host->can_queue = QLAFX00_MAX_CANQUEUE;
2727 else
2728 host->can_queue = req->num_outstanding_cmds - 10;
2729
2730 ql_dbg(ql_dbg_init, base_vha, 0x0032,
2731 "can_queue=%d, req=%p, mgmt_svr_loop_id=%d, sg_tablesize=%d.\n",
2732 host->can_queue, base_vha->req,
2733 base_vha->mgmt_svr_loop_id, host->sg_tablesize);
2734
7163ea81
AC		 2735 if (ha->mqenable) {
2736 if (qla25xx_setup_mode(base_vha)) {
7c3df132
SK		 2737 ql_log(ql_log_warn, base_vha, 0x00ec,
2738 "Failed to create queues, falling back to single queue mode.\n");
7163ea81
AC		 2739 goto que_init;
2740 }
2741 }
68ca949c 2742
cbc8eb67
AV		 2743 if (ha->flags.running_gold_fw)
2744 goto skip_dpc;
2745
1da177e4
LT		 2746 /*
2747 * Startup the kernel thread for this host adapter
2748 */
39a11240 2749 ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha,
7c3df132 2750 "%s_dpc", base_vha->host_str);
39a11240 2751 if (IS_ERR(ha->dpc_thread)) {
7c3df132
SK		 2752 ql_log(ql_log_fatal, base_vha, 0x00ed,
2753 "Failed to start DPC thread.\n");
39a11240 2754 ret = PTR_ERR(ha->dpc_thread);
1da177e4
LT		 2755 goto probe_failed;
2756 }
7c3df132
SK		 2757 ql_dbg(ql_dbg_init, base_vha, 0x00ee,
2758 "DPC thread started successfully.\n");
1da177e4 2759
2d70c103
NB		 2760 /*
2761 * If we're not coming up in initiator mode, we might sit for
2762 * a while without waking up the dpc thread, which leads to a
2763 * stuck process warning. So just kick the dpc once here and
2764 * let the kthread start (and go back to sleep in qla2x00_do_dpc).
2765 */
2766 qla2xxx_wake_dpc(base_vha);
2767
f3ddac19
CD		 2768 INIT_WORK(&ha->board_disable, qla2x00_disable_board_on_pci_error);
2769
81178772
SK		 2770 if (IS_QLA8031(ha) || IS_MCTP_CAPABLE(ha)) {
2771 sprintf(wq_name, "qla2xxx_%lu_dpc_lp_wq", base_vha->host_no);
2772 ha->dpc_lp_wq = create_singlethread_workqueue(wq_name);
2773 INIT_WORK(&ha->idc_aen, qla83xx_service_idc_aen);
2774
2775 sprintf(wq_name, "qla2xxx_%lu_dpc_hp_wq", base_vha->host_no);
2776 ha->dpc_hp_wq = create_singlethread_workqueue(wq_name);
2777 INIT_WORK(&ha->nic_core_reset, qla83xx_nic_core_reset_work);
2778 INIT_WORK(&ha->idc_state_handler,
2779 qla83xx_idc_state_handler_work);
2780 INIT_WORK(&ha->nic_core_unrecoverable,
2781 qla83xx_nic_core_unrecoverable_work);
2782 }
2783
cbc8eb67 2784skip_dpc:
e315cd28
AC		 2785 list_add_tail(&base_vha->list, &ha->vp_list);
2786 base_vha->host->irq = ha->pdev->irq;
1da177e4
LT		 2787
2788 /* Initialized the timer */
e315cd28 2789 qla2x00_start_timer(base_vha, qla2x00_timer, WATCH_INTERVAL);
7c3df132
SK		 2790 ql_dbg(ql_dbg_init, base_vha, 0x00ef,
2791 "Started qla2x00_timer with "
2792 "interval=%d.\n", WATCH_INTERVAL);
2793 ql_dbg(ql_dbg_init, base_vha, 0x00f0,
2794 "Detected hba at address=%p.\n",
2795 ha);
d19044c3 2796
e02587d7 2797 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) {
bad75002 2798 if (ha->fw_attributes & BIT_4) {
9e522cd8 2799 int prot = 0, guard;
bad75002 2800 base_vha->flags.difdix_supported = 1;
7c3df132
SK		 2801 ql_dbg(ql_dbg_init, base_vha, 0x00f1,
2802 "Registering for DIF/DIX type 1 and 3 protection.\n");
8cb2049c
AE		 2803 if (ql2xenabledif == 1)
2804 prot = SHOST_DIX_TYPE0_PROTECTION;
bad75002 2805 scsi_host_set_prot(host,
8cb2049c 2806 prot | SHOST_DIF_TYPE1_PROTECTION
0c470874 2807 | SHOST_DIF_TYPE2_PROTECTION
bad75002
AE		 2808 | SHOST_DIF_TYPE3_PROTECTION
2809 | SHOST_DIX_TYPE1_PROTECTION
0c470874 2810 | SHOST_DIX_TYPE2_PROTECTION
bad75002 2811 | SHOST_DIX_TYPE3_PROTECTION);
9e522cd8
AE		 2812
2813 guard = SHOST_DIX_GUARD_CRC;
2814
2815 if (IS_PI_IPGUARD_CAPABLE(ha) &&
2816 (ql2xenabledif > 1 || IS_PI_DIFB_DIX0_CAPABLE(ha)))
2817 guard |= SHOST_DIX_GUARD_IP;
2818
2819 scsi_host_set_guard(host, guard);
bad75002
AE		 2820 } else
2821 base_vha->flags.difdix_supported = 0;
2822 }
2823
a9083016
GM		 2824 ha->isp_ops->enable_intrs(ha);
2825
1fe19ee4
AB		 2826 if (IS_QLAFX00(ha)) {
2827 ret = qlafx00_fx_disc(base_vha,
2828 &base_vha->hw->mr.fcport, FXDISC_GET_CONFIG_INFO);
2829 host->sg_tablesize = (ha->mr.extended_io_enabled) ?
2830 QLA_SG_ALL : 128;
2831 }
2832
a1541d5a
AV		 2833 ret = scsi_add_host(host, &pdev->dev);
2834 if (ret)
2835 goto probe_failed;
2836
1486400f
MR		 2837 base_vha->flags.init_done = 1;
2838 base_vha->flags.online = 1;
edaa5c74 2839 ha->prev_minidump_failed = 0;
1486400f 2840
7c3df132
SK		 2841 ql_dbg(ql_dbg_init, base_vha, 0x00f2,
2842 "Init done and hba is online.\n");
2843
2d70c103
NB		 2844 if (qla_ini_mode_enabled(base_vha))
2845 scsi_scan_host(host);
2846 else
2847 ql_dbg(ql_dbg_init, base_vha, 0x0122,
2848 "skipping scsi_scan_host() for non-initiator port\n");
1e99e33a 2849
e315cd28 2850 qla2x00_alloc_sysfs_attr(base_vha);
a1541d5a 2851
8ae6d9c7 2852 if (IS_QLAFX00(ha)) {
8ae6d9c7
GM		 2853 ret = qlafx00_fx_disc(base_vha,
2854 &base_vha->hw->mr.fcport, FXDISC_GET_PORT_INFO);
2855
2856 /* Register system information */
2857 ret = qlafx00_fx_disc(base_vha,
2858 &base_vha->hw->mr.fcport, FXDISC_REG_HOST_INFO);
2859 }
2860
e315cd28 2861 qla2x00_init_host_attr(base_vha);
a1541d5a 2862
e315cd28 2863 qla2x00_dfs_setup(base_vha);
df613b96 2864
03eb912a
AB		 2865 ql_log(ql_log_info, base_vha, 0x00fb,
2866 "QLogic %s - %s.\n", ha->model_number, ha->model_desc);
7c3df132
SK		 2867 ql_log(ql_log_info, base_vha, 0x00fc,
2868 "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n",
2869 pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info),
2870 pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-',
2871 base_vha->host_no,
df57caba 2872 ha->isp_ops->fw_version_str(base_vha, fw_str, sizeof(fw_str)));
1da177e4 2873
2d70c103
NB		 2874 qlt_add_target(ha, base_vha);
2875
6b383979 2876 clear_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags);
1da177e4
LT		 2877 return 0;
2878
6e9f21f3 2879probe_init_failed:
2afa19a9 2880 qla2x00_free_req_que(ha, req);
9a347ff4
CD		 2881 ha->req_q_map[0] = NULL;
2882 clear_bit(0, ha->req_qid_map);
2afa19a9 2883 qla2x00_free_rsp_que(ha, rsp);
9a347ff4
CD		 2884 ha->rsp_q_map[0] = NULL;
2885 clear_bit(0, ha->rsp_qid_map);
2afa19a9 2886 ha->max_req_queues = ha->max_rsp_queues = 0;
6e9f21f3 2887
1da177e4 2888probe_failed:
b9978769
AV		 2889 if (base_vha->timer_active)
2890 qla2x00_stop_timer(base_vha);
2891 base_vha->flags.online = 0;
2892 if (ha->dpc_thread) {
2893 struct task_struct *t = ha->dpc_thread;
2894
2895 ha->dpc_thread = NULL;
2896 kthread_stop(t);
2897 }
2898
e315cd28 2899 qla2x00_free_device(base_vha);
1da177e4 2900
e315cd28 2901 scsi_host_put(base_vha->host);
1da177e4 2902
e315cd28 2903probe_hw_failed:
1a2fbf18
JL		 2904 qla2x00_clear_drv_active(ha);
2905
0a63ad12 2906iospace_config_failed:
7ec0effd 2907 if (IS_P3P_TYPE(ha)) {
0a63ad12 2908 if (!ha->nx_pcibase)
f73cb695 2909 iounmap((device_reg_t *)ha->nx_pcibase);
a9083016 2910 if (!ql2xdbwr)
f73cb695 2911 iounmap((device_reg_t *)ha->nxdb_wr_ptr);
a9083016
GM		 2912 } else {
2913 if (ha->iobase)
2914 iounmap(ha->iobase);
8ae6d9c7
GM		 2915 if (ha->cregbase)
2916 iounmap(ha->cregbase);
a9083016 2917 }
e315cd28
AC		 2918 pci_release_selected_regions(ha->pdev, ha->bars);
2919 kfree(ha);
2920 ha = NULL;
1da177e4 2921
a1541d5a 2922probe_out:
e315cd28 2923 pci_disable_device(pdev);
a1541d5a 2924 return ret;
1da177e4 2925}
1da177e4 2926
e30d1756
MI		 2927static void
2928qla2x00_shutdown(struct pci_dev *pdev)
2929{
2930 scsi_qla_host_t *vha;
2931 struct qla_hw_data *ha;
2932
552f3f9a
MI		 2933 if (!atomic_read(&pdev->enable_cnt))
2934 return;
2935
e30d1756
MI		 2936 vha = pci_get_drvdata(pdev);
2937 ha = vha->hw;
2938
42479343
AB		 2939 /* Notify ISPFX00 firmware */
2940 if (IS_QLAFX00(ha))
2941 qlafx00_driver_shutdown(vha, 20);
2942
e30d1756
MI		 2943 /* Turn-off FCE trace */
2944 if (ha->flags.fce_enabled) {
2945 qla2x00_disable_fce_trace(vha, NULL, NULL);
2946 ha->flags.fce_enabled = 0;
2947 }
2948
2949 /* Turn-off EFT trace */
2950 if (ha->eft)
2951 qla2x00_disable_eft_trace(vha);
2952
2953 /* Stop currently executing firmware. */
2954 qla2x00_try_to_stop_firmware(vha);
2955
2956 /* Turn adapter off line */
2957 vha->flags.online = 0;
2958
2959 /* turn-off interrupts on the card */
2960 if (ha->interrupts_on) {
2961 vha->flags.init_done = 0;
2962 ha->isp_ops->disable_intrs(ha);
2963 }
2964
2965 qla2x00_free_irqs(vha);
2966
2967 qla2x00_free_fw_dump(ha);
61d41f61
CD		 2968
2969 pci_disable_pcie_error_reporting(pdev);
2970 pci_disable_device(pdev);
e30d1756
MI		 2971}
2972
fe1b806f 2973/* Deletes all the virtual ports for a given ha */
4c993f76 2974static void
fe1b806f 2975qla2x00_delete_all_vps(struct qla_hw_data *ha, scsi_qla_host_t *base_vha)
1da177e4 2976{
fe1b806f
CD		 2977 struct Scsi_Host *scsi_host;
2978 scsi_qla_host_t *vha;
feafb7b1 2979 unsigned long flags;
e315cd28 2980
43ebf16d
AE		 2981 mutex_lock(&ha->vport_lock);
2982 while (ha->cur_vport_count) {
43ebf16d 2983 spin_lock_irqsave(&ha->vport_slock, flags);
feafb7b1 2984
43ebf16d
AE		 2985 BUG_ON(base_vha->list.next == &ha->vp_list);
2986 /* This assumes first entry in ha->vp_list is always base vha */
2987 vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list);
fe1b806f 2988 scsi_host = scsi_host_get(vha->host);
feafb7b1 2989
43ebf16d
AE		 2990 spin_unlock_irqrestore(&ha->vport_slock, flags);
2991 mutex_unlock(&ha->vport_lock);
2992
2993 fc_vport_terminate(vha->fc_vport);
2994 scsi_host_put(vha->host);
feafb7b1 2995
43ebf16d 2996 mutex_lock(&ha->vport_lock);
e315cd28 2997 }
43ebf16d 2998 mutex_unlock(&ha->vport_lock);
fe1b806f 2999}
1da177e4 3000
fe1b806f
CD		 3001/* Stops all deferred work threads */
3002static void
3003qla2x00_destroy_deferred_work(struct qla_hw_data *ha)
3004{
68ca949c
AC		 3005 /* Flush the work queue and remove it */
3006 if (ha->wq) {
3007 flush_workqueue(ha->wq);
3008 destroy_workqueue(ha->wq);
3009 ha->wq = NULL;
3010 }
3011
7d613ac6
SV		 3012 /* Cancel all work and destroy DPC workqueues */
3013 if (ha->dpc_lp_wq) {
3014 cancel_work_sync(&ha->idc_aen);
3015 destroy_workqueue(ha->dpc_lp_wq);
3016 ha->dpc_lp_wq = NULL;
3017 }
3018
3019 if (ha->dpc_hp_wq) {
3020 cancel_work_sync(&ha->nic_core_reset);
3021 cancel_work_sync(&ha->idc_state_handler);
3022 cancel_work_sync(&ha->nic_core_unrecoverable);
3023 destroy_workqueue(ha->dpc_hp_wq);
3024 ha->dpc_hp_wq = NULL;
3025 }
3026
b9978769
AV		 3027 /* Kill the kernel thread for this host */
3028 if (ha->dpc_thread) {
3029 struct task_struct *t = ha->dpc_thread;
3030
3031 /*
3032 * qla2xxx_wake_dpc checks for ->dpc_thread
3033 * so we need to zero it out.
3034 */
3035 ha->dpc_thread = NULL;
3036 kthread_stop(t);
3037 }
fe1b806f 3038}
1da177e4 3039
fe1b806f
CD		 3040static void
3041qla2x00_unmap_iobases(struct qla_hw_data *ha)
3042{
a9083016 3043 if (IS_QLA82XX(ha)) {
b963752f 3044
f73cb695 3045 iounmap((device_reg_t *)ha->nx_pcibase);
a9083016 3046 if (!ql2xdbwr)
f73cb695 3047 iounmap((device_reg_t *)ha->nxdb_wr_ptr);
a9083016
GM		 3048 } else {
3049 if (ha->iobase)
3050 iounmap(ha->iobase);
1da177e4 3051
8ae6d9c7
GM		 3052 if (ha->cregbase)
3053 iounmap(ha->cregbase);
3054
a9083016
GM		 3055 if (ha->mqiobase)
3056 iounmap(ha->mqiobase);
6246b8a1 3057
f73cb695 3058 if ((IS_QLA83XX(ha) || IS_QLA27XX(ha)) && ha->msixbase)
6246b8a1 3059 iounmap(ha->msixbase);
a9083016 3060 }
fe1b806f
CD		 3061}
3062
3063static void
db7157d4 3064qla2x00_clear_drv_active(struct qla_hw_data *ha)
fe1b806f 3065{
fe1b806f
CD		 3066 if (IS_QLA8044(ha)) {
3067 qla8044_idc_lock(ha);
c41afc9a 3068 qla8044_clear_drv_active(ha);
fe1b806f
CD		 3069 qla8044_idc_unlock(ha);
3070 } else if (IS_QLA82XX(ha)) {
3071 qla82xx_idc_lock(ha);
3072 qla82xx_clear_drv_active(ha);
3073 qla82xx_idc_unlock(ha);
3074 }
3075}
3076
3077static void
3078qla2x00_remove_one(struct pci_dev *pdev)
3079{
3080 scsi_qla_host_t *base_vha;
3081 struct qla_hw_data *ha;
3082
beb9e315
JL		 3083 base_vha = pci_get_drvdata(pdev);
3084 ha = base_vha->hw;
3085
3086 /* Indicate device removal to prevent future board_disable and wait
3087 * until any pending board_disable has completed. */
3088 set_bit(PFLG_DRIVER_REMOVING, &base_vha->pci_flags);
3089 cancel_work_sync(&ha->board_disable);
3090
fe1b806f 3091 /*
beb9e315
JL		 3092 * If the PCI device is disabled then there was a PCI-disconnect and
3093 * qla2x00_disable_board_on_pci_error has taken care of most of the
3094 * resources.
fe1b806f 3095 */
beb9e315
JL		 3096 if (!atomic_read(&pdev->enable_cnt)) {
3097 scsi_host_put(base_vha->host);
3098 kfree(ha);
3099 pci_set_drvdata(pdev, NULL);
fe1b806f 3100 return;
beb9e315 3101 }
fe1b806f 3102
638a1a01
SC		 3103 qla2x00_wait_for_hba_ready(base_vha);
3104
fe1b806f
CD		 3105 set_bit(UNLOADING, &base_vha->dpc_flags);
3106
3107 if (IS_QLAFX00(ha))
3108 qlafx00_driver_shutdown(base_vha, 20);
3109
3110 qla2x00_delete_all_vps(ha, base_vha);
3111
3112 if (IS_QLA8031(ha)) {
3113 ql_dbg(ql_dbg_p3p, base_vha, 0xb07e,
3114 "Clearing fcoe driver presence.\n");
3115 if (qla83xx_clear_drv_presence(base_vha) != QLA_SUCCESS)
3116 ql_dbg(ql_dbg_p3p, base_vha, 0xb079,
3117 "Error while clearing DRV-Presence.\n");
3118 }
3119
3120 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
3121
3122 qla2x00_dfs_remove(base_vha);
3123
3124 qla84xx_put_chip(base_vha);
3125
2d5a4c34
HM		 3126 /* Laser should be disabled only for ISP2031 */
3127 if (IS_QLA2031(ha))
3128 qla83xx_disable_laser(base_vha);
3129
fe1b806f
CD		 3130 /* Disable timer */
3131 if (base_vha->timer_active)
3132 qla2x00_stop_timer(base_vha);
3133
3134 base_vha->flags.online = 0;
3135
3136 qla2x00_destroy_deferred_work(ha);
3137
3138 qlt_remove_target(ha, base_vha);
3139
3140 qla2x00_free_sysfs_attr(base_vha, true);
3141
3142 fc_remove_host(base_vha->host);
3143
3144 scsi_remove_host(base_vha->host);
3145
3146 qla2x00_free_device(base_vha);
3147
db7157d4 3148 qla2x00_clear_drv_active(ha);
fe1b806f 3149
d2749ffa
AE		 3150 scsi_host_put(base_vha->host);
3151
fe1b806f 3152 qla2x00_unmap_iobases(ha);
73208dfd 3153
e315cd28
AC		 3154 pci_release_selected_regions(ha->pdev, ha->bars);
3155 kfree(ha);
3156 ha = NULL;
1da177e4 3157
90a86fc0
JC		 3158 pci_disable_pcie_error_reporting(pdev);
3159
665db93b 3160 pci_disable_device(pdev);
1da177e4 3161}
1da177e4
LT		 3162
3163static void
e315cd28 3164qla2x00_free_device(scsi_qla_host_t *vha)
1da177e4 3165{
e315cd28 3166 struct qla_hw_data *ha = vha->hw;
1da177e4 3167
85880801
AV		 3168 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
3169
3170 /* Disable timer */
3171 if (vha->timer_active)
3172 qla2x00_stop_timer(vha);
3173
2afa19a9 3174 qla25xx_delete_queues(vha);
fe1b806f 3175
df613b96 3176 if (ha->flags.fce_enabled)
e315cd28 3177 qla2x00_disable_fce_trace(vha, NULL, NULL);
df613b96 3178
a7a167bf 3179 if (ha->eft)
e315cd28 3180 qla2x00_disable_eft_trace(vha);
a7a167bf 3181
f6ef3b18 3182 /* Stop currently executing firmware. */
e315cd28 3183 qla2x00_try_to_stop_firmware(vha);
1da177e4 3184
85880801
AV		 3185 vha->flags.online = 0;
3186
f6ef3b18 3187 /* turn-off interrupts on the card */
a9083016
GM		 3188 if (ha->interrupts_on) {
3189 vha->flags.init_done = 0;
fd34f556 3190 ha->isp_ops->disable_intrs(ha);
a9083016 3191 }
f6ef3b18 3192
e315cd28 3193 qla2x00_free_irqs(vha);
1da177e4 3194
8867048b
CD		 3195 qla2x00_free_fcports(vha);
3196
e315cd28 3197 qla2x00_mem_free(ha);
73208dfd 3198
08de2844
GM		 3199 qla82xx_md_free(vha);
3200
73208dfd 3201 qla2x00_free_queues(ha);
1da177e4
LT		 3202}
3203
8867048b
CD		 3204void qla2x00_free_fcports(struct scsi_qla_host *vha)
3205{
3206 fc_port_t *fcport, *tfcport;
3207
3208 list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list) {
3209 list_del(&fcport->list);
5f16b331 3210 qla2x00_clear_loop_id(fcport);
8867048b
CD		 3211 kfree(fcport);
3212 fcport = NULL;
3213 }
3214}
3215
d97994dc 3216static inline void
e315cd28 3217qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport,
d97994dc 3218 int defer)
3219{
d97994dc 3220 struct fc_rport *rport;
67becc00 3221 scsi_qla_host_t *base_vha;
044d78e1 3222 unsigned long flags;
d97994dc 3223
3224 if (!fcport->rport)
3225 return;
3226
3227 rport = fcport->rport;
3228 if (defer) {
67becc00 3229 base_vha = pci_get_drvdata(vha->hw->pdev);
044d78e1 3230 spin_lock_irqsave(vha->host->host_lock, flags);
d97994dc 3231 fcport->drport = rport;
044d78e1 3232 spin_unlock_irqrestore(vha->host->host_lock, flags);
67becc00
AV		 3233 set_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags);
3234 qla2xxx_wake_dpc(base_vha);
2d70c103 3235 } else {
d97994dc 3236 fc_remote_port_delete(rport);
2d70c103
NB		 3237 qlt_fc_port_deleted(vha, fcport);
3238 }
d97994dc 3239}
3240
1da177e4
LT		 3241/*
3242 * qla2x00_mark_device_lost Updates fcport state when device goes offline.
3243 *
3244 * Input: ha = adapter block pointer. fcport = port structure pointer.
3245 *
3246 * Return: None.
3247 *
3248 * Context:
3249 */
e315cd28 3250void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport,
d97994dc 3251 int do_login, int defer)
1da177e4 3252{
8ae6d9c7
GM		 3253 if (IS_QLAFX00(vha->hw)) {
3254 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
3255 qla2x00_schedule_rport_del(vha, fcport, defer);
3256 return;
3257 }
3258
2c3dfe3f 3259 if (atomic_read(&fcport->state) == FCS_ONLINE &&
c6d39e23 3260 vha->vp_idx == fcport->vha->vp_idx) {
ec426e10 3261 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
e315cd28
AC		 3262 qla2x00_schedule_rport_del(vha, fcport, defer);
3263 }
fa2a1ce5 3264 /*
1da177e4
LT		 3265 * We may need to retry the login, so don't change the state of the
3266 * port but do the retries.
3267 */
3268 if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD)
ec426e10 3269 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
1da177e4
LT		 3270
3271 if (!do_login)
3272 return;
3273
3274 if (fcport->login_retry == 0) {
e315cd28
AC		 3275 fcport->login_retry = vha->hw->login_retry_count;
3276 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
1da177e4 3277
7c3df132 3278 ql_dbg(ql_dbg_disc, vha, 0x2067,
7b833558
OK		 3279 "Port login retry %8phN, id = 0x%04x retry cnt=%d.\n",
3280 fcport->port_name, fcport->loop_id, fcport->login_retry);
1da177e4
LT		 3281 }
3282}
3283
3284/*
3285 * qla2x00_mark_all_devices_lost
3286 * Updates fcport state when device goes offline.
3287 *
3288 * Input:
3289 * ha = adapter block pointer.
3290 * fcport = port structure pointer.
3291 *
3292 * Return:
3293 * None.
3294 *
3295 * Context:
3296 */
3297void
e315cd28 3298qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha, int defer)
1da177e4
LT		 3299{
3300 fc_port_t *fcport;
3301
e315cd28 3302 list_for_each_entry(fcport, &vha->vp_fcports, list) {
c6d39e23 3303 if (vha->vp_idx != 0 && vha->vp_idx != fcport->vha->vp_idx)
1da177e4 3304 continue;
0d6e61bc 3305
1da177e4
LT		 3306 /*
3307 * No point in marking the device as lost, if the device is
3308 * already DEAD.
3309 */
3310 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD)
3311 continue;
e315cd28 3312 if (atomic_read(&fcport->state) == FCS_ONLINE) {
ec426e10 3313 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
0d6e61bc
AV		 3314 if (defer)
3315 qla2x00_schedule_rport_del(vha, fcport, defer);
c6d39e23 3316 else if (vha->vp_idx == fcport->vha->vp_idx)
0d6e61bc
AV		 3317 qla2x00_schedule_rport_del(vha, fcport, defer);
3318 }
1da177e4
LT		 3319 }
3320}
3321
3322/*
3323* qla2x00_mem_alloc
3324* Allocates adapter memory.
3325*
3326* Returns:
3327* 0 = success.
e8711085 3328* !0 = failure.
1da177e4 3329*/
e8711085 3330static int
73208dfd
AC		 3331qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len,
3332 struct req_que **req, struct rsp_que **rsp)
1da177e4
LT		 3333{
3334 char name[16];
1da177e4 3335
e8711085 3336 ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size,
e315cd28 3337 &ha->init_cb_dma, GFP_KERNEL);
e8711085 3338 if (!ha->init_cb)
e315cd28 3339 goto fail;
e8711085 3340
2d70c103
NB		 3341 if (qlt_mem_alloc(ha) < 0)
3342 goto fail_free_init_cb;
3343
642ef983
CD		 3344 ha->gid_list = dma_alloc_coherent(&ha->pdev->dev,
3345 qla2x00_gid_list_size(ha), &ha->gid_list_dma, GFP_KERNEL);
e315cd28 3346 if (!ha->gid_list)
2d70c103 3347 goto fail_free_tgt_mem;
1da177e4 3348
e8711085
AV		 3349 ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep);
3350 if (!ha->srb_mempool)
e315cd28 3351 goto fail_free_gid_list;
e8711085 3352
7ec0effd 3353 if (IS_P3P_TYPE(ha)) {
a9083016
GM		 3354 /* Allocate cache for CT6 Ctx. */
3355 if (!ctx_cachep) {
3356 ctx_cachep = kmem_cache_create("qla2xxx_ctx",
3357 sizeof(struct ct6_dsd), 0,
3358 SLAB_HWCACHE_ALIGN, NULL);
3359 if (!ctx_cachep)
3360 goto fail_free_gid_list;
3361 }
3362 ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ,
3363 ctx_cachep);
3364 if (!ha->ctx_mempool)
3365 goto fail_free_srb_mempool;
7c3df132
SK		 3366 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021,
3367 "ctx_cachep=%p ctx_mempool=%p.\n",
3368 ctx_cachep, ha->ctx_mempool);
a9083016
GM		 3369 }
3370
e8711085
AV		 3371 /* Get memory for cached NVRAM */
3372 ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL);
3373 if (!ha->nvram)
a9083016 3374 goto fail_free_ctx_mempool;
e8711085 3375
e315cd28
AC		 3376 snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME,
3377 ha->pdev->device);
3378 ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3379 DMA_POOL_SIZE, 8, 0);
3380 if (!ha->s_dma_pool)
3381 goto fail_free_nvram;
3382
7c3df132
SK		 3383 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022,
3384 "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n",
3385 ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool);
3386
7ec0effd 3387 if (IS_P3P_TYPE(ha) || ql2xenabledif) {
a9083016
GM		 3388 ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3389 DSD_LIST_DMA_POOL_SIZE, 8, 0);
3390 if (!ha->dl_dma_pool) {
7c3df132
SK		 3391 ql_log_pci(ql_log_fatal, ha->pdev, 0x0023,
3392 "Failed to allocate memory for dl_dma_pool.\n");
a9083016
GM		 3393 goto fail_s_dma_pool;
3394 }
3395
3396 ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3397 FCP_CMND_DMA_POOL_SIZE, 8, 0);
3398 if (!ha->fcp_cmnd_dma_pool) {
7c3df132
SK		 3399 ql_log_pci(ql_log_fatal, ha->pdev, 0x0024,
3400 "Failed to allocate memory for fcp_cmnd_dma_pool.\n");
a9083016
GM		 3401 goto fail_dl_dma_pool;
3402 }
7c3df132
SK		 3403 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025,
3404 "dl_dma_pool=%p fcp_cmnd_dma_pool=%p.\n",
3405 ha->dl_dma_pool, ha->fcp_cmnd_dma_pool);
a9083016
GM		 3406 }
3407
e8711085
AV		 3408 /* Allocate memory for SNS commands */
3409 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
e315cd28 3410 /* Get consistent memory allocated for SNS commands */
e8711085 3411 ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev,
e315cd28 3412 sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL);
e8711085 3413 if (!ha->sns_cmd)
e315cd28 3414 goto fail_dma_pool;
7c3df132 3415 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026,
d8424f68 3416 "sns_cmd: %p.\n", ha->sns_cmd);
e8711085 3417 } else {
e315cd28 3418 /* Get consistent memory allocated for MS IOCB */
e8711085 3419 ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
e315cd28 3420 &ha->ms_iocb_dma);
e8711085 3421 if (!ha->ms_iocb)
e315cd28
AC		 3422 goto fail_dma_pool;
3423 /* Get consistent memory allocated for CT SNS commands */
e8711085 3424 ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev,
e315cd28 3425 sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL);
e8711085
AV		 3426 if (!ha->ct_sns)
3427 goto fail_free_ms_iocb;
7c3df132
SK		 3428 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027,
3429 "ms_iocb=%p ct_sns=%p.\n",
3430 ha->ms_iocb, ha->ct_sns);
1da177e4
LT		 3431 }
3432
e315cd28 3433 /* Allocate memory for request ring */
73208dfd
AC		 3434 *req = kzalloc(sizeof(struct req_que), GFP_KERNEL);
3435 if (!*req) {
7c3df132
SK		 3436 ql_log_pci(ql_log_fatal, ha->pdev, 0x0028,
3437 "Failed to allocate memory for req.\n");
e315cd28
AC		 3438 goto fail_req;
3439 }
73208dfd
AC		 3440 (*req)->length = req_len;
3441 (*req)->ring = dma_alloc_coherent(&ha->pdev->dev,
3442 ((*req)->length + 1) * sizeof(request_t),
3443 &(*req)->dma, GFP_KERNEL);
3444 if (!(*req)->ring) {
7c3df132
SK		 3445 ql_log_pci(ql_log_fatal, ha->pdev, 0x0029,
3446 "Failed to allocate memory for req_ring.\n");
e315cd28
AC		 3447 goto fail_req_ring;
3448 }
3449 /* Allocate memory for response ring */
73208dfd
AC		 3450 *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL);
3451 if (!*rsp) {
7c3df132
SK		 3452 ql_log_pci(ql_log_fatal, ha->pdev, 0x002a,
3453 "Failed to allocate memory for rsp.\n");
e315cd28
AC		 3454 goto fail_rsp;
3455 }
73208dfd
AC		 3456 (*rsp)->hw = ha;
3457 (*rsp)->length = rsp_len;
3458 (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev,
3459 ((*rsp)->length + 1) * sizeof(response_t),
3460 &(*rsp)->dma, GFP_KERNEL);
3461 if (!(*rsp)->ring) {
7c3df132
SK		 3462 ql_log_pci(ql_log_fatal, ha->pdev, 0x002b,
3463 "Failed to allocate memory for rsp_ring.\n");
e315cd28
AC		 3464 goto fail_rsp_ring;
3465 }
73208dfd
AC		 3466 (*req)->rsp = *rsp;
3467 (*rsp)->req = *req;
7c3df132
SK		 3468 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c,
3469 "req=%p req->length=%d req->ring=%p rsp=%p "
3470 "rsp->length=%d rsp->ring=%p.\n",
3471 *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length,
3472 (*rsp)->ring);
73208dfd
AC		 3473 /* Allocate memory for NVRAM data for vports */
3474 if (ha->nvram_npiv_size) {
3475 ha->npiv_info = kzalloc(sizeof(struct qla_npiv_entry) *
7c3df132 3476 ha->nvram_npiv_size, GFP_KERNEL);
73208dfd 3477 if (!ha->npiv_info) {
7c3df132
SK		 3478 ql_log_pci(ql_log_fatal, ha->pdev, 0x002d,
3479 "Failed to allocate memory for npiv_info.\n");
73208dfd
AC		 3480 goto fail_npiv_info;
3481 }
3482 } else
3483 ha->npiv_info = NULL;
e8711085 3484
b64b0e8f 3485 /* Get consistent memory allocated for EX-INIT-CB. */
f73cb695 3486 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha)) {
b64b0e8f
AV		 3487 ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
3488 &ha->ex_init_cb_dma);
3489 if (!ha->ex_init_cb)
3490 goto fail_ex_init_cb;
7c3df132
SK		 3491 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e,
3492 "ex_init_cb=%p.\n", ha->ex_init_cb);
b64b0e8f
AV		 3493 }
3494
a9083016
GM		 3495 INIT_LIST_HEAD(&ha->gbl_dsd_list);
3496
5ff1d584
AV		 3497 /* Get consistent memory allocated for Async Port-Database. */
3498 if (!IS_FWI2_CAPABLE(ha)) {
3499 ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
3500 &ha->async_pd_dma);
3501 if (!ha->async_pd)
3502 goto fail_async_pd;
7c3df132
SK		 3503 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f,
3504 "async_pd=%p.\n", ha->async_pd);
5ff1d584
AV		 3505 }
3506
e315cd28 3507 INIT_LIST_HEAD(&ha->vp_list);
5f16b331
CD		 3508
3509 /* Allocate memory for our loop_id bitmap */
3510 ha->loop_id_map = kzalloc(BITS_TO_LONGS(LOOPID_MAP_SIZE) * sizeof(long),
3511 GFP_KERNEL);
3512 if (!ha->loop_id_map)
3513 goto fail_async_pd;
3514 else {
3515 qla2x00_set_reserved_loop_ids(ha);
3516 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0123,
b2a72ec3 3517 "loop_id_map=%p.\n", ha->loop_id_map);
5f16b331
CD		 3518 }
3519
b2a72ec3 3520 return 0;
e315cd28 3521
5ff1d584
AV		 3522fail_async_pd:
3523 dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma);
b64b0e8f
AV		 3524fail_ex_init_cb:
3525 kfree(ha->npiv_info);
73208dfd
AC		 3526fail_npiv_info:
3527 dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) *
3528 sizeof(response_t), (*rsp)->ring, (*rsp)->dma);
3529 (*rsp)->ring = NULL;
3530 (*rsp)->dma = 0;
e315cd28 3531fail_rsp_ring:
73208dfd 3532 kfree(*rsp);
e315cd28 3533fail_rsp:
73208dfd
AC		 3534 dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) *
3535 sizeof(request_t), (*req)->ring, (*req)->dma);
3536 (*req)->ring = NULL;
3537 (*req)->dma = 0;
e315cd28 3538fail_req_ring:
73208dfd 3539 kfree(*req);
e315cd28
AC		 3540fail_req:
3541 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
3542 ha->ct_sns, ha->ct_sns_dma);
3543 ha->ct_sns = NULL;
3544 ha->ct_sns_dma = 0;
e8711085
AV		 3545fail_free_ms_iocb:
3546 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
3547 ha->ms_iocb = NULL;
3548 ha->ms_iocb_dma = 0;
e315cd28 3549fail_dma_pool:
bad75002 3550 if (IS_QLA82XX(ha) || ql2xenabledif) {
a9083016
GM		 3551 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
3552 ha->fcp_cmnd_dma_pool = NULL;
3553 }
3554fail_dl_dma_pool:
bad75002 3555 if (IS_QLA82XX(ha) || ql2xenabledif) {
a9083016
GM		 3556 dma_pool_destroy(ha->dl_dma_pool);
3557 ha->dl_dma_pool = NULL;
3558 }
3559fail_s_dma_pool:
e315cd28
AC		 3560 dma_pool_destroy(ha->s_dma_pool);
3561 ha->s_dma_pool = NULL;
e8711085
AV		 3562fail_free_nvram:
3563 kfree(ha->nvram);
3564 ha->nvram = NULL;
a9083016
GM		 3565fail_free_ctx_mempool:
3566 mempool_destroy(ha->ctx_mempool);
3567 ha->ctx_mempool = NULL;
e8711085
AV		 3568fail_free_srb_mempool:
3569 mempool_destroy(ha->srb_mempool);
3570 ha->srb_mempool = NULL;
e8711085 3571fail_free_gid_list:
642ef983
CD		 3572 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
3573 ha->gid_list,
e315cd28 3574 ha->gid_list_dma);
e8711085
AV		 3575 ha->gid_list = NULL;
3576 ha->gid_list_dma = 0;
2d70c103
NB		 3577fail_free_tgt_mem:
3578 qlt_mem_free(ha);
e315cd28
AC		 3579fail_free_init_cb:
3580 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb,
3581 ha->init_cb_dma);
3582 ha->init_cb = NULL;
3583 ha->init_cb_dma = 0;
e8711085 3584fail:
7c3df132
SK		 3585 ql_log(ql_log_fatal, NULL, 0x0030,
3586 "Memory allocation failure.\n");
e8711085 3587 return -ENOMEM;
1da177e4
LT		 3588}
3589
3590/*
e30d1756
MI		 3591* qla2x00_free_fw_dump
3592* Frees fw dump stuff.
1da177e4
LT		 3593*
3594* Input:
7ec0effd 3595* ha = adapter block pointer
1da177e4 3596*/
a824ebb3 3597static void
e30d1756 3598qla2x00_free_fw_dump(struct qla_hw_data *ha)
1da177e4 3599{
df613b96 3600 if (ha->fce)
f73cb695
CD		 3601 dma_free_coherent(&ha->pdev->dev,
3602 FCE_SIZE, ha->fce, ha->fce_dma);
df613b96 3603
f73cb695
CD		 3604 if (ha->eft)
3605 dma_free_coherent(&ha->pdev->dev,
3606 EFT_SIZE, ha->eft, ha->eft_dma);
3607
3608 if (ha->fw_dump)
a7a167bf 3609 vfree(ha->fw_dump);
f73cb695
CD		 3610 if (ha->fw_dump_template)
3611 vfree(ha->fw_dump_template);
3612
e30d1756
MI		 3613 ha->fce = NULL;
3614 ha->fce_dma = 0;
3615 ha->eft = NULL;
3616 ha->eft_dma = 0;
e30d1756 3617 ha->fw_dumped = 0;
61f098dd 3618 ha->fw_dump_cap_flags = 0;
e30d1756 3619 ha->fw_dump_reading = 0;
f73cb695
CD		 3620 ha->fw_dump = NULL;
3621 ha->fw_dump_len = 0;
3622 ha->fw_dump_template = NULL;
3623 ha->fw_dump_template_len = 0;
e30d1756
MI		 3624}
3625
3626/*
3627* qla2x00_mem_free
3628* Frees all adapter allocated memory.
3629*
3630* Input:
3631* ha = adapter block pointer.
3632*/
3633static void
3634qla2x00_mem_free(struct qla_hw_data *ha)
3635{
3636 qla2x00_free_fw_dump(ha);
3637
81178772
SK		 3638 if (ha->mctp_dump)
3639 dma_free_coherent(&ha->pdev->dev, MCTP_DUMP_SIZE, ha->mctp_dump,
3640 ha->mctp_dump_dma);
3641
e30d1756
MI		 3642 if (ha->srb_mempool)
3643 mempool_destroy(ha->srb_mempool);
a7a167bf 3644
11bbc1d8
AV		 3645 if (ha->dcbx_tlv)
3646 dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE,
3647 ha->dcbx_tlv, ha->dcbx_tlv_dma);
3648
ce0423f4
AV		 3649 if (ha->xgmac_data)
3650 dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE,
3651 ha->xgmac_data, ha->xgmac_data_dma);
3652
1da177e4
LT		 3653 if (ha->sns_cmd)
3654 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
e315cd28 3655 ha->sns_cmd, ha->sns_cmd_dma);
1da177e4
LT		 3656
3657 if (ha->ct_sns)
3658 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
e315cd28 3659 ha->ct_sns, ha->ct_sns_dma);
1da177e4 3660
88729e53
AV		 3661 if (ha->sfp_data)
3662 dma_pool_free(ha->s_dma_pool, ha->sfp_data, ha->sfp_data_dma);
3663
1da177e4
LT		 3664 if (ha->ms_iocb)
3665 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
3666
b64b0e8f 3667 if (ha->ex_init_cb)
a9083016
GM		 3668 dma_pool_free(ha->s_dma_pool,
3669 ha->ex_init_cb, ha->ex_init_cb_dma);
b64b0e8f 3670
5ff1d584
AV		 3671 if (ha->async_pd)
3672 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
3673
1da177e4
LT		 3674 if (ha->s_dma_pool)
3675 dma_pool_destroy(ha->s_dma_pool);
3676
1da177e4 3677 if (ha->gid_list)
642ef983
CD		 3678 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
3679 ha->gid_list, ha->gid_list_dma);
1da177e4 3680
a9083016
GM		 3681 if (IS_QLA82XX(ha)) {
3682 if (!list_empty(&ha->gbl_dsd_list)) {
3683 struct dsd_dma *dsd_ptr, *tdsd_ptr;
3684
3685 /* clean up allocated prev pool */
3686 list_for_each_entry_safe(dsd_ptr,
3687 tdsd_ptr, &ha->gbl_dsd_list, list) {
3688 dma_pool_free(ha->dl_dma_pool,
3689 dsd_ptr->dsd_addr, dsd_ptr->dsd_list_dma);
3690 list_del(&dsd_ptr->list);
3691 kfree(dsd_ptr);
3692 }
3693 }
3694 }
3695
3696 if (ha->dl_dma_pool)
3697 dma_pool_destroy(ha->dl_dma_pool);
3698
3699 if (ha->fcp_cmnd_dma_pool)
3700 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
3701
3702 if (ha->ctx_mempool)
3703 mempool_destroy(ha->ctx_mempool);
3704
2d70c103
NB		 3705 qlt_mem_free(ha);
3706
e315cd28
AC		 3707 if (ha->init_cb)
3708 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size,
a9083016 3709 ha->init_cb, ha->init_cb_dma);
e315cd28
AC		 3710 vfree(ha->optrom_buffer);
3711 kfree(ha->nvram);
73208dfd 3712 kfree(ha->npiv_info);
7a67735b 3713 kfree(ha->swl);
5f16b331 3714 kfree(ha->loop_id_map);
1da177e4 3715
e8711085 3716 ha->srb_mempool = NULL;
a9083016 3717 ha->ctx_mempool = NULL;
1da177e4
LT		 3718 ha->sns_cmd = NULL;
3719 ha->sns_cmd_dma = 0;
3720 ha->ct_sns = NULL;
3721 ha->ct_sns_dma = 0;
3722 ha->ms_iocb = NULL;
3723 ha->ms_iocb_dma = 0;
1da177e4
LT		 3724 ha->init_cb = NULL;
3725 ha->init_cb_dma = 0;
b64b0e8f
AV		 3726 ha->ex_init_cb = NULL;
3727 ha->ex_init_cb_dma = 0;
5ff1d584
AV		 3728 ha->async_pd = NULL;
3729 ha->async_pd_dma = 0;
1da177e4
LT		 3730
3731 ha->s_dma_pool = NULL;
a9083016
GM		 3732 ha->dl_dma_pool = NULL;
3733 ha->fcp_cmnd_dma_pool = NULL;
1da177e4 3734
1da177e4
LT		 3735 ha->gid_list = NULL;
3736 ha->gid_list_dma = 0;
2d70c103
NB		 3737
3738 ha->tgt.atio_ring = NULL;
3739 ha->tgt.atio_dma = 0;
3740 ha->tgt.tgt_vp_map = NULL;
e315cd28 3741}
1da177e4 3742
e315cd28
AC		 3743struct scsi_qla_host *qla2x00_create_host(struct scsi_host_template *sht,
3744 struct qla_hw_data *ha)
3745{
3746 struct Scsi_Host *host;
3747 struct scsi_qla_host *vha = NULL;
854165f4 3748
e315cd28
AC		 3749 host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t));
3750 if (host == NULL) {
7c3df132
SK		 3751 ql_log_pci(ql_log_fatal, ha->pdev, 0x0107,
3752 "Failed to allocate host from the scsi layer, aborting.\n");
e315cd28
AC		 3753 goto fail;
3754 }
3755
3756 /* Clear our data area */
3757 vha = shost_priv(host);
3758 memset(vha, 0, sizeof(scsi_qla_host_t));
3759
3760 vha->host = host;
3761 vha->host_no = host->host_no;
3762 vha->hw = ha;
3763
3764 INIT_LIST_HEAD(&vha->vp_fcports);
3765 INIT_LIST_HEAD(&vha->work_list);
3766 INIT_LIST_HEAD(&vha->list);
8b2f5ff3
SN		 3767 INIT_LIST_HEAD(&vha->qla_cmd_list);
3768 INIT_LIST_HEAD(&vha->qla_sess_op_cmd_list);
e315cd28 3769
f999f4c1 3770 spin_lock_init(&vha->work_lock);
8b2f5ff3 3771 spin_lock_init(&vha->cmd_list_lock);
f999f4c1 3772
e315cd28 3773 sprintf(vha->host_str, "%s_%ld", QLA2XXX_DRIVER_NAME, vha->host_no);
7c3df132
SK		 3774 ql_dbg(ql_dbg_init, vha, 0x0041,
3775 "Allocated the host=%p hw=%p vha=%p dev_name=%s",
3776 vha->host, vha->hw, vha,
3777 dev_name(&(ha->pdev->dev)));
3778
e315cd28
AC		 3779 return vha;
3780
3781fail:
3782 return vha;
1da177e4
LT		 3783}
3784
01ef66bb 3785static struct qla_work_evt *
f999f4c1 3786qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type)
0971de7f
AV		 3787{
3788 struct qla_work_evt *e;
feafb7b1
AE		 3789 uint8_t bail;
3790
3791 QLA_VHA_MARK_BUSY(vha, bail);
3792 if (bail)
3793 return NULL;
0971de7f 3794
f999f4c1 3795 e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC);
feafb7b1
AE		 3796 if (!e) {
3797 QLA_VHA_MARK_NOT_BUSY(vha);
0971de7f 3798 return NULL;
feafb7b1 3799 }
0971de7f
AV		 3800
3801 INIT_LIST_HEAD(&e->list);
3802 e->type = type;
3803 e->flags = QLA_EVT_FLAG_FREE;
3804 return e;
3805}
3806
01ef66bb 3807static int
f999f4c1 3808qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e)
0971de7f 3809{
f999f4c1 3810 unsigned long flags;
0971de7f 3811
f999f4c1 3812 spin_lock_irqsave(&vha->work_lock, flags);
e315cd28 3813 list_add_tail(&e->list, &vha->work_list);
f999f4c1 3814 spin_unlock_irqrestore(&vha->work_lock, flags);
e315cd28 3815 qla2xxx_wake_dpc(vha);
f999f4c1 3816
0971de7f
AV		 3817 return QLA_SUCCESS;
3818}
3819
3820int
e315cd28 3821qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code,
0971de7f
AV		 3822 u32 data)
3823{
3824 struct qla_work_evt *e;
3825
f999f4c1 3826 e = qla2x00_alloc_work(vha, QLA_EVT_AEN);
0971de7f
AV		 3827 if (!e)
3828 return QLA_FUNCTION_FAILED;
3829
3830 e->u.aen.code = code;
3831 e->u.aen.data = data;
f999f4c1 3832 return qla2x00_post_work(vha, e);
0971de7f
AV		 3833}
3834
8a659571
AV		 3835int
3836qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb)
3837{
3838 struct qla_work_evt *e;
3839
f999f4c1 3840 e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK);
8a659571
AV		 3841 if (!e)
3842 return QLA_FUNCTION_FAILED;
3843
3844 memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t));
f999f4c1 3845 return qla2x00_post_work(vha, e);
8a659571
AV		 3846}
3847
ac280b67
AV		 3848#define qla2x00_post_async_work(name, type) \
3849int qla2x00_post_async_##name##_work( \
3850 struct scsi_qla_host *vha, \
3851 fc_port_t *fcport, uint16_t *data) \
3852{ \
3853 struct qla_work_evt *e; \
3854 \
3855 e = qla2x00_alloc_work(vha, type); \
3856 if (!e) \
3857 return QLA_FUNCTION_FAILED; \
3858 \
3859 e->u.logio.fcport = fcport; \
3860 if (data) { \
3861 e->u.logio.data[0] = data[0]; \
3862 e->u.logio.data[1] = data[1]; \
3863 } \
3864 return qla2x00_post_work(vha, e); \
3865}
3866
3867qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN);
3868qla2x00_post_async_work(login_done, QLA_EVT_ASYNC_LOGIN_DONE);
3869qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT);
3870qla2x00_post_async_work(logout_done, QLA_EVT_ASYNC_LOGOUT_DONE);
5ff1d584
AV		 3871qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC);
3872qla2x00_post_async_work(adisc_done, QLA_EVT_ASYNC_ADISC_DONE);
ac280b67 3873
3420d36c
AV		 3874int
3875qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code)
3876{
3877 struct qla_work_evt *e;
3878
3879 e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT);
3880 if (!e)
3881 return QLA_FUNCTION_FAILED;
3882
3883 e->u.uevent.code = code;
3884 return qla2x00_post_work(vha, e);
3885}
3886
3887static void
3888qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code)
3889{
3890 char event_string[40];
3891 char *envp[] = { event_string, NULL };
3892
3893 switch (code) {
3894 case QLA_UEVENT_CODE_FW_DUMP:
3895 snprintf(event_string, sizeof(event_string), "FW_DUMP=%ld",
3896 vha->host_no);
3897 break;
3898 default:
3899 /* do nothing */
3900 break;
3901 }
3902 kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp);
3903}
3904
8ae6d9c7
GM		 3905int
3906qlafx00_post_aenfx_work(struct scsi_qla_host *vha, uint32_t evtcode,
3907 uint32_t *data, int cnt)
3908{
3909 struct qla_work_evt *e;
3910
3911 e = qla2x00_alloc_work(vha, QLA_EVT_AENFX);
3912 if (!e)
3913 return QLA_FUNCTION_FAILED;
3914
3915 e->u.aenfx.evtcode = evtcode;
3916 e->u.aenfx.count = cnt;
3917 memcpy(e->u.aenfx.mbx, data, sizeof(*data) * cnt);
3918 return qla2x00_post_work(vha, e);
3919}
3920
ac280b67 3921void
e315cd28 3922qla2x00_do_work(struct scsi_qla_host *vha)
0971de7f 3923{
f999f4c1
AV		 3924 struct qla_work_evt *e, *tmp;
3925 unsigned long flags;
3926 LIST_HEAD(work);
0971de7f 3927
f999f4c1
AV		 3928 spin_lock_irqsave(&vha->work_lock, flags);
3929 list_splice_init(&vha->work_list, &work);
3930 spin_unlock_irqrestore(&vha->work_lock, flags);
3931
3932 list_for_each_entry_safe(e, tmp, &work, list) {
0971de7f 3933 list_del_init(&e->list);
0971de7f
AV		 3934
3935 switch (e->type) {
3936 case QLA_EVT_AEN:
e315cd28 3937 fc_host_post_event(vha->host, fc_get_event_number(),
0971de7f
AV		 3938 e->u.aen.code, e->u.aen.data);
3939 break;
8a659571
AV		 3940 case QLA_EVT_IDC_ACK:
3941 qla81xx_idc_ack(vha, e->u.idc_ack.mb);
3942 break;
ac280b67
AV		 3943 case QLA_EVT_ASYNC_LOGIN:
3944 qla2x00_async_login(vha, e->u.logio.fcport,
3945 e->u.logio.data);
3946 break;
3947 case QLA_EVT_ASYNC_LOGIN_DONE:
3948 qla2x00_async_login_done(vha, e->u.logio.fcport,
3949 e->u.logio.data);
3950 break;
3951 case QLA_EVT_ASYNC_LOGOUT:
3952 qla2x00_async_logout(vha, e->u.logio.fcport);
3953 break;
3954 case QLA_EVT_ASYNC_LOGOUT_DONE:
3955 qla2x00_async_logout_done(vha, e->u.logio.fcport,
3956 e->u.logio.data);
3957 break;
5ff1d584
AV		 3958 case QLA_EVT_ASYNC_ADISC:
3959 qla2x00_async_adisc(vha, e->u.logio.fcport,
3960 e->u.logio.data);
3961 break;
3962 case QLA_EVT_ASYNC_ADISC_DONE:
3963 qla2x00_async_adisc_done(vha, e->u.logio.fcport,
3964 e->u.logio.data);
3965 break;
3420d36c
AV		 3966 case QLA_EVT_UEVENT:
3967 qla2x00_uevent_emit(vha, e->u.uevent.code);
3968 break;
8ae6d9c7
GM		 3969 case QLA_EVT_AENFX:
3970 qlafx00_process_aen(vha, e);
3971 break;
0971de7f
AV		 3972 }
3973 if (e->flags & QLA_EVT_FLAG_FREE)
3974 kfree(e);
feafb7b1
AE		 3975
3976 /* For each work completed decrement vha ref count */
3977 QLA_VHA_MARK_NOT_BUSY(vha);
e315cd28 3978 }
e315cd28 3979}
f999f4c1 3980
e315cd28
AC		 3981/* Relogins all the fcports of a vport
3982 * Context: dpc thread
3983 */
3984void qla2x00_relogin(struct scsi_qla_host *vha)
3985{
3986 fc_port_t *fcport;
c6b2fca8 3987 int status;
e315cd28
AC		 3988 uint16_t next_loopid = 0;
3989 struct qla_hw_data *ha = vha->hw;
ac280b67 3990 uint16_t data[2];
e315cd28
AC		 3991
3992 list_for_each_entry(fcport, &vha->vp_fcports, list) {
3993 /*
3994 * If the port is not ONLINE then try to login
3995 * to it if we haven't run out of retries.
3996 */
5ff1d584
AV		 3997 if (atomic_read(&fcport->state) != FCS_ONLINE &&
3998 fcport->login_retry && !(fcport->flags & FCF_ASYNC_SENT)) {
ac280b67 3999 fcport->login_retry--;
e315cd28 4000 if (fcport->flags & FCF_FABRIC_DEVICE) {
f08b7251 4001 if (fcport->flags & FCF_FCP2_DEVICE)
e315cd28
AC		 4002 ha->isp_ops->fabric_logout(vha,
4003 fcport->loop_id,
4004 fcport->d_id.b.domain,
4005 fcport->d_id.b.area,
4006 fcport->d_id.b.al_pa);
4007
03bcfb57
JC		 4008 if (fcport->loop_id == FC_NO_LOOP_ID) {
4009 fcport->loop_id = next_loopid =
4010 ha->min_external_loopid;
4011 status = qla2x00_find_new_loop_id(
4012 vha, fcport);
4013 if (status != QLA_SUCCESS) {
4014 /* Ran out of IDs to use */
4015 break;
4016 }
4017 }
4018
ac280b67 4019 if (IS_ALOGIO_CAPABLE(ha)) {
5ff1d584 4020 fcport->flags |= FCF_ASYNC_SENT;
ac280b67
AV		 4021 data[0] = 0;
4022 data[1] = QLA_LOGIO_LOGIN_RETRIED;
4023 status = qla2x00_post_async_login_work(
4024 vha, fcport, data);
4025 if (status == QLA_SUCCESS)
4026 continue;
4027 /* Attempt a retry. */
4028 status = 1;
aaf4d3e2 4029 } else {
ac280b67
AV		 4030 status = qla2x00_fabric_login(vha,
4031 fcport, &next_loopid);
aaf4d3e2
SK		 4032 if (status == QLA_SUCCESS) {
4033 int status2;
4034 uint8_t opts;
4035
4036 opts = 0;
4037 if (fcport->flags &
4038 FCF_FCP2_DEVICE)
4039 opts |= BIT_1;
03003960
SK		 4040 status2 =
4041 qla2x00_get_port_database(
4042 vha, fcport, opts);
aaf4d3e2
SK		 4043 if (status2 != QLA_SUCCESS)
4044 status = 1;
4045 }
4046 }
e315cd28
AC		 4047 } else
4048 status = qla2x00_local_device_login(vha,
4049 fcport);
4050
e315cd28
AC		 4051 if (status == QLA_SUCCESS) {
4052 fcport->old_loop_id = fcport->loop_id;
4053
7c3df132
SK		 4054 ql_dbg(ql_dbg_disc, vha, 0x2003,
4055 "Port login OK: logged in ID 0x%x.\n",
4056 fcport->loop_id);
e315cd28
AC		 4057
4058 qla2x00_update_fcport(vha, fcport);
4059
4060 } else if (status == 1) {
4061 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
4062 /* retry the login again */
7c3df132
SK		 4063 ql_dbg(ql_dbg_disc, vha, 0x2007,
4064 "Retrying %d login again loop_id 0x%x.\n",
4065 fcport->login_retry, fcport->loop_id);
e315cd28
AC		 4066 } else {
4067 fcport->login_retry = 0;
4068 }
4069
4070 if (fcport->login_retry == 0 && status != QLA_SUCCESS)
5f16b331 4071 qla2x00_clear_loop_id(fcport);
e315cd28
AC		 4072 }
4073 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
4074 break;
0971de7f 4075 }
0971de7f
AV		 4076}
4077
7d613ac6
SV		 4078/* Schedule work on any of the dpc-workqueues */
4079void
4080qla83xx_schedule_work(scsi_qla_host_t *base_vha, int work_code)
4081{
4082 struct qla_hw_data *ha = base_vha->hw;
4083
4084 switch (work_code) {
4085 case MBA_IDC_AEN: /* 0x8200 */
4086 if (ha->dpc_lp_wq)
4087 queue_work(ha->dpc_lp_wq, &ha->idc_aen);
4088 break;
4089
4090 case QLA83XX_NIC_CORE_RESET: /* 0x1 */
4091 if (!ha->flags.nic_core_reset_hdlr_active) {
4092 if (ha->dpc_hp_wq)
4093 queue_work(ha->dpc_hp_wq, &ha->nic_core_reset);
4094 } else
4095 ql_dbg(ql_dbg_p3p, base_vha, 0xb05e,
4096 "NIC Core reset is already active. Skip "
4097 "scheduling it again.\n");
4098 break;
4099 case QLA83XX_IDC_STATE_HANDLER: /* 0x2 */
4100 if (ha->dpc_hp_wq)
4101 queue_work(ha->dpc_hp_wq, &ha->idc_state_handler);
4102 break;
4103 case QLA83XX_NIC_CORE_UNRECOVERABLE: /* 0x3 */
4104 if (ha->dpc_hp_wq)
4105 queue_work(ha->dpc_hp_wq, &ha->nic_core_unrecoverable);
4106 break;
4107 default:
4108 ql_log(ql_log_warn, base_vha, 0xb05f,
d939be3a 4109 "Unknown work-code=0x%x.\n", work_code);
7d613ac6
SV		 4110 }
4111
4112 return;
4113}
4114
4115/* Work: Perform NIC Core Unrecoverable state handling */
4116void
4117qla83xx_nic_core_unrecoverable_work(struct work_struct *work)
4118{
4119 struct qla_hw_data *ha =
2ad1b67c 4120 container_of(work, struct qla_hw_data, nic_core_unrecoverable);
7d613ac6
SV		 4121 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4122 uint32_t dev_state = 0;
4123
4124 qla83xx_idc_lock(base_vha, 0);
4125 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4126 qla83xx_reset_ownership(base_vha);
4127 if (ha->flags.nic_core_reset_owner) {
4128 ha->flags.nic_core_reset_owner = 0;
4129 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
4130 QLA8XXX_DEV_FAILED);
4131 ql_log(ql_log_info, base_vha, 0xb060, "HW State: FAILED.\n");
4132 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
4133 }
4134 qla83xx_idc_unlock(base_vha, 0);
4135}
4136
4137/* Work: Execute IDC state handler */
4138void
4139qla83xx_idc_state_handler_work(struct work_struct *work)
4140{
4141 struct qla_hw_data *ha =
2ad1b67c 4142 container_of(work, struct qla_hw_data, idc_state_handler);
7d613ac6
SV		 4143 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4144 uint32_t dev_state = 0;
4145
4146 qla83xx_idc_lock(base_vha, 0);
4147 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4148 if (dev_state == QLA8XXX_DEV_FAILED ||
4149 dev_state == QLA8XXX_DEV_NEED_QUIESCENT)
4150 qla83xx_idc_state_handler(base_vha);
4151 qla83xx_idc_unlock(base_vha, 0);
4152}
4153
fa492630 4154static int
7d613ac6
SV		 4155qla83xx_check_nic_core_fw_alive(scsi_qla_host_t *base_vha)
4156{
4157 int rval = QLA_SUCCESS;
4158 unsigned long heart_beat_wait = jiffies + (1 * HZ);
4159 uint32_t heart_beat_counter1, heart_beat_counter2;
4160
4161 do {
4162 if (time_after(jiffies, heart_beat_wait)) {
4163 ql_dbg(ql_dbg_p3p, base_vha, 0xb07c,
4164 "Nic Core f/w is not alive.\n");
4165 rval = QLA_FUNCTION_FAILED;
4166 break;
4167 }
4168
4169 qla83xx_idc_lock(base_vha, 0);
4170 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
4171 &heart_beat_counter1);
4172 qla83xx_idc_unlock(base_vha, 0);
4173 msleep(100);
4174 qla83xx_idc_lock(base_vha, 0);
4175 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
4176 &heart_beat_counter2);
4177 qla83xx_idc_unlock(base_vha, 0);
4178 } while (heart_beat_counter1 == heart_beat_counter2);
4179
4180 return rval;
4181}
4182
4183/* Work: Perform NIC Core Reset handling */
4184void
4185qla83xx_nic_core_reset_work(struct work_struct *work)
4186{
4187 struct qla_hw_data *ha =
4188 container_of(work, struct qla_hw_data, nic_core_reset);
4189 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4190 uint32_t dev_state = 0;
4191
81178772
SK		 4192 if (IS_QLA2031(ha)) {
4193 if (qla2xxx_mctp_dump(base_vha) != QLA_SUCCESS)
4194 ql_log(ql_log_warn, base_vha, 0xb081,
4195 "Failed to dump mctp\n");
4196 return;
4197 }
4198
7d613ac6
SV		 4199 if (!ha->flags.nic_core_reset_hdlr_active) {
4200 if (qla83xx_check_nic_core_fw_alive(base_vha) == QLA_SUCCESS) {
4201 qla83xx_idc_lock(base_vha, 0);
4202 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE,
4203 &dev_state);
4204 qla83xx_idc_unlock(base_vha, 0);
4205 if (dev_state != QLA8XXX_DEV_NEED_RESET) {
4206 ql_dbg(ql_dbg_p3p, base_vha, 0xb07a,
4207 "Nic Core f/w is alive.\n");
4208 return;
4209 }
4210 }
4211
4212 ha->flags.nic_core_reset_hdlr_active = 1;
4213 if (qla83xx_nic_core_reset(base_vha)) {
4214 /* NIC Core reset failed. */
4215 ql_dbg(ql_dbg_p3p, base_vha, 0xb061,
4216 "NIC Core reset failed.\n");
4217 }
4218 ha->flags.nic_core_reset_hdlr_active = 0;
4219 }
4220}
4221
4222/* Work: Handle 8200 IDC aens */
4223void
4224qla83xx_service_idc_aen(struct work_struct *work)
4225{
4226 struct qla_hw_data *ha =
4227 container_of(work, struct qla_hw_data, idc_aen);
4228 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4229 uint32_t dev_state, idc_control;
4230
4231 qla83xx_idc_lock(base_vha, 0);
4232 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4233 qla83xx_rd_reg(base_vha, QLA83XX_IDC_CONTROL, &idc_control);
4234 qla83xx_idc_unlock(base_vha, 0);
4235 if (dev_state == QLA8XXX_DEV_NEED_RESET) {
4236 if (idc_control & QLA83XX_IDC_GRACEFUL_RESET) {
4237 ql_dbg(ql_dbg_p3p, base_vha, 0xb062,
4238 "Application requested NIC Core Reset.\n");
4239 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
4240 } else if (qla83xx_check_nic_core_fw_alive(base_vha) ==
4241 QLA_SUCCESS) {
4242 ql_dbg(ql_dbg_p3p, base_vha, 0xb07b,
4243 "Other protocol driver requested NIC Core Reset.\n");
4244 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
4245 }
4246 } else if (dev_state == QLA8XXX_DEV_FAILED ||
4247 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) {
4248 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
4249 }
4250}
4251
4252static void
4253qla83xx_wait_logic(void)
4254{
4255 int i;
4256
4257 /* Yield CPU */
4258 if (!in_interrupt()) {
4259 /*
4260 * Wait about 200ms before retrying again.
4261 * This controls the number of retries for single
4262 * lock operation.
4263 */
4264 msleep(100);
4265 schedule();
4266 } else {
4267 for (i = 0; i < 20; i++)
4268 cpu_relax(); /* This a nop instr on i386 */
4269 }
4270}
4271
fa492630 4272static int
7d613ac6
SV		 4273qla83xx_force_lock_recovery(scsi_qla_host_t *base_vha)
4274{
4275 int rval;
4276 uint32_t data;
4277 uint32_t idc_lck_rcvry_stage_mask = 0x3;
4278 uint32_t idc_lck_rcvry_owner_mask = 0x3c;
4279 struct qla_hw_data *ha = base_vha->hw;
6c315553
SK		 4280 ql_dbg(ql_dbg_p3p, base_vha, 0xb086,
4281 "Trying force recovery of the IDC lock.\n");
7d613ac6
SV		 4282
4283 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, &data);
4284 if (rval)
4285 return rval;
4286
4287 if ((data & idc_lck_rcvry_stage_mask) > 0) {
4288 return QLA_SUCCESS;
4289 } else {
4290 data = (IDC_LOCK_RECOVERY_STAGE1) | (ha->portnum << 2);
4291 rval = qla83xx_wr_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
4292 data);
4293 if (rval)
4294 return rval;
4295
4296 msleep(200);
4297
4298 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
4299 &data);
4300 if (rval)
4301 return rval;
4302
4303 if (((data & idc_lck_rcvry_owner_mask) >> 2) == ha->portnum) {
4304 data &= (IDC_LOCK_RECOVERY_STAGE2 |
4305 ~(idc_lck_rcvry_stage_mask));
4306 rval = qla83xx_wr_reg(base_vha,
4307 QLA83XX_IDC_LOCK_RECOVERY, data);
4308 if (rval)
4309 return rval;
4310
4311 /* Forcefully perform IDC UnLock */
4312 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK,
4313 &data);
4314 if (rval)
4315 return rval;
4316 /* Clear lock-id by setting 0xff */
4317 rval = qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
4318 0xff);
4319 if (rval)
4320 return rval;
4321 /* Clear lock-recovery by setting 0x0 */
4322 rval = qla83xx_wr_reg(base_vha,
4323 QLA83XX_IDC_LOCK_RECOVERY, 0x0);
4324 if (rval)
4325 return rval;
4326 } else
4327 return QLA_SUCCESS;
4328 }
4329
4330 return rval;
4331}
4332
fa492630 4333static int
7d613ac6
SV		 4334qla83xx_idc_lock_recovery(scsi_qla_host_t *base_vha)
4335{
4336 int rval = QLA_SUCCESS;
4337 uint32_t o_drv_lockid, n_drv_lockid;
4338 unsigned long lock_recovery_timeout;
4339
4340 lock_recovery_timeout = jiffies + QLA83XX_MAX_LOCK_RECOVERY_WAIT;
4341retry_lockid:
4342 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &o_drv_lockid);
4343 if (rval)
4344 goto exit;
4345
4346 /* MAX wait time before forcing IDC Lock recovery = 2 secs */
4347 if (time_after_eq(jiffies, lock_recovery_timeout)) {
4348 if (qla83xx_force_lock_recovery(base_vha) == QLA_SUCCESS)
4349 return QLA_SUCCESS;
4350 else
4351 return QLA_FUNCTION_FAILED;
4352 }
4353
4354 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &n_drv_lockid);
4355 if (rval)
4356 goto exit;
4357
4358 if (o_drv_lockid == n_drv_lockid) {
4359 qla83xx_wait_logic();
4360 goto retry_lockid;
4361 } else
4362 return QLA_SUCCESS;
4363
4364exit:
4365 return rval;
4366}
4367
4368void
4369qla83xx_idc_lock(scsi_qla_host_t *base_vha, uint16_t requester_id)
4370{
4371 uint16_t options = (requester_id << 15) | BIT_6;
4372 uint32_t data;
6c315553 4373 uint32_t lock_owner;
7d613ac6
SV		 4374 struct qla_hw_data *ha = base_vha->hw;
4375
4376 /* IDC-lock implementation using driver-lock/lock-id remote registers */
4377retry_lock:
4378 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCK, &data)
4379 == QLA_SUCCESS) {
4380 if (data) {
4381 /* Setting lock-id to our function-number */
4382 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
4383 ha->portnum);
4384 } else {
6c315553
SK		 4385 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID,
4386 &lock_owner);
7d613ac6 4387 ql_dbg(ql_dbg_p3p, base_vha, 0xb063,
6c315553
SK		 4388 "Failed to acquire IDC lock, acquired by %d, "
4389 "retrying...\n", lock_owner);
7d613ac6
SV		 4390
4391 /* Retry/Perform IDC-Lock recovery */
4392 if (qla83xx_idc_lock_recovery(base_vha)
4393 == QLA_SUCCESS) {
4394 qla83xx_wait_logic();
4395 goto retry_lock;
4396 } else
4397 ql_log(ql_log_warn, base_vha, 0xb075,
4398 "IDC Lock recovery FAILED.\n");
4399 }
4400
4401 }
4402
4403 return;
4404
4405 /* XXX: IDC-lock implementation using access-control mbx */
4406retry_lock2:
4407 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
4408 ql_dbg(ql_dbg_p3p, base_vha, 0xb072,
4409 "Failed to acquire IDC lock. retrying...\n");
4410 /* Retry/Perform IDC-Lock recovery */
4411 if (qla83xx_idc_lock_recovery(base_vha) == QLA_SUCCESS) {
4412 qla83xx_wait_logic();
4413 goto retry_lock2;
4414 } else
4415 ql_log(ql_log_warn, base_vha, 0xb076,
4416 "IDC Lock recovery FAILED.\n");
4417 }
4418
4419 return;
4420}
4421
4422void
4423qla83xx_idc_unlock(scsi_qla_host_t *base_vha, uint16_t requester_id)
4424{
5897cb2f
BVA		 4425#if 0
4426 uint16_t options = (requester_id << 15) | BIT_7;
4427#endif
4428 uint16_t retry;
7d613ac6
SV		 4429 uint32_t data;
4430 struct qla_hw_data *ha = base_vha->hw;
4431
4432 /* IDC-unlock implementation using driver-unlock/lock-id
4433 * remote registers
4434 */
4435 retry = 0;
4436retry_unlock:
4437 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &data)
4438 == QLA_SUCCESS) {
4439 if (data == ha->portnum) {
4440 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, &data);
4441 /* Clearing lock-id by setting 0xff */
4442 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 0xff);
4443 } else if (retry < 10) {
4444 /* SV: XXX: IDC unlock retrying needed here? */
4445
4446 /* Retry for IDC-unlock */
4447 qla83xx_wait_logic();
4448 retry++;
4449 ql_dbg(ql_dbg_p3p, base_vha, 0xb064,
4450 "Failed to release IDC lock, retyring=%d\n", retry);
4451 goto retry_unlock;
4452 }
4453 } else if (retry < 10) {
4454 /* Retry for IDC-unlock */
4455 qla83xx_wait_logic();
4456 retry++;
4457 ql_dbg(ql_dbg_p3p, base_vha, 0xb065,
4458 "Failed to read drv-lockid, retyring=%d\n", retry);
4459 goto retry_unlock;
4460 }
4461
4462 return;
4463
5897cb2f 4464#if 0
7d613ac6
SV		 4465 /* XXX: IDC-unlock implementation using access-control mbx */
4466 retry = 0;
4467retry_unlock2:
4468 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
4469 if (retry < 10) {
4470 /* Retry for IDC-unlock */
4471 qla83xx_wait_logic();
4472 retry++;
4473 ql_dbg(ql_dbg_p3p, base_vha, 0xb066,
4474 "Failed to release IDC lock, retyring=%d\n", retry);
4475 goto retry_unlock2;
4476 }
4477 }
4478
4479 return;
5897cb2f 4480#endif
7d613ac6
SV		 4481}
4482
4483int
4484__qla83xx_set_drv_presence(scsi_qla_host_t *vha)
4485{
4486 int rval = QLA_SUCCESS;
4487 struct qla_hw_data *ha = vha->hw;
4488 uint32_t drv_presence;
4489
4490 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
4491 if (rval == QLA_SUCCESS) {
4492 drv_presence |= (1 << ha->portnum);
4493 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
4494 drv_presence);
4495 }
4496
4497 return rval;
4498}
4499
4500int
4501qla83xx_set_drv_presence(scsi_qla_host_t *vha)
4502{
4503 int rval = QLA_SUCCESS;
4504
4505 qla83xx_idc_lock(vha, 0);
4506 rval = __qla83xx_set_drv_presence(vha);
4507 qla83xx_idc_unlock(vha, 0);
4508
4509 return rval;
4510}
4511
4512int
4513__qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
4514{
4515 int rval = QLA_SUCCESS;
4516 struct qla_hw_data *ha = vha->hw;
4517 uint32_t drv_presence;
4518
4519 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
4520 if (rval == QLA_SUCCESS) {
4521 drv_presence &= ~(1 << ha->portnum);
4522 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
4523 drv_presence);
4524 }
4525
4526 return rval;
4527}
4528
4529int
4530qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
4531{
4532 int rval = QLA_SUCCESS;
4533
4534 qla83xx_idc_lock(vha, 0);
4535 rval = __qla83xx_clear_drv_presence(vha);
4536 qla83xx_idc_unlock(vha, 0);
4537
4538 return rval;
4539}
4540
fa492630 4541static void
7d613ac6
SV		 4542qla83xx_need_reset_handler(scsi_qla_host_t *vha)
4543{
4544 struct qla_hw_data *ha = vha->hw;
4545 uint32_t drv_ack, drv_presence;
4546 unsigned long ack_timeout;
4547
4548 /* Wait for IDC ACK from all functions (DRV-ACK == DRV-PRESENCE) */
4549 ack_timeout = jiffies + (ha->fcoe_reset_timeout * HZ);
4550 while (1) {
4551 qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
4552 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
807fb6d8 4553 if ((drv_ack & drv_presence) == drv_presence)
7d613ac6
SV		 4554 break;
4555
4556 if (time_after_eq(jiffies, ack_timeout)) {
4557 ql_log(ql_log_warn, vha, 0xb067,
4558 "RESET ACK TIMEOUT! drv_presence=0x%x "
4559 "drv_ack=0x%x\n", drv_presence, drv_ack);
4560 /*
4561 * The function(s) which did not ack in time are forced
4562 * to withdraw any further participation in the IDC
4563 * reset.
4564 */
4565 if (drv_ack != drv_presence)
4566 qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
4567 drv_ack);
4568 break;
4569 }
4570
4571 qla83xx_idc_unlock(vha, 0);
4572 msleep(1000);
4573 qla83xx_idc_lock(vha, 0);
4574 }
4575
4576 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_COLD);
4577 ql_log(ql_log_info, vha, 0xb068, "HW State: COLD/RE-INIT.\n");
4578}
4579
fa492630 4580static int
7d613ac6
SV		 4581qla83xx_device_bootstrap(scsi_qla_host_t *vha)
4582{
4583 int rval = QLA_SUCCESS;
4584 uint32_t idc_control;
4585
4586 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_INITIALIZING);
4587 ql_log(ql_log_info, vha, 0xb069, "HW State: INITIALIZING.\n");
4588
4589 /* Clearing IDC-Control Graceful-Reset Bit before resetting f/w */
4590 __qla83xx_get_idc_control(vha, &idc_control);
4591 idc_control &= ~QLA83XX_IDC_GRACEFUL_RESET;
4592 __qla83xx_set_idc_control(vha, 0);
4593
4594 qla83xx_idc_unlock(vha, 0);
4595 rval = qla83xx_restart_nic_firmware(vha);
4596 qla83xx_idc_lock(vha, 0);
4597
4598 if (rval != QLA_SUCCESS) {
4599 ql_log(ql_log_fatal, vha, 0xb06a,
4600 "Failed to restart NIC f/w.\n");
4601 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_FAILED);
4602 ql_log(ql_log_info, vha, 0xb06b, "HW State: FAILED.\n");
4603 } else {
4604 ql_dbg(ql_dbg_p3p, vha, 0xb06c,
4605 "Success in restarting nic f/w.\n");
4606 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_READY);
4607 ql_log(ql_log_info, vha, 0xb06d, "HW State: READY.\n");
4608 }
4609
4610 return rval;
4611}
4612
4613/* Assumes idc_lock always held on entry */
4614int
4615qla83xx_idc_state_handler(scsi_qla_host_t *base_vha)
4616{
4617 struct qla_hw_data *ha = base_vha->hw;
4618 int rval = QLA_SUCCESS;
4619 unsigned long dev_init_timeout;
4620 uint32_t dev_state;
4621
4622 /* Wait for MAX-INIT-TIMEOUT for the device to go ready */
4623 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ);
4624
4625 while (1) {
4626
4627 if (time_after_eq(jiffies, dev_init_timeout)) {
4628 ql_log(ql_log_warn, base_vha, 0xb06e,
4629 "Initialization TIMEOUT!\n");
4630 /* Init timeout. Disable further NIC Core
4631 * communication.
4632 */
4633 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
4634 QLA8XXX_DEV_FAILED);
4635 ql_log(ql_log_info, base_vha, 0xb06f,
4636 "HW State: FAILED.\n");
4637 }
4638
4639 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4640 switch (dev_state) {
4641 case QLA8XXX_DEV_READY:
4642 if (ha->flags.nic_core_reset_owner)
4643 qla83xx_idc_audit(base_vha,
4644 IDC_AUDIT_COMPLETION);
4645 ha->flags.nic_core_reset_owner = 0;
4646 ql_dbg(ql_dbg_p3p, base_vha, 0xb070,
4647 "Reset_owner reset by 0x%x.\n",
4648 ha->portnum);
4649 goto exit;
4650 case QLA8XXX_DEV_COLD:
4651 if (ha->flags.nic_core_reset_owner)
4652 rval = qla83xx_device_bootstrap(base_vha);
4653 else {
4654 /* Wait for AEN to change device-state */
4655 qla83xx_idc_unlock(base_vha, 0);
4656 msleep(1000);
4657 qla83xx_idc_lock(base_vha, 0);
4658 }
4659 break;
4660 case QLA8XXX_DEV_INITIALIZING:
4661 /* Wait for AEN to change device-state */
4662 qla83xx_idc_unlock(base_vha, 0);
4663 msleep(1000);
4664 qla83xx_idc_lock(base_vha, 0);
4665 break;
4666 case QLA8XXX_DEV_NEED_RESET:
4667 if (!ql2xdontresethba && ha->flags.nic_core_reset_owner)
4668 qla83xx_need_reset_handler(base_vha);
4669 else {
4670 /* Wait for AEN to change device-state */
4671 qla83xx_idc_unlock(base_vha, 0);
4672 msleep(1000);
4673 qla83xx_idc_lock(base_vha, 0);
4674 }
4675 /* reset timeout value after need reset handler */
4676 dev_init_timeout = jiffies +
4677 (ha->fcoe_dev_init_timeout * HZ);
4678 break;
4679 case QLA8XXX_DEV_NEED_QUIESCENT:
4680 /* XXX: DEBUG for now */
4681 qla83xx_idc_unlock(base_vha, 0);
4682 msleep(1000);
4683 qla83xx_idc_lock(base_vha, 0);
4684 break;
4685 case QLA8XXX_DEV_QUIESCENT:
4686 /* XXX: DEBUG for now */
4687 if (ha->flags.quiesce_owner)
4688 goto exit;
4689
4690 qla83xx_idc_unlock(base_vha, 0);
4691 msleep(1000);
4692 qla83xx_idc_lock(base_vha, 0);
4693 dev_init_timeout = jiffies +
4694 (ha->fcoe_dev_init_timeout * HZ);
4695 break;
4696 case QLA8XXX_DEV_FAILED:
4697 if (ha->flags.nic_core_reset_owner)
4698 qla83xx_idc_audit(base_vha,
4699 IDC_AUDIT_COMPLETION);
4700 ha->flags.nic_core_reset_owner = 0;
4701 __qla83xx_clear_drv_presence(base_vha);
4702 qla83xx_idc_unlock(base_vha, 0);
4703 qla8xxx_dev_failed_handler(base_vha);
4704 rval = QLA_FUNCTION_FAILED;
4705 qla83xx_idc_lock(base_vha, 0);
4706 goto exit;
4707 case QLA8XXX_BAD_VALUE:
4708 qla83xx_idc_unlock(base_vha, 0);
4709 msleep(1000);
4710 qla83xx_idc_lock(base_vha, 0);
4711 break;
4712 default:
4713 ql_log(ql_log_warn, base_vha, 0xb071,
d939be3a 4714 "Unknown Device State: %x.\n", dev_state);
7d613ac6
SV		 4715 qla83xx_idc_unlock(base_vha, 0);
4716 qla8xxx_dev_failed_handler(base_vha);
4717 rval = QLA_FUNCTION_FAILED;
4718 qla83xx_idc_lock(base_vha, 0);
4719 goto exit;
4720 }
4721 }
4722
4723exit:
4724 return rval;
4725}
4726
f3ddac19
CD		 4727void
4728qla2x00_disable_board_on_pci_error(struct work_struct *work)
4729{
4730 struct qla_hw_data *ha = container_of(work, struct qla_hw_data,
4731 board_disable);
4732 struct pci_dev *pdev = ha->pdev;
4733 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4734
4735 ql_log(ql_log_warn, base_vha, 0x015b,
4736 "Disabling adapter.\n");
4737
4738 set_bit(UNLOADING, &base_vha->dpc_flags);
4739
4740 qla2x00_delete_all_vps(ha, base_vha);
4741
4742 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
4743
4744 qla2x00_dfs_remove(base_vha);
4745
4746 qla84xx_put_chip(base_vha);
4747
4748 if (base_vha->timer_active)
4749 qla2x00_stop_timer(base_vha);
4750
4751 base_vha->flags.online = 0;
4752
4753 qla2x00_destroy_deferred_work(ha);
4754
4755 /*
4756 * Do not try to stop beacon blink as it will issue a mailbox
4757 * command.
4758 */
4759 qla2x00_free_sysfs_attr(base_vha, false);
4760
4761 fc_remove_host(base_vha->host);
4762
4763 scsi_remove_host(base_vha->host);
4764
4765 base_vha->flags.init_done = 0;
4766 qla25xx_delete_queues(base_vha);
4767 qla2x00_free_irqs(base_vha);
4768 qla2x00_free_fcports(base_vha);
4769 qla2x00_mem_free(ha);
4770 qla82xx_md_free(base_vha);
4771 qla2x00_free_queues(ha);
4772
f3ddac19
CD		 4773 qla2x00_unmap_iobases(ha);
4774
4775 pci_release_selected_regions(ha->pdev, ha->bars);
f3ddac19
CD		 4776 pci_disable_pcie_error_reporting(pdev);
4777 pci_disable_device(pdev);
f3ddac19 4778
beb9e315
JL		 4779 /*
4780 * Let qla2x00_remove_one cleanup qla_hw_data on device removal.
4781 */
f3ddac19
CD		 4782}
4783
1da177e4
LT		 4784/**************************************************************************
4785* qla2x00_do_dpc
4786* This kernel thread is a task that is schedule by the interrupt handler
4787* to perform the background processing for interrupts.
4788*
4789* Notes:
4790* This task always run in the context of a kernel thread. It
4791* is kick-off by the driver's detect code and starts up
4792* up one per adapter. It immediately goes to sleep and waits for
4793* some fibre event. When either the interrupt handler or
4794* the timer routine detects a event it will one of the task
4795* bits then wake us up.
4796**************************************************************************/
4797static int
4798qla2x00_do_dpc(void *data)
4799{
2c3dfe3f 4800 int rval;
e315cd28
AC		 4801 scsi_qla_host_t *base_vha;
4802 struct qla_hw_data *ha;
1da177e4 4803
e315cd28
AC		 4804 ha = (struct qla_hw_data *)data;
4805 base_vha = pci_get_drvdata(ha->pdev);
1da177e4 4806
8698a745 4807 set_user_nice(current, MIN_NICE);
1da177e4 4808
563585ec 4809 set_current_state(TASK_INTERRUPTIBLE);
39a11240 4810 while (!kthread_should_stop()) {
7c3df132
SK		 4811 ql_dbg(ql_dbg_dpc, base_vha, 0x4000,
4812 "DPC handler sleeping.\n");
1da177e4 4813
39a11240 4814 schedule();
1da177e4 4815
c142caf0
AV		 4816 if (!base_vha->flags.init_done || ha->flags.mbox_busy)
4817 goto end_loop;
1da177e4 4818
85880801 4819 if (ha->flags.eeh_busy) {
7c3df132
SK		 4820 ql_dbg(ql_dbg_dpc, base_vha, 0x4003,
4821 "eeh_busy=%d.\n", ha->flags.eeh_busy);
c142caf0 4822 goto end_loop;
85880801
AV		 4823 }
4824
1da177e4
LT		 4825 ha->dpc_active = 1;
4826
5f28d2d7
SK		 4827 ql_dbg(ql_dbg_dpc + ql_dbg_verbose, base_vha, 0x4001,
4828 "DPC handler waking up, dpc_flags=0x%lx.\n",
4829 base_vha->dpc_flags);
1da177e4 4830
e315cd28 4831 qla2x00_do_work(base_vha);
0971de7f 4832
7ec0effd
AD		 4833 if (IS_P3P_TYPE(ha)) {
4834 if (IS_QLA8044(ha)) {
4835 if (test_and_clear_bit(ISP_UNRECOVERABLE,
4836 &base_vha->dpc_flags)) {
4837 qla8044_idc_lock(ha);
4838 qla8044_wr_direct(base_vha,
4839 QLA8044_CRB_DEV_STATE_INDEX,
4840 QLA8XXX_DEV_FAILED);
4841 qla8044_idc_unlock(ha);
4842 ql_log(ql_log_info, base_vha, 0x4004,
4843 "HW State: FAILED.\n");
4844 qla8044_device_state_handler(base_vha);
4845 continue;
4846 }
4847
4848 } else {
4849 if (test_and_clear_bit(ISP_UNRECOVERABLE,
4850 &base_vha->dpc_flags)) {
4851 qla82xx_idc_lock(ha);
4852 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
4853 QLA8XXX_DEV_FAILED);
4854 qla82xx_idc_unlock(ha);
4855 ql_log(ql_log_info, base_vha, 0x0151,
4856 "HW State: FAILED.\n");
4857 qla82xx_device_state_handler(base_vha);
4858 continue;
4859 }
a9083016
GM		 4860 }
4861
4862 if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED,
4863 &base_vha->dpc_flags)) {
4864
7c3df132
SK		 4865 ql_dbg(ql_dbg_dpc, base_vha, 0x4005,
4866 "FCoE context reset scheduled.\n");
a9083016
GM		 4867 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
4868 &base_vha->dpc_flags))) {
4869 if (qla82xx_fcoe_ctx_reset(base_vha)) {
4870 /* FCoE-ctx reset failed.
4871 * Escalate to chip-reset
4872 */
4873 set_bit(ISP_ABORT_NEEDED,
4874 &base_vha->dpc_flags);
4875 }
4876 clear_bit(ABORT_ISP_ACTIVE,
4877 &base_vha->dpc_flags);
4878 }
4879
7c3df132
SK		 4880 ql_dbg(ql_dbg_dpc, base_vha, 0x4006,
4881 "FCoE context reset end.\n");
a9083016 4882 }
8ae6d9c7
GM		 4883 } else if (IS_QLAFX00(ha)) {
4884 if (test_and_clear_bit(ISP_UNRECOVERABLE,
4885 &base_vha->dpc_flags)) {
4886 ql_dbg(ql_dbg_dpc, base_vha, 0x4020,
4887 "Firmware Reset Recovery\n");
4888 if (qlafx00_reset_initialize(base_vha)) {
4889 /* Failed. Abort isp later. */
4890 if (!test_bit(UNLOADING,
f92f82d6 4891 &base_vha->dpc_flags)) {
8ae6d9c7
GM		 4892 set_bit(ISP_UNRECOVERABLE,
4893 &base_vha->dpc_flags);
4894 ql_dbg(ql_dbg_dpc, base_vha,
4895 0x4021,
4896 "Reset Recovery Failed\n");
f92f82d6 4897 }
8ae6d9c7
GM		 4898 }
4899 }
4900
4901 if (test_and_clear_bit(FX00_TARGET_SCAN,
4902 &base_vha->dpc_flags)) {
4903 ql_dbg(ql_dbg_dpc, base_vha, 0x4022,
4904 "ISPFx00 Target Scan scheduled\n");
4905 if (qlafx00_rescan_isp(base_vha)) {
4906 if (!test_bit(UNLOADING,
4907 &base_vha->dpc_flags))
4908 set_bit(ISP_UNRECOVERABLE,
4909 &base_vha->dpc_flags);
4910 ql_dbg(ql_dbg_dpc, base_vha, 0x401e,
4911 "ISPFx00 Target Scan Failed\n");
4912 }
4913 ql_dbg(ql_dbg_dpc, base_vha, 0x401f,
4914 "ISPFx00 Target Scan End\n");
4915 }
e8f5e95d
AB		 4916 if (test_and_clear_bit(FX00_HOST_INFO_RESEND,
4917 &base_vha->dpc_flags)) {
4918 ql_dbg(ql_dbg_dpc, base_vha, 0x4023,
4919 "ISPFx00 Host Info resend scheduled\n");
4920 qlafx00_fx_disc(base_vha,
4921 &base_vha->hw->mr.fcport,
4922 FXDISC_REG_HOST_INFO);
4923 }
a9083016
GM		 4924 }
4925
e315cd28
AC		 4926 if (test_and_clear_bit(ISP_ABORT_NEEDED,
4927 &base_vha->dpc_flags)) {
1da177e4 4928
7c3df132
SK		 4929 ql_dbg(ql_dbg_dpc, base_vha, 0x4007,
4930 "ISP abort scheduled.\n");
1da177e4 4931 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
e315cd28 4932 &base_vha->dpc_flags))) {
1da177e4 4933
a9083016 4934 if (ha->isp_ops->abort_isp(base_vha)) {
1da177e4
LT		 4935 /* failed. retry later */
4936 set_bit(ISP_ABORT_NEEDED,
e315cd28 4937 &base_vha->dpc_flags);
99363ef8 4938 }
e315cd28
AC		 4939 clear_bit(ABORT_ISP_ACTIVE,
4940 &base_vha->dpc_flags);
99363ef8
SJ		 4941 }
4942
7c3df132
SK		 4943 ql_dbg(ql_dbg_dpc, base_vha, 0x4008,
4944 "ISP abort end.\n");
1da177e4
LT		 4945 }
4946
a394aac8
DJ		 4947 if (test_and_clear_bit(FCPORT_UPDATE_NEEDED,
4948 &base_vha->dpc_flags)) {
e315cd28 4949 qla2x00_update_fcports(base_vha);
c9c5ced9 4950 }
d97994dc 4951
2d70c103
NB		 4952 if (test_bit(SCR_PENDING, &base_vha->dpc_flags)) {
4953 int ret;
4954 ret = qla2x00_send_change_request(base_vha, 0x3, 0);
4955 if (ret != QLA_SUCCESS)
4956 ql_log(ql_log_warn, base_vha, 0x121,
4957 "Failed to enable receiving of RSCN "
4958 "requests: 0x%x.\n", ret);
4959 clear_bit(SCR_PENDING, &base_vha->dpc_flags);
4960 }
4961
8ae6d9c7
GM		 4962 if (IS_QLAFX00(ha))
4963 goto loop_resync_check;
4964
579d12b5 4965 if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) {
7c3df132
SK		 4966 ql_dbg(ql_dbg_dpc, base_vha, 0x4009,
4967 "Quiescence mode scheduled.\n");
7ec0effd
AD		 4968 if (IS_P3P_TYPE(ha)) {
4969 if (IS_QLA82XX(ha))
4970 qla82xx_device_state_handler(base_vha);
4971 if (IS_QLA8044(ha))
4972 qla8044_device_state_handler(base_vha);
8fcd6b8b
CD		 4973 clear_bit(ISP_QUIESCE_NEEDED,
4974 &base_vha->dpc_flags);
4975 if (!ha->flags.quiesce_owner) {
4976 qla2x00_perform_loop_resync(base_vha);
7ec0effd
AD		 4977 if (IS_QLA82XX(ha)) {
4978 qla82xx_idc_lock(ha);
4979 qla82xx_clear_qsnt_ready(
4980 base_vha);
4981 qla82xx_idc_unlock(ha);
4982 } else if (IS_QLA8044(ha)) {
4983 qla8044_idc_lock(ha);
4984 qla8044_clear_qsnt_ready(
4985 base_vha);
4986 qla8044_idc_unlock(ha);
4987 }
8fcd6b8b
CD		 4988 }
4989 } else {
4990 clear_bit(ISP_QUIESCE_NEEDED,
4991 &base_vha->dpc_flags);
4992 qla2x00_quiesce_io(base_vha);
579d12b5 4993 }
7c3df132
SK		 4994 ql_dbg(ql_dbg_dpc, base_vha, 0x400a,
4995 "Quiescence mode end.\n");
579d12b5
SK		 4996 }
4997
e315cd28 4998 if (test_and_clear_bit(RESET_MARKER_NEEDED,
8ae6d9c7 4999 &base_vha->dpc_flags) &&
e315cd28 5000 (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) {
1da177e4 5001
7c3df132
SK		 5002 ql_dbg(ql_dbg_dpc, base_vha, 0x400b,
5003 "Reset marker scheduled.\n");
e315cd28
AC		 5004 qla2x00_rst_aen(base_vha);
5005 clear_bit(RESET_ACTIVE, &base_vha->dpc_flags);
7c3df132
SK		 5006 ql_dbg(ql_dbg_dpc, base_vha, 0x400c,
5007 "Reset marker end.\n");
1da177e4
LT		 5008 }
5009
5010 /* Retry each device up to login retry count */
e315cd28
AC		 5011 if ((test_and_clear_bit(RELOGIN_NEEDED,
5012 &base_vha->dpc_flags)) &&
5013 !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) &&
5014 atomic_read(&base_vha->loop_state) != LOOP_DOWN) {
1da177e4 5015
7c3df132
SK		 5016 ql_dbg(ql_dbg_dpc, base_vha, 0x400d,
5017 "Relogin scheduled.\n");
e315cd28 5018 qla2x00_relogin(base_vha);
7c3df132
SK		 5019 ql_dbg(ql_dbg_dpc, base_vha, 0x400e,
5020 "Relogin end.\n");
1da177e4 5021 }
8ae6d9c7 5022loop_resync_check:
e315cd28 5023 if (test_and_clear_bit(LOOP_RESYNC_NEEDED,
8ae6d9c7 5024 &base_vha->dpc_flags)) {
1da177e4 5025
7c3df132
SK		 5026 ql_dbg(ql_dbg_dpc, base_vha, 0x400f,
5027 "Loop resync scheduled.\n");
1da177e4
LT		 5028
5029 if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE,
e315cd28 5030 &base_vha->dpc_flags))) {
1da177e4 5031
e315cd28 5032 rval = qla2x00_loop_resync(base_vha);
1da177e4 5033
e315cd28
AC		 5034 clear_bit(LOOP_RESYNC_ACTIVE,
5035 &base_vha->dpc_flags);
1da177e4
LT		 5036 }
5037
7c3df132
SK		 5038 ql_dbg(ql_dbg_dpc, base_vha, 0x4010,
5039 "Loop resync end.\n");
1da177e4
LT		 5040 }
5041
8ae6d9c7
GM		 5042 if (IS_QLAFX00(ha))
5043 goto intr_on_check;
5044
e315cd28
AC		 5045 if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) &&
5046 atomic_read(&base_vha->loop_state) == LOOP_READY) {
5047 clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags);
5048 qla2xxx_flash_npiv_conf(base_vha);
272976ca
AV		 5049 }
5050
8ae6d9c7 5051intr_on_check:
1da177e4 5052 if (!ha->interrupts_on)
fd34f556 5053 ha->isp_ops->enable_intrs(ha);
1da177e4 5054
e315cd28 5055 if (test_and_clear_bit(BEACON_BLINK_NEEDED,
90b604f2
HM		 5056 &base_vha->dpc_flags)) {
5057 if (ha->beacon_blink_led == 1)
5058 ha->isp_ops->beacon_blink(base_vha);
5059 }
f6df144c 5060
8ae6d9c7
GM		 5061 if (!IS_QLAFX00(ha))
5062 qla2x00_do_dpc_all_vps(base_vha);
2c3dfe3f 5063
1da177e4 5064 ha->dpc_active = 0;
c142caf0 5065end_loop:
563585ec 5066 set_current_state(TASK_INTERRUPTIBLE);
1da177e4 5067 } /* End of while(1) */
563585ec 5068 __set_current_state(TASK_RUNNING);
1da177e4 5069
7c3df132
SK		 5070 ql_dbg(ql_dbg_dpc, base_vha, 0x4011,
5071 "DPC handler exiting.\n");
1da177e4
LT		 5072
5073 /*
5074 * Make sure that nobody tries to wake us up again.
5075 */
1da177e4
LT		 5076 ha->dpc_active = 0;
5077
ac280b67
AV		 5078 /* Cleanup any residual CTX SRBs. */
5079 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
5080
39a11240
CH		 5081 return 0;
5082}
5083
5084void
e315cd28 5085qla2xxx_wake_dpc(struct scsi_qla_host *vha)
39a11240 5086{
e315cd28 5087 struct qla_hw_data *ha = vha->hw;
c795c1e4
AV		 5088 struct task_struct *t = ha->dpc_thread;
5089
e315cd28 5090 if (!test_bit(UNLOADING, &vha->dpc_flags) && t)
c795c1e4 5091 wake_up_process(t);
1da177e4
LT		 5092}
5093
1da177e4
LT		 5094/*
5095* qla2x00_rst_aen
5096* Processes asynchronous reset.
5097*
5098* Input:
5099* ha = adapter block pointer.
5100*/
5101static void
e315cd28 5102qla2x00_rst_aen(scsi_qla_host_t *vha)
1da177e4 5103{
e315cd28
AC		 5104 if (vha->flags.online && !vha->flags.reset_active &&
5105 !atomic_read(&vha->loop_down_timer) &&
5106 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) {
1da177e4 5107 do {
e315cd28 5108 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
1da177e4
LT		 5109
5110 /*
5111 * Issue marker command only when we are going to start
5112 * the I/O.
5113 */
e315cd28
AC		 5114 vha->marker_needed = 1;
5115 } while (!atomic_read(&vha->loop_down_timer) &&
5116 (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)));
1da177e4
LT		 5117 }
5118}
5119
1da177e4
LT		 5120/**************************************************************************
5121* qla2x00_timer
5122*
5123* Description:
5124* One second timer
5125*
5126* Context: Interrupt
5127***************************************************************************/
2c3dfe3f 5128void
e315cd28 5129qla2x00_timer(scsi_qla_host_t *vha)
1da177e4 5130{
1da177e4 5131 unsigned long cpu_flags = 0;
1da177e4
LT		 5132 int start_dpc = 0;
5133 int index;
5134 srb_t *sp;
85880801 5135 uint16_t w;
e315cd28 5136 struct qla_hw_data *ha = vha->hw;
73208dfd 5137 struct req_que *req;
85880801 5138
a5b36321 5139 if (ha->flags.eeh_busy) {
7c3df132
SK		 5140 ql_dbg(ql_dbg_timer, vha, 0x6000,
5141 "EEH = %d, restarting timer.\n",
5142 ha->flags.eeh_busy);
a5b36321
LC		 5143 qla2x00_restart_timer(vha, WATCH_INTERVAL);
5144 return;
5145 }
5146
f3ddac19
CD		 5147 /*
5148 * Hardware read to raise pending EEH errors during mailbox waits. If
5149 * the read returns -1 then disable the board.
5150 */
5151 if (!pci_channel_offline(ha->pdev)) {
85880801 5152 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w);
c821e0d5 5153 qla2x00_check_reg16_for_disconnect(vha, w);
f3ddac19 5154 }
1da177e4 5155
cefcaba6 5156 /* Make sure qla82xx_watchdog is run only for physical port */
7ec0effd 5157 if (!vha->vp_idx && IS_P3P_TYPE(ha)) {
579d12b5
SK		 5158 if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags))
5159 start_dpc++;
7ec0effd
AD		 5160 if (IS_QLA82XX(ha))
5161 qla82xx_watchdog(vha);
5162 else if (IS_QLA8044(ha))
5163 qla8044_watchdog(vha);
579d12b5
SK		 5164 }
5165
8ae6d9c7
GM		 5166 if (!vha->vp_idx && IS_QLAFX00(ha))
5167 qlafx00_timer_routine(vha);
5168
1da177e4 5169 /* Loop down handler. */
e315cd28 5170 if (atomic_read(&vha->loop_down_timer) > 0 &&
8f7daead
GM		 5171 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) &&
5172 !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags))
e315cd28 5173 && vha->flags.online) {
1da177e4 5174
e315cd28
AC		 5175 if (atomic_read(&vha->loop_down_timer) ==
5176 vha->loop_down_abort_time) {
1da177e4 5177
7c3df132
SK		 5178 ql_log(ql_log_info, vha, 0x6008,
5179 "Loop down - aborting the queues before time expires.\n");
1da177e4 5180
e315cd28
AC		 5181 if (!IS_QLA2100(ha) && vha->link_down_timeout)
5182 atomic_set(&vha->loop_state, LOOP_DEAD);
1da177e4 5183
f08b7251
AV		 5184 /*
5185 * Schedule an ISP abort to return any FCP2-device
5186 * commands.
5187 */
2c3dfe3f 5188 /* NPIV - scan physical port only */
e315cd28 5189 if (!vha->vp_idx) {
2c3dfe3f
SJ		 5190 spin_lock_irqsave(&ha->hardware_lock,
5191 cpu_flags);
73208dfd 5192 req = ha->req_q_map[0];
2c3dfe3f 5193 for (index = 1;
8d93f550 5194 index < req->num_outstanding_cmds;
2c3dfe3f
SJ		 5195 index++) {
5196 fc_port_t *sfcp;
5197
e315cd28 5198 sp = req->outstanding_cmds[index];
2c3dfe3f
SJ		 5199 if (!sp)
5200 continue;
9ba56b95 5201 if (sp->type != SRB_SCSI_CMD)
cf53b069 5202 continue;
2c3dfe3f 5203 sfcp = sp->fcport;
f08b7251 5204 if (!(sfcp->flags & FCF_FCP2_DEVICE))
2c3dfe3f 5205 continue;
bdf79621 5206
8f7daead
GM		 5207 if (IS_QLA82XX(ha))
5208 set_bit(FCOE_CTX_RESET_NEEDED,
5209 &vha->dpc_flags);
5210 else
5211 set_bit(ISP_ABORT_NEEDED,
e315cd28 5212 &vha->dpc_flags);
2c3dfe3f
SJ		 5213 break;
5214 }
5215 spin_unlock_irqrestore(&ha->hardware_lock,
e315cd28 5216 cpu_flags);
1da177e4 5217 }
1da177e4
LT		 5218 start_dpc++;
5219 }
5220
5221 /* if the loop has been down for 4 minutes, reinit adapter */
e315cd28 5222 if (atomic_dec_and_test(&vha->loop_down_timer) != 0) {
0d6e61bc 5223 if (!(vha->device_flags & DFLG_NO_CABLE)) {
7c3df132 5224 ql_log(ql_log_warn, vha, 0x6009,
1da177e4
LT		 5225 "Loop down - aborting ISP.\n");
5226
8f7daead
GM		 5227 if (IS_QLA82XX(ha))
5228 set_bit(FCOE_CTX_RESET_NEEDED,
5229 &vha->dpc_flags);
5230 else
5231 set_bit(ISP_ABORT_NEEDED,
5232 &vha->dpc_flags);
1da177e4
LT		 5233 }
5234 }
7c3df132
SK		 5235 ql_dbg(ql_dbg_timer, vha, 0x600a,
5236 "Loop down - seconds remaining %d.\n",
5237 atomic_read(&vha->loop_down_timer));
1da177e4 5238 }
cefcaba6
SK		 5239 /* Check if beacon LED needs to be blinked for physical host only */
5240 if (!vha->vp_idx && (ha->beacon_blink_led == 1)) {
999916dc 5241 /* There is no beacon_blink function for ISP82xx */
7ec0effd 5242 if (!IS_P3P_TYPE(ha)) {
999916dc
SK		 5243 set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags);
5244 start_dpc++;
5245 }
f6df144c 5246 }
5247
550bf57d 5248 /* Process any deferred work. */
e315cd28 5249 if (!list_empty(&vha->work_list))
550bf57d
AV		 5250 start_dpc++;
5251
1da177e4 5252 /* Schedule the DPC routine if needed */
e315cd28
AC		 5253 if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) ||
5254 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) ||
5255 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags) ||
1da177e4 5256 start_dpc ||
e315cd28
AC		 5257 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) ||
5258 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) ||
a9083016
GM		 5259 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) ||
5260 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) ||
e315cd28 5261 test_bit(VP_DPC_NEEDED, &vha->dpc_flags) ||
50280c01 5262 test_bit(RELOGIN_NEEDED, &vha->dpc_flags))) {
7c3df132
SK		 5263 ql_dbg(ql_dbg_timer, vha, 0x600b,
5264 "isp_abort_needed=%d loop_resync_needed=%d "
5265 "fcport_update_needed=%d start_dpc=%d "
5266 "reset_marker_needed=%d",
5267 test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags),
5268 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags),
5269 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags),
5270 start_dpc,
5271 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags));
5272 ql_dbg(ql_dbg_timer, vha, 0x600c,
5273 "beacon_blink_needed=%d isp_unrecoverable=%d "
5274 "fcoe_ctx_reset_needed=%d vp_dpc_needed=%d "
50280c01 5275 "relogin_needed=%d.\n",
7c3df132
SK		 5276 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags),
5277 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags),
5278 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags),
5279 test_bit(VP_DPC_NEEDED, &vha->dpc_flags),
50280c01 5280 test_bit(RELOGIN_NEEDED, &vha->dpc_flags));
e315cd28 5281 qla2xxx_wake_dpc(vha);
7c3df132 5282 }
1da177e4 5283
e315cd28 5284 qla2x00_restart_timer(vha, WATCH_INTERVAL);
1da177e4
LT		 5285}
5286
5433383e
AV		 5287/* Firmware interface routines. */
5288
f73cb695 5289#define FW_BLOBS 11
5433383e
AV		 5290#define FW_ISP21XX 0
5291#define FW_ISP22XX 1
5292#define FW_ISP2300 2
5293#define FW_ISP2322 3
48c02fde 5294#define FW_ISP24XX 4
c3a2f0df 5295#define FW_ISP25XX 5
3a03eb79 5296#define FW_ISP81XX 6
a9083016 5297#define FW_ISP82XX 7
6246b8a1
GM		 5298#define FW_ISP2031 8
5299#define FW_ISP8031 9
2c5bbbb2 5300#define FW_ISP27XX 10
5433383e 5301
bb8ee499
AV		 5302#define FW_FILE_ISP21XX "ql2100_fw.bin"
5303#define FW_FILE_ISP22XX "ql2200_fw.bin"
5304#define FW_FILE_ISP2300 "ql2300_fw.bin"
5305#define FW_FILE_ISP2322 "ql2322_fw.bin"
5306#define FW_FILE_ISP24XX "ql2400_fw.bin"
c3a2f0df 5307#define FW_FILE_ISP25XX "ql2500_fw.bin"
3a03eb79 5308#define FW_FILE_ISP81XX "ql8100_fw.bin"
a9083016 5309#define FW_FILE_ISP82XX "ql8200_fw.bin"
6246b8a1
GM		 5310#define FW_FILE_ISP2031 "ql2600_fw.bin"
5311#define FW_FILE_ISP8031 "ql8300_fw.bin"
2c5bbbb2 5312#define FW_FILE_ISP27XX "ql2700_fw.bin"
f73cb695 5313
bb8ee499 5314
e1e82b6f 5315static DEFINE_MUTEX(qla_fw_lock);
5433383e
AV		 5316
5317static struct fw_blob qla_fw_blobs[FW_BLOBS] = {
bb8ee499
AV		 5318 { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, },
5319 { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, },
5320 { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, },
5321 { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, },
5322 { .name = FW_FILE_ISP24XX, },
c3a2f0df 5323 { .name = FW_FILE_ISP25XX, },
3a03eb79 5324 { .name = FW_FILE_ISP81XX, },
a9083016 5325 { .name = FW_FILE_ISP82XX, },
6246b8a1
GM		 5326 { .name = FW_FILE_ISP2031, },
5327 { .name = FW_FILE_ISP8031, },
2c5bbbb2 5328 { .name = FW_FILE_ISP27XX, },
5433383e
AV		 5329};
5330
5331struct fw_blob *
e315cd28 5332qla2x00_request_firmware(scsi_qla_host_t *vha)
5433383e 5333{
e315cd28 5334 struct qla_hw_data *ha = vha->hw;
5433383e
AV		 5335 struct fw_blob *blob;
5336
5433383e
AV		 5337 if (IS_QLA2100(ha)) {
5338 blob = &qla_fw_blobs[FW_ISP21XX];
5339 } else if (IS_QLA2200(ha)) {
5340 blob = &qla_fw_blobs[FW_ISP22XX];
48c02fde 5341 } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
5433383e 5342 blob = &qla_fw_blobs[FW_ISP2300];
48c02fde 5343 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
5433383e 5344 blob = &qla_fw_blobs[FW_ISP2322];
4d4df193 5345 } else if (IS_QLA24XX_TYPE(ha)) {
5433383e 5346 blob = &qla_fw_blobs[FW_ISP24XX];
c3a2f0df
AV		 5347 } else if (IS_QLA25XX(ha)) {
5348 blob = &qla_fw_blobs[FW_ISP25XX];
3a03eb79
AV		 5349 } else if (IS_QLA81XX(ha)) {
5350 blob = &qla_fw_blobs[FW_ISP81XX];
a9083016
GM		 5351 } else if (IS_QLA82XX(ha)) {
5352 blob = &qla_fw_blobs[FW_ISP82XX];
6246b8a1
GM		 5353 } else if (IS_QLA2031(ha)) {
5354 blob = &qla_fw_blobs[FW_ISP2031];
5355 } else if (IS_QLA8031(ha)) {
5356 blob = &qla_fw_blobs[FW_ISP8031];
2c5bbbb2
JC		 5357 } else if (IS_QLA27XX(ha)) {
5358 blob = &qla_fw_blobs[FW_ISP27XX];
8a655229
DC		 5359 } else {
5360 return NULL;
5433383e
AV		 5361 }
5362
e1e82b6f 5363 mutex_lock(&qla_fw_lock);
5433383e
AV		 5364 if (blob->fw)
5365 goto out;
5366
5367 if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) {
7c3df132
SK		 5368 ql_log(ql_log_warn, vha, 0x0063,
5369 "Failed to load firmware image (%s).\n", blob->name);
5433383e
AV		 5370 blob->fw = NULL;
5371 blob = NULL;
5372 goto out;
5373 }
5374
5375out:
e1e82b6f 5376 mutex_unlock(&qla_fw_lock);
5433383e
AV		 5377 return blob;
5378}
5379
5380static void
5381qla2x00_release_firmware(void)
5382{
5383 int idx;
5384
e1e82b6f 5385 mutex_lock(&qla_fw_lock);
5433383e 5386 for (idx = 0; idx < FW_BLOBS; idx++)
cf92549f 5387 release_firmware(qla_fw_blobs[idx].fw);
e1e82b6f 5388 mutex_unlock(&qla_fw_lock);
5433383e
AV		 5389}
5390
14e660e6
SJ		 5391static pci_ers_result_t
5392qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
5393{
85880801
AV		 5394 scsi_qla_host_t *vha = pci_get_drvdata(pdev);
5395 struct qla_hw_data *ha = vha->hw;
5396
7c3df132
SK		 5397 ql_dbg(ql_dbg_aer, vha, 0x9000,
5398 "PCI error detected, state %x.\n", state);
b9b12f73 5399
14e660e6
SJ		 5400 switch (state) {
5401 case pci_channel_io_normal:
85880801 5402 ha->flags.eeh_busy = 0;
14e660e6
SJ		 5403 return PCI_ERS_RESULT_CAN_RECOVER;
5404 case pci_channel_io_frozen:
85880801 5405 ha->flags.eeh_busy = 1;
a5b36321
LC		 5406 /* For ISP82XX complete any pending mailbox cmd */
5407 if (IS_QLA82XX(ha)) {
7190575f 5408 ha->flags.isp82xx_fw_hung = 1;
c8f6544e
CD		 5409 ql_dbg(ql_dbg_aer, vha, 0x9001, "Pci channel io frozen\n");
5410 qla82xx_clear_pending_mbx(vha);
a5b36321 5411 }
90a86fc0 5412 qla2x00_free_irqs(vha);
14e660e6 5413 pci_disable_device(pdev);
bddd2d65
LC		 5414 /* Return back all IOs */
5415 qla2x00_abort_all_cmds(vha, DID_RESET << 16);
14e660e6
SJ		 5416 return PCI_ERS_RESULT_NEED_RESET;
5417 case pci_channel_io_perm_failure:
85880801
AV		 5418 ha->flags.pci_channel_io_perm_failure = 1;
5419 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
14e660e6
SJ		 5420 return PCI_ERS_RESULT_DISCONNECT;
5421 }
5422 return PCI_ERS_RESULT_NEED_RESET;
5423}
5424
5425static pci_ers_result_t
5426qla2xxx_pci_mmio_enabled(struct pci_dev *pdev)
5427{
5428 int risc_paused = 0;
5429 uint32_t stat;
5430 unsigned long flags;
e315cd28
AC		 5431 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
5432 struct qla_hw_data *ha = base_vha->hw;
14e660e6
SJ		 5433 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
5434 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
5435
bcc5b6d3
SK		 5436 if (IS_QLA82XX(ha))
5437 return PCI_ERS_RESULT_RECOVERED;
5438
14e660e6
SJ		 5439 spin_lock_irqsave(&ha->hardware_lock, flags);
5440 if (IS_QLA2100(ha) || IS_QLA2200(ha)){
5441 stat = RD_REG_DWORD(&reg->hccr);
5442 if (stat & HCCR_RISC_PAUSE)
5443 risc_paused = 1;
5444 } else if (IS_QLA23XX(ha)) {
5445 stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
5446 if (stat & HSR_RISC_PAUSED)
5447 risc_paused = 1;
5448 } else if (IS_FWI2_CAPABLE(ha)) {
5449 stat = RD_REG_DWORD(&reg24->host_status);
5450 if (stat & HSRX_RISC_PAUSED)
5451 risc_paused = 1;
5452 }
5453 spin_unlock_irqrestore(&ha->hardware_lock, flags);
5454
5455 if (risc_paused) {
7c3df132
SK		 5456 ql_log(ql_log_info, base_vha, 0x9003,
5457 "RISC paused -- mmio_enabled, Dumping firmware.\n");
e315cd28 5458 ha->isp_ops->fw_dump(base_vha, 0);
14e660e6
SJ		 5459
5460 return PCI_ERS_RESULT_NEED_RESET;
5461 } else
5462 return PCI_ERS_RESULT_RECOVERED;
5463}
5464
fa492630
SK		 5465static uint32_t
5466qla82xx_error_recovery(scsi_qla_host_t *base_vha)
a5b36321
LC		 5467{
5468 uint32_t rval = QLA_FUNCTION_FAILED;
5469 uint32_t drv_active = 0;
5470 struct qla_hw_data *ha = base_vha->hw;
5471 int fn;
5472 struct pci_dev *other_pdev = NULL;
5473
7c3df132
SK		 5474 ql_dbg(ql_dbg_aer, base_vha, 0x9006,
5475 "Entered %s.\n", __func__);
a5b36321
LC		 5476
5477 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
5478
5479 if (base_vha->flags.online) {
5480 /* Abort all outstanding commands,
5481 * so as to be requeued later */
5482 qla2x00_abort_isp_cleanup(base_vha);
5483 }
5484
5485
5486 fn = PCI_FUNC(ha->pdev->devfn);
5487 while (fn > 0) {
5488 fn--;
7c3df132
SK		 5489 ql_dbg(ql_dbg_aer, base_vha, 0x9007,
5490 "Finding pci device at function = 0x%x.\n", fn);
a5b36321
LC		 5491 other_pdev =
5492 pci_get_domain_bus_and_slot(pci_domain_nr(ha->pdev->bus),
5493 ha->pdev->bus->number, PCI_DEVFN(PCI_SLOT(ha->pdev->devfn),
5494 fn));
5495
5496 if (!other_pdev)
5497 continue;
5498 if (atomic_read(&other_pdev->enable_cnt)) {
7c3df132
SK		 5499 ql_dbg(ql_dbg_aer, base_vha, 0x9008,
5500 "Found PCI func available and enable at 0x%x.\n",
5501 fn);
a5b36321
LC		 5502 pci_dev_put(other_pdev);
5503 break;
5504 }
5505 pci_dev_put(other_pdev);
5506 }
5507
5508 if (!fn) {
5509 /* Reset owner */
7c3df132
SK		 5510 ql_dbg(ql_dbg_aer, base_vha, 0x9009,
5511 "This devfn is reset owner = 0x%x.\n",
5512 ha->pdev->devfn);
a5b36321
LC		 5513 qla82xx_idc_lock(ha);
5514
5515 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 5516 QLA8XXX_DEV_INITIALIZING);
a5b36321
LC		 5517
5518 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION,
5519 QLA82XX_IDC_VERSION);
5520
5521 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
7c3df132
SK		 5522 ql_dbg(ql_dbg_aer, base_vha, 0x900a,
5523 "drv_active = 0x%x.\n", drv_active);
a5b36321
LC		 5524
5525 qla82xx_idc_unlock(ha);
5526 /* Reset if device is not already reset
5527 * drv_active would be 0 if a reset has already been done
5528 */
5529 if (drv_active)
5530 rval = qla82xx_start_firmware(base_vha);
5531 else
5532 rval = QLA_SUCCESS;
5533 qla82xx_idc_lock(ha);
5534
5535 if (rval != QLA_SUCCESS) {
7c3df132
SK		 5536 ql_log(ql_log_info, base_vha, 0x900b,
5537 "HW State: FAILED.\n");
a5b36321
LC		 5538 qla82xx_clear_drv_active(ha);
5539 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 5540 QLA8XXX_DEV_FAILED);
a5b36321 5541 } else {
7c3df132
SK		 5542 ql_log(ql_log_info, base_vha, 0x900c,
5543 "HW State: READY.\n");
a5b36321 5544 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 5545 QLA8XXX_DEV_READY);
a5b36321 5546 qla82xx_idc_unlock(ha);
7190575f 5547 ha->flags.isp82xx_fw_hung = 0;
a5b36321
LC		 5548 rval = qla82xx_restart_isp(base_vha);
5549 qla82xx_idc_lock(ha);
5550 /* Clear driver state register */
5551 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, 0);
5552 qla82xx_set_drv_active(base_vha);
5553 }
5554 qla82xx_idc_unlock(ha);
5555 } else {
7c3df132
SK		 5556 ql_dbg(ql_dbg_aer, base_vha, 0x900d,
5557 "This devfn is not reset owner = 0x%x.\n",
5558 ha->pdev->devfn);
a5b36321 5559 if ((qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE) ==
7d613ac6 5560 QLA8XXX_DEV_READY)) {
7190575f 5561 ha->flags.isp82xx_fw_hung = 0;
a5b36321
LC		 5562 rval = qla82xx_restart_isp(base_vha);
5563 qla82xx_idc_lock(ha);
5564 qla82xx_set_drv_active(base_vha);
5565 qla82xx_idc_unlock(ha);
5566 }
5567 }
5568 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
5569
5570 return rval;
5571}
5572
14e660e6
SJ		 5573static pci_ers_result_t
5574qla2xxx_pci_slot_reset(struct pci_dev *pdev)
5575{
5576 pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT;
e315cd28
AC		 5577 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
5578 struct qla_hw_data *ha = base_vha->hw;
90a86fc0
JC		 5579 struct rsp_que *rsp;
5580 int rc, retries = 10;
09483916 5581
7c3df132
SK		 5582 ql_dbg(ql_dbg_aer, base_vha, 0x9004,
5583 "Slot Reset.\n");
85880801 5584
90a86fc0
JC		 5585 /* Workaround: qla2xxx driver which access hardware earlier
5586 * needs error state to be pci_channel_io_online.
5587 * Otherwise mailbox command timesout.
5588 */
5589 pdev->error_state = pci_channel_io_normal;
5590
5591 pci_restore_state(pdev);
5592
8c1496bd
RL		 5593 /* pci_restore_state() clears the saved_state flag of the device
5594 * save restored state which resets saved_state flag
5595 */
5596 pci_save_state(pdev);
5597
09483916
BH		 5598 if (ha->mem_only)
5599 rc = pci_enable_device_mem(pdev);
5600 else
5601 rc = pci_enable_device(pdev);
14e660e6 5602
09483916 5603 if (rc) {
7c3df132 5604 ql_log(ql_log_warn, base_vha, 0x9005,
14e660e6 5605 "Can't re-enable PCI device after reset.\n");
a5b36321 5606 goto exit_slot_reset;
14e660e6 5607 }
14e660e6 5608
90a86fc0
JC		 5609 rsp = ha->rsp_q_map[0];
5610 if (qla2x00_request_irqs(ha, rsp))
a5b36321 5611 goto exit_slot_reset;
90a86fc0 5612
e315cd28 5613 if (ha->isp_ops->pci_config(base_vha))
a5b36321
LC		 5614 goto exit_slot_reset;
5615
5616 if (IS_QLA82XX(ha)) {
5617 if (qla82xx_error_recovery(base_vha) == QLA_SUCCESS) {
5618 ret = PCI_ERS_RESULT_RECOVERED;
5619 goto exit_slot_reset;
5620 } else
5621 goto exit_slot_reset;
5622 }
14e660e6 5623
90a86fc0
JC		 5624 while (ha->flags.mbox_busy && retries--)
5625 msleep(1000);
85880801 5626
e315cd28 5627 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
a9083016 5628 if (ha->isp_ops->abort_isp(base_vha) == QLA_SUCCESS)
14e660e6 5629 ret = PCI_ERS_RESULT_RECOVERED;
e315cd28 5630 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
14e660e6 5631
90a86fc0 5632
a5b36321 5633exit_slot_reset:
7c3df132
SK		 5634 ql_dbg(ql_dbg_aer, base_vha, 0x900e,
5635 "slot_reset return %x.\n", ret);
85880801 5636
14e660e6
SJ		 5637 return ret;
5638}
5639
5640static void
5641qla2xxx_pci_resume(struct pci_dev *pdev)
5642{
e315cd28
AC		 5643 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
5644 struct qla_hw_data *ha = base_vha->hw;
14e660e6
SJ		 5645 int ret;
5646
7c3df132
SK		 5647 ql_dbg(ql_dbg_aer, base_vha, 0x900f,
5648 "pci_resume.\n");
85880801 5649
e315cd28 5650 ret = qla2x00_wait_for_hba_online(base_vha);
14e660e6 5651 if (ret != QLA_SUCCESS) {
7c3df132
SK		 5652 ql_log(ql_log_fatal, base_vha, 0x9002,
5653 "The device failed to resume I/O from slot/link_reset.\n");
14e660e6 5654 }
85880801 5655
3e46f031
LC		 5656 pci_cleanup_aer_uncorrect_error_status(pdev);
5657
85880801 5658 ha->flags.eeh_busy = 0;
14e660e6
SJ		 5659}
5660
2d5a4c34
HM		 5661static void
5662qla83xx_disable_laser(scsi_qla_host_t *vha)
5663{
5664 uint32_t reg, data, fn;
5665 struct qla_hw_data *ha = vha->hw;
5666 struct device_reg_24xx __iomem *isp_reg = &ha->iobase->isp24;
5667
5668 /* pci func #/port # */
5669 ql_dbg(ql_dbg_init, vha, 0x004b,
5670 "Disabling Laser for hba: %p\n", vha);
5671
5672 fn = (RD_REG_DWORD(&isp_reg->ctrl_status) &
5673 (BIT_15|BIT_14|BIT_13|BIT_12));
5674
5675 fn = (fn >> 12);
5676
5677 if (fn & 1)
5678 reg = PORT_1_2031;
5679 else
5680 reg = PORT_0_2031;
5681
5682 data = LASER_OFF_2031;
5683
5684 qla83xx_wr_reg(vha, reg, data);
5685}
5686
a55b2d21 5687static const struct pci_error_handlers qla2xxx_err_handler = {
14e660e6
SJ		 5688 .error_detected = qla2xxx_pci_error_detected,
5689 .mmio_enabled = qla2xxx_pci_mmio_enabled,
5690 .slot_reset = qla2xxx_pci_slot_reset,
5691 .resume = qla2xxx_pci_resume,
5692};
5693
5433383e 5694static struct pci_device_id qla2xxx_pci_tbl[] = {
47f5e069
AV		 5695 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) },
5696 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) },
5697 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) },
5698 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) },
5699 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) },
5700 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) },
5701 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) },
5702 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) },
5703 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) },
4d4df193 5704 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) },
47f5e069
AV		 5705 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) },
5706 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) },
c3a2f0df 5707 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) },
6246b8a1 5708 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2031) },
3a03eb79 5709 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) },
a9083016 5710 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) },
650f528f 5711 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8031) },
8ae6d9c7 5712 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISPF001) },
7ec0effd 5713 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8044) },
f73cb695 5714 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2071) },
2c5bbbb2 5715 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2271) },
5433383e
AV		 5716 { 0 },
5717};
5718MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl);
5719
fca29703 5720static struct pci_driver qla2xxx_pci_driver = {
cb63067a 5721 .name = QLA2XXX_DRIVER_NAME,
0a21ef1e
JB		 5722 .driver = {
5723 .owner = THIS_MODULE,
5724 },
fca29703 5725 .id_table = qla2xxx_pci_tbl,
7ee61397 5726 .probe = qla2x00_probe_one,
4c993f76 5727 .remove = qla2x00_remove_one,
e30d1756 5728 .shutdown = qla2x00_shutdown,
14e660e6 5729 .err_handler = &qla2xxx_err_handler,
fca29703
AV		 5730};
5731
75ef9de1 5732static const struct file_operations apidev_fops = {
6a03b4cd 5733 .owner = THIS_MODULE,
6038f373 5734 .llseek = noop_llseek,
6a03b4cd
HZ		 5735};
5736
1da177e4
LT		 5737/**
5738 * qla2x00_module_init - Module initialization.
5739 **/
5740static int __init
5741qla2x00_module_init(void)
5742{
fca29703
AV		 5743 int ret = 0;
5744
1da177e4 5745 /* Allocate cache for SRBs. */
354d6b21 5746 srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0,
20c2df83 5747 SLAB_HWCACHE_ALIGN, NULL);
1da177e4 5748 if (srb_cachep == NULL) {
7c3df132
SK		 5749 ql_log(ql_log_fatal, NULL, 0x0001,
5750 "Unable to allocate SRB cache...Failing load!.\n");
1da177e4
LT		 5751 return -ENOMEM;
5752 }
5753
2d70c103
NB		 5754 /* Initialize target kmem_cache and mem_pools */
5755 ret = qlt_init();
5756 if (ret < 0) {
5757 kmem_cache_destroy(srb_cachep);
5758 return ret;
5759 } else if (ret > 0) {
5760 /*
5761 * If initiator mode is explictly disabled by qlt_init(),
5762 * prevent scsi_transport_fc.c:fc_scsi_scan_rport() from
5763 * performing scsi_scan_target() during LOOP UP event.
5764 */
5765 qla2xxx_transport_functions.disable_target_scan = 1;
5766 qla2xxx_transport_vport_functions.disable_target_scan = 1;
5767 }
5768
1da177e4
LT		 5769 /* Derive version string. */
5770 strcpy(qla2x00_version_str, QLA2XXX_VERSION);
11010fec 5771 if (ql2xextended_error_logging)
0181944f
AV		 5772 strcat(qla2x00_version_str, "-debug");
5773
1c97a12a
AV		 5774 qla2xxx_transport_template =
5775 fc_attach_transport(&qla2xxx_transport_functions);
2c3dfe3f
SJ		 5776 if (!qla2xxx_transport_template) {
5777 kmem_cache_destroy(srb_cachep);
7c3df132
SK		 5778 ql_log(ql_log_fatal, NULL, 0x0002,
5779 "fc_attach_transport failed...Failing load!.\n");
2d70c103 5780 qlt_exit();
1da177e4 5781 return -ENODEV;
2c3dfe3f 5782 }
6a03b4cd
HZ		 5783
5784 apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops);
5785 if (apidev_major < 0) {
7c3df132
SK		 5786 ql_log(ql_log_fatal, NULL, 0x0003,
5787 "Unable to register char device %s.\n", QLA2XXX_APIDEV);
6a03b4cd
HZ		 5788 }
5789
2c3dfe3f
SJ		 5790 qla2xxx_transport_vport_template =
5791 fc_attach_transport(&qla2xxx_transport_vport_functions);
5792 if (!qla2xxx_transport_vport_template) {
5793 kmem_cache_destroy(srb_cachep);
2d70c103 5794 qlt_exit();
2c3dfe3f 5795 fc_release_transport(qla2xxx_transport_template);
7c3df132
SK		 5796 ql_log(ql_log_fatal, NULL, 0x0004,
5797 "fc_attach_transport vport failed...Failing load!.\n");
1da177e4 5798 return -ENODEV;
2c3dfe3f 5799 }
7c3df132
SK		 5800 ql_log(ql_log_info, NULL, 0x0005,
5801 "QLogic Fibre Channel HBA Driver: %s.\n",
fd9a29f0 5802 qla2x00_version_str);
7ee61397 5803 ret = pci_register_driver(&qla2xxx_pci_driver);
fca29703
AV		 5804 if (ret) {
5805 kmem_cache_destroy(srb_cachep);
2d70c103 5806 qlt_exit();
fca29703 5807 fc_release_transport(qla2xxx_transport_template);
2c3dfe3f 5808 fc_release_transport(qla2xxx_transport_vport_template);
7c3df132
SK		 5809 ql_log(ql_log_fatal, NULL, 0x0006,
5810 "pci_register_driver failed...ret=%d Failing load!.\n",
5811 ret);
fca29703
AV		 5812 }
5813 return ret;
1da177e4
LT		 5814}
5815
5816/**
5817 * qla2x00_module_exit - Module cleanup.
5818 **/
5819static void __exit
5820qla2x00_module_exit(void)
5821{
6a03b4cd 5822 unregister_chrdev(apidev_major, QLA2XXX_APIDEV);
7ee61397 5823 pci_unregister_driver(&qla2xxx_pci_driver);
5433383e 5824 qla2x00_release_firmware();
354d6b21 5825 kmem_cache_destroy(srb_cachep);
2d70c103 5826 qlt_exit();
a9083016
GM		 5827 if (ctx_cachep)
5828 kmem_cache_destroy(ctx_cachep);
1da177e4 5829 fc_release_transport(qla2xxx_transport_template);
2c3dfe3f 5830 fc_release_transport(qla2xxx_transport_vport_template);
1da177e4
LT		 5831}
5832
5833module_init(qla2x00_module_init);
5834module_exit(qla2x00_module_exit);
5835
5836MODULE_AUTHOR("QLogic Corporation");
5837MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver");
5838MODULE_LICENSE("GPL");
5839MODULE_VERSION(QLA2XXX_VERSION);
bb8ee499
AV		 5840MODULE_FIRMWARE(FW_FILE_ISP21XX);
5841MODULE_FIRMWARE(FW_FILE_ISP22XX);
5842MODULE_FIRMWARE(FW_FILE_ISP2300);
5843MODULE_FIRMWARE(FW_FILE_ISP2322);
5844MODULE_FIRMWARE(FW_FILE_ISP24XX);
61623fc3 5845MODULE_FIRMWARE(FW_FILE_ISP25XX);
f1458cda
SC		 5846MODULE_FIRMWARE(FW_FILE_ISP2031);
5847MODULE_FIRMWARE(FW_FILE_ISP8031);
5848MODULE_FIRMWARE(FW_FILE_ISP27XX);
Linux 6.x block layer and io_uring tree(s)