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[SCSI] qla2xxx: Make the logging functions verify their arguments and fixed the curre...
[linux-2.6-block.git] / drivers / scsi / qla2xxx / qla_os.c
CommitLineData
1da177e4 1/*
fa90c54f 2 * QLogic Fibre Channel HBA Driver
07e264b7 3 * Copyright (c) 2003-2011 QLogic Corporation
1da177e4 4 *
fa90c54f 5 * See LICENSE.qla2xxx for copyright and licensing details.
1da177e4
LT		 6 */
7#include "qla_def.h"
8
9#include <linux/moduleparam.h>
10#include <linux/vmalloc.h>
1da177e4 11#include <linux/delay.h>
39a11240 12#include <linux/kthread.h>
e1e82b6f 13#include <linux/mutex.h>
3420d36c 14#include <linux/kobject.h>
5a0e3ad6 15#include <linux/slab.h>
1da177e4
LT		 16
17#include <scsi/scsi_tcq.h>
18#include <scsi/scsicam.h>
19#include <scsi/scsi_transport.h>
20#include <scsi/scsi_transport_fc.h>
21
22/*
23 * Driver version
24 */
25char qla2x00_version_str[40];
26
6a03b4cd
HZ		 27static int apidev_major;
28
1da177e4
LT		 29/*
30 * SRB allocation cache
31 */
e18b890b 32static struct kmem_cache *srb_cachep;
1da177e4 33
a9083016
GM		 34/*
35 * CT6 CTX allocation cache
36 */
37static struct kmem_cache *ctx_cachep;
3ce8866c
SK		 38/*
39 * error level for logging
40 */
41int ql_errlev = ql_log_all;
a9083016 42
1da177e4 43int ql2xlogintimeout = 20;
f2019cb1 44module_param(ql2xlogintimeout, int, S_IRUGO);
1da177e4
LT		 45MODULE_PARM_DESC(ql2xlogintimeout,
46 "Login timeout value in seconds.");
47
a7b61842 48int qlport_down_retry;
f2019cb1 49module_param(qlport_down_retry, int, S_IRUGO);
1da177e4 50MODULE_PARM_DESC(qlport_down_retry,
900d9f98 51 "Maximum number of command retries to a port that returns "
1da177e4
LT		 52 "a PORT-DOWN status.");
53
1da177e4
LT		 54int ql2xplogiabsentdevice;
55module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR);
56MODULE_PARM_DESC(ql2xplogiabsentdevice,
57 "Option to enable PLOGI to devices that are not present after "
900d9f98 58 "a Fabric scan. This is needed for several broken switches. "
1da177e4
LT		 59 "Default is 0 - no PLOGI. 1 - perfom PLOGI.");
60
1da177e4 61int ql2xloginretrycount = 0;
f2019cb1 62module_param(ql2xloginretrycount, int, S_IRUGO);
1da177e4
LT		 63MODULE_PARM_DESC(ql2xloginretrycount,
64 "Specify an alternate value for the NVRAM login retry count.");
65
a7a167bf 66int ql2xallocfwdump = 1;
f2019cb1 67module_param(ql2xallocfwdump, int, S_IRUGO);
a7a167bf
AV		 68MODULE_PARM_DESC(ql2xallocfwdump,
69 "Option to enable allocation of memory for a firmware dump "
70 "during HBA initialization. Memory allocation requirements "
71 "vary by ISP type. Default is 1 - allocate memory.");
72
11010fec 73int ql2xextended_error_logging;
27d94035 74module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
11010fec 75MODULE_PARM_DESC(ql2xextended_error_logging,
3ce8866c
SK		 76 "Option to enable extended error logging,\n"
77 "\t\tDefault is 0 - no logging. 0x40000000 - Module Init & Probe.\n"
78 "\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n"
79 "\t\t0x08000000 - IO tracing. 0x04000000 - DPC Thread.\n"
80 "\t\t0x02000000 - Async events. 0x01000000 - Timer routines.\n"
81 "\t\t0x00800000 - User space. 0x00400000 - Task Management.\n"
82 "\t\t0x00200000 - AER/EEH. 0x00100000 - Multi Q.\n"
83 "\t\t0x00080000 - P3P Specific. 0x00040000 - Virtual Port.\n"
84 "\t\t0x00020000 - Buffer Dump. 0x00010000 - Misc.\n"
85 "\t\t0x7fffffff - For enabling all logs, can be too many logs.\n"
86 "\t\tDo LOGICAL OR of the value to enable more than one level");
0181944f 87
a9083016 88int ql2xshiftctondsd = 6;
f2019cb1 89module_param(ql2xshiftctondsd, int, S_IRUGO);
a9083016
GM		 90MODULE_PARM_DESC(ql2xshiftctondsd,
91 "Set to control shifting of command type processing "
92 "based on total number of SG elements.");
93
1da177e4
LT		 94static void qla2x00_free_device(scsi_qla_host_t *);
95
7e47e5ca 96int ql2xfdmienable=1;
f2019cb1 97module_param(ql2xfdmienable, int, S_IRUGO);
cca5335c 98MODULE_PARM_DESC(ql2xfdmienable,
7794a5af
FW		 99 "Enables FDMI registrations. "
100 "0 - no FDMI. Default is 1 - perform FDMI.");
cca5335c 101
df7baa50
AV		 102#define MAX_Q_DEPTH 32
103static int ql2xmaxqdepth = MAX_Q_DEPTH;
104module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR);
105MODULE_PARM_DESC(ql2xmaxqdepth,
106 "Maximum queue depth to report for target devices.");
107
bad75002 108/* Do not change the value of this after module load */
8cb2049c 109int ql2xenabledif = 0;
bad75002
AE		 110module_param(ql2xenabledif, int, S_IRUGO|S_IWUSR);
111MODULE_PARM_DESC(ql2xenabledif,
112 " Enable T10-CRC-DIF "
8cb2049c
AE		 113 " Default is 0 - No DIF Support. 1 - Enable it"
114 ", 2 - Enable DIF for all types, except Type 0.");
bad75002 115
8cb2049c 116int ql2xenablehba_err_chk = 2;
bad75002
AE		 117module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR);
118MODULE_PARM_DESC(ql2xenablehba_err_chk,
8cb2049c
AE		 119 " Enable T10-CRC-DIF Error isolation by HBA:\n"
120 " Default is 1.\n"
121 " 0 -- Error isolation disabled\n"
122 " 1 -- Error isolation enabled only for DIX Type 0\n"
123 " 2 -- Error isolation enabled for all Types\n");
bad75002 124
e5896bd5 125int ql2xiidmaenable=1;
f2019cb1 126module_param(ql2xiidmaenable, int, S_IRUGO);
e5896bd5
AV		 127MODULE_PARM_DESC(ql2xiidmaenable,
128 "Enables iIDMA settings "
129 "Default is 1 - perform iIDMA. 0 - no iIDMA.");
130
73208dfd 131int ql2xmaxqueues = 1;
f2019cb1 132module_param(ql2xmaxqueues, int, S_IRUGO);
73208dfd
AC		 133MODULE_PARM_DESC(ql2xmaxqueues,
134 "Enables MQ settings "
ae68230c
JP		 135 "Default is 1 for single queue. Set it to number "
136 "of queues in MQ mode.");
68ca949c
AC		 137
138int ql2xmultique_tag;
f2019cb1 139module_param(ql2xmultique_tag, int, S_IRUGO);
68ca949c
AC		 140MODULE_PARM_DESC(ql2xmultique_tag,
141 "Enables CPU affinity settings for the driver "
142 "Default is 0 for no affinity of request and response IO. "
143 "Set it to 1 to turn on the cpu affinity.");
e337d907
AV		 144
145int ql2xfwloadbin;
86e45bf6 146module_param(ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
e337d907 147MODULE_PARM_DESC(ql2xfwloadbin,
7c3df132
SK		 148 "Option to specify location from which to load ISP firmware:.\n"
149 " 2 -- load firmware via the request_firmware() (hotplug).\n"
e337d907
AV		 150 " interface.\n"
151 " 1 -- load firmware from flash.\n"
152 " 0 -- use default semantics.\n");
153
ae97c91e 154int ql2xetsenable;
f2019cb1 155module_param(ql2xetsenable, int, S_IRUGO);
ae97c91e
AV		 156MODULE_PARM_DESC(ql2xetsenable,
157 "Enables firmware ETS burst."
158 "Default is 0 - skip ETS enablement.");
159
6907869d 160int ql2xdbwr = 1;
86e45bf6 161module_param(ql2xdbwr, int, S_IRUGO|S_IWUSR);
a9083016 162MODULE_PARM_DESC(ql2xdbwr,
08de2844
GM		 163 "Option to specify scheme for request queue posting.\n"
164 " 0 -- Regular doorbell.\n"
165 " 1 -- CAMRAM doorbell (faster).\n");
a9083016 166
f4c496c1 167int ql2xtargetreset = 1;
f2019cb1 168module_param(ql2xtargetreset, int, S_IRUGO);
f4c496c1
GM		 169MODULE_PARM_DESC(ql2xtargetreset,
170 "Enable target reset."
171 "Default is 1 - use hw defaults.");
172
4da26e16 173int ql2xgffidenable;
f2019cb1 174module_param(ql2xgffidenable, int, S_IRUGO);
4da26e16
CD		 175MODULE_PARM_DESC(ql2xgffidenable,
176 "Enables GFF_ID checks of port type. "
177 "Default is 0 - Do not use GFF_ID information.");
a9083016 178
3822263e 179int ql2xasynctmfenable;
f2019cb1 180module_param(ql2xasynctmfenable, int, S_IRUGO);
3822263e
MI		 181MODULE_PARM_DESC(ql2xasynctmfenable,
182 "Enables issue of TM IOCBs asynchronously via IOCB mechanism"
183 "Default is 0 - Issue TM IOCBs via mailbox mechanism.");
ed0de87c
GM		 184
185int ql2xdontresethba;
86e45bf6 186module_param(ql2xdontresethba, int, S_IRUGO|S_IWUSR);
ed0de87c 187MODULE_PARM_DESC(ql2xdontresethba,
08de2844
GM		 188 "Option to specify reset behaviour.\n"
189 " 0 (Default) -- Reset on failure.\n"
190 " 1 -- Do not reset on failure.\n");
ed0de87c 191
82515920
AV		 192uint ql2xmaxlun = MAX_LUNS;
193module_param(ql2xmaxlun, uint, S_IRUGO);
194MODULE_PARM_DESC(ql2xmaxlun,
195 "Defines the maximum LU number to register with the SCSI "
196 "midlayer. Default is 65535.");
197
08de2844
GM		 198int ql2xmdcapmask = 0x1F;
199module_param(ql2xmdcapmask, int, S_IRUGO);
200MODULE_PARM_DESC(ql2xmdcapmask,
201 "Set the Minidump driver capture mask level. "
202 "Default is 0x7F - Can be set to 0x3, 0x7, 0xF, 0x1F, 0x7F.");
203
3aadff35 204int ql2xmdenable = 1;
08de2844
GM		 205module_param(ql2xmdenable, int, S_IRUGO);
206MODULE_PARM_DESC(ql2xmdenable,
207 "Enable/disable MiniDump. "
3aadff35
GM		 208 "0 - MiniDump disabled. "
209 "1 (Default) - MiniDump enabled.");
08de2844 210
1da177e4 211/*
fa2a1ce5 212 * SCSI host template entry points
1da177e4
LT		 213 */
214static int qla2xxx_slave_configure(struct scsi_device * device);
f4f051eb 215static int qla2xxx_slave_alloc(struct scsi_device *);
1e99e33a
AV		 216static int qla2xxx_scan_finished(struct Scsi_Host *, unsigned long time);
217static void qla2xxx_scan_start(struct Scsi_Host *);
f4f051eb 218static void qla2xxx_slave_destroy(struct scsi_device *);
f281233d 219static int qla2xxx_queuecommand(struct Scsi_Host *h, struct scsi_cmnd *cmd);
1da177e4
LT		 220static int qla2xxx_eh_abort(struct scsi_cmnd *);
221static int qla2xxx_eh_device_reset(struct scsi_cmnd *);
523ec773 222static int qla2xxx_eh_target_reset(struct scsi_cmnd *);
1da177e4
LT		 223static int qla2xxx_eh_bus_reset(struct scsi_cmnd *);
224static int qla2xxx_eh_host_reset(struct scsi_cmnd *);
1da177e4 225
e881a172 226static int qla2x00_change_queue_depth(struct scsi_device *, int, int);
ce7e4af7
AV		 227static int qla2x00_change_queue_type(struct scsi_device *, int);
228
a5326f86 229struct scsi_host_template qla2xxx_driver_template = {
1da177e4 230 .module = THIS_MODULE,
cb63067a 231 .name = QLA2XXX_DRIVER_NAME,
a5326f86 232 .queuecommand = qla2xxx_queuecommand,
fca29703
AV		 233
234 .eh_abort_handler = qla2xxx_eh_abort,
235 .eh_device_reset_handler = qla2xxx_eh_device_reset,
523ec773 236 .eh_target_reset_handler = qla2xxx_eh_target_reset,
fca29703
AV		 237 .eh_bus_reset_handler = qla2xxx_eh_bus_reset,
238 .eh_host_reset_handler = qla2xxx_eh_host_reset,
239
240 .slave_configure = qla2xxx_slave_configure,
241
242 .slave_alloc = qla2xxx_slave_alloc,
243 .slave_destroy = qla2xxx_slave_destroy,
ed677086
AV		 244 .scan_finished = qla2xxx_scan_finished,
245 .scan_start = qla2xxx_scan_start,
ce7e4af7
AV		 246 .change_queue_depth = qla2x00_change_queue_depth,
247 .change_queue_type = qla2x00_change_queue_type,
fca29703
AV		 248 .this_id = -1,
249 .cmd_per_lun = 3,
250 .use_clustering = ENABLE_CLUSTERING,
251 .sg_tablesize = SG_ALL,
252
253 .max_sectors = 0xFFFF,
afb046e2 254 .shost_attrs = qla2x00_host_attrs,
fca29703
AV		 255};
256
1da177e4 257static struct scsi_transport_template *qla2xxx_transport_template = NULL;
2c3dfe3f 258struct scsi_transport_template *qla2xxx_transport_vport_template = NULL;
1da177e4 259
1da177e4
LT		 260/* TODO Convert to inlines
261 *
262 * Timer routines
263 */
1da177e4 264
2c3dfe3f 265__inline__ void
e315cd28 266qla2x00_start_timer(scsi_qla_host_t *vha, void *func, unsigned long interval)
1da177e4 267{
e315cd28
AC		 268 init_timer(&vha->timer);
269 vha->timer.expires = jiffies + interval * HZ;
270 vha->timer.data = (unsigned long)vha;
271 vha->timer.function = (void (*)(unsigned long))func;
272 add_timer(&vha->timer);
273 vha->timer_active = 1;
1da177e4
LT		 274}
275
276static inline void
e315cd28 277qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval)
1da177e4 278{
a9083016 279 /* Currently used for 82XX only. */
7c3df132
SK		 280 if (vha->device_flags & DFLG_DEV_FAILED) {
281 ql_dbg(ql_dbg_timer, vha, 0x600d,
282 "Device in a failed state, returning.\n");
a9083016 283 return;
7c3df132 284 }
a9083016 285
e315cd28 286 mod_timer(&vha->timer, jiffies + interval * HZ);
1da177e4
LT		 287}
288
a824ebb3 289static __inline__ void
e315cd28 290qla2x00_stop_timer(scsi_qla_host_t *vha)
1da177e4 291{
e315cd28
AC		 292 del_timer_sync(&vha->timer);
293 vha->timer_active = 0;
1da177e4
LT		 294}
295
1da177e4
LT		 296static int qla2x00_do_dpc(void *data);
297
298static void qla2x00_rst_aen(scsi_qla_host_t *);
299
73208dfd
AC		 300static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t,
301 struct req_que **, struct rsp_que **);
e30d1756 302static void qla2x00_free_fw_dump(struct qla_hw_data *);
e315cd28
AC		 303static void qla2x00_mem_free(struct qla_hw_data *);
304static void qla2x00_sp_free_dma(srb_t *);
1da177e4 305
1da177e4 306/* -------------------------------------------------------------------------- */
73208dfd
AC		 307static int qla2x00_alloc_queues(struct qla_hw_data *ha)
308{
7c3df132 309 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2afa19a9 310 ha->req_q_map = kzalloc(sizeof(struct req_que *) * ha->max_req_queues,
73208dfd
AC		 311 GFP_KERNEL);
312 if (!ha->req_q_map) {
7c3df132
SK		 313 ql_log(ql_log_fatal, vha, 0x003b,
314 "Unable to allocate memory for request queue ptrs.\n");
73208dfd
AC		 315 goto fail_req_map;
316 }
317
2afa19a9 318 ha->rsp_q_map = kzalloc(sizeof(struct rsp_que *) * ha->max_rsp_queues,
73208dfd
AC		 319 GFP_KERNEL);
320 if (!ha->rsp_q_map) {
7c3df132
SK		 321 ql_log(ql_log_fatal, vha, 0x003c,
322 "Unable to allocate memory for response queue ptrs.\n");
73208dfd
AC		 323 goto fail_rsp_map;
324 }
325 set_bit(0, ha->rsp_qid_map);
326 set_bit(0, ha->req_qid_map);
327 return 1;
328
329fail_rsp_map:
330 kfree(ha->req_q_map);
331 ha->req_q_map = NULL;
332fail_req_map:
333 return -ENOMEM;
334}
335
2afa19a9 336static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req)
73208dfd 337{
73208dfd
AC		 338 if (req && req->ring)
339 dma_free_coherent(&ha->pdev->dev,
340 (req->length + 1) * sizeof(request_t),
341 req->ring, req->dma);
342
343 kfree(req);
344 req = NULL;
345}
346
2afa19a9
AC		 347static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp)
348{
349 if (rsp && rsp->ring)
350 dma_free_coherent(&ha->pdev->dev,
351 (rsp->length + 1) * sizeof(response_t),
352 rsp->ring, rsp->dma);
353
354 kfree(rsp);
355 rsp = NULL;
356}
357
73208dfd
AC		 358static void qla2x00_free_queues(struct qla_hw_data *ha)
359{
360 struct req_que *req;
361 struct rsp_que *rsp;
362 int cnt;
363
2afa19a9 364 for (cnt = 0; cnt < ha->max_req_queues; cnt++) {
73208dfd 365 req = ha->req_q_map[cnt];
2afa19a9 366 qla2x00_free_req_que(ha, req);
73208dfd 367 }
73208dfd
AC		 368 kfree(ha->req_q_map);
369 ha->req_q_map = NULL;
2afa19a9
AC		 370
371 for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) {
372 rsp = ha->rsp_q_map[cnt];
373 qla2x00_free_rsp_que(ha, rsp);
374 }
375 kfree(ha->rsp_q_map);
376 ha->rsp_q_map = NULL;
73208dfd
AC		 377}
378
68ca949c
AC		 379static int qla25xx_setup_mode(struct scsi_qla_host *vha)
380{
381 uint16_t options = 0;
382 int ques, req, ret;
383 struct qla_hw_data *ha = vha->hw;
384
7163ea81 385 if (!(ha->fw_attributes & BIT_6)) {
7c3df132
SK		 386 ql_log(ql_log_warn, vha, 0x00d8,
387 "Firmware is not multi-queue capable.\n");
7163ea81
AC		 388 goto fail;
389 }
68ca949c 390 if (ql2xmultique_tag) {
68ca949c
AC		 391 /* create a request queue for IO */
392 options |= BIT_7;
393 req = qla25xx_create_req_que(ha, options, 0, 0, -1,
394 QLA_DEFAULT_QUE_QOS);
395 if (!req) {
7c3df132
SK		 396 ql_log(ql_log_warn, vha, 0x00e0,
397 "Failed to create request queue.\n");
68ca949c
AC		 398 goto fail;
399 }
278274d5 400 ha->wq = alloc_workqueue("qla2xxx_wq", WQ_MEM_RECLAIM, 1);
68ca949c
AC		 401 vha->req = ha->req_q_map[req];
402 options |= BIT_1;
403 for (ques = 1; ques < ha->max_rsp_queues; ques++) {
404 ret = qla25xx_create_rsp_que(ha, options, 0, 0, req);
405 if (!ret) {
7c3df132
SK		 406 ql_log(ql_log_warn, vha, 0x00e8,
407 "Failed to create response queue.\n");
68ca949c
AC		 408 goto fail2;
409 }
410 }
7163ea81 411 ha->flags.cpu_affinity_enabled = 1;
7c3df132
SK		 412 ql_dbg(ql_dbg_multiq, vha, 0xc007,
413 "CPU affinity mode enalbed, "
414 "no. of response queues:%d no. of request queues:%d.\n",
415 ha->max_rsp_queues, ha->max_req_queues);
416 ql_dbg(ql_dbg_init, vha, 0x00e9,
417 "CPU affinity mode enalbed, "
418 "no. of response queues:%d no. of request queues:%d.\n",
419 ha->max_rsp_queues, ha->max_req_queues);
68ca949c
AC		 420 }
421 return 0;
422fail2:
423 qla25xx_delete_queues(vha);
7163ea81
AC		 424 destroy_workqueue(ha->wq);
425 ha->wq = NULL;
0cd33fcf 426 vha->req = ha->req_q_map[0];
68ca949c
AC		 427fail:
428 ha->mqenable = 0;
7163ea81
AC		 429 kfree(ha->req_q_map);
430 kfree(ha->rsp_q_map);
431 ha->max_req_queues = ha->max_rsp_queues = 1;
68ca949c
AC		 432 return 1;
433}
434
1da177e4 435static char *
e315cd28 436qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str)
1da177e4 437{
e315cd28 438 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 439 static char *pci_bus_modes[] = {
440 "33", "66", "100", "133",
441 };
442 uint16_t pci_bus;
443
444 strcpy(str, "PCI");
445 pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9;
446 if (pci_bus) {
447 strcat(str, "-X (");
448 strcat(str, pci_bus_modes[pci_bus]);
449 } else {
450 pci_bus = (ha->pci_attr & BIT_8) >> 8;
451 strcat(str, " (");
452 strcat(str, pci_bus_modes[pci_bus]);
453 }
454 strcat(str, " MHz)");
455
456 return (str);
457}
458
fca29703 459static char *
e315cd28 460qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str)
fca29703
AV		 461{
462 static char *pci_bus_modes[] = { "33", "66", "100", "133", };
e315cd28 463 struct qla_hw_data *ha = vha->hw;
fca29703
AV		 464 uint32_t pci_bus;
465 int pcie_reg;
466
467 pcie_reg = pci_find_capability(ha->pdev, PCI_CAP_ID_EXP);
468 if (pcie_reg) {
469 char lwstr[6];
470 uint16_t pcie_lstat, lspeed, lwidth;
471
472 pcie_reg += 0x12;
473 pci_read_config_word(ha->pdev, pcie_reg, &pcie_lstat);
474 lspeed = pcie_lstat & (BIT_0 | BIT_1 | BIT_2 | BIT_3);
475 lwidth = (pcie_lstat &
476 (BIT_4 | BIT_5 | BIT_6 | BIT_7 | BIT_8 | BIT_9)) >> 4;
477
478 strcpy(str, "PCIe (");
479 if (lspeed == 1)
c87a0d8c 480 strcat(str, "2.5GT/s ");
c3a2f0df 481 else if (lspeed == 2)
c87a0d8c 482 strcat(str, "5.0GT/s ");
fca29703
AV		 483 else
484 strcat(str, "<unknown> ");
485 snprintf(lwstr, sizeof(lwstr), "x%d)", lwidth);
486 strcat(str, lwstr);
487
488 return str;
489 }
490
491 strcpy(str, "PCI");
492 pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8;
493 if (pci_bus == 0 || pci_bus == 8) {
494 strcat(str, " (");
495 strcat(str, pci_bus_modes[pci_bus >> 3]);
496 } else {
497 strcat(str, "-X ");
498 if (pci_bus & BIT_2)
499 strcat(str, "Mode 2");
500 else
501 strcat(str, "Mode 1");
502 strcat(str, " (");
503 strcat(str, pci_bus_modes[pci_bus & ~BIT_2]);
504 }
505 strcat(str, " MHz)");
506
507 return str;
508}
509
e5f82ab8 510static char *
e315cd28 511qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str)
1da177e4
LT		 512{
513 char un_str[10];
e315cd28 514 struct qla_hw_data *ha = vha->hw;
fa2a1ce5 515
1da177e4
LT		 516 sprintf(str, "%d.%02d.%02d ", ha->fw_major_version,
517 ha->fw_minor_version,
518 ha->fw_subminor_version);
519
520 if (ha->fw_attributes & BIT_9) {
521 strcat(str, "FLX");
522 return (str);
523 }
524
525 switch (ha->fw_attributes & 0xFF) {
526 case 0x7:
527 strcat(str, "EF");
528 break;
529 case 0x17:
530 strcat(str, "TP");
531 break;
532 case 0x37:
533 strcat(str, "IP");
534 break;
535 case 0x77:
536 strcat(str, "VI");
537 break;
538 default:
539 sprintf(un_str, "(%x)", ha->fw_attributes);
540 strcat(str, un_str);
541 break;
542 }
543 if (ha->fw_attributes & 0x100)
544 strcat(str, "X");
545
546 return (str);
547}
548
e5f82ab8 549static char *
e315cd28 550qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str)
fca29703 551{
e315cd28 552 struct qla_hw_data *ha = vha->hw;
f0883ac6 553
3a03eb79
AV		 554 sprintf(str, "%d.%02d.%02d (%x)", ha->fw_major_version,
555 ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes);
fca29703 556 return str;
fca29703
AV		 557}
558
559static inline srb_t *
e315cd28 560qla2x00_get_new_sp(scsi_qla_host_t *vha, fc_port_t *fcport,
f5e3e40b 561 struct scsi_cmnd *cmd)
fca29703
AV		 562{
563 srb_t *sp;
e315cd28 564 struct qla_hw_data *ha = vha->hw;
fca29703
AV		 565
566 sp = mempool_alloc(ha->srb_mempool, GFP_ATOMIC);
7c3df132
SK		 567 if (!sp) {
568 ql_log(ql_log_warn, vha, 0x3006,
569 "Memory allocation failed for sp.\n");
fca29703 570 return sp;
7c3df132 571 }
fca29703 572
083a469d 573 atomic_set(&sp->ref_count, 1);
fca29703
AV		 574 sp->fcport = fcport;
575 sp->cmd = cmd;
576 sp->flags = 0;
577 CMD_SP(cmd) = (void *)sp;
cf53b069 578 sp->ctx = NULL;
fca29703
AV		 579
580 return sp;
581}
582
1da177e4 583static int
f5e3e40b 584qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
fca29703 585{
134ae078 586 scsi_qla_host_t *vha = shost_priv(host);
fca29703 587 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
19a7b4ae 588 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
e315cd28
AC		 589 struct qla_hw_data *ha = vha->hw;
590 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
fca29703
AV		 591 srb_t *sp;
592 int rval;
593
85880801 594 if (ha->flags.eeh_busy) {
7c3df132
SK		 595 if (ha->flags.pci_channel_io_perm_failure) {
596 ql_dbg(ql_dbg_io, vha, 0x3001,
597 "PCI Channel IO permanent failure, exiting "
598 "cmd=%p.\n", cmd);
b9b12f73 599 cmd->result = DID_NO_CONNECT << 16;
7c3df132
SK		 600 } else {
601 ql_dbg(ql_dbg_io, vha, 0x3002,
602 "EEH_Busy, Requeuing the cmd=%p.\n", cmd);
85880801 603 cmd->result = DID_REQUEUE << 16;
7c3df132 604 }
14e660e6
SJ		 605 goto qc24_fail_command;
606 }
607
19a7b4ae
JSEC		 608 rval = fc_remote_port_chkready(rport);
609 if (rval) {
610 cmd->result = rval;
7c3df132
SK		 611 ql_dbg(ql_dbg_io, vha, 0x3003,
612 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
613 cmd, rval);
fca29703
AV		 614 goto qc24_fail_command;
615 }
616
bad75002
AE		 617 if (!vha->flags.difdix_supported &&
618 scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) {
7c3df132
SK		 619 ql_dbg(ql_dbg_io, vha, 0x3004,
620 "DIF Cap not reg, fail DIF capable cmd's:%p.\n",
621 cmd);
bad75002
AE		 622 cmd->result = DID_NO_CONNECT << 16;
623 goto qc24_fail_command;
624 }
fca29703
AV		 625 if (atomic_read(&fcport->state) != FCS_ONLINE) {
626 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
38170fa8 627 atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
7c3df132
SK		 628 ql_dbg(ql_dbg_io, vha, 0x3005,
629 "Returning DNC, fcport_state=%d loop_state=%d.\n",
630 atomic_read(&fcport->state),
631 atomic_read(&base_vha->loop_state));
fca29703
AV		 632 cmd->result = DID_NO_CONNECT << 16;
633 goto qc24_fail_command;
634 }
7b594131 635 goto qc24_target_busy;
fca29703
AV		 636 }
637
f5e3e40b 638 sp = qla2x00_get_new_sp(base_vha, fcport, cmd);
fca29703 639 if (!sp)
f5e3e40b 640 goto qc24_host_busy;
fca29703 641
e315cd28 642 rval = ha->isp_ops->start_scsi(sp);
7c3df132
SK		 643 if (rval != QLA_SUCCESS) {
644 ql_dbg(ql_dbg_io, vha, 0x3013,
645 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
fca29703 646 goto qc24_host_busy_free_sp;
7c3df132 647 }
fca29703 648
fca29703
AV		 649 return 0;
650
651qc24_host_busy_free_sp:
e315cd28
AC		 652 qla2x00_sp_free_dma(sp);
653 mempool_free(sp, ha->srb_mempool);
fca29703 654
f5e3e40b 655qc24_host_busy:
fca29703
AV		 656 return SCSI_MLQUEUE_HOST_BUSY;
657
7b594131
MC		 658qc24_target_busy:
659 return SCSI_MLQUEUE_TARGET_BUSY;
660
fca29703 661qc24_fail_command:
f5e3e40b 662 cmd->scsi_done(cmd);
fca29703
AV		 663
664 return 0;
665}
666
1da177e4
LT		 667/*
668 * qla2x00_eh_wait_on_command
669 * Waits for the command to be returned by the Firmware for some
670 * max time.
671 *
672 * Input:
1da177e4 673 * cmd = Scsi Command to wait on.
1da177e4
LT		 674 *
675 * Return:
676 * Not Found : 0
677 * Found : 1
678 */
679static int
e315cd28 680qla2x00_eh_wait_on_command(struct scsi_cmnd *cmd)
1da177e4 681{
fe74c71f
AV		 682#define ABORT_POLLING_PERIOD 1000
683#define ABORT_WAIT_ITER ((10 * 1000) / (ABORT_POLLING_PERIOD))
f4f051eb 684 unsigned long wait_iter = ABORT_WAIT_ITER;
85880801
AV		 685 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
686 struct qla_hw_data *ha = vha->hw;
f4f051eb 687 int ret = QLA_SUCCESS;
1da177e4 688
85880801 689 if (unlikely(pci_channel_offline(ha->pdev)) || ha->flags.eeh_busy) {
7c3df132
SK		 690 ql_dbg(ql_dbg_taskm, vha, 0x8005,
691 "Return:eh_wait.\n");
85880801
AV		 692 return ret;
693 }
694
d970432c 695 while (CMD_SP(cmd) && wait_iter--) {
fe74c71f 696 msleep(ABORT_POLLING_PERIOD);
f4f051eb 697 }
698 if (CMD_SP(cmd))
699 ret = QLA_FUNCTION_FAILED;
1da177e4 700
f4f051eb 701 return ret;
1da177e4
LT		 702}
703
704/*
705 * qla2x00_wait_for_hba_online
fa2a1ce5 706 * Wait till the HBA is online after going through
1da177e4
LT		 707 * <= MAX_RETRIES_OF_ISP_ABORT or
708 * finally HBA is disabled ie marked offline
709 *
710 * Input:
711 * ha - pointer to host adapter structure
fa2a1ce5
AV		 712 *
713 * Note:
1da177e4
LT		 714 * Does context switching-Release SPIN_LOCK
715 * (if any) before calling this routine.
716 *
717 * Return:
718 * Success (Adapter is online) : 0
719 * Failed (Adapter is offline/disabled) : 1
720 */
854165f4 721int
e315cd28 722qla2x00_wait_for_hba_online(scsi_qla_host_t *vha)
1da177e4 723{
fca29703
AV		 724 int return_status;
725 unsigned long wait_online;
e315cd28
AC		 726 struct qla_hw_data *ha = vha->hw;
727 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4 728
fa2a1ce5 729 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ);
e315cd28
AC		 730 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
731 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
732 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
733 ha->dpc_active) && time_before(jiffies, wait_online)) {
1da177e4
LT		 734
735 msleep(1000);
736 }
e315cd28 737 if (base_vha->flags.online)
fa2a1ce5 738 return_status = QLA_SUCCESS;
1da177e4
LT		 739 else
740 return_status = QLA_FUNCTION_FAILED;
741
1da177e4
LT		 742 return (return_status);
743}
744
86fbee86
LC		 745/*
746 * qla2x00_wait_for_reset_ready
747 * Wait till the HBA is online after going through
748 * <= MAX_RETRIES_OF_ISP_ABORT or
749 * finally HBA is disabled ie marked offline or flash
750 * operations are in progress.
751 *
752 * Input:
753 * ha - pointer to host adapter structure
754 *
755 * Note:
756 * Does context switching-Release SPIN_LOCK
757 * (if any) before calling this routine.
758 *
759 * Return:
760 * Success (Adapter is online/no flash ops) : 0
761 * Failed (Adapter is offline/disabled/flash ops in progress) : 1
762 */
3dbe756a 763static int
86fbee86
LC		 764qla2x00_wait_for_reset_ready(scsi_qla_host_t *vha)
765{
766 int return_status;
767 unsigned long wait_online;
768 struct qla_hw_data *ha = vha->hw;
769 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
770
771 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ);
772 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
773 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
774 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
775 ha->optrom_state != QLA_SWAITING ||
776 ha->dpc_active) && time_before(jiffies, wait_online))
777 msleep(1000);
778
779 if (base_vha->flags.online && ha->optrom_state == QLA_SWAITING)
780 return_status = QLA_SUCCESS;
781 else
782 return_status = QLA_FUNCTION_FAILED;
783
7c3df132
SK		 784 ql_dbg(ql_dbg_taskm, vha, 0x8019,
785 "%s return status=%d.\n", __func__, return_status);
86fbee86
LC		 786
787 return return_status;
788}
789
2533cf67
LC		 790int
791qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha)
792{
793 int return_status;
794 unsigned long wait_reset;
795 struct qla_hw_data *ha = vha->hw;
796 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
797
798 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ);
799 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
800 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
801 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
802 ha->dpc_active) && time_before(jiffies, wait_reset)) {
803
804 msleep(1000);
805
806 if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) &&
807 ha->flags.chip_reset_done)
808 break;
809 }
810 if (ha->flags.chip_reset_done)
811 return_status = QLA_SUCCESS;
812 else
813 return_status = QLA_FUNCTION_FAILED;
814
815 return return_status;
816}
817
083a469d
GM		 818static void
819sp_get(struct srb *sp)
820{
821 atomic_inc(&sp->ref_count);
822}
823
1da177e4
LT		 824/**************************************************************************
825* qla2xxx_eh_abort
826*
827* Description:
828* The abort function will abort the specified command.
829*
830* Input:
831* cmd = Linux SCSI command packet to be aborted.
832*
833* Returns:
834* Either SUCCESS or FAILED.
835*
836* Note:
2ea00202 837* Only return FAILED if command not returned by firmware.
1da177e4 838**************************************************************************/
e5f82ab8 839static int
1da177e4
LT		 840qla2xxx_eh_abort(struct scsi_cmnd *cmd)
841{
e315cd28 842 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
f4f051eb 843 srb_t *sp;
4e98d3b8 844 int ret;
f4f051eb 845 unsigned int id, lun;
18e144d3 846 unsigned long flags;
2ea00202 847 int wait = 0;
e315cd28 848 struct qla_hw_data *ha = vha->hw;
1da177e4 849
7c3df132
SK		 850 ql_dbg(ql_dbg_taskm, vha, 0x8000,
851 "Entered %s for cmd=%p.\n", __func__, cmd);
f4f051eb 852 if (!CMD_SP(cmd))
2ea00202 853 return SUCCESS;
1da177e4 854
4e98d3b8 855 ret = fc_block_scsi_eh(cmd);
7c3df132
SK		 856 ql_dbg(ql_dbg_taskm, vha, 0x8001,
857 "Return value of fc_block_scsi_eh=%d.\n", ret);
4e98d3b8
AV		 858 if (ret != 0)
859 return ret;
860 ret = SUCCESS;
861
f4f051eb 862 id = cmd->device->id;
863 lun = cmd->device->lun;
1da177e4 864
e315cd28 865 spin_lock_irqsave(&ha->hardware_lock, flags);
170babc3
MC		 866 sp = (srb_t *) CMD_SP(cmd);
867 if (!sp) {
868 spin_unlock_irqrestore(&ha->hardware_lock, flags);
869 return SUCCESS;
870 }
1da177e4 871
7c3df132
SK		 872 ql_dbg(ql_dbg_taskm, vha, 0x8002,
873 "Aborting sp=%p cmd=%p from RISC ", sp, cmd);
17d98630 874
170babc3
MC		 875 /* Get a reference to the sp and drop the lock.*/
876 sp_get(sp);
083a469d 877
e315cd28 878 spin_unlock_irqrestore(&ha->hardware_lock, flags);
170babc3 879 if (ha->isp_ops->abort_command(sp)) {
7c3df132
SK		 880 ql_dbg(ql_dbg_taskm, vha, 0x8003,
881 "Abort command mbx failed for cmd=%p.\n", cmd);
170babc3 882 } else {
7c3df132
SK		 883 ql_dbg(ql_dbg_taskm, vha, 0x8004,
884 "Abort command mbx success.\n");
170babc3
MC		 885 wait = 1;
886 }
75942064
SK		 887
888 spin_lock_irqsave(&ha->hardware_lock, flags);
170babc3 889 qla2x00_sp_compl(ha, sp);
75942064 890 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1da177e4 891
bc91ade9
CD		 892 /* Did the command return during mailbox execution? */
893 if (ret == FAILED && !CMD_SP(cmd))
894 ret = SUCCESS;
895
f4f051eb 896 /* Wait for the command to be returned. */
2ea00202 897 if (wait) {
e315cd28 898 if (qla2x00_eh_wait_on_command(cmd) != QLA_SUCCESS) {
7c3df132
SK		 899 ql_log(ql_log_warn, vha, 0x8006,
900 "Abort handler timed out for cmd=%p.\n", cmd);
2ea00202 901 ret = FAILED;
f4f051eb 902 }
1da177e4 903 }
1da177e4 904
7c3df132
SK		 905 ql_log(ql_log_info, vha, 0x801c,
906 "Abort command issued -- %d %x.\n", wait, ret);
1da177e4 907
f4f051eb 908 return ret;
909}
1da177e4 910
4d78c973 911int
e315cd28 912qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t,
4d78c973 913 unsigned int l, enum nexus_wait_type type)
f4f051eb 914{
17d98630 915 int cnt, match, status;
18e144d3 916 unsigned long flags;
e315cd28 917 struct qla_hw_data *ha = vha->hw;
73208dfd 918 struct req_que *req;
4d78c973 919 srb_t *sp;
1da177e4 920
523ec773 921 status = QLA_SUCCESS;
17d98630 922
e315cd28 923 spin_lock_irqsave(&ha->hardware_lock, flags);
67c2e93a 924 req = vha->req;
17d98630
AC		 925 for (cnt = 1; status == QLA_SUCCESS &&
926 cnt < MAX_OUTSTANDING_COMMANDS; cnt++) {
927 sp = req->outstanding_cmds[cnt];
928 if (!sp)
523ec773 929 continue;
bad75002 930 if ((sp->ctx) && !IS_PROT_IO(sp))
cf53b069 931 continue;
17d98630
AC		 932 if (vha->vp_idx != sp->fcport->vha->vp_idx)
933 continue;
934 match = 0;
935 switch (type) {
936 case WAIT_HOST:
937 match = 1;
938 break;
939 case WAIT_TARGET:
940 match = sp->cmd->device->id == t;
941 break;
942 case WAIT_LUN:
943 match = (sp->cmd->device->id == t &&
944 sp->cmd->device->lun == l);
945 break;
73208dfd 946 }
17d98630
AC		 947 if (!match)
948 continue;
949
950 spin_unlock_irqrestore(&ha->hardware_lock, flags);
951 status = qla2x00_eh_wait_on_command(sp->cmd);
952 spin_lock_irqsave(&ha->hardware_lock, flags);
1da177e4 953 }
e315cd28 954 spin_unlock_irqrestore(&ha->hardware_lock, flags);
523ec773
AV		 955
956 return status;
1da177e4
LT		 957}
958
523ec773
AV		 959static char *reset_errors[] = {
960 "HBA not online",
961 "HBA not ready",
962 "Task management failed",
963 "Waiting for command completions",
964};
1da177e4 965
e5f82ab8 966static int
523ec773 967__qla2xxx_eh_generic_reset(char *name, enum nexus_wait_type type,
2afa19a9 968 struct scsi_cmnd *cmd, int (*do_reset)(struct fc_port *, unsigned int, int))
1da177e4 969{
e315cd28 970 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
bdf79621 971 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
523ec773 972 int err;
1da177e4 973
7c3df132
SK		 974 if (!fcport) {
975 ql_log(ql_log_warn, vha, 0x8007,
976 "fcport is NULL.\n");
523ec773 977 return FAILED;
7c3df132 978 }
1da177e4 979
4e98d3b8 980 err = fc_block_scsi_eh(cmd);
7c3df132
SK		 981 ql_dbg(ql_dbg_taskm, vha, 0x8008,
982 "fc_block_scsi_eh ret=%d.\n", err);
4e98d3b8
AV		 983 if (err != 0)
984 return err;
985
7c3df132
SK		 986 ql_log(ql_log_info, vha, 0x8009,
987 "%s RESET ISSUED for id %d lun %d cmd=%p.\n", name,
988 cmd->device->id, cmd->device->lun, cmd);
1da177e4 989
523ec773 990 err = 0;
7c3df132
SK		 991 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
992 ql_log(ql_log_warn, vha, 0x800a,
993 "Wait for hba online failed for cmd=%p.\n", cmd);
523ec773 994 goto eh_reset_failed;
7c3df132 995 }
523ec773 996 err = 2;
2afa19a9 997 if (do_reset(fcport, cmd->device->lun, cmd->request->cpu + 1)
7c3df132
SK		 998 != QLA_SUCCESS) {
999 ql_log(ql_log_warn, vha, 0x800c,
1000 "do_reset failed for cmd=%p.\n", cmd);
523ec773 1001 goto eh_reset_failed;
7c3df132 1002 }
523ec773 1003 err = 3;
e315cd28 1004 if (qla2x00_eh_wait_for_pending_commands(vha, cmd->device->id,
7c3df132
SK		 1005 cmd->device->lun, type) != QLA_SUCCESS) {
1006 ql_log(ql_log_warn, vha, 0x800d,
1007 "wait for peding cmds failed for cmd=%p.\n", cmd);
523ec773 1008 goto eh_reset_failed;
7c3df132 1009 }
523ec773 1010
7c3df132
SK		 1011 ql_log(ql_log_info, vha, 0x800e,
1012 "%s RESET SUCCEEDED for id %d lun %d cmd=%p.\n", name,
1013 cmd->device->id, cmd->device->lun, cmd);
523ec773
AV		 1014
1015 return SUCCESS;
1016
4d78c973 1017eh_reset_failed:
7c3df132
SK		 1018 ql_log(ql_log_info, vha, 0x800f,
1019 "%s RESET FAILED: %s for id %d lun %d cmd=%p.\n", name,
d8424f68 1020 reset_errors[err], cmd->device->id, cmd->device->lun, cmd);
523ec773
AV		 1021 return FAILED;
1022}
1da177e4 1023
523ec773
AV		 1024static int
1025qla2xxx_eh_device_reset(struct scsi_cmnd *cmd)
1026{
e315cd28
AC		 1027 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1028 struct qla_hw_data *ha = vha->hw;
1da177e4 1029
523ec773
AV		 1030 return __qla2xxx_eh_generic_reset("DEVICE", WAIT_LUN, cmd,
1031 ha->isp_ops->lun_reset);
1da177e4
LT		 1032}
1033
1da177e4 1034static int
523ec773 1035qla2xxx_eh_target_reset(struct scsi_cmnd *cmd)
1da177e4 1036{
e315cd28
AC		 1037 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1038 struct qla_hw_data *ha = vha->hw;
1da177e4 1039
523ec773
AV		 1040 return __qla2xxx_eh_generic_reset("TARGET", WAIT_TARGET, cmd,
1041 ha->isp_ops->target_reset);
1da177e4
LT		 1042}
1043
1da177e4
LT		 1044/**************************************************************************
1045* qla2xxx_eh_bus_reset
1046*
1047* Description:
1048* The bus reset function will reset the bus and abort any executing
1049* commands.
1050*
1051* Input:
1052* cmd = Linux SCSI command packet of the command that cause the
1053* bus reset.
1054*
1055* Returns:
1056* SUCCESS/FAILURE (defined as macro in scsi.h).
1057*
1058**************************************************************************/
e5f82ab8 1059static int
1da177e4
LT		 1060qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd)
1061{
e315cd28 1062 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
bdf79621 1063 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
2c3dfe3f 1064 int ret = FAILED;
f4f051eb 1065 unsigned int id, lun;
f4f051eb 1066
f4f051eb 1067 id = cmd->device->id;
1068 lun = cmd->device->lun;
1da177e4 1069
7c3df132
SK		 1070 if (!fcport) {
1071 ql_log(ql_log_warn, vha, 0x8010,
1072 "fcport is NULL.\n");
f4f051eb 1073 return ret;
7c3df132 1074 }
1da177e4 1075
4e98d3b8 1076 ret = fc_block_scsi_eh(cmd);
7c3df132
SK		 1077 ql_dbg(ql_dbg_taskm, vha, 0x8011,
1078 "fc_block_scsi_eh ret=%d.\n", ret);
4e98d3b8
AV		 1079 if (ret != 0)
1080 return ret;
1081 ret = FAILED;
1082
7c3df132
SK		 1083 ql_log(ql_log_info, vha, 0x8012,
1084 "BUS RESET ISSUED for id %d lun %d.\n", id, lun);
1da177e4 1085
e315cd28 1086 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
7c3df132
SK		 1087 ql_log(ql_log_fatal, vha, 0x8013,
1088 "Wait for hba online failed board disabled.\n");
f4f051eb 1089 goto eh_bus_reset_done;
1da177e4
LT		 1090 }
1091
ad537689
SK		 1092 if (qla2x00_loop_reset(vha) == QLA_SUCCESS)
1093 ret = SUCCESS;
1094
f4f051eb 1095 if (ret == FAILED)
1096 goto eh_bus_reset_done;
1da177e4 1097
9a41a62b 1098 /* Flush outstanding commands. */
4d78c973 1099 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) !=
7c3df132
SK		 1100 QLA_SUCCESS) {
1101 ql_log(ql_log_warn, vha, 0x8014,
1102 "Wait for pending commands failed.\n");
9a41a62b 1103 ret = FAILED;
7c3df132 1104 }
1da177e4 1105
f4f051eb 1106eh_bus_reset_done:
7c3df132
SK		 1107 ql_log(ql_log_warn, vha, 0x802b,
1108 "BUS RESET %s.\n", (ret == FAILED) ? "FAILED" : "SUCCEDED");
1da177e4 1109
f4f051eb 1110 return ret;
1da177e4
LT		 1111}
1112
1113/**************************************************************************
1114* qla2xxx_eh_host_reset
1115*
1116* Description:
1117* The reset function will reset the Adapter.
1118*
1119* Input:
1120* cmd = Linux SCSI command packet of the command that cause the
1121* adapter reset.
1122*
1123* Returns:
1124* Either SUCCESS or FAILED.
1125*
1126* Note:
1127**************************************************************************/
e5f82ab8 1128static int
1da177e4
LT		 1129qla2xxx_eh_host_reset(struct scsi_cmnd *cmd)
1130{
e315cd28 1131 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
bdf79621 1132 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
e315cd28 1133 struct qla_hw_data *ha = vha->hw;
2c3dfe3f 1134 int ret = FAILED;
f4f051eb 1135 unsigned int id, lun;
e315cd28 1136 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4 1137
f4f051eb 1138 id = cmd->device->id;
1139 lun = cmd->device->lun;
f4f051eb 1140
7c3df132
SK		 1141 if (!fcport) {
1142 ql_log(ql_log_warn, vha, 0x8016,
1143 "fcport is NULL.\n");
f4f051eb 1144 return ret;
7c3df132 1145 }
1da177e4 1146
4e98d3b8 1147 ret = fc_block_scsi_eh(cmd);
7c3df132
SK		 1148 ql_dbg(ql_dbg_taskm, vha, 0x8017,
1149 "fc_block_scsi_eh ret=%d.\n", ret);
4e98d3b8
AV		 1150 if (ret != 0)
1151 return ret;
1152 ret = FAILED;
1153
7c3df132
SK		 1154 ql_log(ql_log_info, vha, 0x8018,
1155 "ADAPTER RESET ISSUED for id %d lun %d.\n", id, lun);
1da177e4 1156
86fbee86 1157 if (qla2x00_wait_for_reset_ready(vha) != QLA_SUCCESS)
f4f051eb 1158 goto eh_host_reset_lock;
1da177e4 1159
e315cd28
AC		 1160 if (vha != base_vha) {
1161 if (qla2x00_vp_abort_isp(vha))
f4f051eb 1162 goto eh_host_reset_lock;
e315cd28 1163 } else {
a9083016
GM		 1164 if (IS_QLA82XX(vha->hw)) {
1165 if (!qla82xx_fcoe_ctx_reset(vha)) {
1166 /* Ctx reset success */
1167 ret = SUCCESS;
1168 goto eh_host_reset_lock;
1169 }
1170 /* fall thru if ctx reset failed */
1171 }
68ca949c
AC		 1172 if (ha->wq)
1173 flush_workqueue(ha->wq);
1174
e315cd28 1175 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
a9083016 1176 if (ha->isp_ops->abort_isp(base_vha)) {
e315cd28
AC		 1177 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1178 /* failed. schedule dpc to try */
1179 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
1180
7c3df132
SK		 1181 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1182 ql_log(ql_log_warn, vha, 0x802a,
1183 "wait for hba online failed.\n");
e315cd28 1184 goto eh_host_reset_lock;
7c3df132 1185 }
e315cd28
AC		 1186 }
1187 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
fa2a1ce5 1188 }
1da177e4 1189
e315cd28 1190 /* Waiting for command to be returned to OS.*/
4d78c973 1191 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) ==
e315cd28 1192 QLA_SUCCESS)
f4f051eb 1193 ret = SUCCESS;
1da177e4 1194
f4f051eb 1195eh_host_reset_lock:
7c3df132 1196 qla_printk(KERN_INFO, ha, "%s: reset %s.\n", __func__,
25985edc 1197 (ret == FAILED) ? "failed" : "succeeded");
1da177e4 1198
f4f051eb 1199 return ret;
1200}
1da177e4
LT		 1201
1202/*
1203* qla2x00_loop_reset
1204* Issue loop reset.
1205*
1206* Input:
1207* ha = adapter block pointer.
1208*
1209* Returns:
1210* 0 = success
1211*/
a4722cf2 1212int
e315cd28 1213qla2x00_loop_reset(scsi_qla_host_t *vha)
1da177e4 1214{
0c8c39af 1215 int ret;
bdf79621 1216 struct fc_port *fcport;
e315cd28 1217 struct qla_hw_data *ha = vha->hw;
1da177e4 1218
f4c496c1 1219 if (ql2xtargetreset == 1 && ha->flags.enable_target_reset) {
55e5ed27
AV		 1220 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1221 if (fcport->port_type != FCT_TARGET)
1222 continue;
1223
1224 ret = ha->isp_ops->target_reset(fcport, 0, 0);
1225 if (ret != QLA_SUCCESS) {
7c3df132
SK		 1226 ql_dbg(ql_dbg_taskm, vha, 0x802c,
1227 "Bus Reset failed: Target Reset=%d "
1228 "d_id=%x.\n", ret, fcport->d_id.b24);
55e5ed27
AV		 1229 }
1230 }
1231 }
1232
a9083016 1233 if (ha->flags.enable_lip_full_login && !IS_QLA8XXX_TYPE(ha)) {
e315cd28 1234 ret = qla2x00_full_login_lip(vha);
0c8c39af 1235 if (ret != QLA_SUCCESS) {
7c3df132
SK		 1236 ql_dbg(ql_dbg_taskm, vha, 0x802d,
1237 "full_login_lip=%d.\n", ret);
749af3d5
AC		 1238 }
1239 atomic_set(&vha->loop_state, LOOP_DOWN);
1240 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
1241 qla2x00_mark_all_devices_lost(vha, 0);
0c8c39af
AV		 1242 }
1243
0d6e61bc 1244 if (ha->flags.enable_lip_reset) {
e315cd28 1245 ret = qla2x00_lip_reset(vha);
ad537689 1246 if (ret != QLA_SUCCESS)
7c3df132
SK		 1247 ql_dbg(ql_dbg_taskm, vha, 0x802e,
1248 "lip_reset failed (%d).\n", ret);
1da177e4
LT		 1249 }
1250
1da177e4 1251 /* Issue marker command only when we are going to start the I/O */
e315cd28 1252 vha->marker_needed = 1;
1da177e4 1253
0c8c39af 1254 return QLA_SUCCESS;
1da177e4
LT		 1255}
1256
df4bf0bb 1257void
e315cd28 1258qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res)
df4bf0bb 1259{
73208dfd 1260 int que, cnt;
df4bf0bb
AV		 1261 unsigned long flags;
1262 srb_t *sp;
ac280b67 1263 struct srb_ctx *ctx;
e315cd28 1264 struct qla_hw_data *ha = vha->hw;
73208dfd 1265 struct req_que *req;
df4bf0bb
AV		 1266
1267 spin_lock_irqsave(&ha->hardware_lock, flags);
2afa19a9 1268 for (que = 0; que < ha->max_req_queues; que++) {
29bdccbe 1269 req = ha->req_q_map[que];
73208dfd
AC		 1270 if (!req)
1271 continue;
1272 for (cnt = 1; cnt < MAX_OUTSTANDING_COMMANDS; cnt++) {
1273 sp = req->outstanding_cmds[cnt];
e612d465 1274 if (sp) {
73208dfd 1275 req->outstanding_cmds[cnt] = NULL;
a9083016 1276 if (!sp->ctx ||
bad75002
AE		 1277 (sp->flags & SRB_FCP_CMND_DMA_VALID) ||
1278 IS_PROT_IO(sp)) {
ac280b67
AV		 1279 sp->cmd->result = res;
1280 qla2x00_sp_compl(ha, sp);
1281 } else {
1282 ctx = sp->ctx;
9bfacd01
RD		 1283 if (ctx->type == SRB_ELS_CMD_RPT ||
1284 ctx->type == SRB_ELS_CMD_HST ||
1285 ctx->type == SRB_CT_CMD) {
6c452a45 1286 struct fc_bsg_job *bsg_job =
4916392b 1287 ctx->u.bsg_job;
6c452a45
AV		 1288 if (bsg_job->request->msgcode
1289 == FC_BSG_HST_CT)
db3ad7f8 1290 kfree(sp->fcport);
6c452a45
AV		 1291 bsg_job->req->errors = 0;
1292 bsg_job->reply->result = res;
4916392b 1293 bsg_job->job_done(bsg_job);
db3ad7f8 1294 kfree(sp->ctx);
6c452a45 1295 mempool_free(sp,
4916392b 1296 ha->srb_mempool);
9bfacd01
RD		 1297 } else {
1298 ctx->u.iocb_cmd->free(sp);
db3ad7f8 1299 }
ac280b67 1300 }
73208dfd 1301 }
df4bf0bb
AV		 1302 }
1303 }
1304 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1305}
1306
f4f051eb 1307static int
1308qla2xxx_slave_alloc(struct scsi_device *sdev)
1da177e4 1309{
bdf79621 1310 struct fc_rport *rport = starget_to_rport(scsi_target(sdev));
1da177e4 1311
19a7b4ae 1312 if (!rport || fc_remote_port_chkready(rport))
f4f051eb 1313 return -ENXIO;
bdf79621 1314
19a7b4ae 1315 sdev->hostdata = *(fc_port_t **)rport->dd_data;
1da177e4 1316
f4f051eb 1317 return 0;
1318}
1da177e4 1319
f4f051eb 1320static int
1321qla2xxx_slave_configure(struct scsi_device *sdev)
1322{
e315cd28 1323 scsi_qla_host_t *vha = shost_priv(sdev->host);
2afa19a9 1324 struct req_que *req = vha->req;
8482e118 1325
f4f051eb 1326 if (sdev->tagged_supported)
73208dfd 1327 scsi_activate_tcq(sdev, req->max_q_depth);
f4f051eb 1328 else
73208dfd 1329 scsi_deactivate_tcq(sdev, req->max_q_depth);
f4f051eb 1330 return 0;
1331}
1da177e4 1332
f4f051eb 1333static void
1334qla2xxx_slave_destroy(struct scsi_device *sdev)
1335{
1336 sdev->hostdata = NULL;
1da177e4
LT		 1337}
1338
c45dd305
GM		 1339static void qla2x00_handle_queue_full(struct scsi_device *sdev, int qdepth)
1340{
1341 fc_port_t *fcport = (struct fc_port *) sdev->hostdata;
1342
1343 if (!scsi_track_queue_full(sdev, qdepth))
1344 return;
1345
7c3df132
SK		 1346 ql_dbg(ql_dbg_io, fcport->vha, 0x3029,
1347 "Queue depth adjusted-down "
1348 "to %d for scsi(%ld:%d:%d:%d).\n",
1349 sdev->queue_depth, fcport->vha->host_no,
1350 sdev->channel, sdev->id, sdev->lun);
c45dd305
GM		 1351}
1352
1353static void qla2x00_adjust_sdev_qdepth_up(struct scsi_device *sdev, int qdepth)
1354{
1355 fc_port_t *fcport = sdev->hostdata;
1356 struct scsi_qla_host *vha = fcport->vha;
c45dd305
GM		 1357 struct req_que *req = NULL;
1358
1359 req = vha->req;
1360 if (!req)
1361 return;
1362
1363 if (req->max_q_depth <= sdev->queue_depth || req->max_q_depth < qdepth)
1364 return;
1365
1366 if (sdev->ordered_tags)
1367 scsi_adjust_queue_depth(sdev, MSG_ORDERED_TAG, qdepth);
1368 else
1369 scsi_adjust_queue_depth(sdev, MSG_SIMPLE_TAG, qdepth);
1370
7c3df132
SK		 1371 ql_dbg(ql_dbg_io, vha, 0x302a,
1372 "Queue depth adjusted-up to %d for "
1373 "scsi(%ld:%d:%d:%d).\n",
1374 sdev->queue_depth, fcport->vha->host_no,
1375 sdev->channel, sdev->id, sdev->lun);
c45dd305
GM		 1376}
1377
ce7e4af7 1378static int
e881a172 1379qla2x00_change_queue_depth(struct scsi_device *sdev, int qdepth, int reason)
ce7e4af7 1380{
c45dd305
GM		 1381 switch (reason) {
1382 case SCSI_QDEPTH_DEFAULT:
1383 scsi_adjust_queue_depth(sdev, scsi_get_tag_type(sdev), qdepth);
1384 break;
1385 case SCSI_QDEPTH_QFULL:
1386 qla2x00_handle_queue_full(sdev, qdepth);
1387 break;
1388 case SCSI_QDEPTH_RAMP_UP:
1389 qla2x00_adjust_sdev_qdepth_up(sdev, qdepth);
1390 break;
1391 default:
08002af2 1392 return -EOPNOTSUPP;
c45dd305 1393 }
e881a172 1394
ce7e4af7
AV		 1395 return sdev->queue_depth;
1396}
1397
1398static int
1399qla2x00_change_queue_type(struct scsi_device *sdev, int tag_type)
1400{
1401 if (sdev->tagged_supported) {
1402 scsi_set_tag_type(sdev, tag_type);
1403 if (tag_type)
1404 scsi_activate_tcq(sdev, sdev->queue_depth);
1405 else
1406 scsi_deactivate_tcq(sdev, sdev->queue_depth);
1407 } else
1408 tag_type = 0;
1409
1410 return tag_type;
1411}
1412
1da177e4
LT		 1413/**
1414 * qla2x00_config_dma_addressing() - Configure OS DMA addressing method.
1415 * @ha: HA context
1416 *
1417 * At exit, the @ha's flags.enable_64bit_addressing set to indicated
1418 * supported addressing method.
1419 */
1420static void
53303c42 1421qla2x00_config_dma_addressing(struct qla_hw_data *ha)
1da177e4 1422{
7524f9b9 1423 /* Assume a 32bit DMA mask. */
1da177e4 1424 ha->flags.enable_64bit_addressing = 0;
1da177e4 1425
6a35528a 1426 if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) {
7524f9b9
AV		 1427 /* Any upper-dword bits set? */
1428 if (MSD(dma_get_required_mask(&ha->pdev->dev)) &&
6a35528a 1429 !pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(64))) {
7524f9b9 1430 /* Ok, a 64bit DMA mask is applicable. */
1da177e4 1431 ha->flags.enable_64bit_addressing = 1;
fd34f556
AV		 1432 ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64;
1433 ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64;
7524f9b9 1434 return;
1da177e4 1435 }
1da177e4 1436 }
7524f9b9 1437
284901a9
YH		 1438 dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32));
1439 pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(32));
1da177e4
LT		 1440}
1441
fd34f556 1442static void
e315cd28 1443qla2x00_enable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1444{
1445 unsigned long flags = 0;
1446 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1447
1448 spin_lock_irqsave(&ha->hardware_lock, flags);
1449 ha->interrupts_on = 1;
1450 /* enable risc and host interrupts */
1451 WRT_REG_WORD(&reg->ictrl, ICR_EN_INT | ICR_EN_RISC);
1452 RD_REG_WORD(&reg->ictrl);
1453 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1454
1455}
1456
1457static void
e315cd28 1458qla2x00_disable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1459{
1460 unsigned long flags = 0;
1461 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1462
1463 spin_lock_irqsave(&ha->hardware_lock, flags);
1464 ha->interrupts_on = 0;
1465 /* disable risc and host interrupts */
1466 WRT_REG_WORD(&reg->ictrl, 0);
1467 RD_REG_WORD(&reg->ictrl);
1468 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1469}
1470
1471static void
e315cd28 1472qla24xx_enable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1473{
1474 unsigned long flags = 0;
1475 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1476
1477 spin_lock_irqsave(&ha->hardware_lock, flags);
1478 ha->interrupts_on = 1;
1479 WRT_REG_DWORD(&reg->ictrl, ICRX_EN_RISC_INT);
1480 RD_REG_DWORD(&reg->ictrl);
1481 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1482}
1483
1484static void
e315cd28 1485qla24xx_disable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1486{
1487 unsigned long flags = 0;
1488 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1489
124f85e6
AV		 1490 if (IS_NOPOLLING_TYPE(ha))
1491 return;
fd34f556
AV		 1492 spin_lock_irqsave(&ha->hardware_lock, flags);
1493 ha->interrupts_on = 0;
1494 WRT_REG_DWORD(&reg->ictrl, 0);
1495 RD_REG_DWORD(&reg->ictrl);
1496 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1497}
1498
1499static struct isp_operations qla2100_isp_ops = {
1500 .pci_config = qla2100_pci_config,
1501 .reset_chip = qla2x00_reset_chip,
1502 .chip_diag = qla2x00_chip_diag,
1503 .config_rings = qla2x00_config_rings,
1504 .reset_adapter = qla2x00_reset_adapter,
1505 .nvram_config = qla2x00_nvram_config,
1506 .update_fw_options = qla2x00_update_fw_options,
1507 .load_risc = qla2x00_load_risc,
1508 .pci_info_str = qla2x00_pci_info_str,
1509 .fw_version_str = qla2x00_fw_version_str,
1510 .intr_handler = qla2100_intr_handler,
1511 .enable_intrs = qla2x00_enable_intrs,
1512 .disable_intrs = qla2x00_disable_intrs,
1513 .abort_command = qla2x00_abort_command,
523ec773
AV		 1514 .target_reset = qla2x00_abort_target,
1515 .lun_reset = qla2x00_lun_reset,
fd34f556
AV		 1516 .fabric_login = qla2x00_login_fabric,
1517 .fabric_logout = qla2x00_fabric_logout,
1518 .calc_req_entries = qla2x00_calc_iocbs_32,
1519 .build_iocbs = qla2x00_build_scsi_iocbs_32,
1520 .prep_ms_iocb = qla2x00_prep_ms_iocb,
1521 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
1522 .read_nvram = qla2x00_read_nvram_data,
1523 .write_nvram = qla2x00_write_nvram_data,
1524 .fw_dump = qla2100_fw_dump,
1525 .beacon_on = NULL,
1526 .beacon_off = NULL,
1527 .beacon_blink = NULL,
1528 .read_optrom = qla2x00_read_optrom_data,
1529 .write_optrom = qla2x00_write_optrom_data,
1530 .get_flash_version = qla2x00_get_flash_version,
e315cd28 1531 .start_scsi = qla2x00_start_scsi,
a9083016 1532 .abort_isp = qla2x00_abort_isp,
fd34f556
AV		 1533};
1534
1535static struct isp_operations qla2300_isp_ops = {
1536 .pci_config = qla2300_pci_config,
1537 .reset_chip = qla2x00_reset_chip,
1538 .chip_diag = qla2x00_chip_diag,
1539 .config_rings = qla2x00_config_rings,
1540 .reset_adapter = qla2x00_reset_adapter,
1541 .nvram_config = qla2x00_nvram_config,
1542 .update_fw_options = qla2x00_update_fw_options,
1543 .load_risc = qla2x00_load_risc,
1544 .pci_info_str = qla2x00_pci_info_str,
1545 .fw_version_str = qla2x00_fw_version_str,
1546 .intr_handler = qla2300_intr_handler,
1547 .enable_intrs = qla2x00_enable_intrs,
1548 .disable_intrs = qla2x00_disable_intrs,
1549 .abort_command = qla2x00_abort_command,
523ec773
AV		 1550 .target_reset = qla2x00_abort_target,
1551 .lun_reset = qla2x00_lun_reset,
fd34f556
AV		 1552 .fabric_login = qla2x00_login_fabric,
1553 .fabric_logout = qla2x00_fabric_logout,
1554 .calc_req_entries = qla2x00_calc_iocbs_32,
1555 .build_iocbs = qla2x00_build_scsi_iocbs_32,
1556 .prep_ms_iocb = qla2x00_prep_ms_iocb,
1557 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
1558 .read_nvram = qla2x00_read_nvram_data,
1559 .write_nvram = qla2x00_write_nvram_data,
1560 .fw_dump = qla2300_fw_dump,
1561 .beacon_on = qla2x00_beacon_on,
1562 .beacon_off = qla2x00_beacon_off,
1563 .beacon_blink = qla2x00_beacon_blink,
1564 .read_optrom = qla2x00_read_optrom_data,
1565 .write_optrom = qla2x00_write_optrom_data,
1566 .get_flash_version = qla2x00_get_flash_version,
e315cd28 1567 .start_scsi = qla2x00_start_scsi,
a9083016 1568 .abort_isp = qla2x00_abort_isp,
fd34f556
AV		 1569};
1570
1571static struct isp_operations qla24xx_isp_ops = {
1572 .pci_config = qla24xx_pci_config,
1573 .reset_chip = qla24xx_reset_chip,
1574 .chip_diag = qla24xx_chip_diag,
1575 .config_rings = qla24xx_config_rings,
1576 .reset_adapter = qla24xx_reset_adapter,
1577 .nvram_config = qla24xx_nvram_config,
1578 .update_fw_options = qla24xx_update_fw_options,
1579 .load_risc = qla24xx_load_risc,
1580 .pci_info_str = qla24xx_pci_info_str,
1581 .fw_version_str = qla24xx_fw_version_str,
1582 .intr_handler = qla24xx_intr_handler,
1583 .enable_intrs = qla24xx_enable_intrs,
1584 .disable_intrs = qla24xx_disable_intrs,
1585 .abort_command = qla24xx_abort_command,
523ec773
AV		 1586 .target_reset = qla24xx_abort_target,
1587 .lun_reset = qla24xx_lun_reset,
fd34f556
AV		 1588 .fabric_login = qla24xx_login_fabric,
1589 .fabric_logout = qla24xx_fabric_logout,
1590 .calc_req_entries = NULL,
1591 .build_iocbs = NULL,
1592 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1593 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1594 .read_nvram = qla24xx_read_nvram_data,
1595 .write_nvram = qla24xx_write_nvram_data,
1596 .fw_dump = qla24xx_fw_dump,
1597 .beacon_on = qla24xx_beacon_on,
1598 .beacon_off = qla24xx_beacon_off,
1599 .beacon_blink = qla24xx_beacon_blink,
1600 .read_optrom = qla24xx_read_optrom_data,
1601 .write_optrom = qla24xx_write_optrom_data,
1602 .get_flash_version = qla24xx_get_flash_version,
e315cd28 1603 .start_scsi = qla24xx_start_scsi,
a9083016 1604 .abort_isp = qla2x00_abort_isp,
fd34f556
AV		 1605};
1606
c3a2f0df
AV		 1607static struct isp_operations qla25xx_isp_ops = {
1608 .pci_config = qla25xx_pci_config,
1609 .reset_chip = qla24xx_reset_chip,
1610 .chip_diag = qla24xx_chip_diag,
1611 .config_rings = qla24xx_config_rings,
1612 .reset_adapter = qla24xx_reset_adapter,
1613 .nvram_config = qla24xx_nvram_config,
1614 .update_fw_options = qla24xx_update_fw_options,
1615 .load_risc = qla24xx_load_risc,
1616 .pci_info_str = qla24xx_pci_info_str,
1617 .fw_version_str = qla24xx_fw_version_str,
1618 .intr_handler = qla24xx_intr_handler,
1619 .enable_intrs = qla24xx_enable_intrs,
1620 .disable_intrs = qla24xx_disable_intrs,
1621 .abort_command = qla24xx_abort_command,
523ec773
AV		 1622 .target_reset = qla24xx_abort_target,
1623 .lun_reset = qla24xx_lun_reset,
c3a2f0df
AV		 1624 .fabric_login = qla24xx_login_fabric,
1625 .fabric_logout = qla24xx_fabric_logout,
1626 .calc_req_entries = NULL,
1627 .build_iocbs = NULL,
1628 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1629 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1630 .read_nvram = qla25xx_read_nvram_data,
1631 .write_nvram = qla25xx_write_nvram_data,
1632 .fw_dump = qla25xx_fw_dump,
1633 .beacon_on = qla24xx_beacon_on,
1634 .beacon_off = qla24xx_beacon_off,
1635 .beacon_blink = qla24xx_beacon_blink,
338c9161 1636 .read_optrom = qla25xx_read_optrom_data,
c3a2f0df
AV		 1637 .write_optrom = qla24xx_write_optrom_data,
1638 .get_flash_version = qla24xx_get_flash_version,
bad75002 1639 .start_scsi = qla24xx_dif_start_scsi,
a9083016 1640 .abort_isp = qla2x00_abort_isp,
c3a2f0df
AV		 1641};
1642
3a03eb79
AV		 1643static struct isp_operations qla81xx_isp_ops = {
1644 .pci_config = qla25xx_pci_config,
1645 .reset_chip = qla24xx_reset_chip,
1646 .chip_diag = qla24xx_chip_diag,
1647 .config_rings = qla24xx_config_rings,
1648 .reset_adapter = qla24xx_reset_adapter,
1649 .nvram_config = qla81xx_nvram_config,
1650 .update_fw_options = qla81xx_update_fw_options,
eaac30be 1651 .load_risc = qla81xx_load_risc,
3a03eb79
AV		 1652 .pci_info_str = qla24xx_pci_info_str,
1653 .fw_version_str = qla24xx_fw_version_str,
1654 .intr_handler = qla24xx_intr_handler,
1655 .enable_intrs = qla24xx_enable_intrs,
1656 .disable_intrs = qla24xx_disable_intrs,
1657 .abort_command = qla24xx_abort_command,
1658 .target_reset = qla24xx_abort_target,
1659 .lun_reset = qla24xx_lun_reset,
1660 .fabric_login = qla24xx_login_fabric,
1661 .fabric_logout = qla24xx_fabric_logout,
1662 .calc_req_entries = NULL,
1663 .build_iocbs = NULL,
1664 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1665 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
3d79038f
AV		 1666 .read_nvram = NULL,
1667 .write_nvram = NULL,
3a03eb79
AV		 1668 .fw_dump = qla81xx_fw_dump,
1669 .beacon_on = qla24xx_beacon_on,
1670 .beacon_off = qla24xx_beacon_off,
1671 .beacon_blink = qla24xx_beacon_blink,
1672 .read_optrom = qla25xx_read_optrom_data,
1673 .write_optrom = qla24xx_write_optrom_data,
1674 .get_flash_version = qla24xx_get_flash_version,
ba77ef53 1675 .start_scsi = qla24xx_dif_start_scsi,
a9083016
GM		 1676 .abort_isp = qla2x00_abort_isp,
1677};
1678
1679static struct isp_operations qla82xx_isp_ops = {
1680 .pci_config = qla82xx_pci_config,
1681 .reset_chip = qla82xx_reset_chip,
1682 .chip_diag = qla24xx_chip_diag,
1683 .config_rings = qla82xx_config_rings,
1684 .reset_adapter = qla24xx_reset_adapter,
1685 .nvram_config = qla81xx_nvram_config,
1686 .update_fw_options = qla24xx_update_fw_options,
1687 .load_risc = qla82xx_load_risc,
1688 .pci_info_str = qla82xx_pci_info_str,
1689 .fw_version_str = qla24xx_fw_version_str,
1690 .intr_handler = qla82xx_intr_handler,
1691 .enable_intrs = qla82xx_enable_intrs,
1692 .disable_intrs = qla82xx_disable_intrs,
1693 .abort_command = qla24xx_abort_command,
1694 .target_reset = qla24xx_abort_target,
1695 .lun_reset = qla24xx_lun_reset,
1696 .fabric_login = qla24xx_login_fabric,
1697 .fabric_logout = qla24xx_fabric_logout,
1698 .calc_req_entries = NULL,
1699 .build_iocbs = NULL,
1700 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1701 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1702 .read_nvram = qla24xx_read_nvram_data,
1703 .write_nvram = qla24xx_write_nvram_data,
1704 .fw_dump = qla24xx_fw_dump,
999916dc
SK		 1705 .beacon_on = qla82xx_beacon_on,
1706 .beacon_off = qla82xx_beacon_off,
1707 .beacon_blink = NULL,
a9083016
GM		 1708 .read_optrom = qla82xx_read_optrom_data,
1709 .write_optrom = qla82xx_write_optrom_data,
1710 .get_flash_version = qla24xx_get_flash_version,
1711 .start_scsi = qla82xx_start_scsi,
1712 .abort_isp = qla82xx_abort_isp,
3a03eb79
AV		 1713};
1714
ea5b6382 1715static inline void
e315cd28 1716qla2x00_set_isp_flags(struct qla_hw_data *ha)
ea5b6382 1717{
1718 ha->device_type = DT_EXTENDED_IDS;
1719 switch (ha->pdev->device) {
1720 case PCI_DEVICE_ID_QLOGIC_ISP2100:
1721 ha->device_type |= DT_ISP2100;
1722 ha->device_type &= ~DT_EXTENDED_IDS;
441d1072 1723 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
ea5b6382 1724 break;
1725 case PCI_DEVICE_ID_QLOGIC_ISP2200:
1726 ha->device_type |= DT_ISP2200;
1727 ha->device_type &= ~DT_EXTENDED_IDS;
441d1072 1728 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
ea5b6382 1729 break;
1730 case PCI_DEVICE_ID_QLOGIC_ISP2300:
1731 ha->device_type |= DT_ISP2300;
4a59f71d 1732 ha->device_type |= DT_ZIO_SUPPORTED;
441d1072 1733 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 1734 break;
1735 case PCI_DEVICE_ID_QLOGIC_ISP2312:
1736 ha->device_type |= DT_ISP2312;
4a59f71d 1737 ha->device_type |= DT_ZIO_SUPPORTED;
441d1072 1738 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 1739 break;
1740 case PCI_DEVICE_ID_QLOGIC_ISP2322:
1741 ha->device_type |= DT_ISP2322;
4a59f71d 1742 ha->device_type |= DT_ZIO_SUPPORTED;
ea5b6382 1743 if (ha->pdev->subsystem_vendor == 0x1028 &&
1744 ha->pdev->subsystem_device == 0x0170)
1745 ha->device_type |= DT_OEM_001;
441d1072 1746 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 1747 break;
1748 case PCI_DEVICE_ID_QLOGIC_ISP6312:
1749 ha->device_type |= DT_ISP6312;
441d1072 1750 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 1751 break;
1752 case PCI_DEVICE_ID_QLOGIC_ISP6322:
1753 ha->device_type |= DT_ISP6322;
441d1072 1754 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 1755 break;
1756 case PCI_DEVICE_ID_QLOGIC_ISP2422:
1757 ha->device_type |= DT_ISP2422;
4a59f71d 1758 ha->device_type |= DT_ZIO_SUPPORTED;
e428924c 1759 ha->device_type |= DT_FWI2;
c76f2c01 1760 ha->device_type |= DT_IIDMA;
441d1072 1761 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 1762 break;
1763 case PCI_DEVICE_ID_QLOGIC_ISP2432:
1764 ha->device_type |= DT_ISP2432;
4a59f71d 1765 ha->device_type |= DT_ZIO_SUPPORTED;
e428924c 1766 ha->device_type |= DT_FWI2;
c76f2c01 1767 ha->device_type |= DT_IIDMA;
441d1072 1768 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 1769 break;
4d4df193
HK		 1770 case PCI_DEVICE_ID_QLOGIC_ISP8432:
1771 ha->device_type |= DT_ISP8432;
1772 ha->device_type |= DT_ZIO_SUPPORTED;
1773 ha->device_type |= DT_FWI2;
1774 ha->device_type |= DT_IIDMA;
1775 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
1776 break;
044cc6c8 1777 case PCI_DEVICE_ID_QLOGIC_ISP5422:
1778 ha->device_type |= DT_ISP5422;
e428924c 1779 ha->device_type |= DT_FWI2;
441d1072 1780 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 1781 break;
044cc6c8 1782 case PCI_DEVICE_ID_QLOGIC_ISP5432:
1783 ha->device_type |= DT_ISP5432;
e428924c 1784 ha->device_type |= DT_FWI2;
441d1072 1785 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 1786 break;
c3a2f0df
AV		 1787 case PCI_DEVICE_ID_QLOGIC_ISP2532:
1788 ha->device_type |= DT_ISP2532;
1789 ha->device_type |= DT_ZIO_SUPPORTED;
1790 ha->device_type |= DT_FWI2;
1791 ha->device_type |= DT_IIDMA;
441d1072 1792 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 1793 break;
3a03eb79
AV		 1794 case PCI_DEVICE_ID_QLOGIC_ISP8001:
1795 ha->device_type |= DT_ISP8001;
1796 ha->device_type |= DT_ZIO_SUPPORTED;
1797 ha->device_type |= DT_FWI2;
1798 ha->device_type |= DT_IIDMA;
1799 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
1800 break;
a9083016
GM		 1801 case PCI_DEVICE_ID_QLOGIC_ISP8021:
1802 ha->device_type |= DT_ISP8021;
1803 ha->device_type |= DT_ZIO_SUPPORTED;
1804 ha->device_type |= DT_FWI2;
1805 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
1806 /* Initialize 82XX ISP flags */
1807 qla82xx_init_flags(ha);
1808 break;
ea5b6382 1809 }
e5b68a61 1810
a9083016
GM		 1811 if (IS_QLA82XX(ha))
1812 ha->port_no = !(ha->portnum & 1);
1813 else
1814 /* Get adapter physical port no from interrupt pin register. */
1815 pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no);
1816
e5b68a61
AC		 1817 if (ha->port_no & 1)
1818 ha->flags.port0 = 1;
1819 else
1820 ha->flags.port0 = 0;
7c3df132 1821 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b,
d8424f68 1822 "device_type=0x%x port=%d fw_srisc_address=0x%x.\n",
7c3df132 1823 ha->device_type, ha->flags.port0, ha->fw_srisc_address);
ea5b6382 1824}
1825
1da177e4 1826static int
e315cd28 1827qla2x00_iospace_config(struct qla_hw_data *ha)
1da177e4 1828{
3776541d 1829 resource_size_t pio;
73208dfd 1830 uint16_t msix;
68ca949c 1831 int cpus;
1da177e4 1832
a9083016
GM		 1833 if (IS_QLA82XX(ha))
1834 return qla82xx_iospace_config(ha);
1835
285d0321
AV		 1836 if (pci_request_selected_regions(ha->pdev, ha->bars,
1837 QLA2XXX_DRIVER_NAME)) {
7c3df132
SK		 1838 ql_log_pci(ql_log_fatal, ha->pdev, 0x0011,
1839 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
285d0321 1840 pci_name(ha->pdev));
285d0321
AV		 1841 goto iospace_error_exit;
1842 }
1843 if (!(ha->bars & 1))
1844 goto skip_pio;
1845
1da177e4
LT		 1846 /* We only need PIO for Flash operations on ISP2312 v2 chips. */
1847 pio = pci_resource_start(ha->pdev, 0);
3776541d
AV		 1848 if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) {
1849 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
7c3df132
SK		 1850 ql_log_pci(ql_log_warn, ha->pdev, 0x0012,
1851 "Invalid pci I/O region size (%s).\n",
1852 pci_name(ha->pdev));
1da177e4
LT		 1853 pio = 0;
1854 }
1855 } else {
7c3df132
SK		 1856 ql_log_pci(ql_log_warn, ha->pdev, 0x0013,
1857 "Region #0 no a PIO resource (%s).\n",
1da177e4
LT		 1858 pci_name(ha->pdev));
1859 pio = 0;
1860 }
285d0321 1861 ha->pio_address = pio;
7c3df132 1862 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014,
d8424f68
JP		 1863 "PIO address=%llu.\n",
1864 (unsigned long long)ha->pio_address);
1da177e4 1865
285d0321 1866skip_pio:
1da177e4 1867 /* Use MMIO operations for all accesses. */
3776541d 1868 if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) {
7c3df132
SK		 1869 ql_log_pci(ql_log_fatal, ha->pdev, 0x0015,
1870 "Region #1 not an MMIO resource (%s), aborting.\n",
1da177e4
LT		 1871 pci_name(ha->pdev));
1872 goto iospace_error_exit;
1873 }
3776541d 1874 if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) {
7c3df132
SK		 1875 ql_log_pci(ql_log_fatal, ha->pdev, 0x0016,
1876 "Invalid PCI mem region size (%s), aborting.\n",
1877 pci_name(ha->pdev));
1da177e4
LT		 1878 goto iospace_error_exit;
1879 }
1880
3776541d 1881 ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN);
1da177e4 1882 if (!ha->iobase) {
7c3df132
SK		 1883 ql_log_pci(ql_log_fatal, ha->pdev, 0x0017,
1884 "Cannot remap MMIO (%s), aborting.\n",
1885 pci_name(ha->pdev));
1da177e4
LT		 1886 goto iospace_error_exit;
1887 }
1888
73208dfd 1889 /* Determine queue resources */
2afa19a9 1890 ha->max_req_queues = ha->max_rsp_queues = 1;
d84a47c2
MH		 1891 if ((ql2xmaxqueues <= 1 && !ql2xmultique_tag) ||
1892 (ql2xmaxqueues > 1 && ql2xmultique_tag) ||
2afa19a9 1893 (!IS_QLA25XX(ha) && !IS_QLA81XX(ha)))
17d98630 1894 goto mqiobase_exit;
d84a47c2 1895
17d98630
AC		 1896 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3),
1897 pci_resource_len(ha->pdev, 3));
1898 if (ha->mqiobase) {
7c3df132
SK		 1899 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018,
1900 "MQIO Base=%p.\n", ha->mqiobase);
17d98630
AC		 1901 /* Read MSIX vector size of the board */
1902 pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix);
1903 ha->msix_count = msix;
68ca949c
AC		 1904 /* Max queues are bounded by available msix vectors */
1905 /* queue 0 uses two msix vectors */
1906 if (ql2xmultique_tag) {
1907 cpus = num_online_cpus();
27dc9c5a 1908 ha->max_rsp_queues = (ha->msix_count - 1 > cpus) ?
68ca949c
AC		 1909 (cpus + 1) : (ha->msix_count - 1);
1910 ha->max_req_queues = 2;
1911 } else if (ql2xmaxqueues > 1) {
2afa19a9 1912 ha->max_req_queues = ql2xmaxqueues > QLA_MQ_SIZE ?
7c3df132
SK		 1913 QLA_MQ_SIZE : ql2xmaxqueues;
1914 ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc008,
1915 "QoS mode set, max no of request queues:%d.\n",
1916 ha->max_req_queues);
1917 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0019,
1918 "QoS mode set, max no of request queues:%d.\n",
1919 ha->max_req_queues);
2afa19a9 1920 }
7c3df132
SK		 1921 ql_log_pci(ql_log_info, ha->pdev, 0x001a,
1922 "MSI-X vector count: %d.\n", msix);
2afa19a9 1923 } else
7c3df132
SK		 1924 ql_log_pci(ql_log_info, ha->pdev, 0x001b,
1925 "BAR 3 not enabled.\n");
17d98630
AC		 1926
1927mqiobase_exit:
2afa19a9 1928 ha->msix_count = ha->max_rsp_queues + 1;
7c3df132
SK		 1929 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c,
1930 "MSIX Count:%d.\n", ha->msix_count);
1da177e4
LT		 1931 return (0);
1932
1933iospace_error_exit:
1934 return (-ENOMEM);
1935}
1936
1e99e33a
AV		 1937static void
1938qla2xxx_scan_start(struct Scsi_Host *shost)
1939{
e315cd28 1940 scsi_qla_host_t *vha = shost_priv(shost);
1e99e33a 1941
cbc8eb67
AV		 1942 if (vha->hw->flags.running_gold_fw)
1943 return;
1944
e315cd28
AC		 1945 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
1946 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
1947 set_bit(RSCN_UPDATE, &vha->dpc_flags);
1948 set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags);
1e99e33a
AV		 1949}
1950
1951static int
1952qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time)
1953{
e315cd28 1954 scsi_qla_host_t *vha = shost_priv(shost);
1e99e33a 1955
e315cd28 1956 if (!vha->host)
1e99e33a 1957 return 1;
e315cd28 1958 if (time > vha->hw->loop_reset_delay * HZ)
1e99e33a
AV		 1959 return 1;
1960
e315cd28 1961 return atomic_read(&vha->loop_state) == LOOP_READY;
1e99e33a
AV		 1962}
1963
1da177e4
LT		 1964/*
1965 * PCI driver interface
1966 */
7ee61397
AV		 1967static int __devinit
1968qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
1da177e4 1969{
a1541d5a 1970 int ret = -ENODEV;
1da177e4 1971 struct Scsi_Host *host;
e315cd28
AC		 1972 scsi_qla_host_t *base_vha = NULL;
1973 struct qla_hw_data *ha;
29856e28 1974 char pci_info[30];
1da177e4 1975 char fw_str[30];
5433383e 1976 struct scsi_host_template *sht;
c51da4ec 1977 int bars, max_id, mem_only = 0;
e315cd28 1978 uint16_t req_length = 0, rsp_length = 0;
73208dfd
AC		 1979 struct req_que *req = NULL;
1980 struct rsp_que *rsp = NULL;
1da177e4 1981
285d0321 1982 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO);
a5326f86 1983 sht = &qla2xxx_driver_template;
5433383e 1984 if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 ||
8bc69e7d 1985 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 ||
4d4df193 1986 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 ||
8bc69e7d 1987 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 ||
c3a2f0df 1988 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 ||
3a03eb79 1989 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 ||
a9083016
GM		 1990 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 ||
1991 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021) {
285d0321 1992 bars = pci_select_bars(pdev, IORESOURCE_MEM);
09483916 1993 mem_only = 1;
7c3df132
SK		 1994 ql_dbg_pci(ql_dbg_init, pdev, 0x0007,
1995 "Mem only adapter.\n");
285d0321 1996 }
7c3df132
SK		 1997 ql_dbg_pci(ql_dbg_init, pdev, 0x0008,
1998 "Bars=%d.\n", bars);
285d0321 1999
09483916
BH		 2000 if (mem_only) {
2001 if (pci_enable_device_mem(pdev))
2002 goto probe_out;
2003 } else {
2004 if (pci_enable_device(pdev))
2005 goto probe_out;
2006 }
285d0321 2007
0927678f
JB		 2008 /* This may fail but that's ok */
2009 pci_enable_pcie_error_reporting(pdev);
285d0321 2010
e315cd28
AC		 2011 ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL);
2012 if (!ha) {
7c3df132
SK		 2013 ql_log_pci(ql_log_fatal, pdev, 0x0009,
2014 "Unable to allocate memory for ha.\n");
e315cd28 2015 goto probe_out;
1da177e4 2016 }
7c3df132
SK		 2017 ql_dbg_pci(ql_dbg_init, pdev, 0x000a,
2018 "Memory allocated for ha=%p.\n", ha);
e315cd28 2019 ha->pdev = pdev;
1da177e4
LT		 2020
2021 /* Clear our data area */
285d0321 2022 ha->bars = bars;
09483916 2023 ha->mem_only = mem_only;
df4bf0bb 2024 spin_lock_init(&ha->hardware_lock);
339aa70e 2025 spin_lock_init(&ha->vport_slock);
1da177e4 2026
ea5b6382 2027 /* Set ISP-type information. */
2028 qla2x00_set_isp_flags(ha);
ca79cf66
DG		 2029
2030 /* Set EEH reset type to fundamental if required by hba */
2031 if ( IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha)) {
2032 pdev->needs_freset = 1;
ca79cf66
DG		 2033 }
2034
1da177e4
LT		 2035 /* Configure PCI I/O space */
2036 ret = qla2x00_iospace_config(ha);
a1541d5a 2037 if (ret)
e315cd28 2038 goto probe_hw_failed;
1da177e4 2039
7c3df132
SK		 2040 ql_log_pci(ql_log_info, pdev, 0x001d,
2041 "Found an ISP%04X irq %d iobase 0x%p.\n",
2042 pdev->device, pdev->irq, ha->iobase);
1da177e4 2043 ha->prev_topology = 0;
fca29703 2044 ha->init_cb_size = sizeof(init_cb_t);
d8b45213 2045 ha->link_data_rate = PORT_SPEED_UNKNOWN;
854165f4 2046 ha->optrom_size = OPTROM_SIZE_2300;
1da177e4 2047
abbd8870 2048 /* Assign ISP specific operations. */
e315cd28 2049 max_id = MAX_TARGETS_2200;
1da177e4 2050 if (IS_QLA2100(ha)) {
e315cd28 2051 max_id = MAX_TARGETS_2100;
1da177e4 2052 ha->mbx_count = MAILBOX_REGISTER_COUNT_2100;
e315cd28
AC		 2053 req_length = REQUEST_ENTRY_CNT_2100;
2054 rsp_length = RESPONSE_ENTRY_CNT_2100;
2055 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
abbd8870 2056 ha->gid_list_info_size = 4;
3a03eb79
AV		 2057 ha->flash_conf_off = ~0;
2058 ha->flash_data_off = ~0;
2059 ha->nvram_conf_off = ~0;
2060 ha->nvram_data_off = ~0;
fd34f556 2061 ha->isp_ops = &qla2100_isp_ops;
1da177e4 2062 } else if (IS_QLA2200(ha)) {
1da177e4 2063 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2064 req_length = REQUEST_ENTRY_CNT_2200;
2065 rsp_length = RESPONSE_ENTRY_CNT_2100;
2066 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
abbd8870 2067 ha->gid_list_info_size = 4;
3a03eb79
AV		 2068 ha->flash_conf_off = ~0;
2069 ha->flash_data_off = ~0;
2070 ha->nvram_conf_off = ~0;
2071 ha->nvram_data_off = ~0;
fd34f556 2072 ha->isp_ops = &qla2100_isp_ops;
fca29703 2073 } else if (IS_QLA23XX(ha)) {
1da177e4 2074 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2075 req_length = REQUEST_ENTRY_CNT_2200;
2076 rsp_length = RESPONSE_ENTRY_CNT_2300;
2077 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
abbd8870 2078 ha->gid_list_info_size = 6;
854165f4 2079 if (IS_QLA2322(ha) || IS_QLA6322(ha))
2080 ha->optrom_size = OPTROM_SIZE_2322;
3a03eb79
AV		 2081 ha->flash_conf_off = ~0;
2082 ha->flash_data_off = ~0;
2083 ha->nvram_conf_off = ~0;
2084 ha->nvram_data_off = ~0;
fd34f556 2085 ha->isp_ops = &qla2300_isp_ops;
4d4df193 2086 } else if (IS_QLA24XX_TYPE(ha)) {
fca29703 2087 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2088 req_length = REQUEST_ENTRY_CNT_24XX;
2089 rsp_length = RESPONSE_ENTRY_CNT_2300;
2090 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2c3dfe3f 2091 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
fca29703 2092 ha->gid_list_info_size = 8;
854165f4 2093 ha->optrom_size = OPTROM_SIZE_24XX;
73208dfd 2094 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX;
fd34f556 2095 ha->isp_ops = &qla24xx_isp_ops;
3a03eb79
AV		 2096 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2097 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2098 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2099 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
c3a2f0df 2100 } else if (IS_QLA25XX(ha)) {
c3a2f0df 2101 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2102 req_length = REQUEST_ENTRY_CNT_24XX;
2103 rsp_length = RESPONSE_ENTRY_CNT_2300;
2104 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
c3a2f0df 2105 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
c3a2f0df
AV		 2106 ha->gid_list_info_size = 8;
2107 ha->optrom_size = OPTROM_SIZE_25XX;
73208dfd 2108 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
c3a2f0df 2109 ha->isp_ops = &qla25xx_isp_ops;
3a03eb79
AV		 2110 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2111 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2112 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2113 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
2114 } else if (IS_QLA81XX(ha)) {
2115 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2116 req_length = REQUEST_ENTRY_CNT_24XX;
2117 rsp_length = RESPONSE_ENTRY_CNT_2300;
2118 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2119 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2120 ha->gid_list_info_size = 8;
2121 ha->optrom_size = OPTROM_SIZE_81XX;
40859ae5 2122 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3a03eb79
AV		 2123 ha->isp_ops = &qla81xx_isp_ops;
2124 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2125 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2126 ha->nvram_conf_off = ~0;
2127 ha->nvram_data_off = ~0;
a9083016
GM		 2128 } else if (IS_QLA82XX(ha)) {
2129 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2130 req_length = REQUEST_ENTRY_CNT_82XX;
2131 rsp_length = RESPONSE_ENTRY_CNT_82XX;
2132 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2133 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2134 ha->gid_list_info_size = 8;
2135 ha->optrom_size = OPTROM_SIZE_82XX;
087c621e 2136 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
a9083016
GM		 2137 ha->isp_ops = &qla82xx_isp_ops;
2138 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2139 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2140 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2141 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
1da177e4 2142 }
7c3df132
SK		 2143 ql_dbg_pci(ql_dbg_init, pdev, 0x001e,
2144 "mbx_count=%d, req_length=%d, "
2145 "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, "
2146 "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, .\n",
2147 ha->mbx_count, req_length, rsp_length, ha->max_loop_id,
2148 ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size,
2149 ha->nvram_npiv_size);
2150 ql_dbg_pci(ql_dbg_init, pdev, 0x001f,
2151 "isp_ops=%p, flash_conf_off=%d, "
2152 "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n",
2153 ha->isp_ops, ha->flash_conf_off, ha->flash_data_off,
2154 ha->nvram_conf_off, ha->nvram_data_off);
6c2f527c 2155 mutex_init(&ha->vport_lock);
0b05a1f0
MB		 2156 init_completion(&ha->mbx_cmd_comp);
2157 complete(&ha->mbx_cmd_comp);
2158 init_completion(&ha->mbx_intr_comp);
23f2ebd1 2159 init_completion(&ha->dcbx_comp);
1da177e4 2160
2c3dfe3f 2161 set_bit(0, (unsigned long *) ha->vp_idx_map);
1da177e4 2162
53303c42 2163 qla2x00_config_dma_addressing(ha);
7c3df132
SK		 2164 ql_dbg_pci(ql_dbg_init, pdev, 0x0020,
2165 "64 Bit addressing is %s.\n",
2166 ha->flags.enable_64bit_addressing ? "enable" :
2167 "disable");
73208dfd 2168 ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp);
e315cd28 2169 if (!ret) {
7c3df132
SK		 2170 ql_log_pci(ql_log_fatal, pdev, 0x0031,
2171 "Failed to allocate memory for adapter, aborting.\n");
1da177e4 2172
e315cd28
AC		 2173 goto probe_hw_failed;
2174 }
2175
73208dfd 2176 req->max_q_depth = MAX_Q_DEPTH;
e315cd28 2177 if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU)
73208dfd
AC		 2178 req->max_q_depth = ql2xmaxqdepth;
2179
e315cd28
AC		 2180
2181 base_vha = qla2x00_create_host(sht, ha);
2182 if (!base_vha) {
a1541d5a 2183 ret = -ENOMEM;
6e9f21f3 2184 qla2x00_mem_free(ha);
2afa19a9
AC		 2185 qla2x00_free_req_que(ha, req);
2186 qla2x00_free_rsp_que(ha, rsp);
e315cd28 2187 goto probe_hw_failed;
1da177e4
LT		 2188 }
2189
e315cd28
AC		 2190 pci_set_drvdata(pdev, base_vha);
2191
e315cd28 2192 host = base_vha->host;
2afa19a9 2193 base_vha->req = req;
73208dfd
AC		 2194 host->can_queue = req->length + 128;
2195 if (IS_QLA2XXX_MIDTYPE(ha))
e315cd28 2196 base_vha->mgmt_svr_loop_id = 10 + base_vha->vp_idx;
73208dfd 2197 else
e315cd28
AC		 2198 base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER +
2199 base_vha->vp_idx;
58548cb5
GM		 2200
2201 /* Set the SG table size based on ISP type */
2202 if (!IS_FWI2_CAPABLE(ha)) {
2203 if (IS_QLA2100(ha))
2204 host->sg_tablesize = 32;
2205 } else {
2206 if (!IS_QLA82XX(ha))
2207 host->sg_tablesize = QLA_SG_ALL;
2208 }
7c3df132
SK		 2209 ql_dbg(ql_dbg_init, base_vha, 0x0032,
2210 "can_queue=%d, req=%p, "
2211 "mgmt_svr_loop_id=%d, sg_tablesize=%d.\n",
2212 host->can_queue, base_vha->req,
2213 base_vha->mgmt_svr_loop_id, host->sg_tablesize);
e315cd28
AC		 2214 host->max_id = max_id;
2215 host->this_id = 255;
2216 host->cmd_per_lun = 3;
2217 host->unique_id = host->host_no;
e02587d7 2218 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif)
0c470874
AE		 2219 host->max_cmd_len = 32;
2220 else
2221 host->max_cmd_len = MAX_CMDSZ;
e315cd28 2222 host->max_channel = MAX_BUSES - 1;
82515920 2223 host->max_lun = ql2xmaxlun;
e315cd28 2224 host->transportt = qla2xxx_transport_template;
9a069e19 2225 sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC);
e315cd28 2226
7c3df132
SK		 2227 ql_dbg(ql_dbg_init, base_vha, 0x0033,
2228 "max_id=%d this_id=%d "
2229 "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d "
d8424f68 2230 "max_lun=%d transportt=%p, vendor_id=%llu.\n", host->max_id,
7c3df132
SK		 2231 host->this_id, host->cmd_per_lun, host->unique_id,
2232 host->max_cmd_len, host->max_channel, host->max_lun,
2233 host->transportt, sht->vendor_id);
2234
73208dfd
AC		 2235 /* Set up the irqs */
2236 ret = qla2x00_request_irqs(ha, rsp);
2237 if (ret)
6e9f21f3 2238 goto probe_init_failed;
90a86fc0
JC		 2239
2240 pci_save_state(pdev);
2241
73208dfd 2242 /* Alloc arrays of request and response ring ptrs */
7163ea81 2243que_init:
73208dfd 2244 if (!qla2x00_alloc_queues(ha)) {
7c3df132
SK		 2245 ql_log(ql_log_fatal, base_vha, 0x003d,
2246 "Failed to allocate memory for queue pointers.. aborting.\n");
6e9f21f3 2247 goto probe_init_failed;
73208dfd 2248 }
a9083016 2249
73208dfd
AC		 2250 ha->rsp_q_map[0] = rsp;
2251 ha->req_q_map[0] = req;
2afa19a9
AC		 2252 rsp->req = req;
2253 req->rsp = rsp;
2254 set_bit(0, ha->req_qid_map);
2255 set_bit(0, ha->rsp_qid_map);
08029990
AV		 2256 /* FWI2-capable only. */
2257 req->req_q_in = &ha->iobase->isp24.req_q_in;
2258 req->req_q_out = &ha->iobase->isp24.req_q_out;
2259 rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in;
2260 rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out;
17d98630 2261 if (ha->mqenable) {
08029990
AV		 2262 req->req_q_in = &ha->mqiobase->isp25mq.req_q_in;
2263 req->req_q_out = &ha->mqiobase->isp25mq.req_q_out;
2264 rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in;
2265 rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out;
17d98630
AC		 2266 }
2267
a9083016
GM		 2268 if (IS_QLA82XX(ha)) {
2269 req->req_q_out = &ha->iobase->isp82.req_q_out[0];
2270 rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0];
2271 rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0];
2272 }
2273
7c3df132
SK		 2274 ql_dbg(ql_dbg_multiq, base_vha, 0xc009,
2275 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
2276 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
2277 ql_dbg(ql_dbg_multiq, base_vha, 0xc00a,
2278 "req->req_q_in=%p req->req_q_out=%p "
2279 "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
2280 req->req_q_in, req->req_q_out,
2281 rsp->rsp_q_in, rsp->rsp_q_out);
2282 ql_dbg(ql_dbg_init, base_vha, 0x003e,
2283 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
2284 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
2285 ql_dbg(ql_dbg_init, base_vha, 0x003f,
2286 "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
2287 req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out);
1da177e4 2288
7c3df132
SK		 2289 if (qla2x00_initialize_adapter(base_vha)) {
2290 ql_log(ql_log_fatal, base_vha, 0x00d6,
2291 "Failed to initialize adapter - Adapter flags %x.\n",
2292 base_vha->device_flags);
1da177e4 2293
a9083016
GM		 2294 if (IS_QLA82XX(ha)) {
2295 qla82xx_idc_lock(ha);
2296 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
2297 QLA82XX_DEV_FAILED);
2298 qla82xx_idc_unlock(ha);
7c3df132
SK		 2299 ql_log(ql_log_fatal, base_vha, 0x00d7,
2300 "HW State: FAILED.\n");
a9083016
GM		 2301 }
2302
a1541d5a 2303 ret = -ENODEV;
1da177e4
LT		 2304 goto probe_failed;
2305 }
2306
7163ea81
AC		 2307 if (ha->mqenable) {
2308 if (qla25xx_setup_mode(base_vha)) {
7c3df132
SK		 2309 ql_log(ql_log_warn, base_vha, 0x00ec,
2310 "Failed to create queues, falling back to single queue mode.\n");
7163ea81
AC		 2311 goto que_init;
2312 }
2313 }
68ca949c 2314
cbc8eb67
AV		 2315 if (ha->flags.running_gold_fw)
2316 goto skip_dpc;
2317
1da177e4
LT		 2318 /*
2319 * Startup the kernel thread for this host adapter
2320 */
39a11240 2321 ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha,
7c3df132 2322 "%s_dpc", base_vha->host_str);
39a11240 2323 if (IS_ERR(ha->dpc_thread)) {
7c3df132
SK		 2324 ql_log(ql_log_fatal, base_vha, 0x00ed,
2325 "Failed to start DPC thread.\n");
39a11240 2326 ret = PTR_ERR(ha->dpc_thread);
1da177e4
LT		 2327 goto probe_failed;
2328 }
7c3df132
SK		 2329 ql_dbg(ql_dbg_init, base_vha, 0x00ee,
2330 "DPC thread started successfully.\n");
1da177e4 2331
cbc8eb67 2332skip_dpc:
e315cd28
AC		 2333 list_add_tail(&base_vha->list, &ha->vp_list);
2334 base_vha->host->irq = ha->pdev->irq;
1da177e4
LT		 2335
2336 /* Initialized the timer */
e315cd28 2337 qla2x00_start_timer(base_vha, qla2x00_timer, WATCH_INTERVAL);
7c3df132
SK		 2338 ql_dbg(ql_dbg_init, base_vha, 0x00ef,
2339 "Started qla2x00_timer with "
2340 "interval=%d.\n", WATCH_INTERVAL);
2341 ql_dbg(ql_dbg_init, base_vha, 0x00f0,
2342 "Detected hba at address=%p.\n",
2343 ha);
d19044c3 2344
e02587d7 2345 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) {
bad75002 2346 if (ha->fw_attributes & BIT_4) {
8cb2049c 2347 int prot = 0;
bad75002 2348 base_vha->flags.difdix_supported = 1;
7c3df132
SK		 2349 ql_dbg(ql_dbg_init, base_vha, 0x00f1,
2350 "Registering for DIF/DIX type 1 and 3 protection.\n");
8cb2049c
AE		 2351 if (ql2xenabledif == 1)
2352 prot = SHOST_DIX_TYPE0_PROTECTION;
bad75002 2353 scsi_host_set_prot(host,
8cb2049c 2354 prot | SHOST_DIF_TYPE1_PROTECTION
0c470874 2355 | SHOST_DIF_TYPE2_PROTECTION
bad75002
AE		 2356 | SHOST_DIF_TYPE3_PROTECTION
2357 | SHOST_DIX_TYPE1_PROTECTION
0c470874 2358 | SHOST_DIX_TYPE2_PROTECTION
bad75002
AE		 2359 | SHOST_DIX_TYPE3_PROTECTION);
2360 scsi_host_set_guard(host, SHOST_DIX_GUARD_CRC);
2361 } else
2362 base_vha->flags.difdix_supported = 0;
2363 }
2364
a9083016
GM		 2365 ha->isp_ops->enable_intrs(ha);
2366
a1541d5a
AV		 2367 ret = scsi_add_host(host, &pdev->dev);
2368 if (ret)
2369 goto probe_failed;
2370
1486400f
MR		 2371 base_vha->flags.init_done = 1;
2372 base_vha->flags.online = 1;
2373
7c3df132
SK		 2374 ql_dbg(ql_dbg_init, base_vha, 0x00f2,
2375 "Init done and hba is online.\n");
2376
1e99e33a
AV		 2377 scsi_scan_host(host);
2378
e315cd28 2379 qla2x00_alloc_sysfs_attr(base_vha);
a1541d5a 2380
e315cd28 2381 qla2x00_init_host_attr(base_vha);
a1541d5a 2382
e315cd28 2383 qla2x00_dfs_setup(base_vha);
df613b96 2384
7c3df132
SK		 2385 ql_log(ql_log_info, base_vha, 0x00fa,
2386 "QLogic Fibre Channed HBA Driver: %s.\n",
2387 qla2x00_version_str);
2388 ql_log(ql_log_info, base_vha, 0x00fb,
2389 "QLogic %s - %s.\n",
2390 ha->model_number, ha->model_desc ? ha->model_desc : "");
2391 ql_log(ql_log_info, base_vha, 0x00fc,
2392 "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n",
2393 pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info),
2394 pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-',
2395 base_vha->host_no,
e315cd28 2396 ha->isp_ops->fw_version_str(base_vha, fw_str));
1da177e4 2397
1da177e4
LT		 2398 return 0;
2399
6e9f21f3 2400probe_init_failed:
2afa19a9
AC		 2401 qla2x00_free_req_que(ha, req);
2402 qla2x00_free_rsp_que(ha, rsp);
2403 ha->max_req_queues = ha->max_rsp_queues = 0;
6e9f21f3 2404
1da177e4 2405probe_failed:
b9978769
AV		 2406 if (base_vha->timer_active)
2407 qla2x00_stop_timer(base_vha);
2408 base_vha->flags.online = 0;
2409 if (ha->dpc_thread) {
2410 struct task_struct *t = ha->dpc_thread;
2411
2412 ha->dpc_thread = NULL;
2413 kthread_stop(t);
2414 }
2415
e315cd28 2416 qla2x00_free_device(base_vha);
1da177e4 2417
e315cd28 2418 scsi_host_put(base_vha->host);
1da177e4 2419
e315cd28 2420probe_hw_failed:
a9083016
GM		 2421 if (IS_QLA82XX(ha)) {
2422 qla82xx_idc_lock(ha);
2423 qla82xx_clear_drv_active(ha);
2424 qla82xx_idc_unlock(ha);
2425 iounmap((device_reg_t __iomem *)ha->nx_pcibase);
2426 if (!ql2xdbwr)
2427 iounmap((device_reg_t __iomem *)ha->nxdb_wr_ptr);
2428 } else {
2429 if (ha->iobase)
2430 iounmap(ha->iobase);
2431 }
e315cd28
AC		 2432 pci_release_selected_regions(ha->pdev, ha->bars);
2433 kfree(ha);
2434 ha = NULL;
1da177e4 2435
a1541d5a 2436probe_out:
e315cd28 2437 pci_disable_device(pdev);
a1541d5a 2438 return ret;
1da177e4 2439}
1da177e4 2440
e30d1756
MI		 2441static void
2442qla2x00_shutdown(struct pci_dev *pdev)
2443{
2444 scsi_qla_host_t *vha;
2445 struct qla_hw_data *ha;
2446
2447 vha = pci_get_drvdata(pdev);
2448 ha = vha->hw;
2449
2450 /* Turn-off FCE trace */
2451 if (ha->flags.fce_enabled) {
2452 qla2x00_disable_fce_trace(vha, NULL, NULL);
2453 ha->flags.fce_enabled = 0;
2454 }
2455
2456 /* Turn-off EFT trace */
2457 if (ha->eft)
2458 qla2x00_disable_eft_trace(vha);
2459
2460 /* Stop currently executing firmware. */
2461 qla2x00_try_to_stop_firmware(vha);
2462
2463 /* Turn adapter off line */
2464 vha->flags.online = 0;
2465
2466 /* turn-off interrupts on the card */
2467 if (ha->interrupts_on) {
2468 vha->flags.init_done = 0;
2469 ha->isp_ops->disable_intrs(ha);
2470 }
2471
2472 qla2x00_free_irqs(vha);
2473
2474 qla2x00_free_fw_dump(ha);
2475}
2476
4c993f76 2477static void
7ee61397 2478qla2x00_remove_one(struct pci_dev *pdev)
1da177e4 2479{
feafb7b1 2480 scsi_qla_host_t *base_vha, *vha;
e315cd28 2481 struct qla_hw_data *ha;
feafb7b1 2482 unsigned long flags;
e315cd28
AC		 2483
2484 base_vha = pci_get_drvdata(pdev);
2485 ha = base_vha->hw;
2486
43ebf16d
AE		 2487 mutex_lock(&ha->vport_lock);
2488 while (ha->cur_vport_count) {
2489 struct Scsi_Host *scsi_host;
feafb7b1 2490
43ebf16d 2491 spin_lock_irqsave(&ha->vport_slock, flags);
feafb7b1 2492
43ebf16d
AE		 2493 BUG_ON(base_vha->list.next == &ha->vp_list);
2494 /* This assumes first entry in ha->vp_list is always base vha */
2495 vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list);
2496 scsi_host = scsi_host_get(vha->host);
feafb7b1 2497
43ebf16d
AE		 2498 spin_unlock_irqrestore(&ha->vport_slock, flags);
2499 mutex_unlock(&ha->vport_lock);
2500
2501 fc_vport_terminate(vha->fc_vport);
2502 scsi_host_put(vha->host);
feafb7b1 2503
43ebf16d 2504 mutex_lock(&ha->vport_lock);
e315cd28 2505 }
43ebf16d 2506 mutex_unlock(&ha->vport_lock);
1da177e4 2507
e315cd28 2508 set_bit(UNLOADING, &base_vha->dpc_flags);
1da177e4 2509
b9978769
AV		 2510 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
2511
e315cd28 2512 qla2x00_dfs_remove(base_vha);
c795c1e4 2513
e315cd28 2514 qla84xx_put_chip(base_vha);
c795c1e4 2515
b9978769
AV		 2516 /* Disable timer */
2517 if (base_vha->timer_active)
2518 qla2x00_stop_timer(base_vha);
2519
2520 base_vha->flags.online = 0;
2521
68ca949c
AC		 2522 /* Flush the work queue and remove it */
2523 if (ha->wq) {
2524 flush_workqueue(ha->wq);
2525 destroy_workqueue(ha->wq);
2526 ha->wq = NULL;
2527 }
2528
b9978769
AV		 2529 /* Kill the kernel thread for this host */
2530 if (ha->dpc_thread) {
2531 struct task_struct *t = ha->dpc_thread;
2532
2533 /*
2534 * qla2xxx_wake_dpc checks for ->dpc_thread
2535 * so we need to zero it out.
2536 */
2537 ha->dpc_thread = NULL;
2538 kthread_stop(t);
2539 }
2540
e315cd28 2541 qla2x00_free_sysfs_attr(base_vha);
df613b96 2542
e315cd28 2543 fc_remove_host(base_vha->host);
4d4df193 2544
e315cd28 2545 scsi_remove_host(base_vha->host);
1da177e4 2546
e315cd28 2547 qla2x00_free_device(base_vha);
bdf79621 2548
e315cd28 2549 scsi_host_put(base_vha->host);
1da177e4 2550
a9083016 2551 if (IS_QLA82XX(ha)) {
b963752f
GM		 2552 qla82xx_idc_lock(ha);
2553 qla82xx_clear_drv_active(ha);
2554 qla82xx_idc_unlock(ha);
2555
a9083016
GM		 2556 iounmap((device_reg_t __iomem *)ha->nx_pcibase);
2557 if (!ql2xdbwr)
2558 iounmap((device_reg_t __iomem *)ha->nxdb_wr_ptr);
2559 } else {
2560 if (ha->iobase)
2561 iounmap(ha->iobase);
1da177e4 2562
a9083016
GM		 2563 if (ha->mqiobase)
2564 iounmap(ha->mqiobase);
2565 }
73208dfd 2566
e315cd28
AC		 2567 pci_release_selected_regions(ha->pdev, ha->bars);
2568 kfree(ha);
2569 ha = NULL;
1da177e4 2570
90a86fc0
JC		 2571 pci_disable_pcie_error_reporting(pdev);
2572
665db93b 2573 pci_disable_device(pdev);
1da177e4
LT		 2574 pci_set_drvdata(pdev, NULL);
2575}
1da177e4
LT		 2576
2577static void
e315cd28 2578qla2x00_free_device(scsi_qla_host_t *vha)
1da177e4 2579{
e315cd28 2580 struct qla_hw_data *ha = vha->hw;
1da177e4 2581
85880801
AV		 2582 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
2583
2584 /* Disable timer */
2585 if (vha->timer_active)
2586 qla2x00_stop_timer(vha);
2587
2588 /* Kill the kernel thread for this host */
2589 if (ha->dpc_thread) {
2590 struct task_struct *t = ha->dpc_thread;
2591
2592 /*
2593 * qla2xxx_wake_dpc checks for ->dpc_thread
2594 * so we need to zero it out.
2595 */
2596 ha->dpc_thread = NULL;
2597 kthread_stop(t);
2598 }
2599
2afa19a9
AC		 2600 qla25xx_delete_queues(vha);
2601
df613b96 2602 if (ha->flags.fce_enabled)
e315cd28 2603 qla2x00_disable_fce_trace(vha, NULL, NULL);
df613b96 2604
a7a167bf 2605 if (ha->eft)
e315cd28 2606 qla2x00_disable_eft_trace(vha);
a7a167bf 2607
f6ef3b18 2608 /* Stop currently executing firmware. */
e315cd28 2609 qla2x00_try_to_stop_firmware(vha);
1da177e4 2610
85880801
AV		 2611 vha->flags.online = 0;
2612
f6ef3b18 2613 /* turn-off interrupts on the card */
a9083016
GM		 2614 if (ha->interrupts_on) {
2615 vha->flags.init_done = 0;
fd34f556 2616 ha->isp_ops->disable_intrs(ha);
a9083016 2617 }
f6ef3b18 2618
e315cd28 2619 qla2x00_free_irqs(vha);
1da177e4 2620
8867048b
CD		 2621 qla2x00_free_fcports(vha);
2622
e315cd28 2623 qla2x00_mem_free(ha);
73208dfd 2624
08de2844
GM		 2625 qla82xx_md_free(vha);
2626
73208dfd 2627 qla2x00_free_queues(ha);
1da177e4
LT		 2628}
2629
8867048b
CD		 2630void qla2x00_free_fcports(struct scsi_qla_host *vha)
2631{
2632 fc_port_t *fcport, *tfcport;
2633
2634 list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list) {
2635 list_del(&fcport->list);
2636 kfree(fcport);
2637 fcport = NULL;
2638 }
2639}
2640
d97994dc 2641static inline void
e315cd28 2642qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport,
d97994dc 2643 int defer)
2644{
d97994dc 2645 struct fc_rport *rport;
67becc00 2646 scsi_qla_host_t *base_vha;
044d78e1 2647 unsigned long flags;
d97994dc 2648
2649 if (!fcport->rport)
2650 return;
2651
2652 rport = fcport->rport;
2653 if (defer) {
67becc00 2654 base_vha = pci_get_drvdata(vha->hw->pdev);
044d78e1 2655 spin_lock_irqsave(vha->host->host_lock, flags);
d97994dc 2656 fcport->drport = rport;
044d78e1 2657 spin_unlock_irqrestore(vha->host->host_lock, flags);
67becc00
AV		 2658 set_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags);
2659 qla2xxx_wake_dpc(base_vha);
5f3a9a20 2660 } else
d97994dc 2661 fc_remote_port_delete(rport);
d97994dc 2662}
2663
1da177e4
LT		 2664/*
2665 * qla2x00_mark_device_lost Updates fcport state when device goes offline.
2666 *
2667 * Input: ha = adapter block pointer. fcport = port structure pointer.
2668 *
2669 * Return: None.
2670 *
2671 * Context:
2672 */
e315cd28 2673void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport,
d97994dc 2674 int do_login, int defer)
1da177e4 2675{
2c3dfe3f 2676 if (atomic_read(&fcport->state) == FCS_ONLINE &&
e315cd28 2677 vha->vp_idx == fcport->vp_idx) {
ec426e10 2678 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
e315cd28
AC		 2679 qla2x00_schedule_rport_del(vha, fcport, defer);
2680 }
fa2a1ce5 2681 /*
1da177e4
LT		 2682 * We may need to retry the login, so don't change the state of the
2683 * port but do the retries.
2684 */
2685 if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD)
ec426e10 2686 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
1da177e4
LT		 2687
2688 if (!do_login)
2689 return;
2690
2691 if (fcport->login_retry == 0) {
e315cd28
AC		 2692 fcport->login_retry = vha->hw->login_retry_count;
2693 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
1da177e4 2694
7c3df132
SK		 2695 ql_dbg(ql_dbg_disc, vha, 0x2067,
2696 "Port login retry "
1da177e4 2697 "%02x%02x%02x%02x%02x%02x%02x%02x, "
7c3df132
SK		 2698 "id = 0x%04x retry cnt=%d.\n",
2699 fcport->port_name[0], fcport->port_name[1],
2700 fcport->port_name[2], fcport->port_name[3],
2701 fcport->port_name[4], fcport->port_name[5],
2702 fcport->port_name[6], fcport->port_name[7],
2703 fcport->loop_id, fcport->login_retry);
1da177e4
LT		 2704 }
2705}
2706
2707/*
2708 * qla2x00_mark_all_devices_lost
2709 * Updates fcport state when device goes offline.
2710 *
2711 * Input:
2712 * ha = adapter block pointer.
2713 * fcport = port structure pointer.
2714 *
2715 * Return:
2716 * None.
2717 *
2718 * Context:
2719 */
2720void
e315cd28 2721qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha, int defer)
1da177e4
LT		 2722{
2723 fc_port_t *fcport;
2724
e315cd28 2725 list_for_each_entry(fcport, &vha->vp_fcports, list) {
0d6e61bc 2726 if (vha->vp_idx != 0 && vha->vp_idx != fcport->vp_idx)
1da177e4 2727 continue;
0d6e61bc 2728
1da177e4
LT		 2729 /*
2730 * No point in marking the device as lost, if the device is
2731 * already DEAD.
2732 */
2733 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD)
2734 continue;
e315cd28 2735 if (atomic_read(&fcport->state) == FCS_ONLINE) {
ec426e10 2736 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
0d6e61bc
AV		 2737 if (defer)
2738 qla2x00_schedule_rport_del(vha, fcport, defer);
2739 else if (vha->vp_idx == fcport->vp_idx)
2740 qla2x00_schedule_rport_del(vha, fcport, defer);
2741 }
1da177e4
LT		 2742 }
2743}
2744
2745/*
2746* qla2x00_mem_alloc
2747* Allocates adapter memory.
2748*
2749* Returns:
2750* 0 = success.
e8711085 2751* !0 = failure.
1da177e4 2752*/
e8711085 2753static int
73208dfd
AC		 2754qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len,
2755 struct req_que **req, struct rsp_que **rsp)
1da177e4
LT		 2756{
2757 char name[16];
1da177e4 2758
e8711085 2759 ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size,
e315cd28 2760 &ha->init_cb_dma, GFP_KERNEL);
e8711085 2761 if (!ha->init_cb)
e315cd28 2762 goto fail;
e8711085 2763
e315cd28
AC		 2764 ha->gid_list = dma_alloc_coherent(&ha->pdev->dev, GID_LIST_SIZE,
2765 &ha->gid_list_dma, GFP_KERNEL);
2766 if (!ha->gid_list)
e8711085 2767 goto fail_free_init_cb;
1da177e4 2768
e8711085
AV		 2769 ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep);
2770 if (!ha->srb_mempool)
e315cd28 2771 goto fail_free_gid_list;
e8711085 2772
a9083016
GM		 2773 if (IS_QLA82XX(ha)) {
2774 /* Allocate cache for CT6 Ctx. */
2775 if (!ctx_cachep) {
2776 ctx_cachep = kmem_cache_create("qla2xxx_ctx",
2777 sizeof(struct ct6_dsd), 0,
2778 SLAB_HWCACHE_ALIGN, NULL);
2779 if (!ctx_cachep)
2780 goto fail_free_gid_list;
2781 }
2782 ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ,
2783 ctx_cachep);
2784 if (!ha->ctx_mempool)
2785 goto fail_free_srb_mempool;
7c3df132
SK		 2786 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021,
2787 "ctx_cachep=%p ctx_mempool=%p.\n",
2788 ctx_cachep, ha->ctx_mempool);
a9083016
GM		 2789 }
2790
e8711085
AV		 2791 /* Get memory for cached NVRAM */
2792 ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL);
2793 if (!ha->nvram)
a9083016 2794 goto fail_free_ctx_mempool;
e8711085 2795
e315cd28
AC		 2796 snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME,
2797 ha->pdev->device);
2798 ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev,
2799 DMA_POOL_SIZE, 8, 0);
2800 if (!ha->s_dma_pool)
2801 goto fail_free_nvram;
2802
7c3df132
SK		 2803 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022,
2804 "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n",
2805 ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool);
2806
bad75002 2807 if (IS_QLA82XX(ha) || ql2xenabledif) {
a9083016
GM		 2808 ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev,
2809 DSD_LIST_DMA_POOL_SIZE, 8, 0);
2810 if (!ha->dl_dma_pool) {
7c3df132
SK		 2811 ql_log_pci(ql_log_fatal, ha->pdev, 0x0023,
2812 "Failed to allocate memory for dl_dma_pool.\n");
a9083016
GM		 2813 goto fail_s_dma_pool;
2814 }
2815
2816 ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev,
2817 FCP_CMND_DMA_POOL_SIZE, 8, 0);
2818 if (!ha->fcp_cmnd_dma_pool) {
7c3df132
SK		 2819 ql_log_pci(ql_log_fatal, ha->pdev, 0x0024,
2820 "Failed to allocate memory for fcp_cmnd_dma_pool.\n");
a9083016
GM		 2821 goto fail_dl_dma_pool;
2822 }
7c3df132
SK		 2823 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025,
2824 "dl_dma_pool=%p fcp_cmnd_dma_pool=%p.\n",
2825 ha->dl_dma_pool, ha->fcp_cmnd_dma_pool);
a9083016
GM		 2826 }
2827
e8711085
AV		 2828 /* Allocate memory for SNS commands */
2829 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
e315cd28 2830 /* Get consistent memory allocated for SNS commands */
e8711085 2831 ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev,
e315cd28 2832 sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL);
e8711085 2833 if (!ha->sns_cmd)
e315cd28 2834 goto fail_dma_pool;
7c3df132 2835 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026,
d8424f68 2836 "sns_cmd: %p.\n", ha->sns_cmd);
e8711085 2837 } else {
e315cd28 2838 /* Get consistent memory allocated for MS IOCB */
e8711085 2839 ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
e315cd28 2840 &ha->ms_iocb_dma);
e8711085 2841 if (!ha->ms_iocb)
e315cd28
AC		 2842 goto fail_dma_pool;
2843 /* Get consistent memory allocated for CT SNS commands */
e8711085 2844 ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev,
e315cd28 2845 sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL);
e8711085
AV		 2846 if (!ha->ct_sns)
2847 goto fail_free_ms_iocb;
7c3df132
SK		 2848 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027,
2849 "ms_iocb=%p ct_sns=%p.\n",
2850 ha->ms_iocb, ha->ct_sns);
1da177e4
LT		 2851 }
2852
e315cd28 2853 /* Allocate memory for request ring */
73208dfd
AC		 2854 *req = kzalloc(sizeof(struct req_que), GFP_KERNEL);
2855 if (!*req) {
7c3df132
SK		 2856 ql_log_pci(ql_log_fatal, ha->pdev, 0x0028,
2857 "Failed to allocate memory for req.\n");
e315cd28
AC		 2858 goto fail_req;
2859 }
73208dfd
AC		 2860 (*req)->length = req_len;
2861 (*req)->ring = dma_alloc_coherent(&ha->pdev->dev,
2862 ((*req)->length + 1) * sizeof(request_t),
2863 &(*req)->dma, GFP_KERNEL);
2864 if (!(*req)->ring) {
7c3df132
SK		 2865 ql_log_pci(ql_log_fatal, ha->pdev, 0x0029,
2866 "Failed to allocate memory for req_ring.\n");
e315cd28
AC		 2867 goto fail_req_ring;
2868 }
2869 /* Allocate memory for response ring */
73208dfd
AC		 2870 *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL);
2871 if (!*rsp) {
7c3df132
SK		 2872 ql_log_pci(ql_log_fatal, ha->pdev, 0x002a,
2873 "Failed to allocate memory for rsp.\n");
e315cd28
AC		 2874 goto fail_rsp;
2875 }
73208dfd
AC		 2876 (*rsp)->hw = ha;
2877 (*rsp)->length = rsp_len;
2878 (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev,
2879 ((*rsp)->length + 1) * sizeof(response_t),
2880 &(*rsp)->dma, GFP_KERNEL);
2881 if (!(*rsp)->ring) {
7c3df132
SK		 2882 ql_log_pci(ql_log_fatal, ha->pdev, 0x002b,
2883 "Failed to allocate memory for rsp_ring.\n");
e315cd28
AC		 2884 goto fail_rsp_ring;
2885 }
73208dfd
AC		 2886 (*req)->rsp = *rsp;
2887 (*rsp)->req = *req;
7c3df132
SK		 2888 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c,
2889 "req=%p req->length=%d req->ring=%p rsp=%p "
2890 "rsp->length=%d rsp->ring=%p.\n",
2891 *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length,
2892 (*rsp)->ring);
73208dfd
AC		 2893 /* Allocate memory for NVRAM data for vports */
2894 if (ha->nvram_npiv_size) {
2895 ha->npiv_info = kzalloc(sizeof(struct qla_npiv_entry) *
7c3df132 2896 ha->nvram_npiv_size, GFP_KERNEL);
73208dfd 2897 if (!ha->npiv_info) {
7c3df132
SK		 2898 ql_log_pci(ql_log_fatal, ha->pdev, 0x002d,
2899 "Failed to allocate memory for npiv_info.\n");
73208dfd
AC		 2900 goto fail_npiv_info;
2901 }
2902 } else
2903 ha->npiv_info = NULL;
e8711085 2904
b64b0e8f 2905 /* Get consistent memory allocated for EX-INIT-CB. */
a9083016 2906 if (IS_QLA8XXX_TYPE(ha)) {
b64b0e8f
AV		 2907 ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
2908 &ha->ex_init_cb_dma);
2909 if (!ha->ex_init_cb)
2910 goto fail_ex_init_cb;
7c3df132
SK		 2911 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e,
2912 "ex_init_cb=%p.\n", ha->ex_init_cb);
b64b0e8f
AV		 2913 }
2914
a9083016
GM		 2915 INIT_LIST_HEAD(&ha->gbl_dsd_list);
2916
5ff1d584
AV		 2917 /* Get consistent memory allocated for Async Port-Database. */
2918 if (!IS_FWI2_CAPABLE(ha)) {
2919 ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
2920 &ha->async_pd_dma);
2921 if (!ha->async_pd)
2922 goto fail_async_pd;
7c3df132
SK		 2923 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f,
2924 "async_pd=%p.\n", ha->async_pd);
5ff1d584
AV		 2925 }
2926
e315cd28
AC		 2927 INIT_LIST_HEAD(&ha->vp_list);
2928 return 1;
2929
5ff1d584
AV		 2930fail_async_pd:
2931 dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma);
b64b0e8f
AV		 2932fail_ex_init_cb:
2933 kfree(ha->npiv_info);
73208dfd
AC		 2934fail_npiv_info:
2935 dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) *
2936 sizeof(response_t), (*rsp)->ring, (*rsp)->dma);
2937 (*rsp)->ring = NULL;
2938 (*rsp)->dma = 0;
e315cd28 2939fail_rsp_ring:
73208dfd 2940 kfree(*rsp);
e315cd28 2941fail_rsp:
73208dfd
AC		 2942 dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) *
2943 sizeof(request_t), (*req)->ring, (*req)->dma);
2944 (*req)->ring = NULL;
2945 (*req)->dma = 0;
e315cd28 2946fail_req_ring:
73208dfd 2947 kfree(*req);
e315cd28
AC		 2948fail_req:
2949 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
2950 ha->ct_sns, ha->ct_sns_dma);
2951 ha->ct_sns = NULL;
2952 ha->ct_sns_dma = 0;
e8711085
AV		 2953fail_free_ms_iocb:
2954 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
2955 ha->ms_iocb = NULL;
2956 ha->ms_iocb_dma = 0;
e315cd28 2957fail_dma_pool:
bad75002 2958 if (IS_QLA82XX(ha) || ql2xenabledif) {
a9083016
GM		 2959 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
2960 ha->fcp_cmnd_dma_pool = NULL;
2961 }
2962fail_dl_dma_pool:
bad75002 2963 if (IS_QLA82XX(ha) || ql2xenabledif) {
a9083016
GM		 2964 dma_pool_destroy(ha->dl_dma_pool);
2965 ha->dl_dma_pool = NULL;
2966 }
2967fail_s_dma_pool:
e315cd28
AC		 2968 dma_pool_destroy(ha->s_dma_pool);
2969 ha->s_dma_pool = NULL;
e8711085
AV		 2970fail_free_nvram:
2971 kfree(ha->nvram);
2972 ha->nvram = NULL;
a9083016
GM		 2973fail_free_ctx_mempool:
2974 mempool_destroy(ha->ctx_mempool);
2975 ha->ctx_mempool = NULL;
e8711085
AV		 2976fail_free_srb_mempool:
2977 mempool_destroy(ha->srb_mempool);
2978 ha->srb_mempool = NULL;
e8711085
AV		 2979fail_free_gid_list:
2980 dma_free_coherent(&ha->pdev->dev, GID_LIST_SIZE, ha->gid_list,
e315cd28 2981 ha->gid_list_dma);
e8711085
AV		 2982 ha->gid_list = NULL;
2983 ha->gid_list_dma = 0;
e315cd28
AC		 2984fail_free_init_cb:
2985 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb,
2986 ha->init_cb_dma);
2987 ha->init_cb = NULL;
2988 ha->init_cb_dma = 0;
e8711085 2989fail:
7c3df132
SK		 2990 ql_log(ql_log_fatal, NULL, 0x0030,
2991 "Memory allocation failure.\n");
e8711085 2992 return -ENOMEM;
1da177e4
LT		 2993}
2994
2995/*
e30d1756
MI		 2996* qla2x00_free_fw_dump
2997* Frees fw dump stuff.
1da177e4
LT		 2998*
2999* Input:
e30d1756 3000* ha = adapter block pointer.
1da177e4 3001*/
a824ebb3 3002static void
e30d1756 3003qla2x00_free_fw_dump(struct qla_hw_data *ha)
1da177e4 3004{
df613b96
AV		 3005 if (ha->fce)
3006 dma_free_coherent(&ha->pdev->dev, FCE_SIZE, ha->fce,
e30d1756 3007 ha->fce_dma);
df613b96 3008
a7a167bf
AV		 3009 if (ha->fw_dump) {
3010 if (ha->eft)
3011 dma_free_coherent(&ha->pdev->dev,
e30d1756 3012 ntohl(ha->fw_dump->eft_size), ha->eft, ha->eft_dma);
a7a167bf
AV		 3013 vfree(ha->fw_dump);
3014 }
e30d1756
MI		 3015 ha->fce = NULL;
3016 ha->fce_dma = 0;
3017 ha->eft = NULL;
3018 ha->eft_dma = 0;
3019 ha->fw_dump = NULL;
3020 ha->fw_dumped = 0;
3021 ha->fw_dump_reading = 0;
3022}
3023
3024/*
3025* qla2x00_mem_free
3026* Frees all adapter allocated memory.
3027*
3028* Input:
3029* ha = adapter block pointer.
3030*/
3031static void
3032qla2x00_mem_free(struct qla_hw_data *ha)
3033{
3034 qla2x00_free_fw_dump(ha);
3035
3036 if (ha->srb_mempool)
3037 mempool_destroy(ha->srb_mempool);
a7a167bf 3038
11bbc1d8
AV		 3039 if (ha->dcbx_tlv)
3040 dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE,
3041 ha->dcbx_tlv, ha->dcbx_tlv_dma);
3042
ce0423f4
AV		 3043 if (ha->xgmac_data)
3044 dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE,
3045 ha->xgmac_data, ha->xgmac_data_dma);
3046
1da177e4
LT		 3047 if (ha->sns_cmd)
3048 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
e315cd28 3049 ha->sns_cmd, ha->sns_cmd_dma);
1da177e4
LT		 3050
3051 if (ha->ct_sns)
3052 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
e315cd28 3053 ha->ct_sns, ha->ct_sns_dma);
1da177e4 3054
88729e53
AV		 3055 if (ha->sfp_data)
3056 dma_pool_free(ha->s_dma_pool, ha->sfp_data, ha->sfp_data_dma);
3057
ad0ecd61
JC		 3058 if (ha->edc_data)
3059 dma_pool_free(ha->s_dma_pool, ha->edc_data, ha->edc_data_dma);
3060
1da177e4
LT		 3061 if (ha->ms_iocb)
3062 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
3063
b64b0e8f 3064 if (ha->ex_init_cb)
a9083016
GM		 3065 dma_pool_free(ha->s_dma_pool,
3066 ha->ex_init_cb, ha->ex_init_cb_dma);
b64b0e8f 3067
5ff1d584
AV		 3068 if (ha->async_pd)
3069 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
3070
1da177e4
LT		 3071 if (ha->s_dma_pool)
3072 dma_pool_destroy(ha->s_dma_pool);
3073
1da177e4
LT		 3074 if (ha->gid_list)
3075 dma_free_coherent(&ha->pdev->dev, GID_LIST_SIZE, ha->gid_list,
e315cd28 3076 ha->gid_list_dma);
1da177e4 3077
a9083016
GM		 3078 if (IS_QLA82XX(ha)) {
3079 if (!list_empty(&ha->gbl_dsd_list)) {
3080 struct dsd_dma *dsd_ptr, *tdsd_ptr;
3081
3082 /* clean up allocated prev pool */
3083 list_for_each_entry_safe(dsd_ptr,
3084 tdsd_ptr, &ha->gbl_dsd_list, list) {
3085 dma_pool_free(ha->dl_dma_pool,
3086 dsd_ptr->dsd_addr, dsd_ptr->dsd_list_dma);
3087 list_del(&dsd_ptr->list);
3088 kfree(dsd_ptr);
3089 }
3090 }
3091 }
3092
3093 if (ha->dl_dma_pool)
3094 dma_pool_destroy(ha->dl_dma_pool);
3095
3096 if (ha->fcp_cmnd_dma_pool)
3097 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
3098
3099 if (ha->ctx_mempool)
3100 mempool_destroy(ha->ctx_mempool);
3101
e315cd28
AC		 3102 if (ha->init_cb)
3103 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size,
a9083016 3104 ha->init_cb, ha->init_cb_dma);
e315cd28
AC		 3105 vfree(ha->optrom_buffer);
3106 kfree(ha->nvram);
73208dfd 3107 kfree(ha->npiv_info);
1da177e4 3108
e8711085 3109 ha->srb_mempool = NULL;
a9083016 3110 ha->ctx_mempool = NULL;
1da177e4
LT		 3111 ha->sns_cmd = NULL;
3112 ha->sns_cmd_dma = 0;
3113 ha->ct_sns = NULL;
3114 ha->ct_sns_dma = 0;
3115 ha->ms_iocb = NULL;
3116 ha->ms_iocb_dma = 0;
1da177e4
LT		 3117 ha->init_cb = NULL;
3118 ha->init_cb_dma = 0;
b64b0e8f
AV		 3119 ha->ex_init_cb = NULL;
3120 ha->ex_init_cb_dma = 0;
5ff1d584
AV		 3121 ha->async_pd = NULL;
3122 ha->async_pd_dma = 0;
1da177e4
LT		 3123
3124 ha->s_dma_pool = NULL;
a9083016
GM		 3125 ha->dl_dma_pool = NULL;
3126 ha->fcp_cmnd_dma_pool = NULL;
1da177e4 3127
1da177e4
LT		 3128 ha->gid_list = NULL;
3129 ha->gid_list_dma = 0;
e315cd28 3130}
1da177e4 3131
e315cd28
AC		 3132struct scsi_qla_host *qla2x00_create_host(struct scsi_host_template *sht,
3133 struct qla_hw_data *ha)
3134{
3135 struct Scsi_Host *host;
3136 struct scsi_qla_host *vha = NULL;
854165f4 3137
e315cd28
AC		 3138 host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t));
3139 if (host == NULL) {
7c3df132
SK		 3140 ql_log_pci(ql_log_fatal, ha->pdev, 0x0107,
3141 "Failed to allocate host from the scsi layer, aborting.\n");
e315cd28
AC		 3142 goto fail;
3143 }
3144
3145 /* Clear our data area */
3146 vha = shost_priv(host);
3147 memset(vha, 0, sizeof(scsi_qla_host_t));
3148
3149 vha->host = host;
3150 vha->host_no = host->host_no;
3151 vha->hw = ha;
3152
3153 INIT_LIST_HEAD(&vha->vp_fcports);
3154 INIT_LIST_HEAD(&vha->work_list);
3155 INIT_LIST_HEAD(&vha->list);
3156
f999f4c1
AV		 3157 spin_lock_init(&vha->work_lock);
3158
e315cd28 3159 sprintf(vha->host_str, "%s_%ld", QLA2XXX_DRIVER_NAME, vha->host_no);
7c3df132
SK		 3160 ql_dbg(ql_dbg_init, vha, 0x0041,
3161 "Allocated the host=%p hw=%p vha=%p dev_name=%s",
3162 vha->host, vha->hw, vha,
3163 dev_name(&(ha->pdev->dev)));
3164
e315cd28
AC		 3165 return vha;
3166
3167fail:
3168 return vha;
1da177e4
LT		 3169}
3170
01ef66bb 3171static struct qla_work_evt *
f999f4c1 3172qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type)
0971de7f
AV		 3173{
3174 struct qla_work_evt *e;
feafb7b1
AE		 3175 uint8_t bail;
3176
3177 QLA_VHA_MARK_BUSY(vha, bail);
3178 if (bail)
3179 return NULL;
0971de7f 3180
f999f4c1 3181 e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC);
feafb7b1
AE		 3182 if (!e) {
3183 QLA_VHA_MARK_NOT_BUSY(vha);
0971de7f 3184 return NULL;
feafb7b1 3185 }
0971de7f
AV		 3186
3187 INIT_LIST_HEAD(&e->list);
3188 e->type = type;
3189 e->flags = QLA_EVT_FLAG_FREE;
3190 return e;
3191}
3192
01ef66bb 3193static int
f999f4c1 3194qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e)
0971de7f 3195{
f999f4c1 3196 unsigned long flags;
0971de7f 3197
f999f4c1 3198 spin_lock_irqsave(&vha->work_lock, flags);
e315cd28 3199 list_add_tail(&e->list, &vha->work_list);
f999f4c1 3200 spin_unlock_irqrestore(&vha->work_lock, flags);
e315cd28 3201 qla2xxx_wake_dpc(vha);
f999f4c1 3202
0971de7f
AV		 3203 return QLA_SUCCESS;
3204}
3205
3206int
e315cd28 3207qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code,
0971de7f
AV		 3208 u32 data)
3209{
3210 struct qla_work_evt *e;
3211
f999f4c1 3212 e = qla2x00_alloc_work(vha, QLA_EVT_AEN);
0971de7f
AV		 3213 if (!e)
3214 return QLA_FUNCTION_FAILED;
3215
3216 e->u.aen.code = code;
3217 e->u.aen.data = data;
f999f4c1 3218 return qla2x00_post_work(vha, e);
0971de7f
AV		 3219}
3220
8a659571
AV		 3221int
3222qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb)
3223{
3224 struct qla_work_evt *e;
3225
f999f4c1 3226 e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK);
8a659571
AV		 3227 if (!e)
3228 return QLA_FUNCTION_FAILED;
3229
3230 memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t));
f999f4c1 3231 return qla2x00_post_work(vha, e);
8a659571
AV		 3232}
3233
ac280b67
AV		 3234#define qla2x00_post_async_work(name, type) \
3235int qla2x00_post_async_##name##_work( \
3236 struct scsi_qla_host *vha, \
3237 fc_port_t *fcport, uint16_t *data) \
3238{ \
3239 struct qla_work_evt *e; \
3240 \
3241 e = qla2x00_alloc_work(vha, type); \
3242 if (!e) \
3243 return QLA_FUNCTION_FAILED; \
3244 \
3245 e->u.logio.fcport = fcport; \
3246 if (data) { \
3247 e->u.logio.data[0] = data[0]; \
3248 e->u.logio.data[1] = data[1]; \
3249 } \
3250 return qla2x00_post_work(vha, e); \
3251}
3252
3253qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN);
3254qla2x00_post_async_work(login_done, QLA_EVT_ASYNC_LOGIN_DONE);
3255qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT);
3256qla2x00_post_async_work(logout_done, QLA_EVT_ASYNC_LOGOUT_DONE);
5ff1d584
AV		 3257qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC);
3258qla2x00_post_async_work(adisc_done, QLA_EVT_ASYNC_ADISC_DONE);
ac280b67 3259
3420d36c
AV		 3260int
3261qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code)
3262{
3263 struct qla_work_evt *e;
3264
3265 e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT);
3266 if (!e)
3267 return QLA_FUNCTION_FAILED;
3268
3269 e->u.uevent.code = code;
3270 return qla2x00_post_work(vha, e);
3271}
3272
3273static void
3274qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code)
3275{
3276 char event_string[40];
3277 char *envp[] = { event_string, NULL };
3278
3279 switch (code) {
3280 case QLA_UEVENT_CODE_FW_DUMP:
3281 snprintf(event_string, sizeof(event_string), "FW_DUMP=%ld",
3282 vha->host_no);
3283 break;
3284 default:
3285 /* do nothing */
3286 break;
3287 }
3288 kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp);
3289}
3290
ac280b67 3291void
e315cd28 3292qla2x00_do_work(struct scsi_qla_host *vha)
0971de7f 3293{
f999f4c1
AV		 3294 struct qla_work_evt *e, *tmp;
3295 unsigned long flags;
3296 LIST_HEAD(work);
0971de7f 3297
f999f4c1
AV		 3298 spin_lock_irqsave(&vha->work_lock, flags);
3299 list_splice_init(&vha->work_list, &work);
3300 spin_unlock_irqrestore(&vha->work_lock, flags);
3301
3302 list_for_each_entry_safe(e, tmp, &work, list) {
0971de7f 3303 list_del_init(&e->list);
0971de7f
AV		 3304
3305 switch (e->type) {
3306 case QLA_EVT_AEN:
e315cd28 3307 fc_host_post_event(vha->host, fc_get_event_number(),
0971de7f
AV		 3308 e->u.aen.code, e->u.aen.data);
3309 break;
8a659571
AV		 3310 case QLA_EVT_IDC_ACK:
3311 qla81xx_idc_ack(vha, e->u.idc_ack.mb);
3312 break;
ac280b67
AV		 3313 case QLA_EVT_ASYNC_LOGIN:
3314 qla2x00_async_login(vha, e->u.logio.fcport,
3315 e->u.logio.data);
3316 break;
3317 case QLA_EVT_ASYNC_LOGIN_DONE:
3318 qla2x00_async_login_done(vha, e->u.logio.fcport,
3319 e->u.logio.data);
3320 break;
3321 case QLA_EVT_ASYNC_LOGOUT:
3322 qla2x00_async_logout(vha, e->u.logio.fcport);
3323 break;
3324 case QLA_EVT_ASYNC_LOGOUT_DONE:
3325 qla2x00_async_logout_done(vha, e->u.logio.fcport,
3326 e->u.logio.data);
3327 break;
5ff1d584
AV		 3328 case QLA_EVT_ASYNC_ADISC:
3329 qla2x00_async_adisc(vha, e->u.logio.fcport,
3330 e->u.logio.data);
3331 break;
3332 case QLA_EVT_ASYNC_ADISC_DONE:
3333 qla2x00_async_adisc_done(vha, e->u.logio.fcport,
3334 e->u.logio.data);
3335 break;
3420d36c
AV		 3336 case QLA_EVT_UEVENT:
3337 qla2x00_uevent_emit(vha, e->u.uevent.code);
3338 break;
0971de7f
AV		 3339 }
3340 if (e->flags & QLA_EVT_FLAG_FREE)
3341 kfree(e);
feafb7b1
AE		 3342
3343 /* For each work completed decrement vha ref count */
3344 QLA_VHA_MARK_NOT_BUSY(vha);
e315cd28 3345 }
e315cd28 3346}
f999f4c1 3347
e315cd28
AC		 3348/* Relogins all the fcports of a vport
3349 * Context: dpc thread
3350 */
3351void qla2x00_relogin(struct scsi_qla_host *vha)
3352{
3353 fc_port_t *fcport;
c6b2fca8 3354 int status;
e315cd28
AC		 3355 uint16_t next_loopid = 0;
3356 struct qla_hw_data *ha = vha->hw;
ac280b67 3357 uint16_t data[2];
e315cd28
AC		 3358
3359 list_for_each_entry(fcport, &vha->vp_fcports, list) {
3360 /*
3361 * If the port is not ONLINE then try to login
3362 * to it if we haven't run out of retries.
3363 */
5ff1d584
AV		 3364 if (atomic_read(&fcport->state) != FCS_ONLINE &&
3365 fcport->login_retry && !(fcport->flags & FCF_ASYNC_SENT)) {
ac280b67 3366 fcport->login_retry--;
e315cd28 3367 if (fcport->flags & FCF_FABRIC_DEVICE) {
f08b7251 3368 if (fcport->flags & FCF_FCP2_DEVICE)
e315cd28
AC		 3369 ha->isp_ops->fabric_logout(vha,
3370 fcport->loop_id,
3371 fcport->d_id.b.domain,
3372 fcport->d_id.b.area,
3373 fcport->d_id.b.al_pa);
3374
03bcfb57
JC		 3375 if (fcport->loop_id == FC_NO_LOOP_ID) {
3376 fcport->loop_id = next_loopid =
3377 ha->min_external_loopid;
3378 status = qla2x00_find_new_loop_id(
3379 vha, fcport);
3380 if (status != QLA_SUCCESS) {
3381 /* Ran out of IDs to use */
3382 break;
3383 }
3384 }
3385
ac280b67 3386 if (IS_ALOGIO_CAPABLE(ha)) {
5ff1d584 3387 fcport->flags |= FCF_ASYNC_SENT;
ac280b67
AV		 3388 data[0] = 0;
3389 data[1] = QLA_LOGIO_LOGIN_RETRIED;
3390 status = qla2x00_post_async_login_work(
3391 vha, fcport, data);
3392 if (status == QLA_SUCCESS)
3393 continue;
3394 /* Attempt a retry. */
3395 status = 1;
3396 } else
3397 status = qla2x00_fabric_login(vha,
3398 fcport, &next_loopid);
e315cd28
AC		 3399 } else
3400 status = qla2x00_local_device_login(vha,
3401 fcport);
3402
e315cd28
AC		 3403 if (status == QLA_SUCCESS) {
3404 fcport->old_loop_id = fcport->loop_id;
3405
7c3df132
SK		 3406 ql_dbg(ql_dbg_disc, vha, 0x2003,
3407 "Port login OK: logged in ID 0x%x.\n",
3408 fcport->loop_id);
e315cd28
AC		 3409
3410 qla2x00_update_fcport(vha, fcport);
3411
3412 } else if (status == 1) {
3413 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
3414 /* retry the login again */
7c3df132
SK		 3415 ql_dbg(ql_dbg_disc, vha, 0x2007,
3416 "Retrying %d login again loop_id 0x%x.\n",
3417 fcport->login_retry, fcport->loop_id);
e315cd28
AC		 3418 } else {
3419 fcport->login_retry = 0;
3420 }
3421
3422 if (fcport->login_retry == 0 && status != QLA_SUCCESS)
3423 fcport->loop_id = FC_NO_LOOP_ID;
3424 }
3425 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
3426 break;
0971de7f 3427 }
0971de7f
AV		 3428}
3429
1da177e4
LT		 3430/**************************************************************************
3431* qla2x00_do_dpc
3432* This kernel thread is a task that is schedule by the interrupt handler
3433* to perform the background processing for interrupts.
3434*
3435* Notes:
3436* This task always run in the context of a kernel thread. It
3437* is kick-off by the driver's detect code and starts up
3438* up one per adapter. It immediately goes to sleep and waits for
3439* some fibre event. When either the interrupt handler or
3440* the timer routine detects a event it will one of the task
3441* bits then wake us up.
3442**************************************************************************/
3443static int
3444qla2x00_do_dpc(void *data)
3445{
2c3dfe3f 3446 int rval;
e315cd28
AC		 3447 scsi_qla_host_t *base_vha;
3448 struct qla_hw_data *ha;
1da177e4 3449
e315cd28
AC		 3450 ha = (struct qla_hw_data *)data;
3451 base_vha = pci_get_drvdata(ha->pdev);
1da177e4 3452
1da177e4
LT		 3453 set_user_nice(current, -20);
3454
563585ec 3455 set_current_state(TASK_INTERRUPTIBLE);
39a11240 3456 while (!kthread_should_stop()) {
7c3df132
SK		 3457 ql_dbg(ql_dbg_dpc, base_vha, 0x4000,
3458 "DPC handler sleeping.\n");
1da177e4 3459
39a11240
CH		 3460 schedule();
3461 __set_current_state(TASK_RUNNING);
1da177e4 3462
7c3df132
SK		 3463 ql_dbg(ql_dbg_dpc, base_vha, 0x4001,
3464 "DPC handler waking up.\n");
3465 ql_dbg(ql_dbg_dpc, base_vha, 0x4002,
3466 "dpc_flags=0x%lx.\n", base_vha->dpc_flags);
1da177e4
LT		 3467
3468 /* Initialization not yet finished. Don't do anything yet. */
e315cd28 3469 if (!base_vha->flags.init_done)
1da177e4
LT		 3470 continue;
3471
85880801 3472 if (ha->flags.eeh_busy) {
7c3df132
SK		 3473 ql_dbg(ql_dbg_dpc, base_vha, 0x4003,
3474 "eeh_busy=%d.\n", ha->flags.eeh_busy);
85880801
AV		 3475 continue;
3476 }
3477
1da177e4
LT		 3478 ha->dpc_active = 1;
3479
1da177e4 3480 if (ha->flags.mbox_busy) {
1da177e4
LT		 3481 ha->dpc_active = 0;
3482 continue;
3483 }
3484
e315cd28 3485 qla2x00_do_work(base_vha);
0971de7f 3486
a9083016
GM		 3487 if (IS_QLA82XX(ha)) {
3488 if (test_and_clear_bit(ISP_UNRECOVERABLE,
3489 &base_vha->dpc_flags)) {
3490 qla82xx_idc_lock(ha);
3491 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
3492 QLA82XX_DEV_FAILED);
3493 qla82xx_idc_unlock(ha);
7c3df132
SK		 3494 ql_log(ql_log_info, base_vha, 0x4004,
3495 "HW State: FAILED.\n");
a9083016
GM		 3496 qla82xx_device_state_handler(base_vha);
3497 continue;
3498 }
3499
3500 if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED,
3501 &base_vha->dpc_flags)) {
3502
7c3df132
SK		 3503 ql_dbg(ql_dbg_dpc, base_vha, 0x4005,
3504 "FCoE context reset scheduled.\n");
a9083016
GM		 3505 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
3506 &base_vha->dpc_flags))) {
3507 if (qla82xx_fcoe_ctx_reset(base_vha)) {
3508 /* FCoE-ctx reset failed.
3509 * Escalate to chip-reset
3510 */
3511 set_bit(ISP_ABORT_NEEDED,
3512 &base_vha->dpc_flags);
3513 }
3514 clear_bit(ABORT_ISP_ACTIVE,
3515 &base_vha->dpc_flags);
3516 }
3517
7c3df132
SK		 3518 ql_dbg(ql_dbg_dpc, base_vha, 0x4006,
3519 "FCoE context reset end.\n");
a9083016
GM		 3520 }
3521 }
3522
e315cd28
AC		 3523 if (test_and_clear_bit(ISP_ABORT_NEEDED,
3524 &base_vha->dpc_flags)) {
1da177e4 3525
7c3df132
SK		 3526 ql_dbg(ql_dbg_dpc, base_vha, 0x4007,
3527 "ISP abort scheduled.\n");
1da177e4 3528 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
e315cd28 3529 &base_vha->dpc_flags))) {
1da177e4 3530
a9083016 3531 if (ha->isp_ops->abort_isp(base_vha)) {
1da177e4
LT		 3532 /* failed. retry later */
3533 set_bit(ISP_ABORT_NEEDED,
e315cd28 3534 &base_vha->dpc_flags);
99363ef8 3535 }
e315cd28
AC		 3536 clear_bit(ABORT_ISP_ACTIVE,
3537 &base_vha->dpc_flags);
99363ef8
SJ		 3538 }
3539
7c3df132
SK		 3540 ql_dbg(ql_dbg_dpc, base_vha, 0x4008,
3541 "ISP abort end.\n");
1da177e4
LT		 3542 }
3543
e315cd28
AC		 3544 if (test_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags)) {
3545 qla2x00_update_fcports(base_vha);
3546 clear_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags);
c9c5ced9 3547 }
d97994dc 3548
579d12b5 3549 if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) {
7c3df132
SK		 3550 ql_dbg(ql_dbg_dpc, base_vha, 0x4009,
3551 "Quiescence mode scheduled.\n");
579d12b5
SK		 3552 qla82xx_device_state_handler(base_vha);
3553 clear_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags);
3554 if (!ha->flags.quiesce_owner) {
3555 qla2x00_perform_loop_resync(base_vha);
3556
3557 qla82xx_idc_lock(ha);
3558 qla82xx_clear_qsnt_ready(base_vha);
3559 qla82xx_idc_unlock(ha);
3560 }
7c3df132
SK		 3561 ql_dbg(ql_dbg_dpc, base_vha, 0x400a,
3562 "Quiescence mode end.\n");
579d12b5
SK		 3563 }
3564
e315cd28
AC		 3565 if (test_and_clear_bit(RESET_MARKER_NEEDED,
3566 &base_vha->dpc_flags) &&
3567 (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) {
1da177e4 3568
7c3df132
SK		 3569 ql_dbg(ql_dbg_dpc, base_vha, 0x400b,
3570 "Reset marker scheduled.\n");
e315cd28
AC		 3571 qla2x00_rst_aen(base_vha);
3572 clear_bit(RESET_ACTIVE, &base_vha->dpc_flags);
7c3df132
SK		 3573 ql_dbg(ql_dbg_dpc, base_vha, 0x400c,
3574 "Reset marker end.\n");
1da177e4
LT		 3575 }
3576
3577 /* Retry each device up to login retry count */
e315cd28
AC		 3578 if ((test_and_clear_bit(RELOGIN_NEEDED,
3579 &base_vha->dpc_flags)) &&
3580 !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) &&
3581 atomic_read(&base_vha->loop_state) != LOOP_DOWN) {
1da177e4 3582
7c3df132
SK		 3583 ql_dbg(ql_dbg_dpc, base_vha, 0x400d,
3584 "Relogin scheduled.\n");
e315cd28 3585 qla2x00_relogin(base_vha);
7c3df132
SK		 3586 ql_dbg(ql_dbg_dpc, base_vha, 0x400e,
3587 "Relogin end.\n");
1da177e4
LT		 3588 }
3589
e315cd28
AC		 3590 if (test_and_clear_bit(LOOP_RESYNC_NEEDED,
3591 &base_vha->dpc_flags)) {
1da177e4 3592
7c3df132
SK		 3593 ql_dbg(ql_dbg_dpc, base_vha, 0x400f,
3594 "Loop resync scheduled.\n");
1da177e4
LT		 3595
3596 if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE,
e315cd28 3597 &base_vha->dpc_flags))) {
1da177e4 3598
e315cd28 3599 rval = qla2x00_loop_resync(base_vha);
1da177e4 3600
e315cd28
AC		 3601 clear_bit(LOOP_RESYNC_ACTIVE,
3602 &base_vha->dpc_flags);
1da177e4
LT		 3603 }
3604
7c3df132
SK		 3605 ql_dbg(ql_dbg_dpc, base_vha, 0x4010,
3606 "Loop resync end.\n");
1da177e4
LT		 3607 }
3608
e315cd28
AC		 3609 if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) &&
3610 atomic_read(&base_vha->loop_state) == LOOP_READY) {
3611 clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags);
3612 qla2xxx_flash_npiv_conf(base_vha);
272976ca
AV		 3613 }
3614
1da177e4 3615 if (!ha->interrupts_on)
fd34f556 3616 ha->isp_ops->enable_intrs(ha);
1da177e4 3617
e315cd28
AC		 3618 if (test_and_clear_bit(BEACON_BLINK_NEEDED,
3619 &base_vha->dpc_flags))
3620 ha->isp_ops->beacon_blink(base_vha);
f6df144c 3621
e315cd28 3622 qla2x00_do_dpc_all_vps(base_vha);
2c3dfe3f 3623
1da177e4 3624 ha->dpc_active = 0;
563585ec 3625 set_current_state(TASK_INTERRUPTIBLE);
1da177e4 3626 } /* End of while(1) */
563585ec 3627 __set_current_state(TASK_RUNNING);
1da177e4 3628
7c3df132
SK		 3629 ql_dbg(ql_dbg_dpc, base_vha, 0x4011,
3630 "DPC handler exiting.\n");
1da177e4
LT		 3631
3632 /*
3633 * Make sure that nobody tries to wake us up again.
3634 */
1da177e4
LT		 3635 ha->dpc_active = 0;
3636
ac280b67
AV		 3637 /* Cleanup any residual CTX SRBs. */
3638 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
3639
39a11240
CH		 3640 return 0;
3641}
3642
3643void
e315cd28 3644qla2xxx_wake_dpc(struct scsi_qla_host *vha)
39a11240 3645{
e315cd28 3646 struct qla_hw_data *ha = vha->hw;
c795c1e4
AV		 3647 struct task_struct *t = ha->dpc_thread;
3648
e315cd28 3649 if (!test_bit(UNLOADING, &vha->dpc_flags) && t)
c795c1e4 3650 wake_up_process(t);
1da177e4
LT		 3651}
3652
1da177e4
LT		 3653/*
3654* qla2x00_rst_aen
3655* Processes asynchronous reset.
3656*
3657* Input:
3658* ha = adapter block pointer.
3659*/
3660static void
e315cd28 3661qla2x00_rst_aen(scsi_qla_host_t *vha)
1da177e4 3662{
e315cd28
AC		 3663 if (vha->flags.online && !vha->flags.reset_active &&
3664 !atomic_read(&vha->loop_down_timer) &&
3665 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) {
1da177e4 3666 do {
e315cd28 3667 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
1da177e4
LT		 3668
3669 /*
3670 * Issue marker command only when we are going to start
3671 * the I/O.
3672 */
e315cd28
AC		 3673 vha->marker_needed = 1;
3674 } while (!atomic_read(&vha->loop_down_timer) &&
3675 (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)));
1da177e4
LT		 3676 }
3677}
3678
f4f051eb 3679static void
e315cd28 3680qla2x00_sp_free_dma(srb_t *sp)
f4f051eb 3681{
3682 struct scsi_cmnd *cmd = sp->cmd;
bad75002 3683 struct qla_hw_data *ha = sp->fcport->vha->hw;
f4f051eb 3684
3685 if (sp->flags & SRB_DMA_VALID) {
385d70b4 3686 scsi_dma_unmap(cmd);
f4f051eb 3687 sp->flags &= ~SRB_DMA_VALID;
3688 }
bad75002
AE		 3689
3690 if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
3691 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
3692 scsi_prot_sg_count(cmd), cmd->sc_data_direction);
3693 sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
3694 }
3695
3696 if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
3697 /* List assured to be having elements */
3698 qla2x00_clean_dsd_pool(ha, sp);
3699 sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
3700 }
3701
3702 if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
3703 dma_pool_free(ha->dl_dma_pool, sp->ctx,
3704 ((struct crc_context *)sp->ctx)->crc_ctx_dma);
3705 sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
3706 }
3707
fca29703 3708 CMD_SP(cmd) = NULL;
f4f051eb 3709}
3710
3dbe756a 3711static void
083a469d 3712qla2x00_sp_final_compl(struct qla_hw_data *ha, srb_t *sp)
f4f051eb 3713{
3714 struct scsi_cmnd *cmd = sp->cmd;
3715
e315cd28 3716 qla2x00_sp_free_dma(sp);
f4f051eb 3717
a9083016
GM		 3718 if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
3719 struct ct6_dsd *ctx = sp->ctx;
3720 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx->fcp_cmnd,
3721 ctx->fcp_cmnd_dma);
3722 list_splice(&ctx->dsd_list, &ha->gbl_dsd_list);
3723 ha->gbl_dsd_inuse -= ctx->dsd_use_cnt;
3724 ha->gbl_dsd_avail += ctx->dsd_use_cnt;
3725 mempool_free(sp->ctx, ha->ctx_mempool);
3726 sp->ctx = NULL;
3727 }
f4f051eb 3728
a9083016 3729 mempool_free(sp, ha->srb_mempool);
f4f051eb 3730 cmd->scsi_done(cmd);
3731}
bdf79621 3732
083a469d
GM		 3733void
3734qla2x00_sp_compl(struct qla_hw_data *ha, srb_t *sp)
3735{
3736 if (atomic_read(&sp->ref_count) == 0) {
7c3df132
SK		 3737 ql_dbg(ql_dbg_io, sp->fcport->vha, 0x3015,
3738 "SP reference-count to ZERO -- sp=%p cmd=%p.\n",
3739 sp, sp->cmd);
3740 if (ql2xextended_error_logging & ql_dbg_io)
3741 BUG();
083a469d
GM		 3742 return;
3743 }
3744 if (!atomic_dec_and_test(&sp->ref_count))
3745 return;
3746 qla2x00_sp_final_compl(ha, sp);
3747}
3748
1da177e4
LT		 3749/**************************************************************************
3750* qla2x00_timer
3751*
3752* Description:
3753* One second timer
3754*
3755* Context: Interrupt
3756***************************************************************************/
2c3dfe3f 3757void
e315cd28 3758qla2x00_timer(scsi_qla_host_t *vha)
1da177e4 3759{
1da177e4 3760 unsigned long cpu_flags = 0;
1da177e4
LT		 3761 int start_dpc = 0;
3762 int index;
3763 srb_t *sp;
85880801 3764 uint16_t w;
e315cd28 3765 struct qla_hw_data *ha = vha->hw;
73208dfd 3766 struct req_que *req;
85880801 3767
a5b36321 3768 if (ha->flags.eeh_busy) {
7c3df132
SK		 3769 ql_dbg(ql_dbg_timer, vha, 0x6000,
3770 "EEH = %d, restarting timer.\n",
3771 ha->flags.eeh_busy);
a5b36321
LC		 3772 qla2x00_restart_timer(vha, WATCH_INTERVAL);
3773 return;
3774 }
3775
85880801
AV		 3776 /* Hardware read to raise pending EEH errors during mailbox waits. */
3777 if (!pci_channel_offline(ha->pdev))
3778 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w);
1da177e4 3779
cefcaba6
SK		 3780 /* Make sure qla82xx_watchdog is run only for physical port */
3781 if (!vha->vp_idx && IS_QLA82XX(ha)) {
579d12b5
SK		 3782 if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags))
3783 start_dpc++;
3784 qla82xx_watchdog(vha);
3785 }
3786
1da177e4 3787 /* Loop down handler. */
e315cd28 3788 if (atomic_read(&vha->loop_down_timer) > 0 &&
8f7daead
GM		 3789 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) &&
3790 !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags))
e315cd28 3791 && vha->flags.online) {
1da177e4 3792
e315cd28
AC		 3793 if (atomic_read(&vha->loop_down_timer) ==
3794 vha->loop_down_abort_time) {
1da177e4 3795
7c3df132
SK		 3796 ql_log(ql_log_info, vha, 0x6008,
3797 "Loop down - aborting the queues before time expires.\n");
1da177e4 3798
e315cd28
AC		 3799 if (!IS_QLA2100(ha) && vha->link_down_timeout)
3800 atomic_set(&vha->loop_state, LOOP_DEAD);
1da177e4 3801
f08b7251
AV		 3802 /*
3803 * Schedule an ISP abort to return any FCP2-device
3804 * commands.
3805 */
2c3dfe3f 3806 /* NPIV - scan physical port only */
e315cd28 3807 if (!vha->vp_idx) {
2c3dfe3f
SJ		 3808 spin_lock_irqsave(&ha->hardware_lock,
3809 cpu_flags);
73208dfd 3810 req = ha->req_q_map[0];
2c3dfe3f
SJ		 3811 for (index = 1;
3812 index < MAX_OUTSTANDING_COMMANDS;
3813 index++) {
3814 fc_port_t *sfcp;
3815
e315cd28 3816 sp = req->outstanding_cmds[index];
2c3dfe3f
SJ		 3817 if (!sp)
3818 continue;
bad75002 3819 if (sp->ctx && !IS_PROT_IO(sp))
cf53b069 3820 continue;
2c3dfe3f 3821 sfcp = sp->fcport;
f08b7251 3822 if (!(sfcp->flags & FCF_FCP2_DEVICE))
2c3dfe3f 3823 continue;
bdf79621 3824
8f7daead
GM		 3825 if (IS_QLA82XX(ha))
3826 set_bit(FCOE_CTX_RESET_NEEDED,
3827 &vha->dpc_flags);
3828 else
3829 set_bit(ISP_ABORT_NEEDED,
e315cd28 3830 &vha->dpc_flags);
2c3dfe3f
SJ		 3831 break;
3832 }
3833 spin_unlock_irqrestore(&ha->hardware_lock,
e315cd28 3834 cpu_flags);
1da177e4 3835 }
1da177e4
LT		 3836 start_dpc++;
3837 }
3838
3839 /* if the loop has been down for 4 minutes, reinit adapter */
e315cd28 3840 if (atomic_dec_and_test(&vha->loop_down_timer) != 0) {
0d6e61bc 3841 if (!(vha->device_flags & DFLG_NO_CABLE)) {
7c3df132 3842 ql_log(ql_log_warn, vha, 0x6009,
1da177e4
LT		 3843 "Loop down - aborting ISP.\n");
3844
8f7daead
GM		 3845 if (IS_QLA82XX(ha))
3846 set_bit(FCOE_CTX_RESET_NEEDED,
3847 &vha->dpc_flags);
3848 else
3849 set_bit(ISP_ABORT_NEEDED,
3850 &vha->dpc_flags);
1da177e4
LT		 3851 }
3852 }
7c3df132
SK		 3853 ql_dbg(ql_dbg_timer, vha, 0x600a,
3854 "Loop down - seconds remaining %d.\n",
3855 atomic_read(&vha->loop_down_timer));
1da177e4
LT		 3856 }
3857
cefcaba6
SK		 3858 /* Check if beacon LED needs to be blinked for physical host only */
3859 if (!vha->vp_idx && (ha->beacon_blink_led == 1)) {
999916dc
SK		 3860 /* There is no beacon_blink function for ISP82xx */
3861 if (!IS_QLA82XX(ha)) {
3862 set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags);
3863 start_dpc++;
3864 }
f6df144c 3865 }
3866
550bf57d 3867 /* Process any deferred work. */
e315cd28 3868 if (!list_empty(&vha->work_list))
550bf57d
AV		 3869 start_dpc++;
3870
1da177e4 3871 /* Schedule the DPC routine if needed */
e315cd28
AC		 3872 if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) ||
3873 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) ||
3874 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags) ||
1da177e4 3875 start_dpc ||
e315cd28
AC		 3876 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) ||
3877 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) ||
a9083016
GM		 3878 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) ||
3879 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) ||
e315cd28 3880 test_bit(VP_DPC_NEEDED, &vha->dpc_flags) ||
7c3df132
SK		 3881 test_bit(RELOGIN_NEEDED, &vha->dpc_flags))) {
3882 ql_dbg(ql_dbg_timer, vha, 0x600b,
3883 "isp_abort_needed=%d loop_resync_needed=%d "
3884 "fcport_update_needed=%d start_dpc=%d "
3885 "reset_marker_needed=%d",
3886 test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags),
3887 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags),
3888 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags),
3889 start_dpc,
3890 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags));
3891 ql_dbg(ql_dbg_timer, vha, 0x600c,
3892 "beacon_blink_needed=%d isp_unrecoverable=%d "
3893 "fcoe_ctx_reset_needed=%d vp_dpc_needed=%d "
3894 "relogin_needed=%d.\n",
3895 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags),
3896 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags),
3897 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags),
3898 test_bit(VP_DPC_NEEDED, &vha->dpc_flags),
3899 test_bit(RELOGIN_NEEDED, &vha->dpc_flags));
e315cd28 3900 qla2xxx_wake_dpc(vha);
7c3df132 3901 }
1da177e4 3902
e315cd28 3903 qla2x00_restart_timer(vha, WATCH_INTERVAL);
1da177e4
LT		 3904}
3905
5433383e
AV		 3906/* Firmware interface routines. */
3907
a9083016 3908#define FW_BLOBS 8
5433383e
AV		 3909#define FW_ISP21XX 0
3910#define FW_ISP22XX 1
3911#define FW_ISP2300 2
3912#define FW_ISP2322 3
48c02fde 3913#define FW_ISP24XX 4
c3a2f0df 3914#define FW_ISP25XX 5
3a03eb79 3915#define FW_ISP81XX 6
a9083016 3916#define FW_ISP82XX 7
5433383e 3917
bb8ee499
AV		 3918#define FW_FILE_ISP21XX "ql2100_fw.bin"
3919#define FW_FILE_ISP22XX "ql2200_fw.bin"
3920#define FW_FILE_ISP2300 "ql2300_fw.bin"
3921#define FW_FILE_ISP2322 "ql2322_fw.bin"
3922#define FW_FILE_ISP24XX "ql2400_fw.bin"
c3a2f0df 3923#define FW_FILE_ISP25XX "ql2500_fw.bin"
3a03eb79 3924#define FW_FILE_ISP81XX "ql8100_fw.bin"
a9083016 3925#define FW_FILE_ISP82XX "ql8200_fw.bin"
bb8ee499 3926
e1e82b6f 3927static DEFINE_MUTEX(qla_fw_lock);
5433383e
AV		 3928
3929static struct fw_blob qla_fw_blobs[FW_BLOBS] = {
bb8ee499
AV		 3930 { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, },
3931 { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, },
3932 { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, },
3933 { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, },
3934 { .name = FW_FILE_ISP24XX, },
c3a2f0df 3935 { .name = FW_FILE_ISP25XX, },
3a03eb79 3936 { .name = FW_FILE_ISP81XX, },
a9083016 3937 { .name = FW_FILE_ISP82XX, },
5433383e
AV		 3938};
3939
3940struct fw_blob *
e315cd28 3941qla2x00_request_firmware(scsi_qla_host_t *vha)
5433383e 3942{
e315cd28 3943 struct qla_hw_data *ha = vha->hw;
5433383e
AV		 3944 struct fw_blob *blob;
3945
3946 blob = NULL;
3947 if (IS_QLA2100(ha)) {
3948 blob = &qla_fw_blobs[FW_ISP21XX];
3949 } else if (IS_QLA2200(ha)) {
3950 blob = &qla_fw_blobs[FW_ISP22XX];
48c02fde 3951 } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
5433383e 3952 blob = &qla_fw_blobs[FW_ISP2300];
48c02fde 3953 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
5433383e 3954 blob = &qla_fw_blobs[FW_ISP2322];
4d4df193 3955 } else if (IS_QLA24XX_TYPE(ha)) {
5433383e 3956 blob = &qla_fw_blobs[FW_ISP24XX];
c3a2f0df
AV		 3957 } else if (IS_QLA25XX(ha)) {
3958 blob = &qla_fw_blobs[FW_ISP25XX];
3a03eb79
AV		 3959 } else if (IS_QLA81XX(ha)) {
3960 blob = &qla_fw_blobs[FW_ISP81XX];
a9083016
GM		 3961 } else if (IS_QLA82XX(ha)) {
3962 blob = &qla_fw_blobs[FW_ISP82XX];
5433383e
AV		 3963 }
3964
e1e82b6f 3965 mutex_lock(&qla_fw_lock);
5433383e
AV		 3966 if (blob->fw)
3967 goto out;
3968
3969 if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) {
7c3df132
SK		 3970 ql_log(ql_log_warn, vha, 0x0063,
3971 "Failed to load firmware image (%s).\n", blob->name);
5433383e
AV		 3972 blob->fw = NULL;
3973 blob = NULL;
3974 goto out;
3975 }
3976
3977out:
e1e82b6f 3978 mutex_unlock(&qla_fw_lock);
5433383e
AV		 3979 return blob;
3980}
3981
3982static void
3983qla2x00_release_firmware(void)
3984{
3985 int idx;
3986
e1e82b6f 3987 mutex_lock(&qla_fw_lock);
5433383e
AV		 3988 for (idx = 0; idx < FW_BLOBS; idx++)
3989 if (qla_fw_blobs[idx].fw)
3990 release_firmware(qla_fw_blobs[idx].fw);
e1e82b6f 3991 mutex_unlock(&qla_fw_lock);
5433383e
AV		 3992}
3993
14e660e6
SJ		 3994static pci_ers_result_t
3995qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
3996{
85880801
AV		 3997 scsi_qla_host_t *vha = pci_get_drvdata(pdev);
3998 struct qla_hw_data *ha = vha->hw;
3999
7c3df132
SK		 4000 ql_dbg(ql_dbg_aer, vha, 0x9000,
4001 "PCI error detected, state %x.\n", state);
b9b12f73 4002
14e660e6
SJ		 4003 switch (state) {
4004 case pci_channel_io_normal:
85880801 4005 ha->flags.eeh_busy = 0;
14e660e6
SJ		 4006 return PCI_ERS_RESULT_CAN_RECOVER;
4007 case pci_channel_io_frozen:
85880801 4008 ha->flags.eeh_busy = 1;
a5b36321
LC		 4009 /* For ISP82XX complete any pending mailbox cmd */
4010 if (IS_QLA82XX(ha)) {
7190575f 4011 ha->flags.isp82xx_fw_hung = 1;
c8f6544e
CD		 4012 ql_dbg(ql_dbg_aer, vha, 0x9001, "Pci channel io frozen\n");
4013 qla82xx_clear_pending_mbx(vha);
a5b36321 4014 }
90a86fc0 4015 qla2x00_free_irqs(vha);
14e660e6 4016 pci_disable_device(pdev);
bddd2d65
LC		 4017 /* Return back all IOs */
4018 qla2x00_abort_all_cmds(vha, DID_RESET << 16);
14e660e6
SJ		 4019 return PCI_ERS_RESULT_NEED_RESET;
4020 case pci_channel_io_perm_failure:
85880801
AV		 4021 ha->flags.pci_channel_io_perm_failure = 1;
4022 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
14e660e6
SJ		 4023 return PCI_ERS_RESULT_DISCONNECT;
4024 }
4025 return PCI_ERS_RESULT_NEED_RESET;
4026}
4027
4028static pci_ers_result_t
4029qla2xxx_pci_mmio_enabled(struct pci_dev *pdev)
4030{
4031 int risc_paused = 0;
4032 uint32_t stat;
4033 unsigned long flags;
e315cd28
AC		 4034 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
4035 struct qla_hw_data *ha = base_vha->hw;
14e660e6
SJ		 4036 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
4037 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
4038
bcc5b6d3
SK		 4039 if (IS_QLA82XX(ha))
4040 return PCI_ERS_RESULT_RECOVERED;
4041
14e660e6
SJ		 4042 spin_lock_irqsave(&ha->hardware_lock, flags);
4043 if (IS_QLA2100(ha) || IS_QLA2200(ha)){
4044 stat = RD_REG_DWORD(&reg->hccr);
4045 if (stat & HCCR_RISC_PAUSE)
4046 risc_paused = 1;
4047 } else if (IS_QLA23XX(ha)) {
4048 stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
4049 if (stat & HSR_RISC_PAUSED)
4050 risc_paused = 1;
4051 } else if (IS_FWI2_CAPABLE(ha)) {
4052 stat = RD_REG_DWORD(&reg24->host_status);
4053 if (stat & HSRX_RISC_PAUSED)
4054 risc_paused = 1;
4055 }
4056 spin_unlock_irqrestore(&ha->hardware_lock, flags);
4057
4058 if (risc_paused) {
7c3df132
SK		 4059 ql_log(ql_log_info, base_vha, 0x9003,
4060 "RISC paused -- mmio_enabled, Dumping firmware.\n");
e315cd28 4061 ha->isp_ops->fw_dump(base_vha, 0);
14e660e6
SJ		 4062
4063 return PCI_ERS_RESULT_NEED_RESET;
4064 } else
4065 return PCI_ERS_RESULT_RECOVERED;
4066}
4067
a5b36321
LC		 4068uint32_t qla82xx_error_recovery(scsi_qla_host_t *base_vha)
4069{
4070 uint32_t rval = QLA_FUNCTION_FAILED;
4071 uint32_t drv_active = 0;
4072 struct qla_hw_data *ha = base_vha->hw;
4073 int fn;
4074 struct pci_dev *other_pdev = NULL;
4075
7c3df132
SK		 4076 ql_dbg(ql_dbg_aer, base_vha, 0x9006,
4077 "Entered %s.\n", __func__);
a5b36321
LC		 4078
4079 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
4080
4081 if (base_vha->flags.online) {
4082 /* Abort all outstanding commands,
4083 * so as to be requeued later */
4084 qla2x00_abort_isp_cleanup(base_vha);
4085 }
4086
4087
4088 fn = PCI_FUNC(ha->pdev->devfn);
4089 while (fn > 0) {
4090 fn--;
7c3df132
SK		 4091 ql_dbg(ql_dbg_aer, base_vha, 0x9007,
4092 "Finding pci device at function = 0x%x.\n", fn);
a5b36321
LC		 4093 other_pdev =
4094 pci_get_domain_bus_and_slot(pci_domain_nr(ha->pdev->bus),
4095 ha->pdev->bus->number, PCI_DEVFN(PCI_SLOT(ha->pdev->devfn),
4096 fn));
4097
4098 if (!other_pdev)
4099 continue;
4100 if (atomic_read(&other_pdev->enable_cnt)) {
7c3df132
SK		 4101 ql_dbg(ql_dbg_aer, base_vha, 0x9008,
4102 "Found PCI func available and enable at 0x%x.\n",
4103 fn);
a5b36321
LC		 4104 pci_dev_put(other_pdev);
4105 break;
4106 }
4107 pci_dev_put(other_pdev);
4108 }
4109
4110 if (!fn) {
4111 /* Reset owner */
7c3df132
SK		 4112 ql_dbg(ql_dbg_aer, base_vha, 0x9009,
4113 "This devfn is reset owner = 0x%x.\n",
4114 ha->pdev->devfn);
a5b36321
LC		 4115 qla82xx_idc_lock(ha);
4116
4117 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
4118 QLA82XX_DEV_INITIALIZING);
4119
4120 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION,
4121 QLA82XX_IDC_VERSION);
4122
4123 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
7c3df132
SK		 4124 ql_dbg(ql_dbg_aer, base_vha, 0x900a,
4125 "drv_active = 0x%x.\n", drv_active);
a5b36321
LC		 4126
4127 qla82xx_idc_unlock(ha);
4128 /* Reset if device is not already reset
4129 * drv_active would be 0 if a reset has already been done
4130 */
4131 if (drv_active)
4132 rval = qla82xx_start_firmware(base_vha);
4133 else
4134 rval = QLA_SUCCESS;
4135 qla82xx_idc_lock(ha);
4136
4137 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4138 ql_log(ql_log_info, base_vha, 0x900b,
4139 "HW State: FAILED.\n");
a5b36321
LC		 4140 qla82xx_clear_drv_active(ha);
4141 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
4142 QLA82XX_DEV_FAILED);
4143 } else {
7c3df132
SK		 4144 ql_log(ql_log_info, base_vha, 0x900c,
4145 "HW State: READY.\n");
a5b36321
LC		 4146 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
4147 QLA82XX_DEV_READY);
4148 qla82xx_idc_unlock(ha);
7190575f 4149 ha->flags.isp82xx_fw_hung = 0;
a5b36321
LC		 4150 rval = qla82xx_restart_isp(base_vha);
4151 qla82xx_idc_lock(ha);
4152 /* Clear driver state register */
4153 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, 0);
4154 qla82xx_set_drv_active(base_vha);
4155 }
4156 qla82xx_idc_unlock(ha);
4157 } else {
7c3df132
SK		 4158 ql_dbg(ql_dbg_aer, base_vha, 0x900d,
4159 "This devfn is not reset owner = 0x%x.\n",
4160 ha->pdev->devfn);
a5b36321
LC		 4161 if ((qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE) ==
4162 QLA82XX_DEV_READY)) {
7190575f 4163 ha->flags.isp82xx_fw_hung = 0;
a5b36321
LC		 4164 rval = qla82xx_restart_isp(base_vha);
4165 qla82xx_idc_lock(ha);
4166 qla82xx_set_drv_active(base_vha);
4167 qla82xx_idc_unlock(ha);
4168 }
4169 }
4170 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
4171
4172 return rval;
4173}
4174
14e660e6
SJ		 4175static pci_ers_result_t
4176qla2xxx_pci_slot_reset(struct pci_dev *pdev)
4177{
4178 pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT;
e315cd28
AC		 4179 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
4180 struct qla_hw_data *ha = base_vha->hw;
90a86fc0
JC		 4181 struct rsp_que *rsp;
4182 int rc, retries = 10;
09483916 4183
7c3df132
SK		 4184 ql_dbg(ql_dbg_aer, base_vha, 0x9004,
4185 "Slot Reset.\n");
85880801 4186
90a86fc0
JC		 4187 /* Workaround: qla2xxx driver which access hardware earlier
4188 * needs error state to be pci_channel_io_online.
4189 * Otherwise mailbox command timesout.
4190 */
4191 pdev->error_state = pci_channel_io_normal;
4192
4193 pci_restore_state(pdev);
4194
8c1496bd
RL		 4195 /* pci_restore_state() clears the saved_state flag of the device
4196 * save restored state which resets saved_state flag
4197 */
4198 pci_save_state(pdev);
4199
09483916
BH		 4200 if (ha->mem_only)
4201 rc = pci_enable_device_mem(pdev);
4202 else
4203 rc = pci_enable_device(pdev);
14e660e6 4204
09483916 4205 if (rc) {
7c3df132 4206 ql_log(ql_log_warn, base_vha, 0x9005,
14e660e6 4207 "Can't re-enable PCI device after reset.\n");
a5b36321 4208 goto exit_slot_reset;
14e660e6 4209 }
14e660e6 4210
90a86fc0
JC		 4211 rsp = ha->rsp_q_map[0];
4212 if (qla2x00_request_irqs(ha, rsp))
a5b36321 4213 goto exit_slot_reset;
90a86fc0 4214
e315cd28 4215 if (ha->isp_ops->pci_config(base_vha))
a5b36321
LC		 4216 goto exit_slot_reset;
4217
4218 if (IS_QLA82XX(ha)) {
4219 if (qla82xx_error_recovery(base_vha) == QLA_SUCCESS) {
4220 ret = PCI_ERS_RESULT_RECOVERED;
4221 goto exit_slot_reset;
4222 } else
4223 goto exit_slot_reset;
4224 }
14e660e6 4225
90a86fc0
JC		 4226 while (ha->flags.mbox_busy && retries--)
4227 msleep(1000);
85880801 4228
e315cd28 4229 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
a9083016 4230 if (ha->isp_ops->abort_isp(base_vha) == QLA_SUCCESS)
14e660e6 4231 ret = PCI_ERS_RESULT_RECOVERED;
e315cd28 4232 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
14e660e6 4233
90a86fc0 4234
a5b36321 4235exit_slot_reset:
7c3df132
SK		 4236 ql_dbg(ql_dbg_aer, base_vha, 0x900e,
4237 "slot_reset return %x.\n", ret);
85880801 4238
14e660e6
SJ		 4239 return ret;
4240}
4241
4242static void
4243qla2xxx_pci_resume(struct pci_dev *pdev)
4244{
e315cd28
AC		 4245 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
4246 struct qla_hw_data *ha = base_vha->hw;
14e660e6
SJ		 4247 int ret;
4248
7c3df132
SK		 4249 ql_dbg(ql_dbg_aer, base_vha, 0x900f,
4250 "pci_resume.\n");
85880801 4251
e315cd28 4252 ret = qla2x00_wait_for_hba_online(base_vha);
14e660e6 4253 if (ret != QLA_SUCCESS) {
7c3df132
SK		 4254 ql_log(ql_log_fatal, base_vha, 0x9002,
4255 "The device failed to resume I/O from slot/link_reset.\n");
14e660e6 4256 }
85880801 4257
3e46f031
LC		 4258 pci_cleanup_aer_uncorrect_error_status(pdev);
4259
85880801 4260 ha->flags.eeh_busy = 0;
14e660e6
SJ		 4261}
4262
4263static struct pci_error_handlers qla2xxx_err_handler = {
4264 .error_detected = qla2xxx_pci_error_detected,
4265 .mmio_enabled = qla2xxx_pci_mmio_enabled,
4266 .slot_reset = qla2xxx_pci_slot_reset,
4267 .resume = qla2xxx_pci_resume,
4268};
4269
5433383e 4270static struct pci_device_id qla2xxx_pci_tbl[] = {
47f5e069
AV		 4271 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) },
4272 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) },
4273 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) },
4274 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) },
4275 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) },
4276 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) },
4277 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) },
4278 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) },
4279 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) },
4d4df193 4280 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) },
47f5e069
AV		 4281 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) },
4282 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) },
c3a2f0df 4283 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) },
3a03eb79 4284 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) },
a9083016 4285 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) },
5433383e
AV		 4286 { 0 },
4287};
4288MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl);
4289
fca29703 4290static struct pci_driver qla2xxx_pci_driver = {
cb63067a 4291 .name = QLA2XXX_DRIVER_NAME,
0a21ef1e
JB		 4292 .driver = {
4293 .owner = THIS_MODULE,
4294 },
fca29703 4295 .id_table = qla2xxx_pci_tbl,
7ee61397 4296 .probe = qla2x00_probe_one,
4c993f76 4297 .remove = qla2x00_remove_one,
e30d1756 4298 .shutdown = qla2x00_shutdown,
14e660e6 4299 .err_handler = &qla2xxx_err_handler,
fca29703
AV		 4300};
4301
6a03b4cd
HZ		 4302static struct file_operations apidev_fops = {
4303 .owner = THIS_MODULE,
6038f373 4304 .llseek = noop_llseek,
6a03b4cd
HZ		 4305};
4306
1da177e4
LT		 4307/**
4308 * qla2x00_module_init - Module initialization.
4309 **/
4310static int __init
4311qla2x00_module_init(void)
4312{
fca29703
AV		 4313 int ret = 0;
4314
1da177e4 4315 /* Allocate cache for SRBs. */
354d6b21 4316 srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0,
20c2df83 4317 SLAB_HWCACHE_ALIGN, NULL);
1da177e4 4318 if (srb_cachep == NULL) {
7c3df132
SK		 4319 ql_log(ql_log_fatal, NULL, 0x0001,
4320 "Unable to allocate SRB cache...Failing load!.\n");
1da177e4
LT		 4321 return -ENOMEM;
4322 }
4323
4324 /* Derive version string. */
4325 strcpy(qla2x00_version_str, QLA2XXX_VERSION);
11010fec 4326 if (ql2xextended_error_logging)
0181944f
AV		 4327 strcat(qla2x00_version_str, "-debug");
4328
1c97a12a
AV		 4329 qla2xxx_transport_template =
4330 fc_attach_transport(&qla2xxx_transport_functions);
2c3dfe3f
SJ		 4331 if (!qla2xxx_transport_template) {
4332 kmem_cache_destroy(srb_cachep);
7c3df132
SK		 4333 ql_log(ql_log_fatal, NULL, 0x0002,
4334 "fc_attach_transport failed...Failing load!.\n");
1da177e4 4335 return -ENODEV;
2c3dfe3f 4336 }
6a03b4cd
HZ		 4337
4338 apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops);
4339 if (apidev_major < 0) {
7c3df132
SK		 4340 ql_log(ql_log_fatal, NULL, 0x0003,
4341 "Unable to register char device %s.\n", QLA2XXX_APIDEV);
6a03b4cd
HZ		 4342 }
4343
2c3dfe3f
SJ		 4344 qla2xxx_transport_vport_template =
4345 fc_attach_transport(&qla2xxx_transport_vport_functions);
4346 if (!qla2xxx_transport_vport_template) {
4347 kmem_cache_destroy(srb_cachep);
4348 fc_release_transport(qla2xxx_transport_template);
7c3df132
SK		 4349 ql_log(ql_log_fatal, NULL, 0x0004,
4350 "fc_attach_transport vport failed...Failing load!.\n");
1da177e4 4351 return -ENODEV;
2c3dfe3f 4352 }
7c3df132
SK		 4353 ql_log(ql_log_info, NULL, 0x0005,
4354 "QLogic Fibre Channel HBA Driver: %s.\n",
fd9a29f0 4355 qla2x00_version_str);
7ee61397 4356 ret = pci_register_driver(&qla2xxx_pci_driver);
fca29703
AV		 4357 if (ret) {
4358 kmem_cache_destroy(srb_cachep);
4359 fc_release_transport(qla2xxx_transport_template);
2c3dfe3f 4360 fc_release_transport(qla2xxx_transport_vport_template);
7c3df132
SK		 4361 ql_log(ql_log_fatal, NULL, 0x0006,
4362 "pci_register_driver failed...ret=%d Failing load!.\n",
4363 ret);
fca29703
AV		 4364 }
4365 return ret;
1da177e4
LT		 4366}
4367
4368/**
4369 * qla2x00_module_exit - Module cleanup.
4370 **/
4371static void __exit
4372qla2x00_module_exit(void)
4373{
6a03b4cd 4374 unregister_chrdev(apidev_major, QLA2XXX_APIDEV);
7ee61397 4375 pci_unregister_driver(&qla2xxx_pci_driver);
5433383e 4376 qla2x00_release_firmware();
354d6b21 4377 kmem_cache_destroy(srb_cachep);
a9083016
GM		 4378 if (ctx_cachep)
4379 kmem_cache_destroy(ctx_cachep);
1da177e4 4380 fc_release_transport(qla2xxx_transport_template);
2c3dfe3f 4381 fc_release_transport(qla2xxx_transport_vport_template);
1da177e4
LT		 4382}
4383
4384module_init(qla2x00_module_init);
4385module_exit(qla2x00_module_exit);
4386
4387MODULE_AUTHOR("QLogic Corporation");
4388MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver");
4389MODULE_LICENSE("GPL");
4390MODULE_VERSION(QLA2XXX_VERSION);
bb8ee499
AV		 4391MODULE_FIRMWARE(FW_FILE_ISP21XX);
4392MODULE_FIRMWARE(FW_FILE_ISP22XX);
4393MODULE_FIRMWARE(FW_FILE_ISP2300);
4394MODULE_FIRMWARE(FW_FILE_ISP2322);
4395MODULE_FIRMWARE(FW_FILE_ISP24XX);
61623fc3 4396MODULE_FIRMWARE(FW_FILE_ISP25XX);
Linux 6.x block layer and io_uring tree(s)