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scsi: qla2xxx: Fix unintended Logout
[linux-2.6-block.git] / drivers / scsi / qla2xxx / qla_os.c
CommitLineData
1da177e4 1/*
fa90c54f 2 * QLogic Fibre Channel HBA Driver
bd21eaf9 3 * Copyright (c) 2003-2014 QLogic Corporation
1da177e4 4 *
fa90c54f 5 * See LICENSE.qla2xxx for copyright and licensing details.
1da177e4
LT		 6 */
7#include "qla_def.h"
8
9#include <linux/moduleparam.h>
10#include <linux/vmalloc.h>
1da177e4 11#include <linux/delay.h>
39a11240 12#include <linux/kthread.h>
e1e82b6f 13#include <linux/mutex.h>
3420d36c 14#include <linux/kobject.h>
5a0e3ad6 15#include <linux/slab.h>
5601236b 16#include <linux/blk-mq-pci.h>
1da177e4
LT		 17#include <scsi/scsi_tcq.h>
18#include <scsi/scsicam.h>
19#include <scsi/scsi_transport.h>
20#include <scsi/scsi_transport_fc.h>
21
2d70c103
NB		 22#include "qla_target.h"
23
1da177e4
LT		 24/*
25 * Driver version
26 */
27char qla2x00_version_str[40];
28
6a03b4cd
HZ		 29static int apidev_major;
30
1da177e4
LT		 31/*
32 * SRB allocation cache
33 */
d7459527 34struct kmem_cache *srb_cachep;
1da177e4 35
a9083016
GM		 36/*
37 * CT6 CTX allocation cache
38 */
39static struct kmem_cache *ctx_cachep;
3ce8866c
SK		 40/*
41 * error level for logging
42 */
43int ql_errlev = ql_log_all;
a9083016 44
fa492630 45static int ql2xenableclass2;
2d70c103
NB		 46module_param(ql2xenableclass2, int, S_IRUGO|S_IRUSR);
47MODULE_PARM_DESC(ql2xenableclass2,
48 "Specify if Class 2 operations are supported from the very "
49 "beginning. Default is 0 - class 2 not supported.");
50
8ae6d9c7 51
1da177e4 52int ql2xlogintimeout = 20;
f2019cb1 53module_param(ql2xlogintimeout, int, S_IRUGO);
1da177e4
LT		 54MODULE_PARM_DESC(ql2xlogintimeout,
55 "Login timeout value in seconds.");
56
a7b61842 57int qlport_down_retry;
f2019cb1 58module_param(qlport_down_retry, int, S_IRUGO);
1da177e4 59MODULE_PARM_DESC(qlport_down_retry,
900d9f98 60 "Maximum number of command retries to a port that returns "
1da177e4
LT		 61 "a PORT-DOWN status.");
62
1da177e4
LT		 63int ql2xplogiabsentdevice;
64module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR);
65MODULE_PARM_DESC(ql2xplogiabsentdevice,
66 "Option to enable PLOGI to devices that are not present after "
900d9f98 67 "a Fabric scan. This is needed for several broken switches. "
1da177e4
LT		 68 "Default is 0 - no PLOGI. 1 - perfom PLOGI.");
69
1da177e4 70int ql2xloginretrycount = 0;
f2019cb1 71module_param(ql2xloginretrycount, int, S_IRUGO);
1da177e4
LT		 72MODULE_PARM_DESC(ql2xloginretrycount,
73 "Specify an alternate value for the NVRAM login retry count.");
74
a7a167bf 75int ql2xallocfwdump = 1;
f2019cb1 76module_param(ql2xallocfwdump, int, S_IRUGO);
a7a167bf
AV		 77MODULE_PARM_DESC(ql2xallocfwdump,
78 "Option to enable allocation of memory for a firmware dump "
79 "during HBA initialization. Memory allocation requirements "
80 "vary by ISP type. Default is 1 - allocate memory.");
81
11010fec 82int ql2xextended_error_logging;
27d94035 83module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
a2b3e01d 84module_param_named(logging, ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
11010fec 85MODULE_PARM_DESC(ql2xextended_error_logging,
3ce8866c
SK		 86 "Option to enable extended error logging,\n"
87 "\t\tDefault is 0 - no logging. 0x40000000 - Module Init & Probe.\n"
88 "\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n"
89 "\t\t0x08000000 - IO tracing. 0x04000000 - DPC Thread.\n"
90 "\t\t0x02000000 - Async events. 0x01000000 - Timer routines.\n"
91 "\t\t0x00800000 - User space. 0x00400000 - Task Management.\n"
92 "\t\t0x00200000 - AER/EEH. 0x00100000 - Multi Q.\n"
93 "\t\t0x00080000 - P3P Specific. 0x00040000 - Virtual Port.\n"
94 "\t\t0x00020000 - Buffer Dump. 0x00010000 - Misc.\n"
29f9f90c
CD		 95 "\t\t0x00008000 - Verbose. 0x00004000 - Target.\n"
96 "\t\t0x00002000 - Target Mgmt. 0x00001000 - Target TMF.\n"
3ce8866c 97 "\t\t0x7fffffff - For enabling all logs, can be too many logs.\n"
cfb0919c
CD		 98 "\t\t0x1e400000 - Preferred value for capturing essential "
99 "debug information (equivalent to old "
100 "ql2xextended_error_logging=1).\n"
3ce8866c 101 "\t\tDo LOGICAL OR of the value to enable more than one level");
0181944f 102
a9083016 103int ql2xshiftctondsd = 6;
f2019cb1 104module_param(ql2xshiftctondsd, int, S_IRUGO);
a9083016
GM		 105MODULE_PARM_DESC(ql2xshiftctondsd,
106 "Set to control shifting of command type processing "
107 "based on total number of SG elements.");
108
7e47e5ca 109int ql2xfdmienable=1;
de187df8 110module_param(ql2xfdmienable, int, S_IRUGO|S_IWUSR);
a2b3e01d 111module_param_named(fdmi, ql2xfdmienable, int, S_IRUGO|S_IWUSR);
cca5335c 112MODULE_PARM_DESC(ql2xfdmienable,
7794a5af
FW		 113 "Enables FDMI registrations. "
114 "0 - no FDMI. Default is 1 - perform FDMI.");
cca5335c 115
d213a4b7 116#define MAX_Q_DEPTH 64
50280c01 117static int ql2xmaxqdepth = MAX_Q_DEPTH;
df7baa50
AV		 118module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR);
119MODULE_PARM_DESC(ql2xmaxqdepth,
e92e4a8f 120 "Maximum queue depth to set for each LUN. "
d213a4b7 121 "Default is 64.");
df7baa50 122
e84067d7
DG		 123#if (IS_ENABLED(CONFIG_NVME_FC))
124int ql2xenabledif;
125#else
9e522cd8 126int ql2xenabledif = 2;
e84067d7 127#endif
9e522cd8 128module_param(ql2xenabledif, int, S_IRUGO);
bad75002 129MODULE_PARM_DESC(ql2xenabledif,
b97f5d0b
SM		 130 " Enable T10-CRC-DIF:\n"
131 " Default is 2.\n"
132 " 0 -- No DIF Support\n"
133 " 1 -- Enable DIF for all types\n"
134 " 2 -- Enable DIF for all types, except Type 0.\n");
bad75002 135
e84067d7
DG		 136#if (IS_ENABLED(CONFIG_NVME_FC))
137int ql2xnvmeenable = 1;
138#else
139int ql2xnvmeenable;
140#endif
141module_param(ql2xnvmeenable, int, 0644);
142MODULE_PARM_DESC(ql2xnvmeenable,
143 "Enables NVME support. "
144 "0 - no NVMe. Default is Y");
145
8cb2049c 146int ql2xenablehba_err_chk = 2;
bad75002
AE		 147module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR);
148MODULE_PARM_DESC(ql2xenablehba_err_chk,
8cb2049c 149 " Enable T10-CRC-DIF Error isolation by HBA:\n"
b97f5d0b 150 " Default is 2.\n"
8cb2049c
AE		 151 " 0 -- Error isolation disabled\n"
152 " 1 -- Error isolation enabled only for DIX Type 0\n"
153 " 2 -- Error isolation enabled for all Types\n");
bad75002 154
e5896bd5 155int ql2xiidmaenable=1;
f2019cb1 156module_param(ql2xiidmaenable, int, S_IRUGO);
e5896bd5
AV		 157MODULE_PARM_DESC(ql2xiidmaenable,
158 "Enables iIDMA settings "
159 "Default is 1 - perform iIDMA. 0 - no iIDMA.");
160
d7459527
MH		 161int ql2xmqsupport = 1;
162module_param(ql2xmqsupport, int, S_IRUGO);
163MODULE_PARM_DESC(ql2xmqsupport,
164 "Enable on demand multiple queue pairs support "
165 "Default is 1 for supported. "
166 "Set it to 0 to turn off mq qpair support.");
e337d907
AV		 167
168int ql2xfwloadbin;
86e45bf6 169module_param(ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
a2b3e01d 170module_param_named(fwload, ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
e337d907 171MODULE_PARM_DESC(ql2xfwloadbin,
7c3df132
SK		 172 "Option to specify location from which to load ISP firmware:.\n"
173 " 2 -- load firmware via the request_firmware() (hotplug).\n"
e337d907
AV		 174 " interface.\n"
175 " 1 -- load firmware from flash.\n"
176 " 0 -- use default semantics.\n");
177
ae97c91e 178int ql2xetsenable;
f2019cb1 179module_param(ql2xetsenable, int, S_IRUGO);
ae97c91e
AV		 180MODULE_PARM_DESC(ql2xetsenable,
181 "Enables firmware ETS burst."
182 "Default is 0 - skip ETS enablement.");
183
6907869d 184int ql2xdbwr = 1;
86e45bf6 185module_param(ql2xdbwr, int, S_IRUGO|S_IWUSR);
a9083016 186MODULE_PARM_DESC(ql2xdbwr,
08de2844
GM		 187 "Option to specify scheme for request queue posting.\n"
188 " 0 -- Regular doorbell.\n"
189 " 1 -- CAMRAM doorbell (faster).\n");
a9083016 190
f4c496c1 191int ql2xtargetreset = 1;
f2019cb1 192module_param(ql2xtargetreset, int, S_IRUGO);
f4c496c1
GM		 193MODULE_PARM_DESC(ql2xtargetreset,
194 "Enable target reset."
195 "Default is 1 - use hw defaults.");
196
4da26e16 197int ql2xgffidenable;
f2019cb1 198module_param(ql2xgffidenable, int, S_IRUGO);
4da26e16
CD		 199MODULE_PARM_DESC(ql2xgffidenable,
200 "Enables GFF_ID checks of port type. "
201 "Default is 0 - Do not use GFF_ID information.");
a9083016 202
043dc1d7 203int ql2xasynctmfenable = 1;
f2019cb1 204module_param(ql2xasynctmfenable, int, S_IRUGO);
3822263e
MI		 205MODULE_PARM_DESC(ql2xasynctmfenable,
206 "Enables issue of TM IOCBs asynchronously via IOCB mechanism"
207 "Default is 0 - Issue TM IOCBs via mailbox mechanism.");
ed0de87c
GM		 208
209int ql2xdontresethba;
86e45bf6 210module_param(ql2xdontresethba, int, S_IRUGO|S_IWUSR);
ed0de87c 211MODULE_PARM_DESC(ql2xdontresethba,
08de2844
GM		 212 "Option to specify reset behaviour.\n"
213 " 0 (Default) -- Reset on failure.\n"
214 " 1 -- Do not reset on failure.\n");
ed0de87c 215
1abf635d
HR		 216uint64_t ql2xmaxlun = MAX_LUNS;
217module_param(ql2xmaxlun, ullong, S_IRUGO);
82515920
AV		 218MODULE_PARM_DESC(ql2xmaxlun,
219 "Defines the maximum LU number to register with the SCSI "
220 "midlayer. Default is 65535.");
221
08de2844
GM		 222int ql2xmdcapmask = 0x1F;
223module_param(ql2xmdcapmask, int, S_IRUGO);
224MODULE_PARM_DESC(ql2xmdcapmask,
225 "Set the Minidump driver capture mask level. "
6e96fa7b 226 "Default is 0x1F - Can be set to 0x3, 0x7, 0xF, 0x1F, 0x7F.");
08de2844 227
3aadff35 228int ql2xmdenable = 1;
08de2844
GM		 229module_param(ql2xmdenable, int, S_IRUGO);
230MODULE_PARM_DESC(ql2xmdenable,
231 "Enable/disable MiniDump. "
3aadff35
GM		 232 "0 - MiniDump disabled. "
233 "1 (Default) - MiniDump enabled.");
08de2844 234
b0d6cabd
HM		 235int ql2xexlogins = 0;
236module_param(ql2xexlogins, uint, S_IRUGO|S_IWUSR);
237MODULE_PARM_DESC(ql2xexlogins,
238 "Number of extended Logins. "
239 "0 (Default)- Disabled.");
240
99e1b683
QT		 241int ql2xexchoffld = 1024;
242module_param(ql2xexchoffld, uint, 0644);
2f56a7f1 243MODULE_PARM_DESC(ql2xexchoffld,
99e1b683
QT		 244 "Number of target exchanges.");
245
246int ql2xiniexchg = 1024;
247module_param(ql2xiniexchg, uint, 0644);
248MODULE_PARM_DESC(ql2xiniexchg,
249 "Number of initiator exchanges.");
2f56a7f1 250
f198cafa
HM		 251int ql2xfwholdabts = 0;
252module_param(ql2xfwholdabts, int, S_IRUGO);
253MODULE_PARM_DESC(ql2xfwholdabts,
254 "Allow FW to hold status IOCB until ABTS rsp received. "
255 "0 (Default) Do not set fw option. "
256 "1 - Set fw option to hold ABTS.");
257
41dc529a
QT		 258int ql2xmvasynctoatio = 1;
259module_param(ql2xmvasynctoatio, int, S_IRUGO|S_IWUSR);
260MODULE_PARM_DESC(ql2xmvasynctoatio,
261 "Move PUREX, ABTS RX and RIDA IOCBs to ATIOQ"
262 "0 (Default). Do not move IOCBs"
263 "1 - Move IOCBs.");
264
e4e3a2ce
QT		 265int ql2xautodetectsfp = 1;
266module_param(ql2xautodetectsfp, int, 0444);
267MODULE_PARM_DESC(ql2xautodetectsfp,
268 "Detect SFP range and set appropriate distance.\n"
269 "1 (Default): Enable\n");
270
e7240af5
HM		 271int ql2xenablemsix = 1;
272module_param(ql2xenablemsix, int, 0444);
273MODULE_PARM_DESC(ql2xenablemsix,
274 "Set to enable MSI or MSI-X interrupt mechanism.\n"
275 " Default is 1, enable MSI-X interrupt mechanism.\n"
276 " 0 -- enable traditional pin-based mechanism.\n"
277 " 1 -- enable MSI-X interrupt mechanism.\n"
278 " 2 -- enable MSI interrupt mechanism.\n");
279
9ecf0b0d
QT		 280int qla2xuseresexchforels;
281module_param(qla2xuseresexchforels, int, 0444);
282MODULE_PARM_DESC(qla2xuseresexchforels,
283 "Reserve 1/2 of emergency exchanges for ELS.\n"
284 " 0 (default): disabled");
285
1da177e4 286/*
fa2a1ce5 287 * SCSI host template entry points
1da177e4
LT		 288 */
289static int qla2xxx_slave_configure(struct scsi_device * device);
f4f051eb 290static int qla2xxx_slave_alloc(struct scsi_device *);
1e99e33a
AV		 291static int qla2xxx_scan_finished(struct Scsi_Host *, unsigned long time);
292static void qla2xxx_scan_start(struct Scsi_Host *);
f4f051eb 293static void qla2xxx_slave_destroy(struct scsi_device *);
f281233d 294static int qla2xxx_queuecommand(struct Scsi_Host *h, struct scsi_cmnd *cmd);
1da177e4
LT		 295static int qla2xxx_eh_abort(struct scsi_cmnd *);
296static int qla2xxx_eh_device_reset(struct scsi_cmnd *);
523ec773 297static int qla2xxx_eh_target_reset(struct scsi_cmnd *);
1da177e4
LT		 298static int qla2xxx_eh_bus_reset(struct scsi_cmnd *);
299static int qla2xxx_eh_host_reset(struct scsi_cmnd *);
1da177e4 300
1a2fbf18 301static void qla2x00_clear_drv_active(struct qla_hw_data *);
3491255e 302static void qla2x00_free_device(scsi_qla_host_t *);
5601236b 303static int qla2xxx_map_queues(struct Scsi_Host *shost);
e84067d7 304static void qla2x00_destroy_deferred_work(struct qla_hw_data *);
ce7e4af7 305
a5326f86 306struct scsi_host_template qla2xxx_driver_template = {
1da177e4 307 .module = THIS_MODULE,
cb63067a 308 .name = QLA2XXX_DRIVER_NAME,
a5326f86 309 .queuecommand = qla2xxx_queuecommand,
fca29703 310
b6a05c82 311 .eh_timed_out = fc_eh_timed_out,
fca29703
AV		 312 .eh_abort_handler = qla2xxx_eh_abort,
313 .eh_device_reset_handler = qla2xxx_eh_device_reset,
523ec773 314 .eh_target_reset_handler = qla2xxx_eh_target_reset,
fca29703
AV		 315 .eh_bus_reset_handler = qla2xxx_eh_bus_reset,
316 .eh_host_reset_handler = qla2xxx_eh_host_reset,
317
318 .slave_configure = qla2xxx_slave_configure,
319
320 .slave_alloc = qla2xxx_slave_alloc,
321 .slave_destroy = qla2xxx_slave_destroy,
ed677086
AV		 322 .scan_finished = qla2xxx_scan_finished,
323 .scan_start = qla2xxx_scan_start,
db5ed4df 324 .change_queue_depth = scsi_change_queue_depth,
5601236b 325 .map_queues = qla2xxx_map_queues,
fca29703
AV		 326 .this_id = -1,
327 .cmd_per_lun = 3,
328 .use_clustering = ENABLE_CLUSTERING,
329 .sg_tablesize = SG_ALL,
330
331 .max_sectors = 0xFFFF,
afb046e2 332 .shost_attrs = qla2x00_host_attrs,
2d70c103
NB		 333
334 .supported_mode = MODE_INITIATOR,
c40ecc12 335 .track_queue_depth = 1,
fca29703
AV		 336};
337
1da177e4 338static struct scsi_transport_template *qla2xxx_transport_template = NULL;
2c3dfe3f 339struct scsi_transport_template *qla2xxx_transport_vport_template = NULL;
1da177e4 340
1da177e4
LT		 341/* TODO Convert to inlines
342 *
343 * Timer routines
344 */
1da177e4 345
2c3dfe3f 346__inline__ void
8e5f4ba0 347qla2x00_start_timer(scsi_qla_host_t *vha, unsigned long interval)
1da177e4 348{
8e5f4ba0 349 timer_setup(&vha->timer, qla2x00_timer, 0);
e315cd28 350 vha->timer.expires = jiffies + interval * HZ;
e315cd28
AC		 351 add_timer(&vha->timer);
352 vha->timer_active = 1;
1da177e4
LT		 353}
354
355static inline void
e315cd28 356qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval)
1da177e4 357{
a9083016 358 /* Currently used for 82XX only. */
7c3df132
SK		 359 if (vha->device_flags & DFLG_DEV_FAILED) {
360 ql_dbg(ql_dbg_timer, vha, 0x600d,
361 "Device in a failed state, returning.\n");
a9083016 362 return;
7c3df132 363 }
a9083016 364
e315cd28 365 mod_timer(&vha->timer, jiffies + interval * HZ);
1da177e4
LT		 366}
367
a824ebb3 368static __inline__ void
e315cd28 369qla2x00_stop_timer(scsi_qla_host_t *vha)
1da177e4 370{
e315cd28
AC		 371 del_timer_sync(&vha->timer);
372 vha->timer_active = 0;
1da177e4
LT		 373}
374
1da177e4
LT		 375static int qla2x00_do_dpc(void *data);
376
377static void qla2x00_rst_aen(scsi_qla_host_t *);
378
73208dfd
AC		 379static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t,
380 struct req_que **, struct rsp_que **);
e30d1756 381static void qla2x00_free_fw_dump(struct qla_hw_data *);
e315cd28 382static void qla2x00_mem_free(struct qla_hw_data *);
d7459527
MH		 383int qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd,
384 struct qla_qpair *qpair);
1da177e4 385
1da177e4 386/* -------------------------------------------------------------------------- */
8abfa9e2
QT		 387static void qla_init_base_qpair(struct scsi_qla_host *vha, struct req_que *req,
388 struct rsp_que *rsp)
389{
390 struct qla_hw_data *ha = vha->hw;
391 rsp->qpair = ha->base_qpair;
392 rsp->req = req;
393 ha->base_qpair->req = req;
394 ha->base_qpair->rsp = rsp;
395 ha->base_qpair->vha = vha;
396 ha->base_qpair->qp_lock_ptr = &ha->hardware_lock;
397 ha->base_qpair->use_shadow_reg = IS_SHADOW_REG_CAPABLE(ha) ? 1 : 0;
398 ha->base_qpair->msix = &ha->msix_entries[QLA_MSIX_RSP_Q];
399 INIT_LIST_HEAD(&ha->base_qpair->hints_list);
400 ha->base_qpair->enable_class_2 = ql2xenableclass2;
401 /* init qpair to this cpu. Will adjust at run time. */
86531887 402 qla_cpu_update(rsp->qpair, raw_smp_processor_id());
8abfa9e2
QT		 403 ha->base_qpair->pdev = ha->pdev;
404
405 if (IS_QLA27XX(ha) || IS_QLA83XX(ha))
406 ha->base_qpair->reqq_start_iocbs = qla_83xx_start_iocbs;
407}
408
9a347ff4
CD		 409static int qla2x00_alloc_queues(struct qla_hw_data *ha, struct req_que *req,
410 struct rsp_que *rsp)
73208dfd 411{
7c3df132 412 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
6396bb22 413 ha->req_q_map = kcalloc(ha->max_req_queues, sizeof(struct req_que *),
73208dfd
AC		 414 GFP_KERNEL);
415 if (!ha->req_q_map) {
7c3df132
SK		 416 ql_log(ql_log_fatal, vha, 0x003b,
417 "Unable to allocate memory for request queue ptrs.\n");
73208dfd
AC		 418 goto fail_req_map;
419 }
420
6396bb22 421 ha->rsp_q_map = kcalloc(ha->max_rsp_queues, sizeof(struct rsp_que *),
73208dfd
AC		 422 GFP_KERNEL);
423 if (!ha->rsp_q_map) {
7c3df132
SK		 424 ql_log(ql_log_fatal, vha, 0x003c,
425 "Unable to allocate memory for response queue ptrs.\n");
73208dfd
AC		 426 goto fail_rsp_map;
427 }
d7459527 428
e326d22a
QT		 429 ha->base_qpair = kzalloc(sizeof(struct qla_qpair), GFP_KERNEL);
430 if (ha->base_qpair == NULL) {
431 ql_log(ql_log_warn, vha, 0x00e0,
432 "Failed to allocate base queue pair memory.\n");
433 goto fail_base_qpair;
434 }
435
8abfa9e2 436 qla_init_base_qpair(vha, req, rsp);
e326d22a 437
c38d1baf 438 if ((ql2xmqsupport || ql2xnvmeenable) && ha->max_qpairs) {
d7459527
MH		 439 ha->queue_pair_map = kcalloc(ha->max_qpairs, sizeof(struct qla_qpair *),
440 GFP_KERNEL);
441 if (!ha->queue_pair_map) {
442 ql_log(ql_log_fatal, vha, 0x0180,
443 "Unable to allocate memory for queue pair ptrs.\n");
444 goto fail_qpair_map;
445 }
d7459527
MH		 446 }
447
9a347ff4
CD		 448 /*
449 * Make sure we record at least the request and response queue zero in
450 * case we need to free them if part of the probe fails.
451 */
452 ha->rsp_q_map[0] = rsp;
453 ha->req_q_map[0] = req;
73208dfd
AC		 454 set_bit(0, ha->rsp_qid_map);
455 set_bit(0, ha->req_qid_map);
6a2cf8d3 456 return 0;
73208dfd 457
d7459527 458fail_qpair_map:
82de802a
QT		 459 kfree(ha->base_qpair);
460 ha->base_qpair = NULL;
461fail_base_qpair:
d7459527
MH		 462 kfree(ha->rsp_q_map);
463 ha->rsp_q_map = NULL;
73208dfd
AC		 464fail_rsp_map:
465 kfree(ha->req_q_map);
466 ha->req_q_map = NULL;
467fail_req_map:
468 return -ENOMEM;
469}
470
2afa19a9 471static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req)
73208dfd 472{
8ae6d9c7
GM		 473 if (IS_QLAFX00(ha)) {
474 if (req && req->ring_fx00)
475 dma_free_coherent(&ha->pdev->dev,
476 (req->length_fx00 + 1) * sizeof(request_t),
477 req->ring_fx00, req->dma_fx00);
478 } else if (req && req->ring)
73208dfd
AC		 479 dma_free_coherent(&ha->pdev->dev,
480 (req->length + 1) * sizeof(request_t),
481 req->ring, req->dma);
482
6d634067 483 if (req)
8d93f550 484 kfree(req->outstanding_cmds);
6d634067
BK		 485
486 kfree(req);
73208dfd
AC		 487}
488
2afa19a9
AC		 489static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp)
490{
8ae6d9c7 491 if (IS_QLAFX00(ha)) {
3f6c9be2 492 if (rsp && rsp->ring_fx00)
8ae6d9c7
GM		 493 dma_free_coherent(&ha->pdev->dev,
494 (rsp->length_fx00 + 1) * sizeof(request_t),
495 rsp->ring_fx00, rsp->dma_fx00);
496 } else if (rsp && rsp->ring) {
2afa19a9
AC		 497 dma_free_coherent(&ha->pdev->dev,
498 (rsp->length + 1) * sizeof(response_t),
499 rsp->ring, rsp->dma);
8ae6d9c7 500 }
6d634067 501 kfree(rsp);
2afa19a9
AC		 502}
503
73208dfd
AC		 504static void qla2x00_free_queues(struct qla_hw_data *ha)
505{
506 struct req_que *req;
507 struct rsp_que *rsp;
508 int cnt;
093df737 509 unsigned long flags;
73208dfd 510
82de802a
QT		 511 if (ha->queue_pair_map) {
512 kfree(ha->queue_pair_map);
513 ha->queue_pair_map = NULL;
514 }
515 if (ha->base_qpair) {
516 kfree(ha->base_qpair);
517 ha->base_qpair = NULL;
518 }
519
093df737 520 spin_lock_irqsave(&ha->hardware_lock, flags);
2afa19a9 521 for (cnt = 0; cnt < ha->max_req_queues; cnt++) {
cb43285f
QT		 522 if (!test_bit(cnt, ha->req_qid_map))
523 continue;
524
73208dfd 525 req = ha->req_q_map[cnt];
093df737
QT		 526 clear_bit(cnt, ha->req_qid_map);
527 ha->req_q_map[cnt] = NULL;
528
529 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2afa19a9 530 qla2x00_free_req_que(ha, req);
093df737 531 spin_lock_irqsave(&ha->hardware_lock, flags);
73208dfd 532 }
093df737
QT		 533 spin_unlock_irqrestore(&ha->hardware_lock, flags);
534
73208dfd
AC		 535 kfree(ha->req_q_map);
536 ha->req_q_map = NULL;
2afa19a9 537
093df737
QT		 538
539 spin_lock_irqsave(&ha->hardware_lock, flags);
2afa19a9 540 for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) {
cb43285f
QT		 541 if (!test_bit(cnt, ha->rsp_qid_map))
542 continue;
543
2afa19a9 544 rsp = ha->rsp_q_map[cnt];
c3c42394 545 clear_bit(cnt, ha->rsp_qid_map);
093df737
QT		 546 ha->rsp_q_map[cnt] = NULL;
547 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2afa19a9 548 qla2x00_free_rsp_que(ha, rsp);
093df737 549 spin_lock_irqsave(&ha->hardware_lock, flags);
2afa19a9 550 }
093df737
QT		 551 spin_unlock_irqrestore(&ha->hardware_lock, flags);
552
2afa19a9
AC		 553 kfree(ha->rsp_q_map);
554 ha->rsp_q_map = NULL;
73208dfd
AC		 555}
556
1da177e4 557static char *
e315cd28 558qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str)
1da177e4 559{
e315cd28 560 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 561 static char *pci_bus_modes[] = {
562 "33", "66", "100", "133",
563 };
564 uint16_t pci_bus;
565
566 strcpy(str, "PCI");
567 pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9;
568 if (pci_bus) {
569 strcat(str, "-X (");
570 strcat(str, pci_bus_modes[pci_bus]);
571 } else {
572 pci_bus = (ha->pci_attr & BIT_8) >> 8;
573 strcat(str, " (");
574 strcat(str, pci_bus_modes[pci_bus]);
575 }
576 strcat(str, " MHz)");
577
578 return (str);
579}
580
fca29703 581static char *
e315cd28 582qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str)
fca29703
AV		 583{
584 static char *pci_bus_modes[] = { "33", "66", "100", "133", };
e315cd28 585 struct qla_hw_data *ha = vha->hw;
fca29703 586 uint32_t pci_bus;
fca29703 587
62a276f8 588 if (pci_is_pcie(ha->pdev)) {
fca29703 589 char lwstr[6];
62a276f8 590 uint32_t lstat, lspeed, lwidth;
fca29703 591
62a276f8
BH		 592 pcie_capability_read_dword(ha->pdev, PCI_EXP_LNKCAP, &lstat);
593 lspeed = lstat & PCI_EXP_LNKCAP_SLS;
594 lwidth = (lstat & PCI_EXP_LNKCAP_MLW) >> 4;
fca29703
AV		 595
596 strcpy(str, "PCIe (");
49300af7
SK		 597 switch (lspeed) {
598 case 1:
c87a0d8c 599 strcat(str, "2.5GT/s ");
49300af7
SK		 600 break;
601 case 2:
c87a0d8c 602 strcat(str, "5.0GT/s ");
49300af7
SK		 603 break;
604 case 3:
605 strcat(str, "8.0GT/s ");
606 break;
607 default:
fca29703 608 strcat(str, "<unknown> ");
49300af7
SK		 609 break;
610 }
fca29703
AV		 611 snprintf(lwstr, sizeof(lwstr), "x%d)", lwidth);
612 strcat(str, lwstr);
613
614 return str;
615 }
616
617 strcpy(str, "PCI");
618 pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8;
619 if (pci_bus == 0 || pci_bus == 8) {
620 strcat(str, " (");
621 strcat(str, pci_bus_modes[pci_bus >> 3]);
622 } else {
623 strcat(str, "-X ");
624 if (pci_bus & BIT_2)
625 strcat(str, "Mode 2");
626 else
627 strcat(str, "Mode 1");
628 strcat(str, " (");
629 strcat(str, pci_bus_modes[pci_bus & ~BIT_2]);
630 }
631 strcat(str, " MHz)");
632
633 return str;
634}
635
e5f82ab8 636static char *
df57caba 637qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
1da177e4
LT		 638{
639 char un_str[10];
e315cd28 640 struct qla_hw_data *ha = vha->hw;
fa2a1ce5 641
df57caba
HM		 642 snprintf(str, size, "%d.%02d.%02d ", ha->fw_major_version,
643 ha->fw_minor_version, ha->fw_subminor_version);
1da177e4
LT		 644
645 if (ha->fw_attributes & BIT_9) {
646 strcat(str, "FLX");
647 return (str);
648 }
649
650 switch (ha->fw_attributes & 0xFF) {
651 case 0x7:
652 strcat(str, "EF");
653 break;
654 case 0x17:
655 strcat(str, "TP");
656 break;
657 case 0x37:
658 strcat(str, "IP");
659 break;
660 case 0x77:
661 strcat(str, "VI");
662 break;
663 default:
664 sprintf(un_str, "(%x)", ha->fw_attributes);
665 strcat(str, un_str);
666 break;
667 }
668 if (ha->fw_attributes & 0x100)
669 strcat(str, "X");
670
671 return (str);
672}
673
e5f82ab8 674static char *
df57caba 675qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
fca29703 676{
e315cd28 677 struct qla_hw_data *ha = vha->hw;
f0883ac6 678
df57caba 679 snprintf(str, size, "%d.%02d.%02d (%x)", ha->fw_major_version,
3a03eb79 680 ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes);
fca29703 681 return str;
fca29703
AV		 682}
683
9ba56b95 684void
25ff6af1 685qla2x00_sp_free_dma(void *ptr)
fca29703 686{
25ff6af1
JC		 687 srb_t *sp = ptr;
688 struct qla_hw_data *ha = sp->vha->hw;
9ba56b95 689 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
9ba56b95 690 void *ctx = GET_CMD_CTX_SP(sp);
fca29703 691
9ba56b95
GM		 692 if (sp->flags & SRB_DMA_VALID) {
693 scsi_dma_unmap(cmd);
694 sp->flags &= ~SRB_DMA_VALID;
7c3df132 695 }
fca29703 696
9ba56b95
GM		 697 if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
698 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
699 scsi_prot_sg_count(cmd), cmd->sc_data_direction);
700 sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
701 }
702
d5ff0eed
JC		 703 if (!ctx)
704 goto end;
705
9ba56b95
GM		 706 if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
707 /* List assured to be having elements */
d5ff0eed 708 qla2x00_clean_dsd_pool(ha, ctx);
9ba56b95
GM		 709 sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
710 }
711
712 if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
d5ff0eed
JC		 713 struct crc_context *ctx0 = ctx;
714
715 dma_pool_free(ha->dl_dma_pool, ctx0, ctx0->crc_ctx_dma);
9ba56b95
GM		 716 sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
717 }
718
719 if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
d5ff0eed 720 struct ct6_dsd *ctx1 = ctx;
fca29703 721
9ba56b95 722 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd,
d5ff0eed 723 ctx1->fcp_cmnd_dma);
9ba56b95
GM		 724 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list);
725 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt;
726 ha->gbl_dsd_avail += ctx1->dsd_use_cnt;
727 mempool_free(ctx1, ha->ctx_mempool);
9ba56b95
GM		 728 }
729
d5ff0eed 730end:
6fcd98fd 731 if (sp->type != SRB_NVME_CMD && sp->type != SRB_NVME_LS) {
7401bc18
DG		 732 CMD_SP(cmd) = NULL;
733 qla2x00_rel_sp(sp);
734 }
9ba56b95
GM		 735}
736
d7459527 737void
25ff6af1 738qla2x00_sp_compl(void *ptr, int res)
9ba56b95 739{
25ff6af1 740 srb_t *sp = ptr;
9ba56b95
GM		 741 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
742
743 cmd->result = res;
744
745 if (atomic_read(&sp->ref_count) == 0) {
25ff6af1 746 ql_dbg(ql_dbg_io, sp->vha, 0x3015,
9ba56b95
GM		 747 "SP reference-count to ZERO -- sp=%p cmd=%p.\n",
748 sp, GET_CMD_SP(sp));
749 if (ql2xextended_error_logging & ql_dbg_io)
8fbdac8c 750 WARN_ON(atomic_read(&sp->ref_count) == 0);
9ba56b95
GM		 751 return;
752 }
753 if (!atomic_dec_and_test(&sp->ref_count))
754 return;
755
f3caa990 756 sp->free(sp);
9ba56b95 757 cmd->scsi_done(cmd);
fca29703
AV		 758}
759
d7459527 760void
25ff6af1 761qla2xxx_qpair_sp_free_dma(void *ptr)
d7459527
MH		 762{
763 srb_t *sp = (srb_t *)ptr;
764 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
765 struct qla_hw_data *ha = sp->fcport->vha->hw;
766 void *ctx = GET_CMD_CTX_SP(sp);
767
768 if (sp->flags & SRB_DMA_VALID) {
769 scsi_dma_unmap(cmd);
770 sp->flags &= ~SRB_DMA_VALID;
771 }
772
773 if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
774 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
775 scsi_prot_sg_count(cmd), cmd->sc_data_direction);
776 sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
777 }
778
d5ff0eed
JC		 779 if (!ctx)
780 goto end;
781
d7459527
MH		 782 if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
783 /* List assured to be having elements */
d5ff0eed 784 qla2x00_clean_dsd_pool(ha, ctx);
d7459527
MH		 785 sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
786 }
787
788 if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
d5ff0eed
JC		 789 struct crc_context *ctx0 = ctx;
790
791 dma_pool_free(ha->dl_dma_pool, ctx, ctx0->crc_ctx_dma);
d7459527
MH		 792 sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
793 }
794
795 if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
d5ff0eed 796 struct ct6_dsd *ctx1 = ctx;
d7459527
MH		 797 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd,
798 ctx1->fcp_cmnd_dma);
799 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list);
800 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt;
801 ha->gbl_dsd_avail += ctx1->dsd_use_cnt;
802 mempool_free(ctx1, ha->ctx_mempool);
803 }
d5ff0eed 804end:
d7459527
MH		 805 CMD_SP(cmd) = NULL;
806 qla2xxx_rel_qpair_sp(sp->qpair, sp);
807}
808
809void
25ff6af1 810qla2xxx_qpair_sp_compl(void *ptr, int res)
d7459527 811{
25ff6af1 812 srb_t *sp = ptr;
d7459527
MH		 813 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
814
815 cmd->result = res;
816
817 if (atomic_read(&sp->ref_count) == 0) {
818 ql_dbg(ql_dbg_io, sp->fcport->vha, 0x3079,
819 "SP reference-count to ZERO -- sp=%p cmd=%p.\n",
820 sp, GET_CMD_SP(sp));
821 if (ql2xextended_error_logging & ql_dbg_io)
822 WARN_ON(atomic_read(&sp->ref_count) == 0);
823 return;
824 }
825 if (!atomic_dec_and_test(&sp->ref_count))
826 return;
827
f3caa990 828 sp->free(sp);
d7459527
MH		 829 cmd->scsi_done(cmd);
830}
831
8ae6d9c7
GM		 832/* If we are SP1 here, we need to still take and release the host_lock as SP1
833 * does not have the changes necessary to avoid taking host->host_lock.
834 */
1da177e4 835static int
f5e3e40b 836qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
fca29703 837{
134ae078 838 scsi_qla_host_t *vha = shost_priv(host);
fca29703 839 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
19a7b4ae 840 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
e315cd28
AC		 841 struct qla_hw_data *ha = vha->hw;
842 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
fca29703
AV		 843 srb_t *sp;
844 int rval;
5601236b
MH		 845 struct qla_qpair *qpair = NULL;
846 uint32_t tag;
847 uint16_t hwq;
fca29703 848
04dfaa53
MFO		 849 if (unlikely(test_bit(UNLOADING, &base_vha->dpc_flags))) {
850 cmd->result = DID_NO_CONNECT << 16;
851 goto qc24_fail_command;
852 }
853
5601236b
MH		 854 if (ha->mqenable) {
855 if (shost_use_blk_mq(vha->host)) {
856 tag = blk_mq_unique_tag(cmd->request);
857 hwq = blk_mq_unique_tag_to_hwq(tag);
858 qpair = ha->queue_pair_map[hwq];
859 } else if (vha->vp_idx && vha->qpair) {
860 qpair = vha->qpair;
861 }
862
863 if (qpair)
864 return qla2xxx_mqueuecommand(host, cmd, qpair);
d7459527
MH		 865 }
866
85880801 867 if (ha->flags.eeh_busy) {
7c3df132 868 if (ha->flags.pci_channel_io_perm_failure) {
5f28d2d7 869 ql_dbg(ql_dbg_aer, vha, 0x9010,
7c3df132
SK		 870 "PCI Channel IO permanent failure, exiting "
871 "cmd=%p.\n", cmd);
b9b12f73 872 cmd->result = DID_NO_CONNECT << 16;
7c3df132 873 } else {
5f28d2d7 874 ql_dbg(ql_dbg_aer, vha, 0x9011,
7c3df132 875 "EEH_Busy, Requeuing the cmd=%p.\n", cmd);
85880801 876 cmd->result = DID_REQUEUE << 16;
7c3df132 877 }
14e660e6
SJ		 878 goto qc24_fail_command;
879 }
880
19a7b4ae
JSEC		 881 rval = fc_remote_port_chkready(rport);
882 if (rval) {
883 cmd->result = rval;
5f28d2d7 884 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3003,
7c3df132
SK		 885 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
886 cmd, rval);
fca29703
AV		 887 goto qc24_fail_command;
888 }
889
bad75002
AE		 890 if (!vha->flags.difdix_supported &&
891 scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) {
7c3df132
SK		 892 ql_dbg(ql_dbg_io, vha, 0x3004,
893 "DIF Cap not reg, fail DIF capable cmd's:%p.\n",
894 cmd);
bad75002
AE		 895 cmd->result = DID_NO_CONNECT << 16;
896 goto qc24_fail_command;
897 }
aa651be8
CD		 898
899 if (!fcport) {
900 cmd->result = DID_NO_CONNECT << 16;
901 goto qc24_fail_command;
902 }
903
fca29703
AV		 904 if (atomic_read(&fcport->state) != FCS_ONLINE) {
905 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
38170fa8 906 atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
7c3df132
SK		 907 ql_dbg(ql_dbg_io, vha, 0x3005,
908 "Returning DNC, fcport_state=%d loop_state=%d.\n",
909 atomic_read(&fcport->state),
910 atomic_read(&base_vha->loop_state));
fca29703
AV		 911 cmd->result = DID_NO_CONNECT << 16;
912 goto qc24_fail_command;
913 }
7b594131 914 goto qc24_target_busy;
fca29703
AV		 915 }
916
e05fe292
CD		 917 /*
918 * Return target busy if we've received a non-zero retry_delay_timer
919 * in a FCP_RSP.
920 */
975f7d46
BP		 921 if (fcport->retry_delay_timestamp == 0) {
922 /* retry delay not set */
923 } else if (time_after(jiffies, fcport->retry_delay_timestamp))
e05fe292
CD		 924 fcport->retry_delay_timestamp = 0;
925 else
926 goto qc24_target_busy;
927
b00ee7d7 928 sp = qla2x00_get_sp(vha, fcport, GFP_ATOMIC);
50280c01 929 if (!sp)
f5e3e40b 930 goto qc24_host_busy;
fca29703 931
9ba56b95
GM		 932 sp->u.scmd.cmd = cmd;
933 sp->type = SRB_SCSI_CMD;
934 atomic_set(&sp->ref_count, 1);
935 CMD_SP(cmd) = (void *)sp;
936 sp->free = qla2x00_sp_free_dma;
937 sp->done = qla2x00_sp_compl;
938
e315cd28 939 rval = ha->isp_ops->start_scsi(sp);
7c3df132 940 if (rval != QLA_SUCCESS) {
53016ed3 941 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3013,
7c3df132 942 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
fca29703 943 goto qc24_host_busy_free_sp;
7c3df132 944 }
fca29703 945
fca29703
AV		 946 return 0;
947
948qc24_host_busy_free_sp:
f3caa990 949 sp->free(sp);
fca29703 950
f5e3e40b 951qc24_host_busy:
fca29703
AV		 952 return SCSI_MLQUEUE_HOST_BUSY;
953
7b594131
MC		 954qc24_target_busy:
955 return SCSI_MLQUEUE_TARGET_BUSY;
956
fca29703 957qc24_fail_command:
f5e3e40b 958 cmd->scsi_done(cmd);
fca29703
AV		 959
960 return 0;
961}
962
d7459527
MH		 963/* For MQ supported I/O */
964int
965qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd,
966 struct qla_qpair *qpair)
967{
968 scsi_qla_host_t *vha = shost_priv(host);
969 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
970 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
971 struct qla_hw_data *ha = vha->hw;
972 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
973 srb_t *sp;
974 int rval;
975
976 rval = fc_remote_port_chkready(rport);
977 if (rval) {
978 cmd->result = rval;
979 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3076,
980 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
981 cmd, rval);
982 goto qc24_fail_command;
983 }
984
985 if (!fcport) {
986 cmd->result = DID_NO_CONNECT << 16;
987 goto qc24_fail_command;
988 }
989
990 if (atomic_read(&fcport->state) != FCS_ONLINE) {
991 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
992 atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
993 ql_dbg(ql_dbg_io, vha, 0x3077,
994 "Returning DNC, fcport_state=%d loop_state=%d.\n",
995 atomic_read(&fcport->state),
996 atomic_read(&base_vha->loop_state));
997 cmd->result = DID_NO_CONNECT << 16;
998 goto qc24_fail_command;
999 }
1000 goto qc24_target_busy;
1001 }
1002
1003 /*
1004 * Return target busy if we've received a non-zero retry_delay_timer
1005 * in a FCP_RSP.
1006 */
1007 if (fcport->retry_delay_timestamp == 0) {
1008 /* retry delay not set */
1009 } else if (time_after(jiffies, fcport->retry_delay_timestamp))
1010 fcport->retry_delay_timestamp = 0;
1011 else
1012 goto qc24_target_busy;
1013
1014 sp = qla2xxx_get_qpair_sp(qpair, fcport, GFP_ATOMIC);
1015 if (!sp)
1016 goto qc24_host_busy;
1017
1018 sp->u.scmd.cmd = cmd;
1019 sp->type = SRB_SCSI_CMD;
1020 atomic_set(&sp->ref_count, 1);
1021 CMD_SP(cmd) = (void *)sp;
1022 sp->free = qla2xxx_qpair_sp_free_dma;
1023 sp->done = qla2xxx_qpair_sp_compl;
1024 sp->qpair = qpair;
1025
1026 rval = ha->isp_ops->start_scsi_mq(sp);
1027 if (rval != QLA_SUCCESS) {
1028 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3078,
1029 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
1030 if (rval == QLA_INTERFACE_ERROR)
1031 goto qc24_fail_command;
1032 goto qc24_host_busy_free_sp;
1033 }
1034
1035 return 0;
1036
1037qc24_host_busy_free_sp:
f3caa990 1038 sp->free(sp);
d7459527
MH		 1039
1040qc24_host_busy:
1041 return SCSI_MLQUEUE_HOST_BUSY;
1042
1043qc24_target_busy:
1044 return SCSI_MLQUEUE_TARGET_BUSY;
1045
1046qc24_fail_command:
1047 cmd->scsi_done(cmd);
1048
1049 return 0;
1050}
1051
1da177e4
LT		 1052/*
1053 * qla2x00_eh_wait_on_command
1054 * Waits for the command to be returned by the Firmware for some
1055 * max time.
1056 *
1057 * Input:
1da177e4 1058 * cmd = Scsi Command to wait on.
1da177e4
LT		 1059 *
1060 * Return:
1061 * Not Found : 0
1062 * Found : 1
1063 */
1064static int
e315cd28 1065qla2x00_eh_wait_on_command(struct scsi_cmnd *cmd)
1da177e4 1066{
fe74c71f 1067#define ABORT_POLLING_PERIOD 1000
478c3b03 1068#define ABORT_WAIT_ITER ((2 * 1000) / (ABORT_POLLING_PERIOD))
f4f051eb 1069 unsigned long wait_iter = ABORT_WAIT_ITER;
85880801
AV		 1070 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1071 struct qla_hw_data *ha = vha->hw;
f4f051eb 1072 int ret = QLA_SUCCESS;
1da177e4 1073
85880801 1074 if (unlikely(pci_channel_offline(ha->pdev)) || ha->flags.eeh_busy) {
7c3df132
SK		 1075 ql_dbg(ql_dbg_taskm, vha, 0x8005,
1076 "Return:eh_wait.\n");
85880801
AV		 1077 return ret;
1078 }
1079
d970432c 1080 while (CMD_SP(cmd) && wait_iter--) {
fe74c71f 1081 msleep(ABORT_POLLING_PERIOD);
f4f051eb 1082 }
1083 if (CMD_SP(cmd))
1084 ret = QLA_FUNCTION_FAILED;
1da177e4 1085
f4f051eb 1086 return ret;
1da177e4
LT		 1087}
1088
1089/*
1090 * qla2x00_wait_for_hba_online
fa2a1ce5 1091 * Wait till the HBA is online after going through
1da177e4
LT		 1092 * <= MAX_RETRIES_OF_ISP_ABORT or
1093 * finally HBA is disabled ie marked offline
1094 *
1095 * Input:
1096 * ha - pointer to host adapter structure
fa2a1ce5
AV		 1097 *
1098 * Note:
1da177e4
LT		 1099 * Does context switching-Release SPIN_LOCK
1100 * (if any) before calling this routine.
1101 *
1102 * Return:
1103 * Success (Adapter is online) : 0
1104 * Failed (Adapter is offline/disabled) : 1
1105 */
854165f4 1106int
e315cd28 1107qla2x00_wait_for_hba_online(scsi_qla_host_t *vha)
1da177e4 1108{
fca29703
AV		 1109 int return_status;
1110 unsigned long wait_online;
e315cd28
AC		 1111 struct qla_hw_data *ha = vha->hw;
1112 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4 1113
fa2a1ce5 1114 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ);
e315cd28
AC		 1115 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
1116 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
1117 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
1118 ha->dpc_active) && time_before(jiffies, wait_online)) {
1da177e4
LT		 1119
1120 msleep(1000);
1121 }
e315cd28 1122 if (base_vha->flags.online)
fa2a1ce5 1123 return_status = QLA_SUCCESS;
1da177e4
LT		 1124 else
1125 return_status = QLA_FUNCTION_FAILED;
1126
1da177e4
LT		 1127 return (return_status);
1128}
1129
726b8548
QT		 1130static inline int test_fcport_count(scsi_qla_host_t *vha)
1131{
1132 struct qla_hw_data *ha = vha->hw;
1133 unsigned long flags;
1134 int res;
1135
1136 spin_lock_irqsave(&ha->tgt.sess_lock, flags);
83548fe2
QT		 1137 ql_dbg(ql_dbg_init, vha, 0x00ec,
1138 "tgt %p, fcport_count=%d\n",
1139 vha, vha->fcport_count);
726b8548
QT		 1140 res = (vha->fcport_count == 0);
1141 spin_unlock_irqrestore(&ha->tgt.sess_lock, flags);
1142
1143 return res;
1144}
1145
1146/*
1147 * qla2x00_wait_for_sess_deletion can only be called from remove_one.
1148 * it has dependency on UNLOADING flag to stop device discovery
1149 */
1150static void
1151qla2x00_wait_for_sess_deletion(scsi_qla_host_t *vha)
1152{
1153 qla2x00_mark_all_devices_lost(vha, 0);
1154
b85e0957 1155 wait_event_timeout(vha->fcport_waitQ, test_fcport_count(vha), 10*HZ);
726b8548
QT		 1156}
1157
86fbee86 1158/*
638a1a01
SC		 1159 * qla2x00_wait_for_hba_ready
1160 * Wait till the HBA is ready before doing driver unload
86fbee86
LC		 1161 *
1162 * Input:
1163 * ha - pointer to host adapter structure
1164 *
1165 * Note:
1166 * Does context switching-Release SPIN_LOCK
1167 * (if any) before calling this routine.
1168 *
86fbee86 1169 */
638a1a01
SC		 1170static void
1171qla2x00_wait_for_hba_ready(scsi_qla_host_t *vha)
86fbee86 1172{
86fbee86 1173 struct qla_hw_data *ha = vha->hw;
783e0dc4 1174 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
86fbee86 1175
1d483901
DC		 1176 while ((qla2x00_reset_active(vha) || ha->dpc_active ||
1177 ha->flags.mbox_busy) ||
1178 test_bit(FX00_RESET_RECOVERY, &vha->dpc_flags) ||
1179 test_bit(FX00_TARGET_SCAN, &vha->dpc_flags)) {
1180 if (test_bit(UNLOADING, &base_vha->dpc_flags))
1181 break;
86fbee86 1182 msleep(1000);
783e0dc4 1183 }
86fbee86
LC		 1184}
1185
2533cf67
LC		 1186int
1187qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha)
1188{
1189 int return_status;
1190 unsigned long wait_reset;
1191 struct qla_hw_data *ha = vha->hw;
1192 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1193
1194 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ);
1195 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
1196 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
1197 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
1198 ha->dpc_active) && time_before(jiffies, wait_reset)) {
1199
1200 msleep(1000);
1201
1202 if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) &&
1203 ha->flags.chip_reset_done)
1204 break;
1205 }
1206 if (ha->flags.chip_reset_done)
1207 return_status = QLA_SUCCESS;
1208 else
1209 return_status = QLA_FUNCTION_FAILED;
1210
1211 return return_status;
1212}
1213
083a469d
GM		 1214static void
1215sp_get(struct srb *sp)
1216{
1217 atomic_inc(&sp->ref_count);
1218}
1219
a465537a
SC		 1220#define ISP_REG_DISCONNECT 0xffffffffU
1221/**************************************************************************
1222* qla2x00_isp_reg_stat
1223*
1224* Description:
1225* Read the host status register of ISP before aborting the command.
1226*
1227* Input:
1228* ha = pointer to host adapter structure.
1229*
1230*
1231* Returns:
1232* Either true or false.
1233*
1234* Note: Return true if there is register disconnect.
1235**************************************************************************/
1236static inline
1237uint32_t qla2x00_isp_reg_stat(struct qla_hw_data *ha)
1238{
1239 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
bf6061b1 1240 struct device_reg_82xx __iomem *reg82 = &ha->iobase->isp82;
a465537a 1241
bf6061b1
SC		 1242 if (IS_P3P_TYPE(ha))
1243 return ((RD_REG_DWORD(&reg82->host_int)) == ISP_REG_DISCONNECT);
1244 else
1245 return ((RD_REG_DWORD(&reg->host_status)) ==
1246 ISP_REG_DISCONNECT);
a465537a
SC		 1247}
1248
1da177e4
LT		 1249/**************************************************************************
1250* qla2xxx_eh_abort
1251*
1252* Description:
1253* The abort function will abort the specified command.
1254*
1255* Input:
1256* cmd = Linux SCSI command packet to be aborted.
1257*
1258* Returns:
1259* Either SUCCESS or FAILED.
1260*
1261* Note:
2ea00202 1262* Only return FAILED if command not returned by firmware.
1da177e4 1263**************************************************************************/
e5f82ab8 1264static int
1da177e4
LT		 1265qla2xxx_eh_abort(struct scsi_cmnd *cmd)
1266{
e315cd28 1267 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
f4f051eb 1268 srb_t *sp;
4e98d3b8 1269 int ret;
9cb78c16
HR		 1270 unsigned int id;
1271 uint64_t lun;
18e144d3 1272 unsigned long flags;
f934c9d0 1273 int rval, wait = 0;
e315cd28 1274 struct qla_hw_data *ha = vha->hw;
1da177e4 1275
a465537a
SC		 1276 if (qla2x00_isp_reg_stat(ha)) {
1277 ql_log(ql_log_info, vha, 0x8042,
1278 "PCI/Register disconnect, exiting.\n");
1279 return FAILED;
1280 }
f4f051eb 1281 if (!CMD_SP(cmd))
2ea00202 1282 return SUCCESS;
1da177e4 1283
4e98d3b8
AV		 1284 ret = fc_block_scsi_eh(cmd);
1285 if (ret != 0)
1286 return ret;
1287 ret = SUCCESS;
1288
f4f051eb 1289 id = cmd->device->id;
1290 lun = cmd->device->lun;
1da177e4 1291
e315cd28 1292 spin_lock_irqsave(&ha->hardware_lock, flags);
170babc3
MC		 1293 sp = (srb_t *) CMD_SP(cmd);
1294 if (!sp) {
1295 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1296 return SUCCESS;
1297 }
1da177e4 1298
7c3df132 1299 ql_dbg(ql_dbg_taskm, vha, 0x8002,
c7bc4cae
CD		 1300 "Aborting from RISC nexus=%ld:%d:%llu sp=%p cmd=%p handle=%x\n",
1301 vha->host_no, id, lun, sp, cmd, sp->handle);
17d98630 1302
170babc3
MC		 1303 /* Get a reference to the sp and drop the lock.*/
1304 sp_get(sp);
083a469d 1305
e315cd28 1306 spin_unlock_irqrestore(&ha->hardware_lock, flags);
f934c9d0
CD		 1307 rval = ha->isp_ops->abort_command(sp);
1308 if (rval) {
96219424 1309 if (rval == QLA_FUNCTION_PARAMETER_ERROR)
f934c9d0 1310 ret = SUCCESS;
96219424 1311 else
f934c9d0
CD		 1312 ret = FAILED;
1313
7c3df132 1314 ql_dbg(ql_dbg_taskm, vha, 0x8003,
f934c9d0 1315 "Abort command mbx failed cmd=%p, rval=%x.\n", cmd, rval);
170babc3 1316 } else {
7c3df132 1317 ql_dbg(ql_dbg_taskm, vha, 0x8004,
cfb0919c 1318 "Abort command mbx success cmd=%p.\n", cmd);
170babc3
MC		 1319 wait = 1;
1320 }
75942064
SK		 1321
1322 spin_lock_irqsave(&ha->hardware_lock, flags);
25ff6af1 1323 sp->done(sp, 0);
75942064 1324 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1da177e4 1325
bc91ade9
CD		 1326 /* Did the command return during mailbox execution? */
1327 if (ret == FAILED && !CMD_SP(cmd))
1328 ret = SUCCESS;
1329
f4f051eb 1330 /* Wait for the command to be returned. */
2ea00202 1331 if (wait) {
e315cd28 1332 if (qla2x00_eh_wait_on_command(cmd) != QLA_SUCCESS) {
7c3df132 1333 ql_log(ql_log_warn, vha, 0x8006,
cfb0919c 1334 "Abort handler timed out cmd=%p.\n", cmd);
2ea00202 1335 ret = FAILED;
f4f051eb 1336 }
1da177e4 1337 }
1da177e4 1338
7c3df132 1339 ql_log(ql_log_info, vha, 0x801c,
9cb78c16 1340 "Abort command issued nexus=%ld:%d:%llu -- %d %x.\n",
cfb0919c 1341 vha->host_no, id, lun, wait, ret);
1da177e4 1342
f4f051eb 1343 return ret;
1344}
1da177e4 1345
4d78c973 1346int
e315cd28 1347qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t,
9cb78c16 1348 uint64_t l, enum nexus_wait_type type)
f4f051eb 1349{
17d98630 1350 int cnt, match, status;
18e144d3 1351 unsigned long flags;
e315cd28 1352 struct qla_hw_data *ha = vha->hw;
73208dfd 1353 struct req_que *req;
4d78c973 1354 srb_t *sp;
9ba56b95 1355 struct scsi_cmnd *cmd;
1da177e4 1356
523ec773 1357 status = QLA_SUCCESS;
17d98630 1358
e315cd28 1359 spin_lock_irqsave(&ha->hardware_lock, flags);
67c2e93a 1360 req = vha->req;
17d98630 1361 for (cnt = 1; status == QLA_SUCCESS &&
8d93f550 1362 cnt < req->num_outstanding_cmds; cnt++) {
17d98630
AC		 1363 sp = req->outstanding_cmds[cnt];
1364 if (!sp)
523ec773 1365 continue;
9ba56b95 1366 if (sp->type != SRB_SCSI_CMD)
cf53b069 1367 continue;
25ff6af1 1368 if (vha->vp_idx != sp->vha->vp_idx)
17d98630
AC		 1369 continue;
1370 match = 0;
9ba56b95 1371 cmd = GET_CMD_SP(sp);
17d98630
AC		 1372 switch (type) {
1373 case WAIT_HOST:
1374 match = 1;
1375 break;
1376 case WAIT_TARGET:
9ba56b95 1377 match = cmd->device->id == t;
17d98630
AC		 1378 break;
1379 case WAIT_LUN:
9ba56b95
GM		 1380 match = (cmd->device->id == t &&
1381 cmd->device->lun == l);
17d98630 1382 break;
73208dfd 1383 }
17d98630
AC		 1384 if (!match)
1385 continue;
1386
1387 spin_unlock_irqrestore(&ha->hardware_lock, flags);
9ba56b95 1388 status = qla2x00_eh_wait_on_command(cmd);
17d98630 1389 spin_lock_irqsave(&ha->hardware_lock, flags);
1da177e4 1390 }
e315cd28 1391 spin_unlock_irqrestore(&ha->hardware_lock, flags);
523ec773
AV		 1392
1393 return status;
1da177e4
LT		 1394}
1395
523ec773
AV		 1396static char *reset_errors[] = {
1397 "HBA not online",
1398 "HBA not ready",
1399 "Task management failed",
1400 "Waiting for command completions",
1401};
1da177e4 1402
e5f82ab8 1403static int
523ec773 1404__qla2xxx_eh_generic_reset(char *name, enum nexus_wait_type type,
9cb78c16 1405 struct scsi_cmnd *cmd, int (*do_reset)(struct fc_port *, uint64_t, int))
1da177e4 1406{
e315cd28 1407 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
bdf79621 1408 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
523ec773 1409 int err;
1da177e4 1410
7c3df132 1411 if (!fcport) {
523ec773 1412 return FAILED;
7c3df132 1413 }
1da177e4 1414
4e98d3b8
AV		 1415 err = fc_block_scsi_eh(cmd);
1416 if (err != 0)
1417 return err;
1418
7c3df132 1419 ql_log(ql_log_info, vha, 0x8009,
9cb78c16 1420 "%s RESET ISSUED nexus=%ld:%d:%llu cmd=%p.\n", name, vha->host_no,
7c3df132 1421 cmd->device->id, cmd->device->lun, cmd);
1da177e4 1422
523ec773 1423 err = 0;
7c3df132
SK		 1424 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1425 ql_log(ql_log_warn, vha, 0x800a,
1426 "Wait for hba online failed for cmd=%p.\n", cmd);
523ec773 1427 goto eh_reset_failed;
7c3df132 1428 }
523ec773 1429 err = 2;
2afa19a9 1430 if (do_reset(fcport, cmd->device->lun, cmd->request->cpu + 1)
7c3df132
SK		 1431 != QLA_SUCCESS) {
1432 ql_log(ql_log_warn, vha, 0x800c,
1433 "do_reset failed for cmd=%p.\n", cmd);
523ec773 1434 goto eh_reset_failed;
7c3df132 1435 }
523ec773 1436 err = 3;
e315cd28 1437 if (qla2x00_eh_wait_for_pending_commands(vha, cmd->device->id,
7c3df132
SK		 1438 cmd->device->lun, type) != QLA_SUCCESS) {
1439 ql_log(ql_log_warn, vha, 0x800d,
d6a03581 1440 "wait for pending cmds failed for cmd=%p.\n", cmd);
523ec773 1441 goto eh_reset_failed;
7c3df132 1442 }
523ec773 1443
7c3df132 1444 ql_log(ql_log_info, vha, 0x800e,
9cb78c16 1445 "%s RESET SUCCEEDED nexus:%ld:%d:%llu cmd=%p.\n", name,
cfb0919c 1446 vha->host_no, cmd->device->id, cmd->device->lun, cmd);
523ec773
AV		 1447
1448 return SUCCESS;
1449
4d78c973 1450eh_reset_failed:
7c3df132 1451 ql_log(ql_log_info, vha, 0x800f,
9cb78c16 1452 "%s RESET FAILED: %s nexus=%ld:%d:%llu cmd=%p.\n", name,
cfb0919c
CD		 1453 reset_errors[err], vha->host_no, cmd->device->id, cmd->device->lun,
1454 cmd);
523ec773
AV		 1455 return FAILED;
1456}
1da177e4 1457
523ec773
AV		 1458static int
1459qla2xxx_eh_device_reset(struct scsi_cmnd *cmd)
1460{
e315cd28
AC		 1461 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1462 struct qla_hw_data *ha = vha->hw;
1da177e4 1463
a465537a
SC		 1464 if (qla2x00_isp_reg_stat(ha)) {
1465 ql_log(ql_log_info, vha, 0x803e,
1466 "PCI/Register disconnect, exiting.\n");
1467 return FAILED;
1468 }
1469
523ec773
AV		 1470 return __qla2xxx_eh_generic_reset("DEVICE", WAIT_LUN, cmd,
1471 ha->isp_ops->lun_reset);
1da177e4
LT		 1472}
1473
1da177e4 1474static int
523ec773 1475qla2xxx_eh_target_reset(struct scsi_cmnd *cmd)
1da177e4 1476{
e315cd28
AC		 1477 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1478 struct qla_hw_data *ha = vha->hw;
1da177e4 1479
a465537a
SC		 1480 if (qla2x00_isp_reg_stat(ha)) {
1481 ql_log(ql_log_info, vha, 0x803f,
1482 "PCI/Register disconnect, exiting.\n");
1483 return FAILED;
1484 }
1485
523ec773
AV		 1486 return __qla2xxx_eh_generic_reset("TARGET", WAIT_TARGET, cmd,
1487 ha->isp_ops->target_reset);
1da177e4
LT		 1488}
1489
1da177e4
LT		 1490/**************************************************************************
1491* qla2xxx_eh_bus_reset
1492*
1493* Description:
1494* The bus reset function will reset the bus and abort any executing
1495* commands.
1496*
1497* Input:
1498* cmd = Linux SCSI command packet of the command that cause the
1499* bus reset.
1500*
1501* Returns:
1502* SUCCESS/FAILURE (defined as macro in scsi.h).
1503*
1504**************************************************************************/
e5f82ab8 1505static int
1da177e4
LT		 1506qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd)
1507{
e315cd28 1508 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
bdf79621 1509 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
2c3dfe3f 1510 int ret = FAILED;
9cb78c16
HR		 1511 unsigned int id;
1512 uint64_t lun;
a465537a
SC		 1513 struct qla_hw_data *ha = vha->hw;
1514
1515 if (qla2x00_isp_reg_stat(ha)) {
1516 ql_log(ql_log_info, vha, 0x8040,
1517 "PCI/Register disconnect, exiting.\n");
1518 return FAILED;
1519 }
f4f051eb 1520
f4f051eb 1521 id = cmd->device->id;
1522 lun = cmd->device->lun;
1da177e4 1523
7c3df132 1524 if (!fcport) {
f4f051eb 1525 return ret;
7c3df132 1526 }
1da177e4 1527
4e98d3b8
AV		 1528 ret = fc_block_scsi_eh(cmd);
1529 if (ret != 0)
1530 return ret;
1531 ret = FAILED;
1532
7c3df132 1533 ql_log(ql_log_info, vha, 0x8012,
9cb78c16 1534 "BUS RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun);
1da177e4 1535
e315cd28 1536 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
7c3df132
SK		 1537 ql_log(ql_log_fatal, vha, 0x8013,
1538 "Wait for hba online failed board disabled.\n");
f4f051eb 1539 goto eh_bus_reset_done;
1da177e4
LT		 1540 }
1541
ad537689
SK		 1542 if (qla2x00_loop_reset(vha) == QLA_SUCCESS)
1543 ret = SUCCESS;
1544
f4f051eb 1545 if (ret == FAILED)
1546 goto eh_bus_reset_done;
1da177e4 1547
9a41a62b 1548 /* Flush outstanding commands. */
4d78c973 1549 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) !=
7c3df132
SK		 1550 QLA_SUCCESS) {
1551 ql_log(ql_log_warn, vha, 0x8014,
1552 "Wait for pending commands failed.\n");
9a41a62b 1553 ret = FAILED;
7c3df132 1554 }
1da177e4 1555
f4f051eb 1556eh_bus_reset_done:
7c3df132 1557 ql_log(ql_log_warn, vha, 0x802b,
9cb78c16 1558 "BUS RESET %s nexus=%ld:%d:%llu.\n",
d6a03581 1559 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1da177e4 1560
f4f051eb 1561 return ret;
1da177e4
LT		 1562}
1563
1564/**************************************************************************
1565* qla2xxx_eh_host_reset
1566*
1567* Description:
1568* The reset function will reset the Adapter.
1569*
1570* Input:
1571* cmd = Linux SCSI command packet of the command that cause the
1572* adapter reset.
1573*
1574* Returns:
1575* Either SUCCESS or FAILED.
1576*
1577* Note:
1578**************************************************************************/
e5f82ab8 1579static int
1da177e4
LT		 1580qla2xxx_eh_host_reset(struct scsi_cmnd *cmd)
1581{
e315cd28 1582 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
e315cd28 1583 struct qla_hw_data *ha = vha->hw;
2c3dfe3f 1584 int ret = FAILED;
9cb78c16
HR		 1585 unsigned int id;
1586 uint64_t lun;
e315cd28 1587 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4 1588
a465537a
SC		 1589 if (qla2x00_isp_reg_stat(ha)) {
1590 ql_log(ql_log_info, vha, 0x8041,
1591 "PCI/Register disconnect, exiting.\n");
1592 schedule_work(&ha->board_disable);
1593 return SUCCESS;
1594 }
1595
f4f051eb 1596 id = cmd->device->id;
1597 lun = cmd->device->lun;
f4f051eb 1598
7c3df132 1599 ql_log(ql_log_info, vha, 0x8018,
9cb78c16 1600 "ADAPTER RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun);
1da177e4 1601
63ee7072
CD		 1602 /*
1603 * No point in issuing another reset if one is active. Also do not
1604 * attempt a reset if we are updating flash.
1605 */
1606 if (qla2x00_reset_active(vha) || ha->optrom_state != QLA_SWAITING)
f4f051eb 1607 goto eh_host_reset_lock;
1da177e4 1608
e315cd28
AC		 1609 if (vha != base_vha) {
1610 if (qla2x00_vp_abort_isp(vha))
f4f051eb 1611 goto eh_host_reset_lock;
e315cd28 1612 } else {
7ec0effd 1613 if (IS_P3P_TYPE(vha->hw)) {
a9083016
GM		 1614 if (!qla82xx_fcoe_ctx_reset(vha)) {
1615 /* Ctx reset success */
1616 ret = SUCCESS;
1617 goto eh_host_reset_lock;
1618 }
1619 /* fall thru if ctx reset failed */
1620 }
68ca949c
AC		 1621 if (ha->wq)
1622 flush_workqueue(ha->wq);
1623
e315cd28 1624 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
a9083016 1625 if (ha->isp_ops->abort_isp(base_vha)) {
e315cd28
AC		 1626 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1627 /* failed. schedule dpc to try */
1628 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
1629
7c3df132
SK		 1630 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1631 ql_log(ql_log_warn, vha, 0x802a,
1632 "wait for hba online failed.\n");
e315cd28 1633 goto eh_host_reset_lock;
7c3df132 1634 }
e315cd28
AC		 1635 }
1636 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
fa2a1ce5 1637 }
1da177e4 1638
e315cd28 1639 /* Waiting for command to be returned to OS.*/
4d78c973 1640 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) ==
e315cd28 1641 QLA_SUCCESS)
f4f051eb 1642 ret = SUCCESS;
1da177e4 1643
f4f051eb 1644eh_host_reset_lock:
cfb0919c 1645 ql_log(ql_log_info, vha, 0x8017,
9cb78c16 1646 "ADAPTER RESET %s nexus=%ld:%d:%llu.\n",
cfb0919c 1647 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1da177e4 1648
f4f051eb 1649 return ret;
1650}
1da177e4
LT		 1651
1652/*
1653* qla2x00_loop_reset
1654* Issue loop reset.
1655*
1656* Input:
1657* ha = adapter block pointer.
1658*
1659* Returns:
1660* 0 = success
1661*/
a4722cf2 1662int
e315cd28 1663qla2x00_loop_reset(scsi_qla_host_t *vha)
1da177e4 1664{
0c8c39af 1665 int ret;
bdf79621 1666 struct fc_port *fcport;
e315cd28 1667 struct qla_hw_data *ha = vha->hw;
1da177e4 1668
5854771e
AB		 1669 if (IS_QLAFX00(ha)) {
1670 return qlafx00_loop_reset(vha);
1671 }
1672
f4c496c1 1673 if (ql2xtargetreset == 1 && ha->flags.enable_target_reset) {
55e5ed27
AV		 1674 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1675 if (fcport->port_type != FCT_TARGET)
1676 continue;
1677
1678 ret = ha->isp_ops->target_reset(fcport, 0, 0);
1679 if (ret != QLA_SUCCESS) {
7c3df132 1680 ql_dbg(ql_dbg_taskm, vha, 0x802c,
5854771e 1681 "Bus Reset failed: Reset=%d "
7c3df132 1682 "d_id=%x.\n", ret, fcport->d_id.b24);
55e5ed27
AV		 1683 }
1684 }
1685 }
1686
8ae6d9c7 1687
6246b8a1 1688 if (ha->flags.enable_lip_full_login && !IS_CNA_CAPABLE(ha)) {
0b7e7c53
AV		 1689 atomic_set(&vha->loop_state, LOOP_DOWN);
1690 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
1691 qla2x00_mark_all_devices_lost(vha, 0);
e315cd28 1692 ret = qla2x00_full_login_lip(vha);
0c8c39af 1693 if (ret != QLA_SUCCESS) {
7c3df132
SK		 1694 ql_dbg(ql_dbg_taskm, vha, 0x802d,
1695 "full_login_lip=%d.\n", ret);
749af3d5 1696 }
0c8c39af
AV		 1697 }
1698
0d6e61bc 1699 if (ha->flags.enable_lip_reset) {
e315cd28 1700 ret = qla2x00_lip_reset(vha);
ad537689 1701 if (ret != QLA_SUCCESS)
7c3df132
SK		 1702 ql_dbg(ql_dbg_taskm, vha, 0x802e,
1703 "lip_reset failed (%d).\n", ret);
1da177e4
LT		 1704 }
1705
1da177e4 1706 /* Issue marker command only when we are going to start the I/O */
e315cd28 1707 vha->marker_needed = 1;
1da177e4 1708
0c8c39af 1709 return QLA_SUCCESS;
1da177e4
LT		 1710}
1711
bbead493
QT		 1712static void
1713__qla2x00_abort_all_cmds(struct qla_qpair *qp, int res)
df4bf0bb 1714{
bbead493 1715 int cnt, status;
df4bf0bb
AV		 1716 unsigned long flags;
1717 srb_t *sp;
bbead493 1718 scsi_qla_host_t *vha = qp->vha;
e315cd28 1719 struct qla_hw_data *ha = vha->hw;
73208dfd 1720 struct req_que *req;
c5419e26
QT		 1721 struct qla_tgt *tgt = vha->vha_tgt.qla_tgt;
1722 struct qla_tgt_cmd *cmd;
1723 uint8_t trace = 0;
c0cb4496 1724
6a2cf8d3
BK		 1725 if (!ha->req_q_map)
1726 return;
bbead493
QT		 1727 spin_lock_irqsave(qp->qp_lock_ptr, flags);
1728 req = qp->req;
1729 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) {
1730 sp = req->outstanding_cmds[cnt];
1731 if (sp) {
1732 req->outstanding_cmds[cnt] = NULL;
1733 if (sp->cmd_type == TYPE_SRB) {
1734 if (sp->type == SRB_NVME_CMD ||
1735 sp->type == SRB_NVME_LS) {
1736 sp_get(sp);
1737 spin_unlock_irqrestore(qp->qp_lock_ptr,
1738 flags);
623ee824 1739 qla_nvme_abort(ha, sp, res);
bbead493
QT		 1740 spin_lock_irqsave(qp->qp_lock_ptr,
1741 flags);
1742 } else if (GET_CMD_SP(sp) &&
1743 !ha->flags.eeh_busy &&
1744 (!test_bit(ABORT_ISP_ACTIVE,
1745 &vha->dpc_flags)) &&
1746 (sp->type == SRB_SCSI_CMD)) {
1747 /*
1748 * Don't abort commands in
1749 * adapter during EEH
1750 * recovery as it's not
1751 * accessible/responding.
1752 *
1753 * Get a reference to the sp
1754 * and drop the lock. The
1755 * reference ensures this
1756 * sp->done() call and not the
1757 * call in qla2xxx_eh_abort()
1758 * ends the SCSI command (with
1759 * result 'res').
1760 */
1761 sp_get(sp);
1762 spin_unlock_irqrestore(qp->qp_lock_ptr,
1763 flags);
1764 status = qla2xxx_eh_abort(
1765 GET_CMD_SP(sp));
1766 spin_lock_irqsave(qp->qp_lock_ptr,
1767 flags);
1768 /*
1769 * Get rid of extra reference
1770 * if immediate exit from
1771 * ql2xxx_eh_abort
1772 */
1773 if (status == FAILED &&
1774 (qla2x00_isp_reg_stat(ha)))
1775 atomic_dec(
1776 &sp->ref_count);
1777 }
1778 sp->done(sp, res);
1779 } else {
1780 if (!vha->hw->tgt.tgt_ops || !tgt ||
1781 qla_ini_mode_enabled(vha)) {
1782 if (!trace)
1783 ql_dbg(ql_dbg_tgt_mgt,
1784 vha, 0xf003,
1785 "HOST-ABORT-HNDLR: dpc_flags=%lx. Target mode disabled\n",
1786 vha->dpc_flags);
1787 continue;
c733ab35 1788 }
bbead493
QT		 1789 cmd = (struct qla_tgt_cmd *)sp;
1790 qlt_abort_cmd_on_host_reset(cmd->vha, cmd);
73208dfd 1791 }
df4bf0bb
AV		 1792 }
1793 }
bbead493
QT		 1794 spin_unlock_irqrestore(qp->qp_lock_ptr, flags);
1795}
1796
1797void
1798qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res)
1799{
1800 int que;
1801 struct qla_hw_data *ha = vha->hw;
1802
1803 __qla2x00_abort_all_cmds(ha->base_qpair, res);
1804
1805 for (que = 0; que < ha->max_qpairs; que++) {
1806 if (!ha->queue_pair_map[que])
1807 continue;
1808
1809 __qla2x00_abort_all_cmds(ha->queue_pair_map[que], res);
1810 }
df4bf0bb
AV		 1811}
1812
f4f051eb 1813static int
1814qla2xxx_slave_alloc(struct scsi_device *sdev)
1da177e4 1815{
bdf79621 1816 struct fc_rport *rport = starget_to_rport(scsi_target(sdev));
1da177e4 1817
19a7b4ae 1818 if (!rport || fc_remote_port_chkready(rport))
f4f051eb 1819 return -ENXIO;
bdf79621 1820
19a7b4ae 1821 sdev->hostdata = *(fc_port_t **)rport->dd_data;
1da177e4 1822
f4f051eb 1823 return 0;
1824}
1da177e4 1825
f4f051eb 1826static int
1827qla2xxx_slave_configure(struct scsi_device *sdev)
1828{
e315cd28 1829 scsi_qla_host_t *vha = shost_priv(sdev->host);
2afa19a9 1830 struct req_que *req = vha->req;
8482e118 1831
9e522cd8
AE		 1832 if (IS_T10_PI_CAPABLE(vha->hw))
1833 blk_queue_update_dma_alignment(sdev->request_queue, 0x7);
1834
db5ed4df 1835 scsi_change_queue_depth(sdev, req->max_q_depth);
f4f051eb 1836 return 0;
1837}
1da177e4 1838
f4f051eb 1839static void
1840qla2xxx_slave_destroy(struct scsi_device *sdev)
1841{
1842 sdev->hostdata = NULL;
1da177e4
LT		 1843}
1844
1845/**
1846 * qla2x00_config_dma_addressing() - Configure OS DMA addressing method.
1847 * @ha: HA context
1848 *
1849 * At exit, the @ha's flags.enable_64bit_addressing set to indicated
1850 * supported addressing method.
1851 */
1852static void
53303c42 1853qla2x00_config_dma_addressing(struct qla_hw_data *ha)
1da177e4 1854{
7524f9b9 1855 /* Assume a 32bit DMA mask. */
1da177e4 1856 ha->flags.enable_64bit_addressing = 0;
1da177e4 1857
6a35528a 1858 if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) {
7524f9b9
AV		 1859 /* Any upper-dword bits set? */
1860 if (MSD(dma_get_required_mask(&ha->pdev->dev)) &&
6a35528a 1861 !pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(64))) {
7524f9b9 1862 /* Ok, a 64bit DMA mask is applicable. */
1da177e4 1863 ha->flags.enable_64bit_addressing = 1;
fd34f556
AV		 1864 ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64;
1865 ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64;
7524f9b9 1866 return;
1da177e4 1867 }
1da177e4 1868 }
7524f9b9 1869
284901a9
YH		 1870 dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32));
1871 pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(32));
1da177e4
LT		 1872}
1873
fd34f556 1874static void
e315cd28 1875qla2x00_enable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1876{
1877 unsigned long flags = 0;
1878 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1879
1880 spin_lock_irqsave(&ha->hardware_lock, flags);
1881 ha->interrupts_on = 1;
1882 /* enable risc and host interrupts */
1883 WRT_REG_WORD(&reg->ictrl, ICR_EN_INT | ICR_EN_RISC);
1884 RD_REG_WORD(&reg->ictrl);
1885 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1886
1887}
1888
1889static void
e315cd28 1890qla2x00_disable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1891{
1892 unsigned long flags = 0;
1893 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1894
1895 spin_lock_irqsave(&ha->hardware_lock, flags);
1896 ha->interrupts_on = 0;
1897 /* disable risc and host interrupts */
1898 WRT_REG_WORD(&reg->ictrl, 0);
1899 RD_REG_WORD(&reg->ictrl);
1900 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1901}
1902
1903static void
e315cd28 1904qla24xx_enable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1905{
1906 unsigned long flags = 0;
1907 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1908
1909 spin_lock_irqsave(&ha->hardware_lock, flags);
1910 ha->interrupts_on = 1;
1911 WRT_REG_DWORD(&reg->ictrl, ICRX_EN_RISC_INT);
1912 RD_REG_DWORD(&reg->ictrl);
1913 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1914}
1915
1916static void
e315cd28 1917qla24xx_disable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1918{
1919 unsigned long flags = 0;
1920 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1921
124f85e6
AV		 1922 if (IS_NOPOLLING_TYPE(ha))
1923 return;
fd34f556
AV		 1924 spin_lock_irqsave(&ha->hardware_lock, flags);
1925 ha->interrupts_on = 0;
1926 WRT_REG_DWORD(&reg->ictrl, 0);
1927 RD_REG_DWORD(&reg->ictrl);
1928 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1929}
1930
706f457d
GM		 1931static int
1932qla2x00_iospace_config(struct qla_hw_data *ha)
1933{
1934 resource_size_t pio;
1935 uint16_t msix;
706f457d 1936
706f457d
GM		 1937 if (pci_request_selected_regions(ha->pdev, ha->bars,
1938 QLA2XXX_DRIVER_NAME)) {
1939 ql_log_pci(ql_log_fatal, ha->pdev, 0x0011,
1940 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
1941 pci_name(ha->pdev));
1942 goto iospace_error_exit;
1943 }
1944 if (!(ha->bars & 1))
1945 goto skip_pio;
1946
1947 /* We only need PIO for Flash operations on ISP2312 v2 chips. */
1948 pio = pci_resource_start(ha->pdev, 0);
1949 if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) {
1950 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
1951 ql_log_pci(ql_log_warn, ha->pdev, 0x0012,
1952 "Invalid pci I/O region size (%s).\n",
1953 pci_name(ha->pdev));
1954 pio = 0;
1955 }
1956 } else {
1957 ql_log_pci(ql_log_warn, ha->pdev, 0x0013,
1958 "Region #0 no a PIO resource (%s).\n",
1959 pci_name(ha->pdev));
1960 pio = 0;
1961 }
1962 ha->pio_address = pio;
1963 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014,
1964 "PIO address=%llu.\n",
1965 (unsigned long long)ha->pio_address);
1966
1967skip_pio:
1968 /* Use MMIO operations for all accesses. */
1969 if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) {
1970 ql_log_pci(ql_log_fatal, ha->pdev, 0x0015,
1971 "Region #1 not an MMIO resource (%s), aborting.\n",
1972 pci_name(ha->pdev));
1973 goto iospace_error_exit;
1974 }
1975 if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) {
1976 ql_log_pci(ql_log_fatal, ha->pdev, 0x0016,
1977 "Invalid PCI mem region size (%s), aborting.\n",
1978 pci_name(ha->pdev));
1979 goto iospace_error_exit;
1980 }
1981
1982 ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN);
1983 if (!ha->iobase) {
1984 ql_log_pci(ql_log_fatal, ha->pdev, 0x0017,
1985 "Cannot remap MMIO (%s), aborting.\n",
1986 pci_name(ha->pdev));
1987 goto iospace_error_exit;
1988 }
1989
1990 /* Determine queue resources */
1991 ha->max_req_queues = ha->max_rsp_queues = 1;
f54f2cb5 1992 ha->msix_count = QLA_BASE_VECTORS;
c38d1baf
HM		 1993 if (!ql2xmqsupport || !ql2xnvmeenable ||
1994 (!IS_QLA25XX(ha) && !IS_QLA81XX(ha)))
706f457d
GM		 1995 goto mqiobase_exit;
1996
1997 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3),
1998 pci_resource_len(ha->pdev, 3));
1999 if (ha->mqiobase) {
2000 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018,
2001 "MQIO Base=%p.\n", ha->mqiobase);
2002 /* Read MSIX vector size of the board */
2003 pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix);
d7459527 2004 ha->msix_count = msix + 1;
706f457d 2005 /* Max queues are bounded by available msix vectors */
d7459527
MH		 2006 /* MB interrupt uses 1 vector */
2007 ha->max_req_queues = ha->msix_count - 1;
2008 ha->max_rsp_queues = ha->max_req_queues;
2009 /* Queue pairs is the max value minus the base queue pair */
2010 ha->max_qpairs = ha->max_rsp_queues - 1;
2011 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0188,
2012 "Max no of queues pairs: %d.\n", ha->max_qpairs);
2013
706f457d 2014 ql_log_pci(ql_log_info, ha->pdev, 0x001a,
d7459527 2015 "MSI-X vector count: %d.\n", ha->msix_count);
706f457d
GM		 2016 } else
2017 ql_log_pci(ql_log_info, ha->pdev, 0x001b,
2018 "BAR 3 not enabled.\n");
2019
2020mqiobase_exit:
706f457d 2021 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c,
f54f2cb5 2022 "MSIX Count: %d.\n", ha->msix_count);
706f457d
GM		 2023 return (0);
2024
2025iospace_error_exit:
2026 return (-ENOMEM);
2027}
2028
2029
6246b8a1
GM		 2030static int
2031qla83xx_iospace_config(struct qla_hw_data *ha)
2032{
2033 uint16_t msix;
6246b8a1
GM		 2034
2035 if (pci_request_selected_regions(ha->pdev, ha->bars,
2036 QLA2XXX_DRIVER_NAME)) {
2037 ql_log_pci(ql_log_fatal, ha->pdev, 0x0117,
2038 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
2039 pci_name(ha->pdev));
2040
2041 goto iospace_error_exit;
2042 }
2043
2044 /* Use MMIO operations for all accesses. */
2045 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) {
2046 ql_log_pci(ql_log_warn, ha->pdev, 0x0118,
2047 "Invalid pci I/O region size (%s).\n",
2048 pci_name(ha->pdev));
2049 goto iospace_error_exit;
2050 }
2051 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
2052 ql_log_pci(ql_log_warn, ha->pdev, 0x0119,
2053 "Invalid PCI mem region size (%s), aborting\n",
2054 pci_name(ha->pdev));
2055 goto iospace_error_exit;
2056 }
2057
2058 ha->iobase = ioremap(pci_resource_start(ha->pdev, 0), MIN_IOBASE_LEN);
2059 if (!ha->iobase) {
2060 ql_log_pci(ql_log_fatal, ha->pdev, 0x011a,
2061 "Cannot remap MMIO (%s), aborting.\n",
2062 pci_name(ha->pdev));
2063 goto iospace_error_exit;
2064 }
2065
2066 /* 64bit PCI BAR - BAR2 will correspoond to region 4 */
2067 /* 83XX 26XX always use MQ type access for queues
2068 * - mbar 2, a.k.a region 4 */
2069 ha->max_req_queues = ha->max_rsp_queues = 1;
f54f2cb5 2070 ha->msix_count = QLA_BASE_VECTORS;
6246b8a1
GM		 2071 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 4),
2072 pci_resource_len(ha->pdev, 4));
2073
2074 if (!ha->mqiobase) {
2075 ql_log_pci(ql_log_fatal, ha->pdev, 0x011d,
2076 "BAR2/region4 not enabled\n");
2077 goto mqiobase_exit;
2078 }
2079
2080 ha->msixbase = ioremap(pci_resource_start(ha->pdev, 2),
2081 pci_resource_len(ha->pdev, 2));
2082 if (ha->msixbase) {
2083 /* Read MSIX vector size of the board */
2084 pci_read_config_word(ha->pdev,
2085 QLA_83XX_PCI_MSIX_CONTROL, &msix);
e326d22a 2086 ha->msix_count = (msix & PCI_MSIX_FLAGS_QSIZE) + 1;
093df737
QT		 2087 /*
2088 * By default, driver uses at least two msix vectors
2089 * (default & rspq)
2090 */
c38d1baf 2091 if (ql2xmqsupport || ql2xnvmeenable) {
d7459527
MH		 2092 /* MB interrupt uses 1 vector */
2093 ha->max_req_queues = ha->msix_count - 1;
093df737
QT		 2094
2095 /* ATIOQ needs 1 vector. That's 1 less QPair */
2096 if (QLA_TGT_MODE_ENABLED())
2097 ha->max_req_queues--;
2098
d0d2c68b
MH		 2099 ha->max_rsp_queues = ha->max_req_queues;
2100
d7459527
MH		 2101 /* Queue pairs is the max value minus
2102 * the base queue pair */
2103 ha->max_qpairs = ha->max_req_queues - 1;
83548fe2 2104 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x00e3,
d7459527 2105 "Max no of queues pairs: %d.\n", ha->max_qpairs);
6246b8a1
GM		 2106 }
2107 ql_log_pci(ql_log_info, ha->pdev, 0x011c,
d7459527 2108 "MSI-X vector count: %d.\n", ha->msix_count);
6246b8a1
GM		 2109 } else
2110 ql_log_pci(ql_log_info, ha->pdev, 0x011e,
2111 "BAR 1 not enabled.\n");
2112
2113mqiobase_exit:
6246b8a1 2114 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011f,
f54f2cb5 2115 "MSIX Count: %d.\n", ha->msix_count);
6246b8a1
GM		 2116 return 0;
2117
2118iospace_error_exit:
2119 return -ENOMEM;
2120}
2121
fd34f556
AV		 2122static struct isp_operations qla2100_isp_ops = {
2123 .pci_config = qla2100_pci_config,
2124 .reset_chip = qla2x00_reset_chip,
2125 .chip_diag = qla2x00_chip_diag,
2126 .config_rings = qla2x00_config_rings,
2127 .reset_adapter = qla2x00_reset_adapter,
2128 .nvram_config = qla2x00_nvram_config,
2129 .update_fw_options = qla2x00_update_fw_options,
2130 .load_risc = qla2x00_load_risc,
2131 .pci_info_str = qla2x00_pci_info_str,
2132 .fw_version_str = qla2x00_fw_version_str,
2133 .intr_handler = qla2100_intr_handler,
2134 .enable_intrs = qla2x00_enable_intrs,
2135 .disable_intrs = qla2x00_disable_intrs,
2136 .abort_command = qla2x00_abort_command,
523ec773
AV		 2137 .target_reset = qla2x00_abort_target,
2138 .lun_reset = qla2x00_lun_reset,
fd34f556
AV		 2139 .fabric_login = qla2x00_login_fabric,
2140 .fabric_logout = qla2x00_fabric_logout,
2141 .calc_req_entries = qla2x00_calc_iocbs_32,
2142 .build_iocbs = qla2x00_build_scsi_iocbs_32,
2143 .prep_ms_iocb = qla2x00_prep_ms_iocb,
2144 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
2145 .read_nvram = qla2x00_read_nvram_data,
2146 .write_nvram = qla2x00_write_nvram_data,
2147 .fw_dump = qla2100_fw_dump,
2148 .beacon_on = NULL,
2149 .beacon_off = NULL,
2150 .beacon_blink = NULL,
2151 .read_optrom = qla2x00_read_optrom_data,
2152 .write_optrom = qla2x00_write_optrom_data,
2153 .get_flash_version = qla2x00_get_flash_version,
e315cd28 2154 .start_scsi = qla2x00_start_scsi,
d7459527 2155 .start_scsi_mq = NULL,
a9083016 2156 .abort_isp = qla2x00_abort_isp,
706f457d 2157 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2158 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 2159};
2160
2161static struct isp_operations qla2300_isp_ops = {
2162 .pci_config = qla2300_pci_config,
2163 .reset_chip = qla2x00_reset_chip,
2164 .chip_diag = qla2x00_chip_diag,
2165 .config_rings = qla2x00_config_rings,
2166 .reset_adapter = qla2x00_reset_adapter,
2167 .nvram_config = qla2x00_nvram_config,
2168 .update_fw_options = qla2x00_update_fw_options,
2169 .load_risc = qla2x00_load_risc,
2170 .pci_info_str = qla2x00_pci_info_str,
2171 .fw_version_str = qla2x00_fw_version_str,
2172 .intr_handler = qla2300_intr_handler,
2173 .enable_intrs = qla2x00_enable_intrs,
2174 .disable_intrs = qla2x00_disable_intrs,
2175 .abort_command = qla2x00_abort_command,
523ec773
AV		 2176 .target_reset = qla2x00_abort_target,
2177 .lun_reset = qla2x00_lun_reset,
fd34f556
AV		 2178 .fabric_login = qla2x00_login_fabric,
2179 .fabric_logout = qla2x00_fabric_logout,
2180 .calc_req_entries = qla2x00_calc_iocbs_32,
2181 .build_iocbs = qla2x00_build_scsi_iocbs_32,
2182 .prep_ms_iocb = qla2x00_prep_ms_iocb,
2183 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
2184 .read_nvram = qla2x00_read_nvram_data,
2185 .write_nvram = qla2x00_write_nvram_data,
2186 .fw_dump = qla2300_fw_dump,
2187 .beacon_on = qla2x00_beacon_on,
2188 .beacon_off = qla2x00_beacon_off,
2189 .beacon_blink = qla2x00_beacon_blink,
2190 .read_optrom = qla2x00_read_optrom_data,
2191 .write_optrom = qla2x00_write_optrom_data,
2192 .get_flash_version = qla2x00_get_flash_version,
e315cd28 2193 .start_scsi = qla2x00_start_scsi,
d7459527 2194 .start_scsi_mq = NULL,
a9083016 2195 .abort_isp = qla2x00_abort_isp,
7ec0effd 2196 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2197 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 2198};
2199
2200static struct isp_operations qla24xx_isp_ops = {
2201 .pci_config = qla24xx_pci_config,
2202 .reset_chip = qla24xx_reset_chip,
2203 .chip_diag = qla24xx_chip_diag,
2204 .config_rings = qla24xx_config_rings,
2205 .reset_adapter = qla24xx_reset_adapter,
2206 .nvram_config = qla24xx_nvram_config,
2207 .update_fw_options = qla24xx_update_fw_options,
2208 .load_risc = qla24xx_load_risc,
2209 .pci_info_str = qla24xx_pci_info_str,
2210 .fw_version_str = qla24xx_fw_version_str,
2211 .intr_handler = qla24xx_intr_handler,
2212 .enable_intrs = qla24xx_enable_intrs,
2213 .disable_intrs = qla24xx_disable_intrs,
2214 .abort_command = qla24xx_abort_command,
523ec773
AV		 2215 .target_reset = qla24xx_abort_target,
2216 .lun_reset = qla24xx_lun_reset,
fd34f556
AV		 2217 .fabric_login = qla24xx_login_fabric,
2218 .fabric_logout = qla24xx_fabric_logout,
2219 .calc_req_entries = NULL,
2220 .build_iocbs = NULL,
2221 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2222 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2223 .read_nvram = qla24xx_read_nvram_data,
2224 .write_nvram = qla24xx_write_nvram_data,
2225 .fw_dump = qla24xx_fw_dump,
2226 .beacon_on = qla24xx_beacon_on,
2227 .beacon_off = qla24xx_beacon_off,
2228 .beacon_blink = qla24xx_beacon_blink,
2229 .read_optrom = qla24xx_read_optrom_data,
2230 .write_optrom = qla24xx_write_optrom_data,
2231 .get_flash_version = qla24xx_get_flash_version,
e315cd28 2232 .start_scsi = qla24xx_start_scsi,
d7459527 2233 .start_scsi_mq = NULL,
a9083016 2234 .abort_isp = qla2x00_abort_isp,
7ec0effd 2235 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2236 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 2237};
2238
c3a2f0df
AV		 2239static struct isp_operations qla25xx_isp_ops = {
2240 .pci_config = qla25xx_pci_config,
2241 .reset_chip = qla24xx_reset_chip,
2242 .chip_diag = qla24xx_chip_diag,
2243 .config_rings = qla24xx_config_rings,
2244 .reset_adapter = qla24xx_reset_adapter,
2245 .nvram_config = qla24xx_nvram_config,
2246 .update_fw_options = qla24xx_update_fw_options,
2247 .load_risc = qla24xx_load_risc,
2248 .pci_info_str = qla24xx_pci_info_str,
2249 .fw_version_str = qla24xx_fw_version_str,
2250 .intr_handler = qla24xx_intr_handler,
2251 .enable_intrs = qla24xx_enable_intrs,
2252 .disable_intrs = qla24xx_disable_intrs,
2253 .abort_command = qla24xx_abort_command,
523ec773
AV		 2254 .target_reset = qla24xx_abort_target,
2255 .lun_reset = qla24xx_lun_reset,
c3a2f0df
AV		 2256 .fabric_login = qla24xx_login_fabric,
2257 .fabric_logout = qla24xx_fabric_logout,
2258 .calc_req_entries = NULL,
2259 .build_iocbs = NULL,
2260 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2261 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2262 .read_nvram = qla25xx_read_nvram_data,
2263 .write_nvram = qla25xx_write_nvram_data,
2264 .fw_dump = qla25xx_fw_dump,
2265 .beacon_on = qla24xx_beacon_on,
2266 .beacon_off = qla24xx_beacon_off,
2267 .beacon_blink = qla24xx_beacon_blink,
338c9161 2268 .read_optrom = qla25xx_read_optrom_data,
c3a2f0df
AV		 2269 .write_optrom = qla24xx_write_optrom_data,
2270 .get_flash_version = qla24xx_get_flash_version,
bad75002 2271 .start_scsi = qla24xx_dif_start_scsi,
d7459527 2272 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
a9083016 2273 .abort_isp = qla2x00_abort_isp,
7ec0effd 2274 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2275 .initialize_adapter = qla2x00_initialize_adapter,
c3a2f0df
AV		 2276};
2277
3a03eb79
AV		 2278static struct isp_operations qla81xx_isp_ops = {
2279 .pci_config = qla25xx_pci_config,
2280 .reset_chip = qla24xx_reset_chip,
2281 .chip_diag = qla24xx_chip_diag,
2282 .config_rings = qla24xx_config_rings,
2283 .reset_adapter = qla24xx_reset_adapter,
2284 .nvram_config = qla81xx_nvram_config,
2285 .update_fw_options = qla81xx_update_fw_options,
eaac30be 2286 .load_risc = qla81xx_load_risc,
3a03eb79
AV		 2287 .pci_info_str = qla24xx_pci_info_str,
2288 .fw_version_str = qla24xx_fw_version_str,
2289 .intr_handler = qla24xx_intr_handler,
2290 .enable_intrs = qla24xx_enable_intrs,
2291 .disable_intrs = qla24xx_disable_intrs,
2292 .abort_command = qla24xx_abort_command,
2293 .target_reset = qla24xx_abort_target,
2294 .lun_reset = qla24xx_lun_reset,
2295 .fabric_login = qla24xx_login_fabric,
2296 .fabric_logout = qla24xx_fabric_logout,
2297 .calc_req_entries = NULL,
2298 .build_iocbs = NULL,
2299 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2300 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
3d79038f
AV		 2301 .read_nvram = NULL,
2302 .write_nvram = NULL,
3a03eb79
AV		 2303 .fw_dump = qla81xx_fw_dump,
2304 .beacon_on = qla24xx_beacon_on,
2305 .beacon_off = qla24xx_beacon_off,
6246b8a1 2306 .beacon_blink = qla83xx_beacon_blink,
3a03eb79
AV		 2307 .read_optrom = qla25xx_read_optrom_data,
2308 .write_optrom = qla24xx_write_optrom_data,
2309 .get_flash_version = qla24xx_get_flash_version,
ba77ef53 2310 .start_scsi = qla24xx_dif_start_scsi,
d7459527 2311 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
a9083016 2312 .abort_isp = qla2x00_abort_isp,
7ec0effd 2313 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2314 .initialize_adapter = qla2x00_initialize_adapter,
a9083016
GM		 2315};
2316
2317static struct isp_operations qla82xx_isp_ops = {
2318 .pci_config = qla82xx_pci_config,
2319 .reset_chip = qla82xx_reset_chip,
2320 .chip_diag = qla24xx_chip_diag,
2321 .config_rings = qla82xx_config_rings,
2322 .reset_adapter = qla24xx_reset_adapter,
2323 .nvram_config = qla81xx_nvram_config,
2324 .update_fw_options = qla24xx_update_fw_options,
2325 .load_risc = qla82xx_load_risc,
9d55ca66 2326 .pci_info_str = qla24xx_pci_info_str,
a9083016
GM		 2327 .fw_version_str = qla24xx_fw_version_str,
2328 .intr_handler = qla82xx_intr_handler,
2329 .enable_intrs = qla82xx_enable_intrs,
2330 .disable_intrs = qla82xx_disable_intrs,
2331 .abort_command = qla24xx_abort_command,
2332 .target_reset = qla24xx_abort_target,
2333 .lun_reset = qla24xx_lun_reset,
2334 .fabric_login = qla24xx_login_fabric,
2335 .fabric_logout = qla24xx_fabric_logout,
2336 .calc_req_entries = NULL,
2337 .build_iocbs = NULL,
2338 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2339 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2340 .read_nvram = qla24xx_read_nvram_data,
2341 .write_nvram = qla24xx_write_nvram_data,
a1b23c5a 2342 .fw_dump = qla82xx_fw_dump,
999916dc
SK		 2343 .beacon_on = qla82xx_beacon_on,
2344 .beacon_off = qla82xx_beacon_off,
2345 .beacon_blink = NULL,
a9083016
GM		 2346 .read_optrom = qla82xx_read_optrom_data,
2347 .write_optrom = qla82xx_write_optrom_data,
7ec0effd 2348 .get_flash_version = qla82xx_get_flash_version,
a9083016 2349 .start_scsi = qla82xx_start_scsi,
d7459527 2350 .start_scsi_mq = NULL,
a9083016 2351 .abort_isp = qla82xx_abort_isp,
706f457d 2352 .iospace_config = qla82xx_iospace_config,
8ae6d9c7 2353 .initialize_adapter = qla2x00_initialize_adapter,
3a03eb79
AV		 2354};
2355
7ec0effd
AD		 2356static struct isp_operations qla8044_isp_ops = {
2357 .pci_config = qla82xx_pci_config,
2358 .reset_chip = qla82xx_reset_chip,
2359 .chip_diag = qla24xx_chip_diag,
2360 .config_rings = qla82xx_config_rings,
2361 .reset_adapter = qla24xx_reset_adapter,
2362 .nvram_config = qla81xx_nvram_config,
2363 .update_fw_options = qla24xx_update_fw_options,
2364 .load_risc = qla82xx_load_risc,
2365 .pci_info_str = qla24xx_pci_info_str,
2366 .fw_version_str = qla24xx_fw_version_str,
2367 .intr_handler = qla8044_intr_handler,
2368 .enable_intrs = qla82xx_enable_intrs,
2369 .disable_intrs = qla82xx_disable_intrs,
2370 .abort_command = qla24xx_abort_command,
2371 .target_reset = qla24xx_abort_target,
2372 .lun_reset = qla24xx_lun_reset,
2373 .fabric_login = qla24xx_login_fabric,
2374 .fabric_logout = qla24xx_fabric_logout,
2375 .calc_req_entries = NULL,
2376 .build_iocbs = NULL,
2377 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2378 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2379 .read_nvram = NULL,
2380 .write_nvram = NULL,
a1b23c5a 2381 .fw_dump = qla8044_fw_dump,
7ec0effd
AD		 2382 .beacon_on = qla82xx_beacon_on,
2383 .beacon_off = qla82xx_beacon_off,
2384 .beacon_blink = NULL,
888e639d 2385 .read_optrom = qla8044_read_optrom_data,
7ec0effd
AD		 2386 .write_optrom = qla8044_write_optrom_data,
2387 .get_flash_version = qla82xx_get_flash_version,
2388 .start_scsi = qla82xx_start_scsi,
d7459527 2389 .start_scsi_mq = NULL,
7ec0effd
AD		 2390 .abort_isp = qla8044_abort_isp,
2391 .iospace_config = qla82xx_iospace_config,
2392 .initialize_adapter = qla2x00_initialize_adapter,
2393};
2394
6246b8a1
GM		 2395static struct isp_operations qla83xx_isp_ops = {
2396 .pci_config = qla25xx_pci_config,
2397 .reset_chip = qla24xx_reset_chip,
2398 .chip_diag = qla24xx_chip_diag,
2399 .config_rings = qla24xx_config_rings,
2400 .reset_adapter = qla24xx_reset_adapter,
2401 .nvram_config = qla81xx_nvram_config,
2402 .update_fw_options = qla81xx_update_fw_options,
2403 .load_risc = qla81xx_load_risc,
2404 .pci_info_str = qla24xx_pci_info_str,
2405 .fw_version_str = qla24xx_fw_version_str,
2406 .intr_handler = qla24xx_intr_handler,
2407 .enable_intrs = qla24xx_enable_intrs,
2408 .disable_intrs = qla24xx_disable_intrs,
2409 .abort_command = qla24xx_abort_command,
2410 .target_reset = qla24xx_abort_target,
2411 .lun_reset = qla24xx_lun_reset,
2412 .fabric_login = qla24xx_login_fabric,
2413 .fabric_logout = qla24xx_fabric_logout,
2414 .calc_req_entries = NULL,
2415 .build_iocbs = NULL,
2416 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2417 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2418 .read_nvram = NULL,
2419 .write_nvram = NULL,
2420 .fw_dump = qla83xx_fw_dump,
2421 .beacon_on = qla24xx_beacon_on,
2422 .beacon_off = qla24xx_beacon_off,
2423 .beacon_blink = qla83xx_beacon_blink,
2424 .read_optrom = qla25xx_read_optrom_data,
2425 .write_optrom = qla24xx_write_optrom_data,
2426 .get_flash_version = qla24xx_get_flash_version,
2427 .start_scsi = qla24xx_dif_start_scsi,
d7459527 2428 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
6246b8a1
GM		 2429 .abort_isp = qla2x00_abort_isp,
2430 .iospace_config = qla83xx_iospace_config,
8ae6d9c7
GM		 2431 .initialize_adapter = qla2x00_initialize_adapter,
2432};
2433
2434static struct isp_operations qlafx00_isp_ops = {
2435 .pci_config = qlafx00_pci_config,
2436 .reset_chip = qlafx00_soft_reset,
2437 .chip_diag = qlafx00_chip_diag,
2438 .config_rings = qlafx00_config_rings,
2439 .reset_adapter = qlafx00_soft_reset,
2440 .nvram_config = NULL,
2441 .update_fw_options = NULL,
2442 .load_risc = NULL,
2443 .pci_info_str = qlafx00_pci_info_str,
2444 .fw_version_str = qlafx00_fw_version_str,
2445 .intr_handler = qlafx00_intr_handler,
2446 .enable_intrs = qlafx00_enable_intrs,
2447 .disable_intrs = qlafx00_disable_intrs,
4440e46d 2448 .abort_command = qla24xx_async_abort_command,
8ae6d9c7
GM		 2449 .target_reset = qlafx00_abort_target,
2450 .lun_reset = qlafx00_lun_reset,
2451 .fabric_login = NULL,
2452 .fabric_logout = NULL,
2453 .calc_req_entries = NULL,
2454 .build_iocbs = NULL,
2455 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2456 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2457 .read_nvram = qla24xx_read_nvram_data,
2458 .write_nvram = qla24xx_write_nvram_data,
2459 .fw_dump = NULL,
2460 .beacon_on = qla24xx_beacon_on,
2461 .beacon_off = qla24xx_beacon_off,
2462 .beacon_blink = NULL,
2463 .read_optrom = qla24xx_read_optrom_data,
2464 .write_optrom = qla24xx_write_optrom_data,
2465 .get_flash_version = qla24xx_get_flash_version,
2466 .start_scsi = qlafx00_start_scsi,
d7459527 2467 .start_scsi_mq = NULL,
8ae6d9c7
GM		 2468 .abort_isp = qlafx00_abort_isp,
2469 .iospace_config = qlafx00_iospace_config,
2470 .initialize_adapter = qlafx00_initialize_adapter,
6246b8a1
GM		 2471};
2472
f73cb695
CD		 2473static struct isp_operations qla27xx_isp_ops = {
2474 .pci_config = qla25xx_pci_config,
2475 .reset_chip = qla24xx_reset_chip,
2476 .chip_diag = qla24xx_chip_diag,
2477 .config_rings = qla24xx_config_rings,
2478 .reset_adapter = qla24xx_reset_adapter,
2479 .nvram_config = qla81xx_nvram_config,
2480 .update_fw_options = qla81xx_update_fw_options,
2481 .load_risc = qla81xx_load_risc,
2482 .pci_info_str = qla24xx_pci_info_str,
2483 .fw_version_str = qla24xx_fw_version_str,
2484 .intr_handler = qla24xx_intr_handler,
2485 .enable_intrs = qla24xx_enable_intrs,
2486 .disable_intrs = qla24xx_disable_intrs,
2487 .abort_command = qla24xx_abort_command,
2488 .target_reset = qla24xx_abort_target,
2489 .lun_reset = qla24xx_lun_reset,
2490 .fabric_login = qla24xx_login_fabric,
2491 .fabric_logout = qla24xx_fabric_logout,
2492 .calc_req_entries = NULL,
2493 .build_iocbs = NULL,
2494 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2495 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2496 .read_nvram = NULL,
2497 .write_nvram = NULL,
2498 .fw_dump = qla27xx_fwdump,
2499 .beacon_on = qla24xx_beacon_on,
2500 .beacon_off = qla24xx_beacon_off,
2501 .beacon_blink = qla83xx_beacon_blink,
2502 .read_optrom = qla25xx_read_optrom_data,
2503 .write_optrom = qla24xx_write_optrom_data,
2504 .get_flash_version = qla24xx_get_flash_version,
2505 .start_scsi = qla24xx_dif_start_scsi,
d7459527 2506 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
f73cb695
CD		 2507 .abort_isp = qla2x00_abort_isp,
2508 .iospace_config = qla83xx_iospace_config,
2509 .initialize_adapter = qla2x00_initialize_adapter,
2510};
2511
ea5b6382 2512static inline void
e315cd28 2513qla2x00_set_isp_flags(struct qla_hw_data *ha)
ea5b6382 2514{
2515 ha->device_type = DT_EXTENDED_IDS;
2516 switch (ha->pdev->device) {
2517 case PCI_DEVICE_ID_QLOGIC_ISP2100:
9e052e2d 2518 ha->isp_type |= DT_ISP2100;
ea5b6382 2519 ha->device_type &= ~DT_EXTENDED_IDS;
441d1072 2520 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
ea5b6382 2521 break;
2522 case PCI_DEVICE_ID_QLOGIC_ISP2200:
9e052e2d 2523 ha->isp_type |= DT_ISP2200;
ea5b6382 2524 ha->device_type &= ~DT_EXTENDED_IDS;
441d1072 2525 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
ea5b6382 2526 break;
2527 case PCI_DEVICE_ID_QLOGIC_ISP2300:
9e052e2d 2528 ha->isp_type |= DT_ISP2300;
4a59f71d 2529 ha->device_type |= DT_ZIO_SUPPORTED;
441d1072 2530 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 2531 break;
2532 case PCI_DEVICE_ID_QLOGIC_ISP2312:
9e052e2d 2533 ha->isp_type |= DT_ISP2312;
4a59f71d 2534 ha->device_type |= DT_ZIO_SUPPORTED;
441d1072 2535 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 2536 break;
2537 case PCI_DEVICE_ID_QLOGIC_ISP2322:
9e052e2d 2538 ha->isp_type |= DT_ISP2322;
4a59f71d 2539 ha->device_type |= DT_ZIO_SUPPORTED;
ea5b6382 2540 if (ha->pdev->subsystem_vendor == 0x1028 &&
2541 ha->pdev->subsystem_device == 0x0170)
2542 ha->device_type |= DT_OEM_001;
441d1072 2543 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 2544 break;
2545 case PCI_DEVICE_ID_QLOGIC_ISP6312:
9e052e2d 2546 ha->isp_type |= DT_ISP6312;
441d1072 2547 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 2548 break;
2549 case PCI_DEVICE_ID_QLOGIC_ISP6322:
9e052e2d 2550 ha->isp_type |= DT_ISP6322;
441d1072 2551 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 2552 break;
2553 case PCI_DEVICE_ID_QLOGIC_ISP2422:
9e052e2d 2554 ha->isp_type |= DT_ISP2422;
4a59f71d 2555 ha->device_type |= DT_ZIO_SUPPORTED;
e428924c 2556 ha->device_type |= DT_FWI2;
c76f2c01 2557 ha->device_type |= DT_IIDMA;
441d1072 2558 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2559 break;
2560 case PCI_DEVICE_ID_QLOGIC_ISP2432:
9e052e2d 2561 ha->isp_type |= DT_ISP2432;
4a59f71d 2562 ha->device_type |= DT_ZIO_SUPPORTED;
e428924c 2563 ha->device_type |= DT_FWI2;
c76f2c01 2564 ha->device_type |= DT_IIDMA;
441d1072 2565 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2566 break;
4d4df193 2567 case PCI_DEVICE_ID_QLOGIC_ISP8432:
9e052e2d 2568 ha->isp_type |= DT_ISP8432;
4d4df193
HK		 2569 ha->device_type |= DT_ZIO_SUPPORTED;
2570 ha->device_type |= DT_FWI2;
2571 ha->device_type |= DT_IIDMA;
2572 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2573 break;
044cc6c8 2574 case PCI_DEVICE_ID_QLOGIC_ISP5422:
9e052e2d 2575 ha->isp_type |= DT_ISP5422;
e428924c 2576 ha->device_type |= DT_FWI2;
441d1072 2577 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2578 break;
044cc6c8 2579 case PCI_DEVICE_ID_QLOGIC_ISP5432:
9e052e2d 2580 ha->isp_type |= DT_ISP5432;
e428924c 2581 ha->device_type |= DT_FWI2;
441d1072 2582 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2583 break;
c3a2f0df 2584 case PCI_DEVICE_ID_QLOGIC_ISP2532:
9e052e2d 2585 ha->isp_type |= DT_ISP2532;
c3a2f0df
AV		 2586 ha->device_type |= DT_ZIO_SUPPORTED;
2587 ha->device_type |= DT_FWI2;
2588 ha->device_type |= DT_IIDMA;
441d1072 2589 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2590 break;
3a03eb79 2591 case PCI_DEVICE_ID_QLOGIC_ISP8001:
9e052e2d 2592 ha->isp_type |= DT_ISP8001;
3a03eb79
AV		 2593 ha->device_type |= DT_ZIO_SUPPORTED;
2594 ha->device_type |= DT_FWI2;
2595 ha->device_type |= DT_IIDMA;
2596 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2597 break;
a9083016 2598 case PCI_DEVICE_ID_QLOGIC_ISP8021:
9e052e2d 2599 ha->isp_type |= DT_ISP8021;
a9083016
GM		 2600 ha->device_type |= DT_ZIO_SUPPORTED;
2601 ha->device_type |= DT_FWI2;
2602 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2603 /* Initialize 82XX ISP flags */
2604 qla82xx_init_flags(ha);
2605 break;
7ec0effd 2606 case PCI_DEVICE_ID_QLOGIC_ISP8044:
9e052e2d 2607 ha->isp_type |= DT_ISP8044;
7ec0effd
AD		 2608 ha->device_type |= DT_ZIO_SUPPORTED;
2609 ha->device_type |= DT_FWI2;
2610 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2611 /* Initialize 82XX ISP flags */
2612 qla82xx_init_flags(ha);
2613 break;
6246b8a1 2614 case PCI_DEVICE_ID_QLOGIC_ISP2031:
9e052e2d 2615 ha->isp_type |= DT_ISP2031;
6246b8a1
GM		 2616 ha->device_type |= DT_ZIO_SUPPORTED;
2617 ha->device_type |= DT_FWI2;
2618 ha->device_type |= DT_IIDMA;
2619 ha->device_type |= DT_T10_PI;
2620 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2621 break;
2622 case PCI_DEVICE_ID_QLOGIC_ISP8031:
9e052e2d 2623 ha->isp_type |= DT_ISP8031;
6246b8a1
GM		 2624 ha->device_type |= DT_ZIO_SUPPORTED;
2625 ha->device_type |= DT_FWI2;
2626 ha->device_type |= DT_IIDMA;
2627 ha->device_type |= DT_T10_PI;
2628 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2629 break;
8ae6d9c7 2630 case PCI_DEVICE_ID_QLOGIC_ISPF001:
9e052e2d 2631 ha->isp_type |= DT_ISPFX00;
8ae6d9c7 2632 break;
f73cb695 2633 case PCI_DEVICE_ID_QLOGIC_ISP2071:
9e052e2d 2634 ha->isp_type |= DT_ISP2071;
f73cb695
CD		 2635 ha->device_type |= DT_ZIO_SUPPORTED;
2636 ha->device_type |= DT_FWI2;
2637 ha->device_type |= DT_IIDMA;
8ce3f570 2638 ha->device_type |= DT_T10_PI;
f73cb695
CD		 2639 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2640 break;
2c5bbbb2 2641 case PCI_DEVICE_ID_QLOGIC_ISP2271:
9e052e2d 2642 ha->isp_type |= DT_ISP2271;
2c5bbbb2
JC		 2643 ha->device_type |= DT_ZIO_SUPPORTED;
2644 ha->device_type |= DT_FWI2;
2645 ha->device_type |= DT_IIDMA;
8ce3f570 2646 ha->device_type |= DT_T10_PI;
2c5bbbb2
JC		 2647 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2648 break;
2b48992f 2649 case PCI_DEVICE_ID_QLOGIC_ISP2261:
9e052e2d 2650 ha->isp_type |= DT_ISP2261;
2b48992f
SC		 2651 ha->device_type |= DT_ZIO_SUPPORTED;
2652 ha->device_type |= DT_FWI2;
2653 ha->device_type |= DT_IIDMA;
8ce3f570 2654 ha->device_type |= DT_T10_PI;
2b48992f
SC		 2655 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2656 break;
ea5b6382 2657 }
e5b68a61 2658
a9083016 2659 if (IS_QLA82XX(ha))
43a9c38b 2660 ha->port_no = ha->portnum & 1;
f73cb695 2661 else {
a9083016
GM		 2662 /* Get adapter physical port no from interrupt pin register. */
2663 pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no);
f73cb695
CD		 2664 if (IS_QLA27XX(ha))
2665 ha->port_no--;
2666 else
2667 ha->port_no = !(ha->port_no & 1);
2668 }
a9083016 2669
7c3df132 2670 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b,
d8424f68 2671 "device_type=0x%x port=%d fw_srisc_address=0x%x.\n",
f73cb695 2672 ha->device_type, ha->port_no, ha->fw_srisc_address);
ea5b6382 2673}
2674
1e99e33a
AV		 2675static void
2676qla2xxx_scan_start(struct Scsi_Host *shost)
2677{
e315cd28 2678 scsi_qla_host_t *vha = shost_priv(shost);
1e99e33a 2679
cbc8eb67
AV		 2680 if (vha->hw->flags.running_gold_fw)
2681 return;
2682
e315cd28
AC		 2683 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
2684 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
2685 set_bit(RSCN_UPDATE, &vha->dpc_flags);
2686 set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags);
1e99e33a
AV		 2687}
2688
2689static int
2690qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time)
2691{
e315cd28 2692 scsi_qla_host_t *vha = shost_priv(shost);
1e99e33a 2693
a5dd506e
BK		 2694 if (test_bit(UNLOADING, &vha->dpc_flags))
2695 return 1;
e315cd28 2696 if (!vha->host)
1e99e33a 2697 return 1;
e315cd28 2698 if (time > vha->hw->loop_reset_delay * HZ)
1e99e33a
AV		 2699 return 1;
2700
e315cd28 2701 return atomic_read(&vha->loop_state) == LOOP_READY;
1e99e33a
AV		 2702}
2703
ec7193e2
QT		 2704static void qla2x00_iocb_work_fn(struct work_struct *work)
2705{
2706 struct scsi_qla_host *vha = container_of(work,
2707 struct scsi_qla_host, iocb_work);
9b3e0f4d
QT		 2708 struct qla_hw_data *ha = vha->hw;
2709 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
2710 int i = 20;
2711 unsigned long flags;
2712
2713 if (test_bit(UNLOADING, &base_vha->dpc_flags))
2714 return;
ec7193e2 2715
9b3e0f4d 2716 while (!list_empty(&vha->work_list) && i > 0) {
ec7193e2 2717 qla2x00_do_work(vha);
9b3e0f4d 2718 i--;
ec7193e2 2719 }
9b3e0f4d
QT		 2720
2721 spin_lock_irqsave(&vha->work_lock, flags);
2722 clear_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags);
2723 spin_unlock_irqrestore(&vha->work_lock, flags);
ec7193e2
QT		 2724}
2725
1da177e4
LT		 2726/*
2727 * PCI driver interface
2728 */
6f039790 2729static int
7ee61397 2730qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
1da177e4 2731{
a1541d5a 2732 int ret = -ENODEV;
1da177e4 2733 struct Scsi_Host *host;
e315cd28
AC		 2734 scsi_qla_host_t *base_vha = NULL;
2735 struct qla_hw_data *ha;
29856e28 2736 char pci_info[30];
7d613ac6 2737 char fw_str[30], wq_name[30];
5433383e 2738 struct scsi_host_template *sht;
642ef983 2739 int bars, mem_only = 0;
e315cd28 2740 uint16_t req_length = 0, rsp_length = 0;
73208dfd
AC		 2741 struct req_que *req = NULL;
2742 struct rsp_que *rsp = NULL;
5601236b 2743 int i;
d7459527 2744
285d0321 2745 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO);
a5326f86 2746 sht = &qla2xxx_driver_template;
5433383e 2747 if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 ||
8bc69e7d 2748 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 ||
4d4df193 2749 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 ||
8bc69e7d 2750 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 ||
c3a2f0df 2751 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 ||
3a03eb79 2752 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 ||
a9083016 2753 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 ||
6246b8a1
GM		 2754 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021 ||
2755 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2031 ||
8ae6d9c7 2756 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8031 ||
7ec0effd 2757 pdev->device == PCI_DEVICE_ID_QLOGIC_ISPF001 ||
f73cb695 2758 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8044 ||
2c5bbbb2 2759 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2071 ||
2b48992f
SC		 2760 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2271 ||
2761 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2261) {
285d0321 2762 bars = pci_select_bars(pdev, IORESOURCE_MEM);
09483916 2763 mem_only = 1;
7c3df132
SK		 2764 ql_dbg_pci(ql_dbg_init, pdev, 0x0007,
2765 "Mem only adapter.\n");
285d0321 2766 }
7c3df132
SK		 2767 ql_dbg_pci(ql_dbg_init, pdev, 0x0008,
2768 "Bars=%d.\n", bars);
285d0321 2769
09483916
BH		 2770 if (mem_only) {
2771 if (pci_enable_device_mem(pdev))
ddff7ed4 2772 return ret;
09483916
BH		 2773 } else {
2774 if (pci_enable_device(pdev))
ddff7ed4 2775 return ret;
09483916 2776 }
285d0321 2777
0927678f
JB		 2778 /* This may fail but that's ok */
2779 pci_enable_pcie_error_reporting(pdev);
285d0321 2780
e315cd28
AC		 2781 ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL);
2782 if (!ha) {
7c3df132
SK		 2783 ql_log_pci(ql_log_fatal, pdev, 0x0009,
2784 "Unable to allocate memory for ha.\n");
ddff7ed4 2785 goto disable_device;
1da177e4 2786 }
7c3df132
SK		 2787 ql_dbg_pci(ql_dbg_init, pdev, 0x000a,
2788 "Memory allocated for ha=%p.\n", ha);
e315cd28 2789 ha->pdev = pdev;
33e79977
QT		 2790 INIT_LIST_HEAD(&ha->tgt.q_full_list);
2791 spin_lock_init(&ha->tgt.q_full_lock);
7560151b 2792 spin_lock_init(&ha->tgt.sess_lock);
2f424b9b
QT		 2793 spin_lock_init(&ha->tgt.atio_lock);
2794
deeae7a6 2795 atomic_set(&ha->nvme_active_aen_cnt, 0);
1da177e4
LT		 2796
2797 /* Clear our data area */
285d0321 2798 ha->bars = bars;
09483916 2799 ha->mem_only = mem_only;
df4bf0bb 2800 spin_lock_init(&ha->hardware_lock);
339aa70e 2801 spin_lock_init(&ha->vport_slock);
a9b6f722 2802 mutex_init(&ha->selflogin_lock);
7a8ab9c8 2803 mutex_init(&ha->optrom_mutex);
1da177e4 2804
ea5b6382 2805 /* Set ISP-type information. */
2806 qla2x00_set_isp_flags(ha);
ca79cf66
DG		 2807
2808 /* Set EEH reset type to fundamental if required by hba */
95676112 2809 if (IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha) ||
f73cb695 2810 IS_QLA83XX(ha) || IS_QLA27XX(ha))
ca79cf66 2811 pdev->needs_freset = 1;
ca79cf66 2812
cba1e47f
CD		 2813 ha->prev_topology = 0;
2814 ha->init_cb_size = sizeof(init_cb_t);
2815 ha->link_data_rate = PORT_SPEED_UNKNOWN;
2816 ha->optrom_size = OPTROM_SIZE_2300;
d1e3635a 2817 ha->max_exchg = FW_MAX_EXCHANGES_CNT;
cba1e47f 2818
abbd8870 2819 /* Assign ISP specific operations. */
1da177e4 2820 if (IS_QLA2100(ha)) {
642ef983 2821 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
1da177e4 2822 ha->mbx_count = MAILBOX_REGISTER_COUNT_2100;
e315cd28
AC		 2823 req_length = REQUEST_ENTRY_CNT_2100;
2824 rsp_length = RESPONSE_ENTRY_CNT_2100;
2825 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
abbd8870 2826 ha->gid_list_info_size = 4;
3a03eb79
AV		 2827 ha->flash_conf_off = ~0;
2828 ha->flash_data_off = ~0;
2829 ha->nvram_conf_off = ~0;
2830 ha->nvram_data_off = ~0;
fd34f556 2831 ha->isp_ops = &qla2100_isp_ops;
1da177e4 2832 } else if (IS_QLA2200(ha)) {
642ef983 2833 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
67ddda35 2834 ha->mbx_count = MAILBOX_REGISTER_COUNT_2200;
e315cd28
AC		 2835 req_length = REQUEST_ENTRY_CNT_2200;
2836 rsp_length = RESPONSE_ENTRY_CNT_2100;
2837 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
abbd8870 2838 ha->gid_list_info_size = 4;
3a03eb79
AV		 2839 ha->flash_conf_off = ~0;
2840 ha->flash_data_off = ~0;
2841 ha->nvram_conf_off = ~0;
2842 ha->nvram_data_off = ~0;
fd34f556 2843 ha->isp_ops = &qla2100_isp_ops;
fca29703 2844 } else if (IS_QLA23XX(ha)) {
642ef983 2845 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
1da177e4 2846 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2847 req_length = REQUEST_ENTRY_CNT_2200;
2848 rsp_length = RESPONSE_ENTRY_CNT_2300;
2849 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
abbd8870 2850 ha->gid_list_info_size = 6;
854165f4 2851 if (IS_QLA2322(ha) || IS_QLA6322(ha))
2852 ha->optrom_size = OPTROM_SIZE_2322;
3a03eb79
AV		 2853 ha->flash_conf_off = ~0;
2854 ha->flash_data_off = ~0;
2855 ha->nvram_conf_off = ~0;
2856 ha->nvram_data_off = ~0;
fd34f556 2857 ha->isp_ops = &qla2300_isp_ops;
4d4df193 2858 } else if (IS_QLA24XX_TYPE(ha)) {
642ef983 2859 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
fca29703 2860 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2861 req_length = REQUEST_ENTRY_CNT_24XX;
2862 rsp_length = RESPONSE_ENTRY_CNT_2300;
2d70c103 2863 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
e315cd28 2864 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2c3dfe3f 2865 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
fca29703 2866 ha->gid_list_info_size = 8;
854165f4 2867 ha->optrom_size = OPTROM_SIZE_24XX;
73208dfd 2868 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX;
fd34f556 2869 ha->isp_ops = &qla24xx_isp_ops;
3a03eb79
AV		 2870 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2871 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2872 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2873 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
c3a2f0df 2874 } else if (IS_QLA25XX(ha)) {
642ef983 2875 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
c3a2f0df 2876 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2877 req_length = REQUEST_ENTRY_CNT_24XX;
2878 rsp_length = RESPONSE_ENTRY_CNT_2300;
2d70c103 2879 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
e315cd28 2880 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
c3a2f0df 2881 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
c3a2f0df
AV		 2882 ha->gid_list_info_size = 8;
2883 ha->optrom_size = OPTROM_SIZE_25XX;
73208dfd 2884 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
c3a2f0df 2885 ha->isp_ops = &qla25xx_isp_ops;
3a03eb79
AV		 2886 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2887 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2888 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2889 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
2890 } else if (IS_QLA81XX(ha)) {
642ef983 2891 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3a03eb79
AV		 2892 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2893 req_length = REQUEST_ENTRY_CNT_24XX;
2894 rsp_length = RESPONSE_ENTRY_CNT_2300;
aa230bc5 2895 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
3a03eb79
AV		 2896 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2897 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2898 ha->gid_list_info_size = 8;
2899 ha->optrom_size = OPTROM_SIZE_81XX;
40859ae5 2900 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3a03eb79
AV		 2901 ha->isp_ops = &qla81xx_isp_ops;
2902 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2903 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2904 ha->nvram_conf_off = ~0;
2905 ha->nvram_data_off = ~0;
a9083016 2906 } else if (IS_QLA82XX(ha)) {
642ef983 2907 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
a9083016
GM		 2908 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2909 req_length = REQUEST_ENTRY_CNT_82XX;
2910 rsp_length = RESPONSE_ENTRY_CNT_82XX;
2911 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2912 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2913 ha->gid_list_info_size = 8;
2914 ha->optrom_size = OPTROM_SIZE_82XX;
087c621e 2915 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
a9083016
GM		 2916 ha->isp_ops = &qla82xx_isp_ops;
2917 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2918 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2919 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2920 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
7ec0effd
AD		 2921 } else if (IS_QLA8044(ha)) {
2922 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2923 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2924 req_length = REQUEST_ENTRY_CNT_82XX;
2925 rsp_length = RESPONSE_ENTRY_CNT_82XX;
2926 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2927 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2928 ha->gid_list_info_size = 8;
2929 ha->optrom_size = OPTROM_SIZE_83XX;
2930 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2931 ha->isp_ops = &qla8044_isp_ops;
2932 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2933 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2934 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2935 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
6246b8a1 2936 } else if (IS_QLA83XX(ha)) {
7d613ac6 2937 ha->portnum = PCI_FUNC(ha->pdev->devfn);
642ef983 2938 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
6246b8a1 2939 ha->mbx_count = MAILBOX_REGISTER_COUNT;
f2ea653f 2940 req_length = REQUEST_ENTRY_CNT_83XX;
e7b42e33 2941 rsp_length = RESPONSE_ENTRY_CNT_83XX;
b8aa4bdf 2942 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
6246b8a1
GM		 2943 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2944 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2945 ha->gid_list_info_size = 8;
2946 ha->optrom_size = OPTROM_SIZE_83XX;
2947 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2948 ha->isp_ops = &qla83xx_isp_ops;
2949 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2950 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2951 ha->nvram_conf_off = ~0;
2952 ha->nvram_data_off = ~0;
8ae6d9c7
GM		 2953 } else if (IS_QLAFX00(ha)) {
2954 ha->max_fibre_devices = MAX_FIBRE_DEVICES_FX00;
2955 ha->mbx_count = MAILBOX_REGISTER_COUNT_FX00;
2956 ha->aen_mbx_count = AEN_MAILBOX_REGISTER_COUNT_FX00;
2957 req_length = REQUEST_ENTRY_CNT_FX00;
2958 rsp_length = RESPONSE_ENTRY_CNT_FX00;
8ae6d9c7
GM		 2959 ha->isp_ops = &qlafx00_isp_ops;
2960 ha->port_down_retry_count = 30; /* default value */
2961 ha->mr.fw_hbt_cnt = QLAFX00_HEARTBEAT_INTERVAL;
2962 ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL;
71e56003 2963 ha->mr.fw_critemp_timer_tick = QLAFX00_CRITEMP_INTERVAL;
8ae6d9c7 2964 ha->mr.fw_hbt_en = 1;
e8f5e95d
AB		 2965 ha->mr.host_info_resend = false;
2966 ha->mr.hinfo_resend_timer_tick = QLAFX00_HINFO_RESEND_INTERVAL;
f73cb695
CD		 2967 } else if (IS_QLA27XX(ha)) {
2968 ha->portnum = PCI_FUNC(ha->pdev->devfn);
2969 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2970 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e7b42e33
QT		 2971 req_length = REQUEST_ENTRY_CNT_83XX;
2972 rsp_length = RESPONSE_ENTRY_CNT_83XX;
b20f02e1 2973 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
f73cb695
CD		 2974 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2975 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2976 ha->gid_list_info_size = 8;
2977 ha->optrom_size = OPTROM_SIZE_83XX;
2978 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2979 ha->isp_ops = &qla27xx_isp_ops;
2980 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2981 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2982 ha->nvram_conf_off = ~0;
2983 ha->nvram_data_off = ~0;
1da177e4 2984 }
6246b8a1 2985
7c3df132
SK		 2986 ql_dbg_pci(ql_dbg_init, pdev, 0x001e,
2987 "mbx_count=%d, req_length=%d, "
2988 "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, "
642ef983
CD		 2989 "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, "
2990 "max_fibre_devices=%d.\n",
7c3df132
SK		 2991 ha->mbx_count, req_length, rsp_length, ha->max_loop_id,
2992 ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size,
642ef983 2993 ha->nvram_npiv_size, ha->max_fibre_devices);
7c3df132
SK		 2994 ql_dbg_pci(ql_dbg_init, pdev, 0x001f,
2995 "isp_ops=%p, flash_conf_off=%d, "
2996 "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n",
2997 ha->isp_ops, ha->flash_conf_off, ha->flash_data_off,
2998 ha->nvram_conf_off, ha->nvram_data_off);
706f457d
GM		 2999
3000 /* Configure PCI I/O space */
3001 ret = ha->isp_ops->iospace_config(ha);
3002 if (ret)
0a63ad12 3003 goto iospace_config_failed;
706f457d
GM		 3004
3005 ql_log_pci(ql_log_info, pdev, 0x001d,
3006 "Found an ISP%04X irq %d iobase 0x%p.\n",
3007 pdev->device, pdev->irq, ha->iobase);
6c2f527c 3008 mutex_init(&ha->vport_lock);
d7459527 3009 mutex_init(&ha->mq_lock);
0b05a1f0
MB		 3010 init_completion(&ha->mbx_cmd_comp);
3011 complete(&ha->mbx_cmd_comp);
3012 init_completion(&ha->mbx_intr_comp);
23f2ebd1 3013 init_completion(&ha->dcbx_comp);
f356bef1 3014 init_completion(&ha->lb_portup_comp);
1da177e4 3015
2c3dfe3f 3016 set_bit(0, (unsigned long *) ha->vp_idx_map);
1da177e4 3017
53303c42 3018 qla2x00_config_dma_addressing(ha);
7c3df132
SK		 3019 ql_dbg_pci(ql_dbg_init, pdev, 0x0020,
3020 "64 Bit addressing is %s.\n",
3021 ha->flags.enable_64bit_addressing ? "enable" :
3022 "disable");
73208dfd 3023 ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp);
b2a72ec3 3024 if (ret) {
7c3df132
SK		 3025 ql_log_pci(ql_log_fatal, pdev, 0x0031,
3026 "Failed to allocate memory for adapter, aborting.\n");
1da177e4 3027
e315cd28
AC		 3028 goto probe_hw_failed;
3029 }
3030
73208dfd 3031 req->max_q_depth = MAX_Q_DEPTH;
e315cd28 3032 if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU)
73208dfd
AC		 3033 req->max_q_depth = ql2xmaxqdepth;
3034
e315cd28
AC		 3035
3036 base_vha = qla2x00_create_host(sht, ha);
3037 if (!base_vha) {
a1541d5a 3038 ret = -ENOMEM;
e315cd28 3039 goto probe_hw_failed;
1da177e4
LT		 3040 }
3041
e315cd28 3042 pci_set_drvdata(pdev, base_vha);
6b383979 3043 set_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags);
e315cd28 3044
e315cd28 3045 host = base_vha->host;
2afa19a9 3046 base_vha->req = req;
73208dfd 3047 if (IS_QLA2XXX_MIDTYPE(ha))
1429f044 3048 base_vha->mgmt_svr_loop_id = NPH_MGMT_SERVER;
73208dfd 3049 else
e315cd28
AC		 3050 base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER +
3051 base_vha->vp_idx;
58548cb5 3052
8ae6d9c7
GM		 3053 /* Setup fcport template structure. */
3054 ha->mr.fcport.vha = base_vha;
3055 ha->mr.fcport.port_type = FCT_UNKNOWN;
3056 ha->mr.fcport.loop_id = FC_NO_LOOP_ID;
3057 qla2x00_set_fcport_state(&ha->mr.fcport, FCS_UNCONFIGURED);
3058 ha->mr.fcport.supported_classes = FC_COS_UNSPECIFIED;
3059 ha->mr.fcport.scan_state = 1;
3060
58548cb5
GM		 3061 /* Set the SG table size based on ISP type */
3062 if (!IS_FWI2_CAPABLE(ha)) {
3063 if (IS_QLA2100(ha))
3064 host->sg_tablesize = 32;
3065 } else {
3066 if (!IS_QLA82XX(ha))
3067 host->sg_tablesize = QLA_SG_ALL;
3068 }
642ef983 3069 host->max_id = ha->max_fibre_devices;
e315cd28
AC		 3070 host->cmd_per_lun = 3;
3071 host->unique_id = host->host_no;
e02587d7 3072 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif)
0c470874
AE		 3073 host->max_cmd_len = 32;
3074 else
3075 host->max_cmd_len = MAX_CMDSZ;
e315cd28 3076 host->max_channel = MAX_BUSES - 1;
755f516b
HR		 3077 /* Older HBAs support only 16-bit LUNs */
3078 if (!IS_QLAFX00(ha) && !IS_FWI2_CAPABLE(ha) &&
3079 ql2xmaxlun > 0xffff)
3080 host->max_lun = 0xffff;
3081 else
3082 host->max_lun = ql2xmaxlun;
e315cd28 3083 host->transportt = qla2xxx_transport_template;
9a069e19 3084 sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC);
e315cd28 3085
7c3df132
SK		 3086 ql_dbg(ql_dbg_init, base_vha, 0x0033,
3087 "max_id=%d this_id=%d "
3088 "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d "
1abf635d 3089 "max_lun=%llu transportt=%p, vendor_id=%llu.\n", host->max_id,
7c3df132
SK		 3090 host->this_id, host->cmd_per_lun, host->unique_id,
3091 host->max_cmd_len, host->max_channel, host->max_lun,
3092 host->transportt, sht->vendor_id);
3093
1010f21e
HM		 3094 INIT_WORK(&base_vha->iocb_work, qla2x00_iocb_work_fn);
3095
d7459527
MH		 3096 /* Set up the irqs */
3097 ret = qla2x00_request_irqs(ha, rsp);
3098 if (ret)
6a2cf8d3 3099 goto probe_failed;
d7459527 3100
9a347ff4 3101 /* Alloc arrays of request and response ring ptrs */
6d634067
BK		 3102 ret = qla2x00_alloc_queues(ha, req, rsp);
3103 if (ret) {
9a347ff4
CD		 3104 ql_log(ql_log_fatal, base_vha, 0x003d,
3105 "Failed to allocate memory for queue pointers..."
3106 "aborting.\n");
6a2cf8d3 3107 goto probe_failed;
9a347ff4
CD		 3108 }
3109
5601236b
MH		 3110 if (ha->mqenable && shost_use_blk_mq(host)) {
3111 /* number of hardware queues supported by blk/scsi-mq*/
3112 host->nr_hw_queues = ha->max_qpairs;
3113
3114 ql_dbg(ql_dbg_init, base_vha, 0x0192,
3115 "blk/scsi-mq enabled, HW queues = %d.\n", host->nr_hw_queues);
c38d1baf
HM		 3116 } else {
3117 if (ql2xnvmeenable) {
3118 host->nr_hw_queues = ha->max_qpairs;
3119 ql_dbg(ql_dbg_init, base_vha, 0x0194,
3120 "FC-NVMe support is enabled, HW queues=%d\n",
3121 host->nr_hw_queues);
3122 } else {
3123 ql_dbg(ql_dbg_init, base_vha, 0x0193,
3124 "blk/scsi-mq disabled.\n");
3125 }
3126 }
5601236b 3127
2d70c103 3128 qlt_probe_one_stage1(base_vha, ha);
9a347ff4 3129
90a86fc0
JC		 3130 pci_save_state(pdev);
3131
9a347ff4 3132 /* Assign back pointers */
2afa19a9
AC		 3133 rsp->req = req;
3134 req->rsp = rsp;
9a347ff4 3135
8ae6d9c7
GM		 3136 if (IS_QLAFX00(ha)) {
3137 ha->rsp_q_map[0] = rsp;
3138 ha->req_q_map[0] = req;
3139 set_bit(0, ha->req_qid_map);
3140 set_bit(0, ha->rsp_qid_map);
3141 }
3142
08029990
AV		 3143 /* FWI2-capable only. */
3144 req->req_q_in = &ha->iobase->isp24.req_q_in;
3145 req->req_q_out = &ha->iobase->isp24.req_q_out;
3146 rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in;
3147 rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out;
f73cb695 3148 if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
08029990
AV		 3149 req->req_q_in = &ha->mqiobase->isp25mq.req_q_in;
3150 req->req_q_out = &ha->mqiobase->isp25mq.req_q_out;
3151 rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in;
3152 rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out;
17d98630
AC		 3153 }
3154
8ae6d9c7
GM		 3155 if (IS_QLAFX00(ha)) {
3156 req->req_q_in = &ha->iobase->ispfx00.req_q_in;
3157 req->req_q_out = &ha->iobase->ispfx00.req_q_out;
3158 rsp->rsp_q_in = &ha->iobase->ispfx00.rsp_q_in;
3159 rsp->rsp_q_out = &ha->iobase->ispfx00.rsp_q_out;
3160 }
3161
7ec0effd 3162 if (IS_P3P_TYPE(ha)) {
a9083016
GM		 3163 req->req_q_out = &ha->iobase->isp82.req_q_out[0];
3164 rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0];
3165 rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0];
3166 }
3167
7c3df132
SK		 3168 ql_dbg(ql_dbg_multiq, base_vha, 0xc009,
3169 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
3170 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
3171 ql_dbg(ql_dbg_multiq, base_vha, 0xc00a,
3172 "req->req_q_in=%p req->req_q_out=%p "
3173 "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
3174 req->req_q_in, req->req_q_out,
3175 rsp->rsp_q_in, rsp->rsp_q_out);
3176 ql_dbg(ql_dbg_init, base_vha, 0x003e,
3177 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
3178 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
3179 ql_dbg(ql_dbg_init, base_vha, 0x003f,
3180 "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
3181 req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out);
1da177e4 3182
8ae6d9c7 3183 if (ha->isp_ops->initialize_adapter(base_vha)) {
7c3df132
SK		 3184 ql_log(ql_log_fatal, base_vha, 0x00d6,
3185 "Failed to initialize adapter - Adapter flags %x.\n",
3186 base_vha->device_flags);
1da177e4 3187
a9083016
GM		 3188 if (IS_QLA82XX(ha)) {
3189 qla82xx_idc_lock(ha);
3190 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 3191 QLA8XXX_DEV_FAILED);
a9083016 3192 qla82xx_idc_unlock(ha);
7c3df132
SK		 3193 ql_log(ql_log_fatal, base_vha, 0x00d7,
3194 "HW State: FAILED.\n");
7ec0effd
AD		 3195 } else if (IS_QLA8044(ha)) {
3196 qla8044_idc_lock(ha);
3197 qla8044_wr_direct(base_vha,
3198 QLA8044_CRB_DEV_STATE_INDEX,
3199 QLA8XXX_DEV_FAILED);
3200 qla8044_idc_unlock(ha);
3201 ql_log(ql_log_fatal, base_vha, 0x0150,
3202 "HW State: FAILED.\n");
a9083016
GM		 3203 }
3204
a1541d5a 3205 ret = -ENODEV;
1da177e4
LT		 3206 goto probe_failed;
3207 }
3208
3b1bef64
CD		 3209 if (IS_QLAFX00(ha))
3210 host->can_queue = QLAFX00_MAX_CANQUEUE;
3211 else
3212 host->can_queue = req->num_outstanding_cmds - 10;
3213
3214 ql_dbg(ql_dbg_init, base_vha, 0x0032,
3215 "can_queue=%d, req=%p, mgmt_svr_loop_id=%d, sg_tablesize=%d.\n",
3216 host->can_queue, base_vha->req,
3217 base_vha->mgmt_svr_loop_id, host->sg_tablesize);
3218
9b3e0f4d 3219 ha->wq = alloc_workqueue("qla2xxx_wq", 0, 0);
a01c77d2 3220
e326d22a
QT		 3221 if (ha->mqenable) {
3222 bool mq = false;
3223 bool startit = false;
e326d22a
QT		 3224
3225 if (QLA_TGT_MODE_ENABLED()) {
3226 mq = true;
3227 startit = false;
3228 }
3229
3230 if ((ql2x_ini_mode == QLA2XXX_INI_MODE_ENABLED) &&
3231 shost_use_blk_mq(host)) {
3232 mq = true;
3233 startit = true;
3234 }
3235
3236 if (mq) {
3237 /* Create start of day qpairs for Block MQ */
5601236b 3238 for (i = 0; i < ha->max_qpairs; i++)
e326d22a 3239 qla2xxx_create_qpair(base_vha, 5, 0, startit);
5601236b
MH		 3240 }
3241 }
68ca949c 3242
cbc8eb67
AV		 3243 if (ha->flags.running_gold_fw)
3244 goto skip_dpc;
3245
1da177e4
LT		 3246 /*
3247 * Startup the kernel thread for this host adapter
3248 */
39a11240 3249 ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha,
7c3df132 3250 "%s_dpc", base_vha->host_str);
39a11240 3251 if (IS_ERR(ha->dpc_thread)) {
7c3df132
SK		 3252 ql_log(ql_log_fatal, base_vha, 0x00ed,
3253 "Failed to start DPC thread.\n");
39a11240 3254 ret = PTR_ERR(ha->dpc_thread);
e2532b4a 3255 ha->dpc_thread = NULL;
1da177e4
LT		 3256 goto probe_failed;
3257 }
7c3df132
SK		 3258 ql_dbg(ql_dbg_init, base_vha, 0x00ee,
3259 "DPC thread started successfully.\n");
1da177e4 3260
2d70c103
NB		 3261 /*
3262 * If we're not coming up in initiator mode, we might sit for
3263 * a while without waking up the dpc thread, which leads to a
3264 * stuck process warning. So just kick the dpc once here and
3265 * let the kthread start (and go back to sleep in qla2x00_do_dpc).
3266 */
3267 qla2xxx_wake_dpc(base_vha);
3268
f3ddac19
CD		 3269 INIT_WORK(&ha->board_disable, qla2x00_disable_board_on_pci_error);
3270
81178772
SK		 3271 if (IS_QLA8031(ha) || IS_MCTP_CAPABLE(ha)) {
3272 sprintf(wq_name, "qla2xxx_%lu_dpc_lp_wq", base_vha->host_no);
3273 ha->dpc_lp_wq = create_singlethread_workqueue(wq_name);
3274 INIT_WORK(&ha->idc_aen, qla83xx_service_idc_aen);
3275
3276 sprintf(wq_name, "qla2xxx_%lu_dpc_hp_wq", base_vha->host_no);
3277 ha->dpc_hp_wq = create_singlethread_workqueue(wq_name);
3278 INIT_WORK(&ha->nic_core_reset, qla83xx_nic_core_reset_work);
3279 INIT_WORK(&ha->idc_state_handler,
3280 qla83xx_idc_state_handler_work);
3281 INIT_WORK(&ha->nic_core_unrecoverable,
3282 qla83xx_nic_core_unrecoverable_work);
3283 }
3284
cbc8eb67 3285skip_dpc:
e315cd28
AC		 3286 list_add_tail(&base_vha->list, &ha->vp_list);
3287 base_vha->host->irq = ha->pdev->irq;
1da177e4
LT		 3288
3289 /* Initialized the timer */
8e5f4ba0 3290 qla2x00_start_timer(base_vha, WATCH_INTERVAL);
7c3df132
SK		 3291 ql_dbg(ql_dbg_init, base_vha, 0x00ef,
3292 "Started qla2x00_timer with "
3293 "interval=%d.\n", WATCH_INTERVAL);
3294 ql_dbg(ql_dbg_init, base_vha, 0x00f0,
3295 "Detected hba at address=%p.\n",
3296 ha);
d19044c3 3297
e02587d7 3298 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) {
bad75002 3299 if (ha->fw_attributes & BIT_4) {
9e522cd8 3300 int prot = 0, guard;
bad75002 3301 base_vha->flags.difdix_supported = 1;
7c3df132
SK		 3302 ql_dbg(ql_dbg_init, base_vha, 0x00f1,
3303 "Registering for DIF/DIX type 1 and 3 protection.\n");
8cb2049c
AE		 3304 if (ql2xenabledif == 1)
3305 prot = SHOST_DIX_TYPE0_PROTECTION;
bad75002 3306 scsi_host_set_prot(host,
8cb2049c 3307 prot | SHOST_DIF_TYPE1_PROTECTION
0c470874 3308 | SHOST_DIF_TYPE2_PROTECTION
bad75002
AE		 3309 | SHOST_DIF_TYPE3_PROTECTION
3310 | SHOST_DIX_TYPE1_PROTECTION
0c470874 3311 | SHOST_DIX_TYPE2_PROTECTION
bad75002 3312 | SHOST_DIX_TYPE3_PROTECTION);
9e522cd8
AE		 3313
3314 guard = SHOST_DIX_GUARD_CRC;
3315
3316 if (IS_PI_IPGUARD_CAPABLE(ha) &&
3317 (ql2xenabledif > 1 || IS_PI_DIFB_DIX0_CAPABLE(ha)))
3318 guard |= SHOST_DIX_GUARD_IP;
3319
3320 scsi_host_set_guard(host, guard);
bad75002
AE		 3321 } else
3322 base_vha->flags.difdix_supported = 0;
3323 }
3324
a9083016
GM		 3325 ha->isp_ops->enable_intrs(ha);
3326
1fe19ee4
AB		 3327 if (IS_QLAFX00(ha)) {
3328 ret = qlafx00_fx_disc(base_vha,
3329 &base_vha->hw->mr.fcport, FXDISC_GET_CONFIG_INFO);
3330 host->sg_tablesize = (ha->mr.extended_io_enabled) ?
3331 QLA_SG_ALL : 128;
3332 }
3333
a1541d5a
AV		 3334 ret = scsi_add_host(host, &pdev->dev);
3335 if (ret)
3336 goto probe_failed;
3337
1486400f
MR		 3338 base_vha->flags.init_done = 1;
3339 base_vha->flags.online = 1;
edaa5c74 3340 ha->prev_minidump_failed = 0;
1486400f 3341
7c3df132
SK		 3342 ql_dbg(ql_dbg_init, base_vha, 0x00f2,
3343 "Init done and hba is online.\n");
3344
726b8548
QT		 3345 if (qla_ini_mode_enabled(base_vha) ||
3346 qla_dual_mode_enabled(base_vha))
2d70c103
NB		 3347 scsi_scan_host(host);
3348 else
3349 ql_dbg(ql_dbg_init, base_vha, 0x0122,
3350 "skipping scsi_scan_host() for non-initiator port\n");
1e99e33a 3351
e315cd28 3352 qla2x00_alloc_sysfs_attr(base_vha);
a1541d5a 3353
8ae6d9c7 3354 if (IS_QLAFX00(ha)) {
8ae6d9c7
GM		 3355 ret = qlafx00_fx_disc(base_vha,
3356 &base_vha->hw->mr.fcport, FXDISC_GET_PORT_INFO);
3357
3358 /* Register system information */
3359 ret = qlafx00_fx_disc(base_vha,
3360 &base_vha->hw->mr.fcport, FXDISC_REG_HOST_INFO);
3361 }
3362
e315cd28 3363 qla2x00_init_host_attr(base_vha);
a1541d5a 3364
e315cd28 3365 qla2x00_dfs_setup(base_vha);
df613b96 3366
03eb912a
AB		 3367 ql_log(ql_log_info, base_vha, 0x00fb,
3368 "QLogic %s - %s.\n", ha->model_number, ha->model_desc);
7c3df132
SK		 3369 ql_log(ql_log_info, base_vha, 0x00fc,
3370 "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n",
3371 pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info),
3372 pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-',
3373 base_vha->host_no,
df57caba 3374 ha->isp_ops->fw_version_str(base_vha, fw_str, sizeof(fw_str)));
1da177e4 3375
2d70c103
NB		 3376 qlt_add_target(ha, base_vha);
3377
6b383979 3378 clear_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags);
a29b3dd7
JC		 3379
3380 if (test_bit(UNLOADING, &base_vha->dpc_flags))
3381 return -ENODEV;
3382
e4e3a2ce
QT		 3383 if (ha->flags.detected_lr_sfp) {
3384 ql_log(ql_log_info, base_vha, 0xffff,
3385 "Reset chip to pick up LR SFP setting\n");
3386 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
3387 qla2xxx_wake_dpc(base_vha);
3388 }
3389
1da177e4
LT		 3390 return 0;
3391
3392probe_failed:
b9978769
AV		 3393 if (base_vha->timer_active)
3394 qla2x00_stop_timer(base_vha);
3395 base_vha->flags.online = 0;
3396 if (ha->dpc_thread) {
3397 struct task_struct *t = ha->dpc_thread;
3398
3399 ha->dpc_thread = NULL;
3400 kthread_stop(t);
3401 }
3402
e315cd28 3403 qla2x00_free_device(base_vha);
e315cd28 3404 scsi_host_put(base_vha->host);
6d634067
BK		 3405 /*
3406 * Need to NULL out local req/rsp after
3407 * qla2x00_free_device => qla2x00_free_queues frees
3408 * what these are pointing to. Or else we'll
3409 * fall over below in qla2x00_free_req/rsp_que.
3410 */
3411 req = NULL;
3412 rsp = NULL;
1da177e4 3413
e315cd28 3414probe_hw_failed:
d64d6c56 3415 qla2x00_mem_free(ha);
3416 qla2x00_free_req_que(ha, req);
3417 qla2x00_free_rsp_que(ha, rsp);
1a2fbf18
JL		 3418 qla2x00_clear_drv_active(ha);
3419
0a63ad12 3420iospace_config_failed:
7ec0effd 3421 if (IS_P3P_TYPE(ha)) {
0a63ad12 3422 if (!ha->nx_pcibase)
f73cb695 3423 iounmap((device_reg_t *)ha->nx_pcibase);
a9083016 3424 if (!ql2xdbwr)
f73cb695 3425 iounmap((device_reg_t *)ha->nxdb_wr_ptr);
a9083016
GM		 3426 } else {
3427 if (ha->iobase)
3428 iounmap(ha->iobase);
8ae6d9c7
GM		 3429 if (ha->cregbase)
3430 iounmap(ha->cregbase);
a9083016 3431 }
e315cd28
AC		 3432 pci_release_selected_regions(ha->pdev, ha->bars);
3433 kfree(ha);
1da177e4 3434
ddff7ed4 3435disable_device:
e315cd28 3436 pci_disable_device(pdev);
a1541d5a 3437 return ret;
1da177e4 3438}
1da177e4 3439
e30d1756
MI		 3440static void
3441qla2x00_shutdown(struct pci_dev *pdev)
3442{
3443 scsi_qla_host_t *vha;
3444 struct qla_hw_data *ha;
3445
3446 vha = pci_get_drvdata(pdev);
3447 ha = vha->hw;
3448
efdb5760
SC		 3449 ql_log(ql_log_info, vha, 0xfffa,
3450 "Adapter shutdown\n");
3451
3452 /*
3453 * Prevent future board_disable and wait
3454 * until any pending board_disable has completed.
3455 */
3456 set_bit(PFLG_DRIVER_REMOVING, &vha->pci_flags);
3457 cancel_work_sync(&ha->board_disable);
3458
3459 if (!atomic_read(&pdev->enable_cnt))
3460 return;
3461
42479343
AB		 3462 /* Notify ISPFX00 firmware */
3463 if (IS_QLAFX00(ha))
3464 qlafx00_driver_shutdown(vha, 20);
3465
e30d1756
MI		 3466 /* Turn-off FCE trace */
3467 if (ha->flags.fce_enabled) {
3468 qla2x00_disable_fce_trace(vha, NULL, NULL);
3469 ha->flags.fce_enabled = 0;
3470 }
3471
3472 /* Turn-off EFT trace */
3473 if (ha->eft)
3474 qla2x00_disable_eft_trace(vha);
3475
3407fc37
QT		 3476 if (IS_QLA25XX(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha)) {
3477 if (ha->flags.fw_started)
3478 qla2x00_abort_isp_cleanup(vha);
3479 } else {
3480 /* Stop currently executing firmware. */
3481 qla2x00_try_to_stop_firmware(vha);
3482 }
e30d1756
MI		 3483
3484 /* Turn adapter off line */
3485 vha->flags.online = 0;
3486
3487 /* turn-off interrupts on the card */
3488 if (ha->interrupts_on) {
3489 vha->flags.init_done = 0;
3490 ha->isp_ops->disable_intrs(ha);
3491 }
3492
3493 qla2x00_free_irqs(vha);
3494
3495 qla2x00_free_fw_dump(ha);
61d41f61 3496
61d41f61 3497 pci_disable_device(pdev);
efdb5760
SC		 3498 ql_log(ql_log_info, vha, 0xfffe,
3499 "Adapter shutdown successfully.\n");
e30d1756
MI		 3500}
3501
fe1b806f 3502/* Deletes all the virtual ports for a given ha */
4c993f76 3503static void
fe1b806f 3504qla2x00_delete_all_vps(struct qla_hw_data *ha, scsi_qla_host_t *base_vha)
1da177e4 3505{
fe1b806f 3506 scsi_qla_host_t *vha;
feafb7b1 3507 unsigned long flags;
e315cd28 3508
43ebf16d
AE		 3509 mutex_lock(&ha->vport_lock);
3510 while (ha->cur_vport_count) {
43ebf16d 3511 spin_lock_irqsave(&ha->vport_slock, flags);
feafb7b1 3512
43ebf16d
AE		 3513 BUG_ON(base_vha->list.next == &ha->vp_list);
3514 /* This assumes first entry in ha->vp_list is always base vha */
3515 vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list);
52c82823 3516 scsi_host_get(vha->host);
feafb7b1 3517
43ebf16d
AE		 3518 spin_unlock_irqrestore(&ha->vport_slock, flags);
3519 mutex_unlock(&ha->vport_lock);
3520
3521 fc_vport_terminate(vha->fc_vport);
3522 scsi_host_put(vha->host);
feafb7b1 3523
43ebf16d 3524 mutex_lock(&ha->vport_lock);
e315cd28 3525 }
43ebf16d 3526 mutex_unlock(&ha->vport_lock);
fe1b806f 3527}
1da177e4 3528
fe1b806f
CD		 3529/* Stops all deferred work threads */
3530static void
3531qla2x00_destroy_deferred_work(struct qla_hw_data *ha)
3532{
7d613ac6
SV		 3533 /* Cancel all work and destroy DPC workqueues */
3534 if (ha->dpc_lp_wq) {
3535 cancel_work_sync(&ha->idc_aen);
3536 destroy_workqueue(ha->dpc_lp_wq);
3537 ha->dpc_lp_wq = NULL;
3538 }
3539
3540 if (ha->dpc_hp_wq) {
3541 cancel_work_sync(&ha->nic_core_reset);
3542 cancel_work_sync(&ha->idc_state_handler);
3543 cancel_work_sync(&ha->nic_core_unrecoverable);
3544 destroy_workqueue(ha->dpc_hp_wq);
3545 ha->dpc_hp_wq = NULL;
3546 }
3547
b9978769
AV		 3548 /* Kill the kernel thread for this host */
3549 if (ha->dpc_thread) {
3550 struct task_struct *t = ha->dpc_thread;
3551
3552 /*
3553 * qla2xxx_wake_dpc checks for ->dpc_thread
3554 * so we need to zero it out.
3555 */
3556 ha->dpc_thread = NULL;
3557 kthread_stop(t);
3558 }
fe1b806f 3559}
1da177e4 3560
fe1b806f
CD		 3561static void
3562qla2x00_unmap_iobases(struct qla_hw_data *ha)
3563{
a9083016 3564 if (IS_QLA82XX(ha)) {
b963752f 3565
f73cb695 3566 iounmap((device_reg_t *)ha->nx_pcibase);
a9083016 3567 if (!ql2xdbwr)
f73cb695 3568 iounmap((device_reg_t *)ha->nxdb_wr_ptr);
a9083016
GM		 3569 } else {
3570 if (ha->iobase)
3571 iounmap(ha->iobase);
1da177e4 3572
8ae6d9c7
GM		 3573 if (ha->cregbase)
3574 iounmap(ha->cregbase);
3575
a9083016
GM		 3576 if (ha->mqiobase)
3577 iounmap(ha->mqiobase);
6246b8a1 3578
f73cb695 3579 if ((IS_QLA83XX(ha) || IS_QLA27XX(ha)) && ha->msixbase)
6246b8a1 3580 iounmap(ha->msixbase);
a9083016 3581 }
fe1b806f
CD		 3582}
3583
3584static void
db7157d4 3585qla2x00_clear_drv_active(struct qla_hw_data *ha)
fe1b806f 3586{
fe1b806f
CD		 3587 if (IS_QLA8044(ha)) {
3588 qla8044_idc_lock(ha);
c41afc9a 3589 qla8044_clear_drv_active(ha);
fe1b806f
CD		 3590 qla8044_idc_unlock(ha);
3591 } else if (IS_QLA82XX(ha)) {
3592 qla82xx_idc_lock(ha);
3593 qla82xx_clear_drv_active(ha);
3594 qla82xx_idc_unlock(ha);
3595 }
3596}
3597
3598static void
3599qla2x00_remove_one(struct pci_dev *pdev)
3600{
3601 scsi_qla_host_t *base_vha;
3602 struct qla_hw_data *ha;
3603
beb9e315
JL		 3604 base_vha = pci_get_drvdata(pdev);
3605 ha = base_vha->hw;
3606
3607 /* Indicate device removal to prevent future board_disable and wait
3608 * until any pending board_disable has completed. */
3609 set_bit(PFLG_DRIVER_REMOVING, &base_vha->pci_flags);
3610 cancel_work_sync(&ha->board_disable);
3611
fe1b806f 3612 /*
beb9e315
JL		 3613 * If the PCI device is disabled then there was a PCI-disconnect and
3614 * qla2x00_disable_board_on_pci_error has taken care of most of the
3615 * resources.
fe1b806f 3616 */
beb9e315 3617 if (!atomic_read(&pdev->enable_cnt)) {
726b8548
QT		 3618 dma_free_coherent(&ha->pdev->dev, base_vha->gnl.size,
3619 base_vha->gnl.l, base_vha->gnl.ldma);
3620
beb9e315
JL		 3621 scsi_host_put(base_vha->host);
3622 kfree(ha);
3623 pci_set_drvdata(pdev, NULL);
fe1b806f 3624 return;
beb9e315 3625 }
638a1a01
SC		 3626 qla2x00_wait_for_hba_ready(base_vha);
3627
2ce87cc5
QT		 3628 qla2x00_wait_for_sess_deletion(base_vha);
3629
726b8548
QT		 3630 /*
3631 * if UNLOAD flag is already set, then continue unload,
783e0dc4
SC		 3632 * where it was set first.
3633 */
3634 if (test_bit(UNLOADING, &base_vha->dpc_flags))
3635 return;
3636
fe1b806f 3637 set_bit(UNLOADING, &base_vha->dpc_flags);
e84067d7
DG		 3638
3639 qla_nvme_delete(base_vha);
3640
726b8548
QT		 3641 dma_free_coherent(&ha->pdev->dev,
3642 base_vha->gnl.size, base_vha->gnl.l, base_vha->gnl.ldma);
fe1b806f 3643
a4239945
QT		 3644 vfree(base_vha->scan.l);
3645
fe1b806f
CD		 3646 if (IS_QLAFX00(ha))
3647 qlafx00_driver_shutdown(base_vha, 20);
3648
3649 qla2x00_delete_all_vps(ha, base_vha);
3650
3651 if (IS_QLA8031(ha)) {
3652 ql_dbg(ql_dbg_p3p, base_vha, 0xb07e,
3653 "Clearing fcoe driver presence.\n");
3654 if (qla83xx_clear_drv_presence(base_vha) != QLA_SUCCESS)
3655 ql_dbg(ql_dbg_p3p, base_vha, 0xb079,
3656 "Error while clearing DRV-Presence.\n");
3657 }
3658
3659 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
3660
3661 qla2x00_dfs_remove(base_vha);
3662
3663 qla84xx_put_chip(base_vha);
3664
3665 /* Disable timer */
3666 if (base_vha->timer_active)
3667 qla2x00_stop_timer(base_vha);
3668
3669 base_vha->flags.online = 0;
3670
b0d6cabd
HM		 3671 /* free DMA memory */
3672 if (ha->exlogin_buf)
3673 qla2x00_free_exlogin_buffer(ha);
3674
2f56a7f1
HM		 3675 /* free DMA memory */
3676 if (ha->exchoffld_buf)
3677 qla2x00_free_exchoffld_buffer(ha);
3678
fe1b806f
CD		 3679 qla2x00_destroy_deferred_work(ha);
3680
3681 qlt_remove_target(ha, base_vha);
3682
3683 qla2x00_free_sysfs_attr(base_vha, true);
3684
3685 fc_remove_host(base_vha->host);
482c9dc7 3686 qlt_remove_target_resources(ha);
fe1b806f
CD		 3687
3688 scsi_remove_host(base_vha->host);
3689
3690 qla2x00_free_device(base_vha);
3691
db7157d4 3692 qla2x00_clear_drv_active(ha);
fe1b806f 3693
d2749ffa
AE		 3694 scsi_host_put(base_vha->host);
3695
fe1b806f 3696 qla2x00_unmap_iobases(ha);
73208dfd 3697
e315cd28
AC		 3698 pci_release_selected_regions(ha->pdev, ha->bars);
3699 kfree(ha);
1da177e4 3700
90a86fc0
JC		 3701 pci_disable_pcie_error_reporting(pdev);
3702
665db93b 3703 pci_disable_device(pdev);
1da177e4 3704}
1da177e4
LT		 3705
3706static void
e315cd28 3707qla2x00_free_device(scsi_qla_host_t *vha)
1da177e4 3708{
e315cd28 3709 struct qla_hw_data *ha = vha->hw;
1da177e4 3710
85880801
AV		 3711 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
3712
3713 /* Disable timer */
3714 if (vha->timer_active)
3715 qla2x00_stop_timer(vha);
3716
2afa19a9 3717 qla25xx_delete_queues(vha);
fe1b806f 3718
df613b96 3719 if (ha->flags.fce_enabled)
e315cd28 3720 qla2x00_disable_fce_trace(vha, NULL, NULL);
df613b96 3721
a7a167bf 3722 if (ha->eft)
e315cd28 3723 qla2x00_disable_eft_trace(vha);
a7a167bf 3724
3407fc37
QT		 3725 if (IS_QLA25XX(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha)) {
3726 if (ha->flags.fw_started)
3727 qla2x00_abort_isp_cleanup(vha);
3728 } else {
3729 if (ha->flags.fw_started) {
3730 /* Stop currently executing firmware. */
3731 qla2x00_try_to_stop_firmware(vha);
3732 ha->flags.fw_started = 0;
3733 }
3734 }
1da177e4 3735
85880801
AV		 3736 vha->flags.online = 0;
3737
f6ef3b18 3738 /* turn-off interrupts on the card */
a9083016
GM		 3739 if (ha->interrupts_on) {
3740 vha->flags.init_done = 0;
fd34f556 3741 ha->isp_ops->disable_intrs(ha);
a9083016 3742 }
f6ef3b18 3743
093df737
QT		 3744 qla2x00_free_fcports(vha);
3745
e315cd28 3746 qla2x00_free_irqs(vha);
1da177e4 3747
093df737
QT		 3748 /* Flush the work queue and remove it */
3749 if (ha->wq) {
3750 flush_workqueue(ha->wq);
3751 destroy_workqueue(ha->wq);
3752 ha->wq = NULL;
3753 }
3754
8867048b 3755
e315cd28 3756 qla2x00_mem_free(ha);
73208dfd 3757
08de2844
GM		 3758 qla82xx_md_free(vha);
3759
73208dfd 3760 qla2x00_free_queues(ha);
1da177e4
LT		 3761}
3762
8867048b
CD		 3763void qla2x00_free_fcports(struct scsi_qla_host *vha)
3764{
3765 fc_port_t *fcport, *tfcport;
3766
3767 list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list) {
3768 list_del(&fcport->list);
5f16b331 3769 qla2x00_clear_loop_id(fcport);
8867048b 3770 kfree(fcport);
8867048b
CD		 3771 }
3772}
3773
d97994dc 3774static inline void
e315cd28 3775qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport,
d97994dc 3776 int defer)
3777{
d97994dc 3778 struct fc_rport *rport;
67becc00 3779 scsi_qla_host_t *base_vha;
044d78e1 3780 unsigned long flags;
d97994dc 3781
3782 if (!fcport->rport)
3783 return;
3784
3785 rport = fcport->rport;
3786 if (defer) {
67becc00 3787 base_vha = pci_get_drvdata(vha->hw->pdev);
044d78e1 3788 spin_lock_irqsave(vha->host->host_lock, flags);
d97994dc 3789 fcport->drport = rport;
044d78e1 3790 spin_unlock_irqrestore(vha->host->host_lock, flags);
df673274 3791 qlt_do_generation_tick(vha, &base_vha->total_fcport_update_gen);
67becc00
AV		 3792 set_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags);
3793 qla2xxx_wake_dpc(base_vha);
2d70c103 3794 } else {
df673274 3795 int now;
726b8548 3796 if (rport) {
83548fe2
QT		 3797 ql_dbg(ql_dbg_disc, fcport->vha, 0x2109,
3798 "%s %8phN. rport %p roles %x\n",
3799 __func__, fcport->port_name, rport,
3800 rport->roles);
d20ed91b 3801 fc_remote_port_delete(rport);
726b8548 3802 }
df673274 3803 qlt_do_generation_tick(vha, &now);
2d70c103 3804 }
d97994dc 3805}
3806
1da177e4
LT		 3807/*
3808 * qla2x00_mark_device_lost Updates fcport state when device goes offline.
3809 *
3810 * Input: ha = adapter block pointer. fcport = port structure pointer.
3811 *
3812 * Return: None.
3813 *
3814 * Context:
3815 */
e315cd28 3816void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport,
d97994dc 3817 int do_login, int defer)
1da177e4 3818{
8ae6d9c7
GM		 3819 if (IS_QLAFX00(vha->hw)) {
3820 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
3821 qla2x00_schedule_rport_del(vha, fcport, defer);
3822 return;
3823 }
3824
2c3dfe3f 3825 if (atomic_read(&fcport->state) == FCS_ONLINE &&
c6d39e23 3826 vha->vp_idx == fcport->vha->vp_idx) {
ec426e10 3827 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
e315cd28
AC		 3828 qla2x00_schedule_rport_del(vha, fcport, defer);
3829 }
fa2a1ce5 3830 /*
1da177e4
LT		 3831 * We may need to retry the login, so don't change the state of the
3832 * port but do the retries.
3833 */
3834 if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD)
ec426e10 3835 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
1da177e4
LT		 3836
3837 if (!do_login)
3838 return;
3839
a1d0285e 3840 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
1da177e4
LT		 3841}
3842
3843/*
3844 * qla2x00_mark_all_devices_lost
3845 * Updates fcport state when device goes offline.
3846 *
3847 * Input:
3848 * ha = adapter block pointer.
3849 * fcport = port structure pointer.
3850 *
3851 * Return:
3852 * None.
3853 *
3854 * Context:
3855 */
3856void
e315cd28 3857qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha, int defer)
1da177e4
LT		 3858{
3859 fc_port_t *fcport;
3860
83548fe2
QT		 3861 ql_dbg(ql_dbg_disc, vha, 0x20f1,
3862 "Mark all dev lost\n");
726b8548 3863
e315cd28 3864 list_for_each_entry(fcport, &vha->vp_fcports, list) {
726b8548 3865 fcport->scan_state = 0;
d8630bb9 3866 qlt_schedule_sess_for_deletion(fcport);
726b8548 3867
c6d39e23 3868 if (vha->vp_idx != 0 && vha->vp_idx != fcport->vha->vp_idx)
1da177e4 3869 continue;
0d6e61bc 3870
1da177e4
LT		 3871 /*
3872 * No point in marking the device as lost, if the device is
3873 * already DEAD.
3874 */
3875 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD)
3876 continue;
e315cd28 3877 if (atomic_read(&fcport->state) == FCS_ONLINE) {
ec426e10 3878 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
0d6e61bc
AV		 3879 if (defer)
3880 qla2x00_schedule_rport_del(vha, fcport, defer);
c6d39e23 3881 else if (vha->vp_idx == fcport->vha->vp_idx)
0d6e61bc
AV		 3882 qla2x00_schedule_rport_del(vha, fcport, defer);
3883 }
1da177e4
LT		 3884 }
3885}
3886
3887/*
3888* qla2x00_mem_alloc
3889* Allocates adapter memory.
3890*
3891* Returns:
3892* 0 = success.
e8711085 3893* !0 = failure.
1da177e4 3894*/
e8711085 3895static int
73208dfd
AC		 3896qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len,
3897 struct req_que **req, struct rsp_que **rsp)
1da177e4
LT		 3898{
3899 char name[16];
1da177e4 3900
e8711085 3901 ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size,
e315cd28 3902 &ha->init_cb_dma, GFP_KERNEL);
e8711085 3903 if (!ha->init_cb)
e315cd28 3904 goto fail;
e8711085 3905
2d70c103
NB		 3906 if (qlt_mem_alloc(ha) < 0)
3907 goto fail_free_init_cb;
3908
642ef983
CD		 3909 ha->gid_list = dma_alloc_coherent(&ha->pdev->dev,
3910 qla2x00_gid_list_size(ha), &ha->gid_list_dma, GFP_KERNEL);
e315cd28 3911 if (!ha->gid_list)
2d70c103 3912 goto fail_free_tgt_mem;
1da177e4 3913
e8711085
AV		 3914 ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep);
3915 if (!ha->srb_mempool)
e315cd28 3916 goto fail_free_gid_list;
e8711085 3917
7ec0effd 3918 if (IS_P3P_TYPE(ha)) {
a9083016
GM		 3919 /* Allocate cache for CT6 Ctx. */
3920 if (!ctx_cachep) {
3921 ctx_cachep = kmem_cache_create("qla2xxx_ctx",
3922 sizeof(struct ct6_dsd), 0,
3923 SLAB_HWCACHE_ALIGN, NULL);
3924 if (!ctx_cachep)
fc1ffd6c 3925 goto fail_free_srb_mempool;
a9083016
GM		 3926 }
3927 ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ,
3928 ctx_cachep);
3929 if (!ha->ctx_mempool)
3930 goto fail_free_srb_mempool;
7c3df132
SK		 3931 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021,
3932 "ctx_cachep=%p ctx_mempool=%p.\n",
3933 ctx_cachep, ha->ctx_mempool);
a9083016
GM		 3934 }
3935
e8711085
AV		 3936 /* Get memory for cached NVRAM */
3937 ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL);
3938 if (!ha->nvram)
a9083016 3939 goto fail_free_ctx_mempool;
e8711085 3940
e315cd28
AC		 3941 snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME,
3942 ha->pdev->device);
3943 ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3944 DMA_POOL_SIZE, 8, 0);
3945 if (!ha->s_dma_pool)
3946 goto fail_free_nvram;
3947
7c3df132
SK		 3948 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022,
3949 "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n",
3950 ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool);
3951
7ec0effd 3952 if (IS_P3P_TYPE(ha) || ql2xenabledif) {
a9083016
GM		 3953 ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3954 DSD_LIST_DMA_POOL_SIZE, 8, 0);
3955 if (!ha->dl_dma_pool) {
7c3df132
SK		 3956 ql_log_pci(ql_log_fatal, ha->pdev, 0x0023,
3957 "Failed to allocate memory for dl_dma_pool.\n");
a9083016
GM		 3958 goto fail_s_dma_pool;
3959 }
3960
3961 ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3962 FCP_CMND_DMA_POOL_SIZE, 8, 0);
3963 if (!ha->fcp_cmnd_dma_pool) {
7c3df132
SK		 3964 ql_log_pci(ql_log_fatal, ha->pdev, 0x0024,
3965 "Failed to allocate memory for fcp_cmnd_dma_pool.\n");
a9083016
GM		 3966 goto fail_dl_dma_pool;
3967 }
7c3df132
SK		 3968 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025,
3969 "dl_dma_pool=%p fcp_cmnd_dma_pool=%p.\n",
3970 ha->dl_dma_pool, ha->fcp_cmnd_dma_pool);
a9083016
GM		 3971 }
3972
e8711085
AV		 3973 /* Allocate memory for SNS commands */
3974 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
e315cd28 3975 /* Get consistent memory allocated for SNS commands */
e8711085 3976 ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev,
e315cd28 3977 sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL);
e8711085 3978 if (!ha->sns_cmd)
e315cd28 3979 goto fail_dma_pool;
7c3df132 3980 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026,
d8424f68 3981 "sns_cmd: %p.\n", ha->sns_cmd);
e8711085 3982 } else {
e315cd28 3983 /* Get consistent memory allocated for MS IOCB */
e8711085 3984 ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
e315cd28 3985 &ha->ms_iocb_dma);
e8711085 3986 if (!ha->ms_iocb)
e315cd28
AC		 3987 goto fail_dma_pool;
3988 /* Get consistent memory allocated for CT SNS commands */
e8711085 3989 ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev,
e315cd28 3990 sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL);
e8711085
AV		 3991 if (!ha->ct_sns)
3992 goto fail_free_ms_iocb;
7c3df132
SK		 3993 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027,
3994 "ms_iocb=%p ct_sns=%p.\n",
3995 ha->ms_iocb, ha->ct_sns);
1da177e4
LT		 3996 }
3997
e315cd28 3998 /* Allocate memory for request ring */
73208dfd
AC		 3999 *req = kzalloc(sizeof(struct req_que), GFP_KERNEL);
4000 if (!*req) {
7c3df132
SK		 4001 ql_log_pci(ql_log_fatal, ha->pdev, 0x0028,
4002 "Failed to allocate memory for req.\n");
e315cd28
AC		 4003 goto fail_req;
4004 }
73208dfd
AC		 4005 (*req)->length = req_len;
4006 (*req)->ring = dma_alloc_coherent(&ha->pdev->dev,
4007 ((*req)->length + 1) * sizeof(request_t),
4008 &(*req)->dma, GFP_KERNEL);
4009 if (!(*req)->ring) {
7c3df132
SK		 4010 ql_log_pci(ql_log_fatal, ha->pdev, 0x0029,
4011 "Failed to allocate memory for req_ring.\n");
e315cd28
AC		 4012 goto fail_req_ring;
4013 }
4014 /* Allocate memory for response ring */
73208dfd
AC		 4015 *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL);
4016 if (!*rsp) {
7c3df132
SK		 4017 ql_log_pci(ql_log_fatal, ha->pdev, 0x002a,
4018 "Failed to allocate memory for rsp.\n");
e315cd28
AC		 4019 goto fail_rsp;
4020 }
73208dfd
AC		 4021 (*rsp)->hw = ha;
4022 (*rsp)->length = rsp_len;
4023 (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev,
4024 ((*rsp)->length + 1) * sizeof(response_t),
4025 &(*rsp)->dma, GFP_KERNEL);
4026 if (!(*rsp)->ring) {
7c3df132
SK		 4027 ql_log_pci(ql_log_fatal, ha->pdev, 0x002b,
4028 "Failed to allocate memory for rsp_ring.\n");
e315cd28
AC		 4029 goto fail_rsp_ring;
4030 }
73208dfd
AC		 4031 (*req)->rsp = *rsp;
4032 (*rsp)->req = *req;
7c3df132
SK		 4033 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c,
4034 "req=%p req->length=%d req->ring=%p rsp=%p "
4035 "rsp->length=%d rsp->ring=%p.\n",
4036 *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length,
4037 (*rsp)->ring);
73208dfd
AC		 4038 /* Allocate memory for NVRAM data for vports */
4039 if (ha->nvram_npiv_size) {
6396bb22
KC		 4040 ha->npiv_info = kcalloc(ha->nvram_npiv_size,
4041 sizeof(struct qla_npiv_entry),
4042 GFP_KERNEL);
73208dfd 4043 if (!ha->npiv_info) {
7c3df132
SK		 4044 ql_log_pci(ql_log_fatal, ha->pdev, 0x002d,
4045 "Failed to allocate memory for npiv_info.\n");
73208dfd
AC		 4046 goto fail_npiv_info;
4047 }
4048 } else
4049 ha->npiv_info = NULL;
e8711085 4050
b64b0e8f 4051 /* Get consistent memory allocated for EX-INIT-CB. */
f73cb695 4052 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha)) {
b64b0e8f
AV		 4053 ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
4054 &ha->ex_init_cb_dma);
4055 if (!ha->ex_init_cb)
4056 goto fail_ex_init_cb;
7c3df132
SK		 4057 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e,
4058 "ex_init_cb=%p.\n", ha->ex_init_cb);
b64b0e8f
AV		 4059 }
4060
a9083016
GM		 4061 INIT_LIST_HEAD(&ha->gbl_dsd_list);
4062
5ff1d584
AV		 4063 /* Get consistent memory allocated for Async Port-Database. */
4064 if (!IS_FWI2_CAPABLE(ha)) {
4065 ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
4066 &ha->async_pd_dma);
4067 if (!ha->async_pd)
4068 goto fail_async_pd;
7c3df132
SK		 4069 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f,
4070 "async_pd=%p.\n", ha->async_pd);
5ff1d584
AV		 4071 }
4072
e315cd28 4073 INIT_LIST_HEAD(&ha->vp_list);
5f16b331
CD		 4074
4075 /* Allocate memory for our loop_id bitmap */
6396bb22
KC		 4076 ha->loop_id_map = kcalloc(BITS_TO_LONGS(LOOPID_MAP_SIZE),
4077 sizeof(long),
4078 GFP_KERNEL);
5f16b331 4079 if (!ha->loop_id_map)
fc1ffd6c 4080 goto fail_loop_id_map;
5f16b331
CD		 4081 else {
4082 qla2x00_set_reserved_loop_ids(ha);
4083 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0123,
b2a72ec3 4084 "loop_id_map=%p.\n", ha->loop_id_map);
5f16b331
CD		 4085 }
4086
e4e3a2ce
QT		 4087 ha->sfp_data = dma_alloc_coherent(&ha->pdev->dev,
4088 SFP_DEV_SIZE, &ha->sfp_data_dma, GFP_KERNEL);
4089 if (!ha->sfp_data) {
4090 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b,
4091 "Unable to allocate memory for SFP read-data.\n");
4092 goto fail_sfp_data;
4093 }
4094
b2a72ec3 4095 return 0;
e315cd28 4096
e4e3a2ce
QT		 4097fail_sfp_data:
4098 kfree(ha->loop_id_map);
fc1ffd6c
QT		 4099fail_loop_id_map:
4100 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
5ff1d584
AV		 4101fail_async_pd:
4102 dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma);
b64b0e8f
AV		 4103fail_ex_init_cb:
4104 kfree(ha->npiv_info);
73208dfd
AC		 4105fail_npiv_info:
4106 dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) *
4107 sizeof(response_t), (*rsp)->ring, (*rsp)->dma);
4108 (*rsp)->ring = NULL;
4109 (*rsp)->dma = 0;
e315cd28 4110fail_rsp_ring:
73208dfd 4111 kfree(*rsp);
6d634067 4112 *rsp = NULL;
e315cd28 4113fail_rsp:
73208dfd
AC		 4114 dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) *
4115 sizeof(request_t), (*req)->ring, (*req)->dma);
4116 (*req)->ring = NULL;
4117 (*req)->dma = 0;
e315cd28 4118fail_req_ring:
73208dfd 4119 kfree(*req);
6d634067 4120 *req = NULL;
e315cd28
AC		 4121fail_req:
4122 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
4123 ha->ct_sns, ha->ct_sns_dma);
4124 ha->ct_sns = NULL;
4125 ha->ct_sns_dma = 0;
e8711085
AV		 4126fail_free_ms_iocb:
4127 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
4128 ha->ms_iocb = NULL;
4129 ha->ms_iocb_dma = 0;
fc1ffd6c
QT		 4130
4131 if (ha->sns_cmd)
4132 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
4133 ha->sns_cmd, ha->sns_cmd_dma);
e315cd28 4134fail_dma_pool:
bad75002 4135 if (IS_QLA82XX(ha) || ql2xenabledif) {
a9083016
GM		 4136 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
4137 ha->fcp_cmnd_dma_pool = NULL;
4138 }
4139fail_dl_dma_pool:
bad75002 4140 if (IS_QLA82XX(ha) || ql2xenabledif) {
a9083016
GM		 4141 dma_pool_destroy(ha->dl_dma_pool);
4142 ha->dl_dma_pool = NULL;
4143 }
4144fail_s_dma_pool:
e315cd28
AC		 4145 dma_pool_destroy(ha->s_dma_pool);
4146 ha->s_dma_pool = NULL;
e8711085
AV		 4147fail_free_nvram:
4148 kfree(ha->nvram);
4149 ha->nvram = NULL;
a9083016 4150fail_free_ctx_mempool:
fc1ffd6c
QT		 4151 if (ha->ctx_mempool)
4152 mempool_destroy(ha->ctx_mempool);
a9083016 4153 ha->ctx_mempool = NULL;
e8711085 4154fail_free_srb_mempool:
fc1ffd6c
QT		 4155 if (ha->srb_mempool)
4156 mempool_destroy(ha->srb_mempool);
e8711085 4157 ha->srb_mempool = NULL;
e8711085 4158fail_free_gid_list:
642ef983
CD		 4159 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
4160 ha->gid_list,
e315cd28 4161 ha->gid_list_dma);
e8711085
AV		 4162 ha->gid_list = NULL;
4163 ha->gid_list_dma = 0;
2d70c103
NB		 4164fail_free_tgt_mem:
4165 qlt_mem_free(ha);
e315cd28
AC		 4166fail_free_init_cb:
4167 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb,
4168 ha->init_cb_dma);
4169 ha->init_cb = NULL;
4170 ha->init_cb_dma = 0;
e8711085 4171fail:
7c3df132
SK		 4172 ql_log(ql_log_fatal, NULL, 0x0030,
4173 "Memory allocation failure.\n");
e8711085 4174 return -ENOMEM;
1da177e4
LT		 4175}
4176
b0d6cabd
HM		 4177int
4178qla2x00_set_exlogins_buffer(scsi_qla_host_t *vha)
4179{
4180 int rval;
4181 uint16_t size, max_cnt, temp;
4182 struct qla_hw_data *ha = vha->hw;
4183
4184 /* Return if we don't need to alloacate any extended logins */
4185 if (!ql2xexlogins)
4186 return QLA_SUCCESS;
4187
99e1b683
QT		 4188 if (!IS_EXLOGIN_OFFLD_CAPABLE(ha))
4189 return QLA_SUCCESS;
4190
b0d6cabd
HM		 4191 ql_log(ql_log_info, vha, 0xd021, "EXLOGIN count: %d.\n", ql2xexlogins);
4192 max_cnt = 0;
4193 rval = qla_get_exlogin_status(vha, &size, &max_cnt);
4194 if (rval != QLA_SUCCESS) {
4195 ql_log_pci(ql_log_fatal, ha->pdev, 0xd029,
4196 "Failed to get exlogin status.\n");
4197 return rval;
4198 }
4199
4200 temp = (ql2xexlogins > max_cnt) ? max_cnt : ql2xexlogins;
99e1b683
QT		 4201 temp *= size;
4202
4203 if (temp != ha->exlogin_size) {
4204 qla2x00_free_exlogin_buffer(ha);
4205 ha->exlogin_size = temp;
4206
4207 ql_log(ql_log_info, vha, 0xd024,
4208 "EXLOGIN: max_logins=%d, portdb=0x%x, total=%d.\n",
4209 max_cnt, size, temp);
4210
4211 ql_log(ql_log_info, vha, 0xd025,
4212 "EXLOGIN: requested size=0x%x\n", ha->exlogin_size);
4213
4214 /* Get consistent memory for extended logins */
4215 ha->exlogin_buf = dma_alloc_coherent(&ha->pdev->dev,
4216 ha->exlogin_size, &ha->exlogin_buf_dma, GFP_KERNEL);
4217 if (!ha->exlogin_buf) {
4218 ql_log_pci(ql_log_fatal, ha->pdev, 0xd02a,
b0d6cabd 4219 "Failed to allocate memory for exlogin_buf_dma.\n");
99e1b683
QT		 4220 return -ENOMEM;
4221 }
b0d6cabd
HM		 4222 }
4223
4224 /* Now configure the dma buffer */
4225 rval = qla_set_exlogin_mem_cfg(vha, ha->exlogin_buf_dma);
4226 if (rval) {
83548fe2 4227 ql_log(ql_log_fatal, vha, 0xd033,
b0d6cabd
HM		 4228 "Setup extended login buffer ****FAILED****.\n");
4229 qla2x00_free_exlogin_buffer(ha);
4230 }
4231
4232 return rval;
4233}
4234
4235/*
4236* qla2x00_free_exlogin_buffer
4237*
4238* Input:
4239* ha = adapter block pointer
4240*/
4241void
4242qla2x00_free_exlogin_buffer(struct qla_hw_data *ha)
4243{
4244 if (ha->exlogin_buf) {
4245 dma_free_coherent(&ha->pdev->dev, ha->exlogin_size,
4246 ha->exlogin_buf, ha->exlogin_buf_dma);
4247 ha->exlogin_buf = NULL;
4248 ha->exlogin_size = 0;
4249 }
4250}
4251
99e1b683
QT		 4252static void
4253qla2x00_number_of_exch(scsi_qla_host_t *vha, u32 *ret_cnt, u16 max_cnt)
4254{
4255 u32 temp;
4256 *ret_cnt = FW_DEF_EXCHANGES_CNT;
4257
d1e3635a
QT		 4258 if (max_cnt > vha->hw->max_exchg)
4259 max_cnt = vha->hw->max_exchg;
4260
99e1b683
QT		 4261 if (qla_ini_mode_enabled(vha)) {
4262 if (ql2xiniexchg > max_cnt)
4263 ql2xiniexchg = max_cnt;
4264
4265 if (ql2xiniexchg > FW_DEF_EXCHANGES_CNT)
4266 *ret_cnt = ql2xiniexchg;
4267 } else if (qla_tgt_mode_enabled(vha)) {
4268 if (ql2xexchoffld > max_cnt)
4269 ql2xexchoffld = max_cnt;
4270
4271 if (ql2xexchoffld > FW_DEF_EXCHANGES_CNT)
4272 *ret_cnt = ql2xexchoffld;
4273 } else if (qla_dual_mode_enabled(vha)) {
4274 temp = ql2xiniexchg + ql2xexchoffld;
4275 if (temp > max_cnt) {
4276 ql2xiniexchg -= (temp - max_cnt)/2;
4277 ql2xexchoffld -= (((temp - max_cnt)/2) + 1);
4278 temp = max_cnt;
4279 }
4280
4281 if (temp > FW_DEF_EXCHANGES_CNT)
4282 *ret_cnt = temp;
4283 }
4284}
4285
2f56a7f1
HM		 4286int
4287qla2x00_set_exchoffld_buffer(scsi_qla_host_t *vha)
4288{
4289 int rval;
d1e3635a
QT		 4290 u16 size, max_cnt;
4291 u32 actual_cnt, totsz;
2f56a7f1
HM		 4292 struct qla_hw_data *ha = vha->hw;
4293
99e1b683
QT		 4294 if (!ha->flags.exchoffld_enabled)
4295 return QLA_SUCCESS;
4296
4297 if (!IS_EXCHG_OFFLD_CAPABLE(ha))
2f56a7f1
HM		 4298 return QLA_SUCCESS;
4299
2f56a7f1
HM		 4300 max_cnt = 0;
4301 rval = qla_get_exchoffld_status(vha, &size, &max_cnt);
4302 if (rval != QLA_SUCCESS) {
4303 ql_log_pci(ql_log_fatal, ha->pdev, 0xd012,
4304 "Failed to get exlogin status.\n");
4305 return rval;
4306 }
4307
d1e3635a
QT		 4308 qla2x00_number_of_exch(vha, &actual_cnt, max_cnt);
4309 ql_log(ql_log_info, vha, 0xd014,
4310 "Actual exchange offload count: %d.\n", actual_cnt);
4311
4312 totsz = actual_cnt * size;
2f56a7f1 4313
d1e3635a 4314 if (totsz != ha->exchoffld_size) {
99e1b683 4315 qla2x00_free_exchoffld_buffer(ha);
d1e3635a 4316 ha->exchoffld_size = totsz;
99e1b683
QT		 4317
4318 ql_log(ql_log_info, vha, 0xd016,
d1e3635a
QT		 4319 "Exchange offload: max_count=%d, actual count=%d entry sz=0x%x, total sz=0x%x\n",
4320 max_cnt, actual_cnt, size, totsz);
99e1b683
QT		 4321
4322 ql_log(ql_log_info, vha, 0xd017,
4323 "Exchange Buffers requested size = 0x%x\n",
4324 ha->exchoffld_size);
4325
4326 /* Get consistent memory for extended logins */
4327 ha->exchoffld_buf = dma_alloc_coherent(&ha->pdev->dev,
4328 ha->exchoffld_size, &ha->exchoffld_buf_dma, GFP_KERNEL);
4329 if (!ha->exchoffld_buf) {
4330 ql_log_pci(ql_log_fatal, ha->pdev, 0xd013,
d1e3635a
QT		 4331 "Failed to allocate memory for Exchange Offload.\n");
4332
4333 if (ha->max_exchg >
4334 (FW_DEF_EXCHANGES_CNT + REDUCE_EXCHANGES_CNT)) {
4335 ha->max_exchg -= REDUCE_EXCHANGES_CNT;
4336 } else if (ha->max_exchg >
4337 (FW_DEF_EXCHANGES_CNT + 512)) {
4338 ha->max_exchg -= 512;
4339 } else {
4340 ha->flags.exchoffld_enabled = 0;
4341 ql_log_pci(ql_log_fatal, ha->pdev, 0xd013,
4342 "Disabling Exchange offload due to lack of memory\n");
4343 }
4344 ha->exchoffld_size = 0;
4345
99e1b683
QT		 4346 return -ENOMEM;
4347 }
2f56a7f1
HM		 4348 }
4349
4350 /* Now configure the dma buffer */
99e1b683 4351 rval = qla_set_exchoffld_mem_cfg(vha);
2f56a7f1
HM		 4352 if (rval) {
4353 ql_log(ql_log_fatal, vha, 0xd02e,
4354 "Setup exchange offload buffer ****FAILED****.\n");
4355 qla2x00_free_exchoffld_buffer(ha);
99e1b683
QT		 4356 } else {
4357 /* re-adjust number of target exchange */
4358 struct init_cb_81xx *icb = (struct init_cb_81xx *)ha->init_cb;
4359
4360 if (qla_ini_mode_enabled(vha))
4361 icb->exchange_count = 0;
4362 else
4363 icb->exchange_count = cpu_to_le16(ql2xexchoffld);
2f56a7f1
HM		 4364 }
4365
4366 return rval;
4367}
4368
4369/*
4370* qla2x00_free_exchoffld_buffer
4371*
4372* Input:
4373* ha = adapter block pointer
4374*/
4375void
4376qla2x00_free_exchoffld_buffer(struct qla_hw_data *ha)
4377{
4378 if (ha->exchoffld_buf) {
4379 dma_free_coherent(&ha->pdev->dev, ha->exchoffld_size,
4380 ha->exchoffld_buf, ha->exchoffld_buf_dma);
4381 ha->exchoffld_buf = NULL;
4382 ha->exchoffld_size = 0;
4383 }
4384}
4385
1da177e4 4386/*
e30d1756
MI		 4387* qla2x00_free_fw_dump
4388* Frees fw dump stuff.
1da177e4
LT		 4389*
4390* Input:
7ec0effd 4391* ha = adapter block pointer
1da177e4 4392*/
a824ebb3 4393static void
e30d1756 4394qla2x00_free_fw_dump(struct qla_hw_data *ha)
1da177e4 4395{
df613b96 4396 if (ha->fce)
f73cb695
CD		 4397 dma_free_coherent(&ha->pdev->dev,
4398 FCE_SIZE, ha->fce, ha->fce_dma);
df613b96 4399
f73cb695
CD		 4400 if (ha->eft)
4401 dma_free_coherent(&ha->pdev->dev,
4402 EFT_SIZE, ha->eft, ha->eft_dma);
4403
4404 if (ha->fw_dump)
a7a167bf 4405 vfree(ha->fw_dump);
f73cb695
CD		 4406 if (ha->fw_dump_template)
4407 vfree(ha->fw_dump_template);
4408
e30d1756
MI		 4409 ha->fce = NULL;
4410 ha->fce_dma = 0;
4411 ha->eft = NULL;
4412 ha->eft_dma = 0;
e30d1756 4413 ha->fw_dumped = 0;
61f098dd 4414 ha->fw_dump_cap_flags = 0;
e30d1756 4415 ha->fw_dump_reading = 0;
f73cb695
CD		 4416 ha->fw_dump = NULL;
4417 ha->fw_dump_len = 0;
4418 ha->fw_dump_template = NULL;
4419 ha->fw_dump_template_len = 0;
e30d1756
MI		 4420}
4421
4422/*
4423* qla2x00_mem_free
4424* Frees all adapter allocated memory.
4425*
4426* Input:
4427* ha = adapter block pointer.
4428*/
4429static void
4430qla2x00_mem_free(struct qla_hw_data *ha)
4431{
4432 qla2x00_free_fw_dump(ha);
4433
81178772
SK		 4434 if (ha->mctp_dump)
4435 dma_free_coherent(&ha->pdev->dev, MCTP_DUMP_SIZE, ha->mctp_dump,
4436 ha->mctp_dump_dma);
4437
e30d1756
MI		 4438 if (ha->srb_mempool)
4439 mempool_destroy(ha->srb_mempool);
a7a167bf 4440
11bbc1d8
AV		 4441 if (ha->dcbx_tlv)
4442 dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE,
4443 ha->dcbx_tlv, ha->dcbx_tlv_dma);
4444
ce0423f4
AV		 4445 if (ha->xgmac_data)
4446 dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE,
4447 ha->xgmac_data, ha->xgmac_data_dma);
4448
1da177e4
LT		 4449 if (ha->sns_cmd)
4450 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
e315cd28 4451 ha->sns_cmd, ha->sns_cmd_dma);
1da177e4
LT		 4452
4453 if (ha->ct_sns)
4454 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
e315cd28 4455 ha->ct_sns, ha->ct_sns_dma);
1da177e4 4456
88729e53 4457 if (ha->sfp_data)
e4e3a2ce
QT		 4458 dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE, ha->sfp_data,
4459 ha->sfp_data_dma);
88729e53 4460
1da177e4
LT		 4461 if (ha->ms_iocb)
4462 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
4463
b64b0e8f 4464 if (ha->ex_init_cb)
a9083016
GM		 4465 dma_pool_free(ha->s_dma_pool,
4466 ha->ex_init_cb, ha->ex_init_cb_dma);
b64b0e8f 4467
5ff1d584
AV		 4468 if (ha->async_pd)
4469 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
4470
1da177e4
LT		 4471 if (ha->s_dma_pool)
4472 dma_pool_destroy(ha->s_dma_pool);
4473
1da177e4 4474 if (ha->gid_list)
642ef983
CD		 4475 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
4476 ha->gid_list, ha->gid_list_dma);
1da177e4 4477
a9083016
GM		 4478 if (IS_QLA82XX(ha)) {
4479 if (!list_empty(&ha->gbl_dsd_list)) {
4480 struct dsd_dma *dsd_ptr, *tdsd_ptr;
4481
4482 /* clean up allocated prev pool */
4483 list_for_each_entry_safe(dsd_ptr,
4484 tdsd_ptr, &ha->gbl_dsd_list, list) {
4485 dma_pool_free(ha->dl_dma_pool,
4486 dsd_ptr->dsd_addr, dsd_ptr->dsd_list_dma);
4487 list_del(&dsd_ptr->list);
4488 kfree(dsd_ptr);
4489 }
4490 }
4491 }
4492
4493 if (ha->dl_dma_pool)
4494 dma_pool_destroy(ha->dl_dma_pool);
4495
4496 if (ha->fcp_cmnd_dma_pool)
4497 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
4498
4499 if (ha->ctx_mempool)
4500 mempool_destroy(ha->ctx_mempool);
4501
2d70c103
NB		 4502 qlt_mem_free(ha);
4503
e315cd28
AC		 4504 if (ha->init_cb)
4505 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size,
a9083016 4506 ha->init_cb, ha->init_cb_dma);
6a2cf8d3 4507
6d634067
BK		 4508 vfree(ha->optrom_buffer);
4509 kfree(ha->nvram);
4510 kfree(ha->npiv_info);
4511 kfree(ha->swl);
4512 kfree(ha->loop_id_map);
1da177e4 4513
e8711085 4514 ha->srb_mempool = NULL;
a9083016 4515 ha->ctx_mempool = NULL;
1da177e4
LT		 4516 ha->sns_cmd = NULL;
4517 ha->sns_cmd_dma = 0;
4518 ha->ct_sns = NULL;
4519 ha->ct_sns_dma = 0;
4520 ha->ms_iocb = NULL;
4521 ha->ms_iocb_dma = 0;
1da177e4
LT		 4522 ha->init_cb = NULL;
4523 ha->init_cb_dma = 0;
b64b0e8f
AV		 4524 ha->ex_init_cb = NULL;
4525 ha->ex_init_cb_dma = 0;
5ff1d584
AV		 4526 ha->async_pd = NULL;
4527 ha->async_pd_dma = 0;
6a2cf8d3
BK		 4528 ha->loop_id_map = NULL;
4529 ha->npiv_info = NULL;
4530 ha->optrom_buffer = NULL;
4531 ha->swl = NULL;
4532 ha->nvram = NULL;
4533 ha->mctp_dump = NULL;
4534 ha->dcbx_tlv = NULL;
4535 ha->xgmac_data = NULL;
4536 ha->sfp_data = NULL;
1da177e4
LT		 4537
4538 ha->s_dma_pool = NULL;
a9083016
GM		 4539 ha->dl_dma_pool = NULL;
4540 ha->fcp_cmnd_dma_pool = NULL;
1da177e4 4541
1da177e4
LT		 4542 ha->gid_list = NULL;
4543 ha->gid_list_dma = 0;
2d70c103
NB		 4544
4545 ha->tgt.atio_ring = NULL;
4546 ha->tgt.atio_dma = 0;
4547 ha->tgt.tgt_vp_map = NULL;
e315cd28 4548}
1da177e4 4549
e315cd28
AC		 4550struct scsi_qla_host *qla2x00_create_host(struct scsi_host_template *sht,
4551 struct qla_hw_data *ha)
4552{
4553 struct Scsi_Host *host;
4554 struct scsi_qla_host *vha = NULL;
854165f4 4555
e315cd28 4556 host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t));
41dc529a 4557 if (!host) {
7c3df132
SK		 4558 ql_log_pci(ql_log_fatal, ha->pdev, 0x0107,
4559 "Failed to allocate host from the scsi layer, aborting.\n");
41dc529a 4560 return NULL;
e315cd28
AC		 4561 }
4562
4563 /* Clear our data area */
4564 vha = shost_priv(host);
4565 memset(vha, 0, sizeof(scsi_qla_host_t));
4566
4567 vha->host = host;
4568 vha->host_no = host->host_no;
4569 vha->hw = ha;
4570
4571 INIT_LIST_HEAD(&vha->vp_fcports);
4572 INIT_LIST_HEAD(&vha->work_list);
4573 INIT_LIST_HEAD(&vha->list);
8b2f5ff3
SN		 4574 INIT_LIST_HEAD(&vha->qla_cmd_list);
4575 INIT_LIST_HEAD(&vha->qla_sess_op_cmd_list);
71cdc079 4576 INIT_LIST_HEAD(&vha->logo_list);
b7bd104e 4577 INIT_LIST_HEAD(&vha->plogi_ack_list);
d7459527 4578 INIT_LIST_HEAD(&vha->qp_list);
41dc529a 4579 INIT_LIST_HEAD(&vha->gnl.fcports);
a5d42f4c 4580 INIT_LIST_HEAD(&vha->nvme_rport_list);
2d73ac61 4581 INIT_LIST_HEAD(&vha->gpnid_list);
9b3e0f4d 4582 INIT_WORK(&vha->iocb_work, qla2x00_iocb_work_fn);
e315cd28 4583
f999f4c1 4584 spin_lock_init(&vha->work_lock);
8b2f5ff3 4585 spin_lock_init(&vha->cmd_list_lock);
1c6cacf4 4586 spin_lock_init(&vha->gnl.fcports_lock);
726b8548 4587 init_waitqueue_head(&vha->fcport_waitQ);
c4a9b538 4588 init_waitqueue_head(&vha->vref_waitq);
f999f4c1 4589
2fdbc65e
BVA		 4590 vha->gnl.size = sizeof(struct get_name_list_extended) *
4591 (ha->max_loop_id + 1);
41dc529a
QT		 4592 vha->gnl.l = dma_alloc_coherent(&ha->pdev->dev,
4593 vha->gnl.size, &vha->gnl.ldma, GFP_KERNEL);
4594 if (!vha->gnl.l) {
83548fe2 4595 ql_log(ql_log_fatal, vha, 0xd04a,
41dc529a
QT		 4596 "Alloc failed for name list.\n");
4597 scsi_remove_host(vha->host);
4598 return NULL;
4599 }
f999f4c1 4600
a4239945
QT		 4601 /* todo: what about ext login? */
4602 vha->scan.size = ha->max_fibre_devices * sizeof(struct fab_scan_rp);
4603 vha->scan.l = vmalloc(vha->scan.size);
4604 if (!vha->scan.l) {
4605 ql_log(ql_log_fatal, vha, 0xd04a,
4606 "Alloc failed for scan database.\n");
4607 dma_free_coherent(&ha->pdev->dev, vha->gnl.size,
4608 vha->gnl.l, vha->gnl.ldma);
4609 scsi_remove_host(vha->host);
4610 return NULL;
4611 }
f352eeb7 4612 INIT_DELAYED_WORK(&vha->scan.scan_work, qla_scan_work_fn);
a4239945 4613
e315cd28 4614 sprintf(vha->host_str, "%s_%ld", QLA2XXX_DRIVER_NAME, vha->host_no);
7c3df132
SK		 4615 ql_dbg(ql_dbg_init, vha, 0x0041,
4616 "Allocated the host=%p hw=%p vha=%p dev_name=%s",
4617 vha->host, vha->hw, vha,
4618 dev_name(&(ha->pdev->dev)));
4619
e315cd28 4620 return vha;
1da177e4
LT		 4621}
4622
726b8548 4623struct qla_work_evt *
f999f4c1 4624qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type)
0971de7f
AV		 4625{
4626 struct qla_work_evt *e;
feafb7b1
AE		 4627 uint8_t bail;
4628
4629 QLA_VHA_MARK_BUSY(vha, bail);
4630 if (bail)
4631 return NULL;
0971de7f 4632
f999f4c1 4633 e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC);
feafb7b1
AE		 4634 if (!e) {
4635 QLA_VHA_MARK_NOT_BUSY(vha);
0971de7f 4636 return NULL;
feafb7b1 4637 }
0971de7f
AV		 4638
4639 INIT_LIST_HEAD(&e->list);
4640 e->type = type;
4641 e->flags = QLA_EVT_FLAG_FREE;
4642 return e;
4643}
4644
726b8548 4645int
f999f4c1 4646qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e)
0971de7f 4647{
f999f4c1 4648 unsigned long flags;
9b3e0f4d 4649 bool q = false;
0971de7f 4650
f999f4c1 4651 spin_lock_irqsave(&vha->work_lock, flags);
e315cd28 4652 list_add_tail(&e->list, &vha->work_list);
9b3e0f4d
QT		 4653
4654 if (!test_and_set_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags))
4655 q = true;
4656
f999f4c1 4657 spin_unlock_irqrestore(&vha->work_lock, flags);
ec7193e2 4658
9b3e0f4d
QT		 4659 if (q)
4660 queue_work(vha->hw->wq, &vha->iocb_work);
f999f4c1 4661
0971de7f
AV		 4662 return QLA_SUCCESS;
4663}
4664
4665int
e315cd28 4666qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code,
0971de7f
AV		 4667 u32 data)
4668{
4669 struct qla_work_evt *e;
4670
f999f4c1 4671 e = qla2x00_alloc_work(vha, QLA_EVT_AEN);
0971de7f
AV		 4672 if (!e)
4673 return QLA_FUNCTION_FAILED;
4674
4675 e->u.aen.code = code;
4676 e->u.aen.data = data;
f999f4c1 4677 return qla2x00_post_work(vha, e);
0971de7f
AV		 4678}
4679
8a659571
AV		 4680int
4681qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb)
4682{
4683 struct qla_work_evt *e;
4684
f999f4c1 4685 e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK);
8a659571
AV		 4686 if (!e)
4687 return QLA_FUNCTION_FAILED;
4688
4689 memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t));
f999f4c1 4690 return qla2x00_post_work(vha, e);
8a659571
AV		 4691}
4692
ac280b67
AV		 4693#define qla2x00_post_async_work(name, type) \
4694int qla2x00_post_async_##name##_work( \
4695 struct scsi_qla_host *vha, \
4696 fc_port_t *fcport, uint16_t *data) \
4697{ \
4698 struct qla_work_evt *e; \
4699 \
4700 e = qla2x00_alloc_work(vha, type); \
4701 if (!e) \
4702 return QLA_FUNCTION_FAILED; \
4703 \
4704 e->u.logio.fcport = fcport; \
4705 if (data) { \
4706 e->u.logio.data[0] = data[0]; \
4707 e->u.logio.data[1] = data[1]; \
4708 } \
6d674927 4709 fcport->flags |= FCF_ASYNC_ACTIVE; \
ac280b67
AV		 4710 return qla2x00_post_work(vha, e); \
4711}
4712
4713qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN);
ac280b67
AV		 4714qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT);
4715qla2x00_post_async_work(logout_done, QLA_EVT_ASYNC_LOGOUT_DONE);
5ff1d584
AV		 4716qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC);
4717qla2x00_post_async_work(adisc_done, QLA_EVT_ASYNC_ADISC_DONE);
11aea16a
QT		 4718qla2x00_post_async_work(prlo, QLA_EVT_ASYNC_PRLO);
4719qla2x00_post_async_work(prlo_done, QLA_EVT_ASYNC_PRLO_DONE);
ac280b67 4720
3420d36c
AV		 4721int
4722qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code)
4723{
4724 struct qla_work_evt *e;
4725
4726 e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT);
4727 if (!e)
4728 return QLA_FUNCTION_FAILED;
4729
4730 e->u.uevent.code = code;
4731 return qla2x00_post_work(vha, e);
4732}
4733
4734static void
4735qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code)
4736{
4737 char event_string[40];
4738 char *envp[] = { event_string, NULL };
4739
4740 switch (code) {
4741 case QLA_UEVENT_CODE_FW_DUMP:
4742 snprintf(event_string, sizeof(event_string), "FW_DUMP=%ld",
4743 vha->host_no);
4744 break;
4745 default:
4746 /* do nothing */
4747 break;
4748 }
4749 kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp);
4750}
4751
8ae6d9c7
GM		 4752int
4753qlafx00_post_aenfx_work(struct scsi_qla_host *vha, uint32_t evtcode,
4754 uint32_t *data, int cnt)
4755{
4756 struct qla_work_evt *e;
4757
4758 e = qla2x00_alloc_work(vha, QLA_EVT_AENFX);
4759 if (!e)
4760 return QLA_FUNCTION_FAILED;
4761
4762 e->u.aenfx.evtcode = evtcode;
4763 e->u.aenfx.count = cnt;
4764 memcpy(e->u.aenfx.mbx, data, sizeof(*data) * cnt);
4765 return qla2x00_post_work(vha, e);
4766}
4767
726b8548
QT		 4768int qla24xx_post_upd_fcport_work(struct scsi_qla_host *vha, fc_port_t *fcport)
4769{
4770 struct qla_work_evt *e;
4771
4772 e = qla2x00_alloc_work(vha, QLA_EVT_UPD_FCPORT);
4773 if (!e)
4774 return QLA_FUNCTION_FAILED;
4775
4776 e->u.fcport.fcport = fcport;
4777 return qla2x00_post_work(vha, e);
4778}
4779
4780static
4781void qla24xx_create_new_sess(struct scsi_qla_host *vha, struct qla_work_evt *e)
4782{
4783 unsigned long flags;
b5d15312 4784 fc_port_t *fcport = NULL, *tfcp;
726b8548
QT		 4785 struct qlt_plogi_ack_t *pla =
4786 (struct qlt_plogi_ack_t *)e->u.new_sess.pla;
b5d15312 4787 uint8_t free_fcport = 0;
a4239945 4788 u64 wwn;
726b8548 4789
9cd883f0
QT		 4790 ql_dbg(ql_dbg_disc, vha, 0xffff,
4791 "%s %d %8phC enter\n",
4792 __func__, __LINE__, e->u.new_sess.port_name);
4793
726b8548
QT		 4794 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
4795 fcport = qla2x00_find_fcport_by_wwpn(vha, e->u.new_sess.port_name, 1);
4796 if (fcport) {
4797 fcport->d_id = e->u.new_sess.id;
4798 if (pla) {
4799 fcport->fw_login_state = DSC_LS_PLOGI_PEND;
9b3e0f4d
QT		 4800 memcpy(fcport->node_name,
4801 pla->iocb.u.isp24.u.plogi.node_name,
4802 WWN_SIZE);
726b8548
QT		 4803 qlt_plogi_ack_link(vha, pla, fcport, QLT_PLOGI_LINK_SAME_WWN);
4804 /* we took an extra ref_count to prevent PLOGI ACK when
4805 * fcport/sess has not been created.
4806 */
4807 pla->ref_count--;
4808 }
4809 } else {
b5d15312 4810 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
726b8548
QT		 4811 fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
4812 if (fcport) {
4813 fcport->d_id = e->u.new_sess.id;
726b8548
QT		 4814 fcport->flags |= FCF_FABRIC_DEVICE;
4815 fcport->fw_login_state = DSC_LS_PLOGI_PEND;
33b28357 4816 if (e->u.new_sess.fc4_type & FS_FC4TYPE_FCP)
a4239945 4817 fcport->fc4_type = FC4_TYPE_FCP_SCSI;
726b8548 4818
33b28357 4819 if (e->u.new_sess.fc4_type & FS_FC4TYPE_NVME) {
2b5b9647
DT		 4820 fcport->fc4_type = FC4_TYPE_OTHER;
4821 fcport->fc4f_nvme = FC4_TYPE_NVME;
4822 }
33b28357 4823
726b8548
QT		 4824 memcpy(fcport->port_name, e->u.new_sess.port_name,
4825 WWN_SIZE);
b5d15312
QT		 4826 } else {
4827 ql_dbg(ql_dbg_disc, vha, 0xffff,
4828 "%s %8phC mem alloc fail.\n",
4829 __func__, e->u.new_sess.port_name);
4830
4831 if (pla)
4832 kmem_cache_free(qla_tgt_plogi_cachep, pla);
4833 return;
4834 }
4835
4836 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
a4239945 4837 /* search again to make sure no one else got ahead */
b5d15312
QT		 4838 tfcp = qla2x00_find_fcport_by_wwpn(vha,
4839 e->u.new_sess.port_name, 1);
4840 if (tfcp) {
4841 /* should rarily happen */
4842 ql_dbg(ql_dbg_disc, vha, 0xffff,
4843 "%s %8phC found existing fcport b4 add. DS %d LS %d\n",
4844 __func__, tfcp->port_name, tfcp->disc_state,
4845 tfcp->fw_login_state);
4846
4847 free_fcport = 1;
4848 } else {
726b8548
QT		 4849 list_add_tail(&fcport->list, &vha->vp_fcports);
4850
19759033
QT		 4851 }
4852 if (pla) {
4853 qlt_plogi_ack_link(vha, pla, fcport,
4854 QLT_PLOGI_LINK_SAME_WWN);
4855 pla->ref_count--;
726b8548
QT		 4856 }
4857 }
4858 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
4859
4860 if (fcport) {
9cd883f0
QT		 4861 if (N2N_TOPO(vha->hw))
4862 fcport->flags &= ~FCF_FABRIC_DEVICE;
4863
a4239945
QT		 4864 fcport->id_changed = 1;
4865 fcport->scan_state = QLA_FCPORT_FOUND;
4866 memcpy(fcport->node_name, e->u.new_sess.node_name, WWN_SIZE);
4867
5ef696aa 4868 if (pla) {
9cd883f0
QT		 4869 if (pla->iocb.u.isp24.status_subcode == ELS_PRLI) {
4870 u16 wd3_lo;
4871
4872 fcport->fw_login_state = DSC_LS_PRLI_PEND;
4873 fcport->local = 0;
4874 fcport->loop_id =
4875 le16_to_cpu(
4876 pla->iocb.u.isp24.nport_handle);
4877 fcport->fw_login_state = DSC_LS_PRLI_PEND;
4878 wd3_lo =
4879 le16_to_cpu(
4880 pla->iocb.u.isp24.u.prli.wd3_lo);
4881
4882 if (wd3_lo & BIT_7)
4883 fcport->conf_compl_supported = 1;
4884
4885 if ((wd3_lo & BIT_4) == 0)
4886 fcport->port_type = FCT_INITIATOR;
4887 else
4888 fcport->port_type = FCT_TARGET;
4889 }
726b8548 4890 qlt_plogi_ack_unref(vha, pla);
5ef696aa 4891 } else {
1c6cacf4
HR		 4892 fc_port_t *dfcp = NULL;
4893
5ef696aa
QT		 4894 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
4895 tfcp = qla2x00_find_fcport_by_nportid(vha,
4896 &e->u.new_sess.id, 1);
4897 if (tfcp && (tfcp != fcport)) {
4898 /*
4899 * We have a conflict fcport with same NportID.
4900 */
4901 ql_dbg(ql_dbg_disc, vha, 0xffff,
4902 "%s %8phC found conflict b4 add. DS %d LS %d\n",
4903 __func__, tfcp->port_name, tfcp->disc_state,
4904 tfcp->fw_login_state);
4905
4906 switch (tfcp->disc_state) {
4907 case DSC_DELETED:
4908 break;
4909 case DSC_DELETE_PEND:
4910 fcport->login_pause = 1;
4911 tfcp->conflict = fcport;
4912 break;
4913 default:
4914 fcport->login_pause = 1;
4915 tfcp->conflict = fcport;
1c6cacf4 4916 dfcp = tfcp;
5ef696aa
QT		 4917 break;
4918 }
4919 }
4920 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
1c6cacf4
HR		 4921 if (dfcp)
4922 qlt_schedule_sess_for_deletion(tfcp);
a4239945
QT		 4923
4924 wwn = wwn_to_u64(fcport->node_name);
4925
4926 if (!wwn)
4927 qla24xx_async_gnnid(vha, fcport);
4928 else
4929 qla24xx_async_gnl(vha, fcport);
5ef696aa 4930 }
726b8548 4931 }
b5d15312
QT		 4932
4933 if (free_fcport) {
4934 qla2x00_free_fcport(fcport);
4935 if (pla)
4936 kmem_cache_free(qla_tgt_plogi_cachep, pla);
4937 }
726b8548
QT		 4938}
4939
e374f9f5
QT		 4940static void qla_sp_retry(struct scsi_qla_host *vha, struct qla_work_evt *e)
4941{
4942 struct srb *sp = e->u.iosb.sp;
4943 int rval;
4944
4945 rval = qla2x00_start_sp(sp);
4946 if (rval != QLA_SUCCESS) {
4947 ql_dbg(ql_dbg_disc, vha, 0x2043,
4948 "%s: %s: Re-issue IOCB failed (%d).\n",
4949 __func__, sp->name, rval);
4950 qla24xx_sp_unmap(vha, sp);
4951 }
4952}
4953
ac280b67 4954void
e315cd28 4955qla2x00_do_work(struct scsi_qla_host *vha)
0971de7f 4956{
f999f4c1
AV		 4957 struct qla_work_evt *e, *tmp;
4958 unsigned long flags;
4959 LIST_HEAD(work);
0971de7f 4960
f999f4c1
AV		 4961 spin_lock_irqsave(&vha->work_lock, flags);
4962 list_splice_init(&vha->work_list, &work);
4963 spin_unlock_irqrestore(&vha->work_lock, flags);
4964
4965 list_for_each_entry_safe(e, tmp, &work, list) {
0971de7f 4966 list_del_init(&e->list);
0971de7f
AV		 4967
4968 switch (e->type) {
4969 case QLA_EVT_AEN:
e315cd28 4970 fc_host_post_event(vha->host, fc_get_event_number(),
0971de7f
AV		 4971 e->u.aen.code, e->u.aen.data);
4972 break;
8a659571
AV		 4973 case QLA_EVT_IDC_ACK:
4974 qla81xx_idc_ack(vha, e->u.idc_ack.mb);
4975 break;
ac280b67
AV		 4976 case QLA_EVT_ASYNC_LOGIN:
4977 qla2x00_async_login(vha, e->u.logio.fcport,
4978 e->u.logio.data);
4979 break;
ac280b67
AV		 4980 case QLA_EVT_ASYNC_LOGOUT:
4981 qla2x00_async_logout(vha, e->u.logio.fcport);
4982 break;
4983 case QLA_EVT_ASYNC_LOGOUT_DONE:
4984 qla2x00_async_logout_done(vha, e->u.logio.fcport,
4985 e->u.logio.data);
4986 break;
5ff1d584
AV		 4987 case QLA_EVT_ASYNC_ADISC:
4988 qla2x00_async_adisc(vha, e->u.logio.fcport,
4989 e->u.logio.data);
4990 break;
4991 case QLA_EVT_ASYNC_ADISC_DONE:
4992 qla2x00_async_adisc_done(vha, e->u.logio.fcport,
4993 e->u.logio.data);
4994 break;
3420d36c
AV		 4995 case QLA_EVT_UEVENT:
4996 qla2x00_uevent_emit(vha, e->u.uevent.code);
4997 break;
8ae6d9c7
GM		 4998 case QLA_EVT_AENFX:
4999 qlafx00_process_aen(vha, e);
5000 break;
726b8548
QT		 5001 case QLA_EVT_GIDPN:
5002 qla24xx_async_gidpn(vha, e->u.fcport.fcport);
5003 break;
5004 case QLA_EVT_GPNID:
5005 qla24xx_async_gpnid(vha, &e->u.gpnid.id);
5006 break;
e374f9f5
QT		 5007 case QLA_EVT_UNMAP:
5008 qla24xx_sp_unmap(vha, e->u.iosb.sp);
726b8548 5009 break;
9b3e0f4d
QT		 5010 case QLA_EVT_RELOGIN:
5011 qla2x00_relogin(vha);
5012 break;
726b8548
QT		 5013 case QLA_EVT_NEW_SESS:
5014 qla24xx_create_new_sess(vha, e);
5015 break;
5016 case QLA_EVT_GPDB:
5017 qla24xx_async_gpdb(vha, e->u.fcport.fcport,
5018 e->u.fcport.opt);
5019 break;
a5d42f4c
DG		 5020 case QLA_EVT_PRLI:
5021 qla24xx_async_prli(vha, e->u.fcport.fcport);
5022 break;
726b8548
QT		 5023 case QLA_EVT_GPSC:
5024 qla24xx_async_gpsc(vha, e->u.fcport.fcport);
5025 break;
5026 case QLA_EVT_UPD_FCPORT:
5027 qla2x00_update_fcport(vha, e->u.fcport.fcport);
5028 break;
5029 case QLA_EVT_GNL:
5030 qla24xx_async_gnl(vha, e->u.fcport.fcport);
5031 break;
5032 case QLA_EVT_NACK:
5033 qla24xx_do_nack_work(vha, e);
5034 break;
11aea16a
QT		 5035 case QLA_EVT_ASYNC_PRLO:
5036 qla2x00_async_prlo(vha, e->u.logio.fcport);
5037 break;
5038 case QLA_EVT_ASYNC_PRLO_DONE:
5039 qla2x00_async_prlo_done(vha, e->u.logio.fcport,
5040 e->u.logio.data);
5041 break;
a4239945 5042 case QLA_EVT_GPNFT:
33b28357
QT		 5043 qla24xx_async_gpnft(vha, e->u.gpnft.fc4_type,
5044 e->u.gpnft.sp);
a4239945
QT		 5045 break;
5046 case QLA_EVT_GPNFT_DONE:
5047 qla24xx_async_gpnft_done(vha, e->u.iosb.sp);
5048 break;
5049 case QLA_EVT_GNNFT_DONE:
5050 qla24xx_async_gnnft_done(vha, e->u.iosb.sp);
5051 break;
5052 case QLA_EVT_GNNID:
5053 qla24xx_async_gnnid(vha, e->u.fcport.fcport);
5054 break;
5055 case QLA_EVT_GFPNID:
5056 qla24xx_async_gfpnid(vha, e->u.fcport.fcport);
5057 break;
e374f9f5
QT		 5058 case QLA_EVT_SP_RETRY:
5059 qla_sp_retry(vha, e);
cc28e0ac
QT		 5060 break;
5061 case QLA_EVT_IIDMA:
5062 qla_do_iidma_work(vha, e->u.fcport.fcport);
5063 break;
0971de7f
AV		 5064 }
5065 if (e->flags & QLA_EVT_FLAG_FREE)
5066 kfree(e);
feafb7b1
AE		 5067
5068 /* For each work completed decrement vha ref count */
5069 QLA_VHA_MARK_NOT_BUSY(vha);
e315cd28 5070 }
e315cd28 5071}
f999f4c1 5072
9b3e0f4d
QT		 5073int qla24xx_post_relogin_work(struct scsi_qla_host *vha)
5074{
5075 struct qla_work_evt *e;
5076
5077 e = qla2x00_alloc_work(vha, QLA_EVT_RELOGIN);
5078
5079 if (!e) {
5080 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
5081 return QLA_FUNCTION_FAILED;
5082 }
5083
5084 return qla2x00_post_work(vha, e);
5085}
5086
e315cd28
AC		 5087/* Relogins all the fcports of a vport
5088 * Context: dpc thread
5089 */
5090void qla2x00_relogin(struct scsi_qla_host *vha)
5091{
5092 fc_port_t *fcport;
23dd98a6 5093 int status, relogin_needed = 0;
726b8548 5094 struct event_arg ea;
e315cd28
AC		 5095
5096 list_for_each_entry(fcport, &vha->vp_fcports, list) {
9cd883f0
QT		 5097 /*
5098 * If the port is not ONLINE then try to login
5099 * to it if we haven't run out of retries.
5100 */
5ff1d584 5101 if (atomic_read(&fcport->state) != FCS_ONLINE &&
23dd98a6
QT		 5102 fcport->login_retry) {
5103 if (fcport->scan_state != QLA_FCPORT_FOUND ||
5104 fcport->disc_state == DSC_LOGIN_COMPLETE)
5105 continue;
e315cd28 5106
23dd98a6
QT		 5107 if (fcport->flags & (FCF_ASYNC_SENT|FCF_ASYNC_ACTIVE) ||
5108 fcport->disc_state == DSC_DELETE_PEND) {
5109 relogin_needed = 1;
5110 } else {
5111 if (vha->hw->current_topology != ISP_CFG_NL) {
5112 memset(&ea, 0, sizeof(ea));
5113 ea.event = FCME_RELOGIN;
5114 ea.fcport = fcport;
5115 qla2x00_fcport_event_handler(vha, &ea);
5116 } else if (vha->hw->current_topology ==
5117 ISP_CFG_NL) {
5118 fcport->login_retry--;
5119 status =
5120 qla2x00_local_device_login(vha,
5121 fcport);
5122 if (status == QLA_SUCCESS) {
5123 fcport->old_loop_id =
5124 fcport->loop_id;
5125 ql_dbg(ql_dbg_disc, vha, 0x2003,
5126 "Port login OK: logged in ID 0x%x.\n",
5127 fcport->loop_id);
5128 qla2x00_update_fcport
5129 (vha, fcport);
5130 } else if (status == 1) {
5131 set_bit(RELOGIN_NEEDED,
5132 &vha->dpc_flags);
5133 /* retry the login again */
5134 ql_dbg(ql_dbg_disc, vha, 0x2007,
5135 "Retrying %d login again loop_id 0x%x.\n",
5136 fcport->login_retry,
5137 fcport->loop_id);
5138 } else {
5139 fcport->login_retry = 0;
5140 }
5141
5142 if (fcport->login_retry == 0 &&
5143 status != QLA_SUCCESS)
5144 qla2x00_clear_loop_id(fcport);
5145 }
e315cd28 5146 }
e315cd28
AC		 5147 }
5148 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
5149 break;
0971de7f 5150 }
9b3e0f4d 5151
23dd98a6
QT		 5152 if (relogin_needed)
5153 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
5154
9b3e0f4d
QT		 5155 ql_dbg(ql_dbg_disc, vha, 0x400e,
5156 "Relogin end.\n");
0971de7f
AV		 5157}
5158
7d613ac6
SV		 5159/* Schedule work on any of the dpc-workqueues */
5160void
5161qla83xx_schedule_work(scsi_qla_host_t *base_vha, int work_code)
5162{
5163 struct qla_hw_data *ha = base_vha->hw;
5164
5165 switch (work_code) {
5166 case MBA_IDC_AEN: /* 0x8200 */
5167 if (ha->dpc_lp_wq)
5168 queue_work(ha->dpc_lp_wq, &ha->idc_aen);
5169 break;
5170
5171 case QLA83XX_NIC_CORE_RESET: /* 0x1 */
5172 if (!ha->flags.nic_core_reset_hdlr_active) {
5173 if (ha->dpc_hp_wq)
5174 queue_work(ha->dpc_hp_wq, &ha->nic_core_reset);
5175 } else
5176 ql_dbg(ql_dbg_p3p, base_vha, 0xb05e,
5177 "NIC Core reset is already active. Skip "
5178 "scheduling it again.\n");
5179 break;
5180 case QLA83XX_IDC_STATE_HANDLER: /* 0x2 */
5181 if (ha->dpc_hp_wq)
5182 queue_work(ha->dpc_hp_wq, &ha->idc_state_handler);
5183 break;
5184 case QLA83XX_NIC_CORE_UNRECOVERABLE: /* 0x3 */
5185 if (ha->dpc_hp_wq)
5186 queue_work(ha->dpc_hp_wq, &ha->nic_core_unrecoverable);
5187 break;
5188 default:
5189 ql_log(ql_log_warn, base_vha, 0xb05f,
d939be3a 5190 "Unknown work-code=0x%x.\n", work_code);
7d613ac6
SV		 5191 }
5192
5193 return;
5194}
5195
5196/* Work: Perform NIC Core Unrecoverable state handling */
5197void
5198qla83xx_nic_core_unrecoverable_work(struct work_struct *work)
5199{
5200 struct qla_hw_data *ha =
2ad1b67c 5201 container_of(work, struct qla_hw_data, nic_core_unrecoverable);
7d613ac6
SV		 5202 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5203 uint32_t dev_state = 0;
5204
5205 qla83xx_idc_lock(base_vha, 0);
5206 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
5207 qla83xx_reset_ownership(base_vha);
5208 if (ha->flags.nic_core_reset_owner) {
5209 ha->flags.nic_core_reset_owner = 0;
5210 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
5211 QLA8XXX_DEV_FAILED);
5212 ql_log(ql_log_info, base_vha, 0xb060, "HW State: FAILED.\n");
5213 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
5214 }
5215 qla83xx_idc_unlock(base_vha, 0);
5216}
5217
5218/* Work: Execute IDC state handler */
5219void
5220qla83xx_idc_state_handler_work(struct work_struct *work)
5221{
5222 struct qla_hw_data *ha =
2ad1b67c 5223 container_of(work, struct qla_hw_data, idc_state_handler);
7d613ac6
SV		 5224 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5225 uint32_t dev_state = 0;
5226
5227 qla83xx_idc_lock(base_vha, 0);
5228 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
5229 if (dev_state == QLA8XXX_DEV_FAILED ||
5230 dev_state == QLA8XXX_DEV_NEED_QUIESCENT)
5231 qla83xx_idc_state_handler(base_vha);
5232 qla83xx_idc_unlock(base_vha, 0);
5233}
5234
fa492630 5235static int
7d613ac6
SV		 5236qla83xx_check_nic_core_fw_alive(scsi_qla_host_t *base_vha)
5237{
5238 int rval = QLA_SUCCESS;
5239 unsigned long heart_beat_wait = jiffies + (1 * HZ);
5240 uint32_t heart_beat_counter1, heart_beat_counter2;
5241
5242 do {
5243 if (time_after(jiffies, heart_beat_wait)) {
5244 ql_dbg(ql_dbg_p3p, base_vha, 0xb07c,
5245 "Nic Core f/w is not alive.\n");
5246 rval = QLA_FUNCTION_FAILED;
5247 break;
5248 }
5249
5250 qla83xx_idc_lock(base_vha, 0);
5251 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
5252 &heart_beat_counter1);
5253 qla83xx_idc_unlock(base_vha, 0);
5254 msleep(100);
5255 qla83xx_idc_lock(base_vha, 0);
5256 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
5257 &heart_beat_counter2);
5258 qla83xx_idc_unlock(base_vha, 0);
5259 } while (heart_beat_counter1 == heart_beat_counter2);
5260
5261 return rval;
5262}
5263
5264/* Work: Perform NIC Core Reset handling */
5265void
5266qla83xx_nic_core_reset_work(struct work_struct *work)
5267{
5268 struct qla_hw_data *ha =
5269 container_of(work, struct qla_hw_data, nic_core_reset);
5270 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5271 uint32_t dev_state = 0;
5272
81178772
SK		 5273 if (IS_QLA2031(ha)) {
5274 if (qla2xxx_mctp_dump(base_vha) != QLA_SUCCESS)
5275 ql_log(ql_log_warn, base_vha, 0xb081,
5276 "Failed to dump mctp\n");
5277 return;
5278 }
5279
7d613ac6
SV		 5280 if (!ha->flags.nic_core_reset_hdlr_active) {
5281 if (qla83xx_check_nic_core_fw_alive(base_vha) == QLA_SUCCESS) {
5282 qla83xx_idc_lock(base_vha, 0);
5283 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE,
5284 &dev_state);
5285 qla83xx_idc_unlock(base_vha, 0);
5286 if (dev_state != QLA8XXX_DEV_NEED_RESET) {
5287 ql_dbg(ql_dbg_p3p, base_vha, 0xb07a,
5288 "Nic Core f/w is alive.\n");
5289 return;
5290 }
5291 }
5292
5293 ha->flags.nic_core_reset_hdlr_active = 1;
5294 if (qla83xx_nic_core_reset(base_vha)) {
5295 /* NIC Core reset failed. */
5296 ql_dbg(ql_dbg_p3p, base_vha, 0xb061,
5297 "NIC Core reset failed.\n");
5298 }
5299 ha->flags.nic_core_reset_hdlr_active = 0;
5300 }
5301}
5302
5303/* Work: Handle 8200 IDC aens */
5304void
5305qla83xx_service_idc_aen(struct work_struct *work)
5306{
5307 struct qla_hw_data *ha =
5308 container_of(work, struct qla_hw_data, idc_aen);
5309 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5310 uint32_t dev_state, idc_control;
5311
5312 qla83xx_idc_lock(base_vha, 0);
5313 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
5314 qla83xx_rd_reg(base_vha, QLA83XX_IDC_CONTROL, &idc_control);
5315 qla83xx_idc_unlock(base_vha, 0);
5316 if (dev_state == QLA8XXX_DEV_NEED_RESET) {
5317 if (idc_control & QLA83XX_IDC_GRACEFUL_RESET) {
5318 ql_dbg(ql_dbg_p3p, base_vha, 0xb062,
5319 "Application requested NIC Core Reset.\n");
5320 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
5321 } else if (qla83xx_check_nic_core_fw_alive(base_vha) ==
5322 QLA_SUCCESS) {
5323 ql_dbg(ql_dbg_p3p, base_vha, 0xb07b,
5324 "Other protocol driver requested NIC Core Reset.\n");
5325 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
5326 }
5327 } else if (dev_state == QLA8XXX_DEV_FAILED ||
5328 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) {
5329 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
5330 }
5331}
5332
5333static void
5334qla83xx_wait_logic(void)
5335{
5336 int i;
5337
5338 /* Yield CPU */
5339 if (!in_interrupt()) {
5340 /*
5341 * Wait about 200ms before retrying again.
5342 * This controls the number of retries for single
5343 * lock operation.
5344 */
5345 msleep(100);
5346 schedule();
5347 } else {
5348 for (i = 0; i < 20; i++)
5349 cpu_relax(); /* This a nop instr on i386 */
5350 }
5351}
5352
fa492630 5353static int
7d613ac6
SV		 5354qla83xx_force_lock_recovery(scsi_qla_host_t *base_vha)
5355{
5356 int rval;
5357 uint32_t data;
5358 uint32_t idc_lck_rcvry_stage_mask = 0x3;
5359 uint32_t idc_lck_rcvry_owner_mask = 0x3c;
5360 struct qla_hw_data *ha = base_vha->hw;
6c315553
SK		 5361 ql_dbg(ql_dbg_p3p, base_vha, 0xb086,
5362 "Trying force recovery of the IDC lock.\n");
7d613ac6
SV		 5363
5364 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, &data);
5365 if (rval)
5366 return rval;
5367
5368 if ((data & idc_lck_rcvry_stage_mask) > 0) {
5369 return QLA_SUCCESS;
5370 } else {
5371 data = (IDC_LOCK_RECOVERY_STAGE1) | (ha->portnum << 2);
5372 rval = qla83xx_wr_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
5373 data);
5374 if (rval)
5375 return rval;
5376
5377 msleep(200);
5378
5379 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
5380 &data);
5381 if (rval)
5382 return rval;
5383
5384 if (((data & idc_lck_rcvry_owner_mask) >> 2) == ha->portnum) {
5385 data &= (IDC_LOCK_RECOVERY_STAGE2 |
5386 ~(idc_lck_rcvry_stage_mask));
5387 rval = qla83xx_wr_reg(base_vha,
5388 QLA83XX_IDC_LOCK_RECOVERY, data);
5389 if (rval)
5390 return rval;
5391
5392 /* Forcefully perform IDC UnLock */
5393 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK,
5394 &data);
5395 if (rval)
5396 return rval;
5397 /* Clear lock-id by setting 0xff */
5398 rval = qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
5399 0xff);
5400 if (rval)
5401 return rval;
5402 /* Clear lock-recovery by setting 0x0 */
5403 rval = qla83xx_wr_reg(base_vha,
5404 QLA83XX_IDC_LOCK_RECOVERY, 0x0);
5405 if (rval)
5406 return rval;
5407 } else
5408 return QLA_SUCCESS;
5409 }
5410
5411 return rval;
5412}
5413
fa492630 5414static int
7d613ac6
SV		 5415qla83xx_idc_lock_recovery(scsi_qla_host_t *base_vha)
5416{
5417 int rval = QLA_SUCCESS;
5418 uint32_t o_drv_lockid, n_drv_lockid;
5419 unsigned long lock_recovery_timeout;
5420
5421 lock_recovery_timeout = jiffies + QLA83XX_MAX_LOCK_RECOVERY_WAIT;
5422retry_lockid:
5423 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &o_drv_lockid);
5424 if (rval)
5425 goto exit;
5426
5427 /* MAX wait time before forcing IDC Lock recovery = 2 secs */
5428 if (time_after_eq(jiffies, lock_recovery_timeout)) {
5429 if (qla83xx_force_lock_recovery(base_vha) == QLA_SUCCESS)
5430 return QLA_SUCCESS;
5431 else
5432 return QLA_FUNCTION_FAILED;
5433 }
5434
5435 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &n_drv_lockid);
5436 if (rval)
5437 goto exit;
5438
5439 if (o_drv_lockid == n_drv_lockid) {
5440 qla83xx_wait_logic();
5441 goto retry_lockid;
5442 } else
5443 return QLA_SUCCESS;
5444
5445exit:
5446 return rval;
5447}
5448
5449void
5450qla83xx_idc_lock(scsi_qla_host_t *base_vha, uint16_t requester_id)
5451{
5452 uint16_t options = (requester_id << 15) | BIT_6;
5453 uint32_t data;
6c315553 5454 uint32_t lock_owner;
7d613ac6
SV		 5455 struct qla_hw_data *ha = base_vha->hw;
5456
5457 /* IDC-lock implementation using driver-lock/lock-id remote registers */
5458retry_lock:
5459 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCK, &data)
5460 == QLA_SUCCESS) {
5461 if (data) {
5462 /* Setting lock-id to our function-number */
5463 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
5464 ha->portnum);
5465 } else {
6c315553
SK		 5466 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID,
5467 &lock_owner);
7d613ac6 5468 ql_dbg(ql_dbg_p3p, base_vha, 0xb063,
6c315553
SK		 5469 "Failed to acquire IDC lock, acquired by %d, "
5470 "retrying...\n", lock_owner);
7d613ac6
SV		 5471
5472 /* Retry/Perform IDC-Lock recovery */
5473 if (qla83xx_idc_lock_recovery(base_vha)
5474 == QLA_SUCCESS) {
5475 qla83xx_wait_logic();
5476 goto retry_lock;
5477 } else
5478 ql_log(ql_log_warn, base_vha, 0xb075,
5479 "IDC Lock recovery FAILED.\n");
5480 }
5481
5482 }
5483
5484 return;
5485
5486 /* XXX: IDC-lock implementation using access-control mbx */
5487retry_lock2:
5488 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
5489 ql_dbg(ql_dbg_p3p, base_vha, 0xb072,
5490 "Failed to acquire IDC lock. retrying...\n");
5491 /* Retry/Perform IDC-Lock recovery */
5492 if (qla83xx_idc_lock_recovery(base_vha) == QLA_SUCCESS) {
5493 qla83xx_wait_logic();
5494 goto retry_lock2;
5495 } else
5496 ql_log(ql_log_warn, base_vha, 0xb076,
5497 "IDC Lock recovery FAILED.\n");
5498 }
5499
5500 return;
5501}
5502
5503void
5504qla83xx_idc_unlock(scsi_qla_host_t *base_vha, uint16_t requester_id)
5505{
5897cb2f
BVA		 5506#if 0
5507 uint16_t options = (requester_id << 15) | BIT_7;
5508#endif
5509 uint16_t retry;
7d613ac6
SV		 5510 uint32_t data;
5511 struct qla_hw_data *ha = base_vha->hw;
5512
5513 /* IDC-unlock implementation using driver-unlock/lock-id
5514 * remote registers
5515 */
5516 retry = 0;
5517retry_unlock:
5518 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &data)
5519 == QLA_SUCCESS) {
5520 if (data == ha->portnum) {
5521 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, &data);
5522 /* Clearing lock-id by setting 0xff */
5523 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 0xff);
5524 } else if (retry < 10) {
5525 /* SV: XXX: IDC unlock retrying needed here? */
5526
5527 /* Retry for IDC-unlock */
5528 qla83xx_wait_logic();
5529 retry++;
5530 ql_dbg(ql_dbg_p3p, base_vha, 0xb064,
ee6a8773 5531 "Failed to release IDC lock, retrying=%d\n", retry);
7d613ac6
SV		 5532 goto retry_unlock;
5533 }
5534 } else if (retry < 10) {
5535 /* Retry for IDC-unlock */
5536 qla83xx_wait_logic();
5537 retry++;
5538 ql_dbg(ql_dbg_p3p, base_vha, 0xb065,
ee6a8773 5539 "Failed to read drv-lockid, retrying=%d\n", retry);
7d613ac6
SV		 5540 goto retry_unlock;
5541 }
5542
5543 return;
5544
5897cb2f 5545#if 0
7d613ac6
SV		 5546 /* XXX: IDC-unlock implementation using access-control mbx */
5547 retry = 0;
5548retry_unlock2:
5549 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
5550 if (retry < 10) {
5551 /* Retry for IDC-unlock */
5552 qla83xx_wait_logic();
5553 retry++;
5554 ql_dbg(ql_dbg_p3p, base_vha, 0xb066,
ee6a8773 5555 "Failed to release IDC lock, retrying=%d\n", retry);
7d613ac6
SV		 5556 goto retry_unlock2;
5557 }
5558 }
5559
5560 return;
5897cb2f 5561#endif
7d613ac6
SV		 5562}
5563
5564int
5565__qla83xx_set_drv_presence(scsi_qla_host_t *vha)
5566{
5567 int rval = QLA_SUCCESS;
5568 struct qla_hw_data *ha = vha->hw;
5569 uint32_t drv_presence;
5570
5571 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
5572 if (rval == QLA_SUCCESS) {
5573 drv_presence |= (1 << ha->portnum);
5574 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
5575 drv_presence);
5576 }
5577
5578 return rval;
5579}
5580
5581int
5582qla83xx_set_drv_presence(scsi_qla_host_t *vha)
5583{
5584 int rval = QLA_SUCCESS;
5585
5586 qla83xx_idc_lock(vha, 0);
5587 rval = __qla83xx_set_drv_presence(vha);
5588 qla83xx_idc_unlock(vha, 0);
5589
5590 return rval;
5591}
5592
5593int
5594__qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
5595{
5596 int rval = QLA_SUCCESS;
5597 struct qla_hw_data *ha = vha->hw;
5598 uint32_t drv_presence;
5599
5600 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
5601 if (rval == QLA_SUCCESS) {
5602 drv_presence &= ~(1 << ha->portnum);
5603 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
5604 drv_presence);
5605 }
5606
5607 return rval;
5608}
5609
5610int
5611qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
5612{
5613 int rval = QLA_SUCCESS;
5614
5615 qla83xx_idc_lock(vha, 0);
5616 rval = __qla83xx_clear_drv_presence(vha);
5617 qla83xx_idc_unlock(vha, 0);
5618
5619 return rval;
5620}
5621
fa492630 5622static void
7d613ac6
SV		 5623qla83xx_need_reset_handler(scsi_qla_host_t *vha)
5624{
5625 struct qla_hw_data *ha = vha->hw;
5626 uint32_t drv_ack, drv_presence;
5627 unsigned long ack_timeout;
5628
5629 /* Wait for IDC ACK from all functions (DRV-ACK == DRV-PRESENCE) */
5630 ack_timeout = jiffies + (ha->fcoe_reset_timeout * HZ);
5631 while (1) {
5632 qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
5633 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
807fb6d8 5634 if ((drv_ack & drv_presence) == drv_presence)
7d613ac6
SV		 5635 break;
5636
5637 if (time_after_eq(jiffies, ack_timeout)) {
5638 ql_log(ql_log_warn, vha, 0xb067,
5639 "RESET ACK TIMEOUT! drv_presence=0x%x "
5640 "drv_ack=0x%x\n", drv_presence, drv_ack);
5641 /*
5642 * The function(s) which did not ack in time are forced
5643 * to withdraw any further participation in the IDC
5644 * reset.
5645 */
5646 if (drv_ack != drv_presence)
5647 qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
5648 drv_ack);
5649 break;
5650 }
5651
5652 qla83xx_idc_unlock(vha, 0);
5653 msleep(1000);
5654 qla83xx_idc_lock(vha, 0);
5655 }
5656
5657 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_COLD);
5658 ql_log(ql_log_info, vha, 0xb068, "HW State: COLD/RE-INIT.\n");
5659}
5660
fa492630 5661static int
7d613ac6
SV		 5662qla83xx_device_bootstrap(scsi_qla_host_t *vha)
5663{
5664 int rval = QLA_SUCCESS;
5665 uint32_t idc_control;
5666
5667 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_INITIALIZING);
5668 ql_log(ql_log_info, vha, 0xb069, "HW State: INITIALIZING.\n");
5669
5670 /* Clearing IDC-Control Graceful-Reset Bit before resetting f/w */
5671 __qla83xx_get_idc_control(vha, &idc_control);
5672 idc_control &= ~QLA83XX_IDC_GRACEFUL_RESET;
5673 __qla83xx_set_idc_control(vha, 0);
5674
5675 qla83xx_idc_unlock(vha, 0);
5676 rval = qla83xx_restart_nic_firmware(vha);
5677 qla83xx_idc_lock(vha, 0);
5678
5679 if (rval != QLA_SUCCESS) {
5680 ql_log(ql_log_fatal, vha, 0xb06a,
5681 "Failed to restart NIC f/w.\n");
5682 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_FAILED);
5683 ql_log(ql_log_info, vha, 0xb06b, "HW State: FAILED.\n");
5684 } else {
5685 ql_dbg(ql_dbg_p3p, vha, 0xb06c,
5686 "Success in restarting nic f/w.\n");
5687 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_READY);
5688 ql_log(ql_log_info, vha, 0xb06d, "HW State: READY.\n");
5689 }
5690
5691 return rval;
5692}
5693
5694/* Assumes idc_lock always held on entry */
5695int
5696qla83xx_idc_state_handler(scsi_qla_host_t *base_vha)
5697{
5698 struct qla_hw_data *ha = base_vha->hw;
5699 int rval = QLA_SUCCESS;
5700 unsigned long dev_init_timeout;
5701 uint32_t dev_state;
5702
5703 /* Wait for MAX-INIT-TIMEOUT for the device to go ready */
5704 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ);
5705
5706 while (1) {
5707
5708 if (time_after_eq(jiffies, dev_init_timeout)) {
5709 ql_log(ql_log_warn, base_vha, 0xb06e,
5710 "Initialization TIMEOUT!\n");
5711 /* Init timeout. Disable further NIC Core
5712 * communication.
5713 */
5714 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
5715 QLA8XXX_DEV_FAILED);
5716 ql_log(ql_log_info, base_vha, 0xb06f,
5717 "HW State: FAILED.\n");
5718 }
5719
5720 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
5721 switch (dev_state) {
5722 case QLA8XXX_DEV_READY:
5723 if (ha->flags.nic_core_reset_owner)
5724 qla83xx_idc_audit(base_vha,
5725 IDC_AUDIT_COMPLETION);
5726 ha->flags.nic_core_reset_owner = 0;
5727 ql_dbg(ql_dbg_p3p, base_vha, 0xb070,
5728 "Reset_owner reset by 0x%x.\n",
5729 ha->portnum);
5730 goto exit;
5731 case QLA8XXX_DEV_COLD:
5732 if (ha->flags.nic_core_reset_owner)
5733 rval = qla83xx_device_bootstrap(base_vha);
5734 else {
5735 /* Wait for AEN to change device-state */
5736 qla83xx_idc_unlock(base_vha, 0);
5737 msleep(1000);
5738 qla83xx_idc_lock(base_vha, 0);
5739 }
5740 break;
5741 case QLA8XXX_DEV_INITIALIZING:
5742 /* Wait for AEN to change device-state */
5743 qla83xx_idc_unlock(base_vha, 0);
5744 msleep(1000);
5745 qla83xx_idc_lock(base_vha, 0);
5746 break;
5747 case QLA8XXX_DEV_NEED_RESET:
5748 if (!ql2xdontresethba && ha->flags.nic_core_reset_owner)
5749 qla83xx_need_reset_handler(base_vha);
5750 else {
5751 /* Wait for AEN to change device-state */
5752 qla83xx_idc_unlock(base_vha, 0);
5753 msleep(1000);
5754 qla83xx_idc_lock(base_vha, 0);
5755 }
5756 /* reset timeout value after need reset handler */
5757 dev_init_timeout = jiffies +
5758 (ha->fcoe_dev_init_timeout * HZ);
5759 break;
5760 case QLA8XXX_DEV_NEED_QUIESCENT:
5761 /* XXX: DEBUG for now */
5762 qla83xx_idc_unlock(base_vha, 0);
5763 msleep(1000);
5764 qla83xx_idc_lock(base_vha, 0);
5765 break;
5766 case QLA8XXX_DEV_QUIESCENT:
5767 /* XXX: DEBUG for now */
5768 if (ha->flags.quiesce_owner)
5769 goto exit;
5770
5771 qla83xx_idc_unlock(base_vha, 0);
5772 msleep(1000);
5773 qla83xx_idc_lock(base_vha, 0);
5774 dev_init_timeout = jiffies +
5775 (ha->fcoe_dev_init_timeout * HZ);
5776 break;
5777 case QLA8XXX_DEV_FAILED:
5778 if (ha->flags.nic_core_reset_owner)
5779 qla83xx_idc_audit(base_vha,
5780 IDC_AUDIT_COMPLETION);
5781 ha->flags.nic_core_reset_owner = 0;
5782 __qla83xx_clear_drv_presence(base_vha);
5783 qla83xx_idc_unlock(base_vha, 0);
5784 qla8xxx_dev_failed_handler(base_vha);
5785 rval = QLA_FUNCTION_FAILED;
5786 qla83xx_idc_lock(base_vha, 0);
5787 goto exit;
5788 case QLA8XXX_BAD_VALUE:
5789 qla83xx_idc_unlock(base_vha, 0);
5790 msleep(1000);
5791 qla83xx_idc_lock(base_vha, 0);
5792 break;
5793 default:
5794 ql_log(ql_log_warn, base_vha, 0xb071,
d939be3a 5795 "Unknown Device State: %x.\n", dev_state);
7d613ac6
SV		 5796 qla83xx_idc_unlock(base_vha, 0);
5797 qla8xxx_dev_failed_handler(base_vha);
5798 rval = QLA_FUNCTION_FAILED;
5799 qla83xx_idc_lock(base_vha, 0);
5800 goto exit;
5801 }
5802 }
5803
5804exit:
5805 return rval;
5806}
5807
f3ddac19
CD		 5808void
5809qla2x00_disable_board_on_pci_error(struct work_struct *work)
5810{
5811 struct qla_hw_data *ha = container_of(work, struct qla_hw_data,
5812 board_disable);
5813 struct pci_dev *pdev = ha->pdev;
5814 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5815
726b8548
QT		 5816 /*
5817 * if UNLOAD flag is already set, then continue unload,
783e0dc4
SC		 5818 * where it was set first.
5819 */
5820 if (test_bit(UNLOADING, &base_vha->dpc_flags))
5821 return;
5822
f3ddac19
CD		 5823 ql_log(ql_log_warn, base_vha, 0x015b,
5824 "Disabling adapter.\n");
5825
efdb5760
SC		 5826 if (!atomic_read(&pdev->enable_cnt)) {
5827 ql_log(ql_log_info, base_vha, 0xfffc,
5828 "PCI device disabled, no action req for PCI error=%lx\n",
5829 base_vha->pci_flags);
5830 return;
5831 }
5832
726b8548
QT		 5833 qla2x00_wait_for_sess_deletion(base_vha);
5834
f3ddac19
CD		 5835 set_bit(UNLOADING, &base_vha->dpc_flags);
5836
5837 qla2x00_delete_all_vps(ha, base_vha);
5838
5839 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
5840
5841 qla2x00_dfs_remove(base_vha);
5842
5843 qla84xx_put_chip(base_vha);
5844
5845 if (base_vha->timer_active)
5846 qla2x00_stop_timer(base_vha);
5847
5848 base_vha->flags.online = 0;
5849
5850 qla2x00_destroy_deferred_work(ha);
5851
5852 /*
5853 * Do not try to stop beacon blink as it will issue a mailbox
5854 * command.
5855 */
5856 qla2x00_free_sysfs_attr(base_vha, false);
5857
5858 fc_remove_host(base_vha->host);
5859
5860 scsi_remove_host(base_vha->host);
5861
5862 base_vha->flags.init_done = 0;
5863 qla25xx_delete_queues(base_vha);
f3ddac19 5864 qla2x00_free_fcports(base_vha);
093df737 5865 qla2x00_free_irqs(base_vha);
f3ddac19
CD		 5866 qla2x00_mem_free(ha);
5867 qla82xx_md_free(base_vha);
5868 qla2x00_free_queues(ha);
5869
f3ddac19
CD		 5870 qla2x00_unmap_iobases(ha);
5871
5872 pci_release_selected_regions(ha->pdev, ha->bars);
f3ddac19
CD		 5873 pci_disable_pcie_error_reporting(pdev);
5874 pci_disable_device(pdev);
f3ddac19 5875
beb9e315
JL		 5876 /*
5877 * Let qla2x00_remove_one cleanup qla_hw_data on device removal.
5878 */
f3ddac19
CD		 5879}
5880
1da177e4
LT		 5881/**************************************************************************
5882* qla2x00_do_dpc
5883* This kernel thread is a task that is schedule by the interrupt handler
5884* to perform the background processing for interrupts.
5885*
5886* Notes:
5887* This task always run in the context of a kernel thread. It
5888* is kick-off by the driver's detect code and starts up
5889* up one per adapter. It immediately goes to sleep and waits for
5890* some fibre event. When either the interrupt handler or
5891* the timer routine detects a event it will one of the task
5892* bits then wake us up.
5893**************************************************************************/
5894static int
5895qla2x00_do_dpc(void *data)
5896{
e315cd28
AC		 5897 scsi_qla_host_t *base_vha;
5898 struct qla_hw_data *ha;
d7459527
MH		 5899 uint32_t online;
5900 struct qla_qpair *qpair;
1da177e4 5901
e315cd28
AC		 5902 ha = (struct qla_hw_data *)data;
5903 base_vha = pci_get_drvdata(ha->pdev);
1da177e4 5904
8698a745 5905 set_user_nice(current, MIN_NICE);
1da177e4 5906
563585ec 5907 set_current_state(TASK_INTERRUPTIBLE);
39a11240 5908 while (!kthread_should_stop()) {
7c3df132
SK		 5909 ql_dbg(ql_dbg_dpc, base_vha, 0x4000,
5910 "DPC handler sleeping.\n");
1da177e4 5911
39a11240 5912 schedule();
1da177e4 5913
c142caf0
AV		 5914 if (!base_vha->flags.init_done || ha->flags.mbox_busy)
5915 goto end_loop;
1da177e4 5916
85880801 5917 if (ha->flags.eeh_busy) {
7c3df132
SK		 5918 ql_dbg(ql_dbg_dpc, base_vha, 0x4003,
5919 "eeh_busy=%d.\n", ha->flags.eeh_busy);
c142caf0 5920 goto end_loop;
85880801
AV		 5921 }
5922
1da177e4
LT		 5923 ha->dpc_active = 1;
5924
5f28d2d7
SK		 5925 ql_dbg(ql_dbg_dpc + ql_dbg_verbose, base_vha, 0x4001,
5926 "DPC handler waking up, dpc_flags=0x%lx.\n",
5927 base_vha->dpc_flags);
1da177e4 5928
a29b3dd7
JC		 5929 if (test_bit(UNLOADING, &base_vha->dpc_flags))
5930 break;
5931
7ec0effd
AD		 5932 if (IS_P3P_TYPE(ha)) {
5933 if (IS_QLA8044(ha)) {
5934 if (test_and_clear_bit(ISP_UNRECOVERABLE,
5935 &base_vha->dpc_flags)) {
5936 qla8044_idc_lock(ha);
5937 qla8044_wr_direct(base_vha,
5938 QLA8044_CRB_DEV_STATE_INDEX,
5939 QLA8XXX_DEV_FAILED);
5940 qla8044_idc_unlock(ha);
5941 ql_log(ql_log_info, base_vha, 0x4004,
5942 "HW State: FAILED.\n");
5943 qla8044_device_state_handler(base_vha);
5944 continue;
5945 }
5946
5947 } else {
5948 if (test_and_clear_bit(ISP_UNRECOVERABLE,
5949 &base_vha->dpc_flags)) {
5950 qla82xx_idc_lock(ha);
5951 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
5952 QLA8XXX_DEV_FAILED);
5953 qla82xx_idc_unlock(ha);
5954 ql_log(ql_log_info, base_vha, 0x0151,
5955 "HW State: FAILED.\n");
5956 qla82xx_device_state_handler(base_vha);
5957 continue;
5958 }
a9083016
GM		 5959 }
5960
5961 if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED,
5962 &base_vha->dpc_flags)) {
5963
7c3df132
SK		 5964 ql_dbg(ql_dbg_dpc, base_vha, 0x4005,
5965 "FCoE context reset scheduled.\n");
a9083016
GM		 5966 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
5967 &base_vha->dpc_flags))) {
5968 if (qla82xx_fcoe_ctx_reset(base_vha)) {
5969 /* FCoE-ctx reset failed.
5970 * Escalate to chip-reset
5971 */
5972 set_bit(ISP_ABORT_NEEDED,
5973 &base_vha->dpc_flags);
5974 }
5975 clear_bit(ABORT_ISP_ACTIVE,
5976 &base_vha->dpc_flags);
5977 }
5978
7c3df132
SK		 5979 ql_dbg(ql_dbg_dpc, base_vha, 0x4006,
5980 "FCoE context reset end.\n");
a9083016 5981 }
8ae6d9c7
GM		 5982 } else if (IS_QLAFX00(ha)) {
5983 if (test_and_clear_bit(ISP_UNRECOVERABLE,
5984 &base_vha->dpc_flags)) {
5985 ql_dbg(ql_dbg_dpc, base_vha, 0x4020,
5986 "Firmware Reset Recovery\n");
5987 if (qlafx00_reset_initialize(base_vha)) {
5988 /* Failed. Abort isp later. */
5989 if (!test_bit(UNLOADING,
f92f82d6 5990 &base_vha->dpc_flags)) {
8ae6d9c7
GM		 5991 set_bit(ISP_UNRECOVERABLE,
5992 &base_vha->dpc_flags);
5993 ql_dbg(ql_dbg_dpc, base_vha,
5994 0x4021,
5995 "Reset Recovery Failed\n");
f92f82d6 5996 }
8ae6d9c7
GM		 5997 }
5998 }
5999
6000 if (test_and_clear_bit(FX00_TARGET_SCAN,
6001 &base_vha->dpc_flags)) {
6002 ql_dbg(ql_dbg_dpc, base_vha, 0x4022,
6003 "ISPFx00 Target Scan scheduled\n");
6004 if (qlafx00_rescan_isp(base_vha)) {
6005 if (!test_bit(UNLOADING,
6006 &base_vha->dpc_flags))
6007 set_bit(ISP_UNRECOVERABLE,
6008 &base_vha->dpc_flags);
6009 ql_dbg(ql_dbg_dpc, base_vha, 0x401e,
6010 "ISPFx00 Target Scan Failed\n");
6011 }
6012 ql_dbg(ql_dbg_dpc, base_vha, 0x401f,
6013 "ISPFx00 Target Scan End\n");
6014 }
e8f5e95d
AB		 6015 if (test_and_clear_bit(FX00_HOST_INFO_RESEND,
6016 &base_vha->dpc_flags)) {
6017 ql_dbg(ql_dbg_dpc, base_vha, 0x4023,
6018 "ISPFx00 Host Info resend scheduled\n");
6019 qlafx00_fx_disc(base_vha,
6020 &base_vha->hw->mr.fcport,
6021 FXDISC_REG_HOST_INFO);
6022 }
a9083016
GM		 6023 }
6024
e4e3a2ce
QT		 6025 if (test_and_clear_bit(DETECT_SFP_CHANGE,
6026 &base_vha->dpc_flags) &&
6027 !test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) {
6028 qla24xx_detect_sfp(base_vha);
6029
6030 if (ha->flags.detected_lr_sfp !=
6031 ha->flags.using_lr_setting)
6032 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
6033 }
6034
e315cd28
AC		 6035 if (test_and_clear_bit(ISP_ABORT_NEEDED,
6036 &base_vha->dpc_flags)) {
1da177e4 6037
7c3df132
SK		 6038 ql_dbg(ql_dbg_dpc, base_vha, 0x4007,
6039 "ISP abort scheduled.\n");
1da177e4 6040 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
e315cd28 6041 &base_vha->dpc_flags))) {
1da177e4 6042
a9083016 6043 if (ha->isp_ops->abort_isp(base_vha)) {
1da177e4
LT		 6044 /* failed. retry later */
6045 set_bit(ISP_ABORT_NEEDED,
e315cd28 6046 &base_vha->dpc_flags);
99363ef8 6047 }
e315cd28
AC		 6048 clear_bit(ABORT_ISP_ACTIVE,
6049 &base_vha->dpc_flags);
99363ef8
SJ		 6050 }
6051
7c3df132
SK		 6052 ql_dbg(ql_dbg_dpc, base_vha, 0x4008,
6053 "ISP abort end.\n");
1da177e4
LT		 6054 }
6055
a394aac8
DJ		 6056 if (test_and_clear_bit(FCPORT_UPDATE_NEEDED,
6057 &base_vha->dpc_flags)) {
e315cd28 6058 qla2x00_update_fcports(base_vha);
c9c5ced9 6059 }
d97994dc 6060
8ae6d9c7
GM		 6061 if (IS_QLAFX00(ha))
6062 goto loop_resync_check;
6063
579d12b5 6064 if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) {
7c3df132
SK		 6065 ql_dbg(ql_dbg_dpc, base_vha, 0x4009,
6066 "Quiescence mode scheduled.\n");
7ec0effd
AD		 6067 if (IS_P3P_TYPE(ha)) {
6068 if (IS_QLA82XX(ha))
6069 qla82xx_device_state_handler(base_vha);
6070 if (IS_QLA8044(ha))
6071 qla8044_device_state_handler(base_vha);
8fcd6b8b
CD		 6072 clear_bit(ISP_QUIESCE_NEEDED,
6073 &base_vha->dpc_flags);
6074 if (!ha->flags.quiesce_owner) {
6075 qla2x00_perform_loop_resync(base_vha);
7ec0effd
AD		 6076 if (IS_QLA82XX(ha)) {
6077 qla82xx_idc_lock(ha);
6078 qla82xx_clear_qsnt_ready(
6079 base_vha);
6080 qla82xx_idc_unlock(ha);
6081 } else if (IS_QLA8044(ha)) {
6082 qla8044_idc_lock(ha);
6083 qla8044_clear_qsnt_ready(
6084 base_vha);
6085 qla8044_idc_unlock(ha);
6086 }
8fcd6b8b
CD		 6087 }
6088 } else {
6089 clear_bit(ISP_QUIESCE_NEEDED,
6090 &base_vha->dpc_flags);
6091 qla2x00_quiesce_io(base_vha);
579d12b5 6092 }
7c3df132
SK		 6093 ql_dbg(ql_dbg_dpc, base_vha, 0x400a,
6094 "Quiescence mode end.\n");
579d12b5
SK		 6095 }
6096
e315cd28 6097 if (test_and_clear_bit(RESET_MARKER_NEEDED,
8ae6d9c7 6098 &base_vha->dpc_flags) &&
e315cd28 6099 (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) {
1da177e4 6100
7c3df132
SK		 6101 ql_dbg(ql_dbg_dpc, base_vha, 0x400b,
6102 "Reset marker scheduled.\n");
e315cd28
AC		 6103 qla2x00_rst_aen(base_vha);
6104 clear_bit(RESET_ACTIVE, &base_vha->dpc_flags);
7c3df132
SK		 6105 ql_dbg(ql_dbg_dpc, base_vha, 0x400c,
6106 "Reset marker end.\n");
1da177e4
LT		 6107 }
6108
6109 /* Retry each device up to login retry count */
4005a995 6110 if (test_bit(RELOGIN_NEEDED, &base_vha->dpc_flags) &&
e315cd28
AC		 6111 !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) &&
6112 atomic_read(&base_vha->loop_state) != LOOP_DOWN) {
1da177e4 6113
4005a995
QT		 6114 if (!base_vha->relogin_jif ||
6115 time_after_eq(jiffies, base_vha->relogin_jif)) {
6116 base_vha->relogin_jif = jiffies + HZ;
6117 clear_bit(RELOGIN_NEEDED, &base_vha->dpc_flags);
6118
9b3e0f4d 6119 ql_dbg(ql_dbg_disc, base_vha, 0x400d,
4005a995 6120 "Relogin scheduled.\n");
9b3e0f4d 6121 qla24xx_post_relogin_work(base_vha);
4005a995 6122 }
1da177e4 6123 }
8ae6d9c7 6124loop_resync_check:
e315cd28 6125 if (test_and_clear_bit(LOOP_RESYNC_NEEDED,
8ae6d9c7 6126 &base_vha->dpc_flags)) {
1da177e4 6127
7c3df132
SK		 6128 ql_dbg(ql_dbg_dpc, base_vha, 0x400f,
6129 "Loop resync scheduled.\n");
1da177e4
LT		 6130
6131 if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE,
e315cd28 6132 &base_vha->dpc_flags))) {
1da177e4 6133
52c82823 6134 qla2x00_loop_resync(base_vha);
1da177e4 6135
e315cd28
AC		 6136 clear_bit(LOOP_RESYNC_ACTIVE,
6137 &base_vha->dpc_flags);
1da177e4
LT		 6138 }
6139
7c3df132
SK		 6140 ql_dbg(ql_dbg_dpc, base_vha, 0x4010,
6141 "Loop resync end.\n");
1da177e4
LT		 6142 }
6143
8ae6d9c7
GM		 6144 if (IS_QLAFX00(ha))
6145 goto intr_on_check;
6146
e315cd28
AC		 6147 if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) &&
6148 atomic_read(&base_vha->loop_state) == LOOP_READY) {
6149 clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags);
6150 qla2xxx_flash_npiv_conf(base_vha);
272976ca
AV		 6151 }
6152
8ae6d9c7 6153intr_on_check:
1da177e4 6154 if (!ha->interrupts_on)
fd34f556 6155 ha->isp_ops->enable_intrs(ha);
1da177e4 6156
e315cd28 6157 if (test_and_clear_bit(BEACON_BLINK_NEEDED,
90b604f2
HM		 6158 &base_vha->dpc_flags)) {
6159 if (ha->beacon_blink_led == 1)
6160 ha->isp_ops->beacon_blink(base_vha);
6161 }
f6df144c 6162
d7459527
MH		 6163 /* qpair online check */
6164 if (test_and_clear_bit(QPAIR_ONLINE_CHECK_NEEDED,
6165 &base_vha->dpc_flags)) {
6166 if (ha->flags.eeh_busy ||
6167 ha->flags.pci_channel_io_perm_failure)
6168 online = 0;
6169 else
6170 online = 1;
6171
6172 mutex_lock(&ha->mq_lock);
6173 list_for_each_entry(qpair, &base_vha->qp_list,
6174 qp_list_elem)
6175 qpair->online = online;
6176 mutex_unlock(&ha->mq_lock);
6177 }
6178
deeae7a6
DG		 6179 if (test_and_clear_bit(SET_ZIO_THRESHOLD_NEEDED, &base_vha->dpc_flags)) {
6180 ql_log(ql_log_info, base_vha, 0xffffff,
6181 "nvme: SET ZIO Activity exchange threshold to %d.\n",
6182 ha->nvme_last_rptd_aen);
6183 if (qla27xx_set_zio_threshold(base_vha, ha->nvme_last_rptd_aen)) {
6184 ql_log(ql_log_info, base_vha, 0xffffff,
6185 "nvme: Unable to SET ZIO Activity exchange threshold to %d.\n",
6186 ha->nvme_last_rptd_aen);
6187 }
6188 }
6189
8ae6d9c7
GM		 6190 if (!IS_QLAFX00(ha))
6191 qla2x00_do_dpc_all_vps(base_vha);
2c3dfe3f 6192
48acad09
QT		 6193 if (test_and_clear_bit(N2N_LINK_RESET,
6194 &base_vha->dpc_flags)) {
6195 qla2x00_lip_reset(base_vha);
6196 }
6197
1da177e4 6198 ha->dpc_active = 0;
c142caf0 6199end_loop:
563585ec 6200 set_current_state(TASK_INTERRUPTIBLE);
1da177e4 6201 } /* End of while(1) */
563585ec 6202 __set_current_state(TASK_RUNNING);
1da177e4 6203
7c3df132
SK		 6204 ql_dbg(ql_dbg_dpc, base_vha, 0x4011,
6205 "DPC handler exiting.\n");
1da177e4
LT		 6206
6207 /*
6208 * Make sure that nobody tries to wake us up again.
6209 */
1da177e4
LT		 6210 ha->dpc_active = 0;
6211
ac280b67
AV		 6212 /* Cleanup any residual CTX SRBs. */
6213 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
6214
39a11240
CH		 6215 return 0;
6216}
6217
6218void
e315cd28 6219qla2xxx_wake_dpc(struct scsi_qla_host *vha)
39a11240 6220{
e315cd28 6221 struct qla_hw_data *ha = vha->hw;
c795c1e4
AV		 6222 struct task_struct *t = ha->dpc_thread;
6223
e315cd28 6224 if (!test_bit(UNLOADING, &vha->dpc_flags) && t)
c795c1e4 6225 wake_up_process(t);
1da177e4
LT		 6226}
6227
1da177e4
LT		 6228/*
6229* qla2x00_rst_aen
6230* Processes asynchronous reset.
6231*
6232* Input:
6233* ha = adapter block pointer.
6234*/
6235static void
e315cd28 6236qla2x00_rst_aen(scsi_qla_host_t *vha)
1da177e4 6237{
e315cd28
AC		 6238 if (vha->flags.online && !vha->flags.reset_active &&
6239 !atomic_read(&vha->loop_down_timer) &&
6240 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) {
1da177e4 6241 do {
e315cd28 6242 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
1da177e4
LT		 6243
6244 /*
6245 * Issue marker command only when we are going to start
6246 * the I/O.
6247 */
e315cd28
AC		 6248 vha->marker_needed = 1;
6249 } while (!atomic_read(&vha->loop_down_timer) &&
6250 (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)));
1da177e4
LT		 6251 }
6252}
6253
1da177e4
LT		 6254/**************************************************************************
6255* qla2x00_timer
6256*
6257* Description:
6258* One second timer
6259*
6260* Context: Interrupt
6261***************************************************************************/
2c3dfe3f 6262void
8e5f4ba0 6263qla2x00_timer(struct timer_list *t)
1da177e4 6264{
8e5f4ba0 6265 scsi_qla_host_t *vha = from_timer(vha, t, timer);
1da177e4 6266 unsigned long cpu_flags = 0;
1da177e4
LT		 6267 int start_dpc = 0;
6268 int index;
6269 srb_t *sp;
85880801 6270 uint16_t w;
e315cd28 6271 struct qla_hw_data *ha = vha->hw;
73208dfd 6272 struct req_que *req;
85880801 6273
a5b36321 6274 if (ha->flags.eeh_busy) {
7c3df132
SK		 6275 ql_dbg(ql_dbg_timer, vha, 0x6000,
6276 "EEH = %d, restarting timer.\n",
6277 ha->flags.eeh_busy);
a5b36321
LC		 6278 qla2x00_restart_timer(vha, WATCH_INTERVAL);
6279 return;
6280 }
6281
f3ddac19
CD		 6282 /*
6283 * Hardware read to raise pending EEH errors during mailbox waits. If
6284 * the read returns -1 then disable the board.
6285 */
6286 if (!pci_channel_offline(ha->pdev)) {
85880801 6287 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w);
c821e0d5 6288 qla2x00_check_reg16_for_disconnect(vha, w);
f3ddac19 6289 }
1da177e4 6290
cefcaba6 6291 /* Make sure qla82xx_watchdog is run only for physical port */
7ec0effd 6292 if (!vha->vp_idx && IS_P3P_TYPE(ha)) {
579d12b5
SK		 6293 if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags))
6294 start_dpc++;
7ec0effd
AD		 6295 if (IS_QLA82XX(ha))
6296 qla82xx_watchdog(vha);
6297 else if (IS_QLA8044(ha))
6298 qla8044_watchdog(vha);
579d12b5
SK		 6299 }
6300
8ae6d9c7
GM		 6301 if (!vha->vp_idx && IS_QLAFX00(ha))
6302 qlafx00_timer_routine(vha);
6303
1da177e4 6304 /* Loop down handler. */
e315cd28 6305 if (atomic_read(&vha->loop_down_timer) > 0 &&
8f7daead
GM		 6306 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) &&
6307 !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags))
e315cd28 6308 && vha->flags.online) {
1da177e4 6309
e315cd28
AC		 6310 if (atomic_read(&vha->loop_down_timer) ==
6311 vha->loop_down_abort_time) {
1da177e4 6312
7c3df132
SK		 6313 ql_log(ql_log_info, vha, 0x6008,
6314 "Loop down - aborting the queues before time expires.\n");
1da177e4 6315
e315cd28
AC		 6316 if (!IS_QLA2100(ha) && vha->link_down_timeout)
6317 atomic_set(&vha->loop_state, LOOP_DEAD);
1da177e4 6318
f08b7251
AV		 6319 /*
6320 * Schedule an ISP abort to return any FCP2-device
6321 * commands.
6322 */
2c3dfe3f 6323 /* NPIV - scan physical port only */
e315cd28 6324 if (!vha->vp_idx) {
2c3dfe3f
SJ		 6325 spin_lock_irqsave(&ha->hardware_lock,
6326 cpu_flags);
73208dfd 6327 req = ha->req_q_map[0];
2c3dfe3f 6328 for (index = 1;
8d93f550 6329 index < req->num_outstanding_cmds;
2c3dfe3f
SJ		 6330 index++) {
6331 fc_port_t *sfcp;
6332
e315cd28 6333 sp = req->outstanding_cmds[index];
2c3dfe3f
SJ		 6334 if (!sp)
6335 continue;
c5419e26
QT		 6336 if (sp->cmd_type != TYPE_SRB)
6337 continue;
9ba56b95 6338 if (sp->type != SRB_SCSI_CMD)
cf53b069 6339 continue;
2c3dfe3f 6340 sfcp = sp->fcport;
f08b7251 6341 if (!(sfcp->flags & FCF_FCP2_DEVICE))
2c3dfe3f 6342 continue;
bdf79621 6343
8f7daead
GM		 6344 if (IS_QLA82XX(ha))
6345 set_bit(FCOE_CTX_RESET_NEEDED,
6346 &vha->dpc_flags);
6347 else
6348 set_bit(ISP_ABORT_NEEDED,
e315cd28 6349 &vha->dpc_flags);
2c3dfe3f
SJ		 6350 break;
6351 }
6352 spin_unlock_irqrestore(&ha->hardware_lock,
e315cd28 6353 cpu_flags);
1da177e4 6354 }
1da177e4
LT		 6355 start_dpc++;
6356 }
6357
6358 /* if the loop has been down for 4 minutes, reinit adapter */
e315cd28 6359 if (atomic_dec_and_test(&vha->loop_down_timer) != 0) {
0d6e61bc 6360 if (!(vha->device_flags & DFLG_NO_CABLE)) {
7c3df132 6361 ql_log(ql_log_warn, vha, 0x6009,
1da177e4
LT		 6362 "Loop down - aborting ISP.\n");
6363
8f7daead
GM		 6364 if (IS_QLA82XX(ha))
6365 set_bit(FCOE_CTX_RESET_NEEDED,
6366 &vha->dpc_flags);
6367 else
6368 set_bit(ISP_ABORT_NEEDED,
6369 &vha->dpc_flags);
1da177e4
LT		 6370 }
6371 }
7c3df132
SK		 6372 ql_dbg(ql_dbg_timer, vha, 0x600a,
6373 "Loop down - seconds remaining %d.\n",
6374 atomic_read(&vha->loop_down_timer));
1da177e4 6375 }
cefcaba6
SK		 6376 /* Check if beacon LED needs to be blinked for physical host only */
6377 if (!vha->vp_idx && (ha->beacon_blink_led == 1)) {
999916dc 6378 /* There is no beacon_blink function for ISP82xx */
7ec0effd 6379 if (!IS_P3P_TYPE(ha)) {
999916dc
SK		 6380 set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags);
6381 start_dpc++;
6382 }
f6df144c 6383 }
6384
550bf57d 6385 /* Process any deferred work. */
9b3e0f4d
QT		 6386 if (!list_empty(&vha->work_list)) {
6387 unsigned long flags;
6388 bool q = false;
6389
6390 spin_lock_irqsave(&vha->work_lock, flags);
6391 if (!test_and_set_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags))
6392 q = true;
6393 spin_unlock_irqrestore(&vha->work_lock, flags);
6394 if (q)
6395 queue_work(vha->hw->wq, &vha->iocb_work);
6396 }
550bf57d 6397
7401bc18
DG		 6398 /*
6399 * FC-NVME
6400 * see if the active AEN count has changed from what was last reported.
6401 */
deeae7a6
DG		 6402 if (!vha->vp_idx &&
6403 atomic_read(&ha->nvme_active_aen_cnt) != ha->nvme_last_rptd_aen &&
6404 ha->zio_mode == QLA_ZIO_MODE_6) {
7401bc18 6405 ql_log(ql_log_info, vha, 0x3002,
deeae7a6
DG		 6406 "nvme: Sched: Set ZIO exchange threshold to %d.\n",
6407 ha->nvme_last_rptd_aen);
6408 ha->nvme_last_rptd_aen = atomic_read(&ha->nvme_active_aen_cnt);
6409 set_bit(SET_ZIO_THRESHOLD_NEEDED, &vha->dpc_flags);
6410 start_dpc++;
7401bc18
DG		 6411 }
6412
1da177e4 6413 /* Schedule the DPC routine if needed */
e315cd28
AC		 6414 if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) ||
6415 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) ||
6416 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags) ||
1da177e4 6417 start_dpc ||
e315cd28
AC		 6418 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) ||
6419 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) ||
a9083016
GM		 6420 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) ||
6421 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) ||
e315cd28 6422 test_bit(VP_DPC_NEEDED, &vha->dpc_flags) ||
50280c01 6423 test_bit(RELOGIN_NEEDED, &vha->dpc_flags))) {
7c3df132
SK		 6424 ql_dbg(ql_dbg_timer, vha, 0x600b,
6425 "isp_abort_needed=%d loop_resync_needed=%d "
6426 "fcport_update_needed=%d start_dpc=%d "
6427 "reset_marker_needed=%d",
6428 test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags),
6429 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags),
6430 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags),
6431 start_dpc,
6432 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags));
6433 ql_dbg(ql_dbg_timer, vha, 0x600c,
6434 "beacon_blink_needed=%d isp_unrecoverable=%d "
6435 "fcoe_ctx_reset_needed=%d vp_dpc_needed=%d "
50280c01 6436 "relogin_needed=%d.\n",
7c3df132
SK		 6437 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags),
6438 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags),
6439 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags),
6440 test_bit(VP_DPC_NEEDED, &vha->dpc_flags),
50280c01 6441 test_bit(RELOGIN_NEEDED, &vha->dpc_flags));
e315cd28 6442 qla2xxx_wake_dpc(vha);
7c3df132 6443 }
1da177e4 6444
e315cd28 6445 qla2x00_restart_timer(vha, WATCH_INTERVAL);
1da177e4
LT		 6446}
6447
5433383e
AV		 6448/* Firmware interface routines. */
6449
f73cb695 6450#define FW_BLOBS 11
5433383e
AV		 6451#define FW_ISP21XX 0
6452#define FW_ISP22XX 1
6453#define FW_ISP2300 2
6454#define FW_ISP2322 3
48c02fde 6455#define FW_ISP24XX 4
c3a2f0df 6456#define FW_ISP25XX 5
3a03eb79 6457#define FW_ISP81XX 6
a9083016 6458#define FW_ISP82XX 7
6246b8a1
GM		 6459#define FW_ISP2031 8
6460#define FW_ISP8031 9
2c5bbbb2 6461#define FW_ISP27XX 10
5433383e 6462
bb8ee499
AV		 6463#define FW_FILE_ISP21XX "ql2100_fw.bin"
6464#define FW_FILE_ISP22XX "ql2200_fw.bin"
6465#define FW_FILE_ISP2300 "ql2300_fw.bin"
6466#define FW_FILE_ISP2322 "ql2322_fw.bin"
6467#define FW_FILE_ISP24XX "ql2400_fw.bin"
c3a2f0df 6468#define FW_FILE_ISP25XX "ql2500_fw.bin"
3a03eb79 6469#define FW_FILE_ISP81XX "ql8100_fw.bin"
a9083016 6470#define FW_FILE_ISP82XX "ql8200_fw.bin"
6246b8a1
GM		 6471#define FW_FILE_ISP2031 "ql2600_fw.bin"
6472#define FW_FILE_ISP8031 "ql8300_fw.bin"
2c5bbbb2 6473#define FW_FILE_ISP27XX "ql2700_fw.bin"
f73cb695 6474
bb8ee499 6475
e1e82b6f 6476static DEFINE_MUTEX(qla_fw_lock);
5433383e
AV		 6477
6478static struct fw_blob qla_fw_blobs[FW_BLOBS] = {
bb8ee499
AV		 6479 { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, },
6480 { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, },
6481 { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, },
6482 { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, },
6483 { .name = FW_FILE_ISP24XX, },
c3a2f0df 6484 { .name = FW_FILE_ISP25XX, },
3a03eb79 6485 { .name = FW_FILE_ISP81XX, },
a9083016 6486 { .name = FW_FILE_ISP82XX, },
6246b8a1
GM		 6487 { .name = FW_FILE_ISP2031, },
6488 { .name = FW_FILE_ISP8031, },
2c5bbbb2 6489 { .name = FW_FILE_ISP27XX, },
5433383e
AV		 6490};
6491
6492struct fw_blob *
e315cd28 6493qla2x00_request_firmware(scsi_qla_host_t *vha)
5433383e 6494{
e315cd28 6495 struct qla_hw_data *ha = vha->hw;
5433383e
AV		 6496 struct fw_blob *blob;
6497
5433383e
AV		 6498 if (IS_QLA2100(ha)) {
6499 blob = &qla_fw_blobs[FW_ISP21XX];
6500 } else if (IS_QLA2200(ha)) {
6501 blob = &qla_fw_blobs[FW_ISP22XX];
48c02fde 6502 } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
5433383e 6503 blob = &qla_fw_blobs[FW_ISP2300];
48c02fde 6504 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
5433383e 6505 blob = &qla_fw_blobs[FW_ISP2322];
4d4df193 6506 } else if (IS_QLA24XX_TYPE(ha)) {
5433383e 6507 blob = &qla_fw_blobs[FW_ISP24XX];
c3a2f0df
AV		 6508 } else if (IS_QLA25XX(ha)) {
6509 blob = &qla_fw_blobs[FW_ISP25XX];
3a03eb79
AV		 6510 } else if (IS_QLA81XX(ha)) {
6511 blob = &qla_fw_blobs[FW_ISP81XX];
a9083016
GM		 6512 } else if (IS_QLA82XX(ha)) {
6513 blob = &qla_fw_blobs[FW_ISP82XX];
6246b8a1
GM		 6514 } else if (IS_QLA2031(ha)) {
6515 blob = &qla_fw_blobs[FW_ISP2031];
6516 } else if (IS_QLA8031(ha)) {
6517 blob = &qla_fw_blobs[FW_ISP8031];
2c5bbbb2
JC		 6518 } else if (IS_QLA27XX(ha)) {
6519 blob = &qla_fw_blobs[FW_ISP27XX];
8a655229
DC		 6520 } else {
6521 return NULL;
5433383e
AV		 6522 }
6523
e1e82b6f 6524 mutex_lock(&qla_fw_lock);
5433383e
AV		 6525 if (blob->fw)
6526 goto out;
6527
6528 if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) {
7c3df132
SK		 6529 ql_log(ql_log_warn, vha, 0x0063,
6530 "Failed to load firmware image (%s).\n", blob->name);
5433383e
AV		 6531 blob->fw = NULL;
6532 blob = NULL;
6533 goto out;
6534 }
6535
6536out:
e1e82b6f 6537 mutex_unlock(&qla_fw_lock);
5433383e
AV		 6538 return blob;
6539}
6540
6541static void
6542qla2x00_release_firmware(void)
6543{
6544 int idx;
6545
e1e82b6f 6546 mutex_lock(&qla_fw_lock);
5433383e 6547 for (idx = 0; idx < FW_BLOBS; idx++)
cf92549f 6548 release_firmware(qla_fw_blobs[idx].fw);
e1e82b6f 6549 mutex_unlock(&qla_fw_lock);
5433383e
AV		 6550}
6551
14e660e6
SJ		 6552static pci_ers_result_t
6553qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
6554{
85880801
AV		 6555 scsi_qla_host_t *vha = pci_get_drvdata(pdev);
6556 struct qla_hw_data *ha = vha->hw;
6557
7c3df132
SK		 6558 ql_dbg(ql_dbg_aer, vha, 0x9000,
6559 "PCI error detected, state %x.\n", state);
b9b12f73 6560
efdb5760
SC		 6561 if (!atomic_read(&pdev->enable_cnt)) {
6562 ql_log(ql_log_info, vha, 0xffff,
6563 "PCI device is disabled,state %x\n", state);
6564 return PCI_ERS_RESULT_NEED_RESET;
6565 }
6566
14e660e6
SJ		 6567 switch (state) {
6568 case pci_channel_io_normal:
85880801 6569 ha->flags.eeh_busy = 0;
c38d1baf 6570 if (ql2xmqsupport || ql2xnvmeenable) {
d7459527
MH		 6571 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags);
6572 qla2xxx_wake_dpc(vha);
6573 }
14e660e6
SJ		 6574 return PCI_ERS_RESULT_CAN_RECOVER;
6575 case pci_channel_io_frozen:
85880801 6576 ha->flags.eeh_busy = 1;
a5b36321
LC		 6577 /* For ISP82XX complete any pending mailbox cmd */
6578 if (IS_QLA82XX(ha)) {
7190575f 6579 ha->flags.isp82xx_fw_hung = 1;
c8f6544e
CD		 6580 ql_dbg(ql_dbg_aer, vha, 0x9001, "Pci channel io frozen\n");
6581 qla82xx_clear_pending_mbx(vha);
a5b36321 6582 }
90a86fc0 6583 qla2x00_free_irqs(vha);
14e660e6 6584 pci_disable_device(pdev);
bddd2d65
LC		 6585 /* Return back all IOs */
6586 qla2x00_abort_all_cmds(vha, DID_RESET << 16);
c38d1baf 6587 if (ql2xmqsupport || ql2xnvmeenable) {
d7459527
MH		 6588 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags);
6589 qla2xxx_wake_dpc(vha);
6590 }
14e660e6
SJ		 6591 return PCI_ERS_RESULT_NEED_RESET;
6592 case pci_channel_io_perm_failure:
85880801
AV		 6593 ha->flags.pci_channel_io_perm_failure = 1;
6594 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
c38d1baf 6595 if (ql2xmqsupport || ql2xnvmeenable) {
d7459527
MH		 6596 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags);
6597 qla2xxx_wake_dpc(vha);
6598 }
14e660e6
SJ		 6599 return PCI_ERS_RESULT_DISCONNECT;
6600 }
6601 return PCI_ERS_RESULT_NEED_RESET;
6602}
6603
6604static pci_ers_result_t
6605qla2xxx_pci_mmio_enabled(struct pci_dev *pdev)
6606{
6607 int risc_paused = 0;
6608 uint32_t stat;
6609 unsigned long flags;
e315cd28
AC		 6610 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
6611 struct qla_hw_data *ha = base_vha->hw;
14e660e6
SJ		 6612 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
6613 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
6614
bcc5b6d3
SK		 6615 if (IS_QLA82XX(ha))
6616 return PCI_ERS_RESULT_RECOVERED;
6617
14e660e6
SJ		 6618 spin_lock_irqsave(&ha->hardware_lock, flags);
6619 if (IS_QLA2100(ha) || IS_QLA2200(ha)){
6620 stat = RD_REG_DWORD(&reg->hccr);
6621 if (stat & HCCR_RISC_PAUSE)
6622 risc_paused = 1;
6623 } else if (IS_QLA23XX(ha)) {
6624 stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
6625 if (stat & HSR_RISC_PAUSED)
6626 risc_paused = 1;
6627 } else if (IS_FWI2_CAPABLE(ha)) {
6628 stat = RD_REG_DWORD(&reg24->host_status);
6629 if (stat & HSRX_RISC_PAUSED)
6630 risc_paused = 1;
6631 }
6632 spin_unlock_irqrestore(&ha->hardware_lock, flags);
6633
6634 if (risc_paused) {
7c3df132
SK		 6635 ql_log(ql_log_info, base_vha, 0x9003,
6636 "RISC paused -- mmio_enabled, Dumping firmware.\n");
e315cd28 6637 ha->isp_ops->fw_dump(base_vha, 0);
14e660e6
SJ		 6638
6639 return PCI_ERS_RESULT_NEED_RESET;
6640 } else
6641 return PCI_ERS_RESULT_RECOVERED;
6642}
6643
fa492630
SK		 6644static uint32_t
6645qla82xx_error_recovery(scsi_qla_host_t *base_vha)
a5b36321
LC		 6646{
6647 uint32_t rval = QLA_FUNCTION_FAILED;
6648 uint32_t drv_active = 0;
6649 struct qla_hw_data *ha = base_vha->hw;
6650 int fn;
6651 struct pci_dev *other_pdev = NULL;
6652
7c3df132
SK		 6653 ql_dbg(ql_dbg_aer, base_vha, 0x9006,
6654 "Entered %s.\n", __func__);
a5b36321
LC		 6655
6656 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
6657
6658 if (base_vha->flags.online) {
6659 /* Abort all outstanding commands,
6660 * so as to be requeued later */
6661 qla2x00_abort_isp_cleanup(base_vha);
6662 }
6663
6664
6665 fn = PCI_FUNC(ha->pdev->devfn);
6666 while (fn > 0) {
6667 fn--;
7c3df132
SK		 6668 ql_dbg(ql_dbg_aer, base_vha, 0x9007,
6669 "Finding pci device at function = 0x%x.\n", fn);
a5b36321
LC		 6670 other_pdev =
6671 pci_get_domain_bus_and_slot(pci_domain_nr(ha->pdev->bus),
6672 ha->pdev->bus->number, PCI_DEVFN(PCI_SLOT(ha->pdev->devfn),
6673 fn));
6674
6675 if (!other_pdev)
6676 continue;
6677 if (atomic_read(&other_pdev->enable_cnt)) {
7c3df132
SK		 6678 ql_dbg(ql_dbg_aer, base_vha, 0x9008,
6679 "Found PCI func available and enable at 0x%x.\n",
6680 fn);
a5b36321
LC		 6681 pci_dev_put(other_pdev);
6682 break;
6683 }
6684 pci_dev_put(other_pdev);
6685 }
6686
6687 if (!fn) {
6688 /* Reset owner */
7c3df132
SK		 6689 ql_dbg(ql_dbg_aer, base_vha, 0x9009,
6690 "This devfn is reset owner = 0x%x.\n",
6691 ha->pdev->devfn);
a5b36321
LC		 6692 qla82xx_idc_lock(ha);
6693
6694 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 6695 QLA8XXX_DEV_INITIALIZING);
a5b36321
LC		 6696
6697 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION,
6698 QLA82XX_IDC_VERSION);
6699
6700 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
7c3df132
SK		 6701 ql_dbg(ql_dbg_aer, base_vha, 0x900a,
6702 "drv_active = 0x%x.\n", drv_active);
a5b36321
LC		 6703
6704 qla82xx_idc_unlock(ha);
6705 /* Reset if device is not already reset
6706 * drv_active would be 0 if a reset has already been done
6707 */
6708 if (drv_active)
6709 rval = qla82xx_start_firmware(base_vha);
6710 else
6711 rval = QLA_SUCCESS;
6712 qla82xx_idc_lock(ha);
6713
6714 if (rval != QLA_SUCCESS) {
7c3df132
SK		 6715 ql_log(ql_log_info, base_vha, 0x900b,
6716 "HW State: FAILED.\n");
a5b36321
LC		 6717 qla82xx_clear_drv_active(ha);
6718 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 6719 QLA8XXX_DEV_FAILED);
a5b36321 6720 } else {
7c3df132
SK		 6721 ql_log(ql_log_info, base_vha, 0x900c,
6722 "HW State: READY.\n");
a5b36321 6723 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 6724 QLA8XXX_DEV_READY);
a5b36321 6725 qla82xx_idc_unlock(ha);
7190575f 6726 ha->flags.isp82xx_fw_hung = 0;
a5b36321
LC		 6727 rval = qla82xx_restart_isp(base_vha);
6728 qla82xx_idc_lock(ha);
6729 /* Clear driver state register */
6730 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, 0);
6731 qla82xx_set_drv_active(base_vha);
6732 }
6733 qla82xx_idc_unlock(ha);
6734 } else {
7c3df132
SK		 6735 ql_dbg(ql_dbg_aer, base_vha, 0x900d,
6736 "This devfn is not reset owner = 0x%x.\n",
6737 ha->pdev->devfn);
a5b36321 6738 if ((qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE) ==
7d613ac6 6739 QLA8XXX_DEV_READY)) {
7190575f 6740 ha->flags.isp82xx_fw_hung = 0;
a5b36321
LC		 6741 rval = qla82xx_restart_isp(base_vha);
6742 qla82xx_idc_lock(ha);
6743 qla82xx_set_drv_active(base_vha);
6744 qla82xx_idc_unlock(ha);
6745 }
6746 }
6747 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
6748
6749 return rval;
6750}
6751
14e660e6
SJ		 6752static pci_ers_result_t
6753qla2xxx_pci_slot_reset(struct pci_dev *pdev)
6754{
6755 pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT;
e315cd28
AC		 6756 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
6757 struct qla_hw_data *ha = base_vha->hw;
90a86fc0
JC		 6758 struct rsp_que *rsp;
6759 int rc, retries = 10;
09483916 6760
7c3df132
SK		 6761 ql_dbg(ql_dbg_aer, base_vha, 0x9004,
6762 "Slot Reset.\n");
85880801 6763
90a86fc0
JC		 6764 /* Workaround: qla2xxx driver which access hardware earlier
6765 * needs error state to be pci_channel_io_online.
6766 * Otherwise mailbox command timesout.
6767 */
6768 pdev->error_state = pci_channel_io_normal;
6769
6770 pci_restore_state(pdev);
6771
8c1496bd
RL		 6772 /* pci_restore_state() clears the saved_state flag of the device
6773 * save restored state which resets saved_state flag
6774 */
6775 pci_save_state(pdev);
6776
09483916
BH		 6777 if (ha->mem_only)
6778 rc = pci_enable_device_mem(pdev);
6779 else
6780 rc = pci_enable_device(pdev);
14e660e6 6781
09483916 6782 if (rc) {
7c3df132 6783 ql_log(ql_log_warn, base_vha, 0x9005,
14e660e6 6784 "Can't re-enable PCI device after reset.\n");
a5b36321 6785 goto exit_slot_reset;
14e660e6 6786 }
14e660e6 6787
90a86fc0
JC		 6788 rsp = ha->rsp_q_map[0];
6789 if (qla2x00_request_irqs(ha, rsp))
a5b36321 6790 goto exit_slot_reset;
90a86fc0 6791
e315cd28 6792 if (ha->isp_ops->pci_config(base_vha))
a5b36321
LC		 6793 goto exit_slot_reset;
6794
6795 if (IS_QLA82XX(ha)) {
6796 if (qla82xx_error_recovery(base_vha) == QLA_SUCCESS) {
6797 ret = PCI_ERS_RESULT_RECOVERED;
6798 goto exit_slot_reset;
6799 } else
6800 goto exit_slot_reset;
6801 }
14e660e6 6802
90a86fc0
JC		 6803 while (ha->flags.mbox_busy && retries--)
6804 msleep(1000);
85880801 6805
e315cd28 6806 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
a9083016 6807 if (ha->isp_ops->abort_isp(base_vha) == QLA_SUCCESS)
14e660e6 6808 ret = PCI_ERS_RESULT_RECOVERED;
e315cd28 6809 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
14e660e6 6810
90a86fc0 6811
a5b36321 6812exit_slot_reset:
7c3df132
SK		 6813 ql_dbg(ql_dbg_aer, base_vha, 0x900e,
6814 "slot_reset return %x.\n", ret);
85880801 6815
14e660e6
SJ		 6816 return ret;
6817}
6818
6819static void
6820qla2xxx_pci_resume(struct pci_dev *pdev)
6821{
e315cd28
AC		 6822 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
6823 struct qla_hw_data *ha = base_vha->hw;
14e660e6
SJ		 6824 int ret;
6825
7c3df132
SK		 6826 ql_dbg(ql_dbg_aer, base_vha, 0x900f,
6827 "pci_resume.\n");
85880801 6828
e315cd28 6829 ret = qla2x00_wait_for_hba_online(base_vha);
14e660e6 6830 if (ret != QLA_SUCCESS) {
7c3df132
SK		 6831 ql_log(ql_log_fatal, base_vha, 0x9002,
6832 "The device failed to resume I/O from slot/link_reset.\n");
14e660e6 6833 }
85880801 6834
3e46f031
LC		 6835 pci_cleanup_aer_uncorrect_error_status(pdev);
6836
85880801 6837 ha->flags.eeh_busy = 0;
14e660e6
SJ		 6838}
6839
5601236b
MH		 6840static int qla2xxx_map_queues(struct Scsi_Host *shost)
6841{
d68b850e 6842 int rc;
5601236b
MH		 6843 scsi_qla_host_t *vha = (scsi_qla_host_t *)shost->hostdata;
6844
d68b850e
QT		 6845 if (USER_CTRL_IRQ(vha->hw))
6846 rc = blk_mq_map_queues(&shost->tag_set);
6847 else
f23f5bec 6848 rc = blk_mq_pci_map_queues(&shost->tag_set, vha->hw->pdev, 0);
d68b850e 6849 return rc;
5601236b
MH		 6850}
6851
a55b2d21 6852static const struct pci_error_handlers qla2xxx_err_handler = {
14e660e6
SJ		 6853 .error_detected = qla2xxx_pci_error_detected,
6854 .mmio_enabled = qla2xxx_pci_mmio_enabled,
6855 .slot_reset = qla2xxx_pci_slot_reset,
6856 .resume = qla2xxx_pci_resume,
6857};
6858
5433383e 6859static struct pci_device_id qla2xxx_pci_tbl[] = {
47f5e069
AV		 6860 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) },
6861 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) },
6862 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) },
6863 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) },
6864 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) },
6865 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) },
6866 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) },
6867 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) },
6868 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) },
4d4df193 6869 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) },
47f5e069
AV		 6870 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) },
6871 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) },
c3a2f0df 6872 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) },
6246b8a1 6873 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2031) },
3a03eb79 6874 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) },
a9083016 6875 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) },
650f528f 6876 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8031) },
8ae6d9c7 6877 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISPF001) },
7ec0effd 6878 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8044) },
f73cb695 6879 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2071) },
2c5bbbb2 6880 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2271) },
2b48992f 6881 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2261) },
5433383e
AV		 6882 { 0 },
6883};
6884MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl);
6885
fca29703 6886static struct pci_driver qla2xxx_pci_driver = {
cb63067a 6887 .name = QLA2XXX_DRIVER_NAME,
0a21ef1e
JB		 6888 .driver = {
6889 .owner = THIS_MODULE,
6890 },
fca29703 6891 .id_table = qla2xxx_pci_tbl,
7ee61397 6892 .probe = qla2x00_probe_one,
4c993f76 6893 .remove = qla2x00_remove_one,
e30d1756 6894 .shutdown = qla2x00_shutdown,
14e660e6 6895 .err_handler = &qla2xxx_err_handler,
fca29703
AV		 6896};
6897
75ef9de1 6898static const struct file_operations apidev_fops = {
6a03b4cd 6899 .owner = THIS_MODULE,
6038f373 6900 .llseek = noop_llseek,
6a03b4cd
HZ		 6901};
6902
1da177e4
LT		 6903/**
6904 * qla2x00_module_init - Module initialization.
6905 **/
6906static int __init
6907qla2x00_module_init(void)
6908{
fca29703
AV		 6909 int ret = 0;
6910
1da177e4 6911 /* Allocate cache for SRBs. */
354d6b21 6912 srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0,
20c2df83 6913 SLAB_HWCACHE_ALIGN, NULL);
1da177e4 6914 if (srb_cachep == NULL) {
7c3df132
SK		 6915 ql_log(ql_log_fatal, NULL, 0x0001,
6916 "Unable to allocate SRB cache...Failing load!.\n");
1da177e4
LT		 6917 return -ENOMEM;
6918 }
6919
2d70c103
NB		 6920 /* Initialize target kmem_cache and mem_pools */
6921 ret = qlt_init();
6922 if (ret < 0) {
6923 kmem_cache_destroy(srb_cachep);
6924 return ret;
6925 } else if (ret > 0) {
6926 /*
6927 * If initiator mode is explictly disabled by qlt_init(),
6928 * prevent scsi_transport_fc.c:fc_scsi_scan_rport() from
6929 * performing scsi_scan_target() during LOOP UP event.
6930 */
6931 qla2xxx_transport_functions.disable_target_scan = 1;
6932 qla2xxx_transport_vport_functions.disable_target_scan = 1;
6933 }
6934
1da177e4
LT		 6935 /* Derive version string. */
6936 strcpy(qla2x00_version_str, QLA2XXX_VERSION);
11010fec 6937 if (ql2xextended_error_logging)
0181944f 6938 strcat(qla2x00_version_str, "-debug");
fed0f68a
JC		 6939 if (ql2xextended_error_logging == 1)
6940 ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK;
0181944f 6941
1c97a12a
AV		 6942 qla2xxx_transport_template =
6943 fc_attach_transport(&qla2xxx_transport_functions);
2c3dfe3f
SJ		 6944 if (!qla2xxx_transport_template) {
6945 kmem_cache_destroy(srb_cachep);
7c3df132
SK		 6946 ql_log(ql_log_fatal, NULL, 0x0002,
6947 "fc_attach_transport failed...Failing load!.\n");
2d70c103 6948 qlt_exit();
1da177e4 6949 return -ENODEV;
2c3dfe3f 6950 }
6a03b4cd
HZ		 6951
6952 apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops);
6953 if (apidev_major < 0) {
7c3df132
SK		 6954 ql_log(ql_log_fatal, NULL, 0x0003,
6955 "Unable to register char device %s.\n", QLA2XXX_APIDEV);
6a03b4cd
HZ		 6956 }
6957
2c3dfe3f
SJ		 6958 qla2xxx_transport_vport_template =
6959 fc_attach_transport(&qla2xxx_transport_vport_functions);
6960 if (!qla2xxx_transport_vport_template) {
6961 kmem_cache_destroy(srb_cachep);
2d70c103 6962 qlt_exit();
2c3dfe3f 6963 fc_release_transport(qla2xxx_transport_template);
7c3df132
SK		 6964 ql_log(ql_log_fatal, NULL, 0x0004,
6965 "fc_attach_transport vport failed...Failing load!.\n");
1da177e4 6966 return -ENODEV;
2c3dfe3f 6967 }
7c3df132
SK		 6968 ql_log(ql_log_info, NULL, 0x0005,
6969 "QLogic Fibre Channel HBA Driver: %s.\n",
fd9a29f0 6970 qla2x00_version_str);
7ee61397 6971 ret = pci_register_driver(&qla2xxx_pci_driver);
fca29703
AV		 6972 if (ret) {
6973 kmem_cache_destroy(srb_cachep);
2d70c103 6974 qlt_exit();
fca29703 6975 fc_release_transport(qla2xxx_transport_template);
2c3dfe3f 6976 fc_release_transport(qla2xxx_transport_vport_template);
7c3df132
SK		 6977 ql_log(ql_log_fatal, NULL, 0x0006,
6978 "pci_register_driver failed...ret=%d Failing load!.\n",
6979 ret);
fca29703
AV		 6980 }
6981 return ret;
1da177e4
LT		 6982}
6983
6984/**
6985 * qla2x00_module_exit - Module cleanup.
6986 **/
6987static void __exit
6988qla2x00_module_exit(void)
6989{
6a03b4cd 6990 unregister_chrdev(apidev_major, QLA2XXX_APIDEV);
7ee61397 6991 pci_unregister_driver(&qla2xxx_pci_driver);
5433383e 6992 qla2x00_release_firmware();
354d6b21 6993 kmem_cache_destroy(srb_cachep);
2d70c103 6994 qlt_exit();
a9083016
GM		 6995 if (ctx_cachep)
6996 kmem_cache_destroy(ctx_cachep);
1da177e4 6997 fc_release_transport(qla2xxx_transport_template);
2c3dfe3f 6998 fc_release_transport(qla2xxx_transport_vport_template);
1da177e4
LT		 6999}
7000
7001module_init(qla2x00_module_init);
7002module_exit(qla2x00_module_exit);
7003
7004MODULE_AUTHOR("QLogic Corporation");
7005MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver");
7006MODULE_LICENSE("GPL");
7007MODULE_VERSION(QLA2XXX_VERSION);
bb8ee499
AV		 7008MODULE_FIRMWARE(FW_FILE_ISP21XX);
7009MODULE_FIRMWARE(FW_FILE_ISP22XX);
7010MODULE_FIRMWARE(FW_FILE_ISP2300);
7011MODULE_FIRMWARE(FW_FILE_ISP2322);
7012MODULE_FIRMWARE(FW_FILE_ISP24XX);
61623fc3 7013MODULE_FIRMWARE(FW_FILE_ISP25XX);
Linux 6.x block layer and io_uring tree(s)