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[SCSI] qla2xxx: Prevent CPU lockups when "ql2xdontresethba" module param is set.
[linux-2.6-block.git] / drivers / scsi / qla2xxx / qla_os.c
CommitLineData
1da177e4 1/*
fa90c54f 2 * QLogic Fibre Channel HBA Driver
07e264b7 3 * Copyright (c) 2003-2011 QLogic Corporation
1da177e4 4 *
fa90c54f 5 * See LICENSE.qla2xxx for copyright and licensing details.
1da177e4
LT		 6 */
7#include "qla_def.h"
8
9#include <linux/moduleparam.h>
10#include <linux/vmalloc.h>
1da177e4 11#include <linux/delay.h>
39a11240 12#include <linux/kthread.h>
e1e82b6f 13#include <linux/mutex.h>
3420d36c 14#include <linux/kobject.h>
5a0e3ad6 15#include <linux/slab.h>
1da177e4
LT		 16
17#include <scsi/scsi_tcq.h>
18#include <scsi/scsicam.h>
19#include <scsi/scsi_transport.h>
20#include <scsi/scsi_transport_fc.h>
21
22/*
23 * Driver version
24 */
25char qla2x00_version_str[40];
26
6a03b4cd
HZ		 27static int apidev_major;
28
1da177e4
LT		 29/*
30 * SRB allocation cache
31 */
e18b890b 32static struct kmem_cache *srb_cachep;
1da177e4 33
a9083016
GM		 34/*
35 * CT6 CTX allocation cache
36 */
37static struct kmem_cache *ctx_cachep;
3ce8866c
SK		 38/*
39 * error level for logging
40 */
41int ql_errlev = ql_log_all;
a9083016 42
1da177e4 43int ql2xlogintimeout = 20;
f2019cb1 44module_param(ql2xlogintimeout, int, S_IRUGO);
1da177e4
LT		 45MODULE_PARM_DESC(ql2xlogintimeout,
46 "Login timeout value in seconds.");
47
a7b61842 48int qlport_down_retry;
f2019cb1 49module_param(qlport_down_retry, int, S_IRUGO);
1da177e4 50MODULE_PARM_DESC(qlport_down_retry,
900d9f98 51 "Maximum number of command retries to a port that returns "
1da177e4
LT		 52 "a PORT-DOWN status.");
53
1da177e4
LT		 54int ql2xplogiabsentdevice;
55module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR);
56MODULE_PARM_DESC(ql2xplogiabsentdevice,
57 "Option to enable PLOGI to devices that are not present after "
900d9f98 58 "a Fabric scan. This is needed for several broken switches. "
1da177e4
LT		 59 "Default is 0 - no PLOGI. 1 - perfom PLOGI.");
60
1da177e4 61int ql2xloginretrycount = 0;
f2019cb1 62module_param(ql2xloginretrycount, int, S_IRUGO);
1da177e4
LT		 63MODULE_PARM_DESC(ql2xloginretrycount,
64 "Specify an alternate value for the NVRAM login retry count.");
65
a7a167bf 66int ql2xallocfwdump = 1;
f2019cb1 67module_param(ql2xallocfwdump, int, S_IRUGO);
a7a167bf
AV		 68MODULE_PARM_DESC(ql2xallocfwdump,
69 "Option to enable allocation of memory for a firmware dump "
70 "during HBA initialization. Memory allocation requirements "
71 "vary by ISP type. Default is 1 - allocate memory.");
72
11010fec 73int ql2xextended_error_logging;
27d94035 74module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
11010fec 75MODULE_PARM_DESC(ql2xextended_error_logging,
3ce8866c
SK		 76 "Option to enable extended error logging,\n"
77 "\t\tDefault is 0 - no logging. 0x40000000 - Module Init & Probe.\n"
78 "\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n"
79 "\t\t0x08000000 - IO tracing. 0x04000000 - DPC Thread.\n"
80 "\t\t0x02000000 - Async events. 0x01000000 - Timer routines.\n"
81 "\t\t0x00800000 - User space. 0x00400000 - Task Management.\n"
82 "\t\t0x00200000 - AER/EEH. 0x00100000 - Multi Q.\n"
83 "\t\t0x00080000 - P3P Specific. 0x00040000 - Virtual Port.\n"
84 "\t\t0x00020000 - Buffer Dump. 0x00010000 - Misc.\n"
85 "\t\t0x7fffffff - For enabling all logs, can be too many logs.\n"
86 "\t\tDo LOGICAL OR of the value to enable more than one level");
0181944f 87
a9083016 88int ql2xshiftctondsd = 6;
f2019cb1 89module_param(ql2xshiftctondsd, int, S_IRUGO);
a9083016
GM		 90MODULE_PARM_DESC(ql2xshiftctondsd,
91 "Set to control shifting of command type processing "
92 "based on total number of SG elements.");
93
1da177e4
LT		 94static void qla2x00_free_device(scsi_qla_host_t *);
95
7e47e5ca 96int ql2xfdmienable=1;
f2019cb1 97module_param(ql2xfdmienable, int, S_IRUGO);
cca5335c 98MODULE_PARM_DESC(ql2xfdmienable,
7794a5af
FW		 99 "Enables FDMI registrations. "
100 "0 - no FDMI. Default is 1 - perform FDMI.");
cca5335c 101
df7baa50
AV		 102#define MAX_Q_DEPTH 32
103static int ql2xmaxqdepth = MAX_Q_DEPTH;
104module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR);
105MODULE_PARM_DESC(ql2xmaxqdepth,
106 "Maximum queue depth to report for target devices.");
107
bad75002 108/* Do not change the value of this after module load */
8cb2049c 109int ql2xenabledif = 0;
bad75002
AE		 110module_param(ql2xenabledif, int, S_IRUGO|S_IWUSR);
111MODULE_PARM_DESC(ql2xenabledif,
112 " Enable T10-CRC-DIF "
8cb2049c
AE		 113 " Default is 0 - No DIF Support. 1 - Enable it"
114 ", 2 - Enable DIF for all types, except Type 0.");
bad75002 115
8cb2049c 116int ql2xenablehba_err_chk = 2;
bad75002
AE		 117module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR);
118MODULE_PARM_DESC(ql2xenablehba_err_chk,
8cb2049c
AE		 119 " Enable T10-CRC-DIF Error isolation by HBA:\n"
120 " Default is 1.\n"
121 " 0 -- Error isolation disabled\n"
122 " 1 -- Error isolation enabled only for DIX Type 0\n"
123 " 2 -- Error isolation enabled for all Types\n");
bad75002 124
e5896bd5 125int ql2xiidmaenable=1;
f2019cb1 126module_param(ql2xiidmaenable, int, S_IRUGO);
e5896bd5
AV		 127MODULE_PARM_DESC(ql2xiidmaenable,
128 "Enables iIDMA settings "
129 "Default is 1 - perform iIDMA. 0 - no iIDMA.");
130
73208dfd 131int ql2xmaxqueues = 1;
f2019cb1 132module_param(ql2xmaxqueues, int, S_IRUGO);
73208dfd
AC		 133MODULE_PARM_DESC(ql2xmaxqueues,
134 "Enables MQ settings "
ae68230c
JP		 135 "Default is 1 for single queue. Set it to number "
136 "of queues in MQ mode.");
68ca949c
AC		 137
138int ql2xmultique_tag;
f2019cb1 139module_param(ql2xmultique_tag, int, S_IRUGO);
68ca949c
AC		 140MODULE_PARM_DESC(ql2xmultique_tag,
141 "Enables CPU affinity settings for the driver "
142 "Default is 0 for no affinity of request and response IO. "
143 "Set it to 1 to turn on the cpu affinity.");
e337d907
AV		 144
145int ql2xfwloadbin;
f2019cb1 146module_param(ql2xfwloadbin, int, S_IRUGO);
e337d907 147MODULE_PARM_DESC(ql2xfwloadbin,
7c3df132
SK		 148 "Option to specify location from which to load ISP firmware:.\n"
149 " 2 -- load firmware via the request_firmware() (hotplug).\n"
e337d907
AV		 150 " interface.\n"
151 " 1 -- load firmware from flash.\n"
152 " 0 -- use default semantics.\n");
153
ae97c91e 154int ql2xetsenable;
f2019cb1 155module_param(ql2xetsenable, int, S_IRUGO);
ae97c91e
AV		 156MODULE_PARM_DESC(ql2xetsenable,
157 "Enables firmware ETS burst."
158 "Default is 0 - skip ETS enablement.");
159
6907869d 160int ql2xdbwr = 1;
f2019cb1 161module_param(ql2xdbwr, int, S_IRUGO);
a9083016 162MODULE_PARM_DESC(ql2xdbwr,
08de2844
GM		 163 "Option to specify scheme for request queue posting.\n"
164 " 0 -- Regular doorbell.\n"
165 " 1 -- CAMRAM doorbell (faster).\n");
a9083016 166
f4c496c1 167int ql2xtargetreset = 1;
f2019cb1 168module_param(ql2xtargetreset, int, S_IRUGO);
f4c496c1
GM		 169MODULE_PARM_DESC(ql2xtargetreset,
170 "Enable target reset."
171 "Default is 1 - use hw defaults.");
172
4da26e16 173int ql2xgffidenable;
f2019cb1 174module_param(ql2xgffidenable, int, S_IRUGO);
4da26e16
CD		 175MODULE_PARM_DESC(ql2xgffidenable,
176 "Enables GFF_ID checks of port type. "
177 "Default is 0 - Do not use GFF_ID information.");
a9083016 178
3822263e 179int ql2xasynctmfenable;
f2019cb1 180module_param(ql2xasynctmfenable, int, S_IRUGO);
3822263e
MI		 181MODULE_PARM_DESC(ql2xasynctmfenable,
182 "Enables issue of TM IOCBs asynchronously via IOCB mechanism"
183 "Default is 0 - Issue TM IOCBs via mailbox mechanism.");
ed0de87c
GM		 184
185int ql2xdontresethba;
186module_param(ql2xdontresethba, int, S_IRUGO);
187MODULE_PARM_DESC(ql2xdontresethba,
08de2844
GM		 188 "Option to specify reset behaviour.\n"
189 " 0 (Default) -- Reset on failure.\n"
190 " 1 -- Do not reset on failure.\n");
ed0de87c 191
82515920
AV		 192uint ql2xmaxlun = MAX_LUNS;
193module_param(ql2xmaxlun, uint, S_IRUGO);
194MODULE_PARM_DESC(ql2xmaxlun,
195 "Defines the maximum LU number to register with the SCSI "
196 "midlayer. Default is 65535.");
197
08de2844
GM		 198int ql2xmdcapmask = 0x1F;
199module_param(ql2xmdcapmask, int, S_IRUGO);
200MODULE_PARM_DESC(ql2xmdcapmask,
201 "Set the Minidump driver capture mask level. "
202 "Default is 0x7F - Can be set to 0x3, 0x7, 0xF, 0x1F, 0x7F.");
203
204int ql2xmdenable;
205module_param(ql2xmdenable, int, S_IRUGO);
206MODULE_PARM_DESC(ql2xmdenable,
207 "Enable/disable MiniDump. "
208 "0 (Default) - MiniDump disabled. "
209 "1 - MiniDump enabled.");
210
1da177e4 211/*
fa2a1ce5 212 * SCSI host template entry points
1da177e4
LT		 213 */
214static int qla2xxx_slave_configure(struct scsi_device * device);
f4f051eb 215static int qla2xxx_slave_alloc(struct scsi_device *);
1e99e33a
AV		 216static int qla2xxx_scan_finished(struct Scsi_Host *, unsigned long time);
217static void qla2xxx_scan_start(struct Scsi_Host *);
f4f051eb 218static void qla2xxx_slave_destroy(struct scsi_device *);
f281233d 219static int qla2xxx_queuecommand(struct Scsi_Host *h, struct scsi_cmnd *cmd);
1da177e4
LT		 220static int qla2xxx_eh_abort(struct scsi_cmnd *);
221static int qla2xxx_eh_device_reset(struct scsi_cmnd *);
523ec773 222static int qla2xxx_eh_target_reset(struct scsi_cmnd *);
1da177e4
LT		 223static int qla2xxx_eh_bus_reset(struct scsi_cmnd *);
224static int qla2xxx_eh_host_reset(struct scsi_cmnd *);
1da177e4 225
e881a172 226static int qla2x00_change_queue_depth(struct scsi_device *, int, int);
ce7e4af7
AV		 227static int qla2x00_change_queue_type(struct scsi_device *, int);
228
a5326f86 229struct scsi_host_template qla2xxx_driver_template = {
1da177e4 230 .module = THIS_MODULE,
cb63067a 231 .name = QLA2XXX_DRIVER_NAME,
a5326f86 232 .queuecommand = qla2xxx_queuecommand,
fca29703
AV		 233
234 .eh_abort_handler = qla2xxx_eh_abort,
235 .eh_device_reset_handler = qla2xxx_eh_device_reset,
523ec773 236 .eh_target_reset_handler = qla2xxx_eh_target_reset,
fca29703
AV		 237 .eh_bus_reset_handler = qla2xxx_eh_bus_reset,
238 .eh_host_reset_handler = qla2xxx_eh_host_reset,
239
240 .slave_configure = qla2xxx_slave_configure,
241
242 .slave_alloc = qla2xxx_slave_alloc,
243 .slave_destroy = qla2xxx_slave_destroy,
ed677086
AV		 244 .scan_finished = qla2xxx_scan_finished,
245 .scan_start = qla2xxx_scan_start,
ce7e4af7
AV		 246 .change_queue_depth = qla2x00_change_queue_depth,
247 .change_queue_type = qla2x00_change_queue_type,
fca29703
AV		 248 .this_id = -1,
249 .cmd_per_lun = 3,
250 .use_clustering = ENABLE_CLUSTERING,
251 .sg_tablesize = SG_ALL,
252
253 .max_sectors = 0xFFFF,
afb046e2 254 .shost_attrs = qla2x00_host_attrs,
fca29703
AV		 255};
256
1da177e4 257static struct scsi_transport_template *qla2xxx_transport_template = NULL;
2c3dfe3f 258struct scsi_transport_template *qla2xxx_transport_vport_template = NULL;
1da177e4 259
1da177e4
LT		 260/* TODO Convert to inlines
261 *
262 * Timer routines
263 */
1da177e4 264
2c3dfe3f 265__inline__ void
e315cd28 266qla2x00_start_timer(scsi_qla_host_t *vha, void *func, unsigned long interval)
1da177e4 267{
e315cd28
AC		 268 init_timer(&vha->timer);
269 vha->timer.expires = jiffies + interval * HZ;
270 vha->timer.data = (unsigned long)vha;
271 vha->timer.function = (void (*)(unsigned long))func;
272 add_timer(&vha->timer);
273 vha->timer_active = 1;
1da177e4
LT		 274}
275
276static inline void
e315cd28 277qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval)
1da177e4 278{
a9083016 279 /* Currently used for 82XX only. */
7c3df132
SK		 280 if (vha->device_flags & DFLG_DEV_FAILED) {
281 ql_dbg(ql_dbg_timer, vha, 0x600d,
282 "Device in a failed state, returning.\n");
a9083016 283 return;
7c3df132 284 }
a9083016 285
e315cd28 286 mod_timer(&vha->timer, jiffies + interval * HZ);
1da177e4
LT		 287}
288
a824ebb3 289static __inline__ void
e315cd28 290qla2x00_stop_timer(scsi_qla_host_t *vha)
1da177e4 291{
e315cd28
AC		 292 del_timer_sync(&vha->timer);
293 vha->timer_active = 0;
1da177e4
LT		 294}
295
1da177e4
LT		 296static int qla2x00_do_dpc(void *data);
297
298static void qla2x00_rst_aen(scsi_qla_host_t *);
299
73208dfd
AC		 300static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t,
301 struct req_que **, struct rsp_que **);
e30d1756 302static void qla2x00_free_fw_dump(struct qla_hw_data *);
e315cd28
AC		 303static void qla2x00_mem_free(struct qla_hw_data *);
304static void qla2x00_sp_free_dma(srb_t *);
1da177e4 305
1da177e4 306/* -------------------------------------------------------------------------- */
73208dfd
AC		 307static int qla2x00_alloc_queues(struct qla_hw_data *ha)
308{
7c3df132 309 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2afa19a9 310 ha->req_q_map = kzalloc(sizeof(struct req_que *) * ha->max_req_queues,
73208dfd
AC		 311 GFP_KERNEL);
312 if (!ha->req_q_map) {
7c3df132
SK		 313 ql_log(ql_log_fatal, vha, 0x003b,
314 "Unable to allocate memory for request queue ptrs.\n");
73208dfd
AC		 315 goto fail_req_map;
316 }
317
2afa19a9 318 ha->rsp_q_map = kzalloc(sizeof(struct rsp_que *) * ha->max_rsp_queues,
73208dfd
AC		 319 GFP_KERNEL);
320 if (!ha->rsp_q_map) {
7c3df132
SK		 321 ql_log(ql_log_fatal, vha, 0x003c,
322 "Unable to allocate memory for response queue ptrs.\n");
73208dfd
AC		 323 goto fail_rsp_map;
324 }
325 set_bit(0, ha->rsp_qid_map);
326 set_bit(0, ha->req_qid_map);
327 return 1;
328
329fail_rsp_map:
330 kfree(ha->req_q_map);
331 ha->req_q_map = NULL;
332fail_req_map:
333 return -ENOMEM;
334}
335
2afa19a9 336static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req)
73208dfd 337{
73208dfd
AC		 338 if (req && req->ring)
339 dma_free_coherent(&ha->pdev->dev,
340 (req->length + 1) * sizeof(request_t),
341 req->ring, req->dma);
342
343 kfree(req);
344 req = NULL;
345}
346
2afa19a9
AC		 347static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp)
348{
349 if (rsp && rsp->ring)
350 dma_free_coherent(&ha->pdev->dev,
351 (rsp->length + 1) * sizeof(response_t),
352 rsp->ring, rsp->dma);
353
354 kfree(rsp);
355 rsp = NULL;
356}
357
73208dfd
AC		 358static void qla2x00_free_queues(struct qla_hw_data *ha)
359{
360 struct req_que *req;
361 struct rsp_que *rsp;
362 int cnt;
363
2afa19a9 364 for (cnt = 0; cnt < ha->max_req_queues; cnt++) {
73208dfd 365 req = ha->req_q_map[cnt];
2afa19a9 366 qla2x00_free_req_que(ha, req);
73208dfd 367 }
73208dfd
AC		 368 kfree(ha->req_q_map);
369 ha->req_q_map = NULL;
2afa19a9
AC		 370
371 for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) {
372 rsp = ha->rsp_q_map[cnt];
373 qla2x00_free_rsp_que(ha, rsp);
374 }
375 kfree(ha->rsp_q_map);
376 ha->rsp_q_map = NULL;
73208dfd
AC		 377}
378
68ca949c
AC		 379static int qla25xx_setup_mode(struct scsi_qla_host *vha)
380{
381 uint16_t options = 0;
382 int ques, req, ret;
383 struct qla_hw_data *ha = vha->hw;
384
7163ea81 385 if (!(ha->fw_attributes & BIT_6)) {
7c3df132
SK		 386 ql_log(ql_log_warn, vha, 0x00d8,
387 "Firmware is not multi-queue capable.\n");
7163ea81
AC		 388 goto fail;
389 }
68ca949c 390 if (ql2xmultique_tag) {
68ca949c
AC		 391 /* create a request queue for IO */
392 options |= BIT_7;
393 req = qla25xx_create_req_que(ha, options, 0, 0, -1,
394 QLA_DEFAULT_QUE_QOS);
395 if (!req) {
7c3df132
SK		 396 ql_log(ql_log_warn, vha, 0x00e0,
397 "Failed to create request queue.\n");
68ca949c
AC		 398 goto fail;
399 }
278274d5 400 ha->wq = alloc_workqueue("qla2xxx_wq", WQ_MEM_RECLAIM, 1);
68ca949c
AC		 401 vha->req = ha->req_q_map[req];
402 options |= BIT_1;
403 for (ques = 1; ques < ha->max_rsp_queues; ques++) {
404 ret = qla25xx_create_rsp_que(ha, options, 0, 0, req);
405 if (!ret) {
7c3df132
SK		 406 ql_log(ql_log_warn, vha, 0x00e8,
407 "Failed to create response queue.\n");
68ca949c
AC		 408 goto fail2;
409 }
410 }
7163ea81 411 ha->flags.cpu_affinity_enabled = 1;
7c3df132
SK		 412 ql_dbg(ql_dbg_multiq, vha, 0xc007,
413 "CPU affinity mode enalbed, "
414 "no. of response queues:%d no. of request queues:%d.\n",
415 ha->max_rsp_queues, ha->max_req_queues);
416 ql_dbg(ql_dbg_init, vha, 0x00e9,
417 "CPU affinity mode enalbed, "
418 "no. of response queues:%d no. of request queues:%d.\n",
419 ha->max_rsp_queues, ha->max_req_queues);
68ca949c
AC		 420 }
421 return 0;
422fail2:
423 qla25xx_delete_queues(vha);
7163ea81
AC		 424 destroy_workqueue(ha->wq);
425 ha->wq = NULL;
68ca949c
AC		 426fail:
427 ha->mqenable = 0;
7163ea81
AC		 428 kfree(ha->req_q_map);
429 kfree(ha->rsp_q_map);
430 ha->max_req_queues = ha->max_rsp_queues = 1;
68ca949c
AC		 431 return 1;
432}
433
1da177e4 434static char *
e315cd28 435qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str)
1da177e4 436{
e315cd28 437 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 438 static char *pci_bus_modes[] = {
439 "33", "66", "100", "133",
440 };
441 uint16_t pci_bus;
442
443 strcpy(str, "PCI");
444 pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9;
445 if (pci_bus) {
446 strcat(str, "-X (");
447 strcat(str, pci_bus_modes[pci_bus]);
448 } else {
449 pci_bus = (ha->pci_attr & BIT_8) >> 8;
450 strcat(str, " (");
451 strcat(str, pci_bus_modes[pci_bus]);
452 }
453 strcat(str, " MHz)");
454
455 return (str);
456}
457
fca29703 458static char *
e315cd28 459qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str)
fca29703
AV		 460{
461 static char *pci_bus_modes[] = { "33", "66", "100", "133", };
e315cd28 462 struct qla_hw_data *ha = vha->hw;
fca29703
AV		 463 uint32_t pci_bus;
464 int pcie_reg;
465
466 pcie_reg = pci_find_capability(ha->pdev, PCI_CAP_ID_EXP);
467 if (pcie_reg) {
468 char lwstr[6];
469 uint16_t pcie_lstat, lspeed, lwidth;
470
471 pcie_reg += 0x12;
472 pci_read_config_word(ha->pdev, pcie_reg, &pcie_lstat);
473 lspeed = pcie_lstat & (BIT_0 | BIT_1 | BIT_2 | BIT_3);
474 lwidth = (pcie_lstat &
475 (BIT_4 | BIT_5 | BIT_6 | BIT_7 | BIT_8 | BIT_9)) >> 4;
476
477 strcpy(str, "PCIe (");
478 if (lspeed == 1)
c87a0d8c 479 strcat(str, "2.5GT/s ");
c3a2f0df 480 else if (lspeed == 2)
c87a0d8c 481 strcat(str, "5.0GT/s ");
fca29703
AV		 482 else
483 strcat(str, "<unknown> ");
484 snprintf(lwstr, sizeof(lwstr), "x%d)", lwidth);
485 strcat(str, lwstr);
486
487 return str;
488 }
489
490 strcpy(str, "PCI");
491 pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8;
492 if (pci_bus == 0 || pci_bus == 8) {
493 strcat(str, " (");
494 strcat(str, pci_bus_modes[pci_bus >> 3]);
495 } else {
496 strcat(str, "-X ");
497 if (pci_bus & BIT_2)
498 strcat(str, "Mode 2");
499 else
500 strcat(str, "Mode 1");
501 strcat(str, " (");
502 strcat(str, pci_bus_modes[pci_bus & ~BIT_2]);
503 }
504 strcat(str, " MHz)");
505
506 return str;
507}
508
e5f82ab8 509static char *
e315cd28 510qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str)
1da177e4
LT		 511{
512 char un_str[10];
e315cd28 513 struct qla_hw_data *ha = vha->hw;
fa2a1ce5 514
1da177e4
LT		 515 sprintf(str, "%d.%02d.%02d ", ha->fw_major_version,
516 ha->fw_minor_version,
517 ha->fw_subminor_version);
518
519 if (ha->fw_attributes & BIT_9) {
520 strcat(str, "FLX");
521 return (str);
522 }
523
524 switch (ha->fw_attributes & 0xFF) {
525 case 0x7:
526 strcat(str, "EF");
527 break;
528 case 0x17:
529 strcat(str, "TP");
530 break;
531 case 0x37:
532 strcat(str, "IP");
533 break;
534 case 0x77:
535 strcat(str, "VI");
536 break;
537 default:
538 sprintf(un_str, "(%x)", ha->fw_attributes);
539 strcat(str, un_str);
540 break;
541 }
542 if (ha->fw_attributes & 0x100)
543 strcat(str, "X");
544
545 return (str);
546}
547
e5f82ab8 548static char *
e315cd28 549qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str)
fca29703 550{
e315cd28 551 struct qla_hw_data *ha = vha->hw;
f0883ac6 552
3a03eb79
AV		 553 sprintf(str, "%d.%02d.%02d (%x)", ha->fw_major_version,
554 ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes);
fca29703 555 return str;
fca29703
AV		 556}
557
558static inline srb_t *
e315cd28 559qla2x00_get_new_sp(scsi_qla_host_t *vha, fc_port_t *fcport,
f5e3e40b 560 struct scsi_cmnd *cmd)
fca29703
AV		 561{
562 srb_t *sp;
e315cd28 563 struct qla_hw_data *ha = vha->hw;
fca29703
AV		 564
565 sp = mempool_alloc(ha->srb_mempool, GFP_ATOMIC);
7c3df132
SK		 566 if (!sp) {
567 ql_log(ql_log_warn, vha, 0x3006,
568 "Memory allocation failed for sp.\n");
fca29703 569 return sp;
7c3df132 570 }
fca29703 571
083a469d 572 atomic_set(&sp->ref_count, 1);
fca29703
AV		 573 sp->fcport = fcport;
574 sp->cmd = cmd;
575 sp->flags = 0;
576 CMD_SP(cmd) = (void *)sp;
cf53b069 577 sp->ctx = NULL;
fca29703
AV		 578
579 return sp;
580}
581
1da177e4 582static int
f5e3e40b 583qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
fca29703 584{
134ae078 585 scsi_qla_host_t *vha = shost_priv(host);
fca29703 586 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
19a7b4ae 587 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
e315cd28
AC		 588 struct qla_hw_data *ha = vha->hw;
589 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
fca29703
AV		 590 srb_t *sp;
591 int rval;
592
85880801 593 if (ha->flags.eeh_busy) {
7c3df132
SK		 594 if (ha->flags.pci_channel_io_perm_failure) {
595 ql_dbg(ql_dbg_io, vha, 0x3001,
596 "PCI Channel IO permanent failure, exiting "
597 "cmd=%p.\n", cmd);
b9b12f73 598 cmd->result = DID_NO_CONNECT << 16;
7c3df132
SK		 599 } else {
600 ql_dbg(ql_dbg_io, vha, 0x3002,
601 "EEH_Busy, Requeuing the cmd=%p.\n", cmd);
85880801 602 cmd->result = DID_REQUEUE << 16;
7c3df132 603 }
14e660e6
SJ		 604 goto qc24_fail_command;
605 }
606
19a7b4ae
JSEC		 607 rval = fc_remote_port_chkready(rport);
608 if (rval) {
609 cmd->result = rval;
7c3df132
SK		 610 ql_dbg(ql_dbg_io, vha, 0x3003,
611 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
612 cmd, rval);
fca29703
AV		 613 goto qc24_fail_command;
614 }
615
bad75002
AE		 616 if (!vha->flags.difdix_supported &&
617 scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) {
7c3df132
SK		 618 ql_dbg(ql_dbg_io, vha, 0x3004,
619 "DIF Cap not reg, fail DIF capable cmd's:%p.\n",
620 cmd);
bad75002
AE		 621 cmd->result = DID_NO_CONNECT << 16;
622 goto qc24_fail_command;
623 }
fca29703
AV		 624 if (atomic_read(&fcport->state) != FCS_ONLINE) {
625 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
38170fa8 626 atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
7c3df132
SK		 627 ql_dbg(ql_dbg_io, vha, 0x3005,
628 "Returning DNC, fcport_state=%d loop_state=%d.\n",
629 atomic_read(&fcport->state),
630 atomic_read(&base_vha->loop_state));
fca29703
AV		 631 cmd->result = DID_NO_CONNECT << 16;
632 goto qc24_fail_command;
633 }
7b594131 634 goto qc24_target_busy;
fca29703
AV		 635 }
636
f5e3e40b 637 sp = qla2x00_get_new_sp(base_vha, fcport, cmd);
fca29703 638 if (!sp)
f5e3e40b 639 goto qc24_host_busy;
fca29703 640
e315cd28 641 rval = ha->isp_ops->start_scsi(sp);
7c3df132
SK		 642 if (rval != QLA_SUCCESS) {
643 ql_dbg(ql_dbg_io, vha, 0x3013,
644 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
fca29703 645 goto qc24_host_busy_free_sp;
7c3df132 646 }
fca29703 647
fca29703
AV		 648 return 0;
649
650qc24_host_busy_free_sp:
e315cd28
AC		 651 qla2x00_sp_free_dma(sp);
652 mempool_free(sp, ha->srb_mempool);
fca29703 653
f5e3e40b 654qc24_host_busy:
fca29703
AV		 655 return SCSI_MLQUEUE_HOST_BUSY;
656
7b594131
MC		 657qc24_target_busy:
658 return SCSI_MLQUEUE_TARGET_BUSY;
659
fca29703 660qc24_fail_command:
f5e3e40b 661 cmd->scsi_done(cmd);
fca29703
AV		 662
663 return 0;
664}
665
1da177e4
LT		 666/*
667 * qla2x00_eh_wait_on_command
668 * Waits for the command to be returned by the Firmware for some
669 * max time.
670 *
671 * Input:
1da177e4 672 * cmd = Scsi Command to wait on.
1da177e4
LT		 673 *
674 * Return:
675 * Not Found : 0
676 * Found : 1
677 */
678static int
e315cd28 679qla2x00_eh_wait_on_command(struct scsi_cmnd *cmd)
1da177e4 680{
fe74c71f
AV		 681#define ABORT_POLLING_PERIOD 1000
682#define ABORT_WAIT_ITER ((10 * 1000) / (ABORT_POLLING_PERIOD))
f4f051eb 683 unsigned long wait_iter = ABORT_WAIT_ITER;
85880801
AV		 684 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
685 struct qla_hw_data *ha = vha->hw;
f4f051eb 686 int ret = QLA_SUCCESS;
1da177e4 687
85880801 688 if (unlikely(pci_channel_offline(ha->pdev)) || ha->flags.eeh_busy) {
7c3df132
SK		 689 ql_dbg(ql_dbg_taskm, vha, 0x8005,
690 "Return:eh_wait.\n");
85880801
AV		 691 return ret;
692 }
693
d970432c 694 while (CMD_SP(cmd) && wait_iter--) {
fe74c71f 695 msleep(ABORT_POLLING_PERIOD);
f4f051eb 696 }
697 if (CMD_SP(cmd))
698 ret = QLA_FUNCTION_FAILED;
1da177e4 699
f4f051eb 700 return ret;
1da177e4
LT		 701}
702
703/*
704 * qla2x00_wait_for_hba_online
fa2a1ce5 705 * Wait till the HBA is online after going through
1da177e4
LT		 706 * <= MAX_RETRIES_OF_ISP_ABORT or
707 * finally HBA is disabled ie marked offline
708 *
709 * Input:
710 * ha - pointer to host adapter structure
fa2a1ce5
AV		 711 *
712 * Note:
1da177e4
LT		 713 * Does context switching-Release SPIN_LOCK
714 * (if any) before calling this routine.
715 *
716 * Return:
717 * Success (Adapter is online) : 0
718 * Failed (Adapter is offline/disabled) : 1
719 */
854165f4 720int
e315cd28 721qla2x00_wait_for_hba_online(scsi_qla_host_t *vha)
1da177e4 722{
fca29703
AV		 723 int return_status;
724 unsigned long wait_online;
e315cd28
AC		 725 struct qla_hw_data *ha = vha->hw;
726 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4 727
fa2a1ce5 728 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ);
e315cd28
AC		 729 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
730 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
731 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
732 ha->dpc_active) && time_before(jiffies, wait_online)) {
1da177e4
LT		 733
734 msleep(1000);
735 }
e315cd28 736 if (base_vha->flags.online)
fa2a1ce5 737 return_status = QLA_SUCCESS;
1da177e4
LT		 738 else
739 return_status = QLA_FUNCTION_FAILED;
740
1da177e4
LT		 741 return (return_status);
742}
743
86fbee86
LC		 744/*
745 * qla2x00_wait_for_reset_ready
746 * Wait till the HBA is online after going through
747 * <= MAX_RETRIES_OF_ISP_ABORT or
748 * finally HBA is disabled ie marked offline or flash
749 * operations are in progress.
750 *
751 * Input:
752 * ha - pointer to host adapter structure
753 *
754 * Note:
755 * Does context switching-Release SPIN_LOCK
756 * (if any) before calling this routine.
757 *
758 * Return:
759 * Success (Adapter is online/no flash ops) : 0
760 * Failed (Adapter is offline/disabled/flash ops in progress) : 1
761 */
3dbe756a 762static int
86fbee86
LC		 763qla2x00_wait_for_reset_ready(scsi_qla_host_t *vha)
764{
765 int return_status;
766 unsigned long wait_online;
767 struct qla_hw_data *ha = vha->hw;
768 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
769
770 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ);
771 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
772 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
773 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
774 ha->optrom_state != QLA_SWAITING ||
775 ha->dpc_active) && time_before(jiffies, wait_online))
776 msleep(1000);
777
778 if (base_vha->flags.online && ha->optrom_state == QLA_SWAITING)
779 return_status = QLA_SUCCESS;
780 else
781 return_status = QLA_FUNCTION_FAILED;
782
7c3df132
SK		 783 ql_dbg(ql_dbg_taskm, vha, 0x8019,
784 "%s return status=%d.\n", __func__, return_status);
86fbee86
LC		 785
786 return return_status;
787}
788
2533cf67
LC		 789int
790qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha)
791{
792 int return_status;
793 unsigned long wait_reset;
794 struct qla_hw_data *ha = vha->hw;
795 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
796
797 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ);
798 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
799 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
800 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
801 ha->dpc_active) && time_before(jiffies, wait_reset)) {
802
803 msleep(1000);
804
805 if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) &&
806 ha->flags.chip_reset_done)
807 break;
808 }
809 if (ha->flags.chip_reset_done)
810 return_status = QLA_SUCCESS;
811 else
812 return_status = QLA_FUNCTION_FAILED;
813
814 return return_status;
815}
816
1da177e4
LT		 817/*
818 * qla2x00_wait_for_loop_ready
819 * Wait for MAX_LOOP_TIMEOUT(5 min) value for loop
fa2a1ce5 820 * to be in LOOP_READY state.
1da177e4
LT		 821 * Input:
822 * ha - pointer to host adapter structure
fa2a1ce5
AV		 823 *
824 * Note:
1da177e4
LT		 825 * Does context switching-Release SPIN_LOCK
826 * (if any) before calling this routine.
fa2a1ce5 827 *
1da177e4
LT		 828 *
829 * Return:
830 * Success (LOOP_READY) : 0
831 * Failed (LOOP_NOT_READY) : 1
832 */
fa2a1ce5 833static inline int
e315cd28 834qla2x00_wait_for_loop_ready(scsi_qla_host_t *vha)
1da177e4
LT		 835{
836 int return_status = QLA_SUCCESS;
837 unsigned long loop_timeout ;
e315cd28
AC		 838 struct qla_hw_data *ha = vha->hw;
839 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4
LT		 840
841 /* wait for 5 min at the max for loop to be ready */
fa2a1ce5 842 loop_timeout = jiffies + (MAX_LOOP_TIMEOUT * HZ);
1da177e4 843
e315cd28
AC		 844 while ((!atomic_read(&base_vha->loop_down_timer) &&
845 atomic_read(&base_vha->loop_state) == LOOP_DOWN) ||
846 atomic_read(&base_vha->loop_state) != LOOP_READY) {
847 if (atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
57680080
RA		 848 return_status = QLA_FUNCTION_FAILED;
849 break;
850 }
1da177e4
LT		 851 msleep(1000);
852 if (time_after_eq(jiffies, loop_timeout)) {
853 return_status = QLA_FUNCTION_FAILED;
854 break;
855 }
856 }
fa2a1ce5 857 return (return_status);
1da177e4
LT		 858}
859
083a469d
GM		 860static void
861sp_get(struct srb *sp)
862{
863 atomic_inc(&sp->ref_count);
864}
865
1da177e4
LT		 866/**************************************************************************
867* qla2xxx_eh_abort
868*
869* Description:
870* The abort function will abort the specified command.
871*
872* Input:
873* cmd = Linux SCSI command packet to be aborted.
874*
875* Returns:
876* Either SUCCESS or FAILED.
877*
878* Note:
2ea00202 879* Only return FAILED if command not returned by firmware.
1da177e4 880**************************************************************************/
e5f82ab8 881static int
1da177e4
LT		 882qla2xxx_eh_abort(struct scsi_cmnd *cmd)
883{
e315cd28 884 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
f4f051eb 885 srb_t *sp;
4e98d3b8 886 int ret;
f4f051eb 887 unsigned int id, lun;
18e144d3 888 unsigned long flags;
2ea00202 889 int wait = 0;
e315cd28 890 struct qla_hw_data *ha = vha->hw;
1da177e4 891
7c3df132
SK		 892 ql_dbg(ql_dbg_taskm, vha, 0x8000,
893 "Entered %s for cmd=%p.\n", __func__, cmd);
f4f051eb 894 if (!CMD_SP(cmd))
2ea00202 895 return SUCCESS;
1da177e4 896
4e98d3b8 897 ret = fc_block_scsi_eh(cmd);
7c3df132
SK		 898 ql_dbg(ql_dbg_taskm, vha, 0x8001,
899 "Return value of fc_block_scsi_eh=%d.\n", ret);
4e98d3b8
AV		 900 if (ret != 0)
901 return ret;
902 ret = SUCCESS;
903
f4f051eb 904 id = cmd->device->id;
905 lun = cmd->device->lun;
1da177e4 906
e315cd28 907 spin_lock_irqsave(&ha->hardware_lock, flags);
170babc3
MC		 908 sp = (srb_t *) CMD_SP(cmd);
909 if (!sp) {
910 spin_unlock_irqrestore(&ha->hardware_lock, flags);
911 return SUCCESS;
912 }
1da177e4 913
7c3df132
SK		 914 ql_dbg(ql_dbg_taskm, vha, 0x8002,
915 "Aborting sp=%p cmd=%p from RISC ", sp, cmd);
17d98630 916
170babc3
MC		 917 /* Get a reference to the sp and drop the lock.*/
918 sp_get(sp);
083a469d 919
e315cd28 920 spin_unlock_irqrestore(&ha->hardware_lock, flags);
170babc3 921 if (ha->isp_ops->abort_command(sp)) {
7c3df132
SK		 922 ql_dbg(ql_dbg_taskm, vha, 0x8003,
923 "Abort command mbx failed for cmd=%p.\n", cmd);
170babc3 924 } else {
7c3df132
SK		 925 ql_dbg(ql_dbg_taskm, vha, 0x8004,
926 "Abort command mbx success.\n");
170babc3
MC		 927 wait = 1;
928 }
75942064
SK		 929
930 spin_lock_irqsave(&ha->hardware_lock, flags);
170babc3 931 qla2x00_sp_compl(ha, sp);
75942064 932 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1da177e4 933
bc91ade9
CD		 934 /* Did the command return during mailbox execution? */
935 if (ret == FAILED && !CMD_SP(cmd))
936 ret = SUCCESS;
937
f4f051eb 938 /* Wait for the command to be returned. */
2ea00202 939 if (wait) {
e315cd28 940 if (qla2x00_eh_wait_on_command(cmd) != QLA_SUCCESS) {
7c3df132
SK		 941 ql_log(ql_log_warn, vha, 0x8006,
942 "Abort handler timed out for cmd=%p.\n", cmd);
2ea00202 943 ret = FAILED;
f4f051eb 944 }
1da177e4 945 }
1da177e4 946
7c3df132
SK		 947 ql_log(ql_log_info, vha, 0x801c,
948 "Abort command issued -- %d %x.\n", wait, ret);
1da177e4 949
f4f051eb 950 return ret;
951}
1da177e4 952
4d78c973 953int
e315cd28 954qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t,
4d78c973 955 unsigned int l, enum nexus_wait_type type)
f4f051eb 956{
17d98630 957 int cnt, match, status;
18e144d3 958 unsigned long flags;
e315cd28 959 struct qla_hw_data *ha = vha->hw;
73208dfd 960 struct req_que *req;
4d78c973 961 srb_t *sp;
1da177e4 962
523ec773 963 status = QLA_SUCCESS;
17d98630 964
e315cd28 965 spin_lock_irqsave(&ha->hardware_lock, flags);
67c2e93a 966 req = vha->req;
17d98630
AC		 967 for (cnt = 1; status == QLA_SUCCESS &&
968 cnt < MAX_OUTSTANDING_COMMANDS; cnt++) {
969 sp = req->outstanding_cmds[cnt];
970 if (!sp)
523ec773 971 continue;
bad75002 972 if ((sp->ctx) && !IS_PROT_IO(sp))
cf53b069 973 continue;
17d98630
AC		 974 if (vha->vp_idx != sp->fcport->vha->vp_idx)
975 continue;
976 match = 0;
977 switch (type) {
978 case WAIT_HOST:
979 match = 1;
980 break;
981 case WAIT_TARGET:
982 match = sp->cmd->device->id == t;
983 break;
984 case WAIT_LUN:
985 match = (sp->cmd->device->id == t &&
986 sp->cmd->device->lun == l);
987 break;
73208dfd 988 }
17d98630
AC		 989 if (!match)
990 continue;
991
992 spin_unlock_irqrestore(&ha->hardware_lock, flags);
993 status = qla2x00_eh_wait_on_command(sp->cmd);
994 spin_lock_irqsave(&ha->hardware_lock, flags);
1da177e4 995 }
e315cd28 996 spin_unlock_irqrestore(&ha->hardware_lock, flags);
523ec773
AV		 997
998 return status;
1da177e4
LT		 999}
1000
523ec773
AV		 1001static char *reset_errors[] = {
1002 "HBA not online",
1003 "HBA not ready",
1004 "Task management failed",
1005 "Waiting for command completions",
1006};
1da177e4 1007
e5f82ab8 1008static int
523ec773 1009__qla2xxx_eh_generic_reset(char *name, enum nexus_wait_type type,
2afa19a9 1010 struct scsi_cmnd *cmd, int (*do_reset)(struct fc_port *, unsigned int, int))
1da177e4 1011{
e315cd28 1012 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
bdf79621 1013 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
523ec773 1014 int err;
1da177e4 1015
7c3df132
SK		 1016 if (!fcport) {
1017 ql_log(ql_log_warn, vha, 0x8007,
1018 "fcport is NULL.\n");
523ec773 1019 return FAILED;
7c3df132 1020 }
1da177e4 1021
4e98d3b8 1022 err = fc_block_scsi_eh(cmd);
7c3df132
SK		 1023 ql_dbg(ql_dbg_taskm, vha, 0x8008,
1024 "fc_block_scsi_eh ret=%d.\n", err);
4e98d3b8
AV		 1025 if (err != 0)
1026 return err;
1027
7c3df132
SK		 1028 ql_log(ql_log_info, vha, 0x8009,
1029 "%s RESET ISSUED for id %d lun %d cmd=%p.\n", name,
1030 cmd->device->id, cmd->device->lun, cmd);
1da177e4 1031
523ec773 1032 err = 0;
7c3df132
SK		 1033 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1034 ql_log(ql_log_warn, vha, 0x800a,
1035 "Wait for hba online failed for cmd=%p.\n", cmd);
523ec773 1036 goto eh_reset_failed;
7c3df132 1037 }
523ec773 1038 err = 1;
7c3df132
SK		 1039 if (qla2x00_wait_for_loop_ready(vha) != QLA_SUCCESS) {
1040 ql_log(ql_log_warn, vha, 0x800b,
1041 "Wait for loop ready failed for cmd=%p.\n", cmd);
523ec773 1042 goto eh_reset_failed;
7c3df132 1043 }
523ec773 1044 err = 2;
2afa19a9 1045 if (do_reset(fcport, cmd->device->lun, cmd->request->cpu + 1)
7c3df132
SK		 1046 != QLA_SUCCESS) {
1047 ql_log(ql_log_warn, vha, 0x800c,
1048 "do_reset failed for cmd=%p.\n", cmd);
523ec773 1049 goto eh_reset_failed;
7c3df132 1050 }
523ec773 1051 err = 3;
e315cd28 1052 if (qla2x00_eh_wait_for_pending_commands(vha, cmd->device->id,
7c3df132
SK		 1053 cmd->device->lun, type) != QLA_SUCCESS) {
1054 ql_log(ql_log_warn, vha, 0x800d,
1055 "wait for peding cmds failed for cmd=%p.\n", cmd);
523ec773 1056 goto eh_reset_failed;
7c3df132 1057 }
523ec773 1058
7c3df132
SK		 1059 ql_log(ql_log_info, vha, 0x800e,
1060 "%s RESET SUCCEEDED for id %d lun %d cmd=%p.\n", name,
1061 cmd->device->id, cmd->device->lun, cmd);
523ec773
AV		 1062
1063 return SUCCESS;
1064
4d78c973 1065eh_reset_failed:
7c3df132
SK		 1066 ql_log(ql_log_info, vha, 0x800f,
1067 "%s RESET FAILED: %s for id %d lun %d cmd=%p.\n", name,
1068 reset_errors[err], cmd->device->id, cmd->device->lun);
523ec773
AV		 1069 return FAILED;
1070}
1da177e4 1071
523ec773
AV		 1072static int
1073qla2xxx_eh_device_reset(struct scsi_cmnd *cmd)
1074{
e315cd28
AC		 1075 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1076 struct qla_hw_data *ha = vha->hw;
1da177e4 1077
523ec773
AV		 1078 return __qla2xxx_eh_generic_reset("DEVICE", WAIT_LUN, cmd,
1079 ha->isp_ops->lun_reset);
1da177e4
LT		 1080}
1081
1da177e4 1082static int
523ec773 1083qla2xxx_eh_target_reset(struct scsi_cmnd *cmd)
1da177e4 1084{
e315cd28
AC		 1085 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1086 struct qla_hw_data *ha = vha->hw;
1da177e4 1087
523ec773
AV		 1088 return __qla2xxx_eh_generic_reset("TARGET", WAIT_TARGET, cmd,
1089 ha->isp_ops->target_reset);
1da177e4
LT		 1090}
1091
1da177e4
LT		 1092/**************************************************************************
1093* qla2xxx_eh_bus_reset
1094*
1095* Description:
1096* The bus reset function will reset the bus and abort any executing
1097* commands.
1098*
1099* Input:
1100* cmd = Linux SCSI command packet of the command that cause the
1101* bus reset.
1102*
1103* Returns:
1104* SUCCESS/FAILURE (defined as macro in scsi.h).
1105*
1106**************************************************************************/
e5f82ab8 1107static int
1da177e4
LT		 1108qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd)
1109{
e315cd28 1110 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
bdf79621 1111 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
2c3dfe3f 1112 int ret = FAILED;
f4f051eb 1113 unsigned int id, lun;
f4f051eb 1114
f4f051eb 1115 id = cmd->device->id;
1116 lun = cmd->device->lun;
1da177e4 1117
7c3df132
SK		 1118 if (!fcport) {
1119 ql_log(ql_log_warn, vha, 0x8010,
1120 "fcport is NULL.\n");
f4f051eb 1121 return ret;
7c3df132 1122 }
1da177e4 1123
4e98d3b8 1124 ret = fc_block_scsi_eh(cmd);
7c3df132
SK		 1125 ql_dbg(ql_dbg_taskm, vha, 0x8011,
1126 "fc_block_scsi_eh ret=%d.\n", ret);
4e98d3b8
AV		 1127 if (ret != 0)
1128 return ret;
1129 ret = FAILED;
1130
7c3df132
SK		 1131 ql_log(ql_log_info, vha, 0x8012,
1132 "BUS RESET ISSUED for id %d lun %d.\n", id, lun);
1da177e4 1133
e315cd28 1134 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
7c3df132
SK		 1135 ql_log(ql_log_fatal, vha, 0x8013,
1136 "Wait for hba online failed board disabled.\n");
f4f051eb 1137 goto eh_bus_reset_done;
1da177e4
LT		 1138 }
1139
e315cd28
AC		 1140 if (qla2x00_wait_for_loop_ready(vha) == QLA_SUCCESS) {
1141 if (qla2x00_loop_reset(vha) == QLA_SUCCESS)
f4f051eb 1142 ret = SUCCESS;
1da177e4 1143 }
f4f051eb 1144 if (ret == FAILED)
1145 goto eh_bus_reset_done;
1da177e4 1146
9a41a62b 1147 /* Flush outstanding commands. */
4d78c973 1148 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) !=
7c3df132
SK		 1149 QLA_SUCCESS) {
1150 ql_log(ql_log_warn, vha, 0x8014,
1151 "Wait for pending commands failed.\n");
9a41a62b 1152 ret = FAILED;
7c3df132 1153 }
1da177e4 1154
f4f051eb 1155eh_bus_reset_done:
7c3df132
SK		 1156 ql_log(ql_log_warn, vha, 0x802b,
1157 "BUS RESET %s.\n", (ret == FAILED) ? "FAILED" : "SUCCEDED");
1da177e4 1158
f4f051eb 1159 return ret;
1da177e4
LT		 1160}
1161
1162/**************************************************************************
1163* qla2xxx_eh_host_reset
1164*
1165* Description:
1166* The reset function will reset the Adapter.
1167*
1168* Input:
1169* cmd = Linux SCSI command packet of the command that cause the
1170* adapter reset.
1171*
1172* Returns:
1173* Either SUCCESS or FAILED.
1174*
1175* Note:
1176**************************************************************************/
e5f82ab8 1177static int
1da177e4
LT		 1178qla2xxx_eh_host_reset(struct scsi_cmnd *cmd)
1179{
e315cd28 1180 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
bdf79621 1181 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
e315cd28 1182 struct qla_hw_data *ha = vha->hw;
2c3dfe3f 1183 int ret = FAILED;
f4f051eb 1184 unsigned int id, lun;
e315cd28 1185 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4 1186
f4f051eb 1187 id = cmd->device->id;
1188 lun = cmd->device->lun;
f4f051eb 1189
7c3df132
SK		 1190 if (!fcport) {
1191 ql_log(ql_log_warn, vha, 0x8016,
1192 "fcport is NULL.\n");
f4f051eb 1193 return ret;
7c3df132 1194 }
1da177e4 1195
4e98d3b8 1196 ret = fc_block_scsi_eh(cmd);
7c3df132
SK		 1197 ql_dbg(ql_dbg_taskm, vha, 0x8017,
1198 "fc_block_scsi_eh ret=%d.\n", ret);
4e98d3b8
AV		 1199 if (ret != 0)
1200 return ret;
1201 ret = FAILED;
1202
7c3df132
SK		 1203 ql_log(ql_log_info, vha, 0x8018,
1204 "ADAPTER RESET ISSUED for id %d lun %d.\n", id, lun);
1da177e4 1205
86fbee86 1206 if (qla2x00_wait_for_reset_ready(vha) != QLA_SUCCESS)
f4f051eb 1207 goto eh_host_reset_lock;
1da177e4
LT		 1208
1209 /*
1210 * Fixme-may be dpc thread is active and processing
fa2a1ce5 1211 * loop_resync,so wait a while for it to
1da177e4
LT		 1212 * be completed and then issue big hammer.Otherwise
1213 * it may cause I/O failure as big hammer marks the
1214 * devices as lost kicking of the port_down_timer
1215 * while dpc is stuck for the mailbox to complete.
1216 */
e315cd28
AC		 1217 qla2x00_wait_for_loop_ready(vha);
1218 if (vha != base_vha) {
1219 if (qla2x00_vp_abort_isp(vha))
f4f051eb 1220 goto eh_host_reset_lock;
e315cd28 1221 } else {
a9083016
GM		 1222 if (IS_QLA82XX(vha->hw)) {
1223 if (!qla82xx_fcoe_ctx_reset(vha)) {
1224 /* Ctx reset success */
1225 ret = SUCCESS;
1226 goto eh_host_reset_lock;
1227 }
1228 /* fall thru if ctx reset failed */
1229 }
68ca949c
AC		 1230 if (ha->wq)
1231 flush_workqueue(ha->wq);
1232
e315cd28 1233 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
a9083016 1234 if (ha->isp_ops->abort_isp(base_vha)) {
e315cd28
AC		 1235 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1236 /* failed. schedule dpc to try */
1237 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
1238
7c3df132
SK		 1239 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1240 ql_log(ql_log_warn, vha, 0x802a,
1241 "wait for hba online failed.\n");
e315cd28 1242 goto eh_host_reset_lock;
7c3df132 1243 }
e315cd28
AC		 1244 }
1245 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
fa2a1ce5 1246 }
1da177e4 1247
e315cd28 1248 /* Waiting for command to be returned to OS.*/
4d78c973 1249 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) ==
e315cd28 1250 QLA_SUCCESS)
f4f051eb 1251 ret = SUCCESS;
1da177e4 1252
f4f051eb 1253eh_host_reset_lock:
7c3df132 1254 qla_printk(KERN_INFO, ha, "%s: reset %s.\n", __func__,
25985edc 1255 (ret == FAILED) ? "failed" : "succeeded");
1da177e4 1256
f4f051eb 1257 return ret;
1258}
1da177e4
LT		 1259
1260/*
1261* qla2x00_loop_reset
1262* Issue loop reset.
1263*
1264* Input:
1265* ha = adapter block pointer.
1266*
1267* Returns:
1268* 0 = success
1269*/
a4722cf2 1270int
e315cd28 1271qla2x00_loop_reset(scsi_qla_host_t *vha)
1da177e4 1272{
0c8c39af 1273 int ret;
bdf79621 1274 struct fc_port *fcport;
e315cd28 1275 struct qla_hw_data *ha = vha->hw;
1da177e4 1276
f4c496c1 1277 if (ql2xtargetreset == 1 && ha->flags.enable_target_reset) {
55e5ed27
AV		 1278 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1279 if (fcport->port_type != FCT_TARGET)
1280 continue;
1281
1282 ret = ha->isp_ops->target_reset(fcport, 0, 0);
1283 if (ret != QLA_SUCCESS) {
7c3df132
SK		 1284 ql_dbg(ql_dbg_taskm, vha, 0x802c,
1285 "Bus Reset failed: Target Reset=%d "
1286 "d_id=%x.\n", ret, fcport->d_id.b24);
55e5ed27
AV		 1287 }
1288 }
1289 }
1290
a9083016 1291 if (ha->flags.enable_lip_full_login && !IS_QLA8XXX_TYPE(ha)) {
e315cd28 1292 ret = qla2x00_full_login_lip(vha);
0c8c39af 1293 if (ret != QLA_SUCCESS) {
7c3df132
SK		 1294 ql_dbg(ql_dbg_taskm, vha, 0x802d,
1295 "full_login_lip=%d.\n", ret);
749af3d5
AC		 1296 }
1297 atomic_set(&vha->loop_state, LOOP_DOWN);
1298 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
1299 qla2x00_mark_all_devices_lost(vha, 0);
1300 qla2x00_wait_for_loop_ready(vha);
0c8c39af
AV		 1301 }
1302
0d6e61bc 1303 if (ha->flags.enable_lip_reset) {
e315cd28 1304 ret = qla2x00_lip_reset(vha);
0c8c39af 1305 if (ret != QLA_SUCCESS) {
7c3df132
SK		 1306 ql_dbg(ql_dbg_taskm, vha, 0x802e,
1307 "lip_reset failed (%d).\n", ret);
e315cd28
AC		 1308 } else
1309 qla2x00_wait_for_loop_ready(vha);
1da177e4
LT		 1310 }
1311
1da177e4 1312 /* Issue marker command only when we are going to start the I/O */
e315cd28 1313 vha->marker_needed = 1;
1da177e4 1314
0c8c39af 1315 return QLA_SUCCESS;
1da177e4
LT		 1316}
1317
df4bf0bb 1318void
e315cd28 1319qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res)
df4bf0bb 1320{
73208dfd 1321 int que, cnt;
df4bf0bb
AV		 1322 unsigned long flags;
1323 srb_t *sp;
ac280b67 1324 struct srb_ctx *ctx;
e315cd28 1325 struct qla_hw_data *ha = vha->hw;
73208dfd 1326 struct req_que *req;
df4bf0bb
AV		 1327
1328 spin_lock_irqsave(&ha->hardware_lock, flags);
2afa19a9 1329 for (que = 0; que < ha->max_req_queues; que++) {
29bdccbe 1330 req = ha->req_q_map[que];
73208dfd
AC		 1331 if (!req)
1332 continue;
1333 for (cnt = 1; cnt < MAX_OUTSTANDING_COMMANDS; cnt++) {
1334 sp = req->outstanding_cmds[cnt];
e612d465 1335 if (sp) {
73208dfd 1336 req->outstanding_cmds[cnt] = NULL;
a9083016 1337 if (!sp->ctx ||
bad75002
AE		 1338 (sp->flags & SRB_FCP_CMND_DMA_VALID) ||
1339 IS_PROT_IO(sp)) {
ac280b67
AV		 1340 sp->cmd->result = res;
1341 qla2x00_sp_compl(ha, sp);
1342 } else {
1343 ctx = sp->ctx;
6c452a45
AV		 1344 if (ctx->type == SRB_LOGIN_CMD ||
1345 ctx->type == SRB_LOGOUT_CMD) {
4916392b 1346 ctx->u.iocb_cmd->free(sp);
db3ad7f8 1347 } else {
6c452a45 1348 struct fc_bsg_job *bsg_job =
4916392b 1349 ctx->u.bsg_job;
6c452a45
AV		 1350 if (bsg_job->request->msgcode
1351 == FC_BSG_HST_CT)
db3ad7f8 1352 kfree(sp->fcport);
6c452a45
AV		 1353 bsg_job->req->errors = 0;
1354 bsg_job->reply->result = res;
4916392b 1355 bsg_job->job_done(bsg_job);
db3ad7f8 1356 kfree(sp->ctx);
6c452a45 1357 mempool_free(sp,
4916392b 1358 ha->srb_mempool);
db3ad7f8 1359 }
ac280b67 1360 }
73208dfd 1361 }
df4bf0bb
AV		 1362 }
1363 }
1364 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1365}
1366
f4f051eb 1367static int
1368qla2xxx_slave_alloc(struct scsi_device *sdev)
1da177e4 1369{
bdf79621 1370 struct fc_rport *rport = starget_to_rport(scsi_target(sdev));
1da177e4 1371
19a7b4ae 1372 if (!rport || fc_remote_port_chkready(rport))
f4f051eb 1373 return -ENXIO;
bdf79621 1374
19a7b4ae 1375 sdev->hostdata = *(fc_port_t **)rport->dd_data;
1da177e4 1376
f4f051eb 1377 return 0;
1378}
1da177e4 1379
f4f051eb 1380static int
1381qla2xxx_slave_configure(struct scsi_device *sdev)
1382{
e315cd28 1383 scsi_qla_host_t *vha = shost_priv(sdev->host);
2afa19a9 1384 struct req_que *req = vha->req;
8482e118 1385
f4f051eb 1386 if (sdev->tagged_supported)
73208dfd 1387 scsi_activate_tcq(sdev, req->max_q_depth);
f4f051eb 1388 else
73208dfd 1389 scsi_deactivate_tcq(sdev, req->max_q_depth);
f4f051eb 1390 return 0;
1391}
1da177e4 1392
f4f051eb 1393static void
1394qla2xxx_slave_destroy(struct scsi_device *sdev)
1395{
1396 sdev->hostdata = NULL;
1da177e4
LT		 1397}
1398
c45dd305
GM		 1399static void qla2x00_handle_queue_full(struct scsi_device *sdev, int qdepth)
1400{
1401 fc_port_t *fcport = (struct fc_port *) sdev->hostdata;
1402
1403 if (!scsi_track_queue_full(sdev, qdepth))
1404 return;
1405
7c3df132
SK		 1406 ql_dbg(ql_dbg_io, fcport->vha, 0x3029,
1407 "Queue depth adjusted-down "
1408 "to %d for scsi(%ld:%d:%d:%d).\n",
1409 sdev->queue_depth, fcport->vha->host_no,
1410 sdev->channel, sdev->id, sdev->lun);
c45dd305
GM		 1411}
1412
1413static void qla2x00_adjust_sdev_qdepth_up(struct scsi_device *sdev, int qdepth)
1414{
1415 fc_port_t *fcport = sdev->hostdata;
1416 struct scsi_qla_host *vha = fcport->vha;
c45dd305
GM		 1417 struct req_que *req = NULL;
1418
1419 req = vha->req;
1420 if (!req)
1421 return;
1422
1423 if (req->max_q_depth <= sdev->queue_depth || req->max_q_depth < qdepth)
1424 return;
1425
1426 if (sdev->ordered_tags)
1427 scsi_adjust_queue_depth(sdev, MSG_ORDERED_TAG, qdepth);
1428 else
1429 scsi_adjust_queue_depth(sdev, MSG_SIMPLE_TAG, qdepth);
1430
7c3df132
SK		 1431 ql_dbg(ql_dbg_io, vha, 0x302a,
1432 "Queue depth adjusted-up to %d for "
1433 "scsi(%ld:%d:%d:%d).\n",
1434 sdev->queue_depth, fcport->vha->host_no,
1435 sdev->channel, sdev->id, sdev->lun);
c45dd305
GM		 1436}
1437
ce7e4af7 1438static int
e881a172 1439qla2x00_change_queue_depth(struct scsi_device *sdev, int qdepth, int reason)
ce7e4af7 1440{
c45dd305
GM		 1441 switch (reason) {
1442 case SCSI_QDEPTH_DEFAULT:
1443 scsi_adjust_queue_depth(sdev, scsi_get_tag_type(sdev), qdepth);
1444 break;
1445 case SCSI_QDEPTH_QFULL:
1446 qla2x00_handle_queue_full(sdev, qdepth);
1447 break;
1448 case SCSI_QDEPTH_RAMP_UP:
1449 qla2x00_adjust_sdev_qdepth_up(sdev, qdepth);
1450 break;
1451 default:
08002af2 1452 return -EOPNOTSUPP;
c45dd305 1453 }
e881a172 1454
ce7e4af7
AV		 1455 return sdev->queue_depth;
1456}
1457
1458static int
1459qla2x00_change_queue_type(struct scsi_device *sdev, int tag_type)
1460{
1461 if (sdev->tagged_supported) {
1462 scsi_set_tag_type(sdev, tag_type);
1463 if (tag_type)
1464 scsi_activate_tcq(sdev, sdev->queue_depth);
1465 else
1466 scsi_deactivate_tcq(sdev, sdev->queue_depth);
1467 } else
1468 tag_type = 0;
1469
1470 return tag_type;
1471}
1472
1da177e4
LT		 1473/**
1474 * qla2x00_config_dma_addressing() - Configure OS DMA addressing method.
1475 * @ha: HA context
1476 *
1477 * At exit, the @ha's flags.enable_64bit_addressing set to indicated
1478 * supported addressing method.
1479 */
1480static void
53303c42 1481qla2x00_config_dma_addressing(struct qla_hw_data *ha)
1da177e4 1482{
7524f9b9 1483 /* Assume a 32bit DMA mask. */
1da177e4 1484 ha->flags.enable_64bit_addressing = 0;
1da177e4 1485
6a35528a 1486 if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) {
7524f9b9
AV		 1487 /* Any upper-dword bits set? */
1488 if (MSD(dma_get_required_mask(&ha->pdev->dev)) &&
6a35528a 1489 !pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(64))) {
7524f9b9 1490 /* Ok, a 64bit DMA mask is applicable. */
1da177e4 1491 ha->flags.enable_64bit_addressing = 1;
fd34f556
AV		 1492 ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64;
1493 ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64;
7524f9b9 1494 return;
1da177e4 1495 }
1da177e4 1496 }
7524f9b9 1497
284901a9
YH		 1498 dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32));
1499 pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(32));
1da177e4
LT		 1500}
1501
fd34f556 1502static void
e315cd28 1503qla2x00_enable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1504{
1505 unsigned long flags = 0;
1506 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1507
1508 spin_lock_irqsave(&ha->hardware_lock, flags);
1509 ha->interrupts_on = 1;
1510 /* enable risc and host interrupts */
1511 WRT_REG_WORD(&reg->ictrl, ICR_EN_INT | ICR_EN_RISC);
1512 RD_REG_WORD(&reg->ictrl);
1513 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1514
1515}
1516
1517static void
e315cd28 1518qla2x00_disable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1519{
1520 unsigned long flags = 0;
1521 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1522
1523 spin_lock_irqsave(&ha->hardware_lock, flags);
1524 ha->interrupts_on = 0;
1525 /* disable risc and host interrupts */
1526 WRT_REG_WORD(&reg->ictrl, 0);
1527 RD_REG_WORD(&reg->ictrl);
1528 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1529}
1530
1531static void
e315cd28 1532qla24xx_enable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1533{
1534 unsigned long flags = 0;
1535 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1536
1537 spin_lock_irqsave(&ha->hardware_lock, flags);
1538 ha->interrupts_on = 1;
1539 WRT_REG_DWORD(&reg->ictrl, ICRX_EN_RISC_INT);
1540 RD_REG_DWORD(&reg->ictrl);
1541 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1542}
1543
1544static void
e315cd28 1545qla24xx_disable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1546{
1547 unsigned long flags = 0;
1548 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1549
124f85e6
AV		 1550 if (IS_NOPOLLING_TYPE(ha))
1551 return;
fd34f556
AV		 1552 spin_lock_irqsave(&ha->hardware_lock, flags);
1553 ha->interrupts_on = 0;
1554 WRT_REG_DWORD(&reg->ictrl, 0);
1555 RD_REG_DWORD(&reg->ictrl);
1556 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1557}
1558
1559static struct isp_operations qla2100_isp_ops = {
1560 .pci_config = qla2100_pci_config,
1561 .reset_chip = qla2x00_reset_chip,
1562 .chip_diag = qla2x00_chip_diag,
1563 .config_rings = qla2x00_config_rings,
1564 .reset_adapter = qla2x00_reset_adapter,
1565 .nvram_config = qla2x00_nvram_config,
1566 .update_fw_options = qla2x00_update_fw_options,
1567 .load_risc = qla2x00_load_risc,
1568 .pci_info_str = qla2x00_pci_info_str,
1569 .fw_version_str = qla2x00_fw_version_str,
1570 .intr_handler = qla2100_intr_handler,
1571 .enable_intrs = qla2x00_enable_intrs,
1572 .disable_intrs = qla2x00_disable_intrs,
1573 .abort_command = qla2x00_abort_command,
523ec773
AV		 1574 .target_reset = qla2x00_abort_target,
1575 .lun_reset = qla2x00_lun_reset,
fd34f556
AV		 1576 .fabric_login = qla2x00_login_fabric,
1577 .fabric_logout = qla2x00_fabric_logout,
1578 .calc_req_entries = qla2x00_calc_iocbs_32,
1579 .build_iocbs = qla2x00_build_scsi_iocbs_32,
1580 .prep_ms_iocb = qla2x00_prep_ms_iocb,
1581 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
1582 .read_nvram = qla2x00_read_nvram_data,
1583 .write_nvram = qla2x00_write_nvram_data,
1584 .fw_dump = qla2100_fw_dump,
1585 .beacon_on = NULL,
1586 .beacon_off = NULL,
1587 .beacon_blink = NULL,
1588 .read_optrom = qla2x00_read_optrom_data,
1589 .write_optrom = qla2x00_write_optrom_data,
1590 .get_flash_version = qla2x00_get_flash_version,
e315cd28 1591 .start_scsi = qla2x00_start_scsi,
a9083016 1592 .abort_isp = qla2x00_abort_isp,
fd34f556
AV		 1593};
1594
1595static struct isp_operations qla2300_isp_ops = {
1596 .pci_config = qla2300_pci_config,
1597 .reset_chip = qla2x00_reset_chip,
1598 .chip_diag = qla2x00_chip_diag,
1599 .config_rings = qla2x00_config_rings,
1600 .reset_adapter = qla2x00_reset_adapter,
1601 .nvram_config = qla2x00_nvram_config,
1602 .update_fw_options = qla2x00_update_fw_options,
1603 .load_risc = qla2x00_load_risc,
1604 .pci_info_str = qla2x00_pci_info_str,
1605 .fw_version_str = qla2x00_fw_version_str,
1606 .intr_handler = qla2300_intr_handler,
1607 .enable_intrs = qla2x00_enable_intrs,
1608 .disable_intrs = qla2x00_disable_intrs,
1609 .abort_command = qla2x00_abort_command,
523ec773
AV		 1610 .target_reset = qla2x00_abort_target,
1611 .lun_reset = qla2x00_lun_reset,
fd34f556
AV		 1612 .fabric_login = qla2x00_login_fabric,
1613 .fabric_logout = qla2x00_fabric_logout,
1614 .calc_req_entries = qla2x00_calc_iocbs_32,
1615 .build_iocbs = qla2x00_build_scsi_iocbs_32,
1616 .prep_ms_iocb = qla2x00_prep_ms_iocb,
1617 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
1618 .read_nvram = qla2x00_read_nvram_data,
1619 .write_nvram = qla2x00_write_nvram_data,
1620 .fw_dump = qla2300_fw_dump,
1621 .beacon_on = qla2x00_beacon_on,
1622 .beacon_off = qla2x00_beacon_off,
1623 .beacon_blink = qla2x00_beacon_blink,
1624 .read_optrom = qla2x00_read_optrom_data,
1625 .write_optrom = qla2x00_write_optrom_data,
1626 .get_flash_version = qla2x00_get_flash_version,
e315cd28 1627 .start_scsi = qla2x00_start_scsi,
a9083016 1628 .abort_isp = qla2x00_abort_isp,
fd34f556
AV		 1629};
1630
1631static struct isp_operations qla24xx_isp_ops = {
1632 .pci_config = qla24xx_pci_config,
1633 .reset_chip = qla24xx_reset_chip,
1634 .chip_diag = qla24xx_chip_diag,
1635 .config_rings = qla24xx_config_rings,
1636 .reset_adapter = qla24xx_reset_adapter,
1637 .nvram_config = qla24xx_nvram_config,
1638 .update_fw_options = qla24xx_update_fw_options,
1639 .load_risc = qla24xx_load_risc,
1640 .pci_info_str = qla24xx_pci_info_str,
1641 .fw_version_str = qla24xx_fw_version_str,
1642 .intr_handler = qla24xx_intr_handler,
1643 .enable_intrs = qla24xx_enable_intrs,
1644 .disable_intrs = qla24xx_disable_intrs,
1645 .abort_command = qla24xx_abort_command,
523ec773
AV		 1646 .target_reset = qla24xx_abort_target,
1647 .lun_reset = qla24xx_lun_reset,
fd34f556
AV		 1648 .fabric_login = qla24xx_login_fabric,
1649 .fabric_logout = qla24xx_fabric_logout,
1650 .calc_req_entries = NULL,
1651 .build_iocbs = NULL,
1652 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1653 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1654 .read_nvram = qla24xx_read_nvram_data,
1655 .write_nvram = qla24xx_write_nvram_data,
1656 .fw_dump = qla24xx_fw_dump,
1657 .beacon_on = qla24xx_beacon_on,
1658 .beacon_off = qla24xx_beacon_off,
1659 .beacon_blink = qla24xx_beacon_blink,
1660 .read_optrom = qla24xx_read_optrom_data,
1661 .write_optrom = qla24xx_write_optrom_data,
1662 .get_flash_version = qla24xx_get_flash_version,
e315cd28 1663 .start_scsi = qla24xx_start_scsi,
a9083016 1664 .abort_isp = qla2x00_abort_isp,
fd34f556
AV		 1665};
1666
c3a2f0df
AV		 1667static struct isp_operations qla25xx_isp_ops = {
1668 .pci_config = qla25xx_pci_config,
1669 .reset_chip = qla24xx_reset_chip,
1670 .chip_diag = qla24xx_chip_diag,
1671 .config_rings = qla24xx_config_rings,
1672 .reset_adapter = qla24xx_reset_adapter,
1673 .nvram_config = qla24xx_nvram_config,
1674 .update_fw_options = qla24xx_update_fw_options,
1675 .load_risc = qla24xx_load_risc,
1676 .pci_info_str = qla24xx_pci_info_str,
1677 .fw_version_str = qla24xx_fw_version_str,
1678 .intr_handler = qla24xx_intr_handler,
1679 .enable_intrs = qla24xx_enable_intrs,
1680 .disable_intrs = qla24xx_disable_intrs,
1681 .abort_command = qla24xx_abort_command,
523ec773
AV		 1682 .target_reset = qla24xx_abort_target,
1683 .lun_reset = qla24xx_lun_reset,
c3a2f0df
AV		 1684 .fabric_login = qla24xx_login_fabric,
1685 .fabric_logout = qla24xx_fabric_logout,
1686 .calc_req_entries = NULL,
1687 .build_iocbs = NULL,
1688 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1689 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1690 .read_nvram = qla25xx_read_nvram_data,
1691 .write_nvram = qla25xx_write_nvram_data,
1692 .fw_dump = qla25xx_fw_dump,
1693 .beacon_on = qla24xx_beacon_on,
1694 .beacon_off = qla24xx_beacon_off,
1695 .beacon_blink = qla24xx_beacon_blink,
338c9161 1696 .read_optrom = qla25xx_read_optrom_data,
c3a2f0df
AV		 1697 .write_optrom = qla24xx_write_optrom_data,
1698 .get_flash_version = qla24xx_get_flash_version,
bad75002 1699 .start_scsi = qla24xx_dif_start_scsi,
a9083016 1700 .abort_isp = qla2x00_abort_isp,
c3a2f0df
AV		 1701};
1702
3a03eb79
AV		 1703static struct isp_operations qla81xx_isp_ops = {
1704 .pci_config = qla25xx_pci_config,
1705 .reset_chip = qla24xx_reset_chip,
1706 .chip_diag = qla24xx_chip_diag,
1707 .config_rings = qla24xx_config_rings,
1708 .reset_adapter = qla24xx_reset_adapter,
1709 .nvram_config = qla81xx_nvram_config,
1710 .update_fw_options = qla81xx_update_fw_options,
eaac30be 1711 .load_risc = qla81xx_load_risc,
3a03eb79
AV		 1712 .pci_info_str = qla24xx_pci_info_str,
1713 .fw_version_str = qla24xx_fw_version_str,
1714 .intr_handler = qla24xx_intr_handler,
1715 .enable_intrs = qla24xx_enable_intrs,
1716 .disable_intrs = qla24xx_disable_intrs,
1717 .abort_command = qla24xx_abort_command,
1718 .target_reset = qla24xx_abort_target,
1719 .lun_reset = qla24xx_lun_reset,
1720 .fabric_login = qla24xx_login_fabric,
1721 .fabric_logout = qla24xx_fabric_logout,
1722 .calc_req_entries = NULL,
1723 .build_iocbs = NULL,
1724 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1725 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
3d79038f
AV		 1726 .read_nvram = NULL,
1727 .write_nvram = NULL,
3a03eb79
AV		 1728 .fw_dump = qla81xx_fw_dump,
1729 .beacon_on = qla24xx_beacon_on,
1730 .beacon_off = qla24xx_beacon_off,
1731 .beacon_blink = qla24xx_beacon_blink,
1732 .read_optrom = qla25xx_read_optrom_data,
1733 .write_optrom = qla24xx_write_optrom_data,
1734 .get_flash_version = qla24xx_get_flash_version,
ba77ef53 1735 .start_scsi = qla24xx_dif_start_scsi,
a9083016
GM		 1736 .abort_isp = qla2x00_abort_isp,
1737};
1738
1739static struct isp_operations qla82xx_isp_ops = {
1740 .pci_config = qla82xx_pci_config,
1741 .reset_chip = qla82xx_reset_chip,
1742 .chip_diag = qla24xx_chip_diag,
1743 .config_rings = qla82xx_config_rings,
1744 .reset_adapter = qla24xx_reset_adapter,
1745 .nvram_config = qla81xx_nvram_config,
1746 .update_fw_options = qla24xx_update_fw_options,
1747 .load_risc = qla82xx_load_risc,
1748 .pci_info_str = qla82xx_pci_info_str,
1749 .fw_version_str = qla24xx_fw_version_str,
1750 .intr_handler = qla82xx_intr_handler,
1751 .enable_intrs = qla82xx_enable_intrs,
1752 .disable_intrs = qla82xx_disable_intrs,
1753 .abort_command = qla24xx_abort_command,
1754 .target_reset = qla24xx_abort_target,
1755 .lun_reset = qla24xx_lun_reset,
1756 .fabric_login = qla24xx_login_fabric,
1757 .fabric_logout = qla24xx_fabric_logout,
1758 .calc_req_entries = NULL,
1759 .build_iocbs = NULL,
1760 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1761 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1762 .read_nvram = qla24xx_read_nvram_data,
1763 .write_nvram = qla24xx_write_nvram_data,
1764 .fw_dump = qla24xx_fw_dump,
999916dc
SK		 1765 .beacon_on = qla82xx_beacon_on,
1766 .beacon_off = qla82xx_beacon_off,
1767 .beacon_blink = NULL,
a9083016
GM		 1768 .read_optrom = qla82xx_read_optrom_data,
1769 .write_optrom = qla82xx_write_optrom_data,
1770 .get_flash_version = qla24xx_get_flash_version,
1771 .start_scsi = qla82xx_start_scsi,
1772 .abort_isp = qla82xx_abort_isp,
3a03eb79
AV		 1773};
1774
ea5b6382 1775static inline void
e315cd28 1776qla2x00_set_isp_flags(struct qla_hw_data *ha)
ea5b6382 1777{
1778 ha->device_type = DT_EXTENDED_IDS;
1779 switch (ha->pdev->device) {
1780 case PCI_DEVICE_ID_QLOGIC_ISP2100:
1781 ha->device_type |= DT_ISP2100;
1782 ha->device_type &= ~DT_EXTENDED_IDS;
441d1072 1783 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
ea5b6382 1784 break;
1785 case PCI_DEVICE_ID_QLOGIC_ISP2200:
1786 ha->device_type |= DT_ISP2200;
1787 ha->device_type &= ~DT_EXTENDED_IDS;
441d1072 1788 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
ea5b6382 1789 break;
1790 case PCI_DEVICE_ID_QLOGIC_ISP2300:
1791 ha->device_type |= DT_ISP2300;
4a59f71d 1792 ha->device_type |= DT_ZIO_SUPPORTED;
441d1072 1793 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 1794 break;
1795 case PCI_DEVICE_ID_QLOGIC_ISP2312:
1796 ha->device_type |= DT_ISP2312;
4a59f71d 1797 ha->device_type |= DT_ZIO_SUPPORTED;
441d1072 1798 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 1799 break;
1800 case PCI_DEVICE_ID_QLOGIC_ISP2322:
1801 ha->device_type |= DT_ISP2322;
4a59f71d 1802 ha->device_type |= DT_ZIO_SUPPORTED;
ea5b6382 1803 if (ha->pdev->subsystem_vendor == 0x1028 &&
1804 ha->pdev->subsystem_device == 0x0170)
1805 ha->device_type |= DT_OEM_001;
441d1072 1806 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 1807 break;
1808 case PCI_DEVICE_ID_QLOGIC_ISP6312:
1809 ha->device_type |= DT_ISP6312;
441d1072 1810 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 1811 break;
1812 case PCI_DEVICE_ID_QLOGIC_ISP6322:
1813 ha->device_type |= DT_ISP6322;
441d1072 1814 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 1815 break;
1816 case PCI_DEVICE_ID_QLOGIC_ISP2422:
1817 ha->device_type |= DT_ISP2422;
4a59f71d 1818 ha->device_type |= DT_ZIO_SUPPORTED;
e428924c 1819 ha->device_type |= DT_FWI2;
c76f2c01 1820 ha->device_type |= DT_IIDMA;
441d1072 1821 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 1822 break;
1823 case PCI_DEVICE_ID_QLOGIC_ISP2432:
1824 ha->device_type |= DT_ISP2432;
4a59f71d 1825 ha->device_type |= DT_ZIO_SUPPORTED;
e428924c 1826 ha->device_type |= DT_FWI2;
c76f2c01 1827 ha->device_type |= DT_IIDMA;
441d1072 1828 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 1829 break;
4d4df193
HK		 1830 case PCI_DEVICE_ID_QLOGIC_ISP8432:
1831 ha->device_type |= DT_ISP8432;
1832 ha->device_type |= DT_ZIO_SUPPORTED;
1833 ha->device_type |= DT_FWI2;
1834 ha->device_type |= DT_IIDMA;
1835 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
1836 break;
044cc6c8 1837 case PCI_DEVICE_ID_QLOGIC_ISP5422:
1838 ha->device_type |= DT_ISP5422;
e428924c 1839 ha->device_type |= DT_FWI2;
441d1072 1840 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 1841 break;
044cc6c8 1842 case PCI_DEVICE_ID_QLOGIC_ISP5432:
1843 ha->device_type |= DT_ISP5432;
e428924c 1844 ha->device_type |= DT_FWI2;
441d1072 1845 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 1846 break;
c3a2f0df
AV		 1847 case PCI_DEVICE_ID_QLOGIC_ISP2532:
1848 ha->device_type |= DT_ISP2532;
1849 ha->device_type |= DT_ZIO_SUPPORTED;
1850 ha->device_type |= DT_FWI2;
1851 ha->device_type |= DT_IIDMA;
441d1072 1852 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 1853 break;
3a03eb79
AV		 1854 case PCI_DEVICE_ID_QLOGIC_ISP8001:
1855 ha->device_type |= DT_ISP8001;
1856 ha->device_type |= DT_ZIO_SUPPORTED;
1857 ha->device_type |= DT_FWI2;
1858 ha->device_type |= DT_IIDMA;
1859 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
1860 break;
a9083016
GM		 1861 case PCI_DEVICE_ID_QLOGIC_ISP8021:
1862 ha->device_type |= DT_ISP8021;
1863 ha->device_type |= DT_ZIO_SUPPORTED;
1864 ha->device_type |= DT_FWI2;
1865 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
1866 /* Initialize 82XX ISP flags */
1867 qla82xx_init_flags(ha);
1868 break;
ea5b6382 1869 }
e5b68a61 1870
a9083016
GM		 1871 if (IS_QLA82XX(ha))
1872 ha->port_no = !(ha->portnum & 1);
1873 else
1874 /* Get adapter physical port no from interrupt pin register. */
1875 pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no);
1876
e5b68a61
AC		 1877 if (ha->port_no & 1)
1878 ha->flags.port0 = 1;
1879 else
1880 ha->flags.port0 = 0;
7c3df132
SK		 1881 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b,
1882 "device_type=0x%x port=%d fw_srisc_address=%p.\n",
1883 ha->device_type, ha->flags.port0, ha->fw_srisc_address);
ea5b6382 1884}
1885
1da177e4 1886static int
e315cd28 1887qla2x00_iospace_config(struct qla_hw_data *ha)
1da177e4 1888{
3776541d 1889 resource_size_t pio;
73208dfd 1890 uint16_t msix;
68ca949c 1891 int cpus;
1da177e4 1892
a9083016
GM		 1893 if (IS_QLA82XX(ha))
1894 return qla82xx_iospace_config(ha);
1895
285d0321
AV		 1896 if (pci_request_selected_regions(ha->pdev, ha->bars,
1897 QLA2XXX_DRIVER_NAME)) {
7c3df132
SK		 1898 ql_log_pci(ql_log_fatal, ha->pdev, 0x0011,
1899 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
285d0321 1900 pci_name(ha->pdev));
285d0321
AV		 1901 goto iospace_error_exit;
1902 }
1903 if (!(ha->bars & 1))
1904 goto skip_pio;
1905
1da177e4
LT		 1906 /* We only need PIO for Flash operations on ISP2312 v2 chips. */
1907 pio = pci_resource_start(ha->pdev, 0);
3776541d
AV		 1908 if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) {
1909 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
7c3df132
SK		 1910 ql_log_pci(ql_log_warn, ha->pdev, 0x0012,
1911 "Invalid pci I/O region size (%s).\n",
1912 pci_name(ha->pdev));
1da177e4
LT		 1913 pio = 0;
1914 }
1915 } else {
7c3df132
SK		 1916 ql_log_pci(ql_log_warn, ha->pdev, 0x0013,
1917 "Region #0 no a PIO resource (%s).\n",
1da177e4
LT		 1918 pci_name(ha->pdev));
1919 pio = 0;
1920 }
285d0321 1921 ha->pio_address = pio;
7c3df132
SK		 1922 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014,
1923 "PIO address=%p.\n",
1924 ha->pio_address);
1da177e4 1925
285d0321 1926skip_pio:
1da177e4 1927 /* Use MMIO operations for all accesses. */
3776541d 1928 if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) {
7c3df132
SK		 1929 ql_log_pci(ql_log_fatal, ha->pdev, 0x0015,
1930 "Region #1 not an MMIO resource (%s), aborting.\n",
1da177e4
LT		 1931 pci_name(ha->pdev));
1932 goto iospace_error_exit;
1933 }
3776541d 1934 if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) {
7c3df132
SK		 1935 ql_log_pci(ql_log_fatal, ha->pdev, 0x0016,
1936 "Invalid PCI mem region size (%s), aborting.\n",
1937 pci_name(ha->pdev));
1da177e4
LT		 1938 goto iospace_error_exit;
1939 }
1940
3776541d 1941 ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN);
1da177e4 1942 if (!ha->iobase) {
7c3df132
SK		 1943 ql_log_pci(ql_log_fatal, ha->pdev, 0x0017,
1944 "Cannot remap MMIO (%s), aborting.\n",
1945 pci_name(ha->pdev));
1da177e4
LT		 1946 goto iospace_error_exit;
1947 }
1948
73208dfd 1949 /* Determine queue resources */
2afa19a9 1950 ha->max_req_queues = ha->max_rsp_queues = 1;
d84a47c2
MH		 1951 if ((ql2xmaxqueues <= 1 && !ql2xmultique_tag) ||
1952 (ql2xmaxqueues > 1 && ql2xmultique_tag) ||
2afa19a9 1953 (!IS_QLA25XX(ha) && !IS_QLA81XX(ha)))
17d98630 1954 goto mqiobase_exit;
d84a47c2 1955
17d98630
AC		 1956 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3),
1957 pci_resource_len(ha->pdev, 3));
1958 if (ha->mqiobase) {
7c3df132
SK		 1959 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018,
1960 "MQIO Base=%p.\n", ha->mqiobase);
17d98630
AC		 1961 /* Read MSIX vector size of the board */
1962 pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix);
1963 ha->msix_count = msix;
68ca949c
AC		 1964 /* Max queues are bounded by available msix vectors */
1965 /* queue 0 uses two msix vectors */
1966 if (ql2xmultique_tag) {
1967 cpus = num_online_cpus();
27dc9c5a 1968 ha->max_rsp_queues = (ha->msix_count - 1 > cpus) ?
68ca949c
AC		 1969 (cpus + 1) : (ha->msix_count - 1);
1970 ha->max_req_queues = 2;
1971 } else if (ql2xmaxqueues > 1) {
2afa19a9 1972 ha->max_req_queues = ql2xmaxqueues > QLA_MQ_SIZE ?
7c3df132
SK		 1973 QLA_MQ_SIZE : ql2xmaxqueues;
1974 ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc008,
1975 "QoS mode set, max no of request queues:%d.\n",
1976 ha->max_req_queues);
1977 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0019,
1978 "QoS mode set, max no of request queues:%d.\n",
1979 ha->max_req_queues);
2afa19a9 1980 }
7c3df132
SK		 1981 ql_log_pci(ql_log_info, ha->pdev, 0x001a,
1982 "MSI-X vector count: %d.\n", msix);
2afa19a9 1983 } else
7c3df132
SK		 1984 ql_log_pci(ql_log_info, ha->pdev, 0x001b,
1985 "BAR 3 not enabled.\n");
17d98630
AC		 1986
1987mqiobase_exit:
2afa19a9 1988 ha->msix_count = ha->max_rsp_queues + 1;
7c3df132
SK		 1989 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c,
1990 "MSIX Count:%d.\n", ha->msix_count);
1da177e4
LT		 1991 return (0);
1992
1993iospace_error_exit:
1994 return (-ENOMEM);
1995}
1996
1e99e33a
AV		 1997static void
1998qla2xxx_scan_start(struct Scsi_Host *shost)
1999{
e315cd28 2000 scsi_qla_host_t *vha = shost_priv(shost);
1e99e33a 2001
cbc8eb67
AV		 2002 if (vha->hw->flags.running_gold_fw)
2003 return;
2004
e315cd28
AC		 2005 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
2006 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
2007 set_bit(RSCN_UPDATE, &vha->dpc_flags);
2008 set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags);
1e99e33a
AV		 2009}
2010
2011static int
2012qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time)
2013{
e315cd28 2014 scsi_qla_host_t *vha = shost_priv(shost);
1e99e33a 2015
e315cd28 2016 if (!vha->host)
1e99e33a 2017 return 1;
e315cd28 2018 if (time > vha->hw->loop_reset_delay * HZ)
1e99e33a
AV		 2019 return 1;
2020
e315cd28 2021 return atomic_read(&vha->loop_state) == LOOP_READY;
1e99e33a
AV		 2022}
2023
1da177e4
LT		 2024/*
2025 * PCI driver interface
2026 */
7ee61397
AV		 2027static int __devinit
2028qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
1da177e4 2029{
a1541d5a 2030 int ret = -ENODEV;
1da177e4 2031 struct Scsi_Host *host;
e315cd28
AC		 2032 scsi_qla_host_t *base_vha = NULL;
2033 struct qla_hw_data *ha;
29856e28 2034 char pci_info[30];
1da177e4 2035 char fw_str[30];
5433383e 2036 struct scsi_host_template *sht;
c51da4ec 2037 int bars, max_id, mem_only = 0;
e315cd28 2038 uint16_t req_length = 0, rsp_length = 0;
73208dfd
AC		 2039 struct req_que *req = NULL;
2040 struct rsp_que *rsp = NULL;
1da177e4 2041
285d0321 2042 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO);
a5326f86 2043 sht = &qla2xxx_driver_template;
5433383e 2044 if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 ||
8bc69e7d 2045 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 ||
4d4df193 2046 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 ||
8bc69e7d 2047 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 ||
c3a2f0df 2048 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 ||
3a03eb79 2049 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 ||
a9083016
GM		 2050 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 ||
2051 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021) {
285d0321 2052 bars = pci_select_bars(pdev, IORESOURCE_MEM);
09483916 2053 mem_only = 1;
7c3df132
SK		 2054 ql_dbg_pci(ql_dbg_init, pdev, 0x0007,
2055 "Mem only adapter.\n");
285d0321 2056 }
7c3df132
SK		 2057 ql_dbg_pci(ql_dbg_init, pdev, 0x0008,
2058 "Bars=%d.\n", bars);
285d0321 2059
09483916
BH		 2060 if (mem_only) {
2061 if (pci_enable_device_mem(pdev))
2062 goto probe_out;
2063 } else {
2064 if (pci_enable_device(pdev))
2065 goto probe_out;
2066 }
285d0321 2067
0927678f
JB		 2068 /* This may fail but that's ok */
2069 pci_enable_pcie_error_reporting(pdev);
285d0321 2070
e315cd28
AC		 2071 ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL);
2072 if (!ha) {
7c3df132
SK		 2073 ql_log_pci(ql_log_fatal, pdev, 0x0009,
2074 "Unable to allocate memory for ha.\n");
e315cd28 2075 goto probe_out;
1da177e4 2076 }
7c3df132
SK		 2077 ql_dbg_pci(ql_dbg_init, pdev, 0x000a,
2078 "Memory allocated for ha=%p.\n", ha);
e315cd28 2079 ha->pdev = pdev;
1da177e4
LT		 2080
2081 /* Clear our data area */
285d0321 2082 ha->bars = bars;
09483916 2083 ha->mem_only = mem_only;
df4bf0bb 2084 spin_lock_init(&ha->hardware_lock);
339aa70e 2085 spin_lock_init(&ha->vport_slock);
1da177e4 2086
ea5b6382 2087 /* Set ISP-type information. */
2088 qla2x00_set_isp_flags(ha);
ca79cf66
DG		 2089
2090 /* Set EEH reset type to fundamental if required by hba */
2091 if ( IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha)) {
2092 pdev->needs_freset = 1;
ca79cf66
DG		 2093 }
2094
1da177e4
LT		 2095 /* Configure PCI I/O space */
2096 ret = qla2x00_iospace_config(ha);
a1541d5a 2097 if (ret)
e315cd28 2098 goto probe_hw_failed;
1da177e4 2099
7c3df132
SK		 2100 ql_log_pci(ql_log_info, pdev, 0x001d,
2101 "Found an ISP%04X irq %d iobase 0x%p.\n",
2102 pdev->device, pdev->irq, ha->iobase);
1da177e4 2103 ha->prev_topology = 0;
fca29703 2104 ha->init_cb_size = sizeof(init_cb_t);
d8b45213 2105 ha->link_data_rate = PORT_SPEED_UNKNOWN;
854165f4 2106 ha->optrom_size = OPTROM_SIZE_2300;
1da177e4 2107
abbd8870 2108 /* Assign ISP specific operations. */
e315cd28 2109 max_id = MAX_TARGETS_2200;
1da177e4 2110 if (IS_QLA2100(ha)) {
e315cd28 2111 max_id = MAX_TARGETS_2100;
1da177e4 2112 ha->mbx_count = MAILBOX_REGISTER_COUNT_2100;
e315cd28
AC		 2113 req_length = REQUEST_ENTRY_CNT_2100;
2114 rsp_length = RESPONSE_ENTRY_CNT_2100;
2115 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
abbd8870 2116 ha->gid_list_info_size = 4;
3a03eb79
AV		 2117 ha->flash_conf_off = ~0;
2118 ha->flash_data_off = ~0;
2119 ha->nvram_conf_off = ~0;
2120 ha->nvram_data_off = ~0;
fd34f556 2121 ha->isp_ops = &qla2100_isp_ops;
1da177e4 2122 } else if (IS_QLA2200(ha)) {
1da177e4 2123 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2124 req_length = REQUEST_ENTRY_CNT_2200;
2125 rsp_length = RESPONSE_ENTRY_CNT_2100;
2126 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
abbd8870 2127 ha->gid_list_info_size = 4;
3a03eb79
AV		 2128 ha->flash_conf_off = ~0;
2129 ha->flash_data_off = ~0;
2130 ha->nvram_conf_off = ~0;
2131 ha->nvram_data_off = ~0;
fd34f556 2132 ha->isp_ops = &qla2100_isp_ops;
fca29703 2133 } else if (IS_QLA23XX(ha)) {
1da177e4 2134 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2135 req_length = REQUEST_ENTRY_CNT_2200;
2136 rsp_length = RESPONSE_ENTRY_CNT_2300;
2137 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
abbd8870 2138 ha->gid_list_info_size = 6;
854165f4 2139 if (IS_QLA2322(ha) || IS_QLA6322(ha))
2140 ha->optrom_size = OPTROM_SIZE_2322;
3a03eb79
AV		 2141 ha->flash_conf_off = ~0;
2142 ha->flash_data_off = ~0;
2143 ha->nvram_conf_off = ~0;
2144 ha->nvram_data_off = ~0;
fd34f556 2145 ha->isp_ops = &qla2300_isp_ops;
4d4df193 2146 } else if (IS_QLA24XX_TYPE(ha)) {
fca29703 2147 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2148 req_length = REQUEST_ENTRY_CNT_24XX;
2149 rsp_length = RESPONSE_ENTRY_CNT_2300;
2150 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2c3dfe3f 2151 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
fca29703 2152 ha->gid_list_info_size = 8;
854165f4 2153 ha->optrom_size = OPTROM_SIZE_24XX;
73208dfd 2154 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX;
fd34f556 2155 ha->isp_ops = &qla24xx_isp_ops;
3a03eb79
AV		 2156 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2157 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2158 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2159 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
c3a2f0df 2160 } else if (IS_QLA25XX(ha)) {
c3a2f0df 2161 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2162 req_length = REQUEST_ENTRY_CNT_24XX;
2163 rsp_length = RESPONSE_ENTRY_CNT_2300;
2164 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
c3a2f0df 2165 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
c3a2f0df
AV		 2166 ha->gid_list_info_size = 8;
2167 ha->optrom_size = OPTROM_SIZE_25XX;
73208dfd 2168 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
c3a2f0df 2169 ha->isp_ops = &qla25xx_isp_ops;
3a03eb79
AV		 2170 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2171 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2172 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2173 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
2174 } else if (IS_QLA81XX(ha)) {
2175 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2176 req_length = REQUEST_ENTRY_CNT_24XX;
2177 rsp_length = RESPONSE_ENTRY_CNT_2300;
2178 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2179 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2180 ha->gid_list_info_size = 8;
2181 ha->optrom_size = OPTROM_SIZE_81XX;
40859ae5 2182 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3a03eb79
AV		 2183 ha->isp_ops = &qla81xx_isp_ops;
2184 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2185 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2186 ha->nvram_conf_off = ~0;
2187 ha->nvram_data_off = ~0;
a9083016
GM		 2188 } else if (IS_QLA82XX(ha)) {
2189 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2190 req_length = REQUEST_ENTRY_CNT_82XX;
2191 rsp_length = RESPONSE_ENTRY_CNT_82XX;
2192 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2193 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2194 ha->gid_list_info_size = 8;
2195 ha->optrom_size = OPTROM_SIZE_82XX;
087c621e 2196 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
a9083016
GM		 2197 ha->isp_ops = &qla82xx_isp_ops;
2198 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2199 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2200 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2201 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
1da177e4 2202 }
7c3df132
SK		 2203 ql_dbg_pci(ql_dbg_init, pdev, 0x001e,
2204 "mbx_count=%d, req_length=%d, "
2205 "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, "
2206 "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, .\n",
2207 ha->mbx_count, req_length, rsp_length, ha->max_loop_id,
2208 ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size,
2209 ha->nvram_npiv_size);
2210 ql_dbg_pci(ql_dbg_init, pdev, 0x001f,
2211 "isp_ops=%p, flash_conf_off=%d, "
2212 "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n",
2213 ha->isp_ops, ha->flash_conf_off, ha->flash_data_off,
2214 ha->nvram_conf_off, ha->nvram_data_off);
6c2f527c 2215 mutex_init(&ha->vport_lock);
0b05a1f0
MB		 2216 init_completion(&ha->mbx_cmd_comp);
2217 complete(&ha->mbx_cmd_comp);
2218 init_completion(&ha->mbx_intr_comp);
23f2ebd1 2219 init_completion(&ha->dcbx_comp);
1da177e4 2220
2c3dfe3f 2221 set_bit(0, (unsigned long *) ha->vp_idx_map);
1da177e4 2222
53303c42 2223 qla2x00_config_dma_addressing(ha);
7c3df132
SK		 2224 ql_dbg_pci(ql_dbg_init, pdev, 0x0020,
2225 "64 Bit addressing is %s.\n",
2226 ha->flags.enable_64bit_addressing ? "enable" :
2227 "disable");
73208dfd 2228 ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp);
e315cd28 2229 if (!ret) {
7c3df132
SK		 2230 ql_log_pci(ql_log_fatal, pdev, 0x0031,
2231 "Failed to allocate memory for adapter, aborting.\n");
1da177e4 2232
e315cd28
AC		 2233 goto probe_hw_failed;
2234 }
2235
73208dfd 2236 req->max_q_depth = MAX_Q_DEPTH;
e315cd28 2237 if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU)
73208dfd
AC		 2238 req->max_q_depth = ql2xmaxqdepth;
2239
e315cd28
AC		 2240
2241 base_vha = qla2x00_create_host(sht, ha);
2242 if (!base_vha) {
a1541d5a 2243 ret = -ENOMEM;
6e9f21f3 2244 qla2x00_mem_free(ha);
2afa19a9
AC		 2245 qla2x00_free_req_que(ha, req);
2246 qla2x00_free_rsp_que(ha, rsp);
e315cd28 2247 goto probe_hw_failed;
1da177e4
LT		 2248 }
2249
e315cd28
AC		 2250 pci_set_drvdata(pdev, base_vha);
2251
e315cd28 2252 host = base_vha->host;
2afa19a9 2253 base_vha->req = req;
73208dfd
AC		 2254 host->can_queue = req->length + 128;
2255 if (IS_QLA2XXX_MIDTYPE(ha))
e315cd28 2256 base_vha->mgmt_svr_loop_id = 10 + base_vha->vp_idx;
73208dfd 2257 else
e315cd28
AC		 2258 base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER +
2259 base_vha->vp_idx;
58548cb5
GM		 2260
2261 /* Set the SG table size based on ISP type */
2262 if (!IS_FWI2_CAPABLE(ha)) {
2263 if (IS_QLA2100(ha))
2264 host->sg_tablesize = 32;
2265 } else {
2266 if (!IS_QLA82XX(ha))
2267 host->sg_tablesize = QLA_SG_ALL;
2268 }
7c3df132
SK		 2269 ql_dbg(ql_dbg_init, base_vha, 0x0032,
2270 "can_queue=%d, req=%p, "
2271 "mgmt_svr_loop_id=%d, sg_tablesize=%d.\n",
2272 host->can_queue, base_vha->req,
2273 base_vha->mgmt_svr_loop_id, host->sg_tablesize);
e315cd28
AC		 2274 host->max_id = max_id;
2275 host->this_id = 255;
2276 host->cmd_per_lun = 3;
2277 host->unique_id = host->host_no;
e02587d7 2278 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif)
0c470874
AE		 2279 host->max_cmd_len = 32;
2280 else
2281 host->max_cmd_len = MAX_CMDSZ;
e315cd28 2282 host->max_channel = MAX_BUSES - 1;
82515920 2283 host->max_lun = ql2xmaxlun;
e315cd28 2284 host->transportt = qla2xxx_transport_template;
9a069e19 2285 sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC);
e315cd28 2286
7c3df132
SK		 2287 ql_dbg(ql_dbg_init, base_vha, 0x0033,
2288 "max_id=%d this_id=%d "
2289 "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d "
2290 "max_lun=%d transportt=%p, vendor_id=%d.\n", host->max_id,
2291 host->this_id, host->cmd_per_lun, host->unique_id,
2292 host->max_cmd_len, host->max_channel, host->max_lun,
2293 host->transportt, sht->vendor_id);
2294
73208dfd
AC		 2295 /* Set up the irqs */
2296 ret = qla2x00_request_irqs(ha, rsp);
2297 if (ret)
6e9f21f3 2298 goto probe_init_failed;
90a86fc0
JC		 2299
2300 pci_save_state(pdev);
2301
73208dfd 2302 /* Alloc arrays of request and response ring ptrs */
7163ea81 2303que_init:
73208dfd 2304 if (!qla2x00_alloc_queues(ha)) {
7c3df132
SK		 2305 ql_log(ql_log_fatal, base_vha, 0x003d,
2306 "Failed to allocate memory for queue pointers.. aborting.\n");
6e9f21f3 2307 goto probe_init_failed;
73208dfd 2308 }
a9083016 2309
73208dfd
AC		 2310 ha->rsp_q_map[0] = rsp;
2311 ha->req_q_map[0] = req;
2afa19a9
AC		 2312 rsp->req = req;
2313 req->rsp = rsp;
2314 set_bit(0, ha->req_qid_map);
2315 set_bit(0, ha->rsp_qid_map);
08029990
AV		 2316 /* FWI2-capable only. */
2317 req->req_q_in = &ha->iobase->isp24.req_q_in;
2318 req->req_q_out = &ha->iobase->isp24.req_q_out;
2319 rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in;
2320 rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out;
17d98630 2321 if (ha->mqenable) {
08029990
AV		 2322 req->req_q_in = &ha->mqiobase->isp25mq.req_q_in;
2323 req->req_q_out = &ha->mqiobase->isp25mq.req_q_out;
2324 rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in;
2325 rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out;
17d98630
AC		 2326 }
2327
a9083016
GM		 2328 if (IS_QLA82XX(ha)) {
2329 req->req_q_out = &ha->iobase->isp82.req_q_out[0];
2330 rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0];
2331 rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0];
2332 }
2333
7c3df132
SK		 2334 ql_dbg(ql_dbg_multiq, base_vha, 0xc009,
2335 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
2336 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
2337 ql_dbg(ql_dbg_multiq, base_vha, 0xc00a,
2338 "req->req_q_in=%p req->req_q_out=%p "
2339 "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
2340 req->req_q_in, req->req_q_out,
2341 rsp->rsp_q_in, rsp->rsp_q_out);
2342 ql_dbg(ql_dbg_init, base_vha, 0x003e,
2343 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
2344 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
2345 ql_dbg(ql_dbg_init, base_vha, 0x003f,
2346 "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
2347 req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out);
1da177e4 2348
7c3df132
SK		 2349 if (qla2x00_initialize_adapter(base_vha)) {
2350 ql_log(ql_log_fatal, base_vha, 0x00d6,
2351 "Failed to initialize adapter - Adapter flags %x.\n",
2352 base_vha->device_flags);
1da177e4 2353
a9083016
GM		 2354 if (IS_QLA82XX(ha)) {
2355 qla82xx_idc_lock(ha);
2356 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
2357 QLA82XX_DEV_FAILED);
2358 qla82xx_idc_unlock(ha);
7c3df132
SK		 2359 ql_log(ql_log_fatal, base_vha, 0x00d7,
2360 "HW State: FAILED.\n");
a9083016
GM		 2361 }
2362
a1541d5a 2363 ret = -ENODEV;
1da177e4
LT		 2364 goto probe_failed;
2365 }
2366
7163ea81
AC		 2367 if (ha->mqenable) {
2368 if (qla25xx_setup_mode(base_vha)) {
7c3df132
SK		 2369 ql_log(ql_log_warn, base_vha, 0x00ec,
2370 "Failed to create queues, falling back to single queue mode.\n");
7163ea81
AC		 2371 goto que_init;
2372 }
2373 }
68ca949c 2374
cbc8eb67
AV		 2375 if (ha->flags.running_gold_fw)
2376 goto skip_dpc;
2377
1da177e4
LT		 2378 /*
2379 * Startup the kernel thread for this host adapter
2380 */
39a11240 2381 ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha,
7c3df132 2382 "%s_dpc", base_vha->host_str);
39a11240 2383 if (IS_ERR(ha->dpc_thread)) {
7c3df132
SK		 2384 ql_log(ql_log_fatal, base_vha, 0x00ed,
2385 "Failed to start DPC thread.\n");
39a11240 2386 ret = PTR_ERR(ha->dpc_thread);
1da177e4
LT		 2387 goto probe_failed;
2388 }
7c3df132
SK		 2389 ql_dbg(ql_dbg_init, base_vha, 0x00ee,
2390 "DPC thread started successfully.\n");
1da177e4 2391
cbc8eb67 2392skip_dpc:
e315cd28
AC		 2393 list_add_tail(&base_vha->list, &ha->vp_list);
2394 base_vha->host->irq = ha->pdev->irq;
1da177e4
LT		 2395
2396 /* Initialized the timer */
e315cd28 2397 qla2x00_start_timer(base_vha, qla2x00_timer, WATCH_INTERVAL);
7c3df132
SK		 2398 ql_dbg(ql_dbg_init, base_vha, 0x00ef,
2399 "Started qla2x00_timer with "
2400 "interval=%d.\n", WATCH_INTERVAL);
2401 ql_dbg(ql_dbg_init, base_vha, 0x00f0,
2402 "Detected hba at address=%p.\n",
2403 ha);
d19044c3 2404
e02587d7 2405 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) {
bad75002 2406 if (ha->fw_attributes & BIT_4) {
8cb2049c 2407 int prot = 0;
bad75002 2408 base_vha->flags.difdix_supported = 1;
7c3df132
SK		 2409 ql_dbg(ql_dbg_init, base_vha, 0x00f1,
2410 "Registering for DIF/DIX type 1 and 3 protection.\n");
8cb2049c
AE		 2411 if (ql2xenabledif == 1)
2412 prot = SHOST_DIX_TYPE0_PROTECTION;
bad75002 2413 scsi_host_set_prot(host,
8cb2049c 2414 prot | SHOST_DIF_TYPE1_PROTECTION
0c470874 2415 | SHOST_DIF_TYPE2_PROTECTION
bad75002
AE		 2416 | SHOST_DIF_TYPE3_PROTECTION
2417 | SHOST_DIX_TYPE1_PROTECTION
0c470874 2418 | SHOST_DIX_TYPE2_PROTECTION
bad75002
AE		 2419 | SHOST_DIX_TYPE3_PROTECTION);
2420 scsi_host_set_guard(host, SHOST_DIX_GUARD_CRC);
2421 } else
2422 base_vha->flags.difdix_supported = 0;
2423 }
2424
a9083016
GM		 2425 ha->isp_ops->enable_intrs(ha);
2426
a1541d5a
AV		 2427 ret = scsi_add_host(host, &pdev->dev);
2428 if (ret)
2429 goto probe_failed;
2430
1486400f
MR		 2431 base_vha->flags.init_done = 1;
2432 base_vha->flags.online = 1;
2433
7c3df132
SK		 2434 ql_dbg(ql_dbg_init, base_vha, 0x00f2,
2435 "Init done and hba is online.\n");
2436
1e99e33a
AV		 2437 scsi_scan_host(host);
2438
e315cd28 2439 qla2x00_alloc_sysfs_attr(base_vha);
a1541d5a 2440
e315cd28 2441 qla2x00_init_host_attr(base_vha);
a1541d5a 2442
e315cd28 2443 qla2x00_dfs_setup(base_vha);
df613b96 2444
7c3df132
SK		 2445 ql_log(ql_log_info, base_vha, 0x00fa,
2446 "QLogic Fibre Channed HBA Driver: %s.\n",
2447 qla2x00_version_str);
2448 ql_log(ql_log_info, base_vha, 0x00fb,
2449 "QLogic %s - %s.\n",
2450 ha->model_number, ha->model_desc ? ha->model_desc : "");
2451 ql_log(ql_log_info, base_vha, 0x00fc,
2452 "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n",
2453 pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info),
2454 pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-',
2455 base_vha->host_no,
e315cd28 2456 ha->isp_ops->fw_version_str(base_vha, fw_str));
1da177e4 2457
1da177e4
LT		 2458 return 0;
2459
6e9f21f3 2460probe_init_failed:
2afa19a9
AC		 2461 qla2x00_free_req_que(ha, req);
2462 qla2x00_free_rsp_que(ha, rsp);
2463 ha->max_req_queues = ha->max_rsp_queues = 0;
6e9f21f3 2464
1da177e4 2465probe_failed:
b9978769
AV		 2466 if (base_vha->timer_active)
2467 qla2x00_stop_timer(base_vha);
2468 base_vha->flags.online = 0;
2469 if (ha->dpc_thread) {
2470 struct task_struct *t = ha->dpc_thread;
2471
2472 ha->dpc_thread = NULL;
2473 kthread_stop(t);
2474 }
2475
e315cd28 2476 qla2x00_free_device(base_vha);
1da177e4 2477
e315cd28 2478 scsi_host_put(base_vha->host);
1da177e4 2479
e315cd28 2480probe_hw_failed:
a9083016
GM		 2481 if (IS_QLA82XX(ha)) {
2482 qla82xx_idc_lock(ha);
2483 qla82xx_clear_drv_active(ha);
2484 qla82xx_idc_unlock(ha);
2485 iounmap((device_reg_t __iomem *)ha->nx_pcibase);
2486 if (!ql2xdbwr)
2487 iounmap((device_reg_t __iomem *)ha->nxdb_wr_ptr);
2488 } else {
2489 if (ha->iobase)
2490 iounmap(ha->iobase);
2491 }
e315cd28
AC		 2492 pci_release_selected_regions(ha->pdev, ha->bars);
2493 kfree(ha);
2494 ha = NULL;
1da177e4 2495
a1541d5a 2496probe_out:
e315cd28 2497 pci_disable_device(pdev);
a1541d5a 2498 return ret;
1da177e4 2499}
1da177e4 2500
e30d1756
MI		 2501static void
2502qla2x00_shutdown(struct pci_dev *pdev)
2503{
2504 scsi_qla_host_t *vha;
2505 struct qla_hw_data *ha;
2506
2507 vha = pci_get_drvdata(pdev);
2508 ha = vha->hw;
2509
2510 /* Turn-off FCE trace */
2511 if (ha->flags.fce_enabled) {
2512 qla2x00_disable_fce_trace(vha, NULL, NULL);
2513 ha->flags.fce_enabled = 0;
2514 }
2515
2516 /* Turn-off EFT trace */
2517 if (ha->eft)
2518 qla2x00_disable_eft_trace(vha);
2519
2520 /* Stop currently executing firmware. */
2521 qla2x00_try_to_stop_firmware(vha);
2522
2523 /* Turn adapter off line */
2524 vha->flags.online = 0;
2525
2526 /* turn-off interrupts on the card */
2527 if (ha->interrupts_on) {
2528 vha->flags.init_done = 0;
2529 ha->isp_ops->disable_intrs(ha);
2530 }
2531
2532 qla2x00_free_irqs(vha);
2533
2534 qla2x00_free_fw_dump(ha);
2535}
2536
4c993f76 2537static void
7ee61397 2538qla2x00_remove_one(struct pci_dev *pdev)
1da177e4 2539{
feafb7b1 2540 scsi_qla_host_t *base_vha, *vha;
e315cd28 2541 struct qla_hw_data *ha;
feafb7b1 2542 unsigned long flags;
e315cd28
AC		 2543
2544 base_vha = pci_get_drvdata(pdev);
2545 ha = base_vha->hw;
2546
43ebf16d
AE		 2547 mutex_lock(&ha->vport_lock);
2548 while (ha->cur_vport_count) {
2549 struct Scsi_Host *scsi_host;
feafb7b1 2550
43ebf16d 2551 spin_lock_irqsave(&ha->vport_slock, flags);
feafb7b1 2552
43ebf16d
AE		 2553 BUG_ON(base_vha->list.next == &ha->vp_list);
2554 /* This assumes first entry in ha->vp_list is always base vha */
2555 vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list);
2556 scsi_host = scsi_host_get(vha->host);
feafb7b1 2557
43ebf16d
AE		 2558 spin_unlock_irqrestore(&ha->vport_slock, flags);
2559 mutex_unlock(&ha->vport_lock);
2560
2561 fc_vport_terminate(vha->fc_vport);
2562 scsi_host_put(vha->host);
feafb7b1 2563
43ebf16d 2564 mutex_lock(&ha->vport_lock);
e315cd28 2565 }
43ebf16d 2566 mutex_unlock(&ha->vport_lock);
1da177e4 2567
e315cd28 2568 set_bit(UNLOADING, &base_vha->dpc_flags);
1da177e4 2569
b9978769
AV		 2570 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
2571
e315cd28 2572 qla2x00_dfs_remove(base_vha);
c795c1e4 2573
e315cd28 2574 qla84xx_put_chip(base_vha);
c795c1e4 2575
b9978769
AV		 2576 /* Disable timer */
2577 if (base_vha->timer_active)
2578 qla2x00_stop_timer(base_vha);
2579
2580 base_vha->flags.online = 0;
2581
68ca949c
AC		 2582 /* Flush the work queue and remove it */
2583 if (ha->wq) {
2584 flush_workqueue(ha->wq);
2585 destroy_workqueue(ha->wq);
2586 ha->wq = NULL;
2587 }
2588
b9978769
AV		 2589 /* Kill the kernel thread for this host */
2590 if (ha->dpc_thread) {
2591 struct task_struct *t = ha->dpc_thread;
2592
2593 /*
2594 * qla2xxx_wake_dpc checks for ->dpc_thread
2595 * so we need to zero it out.
2596 */
2597 ha->dpc_thread = NULL;
2598 kthread_stop(t);
2599 }
2600
e315cd28 2601 qla2x00_free_sysfs_attr(base_vha);
df613b96 2602
e315cd28 2603 fc_remove_host(base_vha->host);
4d4df193 2604
e315cd28 2605 scsi_remove_host(base_vha->host);
1da177e4 2606
e315cd28 2607 qla2x00_free_device(base_vha);
bdf79621 2608
e315cd28 2609 scsi_host_put(base_vha->host);
1da177e4 2610
a9083016 2611 if (IS_QLA82XX(ha)) {
b963752f
GM		 2612 qla82xx_idc_lock(ha);
2613 qla82xx_clear_drv_active(ha);
2614 qla82xx_idc_unlock(ha);
2615
a9083016
GM		 2616 iounmap((device_reg_t __iomem *)ha->nx_pcibase);
2617 if (!ql2xdbwr)
2618 iounmap((device_reg_t __iomem *)ha->nxdb_wr_ptr);
2619 } else {
2620 if (ha->iobase)
2621 iounmap(ha->iobase);
1da177e4 2622
a9083016
GM		 2623 if (ha->mqiobase)
2624 iounmap(ha->mqiobase);
2625 }
73208dfd 2626
e315cd28
AC		 2627 pci_release_selected_regions(ha->pdev, ha->bars);
2628 kfree(ha);
2629 ha = NULL;
1da177e4 2630
90a86fc0
JC		 2631 pci_disable_pcie_error_reporting(pdev);
2632
665db93b 2633 pci_disable_device(pdev);
1da177e4
LT		 2634 pci_set_drvdata(pdev, NULL);
2635}
1da177e4
LT		 2636
2637static void
e315cd28 2638qla2x00_free_device(scsi_qla_host_t *vha)
1da177e4 2639{
e315cd28 2640 struct qla_hw_data *ha = vha->hw;
1da177e4 2641
85880801
AV		 2642 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
2643
2644 /* Disable timer */
2645 if (vha->timer_active)
2646 qla2x00_stop_timer(vha);
2647
2648 /* Kill the kernel thread for this host */
2649 if (ha->dpc_thread) {
2650 struct task_struct *t = ha->dpc_thread;
2651
2652 /*
2653 * qla2xxx_wake_dpc checks for ->dpc_thread
2654 * so we need to zero it out.
2655 */
2656 ha->dpc_thread = NULL;
2657 kthread_stop(t);
2658 }
2659
2afa19a9
AC		 2660 qla25xx_delete_queues(vha);
2661
df613b96 2662 if (ha->flags.fce_enabled)
e315cd28 2663 qla2x00_disable_fce_trace(vha, NULL, NULL);
df613b96 2664
a7a167bf 2665 if (ha->eft)
e315cd28 2666 qla2x00_disable_eft_trace(vha);
a7a167bf 2667
f6ef3b18 2668 /* Stop currently executing firmware. */
e315cd28 2669 qla2x00_try_to_stop_firmware(vha);
1da177e4 2670
85880801
AV		 2671 vha->flags.online = 0;
2672
f6ef3b18 2673 /* turn-off interrupts on the card */
a9083016
GM		 2674 if (ha->interrupts_on) {
2675 vha->flags.init_done = 0;
fd34f556 2676 ha->isp_ops->disable_intrs(ha);
a9083016 2677 }
f6ef3b18 2678
e315cd28 2679 qla2x00_free_irqs(vha);
1da177e4 2680
8867048b
CD		 2681 qla2x00_free_fcports(vha);
2682
e315cd28 2683 qla2x00_mem_free(ha);
73208dfd 2684
08de2844
GM		 2685 qla82xx_md_free(vha);
2686
73208dfd 2687 qla2x00_free_queues(ha);
1da177e4
LT		 2688}
2689
8867048b
CD		 2690void qla2x00_free_fcports(struct scsi_qla_host *vha)
2691{
2692 fc_port_t *fcport, *tfcport;
2693
2694 list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list) {
2695 list_del(&fcport->list);
2696 kfree(fcport);
2697 fcport = NULL;
2698 }
2699}
2700
d97994dc 2701static inline void
e315cd28 2702qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport,
d97994dc 2703 int defer)
2704{
d97994dc 2705 struct fc_rport *rport;
67becc00 2706 scsi_qla_host_t *base_vha;
044d78e1 2707 unsigned long flags;
d97994dc 2708
2709 if (!fcport->rport)
2710 return;
2711
2712 rport = fcport->rport;
2713 if (defer) {
67becc00 2714 base_vha = pci_get_drvdata(vha->hw->pdev);
044d78e1 2715 spin_lock_irqsave(vha->host->host_lock, flags);
d97994dc 2716 fcport->drport = rport;
044d78e1 2717 spin_unlock_irqrestore(vha->host->host_lock, flags);
67becc00
AV		 2718 set_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags);
2719 qla2xxx_wake_dpc(base_vha);
5f3a9a20 2720 } else
d97994dc 2721 fc_remote_port_delete(rport);
d97994dc 2722}
2723
1da177e4
LT		 2724/*
2725 * qla2x00_mark_device_lost Updates fcport state when device goes offline.
2726 *
2727 * Input: ha = adapter block pointer. fcport = port structure pointer.
2728 *
2729 * Return: None.
2730 *
2731 * Context:
2732 */
e315cd28 2733void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport,
d97994dc 2734 int do_login, int defer)
1da177e4 2735{
2c3dfe3f 2736 if (atomic_read(&fcport->state) == FCS_ONLINE &&
e315cd28 2737 vha->vp_idx == fcport->vp_idx) {
ec426e10 2738 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
e315cd28
AC		 2739 qla2x00_schedule_rport_del(vha, fcport, defer);
2740 }
fa2a1ce5 2741 /*
1da177e4
LT		 2742 * We may need to retry the login, so don't change the state of the
2743 * port but do the retries.
2744 */
2745 if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD)
ec426e10 2746 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
1da177e4
LT		 2747
2748 if (!do_login)
2749 return;
2750
2751 if (fcport->login_retry == 0) {
e315cd28
AC		 2752 fcport->login_retry = vha->hw->login_retry_count;
2753 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
1da177e4 2754
7c3df132
SK		 2755 ql_dbg(ql_dbg_disc, vha, 0x2067,
2756 "Port login retry "
1da177e4 2757 "%02x%02x%02x%02x%02x%02x%02x%02x, "
7c3df132
SK		 2758 "id = 0x%04x retry cnt=%d.\n",
2759 fcport->port_name[0], fcport->port_name[1],
2760 fcport->port_name[2], fcport->port_name[3],
2761 fcport->port_name[4], fcport->port_name[5],
2762 fcport->port_name[6], fcport->port_name[7],
2763 fcport->loop_id, fcport->login_retry);
1da177e4
LT		 2764 }
2765}
2766
2767/*
2768 * qla2x00_mark_all_devices_lost
2769 * Updates fcport state when device goes offline.
2770 *
2771 * Input:
2772 * ha = adapter block pointer.
2773 * fcport = port structure pointer.
2774 *
2775 * Return:
2776 * None.
2777 *
2778 * Context:
2779 */
2780void
e315cd28 2781qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha, int defer)
1da177e4
LT		 2782{
2783 fc_port_t *fcport;
2784
e315cd28 2785 list_for_each_entry(fcport, &vha->vp_fcports, list) {
0d6e61bc 2786 if (vha->vp_idx != 0 && vha->vp_idx != fcport->vp_idx)
1da177e4 2787 continue;
0d6e61bc 2788
1da177e4
LT		 2789 /*
2790 * No point in marking the device as lost, if the device is
2791 * already DEAD.
2792 */
2793 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD)
2794 continue;
e315cd28 2795 if (atomic_read(&fcport->state) == FCS_ONLINE) {
ec426e10 2796 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
0d6e61bc
AV		 2797 if (defer)
2798 qla2x00_schedule_rport_del(vha, fcport, defer);
2799 else if (vha->vp_idx == fcport->vp_idx)
2800 qla2x00_schedule_rport_del(vha, fcport, defer);
2801 }
1da177e4
LT		 2802 }
2803}
2804
2805/*
2806* qla2x00_mem_alloc
2807* Allocates adapter memory.
2808*
2809* Returns:
2810* 0 = success.
e8711085 2811* !0 = failure.
1da177e4 2812*/
e8711085 2813static int
73208dfd
AC		 2814qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len,
2815 struct req_que **req, struct rsp_que **rsp)
1da177e4
LT		 2816{
2817 char name[16];
1da177e4 2818
e8711085 2819 ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size,
e315cd28 2820 &ha->init_cb_dma, GFP_KERNEL);
e8711085 2821 if (!ha->init_cb)
e315cd28 2822 goto fail;
e8711085 2823
e315cd28
AC		 2824 ha->gid_list = dma_alloc_coherent(&ha->pdev->dev, GID_LIST_SIZE,
2825 &ha->gid_list_dma, GFP_KERNEL);
2826 if (!ha->gid_list)
e8711085 2827 goto fail_free_init_cb;
1da177e4 2828
e8711085
AV		 2829 ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep);
2830 if (!ha->srb_mempool)
e315cd28 2831 goto fail_free_gid_list;
e8711085 2832
a9083016
GM		 2833 if (IS_QLA82XX(ha)) {
2834 /* Allocate cache for CT6 Ctx. */
2835 if (!ctx_cachep) {
2836 ctx_cachep = kmem_cache_create("qla2xxx_ctx",
2837 sizeof(struct ct6_dsd), 0,
2838 SLAB_HWCACHE_ALIGN, NULL);
2839 if (!ctx_cachep)
2840 goto fail_free_gid_list;
2841 }
2842 ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ,
2843 ctx_cachep);
2844 if (!ha->ctx_mempool)
2845 goto fail_free_srb_mempool;
7c3df132
SK		 2846 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021,
2847 "ctx_cachep=%p ctx_mempool=%p.\n",
2848 ctx_cachep, ha->ctx_mempool);
a9083016
GM		 2849 }
2850
e8711085
AV		 2851 /* Get memory for cached NVRAM */
2852 ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL);
2853 if (!ha->nvram)
a9083016 2854 goto fail_free_ctx_mempool;
e8711085 2855
e315cd28
AC		 2856 snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME,
2857 ha->pdev->device);
2858 ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev,
2859 DMA_POOL_SIZE, 8, 0);
2860 if (!ha->s_dma_pool)
2861 goto fail_free_nvram;
2862
7c3df132
SK		 2863 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022,
2864 "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n",
2865 ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool);
2866
bad75002 2867 if (IS_QLA82XX(ha) || ql2xenabledif) {
a9083016
GM		 2868 ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev,
2869 DSD_LIST_DMA_POOL_SIZE, 8, 0);
2870 if (!ha->dl_dma_pool) {
7c3df132
SK		 2871 ql_log_pci(ql_log_fatal, ha->pdev, 0x0023,
2872 "Failed to allocate memory for dl_dma_pool.\n");
a9083016
GM		 2873 goto fail_s_dma_pool;
2874 }
2875
2876 ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev,
2877 FCP_CMND_DMA_POOL_SIZE, 8, 0);
2878 if (!ha->fcp_cmnd_dma_pool) {
7c3df132
SK		 2879 ql_log_pci(ql_log_fatal, ha->pdev, 0x0024,
2880 "Failed to allocate memory for fcp_cmnd_dma_pool.\n");
a9083016
GM		 2881 goto fail_dl_dma_pool;
2882 }
7c3df132
SK		 2883 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025,
2884 "dl_dma_pool=%p fcp_cmnd_dma_pool=%p.\n",
2885 ha->dl_dma_pool, ha->fcp_cmnd_dma_pool);
a9083016
GM		 2886 }
2887
e8711085
AV		 2888 /* Allocate memory for SNS commands */
2889 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
e315cd28 2890 /* Get consistent memory allocated for SNS commands */
e8711085 2891 ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev,
e315cd28 2892 sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL);
e8711085 2893 if (!ha->sns_cmd)
e315cd28 2894 goto fail_dma_pool;
7c3df132
SK		 2895 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026,
2896 "sns_cmd.\n", ha->sns_cmd);
e8711085 2897 } else {
e315cd28 2898 /* Get consistent memory allocated for MS IOCB */
e8711085 2899 ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
e315cd28 2900 &ha->ms_iocb_dma);
e8711085 2901 if (!ha->ms_iocb)
e315cd28
AC		 2902 goto fail_dma_pool;
2903 /* Get consistent memory allocated for CT SNS commands */
e8711085 2904 ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev,
e315cd28 2905 sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL);
e8711085
AV		 2906 if (!ha->ct_sns)
2907 goto fail_free_ms_iocb;
7c3df132
SK		 2908 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027,
2909 "ms_iocb=%p ct_sns=%p.\n",
2910 ha->ms_iocb, ha->ct_sns);
1da177e4
LT		 2911 }
2912
e315cd28 2913 /* Allocate memory for request ring */
73208dfd
AC		 2914 *req = kzalloc(sizeof(struct req_que), GFP_KERNEL);
2915 if (!*req) {
7c3df132
SK		 2916 ql_log_pci(ql_log_fatal, ha->pdev, 0x0028,
2917 "Failed to allocate memory for req.\n");
e315cd28
AC		 2918 goto fail_req;
2919 }
73208dfd
AC		 2920 (*req)->length = req_len;
2921 (*req)->ring = dma_alloc_coherent(&ha->pdev->dev,
2922 ((*req)->length + 1) * sizeof(request_t),
2923 &(*req)->dma, GFP_KERNEL);
2924 if (!(*req)->ring) {
7c3df132
SK		 2925 ql_log_pci(ql_log_fatal, ha->pdev, 0x0029,
2926 "Failed to allocate memory for req_ring.\n");
e315cd28
AC		 2927 goto fail_req_ring;
2928 }
2929 /* Allocate memory for response ring */
73208dfd
AC		 2930 *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL);
2931 if (!*rsp) {
7c3df132
SK		 2932 ql_log_pci(ql_log_fatal, ha->pdev, 0x002a,
2933 "Failed to allocate memory for rsp.\n");
e315cd28
AC		 2934 goto fail_rsp;
2935 }
73208dfd
AC		 2936 (*rsp)->hw = ha;
2937 (*rsp)->length = rsp_len;
2938 (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev,
2939 ((*rsp)->length + 1) * sizeof(response_t),
2940 &(*rsp)->dma, GFP_KERNEL);
2941 if (!(*rsp)->ring) {
7c3df132
SK		 2942 ql_log_pci(ql_log_fatal, ha->pdev, 0x002b,
2943 "Failed to allocate memory for rsp_ring.\n");
e315cd28
AC		 2944 goto fail_rsp_ring;
2945 }
73208dfd
AC		 2946 (*req)->rsp = *rsp;
2947 (*rsp)->req = *req;
7c3df132
SK		 2948 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c,
2949 "req=%p req->length=%d req->ring=%p rsp=%p "
2950 "rsp->length=%d rsp->ring=%p.\n",
2951 *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length,
2952 (*rsp)->ring);
73208dfd
AC		 2953 /* Allocate memory for NVRAM data for vports */
2954 if (ha->nvram_npiv_size) {
2955 ha->npiv_info = kzalloc(sizeof(struct qla_npiv_entry) *
7c3df132 2956 ha->nvram_npiv_size, GFP_KERNEL);
73208dfd 2957 if (!ha->npiv_info) {
7c3df132
SK		 2958 ql_log_pci(ql_log_fatal, ha->pdev, 0x002d,
2959 "Failed to allocate memory for npiv_info.\n");
73208dfd
AC		 2960 goto fail_npiv_info;
2961 }
2962 } else
2963 ha->npiv_info = NULL;
e8711085 2964
b64b0e8f 2965 /* Get consistent memory allocated for EX-INIT-CB. */
a9083016 2966 if (IS_QLA8XXX_TYPE(ha)) {
b64b0e8f
AV		 2967 ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
2968 &ha->ex_init_cb_dma);
2969 if (!ha->ex_init_cb)
2970 goto fail_ex_init_cb;
7c3df132
SK		 2971 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e,
2972 "ex_init_cb=%p.\n", ha->ex_init_cb);
b64b0e8f
AV		 2973 }
2974
a9083016
GM		 2975 INIT_LIST_HEAD(&ha->gbl_dsd_list);
2976
5ff1d584
AV		 2977 /* Get consistent memory allocated for Async Port-Database. */
2978 if (!IS_FWI2_CAPABLE(ha)) {
2979 ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
2980 &ha->async_pd_dma);
2981 if (!ha->async_pd)
2982 goto fail_async_pd;
7c3df132
SK		 2983 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f,
2984 "async_pd=%p.\n", ha->async_pd);
5ff1d584
AV		 2985 }
2986
e315cd28
AC		 2987 INIT_LIST_HEAD(&ha->vp_list);
2988 return 1;
2989
5ff1d584
AV		 2990fail_async_pd:
2991 dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma);
b64b0e8f
AV		 2992fail_ex_init_cb:
2993 kfree(ha->npiv_info);
73208dfd
AC		 2994fail_npiv_info:
2995 dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) *
2996 sizeof(response_t), (*rsp)->ring, (*rsp)->dma);
2997 (*rsp)->ring = NULL;
2998 (*rsp)->dma = 0;
e315cd28 2999fail_rsp_ring:
73208dfd 3000 kfree(*rsp);
e315cd28 3001fail_rsp:
73208dfd
AC		 3002 dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) *
3003 sizeof(request_t), (*req)->ring, (*req)->dma);
3004 (*req)->ring = NULL;
3005 (*req)->dma = 0;
e315cd28 3006fail_req_ring:
73208dfd 3007 kfree(*req);
e315cd28
AC		 3008fail_req:
3009 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
3010 ha->ct_sns, ha->ct_sns_dma);
3011 ha->ct_sns = NULL;
3012 ha->ct_sns_dma = 0;
e8711085
AV		 3013fail_free_ms_iocb:
3014 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
3015 ha->ms_iocb = NULL;
3016 ha->ms_iocb_dma = 0;
e315cd28 3017fail_dma_pool:
bad75002 3018 if (IS_QLA82XX(ha) || ql2xenabledif) {
a9083016
GM		 3019 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
3020 ha->fcp_cmnd_dma_pool = NULL;
3021 }
3022fail_dl_dma_pool:
bad75002 3023 if (IS_QLA82XX(ha) || ql2xenabledif) {
a9083016
GM		 3024 dma_pool_destroy(ha->dl_dma_pool);
3025 ha->dl_dma_pool = NULL;
3026 }
3027fail_s_dma_pool:
e315cd28
AC		 3028 dma_pool_destroy(ha->s_dma_pool);
3029 ha->s_dma_pool = NULL;
e8711085
AV		 3030fail_free_nvram:
3031 kfree(ha->nvram);
3032 ha->nvram = NULL;
a9083016
GM		 3033fail_free_ctx_mempool:
3034 mempool_destroy(ha->ctx_mempool);
3035 ha->ctx_mempool = NULL;
e8711085
AV		 3036fail_free_srb_mempool:
3037 mempool_destroy(ha->srb_mempool);
3038 ha->srb_mempool = NULL;
e8711085
AV		 3039fail_free_gid_list:
3040 dma_free_coherent(&ha->pdev->dev, GID_LIST_SIZE, ha->gid_list,
e315cd28 3041 ha->gid_list_dma);
e8711085
AV		 3042 ha->gid_list = NULL;
3043 ha->gid_list_dma = 0;
e315cd28
AC		 3044fail_free_init_cb:
3045 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb,
3046 ha->init_cb_dma);
3047 ha->init_cb = NULL;
3048 ha->init_cb_dma = 0;
e8711085 3049fail:
7c3df132
SK		 3050 ql_log(ql_log_fatal, NULL, 0x0030,
3051 "Memory allocation failure.\n");
e8711085 3052 return -ENOMEM;
1da177e4
LT		 3053}
3054
3055/*
e30d1756
MI		 3056* qla2x00_free_fw_dump
3057* Frees fw dump stuff.
1da177e4
LT		 3058*
3059* Input:
e30d1756 3060* ha = adapter block pointer.
1da177e4 3061*/
a824ebb3 3062static void
e30d1756 3063qla2x00_free_fw_dump(struct qla_hw_data *ha)
1da177e4 3064{
df613b96
AV		 3065 if (ha->fce)
3066 dma_free_coherent(&ha->pdev->dev, FCE_SIZE, ha->fce,
e30d1756 3067 ha->fce_dma);
df613b96 3068
a7a167bf
AV		 3069 if (ha->fw_dump) {
3070 if (ha->eft)
3071 dma_free_coherent(&ha->pdev->dev,
e30d1756 3072 ntohl(ha->fw_dump->eft_size), ha->eft, ha->eft_dma);
a7a167bf
AV		 3073 vfree(ha->fw_dump);
3074 }
e30d1756
MI		 3075 ha->fce = NULL;
3076 ha->fce_dma = 0;
3077 ha->eft = NULL;
3078 ha->eft_dma = 0;
3079 ha->fw_dump = NULL;
3080 ha->fw_dumped = 0;
3081 ha->fw_dump_reading = 0;
3082}
3083
3084/*
3085* qla2x00_mem_free
3086* Frees all adapter allocated memory.
3087*
3088* Input:
3089* ha = adapter block pointer.
3090*/
3091static void
3092qla2x00_mem_free(struct qla_hw_data *ha)
3093{
3094 qla2x00_free_fw_dump(ha);
3095
3096 if (ha->srb_mempool)
3097 mempool_destroy(ha->srb_mempool);
a7a167bf 3098
11bbc1d8
AV		 3099 if (ha->dcbx_tlv)
3100 dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE,
3101 ha->dcbx_tlv, ha->dcbx_tlv_dma);
3102
ce0423f4
AV		 3103 if (ha->xgmac_data)
3104 dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE,
3105 ha->xgmac_data, ha->xgmac_data_dma);
3106
1da177e4
LT		 3107 if (ha->sns_cmd)
3108 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
e315cd28 3109 ha->sns_cmd, ha->sns_cmd_dma);
1da177e4
LT		 3110
3111 if (ha->ct_sns)
3112 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
e315cd28 3113 ha->ct_sns, ha->ct_sns_dma);
1da177e4 3114
88729e53
AV		 3115 if (ha->sfp_data)
3116 dma_pool_free(ha->s_dma_pool, ha->sfp_data, ha->sfp_data_dma);
3117
ad0ecd61
JC		 3118 if (ha->edc_data)
3119 dma_pool_free(ha->s_dma_pool, ha->edc_data, ha->edc_data_dma);
3120
1da177e4
LT		 3121 if (ha->ms_iocb)
3122 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
3123
b64b0e8f 3124 if (ha->ex_init_cb)
a9083016
GM		 3125 dma_pool_free(ha->s_dma_pool,
3126 ha->ex_init_cb, ha->ex_init_cb_dma);
b64b0e8f 3127
5ff1d584
AV		 3128 if (ha->async_pd)
3129 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
3130
1da177e4
LT		 3131 if (ha->s_dma_pool)
3132 dma_pool_destroy(ha->s_dma_pool);
3133
1da177e4
LT		 3134 if (ha->gid_list)
3135 dma_free_coherent(&ha->pdev->dev, GID_LIST_SIZE, ha->gid_list,
e315cd28 3136 ha->gid_list_dma);
1da177e4 3137
a9083016
GM		 3138 if (IS_QLA82XX(ha)) {
3139 if (!list_empty(&ha->gbl_dsd_list)) {
3140 struct dsd_dma *dsd_ptr, *tdsd_ptr;
3141
3142 /* clean up allocated prev pool */
3143 list_for_each_entry_safe(dsd_ptr,
3144 tdsd_ptr, &ha->gbl_dsd_list, list) {
3145 dma_pool_free(ha->dl_dma_pool,
3146 dsd_ptr->dsd_addr, dsd_ptr->dsd_list_dma);
3147 list_del(&dsd_ptr->list);
3148 kfree(dsd_ptr);
3149 }
3150 }
3151 }
3152
3153 if (ha->dl_dma_pool)
3154 dma_pool_destroy(ha->dl_dma_pool);
3155
3156 if (ha->fcp_cmnd_dma_pool)
3157 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
3158
3159 if (ha->ctx_mempool)
3160 mempool_destroy(ha->ctx_mempool);
3161
e315cd28
AC		 3162 if (ha->init_cb)
3163 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size,
a9083016 3164 ha->init_cb, ha->init_cb_dma);
e315cd28
AC		 3165 vfree(ha->optrom_buffer);
3166 kfree(ha->nvram);
73208dfd 3167 kfree(ha->npiv_info);
1da177e4 3168
e8711085 3169 ha->srb_mempool = NULL;
a9083016 3170 ha->ctx_mempool = NULL;
1da177e4
LT		 3171 ha->sns_cmd = NULL;
3172 ha->sns_cmd_dma = 0;
3173 ha->ct_sns = NULL;
3174 ha->ct_sns_dma = 0;
3175 ha->ms_iocb = NULL;
3176 ha->ms_iocb_dma = 0;
1da177e4
LT		 3177 ha->init_cb = NULL;
3178 ha->init_cb_dma = 0;
b64b0e8f
AV		 3179 ha->ex_init_cb = NULL;
3180 ha->ex_init_cb_dma = 0;
5ff1d584
AV		 3181 ha->async_pd = NULL;
3182 ha->async_pd_dma = 0;
1da177e4
LT		 3183
3184 ha->s_dma_pool = NULL;
a9083016
GM		 3185 ha->dl_dma_pool = NULL;
3186 ha->fcp_cmnd_dma_pool = NULL;
1da177e4 3187
1da177e4
LT		 3188 ha->gid_list = NULL;
3189 ha->gid_list_dma = 0;
e315cd28 3190}
1da177e4 3191
e315cd28
AC		 3192struct scsi_qla_host *qla2x00_create_host(struct scsi_host_template *sht,
3193 struct qla_hw_data *ha)
3194{
3195 struct Scsi_Host *host;
3196 struct scsi_qla_host *vha = NULL;
854165f4 3197
e315cd28
AC		 3198 host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t));
3199 if (host == NULL) {
7c3df132
SK		 3200 ql_log_pci(ql_log_fatal, ha->pdev, 0x0107,
3201 "Failed to allocate host from the scsi layer, aborting.\n");
e315cd28
AC		 3202 goto fail;
3203 }
3204
3205 /* Clear our data area */
3206 vha = shost_priv(host);
3207 memset(vha, 0, sizeof(scsi_qla_host_t));
3208
3209 vha->host = host;
3210 vha->host_no = host->host_no;
3211 vha->hw = ha;
3212
3213 INIT_LIST_HEAD(&vha->vp_fcports);
3214 INIT_LIST_HEAD(&vha->work_list);
3215 INIT_LIST_HEAD(&vha->list);
3216
f999f4c1
AV		 3217 spin_lock_init(&vha->work_lock);
3218
e315cd28 3219 sprintf(vha->host_str, "%s_%ld", QLA2XXX_DRIVER_NAME, vha->host_no);
7c3df132
SK		 3220 ql_dbg(ql_dbg_init, vha, 0x0041,
3221 "Allocated the host=%p hw=%p vha=%p dev_name=%s",
3222 vha->host, vha->hw, vha,
3223 dev_name(&(ha->pdev->dev)));
3224
e315cd28
AC		 3225 return vha;
3226
3227fail:
3228 return vha;
1da177e4
LT		 3229}
3230
01ef66bb 3231static struct qla_work_evt *
f999f4c1 3232qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type)
0971de7f
AV		 3233{
3234 struct qla_work_evt *e;
feafb7b1
AE		 3235 uint8_t bail;
3236
3237 QLA_VHA_MARK_BUSY(vha, bail);
3238 if (bail)
3239 return NULL;
0971de7f 3240
f999f4c1 3241 e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC);
feafb7b1
AE		 3242 if (!e) {
3243 QLA_VHA_MARK_NOT_BUSY(vha);
0971de7f 3244 return NULL;
feafb7b1 3245 }
0971de7f
AV		 3246
3247 INIT_LIST_HEAD(&e->list);
3248 e->type = type;
3249 e->flags = QLA_EVT_FLAG_FREE;
3250 return e;
3251}
3252
01ef66bb 3253static int
f999f4c1 3254qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e)
0971de7f 3255{
f999f4c1 3256 unsigned long flags;
0971de7f 3257
f999f4c1 3258 spin_lock_irqsave(&vha->work_lock, flags);
e315cd28 3259 list_add_tail(&e->list, &vha->work_list);
f999f4c1 3260 spin_unlock_irqrestore(&vha->work_lock, flags);
e315cd28 3261 qla2xxx_wake_dpc(vha);
f999f4c1 3262
0971de7f
AV		 3263 return QLA_SUCCESS;
3264}
3265
3266int
e315cd28 3267qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code,
0971de7f
AV		 3268 u32 data)
3269{
3270 struct qla_work_evt *e;
3271
f999f4c1 3272 e = qla2x00_alloc_work(vha, QLA_EVT_AEN);
0971de7f
AV		 3273 if (!e)
3274 return QLA_FUNCTION_FAILED;
3275
3276 e->u.aen.code = code;
3277 e->u.aen.data = data;
f999f4c1 3278 return qla2x00_post_work(vha, e);
0971de7f
AV		 3279}
3280
8a659571
AV		 3281int
3282qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb)
3283{
3284 struct qla_work_evt *e;
3285
f999f4c1 3286 e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK);
8a659571
AV		 3287 if (!e)
3288 return QLA_FUNCTION_FAILED;
3289
3290 memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t));
f999f4c1 3291 return qla2x00_post_work(vha, e);
8a659571
AV		 3292}
3293
ac280b67
AV		 3294#define qla2x00_post_async_work(name, type) \
3295int qla2x00_post_async_##name##_work( \
3296 struct scsi_qla_host *vha, \
3297 fc_port_t *fcport, uint16_t *data) \
3298{ \
3299 struct qla_work_evt *e; \
3300 \
3301 e = qla2x00_alloc_work(vha, type); \
3302 if (!e) \
3303 return QLA_FUNCTION_FAILED; \
3304 \
3305 e->u.logio.fcport = fcport; \
3306 if (data) { \
3307 e->u.logio.data[0] = data[0]; \
3308 e->u.logio.data[1] = data[1]; \
3309 } \
3310 return qla2x00_post_work(vha, e); \
3311}
3312
3313qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN);
3314qla2x00_post_async_work(login_done, QLA_EVT_ASYNC_LOGIN_DONE);
3315qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT);
3316qla2x00_post_async_work(logout_done, QLA_EVT_ASYNC_LOGOUT_DONE);
5ff1d584
AV		 3317qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC);
3318qla2x00_post_async_work(adisc_done, QLA_EVT_ASYNC_ADISC_DONE);
ac280b67 3319
3420d36c
AV		 3320int
3321qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code)
3322{
3323 struct qla_work_evt *e;
3324
3325 e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT);
3326 if (!e)
3327 return QLA_FUNCTION_FAILED;
3328
3329 e->u.uevent.code = code;
3330 return qla2x00_post_work(vha, e);
3331}
3332
3333static void
3334qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code)
3335{
3336 char event_string[40];
3337 char *envp[] = { event_string, NULL };
3338
3339 switch (code) {
3340 case QLA_UEVENT_CODE_FW_DUMP:
3341 snprintf(event_string, sizeof(event_string), "FW_DUMP=%ld",
3342 vha->host_no);
3343 break;
3344 default:
3345 /* do nothing */
3346 break;
3347 }
3348 kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp);
3349}
3350
ac280b67 3351void
e315cd28 3352qla2x00_do_work(struct scsi_qla_host *vha)
0971de7f 3353{
f999f4c1
AV		 3354 struct qla_work_evt *e, *tmp;
3355 unsigned long flags;
3356 LIST_HEAD(work);
0971de7f 3357
f999f4c1
AV		 3358 spin_lock_irqsave(&vha->work_lock, flags);
3359 list_splice_init(&vha->work_list, &work);
3360 spin_unlock_irqrestore(&vha->work_lock, flags);
3361
3362 list_for_each_entry_safe(e, tmp, &work, list) {
0971de7f 3363 list_del_init(&e->list);
0971de7f
AV		 3364
3365 switch (e->type) {
3366 case QLA_EVT_AEN:
e315cd28 3367 fc_host_post_event(vha->host, fc_get_event_number(),
0971de7f
AV		 3368 e->u.aen.code, e->u.aen.data);
3369 break;
8a659571
AV		 3370 case QLA_EVT_IDC_ACK:
3371 qla81xx_idc_ack(vha, e->u.idc_ack.mb);
3372 break;
ac280b67
AV		 3373 case QLA_EVT_ASYNC_LOGIN:
3374 qla2x00_async_login(vha, e->u.logio.fcport,
3375 e->u.logio.data);
3376 break;
3377 case QLA_EVT_ASYNC_LOGIN_DONE:
3378 qla2x00_async_login_done(vha, e->u.logio.fcport,
3379 e->u.logio.data);
3380 break;
3381 case QLA_EVT_ASYNC_LOGOUT:
3382 qla2x00_async_logout(vha, e->u.logio.fcport);
3383 break;
3384 case QLA_EVT_ASYNC_LOGOUT_DONE:
3385 qla2x00_async_logout_done(vha, e->u.logio.fcport,
3386 e->u.logio.data);
3387 break;
5ff1d584
AV		 3388 case QLA_EVT_ASYNC_ADISC:
3389 qla2x00_async_adisc(vha, e->u.logio.fcport,
3390 e->u.logio.data);
3391 break;
3392 case QLA_EVT_ASYNC_ADISC_DONE:
3393 qla2x00_async_adisc_done(vha, e->u.logio.fcport,
3394 e->u.logio.data);
3395 break;
3420d36c
AV		 3396 case QLA_EVT_UEVENT:
3397 qla2x00_uevent_emit(vha, e->u.uevent.code);
3398 break;
0971de7f
AV		 3399 }
3400 if (e->flags & QLA_EVT_FLAG_FREE)
3401 kfree(e);
feafb7b1
AE		 3402
3403 /* For each work completed decrement vha ref count */
3404 QLA_VHA_MARK_NOT_BUSY(vha);
e315cd28 3405 }
e315cd28 3406}
f999f4c1 3407
e315cd28
AC		 3408/* Relogins all the fcports of a vport
3409 * Context: dpc thread
3410 */
3411void qla2x00_relogin(struct scsi_qla_host *vha)
3412{
3413 fc_port_t *fcport;
c6b2fca8 3414 int status;
e315cd28
AC		 3415 uint16_t next_loopid = 0;
3416 struct qla_hw_data *ha = vha->hw;
ac280b67 3417 uint16_t data[2];
e315cd28
AC		 3418
3419 list_for_each_entry(fcport, &vha->vp_fcports, list) {
3420 /*
3421 * If the port is not ONLINE then try to login
3422 * to it if we haven't run out of retries.
3423 */
5ff1d584
AV		 3424 if (atomic_read(&fcport->state) != FCS_ONLINE &&
3425 fcport->login_retry && !(fcport->flags & FCF_ASYNC_SENT)) {
ac280b67 3426 fcport->login_retry--;
e315cd28 3427 if (fcport->flags & FCF_FABRIC_DEVICE) {
f08b7251 3428 if (fcport->flags & FCF_FCP2_DEVICE)
e315cd28
AC		 3429 ha->isp_ops->fabric_logout(vha,
3430 fcport->loop_id,
3431 fcport->d_id.b.domain,
3432 fcport->d_id.b.area,
3433 fcport->d_id.b.al_pa);
3434
03bcfb57
JC		 3435 if (fcport->loop_id == FC_NO_LOOP_ID) {
3436 fcport->loop_id = next_loopid =
3437 ha->min_external_loopid;
3438 status = qla2x00_find_new_loop_id(
3439 vha, fcport);
3440 if (status != QLA_SUCCESS) {
3441 /* Ran out of IDs to use */
3442 break;
3443 }
3444 }
3445
ac280b67 3446 if (IS_ALOGIO_CAPABLE(ha)) {
5ff1d584 3447 fcport->flags |= FCF_ASYNC_SENT;
ac280b67
AV		 3448 data[0] = 0;
3449 data[1] = QLA_LOGIO_LOGIN_RETRIED;
3450 status = qla2x00_post_async_login_work(
3451 vha, fcport, data);
3452 if (status == QLA_SUCCESS)
3453 continue;
3454 /* Attempt a retry. */
3455 status = 1;
3456 } else
3457 status = qla2x00_fabric_login(vha,
3458 fcport, &next_loopid);
e315cd28
AC		 3459 } else
3460 status = qla2x00_local_device_login(vha,
3461 fcport);
3462
e315cd28
AC		 3463 if (status == QLA_SUCCESS) {
3464 fcport->old_loop_id = fcport->loop_id;
3465
7c3df132
SK		 3466 ql_dbg(ql_dbg_disc, vha, 0x2003,
3467 "Port login OK: logged in ID 0x%x.\n",
3468 fcport->loop_id);
e315cd28
AC		 3469
3470 qla2x00_update_fcport(vha, fcport);
3471
3472 } else if (status == 1) {
3473 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
3474 /* retry the login again */
7c3df132
SK		 3475 ql_dbg(ql_dbg_disc, vha, 0x2007,
3476 "Retrying %d login again loop_id 0x%x.\n",
3477 fcport->login_retry, fcport->loop_id);
e315cd28
AC		 3478 } else {
3479 fcport->login_retry = 0;
3480 }
3481
3482 if (fcport->login_retry == 0 && status != QLA_SUCCESS)
3483 fcport->loop_id = FC_NO_LOOP_ID;
3484 }
3485 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
3486 break;
0971de7f 3487 }
0971de7f
AV		 3488}
3489
1da177e4
LT		 3490/**************************************************************************
3491* qla2x00_do_dpc
3492* This kernel thread is a task that is schedule by the interrupt handler
3493* to perform the background processing for interrupts.
3494*
3495* Notes:
3496* This task always run in the context of a kernel thread. It
3497* is kick-off by the driver's detect code and starts up
3498* up one per adapter. It immediately goes to sleep and waits for
3499* some fibre event. When either the interrupt handler or
3500* the timer routine detects a event it will one of the task
3501* bits then wake us up.
3502**************************************************************************/
3503static int
3504qla2x00_do_dpc(void *data)
3505{
2c3dfe3f 3506 int rval;
e315cd28
AC		 3507 scsi_qla_host_t *base_vha;
3508 struct qla_hw_data *ha;
1da177e4 3509
e315cd28
AC		 3510 ha = (struct qla_hw_data *)data;
3511 base_vha = pci_get_drvdata(ha->pdev);
1da177e4 3512
1da177e4
LT		 3513 set_user_nice(current, -20);
3514
563585ec 3515 set_current_state(TASK_INTERRUPTIBLE);
39a11240 3516 while (!kthread_should_stop()) {
7c3df132
SK		 3517 ql_dbg(ql_dbg_dpc, base_vha, 0x4000,
3518 "DPC handler sleeping.\n");
1da177e4 3519
39a11240
CH		 3520 schedule();
3521 __set_current_state(TASK_RUNNING);
1da177e4 3522
7c3df132
SK		 3523 ql_dbg(ql_dbg_dpc, base_vha, 0x4001,
3524 "DPC handler waking up.\n");
3525 ql_dbg(ql_dbg_dpc, base_vha, 0x4002,
3526 "dpc_flags=0x%lx.\n", base_vha->dpc_flags);
1da177e4
LT		 3527
3528 /* Initialization not yet finished. Don't do anything yet. */
e315cd28 3529 if (!base_vha->flags.init_done)
1da177e4
LT		 3530 continue;
3531
85880801 3532 if (ha->flags.eeh_busy) {
7c3df132
SK		 3533 ql_dbg(ql_dbg_dpc, base_vha, 0x4003,
3534 "eeh_busy=%d.\n", ha->flags.eeh_busy);
85880801
AV		 3535 continue;
3536 }
3537
1da177e4
LT		 3538 ha->dpc_active = 1;
3539
1da177e4 3540 if (ha->flags.mbox_busy) {
1da177e4
LT		 3541 ha->dpc_active = 0;
3542 continue;
3543 }
3544
e315cd28 3545 qla2x00_do_work(base_vha);
0971de7f 3546
a9083016
GM		 3547 if (IS_QLA82XX(ha)) {
3548 if (test_and_clear_bit(ISP_UNRECOVERABLE,
3549 &base_vha->dpc_flags)) {
3550 qla82xx_idc_lock(ha);
3551 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
3552 QLA82XX_DEV_FAILED);
3553 qla82xx_idc_unlock(ha);
7c3df132
SK		 3554 ql_log(ql_log_info, base_vha, 0x4004,
3555 "HW State: FAILED.\n");
a9083016
GM		 3556 qla82xx_device_state_handler(base_vha);
3557 continue;
3558 }
3559
3560 if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED,
3561 &base_vha->dpc_flags)) {
3562
7c3df132
SK		 3563 ql_dbg(ql_dbg_dpc, base_vha, 0x4005,
3564 "FCoE context reset scheduled.\n");
a9083016
GM		 3565 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
3566 &base_vha->dpc_flags))) {
3567 if (qla82xx_fcoe_ctx_reset(base_vha)) {
3568 /* FCoE-ctx reset failed.
3569 * Escalate to chip-reset
3570 */
3571 set_bit(ISP_ABORT_NEEDED,
3572 &base_vha->dpc_flags);
3573 }
3574 clear_bit(ABORT_ISP_ACTIVE,
3575 &base_vha->dpc_flags);
3576 }
3577
7c3df132
SK		 3578 ql_dbg(ql_dbg_dpc, base_vha, 0x4006,
3579 "FCoE context reset end.\n");
a9083016
GM		 3580 }
3581 }
3582
e315cd28
AC		 3583 if (test_and_clear_bit(ISP_ABORT_NEEDED,
3584 &base_vha->dpc_flags)) {
1da177e4 3585
7c3df132
SK		 3586 ql_dbg(ql_dbg_dpc, base_vha, 0x4007,
3587 "ISP abort scheduled.\n");
1da177e4 3588 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
e315cd28 3589 &base_vha->dpc_flags))) {
1da177e4 3590
a9083016 3591 if (ha->isp_ops->abort_isp(base_vha)) {
1da177e4
LT		 3592 /* failed. retry later */
3593 set_bit(ISP_ABORT_NEEDED,
e315cd28 3594 &base_vha->dpc_flags);
99363ef8 3595 }
e315cd28
AC		 3596 clear_bit(ABORT_ISP_ACTIVE,
3597 &base_vha->dpc_flags);
99363ef8
SJ		 3598 }
3599
7c3df132
SK		 3600 ql_dbg(ql_dbg_dpc, base_vha, 0x4008,
3601 "ISP abort end.\n");
1da177e4
LT		 3602 }
3603
e315cd28
AC		 3604 if (test_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags)) {
3605 qla2x00_update_fcports(base_vha);
3606 clear_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags);
c9c5ced9 3607 }
d97994dc 3608
579d12b5 3609 if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) {
7c3df132
SK		 3610 ql_dbg(ql_dbg_dpc, base_vha, 0x4009,
3611 "Quiescence mode scheduled.\n");
579d12b5
SK		 3612 qla82xx_device_state_handler(base_vha);
3613 clear_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags);
3614 if (!ha->flags.quiesce_owner) {
3615 qla2x00_perform_loop_resync(base_vha);
3616
3617 qla82xx_idc_lock(ha);
3618 qla82xx_clear_qsnt_ready(base_vha);
3619 qla82xx_idc_unlock(ha);
3620 }
7c3df132
SK		 3621 ql_dbg(ql_dbg_dpc, base_vha, 0x400a,
3622 "Quiescence mode end.\n");
579d12b5
SK		 3623 }
3624
e315cd28
AC		 3625 if (test_and_clear_bit(RESET_MARKER_NEEDED,
3626 &base_vha->dpc_flags) &&
3627 (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) {
1da177e4 3628
7c3df132
SK		 3629 ql_dbg(ql_dbg_dpc, base_vha, 0x400b,
3630 "Reset marker scheduled.\n");
e315cd28
AC		 3631 qla2x00_rst_aen(base_vha);
3632 clear_bit(RESET_ACTIVE, &base_vha->dpc_flags);
7c3df132
SK		 3633 ql_dbg(ql_dbg_dpc, base_vha, 0x400c,
3634 "Reset marker end.\n");
1da177e4
LT		 3635 }
3636
3637 /* Retry each device up to login retry count */
e315cd28
AC		 3638 if ((test_and_clear_bit(RELOGIN_NEEDED,
3639 &base_vha->dpc_flags)) &&
3640 !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) &&
3641 atomic_read(&base_vha->loop_state) != LOOP_DOWN) {
1da177e4 3642
7c3df132
SK		 3643 ql_dbg(ql_dbg_dpc, base_vha, 0x400d,
3644 "Relogin scheduled.\n");
e315cd28 3645 qla2x00_relogin(base_vha);
7c3df132
SK		 3646 ql_dbg(ql_dbg_dpc, base_vha, 0x400e,
3647 "Relogin end.\n");
1da177e4
LT		 3648 }
3649
e315cd28
AC		 3650 if (test_and_clear_bit(LOOP_RESYNC_NEEDED,
3651 &base_vha->dpc_flags)) {
1da177e4 3652
7c3df132
SK		 3653 ql_dbg(ql_dbg_dpc, base_vha, 0x400f,
3654 "Loop resync scheduled.\n");
1da177e4
LT		 3655
3656 if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE,
e315cd28 3657 &base_vha->dpc_flags))) {
1da177e4 3658
e315cd28 3659 rval = qla2x00_loop_resync(base_vha);
1da177e4 3660
e315cd28
AC		 3661 clear_bit(LOOP_RESYNC_ACTIVE,
3662 &base_vha->dpc_flags);
1da177e4
LT		 3663 }
3664
7c3df132
SK		 3665 ql_dbg(ql_dbg_dpc, base_vha, 0x4010,
3666 "Loop resync end.\n");
1da177e4
LT		 3667 }
3668
e315cd28
AC		 3669 if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) &&
3670 atomic_read(&base_vha->loop_state) == LOOP_READY) {
3671 clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags);
3672 qla2xxx_flash_npiv_conf(base_vha);
272976ca
AV		 3673 }
3674
1da177e4 3675 if (!ha->interrupts_on)
fd34f556 3676 ha->isp_ops->enable_intrs(ha);
1da177e4 3677
e315cd28
AC		 3678 if (test_and_clear_bit(BEACON_BLINK_NEEDED,
3679 &base_vha->dpc_flags))
3680 ha->isp_ops->beacon_blink(base_vha);
f6df144c 3681
e315cd28 3682 qla2x00_do_dpc_all_vps(base_vha);
2c3dfe3f 3683
1da177e4 3684 ha->dpc_active = 0;
563585ec 3685 set_current_state(TASK_INTERRUPTIBLE);
1da177e4 3686 } /* End of while(1) */
563585ec 3687 __set_current_state(TASK_RUNNING);
1da177e4 3688
7c3df132
SK		 3689 ql_dbg(ql_dbg_dpc, base_vha, 0x4011,
3690 "DPC handler exiting.\n");
1da177e4
LT		 3691
3692 /*
3693 * Make sure that nobody tries to wake us up again.
3694 */
1da177e4
LT		 3695 ha->dpc_active = 0;
3696
ac280b67
AV		 3697 /* Cleanup any residual CTX SRBs. */
3698 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
3699
39a11240
CH		 3700 return 0;
3701}
3702
3703void
e315cd28 3704qla2xxx_wake_dpc(struct scsi_qla_host *vha)
39a11240 3705{
e315cd28 3706 struct qla_hw_data *ha = vha->hw;
c795c1e4
AV		 3707 struct task_struct *t = ha->dpc_thread;
3708
e315cd28 3709 if (!test_bit(UNLOADING, &vha->dpc_flags) && t)
c795c1e4 3710 wake_up_process(t);
1da177e4
LT		 3711}
3712
1da177e4
LT		 3713/*
3714* qla2x00_rst_aen
3715* Processes asynchronous reset.
3716*
3717* Input:
3718* ha = adapter block pointer.
3719*/
3720static void
e315cd28 3721qla2x00_rst_aen(scsi_qla_host_t *vha)
1da177e4 3722{
e315cd28
AC		 3723 if (vha->flags.online && !vha->flags.reset_active &&
3724 !atomic_read(&vha->loop_down_timer) &&
3725 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) {
1da177e4 3726 do {
e315cd28 3727 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
1da177e4
LT		 3728
3729 /*
3730 * Issue marker command only when we are going to start
3731 * the I/O.
3732 */
e315cd28
AC		 3733 vha->marker_needed = 1;
3734 } while (!atomic_read(&vha->loop_down_timer) &&
3735 (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)));
1da177e4
LT		 3736 }
3737}
3738
f4f051eb 3739static void
e315cd28 3740qla2x00_sp_free_dma(srb_t *sp)
f4f051eb 3741{
3742 struct scsi_cmnd *cmd = sp->cmd;
bad75002 3743 struct qla_hw_data *ha = sp->fcport->vha->hw;
f4f051eb 3744
3745 if (sp->flags & SRB_DMA_VALID) {
385d70b4 3746 scsi_dma_unmap(cmd);
f4f051eb 3747 sp->flags &= ~SRB_DMA_VALID;
3748 }
bad75002
AE		 3749
3750 if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
3751 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
3752 scsi_prot_sg_count(cmd), cmd->sc_data_direction);
3753 sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
3754 }
3755
3756 if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
3757 /* List assured to be having elements */
3758 qla2x00_clean_dsd_pool(ha, sp);
3759 sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
3760 }
3761
3762 if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
3763 dma_pool_free(ha->dl_dma_pool, sp->ctx,
3764 ((struct crc_context *)sp->ctx)->crc_ctx_dma);
3765 sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
3766 }
3767
fca29703 3768 CMD_SP(cmd) = NULL;
f4f051eb 3769}
3770
3dbe756a 3771static void
083a469d 3772qla2x00_sp_final_compl(struct qla_hw_data *ha, srb_t *sp)
f4f051eb 3773{
3774 struct scsi_cmnd *cmd = sp->cmd;
3775
e315cd28 3776 qla2x00_sp_free_dma(sp);
f4f051eb 3777
a9083016
GM		 3778 if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
3779 struct ct6_dsd *ctx = sp->ctx;
3780 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx->fcp_cmnd,
3781 ctx->fcp_cmnd_dma);
3782 list_splice(&ctx->dsd_list, &ha->gbl_dsd_list);
3783 ha->gbl_dsd_inuse -= ctx->dsd_use_cnt;
3784 ha->gbl_dsd_avail += ctx->dsd_use_cnt;
3785 mempool_free(sp->ctx, ha->ctx_mempool);
3786 sp->ctx = NULL;
3787 }
f4f051eb 3788
a9083016 3789 mempool_free(sp, ha->srb_mempool);
f4f051eb 3790 cmd->scsi_done(cmd);
3791}
bdf79621 3792
083a469d
GM		 3793void
3794qla2x00_sp_compl(struct qla_hw_data *ha, srb_t *sp)
3795{
3796 if (atomic_read(&sp->ref_count) == 0) {
7c3df132
SK		 3797 ql_dbg(ql_dbg_io, sp->fcport->vha, 0x3015,
3798 "SP reference-count to ZERO -- sp=%p cmd=%p.\n",
3799 sp, sp->cmd);
3800 if (ql2xextended_error_logging & ql_dbg_io)
3801 BUG();
083a469d
GM		 3802 return;
3803 }
3804 if (!atomic_dec_and_test(&sp->ref_count))
3805 return;
3806 qla2x00_sp_final_compl(ha, sp);
3807}
3808
1da177e4
LT		 3809/**************************************************************************
3810* qla2x00_timer
3811*
3812* Description:
3813* One second timer
3814*
3815* Context: Interrupt
3816***************************************************************************/
2c3dfe3f 3817void
e315cd28 3818qla2x00_timer(scsi_qla_host_t *vha)
1da177e4 3819{
1da177e4 3820 unsigned long cpu_flags = 0;
1da177e4
LT		 3821 int start_dpc = 0;
3822 int index;
3823 srb_t *sp;
85880801 3824 uint16_t w;
e315cd28 3825 struct qla_hw_data *ha = vha->hw;
73208dfd 3826 struct req_que *req;
85880801 3827
a5b36321 3828 if (ha->flags.eeh_busy) {
7c3df132
SK		 3829 ql_dbg(ql_dbg_timer, vha, 0x6000,
3830 "EEH = %d, restarting timer.\n",
3831 ha->flags.eeh_busy);
a5b36321
LC		 3832 qla2x00_restart_timer(vha, WATCH_INTERVAL);
3833 return;
3834 }
3835
85880801
AV		 3836 /* Hardware read to raise pending EEH errors during mailbox waits. */
3837 if (!pci_channel_offline(ha->pdev))
3838 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w);
1da177e4 3839
cefcaba6
SK		 3840 /* Make sure qla82xx_watchdog is run only for physical port */
3841 if (!vha->vp_idx && IS_QLA82XX(ha)) {
579d12b5
SK		 3842 if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags))
3843 start_dpc++;
3844 qla82xx_watchdog(vha);
3845 }
3846
1da177e4 3847 /* Loop down handler. */
e315cd28 3848 if (atomic_read(&vha->loop_down_timer) > 0 &&
8f7daead
GM		 3849 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) &&
3850 !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags))
e315cd28 3851 && vha->flags.online) {
1da177e4 3852
e315cd28
AC		 3853 if (atomic_read(&vha->loop_down_timer) ==
3854 vha->loop_down_abort_time) {
1da177e4 3855
7c3df132
SK		 3856 ql_log(ql_log_info, vha, 0x6008,
3857 "Loop down - aborting the queues before time expires.\n");
1da177e4 3858
e315cd28
AC		 3859 if (!IS_QLA2100(ha) && vha->link_down_timeout)
3860 atomic_set(&vha->loop_state, LOOP_DEAD);
1da177e4 3861
f08b7251
AV		 3862 /*
3863 * Schedule an ISP abort to return any FCP2-device
3864 * commands.
3865 */
2c3dfe3f 3866 /* NPIV - scan physical port only */
e315cd28 3867 if (!vha->vp_idx) {
2c3dfe3f
SJ		 3868 spin_lock_irqsave(&ha->hardware_lock,
3869 cpu_flags);
73208dfd 3870 req = ha->req_q_map[0];
2c3dfe3f
SJ		 3871 for (index = 1;
3872 index < MAX_OUTSTANDING_COMMANDS;
3873 index++) {
3874 fc_port_t *sfcp;
3875
e315cd28 3876 sp = req->outstanding_cmds[index];
2c3dfe3f
SJ		 3877 if (!sp)
3878 continue;
bad75002 3879 if (sp->ctx && !IS_PROT_IO(sp))
cf53b069 3880 continue;
2c3dfe3f 3881 sfcp = sp->fcport;
f08b7251 3882 if (!(sfcp->flags & FCF_FCP2_DEVICE))
2c3dfe3f 3883 continue;
bdf79621 3884
8f7daead
GM		 3885 if (IS_QLA82XX(ha))
3886 set_bit(FCOE_CTX_RESET_NEEDED,
3887 &vha->dpc_flags);
3888 else
3889 set_bit(ISP_ABORT_NEEDED,
e315cd28 3890 &vha->dpc_flags);
2c3dfe3f
SJ		 3891 break;
3892 }
3893 spin_unlock_irqrestore(&ha->hardware_lock,
e315cd28 3894 cpu_flags);
1da177e4 3895 }
1da177e4
LT		 3896 start_dpc++;
3897 }
3898
3899 /* if the loop has been down for 4 minutes, reinit adapter */
e315cd28 3900 if (atomic_dec_and_test(&vha->loop_down_timer) != 0) {
0d6e61bc 3901 if (!(vha->device_flags & DFLG_NO_CABLE)) {
7c3df132 3902 ql_log(ql_log_warn, vha, 0x6009,
1da177e4
LT		 3903 "Loop down - aborting ISP.\n");
3904
8f7daead
GM		 3905 if (IS_QLA82XX(ha))
3906 set_bit(FCOE_CTX_RESET_NEEDED,
3907 &vha->dpc_flags);
3908 else
3909 set_bit(ISP_ABORT_NEEDED,
3910 &vha->dpc_flags);
1da177e4
LT		 3911 }
3912 }
7c3df132
SK		 3913 ql_dbg(ql_dbg_timer, vha, 0x600a,
3914 "Loop down - seconds remaining %d.\n",
3915 atomic_read(&vha->loop_down_timer));
1da177e4
LT		 3916 }
3917
cefcaba6
SK		 3918 /* Check if beacon LED needs to be blinked for physical host only */
3919 if (!vha->vp_idx && (ha->beacon_blink_led == 1)) {
999916dc
SK		 3920 /* There is no beacon_blink function for ISP82xx */
3921 if (!IS_QLA82XX(ha)) {
3922 set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags);
3923 start_dpc++;
3924 }
f6df144c 3925 }
3926
550bf57d 3927 /* Process any deferred work. */
e315cd28 3928 if (!list_empty(&vha->work_list))
550bf57d
AV		 3929 start_dpc++;
3930
1da177e4 3931 /* Schedule the DPC routine if needed */
e315cd28
AC		 3932 if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) ||
3933 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) ||
3934 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags) ||
1da177e4 3935 start_dpc ||
e315cd28
AC		 3936 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) ||
3937 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) ||
a9083016
GM		 3938 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) ||
3939 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) ||
e315cd28 3940 test_bit(VP_DPC_NEEDED, &vha->dpc_flags) ||
7c3df132
SK		 3941 test_bit(RELOGIN_NEEDED, &vha->dpc_flags))) {
3942 ql_dbg(ql_dbg_timer, vha, 0x600b,
3943 "isp_abort_needed=%d loop_resync_needed=%d "
3944 "fcport_update_needed=%d start_dpc=%d "
3945 "reset_marker_needed=%d",
3946 test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags),
3947 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags),
3948 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags),
3949 start_dpc,
3950 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags));
3951 ql_dbg(ql_dbg_timer, vha, 0x600c,
3952 "beacon_blink_needed=%d isp_unrecoverable=%d "
3953 "fcoe_ctx_reset_needed=%d vp_dpc_needed=%d "
3954 "relogin_needed=%d.\n",
3955 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags),
3956 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags),
3957 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags),
3958 test_bit(VP_DPC_NEEDED, &vha->dpc_flags),
3959 test_bit(RELOGIN_NEEDED, &vha->dpc_flags));
e315cd28 3960 qla2xxx_wake_dpc(vha);
7c3df132 3961 }
1da177e4 3962
e315cd28 3963 qla2x00_restart_timer(vha, WATCH_INTERVAL);
1da177e4
LT		 3964}
3965
5433383e
AV		 3966/* Firmware interface routines. */
3967
a9083016 3968#define FW_BLOBS 8
5433383e
AV		 3969#define FW_ISP21XX 0
3970#define FW_ISP22XX 1
3971#define FW_ISP2300 2
3972#define FW_ISP2322 3
48c02fde 3973#define FW_ISP24XX 4
c3a2f0df 3974#define FW_ISP25XX 5
3a03eb79 3975#define FW_ISP81XX 6
a9083016 3976#define FW_ISP82XX 7
5433383e 3977
bb8ee499
AV		 3978#define FW_FILE_ISP21XX "ql2100_fw.bin"
3979#define FW_FILE_ISP22XX "ql2200_fw.bin"
3980#define FW_FILE_ISP2300 "ql2300_fw.bin"
3981#define FW_FILE_ISP2322 "ql2322_fw.bin"
3982#define FW_FILE_ISP24XX "ql2400_fw.bin"
c3a2f0df 3983#define FW_FILE_ISP25XX "ql2500_fw.bin"
3a03eb79 3984#define FW_FILE_ISP81XX "ql8100_fw.bin"
a9083016 3985#define FW_FILE_ISP82XX "ql8200_fw.bin"
bb8ee499 3986
e1e82b6f 3987static DEFINE_MUTEX(qla_fw_lock);
5433383e
AV		 3988
3989static struct fw_blob qla_fw_blobs[FW_BLOBS] = {
bb8ee499
AV		 3990 { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, },
3991 { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, },
3992 { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, },
3993 { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, },
3994 { .name = FW_FILE_ISP24XX, },
c3a2f0df 3995 { .name = FW_FILE_ISP25XX, },
3a03eb79 3996 { .name = FW_FILE_ISP81XX, },
a9083016 3997 { .name = FW_FILE_ISP82XX, },
5433383e
AV		 3998};
3999
4000struct fw_blob *
e315cd28 4001qla2x00_request_firmware(scsi_qla_host_t *vha)
5433383e 4002{
e315cd28 4003 struct qla_hw_data *ha = vha->hw;
5433383e
AV		 4004 struct fw_blob *blob;
4005
4006 blob = NULL;
4007 if (IS_QLA2100(ha)) {
4008 blob = &qla_fw_blobs[FW_ISP21XX];
4009 } else if (IS_QLA2200(ha)) {
4010 blob = &qla_fw_blobs[FW_ISP22XX];
48c02fde 4011 } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
5433383e 4012 blob = &qla_fw_blobs[FW_ISP2300];
48c02fde 4013 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
5433383e 4014 blob = &qla_fw_blobs[FW_ISP2322];
4d4df193 4015 } else if (IS_QLA24XX_TYPE(ha)) {
5433383e 4016 blob = &qla_fw_blobs[FW_ISP24XX];
c3a2f0df
AV		 4017 } else if (IS_QLA25XX(ha)) {
4018 blob = &qla_fw_blobs[FW_ISP25XX];
3a03eb79
AV		 4019 } else if (IS_QLA81XX(ha)) {
4020 blob = &qla_fw_blobs[FW_ISP81XX];
a9083016
GM		 4021 } else if (IS_QLA82XX(ha)) {
4022 blob = &qla_fw_blobs[FW_ISP82XX];
5433383e
AV		 4023 }
4024
e1e82b6f 4025 mutex_lock(&qla_fw_lock);
5433383e
AV		 4026 if (blob->fw)
4027 goto out;
4028
4029 if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) {
7c3df132
SK		 4030 ql_log(ql_log_warn, vha, 0x0063,
4031 "Failed to load firmware image (%s).\n", blob->name);
5433383e
AV		 4032 blob->fw = NULL;
4033 blob = NULL;
4034 goto out;
4035 }
4036
4037out:
e1e82b6f 4038 mutex_unlock(&qla_fw_lock);
5433383e
AV		 4039 return blob;
4040}
4041
4042static void
4043qla2x00_release_firmware(void)
4044{
4045 int idx;
4046
e1e82b6f 4047 mutex_lock(&qla_fw_lock);
5433383e
AV		 4048 for (idx = 0; idx < FW_BLOBS; idx++)
4049 if (qla_fw_blobs[idx].fw)
4050 release_firmware(qla_fw_blobs[idx].fw);
e1e82b6f 4051 mutex_unlock(&qla_fw_lock);
5433383e
AV		 4052}
4053
14e660e6
SJ		 4054static pci_ers_result_t
4055qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
4056{
85880801
AV		 4057 scsi_qla_host_t *vha = pci_get_drvdata(pdev);
4058 struct qla_hw_data *ha = vha->hw;
4059
7c3df132
SK		 4060 ql_dbg(ql_dbg_aer, vha, 0x9000,
4061 "PCI error detected, state %x.\n", state);
b9b12f73 4062
14e660e6
SJ		 4063 switch (state) {
4064 case pci_channel_io_normal:
85880801 4065 ha->flags.eeh_busy = 0;
14e660e6
SJ		 4066 return PCI_ERS_RESULT_CAN_RECOVER;
4067 case pci_channel_io_frozen:
85880801 4068 ha->flags.eeh_busy = 1;
a5b36321
LC		 4069 /* For ISP82XX complete any pending mailbox cmd */
4070 if (IS_QLA82XX(ha)) {
7190575f 4071 ha->flags.isp82xx_fw_hung = 1;
a5b36321
LC		 4072 if (ha->flags.mbox_busy) {
4073 ha->flags.mbox_int = 1;
7c3df132
SK		 4074 ql_dbg(ql_dbg_aer, vha, 0x9001,
4075 "Due to pci channel io frozen, doing premature "
4076 "completion of mbx command.\n");
a5b36321
LC		 4077 complete(&ha->mbx_intr_comp);
4078 }
4079 }
90a86fc0 4080 qla2x00_free_irqs(vha);
14e660e6 4081 pci_disable_device(pdev);
bddd2d65
LC		 4082 /* Return back all IOs */
4083 qla2x00_abort_all_cmds(vha, DID_RESET << 16);
14e660e6
SJ		 4084 return PCI_ERS_RESULT_NEED_RESET;
4085 case pci_channel_io_perm_failure:
85880801
AV		 4086 ha->flags.pci_channel_io_perm_failure = 1;
4087 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
14e660e6
SJ		 4088 return PCI_ERS_RESULT_DISCONNECT;
4089 }
4090 return PCI_ERS_RESULT_NEED_RESET;
4091}
4092
4093static pci_ers_result_t
4094qla2xxx_pci_mmio_enabled(struct pci_dev *pdev)
4095{
4096 int risc_paused = 0;
4097 uint32_t stat;
4098 unsigned long flags;
e315cd28
AC		 4099 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
4100 struct qla_hw_data *ha = base_vha->hw;
14e660e6
SJ		 4101 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
4102 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
4103
bcc5b6d3
SK		 4104 if (IS_QLA82XX(ha))
4105 return PCI_ERS_RESULT_RECOVERED;
4106
14e660e6
SJ		 4107 spin_lock_irqsave(&ha->hardware_lock, flags);
4108 if (IS_QLA2100(ha) || IS_QLA2200(ha)){
4109 stat = RD_REG_DWORD(&reg->hccr);
4110 if (stat & HCCR_RISC_PAUSE)
4111 risc_paused = 1;
4112 } else if (IS_QLA23XX(ha)) {
4113 stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
4114 if (stat & HSR_RISC_PAUSED)
4115 risc_paused = 1;
4116 } else if (IS_FWI2_CAPABLE(ha)) {
4117 stat = RD_REG_DWORD(&reg24->host_status);
4118 if (stat & HSRX_RISC_PAUSED)
4119 risc_paused = 1;
4120 }
4121 spin_unlock_irqrestore(&ha->hardware_lock, flags);
4122
4123 if (risc_paused) {
7c3df132
SK		 4124 ql_log(ql_log_info, base_vha, 0x9003,
4125 "RISC paused -- mmio_enabled, Dumping firmware.\n");
e315cd28 4126 ha->isp_ops->fw_dump(base_vha, 0);
14e660e6
SJ		 4127
4128 return PCI_ERS_RESULT_NEED_RESET;
4129 } else
4130 return PCI_ERS_RESULT_RECOVERED;
4131}
4132
a5b36321
LC		 4133uint32_t qla82xx_error_recovery(scsi_qla_host_t *base_vha)
4134{
4135 uint32_t rval = QLA_FUNCTION_FAILED;
4136 uint32_t drv_active = 0;
4137 struct qla_hw_data *ha = base_vha->hw;
4138 int fn;
4139 struct pci_dev *other_pdev = NULL;
4140
7c3df132
SK		 4141 ql_dbg(ql_dbg_aer, base_vha, 0x9006,
4142 "Entered %s.\n", __func__);
a5b36321
LC		 4143
4144 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
4145
4146 if (base_vha->flags.online) {
4147 /* Abort all outstanding commands,
4148 * so as to be requeued later */
4149 qla2x00_abort_isp_cleanup(base_vha);
4150 }
4151
4152
4153 fn = PCI_FUNC(ha->pdev->devfn);
4154 while (fn > 0) {
4155 fn--;
7c3df132
SK		 4156 ql_dbg(ql_dbg_aer, base_vha, 0x9007,
4157 "Finding pci device at function = 0x%x.\n", fn);
a5b36321
LC		 4158 other_pdev =
4159 pci_get_domain_bus_and_slot(pci_domain_nr(ha->pdev->bus),
4160 ha->pdev->bus->number, PCI_DEVFN(PCI_SLOT(ha->pdev->devfn),
4161 fn));
4162
4163 if (!other_pdev)
4164 continue;
4165 if (atomic_read(&other_pdev->enable_cnt)) {
7c3df132
SK		 4166 ql_dbg(ql_dbg_aer, base_vha, 0x9008,
4167 "Found PCI func available and enable at 0x%x.\n",
4168 fn);
a5b36321
LC		 4169 pci_dev_put(other_pdev);
4170 break;
4171 }
4172 pci_dev_put(other_pdev);
4173 }
4174
4175 if (!fn) {
4176 /* Reset owner */
7c3df132
SK		 4177 ql_dbg(ql_dbg_aer, base_vha, 0x9009,
4178 "This devfn is reset owner = 0x%x.\n",
4179 ha->pdev->devfn);
a5b36321
LC		 4180 qla82xx_idc_lock(ha);
4181
4182 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
4183 QLA82XX_DEV_INITIALIZING);
4184
4185 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION,
4186 QLA82XX_IDC_VERSION);
4187
4188 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
7c3df132
SK		 4189 ql_dbg(ql_dbg_aer, base_vha, 0x900a,
4190 "drv_active = 0x%x.\n", drv_active);
a5b36321
LC		 4191
4192 qla82xx_idc_unlock(ha);
4193 /* Reset if device is not already reset
4194 * drv_active would be 0 if a reset has already been done
4195 */
4196 if (drv_active)
4197 rval = qla82xx_start_firmware(base_vha);
4198 else
4199 rval = QLA_SUCCESS;
4200 qla82xx_idc_lock(ha);
4201
4202 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4203 ql_log(ql_log_info, base_vha, 0x900b,
4204 "HW State: FAILED.\n");
a5b36321
LC		 4205 qla82xx_clear_drv_active(ha);
4206 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
4207 QLA82XX_DEV_FAILED);
4208 } else {
7c3df132
SK		 4209 ql_log(ql_log_info, base_vha, 0x900c,
4210 "HW State: READY.\n");
a5b36321
LC		 4211 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
4212 QLA82XX_DEV_READY);
4213 qla82xx_idc_unlock(ha);
7190575f 4214 ha->flags.isp82xx_fw_hung = 0;
a5b36321
LC		 4215 rval = qla82xx_restart_isp(base_vha);
4216 qla82xx_idc_lock(ha);
4217 /* Clear driver state register */
4218 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, 0);
4219 qla82xx_set_drv_active(base_vha);
4220 }
4221 qla82xx_idc_unlock(ha);
4222 } else {
7c3df132
SK		 4223 ql_dbg(ql_dbg_aer, base_vha, 0x900d,
4224 "This devfn is not reset owner = 0x%x.\n",
4225 ha->pdev->devfn);
a5b36321
LC		 4226 if ((qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE) ==
4227 QLA82XX_DEV_READY)) {
7190575f 4228 ha->flags.isp82xx_fw_hung = 0;
a5b36321
LC		 4229 rval = qla82xx_restart_isp(base_vha);
4230 qla82xx_idc_lock(ha);
4231 qla82xx_set_drv_active(base_vha);
4232 qla82xx_idc_unlock(ha);
4233 }
4234 }
4235 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
4236
4237 return rval;
4238}
4239
14e660e6
SJ		 4240static pci_ers_result_t
4241qla2xxx_pci_slot_reset(struct pci_dev *pdev)
4242{
4243 pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT;
e315cd28
AC		 4244 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
4245 struct qla_hw_data *ha = base_vha->hw;
90a86fc0
JC		 4246 struct rsp_que *rsp;
4247 int rc, retries = 10;
09483916 4248
7c3df132
SK		 4249 ql_dbg(ql_dbg_aer, base_vha, 0x9004,
4250 "Slot Reset.\n");
85880801 4251
90a86fc0
JC		 4252 /* Workaround: qla2xxx driver which access hardware earlier
4253 * needs error state to be pci_channel_io_online.
4254 * Otherwise mailbox command timesout.
4255 */
4256 pdev->error_state = pci_channel_io_normal;
4257
4258 pci_restore_state(pdev);
4259
8c1496bd
RL		 4260 /* pci_restore_state() clears the saved_state flag of the device
4261 * save restored state which resets saved_state flag
4262 */
4263 pci_save_state(pdev);
4264
09483916
BH		 4265 if (ha->mem_only)
4266 rc = pci_enable_device_mem(pdev);
4267 else
4268 rc = pci_enable_device(pdev);
14e660e6 4269
09483916 4270 if (rc) {
7c3df132 4271 ql_log(ql_log_warn, base_vha, 0x9005,
14e660e6 4272 "Can't re-enable PCI device after reset.\n");
a5b36321 4273 goto exit_slot_reset;
14e660e6 4274 }
14e660e6 4275
90a86fc0
JC		 4276 rsp = ha->rsp_q_map[0];
4277 if (qla2x00_request_irqs(ha, rsp))
a5b36321 4278 goto exit_slot_reset;
90a86fc0 4279
e315cd28 4280 if (ha->isp_ops->pci_config(base_vha))
a5b36321
LC		 4281 goto exit_slot_reset;
4282
4283 if (IS_QLA82XX(ha)) {
4284 if (qla82xx_error_recovery(base_vha) == QLA_SUCCESS) {
4285 ret = PCI_ERS_RESULT_RECOVERED;
4286 goto exit_slot_reset;
4287 } else
4288 goto exit_slot_reset;
4289 }
14e660e6 4290
90a86fc0
JC		 4291 while (ha->flags.mbox_busy && retries--)
4292 msleep(1000);
85880801 4293
e315cd28 4294 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
a9083016 4295 if (ha->isp_ops->abort_isp(base_vha) == QLA_SUCCESS)
14e660e6 4296 ret = PCI_ERS_RESULT_RECOVERED;
e315cd28 4297 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
14e660e6 4298
90a86fc0 4299
a5b36321 4300exit_slot_reset:
7c3df132
SK		 4301 ql_dbg(ql_dbg_aer, base_vha, 0x900e,
4302 "slot_reset return %x.\n", ret);
85880801 4303
14e660e6
SJ		 4304 return ret;
4305}
4306
4307static void
4308qla2xxx_pci_resume(struct pci_dev *pdev)
4309{
e315cd28
AC		 4310 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
4311 struct qla_hw_data *ha = base_vha->hw;
14e660e6
SJ		 4312 int ret;
4313
7c3df132
SK		 4314 ql_dbg(ql_dbg_aer, base_vha, 0x900f,
4315 "pci_resume.\n");
85880801 4316
e315cd28 4317 ret = qla2x00_wait_for_hba_online(base_vha);
14e660e6 4318 if (ret != QLA_SUCCESS) {
7c3df132
SK		 4319 ql_log(ql_log_fatal, base_vha, 0x9002,
4320 "The device failed to resume I/O from slot/link_reset.\n");
14e660e6 4321 }
85880801 4322
3e46f031
LC		 4323 pci_cleanup_aer_uncorrect_error_status(pdev);
4324
85880801 4325 ha->flags.eeh_busy = 0;
14e660e6
SJ		 4326}
4327
4328static struct pci_error_handlers qla2xxx_err_handler = {
4329 .error_detected = qla2xxx_pci_error_detected,
4330 .mmio_enabled = qla2xxx_pci_mmio_enabled,
4331 .slot_reset = qla2xxx_pci_slot_reset,
4332 .resume = qla2xxx_pci_resume,
4333};
4334
5433383e 4335static struct pci_device_id qla2xxx_pci_tbl[] = {
47f5e069
AV		 4336 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) },
4337 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) },
4338 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) },
4339 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) },
4340 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) },
4341 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) },
4342 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) },
4343 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) },
4344 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) },
4d4df193 4345 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) },
47f5e069
AV		 4346 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) },
4347 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) },
c3a2f0df 4348 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) },
3a03eb79 4349 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) },
a9083016 4350 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) },
5433383e
AV		 4351 { 0 },
4352};
4353MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl);
4354
fca29703 4355static struct pci_driver qla2xxx_pci_driver = {
cb63067a 4356 .name = QLA2XXX_DRIVER_NAME,
0a21ef1e
JB		 4357 .driver = {
4358 .owner = THIS_MODULE,
4359 },
fca29703 4360 .id_table = qla2xxx_pci_tbl,
7ee61397 4361 .probe = qla2x00_probe_one,
4c993f76 4362 .remove = qla2x00_remove_one,
e30d1756 4363 .shutdown = qla2x00_shutdown,
14e660e6 4364 .err_handler = &qla2xxx_err_handler,
fca29703
AV		 4365};
4366
6a03b4cd
HZ		 4367static struct file_operations apidev_fops = {
4368 .owner = THIS_MODULE,
6038f373 4369 .llseek = noop_llseek,
6a03b4cd
HZ		 4370};
4371
1da177e4
LT		 4372/**
4373 * qla2x00_module_init - Module initialization.
4374 **/
4375static int __init
4376qla2x00_module_init(void)
4377{
fca29703
AV		 4378 int ret = 0;
4379
1da177e4 4380 /* Allocate cache for SRBs. */
354d6b21 4381 srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0,
20c2df83 4382 SLAB_HWCACHE_ALIGN, NULL);
1da177e4 4383 if (srb_cachep == NULL) {
7c3df132
SK		 4384 ql_log(ql_log_fatal, NULL, 0x0001,
4385 "Unable to allocate SRB cache...Failing load!.\n");
1da177e4
LT		 4386 return -ENOMEM;
4387 }
4388
4389 /* Derive version string. */
4390 strcpy(qla2x00_version_str, QLA2XXX_VERSION);
11010fec 4391 if (ql2xextended_error_logging)
0181944f
AV		 4392 strcat(qla2x00_version_str, "-debug");
4393
1c97a12a
AV		 4394 qla2xxx_transport_template =
4395 fc_attach_transport(&qla2xxx_transport_functions);
2c3dfe3f
SJ		 4396 if (!qla2xxx_transport_template) {
4397 kmem_cache_destroy(srb_cachep);
7c3df132
SK		 4398 ql_log(ql_log_fatal, NULL, 0x0002,
4399 "fc_attach_transport failed...Failing load!.\n");
1da177e4 4400 return -ENODEV;
2c3dfe3f 4401 }
6a03b4cd
HZ		 4402
4403 apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops);
4404 if (apidev_major < 0) {
7c3df132
SK		 4405 ql_log(ql_log_fatal, NULL, 0x0003,
4406 "Unable to register char device %s.\n", QLA2XXX_APIDEV);
6a03b4cd
HZ		 4407 }
4408
2c3dfe3f
SJ		 4409 qla2xxx_transport_vport_template =
4410 fc_attach_transport(&qla2xxx_transport_vport_functions);
4411 if (!qla2xxx_transport_vport_template) {
4412 kmem_cache_destroy(srb_cachep);
4413 fc_release_transport(qla2xxx_transport_template);
7c3df132
SK		 4414 ql_log(ql_log_fatal, NULL, 0x0004,
4415 "fc_attach_transport vport failed...Failing load!.\n");
1da177e4 4416 return -ENODEV;
2c3dfe3f 4417 }
7c3df132
SK		 4418 ql_log(ql_log_info, NULL, 0x0005,
4419 "QLogic Fibre Channel HBA Driver: %s.\n",
fd9a29f0 4420 qla2x00_version_str);
7ee61397 4421 ret = pci_register_driver(&qla2xxx_pci_driver);
fca29703
AV		 4422 if (ret) {
4423 kmem_cache_destroy(srb_cachep);
4424 fc_release_transport(qla2xxx_transport_template);
2c3dfe3f 4425 fc_release_transport(qla2xxx_transport_vport_template);
7c3df132
SK		 4426 ql_log(ql_log_fatal, NULL, 0x0006,
4427 "pci_register_driver failed...ret=%d Failing load!.\n",
4428 ret);
fca29703
AV		 4429 }
4430 return ret;
1da177e4
LT		 4431}
4432
4433/**
4434 * qla2x00_module_exit - Module cleanup.
4435 **/
4436static void __exit
4437qla2x00_module_exit(void)
4438{
6a03b4cd 4439 unregister_chrdev(apidev_major, QLA2XXX_APIDEV);
7ee61397 4440 pci_unregister_driver(&qla2xxx_pci_driver);
5433383e 4441 qla2x00_release_firmware();
354d6b21 4442 kmem_cache_destroy(srb_cachep);
a9083016
GM		 4443 if (ctx_cachep)
4444 kmem_cache_destroy(ctx_cachep);
1da177e4 4445 fc_release_transport(qla2xxx_transport_template);
2c3dfe3f 4446 fc_release_transport(qla2xxx_transport_vport_template);
1da177e4
LT		 4447}
4448
4449module_init(qla2x00_module_init);
4450module_exit(qla2x00_module_exit);
4451
4452MODULE_AUTHOR("QLogic Corporation");
4453MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver");
4454MODULE_LICENSE("GPL");
4455MODULE_VERSION(QLA2XXX_VERSION);
bb8ee499
AV		 4456MODULE_FIRMWARE(FW_FILE_ISP21XX);
4457MODULE_FIRMWARE(FW_FILE_ISP22XX);
4458MODULE_FIRMWARE(FW_FILE_ISP2300);
4459MODULE_FIRMWARE(FW_FILE_ISP2322);
4460MODULE_FIRMWARE(FW_FILE_ISP24XX);
61623fc3 4461MODULE_FIRMWARE(FW_FILE_ISP25XX);
Linux 6.x block layer and io_uring tree(s)