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scsi: qla2xxx: Leave a blank line after declarations
[linux-2.6-block.git] / drivers / scsi / qla2xxx / qla_os.c
CommitLineData
1da177e4 1/*
fa90c54f 2 * QLogic Fibre Channel HBA Driver
bd21eaf9 3 * Copyright (c) 2003-2014 QLogic Corporation
1da177e4 4 *
fa90c54f 5 * See LICENSE.qla2xxx for copyright and licensing details.
1da177e4
LT		 6 */
7#include "qla_def.h"
8
9#include <linux/moduleparam.h>
10#include <linux/vmalloc.h>
1da177e4 11#include <linux/delay.h>
39a11240 12#include <linux/kthread.h>
e1e82b6f 13#include <linux/mutex.h>
3420d36c 14#include <linux/kobject.h>
5a0e3ad6 15#include <linux/slab.h>
5601236b 16#include <linux/blk-mq-pci.h>
585def9b
QT		 17#include <linux/refcount.h>
18
1da177e4
LT		 19#include <scsi/scsi_tcq.h>
20#include <scsi/scsicam.h>
21#include <scsi/scsi_transport.h>
22#include <scsi/scsi_transport_fc.h>
23
2d70c103
NB		 24#include "qla_target.h"
25
1da177e4
LT		 26/*
27 * Driver version
28 */
29char qla2x00_version_str[40];
30
6a03b4cd
HZ		 31static int apidev_major;
32
1da177e4
LT		 33/*
34 * SRB allocation cache
35 */
d7459527 36struct kmem_cache *srb_cachep;
1da177e4 37
a9083016
GM		 38/*
39 * CT6 CTX allocation cache
40 */
41static struct kmem_cache *ctx_cachep;
3ce8866c
SK		 42/*
43 * error level for logging
44 */
3f006ac3 45uint ql_errlev = 0x8001;
a9083016 46
fa492630 47static int ql2xenableclass2;
2d70c103
NB		 48module_param(ql2xenableclass2, int, S_IRUGO|S_IRUSR);
49MODULE_PARM_DESC(ql2xenableclass2,
50 "Specify if Class 2 operations are supported from the very "
51 "beginning. Default is 0 - class 2 not supported.");
52
8ae6d9c7 53
1da177e4 54int ql2xlogintimeout = 20;
f2019cb1 55module_param(ql2xlogintimeout, int, S_IRUGO);
1da177e4
LT		 56MODULE_PARM_DESC(ql2xlogintimeout,
57 "Login timeout value in seconds.");
58
a7b61842 59int qlport_down_retry;
f2019cb1 60module_param(qlport_down_retry, int, S_IRUGO);
1da177e4 61MODULE_PARM_DESC(qlport_down_retry,
900d9f98 62 "Maximum number of command retries to a port that returns "
1da177e4
LT		 63 "a PORT-DOWN status.");
64
1da177e4
LT		 65int ql2xplogiabsentdevice;
66module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR);
67MODULE_PARM_DESC(ql2xplogiabsentdevice,
68 "Option to enable PLOGI to devices that are not present after "
900d9f98 69 "a Fabric scan. This is needed for several broken switches. "
0d52e642 70 "Default is 0 - no PLOGI. 1 - perform PLOGI.");
1da177e4 71
1da177e4 72int ql2xloginretrycount = 0;
f2019cb1 73module_param(ql2xloginretrycount, int, S_IRUGO);
1da177e4
LT		 74MODULE_PARM_DESC(ql2xloginretrycount,
75 "Specify an alternate value for the NVRAM login retry count.");
76
a7a167bf 77int ql2xallocfwdump = 1;
f2019cb1 78module_param(ql2xallocfwdump, int, S_IRUGO);
a7a167bf
AV		 79MODULE_PARM_DESC(ql2xallocfwdump,
80 "Option to enable allocation of memory for a firmware dump "
81 "during HBA initialization. Memory allocation requirements "
82 "vary by ISP type. Default is 1 - allocate memory.");
83
11010fec 84int ql2xextended_error_logging;
27d94035 85module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
a2b3e01d 86module_param_named(logging, ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
11010fec 87MODULE_PARM_DESC(ql2xextended_error_logging,
3ce8866c
SK		 88 "Option to enable extended error logging,\n"
89 "\t\tDefault is 0 - no logging. 0x40000000 - Module Init & Probe.\n"
90 "\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n"
91 "\t\t0x08000000 - IO tracing. 0x04000000 - DPC Thread.\n"
92 "\t\t0x02000000 - Async events. 0x01000000 - Timer routines.\n"
93 "\t\t0x00800000 - User space. 0x00400000 - Task Management.\n"
94 "\t\t0x00200000 - AER/EEH. 0x00100000 - Multi Q.\n"
95 "\t\t0x00080000 - P3P Specific. 0x00040000 - Virtual Port.\n"
96 "\t\t0x00020000 - Buffer Dump. 0x00010000 - Misc.\n"
29f9f90c
CD		 97 "\t\t0x00008000 - Verbose. 0x00004000 - Target.\n"
98 "\t\t0x00002000 - Target Mgmt. 0x00001000 - Target TMF.\n"
3ce8866c 99 "\t\t0x7fffffff - For enabling all logs, can be too many logs.\n"
cfb0919c
CD		 100 "\t\t0x1e400000 - Preferred value for capturing essential "
101 "debug information (equivalent to old "
102 "ql2xextended_error_logging=1).\n"
3ce8866c 103 "\t\tDo LOGICAL OR of the value to enable more than one level");
0181944f 104
a9083016 105int ql2xshiftctondsd = 6;
f2019cb1 106module_param(ql2xshiftctondsd, int, S_IRUGO);
a9083016
GM		 107MODULE_PARM_DESC(ql2xshiftctondsd,
108 "Set to control shifting of command type processing "
109 "based on total number of SG elements.");
110
7e47e5ca 111int ql2xfdmienable=1;
de187df8 112module_param(ql2xfdmienable, int, S_IRUGO|S_IWUSR);
a2b3e01d 113module_param_named(fdmi, ql2xfdmienable, int, S_IRUGO|S_IWUSR);
cca5335c 114MODULE_PARM_DESC(ql2xfdmienable,
7794a5af
FW		 115 "Enables FDMI registrations. "
116 "0 - no FDMI. Default is 1 - perform FDMI.");
cca5335c 117
d213a4b7 118#define MAX_Q_DEPTH 64
50280c01 119static int ql2xmaxqdepth = MAX_Q_DEPTH;
df7baa50
AV		 120module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR);
121MODULE_PARM_DESC(ql2xmaxqdepth,
e92e4a8f 122 "Maximum queue depth to set for each LUN. "
d213a4b7 123 "Default is 64.");
df7baa50 124
e84067d7
DG		 125#if (IS_ENABLED(CONFIG_NVME_FC))
126int ql2xenabledif;
127#else
9e522cd8 128int ql2xenabledif = 2;
e84067d7 129#endif
9e522cd8 130module_param(ql2xenabledif, int, S_IRUGO);
bad75002 131MODULE_PARM_DESC(ql2xenabledif,
b97f5d0b
SM		 132 " Enable T10-CRC-DIF:\n"
133 " Default is 2.\n"
134 " 0 -- No DIF Support\n"
135 " 1 -- Enable DIF for all types\n"
136 " 2 -- Enable DIF for all types, except Type 0.\n");
bad75002 137
e84067d7
DG		 138#if (IS_ENABLED(CONFIG_NVME_FC))
139int ql2xnvmeenable = 1;
140#else
141int ql2xnvmeenable;
142#endif
143module_param(ql2xnvmeenable, int, 0644);
144MODULE_PARM_DESC(ql2xnvmeenable,
145 "Enables NVME support. "
146 "0 - no NVMe. Default is Y");
147
8cb2049c 148int ql2xenablehba_err_chk = 2;
bad75002
AE		 149module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR);
150MODULE_PARM_DESC(ql2xenablehba_err_chk,
8cb2049c 151 " Enable T10-CRC-DIF Error isolation by HBA:\n"
b97f5d0b 152 " Default is 2.\n"
8cb2049c
AE		 153 " 0 -- Error isolation disabled\n"
154 " 1 -- Error isolation enabled only for DIX Type 0\n"
155 " 2 -- Error isolation enabled for all Types\n");
bad75002 156
e5896bd5 157int ql2xiidmaenable=1;
f2019cb1 158module_param(ql2xiidmaenable, int, S_IRUGO);
e5896bd5
AV		 159MODULE_PARM_DESC(ql2xiidmaenable,
160 "Enables iIDMA settings "
161 "Default is 1 - perform iIDMA. 0 - no iIDMA.");
162
d7459527
MH		 163int ql2xmqsupport = 1;
164module_param(ql2xmqsupport, int, S_IRUGO);
165MODULE_PARM_DESC(ql2xmqsupport,
166 "Enable on demand multiple queue pairs support "
167 "Default is 1 for supported. "
168 "Set it to 0 to turn off mq qpair support.");
e337d907
AV		 169
170int ql2xfwloadbin;
86e45bf6 171module_param(ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
a2b3e01d 172module_param_named(fwload, ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
e337d907 173MODULE_PARM_DESC(ql2xfwloadbin,
7c3df132
SK		 174 "Option to specify location from which to load ISP firmware:.\n"
175 " 2 -- load firmware via the request_firmware() (hotplug).\n"
e337d907
AV		 176 " interface.\n"
177 " 1 -- load firmware from flash.\n"
178 " 0 -- use default semantics.\n");
179
ae97c91e 180int ql2xetsenable;
f2019cb1 181module_param(ql2xetsenable, int, S_IRUGO);
ae97c91e
AV		 182MODULE_PARM_DESC(ql2xetsenable,
183 "Enables firmware ETS burst."
184 "Default is 0 - skip ETS enablement.");
185
6907869d 186int ql2xdbwr = 1;
86e45bf6 187module_param(ql2xdbwr, int, S_IRUGO|S_IWUSR);
a9083016 188MODULE_PARM_DESC(ql2xdbwr,
08de2844
GM		 189 "Option to specify scheme for request queue posting.\n"
190 " 0 -- Regular doorbell.\n"
191 " 1 -- CAMRAM doorbell (faster).\n");
a9083016 192
f4c496c1 193int ql2xtargetreset = 1;
f2019cb1 194module_param(ql2xtargetreset, int, S_IRUGO);
f4c496c1
GM		 195MODULE_PARM_DESC(ql2xtargetreset,
196 "Enable target reset."
197 "Default is 1 - use hw defaults.");
198
4da26e16 199int ql2xgffidenable;
f2019cb1 200module_param(ql2xgffidenable, int, S_IRUGO);
4da26e16
CD		 201MODULE_PARM_DESC(ql2xgffidenable,
202 "Enables GFF_ID checks of port type. "
203 "Default is 0 - Do not use GFF_ID information.");
a9083016 204
043dc1d7 205int ql2xasynctmfenable = 1;
f2019cb1 206module_param(ql2xasynctmfenable, int, S_IRUGO);
3822263e
MI		 207MODULE_PARM_DESC(ql2xasynctmfenable,
208 "Enables issue of TM IOCBs asynchronously via IOCB mechanism"
84e13c45 209 "Default is 1 - Issue TM IOCBs via mailbox mechanism.");
ed0de87c
GM		 210
211int ql2xdontresethba;
86e45bf6 212module_param(ql2xdontresethba, int, S_IRUGO|S_IWUSR);
ed0de87c 213MODULE_PARM_DESC(ql2xdontresethba,
08de2844
GM		 214 "Option to specify reset behaviour.\n"
215 " 0 (Default) -- Reset on failure.\n"
216 " 1 -- Do not reset on failure.\n");
ed0de87c 217
1abf635d
HR		 218uint64_t ql2xmaxlun = MAX_LUNS;
219module_param(ql2xmaxlun, ullong, S_IRUGO);
82515920
AV		 220MODULE_PARM_DESC(ql2xmaxlun,
221 "Defines the maximum LU number to register with the SCSI "
222 "midlayer. Default is 65535.");
223
08de2844
GM		 224int ql2xmdcapmask = 0x1F;
225module_param(ql2xmdcapmask, int, S_IRUGO);
226MODULE_PARM_DESC(ql2xmdcapmask,
227 "Set the Minidump driver capture mask level. "
6e96fa7b 228 "Default is 0x1F - Can be set to 0x3, 0x7, 0xF, 0x1F, 0x7F.");
08de2844 229
3aadff35 230int ql2xmdenable = 1;
08de2844
GM		 231module_param(ql2xmdenable, int, S_IRUGO);
232MODULE_PARM_DESC(ql2xmdenable,
233 "Enable/disable MiniDump. "
3aadff35
GM		 234 "0 - MiniDump disabled. "
235 "1 (Default) - MiniDump enabled.");
08de2844 236
b0d6cabd
HM		 237int ql2xexlogins = 0;
238module_param(ql2xexlogins, uint, S_IRUGO|S_IWUSR);
239MODULE_PARM_DESC(ql2xexlogins,
240 "Number of extended Logins. "
241 "0 (Default)- Disabled.");
242
99e1b683
QT		 243int ql2xexchoffld = 1024;
244module_param(ql2xexchoffld, uint, 0644);
2f56a7f1 245MODULE_PARM_DESC(ql2xexchoffld,
99e1b683
QT		 246 "Number of target exchanges.");
247
248int ql2xiniexchg = 1024;
249module_param(ql2xiniexchg, uint, 0644);
250MODULE_PARM_DESC(ql2xiniexchg,
251 "Number of initiator exchanges.");
2f56a7f1 252
f198cafa
HM		 253int ql2xfwholdabts = 0;
254module_param(ql2xfwholdabts, int, S_IRUGO);
255MODULE_PARM_DESC(ql2xfwholdabts,
256 "Allow FW to hold status IOCB until ABTS rsp received. "
257 "0 (Default) Do not set fw option. "
258 "1 - Set fw option to hold ABTS.");
259
41dc529a
QT		 260int ql2xmvasynctoatio = 1;
261module_param(ql2xmvasynctoatio, int, S_IRUGO|S_IWUSR);
262MODULE_PARM_DESC(ql2xmvasynctoatio,
263 "Move PUREX, ABTS RX and RIDA IOCBs to ATIOQ"
264 "0 (Default). Do not move IOCBs"
265 "1 - Move IOCBs.");
266
e4e3a2ce
QT		 267int ql2xautodetectsfp = 1;
268module_param(ql2xautodetectsfp, int, 0444);
269MODULE_PARM_DESC(ql2xautodetectsfp,
270 "Detect SFP range and set appropriate distance.\n"
271 "1 (Default): Enable\n");
272
e7240af5
HM		 273int ql2xenablemsix = 1;
274module_param(ql2xenablemsix, int, 0444);
275MODULE_PARM_DESC(ql2xenablemsix,
276 "Set to enable MSI or MSI-X interrupt mechanism.\n"
277 " Default is 1, enable MSI-X interrupt mechanism.\n"
278 " 0 -- enable traditional pin-based mechanism.\n"
279 " 1 -- enable MSI-X interrupt mechanism.\n"
280 " 2 -- enable MSI interrupt mechanism.\n");
281
9ecf0b0d
QT		 282int qla2xuseresexchforels;
283module_param(qla2xuseresexchforels, int, 0444);
284MODULE_PARM_DESC(qla2xuseresexchforels,
285 "Reserve 1/2 of emergency exchanges for ELS.\n"
286 " 0 (default): disabled");
287
b3ede8ea 288static int ql2xprotmask;
7855d2ba
MP		 289module_param(ql2xprotmask, int, 0644);
290MODULE_PARM_DESC(ql2xprotmask,
291 "Override DIF/DIX protection capabilities mask\n"
292 "Default is 0 which sets protection mask based on "
293 "capabilities reported by HBA firmware.\n");
294
b3ede8ea 295static int ql2xprotguard;
7855d2ba
MP		 296module_param(ql2xprotguard, int, 0644);
297MODULE_PARM_DESC(ql2xprotguard, "Override choice of DIX checksum\n"
298 " 0 -- Let HBA firmware decide\n"
299 " 1 -- Force T10 CRC\n"
300 " 2 -- Force IP checksum\n");
301
50b81275
GM		 302int ql2xdifbundlinginternalbuffers;
303module_param(ql2xdifbundlinginternalbuffers, int, 0644);
304MODULE_PARM_DESC(ql2xdifbundlinginternalbuffers,
305 "Force using internal buffers for DIF information\n"
306 "0 (Default). Based on check.\n"
307 "1 Force using internal buffers\n");
308
1a2fbf18 309static void qla2x00_clear_drv_active(struct qla_hw_data *);
3491255e 310static void qla2x00_free_device(scsi_qla_host_t *);
5601236b 311static int qla2xxx_map_queues(struct Scsi_Host *shost);
e84067d7 312static void qla2x00_destroy_deferred_work(struct qla_hw_data *);
ce7e4af7 313
45235022 314
1da177e4 315static struct scsi_transport_template *qla2xxx_transport_template = NULL;
2c3dfe3f 316struct scsi_transport_template *qla2xxx_transport_vport_template = NULL;
1da177e4 317
1da177e4
LT		 318/* TODO Convert to inlines
319 *
320 * Timer routines
321 */
1da177e4 322
2c3dfe3f 323__inline__ void
8e5f4ba0 324qla2x00_start_timer(scsi_qla_host_t *vha, unsigned long interval)
1da177e4 325{
8e5f4ba0 326 timer_setup(&vha->timer, qla2x00_timer, 0);
e315cd28 327 vha->timer.expires = jiffies + interval * HZ;
e315cd28
AC		 328 add_timer(&vha->timer);
329 vha->timer_active = 1;
1da177e4
LT		 330}
331
332static inline void
e315cd28 333qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval)
1da177e4 334{
a9083016 335 /* Currently used for 82XX only. */
7c3df132
SK		 336 if (vha->device_flags & DFLG_DEV_FAILED) {
337 ql_dbg(ql_dbg_timer, vha, 0x600d,
338 "Device in a failed state, returning.\n");
a9083016 339 return;
7c3df132 340 }
a9083016 341
e315cd28 342 mod_timer(&vha->timer, jiffies + interval * HZ);
1da177e4
LT		 343}
344
a824ebb3 345static __inline__ void
e315cd28 346qla2x00_stop_timer(scsi_qla_host_t *vha)
1da177e4 347{
e315cd28
AC		 348 del_timer_sync(&vha->timer);
349 vha->timer_active = 0;
1da177e4
LT		 350}
351
1da177e4
LT		 352static int qla2x00_do_dpc(void *data);
353
354static void qla2x00_rst_aen(scsi_qla_host_t *);
355
73208dfd
AC		 356static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t,
357 struct req_que **, struct rsp_que **);
e30d1756 358static void qla2x00_free_fw_dump(struct qla_hw_data *);
e315cd28 359static void qla2x00_mem_free(struct qla_hw_data *);
d7459527
MH		 360int qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd,
361 struct qla_qpair *qpair);
1da177e4 362
1da177e4 363/* -------------------------------------------------------------------------- */
8abfa9e2
QT		 364static void qla_init_base_qpair(struct scsi_qla_host *vha, struct req_que *req,
365 struct rsp_que *rsp)
366{
367 struct qla_hw_data *ha = vha->hw;
bd432bb5 368
8abfa9e2
QT		 369 rsp->qpair = ha->base_qpair;
370 rsp->req = req;
0691094f 371 ha->base_qpair->hw = ha;
8abfa9e2
QT		 372 ha->base_qpair->req = req;
373 ha->base_qpair->rsp = rsp;
374 ha->base_qpair->vha = vha;
375 ha->base_qpair->qp_lock_ptr = &ha->hardware_lock;
376 ha->base_qpair->use_shadow_reg = IS_SHADOW_REG_CAPABLE(ha) ? 1 : 0;
377 ha->base_qpair->msix = &ha->msix_entries[QLA_MSIX_RSP_Q];
6a629468 378 ha->base_qpair->srb_mempool = ha->srb_mempool;
8abfa9e2
QT		 379 INIT_LIST_HEAD(&ha->base_qpair->hints_list);
380 ha->base_qpair->enable_class_2 = ql2xenableclass2;
381 /* init qpair to this cpu. Will adjust at run time. */
86531887 382 qla_cpu_update(rsp->qpair, raw_smp_processor_id());
8abfa9e2
QT		 383 ha->base_qpair->pdev = ha->pdev;
384
ecc89f25 385 if (IS_QLA27XX(ha) || IS_QLA83XX(ha) || IS_QLA28XX(ha))
8abfa9e2
QT		 386 ha->base_qpair->reqq_start_iocbs = qla_83xx_start_iocbs;
387}
388
9a347ff4
CD		 389static int qla2x00_alloc_queues(struct qla_hw_data *ha, struct req_que *req,
390 struct rsp_que *rsp)
73208dfd 391{
7c3df132 392 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
bd432bb5 393
6396bb22 394 ha->req_q_map = kcalloc(ha->max_req_queues, sizeof(struct req_que *),
73208dfd
AC		 395 GFP_KERNEL);
396 if (!ha->req_q_map) {
7c3df132
SK		 397 ql_log(ql_log_fatal, vha, 0x003b,
398 "Unable to allocate memory for request queue ptrs.\n");
73208dfd
AC		 399 goto fail_req_map;
400 }
401
6396bb22 402 ha->rsp_q_map = kcalloc(ha->max_rsp_queues, sizeof(struct rsp_que *),
73208dfd
AC		 403 GFP_KERNEL);
404 if (!ha->rsp_q_map) {
7c3df132
SK		 405 ql_log(ql_log_fatal, vha, 0x003c,
406 "Unable to allocate memory for response queue ptrs.\n");
73208dfd
AC		 407 goto fail_rsp_map;
408 }
d7459527 409
e326d22a
QT		 410 ha->base_qpair = kzalloc(sizeof(struct qla_qpair), GFP_KERNEL);
411 if (ha->base_qpair == NULL) {
412 ql_log(ql_log_warn, vha, 0x00e0,
413 "Failed to allocate base queue pair memory.\n");
414 goto fail_base_qpair;
415 }
416
8abfa9e2 417 qla_init_base_qpair(vha, req, rsp);
e326d22a 418
c38d1baf 419 if ((ql2xmqsupport || ql2xnvmeenable) && ha->max_qpairs) {
d7459527
MH		 420 ha->queue_pair_map = kcalloc(ha->max_qpairs, sizeof(struct qla_qpair *),
421 GFP_KERNEL);
422 if (!ha->queue_pair_map) {
423 ql_log(ql_log_fatal, vha, 0x0180,
424 "Unable to allocate memory for queue pair ptrs.\n");
425 goto fail_qpair_map;
426 }
d7459527
MH		 427 }
428
9a347ff4
CD		 429 /*
430 * Make sure we record at least the request and response queue zero in
431 * case we need to free them if part of the probe fails.
432 */
433 ha->rsp_q_map[0] = rsp;
434 ha->req_q_map[0] = req;
73208dfd
AC		 435 set_bit(0, ha->rsp_qid_map);
436 set_bit(0, ha->req_qid_map);
6a2cf8d3 437 return 0;
73208dfd 438
d7459527 439fail_qpair_map:
82de802a
QT		 440 kfree(ha->base_qpair);
441 ha->base_qpair = NULL;
442fail_base_qpair:
d7459527
MH		 443 kfree(ha->rsp_q_map);
444 ha->rsp_q_map = NULL;
73208dfd
AC		 445fail_rsp_map:
446 kfree(ha->req_q_map);
447 ha->req_q_map = NULL;
448fail_req_map:
449 return -ENOMEM;
450}
451
2afa19a9 452static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req)
73208dfd 453{
8ae6d9c7
GM		 454 if (IS_QLAFX00(ha)) {
455 if (req && req->ring_fx00)
456 dma_free_coherent(&ha->pdev->dev,
457 (req->length_fx00 + 1) * sizeof(request_t),
458 req->ring_fx00, req->dma_fx00);
459 } else if (req && req->ring)
73208dfd
AC		 460 dma_free_coherent(&ha->pdev->dev,
461 (req->length + 1) * sizeof(request_t),
462 req->ring, req->dma);
463
6d634067 464 if (req)
8d93f550 465 kfree(req->outstanding_cmds);
6d634067
BK		 466
467 kfree(req);
73208dfd
AC		 468}
469
2afa19a9
AC		 470static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp)
471{
8ae6d9c7 472 if (IS_QLAFX00(ha)) {
3f6c9be2 473 if (rsp && rsp->ring_fx00)
8ae6d9c7
GM		 474 dma_free_coherent(&ha->pdev->dev,
475 (rsp->length_fx00 + 1) * sizeof(request_t),
476 rsp->ring_fx00, rsp->dma_fx00);
477 } else if (rsp && rsp->ring) {
2afa19a9
AC		 478 dma_free_coherent(&ha->pdev->dev,
479 (rsp->length + 1) * sizeof(response_t),
480 rsp->ring, rsp->dma);
8ae6d9c7 481 }
6d634067 482 kfree(rsp);
2afa19a9
AC		 483}
484
73208dfd
AC		 485static void qla2x00_free_queues(struct qla_hw_data *ha)
486{
487 struct req_que *req;
488 struct rsp_que *rsp;
489 int cnt;
093df737 490 unsigned long flags;
73208dfd 491
82de802a
QT		 492 if (ha->queue_pair_map) {
493 kfree(ha->queue_pair_map);
494 ha->queue_pair_map = NULL;
495 }
496 if (ha->base_qpair) {
497 kfree(ha->base_qpair);
498 ha->base_qpair = NULL;
499 }
500
093df737 501 spin_lock_irqsave(&ha->hardware_lock, flags);
2afa19a9 502 for (cnt = 0; cnt < ha->max_req_queues; cnt++) {
cb43285f
QT		 503 if (!test_bit(cnt, ha->req_qid_map))
504 continue;
505
73208dfd 506 req = ha->req_q_map[cnt];
093df737
QT		 507 clear_bit(cnt, ha->req_qid_map);
508 ha->req_q_map[cnt] = NULL;
509
510 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2afa19a9 511 qla2x00_free_req_que(ha, req);
093df737 512 spin_lock_irqsave(&ha->hardware_lock, flags);
73208dfd 513 }
093df737
QT		 514 spin_unlock_irqrestore(&ha->hardware_lock, flags);
515
73208dfd
AC		 516 kfree(ha->req_q_map);
517 ha->req_q_map = NULL;
2afa19a9 518
093df737
QT		 519
520 spin_lock_irqsave(&ha->hardware_lock, flags);
2afa19a9 521 for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) {
cb43285f
QT		 522 if (!test_bit(cnt, ha->rsp_qid_map))
523 continue;
524
2afa19a9 525 rsp = ha->rsp_q_map[cnt];
c3c42394 526 clear_bit(cnt, ha->rsp_qid_map);
093df737
QT		 527 ha->rsp_q_map[cnt] = NULL;
528 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2afa19a9 529 qla2x00_free_rsp_que(ha, rsp);
093df737 530 spin_lock_irqsave(&ha->hardware_lock, flags);
2afa19a9 531 }
093df737
QT		 532 spin_unlock_irqrestore(&ha->hardware_lock, flags);
533
2afa19a9
AC		 534 kfree(ha->rsp_q_map);
535 ha->rsp_q_map = NULL;
73208dfd
AC		 536}
537
1da177e4 538static char *
e315cd28 539qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str)
1da177e4 540{
e315cd28 541 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 542 static char *pci_bus_modes[] = {
543 "33", "66", "100", "133",
544 };
545 uint16_t pci_bus;
546
547 strcpy(str, "PCI");
548 pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9;
549 if (pci_bus) {
550 strcat(str, "-X (");
551 strcat(str, pci_bus_modes[pci_bus]);
552 } else {
553 pci_bus = (ha->pci_attr & BIT_8) >> 8;
554 strcat(str, " (");
555 strcat(str, pci_bus_modes[pci_bus]);
556 }
557 strcat(str, " MHz)");
558
559 return (str);
560}
561
fca29703 562static char *
e315cd28 563qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str)
fca29703
AV		 564{
565 static char *pci_bus_modes[] = { "33", "66", "100", "133", };
e315cd28 566 struct qla_hw_data *ha = vha->hw;
fca29703 567 uint32_t pci_bus;
fca29703 568
62a276f8 569 if (pci_is_pcie(ha->pdev)) {
fca29703 570 char lwstr[6];
62a276f8 571 uint32_t lstat, lspeed, lwidth;
fca29703 572
62a276f8
BH		 573 pcie_capability_read_dword(ha->pdev, PCI_EXP_LNKCAP, &lstat);
574 lspeed = lstat & PCI_EXP_LNKCAP_SLS;
575 lwidth = (lstat & PCI_EXP_LNKCAP_MLW) >> 4;
fca29703
AV		 576
577 strcpy(str, "PCIe (");
49300af7
SK		 578 switch (lspeed) {
579 case 1:
c87a0d8c 580 strcat(str, "2.5GT/s ");
49300af7
SK		 581 break;
582 case 2:
c87a0d8c 583 strcat(str, "5.0GT/s ");
49300af7
SK		 584 break;
585 case 3:
586 strcat(str, "8.0GT/s ");
587 break;
588 default:
fca29703 589 strcat(str, "<unknown> ");
49300af7
SK		 590 break;
591 }
fca29703
AV		 592 snprintf(lwstr, sizeof(lwstr), "x%d)", lwidth);
593 strcat(str, lwstr);
594
595 return str;
596 }
597
598 strcpy(str, "PCI");
599 pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8;
600 if (pci_bus == 0 || pci_bus == 8) {
601 strcat(str, " (");
602 strcat(str, pci_bus_modes[pci_bus >> 3]);
603 } else {
604 strcat(str, "-X ");
605 if (pci_bus & BIT_2)
606 strcat(str, "Mode 2");
607 else
608 strcat(str, "Mode 1");
609 strcat(str, " (");
610 strcat(str, pci_bus_modes[pci_bus & ~BIT_2]);
611 }
612 strcat(str, " MHz)");
613
614 return str;
615}
616
e5f82ab8 617static char *
df57caba 618qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
1da177e4
LT		 619{
620 char un_str[10];
e315cd28 621 struct qla_hw_data *ha = vha->hw;
fa2a1ce5 622
df57caba
HM		 623 snprintf(str, size, "%d.%02d.%02d ", ha->fw_major_version,
624 ha->fw_minor_version, ha->fw_subminor_version);
1da177e4
LT		 625
626 if (ha->fw_attributes & BIT_9) {
627 strcat(str, "FLX");
628 return (str);
629 }
630
631 switch (ha->fw_attributes & 0xFF) {
632 case 0x7:
633 strcat(str, "EF");
634 break;
635 case 0x17:
636 strcat(str, "TP");
637 break;
638 case 0x37:
639 strcat(str, "IP");
640 break;
641 case 0x77:
642 strcat(str, "VI");
643 break;
644 default:
645 sprintf(un_str, "(%x)", ha->fw_attributes);
646 strcat(str, un_str);
647 break;
648 }
649 if (ha->fw_attributes & 0x100)
650 strcat(str, "X");
651
652 return (str);
653}
654
e5f82ab8 655static char *
df57caba 656qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
fca29703 657{
e315cd28 658 struct qla_hw_data *ha = vha->hw;
f0883ac6 659
df57caba 660 snprintf(str, size, "%d.%02d.%02d (%x)", ha->fw_major_version,
3a03eb79 661 ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes);
fca29703 662 return str;
fca29703
AV		 663}
664
9ba56b95 665void
25ff6af1 666qla2x00_sp_free_dma(void *ptr)
fca29703 667{
25ff6af1
JC		 668 srb_t *sp = ptr;
669 struct qla_hw_data *ha = sp->vha->hw;
9ba56b95 670 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
9ba56b95 671 void *ctx = GET_CMD_CTX_SP(sp);
fca29703 672
9ba56b95
GM		 673 if (sp->flags & SRB_DMA_VALID) {
674 scsi_dma_unmap(cmd);
675 sp->flags &= ~SRB_DMA_VALID;
7c3df132 676 }
fca29703 677
9ba56b95
GM		 678 if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
679 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
680 scsi_prot_sg_count(cmd), cmd->sc_data_direction);
681 sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
682 }
683
d5ff0eed 684 if (!ctx)
711a08d7 685 return;
d5ff0eed 686
9ba56b95
GM		 687 if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
688 /* List assured to be having elements */
d5ff0eed 689 qla2x00_clean_dsd_pool(ha, ctx);
9ba56b95
GM		 690 sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
691 }
692
693 if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
d5ff0eed
JC		 694 struct crc_context *ctx0 = ctx;
695
696 dma_pool_free(ha->dl_dma_pool, ctx0, ctx0->crc_ctx_dma);
9ba56b95
GM		 697 sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
698 }
699
700 if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
d5ff0eed 701 struct ct6_dsd *ctx1 = ctx;
fca29703 702
9ba56b95 703 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd,
d5ff0eed 704 ctx1->fcp_cmnd_dma);
9ba56b95
GM		 705 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list);
706 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt;
707 ha->gbl_dsd_avail += ctx1->dsd_use_cnt;
708 mempool_free(ctx1, ha->ctx_mempool);
9ba56b95 709 }
9ba56b95
GM		 710}
711
d7459527 712void
25ff6af1 713qla2x00_sp_compl(void *ptr, int res)
9ba56b95 714{
25ff6af1 715 srb_t *sp = ptr;
9ba56b95 716 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
711a08d7 717 wait_queue_head_t *cwaitq = sp->cwaitq;
9ba56b95 718
9ba56b95 719 if (atomic_read(&sp->ref_count) == 0) {
25ff6af1 720 ql_dbg(ql_dbg_io, sp->vha, 0x3015,
9ba56b95
GM		 721 "SP reference-count to ZERO -- sp=%p cmd=%p.\n",
722 sp, GET_CMD_SP(sp));
723 if (ql2xextended_error_logging & ql_dbg_io)
8fbdac8c 724 WARN_ON(atomic_read(&sp->ref_count) == 0);
9ba56b95
GM		 725 return;
726 }
727 if (!atomic_dec_and_test(&sp->ref_count))
728 return;
729
f3caa990 730 sp->free(sp);
740e2935 731 cmd->result = res;
711a08d7 732 CMD_SP(cmd) = NULL;
9ba56b95 733 cmd->scsi_done(cmd);
711a08d7
GM		 734 if (cwaitq)
735 wake_up(cwaitq);
736 qla2x00_rel_sp(sp);
fca29703
AV		 737}
738
d7459527 739void
25ff6af1 740qla2xxx_qpair_sp_free_dma(void *ptr)
d7459527
MH		 741{
742 srb_t *sp = (srb_t *)ptr;
743 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
744 struct qla_hw_data *ha = sp->fcport->vha->hw;
745 void *ctx = GET_CMD_CTX_SP(sp);
746
747 if (sp->flags & SRB_DMA_VALID) {
748 scsi_dma_unmap(cmd);
749 sp->flags &= ~SRB_DMA_VALID;
750 }
751
752 if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
753 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
754 scsi_prot_sg_count(cmd), cmd->sc_data_direction);
755 sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
756 }
757
d5ff0eed 758 if (!ctx)
711a08d7 759 return;
d5ff0eed 760
d7459527
MH		 761 if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
762 /* List assured to be having elements */
d5ff0eed 763 qla2x00_clean_dsd_pool(ha, ctx);
d7459527
MH		 764 sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
765 }
766
767 if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
d5ff0eed
JC		 768 struct crc_context *ctx0 = ctx;
769
770 dma_pool_free(ha->dl_dma_pool, ctx, ctx0->crc_ctx_dma);
d7459527
MH		 771 sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
772 }
773
774 if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
d5ff0eed 775 struct ct6_dsd *ctx1 = ctx;
d7459527
MH		 776 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd,
777 ctx1->fcp_cmnd_dma);
778 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list);
779 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt;
780 ha->gbl_dsd_avail += ctx1->dsd_use_cnt;
781 mempool_free(ctx1, ha->ctx_mempool);
50b81275
GM		 782 sp->flags &= ~SRB_FCP_CMND_DMA_VALID;
783 }
784 if (sp->flags & SRB_DIF_BUNDL_DMA_VALID) {
785 struct crc_context *difctx = sp->u.scmd.ctx;
786 struct dsd_dma *dif_dsd, *nxt_dsd;
787
788 list_for_each_entry_safe(dif_dsd, nxt_dsd,
789 &difctx->ldif_dma_hndl_list, list) {
790 list_del(&dif_dsd->list);
791 dma_pool_free(ha->dif_bundl_pool, dif_dsd->dsd_addr,
792 dif_dsd->dsd_list_dma);
793 kfree(dif_dsd);
794 difctx->no_dif_bundl--;
795 }
796
797 list_for_each_entry_safe(dif_dsd, nxt_dsd,
798 &difctx->ldif_dsd_list, list) {
799 list_del(&dif_dsd->list);
800 dma_pool_free(ha->dl_dma_pool, dif_dsd->dsd_addr,
801 dif_dsd->dsd_list_dma);
802 kfree(dif_dsd);
803 difctx->no_ldif_dsd--;
804 }
805
806 if (difctx->no_ldif_dsd) {
807 ql_dbg(ql_dbg_tgt+ql_dbg_verbose, sp->vha, 0xe022,
808 "%s: difctx->no_ldif_dsd=%x\n",
809 __func__, difctx->no_ldif_dsd);
810 }
811
812 if (difctx->no_dif_bundl) {
813 ql_dbg(ql_dbg_tgt+ql_dbg_verbose, sp->vha, 0xe022,
814 "%s: difctx->no_dif_bundl=%x\n",
815 __func__, difctx->no_dif_bundl);
816 }
817 sp->flags &= ~SRB_DIF_BUNDL_DMA_VALID;
d7459527 818 }
d7459527
MH		 819}
820
821void
25ff6af1 822qla2xxx_qpair_sp_compl(void *ptr, int res)
d7459527 823{
25ff6af1 824 srb_t *sp = ptr;
d7459527 825 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
711a08d7 826 wait_queue_head_t *cwaitq = sp->cwaitq;
d7459527
MH		 827
828 if (atomic_read(&sp->ref_count) == 0) {
829 ql_dbg(ql_dbg_io, sp->fcport->vha, 0x3079,
830 "SP reference-count to ZERO -- sp=%p cmd=%p.\n",
831 sp, GET_CMD_SP(sp));
832 if (ql2xextended_error_logging & ql_dbg_io)
833 WARN_ON(atomic_read(&sp->ref_count) == 0);
834 return;
835 }
836 if (!atomic_dec_and_test(&sp->ref_count))
837 return;
838
f3caa990 839 sp->free(sp);
711a08d7
GM		 840 cmd->result = res;
841 CMD_SP(cmd) = NULL;
d7459527 842 cmd->scsi_done(cmd);
711a08d7
GM		 843 if (cwaitq)
844 wake_up(cwaitq);
845 qla2xxx_rel_qpair_sp(sp->qpair, sp);
d7459527
MH		 846}
847
1da177e4 848static int
f5e3e40b 849qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
fca29703 850{
134ae078 851 scsi_qla_host_t *vha = shost_priv(host);
fca29703 852 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
19a7b4ae 853 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
e315cd28
AC		 854 struct qla_hw_data *ha = vha->hw;
855 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
fca29703
AV		 856 srb_t *sp;
857 int rval;
5601236b
MH		 858 struct qla_qpair *qpair = NULL;
859 uint32_t tag;
860 uint16_t hwq;
fca29703 861
04dfaa53
MFO		 862 if (unlikely(test_bit(UNLOADING, &base_vha->dpc_flags))) {
863 cmd->result = DID_NO_CONNECT << 16;
864 goto qc24_fail_command;
865 }
866
5601236b 867 if (ha->mqenable) {
f664a3cc
JA		 868 tag = blk_mq_unique_tag(cmd->request);
869 hwq = blk_mq_unique_tag_to_hwq(tag);
870 qpair = ha->queue_pair_map[hwq];
5601236b
MH		 871
872 if (qpair)
873 return qla2xxx_mqueuecommand(host, cmd, qpair);
d7459527
MH		 874 }
875
85880801 876 if (ha->flags.eeh_busy) {
7c3df132 877 if (ha->flags.pci_channel_io_perm_failure) {
5f28d2d7 878 ql_dbg(ql_dbg_aer, vha, 0x9010,
7c3df132
SK		 879 "PCI Channel IO permanent failure, exiting "
880 "cmd=%p.\n", cmd);
b9b12f73 881 cmd->result = DID_NO_CONNECT << 16;
7c3df132 882 } else {
5f28d2d7 883 ql_dbg(ql_dbg_aer, vha, 0x9011,
7c3df132 884 "EEH_Busy, Requeuing the cmd=%p.\n", cmd);
85880801 885 cmd->result = DID_REQUEUE << 16;
7c3df132 886 }
14e660e6
SJ		 887 goto qc24_fail_command;
888 }
889
19a7b4ae
JSEC		 890 rval = fc_remote_port_chkready(rport);
891 if (rval) {
892 cmd->result = rval;
5f28d2d7 893 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3003,
7c3df132
SK		 894 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
895 cmd, rval);
fca29703
AV		 896 goto qc24_fail_command;
897 }
898
bad75002
AE		 899 if (!vha->flags.difdix_supported &&
900 scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) {
7c3df132
SK		 901 ql_dbg(ql_dbg_io, vha, 0x3004,
902 "DIF Cap not reg, fail DIF capable cmd's:%p.\n",
903 cmd);
bad75002
AE		 904 cmd->result = DID_NO_CONNECT << 16;
905 goto qc24_fail_command;
906 }
aa651be8
CD		 907
908 if (!fcport) {
909 cmd->result = DID_NO_CONNECT << 16;
910 goto qc24_fail_command;
911 }
912
fca29703
AV		 913 if (atomic_read(&fcport->state) != FCS_ONLINE) {
914 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
38170fa8 915 atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
7c3df132
SK		 916 ql_dbg(ql_dbg_io, vha, 0x3005,
917 "Returning DNC, fcport_state=%d loop_state=%d.\n",
918 atomic_read(&fcport->state),
919 atomic_read(&base_vha->loop_state));
fca29703
AV		 920 cmd->result = DID_NO_CONNECT << 16;
921 goto qc24_fail_command;
922 }
7b594131 923 goto qc24_target_busy;
fca29703
AV		 924 }
925
e05fe292
CD		 926 /*
927 * Return target busy if we've received a non-zero retry_delay_timer
928 * in a FCP_RSP.
929 */
975f7d46
BP		 930 if (fcport->retry_delay_timestamp == 0) {
931 /* retry delay not set */
932 } else if (time_after(jiffies, fcport->retry_delay_timestamp))
e05fe292
CD		 933 fcport->retry_delay_timestamp = 0;
934 else
935 goto qc24_target_busy;
936
b00ee7d7 937 sp = qla2x00_get_sp(vha, fcport, GFP_ATOMIC);
50280c01 938 if (!sp)
f5e3e40b 939 goto qc24_host_busy;
fca29703 940
9ba56b95
GM		 941 sp->u.scmd.cmd = cmd;
942 sp->type = SRB_SCSI_CMD;
943 atomic_set(&sp->ref_count, 1);
944 CMD_SP(cmd) = (void *)sp;
945 sp->free = qla2x00_sp_free_dma;
946 sp->done = qla2x00_sp_compl;
947
e315cd28 948 rval = ha->isp_ops->start_scsi(sp);
7c3df132 949 if (rval != QLA_SUCCESS) {
53016ed3 950 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3013,
7c3df132 951 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
fca29703 952 goto qc24_host_busy_free_sp;
7c3df132 953 }
fca29703 954
fca29703
AV		 955 return 0;
956
957qc24_host_busy_free_sp:
f3caa990 958 sp->free(sp);
fca29703 959
f5e3e40b 960qc24_host_busy:
fca29703
AV		 961 return SCSI_MLQUEUE_HOST_BUSY;
962
7b594131
MC		 963qc24_target_busy:
964 return SCSI_MLQUEUE_TARGET_BUSY;
965
fca29703 966qc24_fail_command:
f5e3e40b 967 cmd->scsi_done(cmd);
fca29703
AV		 968
969 return 0;
970}
971
d7459527
MH		 972/* For MQ supported I/O */
973int
974qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd,
975 struct qla_qpair *qpair)
976{
977 scsi_qla_host_t *vha = shost_priv(host);
978 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
979 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
980 struct qla_hw_data *ha = vha->hw;
981 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
982 srb_t *sp;
983 int rval;
984
985 rval = fc_remote_port_chkready(rport);
986 if (rval) {
987 cmd->result = rval;
988 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3076,
989 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
990 cmd, rval);
991 goto qc24_fail_command;
992 }
993
994 if (!fcport) {
995 cmd->result = DID_NO_CONNECT << 16;
996 goto qc24_fail_command;
997 }
998
999 if (atomic_read(&fcport->state) != FCS_ONLINE) {
1000 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
1001 atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
1002 ql_dbg(ql_dbg_io, vha, 0x3077,
1003 "Returning DNC, fcport_state=%d loop_state=%d.\n",
1004 atomic_read(&fcport->state),
1005 atomic_read(&base_vha->loop_state));
1006 cmd->result = DID_NO_CONNECT << 16;
1007 goto qc24_fail_command;
1008 }
1009 goto qc24_target_busy;
1010 }
1011
1012 /*
1013 * Return target busy if we've received a non-zero retry_delay_timer
1014 * in a FCP_RSP.
1015 */
1016 if (fcport->retry_delay_timestamp == 0) {
1017 /* retry delay not set */
1018 } else if (time_after(jiffies, fcport->retry_delay_timestamp))
1019 fcport->retry_delay_timestamp = 0;
1020 else
1021 goto qc24_target_busy;
1022
6a629468 1023 sp = qla2xxx_get_qpair_sp(vha, qpair, fcport, GFP_ATOMIC);
d7459527
MH		 1024 if (!sp)
1025 goto qc24_host_busy;
1026
1027 sp->u.scmd.cmd = cmd;
1028 sp->type = SRB_SCSI_CMD;
1029 atomic_set(&sp->ref_count, 1);
1030 CMD_SP(cmd) = (void *)sp;
1031 sp->free = qla2xxx_qpair_sp_free_dma;
1032 sp->done = qla2xxx_qpair_sp_compl;
1033 sp->qpair = qpair;
1034
1035 rval = ha->isp_ops->start_scsi_mq(sp);
1036 if (rval != QLA_SUCCESS) {
1037 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3078,
1038 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
1039 if (rval == QLA_INTERFACE_ERROR)
1040 goto qc24_fail_command;
1041 goto qc24_host_busy_free_sp;
1042 }
1043
1044 return 0;
1045
1046qc24_host_busy_free_sp:
f3caa990 1047 sp->free(sp);
d7459527
MH		 1048
1049qc24_host_busy:
1050 return SCSI_MLQUEUE_HOST_BUSY;
1051
1052qc24_target_busy:
1053 return SCSI_MLQUEUE_TARGET_BUSY;
1054
1055qc24_fail_command:
1056 cmd->scsi_done(cmd);
1057
1058 return 0;
1059}
1060
1da177e4
LT		 1061/*
1062 * qla2x00_eh_wait_on_command
1063 * Waits for the command to be returned by the Firmware for some
1064 * max time.
1065 *
1066 * Input:
1da177e4 1067 * cmd = Scsi Command to wait on.
1da177e4
LT		 1068 *
1069 * Return:
1070 * Not Found : 0
1071 * Found : 1
1072 */
1073static int
e315cd28 1074qla2x00_eh_wait_on_command(struct scsi_cmnd *cmd)
1da177e4 1075{
fe74c71f 1076#define ABORT_POLLING_PERIOD 1000
478c3b03 1077#define ABORT_WAIT_ITER ((2 * 1000) / (ABORT_POLLING_PERIOD))
f4f051eb 1078 unsigned long wait_iter = ABORT_WAIT_ITER;
85880801
AV		 1079 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1080 struct qla_hw_data *ha = vha->hw;
f4f051eb 1081 int ret = QLA_SUCCESS;
1da177e4 1082
85880801 1083 if (unlikely(pci_channel_offline(ha->pdev)) || ha->flags.eeh_busy) {
7c3df132
SK		 1084 ql_dbg(ql_dbg_taskm, vha, 0x8005,
1085 "Return:eh_wait.\n");
85880801
AV		 1086 return ret;
1087 }
1088
d970432c 1089 while (CMD_SP(cmd) && wait_iter--) {
fe74c71f 1090 msleep(ABORT_POLLING_PERIOD);
f4f051eb 1091 }
1092 if (CMD_SP(cmd))
1093 ret = QLA_FUNCTION_FAILED;
1da177e4 1094
f4f051eb 1095 return ret;
1da177e4
LT		 1096}
1097
1098/*
1099 * qla2x00_wait_for_hba_online
fa2a1ce5 1100 * Wait till the HBA is online after going through
1da177e4
LT		 1101 * <= MAX_RETRIES_OF_ISP_ABORT or
1102 * finally HBA is disabled ie marked offline
1103 *
1104 * Input:
1105 * ha - pointer to host adapter structure
fa2a1ce5
AV		 1106 *
1107 * Note:
1da177e4
LT		 1108 * Does context switching-Release SPIN_LOCK
1109 * (if any) before calling this routine.
1110 *
1111 * Return:
1112 * Success (Adapter is online) : 0
1113 * Failed (Adapter is offline/disabled) : 1
1114 */
854165f4 1115int
e315cd28 1116qla2x00_wait_for_hba_online(scsi_qla_host_t *vha)
1da177e4 1117{
fca29703
AV		 1118 int return_status;
1119 unsigned long wait_online;
e315cd28
AC		 1120 struct qla_hw_data *ha = vha->hw;
1121 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4 1122
fa2a1ce5 1123 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ);
e315cd28
AC		 1124 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
1125 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
1126 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
1127 ha->dpc_active) && time_before(jiffies, wait_online)) {
1da177e4
LT		 1128
1129 msleep(1000);
1130 }
e315cd28 1131 if (base_vha->flags.online)
fa2a1ce5 1132 return_status = QLA_SUCCESS;
1da177e4
LT		 1133 else
1134 return_status = QLA_FUNCTION_FAILED;
1135
1da177e4
LT		 1136 return (return_status);
1137}
1138
726b8548
QT		 1139static inline int test_fcport_count(scsi_qla_host_t *vha)
1140{
1141 struct qla_hw_data *ha = vha->hw;
1142 unsigned long flags;
1143 int res;
1144
1145 spin_lock_irqsave(&ha->tgt.sess_lock, flags);
83548fe2
QT		 1146 ql_dbg(ql_dbg_init, vha, 0x00ec,
1147 "tgt %p, fcport_count=%d\n",
1148 vha, vha->fcport_count);
726b8548
QT		 1149 res = (vha->fcport_count == 0);
1150 spin_unlock_irqrestore(&ha->tgt.sess_lock, flags);
1151
1152 return res;
1153}
1154
1155/*
1156 * qla2x00_wait_for_sess_deletion can only be called from remove_one.
1157 * it has dependency on UNLOADING flag to stop device discovery
1158 */
efa93f48 1159void
726b8548
QT		 1160qla2x00_wait_for_sess_deletion(scsi_qla_host_t *vha)
1161{
1162 qla2x00_mark_all_devices_lost(vha, 0);
1163
b85e0957 1164 wait_event_timeout(vha->fcport_waitQ, test_fcport_count(vha), 10*HZ);
726b8548
QT		 1165}
1166
86fbee86 1167/*
638a1a01
SC		 1168 * qla2x00_wait_for_hba_ready
1169 * Wait till the HBA is ready before doing driver unload
86fbee86
LC		 1170 *
1171 * Input:
1172 * ha - pointer to host adapter structure
1173 *
1174 * Note:
1175 * Does context switching-Release SPIN_LOCK
1176 * (if any) before calling this routine.
1177 *
86fbee86 1178 */
638a1a01
SC		 1179static void
1180qla2x00_wait_for_hba_ready(scsi_qla_host_t *vha)
86fbee86 1181{
86fbee86 1182 struct qla_hw_data *ha = vha->hw;
783e0dc4 1183 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
86fbee86 1184
1d483901
DC		 1185 while ((qla2x00_reset_active(vha) || ha->dpc_active ||
1186 ha->flags.mbox_busy) ||
1187 test_bit(FX00_RESET_RECOVERY, &vha->dpc_flags) ||
1188 test_bit(FX00_TARGET_SCAN, &vha->dpc_flags)) {
1189 if (test_bit(UNLOADING, &base_vha->dpc_flags))
1190 break;
86fbee86 1191 msleep(1000);
783e0dc4 1192 }
86fbee86
LC		 1193}
1194
2533cf67
LC		 1195int
1196qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha)
1197{
1198 int return_status;
1199 unsigned long wait_reset;
1200 struct qla_hw_data *ha = vha->hw;
1201 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1202
1203 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ);
1204 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
1205 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
1206 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
1207 ha->dpc_active) && time_before(jiffies, wait_reset)) {
1208
1209 msleep(1000);
1210
1211 if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) &&
1212 ha->flags.chip_reset_done)
1213 break;
1214 }
1215 if (ha->flags.chip_reset_done)
1216 return_status = QLA_SUCCESS;
1217 else
1218 return_status = QLA_FUNCTION_FAILED;
1219
1220 return return_status;
1221}
1222
585def9b 1223static int
083a469d
GM		 1224sp_get(struct srb *sp)
1225{
585def9b
QT		 1226 if (!refcount_inc_not_zero((refcount_t*)&sp->ref_count))
1227 /* kref get fail */
1228 return ENXIO;
1229 else
1230 return 0;
083a469d
GM		 1231}
1232
a465537a
SC		 1233#define ISP_REG_DISCONNECT 0xffffffffU
1234/**************************************************************************
1235* qla2x00_isp_reg_stat
1236*
1237* Description:
1238* Read the host status register of ISP before aborting the command.
1239*
1240* Input:
1241* ha = pointer to host adapter structure.
1242*
1243*
1244* Returns:
1245* Either true or false.
1246*
1247* Note: Return true if there is register disconnect.
1248**************************************************************************/
1249static inline
1250uint32_t qla2x00_isp_reg_stat(struct qla_hw_data *ha)
1251{
1252 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
bf6061b1 1253 struct device_reg_82xx __iomem *reg82 = &ha->iobase->isp82;
a465537a 1254
bf6061b1
SC		 1255 if (IS_P3P_TYPE(ha))
1256 return ((RD_REG_DWORD(&reg82->host_int)) == ISP_REG_DISCONNECT);
1257 else
1258 return ((RD_REG_DWORD(&reg->host_status)) ==
1259 ISP_REG_DISCONNECT);
a465537a
SC		 1260}
1261
1da177e4
LT		 1262/**************************************************************************
1263* qla2xxx_eh_abort
1264*
1265* Description:
1266* The abort function will abort the specified command.
1267*
1268* Input:
1269* cmd = Linux SCSI command packet to be aborted.
1270*
1271* Returns:
1272* Either SUCCESS or FAILED.
1273*
1274* Note:
2ea00202 1275* Only return FAILED if command not returned by firmware.
1da177e4 1276**************************************************************************/
e5f82ab8 1277static int
1da177e4
LT		 1278qla2xxx_eh_abort(struct scsi_cmnd *cmd)
1279{
e315cd28 1280 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
f4f051eb 1281 srb_t *sp;
4e98d3b8 1282 int ret;
9cb78c16
HR		 1283 unsigned int id;
1284 uint64_t lun;
18e144d3 1285 unsigned long flags;
f934c9d0 1286 int rval, wait = 0;
e315cd28 1287 struct qla_hw_data *ha = vha->hw;
585def9b 1288 struct qla_qpair *qpair;
1da177e4 1289
a465537a
SC		 1290 if (qla2x00_isp_reg_stat(ha)) {
1291 ql_log(ql_log_info, vha, 0x8042,
1292 "PCI/Register disconnect, exiting.\n");
1293 return FAILED;
1294 }
1da177e4 1295
4e98d3b8
AV		 1296 ret = fc_block_scsi_eh(cmd);
1297 if (ret != 0)
1298 return ret;
1299 ret = SUCCESS;
1300
170babc3 1301 sp = (srb_t *) CMD_SP(cmd);
585def9b
QT		 1302 if (!sp)
1303 return SUCCESS;
1304
1305 qpair = sp->qpair;
1306 if (!qpair)
1307 return SUCCESS;
1308
1309 spin_lock_irqsave(qpair->qp_lock_ptr, flags);
1310 if (!CMD_SP(cmd)) {
1311 /* there's a chance an interrupt could clear
1312 the ptr as part of done & free */
1313 spin_unlock_irqrestore(qpair->qp_lock_ptr, flags);
170babc3
MC		 1314 return SUCCESS;
1315 }
1da177e4 1316
585def9b
QT		 1317 if (sp_get(sp)){
1318 /* ref_count is already 0 */
1319 spin_unlock_irqrestore(qpair->qp_lock_ptr, flags);
170babc3
MC		 1320 return SUCCESS;
1321 }
585def9b
QT		 1322 spin_unlock_irqrestore(qpair->qp_lock_ptr, flags);
1323
1324 id = cmd->device->id;
1325 lun = cmd->device->lun;
1da177e4 1326
7c3df132 1327 ql_dbg(ql_dbg_taskm, vha, 0x8002,
c7bc4cae
CD		 1328 "Aborting from RISC nexus=%ld:%d:%llu sp=%p cmd=%p handle=%x\n",
1329 vha->host_no, id, lun, sp, cmd, sp->handle);
17d98630 1330
170babc3 1331 /* Get a reference to the sp and drop the lock.*/
f934c9d0
CD		 1332 rval = ha->isp_ops->abort_command(sp);
1333 if (rval) {
96219424 1334 if (rval == QLA_FUNCTION_PARAMETER_ERROR)
f934c9d0 1335 ret = SUCCESS;
96219424 1336 else
f934c9d0
CD		 1337 ret = FAILED;
1338
7c3df132 1339 ql_dbg(ql_dbg_taskm, vha, 0x8003,
f934c9d0 1340 "Abort command mbx failed cmd=%p, rval=%x.\n", cmd, rval);
170babc3 1341 } else {
7c3df132 1342 ql_dbg(ql_dbg_taskm, vha, 0x8004,
cfb0919c 1343 "Abort command mbx success cmd=%p.\n", cmd);
170babc3
MC		 1344 wait = 1;
1345 }
75942064 1346
585def9b 1347 spin_lock_irqsave(qpair->qp_lock_ptr, flags);
585def9b
QT		 1348
1349 /*
711a08d7
GM		 1350 * Releasing of the SRB and associated command resources
1351 * is managed through ref_count.
1352 * Whether we need to wait for the abort completion or complete
1353 * the abort handler should be based on the ref_count.
585def9b 1354 */
711a08d7
GM		 1355 if (atomic_read(&sp->ref_count) > 1) {
1356 /*
1357 * The command is not yet completed. We need to wait for either
1358 * command completion or abort completion.
1359 */
1360 DECLARE_WAIT_QUEUE_HEAD_ONSTACK(eh_waitq);
1361 uint32_t ratov = ha->r_a_tov/10;
1362
1363 /* Go ahead and release the extra ref_count obtained earlier */
1364 sp->done(sp, DID_RESET << 16);
1365 sp->cwaitq = &eh_waitq;
1366
1367 if (!wait_event_lock_irq_timeout(eh_waitq,
1368 CMD_SP(cmd) == NULL, *qpair->qp_lock_ptr,
1369 msecs_to_jiffies(4 * ratov * 1000))) {
1370 /*
1371 * The abort got dropped, LOGO will be sent and the
1372 * original command will be completed with CS_TIMEOUT
1373 * completion
1374 */
1375 ql_dbg(ql_dbg_taskm, vha, 0xffff,
1376 "%s: Abort wait timer (4 * R_A_TOV[%d]) expired\n",
1377 __func__, ha->r_a_tov);
1378 sp->cwaitq = NULL;
2ea00202 1379 ret = FAILED;
711a08d7 1380 goto end;
f4f051eb 1381 }
711a08d7
GM		 1382 } else {
1383 /* Command completed while processing the abort */
1384 sp->done(sp, DID_RESET << 16);
1da177e4 1385 }
711a08d7
GM		 1386end:
1387 spin_unlock_irqrestore(qpair->qp_lock_ptr, flags);
7c3df132 1388 ql_log(ql_log_info, vha, 0x801c,
9cb78c16 1389 "Abort command issued nexus=%ld:%d:%llu -- %d %x.\n",
cfb0919c 1390 vha->host_no, id, lun, wait, ret);
1da177e4 1391
f4f051eb 1392 return ret;
1393}
1da177e4 1394
4d78c973 1395int
e315cd28 1396qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t,
9cb78c16 1397 uint64_t l, enum nexus_wait_type type)
f4f051eb 1398{
17d98630 1399 int cnt, match, status;
18e144d3 1400 unsigned long flags;
e315cd28 1401 struct qla_hw_data *ha = vha->hw;
73208dfd 1402 struct req_que *req;
4d78c973 1403 srb_t *sp;
9ba56b95 1404 struct scsi_cmnd *cmd;
1da177e4 1405
523ec773 1406 status = QLA_SUCCESS;
17d98630 1407
e315cd28 1408 spin_lock_irqsave(&ha->hardware_lock, flags);
67c2e93a 1409 req = vha->req;
17d98630 1410 for (cnt = 1; status == QLA_SUCCESS &&
8d93f550 1411 cnt < req->num_outstanding_cmds; cnt++) {
17d98630
AC		 1412 sp = req->outstanding_cmds[cnt];
1413 if (!sp)
523ec773 1414 continue;
9ba56b95 1415 if (sp->type != SRB_SCSI_CMD)
cf53b069 1416 continue;
25ff6af1 1417 if (vha->vp_idx != sp->vha->vp_idx)
17d98630
AC		 1418 continue;
1419 match = 0;
9ba56b95 1420 cmd = GET_CMD_SP(sp);
17d98630
AC		 1421 switch (type) {
1422 case WAIT_HOST:
1423 match = 1;
1424 break;
1425 case WAIT_TARGET:
9ba56b95 1426 match = cmd->device->id == t;
17d98630
AC		 1427 break;
1428 case WAIT_LUN:
9ba56b95
GM		 1429 match = (cmd->device->id == t &&
1430 cmd->device->lun == l);
17d98630 1431 break;
73208dfd 1432 }
17d98630
AC		 1433 if (!match)
1434 continue;
1435
1436 spin_unlock_irqrestore(&ha->hardware_lock, flags);
9ba56b95 1437 status = qla2x00_eh_wait_on_command(cmd);
17d98630 1438 spin_lock_irqsave(&ha->hardware_lock, flags);
1da177e4 1439 }
e315cd28 1440 spin_unlock_irqrestore(&ha->hardware_lock, flags);
523ec773
AV		 1441
1442 return status;
1da177e4
LT		 1443}
1444
523ec773
AV		 1445static char *reset_errors[] = {
1446 "HBA not online",
1447 "HBA not ready",
1448 "Task management failed",
1449 "Waiting for command completions",
1450};
1da177e4 1451
e5f82ab8 1452static int
523ec773 1453__qla2xxx_eh_generic_reset(char *name, enum nexus_wait_type type,
9cb78c16 1454 struct scsi_cmnd *cmd, int (*do_reset)(struct fc_port *, uint64_t, int))
1da177e4 1455{
e315cd28 1456 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
bdf79621 1457 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
523ec773 1458 int err;
1da177e4 1459
7c3df132 1460 if (!fcport) {
523ec773 1461 return FAILED;
7c3df132 1462 }
1da177e4 1463
4e98d3b8
AV		 1464 err = fc_block_scsi_eh(cmd);
1465 if (err != 0)
1466 return err;
1467
7c3df132 1468 ql_log(ql_log_info, vha, 0x8009,
9cb78c16 1469 "%s RESET ISSUED nexus=%ld:%d:%llu cmd=%p.\n", name, vha->host_no,
7c3df132 1470 cmd->device->id, cmd->device->lun, cmd);
1da177e4 1471
523ec773 1472 err = 0;
7c3df132
SK		 1473 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1474 ql_log(ql_log_warn, vha, 0x800a,
1475 "Wait for hba online failed for cmd=%p.\n", cmd);
523ec773 1476 goto eh_reset_failed;
7c3df132 1477 }
523ec773 1478 err = 2;
ac444b4f 1479 if (do_reset(fcport, cmd->device->lun, 1)
7c3df132
SK		 1480 != QLA_SUCCESS) {
1481 ql_log(ql_log_warn, vha, 0x800c,
1482 "do_reset failed for cmd=%p.\n", cmd);
523ec773 1483 goto eh_reset_failed;
7c3df132 1484 }
523ec773 1485 err = 3;
e315cd28 1486 if (qla2x00_eh_wait_for_pending_commands(vha, cmd->device->id,
7c3df132
SK		 1487 cmd->device->lun, type) != QLA_SUCCESS) {
1488 ql_log(ql_log_warn, vha, 0x800d,
d6a03581 1489 "wait for pending cmds failed for cmd=%p.\n", cmd);
523ec773 1490 goto eh_reset_failed;
7c3df132 1491 }
523ec773 1492
7c3df132 1493 ql_log(ql_log_info, vha, 0x800e,
9cb78c16 1494 "%s RESET SUCCEEDED nexus:%ld:%d:%llu cmd=%p.\n", name,
cfb0919c 1495 vha->host_no, cmd->device->id, cmd->device->lun, cmd);
523ec773
AV		 1496
1497 return SUCCESS;
1498
4d78c973 1499eh_reset_failed:
7c3df132 1500 ql_log(ql_log_info, vha, 0x800f,
9cb78c16 1501 "%s RESET FAILED: %s nexus=%ld:%d:%llu cmd=%p.\n", name,
cfb0919c
CD		 1502 reset_errors[err], vha->host_no, cmd->device->id, cmd->device->lun,
1503 cmd);
523ec773
AV		 1504 return FAILED;
1505}
1da177e4 1506
523ec773
AV		 1507static int
1508qla2xxx_eh_device_reset(struct scsi_cmnd *cmd)
1509{
e315cd28
AC		 1510 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1511 struct qla_hw_data *ha = vha->hw;
1da177e4 1512
a465537a
SC		 1513 if (qla2x00_isp_reg_stat(ha)) {
1514 ql_log(ql_log_info, vha, 0x803e,
1515 "PCI/Register disconnect, exiting.\n");
1516 return FAILED;
1517 }
1518
523ec773
AV		 1519 return __qla2xxx_eh_generic_reset("DEVICE", WAIT_LUN, cmd,
1520 ha->isp_ops->lun_reset);
1da177e4
LT		 1521}
1522
1da177e4 1523static int
523ec773 1524qla2xxx_eh_target_reset(struct scsi_cmnd *cmd)
1da177e4 1525{
e315cd28
AC		 1526 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1527 struct qla_hw_data *ha = vha->hw;
1da177e4 1528
a465537a
SC		 1529 if (qla2x00_isp_reg_stat(ha)) {
1530 ql_log(ql_log_info, vha, 0x803f,
1531 "PCI/Register disconnect, exiting.\n");
1532 return FAILED;
1533 }
1534
523ec773
AV		 1535 return __qla2xxx_eh_generic_reset("TARGET", WAIT_TARGET, cmd,
1536 ha->isp_ops->target_reset);
1da177e4
LT		 1537}
1538
1da177e4
LT		 1539/**************************************************************************
1540* qla2xxx_eh_bus_reset
1541*
1542* Description:
1543* The bus reset function will reset the bus and abort any executing
1544* commands.
1545*
1546* Input:
1547* cmd = Linux SCSI command packet of the command that cause the
1548* bus reset.
1549*
1550* Returns:
1551* SUCCESS/FAILURE (defined as macro in scsi.h).
1552*
1553**************************************************************************/
e5f82ab8 1554static int
1da177e4
LT		 1555qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd)
1556{
e315cd28 1557 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
bdf79621 1558 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
2c3dfe3f 1559 int ret = FAILED;
9cb78c16
HR		 1560 unsigned int id;
1561 uint64_t lun;
a465537a
SC		 1562 struct qla_hw_data *ha = vha->hw;
1563
1564 if (qla2x00_isp_reg_stat(ha)) {
1565 ql_log(ql_log_info, vha, 0x8040,
1566 "PCI/Register disconnect, exiting.\n");
1567 return FAILED;
1568 }
f4f051eb 1569
f4f051eb 1570 id = cmd->device->id;
1571 lun = cmd->device->lun;
1da177e4 1572
7c3df132 1573 if (!fcport) {
f4f051eb 1574 return ret;
7c3df132 1575 }
1da177e4 1576
4e98d3b8
AV		 1577 ret = fc_block_scsi_eh(cmd);
1578 if (ret != 0)
1579 return ret;
1580 ret = FAILED;
1581
7c3df132 1582 ql_log(ql_log_info, vha, 0x8012,
9cb78c16 1583 "BUS RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun);
1da177e4 1584
e315cd28 1585 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
7c3df132
SK		 1586 ql_log(ql_log_fatal, vha, 0x8013,
1587 "Wait for hba online failed board disabled.\n");
f4f051eb 1588 goto eh_bus_reset_done;
1da177e4
LT		 1589 }
1590
ad537689
SK		 1591 if (qla2x00_loop_reset(vha) == QLA_SUCCESS)
1592 ret = SUCCESS;
1593
f4f051eb 1594 if (ret == FAILED)
1595 goto eh_bus_reset_done;
1da177e4 1596
9a41a62b 1597 /* Flush outstanding commands. */
4d78c973 1598 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) !=
7c3df132
SK		 1599 QLA_SUCCESS) {
1600 ql_log(ql_log_warn, vha, 0x8014,
1601 "Wait for pending commands failed.\n");
9a41a62b 1602 ret = FAILED;
7c3df132 1603 }
1da177e4 1604
f4f051eb 1605eh_bus_reset_done:
7c3df132 1606 ql_log(ql_log_warn, vha, 0x802b,
9cb78c16 1607 "BUS RESET %s nexus=%ld:%d:%llu.\n",
d6a03581 1608 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1da177e4 1609
f4f051eb 1610 return ret;
1da177e4
LT		 1611}
1612
1613/**************************************************************************
1614* qla2xxx_eh_host_reset
1615*
1616* Description:
1617* The reset function will reset the Adapter.
1618*
1619* Input:
1620* cmd = Linux SCSI command packet of the command that cause the
1621* adapter reset.
1622*
1623* Returns:
1624* Either SUCCESS or FAILED.
1625*
1626* Note:
1627**************************************************************************/
e5f82ab8 1628static int
1da177e4
LT		 1629qla2xxx_eh_host_reset(struct scsi_cmnd *cmd)
1630{
e315cd28 1631 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
e315cd28 1632 struct qla_hw_data *ha = vha->hw;
2c3dfe3f 1633 int ret = FAILED;
9cb78c16
HR		 1634 unsigned int id;
1635 uint64_t lun;
e315cd28 1636 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4 1637
a465537a
SC		 1638 if (qla2x00_isp_reg_stat(ha)) {
1639 ql_log(ql_log_info, vha, 0x8041,
1640 "PCI/Register disconnect, exiting.\n");
1641 schedule_work(&ha->board_disable);
1642 return SUCCESS;
1643 }
1644
f4f051eb 1645 id = cmd->device->id;
1646 lun = cmd->device->lun;
f4f051eb 1647
7c3df132 1648 ql_log(ql_log_info, vha, 0x8018,
9cb78c16 1649 "ADAPTER RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun);
1da177e4 1650
63ee7072
CD		 1651 /*
1652 * No point in issuing another reset if one is active. Also do not
1653 * attempt a reset if we are updating flash.
1654 */
1655 if (qla2x00_reset_active(vha) || ha->optrom_state != QLA_SWAITING)
f4f051eb 1656 goto eh_host_reset_lock;
1da177e4 1657
e315cd28
AC		 1658 if (vha != base_vha) {
1659 if (qla2x00_vp_abort_isp(vha))
f4f051eb 1660 goto eh_host_reset_lock;
e315cd28 1661 } else {
7ec0effd 1662 if (IS_P3P_TYPE(vha->hw)) {
a9083016
GM		 1663 if (!qla82xx_fcoe_ctx_reset(vha)) {
1664 /* Ctx reset success */
1665 ret = SUCCESS;
1666 goto eh_host_reset_lock;
1667 }
1668 /* fall thru if ctx reset failed */
1669 }
68ca949c
AC		 1670 if (ha->wq)
1671 flush_workqueue(ha->wq);
1672
e315cd28 1673 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
a9083016 1674 if (ha->isp_ops->abort_isp(base_vha)) {
e315cd28
AC		 1675 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1676 /* failed. schedule dpc to try */
1677 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
1678
7c3df132
SK		 1679 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1680 ql_log(ql_log_warn, vha, 0x802a,
1681 "wait for hba online failed.\n");
e315cd28 1682 goto eh_host_reset_lock;
7c3df132 1683 }
e315cd28
AC		 1684 }
1685 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
fa2a1ce5 1686 }
1da177e4 1687
e315cd28 1688 /* Waiting for command to be returned to OS.*/
4d78c973 1689 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) ==
e315cd28 1690 QLA_SUCCESS)
f4f051eb 1691 ret = SUCCESS;
1da177e4 1692
f4f051eb 1693eh_host_reset_lock:
cfb0919c 1694 ql_log(ql_log_info, vha, 0x8017,
9cb78c16 1695 "ADAPTER RESET %s nexus=%ld:%d:%llu.\n",
cfb0919c 1696 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1da177e4 1697
f4f051eb 1698 return ret;
1699}
1da177e4
LT		 1700
1701/*
1702* qla2x00_loop_reset
1703* Issue loop reset.
1704*
1705* Input:
1706* ha = adapter block pointer.
1707*
1708* Returns:
1709* 0 = success
1710*/
a4722cf2 1711int
e315cd28 1712qla2x00_loop_reset(scsi_qla_host_t *vha)
1da177e4 1713{
0c8c39af 1714 int ret;
bdf79621 1715 struct fc_port *fcport;
e315cd28 1716 struct qla_hw_data *ha = vha->hw;
1da177e4 1717
5854771e
AB		 1718 if (IS_QLAFX00(ha)) {
1719 return qlafx00_loop_reset(vha);
1720 }
1721
f4c496c1 1722 if (ql2xtargetreset == 1 && ha->flags.enable_target_reset) {
55e5ed27
AV		 1723 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1724 if (fcport->port_type != FCT_TARGET)
1725 continue;
1726
1727 ret = ha->isp_ops->target_reset(fcport, 0, 0);
1728 if (ret != QLA_SUCCESS) {
7c3df132 1729 ql_dbg(ql_dbg_taskm, vha, 0x802c,
5854771e 1730 "Bus Reset failed: Reset=%d "
7c3df132 1731 "d_id=%x.\n", ret, fcport->d_id.b24);
55e5ed27
AV		 1732 }
1733 }
1734 }
1735
8ae6d9c7 1736
6246b8a1 1737 if (ha->flags.enable_lip_full_login && !IS_CNA_CAPABLE(ha)) {
0b7e7c53
AV		 1738 atomic_set(&vha->loop_state, LOOP_DOWN);
1739 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
1740 qla2x00_mark_all_devices_lost(vha, 0);
e315cd28 1741 ret = qla2x00_full_login_lip(vha);
0c8c39af 1742 if (ret != QLA_SUCCESS) {
7c3df132
SK		 1743 ql_dbg(ql_dbg_taskm, vha, 0x802d,
1744 "full_login_lip=%d.\n", ret);
749af3d5 1745 }
0c8c39af
AV		 1746 }
1747
0d6e61bc 1748 if (ha->flags.enable_lip_reset) {
e315cd28 1749 ret = qla2x00_lip_reset(vha);
ad537689 1750 if (ret != QLA_SUCCESS)
7c3df132
SK		 1751 ql_dbg(ql_dbg_taskm, vha, 0x802e,
1752 "lip_reset failed (%d).\n", ret);
1da177e4
LT		 1753 }
1754
1da177e4 1755 /* Issue marker command only when we are going to start the I/O */
e315cd28 1756 vha->marker_needed = 1;
1da177e4 1757
0c8c39af 1758 return QLA_SUCCESS;
1da177e4
LT		 1759}
1760
c4e521b6
BVA		 1761static void qla2x00_abort_srb(struct qla_qpair *qp, srb_t *sp, const int res,
1762 unsigned long *flags)
1763 __releases(qp->qp_lock_ptr)
1764 __acquires(qp->qp_lock_ptr)
1765{
1766 scsi_qla_host_t *vha = qp->vha;
1767 struct qla_hw_data *ha = vha->hw;
1768
1769 if (sp->type == SRB_NVME_CMD || sp->type == SRB_NVME_LS) {
1770 if (!sp_get(sp)) {
1771 /* got sp */
1772 spin_unlock_irqrestore(qp->qp_lock_ptr, *flags);
1773 qla_nvme_abort(ha, sp, res);
1774 spin_lock_irqsave(qp->qp_lock_ptr, *flags);
1775 }
1776 } else if (GET_CMD_SP(sp) && !ha->flags.eeh_busy &&
1777 !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) &&
1778 !qla2x00_isp_reg_stat(ha) && sp->type == SRB_SCSI_CMD) {
1779 /*
1780 * Don't abort commands in adapter during EEH recovery as it's
1781 * not accessible/responding.
1782 *
1783 * Get a reference to the sp and drop the lock. The reference
1784 * ensures this sp->done() call and not the call in
1785 * qla2xxx_eh_abort() ends the SCSI cmd (with result 'res').
1786 */
1787 if (!sp_get(sp)) {
938edb8a
LT		 1788 int status;
1789
c4e521b6 1790 spin_unlock_irqrestore(qp->qp_lock_ptr, *flags);
938edb8a 1791 status = qla2xxx_eh_abort(GET_CMD_SP(sp));
c4e521b6 1792 spin_lock_irqsave(qp->qp_lock_ptr, *flags);
938edb8a
LT		 1793 /*
1794 * Get rid of extra reference caused
1795 * by early exit from qla2xxx_eh_abort
1796 */
1797 if (status == FAST_IO_FAIL)
1798 atomic_dec(&sp->ref_count);
c4e521b6
BVA		 1799 }
1800 }
1801 sp->done(sp, res);
1802}
1803
bbead493
QT		 1804static void
1805__qla2x00_abort_all_cmds(struct qla_qpair *qp, int res)
df4bf0bb 1806{
eb023220 1807 int cnt;
df4bf0bb
AV		 1808 unsigned long flags;
1809 srb_t *sp;
bbead493 1810 scsi_qla_host_t *vha = qp->vha;
e315cd28 1811 struct qla_hw_data *ha = vha->hw;
73208dfd 1812 struct req_que *req;
c5419e26
QT		 1813 struct qla_tgt *tgt = vha->vha_tgt.qla_tgt;
1814 struct qla_tgt_cmd *cmd;
c0cb4496 1815
6a2cf8d3
BK		 1816 if (!ha->req_q_map)
1817 return;
bbead493
QT		 1818 spin_lock_irqsave(qp->qp_lock_ptr, flags);
1819 req = qp->req;
1820 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) {
1821 sp = req->outstanding_cmds[cnt];
1822 if (sp) {
1823 req->outstanding_cmds[cnt] = NULL;
6b0431d6
QT		 1824 switch (sp->cmd_type) {
1825 case TYPE_SRB:
c4e521b6 1826 qla2x00_abort_srb(qp, sp, res, &flags);
585def9b
QT		 1827 break;
1828 case TYPE_TGT_CMD:
bbead493
QT		 1829 if (!vha->hw->tgt.tgt_ops || !tgt ||
1830 qla_ini_mode_enabled(vha)) {
585def9b
QT		 1831 ql_dbg(ql_dbg_tgt_mgt, vha, 0xf003,
1832 "HOST-ABORT-HNDLR: dpc_flags=%lx. Target mode disabled\n",
1833 vha->dpc_flags);
bbead493 1834 continue;
c733ab35 1835 }
bbead493
QT		 1836 cmd = (struct qla_tgt_cmd *)sp;
1837 qlt_abort_cmd_on_host_reset(cmd->vha, cmd);
585def9b
QT		 1838 break;
1839 case TYPE_TGT_TMCMD:
1840 /*
1841 * Currently, only ABTS response gets on the
1842 * outstanding_cmds[]
1843 */
1844 ha->tgt.tgt_ops->free_mcmd(
1845 (struct qla_tgt_mgmt_cmd *)sp);
1846 break;
1847 default:
1848 break;
73208dfd 1849 }
df4bf0bb
AV		 1850 }
1851 }
bbead493
QT		 1852 spin_unlock_irqrestore(qp->qp_lock_ptr, flags);
1853}
1854
1855void
1856qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res)
1857{
1858 int que;
1859 struct qla_hw_data *ha = vha->hw;
1860
1861 __qla2x00_abort_all_cmds(ha->base_qpair, res);
1862
1863 for (que = 0; que < ha->max_qpairs; que++) {
1864 if (!ha->queue_pair_map[que])
1865 continue;
1866
1867 __qla2x00_abort_all_cmds(ha->queue_pair_map[que], res);
1868 }
df4bf0bb
AV		 1869}
1870
f4f051eb 1871static int
1872qla2xxx_slave_alloc(struct scsi_device *sdev)
1da177e4 1873{
bdf79621 1874 struct fc_rport *rport = starget_to_rport(scsi_target(sdev));
1da177e4 1875
19a7b4ae 1876 if (!rport || fc_remote_port_chkready(rport))
f4f051eb 1877 return -ENXIO;
bdf79621 1878
19a7b4ae 1879 sdev->hostdata = *(fc_port_t **)rport->dd_data;
1da177e4 1880
f4f051eb 1881 return 0;
1882}
1da177e4 1883
f4f051eb 1884static int
1885qla2xxx_slave_configure(struct scsi_device *sdev)
1886{
e315cd28 1887 scsi_qla_host_t *vha = shost_priv(sdev->host);
2afa19a9 1888 struct req_que *req = vha->req;
8482e118 1889
9e522cd8
AE		 1890 if (IS_T10_PI_CAPABLE(vha->hw))
1891 blk_queue_update_dma_alignment(sdev->request_queue, 0x7);
1892
db5ed4df 1893 scsi_change_queue_depth(sdev, req->max_q_depth);
f4f051eb 1894 return 0;
1895}
1da177e4 1896
f4f051eb 1897static void
1898qla2xxx_slave_destroy(struct scsi_device *sdev)
1899{
1900 sdev->hostdata = NULL;
1da177e4
LT		 1901}
1902
1903/**
1904 * qla2x00_config_dma_addressing() - Configure OS DMA addressing method.
1905 * @ha: HA context
1906 *
1907 * At exit, the @ha's flags.enable_64bit_addressing set to indicated
1908 * supported addressing method.
1909 */
1910static void
53303c42 1911qla2x00_config_dma_addressing(struct qla_hw_data *ha)
1da177e4 1912{
7524f9b9 1913 /* Assume a 32bit DMA mask. */
1da177e4 1914 ha->flags.enable_64bit_addressing = 0;
1da177e4 1915
6a35528a 1916 if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) {
7524f9b9
AV		 1917 /* Any upper-dword bits set? */
1918 if (MSD(dma_get_required_mask(&ha->pdev->dev)) &&
6a35528a 1919 !pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(64))) {
7524f9b9 1920 /* Ok, a 64bit DMA mask is applicable. */
1da177e4 1921 ha->flags.enable_64bit_addressing = 1;
fd34f556
AV		 1922 ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64;
1923 ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64;
7524f9b9 1924 return;
1da177e4 1925 }
1da177e4 1926 }
7524f9b9 1927
284901a9
YH		 1928 dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32));
1929 pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(32));
1da177e4
LT		 1930}
1931
fd34f556 1932static void
e315cd28 1933qla2x00_enable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1934{
1935 unsigned long flags = 0;
1936 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1937
1938 spin_lock_irqsave(&ha->hardware_lock, flags);
1939 ha->interrupts_on = 1;
1940 /* enable risc and host interrupts */
1941 WRT_REG_WORD(&reg->ictrl, ICR_EN_INT | ICR_EN_RISC);
1942 RD_REG_WORD(&reg->ictrl);
1943 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1944
1945}
1946
1947static void
e315cd28 1948qla2x00_disable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1949{
1950 unsigned long flags = 0;
1951 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1952
1953 spin_lock_irqsave(&ha->hardware_lock, flags);
1954 ha->interrupts_on = 0;
1955 /* disable risc and host interrupts */
1956 WRT_REG_WORD(&reg->ictrl, 0);
1957 RD_REG_WORD(&reg->ictrl);
1958 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1959}
1960
1961static void
e315cd28 1962qla24xx_enable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1963{
1964 unsigned long flags = 0;
1965 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1966
1967 spin_lock_irqsave(&ha->hardware_lock, flags);
1968 ha->interrupts_on = 1;
1969 WRT_REG_DWORD(&reg->ictrl, ICRX_EN_RISC_INT);
1970 RD_REG_DWORD(&reg->ictrl);
1971 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1972}
1973
1974static void
e315cd28 1975qla24xx_disable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1976{
1977 unsigned long flags = 0;
1978 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1979
124f85e6
AV		 1980 if (IS_NOPOLLING_TYPE(ha))
1981 return;
fd34f556
AV		 1982 spin_lock_irqsave(&ha->hardware_lock, flags);
1983 ha->interrupts_on = 0;
1984 WRT_REG_DWORD(&reg->ictrl, 0);
1985 RD_REG_DWORD(&reg->ictrl);
1986 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1987}
1988
706f457d
GM		 1989static int
1990qla2x00_iospace_config(struct qla_hw_data *ha)
1991{
1992 resource_size_t pio;
1993 uint16_t msix;
706f457d 1994
706f457d
GM		 1995 if (pci_request_selected_regions(ha->pdev, ha->bars,
1996 QLA2XXX_DRIVER_NAME)) {
1997 ql_log_pci(ql_log_fatal, ha->pdev, 0x0011,
1998 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
1999 pci_name(ha->pdev));
2000 goto iospace_error_exit;
2001 }
2002 if (!(ha->bars & 1))
2003 goto skip_pio;
2004
2005 /* We only need PIO for Flash operations on ISP2312 v2 chips. */
2006 pio = pci_resource_start(ha->pdev, 0);
2007 if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) {
2008 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
2009 ql_log_pci(ql_log_warn, ha->pdev, 0x0012,
2010 "Invalid pci I/O region size (%s).\n",
2011 pci_name(ha->pdev));
2012 pio = 0;
2013 }
2014 } else {
2015 ql_log_pci(ql_log_warn, ha->pdev, 0x0013,
2016 "Region #0 no a PIO resource (%s).\n",
2017 pci_name(ha->pdev));
2018 pio = 0;
2019 }
2020 ha->pio_address = pio;
2021 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014,
2022 "PIO address=%llu.\n",
2023 (unsigned long long)ha->pio_address);
2024
2025skip_pio:
2026 /* Use MMIO operations for all accesses. */
2027 if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) {
2028 ql_log_pci(ql_log_fatal, ha->pdev, 0x0015,
2029 "Region #1 not an MMIO resource (%s), aborting.\n",
2030 pci_name(ha->pdev));
2031 goto iospace_error_exit;
2032 }
2033 if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) {
2034 ql_log_pci(ql_log_fatal, ha->pdev, 0x0016,
2035 "Invalid PCI mem region size (%s), aborting.\n",
2036 pci_name(ha->pdev));
2037 goto iospace_error_exit;
2038 }
2039
2040 ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN);
2041 if (!ha->iobase) {
2042 ql_log_pci(ql_log_fatal, ha->pdev, 0x0017,
2043 "Cannot remap MMIO (%s), aborting.\n",
2044 pci_name(ha->pdev));
2045 goto iospace_error_exit;
2046 }
2047
2048 /* Determine queue resources */
2049 ha->max_req_queues = ha->max_rsp_queues = 1;
f54f2cb5 2050 ha->msix_count = QLA_BASE_VECTORS;
c38d1baf
HM		 2051 if (!ql2xmqsupport || !ql2xnvmeenable ||
2052 (!IS_QLA25XX(ha) && !IS_QLA81XX(ha)))
706f457d
GM		 2053 goto mqiobase_exit;
2054
2055 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3),
2056 pci_resource_len(ha->pdev, 3));
2057 if (ha->mqiobase) {
2058 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018,
2059 "MQIO Base=%p.\n", ha->mqiobase);
2060 /* Read MSIX vector size of the board */
2061 pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix);
d7459527 2062 ha->msix_count = msix + 1;
706f457d 2063 /* Max queues are bounded by available msix vectors */
d7459527
MH		 2064 /* MB interrupt uses 1 vector */
2065 ha->max_req_queues = ha->msix_count - 1;
2066 ha->max_rsp_queues = ha->max_req_queues;
2067 /* Queue pairs is the max value minus the base queue pair */
2068 ha->max_qpairs = ha->max_rsp_queues - 1;
2069 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0188,
2070 "Max no of queues pairs: %d.\n", ha->max_qpairs);
2071
706f457d 2072 ql_log_pci(ql_log_info, ha->pdev, 0x001a,
d7459527 2073 "MSI-X vector count: %d.\n", ha->msix_count);
706f457d
GM		 2074 } else
2075 ql_log_pci(ql_log_info, ha->pdev, 0x001b,
2076 "BAR 3 not enabled.\n");
2077
2078mqiobase_exit:
706f457d 2079 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c,
f54f2cb5 2080 "MSIX Count: %d.\n", ha->msix_count);
706f457d
GM		 2081 return (0);
2082
2083iospace_error_exit:
2084 return (-ENOMEM);
2085}
2086
2087
6246b8a1
GM		 2088static int
2089qla83xx_iospace_config(struct qla_hw_data *ha)
2090{
2091 uint16_t msix;
6246b8a1
GM		 2092
2093 if (pci_request_selected_regions(ha->pdev, ha->bars,
2094 QLA2XXX_DRIVER_NAME)) {
2095 ql_log_pci(ql_log_fatal, ha->pdev, 0x0117,
2096 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
2097 pci_name(ha->pdev));
2098
2099 goto iospace_error_exit;
2100 }
2101
2102 /* Use MMIO operations for all accesses. */
2103 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) {
2104 ql_log_pci(ql_log_warn, ha->pdev, 0x0118,
2105 "Invalid pci I/O region size (%s).\n",
2106 pci_name(ha->pdev));
2107 goto iospace_error_exit;
2108 }
2109 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
2110 ql_log_pci(ql_log_warn, ha->pdev, 0x0119,
2111 "Invalid PCI mem region size (%s), aborting\n",
2112 pci_name(ha->pdev));
2113 goto iospace_error_exit;
2114 }
2115
2116 ha->iobase = ioremap(pci_resource_start(ha->pdev, 0), MIN_IOBASE_LEN);
2117 if (!ha->iobase) {
2118 ql_log_pci(ql_log_fatal, ha->pdev, 0x011a,
2119 "Cannot remap MMIO (%s), aborting.\n",
2120 pci_name(ha->pdev));
2121 goto iospace_error_exit;
2122 }
2123
2124 /* 64bit PCI BAR - BAR2 will correspoond to region 4 */
2125 /* 83XX 26XX always use MQ type access for queues
2126 * - mbar 2, a.k.a region 4 */
2127 ha->max_req_queues = ha->max_rsp_queues = 1;
f54f2cb5 2128 ha->msix_count = QLA_BASE_VECTORS;
6246b8a1
GM		 2129 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 4),
2130 pci_resource_len(ha->pdev, 4));
2131
2132 if (!ha->mqiobase) {
2133 ql_log_pci(ql_log_fatal, ha->pdev, 0x011d,
2134 "BAR2/region4 not enabled\n");
2135 goto mqiobase_exit;
2136 }
2137
2138 ha->msixbase = ioremap(pci_resource_start(ha->pdev, 2),
2139 pci_resource_len(ha->pdev, 2));
2140 if (ha->msixbase) {
2141 /* Read MSIX vector size of the board */
2142 pci_read_config_word(ha->pdev,
2143 QLA_83XX_PCI_MSIX_CONTROL, &msix);
e326d22a 2144 ha->msix_count = (msix & PCI_MSIX_FLAGS_QSIZE) + 1;
093df737
QT		 2145 /*
2146 * By default, driver uses at least two msix vectors
2147 * (default & rspq)
2148 */
c38d1baf 2149 if (ql2xmqsupport || ql2xnvmeenable) {
d7459527
MH		 2150 /* MB interrupt uses 1 vector */
2151 ha->max_req_queues = ha->msix_count - 1;
093df737
QT		 2152
2153 /* ATIOQ needs 1 vector. That's 1 less QPair */
2154 if (QLA_TGT_MODE_ENABLED())
2155 ha->max_req_queues--;
2156
d0d2c68b
MH		 2157 ha->max_rsp_queues = ha->max_req_queues;
2158
d7459527
MH		 2159 /* Queue pairs is the max value minus
2160 * the base queue pair */
2161 ha->max_qpairs = ha->max_req_queues - 1;
83548fe2 2162 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x00e3,
d7459527 2163 "Max no of queues pairs: %d.\n", ha->max_qpairs);
6246b8a1
GM		 2164 }
2165 ql_log_pci(ql_log_info, ha->pdev, 0x011c,
d7459527 2166 "MSI-X vector count: %d.\n", ha->msix_count);
6246b8a1
GM		 2167 } else
2168 ql_log_pci(ql_log_info, ha->pdev, 0x011e,
2169 "BAR 1 not enabled.\n");
2170
2171mqiobase_exit:
6246b8a1 2172 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011f,
f54f2cb5 2173 "MSIX Count: %d.\n", ha->msix_count);
6246b8a1
GM		 2174 return 0;
2175
2176iospace_error_exit:
2177 return -ENOMEM;
2178}
2179
fd34f556
AV		 2180static struct isp_operations qla2100_isp_ops = {
2181 .pci_config = qla2100_pci_config,
2182 .reset_chip = qla2x00_reset_chip,
2183 .chip_diag = qla2x00_chip_diag,
2184 .config_rings = qla2x00_config_rings,
2185 .reset_adapter = qla2x00_reset_adapter,
2186 .nvram_config = qla2x00_nvram_config,
2187 .update_fw_options = qla2x00_update_fw_options,
2188 .load_risc = qla2x00_load_risc,
2189 .pci_info_str = qla2x00_pci_info_str,
2190 .fw_version_str = qla2x00_fw_version_str,
2191 .intr_handler = qla2100_intr_handler,
2192 .enable_intrs = qla2x00_enable_intrs,
2193 .disable_intrs = qla2x00_disable_intrs,
2194 .abort_command = qla2x00_abort_command,
523ec773
AV		 2195 .target_reset = qla2x00_abort_target,
2196 .lun_reset = qla2x00_lun_reset,
fd34f556
AV		 2197 .fabric_login = qla2x00_login_fabric,
2198 .fabric_logout = qla2x00_fabric_logout,
2199 .calc_req_entries = qla2x00_calc_iocbs_32,
2200 .build_iocbs = qla2x00_build_scsi_iocbs_32,
2201 .prep_ms_iocb = qla2x00_prep_ms_iocb,
2202 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
2203 .read_nvram = qla2x00_read_nvram_data,
2204 .write_nvram = qla2x00_write_nvram_data,
2205 .fw_dump = qla2100_fw_dump,
2206 .beacon_on = NULL,
2207 .beacon_off = NULL,
2208 .beacon_blink = NULL,
2209 .read_optrom = qla2x00_read_optrom_data,
2210 .write_optrom = qla2x00_write_optrom_data,
2211 .get_flash_version = qla2x00_get_flash_version,
e315cd28 2212 .start_scsi = qla2x00_start_scsi,
d7459527 2213 .start_scsi_mq = NULL,
a9083016 2214 .abort_isp = qla2x00_abort_isp,
706f457d 2215 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2216 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 2217};
2218
2219static struct isp_operations qla2300_isp_ops = {
2220 .pci_config = qla2300_pci_config,
2221 .reset_chip = qla2x00_reset_chip,
2222 .chip_diag = qla2x00_chip_diag,
2223 .config_rings = qla2x00_config_rings,
2224 .reset_adapter = qla2x00_reset_adapter,
2225 .nvram_config = qla2x00_nvram_config,
2226 .update_fw_options = qla2x00_update_fw_options,
2227 .load_risc = qla2x00_load_risc,
2228 .pci_info_str = qla2x00_pci_info_str,
2229 .fw_version_str = qla2x00_fw_version_str,
2230 .intr_handler = qla2300_intr_handler,
2231 .enable_intrs = qla2x00_enable_intrs,
2232 .disable_intrs = qla2x00_disable_intrs,
2233 .abort_command = qla2x00_abort_command,
523ec773
AV		 2234 .target_reset = qla2x00_abort_target,
2235 .lun_reset = qla2x00_lun_reset,
fd34f556
AV		 2236 .fabric_login = qla2x00_login_fabric,
2237 .fabric_logout = qla2x00_fabric_logout,
2238 .calc_req_entries = qla2x00_calc_iocbs_32,
2239 .build_iocbs = qla2x00_build_scsi_iocbs_32,
2240 .prep_ms_iocb = qla2x00_prep_ms_iocb,
2241 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
2242 .read_nvram = qla2x00_read_nvram_data,
2243 .write_nvram = qla2x00_write_nvram_data,
2244 .fw_dump = qla2300_fw_dump,
2245 .beacon_on = qla2x00_beacon_on,
2246 .beacon_off = qla2x00_beacon_off,
2247 .beacon_blink = qla2x00_beacon_blink,
2248 .read_optrom = qla2x00_read_optrom_data,
2249 .write_optrom = qla2x00_write_optrom_data,
2250 .get_flash_version = qla2x00_get_flash_version,
e315cd28 2251 .start_scsi = qla2x00_start_scsi,
d7459527 2252 .start_scsi_mq = NULL,
a9083016 2253 .abort_isp = qla2x00_abort_isp,
7ec0effd 2254 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2255 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 2256};
2257
2258static struct isp_operations qla24xx_isp_ops = {
2259 .pci_config = qla24xx_pci_config,
2260 .reset_chip = qla24xx_reset_chip,
2261 .chip_diag = qla24xx_chip_diag,
2262 .config_rings = qla24xx_config_rings,
2263 .reset_adapter = qla24xx_reset_adapter,
2264 .nvram_config = qla24xx_nvram_config,
2265 .update_fw_options = qla24xx_update_fw_options,
2266 .load_risc = qla24xx_load_risc,
2267 .pci_info_str = qla24xx_pci_info_str,
2268 .fw_version_str = qla24xx_fw_version_str,
2269 .intr_handler = qla24xx_intr_handler,
2270 .enable_intrs = qla24xx_enable_intrs,
2271 .disable_intrs = qla24xx_disable_intrs,
2272 .abort_command = qla24xx_abort_command,
523ec773
AV		 2273 .target_reset = qla24xx_abort_target,
2274 .lun_reset = qla24xx_lun_reset,
fd34f556
AV		 2275 .fabric_login = qla24xx_login_fabric,
2276 .fabric_logout = qla24xx_fabric_logout,
2277 .calc_req_entries = NULL,
2278 .build_iocbs = NULL,
2279 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2280 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2281 .read_nvram = qla24xx_read_nvram_data,
2282 .write_nvram = qla24xx_write_nvram_data,
2283 .fw_dump = qla24xx_fw_dump,
2284 .beacon_on = qla24xx_beacon_on,
2285 .beacon_off = qla24xx_beacon_off,
2286 .beacon_blink = qla24xx_beacon_blink,
2287 .read_optrom = qla24xx_read_optrom_data,
2288 .write_optrom = qla24xx_write_optrom_data,
2289 .get_flash_version = qla24xx_get_flash_version,
e315cd28 2290 .start_scsi = qla24xx_start_scsi,
d7459527 2291 .start_scsi_mq = NULL,
a9083016 2292 .abort_isp = qla2x00_abort_isp,
7ec0effd 2293 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2294 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 2295};
2296
c3a2f0df
AV		 2297static struct isp_operations qla25xx_isp_ops = {
2298 .pci_config = qla25xx_pci_config,
2299 .reset_chip = qla24xx_reset_chip,
2300 .chip_diag = qla24xx_chip_diag,
2301 .config_rings = qla24xx_config_rings,
2302 .reset_adapter = qla24xx_reset_adapter,
2303 .nvram_config = qla24xx_nvram_config,
2304 .update_fw_options = qla24xx_update_fw_options,
2305 .load_risc = qla24xx_load_risc,
2306 .pci_info_str = qla24xx_pci_info_str,
2307 .fw_version_str = qla24xx_fw_version_str,
2308 .intr_handler = qla24xx_intr_handler,
2309 .enable_intrs = qla24xx_enable_intrs,
2310 .disable_intrs = qla24xx_disable_intrs,
2311 .abort_command = qla24xx_abort_command,
523ec773
AV		 2312 .target_reset = qla24xx_abort_target,
2313 .lun_reset = qla24xx_lun_reset,
c3a2f0df
AV		 2314 .fabric_login = qla24xx_login_fabric,
2315 .fabric_logout = qla24xx_fabric_logout,
2316 .calc_req_entries = NULL,
2317 .build_iocbs = NULL,
2318 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2319 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2320 .read_nvram = qla25xx_read_nvram_data,
2321 .write_nvram = qla25xx_write_nvram_data,
2322 .fw_dump = qla25xx_fw_dump,
2323 .beacon_on = qla24xx_beacon_on,
2324 .beacon_off = qla24xx_beacon_off,
2325 .beacon_blink = qla24xx_beacon_blink,
338c9161 2326 .read_optrom = qla25xx_read_optrom_data,
c3a2f0df
AV		 2327 .write_optrom = qla24xx_write_optrom_data,
2328 .get_flash_version = qla24xx_get_flash_version,
bad75002 2329 .start_scsi = qla24xx_dif_start_scsi,
d7459527 2330 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
a9083016 2331 .abort_isp = qla2x00_abort_isp,
7ec0effd 2332 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2333 .initialize_adapter = qla2x00_initialize_adapter,
c3a2f0df
AV		 2334};
2335
3a03eb79
AV		 2336static struct isp_operations qla81xx_isp_ops = {
2337 .pci_config = qla25xx_pci_config,
2338 .reset_chip = qla24xx_reset_chip,
2339 .chip_diag = qla24xx_chip_diag,
2340 .config_rings = qla24xx_config_rings,
2341 .reset_adapter = qla24xx_reset_adapter,
2342 .nvram_config = qla81xx_nvram_config,
2343 .update_fw_options = qla81xx_update_fw_options,
eaac30be 2344 .load_risc = qla81xx_load_risc,
3a03eb79
AV		 2345 .pci_info_str = qla24xx_pci_info_str,
2346 .fw_version_str = qla24xx_fw_version_str,
2347 .intr_handler = qla24xx_intr_handler,
2348 .enable_intrs = qla24xx_enable_intrs,
2349 .disable_intrs = qla24xx_disable_intrs,
2350 .abort_command = qla24xx_abort_command,
2351 .target_reset = qla24xx_abort_target,
2352 .lun_reset = qla24xx_lun_reset,
2353 .fabric_login = qla24xx_login_fabric,
2354 .fabric_logout = qla24xx_fabric_logout,
2355 .calc_req_entries = NULL,
2356 .build_iocbs = NULL,
2357 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2358 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
3d79038f
AV		 2359 .read_nvram = NULL,
2360 .write_nvram = NULL,
3a03eb79
AV		 2361 .fw_dump = qla81xx_fw_dump,
2362 .beacon_on = qla24xx_beacon_on,
2363 .beacon_off = qla24xx_beacon_off,
6246b8a1 2364 .beacon_blink = qla83xx_beacon_blink,
3a03eb79
AV		 2365 .read_optrom = qla25xx_read_optrom_data,
2366 .write_optrom = qla24xx_write_optrom_data,
2367 .get_flash_version = qla24xx_get_flash_version,
ba77ef53 2368 .start_scsi = qla24xx_dif_start_scsi,
d7459527 2369 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
a9083016 2370 .abort_isp = qla2x00_abort_isp,
7ec0effd 2371 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2372 .initialize_adapter = qla2x00_initialize_adapter,
a9083016
GM		 2373};
2374
2375static struct isp_operations qla82xx_isp_ops = {
2376 .pci_config = qla82xx_pci_config,
2377 .reset_chip = qla82xx_reset_chip,
2378 .chip_diag = qla24xx_chip_diag,
2379 .config_rings = qla82xx_config_rings,
2380 .reset_adapter = qla24xx_reset_adapter,
2381 .nvram_config = qla81xx_nvram_config,
2382 .update_fw_options = qla24xx_update_fw_options,
2383 .load_risc = qla82xx_load_risc,
9d55ca66 2384 .pci_info_str = qla24xx_pci_info_str,
a9083016
GM		 2385 .fw_version_str = qla24xx_fw_version_str,
2386 .intr_handler = qla82xx_intr_handler,
2387 .enable_intrs = qla82xx_enable_intrs,
2388 .disable_intrs = qla82xx_disable_intrs,
2389 .abort_command = qla24xx_abort_command,
2390 .target_reset = qla24xx_abort_target,
2391 .lun_reset = qla24xx_lun_reset,
2392 .fabric_login = qla24xx_login_fabric,
2393 .fabric_logout = qla24xx_fabric_logout,
2394 .calc_req_entries = NULL,
2395 .build_iocbs = NULL,
2396 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2397 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2398 .read_nvram = qla24xx_read_nvram_data,
2399 .write_nvram = qla24xx_write_nvram_data,
a1b23c5a 2400 .fw_dump = qla82xx_fw_dump,
999916dc
SK		 2401 .beacon_on = qla82xx_beacon_on,
2402 .beacon_off = qla82xx_beacon_off,
2403 .beacon_blink = NULL,
a9083016
GM		 2404 .read_optrom = qla82xx_read_optrom_data,
2405 .write_optrom = qla82xx_write_optrom_data,
7ec0effd 2406 .get_flash_version = qla82xx_get_flash_version,
a9083016 2407 .start_scsi = qla82xx_start_scsi,
d7459527 2408 .start_scsi_mq = NULL,
a9083016 2409 .abort_isp = qla82xx_abort_isp,
706f457d 2410 .iospace_config = qla82xx_iospace_config,
8ae6d9c7 2411 .initialize_adapter = qla2x00_initialize_adapter,
3a03eb79
AV		 2412};
2413
7ec0effd
AD		 2414static struct isp_operations qla8044_isp_ops = {
2415 .pci_config = qla82xx_pci_config,
2416 .reset_chip = qla82xx_reset_chip,
2417 .chip_diag = qla24xx_chip_diag,
2418 .config_rings = qla82xx_config_rings,
2419 .reset_adapter = qla24xx_reset_adapter,
2420 .nvram_config = qla81xx_nvram_config,
2421 .update_fw_options = qla24xx_update_fw_options,
2422 .load_risc = qla82xx_load_risc,
2423 .pci_info_str = qla24xx_pci_info_str,
2424 .fw_version_str = qla24xx_fw_version_str,
2425 .intr_handler = qla8044_intr_handler,
2426 .enable_intrs = qla82xx_enable_intrs,
2427 .disable_intrs = qla82xx_disable_intrs,
2428 .abort_command = qla24xx_abort_command,
2429 .target_reset = qla24xx_abort_target,
2430 .lun_reset = qla24xx_lun_reset,
2431 .fabric_login = qla24xx_login_fabric,
2432 .fabric_logout = qla24xx_fabric_logout,
2433 .calc_req_entries = NULL,
2434 .build_iocbs = NULL,
2435 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2436 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2437 .read_nvram = NULL,
2438 .write_nvram = NULL,
a1b23c5a 2439 .fw_dump = qla8044_fw_dump,
7ec0effd
AD		 2440 .beacon_on = qla82xx_beacon_on,
2441 .beacon_off = qla82xx_beacon_off,
2442 .beacon_blink = NULL,
888e639d 2443 .read_optrom = qla8044_read_optrom_data,
7ec0effd
AD		 2444 .write_optrom = qla8044_write_optrom_data,
2445 .get_flash_version = qla82xx_get_flash_version,
2446 .start_scsi = qla82xx_start_scsi,
d7459527 2447 .start_scsi_mq = NULL,
7ec0effd
AD		 2448 .abort_isp = qla8044_abort_isp,
2449 .iospace_config = qla82xx_iospace_config,
2450 .initialize_adapter = qla2x00_initialize_adapter,
2451};
2452
6246b8a1
GM		 2453static struct isp_operations qla83xx_isp_ops = {
2454 .pci_config = qla25xx_pci_config,
2455 .reset_chip = qla24xx_reset_chip,
2456 .chip_diag = qla24xx_chip_diag,
2457 .config_rings = qla24xx_config_rings,
2458 .reset_adapter = qla24xx_reset_adapter,
2459 .nvram_config = qla81xx_nvram_config,
2460 .update_fw_options = qla81xx_update_fw_options,
2461 .load_risc = qla81xx_load_risc,
2462 .pci_info_str = qla24xx_pci_info_str,
2463 .fw_version_str = qla24xx_fw_version_str,
2464 .intr_handler = qla24xx_intr_handler,
2465 .enable_intrs = qla24xx_enable_intrs,
2466 .disable_intrs = qla24xx_disable_intrs,
2467 .abort_command = qla24xx_abort_command,
2468 .target_reset = qla24xx_abort_target,
2469 .lun_reset = qla24xx_lun_reset,
2470 .fabric_login = qla24xx_login_fabric,
2471 .fabric_logout = qla24xx_fabric_logout,
2472 .calc_req_entries = NULL,
2473 .build_iocbs = NULL,
2474 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2475 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2476 .read_nvram = NULL,
2477 .write_nvram = NULL,
2478 .fw_dump = qla83xx_fw_dump,
2479 .beacon_on = qla24xx_beacon_on,
2480 .beacon_off = qla24xx_beacon_off,
2481 .beacon_blink = qla83xx_beacon_blink,
2482 .read_optrom = qla25xx_read_optrom_data,
2483 .write_optrom = qla24xx_write_optrom_data,
2484 .get_flash_version = qla24xx_get_flash_version,
2485 .start_scsi = qla24xx_dif_start_scsi,
d7459527 2486 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
6246b8a1
GM		 2487 .abort_isp = qla2x00_abort_isp,
2488 .iospace_config = qla83xx_iospace_config,
8ae6d9c7
GM		 2489 .initialize_adapter = qla2x00_initialize_adapter,
2490};
2491
2492static struct isp_operations qlafx00_isp_ops = {
2493 .pci_config = qlafx00_pci_config,
2494 .reset_chip = qlafx00_soft_reset,
2495 .chip_diag = qlafx00_chip_diag,
2496 .config_rings = qlafx00_config_rings,
2497 .reset_adapter = qlafx00_soft_reset,
2498 .nvram_config = NULL,
2499 .update_fw_options = NULL,
2500 .load_risc = NULL,
2501 .pci_info_str = qlafx00_pci_info_str,
2502 .fw_version_str = qlafx00_fw_version_str,
2503 .intr_handler = qlafx00_intr_handler,
2504 .enable_intrs = qlafx00_enable_intrs,
2505 .disable_intrs = qlafx00_disable_intrs,
4440e46d 2506 .abort_command = qla24xx_async_abort_command,
8ae6d9c7
GM		 2507 .target_reset = qlafx00_abort_target,
2508 .lun_reset = qlafx00_lun_reset,
2509 .fabric_login = NULL,
2510 .fabric_logout = NULL,
2511 .calc_req_entries = NULL,
2512 .build_iocbs = NULL,
2513 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2514 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2515 .read_nvram = qla24xx_read_nvram_data,
2516 .write_nvram = qla24xx_write_nvram_data,
2517 .fw_dump = NULL,
2518 .beacon_on = qla24xx_beacon_on,
2519 .beacon_off = qla24xx_beacon_off,
2520 .beacon_blink = NULL,
2521 .read_optrom = qla24xx_read_optrom_data,
2522 .write_optrom = qla24xx_write_optrom_data,
2523 .get_flash_version = qla24xx_get_flash_version,
2524 .start_scsi = qlafx00_start_scsi,
d7459527 2525 .start_scsi_mq = NULL,
8ae6d9c7
GM		 2526 .abort_isp = qlafx00_abort_isp,
2527 .iospace_config = qlafx00_iospace_config,
2528 .initialize_adapter = qlafx00_initialize_adapter,
6246b8a1
GM		 2529};
2530
f73cb695
CD		 2531static struct isp_operations qla27xx_isp_ops = {
2532 .pci_config = qla25xx_pci_config,
2533 .reset_chip = qla24xx_reset_chip,
2534 .chip_diag = qla24xx_chip_diag,
2535 .config_rings = qla24xx_config_rings,
2536 .reset_adapter = qla24xx_reset_adapter,
2537 .nvram_config = qla81xx_nvram_config,
2538 .update_fw_options = qla81xx_update_fw_options,
2539 .load_risc = qla81xx_load_risc,
2540 .pci_info_str = qla24xx_pci_info_str,
2541 .fw_version_str = qla24xx_fw_version_str,
2542 .intr_handler = qla24xx_intr_handler,
2543 .enable_intrs = qla24xx_enable_intrs,
2544 .disable_intrs = qla24xx_disable_intrs,
2545 .abort_command = qla24xx_abort_command,
2546 .target_reset = qla24xx_abort_target,
2547 .lun_reset = qla24xx_lun_reset,
2548 .fabric_login = qla24xx_login_fabric,
2549 .fabric_logout = qla24xx_fabric_logout,
2550 .calc_req_entries = NULL,
2551 .build_iocbs = NULL,
2552 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2553 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2554 .read_nvram = NULL,
2555 .write_nvram = NULL,
2556 .fw_dump = qla27xx_fwdump,
2557 .beacon_on = qla24xx_beacon_on,
2558 .beacon_off = qla24xx_beacon_off,
2559 .beacon_blink = qla83xx_beacon_blink,
2560 .read_optrom = qla25xx_read_optrom_data,
2561 .write_optrom = qla24xx_write_optrom_data,
2562 .get_flash_version = qla24xx_get_flash_version,
2563 .start_scsi = qla24xx_dif_start_scsi,
d7459527 2564 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
f73cb695
CD		 2565 .abort_isp = qla2x00_abort_isp,
2566 .iospace_config = qla83xx_iospace_config,
2567 .initialize_adapter = qla2x00_initialize_adapter,
2568};
2569
ea5b6382 2570static inline void
e315cd28 2571qla2x00_set_isp_flags(struct qla_hw_data *ha)
ea5b6382 2572{
2573 ha->device_type = DT_EXTENDED_IDS;
2574 switch (ha->pdev->device) {
2575 case PCI_DEVICE_ID_QLOGIC_ISP2100:
9e052e2d 2576 ha->isp_type |= DT_ISP2100;
ea5b6382 2577 ha->device_type &= ~DT_EXTENDED_IDS;
441d1072 2578 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
ea5b6382 2579 break;
2580 case PCI_DEVICE_ID_QLOGIC_ISP2200:
9e052e2d 2581 ha->isp_type |= DT_ISP2200;
ea5b6382 2582 ha->device_type &= ~DT_EXTENDED_IDS;
441d1072 2583 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
ea5b6382 2584 break;
2585 case PCI_DEVICE_ID_QLOGIC_ISP2300:
9e052e2d 2586 ha->isp_type |= DT_ISP2300;
4a59f71d 2587 ha->device_type |= DT_ZIO_SUPPORTED;
441d1072 2588 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 2589 break;
2590 case PCI_DEVICE_ID_QLOGIC_ISP2312:
9e052e2d 2591 ha->isp_type |= DT_ISP2312;
4a59f71d 2592 ha->device_type |= DT_ZIO_SUPPORTED;
441d1072 2593 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 2594 break;
2595 case PCI_DEVICE_ID_QLOGIC_ISP2322:
9e052e2d 2596 ha->isp_type |= DT_ISP2322;
4a59f71d 2597 ha->device_type |= DT_ZIO_SUPPORTED;
ea5b6382 2598 if (ha->pdev->subsystem_vendor == 0x1028 &&
2599 ha->pdev->subsystem_device == 0x0170)
2600 ha->device_type |= DT_OEM_001;
441d1072 2601 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 2602 break;
2603 case PCI_DEVICE_ID_QLOGIC_ISP6312:
9e052e2d 2604 ha->isp_type |= DT_ISP6312;
441d1072 2605 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 2606 break;
2607 case PCI_DEVICE_ID_QLOGIC_ISP6322:
9e052e2d 2608 ha->isp_type |= DT_ISP6322;
441d1072 2609 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 2610 break;
2611 case PCI_DEVICE_ID_QLOGIC_ISP2422:
9e052e2d 2612 ha->isp_type |= DT_ISP2422;
4a59f71d 2613 ha->device_type |= DT_ZIO_SUPPORTED;
e428924c 2614 ha->device_type |= DT_FWI2;
c76f2c01 2615 ha->device_type |= DT_IIDMA;
441d1072 2616 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2617 break;
2618 case PCI_DEVICE_ID_QLOGIC_ISP2432:
9e052e2d 2619 ha->isp_type |= DT_ISP2432;
4a59f71d 2620 ha->device_type |= DT_ZIO_SUPPORTED;
e428924c 2621 ha->device_type |= DT_FWI2;
c76f2c01 2622 ha->device_type |= DT_IIDMA;
441d1072 2623 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2624 break;
4d4df193 2625 case PCI_DEVICE_ID_QLOGIC_ISP8432:
9e052e2d 2626 ha->isp_type |= DT_ISP8432;
4d4df193
HK		 2627 ha->device_type |= DT_ZIO_SUPPORTED;
2628 ha->device_type |= DT_FWI2;
2629 ha->device_type |= DT_IIDMA;
2630 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2631 break;
044cc6c8 2632 case PCI_DEVICE_ID_QLOGIC_ISP5422:
9e052e2d 2633 ha->isp_type |= DT_ISP5422;
e428924c 2634 ha->device_type |= DT_FWI2;
441d1072 2635 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2636 break;
044cc6c8 2637 case PCI_DEVICE_ID_QLOGIC_ISP5432:
9e052e2d 2638 ha->isp_type |= DT_ISP5432;
e428924c 2639 ha->device_type |= DT_FWI2;
441d1072 2640 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2641 break;
c3a2f0df 2642 case PCI_DEVICE_ID_QLOGIC_ISP2532:
9e052e2d 2643 ha->isp_type |= DT_ISP2532;
c3a2f0df
AV		 2644 ha->device_type |= DT_ZIO_SUPPORTED;
2645 ha->device_type |= DT_FWI2;
2646 ha->device_type |= DT_IIDMA;
441d1072 2647 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2648 break;
3a03eb79 2649 case PCI_DEVICE_ID_QLOGIC_ISP8001:
9e052e2d 2650 ha->isp_type |= DT_ISP8001;
3a03eb79
AV		 2651 ha->device_type |= DT_ZIO_SUPPORTED;
2652 ha->device_type |= DT_FWI2;
2653 ha->device_type |= DT_IIDMA;
2654 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2655 break;
a9083016 2656 case PCI_DEVICE_ID_QLOGIC_ISP8021:
9e052e2d 2657 ha->isp_type |= DT_ISP8021;
a9083016
GM		 2658 ha->device_type |= DT_ZIO_SUPPORTED;
2659 ha->device_type |= DT_FWI2;
2660 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2661 /* Initialize 82XX ISP flags */
2662 qla82xx_init_flags(ha);
2663 break;
7ec0effd 2664 case PCI_DEVICE_ID_QLOGIC_ISP8044:
9e052e2d 2665 ha->isp_type |= DT_ISP8044;
7ec0effd
AD		 2666 ha->device_type |= DT_ZIO_SUPPORTED;
2667 ha->device_type |= DT_FWI2;
2668 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2669 /* Initialize 82XX ISP flags */
2670 qla82xx_init_flags(ha);
2671 break;
6246b8a1 2672 case PCI_DEVICE_ID_QLOGIC_ISP2031:
9e052e2d 2673 ha->isp_type |= DT_ISP2031;
6246b8a1
GM		 2674 ha->device_type |= DT_ZIO_SUPPORTED;
2675 ha->device_type |= DT_FWI2;
2676 ha->device_type |= DT_IIDMA;
2677 ha->device_type |= DT_T10_PI;
2678 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2679 break;
2680 case PCI_DEVICE_ID_QLOGIC_ISP8031:
9e052e2d 2681 ha->isp_type |= DT_ISP8031;
6246b8a1
GM		 2682 ha->device_type |= DT_ZIO_SUPPORTED;
2683 ha->device_type |= DT_FWI2;
2684 ha->device_type |= DT_IIDMA;
2685 ha->device_type |= DT_T10_PI;
2686 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2687 break;
8ae6d9c7 2688 case PCI_DEVICE_ID_QLOGIC_ISPF001:
9e052e2d 2689 ha->isp_type |= DT_ISPFX00;
8ae6d9c7 2690 break;
f73cb695 2691 case PCI_DEVICE_ID_QLOGIC_ISP2071:
9e052e2d 2692 ha->isp_type |= DT_ISP2071;
f73cb695
CD		 2693 ha->device_type |= DT_ZIO_SUPPORTED;
2694 ha->device_type |= DT_FWI2;
2695 ha->device_type |= DT_IIDMA;
8ce3f570 2696 ha->device_type |= DT_T10_PI;
f73cb695
CD		 2697 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2698 break;
2c5bbbb2 2699 case PCI_DEVICE_ID_QLOGIC_ISP2271:
9e052e2d 2700 ha->isp_type |= DT_ISP2271;
2c5bbbb2
JC		 2701 ha->device_type |= DT_ZIO_SUPPORTED;
2702 ha->device_type |= DT_FWI2;
2703 ha->device_type |= DT_IIDMA;
8ce3f570 2704 ha->device_type |= DT_T10_PI;
2c5bbbb2
JC		 2705 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2706 break;
2b48992f 2707 case PCI_DEVICE_ID_QLOGIC_ISP2261:
9e052e2d 2708 ha->isp_type |= DT_ISP2261;
2b48992f
SC		 2709 ha->device_type |= DT_ZIO_SUPPORTED;
2710 ha->device_type |= DT_FWI2;
2711 ha->device_type |= DT_IIDMA;
8ce3f570 2712 ha->device_type |= DT_T10_PI;
2b48992f
SC		 2713 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2714 break;
ecc89f25
JC		 2715 case PCI_DEVICE_ID_QLOGIC_ISP2081:
2716 case PCI_DEVICE_ID_QLOGIC_ISP2089:
2717 ha->isp_type |= DT_ISP2081;
2718 ha->device_type |= DT_ZIO_SUPPORTED;
2719 ha->device_type |= DT_FWI2;
2720 ha->device_type |= DT_IIDMA;
2721 ha->device_type |= DT_T10_PI;
2722 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2723 break;
2724 case PCI_DEVICE_ID_QLOGIC_ISP2281:
2725 case PCI_DEVICE_ID_QLOGIC_ISP2289:
2726 ha->isp_type |= DT_ISP2281;
2727 ha->device_type |= DT_ZIO_SUPPORTED;
2728 ha->device_type |= DT_FWI2;
2729 ha->device_type |= DT_IIDMA;
2730 ha->device_type |= DT_T10_PI;
2731 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2732 break;
ea5b6382 2733 }
e5b68a61 2734
a9083016 2735 if (IS_QLA82XX(ha))
43a9c38b 2736 ha->port_no = ha->portnum & 1;
f73cb695 2737 else {
a9083016
GM		 2738 /* Get adapter physical port no from interrupt pin register. */
2739 pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no);
ecc89f25
JC		 2740 if (IS_QLA25XX(ha) || IS_QLA2031(ha) ||
2741 IS_QLA27XX(ha) || IS_QLA28XX(ha))
f73cb695
CD		 2742 ha->port_no--;
2743 else
2744 ha->port_no = !(ha->port_no & 1);
2745 }
a9083016 2746
7c3df132 2747 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b,
d8424f68 2748 "device_type=0x%x port=%d fw_srisc_address=0x%x.\n",
f73cb695 2749 ha->device_type, ha->port_no, ha->fw_srisc_address);
ea5b6382 2750}
2751
1e99e33a
AV		 2752static void
2753qla2xxx_scan_start(struct Scsi_Host *shost)
2754{
e315cd28 2755 scsi_qla_host_t *vha = shost_priv(shost);
1e99e33a 2756
cbc8eb67
AV		 2757 if (vha->hw->flags.running_gold_fw)
2758 return;
2759
e315cd28
AC		 2760 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
2761 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
2762 set_bit(RSCN_UPDATE, &vha->dpc_flags);
2763 set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags);
1e99e33a
AV		 2764}
2765
2766static int
2767qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time)
2768{
e315cd28 2769 scsi_qla_host_t *vha = shost_priv(shost);
1e99e33a 2770
a5dd506e
BK		 2771 if (test_bit(UNLOADING, &vha->dpc_flags))
2772 return 1;
e315cd28 2773 if (!vha->host)
1e99e33a 2774 return 1;
e315cd28 2775 if (time > vha->hw->loop_reset_delay * HZ)
1e99e33a
AV		 2776 return 1;
2777
e315cd28 2778 return atomic_read(&vha->loop_state) == LOOP_READY;
1e99e33a
AV		 2779}
2780
ec7193e2
QT		 2781static void qla2x00_iocb_work_fn(struct work_struct *work)
2782{
2783 struct scsi_qla_host *vha = container_of(work,
2784 struct scsi_qla_host, iocb_work);
9b3e0f4d
QT		 2785 struct qla_hw_data *ha = vha->hw;
2786 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
0aca7784 2787 int i = 2;
9b3e0f4d
QT		 2788 unsigned long flags;
2789
2790 if (test_bit(UNLOADING, &base_vha->dpc_flags))
2791 return;
ec7193e2 2792
9b3e0f4d 2793 while (!list_empty(&vha->work_list) && i > 0) {
ec7193e2 2794 qla2x00_do_work(vha);
9b3e0f4d 2795 i--;
ec7193e2 2796 }
9b3e0f4d
QT		 2797
2798 spin_lock_irqsave(&vha->work_lock, flags);
2799 clear_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags);
2800 spin_unlock_irqrestore(&vha->work_lock, flags);
ec7193e2
QT		 2801}
2802
1da177e4
LT		 2803/*
2804 * PCI driver interface
2805 */
6f039790 2806static int
7ee61397 2807qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
1da177e4 2808{
a1541d5a 2809 int ret = -ENODEV;
1da177e4 2810 struct Scsi_Host *host;
e315cd28
AC		 2811 scsi_qla_host_t *base_vha = NULL;
2812 struct qla_hw_data *ha;
29856e28 2813 char pci_info[30];
7d613ac6 2814 char fw_str[30], wq_name[30];
5433383e 2815 struct scsi_host_template *sht;
642ef983 2816 int bars, mem_only = 0;
e315cd28 2817 uint16_t req_length = 0, rsp_length = 0;
73208dfd
AC		 2818 struct req_que *req = NULL;
2819 struct rsp_que *rsp = NULL;
5601236b 2820 int i;
d7459527 2821
285d0321 2822 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO);
a5326f86 2823 sht = &qla2xxx_driver_template;
5433383e 2824 if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 ||
8bc69e7d 2825 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 ||
4d4df193 2826 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 ||
8bc69e7d 2827 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 ||
c3a2f0df 2828 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 ||
3a03eb79 2829 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 ||
a9083016 2830 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 ||
6246b8a1
GM		 2831 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021 ||
2832 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2031 ||
8ae6d9c7 2833 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8031 ||
7ec0effd 2834 pdev->device == PCI_DEVICE_ID_QLOGIC_ISPF001 ||
f73cb695 2835 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8044 ||
2c5bbbb2 2836 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2071 ||
2b48992f 2837 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2271 ||
ecc89f25
JC		 2838 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2261 ||
2839 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2081 ||
2840 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2281 ||
2841 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2089 ||
2842 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2289) {
285d0321 2843 bars = pci_select_bars(pdev, IORESOURCE_MEM);
09483916 2844 mem_only = 1;
7c3df132
SK		 2845 ql_dbg_pci(ql_dbg_init, pdev, 0x0007,
2846 "Mem only adapter.\n");
285d0321 2847 }
7c3df132
SK		 2848 ql_dbg_pci(ql_dbg_init, pdev, 0x0008,
2849 "Bars=%d.\n", bars);
285d0321 2850
09483916
BH		 2851 if (mem_only) {
2852 if (pci_enable_device_mem(pdev))
ddff7ed4 2853 return ret;
09483916
BH		 2854 } else {
2855 if (pci_enable_device(pdev))
ddff7ed4 2856 return ret;
09483916 2857 }
285d0321 2858
0927678f
JB		 2859 /* This may fail but that's ok */
2860 pci_enable_pcie_error_reporting(pdev);
285d0321 2861
5da05a26
GM		 2862 /* Turn off T10-DIF when FC-NVMe is enabled */
2863 if (ql2xnvmeenable)
2864 ql2xenabledif = 0;
2865
e315cd28
AC		 2866 ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL);
2867 if (!ha) {
7c3df132
SK		 2868 ql_log_pci(ql_log_fatal, pdev, 0x0009,
2869 "Unable to allocate memory for ha.\n");
ddff7ed4 2870 goto disable_device;
1da177e4 2871 }
7c3df132
SK		 2872 ql_dbg_pci(ql_dbg_init, pdev, 0x000a,
2873 "Memory allocated for ha=%p.\n", ha);
e315cd28 2874 ha->pdev = pdev;
33e79977
QT		 2875 INIT_LIST_HEAD(&ha->tgt.q_full_list);
2876 spin_lock_init(&ha->tgt.q_full_lock);
7560151b 2877 spin_lock_init(&ha->tgt.sess_lock);
2f424b9b
QT		 2878 spin_lock_init(&ha->tgt.atio_lock);
2879
deeae7a6 2880 atomic_set(&ha->nvme_active_aen_cnt, 0);
1da177e4
LT		 2881
2882 /* Clear our data area */
285d0321 2883 ha->bars = bars;
09483916 2884 ha->mem_only = mem_only;
df4bf0bb 2885 spin_lock_init(&ha->hardware_lock);
339aa70e 2886 spin_lock_init(&ha->vport_slock);
a9b6f722 2887 mutex_init(&ha->selflogin_lock);
7a8ab9c8 2888 mutex_init(&ha->optrom_mutex);
1da177e4 2889
ea5b6382 2890 /* Set ISP-type information. */
2891 qla2x00_set_isp_flags(ha);
ca79cf66
DG		 2892
2893 /* Set EEH reset type to fundamental if required by hba */
95676112 2894 if (IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha) ||
ecc89f25 2895 IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))
ca79cf66 2896 pdev->needs_freset = 1;
ca79cf66 2897
cba1e47f
CD		 2898 ha->prev_topology = 0;
2899 ha->init_cb_size = sizeof(init_cb_t);
2900 ha->link_data_rate = PORT_SPEED_UNKNOWN;
2901 ha->optrom_size = OPTROM_SIZE_2300;
d1e3635a 2902 ha->max_exchg = FW_MAX_EXCHANGES_CNT;
b2000805
QT		 2903 atomic_set(&ha->num_pend_mbx_stage1, 0);
2904 atomic_set(&ha->num_pend_mbx_stage2, 0);
2905 atomic_set(&ha->num_pend_mbx_stage3, 0);
8b4673ba
QT		 2906 atomic_set(&ha->zio_threshold, DEFAULT_ZIO_THRESHOLD);
2907 ha->last_zio_threshold = DEFAULT_ZIO_THRESHOLD;
cba1e47f 2908
abbd8870 2909 /* Assign ISP specific operations. */
1da177e4 2910 if (IS_QLA2100(ha)) {
642ef983 2911 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
1da177e4 2912 ha->mbx_count = MAILBOX_REGISTER_COUNT_2100;
e315cd28
AC		 2913 req_length = REQUEST_ENTRY_CNT_2100;
2914 rsp_length = RESPONSE_ENTRY_CNT_2100;
2915 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
abbd8870 2916 ha->gid_list_info_size = 4;
3a03eb79
AV		 2917 ha->flash_conf_off = ~0;
2918 ha->flash_data_off = ~0;
2919 ha->nvram_conf_off = ~0;
2920 ha->nvram_data_off = ~0;
fd34f556 2921 ha->isp_ops = &qla2100_isp_ops;
1da177e4 2922 } else if (IS_QLA2200(ha)) {
642ef983 2923 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
67ddda35 2924 ha->mbx_count = MAILBOX_REGISTER_COUNT_2200;
e315cd28
AC		 2925 req_length = REQUEST_ENTRY_CNT_2200;
2926 rsp_length = RESPONSE_ENTRY_CNT_2100;
2927 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
abbd8870 2928 ha->gid_list_info_size = 4;
3a03eb79
AV		 2929 ha->flash_conf_off = ~0;
2930 ha->flash_data_off = ~0;
2931 ha->nvram_conf_off = ~0;
2932 ha->nvram_data_off = ~0;
fd34f556 2933 ha->isp_ops = &qla2100_isp_ops;
fca29703 2934 } else if (IS_QLA23XX(ha)) {
642ef983 2935 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
1da177e4 2936 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2937 req_length = REQUEST_ENTRY_CNT_2200;
2938 rsp_length = RESPONSE_ENTRY_CNT_2300;
2939 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
abbd8870 2940 ha->gid_list_info_size = 6;
854165f4 2941 if (IS_QLA2322(ha) || IS_QLA6322(ha))
2942 ha->optrom_size = OPTROM_SIZE_2322;
3a03eb79
AV		 2943 ha->flash_conf_off = ~0;
2944 ha->flash_data_off = ~0;
2945 ha->nvram_conf_off = ~0;
2946 ha->nvram_data_off = ~0;
fd34f556 2947 ha->isp_ops = &qla2300_isp_ops;
4d4df193 2948 } else if (IS_QLA24XX_TYPE(ha)) {
642ef983 2949 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
fca29703 2950 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2951 req_length = REQUEST_ENTRY_CNT_24XX;
2952 rsp_length = RESPONSE_ENTRY_CNT_2300;
2d70c103 2953 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
e315cd28 2954 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2c3dfe3f 2955 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
fca29703 2956 ha->gid_list_info_size = 8;
854165f4 2957 ha->optrom_size = OPTROM_SIZE_24XX;
73208dfd 2958 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX;
fd34f556 2959 ha->isp_ops = &qla24xx_isp_ops;
3a03eb79
AV		 2960 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2961 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2962 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2963 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
c3a2f0df 2964 } else if (IS_QLA25XX(ha)) {
642ef983 2965 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
c3a2f0df 2966 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2967 req_length = REQUEST_ENTRY_CNT_24XX;
2968 rsp_length = RESPONSE_ENTRY_CNT_2300;
2d70c103 2969 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
e315cd28 2970 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
c3a2f0df 2971 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
c3a2f0df
AV		 2972 ha->gid_list_info_size = 8;
2973 ha->optrom_size = OPTROM_SIZE_25XX;
73208dfd 2974 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
c3a2f0df 2975 ha->isp_ops = &qla25xx_isp_ops;
3a03eb79
AV		 2976 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2977 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2978 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2979 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
2980 } else if (IS_QLA81XX(ha)) {
642ef983 2981 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3a03eb79
AV		 2982 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2983 req_length = REQUEST_ENTRY_CNT_24XX;
2984 rsp_length = RESPONSE_ENTRY_CNT_2300;
aa230bc5 2985 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
3a03eb79
AV		 2986 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2987 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2988 ha->gid_list_info_size = 8;
2989 ha->optrom_size = OPTROM_SIZE_81XX;
40859ae5 2990 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3a03eb79
AV		 2991 ha->isp_ops = &qla81xx_isp_ops;
2992 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2993 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2994 ha->nvram_conf_off = ~0;
2995 ha->nvram_data_off = ~0;
a9083016 2996 } else if (IS_QLA82XX(ha)) {
642ef983 2997 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
a9083016
GM		 2998 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2999 req_length = REQUEST_ENTRY_CNT_82XX;
3000 rsp_length = RESPONSE_ENTRY_CNT_82XX;
3001 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
3002 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
3003 ha->gid_list_info_size = 8;
3004 ha->optrom_size = OPTROM_SIZE_82XX;
087c621e 3005 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
a9083016
GM		 3006 ha->isp_ops = &qla82xx_isp_ops;
3007 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
3008 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
3009 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
3010 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
7ec0effd
AD		 3011 } else if (IS_QLA8044(ha)) {
3012 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3013 ha->mbx_count = MAILBOX_REGISTER_COUNT;
3014 req_length = REQUEST_ENTRY_CNT_82XX;
3015 rsp_length = RESPONSE_ENTRY_CNT_82XX;
3016 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
3017 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
3018 ha->gid_list_info_size = 8;
3019 ha->optrom_size = OPTROM_SIZE_83XX;
3020 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3021 ha->isp_ops = &qla8044_isp_ops;
3022 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
3023 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
3024 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
3025 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
6246b8a1 3026 } else if (IS_QLA83XX(ha)) {
7d613ac6 3027 ha->portnum = PCI_FUNC(ha->pdev->devfn);
642ef983 3028 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
6246b8a1 3029 ha->mbx_count = MAILBOX_REGISTER_COUNT;
f2ea653f 3030 req_length = REQUEST_ENTRY_CNT_83XX;
e7b42e33 3031 rsp_length = RESPONSE_ENTRY_CNT_83XX;
b8aa4bdf 3032 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
6246b8a1
GM		 3033 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
3034 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
3035 ha->gid_list_info_size = 8;
3036 ha->optrom_size = OPTROM_SIZE_83XX;
3037 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3038 ha->isp_ops = &qla83xx_isp_ops;
3039 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
3040 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
3041 ha->nvram_conf_off = ~0;
3042 ha->nvram_data_off = ~0;
8ae6d9c7
GM		 3043 } else if (IS_QLAFX00(ha)) {
3044 ha->max_fibre_devices = MAX_FIBRE_DEVICES_FX00;
3045 ha->mbx_count = MAILBOX_REGISTER_COUNT_FX00;
3046 ha->aen_mbx_count = AEN_MAILBOX_REGISTER_COUNT_FX00;
3047 req_length = REQUEST_ENTRY_CNT_FX00;
3048 rsp_length = RESPONSE_ENTRY_CNT_FX00;
8ae6d9c7
GM		 3049 ha->isp_ops = &qlafx00_isp_ops;
3050 ha->port_down_retry_count = 30; /* default value */
3051 ha->mr.fw_hbt_cnt = QLAFX00_HEARTBEAT_INTERVAL;
3052 ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL;
71e56003 3053 ha->mr.fw_critemp_timer_tick = QLAFX00_CRITEMP_INTERVAL;
8ae6d9c7 3054 ha->mr.fw_hbt_en = 1;
e8f5e95d
AB		 3055 ha->mr.host_info_resend = false;
3056 ha->mr.hinfo_resend_timer_tick = QLAFX00_HINFO_RESEND_INTERVAL;
f73cb695
CD		 3057 } else if (IS_QLA27XX(ha)) {
3058 ha->portnum = PCI_FUNC(ha->pdev->devfn);
3059 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3060 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e7b42e33
QT		 3061 req_length = REQUEST_ENTRY_CNT_83XX;
3062 rsp_length = RESPONSE_ENTRY_CNT_83XX;
b20f02e1 3063 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
f73cb695
CD		 3064 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
3065 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
3066 ha->gid_list_info_size = 8;
3067 ha->optrom_size = OPTROM_SIZE_83XX;
3068 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3069 ha->isp_ops = &qla27xx_isp_ops;
3070 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
3071 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
3072 ha->nvram_conf_off = ~0;
3073 ha->nvram_data_off = ~0;
ecc89f25
JC		 3074 } else if (IS_QLA28XX(ha)) {
3075 ha->portnum = PCI_FUNC(ha->pdev->devfn);
3076 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3077 ha->mbx_count = MAILBOX_REGISTER_COUNT;
3078 req_length = REQUEST_ENTRY_CNT_24XX;
3079 rsp_length = RESPONSE_ENTRY_CNT_2300;
3080 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
3081 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
3082 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
3083 ha->gid_list_info_size = 8;
3084 ha->optrom_size = OPTROM_SIZE_28XX;
3085 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3086 ha->isp_ops = &qla27xx_isp_ops;
3087 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_28XX;
3088 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_28XX;
3089 ha->nvram_conf_off = ~0;
3090 ha->nvram_data_off = ~0;
1da177e4 3091 }
6246b8a1 3092
7c3df132
SK		 3093 ql_dbg_pci(ql_dbg_init, pdev, 0x001e,
3094 "mbx_count=%d, req_length=%d, "
3095 "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, "
642ef983
CD		 3096 "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, "
3097 "max_fibre_devices=%d.\n",
7c3df132
SK		 3098 ha->mbx_count, req_length, rsp_length, ha->max_loop_id,
3099 ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size,
642ef983 3100 ha->nvram_npiv_size, ha->max_fibre_devices);
7c3df132
SK		 3101 ql_dbg_pci(ql_dbg_init, pdev, 0x001f,
3102 "isp_ops=%p, flash_conf_off=%d, "
3103 "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n",
3104 ha->isp_ops, ha->flash_conf_off, ha->flash_data_off,
3105 ha->nvram_conf_off, ha->nvram_data_off);
706f457d
GM		 3106
3107 /* Configure PCI I/O space */
3108 ret = ha->isp_ops->iospace_config(ha);
3109 if (ret)
0a63ad12 3110 goto iospace_config_failed;
706f457d
GM		 3111
3112 ql_log_pci(ql_log_info, pdev, 0x001d,
3113 "Found an ISP%04X irq %d iobase 0x%p.\n",
3114 pdev->device, pdev->irq, ha->iobase);
6c2f527c 3115 mutex_init(&ha->vport_lock);
d7459527 3116 mutex_init(&ha->mq_lock);
0b05a1f0
MB		 3117 init_completion(&ha->mbx_cmd_comp);
3118 complete(&ha->mbx_cmd_comp);
3119 init_completion(&ha->mbx_intr_comp);
23f2ebd1 3120 init_completion(&ha->dcbx_comp);
f356bef1 3121 init_completion(&ha->lb_portup_comp);
1da177e4 3122
2c3dfe3f 3123 set_bit(0, (unsigned long *) ha->vp_idx_map);
1da177e4 3124
53303c42 3125 qla2x00_config_dma_addressing(ha);
7c3df132
SK		 3126 ql_dbg_pci(ql_dbg_init, pdev, 0x0020,
3127 "64 Bit addressing is %s.\n",
3128 ha->flags.enable_64bit_addressing ? "enable" :
3129 "disable");
73208dfd 3130 ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp);
b2a72ec3 3131 if (ret) {
7c3df132
SK		 3132 ql_log_pci(ql_log_fatal, pdev, 0x0031,
3133 "Failed to allocate memory for adapter, aborting.\n");
1da177e4 3134
e315cd28
AC		 3135 goto probe_hw_failed;
3136 }
3137
73208dfd 3138 req->max_q_depth = MAX_Q_DEPTH;
e315cd28 3139 if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU)
73208dfd
AC		 3140 req->max_q_depth = ql2xmaxqdepth;
3141
e315cd28
AC		 3142
3143 base_vha = qla2x00_create_host(sht, ha);
3144 if (!base_vha) {
a1541d5a 3145 ret = -ENOMEM;
e315cd28 3146 goto probe_hw_failed;
1da177e4
LT		 3147 }
3148
e315cd28 3149 pci_set_drvdata(pdev, base_vha);
6b383979 3150 set_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags);
e315cd28 3151
e315cd28 3152 host = base_vha->host;
2afa19a9 3153 base_vha->req = req;
73208dfd 3154 if (IS_QLA2XXX_MIDTYPE(ha))
f6602f3b
QT		 3155 base_vha->mgmt_svr_loop_id =
3156 qla2x00_reserve_mgmt_server_loop_id(base_vha);
73208dfd 3157 else
e315cd28
AC		 3158 base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER +
3159 base_vha->vp_idx;
58548cb5 3160
8ae6d9c7
GM		 3161 /* Setup fcport template structure. */
3162 ha->mr.fcport.vha = base_vha;
3163 ha->mr.fcport.port_type = FCT_UNKNOWN;
3164 ha->mr.fcport.loop_id = FC_NO_LOOP_ID;
3165 qla2x00_set_fcport_state(&ha->mr.fcport, FCS_UNCONFIGURED);
3166 ha->mr.fcport.supported_classes = FC_COS_UNSPECIFIED;
3167 ha->mr.fcport.scan_state = 1;
3168
58548cb5
GM		 3169 /* Set the SG table size based on ISP type */
3170 if (!IS_FWI2_CAPABLE(ha)) {
3171 if (IS_QLA2100(ha))
3172 host->sg_tablesize = 32;
3173 } else {
3174 if (!IS_QLA82XX(ha))
3175 host->sg_tablesize = QLA_SG_ALL;
3176 }
642ef983 3177 host->max_id = ha->max_fibre_devices;
e315cd28
AC		 3178 host->cmd_per_lun = 3;
3179 host->unique_id = host->host_no;
e02587d7 3180 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif)
0c470874
AE		 3181 host->max_cmd_len = 32;
3182 else
3183 host->max_cmd_len = MAX_CMDSZ;
e315cd28 3184 host->max_channel = MAX_BUSES - 1;
755f516b
HR		 3185 /* Older HBAs support only 16-bit LUNs */
3186 if (!IS_QLAFX00(ha) && !IS_FWI2_CAPABLE(ha) &&
3187 ql2xmaxlun > 0xffff)
3188 host->max_lun = 0xffff;
3189 else
3190 host->max_lun = ql2xmaxlun;
e315cd28 3191 host->transportt = qla2xxx_transport_template;
9a069e19 3192 sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC);
e315cd28 3193
7c3df132
SK		 3194 ql_dbg(ql_dbg_init, base_vha, 0x0033,
3195 "max_id=%d this_id=%d "
3196 "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d "
1abf635d 3197 "max_lun=%llu transportt=%p, vendor_id=%llu.\n", host->max_id,
7c3df132
SK		 3198 host->this_id, host->cmd_per_lun, host->unique_id,
3199 host->max_cmd_len, host->max_channel, host->max_lun,
3200 host->transportt, sht->vendor_id);
3201
1010f21e
HM		 3202 INIT_WORK(&base_vha->iocb_work, qla2x00_iocb_work_fn);
3203
d7459527
MH		 3204 /* Set up the irqs */
3205 ret = qla2x00_request_irqs(ha, rsp);
3206 if (ret)
6a2cf8d3 3207 goto probe_failed;
d7459527 3208
9a347ff4 3209 /* Alloc arrays of request and response ring ptrs */
6d634067
BK		 3210 ret = qla2x00_alloc_queues(ha, req, rsp);
3211 if (ret) {
9a347ff4
CD		 3212 ql_log(ql_log_fatal, base_vha, 0x003d,
3213 "Failed to allocate memory for queue pointers..."
3214 "aborting.\n");
6a2cf8d3 3215 goto probe_failed;
9a347ff4
CD		 3216 }
3217
f664a3cc 3218 if (ha->mqenable) {
5601236b
MH		 3219 /* number of hardware queues supported by blk/scsi-mq*/
3220 host->nr_hw_queues = ha->max_qpairs;
3221
3222 ql_dbg(ql_dbg_init, base_vha, 0x0192,
3223 "blk/scsi-mq enabled, HW queues = %d.\n", host->nr_hw_queues);
c38d1baf
HM		 3224 } else {
3225 if (ql2xnvmeenable) {
3226 host->nr_hw_queues = ha->max_qpairs;
3227 ql_dbg(ql_dbg_init, base_vha, 0x0194,
3228 "FC-NVMe support is enabled, HW queues=%d\n",
3229 host->nr_hw_queues);
3230 } else {
3231 ql_dbg(ql_dbg_init, base_vha, 0x0193,
3232 "blk/scsi-mq disabled.\n");
3233 }
3234 }
5601236b 3235
2d70c103 3236 qlt_probe_one_stage1(base_vha, ha);
9a347ff4 3237
90a86fc0
JC		 3238 pci_save_state(pdev);
3239
9a347ff4 3240 /* Assign back pointers */
2afa19a9
AC		 3241 rsp->req = req;
3242 req->rsp = rsp;
9a347ff4 3243
8ae6d9c7
GM		 3244 if (IS_QLAFX00(ha)) {
3245 ha->rsp_q_map[0] = rsp;
3246 ha->req_q_map[0] = req;
3247 set_bit(0, ha->req_qid_map);
3248 set_bit(0, ha->rsp_qid_map);
3249 }
3250
08029990
AV		 3251 /* FWI2-capable only. */
3252 req->req_q_in = &ha->iobase->isp24.req_q_in;
3253 req->req_q_out = &ha->iobase->isp24.req_q_out;
3254 rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in;
3255 rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out;
ecc89f25
JC		 3256 if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha) ||
3257 IS_QLA28XX(ha)) {
08029990
AV		 3258 req->req_q_in = &ha->mqiobase->isp25mq.req_q_in;
3259 req->req_q_out = &ha->mqiobase->isp25mq.req_q_out;
3260 rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in;
3261 rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out;
17d98630
AC		 3262 }
3263
8ae6d9c7
GM		 3264 if (IS_QLAFX00(ha)) {
3265 req->req_q_in = &ha->iobase->ispfx00.req_q_in;
3266 req->req_q_out = &ha->iobase->ispfx00.req_q_out;
3267 rsp->rsp_q_in = &ha->iobase->ispfx00.rsp_q_in;
3268 rsp->rsp_q_out = &ha->iobase->ispfx00.rsp_q_out;
3269 }
3270
7ec0effd 3271 if (IS_P3P_TYPE(ha)) {
a9083016
GM		 3272 req->req_q_out = &ha->iobase->isp82.req_q_out[0];
3273 rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0];
3274 rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0];
3275 }
3276
7c3df132
SK		 3277 ql_dbg(ql_dbg_multiq, base_vha, 0xc009,
3278 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
3279 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
3280 ql_dbg(ql_dbg_multiq, base_vha, 0xc00a,
3281 "req->req_q_in=%p req->req_q_out=%p "
3282 "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
3283 req->req_q_in, req->req_q_out,
3284 rsp->rsp_q_in, rsp->rsp_q_out);
3285 ql_dbg(ql_dbg_init, base_vha, 0x003e,
3286 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
3287 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
3288 ql_dbg(ql_dbg_init, base_vha, 0x003f,
3289 "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
3290 req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out);
1da177e4 3291
d48cc67c 3292 ha->wq = alloc_workqueue("qla2xxx_wq", 0, 0);
3293
8ae6d9c7 3294 if (ha->isp_ops->initialize_adapter(base_vha)) {
7c3df132
SK		 3295 ql_log(ql_log_fatal, base_vha, 0x00d6,
3296 "Failed to initialize adapter - Adapter flags %x.\n",
3297 base_vha->device_flags);
1da177e4 3298
a9083016
GM		 3299 if (IS_QLA82XX(ha)) {
3300 qla82xx_idc_lock(ha);
3301 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 3302 QLA8XXX_DEV_FAILED);
a9083016 3303 qla82xx_idc_unlock(ha);
7c3df132
SK		 3304 ql_log(ql_log_fatal, base_vha, 0x00d7,
3305 "HW State: FAILED.\n");
7ec0effd
AD		 3306 } else if (IS_QLA8044(ha)) {
3307 qla8044_idc_lock(ha);
3308 qla8044_wr_direct(base_vha,
3309 QLA8044_CRB_DEV_STATE_INDEX,
3310 QLA8XXX_DEV_FAILED);
3311 qla8044_idc_unlock(ha);
3312 ql_log(ql_log_fatal, base_vha, 0x0150,
3313 "HW State: FAILED.\n");
a9083016
GM		 3314 }
3315
a1541d5a 3316 ret = -ENODEV;
1da177e4
LT		 3317 goto probe_failed;
3318 }
3319
3b1bef64
CD		 3320 if (IS_QLAFX00(ha))
3321 host->can_queue = QLAFX00_MAX_CANQUEUE;
3322 else
3323 host->can_queue = req->num_outstanding_cmds - 10;
3324
3325 ql_dbg(ql_dbg_init, base_vha, 0x0032,
3326 "can_queue=%d, req=%p, mgmt_svr_loop_id=%d, sg_tablesize=%d.\n",
3327 host->can_queue, base_vha->req,
3328 base_vha->mgmt_svr_loop_id, host->sg_tablesize);
3329
e326d22a 3330 if (ha->mqenable) {
e326d22a 3331 bool startit = false;
e326d22a 3332
f664a3cc 3333 if (QLA_TGT_MODE_ENABLED())
e326d22a 3334 startit = false;
e326d22a 3335
f664a3cc 3336 if (ql2x_ini_mode == QLA2XXX_INI_MODE_ENABLED)
e326d22a 3337 startit = true;
e326d22a 3338
f664a3cc
JA		 3339 /* Create start of day qpairs for Block MQ */
3340 for (i = 0; i < ha->max_qpairs; i++)
3341 qla2xxx_create_qpair(base_vha, 5, 0, startit);
5601236b 3342 }
68ca949c 3343
cbc8eb67
AV		 3344 if (ha->flags.running_gold_fw)
3345 goto skip_dpc;
3346
1da177e4
LT		 3347 /*
3348 * Startup the kernel thread for this host adapter
3349 */
39a11240 3350 ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha,
7c3df132 3351 "%s_dpc", base_vha->host_str);
39a11240 3352 if (IS_ERR(ha->dpc_thread)) {
7c3df132
SK		 3353 ql_log(ql_log_fatal, base_vha, 0x00ed,
3354 "Failed to start DPC thread.\n");
39a11240 3355 ret = PTR_ERR(ha->dpc_thread);
e2532b4a 3356 ha->dpc_thread = NULL;
1da177e4
LT		 3357 goto probe_failed;
3358 }
7c3df132
SK		 3359 ql_dbg(ql_dbg_init, base_vha, 0x00ee,
3360 "DPC thread started successfully.\n");
1da177e4 3361
2d70c103
NB		 3362 /*
3363 * If we're not coming up in initiator mode, we might sit for
3364 * a while without waking up the dpc thread, which leads to a
3365 * stuck process warning. So just kick the dpc once here and
3366 * let the kthread start (and go back to sleep in qla2x00_do_dpc).
3367 */
3368 qla2xxx_wake_dpc(base_vha);
3369
f3ddac19
CD		 3370 INIT_WORK(&ha->board_disable, qla2x00_disable_board_on_pci_error);
3371
81178772
SK		 3372 if (IS_QLA8031(ha) || IS_MCTP_CAPABLE(ha)) {
3373 sprintf(wq_name, "qla2xxx_%lu_dpc_lp_wq", base_vha->host_no);
3374 ha->dpc_lp_wq = create_singlethread_workqueue(wq_name);
3375 INIT_WORK(&ha->idc_aen, qla83xx_service_idc_aen);
3376
3377 sprintf(wq_name, "qla2xxx_%lu_dpc_hp_wq", base_vha->host_no);
3378 ha->dpc_hp_wq = create_singlethread_workqueue(wq_name);
3379 INIT_WORK(&ha->nic_core_reset, qla83xx_nic_core_reset_work);
3380 INIT_WORK(&ha->idc_state_handler,
3381 qla83xx_idc_state_handler_work);
3382 INIT_WORK(&ha->nic_core_unrecoverable,
3383 qla83xx_nic_core_unrecoverable_work);
3384 }
3385
cbc8eb67 3386skip_dpc:
e315cd28
AC		 3387 list_add_tail(&base_vha->list, &ha->vp_list);
3388 base_vha->host->irq = ha->pdev->irq;
1da177e4
LT		 3389
3390 /* Initialized the timer */
8e5f4ba0 3391 qla2x00_start_timer(base_vha, WATCH_INTERVAL);
7c3df132
SK		 3392 ql_dbg(ql_dbg_init, base_vha, 0x00ef,
3393 "Started qla2x00_timer with "
3394 "interval=%d.\n", WATCH_INTERVAL);
3395 ql_dbg(ql_dbg_init, base_vha, 0x00f0,
3396 "Detected hba at address=%p.\n",
3397 ha);
d19044c3 3398
e02587d7 3399 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) {
bad75002 3400 if (ha->fw_attributes & BIT_4) {
9e522cd8 3401 int prot = 0, guard;
bd432bb5 3402
bad75002 3403 base_vha->flags.difdix_supported = 1;
7c3df132
SK		 3404 ql_dbg(ql_dbg_init, base_vha, 0x00f1,
3405 "Registering for DIF/DIX type 1 and 3 protection.\n");
8cb2049c
AE		 3406 if (ql2xenabledif == 1)
3407 prot = SHOST_DIX_TYPE0_PROTECTION;
7855d2ba
MP		 3408 if (ql2xprotmask)
3409 scsi_host_set_prot(host, ql2xprotmask);
3410 else
3411 scsi_host_set_prot(host,
3412 prot | SHOST_DIF_TYPE1_PROTECTION
3413 | SHOST_DIF_TYPE2_PROTECTION
3414 | SHOST_DIF_TYPE3_PROTECTION
3415 | SHOST_DIX_TYPE1_PROTECTION
3416 | SHOST_DIX_TYPE2_PROTECTION
3417 | SHOST_DIX_TYPE3_PROTECTION);
9e522cd8
AE		 3418
3419 guard = SHOST_DIX_GUARD_CRC;
3420
3421 if (IS_PI_IPGUARD_CAPABLE(ha) &&
3422 (ql2xenabledif > 1 || IS_PI_DIFB_DIX0_CAPABLE(ha)))
3423 guard |= SHOST_DIX_GUARD_IP;
3424
7855d2ba
MP		 3425 if (ql2xprotguard)
3426 scsi_host_set_guard(host, ql2xprotguard);
3427 else
3428 scsi_host_set_guard(host, guard);
bad75002
AE		 3429 } else
3430 base_vha->flags.difdix_supported = 0;
3431 }
3432
a9083016
GM		 3433 ha->isp_ops->enable_intrs(ha);
3434
1fe19ee4
AB		 3435 if (IS_QLAFX00(ha)) {
3436 ret = qlafx00_fx_disc(base_vha,
3437 &base_vha->hw->mr.fcport, FXDISC_GET_CONFIG_INFO);
3438 host->sg_tablesize = (ha->mr.extended_io_enabled) ?
3439 QLA_SG_ALL : 128;
3440 }
3441
a1541d5a
AV		 3442 ret = scsi_add_host(host, &pdev->dev);
3443 if (ret)
3444 goto probe_failed;
3445
1486400f
MR		 3446 base_vha->flags.init_done = 1;
3447 base_vha->flags.online = 1;
edaa5c74 3448 ha->prev_minidump_failed = 0;
1486400f 3449
7c3df132
SK		 3450 ql_dbg(ql_dbg_init, base_vha, 0x00f2,
3451 "Init done and hba is online.\n");
3452
726b8548
QT		 3453 if (qla_ini_mode_enabled(base_vha) ||
3454 qla_dual_mode_enabled(base_vha))
2d70c103
NB		 3455 scsi_scan_host(host);
3456 else
3457 ql_dbg(ql_dbg_init, base_vha, 0x0122,
3458 "skipping scsi_scan_host() for non-initiator port\n");
1e99e33a 3459
e315cd28 3460 qla2x00_alloc_sysfs_attr(base_vha);
a1541d5a 3461
8ae6d9c7 3462 if (IS_QLAFX00(ha)) {
8ae6d9c7
GM		 3463 ret = qlafx00_fx_disc(base_vha,
3464 &base_vha->hw->mr.fcport, FXDISC_GET_PORT_INFO);
3465
3466 /* Register system information */
3467 ret = qlafx00_fx_disc(base_vha,
3468 &base_vha->hw->mr.fcport, FXDISC_REG_HOST_INFO);
3469 }
3470
e315cd28 3471 qla2x00_init_host_attr(base_vha);
a1541d5a 3472
e315cd28 3473 qla2x00_dfs_setup(base_vha);
df613b96 3474
03eb912a
AB		 3475 ql_log(ql_log_info, base_vha, 0x00fb,
3476 "QLogic %s - %s.\n", ha->model_number, ha->model_desc);
7c3df132
SK		 3477 ql_log(ql_log_info, base_vha, 0x00fc,
3478 "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n",
3479 pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info),
3480 pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-',
3481 base_vha->host_no,
df57caba 3482 ha->isp_ops->fw_version_str(base_vha, fw_str, sizeof(fw_str)));
1da177e4 3483
2d70c103
NB		 3484 qlt_add_target(ha, base_vha);
3485
6b383979 3486 clear_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags);
a29b3dd7
JC		 3487
3488 if (test_bit(UNLOADING, &base_vha->dpc_flags))
3489 return -ENODEV;
3490
e4e3a2ce
QT		 3491 if (ha->flags.detected_lr_sfp) {
3492 ql_log(ql_log_info, base_vha, 0xffff,
3493 "Reset chip to pick up LR SFP setting\n");
3494 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
3495 qla2xxx_wake_dpc(base_vha);
3496 }
3497
1da177e4
LT		 3498 return 0;
3499
3500probe_failed:
b9978769
AV		 3501 if (base_vha->timer_active)
3502 qla2x00_stop_timer(base_vha);
3503 base_vha->flags.online = 0;
3504 if (ha->dpc_thread) {
3505 struct task_struct *t = ha->dpc_thread;
3506
3507 ha->dpc_thread = NULL;
3508 kthread_stop(t);
3509 }
3510
e315cd28 3511 qla2x00_free_device(base_vha);
e315cd28 3512 scsi_host_put(base_vha->host);
6d634067
BK		 3513 /*
3514 * Need to NULL out local req/rsp after
3515 * qla2x00_free_device => qla2x00_free_queues frees
3516 * what these are pointing to. Or else we'll
3517 * fall over below in qla2x00_free_req/rsp_que.
3518 */
3519 req = NULL;
3520 rsp = NULL;
1da177e4 3521
e315cd28 3522probe_hw_failed:
d64d6c56 3523 qla2x00_mem_free(ha);
3524 qla2x00_free_req_que(ha, req);
3525 qla2x00_free_rsp_que(ha, rsp);
1a2fbf18
JL		 3526 qla2x00_clear_drv_active(ha);
3527
0a63ad12 3528iospace_config_failed:
7ec0effd 3529 if (IS_P3P_TYPE(ha)) {
0a63ad12 3530 if (!ha->nx_pcibase)
f73cb695 3531 iounmap((device_reg_t *)ha->nx_pcibase);
a9083016 3532 if (!ql2xdbwr)
f73cb695 3533 iounmap((device_reg_t *)ha->nxdb_wr_ptr);
a9083016
GM		 3534 } else {
3535 if (ha->iobase)
3536 iounmap(ha->iobase);
8ae6d9c7
GM		 3537 if (ha->cregbase)
3538 iounmap(ha->cregbase);
a9083016 3539 }
e315cd28
AC		 3540 pci_release_selected_regions(ha->pdev, ha->bars);
3541 kfree(ha);
1da177e4 3542
ddff7ed4 3543disable_device:
e315cd28 3544 pci_disable_device(pdev);
a1541d5a 3545 return ret;
1da177e4 3546}
1da177e4 3547
e30d1756
MI		 3548static void
3549qla2x00_shutdown(struct pci_dev *pdev)
3550{
3551 scsi_qla_host_t *vha;
3552 struct qla_hw_data *ha;
3553
3554 vha = pci_get_drvdata(pdev);
3555 ha = vha->hw;
3556
efdb5760
SC		 3557 ql_log(ql_log_info, vha, 0xfffa,
3558 "Adapter shutdown\n");
3559
3560 /*
3561 * Prevent future board_disable and wait
3562 * until any pending board_disable has completed.
3563 */
3564 set_bit(PFLG_DRIVER_REMOVING, &vha->pci_flags);
3565 cancel_work_sync(&ha->board_disable);
3566
3567 if (!atomic_read(&pdev->enable_cnt))
3568 return;
3569
42479343
AB		 3570 /* Notify ISPFX00 firmware */
3571 if (IS_QLAFX00(ha))
3572 qlafx00_driver_shutdown(vha, 20);
3573
e30d1756
MI		 3574 /* Turn-off FCE trace */
3575 if (ha->flags.fce_enabled) {
3576 qla2x00_disable_fce_trace(vha, NULL, NULL);
3577 ha->flags.fce_enabled = 0;
3578 }
3579
3580 /* Turn-off EFT trace */
3581 if (ha->eft)
3582 qla2x00_disable_eft_trace(vha);
3583
ecc89f25
JC		 3584 if (IS_QLA25XX(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) ||
3585 IS_QLA28XX(ha)) {
3407fc37
QT		 3586 if (ha->flags.fw_started)
3587 qla2x00_abort_isp_cleanup(vha);
3588 } else {
3589 /* Stop currently executing firmware. */
3590 qla2x00_try_to_stop_firmware(vha);
3591 }
e30d1756
MI		 3592
3593 /* Turn adapter off line */
3594 vha->flags.online = 0;
3595
3596 /* turn-off interrupts on the card */
3597 if (ha->interrupts_on) {
3598 vha->flags.init_done = 0;
3599 ha->isp_ops->disable_intrs(ha);
3600 }
3601
3602 qla2x00_free_irqs(vha);
3603
3604 qla2x00_free_fw_dump(ha);
61d41f61 3605
61d41f61 3606 pci_disable_device(pdev);
efdb5760
SC		 3607 ql_log(ql_log_info, vha, 0xfffe,
3608 "Adapter shutdown successfully.\n");
e30d1756
MI		 3609}
3610
fe1b806f 3611/* Deletes all the virtual ports for a given ha */
4c993f76 3612static void
fe1b806f 3613qla2x00_delete_all_vps(struct qla_hw_data *ha, scsi_qla_host_t *base_vha)
1da177e4 3614{
fe1b806f 3615 scsi_qla_host_t *vha;
feafb7b1 3616 unsigned long flags;
e315cd28 3617
43ebf16d
AE		 3618 mutex_lock(&ha->vport_lock);
3619 while (ha->cur_vport_count) {
43ebf16d 3620 spin_lock_irqsave(&ha->vport_slock, flags);
feafb7b1 3621
43ebf16d
AE		 3622 BUG_ON(base_vha->list.next == &ha->vp_list);
3623 /* This assumes first entry in ha->vp_list is always base vha */
3624 vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list);
52c82823 3625 scsi_host_get(vha->host);
feafb7b1 3626
43ebf16d
AE		 3627 spin_unlock_irqrestore(&ha->vport_slock, flags);
3628 mutex_unlock(&ha->vport_lock);
3629
5e6803b4
HM		 3630 qla_nvme_delete(vha);
3631
43ebf16d
AE		 3632 fc_vport_terminate(vha->fc_vport);
3633 scsi_host_put(vha->host);
feafb7b1 3634
43ebf16d 3635 mutex_lock(&ha->vport_lock);
e315cd28 3636 }
43ebf16d 3637 mutex_unlock(&ha->vport_lock);
fe1b806f 3638}
1da177e4 3639
fe1b806f
CD		 3640/* Stops all deferred work threads */
3641static void
3642qla2x00_destroy_deferred_work(struct qla_hw_data *ha)
3643{
7d613ac6
SV		 3644 /* Cancel all work and destroy DPC workqueues */
3645 if (ha->dpc_lp_wq) {
3646 cancel_work_sync(&ha->idc_aen);
3647 destroy_workqueue(ha->dpc_lp_wq);
3648 ha->dpc_lp_wq = NULL;
3649 }
3650
3651 if (ha->dpc_hp_wq) {
3652 cancel_work_sync(&ha->nic_core_reset);
3653 cancel_work_sync(&ha->idc_state_handler);
3654 cancel_work_sync(&ha->nic_core_unrecoverable);
3655 destroy_workqueue(ha->dpc_hp_wq);
3656 ha->dpc_hp_wq = NULL;
3657 }
3658
b9978769
AV		 3659 /* Kill the kernel thread for this host */
3660 if (ha->dpc_thread) {
3661 struct task_struct *t = ha->dpc_thread;
3662
3663 /*
3664 * qla2xxx_wake_dpc checks for ->dpc_thread
3665 * so we need to zero it out.
3666 */
3667 ha->dpc_thread = NULL;
3668 kthread_stop(t);
3669 }
fe1b806f 3670}
1da177e4 3671
fe1b806f
CD		 3672static void
3673qla2x00_unmap_iobases(struct qla_hw_data *ha)
3674{
a9083016 3675 if (IS_QLA82XX(ha)) {
b963752f 3676
f73cb695 3677 iounmap((device_reg_t *)ha->nx_pcibase);
a9083016 3678 if (!ql2xdbwr)
f73cb695 3679 iounmap((device_reg_t *)ha->nxdb_wr_ptr);
a9083016
GM		 3680 } else {
3681 if (ha->iobase)
3682 iounmap(ha->iobase);
1da177e4 3683
8ae6d9c7
GM		 3684 if (ha->cregbase)
3685 iounmap(ha->cregbase);
3686
a9083016
GM		 3687 if (ha->mqiobase)
3688 iounmap(ha->mqiobase);
6246b8a1 3689
ecc89f25
JC		 3690 if ((IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) &&
3691 ha->msixbase)
6246b8a1 3692 iounmap(ha->msixbase);
a9083016 3693 }
fe1b806f
CD		 3694}
3695
3696static void
db7157d4 3697qla2x00_clear_drv_active(struct qla_hw_data *ha)
fe1b806f 3698{
fe1b806f
CD		 3699 if (IS_QLA8044(ha)) {
3700 qla8044_idc_lock(ha);
c41afc9a 3701 qla8044_clear_drv_active(ha);
fe1b806f
CD		 3702 qla8044_idc_unlock(ha);
3703 } else if (IS_QLA82XX(ha)) {
3704 qla82xx_idc_lock(ha);
3705 qla82xx_clear_drv_active(ha);
3706 qla82xx_idc_unlock(ha);
3707 }
3708}
3709
3710static void
3711qla2x00_remove_one(struct pci_dev *pdev)
3712{
3713 scsi_qla_host_t *base_vha;
3714 struct qla_hw_data *ha;
3715
beb9e315
JL		 3716 base_vha = pci_get_drvdata(pdev);
3717 ha = base_vha->hw;
45235022
QT		 3718 ql_log(ql_log_info, base_vha, 0xb079,
3719 "Removing driver\n");
beb9e315
JL		 3720
3721 /* Indicate device removal to prevent future board_disable and wait
3722 * until any pending board_disable has completed. */
3723 set_bit(PFLG_DRIVER_REMOVING, &base_vha->pci_flags);
3724 cancel_work_sync(&ha->board_disable);
3725
fe1b806f 3726 /*
beb9e315
JL		 3727 * If the PCI device is disabled then there was a PCI-disconnect and
3728 * qla2x00_disable_board_on_pci_error has taken care of most of the
3729 * resources.
fe1b806f 3730 */
beb9e315 3731 if (!atomic_read(&pdev->enable_cnt)) {
726b8548
QT		 3732 dma_free_coherent(&ha->pdev->dev, base_vha->gnl.size,
3733 base_vha->gnl.l, base_vha->gnl.ldma);
3734
beb9e315
JL		 3735 scsi_host_put(base_vha->host);
3736 kfree(ha);
3737 pci_set_drvdata(pdev, NULL);
fe1b806f 3738 return;
beb9e315 3739 }
638a1a01
SC		 3740 qla2x00_wait_for_hba_ready(base_vha);
3741
ecc89f25
JC		 3742 if (IS_QLA25XX(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) ||
3743 IS_QLA28XX(ha)) {
45235022
QT		 3744 if (ha->flags.fw_started)
3745 qla2x00_abort_isp_cleanup(base_vha);
3746 } else if (!IS_QLAFX00(ha)) {
3747 if (IS_QLA8031(ha)) {
3748 ql_dbg(ql_dbg_p3p, base_vha, 0xb07e,
3749 "Clearing fcoe driver presence.\n");
3750 if (qla83xx_clear_drv_presence(base_vha) != QLA_SUCCESS)
3751 ql_dbg(ql_dbg_p3p, base_vha, 0xb079,
3752 "Error while clearing DRV-Presence.\n");
3753 }
3754
3755 qla2x00_try_to_stop_firmware(base_vha);
3756 }
3757
2ce87cc5
QT		 3758 qla2x00_wait_for_sess_deletion(base_vha);
3759
726b8548
QT		 3760 /*
3761 * if UNLOAD flag is already set, then continue unload,
783e0dc4
SC		 3762 * where it was set first.
3763 */
3764 if (test_bit(UNLOADING, &base_vha->dpc_flags))
3765 return;
3766
fe1b806f 3767 set_bit(UNLOADING, &base_vha->dpc_flags);
e84067d7
DG		 3768
3769 qla_nvme_delete(base_vha);
3770
726b8548
QT		 3771 dma_free_coherent(&ha->pdev->dev,
3772 base_vha->gnl.size, base_vha->gnl.l, base_vha->gnl.ldma);
fe1b806f 3773
a4239945
QT		 3774 vfree(base_vha->scan.l);
3775
fe1b806f
CD		 3776 if (IS_QLAFX00(ha))
3777 qlafx00_driver_shutdown(base_vha, 20);
3778
3779 qla2x00_delete_all_vps(ha, base_vha);
3780
fe1b806f
CD		 3781 qla2x00_dfs_remove(base_vha);
3782
3783 qla84xx_put_chip(base_vha);
3784
3785 /* Disable timer */
3786 if (base_vha->timer_active)
3787 qla2x00_stop_timer(base_vha);
3788
3789 base_vha->flags.online = 0;
3790
b0d6cabd
HM		 3791 /* free DMA memory */
3792 if (ha->exlogin_buf)
3793 qla2x00_free_exlogin_buffer(ha);
3794
2f56a7f1
HM		 3795 /* free DMA memory */
3796 if (ha->exchoffld_buf)
3797 qla2x00_free_exchoffld_buffer(ha);
3798
fe1b806f
CD		 3799 qla2x00_destroy_deferred_work(ha);
3800
3801 qlt_remove_target(ha, base_vha);
3802
3803 qla2x00_free_sysfs_attr(base_vha, true);
3804
3805 fc_remove_host(base_vha->host);
482c9dc7 3806 qlt_remove_target_resources(ha);
fe1b806f
CD		 3807
3808 scsi_remove_host(base_vha->host);
3809
3810 qla2x00_free_device(base_vha);
3811
db7157d4 3812 qla2x00_clear_drv_active(ha);
fe1b806f 3813
d2749ffa
AE		 3814 scsi_host_put(base_vha->host);
3815
fe1b806f 3816 qla2x00_unmap_iobases(ha);
73208dfd 3817
e315cd28
AC		 3818 pci_release_selected_regions(ha->pdev, ha->bars);
3819 kfree(ha);
1da177e4 3820
90a86fc0
JC		 3821 pci_disable_pcie_error_reporting(pdev);
3822
665db93b 3823 pci_disable_device(pdev);
1da177e4 3824}
1da177e4
LT		 3825
3826static void
e315cd28 3827qla2x00_free_device(scsi_qla_host_t *vha)
1da177e4 3828{
e315cd28 3829 struct qla_hw_data *ha = vha->hw;
1da177e4 3830
85880801
AV		 3831 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
3832
3833 /* Disable timer */
3834 if (vha->timer_active)
3835 qla2x00_stop_timer(vha);
3836
2afa19a9 3837 qla25xx_delete_queues(vha);
85880801
AV		 3838 vha->flags.online = 0;
3839
f6ef3b18 3840 /* turn-off interrupts on the card */
a9083016
GM		 3841 if (ha->interrupts_on) {
3842 vha->flags.init_done = 0;
fd34f556 3843 ha->isp_ops->disable_intrs(ha);
a9083016 3844 }
f6ef3b18 3845
093df737
QT		 3846 qla2x00_free_fcports(vha);
3847
e315cd28 3848 qla2x00_free_irqs(vha);
1da177e4 3849
093df737
QT		 3850 /* Flush the work queue and remove it */
3851 if (ha->wq) {
3852 flush_workqueue(ha->wq);
3853 destroy_workqueue(ha->wq);
3854 ha->wq = NULL;
3855 }
3856
8867048b 3857
e315cd28 3858 qla2x00_mem_free(ha);
73208dfd 3859
08de2844
GM		 3860 qla82xx_md_free(vha);
3861
73208dfd 3862 qla2x00_free_queues(ha);
1da177e4
LT		 3863}
3864
8867048b
CD		 3865void qla2x00_free_fcports(struct scsi_qla_host *vha)
3866{
3867 fc_port_t *fcport, *tfcport;
3868
ffbc6476
QT		 3869 list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list)
3870 qla2x00_free_fcport(fcport);
8867048b
CD		 3871}
3872
d97994dc 3873static inline void
e315cd28 3874qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport,
d97994dc 3875 int defer)
3876{
d97994dc 3877 struct fc_rport *rport;
67becc00 3878 scsi_qla_host_t *base_vha;
044d78e1 3879 unsigned long flags;
d97994dc 3880
3881 if (!fcport->rport)
3882 return;
3883
3884 rport = fcport->rport;
3885 if (defer) {
67becc00 3886 base_vha = pci_get_drvdata(vha->hw->pdev);
044d78e1 3887 spin_lock_irqsave(vha->host->host_lock, flags);
d97994dc 3888 fcport->drport = rport;
044d78e1 3889 spin_unlock_irqrestore(vha->host->host_lock, flags);
df673274 3890 qlt_do_generation_tick(vha, &base_vha->total_fcport_update_gen);
67becc00
AV		 3891 set_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags);
3892 qla2xxx_wake_dpc(base_vha);
2d70c103 3893 } else {
df673274 3894 int now;
bd432bb5 3895
726b8548 3896 if (rport) {
83548fe2
QT		 3897 ql_dbg(ql_dbg_disc, fcport->vha, 0x2109,
3898 "%s %8phN. rport %p roles %x\n",
3899 __func__, fcport->port_name, rport,
3900 rport->roles);
d20ed91b 3901 fc_remote_port_delete(rport);
726b8548 3902 }
df673274 3903 qlt_do_generation_tick(vha, &now);
2d70c103 3904 }
d97994dc 3905}
3906
1da177e4
LT		 3907/*
3908 * qla2x00_mark_device_lost Updates fcport state when device goes offline.
3909 *
3910 * Input: ha = adapter block pointer. fcport = port structure pointer.
3911 *
3912 * Return: None.
3913 *
3914 * Context:
3915 */
e315cd28 3916void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport,
d97994dc 3917 int do_login, int defer)
1da177e4 3918{
8ae6d9c7
GM		 3919 if (IS_QLAFX00(vha->hw)) {
3920 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
3921 qla2x00_schedule_rport_del(vha, fcport, defer);
3922 return;
3923 }
3924
2c3dfe3f 3925 if (atomic_read(&fcport->state) == FCS_ONLINE &&
c6d39e23 3926 vha->vp_idx == fcport->vha->vp_idx) {
ec426e10 3927 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
e315cd28
AC		 3928 qla2x00_schedule_rport_del(vha, fcport, defer);
3929 }
fa2a1ce5 3930 /*
1da177e4
LT		 3931 * We may need to retry the login, so don't change the state of the
3932 * port but do the retries.
3933 */
3934 if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD)
ec426e10 3935 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
1da177e4
LT		 3936
3937 if (!do_login)
3938 return;
3939
a1d0285e 3940 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
1da177e4
LT		 3941}
3942
3943/*
3944 * qla2x00_mark_all_devices_lost
3945 * Updates fcport state when device goes offline.
3946 *
3947 * Input:
3948 * ha = adapter block pointer.
3949 * fcport = port structure pointer.
3950 *
3951 * Return:
3952 * None.
3953 *
3954 * Context:
3955 */
3956void
e315cd28 3957qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha, int defer)
1da177e4
LT		 3958{
3959 fc_port_t *fcport;
3960
83548fe2
QT		 3961 ql_dbg(ql_dbg_disc, vha, 0x20f1,
3962 "Mark all dev lost\n");
726b8548 3963
e315cd28 3964 list_for_each_entry(fcport, &vha->vp_fcports, list) {
726b8548 3965 fcport->scan_state = 0;
d8630bb9 3966 qlt_schedule_sess_for_deletion(fcport);
726b8548 3967
c6d39e23 3968 if (vha->vp_idx != 0 && vha->vp_idx != fcport->vha->vp_idx)
1da177e4 3969 continue;
0d6e61bc 3970
1da177e4
LT		 3971 /*
3972 * No point in marking the device as lost, if the device is
3973 * already DEAD.
3974 */
3975 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD)
3976 continue;
e315cd28 3977 if (atomic_read(&fcport->state) == FCS_ONLINE) {
ec426e10 3978 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
0d6e61bc
AV		 3979 if (defer)
3980 qla2x00_schedule_rport_del(vha, fcport, defer);
c6d39e23 3981 else if (vha->vp_idx == fcport->vha->vp_idx)
0d6e61bc
AV		 3982 qla2x00_schedule_rport_del(vha, fcport, defer);
3983 }
1da177e4
LT		 3984 }
3985}
3986
3987/*
3988* qla2x00_mem_alloc
3989* Allocates adapter memory.
3990*
3991* Returns:
3992* 0 = success.
e8711085 3993* !0 = failure.
1da177e4 3994*/
e8711085 3995static int
73208dfd
AC		 3996qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len,
3997 struct req_que **req, struct rsp_que **rsp)
1da177e4
LT		 3998{
3999 char name[16];
1da177e4 4000
e8711085 4001 ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size,
e315cd28 4002 &ha->init_cb_dma, GFP_KERNEL);
e8711085 4003 if (!ha->init_cb)
e315cd28 4004 goto fail;
e8711085 4005
2d70c103
NB		 4006 if (qlt_mem_alloc(ha) < 0)
4007 goto fail_free_init_cb;
4008
642ef983
CD		 4009 ha->gid_list = dma_alloc_coherent(&ha->pdev->dev,
4010 qla2x00_gid_list_size(ha), &ha->gid_list_dma, GFP_KERNEL);
e315cd28 4011 if (!ha->gid_list)
2d70c103 4012 goto fail_free_tgt_mem;
1da177e4 4013
e8711085
AV		 4014 ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep);
4015 if (!ha->srb_mempool)
e315cd28 4016 goto fail_free_gid_list;
e8711085 4017
7ec0effd 4018 if (IS_P3P_TYPE(ha)) {
a9083016
GM		 4019 /* Allocate cache for CT6 Ctx. */
4020 if (!ctx_cachep) {
4021 ctx_cachep = kmem_cache_create("qla2xxx_ctx",
4022 sizeof(struct ct6_dsd), 0,
4023 SLAB_HWCACHE_ALIGN, NULL);
4024 if (!ctx_cachep)
fc1ffd6c 4025 goto fail_free_srb_mempool;
a9083016
GM		 4026 }
4027 ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ,
4028 ctx_cachep);
4029 if (!ha->ctx_mempool)
4030 goto fail_free_srb_mempool;
7c3df132
SK		 4031 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021,
4032 "ctx_cachep=%p ctx_mempool=%p.\n",
4033 ctx_cachep, ha->ctx_mempool);
a9083016
GM		 4034 }
4035
e8711085
AV		 4036 /* Get memory for cached NVRAM */
4037 ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL);
4038 if (!ha->nvram)
a9083016 4039 goto fail_free_ctx_mempool;
e8711085 4040
e315cd28
AC		 4041 snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME,
4042 ha->pdev->device);
4043 ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev,
4044 DMA_POOL_SIZE, 8, 0);
4045 if (!ha->s_dma_pool)
4046 goto fail_free_nvram;
4047
7c3df132
SK		 4048 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022,
4049 "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n",
4050 ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool);
4051
7ec0effd 4052 if (IS_P3P_TYPE(ha) || ql2xenabledif) {
a9083016
GM		 4053 ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev,
4054 DSD_LIST_DMA_POOL_SIZE, 8, 0);
4055 if (!ha->dl_dma_pool) {
7c3df132
SK		 4056 ql_log_pci(ql_log_fatal, ha->pdev, 0x0023,
4057 "Failed to allocate memory for dl_dma_pool.\n");
a9083016
GM		 4058 goto fail_s_dma_pool;
4059 }
4060
4061 ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev,
4062 FCP_CMND_DMA_POOL_SIZE, 8, 0);
4063 if (!ha->fcp_cmnd_dma_pool) {
7c3df132
SK		 4064 ql_log_pci(ql_log_fatal, ha->pdev, 0x0024,
4065 "Failed to allocate memory for fcp_cmnd_dma_pool.\n");
a9083016
GM		 4066 goto fail_dl_dma_pool;
4067 }
50b81275
GM		 4068
4069 if (ql2xenabledif) {
4070 u64 bufsize = DIF_BUNDLING_DMA_POOL_SIZE;
4071 struct dsd_dma *dsd, *nxt;
4072 uint i;
4073 /* Creata a DMA pool of buffers for DIF bundling */
4074 ha->dif_bundl_pool = dma_pool_create(name,
4075 &ha->pdev->dev, DIF_BUNDLING_DMA_POOL_SIZE, 8, 0);
4076 if (!ha->dif_bundl_pool) {
4077 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0024,
4078 "%s: failed create dif_bundl_pool\n",
4079 __func__);
4080 goto fail_dif_bundl_dma_pool;
4081 }
4082
4083 INIT_LIST_HEAD(&ha->pool.good.head);
4084 INIT_LIST_HEAD(&ha->pool.unusable.head);
4085 ha->pool.good.count = 0;
4086 ha->pool.unusable.count = 0;
4087 for (i = 0; i < 128; i++) {
4088 dsd = kzalloc(sizeof(*dsd), GFP_ATOMIC);
4089 if (!dsd) {
4090 ql_dbg_pci(ql_dbg_init, ha->pdev,
4091 0xe0ee, "%s: failed alloc dsd\n",
4092 __func__);
4093 return 1;
4094 }
4095 ha->dif_bundle_kallocs++;
4096
4097 dsd->dsd_addr = dma_pool_alloc(
4098 ha->dif_bundl_pool, GFP_ATOMIC,
4099 &dsd->dsd_list_dma);
4100 if (!dsd->dsd_addr) {
4101 ql_dbg_pci(ql_dbg_init, ha->pdev,
4102 0xe0ee,
4103 "%s: failed alloc ->dsd_addr\n",
4104 __func__);
4105 kfree(dsd);
4106 ha->dif_bundle_kallocs--;
4107 continue;
4108 }
4109 ha->dif_bundle_dma_allocs++;
4110
4111 /*
4112 * if DMA buffer crosses 4G boundary,
4113 * put it on bad list
4114 */
4115 if (MSD(dsd->dsd_list_dma) ^
4116 MSD(dsd->dsd_list_dma + bufsize)) {
4117 list_add_tail(&dsd->list,
4118 &ha->pool.unusable.head);
4119 ha->pool.unusable.count++;
4120 } else {
4121 list_add_tail(&dsd->list,
4122 &ha->pool.good.head);
4123 ha->pool.good.count++;
4124 }
4125 }
4126
4127 /* return the good ones back to the pool */
4128 list_for_each_entry_safe(dsd, nxt,
4129 &ha->pool.good.head, list) {
4130 list_del(&dsd->list);
4131 dma_pool_free(ha->dif_bundl_pool,
4132 dsd->dsd_addr, dsd->dsd_list_dma);
4133 ha->dif_bundle_dma_allocs--;
4134 kfree(dsd);
4135 ha->dif_bundle_kallocs--;
4136 }
4137
4138 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0024,
4139 "%s: dif dma pool (good=%u unusable=%u)\n",
4140 __func__, ha->pool.good.count,
4141 ha->pool.unusable.count);
4142 }
4143
7c3df132 4144 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025,
50b81275
GM		 4145 "dl_dma_pool=%p fcp_cmnd_dma_pool=%p dif_bundl_pool=%p.\n",
4146 ha->dl_dma_pool, ha->fcp_cmnd_dma_pool,
4147 ha->dif_bundl_pool);
a9083016
GM		 4148 }
4149
e8711085
AV		 4150 /* Allocate memory for SNS commands */
4151 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
e315cd28 4152 /* Get consistent memory allocated for SNS commands */
e8711085 4153 ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev,
e315cd28 4154 sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL);
e8711085 4155 if (!ha->sns_cmd)
e315cd28 4156 goto fail_dma_pool;
7c3df132 4157 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026,
d8424f68 4158 "sns_cmd: %p.\n", ha->sns_cmd);
e8711085 4159 } else {
e315cd28 4160 /* Get consistent memory allocated for MS IOCB */
e8711085 4161 ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
e315cd28 4162 &ha->ms_iocb_dma);
e8711085 4163 if (!ha->ms_iocb)
e315cd28
AC		 4164 goto fail_dma_pool;
4165 /* Get consistent memory allocated for CT SNS commands */
e8711085 4166 ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev,
e315cd28 4167 sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL);
e8711085
AV		 4168 if (!ha->ct_sns)
4169 goto fail_free_ms_iocb;
7c3df132
SK		 4170 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027,
4171 "ms_iocb=%p ct_sns=%p.\n",
4172 ha->ms_iocb, ha->ct_sns);
1da177e4
LT		 4173 }
4174
e315cd28 4175 /* Allocate memory for request ring */
73208dfd
AC		 4176 *req = kzalloc(sizeof(struct req_que), GFP_KERNEL);
4177 if (!*req) {
7c3df132
SK		 4178 ql_log_pci(ql_log_fatal, ha->pdev, 0x0028,
4179 "Failed to allocate memory for req.\n");
e315cd28
AC		 4180 goto fail_req;
4181 }
73208dfd
AC		 4182 (*req)->length = req_len;
4183 (*req)->ring = dma_alloc_coherent(&ha->pdev->dev,
4184 ((*req)->length + 1) * sizeof(request_t),
4185 &(*req)->dma, GFP_KERNEL);
4186 if (!(*req)->ring) {
7c3df132
SK		 4187 ql_log_pci(ql_log_fatal, ha->pdev, 0x0029,
4188 "Failed to allocate memory for req_ring.\n");
e315cd28
AC		 4189 goto fail_req_ring;
4190 }
4191 /* Allocate memory for response ring */
73208dfd
AC		 4192 *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL);
4193 if (!*rsp) {
7c3df132
SK		 4194 ql_log_pci(ql_log_fatal, ha->pdev, 0x002a,
4195 "Failed to allocate memory for rsp.\n");
e315cd28
AC		 4196 goto fail_rsp;
4197 }
73208dfd
AC		 4198 (*rsp)->hw = ha;
4199 (*rsp)->length = rsp_len;
4200 (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev,
4201 ((*rsp)->length + 1) * sizeof(response_t),
4202 &(*rsp)->dma, GFP_KERNEL);
4203 if (!(*rsp)->ring) {
7c3df132
SK		 4204 ql_log_pci(ql_log_fatal, ha->pdev, 0x002b,
4205 "Failed to allocate memory for rsp_ring.\n");
e315cd28
AC		 4206 goto fail_rsp_ring;
4207 }
73208dfd
AC		 4208 (*req)->rsp = *rsp;
4209 (*rsp)->req = *req;
7c3df132
SK		 4210 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c,
4211 "req=%p req->length=%d req->ring=%p rsp=%p "
4212 "rsp->length=%d rsp->ring=%p.\n",
4213 *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length,
4214 (*rsp)->ring);
73208dfd
AC		 4215 /* Allocate memory for NVRAM data for vports */
4216 if (ha->nvram_npiv_size) {
6396bb22
KC		 4217 ha->npiv_info = kcalloc(ha->nvram_npiv_size,
4218 sizeof(struct qla_npiv_entry),
4219 GFP_KERNEL);
73208dfd 4220 if (!ha->npiv_info) {
7c3df132
SK		 4221 ql_log_pci(ql_log_fatal, ha->pdev, 0x002d,
4222 "Failed to allocate memory for npiv_info.\n");
73208dfd
AC		 4223 goto fail_npiv_info;
4224 }
4225 } else
4226 ha->npiv_info = NULL;
e8711085 4227
b64b0e8f 4228 /* Get consistent memory allocated for EX-INIT-CB. */
ecc89f25
JC		 4229 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) ||
4230 IS_QLA28XX(ha)) {
b64b0e8f
AV		 4231 ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
4232 &ha->ex_init_cb_dma);
4233 if (!ha->ex_init_cb)
4234 goto fail_ex_init_cb;
7c3df132
SK		 4235 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e,
4236 "ex_init_cb=%p.\n", ha->ex_init_cb);
b64b0e8f
AV		 4237 }
4238
a9083016
GM		 4239 INIT_LIST_HEAD(&ha->gbl_dsd_list);
4240
5ff1d584
AV		 4241 /* Get consistent memory allocated for Async Port-Database. */
4242 if (!IS_FWI2_CAPABLE(ha)) {
4243 ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
4244 &ha->async_pd_dma);
4245 if (!ha->async_pd)
4246 goto fail_async_pd;
7c3df132
SK		 4247 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f,
4248 "async_pd=%p.\n", ha->async_pd);
5ff1d584
AV		 4249 }
4250
e315cd28 4251 INIT_LIST_HEAD(&ha->vp_list);
5f16b331
CD		 4252
4253 /* Allocate memory for our loop_id bitmap */
6396bb22
KC		 4254 ha->loop_id_map = kcalloc(BITS_TO_LONGS(LOOPID_MAP_SIZE),
4255 sizeof(long),
4256 GFP_KERNEL);
5f16b331 4257 if (!ha->loop_id_map)
fc1ffd6c 4258 goto fail_loop_id_map;
5f16b331
CD		 4259 else {
4260 qla2x00_set_reserved_loop_ids(ha);
4261 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0123,
b2a72ec3 4262 "loop_id_map=%p.\n", ha->loop_id_map);
5f16b331
CD		 4263 }
4264
e4e3a2ce
QT		 4265 ha->sfp_data = dma_alloc_coherent(&ha->pdev->dev,
4266 SFP_DEV_SIZE, &ha->sfp_data_dma, GFP_KERNEL);
4267 if (!ha->sfp_data) {
4268 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b,
4269 "Unable to allocate memory for SFP read-data.\n");
4270 goto fail_sfp_data;
4271 }
4272
3f006ac3
MH		 4273 ha->flt = dma_alloc_coherent(&ha->pdev->dev,
4274 sizeof(struct qla_flt_header) + FLT_REGIONS_SIZE, &ha->flt_dma,
4275 GFP_KERNEL);
4276 if (!ha->flt) {
4277 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b,
4278 "Unable to allocate memory for FLT.\n");
4279 goto fail_flt_buffer;
4280 }
4281
b2a72ec3 4282 return 0;
e315cd28 4283
3f006ac3
MH		 4284fail_flt_buffer:
4285 dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE,
4286 ha->sfp_data, ha->sfp_data_dma);
e4e3a2ce
QT		 4287fail_sfp_data:
4288 kfree(ha->loop_id_map);
fc1ffd6c
QT		 4289fail_loop_id_map:
4290 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
5ff1d584
AV		 4291fail_async_pd:
4292 dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma);
b64b0e8f
AV		 4293fail_ex_init_cb:
4294 kfree(ha->npiv_info);
73208dfd
AC		 4295fail_npiv_info:
4296 dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) *
4297 sizeof(response_t), (*rsp)->ring, (*rsp)->dma);
4298 (*rsp)->ring = NULL;
4299 (*rsp)->dma = 0;
e315cd28 4300fail_rsp_ring:
73208dfd 4301 kfree(*rsp);
6d634067 4302 *rsp = NULL;
e315cd28 4303fail_rsp:
73208dfd
AC		 4304 dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) *
4305 sizeof(request_t), (*req)->ring, (*req)->dma);
4306 (*req)->ring = NULL;
4307 (*req)->dma = 0;
e315cd28 4308fail_req_ring:
73208dfd 4309 kfree(*req);
6d634067 4310 *req = NULL;
e315cd28
AC		 4311fail_req:
4312 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
4313 ha->ct_sns, ha->ct_sns_dma);
4314 ha->ct_sns = NULL;
4315 ha->ct_sns_dma = 0;
e8711085
AV		 4316fail_free_ms_iocb:
4317 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
4318 ha->ms_iocb = NULL;
4319 ha->ms_iocb_dma = 0;
fc1ffd6c
QT		 4320
4321 if (ha->sns_cmd)
4322 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
4323 ha->sns_cmd, ha->sns_cmd_dma);
e315cd28 4324fail_dma_pool:
50b81275
GM		 4325 if (ql2xenabledif) {
4326 struct dsd_dma *dsd, *nxt;
4327
4328 list_for_each_entry_safe(dsd, nxt, &ha->pool.unusable.head,
4329 list) {
4330 list_del(&dsd->list);
4331 dma_pool_free(ha->dif_bundl_pool, dsd->dsd_addr,
4332 dsd->dsd_list_dma);
4333 ha->dif_bundle_dma_allocs--;
4334 kfree(dsd);
4335 ha->dif_bundle_kallocs--;
4336 ha->pool.unusable.count--;
4337 }
4338 dma_pool_destroy(ha->dif_bundl_pool);
4339 ha->dif_bundl_pool = NULL;
4340 }
4341
4342fail_dif_bundl_dma_pool:
bad75002 4343 if (IS_QLA82XX(ha) || ql2xenabledif) {
a9083016
GM		 4344 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
4345 ha->fcp_cmnd_dma_pool = NULL;
4346 }
4347fail_dl_dma_pool:
bad75002 4348 if (IS_QLA82XX(ha) || ql2xenabledif) {
a9083016
GM		 4349 dma_pool_destroy(ha->dl_dma_pool);
4350 ha->dl_dma_pool = NULL;
4351 }
4352fail_s_dma_pool:
e315cd28
AC		 4353 dma_pool_destroy(ha->s_dma_pool);
4354 ha->s_dma_pool = NULL;
e8711085
AV		 4355fail_free_nvram:
4356 kfree(ha->nvram);
4357 ha->nvram = NULL;
a9083016 4358fail_free_ctx_mempool:
75c1d48a 4359 mempool_destroy(ha->ctx_mempool);
a9083016 4360 ha->ctx_mempool = NULL;
e8711085 4361fail_free_srb_mempool:
75c1d48a 4362 mempool_destroy(ha->srb_mempool);
e8711085 4363 ha->srb_mempool = NULL;
e8711085 4364fail_free_gid_list:
642ef983
CD		 4365 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
4366 ha->gid_list,
e315cd28 4367 ha->gid_list_dma);
e8711085
AV		 4368 ha->gid_list = NULL;
4369 ha->gid_list_dma = 0;
2d70c103
NB		 4370fail_free_tgt_mem:
4371 qlt_mem_free(ha);
e315cd28
AC		 4372fail_free_init_cb:
4373 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb,
4374 ha->init_cb_dma);
4375 ha->init_cb = NULL;
4376 ha->init_cb_dma = 0;
e8711085 4377fail:
7c3df132
SK		 4378 ql_log(ql_log_fatal, NULL, 0x0030,
4379 "Memory allocation failure.\n");
e8711085 4380 return -ENOMEM;
1da177e4
LT		 4381}
4382
b0d6cabd
HM		 4383int
4384qla2x00_set_exlogins_buffer(scsi_qla_host_t *vha)
4385{
4386 int rval;
4387 uint16_t size, max_cnt, temp;
4388 struct qla_hw_data *ha = vha->hw;
4389
4390 /* Return if we don't need to alloacate any extended logins */
4391 if (!ql2xexlogins)
4392 return QLA_SUCCESS;
4393
99e1b683
QT		 4394 if (!IS_EXLOGIN_OFFLD_CAPABLE(ha))
4395 return QLA_SUCCESS;
4396
b0d6cabd
HM		 4397 ql_log(ql_log_info, vha, 0xd021, "EXLOGIN count: %d.\n", ql2xexlogins);
4398 max_cnt = 0;
4399 rval = qla_get_exlogin_status(vha, &size, &max_cnt);
4400 if (rval != QLA_SUCCESS) {
4401 ql_log_pci(ql_log_fatal, ha->pdev, 0xd029,
4402 "Failed to get exlogin status.\n");
4403 return rval;
4404 }
4405
4406 temp = (ql2xexlogins > max_cnt) ? max_cnt : ql2xexlogins;
99e1b683
QT		 4407 temp *= size;
4408
4409 if (temp != ha->exlogin_size) {
4410 qla2x00_free_exlogin_buffer(ha);
4411 ha->exlogin_size = temp;
4412
4413 ql_log(ql_log_info, vha, 0xd024,
4414 "EXLOGIN: max_logins=%d, portdb=0x%x, total=%d.\n",
4415 max_cnt, size, temp);
4416
4417 ql_log(ql_log_info, vha, 0xd025,
4418 "EXLOGIN: requested size=0x%x\n", ha->exlogin_size);
4419
4420 /* Get consistent memory for extended logins */
4421 ha->exlogin_buf = dma_alloc_coherent(&ha->pdev->dev,
4422 ha->exlogin_size, &ha->exlogin_buf_dma, GFP_KERNEL);
4423 if (!ha->exlogin_buf) {
4424 ql_log_pci(ql_log_fatal, ha->pdev, 0xd02a,
b0d6cabd 4425 "Failed to allocate memory for exlogin_buf_dma.\n");
99e1b683
QT		 4426 return -ENOMEM;
4427 }
b0d6cabd
HM		 4428 }
4429
4430 /* Now configure the dma buffer */
4431 rval = qla_set_exlogin_mem_cfg(vha, ha->exlogin_buf_dma);
4432 if (rval) {
83548fe2 4433 ql_log(ql_log_fatal, vha, 0xd033,
b0d6cabd
HM		 4434 "Setup extended login buffer ****FAILED****.\n");
4435 qla2x00_free_exlogin_buffer(ha);
4436 }
4437
4438 return rval;
4439}
4440
4441/*
4442* qla2x00_free_exlogin_buffer
4443*
4444* Input:
4445* ha = adapter block pointer
4446*/
4447void
4448qla2x00_free_exlogin_buffer(struct qla_hw_data *ha)
4449{
4450 if (ha->exlogin_buf) {
4451 dma_free_coherent(&ha->pdev->dev, ha->exlogin_size,
4452 ha->exlogin_buf, ha->exlogin_buf_dma);
4453 ha->exlogin_buf = NULL;
4454 ha->exlogin_size = 0;
4455 }
4456}
4457
99e1b683
QT		 4458static void
4459qla2x00_number_of_exch(scsi_qla_host_t *vha, u32 *ret_cnt, u16 max_cnt)
4460{
4461 u32 temp;
0645cb83 4462 struct init_cb_81xx *icb = (struct init_cb_81xx *)&vha->hw->init_cb;
99e1b683
QT		 4463 *ret_cnt = FW_DEF_EXCHANGES_CNT;
4464
d1e3635a
QT		 4465 if (max_cnt > vha->hw->max_exchg)
4466 max_cnt = vha->hw->max_exchg;
4467
99e1b683 4468 if (qla_ini_mode_enabled(vha)) {
0645cb83
QT		 4469 if (vha->ql2xiniexchg > max_cnt)
4470 vha->ql2xiniexchg = max_cnt;
4471
4472 if (vha->ql2xiniexchg > FW_DEF_EXCHANGES_CNT)
4473 *ret_cnt = vha->ql2xiniexchg;
99e1b683 4474
99e1b683 4475 } else if (qla_tgt_mode_enabled(vha)) {
0645cb83
QT		 4476 if (vha->ql2xexchoffld > max_cnt) {
4477 vha->ql2xexchoffld = max_cnt;
4478 icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld);
4479 }
99e1b683 4480
0645cb83
QT		 4481 if (vha->ql2xexchoffld > FW_DEF_EXCHANGES_CNT)
4482 *ret_cnt = vha->ql2xexchoffld;
99e1b683 4483 } else if (qla_dual_mode_enabled(vha)) {
0645cb83 4484 temp = vha->ql2xiniexchg + vha->ql2xexchoffld;
99e1b683 4485 if (temp > max_cnt) {
0645cb83
QT		 4486 vha->ql2xiniexchg -= (temp - max_cnt)/2;
4487 vha->ql2xexchoffld -= (((temp - max_cnt)/2) + 1);
99e1b683 4488 temp = max_cnt;
0645cb83 4489 icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld);
99e1b683
QT		 4490 }
4491
4492 if (temp > FW_DEF_EXCHANGES_CNT)
4493 *ret_cnt = temp;
4494 }
4495}
4496
2f56a7f1
HM		 4497int
4498qla2x00_set_exchoffld_buffer(scsi_qla_host_t *vha)
4499{
4500 int rval;
d1e3635a
QT		 4501 u16 size, max_cnt;
4502 u32 actual_cnt, totsz;
2f56a7f1
HM		 4503 struct qla_hw_data *ha = vha->hw;
4504
99e1b683
QT		 4505 if (!ha->flags.exchoffld_enabled)
4506 return QLA_SUCCESS;
4507
4508 if (!IS_EXCHG_OFFLD_CAPABLE(ha))
2f56a7f1
HM		 4509 return QLA_SUCCESS;
4510
2f56a7f1
HM		 4511 max_cnt = 0;
4512 rval = qla_get_exchoffld_status(vha, &size, &max_cnt);
4513 if (rval != QLA_SUCCESS) {
4514 ql_log_pci(ql_log_fatal, ha->pdev, 0xd012,
4515 "Failed to get exlogin status.\n");
4516 return rval;
4517 }
4518
d1e3635a
QT		 4519 qla2x00_number_of_exch(vha, &actual_cnt, max_cnt);
4520 ql_log(ql_log_info, vha, 0xd014,
4521 "Actual exchange offload count: %d.\n", actual_cnt);
4522
4523 totsz = actual_cnt * size;
2f56a7f1 4524
d1e3635a 4525 if (totsz != ha->exchoffld_size) {
99e1b683 4526 qla2x00_free_exchoffld_buffer(ha);
0645cb83
QT		 4527 if (actual_cnt <= FW_DEF_EXCHANGES_CNT) {
4528 ha->exchoffld_size = 0;
4529 ha->flags.exchoffld_enabled = 0;
4530 return QLA_SUCCESS;
4531 }
4532
d1e3635a 4533 ha->exchoffld_size = totsz;
99e1b683
QT		 4534
4535 ql_log(ql_log_info, vha, 0xd016,
d1e3635a
QT		 4536 "Exchange offload: max_count=%d, actual count=%d entry sz=0x%x, total sz=0x%x\n",
4537 max_cnt, actual_cnt, size, totsz);
99e1b683
QT		 4538
4539 ql_log(ql_log_info, vha, 0xd017,
4540 "Exchange Buffers requested size = 0x%x\n",
4541 ha->exchoffld_size);
4542
4543 /* Get consistent memory for extended logins */
4544 ha->exchoffld_buf = dma_alloc_coherent(&ha->pdev->dev,
4545 ha->exchoffld_size, &ha->exchoffld_buf_dma, GFP_KERNEL);
4546 if (!ha->exchoffld_buf) {
4547 ql_log_pci(ql_log_fatal, ha->pdev, 0xd013,
d1e3635a
QT		 4548 "Failed to allocate memory for Exchange Offload.\n");
4549
4550 if (ha->max_exchg >
4551 (FW_DEF_EXCHANGES_CNT + REDUCE_EXCHANGES_CNT)) {
4552 ha->max_exchg -= REDUCE_EXCHANGES_CNT;
4553 } else if (ha->max_exchg >
4554 (FW_DEF_EXCHANGES_CNT + 512)) {
4555 ha->max_exchg -= 512;
4556 } else {
4557 ha->flags.exchoffld_enabled = 0;
4558 ql_log_pci(ql_log_fatal, ha->pdev, 0xd013,
4559 "Disabling Exchange offload due to lack of memory\n");
4560 }
4561 ha->exchoffld_size = 0;
4562
99e1b683
QT		 4563 return -ENOMEM;
4564 }
0645cb83
QT		 4565 } else if (!ha->exchoffld_buf || (actual_cnt <= FW_DEF_EXCHANGES_CNT)) {
4566 /* pathological case */
4567 qla2x00_free_exchoffld_buffer(ha);
4568 ha->exchoffld_size = 0;
4569 ha->flags.exchoffld_enabled = 0;
4570 ql_log(ql_log_info, vha, 0xd016,
4571 "Exchange offload not enable: offld size=%d, actual count=%d entry sz=0x%x, total sz=0x%x.\n",
4572 ha->exchoffld_size, actual_cnt, size, totsz);
4573 return 0;
2f56a7f1
HM		 4574 }
4575
4576 /* Now configure the dma buffer */
99e1b683 4577 rval = qla_set_exchoffld_mem_cfg(vha);
2f56a7f1
HM		 4578 if (rval) {
4579 ql_log(ql_log_fatal, vha, 0xd02e,
4580 "Setup exchange offload buffer ****FAILED****.\n");
4581 qla2x00_free_exchoffld_buffer(ha);
99e1b683
QT		 4582 } else {
4583 /* re-adjust number of target exchange */
4584 struct init_cb_81xx *icb = (struct init_cb_81xx *)ha->init_cb;
4585
4586 if (qla_ini_mode_enabled(vha))
4587 icb->exchange_count = 0;
4588 else
0645cb83 4589 icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld);
2f56a7f1
HM		 4590 }
4591
4592 return rval;
4593}
4594
4595/*
4596* qla2x00_free_exchoffld_buffer
4597*
4598* Input:
4599* ha = adapter block pointer
4600*/
4601void
4602qla2x00_free_exchoffld_buffer(struct qla_hw_data *ha)
4603{
4604 if (ha->exchoffld_buf) {
4605 dma_free_coherent(&ha->pdev->dev, ha->exchoffld_size,
4606 ha->exchoffld_buf, ha->exchoffld_buf_dma);
4607 ha->exchoffld_buf = NULL;
4608 ha->exchoffld_size = 0;
4609 }
4610}
4611
1da177e4 4612/*
e30d1756
MI		 4613* qla2x00_free_fw_dump
4614* Frees fw dump stuff.
1da177e4
LT		 4615*
4616* Input:
7ec0effd 4617* ha = adapter block pointer
1da177e4 4618*/
a824ebb3 4619static void
e30d1756 4620qla2x00_free_fw_dump(struct qla_hw_data *ha)
1da177e4 4621{
a28d9e4e
JC		 4622 struct fwdt *fwdt = ha->fwdt;
4623 uint j;
4624
df613b96 4625 if (ha->fce)
f73cb695
CD		 4626 dma_free_coherent(&ha->pdev->dev,
4627 FCE_SIZE, ha->fce, ha->fce_dma);
df613b96 4628
f73cb695
CD		 4629 if (ha->eft)
4630 dma_free_coherent(&ha->pdev->dev,
4631 EFT_SIZE, ha->eft, ha->eft_dma);
4632
4633 if (ha->fw_dump)
a7a167bf 4634 vfree(ha->fw_dump);
f73cb695 4635
e30d1756
MI		 4636 ha->fce = NULL;
4637 ha->fce_dma = 0;
4638 ha->eft = NULL;
4639 ha->eft_dma = 0;
e30d1756 4640 ha->fw_dumped = 0;
61f098dd 4641 ha->fw_dump_cap_flags = 0;
e30d1756 4642 ha->fw_dump_reading = 0;
f73cb695
CD		 4643 ha->fw_dump = NULL;
4644 ha->fw_dump_len = 0;
a28d9e4e
JC		 4645
4646 for (j = 0; j < 2; j++, fwdt++) {
4647 if (fwdt->template)
4648 vfree(fwdt->template);
4649 fwdt->template = NULL;
4650 fwdt->length = 0;
4651 }
e30d1756
MI		 4652}
4653
4654/*
4655* qla2x00_mem_free
4656* Frees all adapter allocated memory.
4657*
4658* Input:
4659* ha = adapter block pointer.
4660*/
4661static void
4662qla2x00_mem_free(struct qla_hw_data *ha)
4663{
4664 qla2x00_free_fw_dump(ha);
4665
81178772
SK		 4666 if (ha->mctp_dump)
4667 dma_free_coherent(&ha->pdev->dev, MCTP_DUMP_SIZE, ha->mctp_dump,
4668 ha->mctp_dump_dma);
4669
75c1d48a 4670 mempool_destroy(ha->srb_mempool);
a7a167bf 4671
11bbc1d8
AV		 4672 if (ha->dcbx_tlv)
4673 dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE,
4674 ha->dcbx_tlv, ha->dcbx_tlv_dma);
4675
ce0423f4
AV		 4676 if (ha->xgmac_data)
4677 dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE,
4678 ha->xgmac_data, ha->xgmac_data_dma);
4679
1da177e4
LT		 4680 if (ha->sns_cmd)
4681 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
e315cd28 4682 ha->sns_cmd, ha->sns_cmd_dma);
1da177e4
LT		 4683
4684 if (ha->ct_sns)
4685 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
e315cd28 4686 ha->ct_sns, ha->ct_sns_dma);
1da177e4 4687
88729e53 4688 if (ha->sfp_data)
e4e3a2ce
QT		 4689 dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE, ha->sfp_data,
4690 ha->sfp_data_dma);
88729e53 4691
3f006ac3
MH		 4692 if (ha->flt)
4693 dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE,
4694 ha->flt, ha->flt_dma);
4695
1da177e4
LT		 4696 if (ha->ms_iocb)
4697 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
4698
b64b0e8f 4699 if (ha->ex_init_cb)
a9083016
GM		 4700 dma_pool_free(ha->s_dma_pool,
4701 ha->ex_init_cb, ha->ex_init_cb_dma);
b64b0e8f 4702
5ff1d584
AV		 4703 if (ha->async_pd)
4704 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
4705
75c1d48a 4706 dma_pool_destroy(ha->s_dma_pool);
1da177e4 4707
1da177e4 4708 if (ha->gid_list)
642ef983
CD		 4709 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
4710 ha->gid_list, ha->gid_list_dma);
1da177e4 4711
a9083016
GM		 4712 if (IS_QLA82XX(ha)) {
4713 if (!list_empty(&ha->gbl_dsd_list)) {
4714 struct dsd_dma *dsd_ptr, *tdsd_ptr;
4715
4716 /* clean up allocated prev pool */
4717 list_for_each_entry_safe(dsd_ptr,
4718 tdsd_ptr, &ha->gbl_dsd_list, list) {
4719 dma_pool_free(ha->dl_dma_pool,
4720 dsd_ptr->dsd_addr, dsd_ptr->dsd_list_dma);
4721 list_del(&dsd_ptr->list);
4722 kfree(dsd_ptr);
4723 }
4724 }
4725 }
4726
75c1d48a 4727 dma_pool_destroy(ha->dl_dma_pool);
a9083016 4728
75c1d48a 4729 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
a9083016 4730
75c1d48a 4731 mempool_destroy(ha->ctx_mempool);
a9083016 4732
50b81275
GM		 4733 if (ql2xenabledif) {
4734 struct dsd_dma *dsd, *nxt;
4735
4736 list_for_each_entry_safe(dsd, nxt, &ha->pool.unusable.head,
4737 list) {
4738 list_del(&dsd->list);
4739 dma_pool_free(ha->dif_bundl_pool, dsd->dsd_addr,
4740 dsd->dsd_list_dma);
4741 ha->dif_bundle_dma_allocs--;
4742 kfree(dsd);
4743 ha->dif_bundle_kallocs--;
4744 ha->pool.unusable.count--;
4745 }
4746 list_for_each_entry_safe(dsd, nxt, &ha->pool.good.head, list) {
4747 list_del(&dsd->list);
4748 dma_pool_free(ha->dif_bundl_pool, dsd->dsd_addr,
4749 dsd->dsd_list_dma);
4750 ha->dif_bundle_dma_allocs--;
4751 kfree(dsd);
4752 ha->dif_bundle_kallocs--;
4753 }
4754 }
4755
4756 if (ha->dif_bundl_pool)
4757 dma_pool_destroy(ha->dif_bundl_pool);
4758
2d70c103
NB		 4759 qlt_mem_free(ha);
4760
e315cd28
AC		 4761 if (ha->init_cb)
4762 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size,
a9083016 4763 ha->init_cb, ha->init_cb_dma);
6a2cf8d3 4764
6d634067
BK		 4765 vfree(ha->optrom_buffer);
4766 kfree(ha->nvram);
4767 kfree(ha->npiv_info);
4768 kfree(ha->swl);
4769 kfree(ha->loop_id_map);
1da177e4 4770
e8711085 4771 ha->srb_mempool = NULL;
a9083016 4772 ha->ctx_mempool = NULL;
1da177e4
LT		 4773 ha->sns_cmd = NULL;
4774 ha->sns_cmd_dma = 0;
4775 ha->ct_sns = NULL;
4776 ha->ct_sns_dma = 0;
4777 ha->ms_iocb = NULL;
4778 ha->ms_iocb_dma = 0;
1da177e4
LT		 4779 ha->init_cb = NULL;
4780 ha->init_cb_dma = 0;
b64b0e8f
AV		 4781 ha->ex_init_cb = NULL;
4782 ha->ex_init_cb_dma = 0;
5ff1d584
AV		 4783 ha->async_pd = NULL;
4784 ha->async_pd_dma = 0;
6a2cf8d3
BK		 4785 ha->loop_id_map = NULL;
4786 ha->npiv_info = NULL;
4787 ha->optrom_buffer = NULL;
4788 ha->swl = NULL;
4789 ha->nvram = NULL;
4790 ha->mctp_dump = NULL;
4791 ha->dcbx_tlv = NULL;
4792 ha->xgmac_data = NULL;
4793 ha->sfp_data = NULL;
1da177e4
LT		 4794
4795 ha->s_dma_pool = NULL;
a9083016
GM		 4796 ha->dl_dma_pool = NULL;
4797 ha->fcp_cmnd_dma_pool = NULL;
1da177e4 4798
1da177e4
LT		 4799 ha->gid_list = NULL;
4800 ha->gid_list_dma = 0;
2d70c103
NB		 4801
4802 ha->tgt.atio_ring = NULL;
4803 ha->tgt.atio_dma = 0;
4804 ha->tgt.tgt_vp_map = NULL;
e315cd28 4805}
1da177e4 4806
e315cd28
AC		 4807struct scsi_qla_host *qla2x00_create_host(struct scsi_host_template *sht,
4808 struct qla_hw_data *ha)
4809{
4810 struct Scsi_Host *host;
4811 struct scsi_qla_host *vha = NULL;
854165f4 4812
e315cd28 4813 host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t));
41dc529a 4814 if (!host) {
7c3df132
SK		 4815 ql_log_pci(ql_log_fatal, ha->pdev, 0x0107,
4816 "Failed to allocate host from the scsi layer, aborting.\n");
41dc529a 4817 return NULL;
e315cd28
AC		 4818 }
4819
4820 /* Clear our data area */
4821 vha = shost_priv(host);
4822 memset(vha, 0, sizeof(scsi_qla_host_t));
4823
4824 vha->host = host;
4825 vha->host_no = host->host_no;
4826 vha->hw = ha;
4827
0645cb83
QT		 4828 vha->qlini_mode = ql2x_ini_mode;
4829 vha->ql2xexchoffld = ql2xexchoffld;
4830 vha->ql2xiniexchg = ql2xiniexchg;
4831
e315cd28
AC		 4832 INIT_LIST_HEAD(&vha->vp_fcports);
4833 INIT_LIST_HEAD(&vha->work_list);
4834 INIT_LIST_HEAD(&vha->list);
8b2f5ff3
SN		 4835 INIT_LIST_HEAD(&vha->qla_cmd_list);
4836 INIT_LIST_HEAD(&vha->qla_sess_op_cmd_list);
71cdc079 4837 INIT_LIST_HEAD(&vha->logo_list);
b7bd104e 4838 INIT_LIST_HEAD(&vha->plogi_ack_list);
d7459527 4839 INIT_LIST_HEAD(&vha->qp_list);
41dc529a 4840 INIT_LIST_HEAD(&vha->gnl.fcports);
a5d42f4c 4841 INIT_LIST_HEAD(&vha->nvme_rport_list);
2d73ac61 4842 INIT_LIST_HEAD(&vha->gpnid_list);
9b3e0f4d 4843 INIT_WORK(&vha->iocb_work, qla2x00_iocb_work_fn);
e315cd28 4844
f999f4c1 4845 spin_lock_init(&vha->work_lock);
8b2f5ff3 4846 spin_lock_init(&vha->cmd_list_lock);
726b8548 4847 init_waitqueue_head(&vha->fcport_waitQ);
c4a9b538 4848 init_waitqueue_head(&vha->vref_waitq);
f999f4c1 4849
2fdbc65e
BVA		 4850 vha->gnl.size = sizeof(struct get_name_list_extended) *
4851 (ha->max_loop_id + 1);
41dc529a
QT		 4852 vha->gnl.l = dma_alloc_coherent(&ha->pdev->dev,
4853 vha->gnl.size, &vha->gnl.ldma, GFP_KERNEL);
4854 if (!vha->gnl.l) {
83548fe2 4855 ql_log(ql_log_fatal, vha, 0xd04a,
41dc529a
QT		 4856 "Alloc failed for name list.\n");
4857 scsi_remove_host(vha->host);
4858 return NULL;
4859 }
f999f4c1 4860
a4239945
QT		 4861 /* todo: what about ext login? */
4862 vha->scan.size = ha->max_fibre_devices * sizeof(struct fab_scan_rp);
4863 vha->scan.l = vmalloc(vha->scan.size);
4864 if (!vha->scan.l) {
4865 ql_log(ql_log_fatal, vha, 0xd04a,
4866 "Alloc failed for scan database.\n");
4867 dma_free_coherent(&ha->pdev->dev, vha->gnl.size,
4868 vha->gnl.l, vha->gnl.ldma);
4869 scsi_remove_host(vha->host);
4870 return NULL;
4871 }
f352eeb7 4872 INIT_DELAYED_WORK(&vha->scan.scan_work, qla_scan_work_fn);
a4239945 4873
e315cd28 4874 sprintf(vha->host_str, "%s_%ld", QLA2XXX_DRIVER_NAME, vha->host_no);
7c3df132
SK		 4875 ql_dbg(ql_dbg_init, vha, 0x0041,
4876 "Allocated the host=%p hw=%p vha=%p dev_name=%s",
4877 vha->host, vha->hw, vha,
4878 dev_name(&(ha->pdev->dev)));
4879
e315cd28 4880 return vha;
1da177e4
LT		 4881}
4882
726b8548 4883struct qla_work_evt *
f999f4c1 4884qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type)
0971de7f
AV		 4885{
4886 struct qla_work_evt *e;
feafb7b1
AE		 4887 uint8_t bail;
4888
4889 QLA_VHA_MARK_BUSY(vha, bail);
4890 if (bail)
4891 return NULL;
0971de7f 4892
f999f4c1 4893 e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC);
feafb7b1
AE		 4894 if (!e) {
4895 QLA_VHA_MARK_NOT_BUSY(vha);
0971de7f 4896 return NULL;
feafb7b1 4897 }
0971de7f
AV		 4898
4899 INIT_LIST_HEAD(&e->list);
4900 e->type = type;
4901 e->flags = QLA_EVT_FLAG_FREE;
4902 return e;
4903}
4904
726b8548 4905int
f999f4c1 4906qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e)
0971de7f 4907{
f999f4c1 4908 unsigned long flags;
9b3e0f4d 4909 bool q = false;
0971de7f 4910
f999f4c1 4911 spin_lock_irqsave(&vha->work_lock, flags);
e315cd28 4912 list_add_tail(&e->list, &vha->work_list);
9b3e0f4d
QT		 4913
4914 if (!test_and_set_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags))
4915 q = true;
4916
f999f4c1 4917 spin_unlock_irqrestore(&vha->work_lock, flags);
ec7193e2 4918
9b3e0f4d
QT		 4919 if (q)
4920 queue_work(vha->hw->wq, &vha->iocb_work);
f999f4c1 4921
0971de7f
AV		 4922 return QLA_SUCCESS;
4923}
4924
4925int
e315cd28 4926qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code,
0971de7f
AV		 4927 u32 data)
4928{
4929 struct qla_work_evt *e;
4930
f999f4c1 4931 e = qla2x00_alloc_work(vha, QLA_EVT_AEN);
0971de7f
AV		 4932 if (!e)
4933 return QLA_FUNCTION_FAILED;
4934
4935 e->u.aen.code = code;
4936 e->u.aen.data = data;
f999f4c1 4937 return qla2x00_post_work(vha, e);
0971de7f
AV		 4938}
4939
8a659571
AV		 4940int
4941qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb)
4942{
4943 struct qla_work_evt *e;
4944
f999f4c1 4945 e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK);
8a659571
AV		 4946 if (!e)
4947 return QLA_FUNCTION_FAILED;
4948
4949 memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t));
f999f4c1 4950 return qla2x00_post_work(vha, e);
8a659571
AV		 4951}
4952
ac280b67
AV		 4953#define qla2x00_post_async_work(name, type) \
4954int qla2x00_post_async_##name##_work( \
4955 struct scsi_qla_host *vha, \
4956 fc_port_t *fcport, uint16_t *data) \
4957{ \
4958 struct qla_work_evt *e; \
4959 \
4960 e = qla2x00_alloc_work(vha, type); \
4961 if (!e) \
4962 return QLA_FUNCTION_FAILED; \
4963 \
4964 e->u.logio.fcport = fcport; \
4965 if (data) { \
4966 e->u.logio.data[0] = data[0]; \
4967 e->u.logio.data[1] = data[1]; \
4968 } \
6d674927 4969 fcport->flags |= FCF_ASYNC_ACTIVE; \
ac280b67
AV		 4970 return qla2x00_post_work(vha, e); \
4971}
4972
4973qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN);
ac280b67
AV		 4974qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT);
4975qla2x00_post_async_work(logout_done, QLA_EVT_ASYNC_LOGOUT_DONE);
5ff1d584 4976qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC);
11aea16a
QT		 4977qla2x00_post_async_work(prlo, QLA_EVT_ASYNC_PRLO);
4978qla2x00_post_async_work(prlo_done, QLA_EVT_ASYNC_PRLO_DONE);
ac280b67 4979
3420d36c
AV		 4980int
4981qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code)
4982{
4983 struct qla_work_evt *e;
4984
4985 e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT);
4986 if (!e)
4987 return QLA_FUNCTION_FAILED;
4988
4989 e->u.uevent.code = code;
4990 return qla2x00_post_work(vha, e);
4991}
4992
4993static void
4994qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code)
4995{
4996 char event_string[40];
4997 char *envp[] = { event_string, NULL };
4998
4999 switch (code) {
5000 case QLA_UEVENT_CODE_FW_DUMP:
5001 snprintf(event_string, sizeof(event_string), "FW_DUMP=%ld",
5002 vha->host_no);
5003 break;
5004 default:
5005 /* do nothing */
5006 break;
5007 }
5008 kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp);
5009}
5010
8ae6d9c7
GM		 5011int
5012qlafx00_post_aenfx_work(struct scsi_qla_host *vha, uint32_t evtcode,
5013 uint32_t *data, int cnt)
5014{
5015 struct qla_work_evt *e;
5016
5017 e = qla2x00_alloc_work(vha, QLA_EVT_AENFX);
5018 if (!e)
5019 return QLA_FUNCTION_FAILED;
5020
5021 e->u.aenfx.evtcode = evtcode;
5022 e->u.aenfx.count = cnt;
5023 memcpy(e->u.aenfx.mbx, data, sizeof(*data) * cnt);
5024 return qla2x00_post_work(vha, e);
5025}
5026
cd4ed6b4 5027void qla24xx_sched_upd_fcport(fc_port_t *fcport)
726b8548 5028{
cd4ed6b4 5029 unsigned long flags;
726b8548 5030
cd4ed6b4
QT		 5031 if (IS_SW_RESV_ADDR(fcport->d_id))
5032 return;
726b8548 5033
cd4ed6b4
QT		 5034 spin_lock_irqsave(&fcport->vha->work_lock, flags);
5035 if (fcport->disc_state == DSC_UPD_FCPORT) {
5036 spin_unlock_irqrestore(&fcport->vha->work_lock, flags);
5037 return;
5038 }
5039 fcport->jiffies_at_registration = jiffies;
5040 fcport->sec_since_registration = 0;
5041 fcport->next_disc_state = DSC_DELETED;
5042 fcport->disc_state = DSC_UPD_FCPORT;
5043 spin_unlock_irqrestore(&fcport->vha->work_lock, flags);
5044
5045 queue_work(system_unbound_wq, &fcport->reg_work);
726b8548
QT		 5046}
5047
5048static
5049void qla24xx_create_new_sess(struct scsi_qla_host *vha, struct qla_work_evt *e)
5050{
5051 unsigned long flags;
b5d15312 5052 fc_port_t *fcport = NULL, *tfcp;
726b8548
QT		 5053 struct qlt_plogi_ack_t *pla =
5054 (struct qlt_plogi_ack_t *)e->u.new_sess.pla;
b5d15312 5055 uint8_t free_fcport = 0;
726b8548 5056
9cd883f0
QT		 5057 ql_dbg(ql_dbg_disc, vha, 0xffff,
5058 "%s %d %8phC enter\n",
5059 __func__, __LINE__, e->u.new_sess.port_name);
5060
726b8548
QT		 5061 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
5062 fcport = qla2x00_find_fcport_by_wwpn(vha, e->u.new_sess.port_name, 1);
5063 if (fcport) {
5064 fcport->d_id = e->u.new_sess.id;
5065 if (pla) {
5066 fcport->fw_login_state = DSC_LS_PLOGI_PEND;
9b3e0f4d
QT		 5067 memcpy(fcport->node_name,
5068 pla->iocb.u.isp24.u.plogi.node_name,
5069 WWN_SIZE);
726b8548
QT		 5070 qlt_plogi_ack_link(vha, pla, fcport, QLT_PLOGI_LINK_SAME_WWN);
5071 /* we took an extra ref_count to prevent PLOGI ACK when
5072 * fcport/sess has not been created.
5073 */
5074 pla->ref_count--;
5075 }
5076 } else {
b5d15312 5077 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
726b8548
QT		 5078 fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
5079 if (fcport) {
5080 fcport->d_id = e->u.new_sess.id;
726b8548
QT		 5081 fcport->flags |= FCF_FABRIC_DEVICE;
5082 fcport->fw_login_state = DSC_LS_PLOGI_PEND;
c64a87f9 5083 if (e->u.new_sess.fc4_type == FS_FC4TYPE_FCP)
a4239945 5084 fcport->fc4_type = FC4_TYPE_FCP_SCSI;
726b8548 5085
c64a87f9 5086 if (e->u.new_sess.fc4_type == FS_FC4TYPE_NVME) {
2b5b9647
DT		 5087 fcport->fc4_type = FC4_TYPE_OTHER;
5088 fcport->fc4f_nvme = FC4_TYPE_NVME;
5089 }
33b28357 5090
726b8548
QT		 5091 memcpy(fcport->port_name, e->u.new_sess.port_name,
5092 WWN_SIZE);
b5d15312
QT		 5093 } else {
5094 ql_dbg(ql_dbg_disc, vha, 0xffff,
5095 "%s %8phC mem alloc fail.\n",
5096 __func__, e->u.new_sess.port_name);
5097
5098 if (pla)
5099 kmem_cache_free(qla_tgt_plogi_cachep, pla);
5100 return;
5101 }
5102
5103 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
a4239945 5104 /* search again to make sure no one else got ahead */
b5d15312
QT		 5105 tfcp = qla2x00_find_fcport_by_wwpn(vha,
5106 e->u.new_sess.port_name, 1);
5107 if (tfcp) {
5108 /* should rarily happen */
5109 ql_dbg(ql_dbg_disc, vha, 0xffff,
5110 "%s %8phC found existing fcport b4 add. DS %d LS %d\n",
5111 __func__, tfcp->port_name, tfcp->disc_state,
5112 tfcp->fw_login_state);
5113
5114 free_fcport = 1;
5115 } else {
726b8548
QT		 5116 list_add_tail(&fcport->list, &vha->vp_fcports);
5117
19759033
QT		 5118 }
5119 if (pla) {
5120 qlt_plogi_ack_link(vha, pla, fcport,
5121 QLT_PLOGI_LINK_SAME_WWN);
5122 pla->ref_count--;
726b8548
QT		 5123 }
5124 }
5125 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
5126
5127 if (fcport) {
a4239945
QT		 5128 fcport->id_changed = 1;
5129 fcport->scan_state = QLA_FCPORT_FOUND;
5130 memcpy(fcport->node_name, e->u.new_sess.node_name, WWN_SIZE);
5131
5ef696aa 5132 if (pla) {
9cd883f0
QT		 5133 if (pla->iocb.u.isp24.status_subcode == ELS_PRLI) {
5134 u16 wd3_lo;
5135
5136 fcport->fw_login_state = DSC_LS_PRLI_PEND;
5137 fcport->local = 0;
5138 fcport->loop_id =
5139 le16_to_cpu(
5140 pla->iocb.u.isp24.nport_handle);
5141 fcport->fw_login_state = DSC_LS_PRLI_PEND;
5142 wd3_lo =
5143 le16_to_cpu(
5144 pla->iocb.u.isp24.u.prli.wd3_lo);
5145
5146 if (wd3_lo & BIT_7)
5147 fcport->conf_compl_supported = 1;
5148
5149 if ((wd3_lo & BIT_4) == 0)
5150 fcport->port_type = FCT_INITIATOR;
5151 else
5152 fcport->port_type = FCT_TARGET;
5153 }
726b8548 5154 qlt_plogi_ack_unref(vha, pla);
5ef696aa 5155 } else {
1c6cacf4
HR		 5156 fc_port_t *dfcp = NULL;
5157
5ef696aa
QT		 5158 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
5159 tfcp = qla2x00_find_fcport_by_nportid(vha,
5160 &e->u.new_sess.id, 1);
5161 if (tfcp && (tfcp != fcport)) {
5162 /*
5163 * We have a conflict fcport with same NportID.
5164 */
5165 ql_dbg(ql_dbg_disc, vha, 0xffff,
5166 "%s %8phC found conflict b4 add. DS %d LS %d\n",
5167 __func__, tfcp->port_name, tfcp->disc_state,
5168 tfcp->fw_login_state);
5169
5170 switch (tfcp->disc_state) {
5171 case DSC_DELETED:
5172 break;
5173 case DSC_DELETE_PEND:
5174 fcport->login_pause = 1;
5175 tfcp->conflict = fcport;
5176 break;
5177 default:
5178 fcport->login_pause = 1;
5179 tfcp->conflict = fcport;
1c6cacf4 5180 dfcp = tfcp;
5ef696aa
QT		 5181 break;
5182 }
5183 }
5184 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
1c6cacf4
HR		 5185 if (dfcp)
5186 qlt_schedule_sess_for_deletion(tfcp);
a4239945 5187
a4239945 5188
8777e431
QT		 5189 if (N2N_TOPO(vha->hw))
5190 fcport->flags &= ~FCF_FABRIC_DEVICE;
5191
5192 if (N2N_TOPO(vha->hw)) {
5193 if (vha->flags.nvme_enabled) {
5194 fcport->fc4f_nvme = 1;
5195 fcport->n2n_flag = 1;
5196 }
5197 fcport->fw_login_state = 0;
5198 /*
5199 * wait link init done before sending login
5200 */
5201 } else {
5202 qla24xx_fcport_handle_login(vha, fcport);
5203 }
5ef696aa 5204 }
726b8548 5205 }
b5d15312
QT		 5206
5207 if (free_fcport) {
5208 qla2x00_free_fcport(fcport);
5209 if (pla)
5210 kmem_cache_free(qla_tgt_plogi_cachep, pla);
5211 }
726b8548
QT		 5212}
5213
e374f9f5
QT		 5214static void qla_sp_retry(struct scsi_qla_host *vha, struct qla_work_evt *e)
5215{
5216 struct srb *sp = e->u.iosb.sp;
5217 int rval;
5218
5219 rval = qla2x00_start_sp(sp);
5220 if (rval != QLA_SUCCESS) {
5221 ql_dbg(ql_dbg_disc, vha, 0x2043,
5222 "%s: %s: Re-issue IOCB failed (%d).\n",
5223 __func__, sp->name, rval);
5224 qla24xx_sp_unmap(vha, sp);
5225 }
5226}
5227
ac280b67 5228void
e315cd28 5229qla2x00_do_work(struct scsi_qla_host *vha)
0971de7f 5230{
f999f4c1
AV		 5231 struct qla_work_evt *e, *tmp;
5232 unsigned long flags;
5233 LIST_HEAD(work);
80676d05 5234 int rc;
0971de7f 5235
f999f4c1
AV		 5236 spin_lock_irqsave(&vha->work_lock, flags);
5237 list_splice_init(&vha->work_list, &work);
5238 spin_unlock_irqrestore(&vha->work_lock, flags);
5239
5240 list_for_each_entry_safe(e, tmp, &work, list) {
80676d05 5241 rc = QLA_SUCCESS;
0971de7f
AV		 5242 switch (e->type) {
5243 case QLA_EVT_AEN:
e315cd28 5244 fc_host_post_event(vha->host, fc_get_event_number(),
0971de7f
AV		 5245 e->u.aen.code, e->u.aen.data);
5246 break;
8a659571
AV		 5247 case QLA_EVT_IDC_ACK:
5248 qla81xx_idc_ack(vha, e->u.idc_ack.mb);
5249 break;
ac280b67
AV		 5250 case QLA_EVT_ASYNC_LOGIN:
5251 qla2x00_async_login(vha, e->u.logio.fcport,
5252 e->u.logio.data);
5253 break;
ac280b67 5254 case QLA_EVT_ASYNC_LOGOUT:
80676d05 5255 rc = qla2x00_async_logout(vha, e->u.logio.fcport);
ac280b67
AV		 5256 break;
5257 case QLA_EVT_ASYNC_LOGOUT_DONE:
5258 qla2x00_async_logout_done(vha, e->u.logio.fcport,
5259 e->u.logio.data);
5260 break;
5ff1d584
AV		 5261 case QLA_EVT_ASYNC_ADISC:
5262 qla2x00_async_adisc(vha, e->u.logio.fcport,
5263 e->u.logio.data);
5264 break;
3420d36c
AV		 5265 case QLA_EVT_UEVENT:
5266 qla2x00_uevent_emit(vha, e->u.uevent.code);
5267 break;
8ae6d9c7
GM		 5268 case QLA_EVT_AENFX:
5269 qlafx00_process_aen(vha, e);
5270 break;
726b8548
QT		 5271 case QLA_EVT_GPNID:
5272 qla24xx_async_gpnid(vha, &e->u.gpnid.id);
5273 break;
e374f9f5
QT		 5274 case QLA_EVT_UNMAP:
5275 qla24xx_sp_unmap(vha, e->u.iosb.sp);
726b8548 5276 break;
9b3e0f4d
QT		 5277 case QLA_EVT_RELOGIN:
5278 qla2x00_relogin(vha);
5279 break;
726b8548
QT		 5280 case QLA_EVT_NEW_SESS:
5281 qla24xx_create_new_sess(vha, e);
5282 break;
5283 case QLA_EVT_GPDB:
5284 qla24xx_async_gpdb(vha, e->u.fcport.fcport,
5285 e->u.fcport.opt);
5286 break;
a5d42f4c
DG		 5287 case QLA_EVT_PRLI:
5288 qla24xx_async_prli(vha, e->u.fcport.fcport);
5289 break;
726b8548
QT		 5290 case QLA_EVT_GPSC:
5291 qla24xx_async_gpsc(vha, e->u.fcport.fcport);
5292 break;
726b8548
QT		 5293 case QLA_EVT_GNL:
5294 qla24xx_async_gnl(vha, e->u.fcport.fcport);
5295 break;
5296 case QLA_EVT_NACK:
5297 qla24xx_do_nack_work(vha, e);
5298 break;
11aea16a 5299 case QLA_EVT_ASYNC_PRLO:
80676d05 5300 rc = qla2x00_async_prlo(vha, e->u.logio.fcport);
11aea16a
QT		 5301 break;
5302 case QLA_EVT_ASYNC_PRLO_DONE:
5303 qla2x00_async_prlo_done(vha, e->u.logio.fcport,
5304 e->u.logio.data);
5305 break;
a4239945 5306 case QLA_EVT_GPNFT:
33b28357
QT		 5307 qla24xx_async_gpnft(vha, e->u.gpnft.fc4_type,
5308 e->u.gpnft.sp);
a4239945
QT		 5309 break;
5310 case QLA_EVT_GPNFT_DONE:
5311 qla24xx_async_gpnft_done(vha, e->u.iosb.sp);
5312 break;
5313 case QLA_EVT_GNNFT_DONE:
5314 qla24xx_async_gnnft_done(vha, e->u.iosb.sp);
5315 break;
5316 case QLA_EVT_GNNID:
5317 qla24xx_async_gnnid(vha, e->u.fcport.fcport);
5318 break;
5319 case QLA_EVT_GFPNID:
5320 qla24xx_async_gfpnid(vha, e->u.fcport.fcport);
5321 break;
e374f9f5
QT		 5322 case QLA_EVT_SP_RETRY:
5323 qla_sp_retry(vha, e);
cc28e0ac
QT		 5324 break;
5325 case QLA_EVT_IIDMA:
5326 qla_do_iidma_work(vha, e->u.fcport.fcport);
5327 break;
8777e431
QT		 5328 case QLA_EVT_ELS_PLOGI:
5329 qla24xx_els_dcmd2_iocb(vha, ELS_DCMD_PLOGI,
5330 e->u.fcport.fcport, false);
5331 break;
0971de7f 5332 }
80676d05
QT		 5333
5334 if (rc == EAGAIN) {
5335 /* put 'work' at head of 'vha->work_list' */
5336 spin_lock_irqsave(&vha->work_lock, flags);
5337 list_splice(&work, &vha->work_list);
5338 spin_unlock_irqrestore(&vha->work_lock, flags);
5339 break;
5340 }
5341 list_del_init(&e->list);
0971de7f
AV		 5342 if (e->flags & QLA_EVT_FLAG_FREE)
5343 kfree(e);
feafb7b1
AE		 5344
5345 /* For each work completed decrement vha ref count */
5346 QLA_VHA_MARK_NOT_BUSY(vha);
e315cd28 5347 }
e315cd28 5348}
f999f4c1 5349
9b3e0f4d
QT		 5350int qla24xx_post_relogin_work(struct scsi_qla_host *vha)
5351{
5352 struct qla_work_evt *e;
5353
5354 e = qla2x00_alloc_work(vha, QLA_EVT_RELOGIN);
5355
5356 if (!e) {
5357 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
5358 return QLA_FUNCTION_FAILED;
5359 }
5360
5361 return qla2x00_post_work(vha, e);
5362}
5363
e315cd28
AC		 5364/* Relogins all the fcports of a vport
5365 * Context: dpc thread
5366 */
5367void qla2x00_relogin(struct scsi_qla_host *vha)
5368{
5369 fc_port_t *fcport;
23dd98a6 5370 int status, relogin_needed = 0;
726b8548 5371 struct event_arg ea;
e315cd28
AC		 5372
5373 list_for_each_entry(fcport, &vha->vp_fcports, list) {
9cd883f0
QT		 5374 /*
5375 * If the port is not ONLINE then try to login
5376 * to it if we haven't run out of retries.
5377 */
5ff1d584 5378 if (atomic_read(&fcport->state) != FCS_ONLINE &&
23dd98a6
QT		 5379 fcport->login_retry) {
5380 if (fcport->scan_state != QLA_FCPORT_FOUND ||
5381 fcport->disc_state == DSC_LOGIN_COMPLETE)
5382 continue;
e315cd28 5383
23dd98a6
QT		 5384 if (fcport->flags & (FCF_ASYNC_SENT|FCF_ASYNC_ACTIVE) ||
5385 fcport->disc_state == DSC_DELETE_PEND) {
5386 relogin_needed = 1;
5387 } else {
5388 if (vha->hw->current_topology != ISP_CFG_NL) {
5389 memset(&ea, 0, sizeof(ea));
5390 ea.event = FCME_RELOGIN;
5391 ea.fcport = fcport;
5392 qla2x00_fcport_event_handler(vha, &ea);
5393 } else if (vha->hw->current_topology ==
5394 ISP_CFG_NL) {
5395 fcport->login_retry--;
5396 status =
5397 qla2x00_local_device_login(vha,
5398 fcport);
5399 if (status == QLA_SUCCESS) {
5400 fcport->old_loop_id =
5401 fcport->loop_id;
5402 ql_dbg(ql_dbg_disc, vha, 0x2003,
5403 "Port login OK: logged in ID 0x%x.\n",
5404 fcport->loop_id);
5405 qla2x00_update_fcport
5406 (vha, fcport);
5407 } else if (status == 1) {
5408 set_bit(RELOGIN_NEEDED,
5409 &vha->dpc_flags);
5410 /* retry the login again */
5411 ql_dbg(ql_dbg_disc, vha, 0x2007,
5412 "Retrying %d login again loop_id 0x%x.\n",
5413 fcport->login_retry,
5414 fcport->loop_id);
5415 } else {
5416 fcport->login_retry = 0;
5417 }
e315cd28 5418
23dd98a6
QT		 5419 if (fcport->login_retry == 0 &&
5420 status != QLA_SUCCESS)
5421 qla2x00_clear_loop_id(fcport);
5422 }
e315cd28 5423 }
e315cd28
AC		 5424 }
5425 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
5426 break;
0971de7f 5427 }
9b3e0f4d 5428
23dd98a6
QT		 5429 if (relogin_needed)
5430 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
5431
9b3e0f4d
QT		 5432 ql_dbg(ql_dbg_disc, vha, 0x400e,
5433 "Relogin end.\n");
0971de7f
AV		 5434}
5435
7d613ac6
SV		 5436/* Schedule work on any of the dpc-workqueues */
5437void
5438qla83xx_schedule_work(scsi_qla_host_t *base_vha, int work_code)
5439{
5440 struct qla_hw_data *ha = base_vha->hw;
5441
5442 switch (work_code) {
5443 case MBA_IDC_AEN: /* 0x8200 */
5444 if (ha->dpc_lp_wq)
5445 queue_work(ha->dpc_lp_wq, &ha->idc_aen);
5446 break;
5447
5448 case QLA83XX_NIC_CORE_RESET: /* 0x1 */
5449 if (!ha->flags.nic_core_reset_hdlr_active) {
5450 if (ha->dpc_hp_wq)
5451 queue_work(ha->dpc_hp_wq, &ha->nic_core_reset);
5452 } else
5453 ql_dbg(ql_dbg_p3p, base_vha, 0xb05e,
5454 "NIC Core reset is already active. Skip "
5455 "scheduling it again.\n");
5456 break;
5457 case QLA83XX_IDC_STATE_HANDLER: /* 0x2 */
5458 if (ha->dpc_hp_wq)
5459 queue_work(ha->dpc_hp_wq, &ha->idc_state_handler);
5460 break;
5461 case QLA83XX_NIC_CORE_UNRECOVERABLE: /* 0x3 */
5462 if (ha->dpc_hp_wq)
5463 queue_work(ha->dpc_hp_wq, &ha->nic_core_unrecoverable);
5464 break;
5465 default:
5466 ql_log(ql_log_warn, base_vha, 0xb05f,
d939be3a 5467 "Unknown work-code=0x%x.\n", work_code);
7d613ac6
SV		 5468 }
5469
5470 return;
5471}
5472
5473/* Work: Perform NIC Core Unrecoverable state handling */
5474void
5475qla83xx_nic_core_unrecoverable_work(struct work_struct *work)
5476{
5477 struct qla_hw_data *ha =
2ad1b67c 5478 container_of(work, struct qla_hw_data, nic_core_unrecoverable);
7d613ac6
SV		 5479 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5480 uint32_t dev_state = 0;
5481
5482 qla83xx_idc_lock(base_vha, 0);
5483 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
5484 qla83xx_reset_ownership(base_vha);
5485 if (ha->flags.nic_core_reset_owner) {
5486 ha->flags.nic_core_reset_owner = 0;
5487 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
5488 QLA8XXX_DEV_FAILED);
5489 ql_log(ql_log_info, base_vha, 0xb060, "HW State: FAILED.\n");
5490 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
5491 }
5492 qla83xx_idc_unlock(base_vha, 0);
5493}
5494
5495/* Work: Execute IDC state handler */
5496void
5497qla83xx_idc_state_handler_work(struct work_struct *work)
5498{
5499 struct qla_hw_data *ha =
2ad1b67c 5500 container_of(work, struct qla_hw_data, idc_state_handler);
7d613ac6
SV		 5501 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5502 uint32_t dev_state = 0;
5503
5504 qla83xx_idc_lock(base_vha, 0);
5505 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
5506 if (dev_state == QLA8XXX_DEV_FAILED ||
5507 dev_state == QLA8XXX_DEV_NEED_QUIESCENT)
5508 qla83xx_idc_state_handler(base_vha);
5509 qla83xx_idc_unlock(base_vha, 0);
5510}
5511
fa492630 5512static int
7d613ac6
SV		 5513qla83xx_check_nic_core_fw_alive(scsi_qla_host_t *base_vha)
5514{
5515 int rval = QLA_SUCCESS;
5516 unsigned long heart_beat_wait = jiffies + (1 * HZ);
5517 uint32_t heart_beat_counter1, heart_beat_counter2;
5518
5519 do {
5520 if (time_after(jiffies, heart_beat_wait)) {
5521 ql_dbg(ql_dbg_p3p, base_vha, 0xb07c,
5522 "Nic Core f/w is not alive.\n");
5523 rval = QLA_FUNCTION_FAILED;
5524 break;
5525 }
5526
5527 qla83xx_idc_lock(base_vha, 0);
5528 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
5529 &heart_beat_counter1);
5530 qla83xx_idc_unlock(base_vha, 0);
5531 msleep(100);
5532 qla83xx_idc_lock(base_vha, 0);
5533 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
5534 &heart_beat_counter2);
5535 qla83xx_idc_unlock(base_vha, 0);
5536 } while (heart_beat_counter1 == heart_beat_counter2);
5537
5538 return rval;
5539}
5540
5541/* Work: Perform NIC Core Reset handling */
5542void
5543qla83xx_nic_core_reset_work(struct work_struct *work)
5544{
5545 struct qla_hw_data *ha =
5546 container_of(work, struct qla_hw_data, nic_core_reset);
5547 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5548 uint32_t dev_state = 0;
5549
81178772
SK		 5550 if (IS_QLA2031(ha)) {
5551 if (qla2xxx_mctp_dump(base_vha) != QLA_SUCCESS)
5552 ql_log(ql_log_warn, base_vha, 0xb081,
5553 "Failed to dump mctp\n");
5554 return;
5555 }
5556
7d613ac6
SV		 5557 if (!ha->flags.nic_core_reset_hdlr_active) {
5558 if (qla83xx_check_nic_core_fw_alive(base_vha) == QLA_SUCCESS) {
5559 qla83xx_idc_lock(base_vha, 0);
5560 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE,
5561 &dev_state);
5562 qla83xx_idc_unlock(base_vha, 0);
5563 if (dev_state != QLA8XXX_DEV_NEED_RESET) {
5564 ql_dbg(ql_dbg_p3p, base_vha, 0xb07a,
5565 "Nic Core f/w is alive.\n");
5566 return;
5567 }
5568 }
5569
5570 ha->flags.nic_core_reset_hdlr_active = 1;
5571 if (qla83xx_nic_core_reset(base_vha)) {
5572 /* NIC Core reset failed. */
5573 ql_dbg(ql_dbg_p3p, base_vha, 0xb061,
5574 "NIC Core reset failed.\n");
5575 }
5576 ha->flags.nic_core_reset_hdlr_active = 0;
5577 }
5578}
5579
5580/* Work: Handle 8200 IDC aens */
5581void
5582qla83xx_service_idc_aen(struct work_struct *work)
5583{
5584 struct qla_hw_data *ha =
5585 container_of(work, struct qla_hw_data, idc_aen);
5586 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5587 uint32_t dev_state, idc_control;
5588
5589 qla83xx_idc_lock(base_vha, 0);
5590 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
5591 qla83xx_rd_reg(base_vha, QLA83XX_IDC_CONTROL, &idc_control);
5592 qla83xx_idc_unlock(base_vha, 0);
5593 if (dev_state == QLA8XXX_DEV_NEED_RESET) {
5594 if (idc_control & QLA83XX_IDC_GRACEFUL_RESET) {
5595 ql_dbg(ql_dbg_p3p, base_vha, 0xb062,
5596 "Application requested NIC Core Reset.\n");
5597 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
5598 } else if (qla83xx_check_nic_core_fw_alive(base_vha) ==
5599 QLA_SUCCESS) {
5600 ql_dbg(ql_dbg_p3p, base_vha, 0xb07b,
5601 "Other protocol driver requested NIC Core Reset.\n");
5602 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
5603 }
5604 } else if (dev_state == QLA8XXX_DEV_FAILED ||
5605 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) {
5606 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
5607 }
5608}
5609
5610static void
5611qla83xx_wait_logic(void)
5612{
5613 int i;
5614
5615 /* Yield CPU */
5616 if (!in_interrupt()) {
5617 /*
5618 * Wait about 200ms before retrying again.
5619 * This controls the number of retries for single
5620 * lock operation.
5621 */
5622 msleep(100);
5623 schedule();
5624 } else {
5625 for (i = 0; i < 20; i++)
5626 cpu_relax(); /* This a nop instr on i386 */
5627 }
5628}
5629
fa492630 5630static int
7d613ac6
SV		 5631qla83xx_force_lock_recovery(scsi_qla_host_t *base_vha)
5632{
5633 int rval;
5634 uint32_t data;
5635 uint32_t idc_lck_rcvry_stage_mask = 0x3;
5636 uint32_t idc_lck_rcvry_owner_mask = 0x3c;
5637 struct qla_hw_data *ha = base_vha->hw;
bd432bb5 5638
6c315553
SK		 5639 ql_dbg(ql_dbg_p3p, base_vha, 0xb086,
5640 "Trying force recovery of the IDC lock.\n");
7d613ac6
SV		 5641
5642 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, &data);
5643 if (rval)
5644 return rval;
5645
5646 if ((data & idc_lck_rcvry_stage_mask) > 0) {
5647 return QLA_SUCCESS;
5648 } else {
5649 data = (IDC_LOCK_RECOVERY_STAGE1) | (ha->portnum << 2);
5650 rval = qla83xx_wr_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
5651 data);
5652 if (rval)
5653 return rval;
5654
5655 msleep(200);
5656
5657 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
5658 &data);
5659 if (rval)
5660 return rval;
5661
5662 if (((data & idc_lck_rcvry_owner_mask) >> 2) == ha->portnum) {
5663 data &= (IDC_LOCK_RECOVERY_STAGE2 |
5664 ~(idc_lck_rcvry_stage_mask));
5665 rval = qla83xx_wr_reg(base_vha,
5666 QLA83XX_IDC_LOCK_RECOVERY, data);
5667 if (rval)
5668 return rval;
5669
5670 /* Forcefully perform IDC UnLock */
5671 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK,
5672 &data);
5673 if (rval)
5674 return rval;
5675 /* Clear lock-id by setting 0xff */
5676 rval = qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
5677 0xff);
5678 if (rval)
5679 return rval;
5680 /* Clear lock-recovery by setting 0x0 */
5681 rval = qla83xx_wr_reg(base_vha,
5682 QLA83XX_IDC_LOCK_RECOVERY, 0x0);
5683 if (rval)
5684 return rval;
5685 } else
5686 return QLA_SUCCESS;
5687 }
5688
5689 return rval;
5690}
5691
fa492630 5692static int
7d613ac6
SV		 5693qla83xx_idc_lock_recovery(scsi_qla_host_t *base_vha)
5694{
5695 int rval = QLA_SUCCESS;
5696 uint32_t o_drv_lockid, n_drv_lockid;
5697 unsigned long lock_recovery_timeout;
5698
5699 lock_recovery_timeout = jiffies + QLA83XX_MAX_LOCK_RECOVERY_WAIT;
5700retry_lockid:
5701 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &o_drv_lockid);
5702 if (rval)
5703 goto exit;
5704
5705 /* MAX wait time before forcing IDC Lock recovery = 2 secs */
5706 if (time_after_eq(jiffies, lock_recovery_timeout)) {
5707 if (qla83xx_force_lock_recovery(base_vha) == QLA_SUCCESS)
5708 return QLA_SUCCESS;
5709 else
5710 return QLA_FUNCTION_FAILED;
5711 }
5712
5713 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &n_drv_lockid);
5714 if (rval)
5715 goto exit;
5716
5717 if (o_drv_lockid == n_drv_lockid) {
5718 qla83xx_wait_logic();
5719 goto retry_lockid;
5720 } else
5721 return QLA_SUCCESS;
5722
5723exit:
5724 return rval;
5725}
5726
5727void
5728qla83xx_idc_lock(scsi_qla_host_t *base_vha, uint16_t requester_id)
5729{
5730 uint16_t options = (requester_id << 15) | BIT_6;
5731 uint32_t data;
6c315553 5732 uint32_t lock_owner;
7d613ac6
SV		 5733 struct qla_hw_data *ha = base_vha->hw;
5734
5735 /* IDC-lock implementation using driver-lock/lock-id remote registers */
5736retry_lock:
5737 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCK, &data)
5738 == QLA_SUCCESS) {
5739 if (data) {
5740 /* Setting lock-id to our function-number */
5741 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
5742 ha->portnum);
5743 } else {
6c315553
SK		 5744 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID,
5745 &lock_owner);
7d613ac6 5746 ql_dbg(ql_dbg_p3p, base_vha, 0xb063,
6c315553
SK		 5747 "Failed to acquire IDC lock, acquired by %d, "
5748 "retrying...\n", lock_owner);
7d613ac6
SV		 5749
5750 /* Retry/Perform IDC-Lock recovery */
5751 if (qla83xx_idc_lock_recovery(base_vha)
5752 == QLA_SUCCESS) {
5753 qla83xx_wait_logic();
5754 goto retry_lock;
5755 } else
5756 ql_log(ql_log_warn, base_vha, 0xb075,
5757 "IDC Lock recovery FAILED.\n");
5758 }
5759
5760 }
5761
5762 return;
5763
5764 /* XXX: IDC-lock implementation using access-control mbx */
5765retry_lock2:
5766 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
5767 ql_dbg(ql_dbg_p3p, base_vha, 0xb072,
5768 "Failed to acquire IDC lock. retrying...\n");
5769 /* Retry/Perform IDC-Lock recovery */
5770 if (qla83xx_idc_lock_recovery(base_vha) == QLA_SUCCESS) {
5771 qla83xx_wait_logic();
5772 goto retry_lock2;
5773 } else
5774 ql_log(ql_log_warn, base_vha, 0xb076,
5775 "IDC Lock recovery FAILED.\n");
5776 }
5777
5778 return;
5779}
5780
5781void
5782qla83xx_idc_unlock(scsi_qla_host_t *base_vha, uint16_t requester_id)
5783{
5897cb2f
BVA		 5784#if 0
5785 uint16_t options = (requester_id << 15) | BIT_7;
5786#endif
5787 uint16_t retry;
7d613ac6
SV		 5788 uint32_t data;
5789 struct qla_hw_data *ha = base_vha->hw;
5790
5791 /* IDC-unlock implementation using driver-unlock/lock-id
5792 * remote registers
5793 */
5794 retry = 0;
5795retry_unlock:
5796 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &data)
5797 == QLA_SUCCESS) {
5798 if (data == ha->portnum) {
5799 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, &data);
5800 /* Clearing lock-id by setting 0xff */
5801 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 0xff);
5802 } else if (retry < 10) {
5803 /* SV: XXX: IDC unlock retrying needed here? */
5804
5805 /* Retry for IDC-unlock */
5806 qla83xx_wait_logic();
5807 retry++;
5808 ql_dbg(ql_dbg_p3p, base_vha, 0xb064,
ee6a8773 5809 "Failed to release IDC lock, retrying=%d\n", retry);
7d613ac6
SV		 5810 goto retry_unlock;
5811 }
5812 } else if (retry < 10) {
5813 /* Retry for IDC-unlock */
5814 qla83xx_wait_logic();
5815 retry++;
5816 ql_dbg(ql_dbg_p3p, base_vha, 0xb065,
ee6a8773 5817 "Failed to read drv-lockid, retrying=%d\n", retry);
7d613ac6
SV		 5818 goto retry_unlock;
5819 }
5820
5821 return;
5822
5897cb2f 5823#if 0
7d613ac6
SV		 5824 /* XXX: IDC-unlock implementation using access-control mbx */
5825 retry = 0;
5826retry_unlock2:
5827 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
5828 if (retry < 10) {
5829 /* Retry for IDC-unlock */
5830 qla83xx_wait_logic();
5831 retry++;
5832 ql_dbg(ql_dbg_p3p, base_vha, 0xb066,
ee6a8773 5833 "Failed to release IDC lock, retrying=%d\n", retry);
7d613ac6
SV		 5834 goto retry_unlock2;
5835 }
5836 }
5837
5838 return;
5897cb2f 5839#endif
7d613ac6
SV		 5840}
5841
5842int
5843__qla83xx_set_drv_presence(scsi_qla_host_t *vha)
5844{
5845 int rval = QLA_SUCCESS;
5846 struct qla_hw_data *ha = vha->hw;
5847 uint32_t drv_presence;
5848
5849 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
5850 if (rval == QLA_SUCCESS) {
5851 drv_presence |= (1 << ha->portnum);
5852 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
5853 drv_presence);
5854 }
5855
5856 return rval;
5857}
5858
5859int
5860qla83xx_set_drv_presence(scsi_qla_host_t *vha)
5861{
5862 int rval = QLA_SUCCESS;
5863
5864 qla83xx_idc_lock(vha, 0);
5865 rval = __qla83xx_set_drv_presence(vha);
5866 qla83xx_idc_unlock(vha, 0);
5867
5868 return rval;
5869}
5870
5871int
5872__qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
5873{
5874 int rval = QLA_SUCCESS;
5875 struct qla_hw_data *ha = vha->hw;
5876 uint32_t drv_presence;
5877
5878 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
5879 if (rval == QLA_SUCCESS) {
5880 drv_presence &= ~(1 << ha->portnum);
5881 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
5882 drv_presence);
5883 }
5884
5885 return rval;
5886}
5887
5888int
5889qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
5890{
5891 int rval = QLA_SUCCESS;
5892
5893 qla83xx_idc_lock(vha, 0);
5894 rval = __qla83xx_clear_drv_presence(vha);
5895 qla83xx_idc_unlock(vha, 0);
5896
5897 return rval;
5898}
5899
fa492630 5900static void
7d613ac6
SV		 5901qla83xx_need_reset_handler(scsi_qla_host_t *vha)
5902{
5903 struct qla_hw_data *ha = vha->hw;
5904 uint32_t drv_ack, drv_presence;
5905 unsigned long ack_timeout;
5906
5907 /* Wait for IDC ACK from all functions (DRV-ACK == DRV-PRESENCE) */
5908 ack_timeout = jiffies + (ha->fcoe_reset_timeout * HZ);
5909 while (1) {
5910 qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
5911 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
807fb6d8 5912 if ((drv_ack & drv_presence) == drv_presence)
7d613ac6
SV		 5913 break;
5914
5915 if (time_after_eq(jiffies, ack_timeout)) {
5916 ql_log(ql_log_warn, vha, 0xb067,
5917 "RESET ACK TIMEOUT! drv_presence=0x%x "
5918 "drv_ack=0x%x\n", drv_presence, drv_ack);
5919 /*
5920 * The function(s) which did not ack in time are forced
5921 * to withdraw any further participation in the IDC
5922 * reset.
5923 */
5924 if (drv_ack != drv_presence)
5925 qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
5926 drv_ack);
5927 break;
5928 }
5929
5930 qla83xx_idc_unlock(vha, 0);
5931 msleep(1000);
5932 qla83xx_idc_lock(vha, 0);
5933 }
5934
5935 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_COLD);
5936 ql_log(ql_log_info, vha, 0xb068, "HW State: COLD/RE-INIT.\n");
5937}
5938
fa492630 5939static int
7d613ac6
SV		 5940qla83xx_device_bootstrap(scsi_qla_host_t *vha)
5941{
5942 int rval = QLA_SUCCESS;
5943 uint32_t idc_control;
5944
5945 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_INITIALIZING);
5946 ql_log(ql_log_info, vha, 0xb069, "HW State: INITIALIZING.\n");
5947
5948 /* Clearing IDC-Control Graceful-Reset Bit before resetting f/w */
5949 __qla83xx_get_idc_control(vha, &idc_control);
5950 idc_control &= ~QLA83XX_IDC_GRACEFUL_RESET;
5951 __qla83xx_set_idc_control(vha, 0);
5952
5953 qla83xx_idc_unlock(vha, 0);
5954 rval = qla83xx_restart_nic_firmware(vha);
5955 qla83xx_idc_lock(vha, 0);
5956
5957 if (rval != QLA_SUCCESS) {
5958 ql_log(ql_log_fatal, vha, 0xb06a,
5959 "Failed to restart NIC f/w.\n");
5960 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_FAILED);
5961 ql_log(ql_log_info, vha, 0xb06b, "HW State: FAILED.\n");
5962 } else {
5963 ql_dbg(ql_dbg_p3p, vha, 0xb06c,
5964 "Success in restarting nic f/w.\n");
5965 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_READY);
5966 ql_log(ql_log_info, vha, 0xb06d, "HW State: READY.\n");
5967 }
5968
5969 return rval;
5970}
5971
5972/* Assumes idc_lock always held on entry */
5973int
5974qla83xx_idc_state_handler(scsi_qla_host_t *base_vha)
5975{
5976 struct qla_hw_data *ha = base_vha->hw;
5977 int rval = QLA_SUCCESS;
5978 unsigned long dev_init_timeout;
5979 uint32_t dev_state;
5980
5981 /* Wait for MAX-INIT-TIMEOUT for the device to go ready */
5982 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ);
5983
5984 while (1) {
5985
5986 if (time_after_eq(jiffies, dev_init_timeout)) {
5987 ql_log(ql_log_warn, base_vha, 0xb06e,
5988 "Initialization TIMEOUT!\n");
5989 /* Init timeout. Disable further NIC Core
5990 * communication.
5991 */
5992 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
5993 QLA8XXX_DEV_FAILED);
5994 ql_log(ql_log_info, base_vha, 0xb06f,
5995 "HW State: FAILED.\n");
5996 }
5997
5998 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
5999 switch (dev_state) {
6000 case QLA8XXX_DEV_READY:
6001 if (ha->flags.nic_core_reset_owner)
6002 qla83xx_idc_audit(base_vha,
6003 IDC_AUDIT_COMPLETION);
6004 ha->flags.nic_core_reset_owner = 0;
6005 ql_dbg(ql_dbg_p3p, base_vha, 0xb070,
6006 "Reset_owner reset by 0x%x.\n",
6007 ha->portnum);
6008 goto exit;
6009 case QLA8XXX_DEV_COLD:
6010 if (ha->flags.nic_core_reset_owner)
6011 rval = qla83xx_device_bootstrap(base_vha);
6012 else {
6013 /* Wait for AEN to change device-state */
6014 qla83xx_idc_unlock(base_vha, 0);
6015 msleep(1000);
6016 qla83xx_idc_lock(base_vha, 0);
6017 }
6018 break;
6019 case QLA8XXX_DEV_INITIALIZING:
6020 /* Wait for AEN to change device-state */
6021 qla83xx_idc_unlock(base_vha, 0);
6022 msleep(1000);
6023 qla83xx_idc_lock(base_vha, 0);
6024 break;
6025 case QLA8XXX_DEV_NEED_RESET:
6026 if (!ql2xdontresethba && ha->flags.nic_core_reset_owner)
6027 qla83xx_need_reset_handler(base_vha);
6028 else {
6029 /* Wait for AEN to change device-state */
6030 qla83xx_idc_unlock(base_vha, 0);
6031 msleep(1000);
6032 qla83xx_idc_lock(base_vha, 0);
6033 }
6034 /* reset timeout value after need reset handler */
6035 dev_init_timeout = jiffies +
6036 (ha->fcoe_dev_init_timeout * HZ);
6037 break;
6038 case QLA8XXX_DEV_NEED_QUIESCENT:
6039 /* XXX: DEBUG for now */
6040 qla83xx_idc_unlock(base_vha, 0);
6041 msleep(1000);
6042 qla83xx_idc_lock(base_vha, 0);
6043 break;
6044 case QLA8XXX_DEV_QUIESCENT:
6045 /* XXX: DEBUG for now */
6046 if (ha->flags.quiesce_owner)
6047 goto exit;
6048
6049 qla83xx_idc_unlock(base_vha, 0);
6050 msleep(1000);
6051 qla83xx_idc_lock(base_vha, 0);
6052 dev_init_timeout = jiffies +
6053 (ha->fcoe_dev_init_timeout * HZ);
6054 break;
6055 case QLA8XXX_DEV_FAILED:
6056 if (ha->flags.nic_core_reset_owner)
6057 qla83xx_idc_audit(base_vha,
6058 IDC_AUDIT_COMPLETION);
6059 ha->flags.nic_core_reset_owner = 0;
6060 __qla83xx_clear_drv_presence(base_vha);
6061 qla83xx_idc_unlock(base_vha, 0);
6062 qla8xxx_dev_failed_handler(base_vha);
6063 rval = QLA_FUNCTION_FAILED;
6064 qla83xx_idc_lock(base_vha, 0);
6065 goto exit;
6066 case QLA8XXX_BAD_VALUE:
6067 qla83xx_idc_unlock(base_vha, 0);
6068 msleep(1000);
6069 qla83xx_idc_lock(base_vha, 0);
6070 break;
6071 default:
6072 ql_log(ql_log_warn, base_vha, 0xb071,
d939be3a 6073 "Unknown Device State: %x.\n", dev_state);
7d613ac6
SV		 6074 qla83xx_idc_unlock(base_vha, 0);
6075 qla8xxx_dev_failed_handler(base_vha);
6076 rval = QLA_FUNCTION_FAILED;
6077 qla83xx_idc_lock(base_vha, 0);
6078 goto exit;
6079 }
6080 }
6081
6082exit:
6083 return rval;
6084}
6085
f3ddac19
CD		 6086void
6087qla2x00_disable_board_on_pci_error(struct work_struct *work)
6088{
6089 struct qla_hw_data *ha = container_of(work, struct qla_hw_data,
6090 board_disable);
6091 struct pci_dev *pdev = ha->pdev;
6092 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
6093
726b8548
QT		 6094 /*
6095 * if UNLOAD flag is already set, then continue unload,
783e0dc4
SC		 6096 * where it was set first.
6097 */
6098 if (test_bit(UNLOADING, &base_vha->dpc_flags))
6099 return;
6100
f3ddac19
CD		 6101 ql_log(ql_log_warn, base_vha, 0x015b,
6102 "Disabling adapter.\n");
6103
efdb5760
SC		 6104 if (!atomic_read(&pdev->enable_cnt)) {
6105 ql_log(ql_log_info, base_vha, 0xfffc,
6106 "PCI device disabled, no action req for PCI error=%lx\n",
6107 base_vha->pci_flags);
6108 return;
6109 }
6110
726b8548
QT		 6111 qla2x00_wait_for_sess_deletion(base_vha);
6112
f3ddac19
CD		 6113 set_bit(UNLOADING, &base_vha->dpc_flags);
6114
6115 qla2x00_delete_all_vps(ha, base_vha);
6116
6117 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
6118
6119 qla2x00_dfs_remove(base_vha);
6120
6121 qla84xx_put_chip(base_vha);
6122
6123 if (base_vha->timer_active)
6124 qla2x00_stop_timer(base_vha);
6125
6126 base_vha->flags.online = 0;
6127
6128 qla2x00_destroy_deferred_work(ha);
6129
6130 /*
6131 * Do not try to stop beacon blink as it will issue a mailbox
6132 * command.
6133 */
6134 qla2x00_free_sysfs_attr(base_vha, false);
6135
6136 fc_remove_host(base_vha->host);
6137
6138 scsi_remove_host(base_vha->host);
6139
6140 base_vha->flags.init_done = 0;
6141 qla25xx_delete_queues(base_vha);
f3ddac19 6142 qla2x00_free_fcports(base_vha);
093df737 6143 qla2x00_free_irqs(base_vha);
f3ddac19
CD		 6144 qla2x00_mem_free(ha);
6145 qla82xx_md_free(base_vha);
6146 qla2x00_free_queues(ha);
6147
f3ddac19
CD		 6148 qla2x00_unmap_iobases(ha);
6149
6150 pci_release_selected_regions(ha->pdev, ha->bars);
f3ddac19
CD		 6151 pci_disable_pcie_error_reporting(pdev);
6152 pci_disable_device(pdev);
f3ddac19 6153
beb9e315
JL		 6154 /*
6155 * Let qla2x00_remove_one cleanup qla_hw_data on device removal.
6156 */
f3ddac19
CD		 6157}
6158
1da177e4
LT		 6159/**************************************************************************
6160* qla2x00_do_dpc
6161* This kernel thread is a task that is schedule by the interrupt handler
6162* to perform the background processing for interrupts.
6163*
6164* Notes:
6165* This task always run in the context of a kernel thread. It
6166* is kick-off by the driver's detect code and starts up
6167* up one per adapter. It immediately goes to sleep and waits for
6168* some fibre event. When either the interrupt handler or
6169* the timer routine detects a event it will one of the task
6170* bits then wake us up.
6171**************************************************************************/
6172static int
6173qla2x00_do_dpc(void *data)
6174{
e315cd28
AC		 6175 scsi_qla_host_t *base_vha;
6176 struct qla_hw_data *ha;
d7459527
MH		 6177 uint32_t online;
6178 struct qla_qpair *qpair;
1da177e4 6179
e315cd28
AC		 6180 ha = (struct qla_hw_data *)data;
6181 base_vha = pci_get_drvdata(ha->pdev);
1da177e4 6182
8698a745 6183 set_user_nice(current, MIN_NICE);
1da177e4 6184
563585ec 6185 set_current_state(TASK_INTERRUPTIBLE);
39a11240 6186 while (!kthread_should_stop()) {
7c3df132
SK		 6187 ql_dbg(ql_dbg_dpc, base_vha, 0x4000,
6188 "DPC handler sleeping.\n");
1da177e4 6189
39a11240 6190 schedule();
1da177e4 6191
c142caf0
AV		 6192 if (!base_vha->flags.init_done || ha->flags.mbox_busy)
6193 goto end_loop;
1da177e4 6194
85880801 6195 if (ha->flags.eeh_busy) {
7c3df132
SK		 6196 ql_dbg(ql_dbg_dpc, base_vha, 0x4003,
6197 "eeh_busy=%d.\n", ha->flags.eeh_busy);
c142caf0 6198 goto end_loop;
85880801
AV		 6199 }
6200
1da177e4
LT		 6201 ha->dpc_active = 1;
6202
5f28d2d7
SK		 6203 ql_dbg(ql_dbg_dpc + ql_dbg_verbose, base_vha, 0x4001,
6204 "DPC handler waking up, dpc_flags=0x%lx.\n",
6205 base_vha->dpc_flags);
1da177e4 6206
a29b3dd7
JC		 6207 if (test_bit(UNLOADING, &base_vha->dpc_flags))
6208 break;
6209
7ec0effd
AD		 6210 if (IS_P3P_TYPE(ha)) {
6211 if (IS_QLA8044(ha)) {
6212 if (test_and_clear_bit(ISP_UNRECOVERABLE,
6213 &base_vha->dpc_flags)) {
6214 qla8044_idc_lock(ha);
6215 qla8044_wr_direct(base_vha,
6216 QLA8044_CRB_DEV_STATE_INDEX,
6217 QLA8XXX_DEV_FAILED);
6218 qla8044_idc_unlock(ha);
6219 ql_log(ql_log_info, base_vha, 0x4004,
6220 "HW State: FAILED.\n");
6221 qla8044_device_state_handler(base_vha);
6222 continue;
6223 }
6224
6225 } else {
6226 if (test_and_clear_bit(ISP_UNRECOVERABLE,
6227 &base_vha->dpc_flags)) {
6228 qla82xx_idc_lock(ha);
6229 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
6230 QLA8XXX_DEV_FAILED);
6231 qla82xx_idc_unlock(ha);
6232 ql_log(ql_log_info, base_vha, 0x0151,
6233 "HW State: FAILED.\n");
6234 qla82xx_device_state_handler(base_vha);
6235 continue;
6236 }
a9083016
GM		 6237 }
6238
6239 if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED,
6240 &base_vha->dpc_flags)) {
6241
7c3df132
SK		 6242 ql_dbg(ql_dbg_dpc, base_vha, 0x4005,
6243 "FCoE context reset scheduled.\n");
a9083016
GM		 6244 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
6245 &base_vha->dpc_flags))) {
6246 if (qla82xx_fcoe_ctx_reset(base_vha)) {
6247 /* FCoE-ctx reset failed.
6248 * Escalate to chip-reset
6249 */
6250 set_bit(ISP_ABORT_NEEDED,
6251 &base_vha->dpc_flags);
6252 }
6253 clear_bit(ABORT_ISP_ACTIVE,
6254 &base_vha->dpc_flags);
6255 }
6256
7c3df132
SK		 6257 ql_dbg(ql_dbg_dpc, base_vha, 0x4006,
6258 "FCoE context reset end.\n");
a9083016 6259 }
8ae6d9c7
GM		 6260 } else if (IS_QLAFX00(ha)) {
6261 if (test_and_clear_bit(ISP_UNRECOVERABLE,
6262 &base_vha->dpc_flags)) {
6263 ql_dbg(ql_dbg_dpc, base_vha, 0x4020,
6264 "Firmware Reset Recovery\n");
6265 if (qlafx00_reset_initialize(base_vha)) {
6266 /* Failed. Abort isp later. */
6267 if (!test_bit(UNLOADING,
f92f82d6 6268 &base_vha->dpc_flags)) {
8ae6d9c7
GM		 6269 set_bit(ISP_UNRECOVERABLE,
6270 &base_vha->dpc_flags);
6271 ql_dbg(ql_dbg_dpc, base_vha,
6272 0x4021,
6273 "Reset Recovery Failed\n");
f92f82d6 6274 }
8ae6d9c7
GM		 6275 }
6276 }
6277
6278 if (test_and_clear_bit(FX00_TARGET_SCAN,
6279 &base_vha->dpc_flags)) {
6280 ql_dbg(ql_dbg_dpc, base_vha, 0x4022,
6281 "ISPFx00 Target Scan scheduled\n");
6282 if (qlafx00_rescan_isp(base_vha)) {
6283 if (!test_bit(UNLOADING,
6284 &base_vha->dpc_flags))
6285 set_bit(ISP_UNRECOVERABLE,
6286 &base_vha->dpc_flags);
6287 ql_dbg(ql_dbg_dpc, base_vha, 0x401e,
6288 "ISPFx00 Target Scan Failed\n");
6289 }
6290 ql_dbg(ql_dbg_dpc, base_vha, 0x401f,
6291 "ISPFx00 Target Scan End\n");
6292 }
e8f5e95d
AB		 6293 if (test_and_clear_bit(FX00_HOST_INFO_RESEND,
6294 &base_vha->dpc_flags)) {
6295 ql_dbg(ql_dbg_dpc, base_vha, 0x4023,
6296 "ISPFx00 Host Info resend scheduled\n");
6297 qlafx00_fx_disc(base_vha,
6298 &base_vha->hw->mr.fcport,
6299 FXDISC_REG_HOST_INFO);
6300 }
a9083016
GM		 6301 }
6302
e4e3a2ce
QT		 6303 if (test_and_clear_bit(DETECT_SFP_CHANGE,
6304 &base_vha->dpc_flags) &&
6305 !test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) {
6306 qla24xx_detect_sfp(base_vha);
6307
6308 if (ha->flags.detected_lr_sfp !=
6309 ha->flags.using_lr_setting)
6310 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
6311 }
6312
b08abbd9
QT		 6313 if (test_and_clear_bit
6314 (ISP_ABORT_NEEDED, &base_vha->dpc_flags) &&
6315 !test_bit(UNLOADING, &base_vha->dpc_flags)) {
93eca613
QT		 6316 bool do_reset = true;
6317
0645cb83 6318 switch (base_vha->qlini_mode) {
93eca613
QT		 6319 case QLA2XXX_INI_MODE_ENABLED:
6320 break;
6321 case QLA2XXX_INI_MODE_DISABLED:
0645cb83
QT		 6322 if (!qla_tgt_mode_enabled(base_vha) &&
6323 !ha->flags.fw_started)
93eca613
QT		 6324 do_reset = false;
6325 break;
6326 case QLA2XXX_INI_MODE_DUAL:
0645cb83
QT		 6327 if (!qla_dual_mode_enabled(base_vha) &&
6328 !ha->flags.fw_started)
93eca613
QT		 6329 do_reset = false;
6330 break;
6331 default:
6332 break;
6333 }
1da177e4 6334
93eca613 6335 if (do_reset && !(test_and_set_bit(ABORT_ISP_ACTIVE,
e315cd28 6336 &base_vha->dpc_flags))) {
93eca613
QT		 6337 ql_dbg(ql_dbg_dpc, base_vha, 0x4007,
6338 "ISP abort scheduled.\n");
a9083016 6339 if (ha->isp_ops->abort_isp(base_vha)) {
1da177e4
LT		 6340 /* failed. retry later */
6341 set_bit(ISP_ABORT_NEEDED,
e315cd28 6342 &base_vha->dpc_flags);
99363ef8 6343 }
e315cd28
AC		 6344 clear_bit(ABORT_ISP_ACTIVE,
6345 &base_vha->dpc_flags);
93eca613
QT		 6346 ql_dbg(ql_dbg_dpc, base_vha, 0x4008,
6347 "ISP abort end.\n");
99363ef8 6348 }
1da177e4
LT		 6349 }
6350
a394aac8
DJ		 6351 if (test_and_clear_bit(FCPORT_UPDATE_NEEDED,
6352 &base_vha->dpc_flags)) {
e315cd28 6353 qla2x00_update_fcports(base_vha);
c9c5ced9 6354 }
d97994dc 6355
8ae6d9c7
GM		 6356 if (IS_QLAFX00(ha))
6357 goto loop_resync_check;
6358
579d12b5 6359 if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) {
7c3df132
SK		 6360 ql_dbg(ql_dbg_dpc, base_vha, 0x4009,
6361 "Quiescence mode scheduled.\n");
7ec0effd
AD		 6362 if (IS_P3P_TYPE(ha)) {
6363 if (IS_QLA82XX(ha))
6364 qla82xx_device_state_handler(base_vha);
6365 if (IS_QLA8044(ha))
6366 qla8044_device_state_handler(base_vha);
8fcd6b8b
CD		 6367 clear_bit(ISP_QUIESCE_NEEDED,
6368 &base_vha->dpc_flags);
6369 if (!ha->flags.quiesce_owner) {
6370 qla2x00_perform_loop_resync(base_vha);
7ec0effd
AD		 6371 if (IS_QLA82XX(ha)) {
6372 qla82xx_idc_lock(ha);
6373 qla82xx_clear_qsnt_ready(
6374 base_vha);
6375 qla82xx_idc_unlock(ha);
6376 } else if (IS_QLA8044(ha)) {
6377 qla8044_idc_lock(ha);
6378 qla8044_clear_qsnt_ready(
6379 base_vha);
6380 qla8044_idc_unlock(ha);
6381 }
8fcd6b8b
CD		 6382 }
6383 } else {
6384 clear_bit(ISP_QUIESCE_NEEDED,
6385 &base_vha->dpc_flags);
6386 qla2x00_quiesce_io(base_vha);
579d12b5 6387 }
7c3df132
SK		 6388 ql_dbg(ql_dbg_dpc, base_vha, 0x400a,
6389 "Quiescence mode end.\n");
579d12b5
SK		 6390 }
6391
e315cd28 6392 if (test_and_clear_bit(RESET_MARKER_NEEDED,
8ae6d9c7 6393 &base_vha->dpc_flags) &&
e315cd28 6394 (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) {
1da177e4 6395
7c3df132
SK		 6396 ql_dbg(ql_dbg_dpc, base_vha, 0x400b,
6397 "Reset marker scheduled.\n");
e315cd28
AC		 6398 qla2x00_rst_aen(base_vha);
6399 clear_bit(RESET_ACTIVE, &base_vha->dpc_flags);
7c3df132
SK		 6400 ql_dbg(ql_dbg_dpc, base_vha, 0x400c,
6401 "Reset marker end.\n");
1da177e4
LT		 6402 }
6403
6404 /* Retry each device up to login retry count */
4005a995 6405 if (test_bit(RELOGIN_NEEDED, &base_vha->dpc_flags) &&
e315cd28
AC		 6406 !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) &&
6407 atomic_read(&base_vha->loop_state) != LOOP_DOWN) {
1da177e4 6408
4005a995
QT		 6409 if (!base_vha->relogin_jif ||
6410 time_after_eq(jiffies, base_vha->relogin_jif)) {
6411 base_vha->relogin_jif = jiffies + HZ;
6412 clear_bit(RELOGIN_NEEDED, &base_vha->dpc_flags);
6413
9b3e0f4d 6414 ql_dbg(ql_dbg_disc, base_vha, 0x400d,
4005a995 6415 "Relogin scheduled.\n");
9b3e0f4d 6416 qla24xx_post_relogin_work(base_vha);
4005a995 6417 }
1da177e4 6418 }
8ae6d9c7 6419loop_resync_check:
e315cd28 6420 if (test_and_clear_bit(LOOP_RESYNC_NEEDED,
8ae6d9c7 6421 &base_vha->dpc_flags)) {
1da177e4 6422
7c3df132
SK		 6423 ql_dbg(ql_dbg_dpc, base_vha, 0x400f,
6424 "Loop resync scheduled.\n");
1da177e4
LT		 6425
6426 if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE,
e315cd28 6427 &base_vha->dpc_flags))) {
1da177e4 6428
52c82823 6429 qla2x00_loop_resync(base_vha);
1da177e4 6430
e315cd28
AC		 6431 clear_bit(LOOP_RESYNC_ACTIVE,
6432 &base_vha->dpc_flags);
1da177e4
LT		 6433 }
6434
7c3df132
SK		 6435 ql_dbg(ql_dbg_dpc, base_vha, 0x4010,
6436 "Loop resync end.\n");
1da177e4
LT		 6437 }
6438
8ae6d9c7
GM		 6439 if (IS_QLAFX00(ha))
6440 goto intr_on_check;
6441
e315cd28
AC		 6442 if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) &&
6443 atomic_read(&base_vha->loop_state) == LOOP_READY) {
6444 clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags);
6445 qla2xxx_flash_npiv_conf(base_vha);
272976ca
AV		 6446 }
6447
8ae6d9c7 6448intr_on_check:
1da177e4 6449 if (!ha->interrupts_on)
fd34f556 6450 ha->isp_ops->enable_intrs(ha);
1da177e4 6451
e315cd28 6452 if (test_and_clear_bit(BEACON_BLINK_NEEDED,
90b604f2
HM		 6453 &base_vha->dpc_flags)) {
6454 if (ha->beacon_blink_led == 1)
6455 ha->isp_ops->beacon_blink(base_vha);
6456 }
f6df144c 6457
d7459527
MH		 6458 /* qpair online check */
6459 if (test_and_clear_bit(QPAIR_ONLINE_CHECK_NEEDED,
6460 &base_vha->dpc_flags)) {
6461 if (ha->flags.eeh_busy ||
6462 ha->flags.pci_channel_io_perm_failure)
6463 online = 0;
6464 else
6465 online = 1;
6466
6467 mutex_lock(&ha->mq_lock);
6468 list_for_each_entry(qpair, &base_vha->qp_list,
6469 qp_list_elem)
6470 qpair->online = online;
6471 mutex_unlock(&ha->mq_lock);
6472 }
6473
8b4673ba
QT		 6474 if (test_and_clear_bit(SET_NVME_ZIO_THRESHOLD_NEEDED,
6475 &base_vha->dpc_flags)) {
deeae7a6
DG		 6476 ql_log(ql_log_info, base_vha, 0xffffff,
6477 "nvme: SET ZIO Activity exchange threshold to %d.\n",
6478 ha->nvme_last_rptd_aen);
8b4673ba
QT		 6479 if (qla27xx_set_zio_threshold(base_vha,
6480 ha->nvme_last_rptd_aen)) {
deeae7a6 6481 ql_log(ql_log_info, base_vha, 0xffffff,
8b4673ba
QT		 6482 "nvme: Unable to SET ZIO Activity exchange threshold to %d.\n",
6483 ha->nvme_last_rptd_aen);
deeae7a6
DG		 6484 }
6485 }
6486
8b4673ba
QT		 6487 if (test_and_clear_bit(SET_ZIO_THRESHOLD_NEEDED,
6488 &base_vha->dpc_flags)) {
6489 ql_log(ql_log_info, base_vha, 0xffffff,
6490 "SET ZIO Activity exchange threshold to %d.\n",
6491 ha->last_zio_threshold);
6492 qla27xx_set_zio_threshold(base_vha,
6493 ha->last_zio_threshold);
6494 }
6495
8ae6d9c7
GM		 6496 if (!IS_QLAFX00(ha))
6497 qla2x00_do_dpc_all_vps(base_vha);
2c3dfe3f 6498
48acad09
QT		 6499 if (test_and_clear_bit(N2N_LINK_RESET,
6500 &base_vha->dpc_flags)) {
6501 qla2x00_lip_reset(base_vha);
6502 }
6503
1da177e4 6504 ha->dpc_active = 0;
c142caf0 6505end_loop:
563585ec 6506 set_current_state(TASK_INTERRUPTIBLE);
1da177e4 6507 } /* End of while(1) */
563585ec 6508 __set_current_state(TASK_RUNNING);
1da177e4 6509
7c3df132
SK		 6510 ql_dbg(ql_dbg_dpc, base_vha, 0x4011,
6511 "DPC handler exiting.\n");
1da177e4
LT		 6512
6513 /*
6514 * Make sure that nobody tries to wake us up again.
6515 */
1da177e4
LT		 6516 ha->dpc_active = 0;
6517
ac280b67
AV		 6518 /* Cleanup any residual CTX SRBs. */
6519 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
6520
39a11240
CH		 6521 return 0;
6522}
6523
6524void
e315cd28 6525qla2xxx_wake_dpc(struct scsi_qla_host *vha)
39a11240 6526{
e315cd28 6527 struct qla_hw_data *ha = vha->hw;
c795c1e4
AV		 6528 struct task_struct *t = ha->dpc_thread;
6529
e315cd28 6530 if (!test_bit(UNLOADING, &vha->dpc_flags) && t)
c795c1e4 6531 wake_up_process(t);
1da177e4
LT		 6532}
6533
1da177e4
LT		 6534/*
6535* qla2x00_rst_aen
6536* Processes asynchronous reset.
6537*
6538* Input:
6539* ha = adapter block pointer.
6540*/
6541static void
e315cd28 6542qla2x00_rst_aen(scsi_qla_host_t *vha)
1da177e4 6543{
e315cd28
AC		 6544 if (vha->flags.online && !vha->flags.reset_active &&
6545 !atomic_read(&vha->loop_down_timer) &&
6546 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) {
1da177e4 6547 do {
e315cd28 6548 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
1da177e4
LT		 6549
6550 /*
6551 * Issue marker command only when we are going to start
6552 * the I/O.
6553 */
e315cd28
AC		 6554 vha->marker_needed = 1;
6555 } while (!atomic_read(&vha->loop_down_timer) &&
6556 (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)));
1da177e4
LT		 6557 }
6558}
6559
1da177e4
LT		 6560/**************************************************************************
6561* qla2x00_timer
6562*
6563* Description:
6564* One second timer
6565*
6566* Context: Interrupt
6567***************************************************************************/
2c3dfe3f 6568void
8e5f4ba0 6569qla2x00_timer(struct timer_list *t)
1da177e4 6570{
8e5f4ba0 6571 scsi_qla_host_t *vha = from_timer(vha, t, timer);
1da177e4 6572 unsigned long cpu_flags = 0;
1da177e4
LT		 6573 int start_dpc = 0;
6574 int index;
6575 srb_t *sp;
85880801 6576 uint16_t w;
e315cd28 6577 struct qla_hw_data *ha = vha->hw;
73208dfd 6578 struct req_que *req;
85880801 6579
a5b36321 6580 if (ha->flags.eeh_busy) {
7c3df132
SK		 6581 ql_dbg(ql_dbg_timer, vha, 0x6000,
6582 "EEH = %d, restarting timer.\n",
6583 ha->flags.eeh_busy);
a5b36321
LC		 6584 qla2x00_restart_timer(vha, WATCH_INTERVAL);
6585 return;
6586 }
6587
f3ddac19
CD		 6588 /*
6589 * Hardware read to raise pending EEH errors during mailbox waits. If
6590 * the read returns -1 then disable the board.
6591 */
6592 if (!pci_channel_offline(ha->pdev)) {
85880801 6593 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w);
c821e0d5 6594 qla2x00_check_reg16_for_disconnect(vha, w);
f3ddac19 6595 }
1da177e4 6596
cefcaba6 6597 /* Make sure qla82xx_watchdog is run only for physical port */
7ec0effd 6598 if (!vha->vp_idx && IS_P3P_TYPE(ha)) {
579d12b5
SK		 6599 if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags))
6600 start_dpc++;
7ec0effd
AD		 6601 if (IS_QLA82XX(ha))
6602 qla82xx_watchdog(vha);
6603 else if (IS_QLA8044(ha))
6604 qla8044_watchdog(vha);
579d12b5
SK		 6605 }
6606
8ae6d9c7
GM		 6607 if (!vha->vp_idx && IS_QLAFX00(ha))
6608 qlafx00_timer_routine(vha);
6609
1da177e4 6610 /* Loop down handler. */
e315cd28 6611 if (atomic_read(&vha->loop_down_timer) > 0 &&
8f7daead
GM		 6612 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) &&
6613 !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags))
e315cd28 6614 && vha->flags.online) {
1da177e4 6615
e315cd28
AC		 6616 if (atomic_read(&vha->loop_down_timer) ==
6617 vha->loop_down_abort_time) {
1da177e4 6618
7c3df132
SK		 6619 ql_log(ql_log_info, vha, 0x6008,
6620 "Loop down - aborting the queues before time expires.\n");
1da177e4 6621
e315cd28
AC		 6622 if (!IS_QLA2100(ha) && vha->link_down_timeout)
6623 atomic_set(&vha->loop_state, LOOP_DEAD);
1da177e4 6624
f08b7251
AV		 6625 /*
6626 * Schedule an ISP abort to return any FCP2-device
6627 * commands.
6628 */
2c3dfe3f 6629 /* NPIV - scan physical port only */
e315cd28 6630 if (!vha->vp_idx) {
2c3dfe3f
SJ		 6631 spin_lock_irqsave(&ha->hardware_lock,
6632 cpu_flags);
73208dfd 6633 req = ha->req_q_map[0];
2c3dfe3f 6634 for (index = 1;
8d93f550 6635 index < req->num_outstanding_cmds;
2c3dfe3f
SJ		 6636 index++) {
6637 fc_port_t *sfcp;
6638
e315cd28 6639 sp = req->outstanding_cmds[index];
2c3dfe3f
SJ		 6640 if (!sp)
6641 continue;
c5419e26
QT		 6642 if (sp->cmd_type != TYPE_SRB)
6643 continue;
9ba56b95 6644 if (sp->type != SRB_SCSI_CMD)
cf53b069 6645 continue;
2c3dfe3f 6646 sfcp = sp->fcport;
f08b7251 6647 if (!(sfcp->flags & FCF_FCP2_DEVICE))
2c3dfe3f 6648 continue;
bdf79621 6649
8f7daead
GM		 6650 if (IS_QLA82XX(ha))
6651 set_bit(FCOE_CTX_RESET_NEEDED,
6652 &vha->dpc_flags);
6653 else
6654 set_bit(ISP_ABORT_NEEDED,
e315cd28 6655 &vha->dpc_flags);
2c3dfe3f
SJ		 6656 break;
6657 }
6658 spin_unlock_irqrestore(&ha->hardware_lock,
e315cd28 6659 cpu_flags);
1da177e4 6660 }
1da177e4
LT		 6661 start_dpc++;
6662 }
6663
6664 /* if the loop has been down for 4 minutes, reinit adapter */
e315cd28 6665 if (atomic_dec_and_test(&vha->loop_down_timer) != 0) {
0d6e61bc 6666 if (!(vha->device_flags & DFLG_NO_CABLE)) {
7c3df132 6667 ql_log(ql_log_warn, vha, 0x6009,
1da177e4
LT		 6668 "Loop down - aborting ISP.\n");
6669
8f7daead
GM		 6670 if (IS_QLA82XX(ha))
6671 set_bit(FCOE_CTX_RESET_NEEDED,
6672 &vha->dpc_flags);
6673 else
6674 set_bit(ISP_ABORT_NEEDED,
6675 &vha->dpc_flags);
1da177e4
LT		 6676 }
6677 }
7c3df132
SK		 6678 ql_dbg(ql_dbg_timer, vha, 0x600a,
6679 "Loop down - seconds remaining %d.\n",
6680 atomic_read(&vha->loop_down_timer));
1da177e4 6681 }
cefcaba6
SK		 6682 /* Check if beacon LED needs to be blinked for physical host only */
6683 if (!vha->vp_idx && (ha->beacon_blink_led == 1)) {
999916dc 6684 /* There is no beacon_blink function for ISP82xx */
7ec0effd 6685 if (!IS_P3P_TYPE(ha)) {
999916dc
SK		 6686 set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags);
6687 start_dpc++;
6688 }
f6df144c 6689 }
6690
550bf57d 6691 /* Process any deferred work. */
9b3e0f4d
QT		 6692 if (!list_empty(&vha->work_list)) {
6693 unsigned long flags;
6694 bool q = false;
6695
6696 spin_lock_irqsave(&vha->work_lock, flags);
6697 if (!test_and_set_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags))
6698 q = true;
6699 spin_unlock_irqrestore(&vha->work_lock, flags);
6700 if (q)
6701 queue_work(vha->hw->wq, &vha->iocb_work);
6702 }
550bf57d 6703
7401bc18
DG		 6704 /*
6705 * FC-NVME
6706 * see if the active AEN count has changed from what was last reported.
6707 */
b2d1453a
GM		 6708 if (!vha->vp_idx &&
6709 (atomic_read(&ha->nvme_active_aen_cnt) != ha->nvme_last_rptd_aen) &&
6710 ha->zio_mode == QLA_ZIO_MODE_6 &&
6711 !ha->flags.host_shutting_down) {
7401bc18 6712 ql_log(ql_log_info, vha, 0x3002,
8b4673ba
QT		 6713 "nvme: Sched: Set ZIO exchange threshold to %d.\n",
6714 ha->nvme_last_rptd_aen);
deeae7a6 6715 ha->nvme_last_rptd_aen = atomic_read(&ha->nvme_active_aen_cnt);
8b4673ba
QT		 6716 set_bit(SET_NVME_ZIO_THRESHOLD_NEEDED, &vha->dpc_flags);
6717 start_dpc++;
6718 }
6719
6720 if (!vha->vp_idx &&
6721 (atomic_read(&ha->zio_threshold) != ha->last_zio_threshold) &&
6722 (ha->zio_mode == QLA_ZIO_MODE_6) &&
ecc89f25 6723 (IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))) {
8b4673ba
QT		 6724 ql_log(ql_log_info, vha, 0x3002,
6725 "Sched: Set ZIO exchange threshold to %d.\n",
6726 ha->last_zio_threshold);
6727 ha->last_zio_threshold = atomic_read(&ha->zio_threshold);
deeae7a6
DG		 6728 set_bit(SET_ZIO_THRESHOLD_NEEDED, &vha->dpc_flags);
6729 start_dpc++;
7401bc18
DG		 6730 }
6731
1da177e4 6732 /* Schedule the DPC routine if needed */
e315cd28
AC		 6733 if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) ||
6734 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) ||
6735 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags) ||
1da177e4 6736 start_dpc ||
e315cd28
AC		 6737 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) ||
6738 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) ||
a9083016
GM		 6739 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) ||
6740 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) ||
e315cd28 6741 test_bit(VP_DPC_NEEDED, &vha->dpc_flags) ||
50280c01 6742 test_bit(RELOGIN_NEEDED, &vha->dpc_flags))) {
7c3df132
SK		 6743 ql_dbg(ql_dbg_timer, vha, 0x600b,
6744 "isp_abort_needed=%d loop_resync_needed=%d "
6745 "fcport_update_needed=%d start_dpc=%d "
6746 "reset_marker_needed=%d",
6747 test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags),
6748 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags),
6749 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags),
6750 start_dpc,
6751 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags));
6752 ql_dbg(ql_dbg_timer, vha, 0x600c,
6753 "beacon_blink_needed=%d isp_unrecoverable=%d "
6754 "fcoe_ctx_reset_needed=%d vp_dpc_needed=%d "
50280c01 6755 "relogin_needed=%d.\n",
7c3df132
SK		 6756 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags),
6757 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags),
6758 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags),
6759 test_bit(VP_DPC_NEEDED, &vha->dpc_flags),
50280c01 6760 test_bit(RELOGIN_NEEDED, &vha->dpc_flags));
e315cd28 6761 qla2xxx_wake_dpc(vha);
7c3df132 6762 }
1da177e4 6763
e315cd28 6764 qla2x00_restart_timer(vha, WATCH_INTERVAL);
1da177e4
LT		 6765}
6766
5433383e
AV		 6767/* Firmware interface routines. */
6768
5433383e
AV		 6769#define FW_ISP21XX 0
6770#define FW_ISP22XX 1
6771#define FW_ISP2300 2
6772#define FW_ISP2322 3
48c02fde 6773#define FW_ISP24XX 4
c3a2f0df 6774#define FW_ISP25XX 5
3a03eb79 6775#define FW_ISP81XX 6
a9083016 6776#define FW_ISP82XX 7
6246b8a1
GM		 6777#define FW_ISP2031 8
6778#define FW_ISP8031 9
2c5bbbb2 6779#define FW_ISP27XX 10
ecc89f25 6780#define FW_ISP28XX 11
5433383e 6781
bb8ee499
AV		 6782#define FW_FILE_ISP21XX "ql2100_fw.bin"
6783#define FW_FILE_ISP22XX "ql2200_fw.bin"
6784#define FW_FILE_ISP2300 "ql2300_fw.bin"
6785#define FW_FILE_ISP2322 "ql2322_fw.bin"
6786#define FW_FILE_ISP24XX "ql2400_fw.bin"
c3a2f0df 6787#define FW_FILE_ISP25XX "ql2500_fw.bin"
3a03eb79 6788#define FW_FILE_ISP81XX "ql8100_fw.bin"
a9083016 6789#define FW_FILE_ISP82XX "ql8200_fw.bin"
6246b8a1
GM		 6790#define FW_FILE_ISP2031 "ql2600_fw.bin"
6791#define FW_FILE_ISP8031 "ql8300_fw.bin"
2c5bbbb2 6792#define FW_FILE_ISP27XX "ql2700_fw.bin"
ecc89f25 6793#define FW_FILE_ISP28XX "ql2800_fw.bin"
f73cb695 6794
bb8ee499 6795
e1e82b6f 6796static DEFINE_MUTEX(qla_fw_lock);
5433383e 6797
ecc89f25 6798static struct fw_blob qla_fw_blobs[] = {
bb8ee499
AV		 6799 { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, },
6800 { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, },
6801 { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, },
6802 { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, },
6803 { .name = FW_FILE_ISP24XX, },
c3a2f0df 6804 { .name = FW_FILE_ISP25XX, },
3a03eb79 6805 { .name = FW_FILE_ISP81XX, },
a9083016 6806 { .name = FW_FILE_ISP82XX, },
6246b8a1
GM		 6807 { .name = FW_FILE_ISP2031, },
6808 { .name = FW_FILE_ISP8031, },
2c5bbbb2 6809 { .name = FW_FILE_ISP27XX, },
ecc89f25
JC		 6810 { .name = FW_FILE_ISP28XX, },
6811 { .name = NULL, },
5433383e
AV		 6812};
6813
6814struct fw_blob *
e315cd28 6815qla2x00_request_firmware(scsi_qla_host_t *vha)
5433383e 6816{
e315cd28 6817 struct qla_hw_data *ha = vha->hw;
5433383e
AV		 6818 struct fw_blob *blob;
6819
5433383e
AV		 6820 if (IS_QLA2100(ha)) {
6821 blob = &qla_fw_blobs[FW_ISP21XX];
6822 } else if (IS_QLA2200(ha)) {
6823 blob = &qla_fw_blobs[FW_ISP22XX];
48c02fde 6824 } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
5433383e 6825 blob = &qla_fw_blobs[FW_ISP2300];
48c02fde 6826 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
5433383e 6827 blob = &qla_fw_blobs[FW_ISP2322];
4d4df193 6828 } else if (IS_QLA24XX_TYPE(ha)) {
5433383e 6829 blob = &qla_fw_blobs[FW_ISP24XX];
c3a2f0df
AV		 6830 } else if (IS_QLA25XX(ha)) {
6831 blob = &qla_fw_blobs[FW_ISP25XX];
3a03eb79
AV		 6832 } else if (IS_QLA81XX(ha)) {
6833 blob = &qla_fw_blobs[FW_ISP81XX];
a9083016
GM		 6834 } else if (IS_QLA82XX(ha)) {
6835 blob = &qla_fw_blobs[FW_ISP82XX];
6246b8a1
GM		 6836 } else if (IS_QLA2031(ha)) {
6837 blob = &qla_fw_blobs[FW_ISP2031];
6838 } else if (IS_QLA8031(ha)) {
6839 blob = &qla_fw_blobs[FW_ISP8031];
2c5bbbb2
JC		 6840 } else if (IS_QLA27XX(ha)) {
6841 blob = &qla_fw_blobs[FW_ISP27XX];
ecc89f25
JC		 6842 } else if (IS_QLA28XX(ha)) {
6843 blob = &qla_fw_blobs[FW_ISP28XX];
8a655229
DC		 6844 } else {
6845 return NULL;
5433383e
AV		 6846 }
6847
ecc89f25
JC		 6848 if (!blob->name)
6849 return NULL;
6850
e1e82b6f 6851 mutex_lock(&qla_fw_lock);
5433383e
AV		 6852 if (blob->fw)
6853 goto out;
6854
6855 if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) {
7c3df132
SK		 6856 ql_log(ql_log_warn, vha, 0x0063,
6857 "Failed to load firmware image (%s).\n", blob->name);
5433383e
AV		 6858 blob->fw = NULL;
6859 blob = NULL;
5433383e
AV		 6860 }
6861
6862out:
e1e82b6f 6863 mutex_unlock(&qla_fw_lock);
5433383e
AV		 6864 return blob;
6865}
6866
6867static void
6868qla2x00_release_firmware(void)
6869{
ecc89f25 6870 struct fw_blob *blob;
5433383e 6871
e1e82b6f 6872 mutex_lock(&qla_fw_lock);
ecc89f25
JC		 6873 for (blob = qla_fw_blobs; blob->name; blob++)
6874 release_firmware(blob->fw);
e1e82b6f 6875 mutex_unlock(&qla_fw_lock);
5433383e
AV		 6876}
6877
14e660e6
SJ		 6878static pci_ers_result_t
6879qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
6880{
85880801
AV		 6881 scsi_qla_host_t *vha = pci_get_drvdata(pdev);
6882 struct qla_hw_data *ha = vha->hw;
6883
7c3df132
SK		 6884 ql_dbg(ql_dbg_aer, vha, 0x9000,
6885 "PCI error detected, state %x.\n", state);
b9b12f73 6886
efdb5760
SC		 6887 if (!atomic_read(&pdev->enable_cnt)) {
6888 ql_log(ql_log_info, vha, 0xffff,
6889 "PCI device is disabled,state %x\n", state);
6890 return PCI_ERS_RESULT_NEED_RESET;
6891 }
6892
14e660e6
SJ		 6893 switch (state) {
6894 case pci_channel_io_normal:
85880801 6895 ha->flags.eeh_busy = 0;
c38d1baf 6896 if (ql2xmqsupport || ql2xnvmeenable) {
d7459527
MH		 6897 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags);
6898 qla2xxx_wake_dpc(vha);
6899 }
14e660e6
SJ		 6900 return PCI_ERS_RESULT_CAN_RECOVER;
6901 case pci_channel_io_frozen:
85880801 6902 ha->flags.eeh_busy = 1;
a5b36321
LC		 6903 /* For ISP82XX complete any pending mailbox cmd */
6904 if (IS_QLA82XX(ha)) {
7190575f 6905 ha->flags.isp82xx_fw_hung = 1;
c8f6544e
CD		 6906 ql_dbg(ql_dbg_aer, vha, 0x9001, "Pci channel io frozen\n");
6907 qla82xx_clear_pending_mbx(vha);
a5b36321 6908 }
90a86fc0 6909 qla2x00_free_irqs(vha);
14e660e6 6910 pci_disable_device(pdev);
bddd2d65
LC		 6911 /* Return back all IOs */
6912 qla2x00_abort_all_cmds(vha, DID_RESET << 16);
c38d1baf 6913 if (ql2xmqsupport || ql2xnvmeenable) {
d7459527
MH		 6914 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags);
6915 qla2xxx_wake_dpc(vha);
6916 }
14e660e6
SJ		 6917 return PCI_ERS_RESULT_NEED_RESET;
6918 case pci_channel_io_perm_failure:
85880801
AV		 6919 ha->flags.pci_channel_io_perm_failure = 1;
6920 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
c38d1baf 6921 if (ql2xmqsupport || ql2xnvmeenable) {
d7459527
MH		 6922 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags);
6923 qla2xxx_wake_dpc(vha);
6924 }
14e660e6
SJ		 6925 return PCI_ERS_RESULT_DISCONNECT;
6926 }
6927 return PCI_ERS_RESULT_NEED_RESET;
6928}
6929
6930static pci_ers_result_t
6931qla2xxx_pci_mmio_enabled(struct pci_dev *pdev)
6932{
6933 int risc_paused = 0;
6934 uint32_t stat;
6935 unsigned long flags;
e315cd28
AC		 6936 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
6937 struct qla_hw_data *ha = base_vha->hw;
14e660e6
SJ		 6938 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
6939 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
6940
bcc5b6d3
SK		 6941 if (IS_QLA82XX(ha))
6942 return PCI_ERS_RESULT_RECOVERED;
6943
14e660e6
SJ		 6944 spin_lock_irqsave(&ha->hardware_lock, flags);
6945 if (IS_QLA2100(ha) || IS_QLA2200(ha)){
6946 stat = RD_REG_DWORD(&reg->hccr);
6947 if (stat & HCCR_RISC_PAUSE)
6948 risc_paused = 1;
6949 } else if (IS_QLA23XX(ha)) {
6950 stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
6951 if (stat & HSR_RISC_PAUSED)
6952 risc_paused = 1;
6953 } else if (IS_FWI2_CAPABLE(ha)) {
6954 stat = RD_REG_DWORD(&reg24->host_status);
6955 if (stat & HSRX_RISC_PAUSED)
6956 risc_paused = 1;
6957 }
6958 spin_unlock_irqrestore(&ha->hardware_lock, flags);
6959
6960 if (risc_paused) {
7c3df132
SK		 6961 ql_log(ql_log_info, base_vha, 0x9003,
6962 "RISC paused -- mmio_enabled, Dumping firmware.\n");
e315cd28 6963 ha->isp_ops->fw_dump(base_vha, 0);
14e660e6
SJ		 6964
6965 return PCI_ERS_RESULT_NEED_RESET;
6966 } else
6967 return PCI_ERS_RESULT_RECOVERED;
6968}
6969
fa492630
SK		 6970static uint32_t
6971qla82xx_error_recovery(scsi_qla_host_t *base_vha)
a5b36321
LC		 6972{
6973 uint32_t rval = QLA_FUNCTION_FAILED;
6974 uint32_t drv_active = 0;
6975 struct qla_hw_data *ha = base_vha->hw;
6976 int fn;
6977 struct pci_dev *other_pdev = NULL;
6978
7c3df132
SK		 6979 ql_dbg(ql_dbg_aer, base_vha, 0x9006,
6980 "Entered %s.\n", __func__);
a5b36321
LC		 6981
6982 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
6983
6984 if (base_vha->flags.online) {
6985 /* Abort all outstanding commands,
6986 * so as to be requeued later */
6987 qla2x00_abort_isp_cleanup(base_vha);
6988 }
6989
6990
6991 fn = PCI_FUNC(ha->pdev->devfn);
6992 while (fn > 0) {
6993 fn--;
7c3df132
SK		 6994 ql_dbg(ql_dbg_aer, base_vha, 0x9007,
6995 "Finding pci device at function = 0x%x.\n", fn);
a5b36321
LC		 6996 other_pdev =
6997 pci_get_domain_bus_and_slot(pci_domain_nr(ha->pdev->bus),
6998 ha->pdev->bus->number, PCI_DEVFN(PCI_SLOT(ha->pdev->devfn),
6999 fn));
7000
7001 if (!other_pdev)
7002 continue;
7003 if (atomic_read(&other_pdev->enable_cnt)) {
7c3df132
SK		 7004 ql_dbg(ql_dbg_aer, base_vha, 0x9008,
7005 "Found PCI func available and enable at 0x%x.\n",
7006 fn);
a5b36321
LC		 7007 pci_dev_put(other_pdev);
7008 break;
7009 }
7010 pci_dev_put(other_pdev);
7011 }
7012
7013 if (!fn) {
7014 /* Reset owner */
7c3df132
SK		 7015 ql_dbg(ql_dbg_aer, base_vha, 0x9009,
7016 "This devfn is reset owner = 0x%x.\n",
7017 ha->pdev->devfn);
a5b36321
LC		 7018 qla82xx_idc_lock(ha);
7019
7020 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 7021 QLA8XXX_DEV_INITIALIZING);
a5b36321
LC		 7022
7023 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION,
7024 QLA82XX_IDC_VERSION);
7025
7026 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
7c3df132
SK		 7027 ql_dbg(ql_dbg_aer, base_vha, 0x900a,
7028 "drv_active = 0x%x.\n", drv_active);
a5b36321
LC		 7029
7030 qla82xx_idc_unlock(ha);
7031 /* Reset if device is not already reset
7032 * drv_active would be 0 if a reset has already been done
7033 */
7034 if (drv_active)
7035 rval = qla82xx_start_firmware(base_vha);
7036 else
7037 rval = QLA_SUCCESS;
7038 qla82xx_idc_lock(ha);
7039
7040 if (rval != QLA_SUCCESS) {
7c3df132
SK		 7041 ql_log(ql_log_info, base_vha, 0x900b,
7042 "HW State: FAILED.\n");
a5b36321
LC		 7043 qla82xx_clear_drv_active(ha);
7044 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 7045 QLA8XXX_DEV_FAILED);
a5b36321 7046 } else {
7c3df132
SK		 7047 ql_log(ql_log_info, base_vha, 0x900c,
7048 "HW State: READY.\n");
a5b36321 7049 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 7050 QLA8XXX_DEV_READY);
a5b36321 7051 qla82xx_idc_unlock(ha);
7190575f 7052 ha->flags.isp82xx_fw_hung = 0;
a5b36321
LC		 7053 rval = qla82xx_restart_isp(base_vha);
7054 qla82xx_idc_lock(ha);
7055 /* Clear driver state register */
7056 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, 0);
7057 qla82xx_set_drv_active(base_vha);
7058 }
7059 qla82xx_idc_unlock(ha);
7060 } else {
7c3df132
SK		 7061 ql_dbg(ql_dbg_aer, base_vha, 0x900d,
7062 "This devfn is not reset owner = 0x%x.\n",
7063 ha->pdev->devfn);
a5b36321 7064 if ((qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE) ==
7d613ac6 7065 QLA8XXX_DEV_READY)) {
7190575f 7066 ha->flags.isp82xx_fw_hung = 0;
a5b36321
LC		 7067 rval = qla82xx_restart_isp(base_vha);
7068 qla82xx_idc_lock(ha);
7069 qla82xx_set_drv_active(base_vha);
7070 qla82xx_idc_unlock(ha);
7071 }
7072 }
7073 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
7074
7075 return rval;
7076}
7077
14e660e6
SJ		 7078static pci_ers_result_t
7079qla2xxx_pci_slot_reset(struct pci_dev *pdev)
7080{
7081 pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT;
e315cd28
AC		 7082 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
7083 struct qla_hw_data *ha = base_vha->hw;
90a86fc0
JC		 7084 struct rsp_que *rsp;
7085 int rc, retries = 10;
09483916 7086
7c3df132
SK		 7087 ql_dbg(ql_dbg_aer, base_vha, 0x9004,
7088 "Slot Reset.\n");
85880801 7089
90a86fc0
JC		 7090 /* Workaround: qla2xxx driver which access hardware earlier
7091 * needs error state to be pci_channel_io_online.
7092 * Otherwise mailbox command timesout.
7093 */
7094 pdev->error_state = pci_channel_io_normal;
7095
7096 pci_restore_state(pdev);
7097
8c1496bd
RL		 7098 /* pci_restore_state() clears the saved_state flag of the device
7099 * save restored state which resets saved_state flag
7100 */
7101 pci_save_state(pdev);
7102
09483916
BH		 7103 if (ha->mem_only)
7104 rc = pci_enable_device_mem(pdev);
7105 else
7106 rc = pci_enable_device(pdev);
14e660e6 7107
09483916 7108 if (rc) {
7c3df132 7109 ql_log(ql_log_warn, base_vha, 0x9005,
14e660e6 7110 "Can't re-enable PCI device after reset.\n");
a5b36321 7111 goto exit_slot_reset;
14e660e6 7112 }
14e660e6 7113
90a86fc0
JC		 7114 rsp = ha->rsp_q_map[0];
7115 if (qla2x00_request_irqs(ha, rsp))
a5b36321 7116 goto exit_slot_reset;
90a86fc0 7117
e315cd28 7118 if (ha->isp_ops->pci_config(base_vha))
a5b36321
LC		 7119 goto exit_slot_reset;
7120
7121 if (IS_QLA82XX(ha)) {
7122 if (qla82xx_error_recovery(base_vha) == QLA_SUCCESS) {
7123 ret = PCI_ERS_RESULT_RECOVERED;
7124 goto exit_slot_reset;
7125 } else
7126 goto exit_slot_reset;
7127 }
14e660e6 7128
90a86fc0
JC		 7129 while (ha->flags.mbox_busy && retries--)
7130 msleep(1000);
85880801 7131
e315cd28 7132 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
a9083016 7133 if (ha->isp_ops->abort_isp(base_vha) == QLA_SUCCESS)
14e660e6 7134 ret = PCI_ERS_RESULT_RECOVERED;
e315cd28 7135 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
14e660e6 7136
90a86fc0 7137
a5b36321 7138exit_slot_reset:
7c3df132
SK		 7139 ql_dbg(ql_dbg_aer, base_vha, 0x900e,
7140 "slot_reset return %x.\n", ret);
85880801 7141
14e660e6
SJ		 7142 return ret;
7143}
7144
7145static void
7146qla2xxx_pci_resume(struct pci_dev *pdev)
7147{
e315cd28
AC		 7148 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
7149 struct qla_hw_data *ha = base_vha->hw;
14e660e6
SJ		 7150 int ret;
7151
7c3df132
SK		 7152 ql_dbg(ql_dbg_aer, base_vha, 0x900f,
7153 "pci_resume.\n");
85880801 7154
e315cd28 7155 ret = qla2x00_wait_for_hba_online(base_vha);
14e660e6 7156 if (ret != QLA_SUCCESS) {
7c3df132
SK		 7157 ql_log(ql_log_fatal, base_vha, 0x9002,
7158 "The device failed to resume I/O from slot/link_reset.\n");
14e660e6 7159 }
85880801
AV		 7160
7161 ha->flags.eeh_busy = 0;
14e660e6
SJ		 7162}
7163
590f806d
QT		 7164static void
7165qla_pci_reset_prepare(struct pci_dev *pdev)
7166{
7167 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
7168 struct qla_hw_data *ha = base_vha->hw;
7169 struct qla_qpair *qpair;
7170
7171 ql_log(ql_log_warn, base_vha, 0xffff,
7172 "%s.\n", __func__);
7173
7174 /*
7175 * PCI FLR/function reset is about to reset the
7176 * slot. Stop the chip to stop all DMA access.
7177 * It is assumed that pci_reset_done will be called
7178 * after FLR to resume Chip operation.
7179 */
7180 ha->flags.eeh_busy = 1;
7181 mutex_lock(&ha->mq_lock);
7182 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem)
7183 qpair->online = 0;
7184 mutex_unlock(&ha->mq_lock);
7185
7186 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
7187 qla2x00_abort_isp_cleanup(base_vha);
7188 qla2x00_abort_all_cmds(base_vha, DID_RESET << 16);
7189}
7190
7191static void
7192qla_pci_reset_done(struct pci_dev *pdev)
7193{
7194 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
7195 struct qla_hw_data *ha = base_vha->hw;
7196 struct qla_qpair *qpair;
7197
7198 ql_log(ql_log_warn, base_vha, 0xffff,
7199 "%s.\n", __func__);
7200
7201 /*
7202 * FLR just completed by PCI layer. Resume adapter
7203 */
7204 ha->flags.eeh_busy = 0;
7205 mutex_lock(&ha->mq_lock);
7206 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem)
7207 qpair->online = 1;
7208 mutex_unlock(&ha->mq_lock);
7209
7210 base_vha->flags.online = 1;
7211 ha->isp_ops->abort_isp(base_vha);
7212 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
7213}
7214
5601236b
MH		 7215static int qla2xxx_map_queues(struct Scsi_Host *shost)
7216{
d68b850e 7217 int rc;
5601236b 7218 scsi_qla_host_t *vha = (scsi_qla_host_t *)shost->hostdata;
485b0eca 7219 struct blk_mq_queue_map *qmap = &shost->tag_set.map[HCTX_TYPE_DEFAULT];
5601236b 7220
f3e02695 7221 if (USER_CTRL_IRQ(vha->hw) || !vha->hw->mqiobase)
ed76e329 7222 rc = blk_mq_map_queues(qmap);
d68b850e 7223 else
f0783d43 7224 rc = blk_mq_pci_map_queues(qmap, vha->hw->pdev, vha->irq_offset);
d68b850e 7225 return rc;
5601236b
MH		 7226}
7227
6515ad71
BVA		 7228struct scsi_host_template qla2xxx_driver_template = {
7229 .module = THIS_MODULE,
7230 .name = QLA2XXX_DRIVER_NAME,
7231 .queuecommand = qla2xxx_queuecommand,
7232
7233 .eh_timed_out = fc_eh_timed_out,
7234 .eh_abort_handler = qla2xxx_eh_abort,
7235 .eh_device_reset_handler = qla2xxx_eh_device_reset,
7236 .eh_target_reset_handler = qla2xxx_eh_target_reset,
7237 .eh_bus_reset_handler = qla2xxx_eh_bus_reset,
7238 .eh_host_reset_handler = qla2xxx_eh_host_reset,
7239
7240 .slave_configure = qla2xxx_slave_configure,
7241
7242 .slave_alloc = qla2xxx_slave_alloc,
7243 .slave_destroy = qla2xxx_slave_destroy,
7244 .scan_finished = qla2xxx_scan_finished,
7245 .scan_start = qla2xxx_scan_start,
7246 .change_queue_depth = scsi_change_queue_depth,
7247 .map_queues = qla2xxx_map_queues,
7248 .this_id = -1,
7249 .cmd_per_lun = 3,
7250 .sg_tablesize = SG_ALL,
7251
7252 .max_sectors = 0xFFFF,
7253 .shost_attrs = qla2x00_host_attrs,
7254
7255 .supported_mode = MODE_INITIATOR,
7256 .track_queue_depth = 1,
7257};
7258
a55b2d21 7259static const struct pci_error_handlers qla2xxx_err_handler = {
14e660e6
SJ		 7260 .error_detected = qla2xxx_pci_error_detected,
7261 .mmio_enabled = qla2xxx_pci_mmio_enabled,
7262 .slot_reset = qla2xxx_pci_slot_reset,
7263 .resume = qla2xxx_pci_resume,
590f806d
QT		 7264 .reset_prepare = qla_pci_reset_prepare,
7265 .reset_done = qla_pci_reset_done,
14e660e6
SJ		 7266};
7267
5433383e 7268static struct pci_device_id qla2xxx_pci_tbl[] = {
47f5e069
AV		 7269 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) },
7270 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) },
7271 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) },
7272 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) },
7273 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) },
7274 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) },
7275 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) },
7276 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) },
7277 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) },
4d4df193 7278 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) },
47f5e069
AV		 7279 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) },
7280 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) },
c3a2f0df 7281 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) },
6246b8a1 7282 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2031) },
3a03eb79 7283 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) },
a9083016 7284 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) },
650f528f 7285 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8031) },
8ae6d9c7 7286 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISPF001) },
7ec0effd 7287 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8044) },
f73cb695 7288 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2071) },
2c5bbbb2 7289 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2271) },
2b48992f 7290 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2261) },
ecc89f25
JC		 7291 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2061) },
7292 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2081) },
7293 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2281) },
7294 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2089) },
7295 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2289) },
5433383e
AV		 7296 { 0 },
7297};
7298MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl);
7299
fca29703 7300static struct pci_driver qla2xxx_pci_driver = {
cb63067a 7301 .name = QLA2XXX_DRIVER_NAME,
0a21ef1e
JB		 7302 .driver = {
7303 .owner = THIS_MODULE,
7304 },
fca29703 7305 .id_table = qla2xxx_pci_tbl,
7ee61397 7306 .probe = qla2x00_probe_one,
4c993f76 7307 .remove = qla2x00_remove_one,
e30d1756 7308 .shutdown = qla2x00_shutdown,
14e660e6 7309 .err_handler = &qla2xxx_err_handler,
fca29703
AV		 7310};
7311
75ef9de1 7312static const struct file_operations apidev_fops = {
6a03b4cd 7313 .owner = THIS_MODULE,
6038f373 7314 .llseek = noop_llseek,
6a03b4cd
HZ		 7315};
7316
1da177e4
LT		 7317/**
7318 * qla2x00_module_init - Module initialization.
7319 **/
7320static int __init
7321qla2x00_module_init(void)
7322{
fca29703
AV		 7323 int ret = 0;
7324
1da177e4 7325 /* Allocate cache for SRBs. */
354d6b21 7326 srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0,
20c2df83 7327 SLAB_HWCACHE_ALIGN, NULL);
1da177e4 7328 if (srb_cachep == NULL) {
7c3df132
SK		 7329 ql_log(ql_log_fatal, NULL, 0x0001,
7330 "Unable to allocate SRB cache...Failing load!.\n");
1da177e4
LT		 7331 return -ENOMEM;
7332 }
7333
2d70c103
NB		 7334 /* Initialize target kmem_cache and mem_pools */
7335 ret = qlt_init();
7336 if (ret < 0) {
c794d24e 7337 goto destroy_cache;
2d70c103
NB		 7338 } else if (ret > 0) {
7339 /*
7340 * If initiator mode is explictly disabled by qlt_init(),
7341 * prevent scsi_transport_fc.c:fc_scsi_scan_rport() from
7342 * performing scsi_scan_target() during LOOP UP event.
7343 */
7344 qla2xxx_transport_functions.disable_target_scan = 1;
7345 qla2xxx_transport_vport_functions.disable_target_scan = 1;
7346 }
7347
1da177e4
LT		 7348 /* Derive version string. */
7349 strcpy(qla2x00_version_str, QLA2XXX_VERSION);
11010fec 7350 if (ql2xextended_error_logging)
0181944f 7351 strcat(qla2x00_version_str, "-debug");
fed0f68a
JC		 7352 if (ql2xextended_error_logging == 1)
7353 ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK;
0181944f 7354
0645cb83
QT		 7355 if (ql2x_ini_mode == QLA2XXX_INI_MODE_DUAL)
7356 qla_insert_tgt_attrs();
7357
1c97a12a
AV		 7358 qla2xxx_transport_template =
7359 fc_attach_transport(&qla2xxx_transport_functions);
2c3dfe3f 7360 if (!qla2xxx_transport_template) {
7c3df132
SK		 7361 ql_log(ql_log_fatal, NULL, 0x0002,
7362 "fc_attach_transport failed...Failing load!.\n");
c794d24e
BVA		 7363 ret = -ENODEV;
7364 goto qlt_exit;
2c3dfe3f 7365 }
6a03b4cd
HZ		 7366
7367 apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops);
7368 if (apidev_major < 0) {
7c3df132
SK		 7369 ql_log(ql_log_fatal, NULL, 0x0003,
7370 "Unable to register char device %s.\n", QLA2XXX_APIDEV);
6a03b4cd
HZ		 7371 }
7372
2c3dfe3f
SJ		 7373 qla2xxx_transport_vport_template =
7374 fc_attach_transport(&qla2xxx_transport_vport_functions);
7375 if (!qla2xxx_transport_vport_template) {
7c3df132
SK		 7376 ql_log(ql_log_fatal, NULL, 0x0004,
7377 "fc_attach_transport vport failed...Failing load!.\n");
c794d24e
BVA		 7378 ret = -ENODEV;
7379 goto unreg_chrdev;
2c3dfe3f 7380 }
7c3df132
SK		 7381 ql_log(ql_log_info, NULL, 0x0005,
7382 "QLogic Fibre Channel HBA Driver: %s.\n",
fd9a29f0 7383 qla2x00_version_str);
7ee61397 7384 ret = pci_register_driver(&qla2xxx_pci_driver);
fca29703 7385 if (ret) {
7c3df132
SK		 7386 ql_log(ql_log_fatal, NULL, 0x0006,
7387 "pci_register_driver failed...ret=%d Failing load!.\n",
7388 ret);
c794d24e 7389 goto release_vport_transport;
fca29703
AV		 7390 }
7391 return ret;
c794d24e
BVA		 7392
7393release_vport_transport:
7394 fc_release_transport(qla2xxx_transport_vport_template);
7395
7396unreg_chrdev:
7397 if (apidev_major >= 0)
7398 unregister_chrdev(apidev_major, QLA2XXX_APIDEV);
7399 fc_release_transport(qla2xxx_transport_template);
7400
7401qlt_exit:
7402 qlt_exit();
7403
7404destroy_cache:
7405 kmem_cache_destroy(srb_cachep);
7406 return ret;
1da177e4
LT		 7407}
7408
7409/**
7410 * qla2x00_module_exit - Module cleanup.
7411 **/
7412static void __exit
7413qla2x00_module_exit(void)
7414{
7ee61397 7415 pci_unregister_driver(&qla2xxx_pci_driver);
5433383e 7416 qla2x00_release_firmware();
75c1d48a 7417 kmem_cache_destroy(ctx_cachep);
2c3dfe3f 7418 fc_release_transport(qla2xxx_transport_vport_template);
59c209a6
BVA		 7419 if (apidev_major >= 0)
7420 unregister_chrdev(apidev_major, QLA2XXX_APIDEV);
7421 fc_release_transport(qla2xxx_transport_template);
7422 qlt_exit();
7423 kmem_cache_destroy(srb_cachep);
1da177e4
LT		 7424}
7425
7426module_init(qla2x00_module_init);
7427module_exit(qla2x00_module_exit);
7428
7429MODULE_AUTHOR("QLogic Corporation");
7430MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver");
7431MODULE_LICENSE("GPL");
7432MODULE_VERSION(QLA2XXX_VERSION);
bb8ee499
AV		 7433MODULE_FIRMWARE(FW_FILE_ISP21XX);
7434MODULE_FIRMWARE(FW_FILE_ISP22XX);
7435MODULE_FIRMWARE(FW_FILE_ISP2300);
7436MODULE_FIRMWARE(FW_FILE_ISP2322);
7437MODULE_FIRMWARE(FW_FILE_ISP24XX);
61623fc3 7438MODULE_FIRMWARE(FW_FILE_ISP25XX);
Linux 6.x block layer and io_uring tree(s)