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qla2xxx: Fix hardware lock/unlock issue causing kernel panic.
[linux-2.6-block.git] / drivers / scsi / qla2xxx / qla_os.c
CommitLineData
1da177e4 1/*
fa90c54f 2 * QLogic Fibre Channel HBA Driver
bd21eaf9 3 * Copyright (c) 2003-2014 QLogic Corporation
1da177e4 4 *
fa90c54f 5 * See LICENSE.qla2xxx for copyright and licensing details.
1da177e4
LT		 6 */
7#include "qla_def.h"
8
9#include <linux/moduleparam.h>
10#include <linux/vmalloc.h>
1da177e4 11#include <linux/delay.h>
39a11240 12#include <linux/kthread.h>
e1e82b6f 13#include <linux/mutex.h>
3420d36c 14#include <linux/kobject.h>
5a0e3ad6 15#include <linux/slab.h>
1da177e4
LT		 16#include <scsi/scsi_tcq.h>
17#include <scsi/scsicam.h>
18#include <scsi/scsi_transport.h>
19#include <scsi/scsi_transport_fc.h>
20
2d70c103
NB		 21#include "qla_target.h"
22
1da177e4
LT		 23/*
24 * Driver version
25 */
26char qla2x00_version_str[40];
27
6a03b4cd
HZ		 28static int apidev_major;
29
1da177e4
LT		 30/*
31 * SRB allocation cache
32 */
e18b890b 33static struct kmem_cache *srb_cachep;
1da177e4 34
a9083016
GM		 35/*
36 * CT6 CTX allocation cache
37 */
38static struct kmem_cache *ctx_cachep;
3ce8866c
SK		 39/*
40 * error level for logging
41 */
42int ql_errlev = ql_log_all;
a9083016 43
fa492630 44static int ql2xenableclass2;
2d70c103
NB		 45module_param(ql2xenableclass2, int, S_IRUGO|S_IRUSR);
46MODULE_PARM_DESC(ql2xenableclass2,
47 "Specify if Class 2 operations are supported from the very "
48 "beginning. Default is 0 - class 2 not supported.");
49
8ae6d9c7 50
1da177e4 51int ql2xlogintimeout = 20;
f2019cb1 52module_param(ql2xlogintimeout, int, S_IRUGO);
1da177e4
LT		 53MODULE_PARM_DESC(ql2xlogintimeout,
54 "Login timeout value in seconds.");
55
a7b61842 56int qlport_down_retry;
f2019cb1 57module_param(qlport_down_retry, int, S_IRUGO);
1da177e4 58MODULE_PARM_DESC(qlport_down_retry,
900d9f98 59 "Maximum number of command retries to a port that returns "
1da177e4
LT		 60 "a PORT-DOWN status.");
61
1da177e4
LT		 62int ql2xplogiabsentdevice;
63module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR);
64MODULE_PARM_DESC(ql2xplogiabsentdevice,
65 "Option to enable PLOGI to devices that are not present after "
900d9f98 66 "a Fabric scan. This is needed for several broken switches. "
1da177e4
LT		 67 "Default is 0 - no PLOGI. 1 - perfom PLOGI.");
68
1da177e4 69int ql2xloginretrycount = 0;
f2019cb1 70module_param(ql2xloginretrycount, int, S_IRUGO);
1da177e4
LT		 71MODULE_PARM_DESC(ql2xloginretrycount,
72 "Specify an alternate value for the NVRAM login retry count.");
73
a7a167bf 74int ql2xallocfwdump = 1;
f2019cb1 75module_param(ql2xallocfwdump, int, S_IRUGO);
a7a167bf
AV		 76MODULE_PARM_DESC(ql2xallocfwdump,
77 "Option to enable allocation of memory for a firmware dump "
78 "during HBA initialization. Memory allocation requirements "
79 "vary by ISP type. Default is 1 - allocate memory.");
80
11010fec 81int ql2xextended_error_logging;
27d94035 82module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
11010fec 83MODULE_PARM_DESC(ql2xextended_error_logging,
3ce8866c
SK		 84 "Option to enable extended error logging,\n"
85 "\t\tDefault is 0 - no logging. 0x40000000 - Module Init & Probe.\n"
86 "\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n"
87 "\t\t0x08000000 - IO tracing. 0x04000000 - DPC Thread.\n"
88 "\t\t0x02000000 - Async events. 0x01000000 - Timer routines.\n"
89 "\t\t0x00800000 - User space. 0x00400000 - Task Management.\n"
90 "\t\t0x00200000 - AER/EEH. 0x00100000 - Multi Q.\n"
91 "\t\t0x00080000 - P3P Specific. 0x00040000 - Virtual Port.\n"
92 "\t\t0x00020000 - Buffer Dump. 0x00010000 - Misc.\n"
29f9f90c
CD		 93 "\t\t0x00008000 - Verbose. 0x00004000 - Target.\n"
94 "\t\t0x00002000 - Target Mgmt. 0x00001000 - Target TMF.\n"
3ce8866c 95 "\t\t0x7fffffff - For enabling all logs, can be too many logs.\n"
cfb0919c
CD		 96 "\t\t0x1e400000 - Preferred value for capturing essential "
97 "debug information (equivalent to old "
98 "ql2xextended_error_logging=1).\n"
3ce8866c 99 "\t\tDo LOGICAL OR of the value to enable more than one level");
0181944f 100
a9083016 101int ql2xshiftctondsd = 6;
f2019cb1 102module_param(ql2xshiftctondsd, int, S_IRUGO);
a9083016
GM		 103MODULE_PARM_DESC(ql2xshiftctondsd,
104 "Set to control shifting of command type processing "
105 "based on total number of SG elements.");
106
7e47e5ca 107int ql2xfdmienable=1;
de187df8 108module_param(ql2xfdmienable, int, S_IRUGO|S_IWUSR);
cca5335c 109MODULE_PARM_DESC(ql2xfdmienable,
7794a5af
FW		 110 "Enables FDMI registrations. "
111 "0 - no FDMI. Default is 1 - perform FDMI.");
cca5335c 112
50280c01
CD		 113#define MAX_Q_DEPTH 32
114static int ql2xmaxqdepth = MAX_Q_DEPTH;
df7baa50
AV		 115module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR);
116MODULE_PARM_DESC(ql2xmaxqdepth,
e92e4a8f
CD		 117 "Maximum queue depth to set for each LUN. "
118 "Default is 32.");
df7baa50 119
9e522cd8
AE		 120int ql2xenabledif = 2;
121module_param(ql2xenabledif, int, S_IRUGO);
bad75002 122MODULE_PARM_DESC(ql2xenabledif,
b97f5d0b
SM		 123 " Enable T10-CRC-DIF:\n"
124 " Default is 2.\n"
125 " 0 -- No DIF Support\n"
126 " 1 -- Enable DIF for all types\n"
127 " 2 -- Enable DIF for all types, except Type 0.\n");
bad75002 128
8cb2049c 129int ql2xenablehba_err_chk = 2;
bad75002
AE		 130module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR);
131MODULE_PARM_DESC(ql2xenablehba_err_chk,
8cb2049c 132 " Enable T10-CRC-DIF Error isolation by HBA:\n"
b97f5d0b 133 " Default is 2.\n"
8cb2049c
AE		 134 " 0 -- Error isolation disabled\n"
135 " 1 -- Error isolation enabled only for DIX Type 0\n"
136 " 2 -- Error isolation enabled for all Types\n");
bad75002 137
e5896bd5 138int ql2xiidmaenable=1;
f2019cb1 139module_param(ql2xiidmaenable, int, S_IRUGO);
e5896bd5
AV		 140MODULE_PARM_DESC(ql2xiidmaenable,
141 "Enables iIDMA settings "
142 "Default is 1 - perform iIDMA. 0 - no iIDMA.");
143
73208dfd 144int ql2xmaxqueues = 1;
f2019cb1 145module_param(ql2xmaxqueues, int, S_IRUGO);
73208dfd
AC		 146MODULE_PARM_DESC(ql2xmaxqueues,
147 "Enables MQ settings "
ae68230c
JP		 148 "Default is 1 for single queue. Set it to number "
149 "of queues in MQ mode.");
68ca949c
AC		 150
151int ql2xmultique_tag;
f2019cb1 152module_param(ql2xmultique_tag, int, S_IRUGO);
68ca949c
AC		 153MODULE_PARM_DESC(ql2xmultique_tag,
154 "Enables CPU affinity settings for the driver "
155 "Default is 0 for no affinity of request and response IO. "
156 "Set it to 1 to turn on the cpu affinity.");
e337d907
AV		 157
158int ql2xfwloadbin;
86e45bf6 159module_param(ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
e337d907 160MODULE_PARM_DESC(ql2xfwloadbin,
7c3df132
SK		 161 "Option to specify location from which to load ISP firmware:.\n"
162 " 2 -- load firmware via the request_firmware() (hotplug).\n"
e337d907
AV		 163 " interface.\n"
164 " 1 -- load firmware from flash.\n"
165 " 0 -- use default semantics.\n");
166
ae97c91e 167int ql2xetsenable;
f2019cb1 168module_param(ql2xetsenable, int, S_IRUGO);
ae97c91e
AV		 169MODULE_PARM_DESC(ql2xetsenable,
170 "Enables firmware ETS burst."
171 "Default is 0 - skip ETS enablement.");
172
6907869d 173int ql2xdbwr = 1;
86e45bf6 174module_param(ql2xdbwr, int, S_IRUGO|S_IWUSR);
a9083016 175MODULE_PARM_DESC(ql2xdbwr,
08de2844
GM		 176 "Option to specify scheme for request queue posting.\n"
177 " 0 -- Regular doorbell.\n"
178 " 1 -- CAMRAM doorbell (faster).\n");
a9083016 179
f4c496c1 180int ql2xtargetreset = 1;
f2019cb1 181module_param(ql2xtargetreset, int, S_IRUGO);
f4c496c1
GM		 182MODULE_PARM_DESC(ql2xtargetreset,
183 "Enable target reset."
184 "Default is 1 - use hw defaults.");
185
4da26e16 186int ql2xgffidenable;
f2019cb1 187module_param(ql2xgffidenable, int, S_IRUGO);
4da26e16
CD		 188MODULE_PARM_DESC(ql2xgffidenable,
189 "Enables GFF_ID checks of port type. "
190 "Default is 0 - Do not use GFF_ID information.");
a9083016 191
3822263e 192int ql2xasynctmfenable;
f2019cb1 193module_param(ql2xasynctmfenable, int, S_IRUGO);
3822263e
MI		 194MODULE_PARM_DESC(ql2xasynctmfenable,
195 "Enables issue of TM IOCBs asynchronously via IOCB mechanism"
196 "Default is 0 - Issue TM IOCBs via mailbox mechanism.");
ed0de87c
GM		 197
198int ql2xdontresethba;
86e45bf6 199module_param(ql2xdontresethba, int, S_IRUGO|S_IWUSR);
ed0de87c 200MODULE_PARM_DESC(ql2xdontresethba,
08de2844
GM		 201 "Option to specify reset behaviour.\n"
202 " 0 (Default) -- Reset on failure.\n"
203 " 1 -- Do not reset on failure.\n");
ed0de87c 204
1abf635d
HR		 205uint64_t ql2xmaxlun = MAX_LUNS;
206module_param(ql2xmaxlun, ullong, S_IRUGO);
82515920
AV		 207MODULE_PARM_DESC(ql2xmaxlun,
208 "Defines the maximum LU number to register with the SCSI "
209 "midlayer. Default is 65535.");
210
08de2844
GM		 211int ql2xmdcapmask = 0x1F;
212module_param(ql2xmdcapmask, int, S_IRUGO);
213MODULE_PARM_DESC(ql2xmdcapmask,
214 "Set the Minidump driver capture mask level. "
6e96fa7b 215 "Default is 0x1F - Can be set to 0x3, 0x7, 0xF, 0x1F, 0x7F.");
08de2844 216
3aadff35 217int ql2xmdenable = 1;
08de2844
GM		 218module_param(ql2xmdenable, int, S_IRUGO);
219MODULE_PARM_DESC(ql2xmdenable,
220 "Enable/disable MiniDump. "
3aadff35
GM		 221 "0 - MiniDump disabled. "
222 "1 (Default) - MiniDump enabled.");
08de2844 223
1da177e4 224/*
fa2a1ce5 225 * SCSI host template entry points
1da177e4
LT		 226 */
227static int qla2xxx_slave_configure(struct scsi_device * device);
f4f051eb 228static int qla2xxx_slave_alloc(struct scsi_device *);
1e99e33a
AV		 229static int qla2xxx_scan_finished(struct Scsi_Host *, unsigned long time);
230static void qla2xxx_scan_start(struct Scsi_Host *);
f4f051eb 231static void qla2xxx_slave_destroy(struct scsi_device *);
f281233d 232static int qla2xxx_queuecommand(struct Scsi_Host *h, struct scsi_cmnd *cmd);
1da177e4
LT		 233static int qla2xxx_eh_abort(struct scsi_cmnd *);
234static int qla2xxx_eh_device_reset(struct scsi_cmnd *);
523ec773 235static int qla2xxx_eh_target_reset(struct scsi_cmnd *);
1da177e4
LT		 236static int qla2xxx_eh_bus_reset(struct scsi_cmnd *);
237static int qla2xxx_eh_host_reset(struct scsi_cmnd *);
1da177e4 238
1a2fbf18 239static void qla2x00_clear_drv_active(struct qla_hw_data *);
3491255e 240static void qla2x00_free_device(scsi_qla_host_t *);
2d5a4c34 241static void qla83xx_disable_laser(scsi_qla_host_t *vha);
ce7e4af7 242
a5326f86 243struct scsi_host_template qla2xxx_driver_template = {
1da177e4 244 .module = THIS_MODULE,
cb63067a 245 .name = QLA2XXX_DRIVER_NAME,
a5326f86 246 .queuecommand = qla2xxx_queuecommand,
fca29703
AV		 247
248 .eh_abort_handler = qla2xxx_eh_abort,
249 .eh_device_reset_handler = qla2xxx_eh_device_reset,
523ec773 250 .eh_target_reset_handler = qla2xxx_eh_target_reset,
fca29703
AV		 251 .eh_bus_reset_handler = qla2xxx_eh_bus_reset,
252 .eh_host_reset_handler = qla2xxx_eh_host_reset,
253
254 .slave_configure = qla2xxx_slave_configure,
255
256 .slave_alloc = qla2xxx_slave_alloc,
257 .slave_destroy = qla2xxx_slave_destroy,
ed677086
AV		 258 .scan_finished = qla2xxx_scan_finished,
259 .scan_start = qla2xxx_scan_start,
db5ed4df 260 .change_queue_depth = scsi_change_queue_depth,
fca29703
AV		 261 .this_id = -1,
262 .cmd_per_lun = 3,
263 .use_clustering = ENABLE_CLUSTERING,
264 .sg_tablesize = SG_ALL,
265
266 .max_sectors = 0xFFFF,
afb046e2 267 .shost_attrs = qla2x00_host_attrs,
2d70c103
NB		 268
269 .supported_mode = MODE_INITIATOR,
2ecb204d 270 .use_blk_tags = 1,
c40ecc12 271 .track_queue_depth = 1,
fca29703
AV		 272};
273
1da177e4 274static struct scsi_transport_template *qla2xxx_transport_template = NULL;
2c3dfe3f 275struct scsi_transport_template *qla2xxx_transport_vport_template = NULL;
1da177e4 276
1da177e4
LT		 277/* TODO Convert to inlines
278 *
279 * Timer routines
280 */
1da177e4 281
2c3dfe3f 282__inline__ void
e315cd28 283qla2x00_start_timer(scsi_qla_host_t *vha, void *func, unsigned long interval)
1da177e4 284{
e315cd28
AC		 285 init_timer(&vha->timer);
286 vha->timer.expires = jiffies + interval * HZ;
287 vha->timer.data = (unsigned long)vha;
288 vha->timer.function = (void (*)(unsigned long))func;
289 add_timer(&vha->timer);
290 vha->timer_active = 1;
1da177e4
LT		 291}
292
293static inline void
e315cd28 294qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval)
1da177e4 295{
a9083016 296 /* Currently used for 82XX only. */
7c3df132
SK		 297 if (vha->device_flags & DFLG_DEV_FAILED) {
298 ql_dbg(ql_dbg_timer, vha, 0x600d,
299 "Device in a failed state, returning.\n");
a9083016 300 return;
7c3df132 301 }
a9083016 302
e315cd28 303 mod_timer(&vha->timer, jiffies + interval * HZ);
1da177e4
LT		 304}
305
a824ebb3 306static __inline__ void
e315cd28 307qla2x00_stop_timer(scsi_qla_host_t *vha)
1da177e4 308{
e315cd28
AC		 309 del_timer_sync(&vha->timer);
310 vha->timer_active = 0;
1da177e4
LT		 311}
312
1da177e4
LT		 313static int qla2x00_do_dpc(void *data);
314
315static void qla2x00_rst_aen(scsi_qla_host_t *);
316
73208dfd
AC		 317static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t,
318 struct req_que **, struct rsp_que **);
e30d1756 319static void qla2x00_free_fw_dump(struct qla_hw_data *);
e315cd28 320static void qla2x00_mem_free(struct qla_hw_data *);
1da177e4 321
1da177e4 322/* -------------------------------------------------------------------------- */
9a347ff4
CD		 323static int qla2x00_alloc_queues(struct qla_hw_data *ha, struct req_que *req,
324 struct rsp_que *rsp)
73208dfd 325{
7c3df132 326 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2afa19a9 327 ha->req_q_map = kzalloc(sizeof(struct req_que *) * ha->max_req_queues,
73208dfd
AC		 328 GFP_KERNEL);
329 if (!ha->req_q_map) {
7c3df132
SK		 330 ql_log(ql_log_fatal, vha, 0x003b,
331 "Unable to allocate memory for request queue ptrs.\n");
73208dfd
AC		 332 goto fail_req_map;
333 }
334
2afa19a9 335 ha->rsp_q_map = kzalloc(sizeof(struct rsp_que *) * ha->max_rsp_queues,
73208dfd
AC		 336 GFP_KERNEL);
337 if (!ha->rsp_q_map) {
7c3df132
SK		 338 ql_log(ql_log_fatal, vha, 0x003c,
339 "Unable to allocate memory for response queue ptrs.\n");
73208dfd
AC		 340 goto fail_rsp_map;
341 }
9a347ff4
CD		 342 /*
343 * Make sure we record at least the request and response queue zero in
344 * case we need to free them if part of the probe fails.
345 */
346 ha->rsp_q_map[0] = rsp;
347 ha->req_q_map[0] = req;
73208dfd
AC		 348 set_bit(0, ha->rsp_qid_map);
349 set_bit(0, ha->req_qid_map);
350 return 1;
351
352fail_rsp_map:
353 kfree(ha->req_q_map);
354 ha->req_q_map = NULL;
355fail_req_map:
356 return -ENOMEM;
357}
358
2afa19a9 359static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req)
73208dfd 360{
8ae6d9c7
GM		 361 if (IS_QLAFX00(ha)) {
362 if (req && req->ring_fx00)
363 dma_free_coherent(&ha->pdev->dev,
364 (req->length_fx00 + 1) * sizeof(request_t),
365 req->ring_fx00, req->dma_fx00);
366 } else if (req && req->ring)
73208dfd
AC		 367 dma_free_coherent(&ha->pdev->dev,
368 (req->length + 1) * sizeof(request_t),
369 req->ring, req->dma);
370
8d93f550
CD		 371 if (req)
372 kfree(req->outstanding_cmds);
373
73208dfd
AC		 374 kfree(req);
375 req = NULL;
376}
377
2afa19a9
AC		 378static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp)
379{
8ae6d9c7
GM		 380 if (IS_QLAFX00(ha)) {
381 if (rsp && rsp->ring)
382 dma_free_coherent(&ha->pdev->dev,
383 (rsp->length_fx00 + 1) * sizeof(request_t),
384 rsp->ring_fx00, rsp->dma_fx00);
385 } else if (rsp && rsp->ring) {
2afa19a9
AC		 386 dma_free_coherent(&ha->pdev->dev,
387 (rsp->length + 1) * sizeof(response_t),
388 rsp->ring, rsp->dma);
8ae6d9c7 389 }
2afa19a9
AC		 390 kfree(rsp);
391 rsp = NULL;
392}
393
73208dfd
AC		 394static void qla2x00_free_queues(struct qla_hw_data *ha)
395{
396 struct req_que *req;
397 struct rsp_que *rsp;
398 int cnt;
399
2afa19a9 400 for (cnt = 0; cnt < ha->max_req_queues; cnt++) {
73208dfd 401 req = ha->req_q_map[cnt];
2afa19a9 402 qla2x00_free_req_que(ha, req);
73208dfd 403 }
73208dfd
AC		 404 kfree(ha->req_q_map);
405 ha->req_q_map = NULL;
2afa19a9
AC		 406
407 for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) {
408 rsp = ha->rsp_q_map[cnt];
409 qla2x00_free_rsp_que(ha, rsp);
410 }
411 kfree(ha->rsp_q_map);
412 ha->rsp_q_map = NULL;
73208dfd
AC		 413}
414
68ca949c
AC		 415static int qla25xx_setup_mode(struct scsi_qla_host *vha)
416{
417 uint16_t options = 0;
418 int ques, req, ret;
419 struct qla_hw_data *ha = vha->hw;
420
7163ea81 421 if (!(ha->fw_attributes & BIT_6)) {
7c3df132
SK		 422 ql_log(ql_log_warn, vha, 0x00d8,
423 "Firmware is not multi-queue capable.\n");
7163ea81
AC		 424 goto fail;
425 }
68ca949c 426 if (ql2xmultique_tag) {
68ca949c
AC		 427 /* create a request queue for IO */
428 options |= BIT_7;
429 req = qla25xx_create_req_que(ha, options, 0, 0, -1,
430 QLA_DEFAULT_QUE_QOS);
431 if (!req) {
7c3df132
SK		 432 ql_log(ql_log_warn, vha, 0x00e0,
433 "Failed to create request queue.\n");
68ca949c
AC		 434 goto fail;
435 }
278274d5 436 ha->wq = alloc_workqueue("qla2xxx_wq", WQ_MEM_RECLAIM, 1);
68ca949c
AC		 437 vha->req = ha->req_q_map[req];
438 options |= BIT_1;
439 for (ques = 1; ques < ha->max_rsp_queues; ques++) {
440 ret = qla25xx_create_rsp_que(ha, options, 0, 0, req);
441 if (!ret) {
7c3df132
SK		 442 ql_log(ql_log_warn, vha, 0x00e8,
443 "Failed to create response queue.\n");
68ca949c
AC		 444 goto fail2;
445 }
446 }
7163ea81 447 ha->flags.cpu_affinity_enabled = 1;
7c3df132 448 ql_dbg(ql_dbg_multiq, vha, 0xc007,
6ef68da7 449 "CPU affinity mode enabled, "
7c3df132
SK		 450 "no. of response queues:%d no. of request queues:%d.\n",
451 ha->max_rsp_queues, ha->max_req_queues);
452 ql_dbg(ql_dbg_init, vha, 0x00e9,
6ef68da7 453 "CPU affinity mode enabled, "
7c3df132
SK		 454 "no. of response queues:%d no. of request queues:%d.\n",
455 ha->max_rsp_queues, ha->max_req_queues);
68ca949c
AC		 456 }
457 return 0;
458fail2:
459 qla25xx_delete_queues(vha);
7163ea81
AC		 460 destroy_workqueue(ha->wq);
461 ha->wq = NULL;
0cd33fcf 462 vha->req = ha->req_q_map[0];
68ca949c
AC		 463fail:
464 ha->mqenable = 0;
7163ea81
AC		 465 kfree(ha->req_q_map);
466 kfree(ha->rsp_q_map);
467 ha->max_req_queues = ha->max_rsp_queues = 1;
68ca949c
AC		 468 return 1;
469}
470
1da177e4 471static char *
e315cd28 472qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str)
1da177e4 473{
e315cd28 474 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 475 static char *pci_bus_modes[] = {
476 "33", "66", "100", "133",
477 };
478 uint16_t pci_bus;
479
480 strcpy(str, "PCI");
481 pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9;
482 if (pci_bus) {
483 strcat(str, "-X (");
484 strcat(str, pci_bus_modes[pci_bus]);
485 } else {
486 pci_bus = (ha->pci_attr & BIT_8) >> 8;
487 strcat(str, " (");
488 strcat(str, pci_bus_modes[pci_bus]);
489 }
490 strcat(str, " MHz)");
491
492 return (str);
493}
494
fca29703 495static char *
e315cd28 496qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str)
fca29703
AV		 497{
498 static char *pci_bus_modes[] = { "33", "66", "100", "133", };
e315cd28 499 struct qla_hw_data *ha = vha->hw;
fca29703 500 uint32_t pci_bus;
fca29703 501
62a276f8 502 if (pci_is_pcie(ha->pdev)) {
fca29703 503 char lwstr[6];
62a276f8 504 uint32_t lstat, lspeed, lwidth;
fca29703 505
62a276f8
BH		 506 pcie_capability_read_dword(ha->pdev, PCI_EXP_LNKCAP, &lstat);
507 lspeed = lstat & PCI_EXP_LNKCAP_SLS;
508 lwidth = (lstat & PCI_EXP_LNKCAP_MLW) >> 4;
fca29703
AV		 509
510 strcpy(str, "PCIe (");
49300af7
SK		 511 switch (lspeed) {
512 case 1:
c87a0d8c 513 strcat(str, "2.5GT/s ");
49300af7
SK		 514 break;
515 case 2:
c87a0d8c 516 strcat(str, "5.0GT/s ");
49300af7
SK		 517 break;
518 case 3:
519 strcat(str, "8.0GT/s ");
520 break;
521 default:
fca29703 522 strcat(str, "<unknown> ");
49300af7
SK		 523 break;
524 }
fca29703
AV		 525 snprintf(lwstr, sizeof(lwstr), "x%d)", lwidth);
526 strcat(str, lwstr);
527
528 return str;
529 }
530
531 strcpy(str, "PCI");
532 pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8;
533 if (pci_bus == 0 || pci_bus == 8) {
534 strcat(str, " (");
535 strcat(str, pci_bus_modes[pci_bus >> 3]);
536 } else {
537 strcat(str, "-X ");
538 if (pci_bus & BIT_2)
539 strcat(str, "Mode 2");
540 else
541 strcat(str, "Mode 1");
542 strcat(str, " (");
543 strcat(str, pci_bus_modes[pci_bus & ~BIT_2]);
544 }
545 strcat(str, " MHz)");
546
547 return str;
548}
549
e5f82ab8 550static char *
df57caba 551qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
1da177e4
LT		 552{
553 char un_str[10];
e315cd28 554 struct qla_hw_data *ha = vha->hw;
fa2a1ce5 555
df57caba
HM		 556 snprintf(str, size, "%d.%02d.%02d ", ha->fw_major_version,
557 ha->fw_minor_version, ha->fw_subminor_version);
1da177e4
LT		 558
559 if (ha->fw_attributes & BIT_9) {
560 strcat(str, "FLX");
561 return (str);
562 }
563
564 switch (ha->fw_attributes & 0xFF) {
565 case 0x7:
566 strcat(str, "EF");
567 break;
568 case 0x17:
569 strcat(str, "TP");
570 break;
571 case 0x37:
572 strcat(str, "IP");
573 break;
574 case 0x77:
575 strcat(str, "VI");
576 break;
577 default:
578 sprintf(un_str, "(%x)", ha->fw_attributes);
579 strcat(str, un_str);
580 break;
581 }
582 if (ha->fw_attributes & 0x100)
583 strcat(str, "X");
584
585 return (str);
586}
587
e5f82ab8 588static char *
df57caba 589qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
fca29703 590{
e315cd28 591 struct qla_hw_data *ha = vha->hw;
f0883ac6 592
df57caba 593 snprintf(str, size, "%d.%02d.%02d (%x)", ha->fw_major_version,
3a03eb79 594 ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes);
fca29703 595 return str;
fca29703
AV		 596}
597
9ba56b95
GM		 598void
599qla2x00_sp_free_dma(void *vha, void *ptr)
fca29703 600{
9ba56b95
GM		 601 srb_t *sp = (srb_t *)ptr;
602 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
603 struct qla_hw_data *ha = sp->fcport->vha->hw;
604 void *ctx = GET_CMD_CTX_SP(sp);
fca29703 605
9ba56b95
GM		 606 if (sp->flags & SRB_DMA_VALID) {
607 scsi_dma_unmap(cmd);
608 sp->flags &= ~SRB_DMA_VALID;
7c3df132 609 }
fca29703 610
9ba56b95
GM		 611 if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
612 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
613 scsi_prot_sg_count(cmd), cmd->sc_data_direction);
614 sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
615 }
616
617 if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
618 /* List assured to be having elements */
f83adb61 619 qla2x00_clean_dsd_pool(ha, sp, NULL);
9ba56b95
GM		 620 sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
621 }
622
623 if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
624 dma_pool_free(ha->dl_dma_pool, ctx,
625 ((struct crc_context *)ctx)->crc_ctx_dma);
626 sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
627 }
628
629 if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
630 struct ct6_dsd *ctx1 = (struct ct6_dsd *)ctx;
fca29703 631
9ba56b95
GM		 632 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd,
633 ctx1->fcp_cmnd_dma);
634 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list);
635 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt;
636 ha->gbl_dsd_avail += ctx1->dsd_use_cnt;
637 mempool_free(ctx1, ha->ctx_mempool);
638 ctx1 = NULL;
639 }
640
641 CMD_SP(cmd) = NULL;
b00ee7d7 642 qla2x00_rel_sp(sp->fcport->vha, sp);
9ba56b95
GM		 643}
644
14b06808 645static void
9ba56b95
GM		 646qla2x00_sp_compl(void *data, void *ptr, int res)
647{
648 struct qla_hw_data *ha = (struct qla_hw_data *)data;
649 srb_t *sp = (srb_t *)ptr;
650 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
651
652 cmd->result = res;
653
654 if (atomic_read(&sp->ref_count) == 0) {
655 ql_dbg(ql_dbg_io, sp->fcport->vha, 0x3015,
656 "SP reference-count to ZERO -- sp=%p cmd=%p.\n",
657 sp, GET_CMD_SP(sp));
658 if (ql2xextended_error_logging & ql_dbg_io)
659 BUG();
660 return;
661 }
662 if (!atomic_dec_and_test(&sp->ref_count))
663 return;
664
665 qla2x00_sp_free_dma(ha, sp);
666 cmd->scsi_done(cmd);
fca29703
AV		 667}
668
8ae6d9c7
GM		 669/* If we are SP1 here, we need to still take and release the host_lock as SP1
670 * does not have the changes necessary to avoid taking host->host_lock.
671 */
1da177e4 672static int
f5e3e40b 673qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
fca29703 674{
134ae078 675 scsi_qla_host_t *vha = shost_priv(host);
fca29703 676 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
19a7b4ae 677 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
e315cd28
AC		 678 struct qla_hw_data *ha = vha->hw;
679 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
fca29703
AV		 680 srb_t *sp;
681 int rval;
682
85880801 683 if (ha->flags.eeh_busy) {
7c3df132 684 if (ha->flags.pci_channel_io_perm_failure) {
5f28d2d7 685 ql_dbg(ql_dbg_aer, vha, 0x9010,
7c3df132
SK		 686 "PCI Channel IO permanent failure, exiting "
687 "cmd=%p.\n", cmd);
b9b12f73 688 cmd->result = DID_NO_CONNECT << 16;
7c3df132 689 } else {
5f28d2d7 690 ql_dbg(ql_dbg_aer, vha, 0x9011,
7c3df132 691 "EEH_Busy, Requeuing the cmd=%p.\n", cmd);
85880801 692 cmd->result = DID_REQUEUE << 16;
7c3df132 693 }
14e660e6
SJ		 694 goto qc24_fail_command;
695 }
696
19a7b4ae
JSEC		 697 rval = fc_remote_port_chkready(rport);
698 if (rval) {
699 cmd->result = rval;
5f28d2d7 700 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3003,
7c3df132
SK		 701 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
702 cmd, rval);
fca29703
AV		 703 goto qc24_fail_command;
704 }
705
bad75002
AE		 706 if (!vha->flags.difdix_supported &&
707 scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) {
7c3df132
SK		 708 ql_dbg(ql_dbg_io, vha, 0x3004,
709 "DIF Cap not reg, fail DIF capable cmd's:%p.\n",
710 cmd);
bad75002
AE		 711 cmd->result = DID_NO_CONNECT << 16;
712 goto qc24_fail_command;
713 }
aa651be8
CD		 714
715 if (!fcport) {
716 cmd->result = DID_NO_CONNECT << 16;
717 goto qc24_fail_command;
718 }
719
fca29703
AV		 720 if (atomic_read(&fcport->state) != FCS_ONLINE) {
721 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
38170fa8 722 atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
7c3df132
SK		 723 ql_dbg(ql_dbg_io, vha, 0x3005,
724 "Returning DNC, fcport_state=%d loop_state=%d.\n",
725 atomic_read(&fcport->state),
726 atomic_read(&base_vha->loop_state));
fca29703
AV		 727 cmd->result = DID_NO_CONNECT << 16;
728 goto qc24_fail_command;
729 }
7b594131 730 goto qc24_target_busy;
fca29703
AV		 731 }
732
e05fe292
CD		 733 /*
734 * Return target busy if we've received a non-zero retry_delay_timer
735 * in a FCP_RSP.
736 */
975f7d46
BP		 737 if (fcport->retry_delay_timestamp == 0) {
738 /* retry delay not set */
739 } else if (time_after(jiffies, fcport->retry_delay_timestamp))
e05fe292
CD		 740 fcport->retry_delay_timestamp = 0;
741 else
742 goto qc24_target_busy;
743
b00ee7d7 744 sp = qla2x00_get_sp(vha, fcport, GFP_ATOMIC);
50280c01 745 if (!sp)
f5e3e40b 746 goto qc24_host_busy;
fca29703 747
9ba56b95
GM		 748 sp->u.scmd.cmd = cmd;
749 sp->type = SRB_SCSI_CMD;
750 atomic_set(&sp->ref_count, 1);
751 CMD_SP(cmd) = (void *)sp;
752 sp->free = qla2x00_sp_free_dma;
753 sp->done = qla2x00_sp_compl;
754
e315cd28 755 rval = ha->isp_ops->start_scsi(sp);
7c3df132 756 if (rval != QLA_SUCCESS) {
53016ed3 757 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3013,
7c3df132 758 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
fca29703 759 goto qc24_host_busy_free_sp;
7c3df132 760 }
fca29703 761
fca29703
AV		 762 return 0;
763
764qc24_host_busy_free_sp:
9ba56b95 765 qla2x00_sp_free_dma(ha, sp);
fca29703 766
f5e3e40b 767qc24_host_busy:
fca29703
AV		 768 return SCSI_MLQUEUE_HOST_BUSY;
769
7b594131
MC		 770qc24_target_busy:
771 return SCSI_MLQUEUE_TARGET_BUSY;
772
fca29703 773qc24_fail_command:
f5e3e40b 774 cmd->scsi_done(cmd);
fca29703
AV		 775
776 return 0;
777}
778
1da177e4
LT		 779/*
780 * qla2x00_eh_wait_on_command
781 * Waits for the command to be returned by the Firmware for some
782 * max time.
783 *
784 * Input:
1da177e4 785 * cmd = Scsi Command to wait on.
1da177e4
LT		 786 *
787 * Return:
788 * Not Found : 0
789 * Found : 1
790 */
791static int
e315cd28 792qla2x00_eh_wait_on_command(struct scsi_cmnd *cmd)
1da177e4 793{
fe74c71f 794#define ABORT_POLLING_PERIOD 1000
478c3b03 795#define ABORT_WAIT_ITER ((2 * 1000) / (ABORT_POLLING_PERIOD))
f4f051eb 796 unsigned long wait_iter = ABORT_WAIT_ITER;
85880801
AV		 797 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
798 struct qla_hw_data *ha = vha->hw;
f4f051eb 799 int ret = QLA_SUCCESS;
1da177e4 800
85880801 801 if (unlikely(pci_channel_offline(ha->pdev)) || ha->flags.eeh_busy) {
7c3df132
SK		 802 ql_dbg(ql_dbg_taskm, vha, 0x8005,
803 "Return:eh_wait.\n");
85880801
AV		 804 return ret;
805 }
806
d970432c 807 while (CMD_SP(cmd) && wait_iter--) {
fe74c71f 808 msleep(ABORT_POLLING_PERIOD);
f4f051eb 809 }
810 if (CMD_SP(cmd))
811 ret = QLA_FUNCTION_FAILED;
1da177e4 812
f4f051eb 813 return ret;
1da177e4
LT		 814}
815
816/*
817 * qla2x00_wait_for_hba_online
fa2a1ce5 818 * Wait till the HBA is online after going through
1da177e4
LT		 819 * <= MAX_RETRIES_OF_ISP_ABORT or
820 * finally HBA is disabled ie marked offline
821 *
822 * Input:
823 * ha - pointer to host adapter structure
fa2a1ce5
AV		 824 *
825 * Note:
1da177e4
LT		 826 * Does context switching-Release SPIN_LOCK
827 * (if any) before calling this routine.
828 *
829 * Return:
830 * Success (Adapter is online) : 0
831 * Failed (Adapter is offline/disabled) : 1
832 */
854165f4 833int
e315cd28 834qla2x00_wait_for_hba_online(scsi_qla_host_t *vha)
1da177e4 835{
fca29703
AV		 836 int return_status;
837 unsigned long wait_online;
e315cd28
AC		 838 struct qla_hw_data *ha = vha->hw;
839 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4 840
fa2a1ce5 841 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ);
e315cd28
AC		 842 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
843 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
844 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
845 ha->dpc_active) && time_before(jiffies, wait_online)) {
1da177e4
LT		 846
847 msleep(1000);
848 }
e315cd28 849 if (base_vha->flags.online)
fa2a1ce5 850 return_status = QLA_SUCCESS;
1da177e4
LT		 851 else
852 return_status = QLA_FUNCTION_FAILED;
853
1da177e4
LT		 854 return (return_status);
855}
856
86fbee86 857/*
638a1a01
SC		 858 * qla2x00_wait_for_hba_ready
859 * Wait till the HBA is ready before doing driver unload
86fbee86
LC		 860 *
861 * Input:
862 * ha - pointer to host adapter structure
863 *
864 * Note:
865 * Does context switching-Release SPIN_LOCK
866 * (if any) before calling this routine.
867 *
86fbee86 868 */
638a1a01
SC		 869static void
870qla2x00_wait_for_hba_ready(scsi_qla_host_t *vha)
86fbee86 871{
86fbee86 872 struct qla_hw_data *ha = vha->hw;
86fbee86 873
9d35894d
SC		 874 while (((qla2x00_reset_active(vha)) || ha->dpc_active ||
875 ha->flags.mbox_busy) ||
876 test_bit(FX00_RESET_RECOVERY, &vha->dpc_flags) ||
877 test_bit(FX00_TARGET_SCAN, &vha->dpc_flags))
86fbee86 878 msleep(1000);
86fbee86
LC		 879}
880
2533cf67
LC		 881int
882qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha)
883{
884 int return_status;
885 unsigned long wait_reset;
886 struct qla_hw_data *ha = vha->hw;
887 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
888
889 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ);
890 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
891 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
892 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
893 ha->dpc_active) && time_before(jiffies, wait_reset)) {
894
895 msleep(1000);
896
897 if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) &&
898 ha->flags.chip_reset_done)
899 break;
900 }
901 if (ha->flags.chip_reset_done)
902 return_status = QLA_SUCCESS;
903 else
904 return_status = QLA_FUNCTION_FAILED;
905
906 return return_status;
907}
908
083a469d
GM		 909static void
910sp_get(struct srb *sp)
911{
912 atomic_inc(&sp->ref_count);
913}
914
1da177e4
LT		 915/**************************************************************************
916* qla2xxx_eh_abort
917*
918* Description:
919* The abort function will abort the specified command.
920*
921* Input:
922* cmd = Linux SCSI command packet to be aborted.
923*
924* Returns:
925* Either SUCCESS or FAILED.
926*
927* Note:
2ea00202 928* Only return FAILED if command not returned by firmware.
1da177e4 929**************************************************************************/
e5f82ab8 930static int
1da177e4
LT		 931qla2xxx_eh_abort(struct scsi_cmnd *cmd)
932{
e315cd28 933 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
f4f051eb 934 srb_t *sp;
4e98d3b8 935 int ret;
9cb78c16
HR		 936 unsigned int id;
937 uint64_t lun;
18e144d3 938 unsigned long flags;
f934c9d0 939 int rval, wait = 0;
e315cd28 940 struct qla_hw_data *ha = vha->hw;
1da177e4 941
f4f051eb 942 if (!CMD_SP(cmd))
2ea00202 943 return SUCCESS;
1da177e4 944
4e98d3b8
AV		 945 ret = fc_block_scsi_eh(cmd);
946 if (ret != 0)
947 return ret;
948 ret = SUCCESS;
949
f4f051eb 950 id = cmd->device->id;
951 lun = cmd->device->lun;
1da177e4 952
e315cd28 953 spin_lock_irqsave(&ha->hardware_lock, flags);
170babc3
MC		 954 sp = (srb_t *) CMD_SP(cmd);
955 if (!sp) {
956 spin_unlock_irqrestore(&ha->hardware_lock, flags);
957 return SUCCESS;
958 }
1da177e4 959
7c3df132 960 ql_dbg(ql_dbg_taskm, vha, 0x8002,
9cb78c16 961 "Aborting from RISC nexus=%ld:%d:%llu sp=%p cmd=%p\n",
cfb0919c 962 vha->host_no, id, lun, sp, cmd);
17d98630 963
170babc3
MC		 964 /* Get a reference to the sp and drop the lock.*/
965 sp_get(sp);
083a469d 966
e315cd28 967 spin_unlock_irqrestore(&ha->hardware_lock, flags);
f934c9d0
CD		 968 rval = ha->isp_ops->abort_command(sp);
969 if (rval) {
970 if (rval == QLA_FUNCTION_PARAMETER_ERROR) {
971 /*
972 * Decrement the ref_count since we can't find the
973 * command
974 */
975 atomic_dec(&sp->ref_count);
976 ret = SUCCESS;
977 } else
978 ret = FAILED;
979
7c3df132 980 ql_dbg(ql_dbg_taskm, vha, 0x8003,
f934c9d0 981 "Abort command mbx failed cmd=%p, rval=%x.\n", cmd, rval);
170babc3 982 } else {
7c3df132 983 ql_dbg(ql_dbg_taskm, vha, 0x8004,
cfb0919c 984 "Abort command mbx success cmd=%p.\n", cmd);
170babc3
MC		 985 wait = 1;
986 }
75942064
SK		 987
988 spin_lock_irqsave(&ha->hardware_lock, flags);
f934c9d0
CD		 989 /*
990 * Clear the slot in the oustanding_cmds array if we can't find the
991 * command to reclaim the resources.
992 */
993 if (rval == QLA_FUNCTION_PARAMETER_ERROR)
994 vha->req->outstanding_cmds[sp->handle] = NULL;
9ba56b95 995 sp->done(ha, sp, 0);
75942064 996 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1da177e4 997
bc91ade9
CD		 998 /* Did the command return during mailbox execution? */
999 if (ret == FAILED && !CMD_SP(cmd))
1000 ret = SUCCESS;
1001
f4f051eb 1002 /* Wait for the command to be returned. */
2ea00202 1003 if (wait) {
e315cd28 1004 if (qla2x00_eh_wait_on_command(cmd) != QLA_SUCCESS) {
7c3df132 1005 ql_log(ql_log_warn, vha, 0x8006,
cfb0919c 1006 "Abort handler timed out cmd=%p.\n", cmd);
2ea00202 1007 ret = FAILED;
f4f051eb 1008 }
1da177e4 1009 }
1da177e4 1010
7c3df132 1011 ql_log(ql_log_info, vha, 0x801c,
9cb78c16 1012 "Abort command issued nexus=%ld:%d:%llu -- %d %x.\n",
cfb0919c 1013 vha->host_no, id, lun, wait, ret);
1da177e4 1014
f4f051eb 1015 return ret;
1016}
1da177e4 1017
4d78c973 1018int
e315cd28 1019qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t,
9cb78c16 1020 uint64_t l, enum nexus_wait_type type)
f4f051eb 1021{
17d98630 1022 int cnt, match, status;
18e144d3 1023 unsigned long flags;
e315cd28 1024 struct qla_hw_data *ha = vha->hw;
73208dfd 1025 struct req_que *req;
4d78c973 1026 srb_t *sp;
9ba56b95 1027 struct scsi_cmnd *cmd;
1da177e4 1028
523ec773 1029 status = QLA_SUCCESS;
17d98630 1030
e315cd28 1031 spin_lock_irqsave(&ha->hardware_lock, flags);
67c2e93a 1032 req = vha->req;
17d98630 1033 for (cnt = 1; status == QLA_SUCCESS &&
8d93f550 1034 cnt < req->num_outstanding_cmds; cnt++) {
17d98630
AC		 1035 sp = req->outstanding_cmds[cnt];
1036 if (!sp)
523ec773 1037 continue;
9ba56b95 1038 if (sp->type != SRB_SCSI_CMD)
cf53b069 1039 continue;
17d98630
AC		 1040 if (vha->vp_idx != sp->fcport->vha->vp_idx)
1041 continue;
1042 match = 0;
9ba56b95 1043 cmd = GET_CMD_SP(sp);
17d98630
AC		 1044 switch (type) {
1045 case WAIT_HOST:
1046 match = 1;
1047 break;
1048 case WAIT_TARGET:
9ba56b95 1049 match = cmd->device->id == t;
17d98630
AC		 1050 break;
1051 case WAIT_LUN:
9ba56b95
GM		 1052 match = (cmd->device->id == t &&
1053 cmd->device->lun == l);
17d98630 1054 break;
73208dfd 1055 }
17d98630
AC		 1056 if (!match)
1057 continue;
1058
1059 spin_unlock_irqrestore(&ha->hardware_lock, flags);
9ba56b95 1060 status = qla2x00_eh_wait_on_command(cmd);
17d98630 1061 spin_lock_irqsave(&ha->hardware_lock, flags);
1da177e4 1062 }
e315cd28 1063 spin_unlock_irqrestore(&ha->hardware_lock, flags);
523ec773
AV		 1064
1065 return status;
1da177e4
LT		 1066}
1067
523ec773
AV		 1068static char *reset_errors[] = {
1069 "HBA not online",
1070 "HBA not ready",
1071 "Task management failed",
1072 "Waiting for command completions",
1073};
1da177e4 1074
e5f82ab8 1075static int
523ec773 1076__qla2xxx_eh_generic_reset(char *name, enum nexus_wait_type type,
9cb78c16 1077 struct scsi_cmnd *cmd, int (*do_reset)(struct fc_port *, uint64_t, int))
1da177e4 1078{
e315cd28 1079 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
bdf79621 1080 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
523ec773 1081 int err;
1da177e4 1082
7c3df132 1083 if (!fcport) {
523ec773 1084 return FAILED;
7c3df132 1085 }
1da177e4 1086
4e98d3b8
AV		 1087 err = fc_block_scsi_eh(cmd);
1088 if (err != 0)
1089 return err;
1090
7c3df132 1091 ql_log(ql_log_info, vha, 0x8009,
9cb78c16 1092 "%s RESET ISSUED nexus=%ld:%d:%llu cmd=%p.\n", name, vha->host_no,
7c3df132 1093 cmd->device->id, cmd->device->lun, cmd);
1da177e4 1094
523ec773 1095 err = 0;
7c3df132
SK		 1096 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1097 ql_log(ql_log_warn, vha, 0x800a,
1098 "Wait for hba online failed for cmd=%p.\n", cmd);
523ec773 1099 goto eh_reset_failed;
7c3df132 1100 }
523ec773 1101 err = 2;
2afa19a9 1102 if (do_reset(fcport, cmd->device->lun, cmd->request->cpu + 1)
7c3df132
SK		 1103 != QLA_SUCCESS) {
1104 ql_log(ql_log_warn, vha, 0x800c,
1105 "do_reset failed for cmd=%p.\n", cmd);
523ec773 1106 goto eh_reset_failed;
7c3df132 1107 }
523ec773 1108 err = 3;
e315cd28 1109 if (qla2x00_eh_wait_for_pending_commands(vha, cmd->device->id,
7c3df132
SK		 1110 cmd->device->lun, type) != QLA_SUCCESS) {
1111 ql_log(ql_log_warn, vha, 0x800d,
d6a03581 1112 "wait for pending cmds failed for cmd=%p.\n", cmd);
523ec773 1113 goto eh_reset_failed;
7c3df132 1114 }
523ec773 1115
7c3df132 1116 ql_log(ql_log_info, vha, 0x800e,
9cb78c16 1117 "%s RESET SUCCEEDED nexus:%ld:%d:%llu cmd=%p.\n", name,
cfb0919c 1118 vha->host_no, cmd->device->id, cmd->device->lun, cmd);
523ec773
AV		 1119
1120 return SUCCESS;
1121
4d78c973 1122eh_reset_failed:
7c3df132 1123 ql_log(ql_log_info, vha, 0x800f,
9cb78c16 1124 "%s RESET FAILED: %s nexus=%ld:%d:%llu cmd=%p.\n", name,
cfb0919c
CD		 1125 reset_errors[err], vha->host_no, cmd->device->id, cmd->device->lun,
1126 cmd);
523ec773
AV		 1127 return FAILED;
1128}
1da177e4 1129
523ec773
AV		 1130static int
1131qla2xxx_eh_device_reset(struct scsi_cmnd *cmd)
1132{
e315cd28
AC		 1133 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1134 struct qla_hw_data *ha = vha->hw;
1da177e4 1135
523ec773
AV		 1136 return __qla2xxx_eh_generic_reset("DEVICE", WAIT_LUN, cmd,
1137 ha->isp_ops->lun_reset);
1da177e4
LT		 1138}
1139
1da177e4 1140static int
523ec773 1141qla2xxx_eh_target_reset(struct scsi_cmnd *cmd)
1da177e4 1142{
e315cd28
AC		 1143 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1144 struct qla_hw_data *ha = vha->hw;
1da177e4 1145
523ec773
AV		 1146 return __qla2xxx_eh_generic_reset("TARGET", WAIT_TARGET, cmd,
1147 ha->isp_ops->target_reset);
1da177e4
LT		 1148}
1149
1da177e4
LT		 1150/**************************************************************************
1151* qla2xxx_eh_bus_reset
1152*
1153* Description:
1154* The bus reset function will reset the bus and abort any executing
1155* commands.
1156*
1157* Input:
1158* cmd = Linux SCSI command packet of the command that cause the
1159* bus reset.
1160*
1161* Returns:
1162* SUCCESS/FAILURE (defined as macro in scsi.h).
1163*
1164**************************************************************************/
e5f82ab8 1165static int
1da177e4
LT		 1166qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd)
1167{
e315cd28 1168 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
bdf79621 1169 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
2c3dfe3f 1170 int ret = FAILED;
9cb78c16
HR		 1171 unsigned int id;
1172 uint64_t lun;
f4f051eb 1173
f4f051eb 1174 id = cmd->device->id;
1175 lun = cmd->device->lun;
1da177e4 1176
7c3df132 1177 if (!fcport) {
f4f051eb 1178 return ret;
7c3df132 1179 }
1da177e4 1180
4e98d3b8
AV		 1181 ret = fc_block_scsi_eh(cmd);
1182 if (ret != 0)
1183 return ret;
1184 ret = FAILED;
1185
7c3df132 1186 ql_log(ql_log_info, vha, 0x8012,
9cb78c16 1187 "BUS RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun);
1da177e4 1188
e315cd28 1189 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
7c3df132
SK		 1190 ql_log(ql_log_fatal, vha, 0x8013,
1191 "Wait for hba online failed board disabled.\n");
f4f051eb 1192 goto eh_bus_reset_done;
1da177e4
LT		 1193 }
1194
ad537689
SK		 1195 if (qla2x00_loop_reset(vha) == QLA_SUCCESS)
1196 ret = SUCCESS;
1197
f4f051eb 1198 if (ret == FAILED)
1199 goto eh_bus_reset_done;
1da177e4 1200
9a41a62b 1201 /* Flush outstanding commands. */
4d78c973 1202 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) !=
7c3df132
SK		 1203 QLA_SUCCESS) {
1204 ql_log(ql_log_warn, vha, 0x8014,
1205 "Wait for pending commands failed.\n");
9a41a62b 1206 ret = FAILED;
7c3df132 1207 }
1da177e4 1208
f4f051eb 1209eh_bus_reset_done:
7c3df132 1210 ql_log(ql_log_warn, vha, 0x802b,
9cb78c16 1211 "BUS RESET %s nexus=%ld:%d:%llu.\n",
d6a03581 1212 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1da177e4 1213
f4f051eb 1214 return ret;
1da177e4
LT		 1215}
1216
1217/**************************************************************************
1218* qla2xxx_eh_host_reset
1219*
1220* Description:
1221* The reset function will reset the Adapter.
1222*
1223* Input:
1224* cmd = Linux SCSI command packet of the command that cause the
1225* adapter reset.
1226*
1227* Returns:
1228* Either SUCCESS or FAILED.
1229*
1230* Note:
1231**************************************************************************/
e5f82ab8 1232static int
1da177e4
LT		 1233qla2xxx_eh_host_reset(struct scsi_cmnd *cmd)
1234{
e315cd28 1235 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
e315cd28 1236 struct qla_hw_data *ha = vha->hw;
2c3dfe3f 1237 int ret = FAILED;
9cb78c16
HR		 1238 unsigned int id;
1239 uint64_t lun;
e315cd28 1240 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4 1241
f4f051eb 1242 id = cmd->device->id;
1243 lun = cmd->device->lun;
f4f051eb 1244
7c3df132 1245 ql_log(ql_log_info, vha, 0x8018,
9cb78c16 1246 "ADAPTER RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun);
1da177e4 1247
63ee7072
CD		 1248 /*
1249 * No point in issuing another reset if one is active. Also do not
1250 * attempt a reset if we are updating flash.
1251 */
1252 if (qla2x00_reset_active(vha) || ha->optrom_state != QLA_SWAITING)
f4f051eb 1253 goto eh_host_reset_lock;
1da177e4 1254
e315cd28
AC		 1255 if (vha != base_vha) {
1256 if (qla2x00_vp_abort_isp(vha))
f4f051eb 1257 goto eh_host_reset_lock;
e315cd28 1258 } else {
7ec0effd 1259 if (IS_P3P_TYPE(vha->hw)) {
a9083016
GM		 1260 if (!qla82xx_fcoe_ctx_reset(vha)) {
1261 /* Ctx reset success */
1262 ret = SUCCESS;
1263 goto eh_host_reset_lock;
1264 }
1265 /* fall thru if ctx reset failed */
1266 }
68ca949c
AC		 1267 if (ha->wq)
1268 flush_workqueue(ha->wq);
1269
e315cd28 1270 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
a9083016 1271 if (ha->isp_ops->abort_isp(base_vha)) {
e315cd28
AC		 1272 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1273 /* failed. schedule dpc to try */
1274 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
1275
7c3df132
SK		 1276 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1277 ql_log(ql_log_warn, vha, 0x802a,
1278 "wait for hba online failed.\n");
e315cd28 1279 goto eh_host_reset_lock;
7c3df132 1280 }
e315cd28
AC		 1281 }
1282 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
fa2a1ce5 1283 }
1da177e4 1284
e315cd28 1285 /* Waiting for command to be returned to OS.*/
4d78c973 1286 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) ==
e315cd28 1287 QLA_SUCCESS)
f4f051eb 1288 ret = SUCCESS;
1da177e4 1289
f4f051eb 1290eh_host_reset_lock:
cfb0919c 1291 ql_log(ql_log_info, vha, 0x8017,
9cb78c16 1292 "ADAPTER RESET %s nexus=%ld:%d:%llu.\n",
cfb0919c 1293 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1da177e4 1294
f4f051eb 1295 return ret;
1296}
1da177e4
LT		 1297
1298/*
1299* qla2x00_loop_reset
1300* Issue loop reset.
1301*
1302* Input:
1303* ha = adapter block pointer.
1304*
1305* Returns:
1306* 0 = success
1307*/
a4722cf2 1308int
e315cd28 1309qla2x00_loop_reset(scsi_qla_host_t *vha)
1da177e4 1310{
0c8c39af 1311 int ret;
bdf79621 1312 struct fc_port *fcport;
e315cd28 1313 struct qla_hw_data *ha = vha->hw;
1da177e4 1314
5854771e
AB		 1315 if (IS_QLAFX00(ha)) {
1316 return qlafx00_loop_reset(vha);
1317 }
1318
f4c496c1 1319 if (ql2xtargetreset == 1 && ha->flags.enable_target_reset) {
55e5ed27
AV		 1320 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1321 if (fcport->port_type != FCT_TARGET)
1322 continue;
1323
1324 ret = ha->isp_ops->target_reset(fcport, 0, 0);
1325 if (ret != QLA_SUCCESS) {
7c3df132 1326 ql_dbg(ql_dbg_taskm, vha, 0x802c,
5854771e 1327 "Bus Reset failed: Reset=%d "
7c3df132 1328 "d_id=%x.\n", ret, fcport->d_id.b24);
55e5ed27
AV		 1329 }
1330 }
1331 }
1332
8ae6d9c7 1333
6246b8a1 1334 if (ha->flags.enable_lip_full_login && !IS_CNA_CAPABLE(ha)) {
0b7e7c53
AV		 1335 atomic_set(&vha->loop_state, LOOP_DOWN);
1336 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
1337 qla2x00_mark_all_devices_lost(vha, 0);
e315cd28 1338 ret = qla2x00_full_login_lip(vha);
0c8c39af 1339 if (ret != QLA_SUCCESS) {
7c3df132
SK		 1340 ql_dbg(ql_dbg_taskm, vha, 0x802d,
1341 "full_login_lip=%d.\n", ret);
749af3d5 1342 }
0c8c39af
AV		 1343 }
1344
0d6e61bc 1345 if (ha->flags.enable_lip_reset) {
e315cd28 1346 ret = qla2x00_lip_reset(vha);
ad537689 1347 if (ret != QLA_SUCCESS)
7c3df132
SK		 1348 ql_dbg(ql_dbg_taskm, vha, 0x802e,
1349 "lip_reset failed (%d).\n", ret);
1da177e4
LT		 1350 }
1351
1da177e4 1352 /* Issue marker command only when we are going to start the I/O */
e315cd28 1353 vha->marker_needed = 1;
1da177e4 1354
0c8c39af 1355 return QLA_SUCCESS;
1da177e4
LT		 1356}
1357
df4bf0bb 1358void
e315cd28 1359qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res)
df4bf0bb 1360{
73208dfd 1361 int que, cnt;
df4bf0bb
AV		 1362 unsigned long flags;
1363 srb_t *sp;
e315cd28 1364 struct qla_hw_data *ha = vha->hw;
73208dfd 1365 struct req_que *req;
df4bf0bb 1366
c0cb4496
AE		 1367 qlt_host_reset_handler(ha);
1368
df4bf0bb 1369 spin_lock_irqsave(&ha->hardware_lock, flags);
2afa19a9 1370 for (que = 0; que < ha->max_req_queues; que++) {
29bdccbe 1371 req = ha->req_q_map[que];
73208dfd
AC		 1372 if (!req)
1373 continue;
8d93f550
CD		 1374 if (!req->outstanding_cmds)
1375 continue;
1376 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) {
73208dfd 1377 sp = req->outstanding_cmds[cnt];
e612d465 1378 if (sp) {
73208dfd 1379 req->outstanding_cmds[cnt] = NULL;
9ba56b95 1380 sp->done(vha, sp, res);
73208dfd 1381 }
df4bf0bb
AV		 1382 }
1383 }
1384 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1385}
1386
f4f051eb 1387static int
1388qla2xxx_slave_alloc(struct scsi_device *sdev)
1da177e4 1389{
bdf79621 1390 struct fc_rport *rport = starget_to_rport(scsi_target(sdev));
1da177e4 1391
19a7b4ae 1392 if (!rport || fc_remote_port_chkready(rport))
f4f051eb 1393 return -ENXIO;
bdf79621 1394
19a7b4ae 1395 sdev->hostdata = *(fc_port_t **)rport->dd_data;
1da177e4 1396
f4f051eb 1397 return 0;
1398}
1da177e4 1399
f4f051eb 1400static int
1401qla2xxx_slave_configure(struct scsi_device *sdev)
1402{
e315cd28 1403 scsi_qla_host_t *vha = shost_priv(sdev->host);
2afa19a9 1404 struct req_que *req = vha->req;
8482e118 1405
9e522cd8
AE		 1406 if (IS_T10_PI_CAPABLE(vha->hw))
1407 blk_queue_update_dma_alignment(sdev->request_queue, 0x7);
1408
db5ed4df 1409 scsi_change_queue_depth(sdev, req->max_q_depth);
f4f051eb 1410 return 0;
1411}
1da177e4 1412
f4f051eb 1413static void
1414qla2xxx_slave_destroy(struct scsi_device *sdev)
1415{
1416 sdev->hostdata = NULL;
1da177e4
LT		 1417}
1418
1419/**
1420 * qla2x00_config_dma_addressing() - Configure OS DMA addressing method.
1421 * @ha: HA context
1422 *
1423 * At exit, the @ha's flags.enable_64bit_addressing set to indicated
1424 * supported addressing method.
1425 */
1426static void
53303c42 1427qla2x00_config_dma_addressing(struct qla_hw_data *ha)
1da177e4 1428{
7524f9b9 1429 /* Assume a 32bit DMA mask. */
1da177e4 1430 ha->flags.enable_64bit_addressing = 0;
1da177e4 1431
6a35528a 1432 if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) {
7524f9b9
AV		 1433 /* Any upper-dword bits set? */
1434 if (MSD(dma_get_required_mask(&ha->pdev->dev)) &&
6a35528a 1435 !pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(64))) {
7524f9b9 1436 /* Ok, a 64bit DMA mask is applicable. */
1da177e4 1437 ha->flags.enable_64bit_addressing = 1;
fd34f556
AV		 1438 ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64;
1439 ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64;
7524f9b9 1440 return;
1da177e4 1441 }
1da177e4 1442 }
7524f9b9 1443
284901a9
YH		 1444 dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32));
1445 pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(32));
1da177e4
LT		 1446}
1447
fd34f556 1448static void
e315cd28 1449qla2x00_enable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1450{
1451 unsigned long flags = 0;
1452 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1453
1454 spin_lock_irqsave(&ha->hardware_lock, flags);
1455 ha->interrupts_on = 1;
1456 /* enable risc and host interrupts */
1457 WRT_REG_WORD(&reg->ictrl, ICR_EN_INT | ICR_EN_RISC);
1458 RD_REG_WORD(&reg->ictrl);
1459 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1460
1461}
1462
1463static void
e315cd28 1464qla2x00_disable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1465{
1466 unsigned long flags = 0;
1467 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1468
1469 spin_lock_irqsave(&ha->hardware_lock, flags);
1470 ha->interrupts_on = 0;
1471 /* disable risc and host interrupts */
1472 WRT_REG_WORD(&reg->ictrl, 0);
1473 RD_REG_WORD(&reg->ictrl);
1474 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1475}
1476
1477static void
e315cd28 1478qla24xx_enable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1479{
1480 unsigned long flags = 0;
1481 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1482
1483 spin_lock_irqsave(&ha->hardware_lock, flags);
1484 ha->interrupts_on = 1;
1485 WRT_REG_DWORD(&reg->ictrl, ICRX_EN_RISC_INT);
1486 RD_REG_DWORD(&reg->ictrl);
1487 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1488}
1489
1490static void
e315cd28 1491qla24xx_disable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1492{
1493 unsigned long flags = 0;
1494 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1495
124f85e6
AV		 1496 if (IS_NOPOLLING_TYPE(ha))
1497 return;
fd34f556
AV		 1498 spin_lock_irqsave(&ha->hardware_lock, flags);
1499 ha->interrupts_on = 0;
1500 WRT_REG_DWORD(&reg->ictrl, 0);
1501 RD_REG_DWORD(&reg->ictrl);
1502 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1503}
1504
706f457d
GM		 1505static int
1506qla2x00_iospace_config(struct qla_hw_data *ha)
1507{
1508 resource_size_t pio;
1509 uint16_t msix;
1510 int cpus;
1511
706f457d
GM		 1512 if (pci_request_selected_regions(ha->pdev, ha->bars,
1513 QLA2XXX_DRIVER_NAME)) {
1514 ql_log_pci(ql_log_fatal, ha->pdev, 0x0011,
1515 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
1516 pci_name(ha->pdev));
1517 goto iospace_error_exit;
1518 }
1519 if (!(ha->bars & 1))
1520 goto skip_pio;
1521
1522 /* We only need PIO for Flash operations on ISP2312 v2 chips. */
1523 pio = pci_resource_start(ha->pdev, 0);
1524 if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) {
1525 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
1526 ql_log_pci(ql_log_warn, ha->pdev, 0x0012,
1527 "Invalid pci I/O region size (%s).\n",
1528 pci_name(ha->pdev));
1529 pio = 0;
1530 }
1531 } else {
1532 ql_log_pci(ql_log_warn, ha->pdev, 0x0013,
1533 "Region #0 no a PIO resource (%s).\n",
1534 pci_name(ha->pdev));
1535 pio = 0;
1536 }
1537 ha->pio_address = pio;
1538 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014,
1539 "PIO address=%llu.\n",
1540 (unsigned long long)ha->pio_address);
1541
1542skip_pio:
1543 /* Use MMIO operations for all accesses. */
1544 if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) {
1545 ql_log_pci(ql_log_fatal, ha->pdev, 0x0015,
1546 "Region #1 not an MMIO resource (%s), aborting.\n",
1547 pci_name(ha->pdev));
1548 goto iospace_error_exit;
1549 }
1550 if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) {
1551 ql_log_pci(ql_log_fatal, ha->pdev, 0x0016,
1552 "Invalid PCI mem region size (%s), aborting.\n",
1553 pci_name(ha->pdev));
1554 goto iospace_error_exit;
1555 }
1556
1557 ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN);
1558 if (!ha->iobase) {
1559 ql_log_pci(ql_log_fatal, ha->pdev, 0x0017,
1560 "Cannot remap MMIO (%s), aborting.\n",
1561 pci_name(ha->pdev));
1562 goto iospace_error_exit;
1563 }
1564
1565 /* Determine queue resources */
1566 ha->max_req_queues = ha->max_rsp_queues = 1;
1567 if ((ql2xmaxqueues <= 1 && !ql2xmultique_tag) ||
1568 (ql2xmaxqueues > 1 && ql2xmultique_tag) ||
1569 (!IS_QLA25XX(ha) && !IS_QLA81XX(ha)))
1570 goto mqiobase_exit;
1571
1572 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3),
1573 pci_resource_len(ha->pdev, 3));
1574 if (ha->mqiobase) {
1575 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018,
1576 "MQIO Base=%p.\n", ha->mqiobase);
1577 /* Read MSIX vector size of the board */
1578 pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix);
1579 ha->msix_count = msix;
1580 /* Max queues are bounded by available msix vectors */
1581 /* queue 0 uses two msix vectors */
1582 if (ql2xmultique_tag) {
1583 cpus = num_online_cpus();
1584 ha->max_rsp_queues = (ha->msix_count - 1 > cpus) ?
1585 (cpus + 1) : (ha->msix_count - 1);
1586 ha->max_req_queues = 2;
1587 } else if (ql2xmaxqueues > 1) {
1588 ha->max_req_queues = ql2xmaxqueues > QLA_MQ_SIZE ?
1589 QLA_MQ_SIZE : ql2xmaxqueues;
1590 ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc008,
1591 "QoS mode set, max no of request queues:%d.\n",
1592 ha->max_req_queues);
1593 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0019,
1594 "QoS mode set, max no of request queues:%d.\n",
1595 ha->max_req_queues);
1596 }
1597 ql_log_pci(ql_log_info, ha->pdev, 0x001a,
1598 "MSI-X vector count: %d.\n", msix);
1599 } else
1600 ql_log_pci(ql_log_info, ha->pdev, 0x001b,
1601 "BAR 3 not enabled.\n");
1602
1603mqiobase_exit:
1604 ha->msix_count = ha->max_rsp_queues + 1;
1605 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c,
1606 "MSIX Count:%d.\n", ha->msix_count);
1607 return (0);
1608
1609iospace_error_exit:
1610 return (-ENOMEM);
1611}
1612
1613
6246b8a1
GM		 1614static int
1615qla83xx_iospace_config(struct qla_hw_data *ha)
1616{
1617 uint16_t msix;
1618 int cpus;
1619
1620 if (pci_request_selected_regions(ha->pdev, ha->bars,
1621 QLA2XXX_DRIVER_NAME)) {
1622 ql_log_pci(ql_log_fatal, ha->pdev, 0x0117,
1623 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
1624 pci_name(ha->pdev));
1625
1626 goto iospace_error_exit;
1627 }
1628
1629 /* Use MMIO operations for all accesses. */
1630 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) {
1631 ql_log_pci(ql_log_warn, ha->pdev, 0x0118,
1632 "Invalid pci I/O region size (%s).\n",
1633 pci_name(ha->pdev));
1634 goto iospace_error_exit;
1635 }
1636 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
1637 ql_log_pci(ql_log_warn, ha->pdev, 0x0119,
1638 "Invalid PCI mem region size (%s), aborting\n",
1639 pci_name(ha->pdev));
1640 goto iospace_error_exit;
1641 }
1642
1643 ha->iobase = ioremap(pci_resource_start(ha->pdev, 0), MIN_IOBASE_LEN);
1644 if (!ha->iobase) {
1645 ql_log_pci(ql_log_fatal, ha->pdev, 0x011a,
1646 "Cannot remap MMIO (%s), aborting.\n",
1647 pci_name(ha->pdev));
1648 goto iospace_error_exit;
1649 }
1650
1651 /* 64bit PCI BAR - BAR2 will correspoond to region 4 */
1652 /* 83XX 26XX always use MQ type access for queues
1653 * - mbar 2, a.k.a region 4 */
1654 ha->max_req_queues = ha->max_rsp_queues = 1;
1655 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 4),
1656 pci_resource_len(ha->pdev, 4));
1657
1658 if (!ha->mqiobase) {
1659 ql_log_pci(ql_log_fatal, ha->pdev, 0x011d,
1660 "BAR2/region4 not enabled\n");
1661 goto mqiobase_exit;
1662 }
1663
1664 ha->msixbase = ioremap(pci_resource_start(ha->pdev, 2),
1665 pci_resource_len(ha->pdev, 2));
1666 if (ha->msixbase) {
1667 /* Read MSIX vector size of the board */
1668 pci_read_config_word(ha->pdev,
1669 QLA_83XX_PCI_MSIX_CONTROL, &msix);
1670 ha->msix_count = msix;
1671 /* Max queues are bounded by available msix vectors */
1672 /* queue 0 uses two msix vectors */
1673 if (ql2xmultique_tag) {
1674 cpus = num_online_cpus();
1675 ha->max_rsp_queues = (ha->msix_count - 1 > cpus) ?
1676 (cpus + 1) : (ha->msix_count - 1);
1677 ha->max_req_queues = 2;
1678 } else if (ql2xmaxqueues > 1) {
1679 ha->max_req_queues = ql2xmaxqueues > QLA_MQ_SIZE ?
1680 QLA_MQ_SIZE : ql2xmaxqueues;
1681 ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc00c,
1682 "QoS mode set, max no of request queues:%d.\n",
1683 ha->max_req_queues);
1684 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b,
1685 "QoS mode set, max no of request queues:%d.\n",
1686 ha->max_req_queues);
1687 }
1688 ql_log_pci(ql_log_info, ha->pdev, 0x011c,
1689 "MSI-X vector count: %d.\n", msix);
1690 } else
1691 ql_log_pci(ql_log_info, ha->pdev, 0x011e,
1692 "BAR 1 not enabled.\n");
1693
1694mqiobase_exit:
1695 ha->msix_count = ha->max_rsp_queues + 1;
aa230bc5
AE		 1696
1697 qlt_83xx_iospace_config(ha);
1698
6246b8a1
GM		 1699 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011f,
1700 "MSIX Count:%d.\n", ha->msix_count);
1701 return 0;
1702
1703iospace_error_exit:
1704 return -ENOMEM;
1705}
1706
fd34f556
AV		 1707static struct isp_operations qla2100_isp_ops = {
1708 .pci_config = qla2100_pci_config,
1709 .reset_chip = qla2x00_reset_chip,
1710 .chip_diag = qla2x00_chip_diag,
1711 .config_rings = qla2x00_config_rings,
1712 .reset_adapter = qla2x00_reset_adapter,
1713 .nvram_config = qla2x00_nvram_config,
1714 .update_fw_options = qla2x00_update_fw_options,
1715 .load_risc = qla2x00_load_risc,
1716 .pci_info_str = qla2x00_pci_info_str,
1717 .fw_version_str = qla2x00_fw_version_str,
1718 .intr_handler = qla2100_intr_handler,
1719 .enable_intrs = qla2x00_enable_intrs,
1720 .disable_intrs = qla2x00_disable_intrs,
1721 .abort_command = qla2x00_abort_command,
523ec773
AV		 1722 .target_reset = qla2x00_abort_target,
1723 .lun_reset = qla2x00_lun_reset,
fd34f556
AV		 1724 .fabric_login = qla2x00_login_fabric,
1725 .fabric_logout = qla2x00_fabric_logout,
1726 .calc_req_entries = qla2x00_calc_iocbs_32,
1727 .build_iocbs = qla2x00_build_scsi_iocbs_32,
1728 .prep_ms_iocb = qla2x00_prep_ms_iocb,
1729 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
1730 .read_nvram = qla2x00_read_nvram_data,
1731 .write_nvram = qla2x00_write_nvram_data,
1732 .fw_dump = qla2100_fw_dump,
1733 .beacon_on = NULL,
1734 .beacon_off = NULL,
1735 .beacon_blink = NULL,
1736 .read_optrom = qla2x00_read_optrom_data,
1737 .write_optrom = qla2x00_write_optrom_data,
1738 .get_flash_version = qla2x00_get_flash_version,
e315cd28 1739 .start_scsi = qla2x00_start_scsi,
a9083016 1740 .abort_isp = qla2x00_abort_isp,
706f457d 1741 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 1742 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 1743};
1744
1745static struct isp_operations qla2300_isp_ops = {
1746 .pci_config = qla2300_pci_config,
1747 .reset_chip = qla2x00_reset_chip,
1748 .chip_diag = qla2x00_chip_diag,
1749 .config_rings = qla2x00_config_rings,
1750 .reset_adapter = qla2x00_reset_adapter,
1751 .nvram_config = qla2x00_nvram_config,
1752 .update_fw_options = qla2x00_update_fw_options,
1753 .load_risc = qla2x00_load_risc,
1754 .pci_info_str = qla2x00_pci_info_str,
1755 .fw_version_str = qla2x00_fw_version_str,
1756 .intr_handler = qla2300_intr_handler,
1757 .enable_intrs = qla2x00_enable_intrs,
1758 .disable_intrs = qla2x00_disable_intrs,
1759 .abort_command = qla2x00_abort_command,
523ec773
AV		 1760 .target_reset = qla2x00_abort_target,
1761 .lun_reset = qla2x00_lun_reset,
fd34f556
AV		 1762 .fabric_login = qla2x00_login_fabric,
1763 .fabric_logout = qla2x00_fabric_logout,
1764 .calc_req_entries = qla2x00_calc_iocbs_32,
1765 .build_iocbs = qla2x00_build_scsi_iocbs_32,
1766 .prep_ms_iocb = qla2x00_prep_ms_iocb,
1767 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
1768 .read_nvram = qla2x00_read_nvram_data,
1769 .write_nvram = qla2x00_write_nvram_data,
1770 .fw_dump = qla2300_fw_dump,
1771 .beacon_on = qla2x00_beacon_on,
1772 .beacon_off = qla2x00_beacon_off,
1773 .beacon_blink = qla2x00_beacon_blink,
1774 .read_optrom = qla2x00_read_optrom_data,
1775 .write_optrom = qla2x00_write_optrom_data,
1776 .get_flash_version = qla2x00_get_flash_version,
e315cd28 1777 .start_scsi = qla2x00_start_scsi,
a9083016 1778 .abort_isp = qla2x00_abort_isp,
7ec0effd 1779 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 1780 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 1781};
1782
1783static struct isp_operations qla24xx_isp_ops = {
1784 .pci_config = qla24xx_pci_config,
1785 .reset_chip = qla24xx_reset_chip,
1786 .chip_diag = qla24xx_chip_diag,
1787 .config_rings = qla24xx_config_rings,
1788 .reset_adapter = qla24xx_reset_adapter,
1789 .nvram_config = qla24xx_nvram_config,
1790 .update_fw_options = qla24xx_update_fw_options,
1791 .load_risc = qla24xx_load_risc,
1792 .pci_info_str = qla24xx_pci_info_str,
1793 .fw_version_str = qla24xx_fw_version_str,
1794 .intr_handler = qla24xx_intr_handler,
1795 .enable_intrs = qla24xx_enable_intrs,
1796 .disable_intrs = qla24xx_disable_intrs,
1797 .abort_command = qla24xx_abort_command,
523ec773
AV		 1798 .target_reset = qla24xx_abort_target,
1799 .lun_reset = qla24xx_lun_reset,
fd34f556
AV		 1800 .fabric_login = qla24xx_login_fabric,
1801 .fabric_logout = qla24xx_fabric_logout,
1802 .calc_req_entries = NULL,
1803 .build_iocbs = NULL,
1804 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1805 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1806 .read_nvram = qla24xx_read_nvram_data,
1807 .write_nvram = qla24xx_write_nvram_data,
1808 .fw_dump = qla24xx_fw_dump,
1809 .beacon_on = qla24xx_beacon_on,
1810 .beacon_off = qla24xx_beacon_off,
1811 .beacon_blink = qla24xx_beacon_blink,
1812 .read_optrom = qla24xx_read_optrom_data,
1813 .write_optrom = qla24xx_write_optrom_data,
1814 .get_flash_version = qla24xx_get_flash_version,
e315cd28 1815 .start_scsi = qla24xx_start_scsi,
a9083016 1816 .abort_isp = qla2x00_abort_isp,
7ec0effd 1817 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 1818 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 1819};
1820
c3a2f0df
AV		 1821static struct isp_operations qla25xx_isp_ops = {
1822 .pci_config = qla25xx_pci_config,
1823 .reset_chip = qla24xx_reset_chip,
1824 .chip_diag = qla24xx_chip_diag,
1825 .config_rings = qla24xx_config_rings,
1826 .reset_adapter = qla24xx_reset_adapter,
1827 .nvram_config = qla24xx_nvram_config,
1828 .update_fw_options = qla24xx_update_fw_options,
1829 .load_risc = qla24xx_load_risc,
1830 .pci_info_str = qla24xx_pci_info_str,
1831 .fw_version_str = qla24xx_fw_version_str,
1832 .intr_handler = qla24xx_intr_handler,
1833 .enable_intrs = qla24xx_enable_intrs,
1834 .disable_intrs = qla24xx_disable_intrs,
1835 .abort_command = qla24xx_abort_command,
523ec773
AV		 1836 .target_reset = qla24xx_abort_target,
1837 .lun_reset = qla24xx_lun_reset,
c3a2f0df
AV		 1838 .fabric_login = qla24xx_login_fabric,
1839 .fabric_logout = qla24xx_fabric_logout,
1840 .calc_req_entries = NULL,
1841 .build_iocbs = NULL,
1842 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1843 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1844 .read_nvram = qla25xx_read_nvram_data,
1845 .write_nvram = qla25xx_write_nvram_data,
1846 .fw_dump = qla25xx_fw_dump,
1847 .beacon_on = qla24xx_beacon_on,
1848 .beacon_off = qla24xx_beacon_off,
1849 .beacon_blink = qla24xx_beacon_blink,
338c9161 1850 .read_optrom = qla25xx_read_optrom_data,
c3a2f0df
AV		 1851 .write_optrom = qla24xx_write_optrom_data,
1852 .get_flash_version = qla24xx_get_flash_version,
bad75002 1853 .start_scsi = qla24xx_dif_start_scsi,
a9083016 1854 .abort_isp = qla2x00_abort_isp,
7ec0effd 1855 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 1856 .initialize_adapter = qla2x00_initialize_adapter,
c3a2f0df
AV		 1857};
1858
3a03eb79
AV		 1859static struct isp_operations qla81xx_isp_ops = {
1860 .pci_config = qla25xx_pci_config,
1861 .reset_chip = qla24xx_reset_chip,
1862 .chip_diag = qla24xx_chip_diag,
1863 .config_rings = qla24xx_config_rings,
1864 .reset_adapter = qla24xx_reset_adapter,
1865 .nvram_config = qla81xx_nvram_config,
1866 .update_fw_options = qla81xx_update_fw_options,
eaac30be 1867 .load_risc = qla81xx_load_risc,
3a03eb79
AV		 1868 .pci_info_str = qla24xx_pci_info_str,
1869 .fw_version_str = qla24xx_fw_version_str,
1870 .intr_handler = qla24xx_intr_handler,
1871 .enable_intrs = qla24xx_enable_intrs,
1872 .disable_intrs = qla24xx_disable_intrs,
1873 .abort_command = qla24xx_abort_command,
1874 .target_reset = qla24xx_abort_target,
1875 .lun_reset = qla24xx_lun_reset,
1876 .fabric_login = qla24xx_login_fabric,
1877 .fabric_logout = qla24xx_fabric_logout,
1878 .calc_req_entries = NULL,
1879 .build_iocbs = NULL,
1880 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1881 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
3d79038f
AV		 1882 .read_nvram = NULL,
1883 .write_nvram = NULL,
3a03eb79
AV		 1884 .fw_dump = qla81xx_fw_dump,
1885 .beacon_on = qla24xx_beacon_on,
1886 .beacon_off = qla24xx_beacon_off,
6246b8a1 1887 .beacon_blink = qla83xx_beacon_blink,
3a03eb79
AV		 1888 .read_optrom = qla25xx_read_optrom_data,
1889 .write_optrom = qla24xx_write_optrom_data,
1890 .get_flash_version = qla24xx_get_flash_version,
ba77ef53 1891 .start_scsi = qla24xx_dif_start_scsi,
a9083016 1892 .abort_isp = qla2x00_abort_isp,
7ec0effd 1893 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 1894 .initialize_adapter = qla2x00_initialize_adapter,
a9083016
GM		 1895};
1896
1897static struct isp_operations qla82xx_isp_ops = {
1898 .pci_config = qla82xx_pci_config,
1899 .reset_chip = qla82xx_reset_chip,
1900 .chip_diag = qla24xx_chip_diag,
1901 .config_rings = qla82xx_config_rings,
1902 .reset_adapter = qla24xx_reset_adapter,
1903 .nvram_config = qla81xx_nvram_config,
1904 .update_fw_options = qla24xx_update_fw_options,
1905 .load_risc = qla82xx_load_risc,
9d55ca66 1906 .pci_info_str = qla24xx_pci_info_str,
a9083016
GM		 1907 .fw_version_str = qla24xx_fw_version_str,
1908 .intr_handler = qla82xx_intr_handler,
1909 .enable_intrs = qla82xx_enable_intrs,
1910 .disable_intrs = qla82xx_disable_intrs,
1911 .abort_command = qla24xx_abort_command,
1912 .target_reset = qla24xx_abort_target,
1913 .lun_reset = qla24xx_lun_reset,
1914 .fabric_login = qla24xx_login_fabric,
1915 .fabric_logout = qla24xx_fabric_logout,
1916 .calc_req_entries = NULL,
1917 .build_iocbs = NULL,
1918 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1919 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1920 .read_nvram = qla24xx_read_nvram_data,
1921 .write_nvram = qla24xx_write_nvram_data,
a1b23c5a 1922 .fw_dump = qla82xx_fw_dump,
999916dc
SK		 1923 .beacon_on = qla82xx_beacon_on,
1924 .beacon_off = qla82xx_beacon_off,
1925 .beacon_blink = NULL,
a9083016
GM		 1926 .read_optrom = qla82xx_read_optrom_data,
1927 .write_optrom = qla82xx_write_optrom_data,
7ec0effd 1928 .get_flash_version = qla82xx_get_flash_version,
a9083016
GM		 1929 .start_scsi = qla82xx_start_scsi,
1930 .abort_isp = qla82xx_abort_isp,
706f457d 1931 .iospace_config = qla82xx_iospace_config,
8ae6d9c7 1932 .initialize_adapter = qla2x00_initialize_adapter,
3a03eb79
AV		 1933};
1934
7ec0effd
AD		 1935static struct isp_operations qla8044_isp_ops = {
1936 .pci_config = qla82xx_pci_config,
1937 .reset_chip = qla82xx_reset_chip,
1938 .chip_diag = qla24xx_chip_diag,
1939 .config_rings = qla82xx_config_rings,
1940 .reset_adapter = qla24xx_reset_adapter,
1941 .nvram_config = qla81xx_nvram_config,
1942 .update_fw_options = qla24xx_update_fw_options,
1943 .load_risc = qla82xx_load_risc,
1944 .pci_info_str = qla24xx_pci_info_str,
1945 .fw_version_str = qla24xx_fw_version_str,
1946 .intr_handler = qla8044_intr_handler,
1947 .enable_intrs = qla82xx_enable_intrs,
1948 .disable_intrs = qla82xx_disable_intrs,
1949 .abort_command = qla24xx_abort_command,
1950 .target_reset = qla24xx_abort_target,
1951 .lun_reset = qla24xx_lun_reset,
1952 .fabric_login = qla24xx_login_fabric,
1953 .fabric_logout = qla24xx_fabric_logout,
1954 .calc_req_entries = NULL,
1955 .build_iocbs = NULL,
1956 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1957 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1958 .read_nvram = NULL,
1959 .write_nvram = NULL,
a1b23c5a 1960 .fw_dump = qla8044_fw_dump,
7ec0effd
AD		 1961 .beacon_on = qla82xx_beacon_on,
1962 .beacon_off = qla82xx_beacon_off,
1963 .beacon_blink = NULL,
888e639d 1964 .read_optrom = qla8044_read_optrom_data,
7ec0effd
AD		 1965 .write_optrom = qla8044_write_optrom_data,
1966 .get_flash_version = qla82xx_get_flash_version,
1967 .start_scsi = qla82xx_start_scsi,
1968 .abort_isp = qla8044_abort_isp,
1969 .iospace_config = qla82xx_iospace_config,
1970 .initialize_adapter = qla2x00_initialize_adapter,
1971};
1972
6246b8a1
GM		 1973static struct isp_operations qla83xx_isp_ops = {
1974 .pci_config = qla25xx_pci_config,
1975 .reset_chip = qla24xx_reset_chip,
1976 .chip_diag = qla24xx_chip_diag,
1977 .config_rings = qla24xx_config_rings,
1978 .reset_adapter = qla24xx_reset_adapter,
1979 .nvram_config = qla81xx_nvram_config,
1980 .update_fw_options = qla81xx_update_fw_options,
1981 .load_risc = qla81xx_load_risc,
1982 .pci_info_str = qla24xx_pci_info_str,
1983 .fw_version_str = qla24xx_fw_version_str,
1984 .intr_handler = qla24xx_intr_handler,
1985 .enable_intrs = qla24xx_enable_intrs,
1986 .disable_intrs = qla24xx_disable_intrs,
1987 .abort_command = qla24xx_abort_command,
1988 .target_reset = qla24xx_abort_target,
1989 .lun_reset = qla24xx_lun_reset,
1990 .fabric_login = qla24xx_login_fabric,
1991 .fabric_logout = qla24xx_fabric_logout,
1992 .calc_req_entries = NULL,
1993 .build_iocbs = NULL,
1994 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1995 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1996 .read_nvram = NULL,
1997 .write_nvram = NULL,
1998 .fw_dump = qla83xx_fw_dump,
1999 .beacon_on = qla24xx_beacon_on,
2000 .beacon_off = qla24xx_beacon_off,
2001 .beacon_blink = qla83xx_beacon_blink,
2002 .read_optrom = qla25xx_read_optrom_data,
2003 .write_optrom = qla24xx_write_optrom_data,
2004 .get_flash_version = qla24xx_get_flash_version,
2005 .start_scsi = qla24xx_dif_start_scsi,
2006 .abort_isp = qla2x00_abort_isp,
2007 .iospace_config = qla83xx_iospace_config,
8ae6d9c7
GM		 2008 .initialize_adapter = qla2x00_initialize_adapter,
2009};
2010
2011static struct isp_operations qlafx00_isp_ops = {
2012 .pci_config = qlafx00_pci_config,
2013 .reset_chip = qlafx00_soft_reset,
2014 .chip_diag = qlafx00_chip_diag,
2015 .config_rings = qlafx00_config_rings,
2016 .reset_adapter = qlafx00_soft_reset,
2017 .nvram_config = NULL,
2018 .update_fw_options = NULL,
2019 .load_risc = NULL,
2020 .pci_info_str = qlafx00_pci_info_str,
2021 .fw_version_str = qlafx00_fw_version_str,
2022 .intr_handler = qlafx00_intr_handler,
2023 .enable_intrs = qlafx00_enable_intrs,
2024 .disable_intrs = qlafx00_disable_intrs,
4440e46d 2025 .abort_command = qla24xx_async_abort_command,
8ae6d9c7
GM		 2026 .target_reset = qlafx00_abort_target,
2027 .lun_reset = qlafx00_lun_reset,
2028 .fabric_login = NULL,
2029 .fabric_logout = NULL,
2030 .calc_req_entries = NULL,
2031 .build_iocbs = NULL,
2032 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2033 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2034 .read_nvram = qla24xx_read_nvram_data,
2035 .write_nvram = qla24xx_write_nvram_data,
2036 .fw_dump = NULL,
2037 .beacon_on = qla24xx_beacon_on,
2038 .beacon_off = qla24xx_beacon_off,
2039 .beacon_blink = NULL,
2040 .read_optrom = qla24xx_read_optrom_data,
2041 .write_optrom = qla24xx_write_optrom_data,
2042 .get_flash_version = qla24xx_get_flash_version,
2043 .start_scsi = qlafx00_start_scsi,
2044 .abort_isp = qlafx00_abort_isp,
2045 .iospace_config = qlafx00_iospace_config,
2046 .initialize_adapter = qlafx00_initialize_adapter,
6246b8a1
GM		 2047};
2048
f73cb695
CD		 2049static struct isp_operations qla27xx_isp_ops = {
2050 .pci_config = qla25xx_pci_config,
2051 .reset_chip = qla24xx_reset_chip,
2052 .chip_diag = qla24xx_chip_diag,
2053 .config_rings = qla24xx_config_rings,
2054 .reset_adapter = qla24xx_reset_adapter,
2055 .nvram_config = qla81xx_nvram_config,
2056 .update_fw_options = qla81xx_update_fw_options,
2057 .load_risc = qla81xx_load_risc,
2058 .pci_info_str = qla24xx_pci_info_str,
2059 .fw_version_str = qla24xx_fw_version_str,
2060 .intr_handler = qla24xx_intr_handler,
2061 .enable_intrs = qla24xx_enable_intrs,
2062 .disable_intrs = qla24xx_disable_intrs,
2063 .abort_command = qla24xx_abort_command,
2064 .target_reset = qla24xx_abort_target,
2065 .lun_reset = qla24xx_lun_reset,
2066 .fabric_login = qla24xx_login_fabric,
2067 .fabric_logout = qla24xx_fabric_logout,
2068 .calc_req_entries = NULL,
2069 .build_iocbs = NULL,
2070 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2071 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2072 .read_nvram = NULL,
2073 .write_nvram = NULL,
2074 .fw_dump = qla27xx_fwdump,
2075 .beacon_on = qla24xx_beacon_on,
2076 .beacon_off = qla24xx_beacon_off,
2077 .beacon_blink = qla83xx_beacon_blink,
2078 .read_optrom = qla25xx_read_optrom_data,
2079 .write_optrom = qla24xx_write_optrom_data,
2080 .get_flash_version = qla24xx_get_flash_version,
2081 .start_scsi = qla24xx_dif_start_scsi,
2082 .abort_isp = qla2x00_abort_isp,
2083 .iospace_config = qla83xx_iospace_config,
2084 .initialize_adapter = qla2x00_initialize_adapter,
2085};
2086
ea5b6382 2087static inline void
e315cd28 2088qla2x00_set_isp_flags(struct qla_hw_data *ha)
ea5b6382 2089{
2090 ha->device_type = DT_EXTENDED_IDS;
2091 switch (ha->pdev->device) {
2092 case PCI_DEVICE_ID_QLOGIC_ISP2100:
2093 ha->device_type |= DT_ISP2100;
2094 ha->device_type &= ~DT_EXTENDED_IDS;
441d1072 2095 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
ea5b6382 2096 break;
2097 case PCI_DEVICE_ID_QLOGIC_ISP2200:
2098 ha->device_type |= DT_ISP2200;
2099 ha->device_type &= ~DT_EXTENDED_IDS;
441d1072 2100 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
ea5b6382 2101 break;
2102 case PCI_DEVICE_ID_QLOGIC_ISP2300:
2103 ha->device_type |= DT_ISP2300;
4a59f71d 2104 ha->device_type |= DT_ZIO_SUPPORTED;
441d1072 2105 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 2106 break;
2107 case PCI_DEVICE_ID_QLOGIC_ISP2312:
2108 ha->device_type |= DT_ISP2312;
4a59f71d 2109 ha->device_type |= DT_ZIO_SUPPORTED;
441d1072 2110 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 2111 break;
2112 case PCI_DEVICE_ID_QLOGIC_ISP2322:
2113 ha->device_type |= DT_ISP2322;
4a59f71d 2114 ha->device_type |= DT_ZIO_SUPPORTED;
ea5b6382 2115 if (ha->pdev->subsystem_vendor == 0x1028 &&
2116 ha->pdev->subsystem_device == 0x0170)
2117 ha->device_type |= DT_OEM_001;
441d1072 2118 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 2119 break;
2120 case PCI_DEVICE_ID_QLOGIC_ISP6312:
2121 ha->device_type |= DT_ISP6312;
441d1072 2122 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 2123 break;
2124 case PCI_DEVICE_ID_QLOGIC_ISP6322:
2125 ha->device_type |= DT_ISP6322;
441d1072 2126 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 2127 break;
2128 case PCI_DEVICE_ID_QLOGIC_ISP2422:
2129 ha->device_type |= DT_ISP2422;
4a59f71d 2130 ha->device_type |= DT_ZIO_SUPPORTED;
e428924c 2131 ha->device_type |= DT_FWI2;
c76f2c01 2132 ha->device_type |= DT_IIDMA;
441d1072 2133 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2134 break;
2135 case PCI_DEVICE_ID_QLOGIC_ISP2432:
2136 ha->device_type |= DT_ISP2432;
4a59f71d 2137 ha->device_type |= DT_ZIO_SUPPORTED;
e428924c 2138 ha->device_type |= DT_FWI2;
c76f2c01 2139 ha->device_type |= DT_IIDMA;
441d1072 2140 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2141 break;
4d4df193
HK		 2142 case PCI_DEVICE_ID_QLOGIC_ISP8432:
2143 ha->device_type |= DT_ISP8432;
2144 ha->device_type |= DT_ZIO_SUPPORTED;
2145 ha->device_type |= DT_FWI2;
2146 ha->device_type |= DT_IIDMA;
2147 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2148 break;
044cc6c8 2149 case PCI_DEVICE_ID_QLOGIC_ISP5422:
2150 ha->device_type |= DT_ISP5422;
e428924c 2151 ha->device_type |= DT_FWI2;
441d1072 2152 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2153 break;
044cc6c8 2154 case PCI_DEVICE_ID_QLOGIC_ISP5432:
2155 ha->device_type |= DT_ISP5432;
e428924c 2156 ha->device_type |= DT_FWI2;
441d1072 2157 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2158 break;
c3a2f0df
AV		 2159 case PCI_DEVICE_ID_QLOGIC_ISP2532:
2160 ha->device_type |= DT_ISP2532;
2161 ha->device_type |= DT_ZIO_SUPPORTED;
2162 ha->device_type |= DT_FWI2;
2163 ha->device_type |= DT_IIDMA;
441d1072 2164 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2165 break;
3a03eb79
AV		 2166 case PCI_DEVICE_ID_QLOGIC_ISP8001:
2167 ha->device_type |= DT_ISP8001;
2168 ha->device_type |= DT_ZIO_SUPPORTED;
2169 ha->device_type |= DT_FWI2;
2170 ha->device_type |= DT_IIDMA;
2171 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2172 break;
a9083016
GM		 2173 case PCI_DEVICE_ID_QLOGIC_ISP8021:
2174 ha->device_type |= DT_ISP8021;
2175 ha->device_type |= DT_ZIO_SUPPORTED;
2176 ha->device_type |= DT_FWI2;
2177 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2178 /* Initialize 82XX ISP flags */
2179 qla82xx_init_flags(ha);
2180 break;
7ec0effd
AD		 2181 case PCI_DEVICE_ID_QLOGIC_ISP8044:
2182 ha->device_type |= DT_ISP8044;
2183 ha->device_type |= DT_ZIO_SUPPORTED;
2184 ha->device_type |= DT_FWI2;
2185 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2186 /* Initialize 82XX ISP flags */
2187 qla82xx_init_flags(ha);
2188 break;
6246b8a1
GM		 2189 case PCI_DEVICE_ID_QLOGIC_ISP2031:
2190 ha->device_type |= DT_ISP2031;
2191 ha->device_type |= DT_ZIO_SUPPORTED;
2192 ha->device_type |= DT_FWI2;
2193 ha->device_type |= DT_IIDMA;
2194 ha->device_type |= DT_T10_PI;
2195 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2196 break;
2197 case PCI_DEVICE_ID_QLOGIC_ISP8031:
2198 ha->device_type |= DT_ISP8031;
2199 ha->device_type |= DT_ZIO_SUPPORTED;
2200 ha->device_type |= DT_FWI2;
2201 ha->device_type |= DT_IIDMA;
2202 ha->device_type |= DT_T10_PI;
2203 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2204 break;
8ae6d9c7
GM		 2205 case PCI_DEVICE_ID_QLOGIC_ISPF001:
2206 ha->device_type |= DT_ISPFX00;
2207 break;
f73cb695
CD		 2208 case PCI_DEVICE_ID_QLOGIC_ISP2071:
2209 ha->device_type |= DT_ISP2071;
2210 ha->device_type |= DT_ZIO_SUPPORTED;
2211 ha->device_type |= DT_FWI2;
2212 ha->device_type |= DT_IIDMA;
2213 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2214 break;
2c5bbbb2
JC		 2215 case PCI_DEVICE_ID_QLOGIC_ISP2271:
2216 ha->device_type |= DT_ISP2271;
2217 ha->device_type |= DT_ZIO_SUPPORTED;
2218 ha->device_type |= DT_FWI2;
2219 ha->device_type |= DT_IIDMA;
2220 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2221 break;
ea5b6382 2222 }
e5b68a61 2223
a9083016 2224 if (IS_QLA82XX(ha))
43a9c38b 2225 ha->port_no = ha->portnum & 1;
f73cb695 2226 else {
a9083016
GM		 2227 /* Get adapter physical port no from interrupt pin register. */
2228 pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no);
f73cb695
CD		 2229 if (IS_QLA27XX(ha))
2230 ha->port_no--;
2231 else
2232 ha->port_no = !(ha->port_no & 1);
2233 }
a9083016 2234
7c3df132 2235 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b,
d8424f68 2236 "device_type=0x%x port=%d fw_srisc_address=0x%x.\n",
f73cb695 2237 ha->device_type, ha->port_no, ha->fw_srisc_address);
ea5b6382 2238}
2239
1e99e33a
AV		 2240static void
2241qla2xxx_scan_start(struct Scsi_Host *shost)
2242{
e315cd28 2243 scsi_qla_host_t *vha = shost_priv(shost);
1e99e33a 2244
cbc8eb67
AV		 2245 if (vha->hw->flags.running_gold_fw)
2246 return;
2247
e315cd28
AC		 2248 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
2249 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
2250 set_bit(RSCN_UPDATE, &vha->dpc_flags);
2251 set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags);
1e99e33a
AV		 2252}
2253
2254static int
2255qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time)
2256{
e315cd28 2257 scsi_qla_host_t *vha = shost_priv(shost);
1e99e33a 2258
e315cd28 2259 if (!vha->host)
1e99e33a 2260 return 1;
e315cd28 2261 if (time > vha->hw->loop_reset_delay * HZ)
1e99e33a
AV		 2262 return 1;
2263
e315cd28 2264 return atomic_read(&vha->loop_state) == LOOP_READY;
1e99e33a
AV		 2265}
2266
1da177e4
LT		 2267/*
2268 * PCI driver interface
2269 */
6f039790 2270static int
7ee61397 2271qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
1da177e4 2272{
a1541d5a 2273 int ret = -ENODEV;
1da177e4 2274 struct Scsi_Host *host;
e315cd28
AC		 2275 scsi_qla_host_t *base_vha = NULL;
2276 struct qla_hw_data *ha;
29856e28 2277 char pci_info[30];
7d613ac6 2278 char fw_str[30], wq_name[30];
5433383e 2279 struct scsi_host_template *sht;
642ef983 2280 int bars, mem_only = 0;
e315cd28 2281 uint16_t req_length = 0, rsp_length = 0;
73208dfd
AC		 2282 struct req_que *req = NULL;
2283 struct rsp_que *rsp = NULL;
285d0321 2284 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO);
a5326f86 2285 sht = &qla2xxx_driver_template;
5433383e 2286 if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 ||
8bc69e7d 2287 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 ||
4d4df193 2288 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 ||
8bc69e7d 2289 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 ||
c3a2f0df 2290 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 ||
3a03eb79 2291 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 ||
a9083016 2292 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 ||
6246b8a1
GM		 2293 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021 ||
2294 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2031 ||
8ae6d9c7 2295 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8031 ||
7ec0effd 2296 pdev->device == PCI_DEVICE_ID_QLOGIC_ISPF001 ||
f73cb695 2297 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8044 ||
2c5bbbb2
JC		 2298 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2071 ||
2299 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2271) {
285d0321 2300 bars = pci_select_bars(pdev, IORESOURCE_MEM);
09483916 2301 mem_only = 1;
7c3df132
SK		 2302 ql_dbg_pci(ql_dbg_init, pdev, 0x0007,
2303 "Mem only adapter.\n");
285d0321 2304 }
7c3df132
SK		 2305 ql_dbg_pci(ql_dbg_init, pdev, 0x0008,
2306 "Bars=%d.\n", bars);
285d0321 2307
09483916
BH		 2308 if (mem_only) {
2309 if (pci_enable_device_mem(pdev))
2310 goto probe_out;
2311 } else {
2312 if (pci_enable_device(pdev))
2313 goto probe_out;
2314 }
285d0321 2315
0927678f
JB		 2316 /* This may fail but that's ok */
2317 pci_enable_pcie_error_reporting(pdev);
285d0321 2318
e315cd28
AC		 2319 ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL);
2320 if (!ha) {
7c3df132
SK		 2321 ql_log_pci(ql_log_fatal, pdev, 0x0009,
2322 "Unable to allocate memory for ha.\n");
e315cd28 2323 goto probe_out;
1da177e4 2324 }
7c3df132
SK		 2325 ql_dbg_pci(ql_dbg_init, pdev, 0x000a,
2326 "Memory allocated for ha=%p.\n", ha);
e315cd28 2327 ha->pdev = pdev;
2d70c103 2328 ha->tgt.enable_class_2 = ql2xenableclass2;
33e79977
QT		 2329 INIT_LIST_HEAD(&ha->tgt.q_full_list);
2330 spin_lock_init(&ha->tgt.q_full_lock);
1da177e4
LT		 2331
2332 /* Clear our data area */
285d0321 2333 ha->bars = bars;
09483916 2334 ha->mem_only = mem_only;
df4bf0bb 2335 spin_lock_init(&ha->hardware_lock);
339aa70e 2336 spin_lock_init(&ha->vport_slock);
a9b6f722 2337 mutex_init(&ha->selflogin_lock);
7a8ab9c8 2338 mutex_init(&ha->optrom_mutex);
1da177e4 2339
ea5b6382 2340 /* Set ISP-type information. */
2341 qla2x00_set_isp_flags(ha);
ca79cf66
DG		 2342
2343 /* Set EEH reset type to fundamental if required by hba */
95676112 2344 if (IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha) ||
f73cb695 2345 IS_QLA83XX(ha) || IS_QLA27XX(ha))
ca79cf66 2346 pdev->needs_freset = 1;
ca79cf66 2347
cba1e47f
CD		 2348 ha->prev_topology = 0;
2349 ha->init_cb_size = sizeof(init_cb_t);
2350 ha->link_data_rate = PORT_SPEED_UNKNOWN;
2351 ha->optrom_size = OPTROM_SIZE_2300;
2352
abbd8870 2353 /* Assign ISP specific operations. */
1da177e4 2354 if (IS_QLA2100(ha)) {
642ef983 2355 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
1da177e4 2356 ha->mbx_count = MAILBOX_REGISTER_COUNT_2100;
e315cd28
AC		 2357 req_length = REQUEST_ENTRY_CNT_2100;
2358 rsp_length = RESPONSE_ENTRY_CNT_2100;
2359 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
abbd8870 2360 ha->gid_list_info_size = 4;
3a03eb79
AV		 2361 ha->flash_conf_off = ~0;
2362 ha->flash_data_off = ~0;
2363 ha->nvram_conf_off = ~0;
2364 ha->nvram_data_off = ~0;
fd34f556 2365 ha->isp_ops = &qla2100_isp_ops;
1da177e4 2366 } else if (IS_QLA2200(ha)) {
642ef983 2367 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
67ddda35 2368 ha->mbx_count = MAILBOX_REGISTER_COUNT_2200;
e315cd28
AC		 2369 req_length = REQUEST_ENTRY_CNT_2200;
2370 rsp_length = RESPONSE_ENTRY_CNT_2100;
2371 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
abbd8870 2372 ha->gid_list_info_size = 4;
3a03eb79
AV		 2373 ha->flash_conf_off = ~0;
2374 ha->flash_data_off = ~0;
2375 ha->nvram_conf_off = ~0;
2376 ha->nvram_data_off = ~0;
fd34f556 2377 ha->isp_ops = &qla2100_isp_ops;
fca29703 2378 } else if (IS_QLA23XX(ha)) {
642ef983 2379 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
1da177e4 2380 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2381 req_length = REQUEST_ENTRY_CNT_2200;
2382 rsp_length = RESPONSE_ENTRY_CNT_2300;
2383 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
abbd8870 2384 ha->gid_list_info_size = 6;
854165f4 2385 if (IS_QLA2322(ha) || IS_QLA6322(ha))
2386 ha->optrom_size = OPTROM_SIZE_2322;
3a03eb79
AV		 2387 ha->flash_conf_off = ~0;
2388 ha->flash_data_off = ~0;
2389 ha->nvram_conf_off = ~0;
2390 ha->nvram_data_off = ~0;
fd34f556 2391 ha->isp_ops = &qla2300_isp_ops;
4d4df193 2392 } else if (IS_QLA24XX_TYPE(ha)) {
642ef983 2393 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
fca29703 2394 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2395 req_length = REQUEST_ENTRY_CNT_24XX;
2396 rsp_length = RESPONSE_ENTRY_CNT_2300;
2d70c103 2397 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
e315cd28 2398 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2c3dfe3f 2399 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
fca29703 2400 ha->gid_list_info_size = 8;
854165f4 2401 ha->optrom_size = OPTROM_SIZE_24XX;
73208dfd 2402 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX;
fd34f556 2403 ha->isp_ops = &qla24xx_isp_ops;
3a03eb79
AV		 2404 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2405 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2406 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2407 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
c3a2f0df 2408 } else if (IS_QLA25XX(ha)) {
642ef983 2409 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
c3a2f0df 2410 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2411 req_length = REQUEST_ENTRY_CNT_24XX;
2412 rsp_length = RESPONSE_ENTRY_CNT_2300;
2d70c103 2413 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
e315cd28 2414 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
c3a2f0df 2415 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
c3a2f0df
AV		 2416 ha->gid_list_info_size = 8;
2417 ha->optrom_size = OPTROM_SIZE_25XX;
73208dfd 2418 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
c3a2f0df 2419 ha->isp_ops = &qla25xx_isp_ops;
3a03eb79
AV		 2420 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2421 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2422 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2423 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
2424 } else if (IS_QLA81XX(ha)) {
642ef983 2425 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3a03eb79
AV		 2426 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2427 req_length = REQUEST_ENTRY_CNT_24XX;
2428 rsp_length = RESPONSE_ENTRY_CNT_2300;
aa230bc5 2429 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
3a03eb79
AV		 2430 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2431 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2432 ha->gid_list_info_size = 8;
2433 ha->optrom_size = OPTROM_SIZE_81XX;
40859ae5 2434 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3a03eb79
AV		 2435 ha->isp_ops = &qla81xx_isp_ops;
2436 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2437 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2438 ha->nvram_conf_off = ~0;
2439 ha->nvram_data_off = ~0;
a9083016 2440 } else if (IS_QLA82XX(ha)) {
642ef983 2441 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
a9083016
GM		 2442 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2443 req_length = REQUEST_ENTRY_CNT_82XX;
2444 rsp_length = RESPONSE_ENTRY_CNT_82XX;
2445 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2446 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2447 ha->gid_list_info_size = 8;
2448 ha->optrom_size = OPTROM_SIZE_82XX;
087c621e 2449 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
a9083016
GM		 2450 ha->isp_ops = &qla82xx_isp_ops;
2451 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2452 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2453 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2454 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
7ec0effd
AD		 2455 } else if (IS_QLA8044(ha)) {
2456 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2457 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2458 req_length = REQUEST_ENTRY_CNT_82XX;
2459 rsp_length = RESPONSE_ENTRY_CNT_82XX;
2460 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2461 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2462 ha->gid_list_info_size = 8;
2463 ha->optrom_size = OPTROM_SIZE_83XX;
2464 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2465 ha->isp_ops = &qla8044_isp_ops;
2466 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2467 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2468 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2469 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
6246b8a1 2470 } else if (IS_QLA83XX(ha)) {
7d613ac6 2471 ha->portnum = PCI_FUNC(ha->pdev->devfn);
642ef983 2472 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
6246b8a1 2473 ha->mbx_count = MAILBOX_REGISTER_COUNT;
f2ea653f 2474 req_length = REQUEST_ENTRY_CNT_83XX;
6246b8a1 2475 rsp_length = RESPONSE_ENTRY_CNT_2300;
b8aa4bdf 2476 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
6246b8a1
GM		 2477 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2478 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2479 ha->gid_list_info_size = 8;
2480 ha->optrom_size = OPTROM_SIZE_83XX;
2481 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2482 ha->isp_ops = &qla83xx_isp_ops;
2483 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2484 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2485 ha->nvram_conf_off = ~0;
2486 ha->nvram_data_off = ~0;
8ae6d9c7
GM		 2487 } else if (IS_QLAFX00(ha)) {
2488 ha->max_fibre_devices = MAX_FIBRE_DEVICES_FX00;
2489 ha->mbx_count = MAILBOX_REGISTER_COUNT_FX00;
2490 ha->aen_mbx_count = AEN_MAILBOX_REGISTER_COUNT_FX00;
2491 req_length = REQUEST_ENTRY_CNT_FX00;
2492 rsp_length = RESPONSE_ENTRY_CNT_FX00;
8ae6d9c7
GM		 2493 ha->isp_ops = &qlafx00_isp_ops;
2494 ha->port_down_retry_count = 30; /* default value */
2495 ha->mr.fw_hbt_cnt = QLAFX00_HEARTBEAT_INTERVAL;
2496 ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL;
71e56003 2497 ha->mr.fw_critemp_timer_tick = QLAFX00_CRITEMP_INTERVAL;
8ae6d9c7 2498 ha->mr.fw_hbt_en = 1;
e8f5e95d
AB		 2499 ha->mr.host_info_resend = false;
2500 ha->mr.hinfo_resend_timer_tick = QLAFX00_HINFO_RESEND_INTERVAL;
f73cb695
CD		 2501 } else if (IS_QLA27XX(ha)) {
2502 ha->portnum = PCI_FUNC(ha->pdev->devfn);
2503 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2504 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2505 req_length = REQUEST_ENTRY_CNT_24XX;
2506 rsp_length = RESPONSE_ENTRY_CNT_2300;
2507 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2508 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2509 ha->gid_list_info_size = 8;
2510 ha->optrom_size = OPTROM_SIZE_83XX;
2511 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2512 ha->isp_ops = &qla27xx_isp_ops;
2513 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2514 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2515 ha->nvram_conf_off = ~0;
2516 ha->nvram_data_off = ~0;
1da177e4 2517 }
6246b8a1 2518
7c3df132
SK		 2519 ql_dbg_pci(ql_dbg_init, pdev, 0x001e,
2520 "mbx_count=%d, req_length=%d, "
2521 "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, "
642ef983
CD		 2522 "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, "
2523 "max_fibre_devices=%d.\n",
7c3df132
SK		 2524 ha->mbx_count, req_length, rsp_length, ha->max_loop_id,
2525 ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size,
642ef983 2526 ha->nvram_npiv_size, ha->max_fibre_devices);
7c3df132
SK		 2527 ql_dbg_pci(ql_dbg_init, pdev, 0x001f,
2528 "isp_ops=%p, flash_conf_off=%d, "
2529 "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n",
2530 ha->isp_ops, ha->flash_conf_off, ha->flash_data_off,
2531 ha->nvram_conf_off, ha->nvram_data_off);
706f457d
GM		 2532
2533 /* Configure PCI I/O space */
2534 ret = ha->isp_ops->iospace_config(ha);
2535 if (ret)
0a63ad12 2536 goto iospace_config_failed;
706f457d
GM		 2537
2538 ql_log_pci(ql_log_info, pdev, 0x001d,
2539 "Found an ISP%04X irq %d iobase 0x%p.\n",
2540 pdev->device, pdev->irq, ha->iobase);
6c2f527c 2541 mutex_init(&ha->vport_lock);
0b05a1f0
MB		 2542 init_completion(&ha->mbx_cmd_comp);
2543 complete(&ha->mbx_cmd_comp);
2544 init_completion(&ha->mbx_intr_comp);
23f2ebd1 2545 init_completion(&ha->dcbx_comp);
f356bef1 2546 init_completion(&ha->lb_portup_comp);
1da177e4 2547
2c3dfe3f 2548 set_bit(0, (unsigned long *) ha->vp_idx_map);
1da177e4 2549
53303c42 2550 qla2x00_config_dma_addressing(ha);
7c3df132
SK		 2551 ql_dbg_pci(ql_dbg_init, pdev, 0x0020,
2552 "64 Bit addressing is %s.\n",
2553 ha->flags.enable_64bit_addressing ? "enable" :
2554 "disable");
73208dfd 2555 ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp);
b2a72ec3 2556 if (ret) {
7c3df132
SK		 2557 ql_log_pci(ql_log_fatal, pdev, 0x0031,
2558 "Failed to allocate memory for adapter, aborting.\n");
1da177e4 2559
e315cd28
AC		 2560 goto probe_hw_failed;
2561 }
2562
73208dfd 2563 req->max_q_depth = MAX_Q_DEPTH;
e315cd28 2564 if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU)
73208dfd
AC		 2565 req->max_q_depth = ql2xmaxqdepth;
2566
e315cd28
AC		 2567
2568 base_vha = qla2x00_create_host(sht, ha);
2569 if (!base_vha) {
a1541d5a 2570 ret = -ENOMEM;
6e9f21f3 2571 qla2x00_mem_free(ha);
2afa19a9
AC		 2572 qla2x00_free_req_que(ha, req);
2573 qla2x00_free_rsp_que(ha, rsp);
e315cd28 2574 goto probe_hw_failed;
1da177e4
LT		 2575 }
2576
e315cd28 2577 pci_set_drvdata(pdev, base_vha);
6b383979 2578 set_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags);
e315cd28 2579
e315cd28 2580 host = base_vha->host;
2afa19a9 2581 base_vha->req = req;
73208dfd 2582 if (IS_QLA2XXX_MIDTYPE(ha))
e315cd28 2583 base_vha->mgmt_svr_loop_id = 10 + base_vha->vp_idx;
73208dfd 2584 else
e315cd28
AC		 2585 base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER +
2586 base_vha->vp_idx;
58548cb5 2587
8ae6d9c7
GM		 2588 /* Setup fcport template structure. */
2589 ha->mr.fcport.vha = base_vha;
2590 ha->mr.fcport.port_type = FCT_UNKNOWN;
2591 ha->mr.fcport.loop_id = FC_NO_LOOP_ID;
2592 qla2x00_set_fcport_state(&ha->mr.fcport, FCS_UNCONFIGURED);
2593 ha->mr.fcport.supported_classes = FC_COS_UNSPECIFIED;
2594 ha->mr.fcport.scan_state = 1;
2595
58548cb5
GM		 2596 /* Set the SG table size based on ISP type */
2597 if (!IS_FWI2_CAPABLE(ha)) {
2598 if (IS_QLA2100(ha))
2599 host->sg_tablesize = 32;
2600 } else {
2601 if (!IS_QLA82XX(ha))
2602 host->sg_tablesize = QLA_SG_ALL;
2603 }
642ef983 2604 host->max_id = ha->max_fibre_devices;
e315cd28
AC		 2605 host->cmd_per_lun = 3;
2606 host->unique_id = host->host_no;
e02587d7 2607 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif)
0c470874
AE		 2608 host->max_cmd_len = 32;
2609 else
2610 host->max_cmd_len = MAX_CMDSZ;
e315cd28 2611 host->max_channel = MAX_BUSES - 1;
755f516b
HR		 2612 /* Older HBAs support only 16-bit LUNs */
2613 if (!IS_QLAFX00(ha) && !IS_FWI2_CAPABLE(ha) &&
2614 ql2xmaxlun > 0xffff)
2615 host->max_lun = 0xffff;
2616 else
2617 host->max_lun = ql2xmaxlun;
e315cd28 2618 host->transportt = qla2xxx_transport_template;
9a069e19 2619 sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC);
e315cd28 2620
7c3df132
SK		 2621 ql_dbg(ql_dbg_init, base_vha, 0x0033,
2622 "max_id=%d this_id=%d "
2623 "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d "
1abf635d 2624 "max_lun=%llu transportt=%p, vendor_id=%llu.\n", host->max_id,
7c3df132
SK		 2625 host->this_id, host->cmd_per_lun, host->unique_id,
2626 host->max_cmd_len, host->max_channel, host->max_lun,
2627 host->transportt, sht->vendor_id);
2628
9a347ff4
CD		 2629que_init:
2630 /* Alloc arrays of request and response ring ptrs */
2631 if (!qla2x00_alloc_queues(ha, req, rsp)) {
2632 ql_log(ql_log_fatal, base_vha, 0x003d,
2633 "Failed to allocate memory for queue pointers..."
2634 "aborting.\n");
2635 goto probe_init_failed;
2636 }
2637
2d70c103 2638 qlt_probe_one_stage1(base_vha, ha);
9a347ff4 2639
73208dfd
AC		 2640 /* Set up the irqs */
2641 ret = qla2x00_request_irqs(ha, rsp);
2642 if (ret)
6e9f21f3 2643 goto probe_init_failed;
90a86fc0
JC		 2644
2645 pci_save_state(pdev);
2646
9a347ff4 2647 /* Assign back pointers */
2afa19a9
AC		 2648 rsp->req = req;
2649 req->rsp = rsp;
9a347ff4 2650
8ae6d9c7
GM		 2651 if (IS_QLAFX00(ha)) {
2652 ha->rsp_q_map[0] = rsp;
2653 ha->req_q_map[0] = req;
2654 set_bit(0, ha->req_qid_map);
2655 set_bit(0, ha->rsp_qid_map);
2656 }
2657
08029990
AV		 2658 /* FWI2-capable only. */
2659 req->req_q_in = &ha->iobase->isp24.req_q_in;
2660 req->req_q_out = &ha->iobase->isp24.req_q_out;
2661 rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in;
2662 rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out;
f73cb695 2663 if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
08029990
AV		 2664 req->req_q_in = &ha->mqiobase->isp25mq.req_q_in;
2665 req->req_q_out = &ha->mqiobase->isp25mq.req_q_out;
2666 rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in;
2667 rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out;
17d98630
AC		 2668 }
2669
8ae6d9c7
GM		 2670 if (IS_QLAFX00(ha)) {
2671 req->req_q_in = &ha->iobase->ispfx00.req_q_in;
2672 req->req_q_out = &ha->iobase->ispfx00.req_q_out;
2673 rsp->rsp_q_in = &ha->iobase->ispfx00.rsp_q_in;
2674 rsp->rsp_q_out = &ha->iobase->ispfx00.rsp_q_out;
2675 }
2676
7ec0effd 2677 if (IS_P3P_TYPE(ha)) {
a9083016
GM		 2678 req->req_q_out = &ha->iobase->isp82.req_q_out[0];
2679 rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0];
2680 rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0];
2681 }
2682
7c3df132
SK		 2683 ql_dbg(ql_dbg_multiq, base_vha, 0xc009,
2684 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
2685 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
2686 ql_dbg(ql_dbg_multiq, base_vha, 0xc00a,
2687 "req->req_q_in=%p req->req_q_out=%p "
2688 "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
2689 req->req_q_in, req->req_q_out,
2690 rsp->rsp_q_in, rsp->rsp_q_out);
2691 ql_dbg(ql_dbg_init, base_vha, 0x003e,
2692 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
2693 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
2694 ql_dbg(ql_dbg_init, base_vha, 0x003f,
2695 "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
2696 req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out);
1da177e4 2697
8ae6d9c7 2698 if (ha->isp_ops->initialize_adapter(base_vha)) {
7c3df132
SK		 2699 ql_log(ql_log_fatal, base_vha, 0x00d6,
2700 "Failed to initialize adapter - Adapter flags %x.\n",
2701 base_vha->device_flags);
1da177e4 2702
a9083016
GM		 2703 if (IS_QLA82XX(ha)) {
2704 qla82xx_idc_lock(ha);
2705 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 2706 QLA8XXX_DEV_FAILED);
a9083016 2707 qla82xx_idc_unlock(ha);
7c3df132
SK		 2708 ql_log(ql_log_fatal, base_vha, 0x00d7,
2709 "HW State: FAILED.\n");
7ec0effd
AD		 2710 } else if (IS_QLA8044(ha)) {
2711 qla8044_idc_lock(ha);
2712 qla8044_wr_direct(base_vha,
2713 QLA8044_CRB_DEV_STATE_INDEX,
2714 QLA8XXX_DEV_FAILED);
2715 qla8044_idc_unlock(ha);
2716 ql_log(ql_log_fatal, base_vha, 0x0150,
2717 "HW State: FAILED.\n");
a9083016
GM		 2718 }
2719
a1541d5a 2720 ret = -ENODEV;
1da177e4
LT		 2721 goto probe_failed;
2722 }
2723
3b1bef64
CD		 2724 if (IS_QLAFX00(ha))
2725 host->can_queue = QLAFX00_MAX_CANQUEUE;
2726 else
2727 host->can_queue = req->num_outstanding_cmds - 10;
2728
2729 ql_dbg(ql_dbg_init, base_vha, 0x0032,
2730 "can_queue=%d, req=%p, mgmt_svr_loop_id=%d, sg_tablesize=%d.\n",
2731 host->can_queue, base_vha->req,
2732 base_vha->mgmt_svr_loop_id, host->sg_tablesize);
2733
7163ea81
AC		 2734 if (ha->mqenable) {
2735 if (qla25xx_setup_mode(base_vha)) {
7c3df132
SK		 2736 ql_log(ql_log_warn, base_vha, 0x00ec,
2737 "Failed to create queues, falling back to single queue mode.\n");
7163ea81
AC		 2738 goto que_init;
2739 }
2740 }
68ca949c 2741
cbc8eb67
AV		 2742 if (ha->flags.running_gold_fw)
2743 goto skip_dpc;
2744
1da177e4
LT		 2745 /*
2746 * Startup the kernel thread for this host adapter
2747 */
39a11240 2748 ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha,
7c3df132 2749 "%s_dpc", base_vha->host_str);
39a11240 2750 if (IS_ERR(ha->dpc_thread)) {
7c3df132
SK		 2751 ql_log(ql_log_fatal, base_vha, 0x00ed,
2752 "Failed to start DPC thread.\n");
39a11240 2753 ret = PTR_ERR(ha->dpc_thread);
1da177e4
LT		 2754 goto probe_failed;
2755 }
7c3df132
SK		 2756 ql_dbg(ql_dbg_init, base_vha, 0x00ee,
2757 "DPC thread started successfully.\n");
1da177e4 2758
2d70c103
NB		 2759 /*
2760 * If we're not coming up in initiator mode, we might sit for
2761 * a while without waking up the dpc thread, which leads to a
2762 * stuck process warning. So just kick the dpc once here and
2763 * let the kthread start (and go back to sleep in qla2x00_do_dpc).
2764 */
2765 qla2xxx_wake_dpc(base_vha);
2766
f3ddac19
CD		 2767 INIT_WORK(&ha->board_disable, qla2x00_disable_board_on_pci_error);
2768
81178772
SK		 2769 if (IS_QLA8031(ha) || IS_MCTP_CAPABLE(ha)) {
2770 sprintf(wq_name, "qla2xxx_%lu_dpc_lp_wq", base_vha->host_no);
2771 ha->dpc_lp_wq = create_singlethread_workqueue(wq_name);
2772 INIT_WORK(&ha->idc_aen, qla83xx_service_idc_aen);
2773
2774 sprintf(wq_name, "qla2xxx_%lu_dpc_hp_wq", base_vha->host_no);
2775 ha->dpc_hp_wq = create_singlethread_workqueue(wq_name);
2776 INIT_WORK(&ha->nic_core_reset, qla83xx_nic_core_reset_work);
2777 INIT_WORK(&ha->idc_state_handler,
2778 qla83xx_idc_state_handler_work);
2779 INIT_WORK(&ha->nic_core_unrecoverable,
2780 qla83xx_nic_core_unrecoverable_work);
2781 }
2782
cbc8eb67 2783skip_dpc:
e315cd28
AC		 2784 list_add_tail(&base_vha->list, &ha->vp_list);
2785 base_vha->host->irq = ha->pdev->irq;
1da177e4
LT		 2786
2787 /* Initialized the timer */
e315cd28 2788 qla2x00_start_timer(base_vha, qla2x00_timer, WATCH_INTERVAL);
7c3df132
SK		 2789 ql_dbg(ql_dbg_init, base_vha, 0x00ef,
2790 "Started qla2x00_timer with "
2791 "interval=%d.\n", WATCH_INTERVAL);
2792 ql_dbg(ql_dbg_init, base_vha, 0x00f0,
2793 "Detected hba at address=%p.\n",
2794 ha);
d19044c3 2795
e02587d7 2796 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) {
bad75002 2797 if (ha->fw_attributes & BIT_4) {
9e522cd8 2798 int prot = 0, guard;
bad75002 2799 base_vha->flags.difdix_supported = 1;
7c3df132
SK		 2800 ql_dbg(ql_dbg_init, base_vha, 0x00f1,
2801 "Registering for DIF/DIX type 1 and 3 protection.\n");
8cb2049c
AE		 2802 if (ql2xenabledif == 1)
2803 prot = SHOST_DIX_TYPE0_PROTECTION;
bad75002 2804 scsi_host_set_prot(host,
8cb2049c 2805 prot | SHOST_DIF_TYPE1_PROTECTION
0c470874 2806 | SHOST_DIF_TYPE2_PROTECTION
bad75002
AE		 2807 | SHOST_DIF_TYPE3_PROTECTION
2808 | SHOST_DIX_TYPE1_PROTECTION
0c470874 2809 | SHOST_DIX_TYPE2_PROTECTION
bad75002 2810 | SHOST_DIX_TYPE3_PROTECTION);
9e522cd8
AE		 2811
2812 guard = SHOST_DIX_GUARD_CRC;
2813
2814 if (IS_PI_IPGUARD_CAPABLE(ha) &&
2815 (ql2xenabledif > 1 || IS_PI_DIFB_DIX0_CAPABLE(ha)))
2816 guard |= SHOST_DIX_GUARD_IP;
2817
2818 scsi_host_set_guard(host, guard);
bad75002
AE		 2819 } else
2820 base_vha->flags.difdix_supported = 0;
2821 }
2822
a9083016
GM		 2823 ha->isp_ops->enable_intrs(ha);
2824
1fe19ee4
AB		 2825 if (IS_QLAFX00(ha)) {
2826 ret = qlafx00_fx_disc(base_vha,
2827 &base_vha->hw->mr.fcport, FXDISC_GET_CONFIG_INFO);
2828 host->sg_tablesize = (ha->mr.extended_io_enabled) ?
2829 QLA_SG_ALL : 128;
2830 }
2831
a1541d5a
AV		 2832 ret = scsi_add_host(host, &pdev->dev);
2833 if (ret)
2834 goto probe_failed;
2835
1486400f
MR		 2836 base_vha->flags.init_done = 1;
2837 base_vha->flags.online = 1;
edaa5c74 2838 ha->prev_minidump_failed = 0;
1486400f 2839
7c3df132
SK		 2840 ql_dbg(ql_dbg_init, base_vha, 0x00f2,
2841 "Init done and hba is online.\n");
2842
2d70c103
NB		 2843 if (qla_ini_mode_enabled(base_vha))
2844 scsi_scan_host(host);
2845 else
2846 ql_dbg(ql_dbg_init, base_vha, 0x0122,
2847 "skipping scsi_scan_host() for non-initiator port\n");
1e99e33a 2848
e315cd28 2849 qla2x00_alloc_sysfs_attr(base_vha);
a1541d5a 2850
8ae6d9c7 2851 if (IS_QLAFX00(ha)) {
8ae6d9c7
GM		 2852 ret = qlafx00_fx_disc(base_vha,
2853 &base_vha->hw->mr.fcport, FXDISC_GET_PORT_INFO);
2854
2855 /* Register system information */
2856 ret = qlafx00_fx_disc(base_vha,
2857 &base_vha->hw->mr.fcport, FXDISC_REG_HOST_INFO);
2858 }
2859
e315cd28 2860 qla2x00_init_host_attr(base_vha);
a1541d5a 2861
e315cd28 2862 qla2x00_dfs_setup(base_vha);
df613b96 2863
03eb912a
AB		 2864 ql_log(ql_log_info, base_vha, 0x00fb,
2865 "QLogic %s - %s.\n", ha->model_number, ha->model_desc);
7c3df132
SK		 2866 ql_log(ql_log_info, base_vha, 0x00fc,
2867 "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n",
2868 pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info),
2869 pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-',
2870 base_vha->host_no,
df57caba 2871 ha->isp_ops->fw_version_str(base_vha, fw_str, sizeof(fw_str)));
1da177e4 2872
2d70c103
NB		 2873 qlt_add_target(ha, base_vha);
2874
6b383979 2875 clear_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags);
1da177e4
LT		 2876 return 0;
2877
6e9f21f3 2878probe_init_failed:
2afa19a9 2879 qla2x00_free_req_que(ha, req);
9a347ff4
CD		 2880 ha->req_q_map[0] = NULL;
2881 clear_bit(0, ha->req_qid_map);
2afa19a9 2882 qla2x00_free_rsp_que(ha, rsp);
9a347ff4
CD		 2883 ha->rsp_q_map[0] = NULL;
2884 clear_bit(0, ha->rsp_qid_map);
2afa19a9 2885 ha->max_req_queues = ha->max_rsp_queues = 0;
6e9f21f3 2886
1da177e4 2887probe_failed:
b9978769
AV		 2888 if (base_vha->timer_active)
2889 qla2x00_stop_timer(base_vha);
2890 base_vha->flags.online = 0;
2891 if (ha->dpc_thread) {
2892 struct task_struct *t = ha->dpc_thread;
2893
2894 ha->dpc_thread = NULL;
2895 kthread_stop(t);
2896 }
2897
e315cd28 2898 qla2x00_free_device(base_vha);
1da177e4 2899
e315cd28 2900 scsi_host_put(base_vha->host);
1da177e4 2901
e315cd28 2902probe_hw_failed:
1a2fbf18
JL		 2903 qla2x00_clear_drv_active(ha);
2904
0a63ad12 2905iospace_config_failed:
7ec0effd 2906 if (IS_P3P_TYPE(ha)) {
0a63ad12 2907 if (!ha->nx_pcibase)
f73cb695 2908 iounmap((device_reg_t *)ha->nx_pcibase);
a9083016 2909 if (!ql2xdbwr)
f73cb695 2910 iounmap((device_reg_t *)ha->nxdb_wr_ptr);
a9083016
GM		 2911 } else {
2912 if (ha->iobase)
2913 iounmap(ha->iobase);
8ae6d9c7
GM		 2914 if (ha->cregbase)
2915 iounmap(ha->cregbase);
a9083016 2916 }
e315cd28
AC		 2917 pci_release_selected_regions(ha->pdev, ha->bars);
2918 kfree(ha);
2919 ha = NULL;
1da177e4 2920
a1541d5a 2921probe_out:
e315cd28 2922 pci_disable_device(pdev);
a1541d5a 2923 return ret;
1da177e4 2924}
1da177e4 2925
e30d1756
MI		 2926static void
2927qla2x00_shutdown(struct pci_dev *pdev)
2928{
2929 scsi_qla_host_t *vha;
2930 struct qla_hw_data *ha;
2931
552f3f9a
MI		 2932 if (!atomic_read(&pdev->enable_cnt))
2933 return;
2934
e30d1756
MI		 2935 vha = pci_get_drvdata(pdev);
2936 ha = vha->hw;
2937
42479343
AB		 2938 /* Notify ISPFX00 firmware */
2939 if (IS_QLAFX00(ha))
2940 qlafx00_driver_shutdown(vha, 20);
2941
e30d1756
MI		 2942 /* Turn-off FCE trace */
2943 if (ha->flags.fce_enabled) {
2944 qla2x00_disable_fce_trace(vha, NULL, NULL);
2945 ha->flags.fce_enabled = 0;
2946 }
2947
2948 /* Turn-off EFT trace */
2949 if (ha->eft)
2950 qla2x00_disable_eft_trace(vha);
2951
2952 /* Stop currently executing firmware. */
2953 qla2x00_try_to_stop_firmware(vha);
2954
2955 /* Turn adapter off line */
2956 vha->flags.online = 0;
2957
2958 /* turn-off interrupts on the card */
2959 if (ha->interrupts_on) {
2960 vha->flags.init_done = 0;
2961 ha->isp_ops->disable_intrs(ha);
2962 }
2963
2964 qla2x00_free_irqs(vha);
2965
2966 qla2x00_free_fw_dump(ha);
61d41f61
CD		 2967
2968 pci_disable_pcie_error_reporting(pdev);
2969 pci_disable_device(pdev);
e30d1756
MI		 2970}
2971
fe1b806f 2972/* Deletes all the virtual ports for a given ha */
4c993f76 2973static void
fe1b806f 2974qla2x00_delete_all_vps(struct qla_hw_data *ha, scsi_qla_host_t *base_vha)
1da177e4 2975{
fe1b806f
CD		 2976 struct Scsi_Host *scsi_host;
2977 scsi_qla_host_t *vha;
feafb7b1 2978 unsigned long flags;
e315cd28 2979
43ebf16d
AE		 2980 mutex_lock(&ha->vport_lock);
2981 while (ha->cur_vport_count) {
43ebf16d 2982 spin_lock_irqsave(&ha->vport_slock, flags);
feafb7b1 2983
43ebf16d
AE		 2984 BUG_ON(base_vha->list.next == &ha->vp_list);
2985 /* This assumes first entry in ha->vp_list is always base vha */
2986 vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list);
fe1b806f 2987 scsi_host = scsi_host_get(vha->host);
feafb7b1 2988
43ebf16d
AE		 2989 spin_unlock_irqrestore(&ha->vport_slock, flags);
2990 mutex_unlock(&ha->vport_lock);
2991
2992 fc_vport_terminate(vha->fc_vport);
2993 scsi_host_put(vha->host);
feafb7b1 2994
43ebf16d 2995 mutex_lock(&ha->vport_lock);
e315cd28 2996 }
43ebf16d 2997 mutex_unlock(&ha->vport_lock);
fe1b806f 2998}
1da177e4 2999
fe1b806f
CD		 3000/* Stops all deferred work threads */
3001static void
3002qla2x00_destroy_deferred_work(struct qla_hw_data *ha)
3003{
68ca949c
AC		 3004 /* Flush the work queue and remove it */
3005 if (ha->wq) {
3006 flush_workqueue(ha->wq);
3007 destroy_workqueue(ha->wq);
3008 ha->wq = NULL;
3009 }
3010
7d613ac6
SV		 3011 /* Cancel all work and destroy DPC workqueues */
3012 if (ha->dpc_lp_wq) {
3013 cancel_work_sync(&ha->idc_aen);
3014 destroy_workqueue(ha->dpc_lp_wq);
3015 ha->dpc_lp_wq = NULL;
3016 }
3017
3018 if (ha->dpc_hp_wq) {
3019 cancel_work_sync(&ha->nic_core_reset);
3020 cancel_work_sync(&ha->idc_state_handler);
3021 cancel_work_sync(&ha->nic_core_unrecoverable);
3022 destroy_workqueue(ha->dpc_hp_wq);
3023 ha->dpc_hp_wq = NULL;
3024 }
3025
b9978769
AV		 3026 /* Kill the kernel thread for this host */
3027 if (ha->dpc_thread) {
3028 struct task_struct *t = ha->dpc_thread;
3029
3030 /*
3031 * qla2xxx_wake_dpc checks for ->dpc_thread
3032 * so we need to zero it out.
3033 */
3034 ha->dpc_thread = NULL;
3035 kthread_stop(t);
3036 }
fe1b806f 3037}
1da177e4 3038
fe1b806f
CD		 3039static void
3040qla2x00_unmap_iobases(struct qla_hw_data *ha)
3041{
a9083016 3042 if (IS_QLA82XX(ha)) {
b963752f 3043
f73cb695 3044 iounmap((device_reg_t *)ha->nx_pcibase);
a9083016 3045 if (!ql2xdbwr)
f73cb695 3046 iounmap((device_reg_t *)ha->nxdb_wr_ptr);
a9083016
GM		 3047 } else {
3048 if (ha->iobase)
3049 iounmap(ha->iobase);
1da177e4 3050
8ae6d9c7
GM		 3051 if (ha->cregbase)
3052 iounmap(ha->cregbase);
3053
a9083016
GM		 3054 if (ha->mqiobase)
3055 iounmap(ha->mqiobase);
6246b8a1 3056
f73cb695 3057 if ((IS_QLA83XX(ha) || IS_QLA27XX(ha)) && ha->msixbase)
6246b8a1 3058 iounmap(ha->msixbase);
a9083016 3059 }
fe1b806f
CD		 3060}
3061
3062static void
db7157d4 3063qla2x00_clear_drv_active(struct qla_hw_data *ha)
fe1b806f 3064{
fe1b806f
CD		 3065 if (IS_QLA8044(ha)) {
3066 qla8044_idc_lock(ha);
c41afc9a 3067 qla8044_clear_drv_active(ha);
fe1b806f
CD		 3068 qla8044_idc_unlock(ha);
3069 } else if (IS_QLA82XX(ha)) {
3070 qla82xx_idc_lock(ha);
3071 qla82xx_clear_drv_active(ha);
3072 qla82xx_idc_unlock(ha);
3073 }
3074}
3075
3076static void
3077qla2x00_remove_one(struct pci_dev *pdev)
3078{
3079 scsi_qla_host_t *base_vha;
3080 struct qla_hw_data *ha;
3081
beb9e315
JL		 3082 base_vha = pci_get_drvdata(pdev);
3083 ha = base_vha->hw;
3084
3085 /* Indicate device removal to prevent future board_disable and wait
3086 * until any pending board_disable has completed. */
3087 set_bit(PFLG_DRIVER_REMOVING, &base_vha->pci_flags);
3088 cancel_work_sync(&ha->board_disable);
3089
fe1b806f 3090 /*
beb9e315
JL		 3091 * If the PCI device is disabled then there was a PCI-disconnect and
3092 * qla2x00_disable_board_on_pci_error has taken care of most of the
3093 * resources.
fe1b806f 3094 */
beb9e315
JL		 3095 if (!atomic_read(&pdev->enable_cnt)) {
3096 scsi_host_put(base_vha->host);
3097 kfree(ha);
3098 pci_set_drvdata(pdev, NULL);
fe1b806f 3099 return;
beb9e315 3100 }
fe1b806f 3101
638a1a01
SC		 3102 qla2x00_wait_for_hba_ready(base_vha);
3103
fe1b806f
CD		 3104 set_bit(UNLOADING, &base_vha->dpc_flags);
3105
3106 if (IS_QLAFX00(ha))
3107 qlafx00_driver_shutdown(base_vha, 20);
3108
3109 qla2x00_delete_all_vps(ha, base_vha);
3110
3111 if (IS_QLA8031(ha)) {
3112 ql_dbg(ql_dbg_p3p, base_vha, 0xb07e,
3113 "Clearing fcoe driver presence.\n");
3114 if (qla83xx_clear_drv_presence(base_vha) != QLA_SUCCESS)
3115 ql_dbg(ql_dbg_p3p, base_vha, 0xb079,
3116 "Error while clearing DRV-Presence.\n");
3117 }
3118
3119 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
3120
3121 qla2x00_dfs_remove(base_vha);
3122
3123 qla84xx_put_chip(base_vha);
3124
2d5a4c34
HM		 3125 /* Laser should be disabled only for ISP2031 */
3126 if (IS_QLA2031(ha))
3127 qla83xx_disable_laser(base_vha);
3128
fe1b806f
CD		 3129 /* Disable timer */
3130 if (base_vha->timer_active)
3131 qla2x00_stop_timer(base_vha);
3132
3133 base_vha->flags.online = 0;
3134
3135 qla2x00_destroy_deferred_work(ha);
3136
3137 qlt_remove_target(ha, base_vha);
3138
3139 qla2x00_free_sysfs_attr(base_vha, true);
3140
3141 fc_remove_host(base_vha->host);
3142
3143 scsi_remove_host(base_vha->host);
3144
3145 qla2x00_free_device(base_vha);
3146
db7157d4 3147 qla2x00_clear_drv_active(ha);
fe1b806f 3148
d2749ffa
AE		 3149 scsi_host_put(base_vha->host);
3150
fe1b806f 3151 qla2x00_unmap_iobases(ha);
73208dfd 3152
e315cd28
AC		 3153 pci_release_selected_regions(ha->pdev, ha->bars);
3154 kfree(ha);
3155 ha = NULL;
1da177e4 3156
90a86fc0
JC		 3157 pci_disable_pcie_error_reporting(pdev);
3158
665db93b 3159 pci_disable_device(pdev);
1da177e4 3160}
1da177e4
LT		 3161
3162static void
e315cd28 3163qla2x00_free_device(scsi_qla_host_t *vha)
1da177e4 3164{
e315cd28 3165 struct qla_hw_data *ha = vha->hw;
1da177e4 3166
85880801
AV		 3167 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
3168
3169 /* Disable timer */
3170 if (vha->timer_active)
3171 qla2x00_stop_timer(vha);
3172
2afa19a9 3173 qla25xx_delete_queues(vha);
fe1b806f 3174
df613b96 3175 if (ha->flags.fce_enabled)
e315cd28 3176 qla2x00_disable_fce_trace(vha, NULL, NULL);
df613b96 3177
a7a167bf 3178 if (ha->eft)
e315cd28 3179 qla2x00_disable_eft_trace(vha);
a7a167bf 3180
f6ef3b18 3181 /* Stop currently executing firmware. */
e315cd28 3182 qla2x00_try_to_stop_firmware(vha);
1da177e4 3183
85880801
AV		 3184 vha->flags.online = 0;
3185
f6ef3b18 3186 /* turn-off interrupts on the card */
a9083016
GM		 3187 if (ha->interrupts_on) {
3188 vha->flags.init_done = 0;
fd34f556 3189 ha->isp_ops->disable_intrs(ha);
a9083016 3190 }
f6ef3b18 3191
e315cd28 3192 qla2x00_free_irqs(vha);
1da177e4 3193
8867048b
CD		 3194 qla2x00_free_fcports(vha);
3195
e315cd28 3196 qla2x00_mem_free(ha);
73208dfd 3197
08de2844
GM		 3198 qla82xx_md_free(vha);
3199
73208dfd 3200 qla2x00_free_queues(ha);
1da177e4
LT		 3201}
3202
8867048b
CD		 3203void qla2x00_free_fcports(struct scsi_qla_host *vha)
3204{
3205 fc_port_t *fcport, *tfcport;
3206
3207 list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list) {
3208 list_del(&fcport->list);
5f16b331 3209 qla2x00_clear_loop_id(fcport);
8867048b
CD		 3210 kfree(fcport);
3211 fcport = NULL;
3212 }
3213}
3214
d97994dc 3215static inline void
e315cd28 3216qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport,
d97994dc 3217 int defer)
3218{
d97994dc 3219 struct fc_rport *rport;
67becc00 3220 scsi_qla_host_t *base_vha;
044d78e1 3221 unsigned long flags;
d97994dc 3222
3223 if (!fcport->rport)
3224 return;
3225
3226 rport = fcport->rport;
3227 if (defer) {
67becc00 3228 base_vha = pci_get_drvdata(vha->hw->pdev);
044d78e1 3229 spin_lock_irqsave(vha->host->host_lock, flags);
d97994dc 3230 fcport->drport = rport;
044d78e1 3231 spin_unlock_irqrestore(vha->host->host_lock, flags);
67becc00
AV		 3232 set_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags);
3233 qla2xxx_wake_dpc(base_vha);
2d70c103 3234 } else {
d97994dc 3235 fc_remote_port_delete(rport);
2d70c103
NB		 3236 qlt_fc_port_deleted(vha, fcport);
3237 }
d97994dc 3238}
3239
1da177e4
LT		 3240/*
3241 * qla2x00_mark_device_lost Updates fcport state when device goes offline.
3242 *
3243 * Input: ha = adapter block pointer. fcport = port structure pointer.
3244 *
3245 * Return: None.
3246 *
3247 * Context:
3248 */
e315cd28 3249void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport,
d97994dc 3250 int do_login, int defer)
1da177e4 3251{
8ae6d9c7
GM		 3252 if (IS_QLAFX00(vha->hw)) {
3253 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
3254 qla2x00_schedule_rport_del(vha, fcport, defer);
3255 return;
3256 }
3257
2c3dfe3f 3258 if (atomic_read(&fcport->state) == FCS_ONLINE &&
c6d39e23 3259 vha->vp_idx == fcport->vha->vp_idx) {
ec426e10 3260 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
e315cd28
AC		 3261 qla2x00_schedule_rport_del(vha, fcport, defer);
3262 }
fa2a1ce5 3263 /*
1da177e4
LT		 3264 * We may need to retry the login, so don't change the state of the
3265 * port but do the retries.
3266 */
3267 if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD)
ec426e10 3268 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
1da177e4
LT		 3269
3270 if (!do_login)
3271 return;
3272
3273 if (fcport->login_retry == 0) {
e315cd28
AC		 3274 fcport->login_retry = vha->hw->login_retry_count;
3275 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
1da177e4 3276
7c3df132 3277 ql_dbg(ql_dbg_disc, vha, 0x2067,
7b833558
OK		 3278 "Port login retry %8phN, id = 0x%04x retry cnt=%d.\n",
3279 fcport->port_name, fcport->loop_id, fcport->login_retry);
1da177e4
LT		 3280 }
3281}
3282
3283/*
3284 * qla2x00_mark_all_devices_lost
3285 * Updates fcport state when device goes offline.
3286 *
3287 * Input:
3288 * ha = adapter block pointer.
3289 * fcport = port structure pointer.
3290 *
3291 * Return:
3292 * None.
3293 *
3294 * Context:
3295 */
3296void
e315cd28 3297qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha, int defer)
1da177e4
LT		 3298{
3299 fc_port_t *fcport;
3300
e315cd28 3301 list_for_each_entry(fcport, &vha->vp_fcports, list) {
c6d39e23 3302 if (vha->vp_idx != 0 && vha->vp_idx != fcport->vha->vp_idx)
1da177e4 3303 continue;
0d6e61bc 3304
1da177e4
LT		 3305 /*
3306 * No point in marking the device as lost, if the device is
3307 * already DEAD.
3308 */
3309 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD)
3310 continue;
e315cd28 3311 if (atomic_read(&fcport->state) == FCS_ONLINE) {
ec426e10 3312 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
0d6e61bc
AV		 3313 if (defer)
3314 qla2x00_schedule_rport_del(vha, fcport, defer);
c6d39e23 3315 else if (vha->vp_idx == fcport->vha->vp_idx)
0d6e61bc
AV		 3316 qla2x00_schedule_rport_del(vha, fcport, defer);
3317 }
1da177e4
LT		 3318 }
3319}
3320
3321/*
3322* qla2x00_mem_alloc
3323* Allocates adapter memory.
3324*
3325* Returns:
3326* 0 = success.
e8711085 3327* !0 = failure.
1da177e4 3328*/
e8711085 3329static int
73208dfd
AC		 3330qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len,
3331 struct req_que **req, struct rsp_que **rsp)
1da177e4
LT		 3332{
3333 char name[16];
1da177e4 3334
e8711085 3335 ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size,
e315cd28 3336 &ha->init_cb_dma, GFP_KERNEL);
e8711085 3337 if (!ha->init_cb)
e315cd28 3338 goto fail;
e8711085 3339
2d70c103
NB		 3340 if (qlt_mem_alloc(ha) < 0)
3341 goto fail_free_init_cb;
3342
642ef983
CD		 3343 ha->gid_list = dma_alloc_coherent(&ha->pdev->dev,
3344 qla2x00_gid_list_size(ha), &ha->gid_list_dma, GFP_KERNEL);
e315cd28 3345 if (!ha->gid_list)
2d70c103 3346 goto fail_free_tgt_mem;
1da177e4 3347
e8711085
AV		 3348 ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep);
3349 if (!ha->srb_mempool)
e315cd28 3350 goto fail_free_gid_list;
e8711085 3351
7ec0effd 3352 if (IS_P3P_TYPE(ha)) {
a9083016
GM		 3353 /* Allocate cache for CT6 Ctx. */
3354 if (!ctx_cachep) {
3355 ctx_cachep = kmem_cache_create("qla2xxx_ctx",
3356 sizeof(struct ct6_dsd), 0,
3357 SLAB_HWCACHE_ALIGN, NULL);
3358 if (!ctx_cachep)
3359 goto fail_free_gid_list;
3360 }
3361 ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ,
3362 ctx_cachep);
3363 if (!ha->ctx_mempool)
3364 goto fail_free_srb_mempool;
7c3df132
SK		 3365 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021,
3366 "ctx_cachep=%p ctx_mempool=%p.\n",
3367 ctx_cachep, ha->ctx_mempool);
a9083016
GM		 3368 }
3369
e8711085
AV		 3370 /* Get memory for cached NVRAM */
3371 ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL);
3372 if (!ha->nvram)
a9083016 3373 goto fail_free_ctx_mempool;
e8711085 3374
e315cd28
AC		 3375 snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME,
3376 ha->pdev->device);
3377 ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3378 DMA_POOL_SIZE, 8, 0);
3379 if (!ha->s_dma_pool)
3380 goto fail_free_nvram;
3381
7c3df132
SK		 3382 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022,
3383 "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n",
3384 ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool);
3385
7ec0effd 3386 if (IS_P3P_TYPE(ha) || ql2xenabledif) {
a9083016
GM		 3387 ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3388 DSD_LIST_DMA_POOL_SIZE, 8, 0);
3389 if (!ha->dl_dma_pool) {
7c3df132
SK		 3390 ql_log_pci(ql_log_fatal, ha->pdev, 0x0023,
3391 "Failed to allocate memory for dl_dma_pool.\n");
a9083016
GM		 3392 goto fail_s_dma_pool;
3393 }
3394
3395 ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3396 FCP_CMND_DMA_POOL_SIZE, 8, 0);
3397 if (!ha->fcp_cmnd_dma_pool) {
7c3df132
SK		 3398 ql_log_pci(ql_log_fatal, ha->pdev, 0x0024,
3399 "Failed to allocate memory for fcp_cmnd_dma_pool.\n");
a9083016
GM		 3400 goto fail_dl_dma_pool;
3401 }
7c3df132
SK		 3402 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025,
3403 "dl_dma_pool=%p fcp_cmnd_dma_pool=%p.\n",
3404 ha->dl_dma_pool, ha->fcp_cmnd_dma_pool);
a9083016
GM		 3405 }
3406
e8711085
AV		 3407 /* Allocate memory for SNS commands */
3408 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
e315cd28 3409 /* Get consistent memory allocated for SNS commands */
e8711085 3410 ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev,
e315cd28 3411 sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL);
e8711085 3412 if (!ha->sns_cmd)
e315cd28 3413 goto fail_dma_pool;
7c3df132 3414 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026,
d8424f68 3415 "sns_cmd: %p.\n", ha->sns_cmd);
e8711085 3416 } else {
e315cd28 3417 /* Get consistent memory allocated for MS IOCB */
e8711085 3418 ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
e315cd28 3419 &ha->ms_iocb_dma);
e8711085 3420 if (!ha->ms_iocb)
e315cd28
AC		 3421 goto fail_dma_pool;
3422 /* Get consistent memory allocated for CT SNS commands */
e8711085 3423 ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev,
e315cd28 3424 sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL);
e8711085
AV		 3425 if (!ha->ct_sns)
3426 goto fail_free_ms_iocb;
7c3df132
SK		 3427 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027,
3428 "ms_iocb=%p ct_sns=%p.\n",
3429 ha->ms_iocb, ha->ct_sns);
1da177e4
LT		 3430 }
3431
e315cd28 3432 /* Allocate memory for request ring */
73208dfd
AC		 3433 *req = kzalloc(sizeof(struct req_que), GFP_KERNEL);
3434 if (!*req) {
7c3df132
SK		 3435 ql_log_pci(ql_log_fatal, ha->pdev, 0x0028,
3436 "Failed to allocate memory for req.\n");
e315cd28
AC		 3437 goto fail_req;
3438 }
73208dfd
AC		 3439 (*req)->length = req_len;
3440 (*req)->ring = dma_alloc_coherent(&ha->pdev->dev,
3441 ((*req)->length + 1) * sizeof(request_t),
3442 &(*req)->dma, GFP_KERNEL);
3443 if (!(*req)->ring) {
7c3df132
SK		 3444 ql_log_pci(ql_log_fatal, ha->pdev, 0x0029,
3445 "Failed to allocate memory for req_ring.\n");
e315cd28
AC		 3446 goto fail_req_ring;
3447 }
3448 /* Allocate memory for response ring */
73208dfd
AC		 3449 *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL);
3450 if (!*rsp) {
7c3df132
SK		 3451 ql_log_pci(ql_log_fatal, ha->pdev, 0x002a,
3452 "Failed to allocate memory for rsp.\n");
e315cd28
AC		 3453 goto fail_rsp;
3454 }
73208dfd
AC		 3455 (*rsp)->hw = ha;
3456 (*rsp)->length = rsp_len;
3457 (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev,
3458 ((*rsp)->length + 1) * sizeof(response_t),
3459 &(*rsp)->dma, GFP_KERNEL);
3460 if (!(*rsp)->ring) {
7c3df132
SK		 3461 ql_log_pci(ql_log_fatal, ha->pdev, 0x002b,
3462 "Failed to allocate memory for rsp_ring.\n");
e315cd28
AC		 3463 goto fail_rsp_ring;
3464 }
73208dfd
AC		 3465 (*req)->rsp = *rsp;
3466 (*rsp)->req = *req;
7c3df132
SK		 3467 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c,
3468 "req=%p req->length=%d req->ring=%p rsp=%p "
3469 "rsp->length=%d rsp->ring=%p.\n",
3470 *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length,
3471 (*rsp)->ring);
73208dfd
AC		 3472 /* Allocate memory for NVRAM data for vports */
3473 if (ha->nvram_npiv_size) {
3474 ha->npiv_info = kzalloc(sizeof(struct qla_npiv_entry) *
7c3df132 3475 ha->nvram_npiv_size, GFP_KERNEL);
73208dfd 3476 if (!ha->npiv_info) {
7c3df132
SK		 3477 ql_log_pci(ql_log_fatal, ha->pdev, 0x002d,
3478 "Failed to allocate memory for npiv_info.\n");
73208dfd
AC		 3479 goto fail_npiv_info;
3480 }
3481 } else
3482 ha->npiv_info = NULL;
e8711085 3483
b64b0e8f 3484 /* Get consistent memory allocated for EX-INIT-CB. */
f73cb695 3485 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha)) {
b64b0e8f
AV		 3486 ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
3487 &ha->ex_init_cb_dma);
3488 if (!ha->ex_init_cb)
3489 goto fail_ex_init_cb;
7c3df132
SK		 3490 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e,
3491 "ex_init_cb=%p.\n", ha->ex_init_cb);
b64b0e8f
AV		 3492 }
3493
a9083016
GM		 3494 INIT_LIST_HEAD(&ha->gbl_dsd_list);
3495
5ff1d584
AV		 3496 /* Get consistent memory allocated for Async Port-Database. */
3497 if (!IS_FWI2_CAPABLE(ha)) {
3498 ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
3499 &ha->async_pd_dma);
3500 if (!ha->async_pd)
3501 goto fail_async_pd;
7c3df132
SK		 3502 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f,
3503 "async_pd=%p.\n", ha->async_pd);
5ff1d584
AV		 3504 }
3505
e315cd28 3506 INIT_LIST_HEAD(&ha->vp_list);
5f16b331
CD		 3507
3508 /* Allocate memory for our loop_id bitmap */
3509 ha->loop_id_map = kzalloc(BITS_TO_LONGS(LOOPID_MAP_SIZE) * sizeof(long),
3510 GFP_KERNEL);
3511 if (!ha->loop_id_map)
3512 goto fail_async_pd;
3513 else {
3514 qla2x00_set_reserved_loop_ids(ha);
3515 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0123,
b2a72ec3 3516 "loop_id_map=%p.\n", ha->loop_id_map);
5f16b331
CD		 3517 }
3518
b2a72ec3 3519 return 0;
e315cd28 3520
5ff1d584
AV		 3521fail_async_pd:
3522 dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma);
b64b0e8f
AV		 3523fail_ex_init_cb:
3524 kfree(ha->npiv_info);
73208dfd
AC		 3525fail_npiv_info:
3526 dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) *
3527 sizeof(response_t), (*rsp)->ring, (*rsp)->dma);
3528 (*rsp)->ring = NULL;
3529 (*rsp)->dma = 0;
e315cd28 3530fail_rsp_ring:
73208dfd 3531 kfree(*rsp);
e315cd28 3532fail_rsp:
73208dfd
AC		 3533 dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) *
3534 sizeof(request_t), (*req)->ring, (*req)->dma);
3535 (*req)->ring = NULL;
3536 (*req)->dma = 0;
e315cd28 3537fail_req_ring:
73208dfd 3538 kfree(*req);
e315cd28
AC		 3539fail_req:
3540 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
3541 ha->ct_sns, ha->ct_sns_dma);
3542 ha->ct_sns = NULL;
3543 ha->ct_sns_dma = 0;
e8711085
AV		 3544fail_free_ms_iocb:
3545 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
3546 ha->ms_iocb = NULL;
3547 ha->ms_iocb_dma = 0;
e315cd28 3548fail_dma_pool:
bad75002 3549 if (IS_QLA82XX(ha) || ql2xenabledif) {
a9083016
GM		 3550 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
3551 ha->fcp_cmnd_dma_pool = NULL;
3552 }
3553fail_dl_dma_pool:
bad75002 3554 if (IS_QLA82XX(ha) || ql2xenabledif) {
a9083016
GM		 3555 dma_pool_destroy(ha->dl_dma_pool);
3556 ha->dl_dma_pool = NULL;
3557 }
3558fail_s_dma_pool:
e315cd28
AC		 3559 dma_pool_destroy(ha->s_dma_pool);
3560 ha->s_dma_pool = NULL;
e8711085
AV		 3561fail_free_nvram:
3562 kfree(ha->nvram);
3563 ha->nvram = NULL;
a9083016
GM		 3564fail_free_ctx_mempool:
3565 mempool_destroy(ha->ctx_mempool);
3566 ha->ctx_mempool = NULL;
e8711085
AV		 3567fail_free_srb_mempool:
3568 mempool_destroy(ha->srb_mempool);
3569 ha->srb_mempool = NULL;
e8711085 3570fail_free_gid_list:
642ef983
CD		 3571 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
3572 ha->gid_list,
e315cd28 3573 ha->gid_list_dma);
e8711085
AV		 3574 ha->gid_list = NULL;
3575 ha->gid_list_dma = 0;
2d70c103
NB		 3576fail_free_tgt_mem:
3577 qlt_mem_free(ha);
e315cd28
AC		 3578fail_free_init_cb:
3579 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb,
3580 ha->init_cb_dma);
3581 ha->init_cb = NULL;
3582 ha->init_cb_dma = 0;
e8711085 3583fail:
7c3df132
SK		 3584 ql_log(ql_log_fatal, NULL, 0x0030,
3585 "Memory allocation failure.\n");
e8711085 3586 return -ENOMEM;
1da177e4
LT		 3587}
3588
3589/*
e30d1756
MI		 3590* qla2x00_free_fw_dump
3591* Frees fw dump stuff.
1da177e4
LT		 3592*
3593* Input:
7ec0effd 3594* ha = adapter block pointer
1da177e4 3595*/
a824ebb3 3596static void
e30d1756 3597qla2x00_free_fw_dump(struct qla_hw_data *ha)
1da177e4 3598{
df613b96 3599 if (ha->fce)
f73cb695
CD		 3600 dma_free_coherent(&ha->pdev->dev,
3601 FCE_SIZE, ha->fce, ha->fce_dma);
df613b96 3602
f73cb695
CD		 3603 if (ha->eft)
3604 dma_free_coherent(&ha->pdev->dev,
3605 EFT_SIZE, ha->eft, ha->eft_dma);
3606
3607 if (ha->fw_dump)
a7a167bf 3608 vfree(ha->fw_dump);
f73cb695
CD		 3609 if (ha->fw_dump_template)
3610 vfree(ha->fw_dump_template);
3611
e30d1756
MI		 3612 ha->fce = NULL;
3613 ha->fce_dma = 0;
3614 ha->eft = NULL;
3615 ha->eft_dma = 0;
e30d1756 3616 ha->fw_dumped = 0;
61f098dd 3617 ha->fw_dump_cap_flags = 0;
e30d1756 3618 ha->fw_dump_reading = 0;
f73cb695
CD		 3619 ha->fw_dump = NULL;
3620 ha->fw_dump_len = 0;
3621 ha->fw_dump_template = NULL;
3622 ha->fw_dump_template_len = 0;
e30d1756
MI		 3623}
3624
3625/*
3626* qla2x00_mem_free
3627* Frees all adapter allocated memory.
3628*
3629* Input:
3630* ha = adapter block pointer.
3631*/
3632static void
3633qla2x00_mem_free(struct qla_hw_data *ha)
3634{
3635 qla2x00_free_fw_dump(ha);
3636
81178772
SK		 3637 if (ha->mctp_dump)
3638 dma_free_coherent(&ha->pdev->dev, MCTP_DUMP_SIZE, ha->mctp_dump,
3639 ha->mctp_dump_dma);
3640
e30d1756
MI		 3641 if (ha->srb_mempool)
3642 mempool_destroy(ha->srb_mempool);
a7a167bf 3643
11bbc1d8
AV		 3644 if (ha->dcbx_tlv)
3645 dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE,
3646 ha->dcbx_tlv, ha->dcbx_tlv_dma);
3647
ce0423f4
AV		 3648 if (ha->xgmac_data)
3649 dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE,
3650 ha->xgmac_data, ha->xgmac_data_dma);
3651
1da177e4
LT		 3652 if (ha->sns_cmd)
3653 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
e315cd28 3654 ha->sns_cmd, ha->sns_cmd_dma);
1da177e4
LT		 3655
3656 if (ha->ct_sns)
3657 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
e315cd28 3658 ha->ct_sns, ha->ct_sns_dma);
1da177e4 3659
88729e53
AV		 3660 if (ha->sfp_data)
3661 dma_pool_free(ha->s_dma_pool, ha->sfp_data, ha->sfp_data_dma);
3662
1da177e4
LT		 3663 if (ha->ms_iocb)
3664 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
3665
b64b0e8f 3666 if (ha->ex_init_cb)
a9083016
GM		 3667 dma_pool_free(ha->s_dma_pool,
3668 ha->ex_init_cb, ha->ex_init_cb_dma);
b64b0e8f 3669
5ff1d584
AV		 3670 if (ha->async_pd)
3671 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
3672
1da177e4
LT		 3673 if (ha->s_dma_pool)
3674 dma_pool_destroy(ha->s_dma_pool);
3675
1da177e4 3676 if (ha->gid_list)
642ef983
CD		 3677 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
3678 ha->gid_list, ha->gid_list_dma);
1da177e4 3679
a9083016
GM		 3680 if (IS_QLA82XX(ha)) {
3681 if (!list_empty(&ha->gbl_dsd_list)) {
3682 struct dsd_dma *dsd_ptr, *tdsd_ptr;
3683
3684 /* clean up allocated prev pool */
3685 list_for_each_entry_safe(dsd_ptr,
3686 tdsd_ptr, &ha->gbl_dsd_list, list) {
3687 dma_pool_free(ha->dl_dma_pool,
3688 dsd_ptr->dsd_addr, dsd_ptr->dsd_list_dma);
3689 list_del(&dsd_ptr->list);
3690 kfree(dsd_ptr);
3691 }
3692 }
3693 }
3694
3695 if (ha->dl_dma_pool)
3696 dma_pool_destroy(ha->dl_dma_pool);
3697
3698 if (ha->fcp_cmnd_dma_pool)
3699 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
3700
3701 if (ha->ctx_mempool)
3702 mempool_destroy(ha->ctx_mempool);
3703
2d70c103
NB		 3704 qlt_mem_free(ha);
3705
e315cd28
AC		 3706 if (ha->init_cb)
3707 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size,
a9083016 3708 ha->init_cb, ha->init_cb_dma);
e315cd28
AC		 3709 vfree(ha->optrom_buffer);
3710 kfree(ha->nvram);
73208dfd 3711 kfree(ha->npiv_info);
7a67735b 3712 kfree(ha->swl);
5f16b331 3713 kfree(ha->loop_id_map);
1da177e4 3714
e8711085 3715 ha->srb_mempool = NULL;
a9083016 3716 ha->ctx_mempool = NULL;
1da177e4
LT		 3717 ha->sns_cmd = NULL;
3718 ha->sns_cmd_dma = 0;
3719 ha->ct_sns = NULL;
3720 ha->ct_sns_dma = 0;
3721 ha->ms_iocb = NULL;
3722 ha->ms_iocb_dma = 0;
1da177e4
LT		 3723 ha->init_cb = NULL;
3724 ha->init_cb_dma = 0;
b64b0e8f
AV		 3725 ha->ex_init_cb = NULL;
3726 ha->ex_init_cb_dma = 0;
5ff1d584
AV		 3727 ha->async_pd = NULL;
3728 ha->async_pd_dma = 0;
1da177e4
LT		 3729
3730 ha->s_dma_pool = NULL;
a9083016
GM		 3731 ha->dl_dma_pool = NULL;
3732 ha->fcp_cmnd_dma_pool = NULL;
1da177e4 3733
1da177e4
LT		 3734 ha->gid_list = NULL;
3735 ha->gid_list_dma = 0;
2d70c103
NB		 3736
3737 ha->tgt.atio_ring = NULL;
3738 ha->tgt.atio_dma = 0;
3739 ha->tgt.tgt_vp_map = NULL;
e315cd28 3740}
1da177e4 3741
e315cd28
AC		 3742struct scsi_qla_host *qla2x00_create_host(struct scsi_host_template *sht,
3743 struct qla_hw_data *ha)
3744{
3745 struct Scsi_Host *host;
3746 struct scsi_qla_host *vha = NULL;
854165f4 3747
e315cd28
AC		 3748 host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t));
3749 if (host == NULL) {
7c3df132
SK		 3750 ql_log_pci(ql_log_fatal, ha->pdev, 0x0107,
3751 "Failed to allocate host from the scsi layer, aborting.\n");
e315cd28
AC		 3752 goto fail;
3753 }
3754
3755 /* Clear our data area */
3756 vha = shost_priv(host);
3757 memset(vha, 0, sizeof(scsi_qla_host_t));
3758
3759 vha->host = host;
3760 vha->host_no = host->host_no;
3761 vha->hw = ha;
3762
3763 INIT_LIST_HEAD(&vha->vp_fcports);
3764 INIT_LIST_HEAD(&vha->work_list);
3765 INIT_LIST_HEAD(&vha->list);
3766
f999f4c1
AV		 3767 spin_lock_init(&vha->work_lock);
3768
e315cd28 3769 sprintf(vha->host_str, "%s_%ld", QLA2XXX_DRIVER_NAME, vha->host_no);
7c3df132
SK		 3770 ql_dbg(ql_dbg_init, vha, 0x0041,
3771 "Allocated the host=%p hw=%p vha=%p dev_name=%s",
3772 vha->host, vha->hw, vha,
3773 dev_name(&(ha->pdev->dev)));
3774
e315cd28
AC		 3775 return vha;
3776
3777fail:
3778 return vha;
1da177e4
LT		 3779}
3780
01ef66bb 3781static struct qla_work_evt *
f999f4c1 3782qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type)
0971de7f
AV		 3783{
3784 struct qla_work_evt *e;
feafb7b1
AE		 3785 uint8_t bail;
3786
3787 QLA_VHA_MARK_BUSY(vha, bail);
3788 if (bail)
3789 return NULL;
0971de7f 3790
f999f4c1 3791 e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC);
feafb7b1
AE		 3792 if (!e) {
3793 QLA_VHA_MARK_NOT_BUSY(vha);
0971de7f 3794 return NULL;
feafb7b1 3795 }
0971de7f
AV		 3796
3797 INIT_LIST_HEAD(&e->list);
3798 e->type = type;
3799 e->flags = QLA_EVT_FLAG_FREE;
3800 return e;
3801}
3802
01ef66bb 3803static int
f999f4c1 3804qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e)
0971de7f 3805{
f999f4c1 3806 unsigned long flags;
0971de7f 3807
f999f4c1 3808 spin_lock_irqsave(&vha->work_lock, flags);
e315cd28 3809 list_add_tail(&e->list, &vha->work_list);
f999f4c1 3810 spin_unlock_irqrestore(&vha->work_lock, flags);
e315cd28 3811 qla2xxx_wake_dpc(vha);
f999f4c1 3812
0971de7f
AV		 3813 return QLA_SUCCESS;
3814}
3815
3816int
e315cd28 3817qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code,
0971de7f
AV		 3818 u32 data)
3819{
3820 struct qla_work_evt *e;
3821
f999f4c1 3822 e = qla2x00_alloc_work(vha, QLA_EVT_AEN);
0971de7f
AV		 3823 if (!e)
3824 return QLA_FUNCTION_FAILED;
3825
3826 e->u.aen.code = code;
3827 e->u.aen.data = data;
f999f4c1 3828 return qla2x00_post_work(vha, e);
0971de7f
AV		 3829}
3830
8a659571
AV		 3831int
3832qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb)
3833{
3834 struct qla_work_evt *e;
3835
f999f4c1 3836 e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK);
8a659571
AV		 3837 if (!e)
3838 return QLA_FUNCTION_FAILED;
3839
3840 memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t));
f999f4c1 3841 return qla2x00_post_work(vha, e);
8a659571
AV		 3842}
3843
ac280b67
AV		 3844#define qla2x00_post_async_work(name, type) \
3845int qla2x00_post_async_##name##_work( \
3846 struct scsi_qla_host *vha, \
3847 fc_port_t *fcport, uint16_t *data) \
3848{ \
3849 struct qla_work_evt *e; \
3850 \
3851 e = qla2x00_alloc_work(vha, type); \
3852 if (!e) \
3853 return QLA_FUNCTION_FAILED; \
3854 \
3855 e->u.logio.fcport = fcport; \
3856 if (data) { \
3857 e->u.logio.data[0] = data[0]; \
3858 e->u.logio.data[1] = data[1]; \
3859 } \
3860 return qla2x00_post_work(vha, e); \
3861}
3862
3863qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN);
3864qla2x00_post_async_work(login_done, QLA_EVT_ASYNC_LOGIN_DONE);
3865qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT);
3866qla2x00_post_async_work(logout_done, QLA_EVT_ASYNC_LOGOUT_DONE);
5ff1d584
AV		 3867qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC);
3868qla2x00_post_async_work(adisc_done, QLA_EVT_ASYNC_ADISC_DONE);
ac280b67 3869
3420d36c
AV		 3870int
3871qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code)
3872{
3873 struct qla_work_evt *e;
3874
3875 e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT);
3876 if (!e)
3877 return QLA_FUNCTION_FAILED;
3878
3879 e->u.uevent.code = code;
3880 return qla2x00_post_work(vha, e);
3881}
3882
3883static void
3884qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code)
3885{
3886 char event_string[40];
3887 char *envp[] = { event_string, NULL };
3888
3889 switch (code) {
3890 case QLA_UEVENT_CODE_FW_DUMP:
3891 snprintf(event_string, sizeof(event_string), "FW_DUMP=%ld",
3892 vha->host_no);
3893 break;
3894 default:
3895 /* do nothing */
3896 break;
3897 }
3898 kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp);
3899}
3900
8ae6d9c7
GM		 3901int
3902qlafx00_post_aenfx_work(struct scsi_qla_host *vha, uint32_t evtcode,
3903 uint32_t *data, int cnt)
3904{
3905 struct qla_work_evt *e;
3906
3907 e = qla2x00_alloc_work(vha, QLA_EVT_AENFX);
3908 if (!e)
3909 return QLA_FUNCTION_FAILED;
3910
3911 e->u.aenfx.evtcode = evtcode;
3912 e->u.aenfx.count = cnt;
3913 memcpy(e->u.aenfx.mbx, data, sizeof(*data) * cnt);
3914 return qla2x00_post_work(vha, e);
3915}
3916
ac280b67 3917void
e315cd28 3918qla2x00_do_work(struct scsi_qla_host *vha)
0971de7f 3919{
f999f4c1
AV		 3920 struct qla_work_evt *e, *tmp;
3921 unsigned long flags;
3922 LIST_HEAD(work);
0971de7f 3923
f999f4c1
AV		 3924 spin_lock_irqsave(&vha->work_lock, flags);
3925 list_splice_init(&vha->work_list, &work);
3926 spin_unlock_irqrestore(&vha->work_lock, flags);
3927
3928 list_for_each_entry_safe(e, tmp, &work, list) {
0971de7f 3929 list_del_init(&e->list);
0971de7f
AV		 3930
3931 switch (e->type) {
3932 case QLA_EVT_AEN:
e315cd28 3933 fc_host_post_event(vha->host, fc_get_event_number(),
0971de7f
AV		 3934 e->u.aen.code, e->u.aen.data);
3935 break;
8a659571
AV		 3936 case QLA_EVT_IDC_ACK:
3937 qla81xx_idc_ack(vha, e->u.idc_ack.mb);
3938 break;
ac280b67
AV		 3939 case QLA_EVT_ASYNC_LOGIN:
3940 qla2x00_async_login(vha, e->u.logio.fcport,
3941 e->u.logio.data);
3942 break;
3943 case QLA_EVT_ASYNC_LOGIN_DONE:
3944 qla2x00_async_login_done(vha, e->u.logio.fcport,
3945 e->u.logio.data);
3946 break;
3947 case QLA_EVT_ASYNC_LOGOUT:
3948 qla2x00_async_logout(vha, e->u.logio.fcport);
3949 break;
3950 case QLA_EVT_ASYNC_LOGOUT_DONE:
3951 qla2x00_async_logout_done(vha, e->u.logio.fcport,
3952 e->u.logio.data);
3953 break;
5ff1d584
AV		 3954 case QLA_EVT_ASYNC_ADISC:
3955 qla2x00_async_adisc(vha, e->u.logio.fcport,
3956 e->u.logio.data);
3957 break;
3958 case QLA_EVT_ASYNC_ADISC_DONE:
3959 qla2x00_async_adisc_done(vha, e->u.logio.fcport,
3960 e->u.logio.data);
3961 break;
3420d36c
AV		 3962 case QLA_EVT_UEVENT:
3963 qla2x00_uevent_emit(vha, e->u.uevent.code);
3964 break;
8ae6d9c7
GM		 3965 case QLA_EVT_AENFX:
3966 qlafx00_process_aen(vha, e);
3967 break;
0971de7f
AV		 3968 }
3969 if (e->flags & QLA_EVT_FLAG_FREE)
3970 kfree(e);
feafb7b1
AE		 3971
3972 /* For each work completed decrement vha ref count */
3973 QLA_VHA_MARK_NOT_BUSY(vha);
e315cd28 3974 }
e315cd28 3975}
f999f4c1 3976
e315cd28
AC		 3977/* Relogins all the fcports of a vport
3978 * Context: dpc thread
3979 */
3980void qla2x00_relogin(struct scsi_qla_host *vha)
3981{
3982 fc_port_t *fcport;
c6b2fca8 3983 int status;
e315cd28
AC		 3984 uint16_t next_loopid = 0;
3985 struct qla_hw_data *ha = vha->hw;
ac280b67 3986 uint16_t data[2];
e315cd28
AC		 3987
3988 list_for_each_entry(fcport, &vha->vp_fcports, list) {
3989 /*
3990 * If the port is not ONLINE then try to login
3991 * to it if we haven't run out of retries.
3992 */
5ff1d584
AV		 3993 if (atomic_read(&fcport->state) != FCS_ONLINE &&
3994 fcport->login_retry && !(fcport->flags & FCF_ASYNC_SENT)) {
ac280b67 3995 fcport->login_retry--;
e315cd28 3996 if (fcport->flags & FCF_FABRIC_DEVICE) {
f08b7251 3997 if (fcport->flags & FCF_FCP2_DEVICE)
e315cd28
AC		 3998 ha->isp_ops->fabric_logout(vha,
3999 fcport->loop_id,
4000 fcport->d_id.b.domain,
4001 fcport->d_id.b.area,
4002 fcport->d_id.b.al_pa);
4003
03bcfb57
JC		 4004 if (fcport->loop_id == FC_NO_LOOP_ID) {
4005 fcport->loop_id = next_loopid =
4006 ha->min_external_loopid;
4007 status = qla2x00_find_new_loop_id(
4008 vha, fcport);
4009 if (status != QLA_SUCCESS) {
4010 /* Ran out of IDs to use */
4011 break;
4012 }
4013 }
4014
ac280b67 4015 if (IS_ALOGIO_CAPABLE(ha)) {
5ff1d584 4016 fcport->flags |= FCF_ASYNC_SENT;
ac280b67
AV		 4017 data[0] = 0;
4018 data[1] = QLA_LOGIO_LOGIN_RETRIED;
4019 status = qla2x00_post_async_login_work(
4020 vha, fcport, data);
4021 if (status == QLA_SUCCESS)
4022 continue;
4023 /* Attempt a retry. */
4024 status = 1;
aaf4d3e2 4025 } else {
ac280b67
AV		 4026 status = qla2x00_fabric_login(vha,
4027 fcport, &next_loopid);
aaf4d3e2
SK		 4028 if (status == QLA_SUCCESS) {
4029 int status2;
4030 uint8_t opts;
4031
4032 opts = 0;
4033 if (fcport->flags &
4034 FCF_FCP2_DEVICE)
4035 opts |= BIT_1;
03003960
SK		 4036 status2 =
4037 qla2x00_get_port_database(
4038 vha, fcport, opts);
aaf4d3e2
SK		 4039 if (status2 != QLA_SUCCESS)
4040 status = 1;
4041 }
4042 }
e315cd28
AC		 4043 } else
4044 status = qla2x00_local_device_login(vha,
4045 fcport);
4046
e315cd28
AC		 4047 if (status == QLA_SUCCESS) {
4048 fcport->old_loop_id = fcport->loop_id;
4049
7c3df132
SK		 4050 ql_dbg(ql_dbg_disc, vha, 0x2003,
4051 "Port login OK: logged in ID 0x%x.\n",
4052 fcport->loop_id);
e315cd28
AC		 4053
4054 qla2x00_update_fcport(vha, fcport);
4055
4056 } else if (status == 1) {
4057 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
4058 /* retry the login again */
7c3df132
SK		 4059 ql_dbg(ql_dbg_disc, vha, 0x2007,
4060 "Retrying %d login again loop_id 0x%x.\n",
4061 fcport->login_retry, fcport->loop_id);
e315cd28
AC		 4062 } else {
4063 fcport->login_retry = 0;
4064 }
4065
4066 if (fcport->login_retry == 0 && status != QLA_SUCCESS)
5f16b331 4067 qla2x00_clear_loop_id(fcport);
e315cd28
AC		 4068 }
4069 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
4070 break;
0971de7f 4071 }
0971de7f
AV		 4072}
4073
7d613ac6
SV		 4074/* Schedule work on any of the dpc-workqueues */
4075void
4076qla83xx_schedule_work(scsi_qla_host_t *base_vha, int work_code)
4077{
4078 struct qla_hw_data *ha = base_vha->hw;
4079
4080 switch (work_code) {
4081 case MBA_IDC_AEN: /* 0x8200 */
4082 if (ha->dpc_lp_wq)
4083 queue_work(ha->dpc_lp_wq, &ha->idc_aen);
4084 break;
4085
4086 case QLA83XX_NIC_CORE_RESET: /* 0x1 */
4087 if (!ha->flags.nic_core_reset_hdlr_active) {
4088 if (ha->dpc_hp_wq)
4089 queue_work(ha->dpc_hp_wq, &ha->nic_core_reset);
4090 } else
4091 ql_dbg(ql_dbg_p3p, base_vha, 0xb05e,
4092 "NIC Core reset is already active. Skip "
4093 "scheduling it again.\n");
4094 break;
4095 case QLA83XX_IDC_STATE_HANDLER: /* 0x2 */
4096 if (ha->dpc_hp_wq)
4097 queue_work(ha->dpc_hp_wq, &ha->idc_state_handler);
4098 break;
4099 case QLA83XX_NIC_CORE_UNRECOVERABLE: /* 0x3 */
4100 if (ha->dpc_hp_wq)
4101 queue_work(ha->dpc_hp_wq, &ha->nic_core_unrecoverable);
4102 break;
4103 default:
4104 ql_log(ql_log_warn, base_vha, 0xb05f,
d939be3a 4105 "Unknown work-code=0x%x.\n", work_code);
7d613ac6
SV		 4106 }
4107
4108 return;
4109}
4110
4111/* Work: Perform NIC Core Unrecoverable state handling */
4112void
4113qla83xx_nic_core_unrecoverable_work(struct work_struct *work)
4114{
4115 struct qla_hw_data *ha =
2ad1b67c 4116 container_of(work, struct qla_hw_data, nic_core_unrecoverable);
7d613ac6
SV		 4117 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4118 uint32_t dev_state = 0;
4119
4120 qla83xx_idc_lock(base_vha, 0);
4121 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4122 qla83xx_reset_ownership(base_vha);
4123 if (ha->flags.nic_core_reset_owner) {
4124 ha->flags.nic_core_reset_owner = 0;
4125 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
4126 QLA8XXX_DEV_FAILED);
4127 ql_log(ql_log_info, base_vha, 0xb060, "HW State: FAILED.\n");
4128 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
4129 }
4130 qla83xx_idc_unlock(base_vha, 0);
4131}
4132
4133/* Work: Execute IDC state handler */
4134void
4135qla83xx_idc_state_handler_work(struct work_struct *work)
4136{
4137 struct qla_hw_data *ha =
2ad1b67c 4138 container_of(work, struct qla_hw_data, idc_state_handler);
7d613ac6
SV		 4139 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4140 uint32_t dev_state = 0;
4141
4142 qla83xx_idc_lock(base_vha, 0);
4143 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4144 if (dev_state == QLA8XXX_DEV_FAILED ||
4145 dev_state == QLA8XXX_DEV_NEED_QUIESCENT)
4146 qla83xx_idc_state_handler(base_vha);
4147 qla83xx_idc_unlock(base_vha, 0);
4148}
4149
fa492630 4150static int
7d613ac6
SV		 4151qla83xx_check_nic_core_fw_alive(scsi_qla_host_t *base_vha)
4152{
4153 int rval = QLA_SUCCESS;
4154 unsigned long heart_beat_wait = jiffies + (1 * HZ);
4155 uint32_t heart_beat_counter1, heart_beat_counter2;
4156
4157 do {
4158 if (time_after(jiffies, heart_beat_wait)) {
4159 ql_dbg(ql_dbg_p3p, base_vha, 0xb07c,
4160 "Nic Core f/w is not alive.\n");
4161 rval = QLA_FUNCTION_FAILED;
4162 break;
4163 }
4164
4165 qla83xx_idc_lock(base_vha, 0);
4166 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
4167 &heart_beat_counter1);
4168 qla83xx_idc_unlock(base_vha, 0);
4169 msleep(100);
4170 qla83xx_idc_lock(base_vha, 0);
4171 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
4172 &heart_beat_counter2);
4173 qla83xx_idc_unlock(base_vha, 0);
4174 } while (heart_beat_counter1 == heart_beat_counter2);
4175
4176 return rval;
4177}
4178
4179/* Work: Perform NIC Core Reset handling */
4180void
4181qla83xx_nic_core_reset_work(struct work_struct *work)
4182{
4183 struct qla_hw_data *ha =
4184 container_of(work, struct qla_hw_data, nic_core_reset);
4185 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4186 uint32_t dev_state = 0;
4187
81178772
SK		 4188 if (IS_QLA2031(ha)) {
4189 if (qla2xxx_mctp_dump(base_vha) != QLA_SUCCESS)
4190 ql_log(ql_log_warn, base_vha, 0xb081,
4191 "Failed to dump mctp\n");
4192 return;
4193 }
4194
7d613ac6
SV		 4195 if (!ha->flags.nic_core_reset_hdlr_active) {
4196 if (qla83xx_check_nic_core_fw_alive(base_vha) == QLA_SUCCESS) {
4197 qla83xx_idc_lock(base_vha, 0);
4198 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE,
4199 &dev_state);
4200 qla83xx_idc_unlock(base_vha, 0);
4201 if (dev_state != QLA8XXX_DEV_NEED_RESET) {
4202 ql_dbg(ql_dbg_p3p, base_vha, 0xb07a,
4203 "Nic Core f/w is alive.\n");
4204 return;
4205 }
4206 }
4207
4208 ha->flags.nic_core_reset_hdlr_active = 1;
4209 if (qla83xx_nic_core_reset(base_vha)) {
4210 /* NIC Core reset failed. */
4211 ql_dbg(ql_dbg_p3p, base_vha, 0xb061,
4212 "NIC Core reset failed.\n");
4213 }
4214 ha->flags.nic_core_reset_hdlr_active = 0;
4215 }
4216}
4217
4218/* Work: Handle 8200 IDC aens */
4219void
4220qla83xx_service_idc_aen(struct work_struct *work)
4221{
4222 struct qla_hw_data *ha =
4223 container_of(work, struct qla_hw_data, idc_aen);
4224 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4225 uint32_t dev_state, idc_control;
4226
4227 qla83xx_idc_lock(base_vha, 0);
4228 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4229 qla83xx_rd_reg(base_vha, QLA83XX_IDC_CONTROL, &idc_control);
4230 qla83xx_idc_unlock(base_vha, 0);
4231 if (dev_state == QLA8XXX_DEV_NEED_RESET) {
4232 if (idc_control & QLA83XX_IDC_GRACEFUL_RESET) {
4233 ql_dbg(ql_dbg_p3p, base_vha, 0xb062,
4234 "Application requested NIC Core Reset.\n");
4235 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
4236 } else if (qla83xx_check_nic_core_fw_alive(base_vha) ==
4237 QLA_SUCCESS) {
4238 ql_dbg(ql_dbg_p3p, base_vha, 0xb07b,
4239 "Other protocol driver requested NIC Core Reset.\n");
4240 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
4241 }
4242 } else if (dev_state == QLA8XXX_DEV_FAILED ||
4243 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) {
4244 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
4245 }
4246}
4247
4248static void
4249qla83xx_wait_logic(void)
4250{
4251 int i;
4252
4253 /* Yield CPU */
4254 if (!in_interrupt()) {
4255 /*
4256 * Wait about 200ms before retrying again.
4257 * This controls the number of retries for single
4258 * lock operation.
4259 */
4260 msleep(100);
4261 schedule();
4262 } else {
4263 for (i = 0; i < 20; i++)
4264 cpu_relax(); /* This a nop instr on i386 */
4265 }
4266}
4267
fa492630 4268static int
7d613ac6
SV		 4269qla83xx_force_lock_recovery(scsi_qla_host_t *base_vha)
4270{
4271 int rval;
4272 uint32_t data;
4273 uint32_t idc_lck_rcvry_stage_mask = 0x3;
4274 uint32_t idc_lck_rcvry_owner_mask = 0x3c;
4275 struct qla_hw_data *ha = base_vha->hw;
6c315553
SK		 4276 ql_dbg(ql_dbg_p3p, base_vha, 0xb086,
4277 "Trying force recovery of the IDC lock.\n");
7d613ac6
SV		 4278
4279 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, &data);
4280 if (rval)
4281 return rval;
4282
4283 if ((data & idc_lck_rcvry_stage_mask) > 0) {
4284 return QLA_SUCCESS;
4285 } else {
4286 data = (IDC_LOCK_RECOVERY_STAGE1) | (ha->portnum << 2);
4287 rval = qla83xx_wr_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
4288 data);
4289 if (rval)
4290 return rval;
4291
4292 msleep(200);
4293
4294 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
4295 &data);
4296 if (rval)
4297 return rval;
4298
4299 if (((data & idc_lck_rcvry_owner_mask) >> 2) == ha->portnum) {
4300 data &= (IDC_LOCK_RECOVERY_STAGE2 |
4301 ~(idc_lck_rcvry_stage_mask));
4302 rval = qla83xx_wr_reg(base_vha,
4303 QLA83XX_IDC_LOCK_RECOVERY, data);
4304 if (rval)
4305 return rval;
4306
4307 /* Forcefully perform IDC UnLock */
4308 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK,
4309 &data);
4310 if (rval)
4311 return rval;
4312 /* Clear lock-id by setting 0xff */
4313 rval = qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
4314 0xff);
4315 if (rval)
4316 return rval;
4317 /* Clear lock-recovery by setting 0x0 */
4318 rval = qla83xx_wr_reg(base_vha,
4319 QLA83XX_IDC_LOCK_RECOVERY, 0x0);
4320 if (rval)
4321 return rval;
4322 } else
4323 return QLA_SUCCESS;
4324 }
4325
4326 return rval;
4327}
4328
fa492630 4329static int
7d613ac6
SV		 4330qla83xx_idc_lock_recovery(scsi_qla_host_t *base_vha)
4331{
4332 int rval = QLA_SUCCESS;
4333 uint32_t o_drv_lockid, n_drv_lockid;
4334 unsigned long lock_recovery_timeout;
4335
4336 lock_recovery_timeout = jiffies + QLA83XX_MAX_LOCK_RECOVERY_WAIT;
4337retry_lockid:
4338 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &o_drv_lockid);
4339 if (rval)
4340 goto exit;
4341
4342 /* MAX wait time before forcing IDC Lock recovery = 2 secs */
4343 if (time_after_eq(jiffies, lock_recovery_timeout)) {
4344 if (qla83xx_force_lock_recovery(base_vha) == QLA_SUCCESS)
4345 return QLA_SUCCESS;
4346 else
4347 return QLA_FUNCTION_FAILED;
4348 }
4349
4350 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &n_drv_lockid);
4351 if (rval)
4352 goto exit;
4353
4354 if (o_drv_lockid == n_drv_lockid) {
4355 qla83xx_wait_logic();
4356 goto retry_lockid;
4357 } else
4358 return QLA_SUCCESS;
4359
4360exit:
4361 return rval;
4362}
4363
4364void
4365qla83xx_idc_lock(scsi_qla_host_t *base_vha, uint16_t requester_id)
4366{
4367 uint16_t options = (requester_id << 15) | BIT_6;
4368 uint32_t data;
6c315553 4369 uint32_t lock_owner;
7d613ac6
SV		 4370 struct qla_hw_data *ha = base_vha->hw;
4371
4372 /* IDC-lock implementation using driver-lock/lock-id remote registers */
4373retry_lock:
4374 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCK, &data)
4375 == QLA_SUCCESS) {
4376 if (data) {
4377 /* Setting lock-id to our function-number */
4378 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
4379 ha->portnum);
4380 } else {
6c315553
SK		 4381 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID,
4382 &lock_owner);
7d613ac6 4383 ql_dbg(ql_dbg_p3p, base_vha, 0xb063,
6c315553
SK		 4384 "Failed to acquire IDC lock, acquired by %d, "
4385 "retrying...\n", lock_owner);
7d613ac6
SV		 4386
4387 /* Retry/Perform IDC-Lock recovery */
4388 if (qla83xx_idc_lock_recovery(base_vha)
4389 == QLA_SUCCESS) {
4390 qla83xx_wait_logic();
4391 goto retry_lock;
4392 } else
4393 ql_log(ql_log_warn, base_vha, 0xb075,
4394 "IDC Lock recovery FAILED.\n");
4395 }
4396
4397 }
4398
4399 return;
4400
4401 /* XXX: IDC-lock implementation using access-control mbx */
4402retry_lock2:
4403 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
4404 ql_dbg(ql_dbg_p3p, base_vha, 0xb072,
4405 "Failed to acquire IDC lock. retrying...\n");
4406 /* Retry/Perform IDC-Lock recovery */
4407 if (qla83xx_idc_lock_recovery(base_vha) == QLA_SUCCESS) {
4408 qla83xx_wait_logic();
4409 goto retry_lock2;
4410 } else
4411 ql_log(ql_log_warn, base_vha, 0xb076,
4412 "IDC Lock recovery FAILED.\n");
4413 }
4414
4415 return;
4416}
4417
4418void
4419qla83xx_idc_unlock(scsi_qla_host_t *base_vha, uint16_t requester_id)
4420{
5897cb2f
BVA		 4421#if 0
4422 uint16_t options = (requester_id << 15) | BIT_7;
4423#endif
4424 uint16_t retry;
7d613ac6
SV		 4425 uint32_t data;
4426 struct qla_hw_data *ha = base_vha->hw;
4427
4428 /* IDC-unlock implementation using driver-unlock/lock-id
4429 * remote registers
4430 */
4431 retry = 0;
4432retry_unlock:
4433 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &data)
4434 == QLA_SUCCESS) {
4435 if (data == ha->portnum) {
4436 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, &data);
4437 /* Clearing lock-id by setting 0xff */
4438 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 0xff);
4439 } else if (retry < 10) {
4440 /* SV: XXX: IDC unlock retrying needed here? */
4441
4442 /* Retry for IDC-unlock */
4443 qla83xx_wait_logic();
4444 retry++;
4445 ql_dbg(ql_dbg_p3p, base_vha, 0xb064,
4446 "Failed to release IDC lock, retyring=%d\n", retry);
4447 goto retry_unlock;
4448 }
4449 } else if (retry < 10) {
4450 /* Retry for IDC-unlock */
4451 qla83xx_wait_logic();
4452 retry++;
4453 ql_dbg(ql_dbg_p3p, base_vha, 0xb065,
4454 "Failed to read drv-lockid, retyring=%d\n", retry);
4455 goto retry_unlock;
4456 }
4457
4458 return;
4459
5897cb2f 4460#if 0
7d613ac6
SV		 4461 /* XXX: IDC-unlock implementation using access-control mbx */
4462 retry = 0;
4463retry_unlock2:
4464 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
4465 if (retry < 10) {
4466 /* Retry for IDC-unlock */
4467 qla83xx_wait_logic();
4468 retry++;
4469 ql_dbg(ql_dbg_p3p, base_vha, 0xb066,
4470 "Failed to release IDC lock, retyring=%d\n", retry);
4471 goto retry_unlock2;
4472 }
4473 }
4474
4475 return;
5897cb2f 4476#endif
7d613ac6
SV		 4477}
4478
4479int
4480__qla83xx_set_drv_presence(scsi_qla_host_t *vha)
4481{
4482 int rval = QLA_SUCCESS;
4483 struct qla_hw_data *ha = vha->hw;
4484 uint32_t drv_presence;
4485
4486 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
4487 if (rval == QLA_SUCCESS) {
4488 drv_presence |= (1 << ha->portnum);
4489 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
4490 drv_presence);
4491 }
4492
4493 return rval;
4494}
4495
4496int
4497qla83xx_set_drv_presence(scsi_qla_host_t *vha)
4498{
4499 int rval = QLA_SUCCESS;
4500
4501 qla83xx_idc_lock(vha, 0);
4502 rval = __qla83xx_set_drv_presence(vha);
4503 qla83xx_idc_unlock(vha, 0);
4504
4505 return rval;
4506}
4507
4508int
4509__qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
4510{
4511 int rval = QLA_SUCCESS;
4512 struct qla_hw_data *ha = vha->hw;
4513 uint32_t drv_presence;
4514
4515 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
4516 if (rval == QLA_SUCCESS) {
4517 drv_presence &= ~(1 << ha->portnum);
4518 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
4519 drv_presence);
4520 }
4521
4522 return rval;
4523}
4524
4525int
4526qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
4527{
4528 int rval = QLA_SUCCESS;
4529
4530 qla83xx_idc_lock(vha, 0);
4531 rval = __qla83xx_clear_drv_presence(vha);
4532 qla83xx_idc_unlock(vha, 0);
4533
4534 return rval;
4535}
4536
fa492630 4537static void
7d613ac6
SV		 4538qla83xx_need_reset_handler(scsi_qla_host_t *vha)
4539{
4540 struct qla_hw_data *ha = vha->hw;
4541 uint32_t drv_ack, drv_presence;
4542 unsigned long ack_timeout;
4543
4544 /* Wait for IDC ACK from all functions (DRV-ACK == DRV-PRESENCE) */
4545 ack_timeout = jiffies + (ha->fcoe_reset_timeout * HZ);
4546 while (1) {
4547 qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
4548 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
807fb6d8 4549 if ((drv_ack & drv_presence) == drv_presence)
7d613ac6
SV		 4550 break;
4551
4552 if (time_after_eq(jiffies, ack_timeout)) {
4553 ql_log(ql_log_warn, vha, 0xb067,
4554 "RESET ACK TIMEOUT! drv_presence=0x%x "
4555 "drv_ack=0x%x\n", drv_presence, drv_ack);
4556 /*
4557 * The function(s) which did not ack in time are forced
4558 * to withdraw any further participation in the IDC
4559 * reset.
4560 */
4561 if (drv_ack != drv_presence)
4562 qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
4563 drv_ack);
4564 break;
4565 }
4566
4567 qla83xx_idc_unlock(vha, 0);
4568 msleep(1000);
4569 qla83xx_idc_lock(vha, 0);
4570 }
4571
4572 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_COLD);
4573 ql_log(ql_log_info, vha, 0xb068, "HW State: COLD/RE-INIT.\n");
4574}
4575
fa492630 4576static int
7d613ac6
SV		 4577qla83xx_device_bootstrap(scsi_qla_host_t *vha)
4578{
4579 int rval = QLA_SUCCESS;
4580 uint32_t idc_control;
4581
4582 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_INITIALIZING);
4583 ql_log(ql_log_info, vha, 0xb069, "HW State: INITIALIZING.\n");
4584
4585 /* Clearing IDC-Control Graceful-Reset Bit before resetting f/w */
4586 __qla83xx_get_idc_control(vha, &idc_control);
4587 idc_control &= ~QLA83XX_IDC_GRACEFUL_RESET;
4588 __qla83xx_set_idc_control(vha, 0);
4589
4590 qla83xx_idc_unlock(vha, 0);
4591 rval = qla83xx_restart_nic_firmware(vha);
4592 qla83xx_idc_lock(vha, 0);
4593
4594 if (rval != QLA_SUCCESS) {
4595 ql_log(ql_log_fatal, vha, 0xb06a,
4596 "Failed to restart NIC f/w.\n");
4597 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_FAILED);
4598 ql_log(ql_log_info, vha, 0xb06b, "HW State: FAILED.\n");
4599 } else {
4600 ql_dbg(ql_dbg_p3p, vha, 0xb06c,
4601 "Success in restarting nic f/w.\n");
4602 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_READY);
4603 ql_log(ql_log_info, vha, 0xb06d, "HW State: READY.\n");
4604 }
4605
4606 return rval;
4607}
4608
4609/* Assumes idc_lock always held on entry */
4610int
4611qla83xx_idc_state_handler(scsi_qla_host_t *base_vha)
4612{
4613 struct qla_hw_data *ha = base_vha->hw;
4614 int rval = QLA_SUCCESS;
4615 unsigned long dev_init_timeout;
4616 uint32_t dev_state;
4617
4618 /* Wait for MAX-INIT-TIMEOUT for the device to go ready */
4619 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ);
4620
4621 while (1) {
4622
4623 if (time_after_eq(jiffies, dev_init_timeout)) {
4624 ql_log(ql_log_warn, base_vha, 0xb06e,
4625 "Initialization TIMEOUT!\n");
4626 /* Init timeout. Disable further NIC Core
4627 * communication.
4628 */
4629 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
4630 QLA8XXX_DEV_FAILED);
4631 ql_log(ql_log_info, base_vha, 0xb06f,
4632 "HW State: FAILED.\n");
4633 }
4634
4635 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4636 switch (dev_state) {
4637 case QLA8XXX_DEV_READY:
4638 if (ha->flags.nic_core_reset_owner)
4639 qla83xx_idc_audit(base_vha,
4640 IDC_AUDIT_COMPLETION);
4641 ha->flags.nic_core_reset_owner = 0;
4642 ql_dbg(ql_dbg_p3p, base_vha, 0xb070,
4643 "Reset_owner reset by 0x%x.\n",
4644 ha->portnum);
4645 goto exit;
4646 case QLA8XXX_DEV_COLD:
4647 if (ha->flags.nic_core_reset_owner)
4648 rval = qla83xx_device_bootstrap(base_vha);
4649 else {
4650 /* Wait for AEN to change device-state */
4651 qla83xx_idc_unlock(base_vha, 0);
4652 msleep(1000);
4653 qla83xx_idc_lock(base_vha, 0);
4654 }
4655 break;
4656 case QLA8XXX_DEV_INITIALIZING:
4657 /* Wait for AEN to change device-state */
4658 qla83xx_idc_unlock(base_vha, 0);
4659 msleep(1000);
4660 qla83xx_idc_lock(base_vha, 0);
4661 break;
4662 case QLA8XXX_DEV_NEED_RESET:
4663 if (!ql2xdontresethba && ha->flags.nic_core_reset_owner)
4664 qla83xx_need_reset_handler(base_vha);
4665 else {
4666 /* Wait for AEN to change device-state */
4667 qla83xx_idc_unlock(base_vha, 0);
4668 msleep(1000);
4669 qla83xx_idc_lock(base_vha, 0);
4670 }
4671 /* reset timeout value after need reset handler */
4672 dev_init_timeout = jiffies +
4673 (ha->fcoe_dev_init_timeout * HZ);
4674 break;
4675 case QLA8XXX_DEV_NEED_QUIESCENT:
4676 /* XXX: DEBUG for now */
4677 qla83xx_idc_unlock(base_vha, 0);
4678 msleep(1000);
4679 qla83xx_idc_lock(base_vha, 0);
4680 break;
4681 case QLA8XXX_DEV_QUIESCENT:
4682 /* XXX: DEBUG for now */
4683 if (ha->flags.quiesce_owner)
4684 goto exit;
4685
4686 qla83xx_idc_unlock(base_vha, 0);
4687 msleep(1000);
4688 qla83xx_idc_lock(base_vha, 0);
4689 dev_init_timeout = jiffies +
4690 (ha->fcoe_dev_init_timeout * HZ);
4691 break;
4692 case QLA8XXX_DEV_FAILED:
4693 if (ha->flags.nic_core_reset_owner)
4694 qla83xx_idc_audit(base_vha,
4695 IDC_AUDIT_COMPLETION);
4696 ha->flags.nic_core_reset_owner = 0;
4697 __qla83xx_clear_drv_presence(base_vha);
4698 qla83xx_idc_unlock(base_vha, 0);
4699 qla8xxx_dev_failed_handler(base_vha);
4700 rval = QLA_FUNCTION_FAILED;
4701 qla83xx_idc_lock(base_vha, 0);
4702 goto exit;
4703 case QLA8XXX_BAD_VALUE:
4704 qla83xx_idc_unlock(base_vha, 0);
4705 msleep(1000);
4706 qla83xx_idc_lock(base_vha, 0);
4707 break;
4708 default:
4709 ql_log(ql_log_warn, base_vha, 0xb071,
d939be3a 4710 "Unknown Device State: %x.\n", dev_state);
7d613ac6
SV		 4711 qla83xx_idc_unlock(base_vha, 0);
4712 qla8xxx_dev_failed_handler(base_vha);
4713 rval = QLA_FUNCTION_FAILED;
4714 qla83xx_idc_lock(base_vha, 0);
4715 goto exit;
4716 }
4717 }
4718
4719exit:
4720 return rval;
4721}
4722
f3ddac19
CD		 4723void
4724qla2x00_disable_board_on_pci_error(struct work_struct *work)
4725{
4726 struct qla_hw_data *ha = container_of(work, struct qla_hw_data,
4727 board_disable);
4728 struct pci_dev *pdev = ha->pdev;
4729 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4730
4731 ql_log(ql_log_warn, base_vha, 0x015b,
4732 "Disabling adapter.\n");
4733
4734 set_bit(UNLOADING, &base_vha->dpc_flags);
4735
4736 qla2x00_delete_all_vps(ha, base_vha);
4737
4738 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
4739
4740 qla2x00_dfs_remove(base_vha);
4741
4742 qla84xx_put_chip(base_vha);
4743
4744 if (base_vha->timer_active)
4745 qla2x00_stop_timer(base_vha);
4746
4747 base_vha->flags.online = 0;
4748
4749 qla2x00_destroy_deferred_work(ha);
4750
4751 /*
4752 * Do not try to stop beacon blink as it will issue a mailbox
4753 * command.
4754 */
4755 qla2x00_free_sysfs_attr(base_vha, false);
4756
4757 fc_remove_host(base_vha->host);
4758
4759 scsi_remove_host(base_vha->host);
4760
4761 base_vha->flags.init_done = 0;
4762 qla25xx_delete_queues(base_vha);
4763 qla2x00_free_irqs(base_vha);
4764 qla2x00_free_fcports(base_vha);
4765 qla2x00_mem_free(ha);
4766 qla82xx_md_free(base_vha);
4767 qla2x00_free_queues(ha);
4768
f3ddac19
CD		 4769 qla2x00_unmap_iobases(ha);
4770
4771 pci_release_selected_regions(ha->pdev, ha->bars);
f3ddac19
CD		 4772 pci_disable_pcie_error_reporting(pdev);
4773 pci_disable_device(pdev);
f3ddac19 4774
beb9e315
JL		 4775 /*
4776 * Let qla2x00_remove_one cleanup qla_hw_data on device removal.
4777 */
f3ddac19
CD		 4778}
4779
1da177e4
LT		 4780/**************************************************************************
4781* qla2x00_do_dpc
4782* This kernel thread is a task that is schedule by the interrupt handler
4783* to perform the background processing for interrupts.
4784*
4785* Notes:
4786* This task always run in the context of a kernel thread. It
4787* is kick-off by the driver's detect code and starts up
4788* up one per adapter. It immediately goes to sleep and waits for
4789* some fibre event. When either the interrupt handler or
4790* the timer routine detects a event it will one of the task
4791* bits then wake us up.
4792**************************************************************************/
4793static int
4794qla2x00_do_dpc(void *data)
4795{
2c3dfe3f 4796 int rval;
e315cd28
AC		 4797 scsi_qla_host_t *base_vha;
4798 struct qla_hw_data *ha;
1da177e4 4799
e315cd28
AC		 4800 ha = (struct qla_hw_data *)data;
4801 base_vha = pci_get_drvdata(ha->pdev);
1da177e4 4802
8698a745 4803 set_user_nice(current, MIN_NICE);
1da177e4 4804
563585ec 4805 set_current_state(TASK_INTERRUPTIBLE);
39a11240 4806 while (!kthread_should_stop()) {
7c3df132
SK		 4807 ql_dbg(ql_dbg_dpc, base_vha, 0x4000,
4808 "DPC handler sleeping.\n");
1da177e4 4809
39a11240 4810 schedule();
1da177e4 4811
c142caf0
AV		 4812 if (!base_vha->flags.init_done || ha->flags.mbox_busy)
4813 goto end_loop;
1da177e4 4814
85880801 4815 if (ha->flags.eeh_busy) {
7c3df132
SK		 4816 ql_dbg(ql_dbg_dpc, base_vha, 0x4003,
4817 "eeh_busy=%d.\n", ha->flags.eeh_busy);
c142caf0 4818 goto end_loop;
85880801
AV		 4819 }
4820
1da177e4
LT		 4821 ha->dpc_active = 1;
4822
5f28d2d7
SK		 4823 ql_dbg(ql_dbg_dpc + ql_dbg_verbose, base_vha, 0x4001,
4824 "DPC handler waking up, dpc_flags=0x%lx.\n",
4825 base_vha->dpc_flags);
1da177e4 4826
e315cd28 4827 qla2x00_do_work(base_vha);
0971de7f 4828
7ec0effd
AD		 4829 if (IS_P3P_TYPE(ha)) {
4830 if (IS_QLA8044(ha)) {
4831 if (test_and_clear_bit(ISP_UNRECOVERABLE,
4832 &base_vha->dpc_flags)) {
4833 qla8044_idc_lock(ha);
4834 qla8044_wr_direct(base_vha,
4835 QLA8044_CRB_DEV_STATE_INDEX,
4836 QLA8XXX_DEV_FAILED);
4837 qla8044_idc_unlock(ha);
4838 ql_log(ql_log_info, base_vha, 0x4004,
4839 "HW State: FAILED.\n");
4840 qla8044_device_state_handler(base_vha);
4841 continue;
4842 }
4843
4844 } else {
4845 if (test_and_clear_bit(ISP_UNRECOVERABLE,
4846 &base_vha->dpc_flags)) {
4847 qla82xx_idc_lock(ha);
4848 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
4849 QLA8XXX_DEV_FAILED);
4850 qla82xx_idc_unlock(ha);
4851 ql_log(ql_log_info, base_vha, 0x0151,
4852 "HW State: FAILED.\n");
4853 qla82xx_device_state_handler(base_vha);
4854 continue;
4855 }
a9083016
GM		 4856 }
4857
4858 if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED,
4859 &base_vha->dpc_flags)) {
4860
7c3df132
SK		 4861 ql_dbg(ql_dbg_dpc, base_vha, 0x4005,
4862 "FCoE context reset scheduled.\n");
a9083016
GM		 4863 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
4864 &base_vha->dpc_flags))) {
4865 if (qla82xx_fcoe_ctx_reset(base_vha)) {
4866 /* FCoE-ctx reset failed.
4867 * Escalate to chip-reset
4868 */
4869 set_bit(ISP_ABORT_NEEDED,
4870 &base_vha->dpc_flags);
4871 }
4872 clear_bit(ABORT_ISP_ACTIVE,
4873 &base_vha->dpc_flags);
4874 }
4875
7c3df132
SK		 4876 ql_dbg(ql_dbg_dpc, base_vha, 0x4006,
4877 "FCoE context reset end.\n");
a9083016 4878 }
8ae6d9c7
GM		 4879 } else if (IS_QLAFX00(ha)) {
4880 if (test_and_clear_bit(ISP_UNRECOVERABLE,
4881 &base_vha->dpc_flags)) {
4882 ql_dbg(ql_dbg_dpc, base_vha, 0x4020,
4883 "Firmware Reset Recovery\n");
4884 if (qlafx00_reset_initialize(base_vha)) {
4885 /* Failed. Abort isp later. */
4886 if (!test_bit(UNLOADING,
f92f82d6 4887 &base_vha->dpc_flags)) {
8ae6d9c7
GM		 4888 set_bit(ISP_UNRECOVERABLE,
4889 &base_vha->dpc_flags);
4890 ql_dbg(ql_dbg_dpc, base_vha,
4891 0x4021,
4892 "Reset Recovery Failed\n");
f92f82d6 4893 }
8ae6d9c7
GM		 4894 }
4895 }
4896
4897 if (test_and_clear_bit(FX00_TARGET_SCAN,
4898 &base_vha->dpc_flags)) {
4899 ql_dbg(ql_dbg_dpc, base_vha, 0x4022,
4900 "ISPFx00 Target Scan scheduled\n");
4901 if (qlafx00_rescan_isp(base_vha)) {
4902 if (!test_bit(UNLOADING,
4903 &base_vha->dpc_flags))
4904 set_bit(ISP_UNRECOVERABLE,
4905 &base_vha->dpc_flags);
4906 ql_dbg(ql_dbg_dpc, base_vha, 0x401e,
4907 "ISPFx00 Target Scan Failed\n");
4908 }
4909 ql_dbg(ql_dbg_dpc, base_vha, 0x401f,
4910 "ISPFx00 Target Scan End\n");
4911 }
e8f5e95d
AB		 4912 if (test_and_clear_bit(FX00_HOST_INFO_RESEND,
4913 &base_vha->dpc_flags)) {
4914 ql_dbg(ql_dbg_dpc, base_vha, 0x4023,
4915 "ISPFx00 Host Info resend scheduled\n");
4916 qlafx00_fx_disc(base_vha,
4917 &base_vha->hw->mr.fcport,
4918 FXDISC_REG_HOST_INFO);
4919 }
a9083016
GM		 4920 }
4921
e315cd28
AC		 4922 if (test_and_clear_bit(ISP_ABORT_NEEDED,
4923 &base_vha->dpc_flags)) {
1da177e4 4924
7c3df132
SK		 4925 ql_dbg(ql_dbg_dpc, base_vha, 0x4007,
4926 "ISP abort scheduled.\n");
1da177e4 4927 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
e315cd28 4928 &base_vha->dpc_flags))) {
1da177e4 4929
a9083016 4930 if (ha->isp_ops->abort_isp(base_vha)) {
1da177e4
LT		 4931 /* failed. retry later */
4932 set_bit(ISP_ABORT_NEEDED,
e315cd28 4933 &base_vha->dpc_flags);
99363ef8 4934 }
e315cd28
AC		 4935 clear_bit(ABORT_ISP_ACTIVE,
4936 &base_vha->dpc_flags);
99363ef8
SJ		 4937 }
4938
7c3df132
SK		 4939 ql_dbg(ql_dbg_dpc, base_vha, 0x4008,
4940 "ISP abort end.\n");
1da177e4
LT		 4941 }
4942
a394aac8
DJ		 4943 if (test_and_clear_bit(FCPORT_UPDATE_NEEDED,
4944 &base_vha->dpc_flags)) {
e315cd28 4945 qla2x00_update_fcports(base_vha);
c9c5ced9 4946 }
d97994dc 4947
2d70c103
NB		 4948 if (test_bit(SCR_PENDING, &base_vha->dpc_flags)) {
4949 int ret;
4950 ret = qla2x00_send_change_request(base_vha, 0x3, 0);
4951 if (ret != QLA_SUCCESS)
4952 ql_log(ql_log_warn, base_vha, 0x121,
4953 "Failed to enable receiving of RSCN "
4954 "requests: 0x%x.\n", ret);
4955 clear_bit(SCR_PENDING, &base_vha->dpc_flags);
4956 }
4957
8ae6d9c7
GM		 4958 if (IS_QLAFX00(ha))
4959 goto loop_resync_check;
4960
579d12b5 4961 if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) {
7c3df132
SK		 4962 ql_dbg(ql_dbg_dpc, base_vha, 0x4009,
4963 "Quiescence mode scheduled.\n");
7ec0effd
AD		 4964 if (IS_P3P_TYPE(ha)) {
4965 if (IS_QLA82XX(ha))
4966 qla82xx_device_state_handler(base_vha);
4967 if (IS_QLA8044(ha))
4968 qla8044_device_state_handler(base_vha);
8fcd6b8b
CD		 4969 clear_bit(ISP_QUIESCE_NEEDED,
4970 &base_vha->dpc_flags);
4971 if (!ha->flags.quiesce_owner) {
4972 qla2x00_perform_loop_resync(base_vha);
7ec0effd
AD		 4973 if (IS_QLA82XX(ha)) {
4974 qla82xx_idc_lock(ha);
4975 qla82xx_clear_qsnt_ready(
4976 base_vha);
4977 qla82xx_idc_unlock(ha);
4978 } else if (IS_QLA8044(ha)) {
4979 qla8044_idc_lock(ha);
4980 qla8044_clear_qsnt_ready(
4981 base_vha);
4982 qla8044_idc_unlock(ha);
4983 }
8fcd6b8b
CD		 4984 }
4985 } else {
4986 clear_bit(ISP_QUIESCE_NEEDED,
4987 &base_vha->dpc_flags);
4988 qla2x00_quiesce_io(base_vha);
579d12b5 4989 }
7c3df132
SK		 4990 ql_dbg(ql_dbg_dpc, base_vha, 0x400a,
4991 "Quiescence mode end.\n");
579d12b5
SK		 4992 }
4993
e315cd28 4994 if (test_and_clear_bit(RESET_MARKER_NEEDED,
8ae6d9c7 4995 &base_vha->dpc_flags) &&
e315cd28 4996 (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) {
1da177e4 4997
7c3df132
SK		 4998 ql_dbg(ql_dbg_dpc, base_vha, 0x400b,
4999 "Reset marker scheduled.\n");
e315cd28
AC		 5000 qla2x00_rst_aen(base_vha);
5001 clear_bit(RESET_ACTIVE, &base_vha->dpc_flags);
7c3df132
SK		 5002 ql_dbg(ql_dbg_dpc, base_vha, 0x400c,
5003 "Reset marker end.\n");
1da177e4
LT		 5004 }
5005
5006 /* Retry each device up to login retry count */
e315cd28
AC		 5007 if ((test_and_clear_bit(RELOGIN_NEEDED,
5008 &base_vha->dpc_flags)) &&
5009 !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) &&
5010 atomic_read(&base_vha->loop_state) != LOOP_DOWN) {
1da177e4 5011
7c3df132
SK		 5012 ql_dbg(ql_dbg_dpc, base_vha, 0x400d,
5013 "Relogin scheduled.\n");
e315cd28 5014 qla2x00_relogin(base_vha);
7c3df132
SK		 5015 ql_dbg(ql_dbg_dpc, base_vha, 0x400e,
5016 "Relogin end.\n");
1da177e4 5017 }
8ae6d9c7 5018loop_resync_check:
e315cd28 5019 if (test_and_clear_bit(LOOP_RESYNC_NEEDED,
8ae6d9c7 5020 &base_vha->dpc_flags)) {
1da177e4 5021
7c3df132
SK		 5022 ql_dbg(ql_dbg_dpc, base_vha, 0x400f,
5023 "Loop resync scheduled.\n");
1da177e4
LT		 5024
5025 if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE,
e315cd28 5026 &base_vha->dpc_flags))) {
1da177e4 5027
e315cd28 5028 rval = qla2x00_loop_resync(base_vha);
1da177e4 5029
e315cd28
AC		 5030 clear_bit(LOOP_RESYNC_ACTIVE,
5031 &base_vha->dpc_flags);
1da177e4
LT		 5032 }
5033
7c3df132
SK		 5034 ql_dbg(ql_dbg_dpc, base_vha, 0x4010,
5035 "Loop resync end.\n");
1da177e4
LT		 5036 }
5037
8ae6d9c7
GM		 5038 if (IS_QLAFX00(ha))
5039 goto intr_on_check;
5040
e315cd28
AC		 5041 if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) &&
5042 atomic_read(&base_vha->loop_state) == LOOP_READY) {
5043 clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags);
5044 qla2xxx_flash_npiv_conf(base_vha);
272976ca
AV		 5045 }
5046
8ae6d9c7 5047intr_on_check:
1da177e4 5048 if (!ha->interrupts_on)
fd34f556 5049 ha->isp_ops->enable_intrs(ha);
1da177e4 5050
e315cd28 5051 if (test_and_clear_bit(BEACON_BLINK_NEEDED,
90b604f2
HM		 5052 &base_vha->dpc_flags)) {
5053 if (ha->beacon_blink_led == 1)
5054 ha->isp_ops->beacon_blink(base_vha);
5055 }
f6df144c 5056
8ae6d9c7
GM		 5057 if (!IS_QLAFX00(ha))
5058 qla2x00_do_dpc_all_vps(base_vha);
2c3dfe3f 5059
1da177e4 5060 ha->dpc_active = 0;
c142caf0 5061end_loop:
563585ec 5062 set_current_state(TASK_INTERRUPTIBLE);
1da177e4 5063 } /* End of while(1) */
563585ec 5064 __set_current_state(TASK_RUNNING);
1da177e4 5065
7c3df132
SK		 5066 ql_dbg(ql_dbg_dpc, base_vha, 0x4011,
5067 "DPC handler exiting.\n");
1da177e4
LT		 5068
5069 /*
5070 * Make sure that nobody tries to wake us up again.
5071 */
1da177e4
LT		 5072 ha->dpc_active = 0;
5073
ac280b67
AV		 5074 /* Cleanup any residual CTX SRBs. */
5075 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
5076
39a11240
CH		 5077 return 0;
5078}
5079
5080void
e315cd28 5081qla2xxx_wake_dpc(struct scsi_qla_host *vha)
39a11240 5082{
e315cd28 5083 struct qla_hw_data *ha = vha->hw;
c795c1e4
AV		 5084 struct task_struct *t = ha->dpc_thread;
5085
e315cd28 5086 if (!test_bit(UNLOADING, &vha->dpc_flags) && t)
c795c1e4 5087 wake_up_process(t);
1da177e4
LT		 5088}
5089
1da177e4
LT		 5090/*
5091* qla2x00_rst_aen
5092* Processes asynchronous reset.
5093*
5094* Input:
5095* ha = adapter block pointer.
5096*/
5097static void
e315cd28 5098qla2x00_rst_aen(scsi_qla_host_t *vha)
1da177e4 5099{
e315cd28
AC		 5100 if (vha->flags.online && !vha->flags.reset_active &&
5101 !atomic_read(&vha->loop_down_timer) &&
5102 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) {
1da177e4 5103 do {
e315cd28 5104 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
1da177e4
LT		 5105
5106 /*
5107 * Issue marker command only when we are going to start
5108 * the I/O.
5109 */
e315cd28
AC		 5110 vha->marker_needed = 1;
5111 } while (!atomic_read(&vha->loop_down_timer) &&
5112 (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)));
1da177e4
LT		 5113 }
5114}
5115
1da177e4
LT		 5116/**************************************************************************
5117* qla2x00_timer
5118*
5119* Description:
5120* One second timer
5121*
5122* Context: Interrupt
5123***************************************************************************/
2c3dfe3f 5124void
e315cd28 5125qla2x00_timer(scsi_qla_host_t *vha)
1da177e4 5126{
1da177e4 5127 unsigned long cpu_flags = 0;
1da177e4
LT		 5128 int start_dpc = 0;
5129 int index;
5130 srb_t *sp;
85880801 5131 uint16_t w;
e315cd28 5132 struct qla_hw_data *ha = vha->hw;
73208dfd 5133 struct req_que *req;
85880801 5134
a5b36321 5135 if (ha->flags.eeh_busy) {
7c3df132
SK		 5136 ql_dbg(ql_dbg_timer, vha, 0x6000,
5137 "EEH = %d, restarting timer.\n",
5138 ha->flags.eeh_busy);
a5b36321
LC		 5139 qla2x00_restart_timer(vha, WATCH_INTERVAL);
5140 return;
5141 }
5142
f3ddac19
CD		 5143 /*
5144 * Hardware read to raise pending EEH errors during mailbox waits. If
5145 * the read returns -1 then disable the board.
5146 */
5147 if (!pci_channel_offline(ha->pdev)) {
85880801 5148 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w);
c821e0d5 5149 qla2x00_check_reg16_for_disconnect(vha, w);
f3ddac19 5150 }
1da177e4 5151
cefcaba6 5152 /* Make sure qla82xx_watchdog is run only for physical port */
7ec0effd 5153 if (!vha->vp_idx && IS_P3P_TYPE(ha)) {
579d12b5
SK		 5154 if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags))
5155 start_dpc++;
7ec0effd
AD		 5156 if (IS_QLA82XX(ha))
5157 qla82xx_watchdog(vha);
5158 else if (IS_QLA8044(ha))
5159 qla8044_watchdog(vha);
579d12b5
SK		 5160 }
5161
8ae6d9c7
GM		 5162 if (!vha->vp_idx && IS_QLAFX00(ha))
5163 qlafx00_timer_routine(vha);
5164
1da177e4 5165 /* Loop down handler. */
e315cd28 5166 if (atomic_read(&vha->loop_down_timer) > 0 &&
8f7daead
GM		 5167 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) &&
5168 !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags))
e315cd28 5169 && vha->flags.online) {
1da177e4 5170
e315cd28
AC		 5171 if (atomic_read(&vha->loop_down_timer) ==
5172 vha->loop_down_abort_time) {
1da177e4 5173
7c3df132
SK		 5174 ql_log(ql_log_info, vha, 0x6008,
5175 "Loop down - aborting the queues before time expires.\n");
1da177e4 5176
e315cd28
AC		 5177 if (!IS_QLA2100(ha) && vha->link_down_timeout)
5178 atomic_set(&vha->loop_state, LOOP_DEAD);
1da177e4 5179
f08b7251
AV		 5180 /*
5181 * Schedule an ISP abort to return any FCP2-device
5182 * commands.
5183 */
2c3dfe3f 5184 /* NPIV - scan physical port only */
e315cd28 5185 if (!vha->vp_idx) {
2c3dfe3f
SJ		 5186 spin_lock_irqsave(&ha->hardware_lock,
5187 cpu_flags);
73208dfd 5188 req = ha->req_q_map[0];
2c3dfe3f 5189 for (index = 1;
8d93f550 5190 index < req->num_outstanding_cmds;
2c3dfe3f
SJ		 5191 index++) {
5192 fc_port_t *sfcp;
5193
e315cd28 5194 sp = req->outstanding_cmds[index];
2c3dfe3f
SJ		 5195 if (!sp)
5196 continue;
9ba56b95 5197 if (sp->type != SRB_SCSI_CMD)
cf53b069 5198 continue;
2c3dfe3f 5199 sfcp = sp->fcport;
f08b7251 5200 if (!(sfcp->flags & FCF_FCP2_DEVICE))
2c3dfe3f 5201 continue;
bdf79621 5202
8f7daead
GM		 5203 if (IS_QLA82XX(ha))
5204 set_bit(FCOE_CTX_RESET_NEEDED,
5205 &vha->dpc_flags);
5206 else
5207 set_bit(ISP_ABORT_NEEDED,
e315cd28 5208 &vha->dpc_flags);
2c3dfe3f
SJ		 5209 break;
5210 }
5211 spin_unlock_irqrestore(&ha->hardware_lock,
e315cd28 5212 cpu_flags);
1da177e4 5213 }
1da177e4
LT		 5214 start_dpc++;
5215 }
5216
5217 /* if the loop has been down for 4 minutes, reinit adapter */
e315cd28 5218 if (atomic_dec_and_test(&vha->loop_down_timer) != 0) {
0d6e61bc 5219 if (!(vha->device_flags & DFLG_NO_CABLE)) {
7c3df132 5220 ql_log(ql_log_warn, vha, 0x6009,
1da177e4
LT		 5221 "Loop down - aborting ISP.\n");
5222
8f7daead
GM		 5223 if (IS_QLA82XX(ha))
5224 set_bit(FCOE_CTX_RESET_NEEDED,
5225 &vha->dpc_flags);
5226 else
5227 set_bit(ISP_ABORT_NEEDED,
5228 &vha->dpc_flags);
1da177e4
LT		 5229 }
5230 }
7c3df132
SK		 5231 ql_dbg(ql_dbg_timer, vha, 0x600a,
5232 "Loop down - seconds remaining %d.\n",
5233 atomic_read(&vha->loop_down_timer));
1da177e4 5234 }
cefcaba6
SK		 5235 /* Check if beacon LED needs to be blinked for physical host only */
5236 if (!vha->vp_idx && (ha->beacon_blink_led == 1)) {
999916dc 5237 /* There is no beacon_blink function for ISP82xx */
7ec0effd 5238 if (!IS_P3P_TYPE(ha)) {
999916dc
SK		 5239 set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags);
5240 start_dpc++;
5241 }
f6df144c 5242 }
5243
550bf57d 5244 /* Process any deferred work. */
e315cd28 5245 if (!list_empty(&vha->work_list))
550bf57d
AV		 5246 start_dpc++;
5247
1da177e4 5248 /* Schedule the DPC routine if needed */
e315cd28
AC		 5249 if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) ||
5250 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) ||
5251 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags) ||
1da177e4 5252 start_dpc ||
e315cd28
AC		 5253 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) ||
5254 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) ||
a9083016
GM		 5255 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) ||
5256 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) ||
e315cd28 5257 test_bit(VP_DPC_NEEDED, &vha->dpc_flags) ||
50280c01 5258 test_bit(RELOGIN_NEEDED, &vha->dpc_flags))) {
7c3df132
SK		 5259 ql_dbg(ql_dbg_timer, vha, 0x600b,
5260 "isp_abort_needed=%d loop_resync_needed=%d "
5261 "fcport_update_needed=%d start_dpc=%d "
5262 "reset_marker_needed=%d",
5263 test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags),
5264 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags),
5265 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags),
5266 start_dpc,
5267 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags));
5268 ql_dbg(ql_dbg_timer, vha, 0x600c,
5269 "beacon_blink_needed=%d isp_unrecoverable=%d "
5270 "fcoe_ctx_reset_needed=%d vp_dpc_needed=%d "
50280c01 5271 "relogin_needed=%d.\n",
7c3df132
SK		 5272 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags),
5273 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags),
5274 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags),
5275 test_bit(VP_DPC_NEEDED, &vha->dpc_flags),
50280c01 5276 test_bit(RELOGIN_NEEDED, &vha->dpc_flags));
e315cd28 5277 qla2xxx_wake_dpc(vha);
7c3df132 5278 }
1da177e4 5279
e315cd28 5280 qla2x00_restart_timer(vha, WATCH_INTERVAL);
1da177e4
LT		 5281}
5282
5433383e
AV		 5283/* Firmware interface routines. */
5284
f73cb695 5285#define FW_BLOBS 11
5433383e
AV		 5286#define FW_ISP21XX 0
5287#define FW_ISP22XX 1
5288#define FW_ISP2300 2
5289#define FW_ISP2322 3
48c02fde 5290#define FW_ISP24XX 4
c3a2f0df 5291#define FW_ISP25XX 5
3a03eb79 5292#define FW_ISP81XX 6
a9083016 5293#define FW_ISP82XX 7
6246b8a1
GM		 5294#define FW_ISP2031 8
5295#define FW_ISP8031 9
2c5bbbb2 5296#define FW_ISP27XX 10
5433383e 5297
bb8ee499
AV		 5298#define FW_FILE_ISP21XX "ql2100_fw.bin"
5299#define FW_FILE_ISP22XX "ql2200_fw.bin"
5300#define FW_FILE_ISP2300 "ql2300_fw.bin"
5301#define FW_FILE_ISP2322 "ql2322_fw.bin"
5302#define FW_FILE_ISP24XX "ql2400_fw.bin"
c3a2f0df 5303#define FW_FILE_ISP25XX "ql2500_fw.bin"
3a03eb79 5304#define FW_FILE_ISP81XX "ql8100_fw.bin"
a9083016 5305#define FW_FILE_ISP82XX "ql8200_fw.bin"
6246b8a1
GM		 5306#define FW_FILE_ISP2031 "ql2600_fw.bin"
5307#define FW_FILE_ISP8031 "ql8300_fw.bin"
2c5bbbb2 5308#define FW_FILE_ISP27XX "ql2700_fw.bin"
f73cb695 5309
bb8ee499 5310
e1e82b6f 5311static DEFINE_MUTEX(qla_fw_lock);
5433383e
AV		 5312
5313static struct fw_blob qla_fw_blobs[FW_BLOBS] = {
bb8ee499
AV		 5314 { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, },
5315 { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, },
5316 { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, },
5317 { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, },
5318 { .name = FW_FILE_ISP24XX, },
c3a2f0df 5319 { .name = FW_FILE_ISP25XX, },
3a03eb79 5320 { .name = FW_FILE_ISP81XX, },
a9083016 5321 { .name = FW_FILE_ISP82XX, },
6246b8a1
GM		 5322 { .name = FW_FILE_ISP2031, },
5323 { .name = FW_FILE_ISP8031, },
2c5bbbb2 5324 { .name = FW_FILE_ISP27XX, },
5433383e
AV		 5325};
5326
5327struct fw_blob *
e315cd28 5328qla2x00_request_firmware(scsi_qla_host_t *vha)
5433383e 5329{
e315cd28 5330 struct qla_hw_data *ha = vha->hw;
5433383e
AV		 5331 struct fw_blob *blob;
5332
5433383e
AV		 5333 if (IS_QLA2100(ha)) {
5334 blob = &qla_fw_blobs[FW_ISP21XX];
5335 } else if (IS_QLA2200(ha)) {
5336 blob = &qla_fw_blobs[FW_ISP22XX];
48c02fde 5337 } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
5433383e 5338 blob = &qla_fw_blobs[FW_ISP2300];
48c02fde 5339 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
5433383e 5340 blob = &qla_fw_blobs[FW_ISP2322];
4d4df193 5341 } else if (IS_QLA24XX_TYPE(ha)) {
5433383e 5342 blob = &qla_fw_blobs[FW_ISP24XX];
c3a2f0df
AV		 5343 } else if (IS_QLA25XX(ha)) {
5344 blob = &qla_fw_blobs[FW_ISP25XX];
3a03eb79
AV		 5345 } else if (IS_QLA81XX(ha)) {
5346 blob = &qla_fw_blobs[FW_ISP81XX];
a9083016
GM		 5347 } else if (IS_QLA82XX(ha)) {
5348 blob = &qla_fw_blobs[FW_ISP82XX];
6246b8a1
GM		 5349 } else if (IS_QLA2031(ha)) {
5350 blob = &qla_fw_blobs[FW_ISP2031];
5351 } else if (IS_QLA8031(ha)) {
5352 blob = &qla_fw_blobs[FW_ISP8031];
2c5bbbb2
JC		 5353 } else if (IS_QLA27XX(ha)) {
5354 blob = &qla_fw_blobs[FW_ISP27XX];
8a655229
DC		 5355 } else {
5356 return NULL;
5433383e
AV		 5357 }
5358
e1e82b6f 5359 mutex_lock(&qla_fw_lock);
5433383e
AV		 5360 if (blob->fw)
5361 goto out;
5362
5363 if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) {
7c3df132
SK		 5364 ql_log(ql_log_warn, vha, 0x0063,
5365 "Failed to load firmware image (%s).\n", blob->name);
5433383e
AV		 5366 blob->fw = NULL;
5367 blob = NULL;
5368 goto out;
5369 }
5370
5371out:
e1e82b6f 5372 mutex_unlock(&qla_fw_lock);
5433383e
AV		 5373 return blob;
5374}
5375
5376static void
5377qla2x00_release_firmware(void)
5378{
5379 int idx;
5380
e1e82b6f 5381 mutex_lock(&qla_fw_lock);
5433383e 5382 for (idx = 0; idx < FW_BLOBS; idx++)
cf92549f 5383 release_firmware(qla_fw_blobs[idx].fw);
e1e82b6f 5384 mutex_unlock(&qla_fw_lock);
5433383e
AV		 5385}
5386
14e660e6
SJ		 5387static pci_ers_result_t
5388qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
5389{
85880801
AV		 5390 scsi_qla_host_t *vha = pci_get_drvdata(pdev);
5391 struct qla_hw_data *ha = vha->hw;
5392
7c3df132
SK		 5393 ql_dbg(ql_dbg_aer, vha, 0x9000,
5394 "PCI error detected, state %x.\n", state);
b9b12f73 5395
14e660e6
SJ		 5396 switch (state) {
5397 case pci_channel_io_normal:
85880801 5398 ha->flags.eeh_busy = 0;
14e660e6
SJ		 5399 return PCI_ERS_RESULT_CAN_RECOVER;
5400 case pci_channel_io_frozen:
85880801 5401 ha->flags.eeh_busy = 1;
a5b36321
LC		 5402 /* For ISP82XX complete any pending mailbox cmd */
5403 if (IS_QLA82XX(ha)) {
7190575f 5404 ha->flags.isp82xx_fw_hung = 1;
c8f6544e
CD		 5405 ql_dbg(ql_dbg_aer, vha, 0x9001, "Pci channel io frozen\n");
5406 qla82xx_clear_pending_mbx(vha);
a5b36321 5407 }
90a86fc0 5408 qla2x00_free_irqs(vha);
14e660e6 5409 pci_disable_device(pdev);
bddd2d65
LC		 5410 /* Return back all IOs */
5411 qla2x00_abort_all_cmds(vha, DID_RESET << 16);
14e660e6
SJ		 5412 return PCI_ERS_RESULT_NEED_RESET;
5413 case pci_channel_io_perm_failure:
85880801
AV		 5414 ha->flags.pci_channel_io_perm_failure = 1;
5415 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
14e660e6
SJ		 5416 return PCI_ERS_RESULT_DISCONNECT;
5417 }
5418 return PCI_ERS_RESULT_NEED_RESET;
5419}
5420
5421static pci_ers_result_t
5422qla2xxx_pci_mmio_enabled(struct pci_dev *pdev)
5423{
5424 int risc_paused = 0;
5425 uint32_t stat;
5426 unsigned long flags;
e315cd28
AC		 5427 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
5428 struct qla_hw_data *ha = base_vha->hw;
14e660e6
SJ		 5429 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
5430 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
5431
bcc5b6d3
SK		 5432 if (IS_QLA82XX(ha))
5433 return PCI_ERS_RESULT_RECOVERED;
5434
14e660e6
SJ		 5435 spin_lock_irqsave(&ha->hardware_lock, flags);
5436 if (IS_QLA2100(ha) || IS_QLA2200(ha)){
5437 stat = RD_REG_DWORD(&reg->hccr);
5438 if (stat & HCCR_RISC_PAUSE)
5439 risc_paused = 1;
5440 } else if (IS_QLA23XX(ha)) {
5441 stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
5442 if (stat & HSR_RISC_PAUSED)
5443 risc_paused = 1;
5444 } else if (IS_FWI2_CAPABLE(ha)) {
5445 stat = RD_REG_DWORD(&reg24->host_status);
5446 if (stat & HSRX_RISC_PAUSED)
5447 risc_paused = 1;
5448 }
5449 spin_unlock_irqrestore(&ha->hardware_lock, flags);
5450
5451 if (risc_paused) {
7c3df132
SK		 5452 ql_log(ql_log_info, base_vha, 0x9003,
5453 "RISC paused -- mmio_enabled, Dumping firmware.\n");
e315cd28 5454 ha->isp_ops->fw_dump(base_vha, 0);
14e660e6
SJ		 5455
5456 return PCI_ERS_RESULT_NEED_RESET;
5457 } else
5458 return PCI_ERS_RESULT_RECOVERED;
5459}
5460
fa492630
SK		 5461static uint32_t
5462qla82xx_error_recovery(scsi_qla_host_t *base_vha)
a5b36321
LC		 5463{
5464 uint32_t rval = QLA_FUNCTION_FAILED;
5465 uint32_t drv_active = 0;
5466 struct qla_hw_data *ha = base_vha->hw;
5467 int fn;
5468 struct pci_dev *other_pdev = NULL;
5469
7c3df132
SK		 5470 ql_dbg(ql_dbg_aer, base_vha, 0x9006,
5471 "Entered %s.\n", __func__);
a5b36321
LC		 5472
5473 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
5474
5475 if (base_vha->flags.online) {
5476 /* Abort all outstanding commands,
5477 * so as to be requeued later */
5478 qla2x00_abort_isp_cleanup(base_vha);
5479 }
5480
5481
5482 fn = PCI_FUNC(ha->pdev->devfn);
5483 while (fn > 0) {
5484 fn--;
7c3df132
SK		 5485 ql_dbg(ql_dbg_aer, base_vha, 0x9007,
5486 "Finding pci device at function = 0x%x.\n", fn);
a5b36321
LC		 5487 other_pdev =
5488 pci_get_domain_bus_and_slot(pci_domain_nr(ha->pdev->bus),
5489 ha->pdev->bus->number, PCI_DEVFN(PCI_SLOT(ha->pdev->devfn),
5490 fn));
5491
5492 if (!other_pdev)
5493 continue;
5494 if (atomic_read(&other_pdev->enable_cnt)) {
7c3df132
SK		 5495 ql_dbg(ql_dbg_aer, base_vha, 0x9008,
5496 "Found PCI func available and enable at 0x%x.\n",
5497 fn);
a5b36321
LC		 5498 pci_dev_put(other_pdev);
5499 break;
5500 }
5501 pci_dev_put(other_pdev);
5502 }
5503
5504 if (!fn) {
5505 /* Reset owner */
7c3df132
SK		 5506 ql_dbg(ql_dbg_aer, base_vha, 0x9009,
5507 "This devfn is reset owner = 0x%x.\n",
5508 ha->pdev->devfn);
a5b36321
LC		 5509 qla82xx_idc_lock(ha);
5510
5511 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 5512 QLA8XXX_DEV_INITIALIZING);
a5b36321
LC		 5513
5514 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION,
5515 QLA82XX_IDC_VERSION);
5516
5517 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
7c3df132
SK		 5518 ql_dbg(ql_dbg_aer, base_vha, 0x900a,
5519 "drv_active = 0x%x.\n", drv_active);
a5b36321
LC		 5520
5521 qla82xx_idc_unlock(ha);
5522 /* Reset if device is not already reset
5523 * drv_active would be 0 if a reset has already been done
5524 */
5525 if (drv_active)
5526 rval = qla82xx_start_firmware(base_vha);
5527 else
5528 rval = QLA_SUCCESS;
5529 qla82xx_idc_lock(ha);
5530
5531 if (rval != QLA_SUCCESS) {
7c3df132
SK		 5532 ql_log(ql_log_info, base_vha, 0x900b,
5533 "HW State: FAILED.\n");
a5b36321
LC		 5534 qla82xx_clear_drv_active(ha);
5535 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 5536 QLA8XXX_DEV_FAILED);
a5b36321 5537 } else {
7c3df132
SK		 5538 ql_log(ql_log_info, base_vha, 0x900c,
5539 "HW State: READY.\n");
a5b36321 5540 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 5541 QLA8XXX_DEV_READY);
a5b36321 5542 qla82xx_idc_unlock(ha);
7190575f 5543 ha->flags.isp82xx_fw_hung = 0;
a5b36321
LC		 5544 rval = qla82xx_restart_isp(base_vha);
5545 qla82xx_idc_lock(ha);
5546 /* Clear driver state register */
5547 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, 0);
5548 qla82xx_set_drv_active(base_vha);
5549 }
5550 qla82xx_idc_unlock(ha);
5551 } else {
7c3df132
SK		 5552 ql_dbg(ql_dbg_aer, base_vha, 0x900d,
5553 "This devfn is not reset owner = 0x%x.\n",
5554 ha->pdev->devfn);
a5b36321 5555 if ((qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE) ==
7d613ac6 5556 QLA8XXX_DEV_READY)) {
7190575f 5557 ha->flags.isp82xx_fw_hung = 0;
a5b36321
LC		 5558 rval = qla82xx_restart_isp(base_vha);
5559 qla82xx_idc_lock(ha);
5560 qla82xx_set_drv_active(base_vha);
5561 qla82xx_idc_unlock(ha);
5562 }
5563 }
5564 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
5565
5566 return rval;
5567}
5568
14e660e6
SJ		 5569static pci_ers_result_t
5570qla2xxx_pci_slot_reset(struct pci_dev *pdev)
5571{
5572 pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT;
e315cd28
AC		 5573 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
5574 struct qla_hw_data *ha = base_vha->hw;
90a86fc0
JC		 5575 struct rsp_que *rsp;
5576 int rc, retries = 10;
09483916 5577
7c3df132
SK		 5578 ql_dbg(ql_dbg_aer, base_vha, 0x9004,
5579 "Slot Reset.\n");
85880801 5580
90a86fc0
JC		 5581 /* Workaround: qla2xxx driver which access hardware earlier
5582 * needs error state to be pci_channel_io_online.
5583 * Otherwise mailbox command timesout.
5584 */
5585 pdev->error_state = pci_channel_io_normal;
5586
5587 pci_restore_state(pdev);
5588
8c1496bd
RL		 5589 /* pci_restore_state() clears the saved_state flag of the device
5590 * save restored state which resets saved_state flag
5591 */
5592 pci_save_state(pdev);
5593
09483916
BH		 5594 if (ha->mem_only)
5595 rc = pci_enable_device_mem(pdev);
5596 else
5597 rc = pci_enable_device(pdev);
14e660e6 5598
09483916 5599 if (rc) {
7c3df132 5600 ql_log(ql_log_warn, base_vha, 0x9005,
14e660e6 5601 "Can't re-enable PCI device after reset.\n");
a5b36321 5602 goto exit_slot_reset;
14e660e6 5603 }
14e660e6 5604
90a86fc0
JC		 5605 rsp = ha->rsp_q_map[0];
5606 if (qla2x00_request_irqs(ha, rsp))
a5b36321 5607 goto exit_slot_reset;
90a86fc0 5608
e315cd28 5609 if (ha->isp_ops->pci_config(base_vha))
a5b36321
LC		 5610 goto exit_slot_reset;
5611
5612 if (IS_QLA82XX(ha)) {
5613 if (qla82xx_error_recovery(base_vha) == QLA_SUCCESS) {
5614 ret = PCI_ERS_RESULT_RECOVERED;
5615 goto exit_slot_reset;
5616 } else
5617 goto exit_slot_reset;
5618 }
14e660e6 5619
90a86fc0
JC		 5620 while (ha->flags.mbox_busy && retries--)
5621 msleep(1000);
85880801 5622
e315cd28 5623 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
a9083016 5624 if (ha->isp_ops->abort_isp(base_vha) == QLA_SUCCESS)
14e660e6 5625 ret = PCI_ERS_RESULT_RECOVERED;
e315cd28 5626 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
14e660e6 5627
90a86fc0 5628
a5b36321 5629exit_slot_reset:
7c3df132
SK		 5630 ql_dbg(ql_dbg_aer, base_vha, 0x900e,
5631 "slot_reset return %x.\n", ret);
85880801 5632
14e660e6
SJ		 5633 return ret;
5634}
5635
5636static void
5637qla2xxx_pci_resume(struct pci_dev *pdev)
5638{
e315cd28
AC		 5639 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
5640 struct qla_hw_data *ha = base_vha->hw;
14e660e6
SJ		 5641 int ret;
5642
7c3df132
SK		 5643 ql_dbg(ql_dbg_aer, base_vha, 0x900f,
5644 "pci_resume.\n");
85880801 5645
e315cd28 5646 ret = qla2x00_wait_for_hba_online(base_vha);
14e660e6 5647 if (ret != QLA_SUCCESS) {
7c3df132
SK		 5648 ql_log(ql_log_fatal, base_vha, 0x9002,
5649 "The device failed to resume I/O from slot/link_reset.\n");
14e660e6 5650 }
85880801 5651
3e46f031
LC		 5652 pci_cleanup_aer_uncorrect_error_status(pdev);
5653
85880801 5654 ha->flags.eeh_busy = 0;
14e660e6
SJ		 5655}
5656
2d5a4c34
HM		 5657static void
5658qla83xx_disable_laser(scsi_qla_host_t *vha)
5659{
5660 uint32_t reg, data, fn;
5661 struct qla_hw_data *ha = vha->hw;
5662 struct device_reg_24xx __iomem *isp_reg = &ha->iobase->isp24;
5663
5664 /* pci func #/port # */
5665 ql_dbg(ql_dbg_init, vha, 0x004b,
5666 "Disabling Laser for hba: %p\n", vha);
5667
5668 fn = (RD_REG_DWORD(&isp_reg->ctrl_status) &
5669 (BIT_15|BIT_14|BIT_13|BIT_12));
5670
5671 fn = (fn >> 12);
5672
5673 if (fn & 1)
5674 reg = PORT_1_2031;
5675 else
5676 reg = PORT_0_2031;
5677
5678 data = LASER_OFF_2031;
5679
5680 qla83xx_wr_reg(vha, reg, data);
5681}
5682
a55b2d21 5683static const struct pci_error_handlers qla2xxx_err_handler = {
14e660e6
SJ		 5684 .error_detected = qla2xxx_pci_error_detected,
5685 .mmio_enabled = qla2xxx_pci_mmio_enabled,
5686 .slot_reset = qla2xxx_pci_slot_reset,
5687 .resume = qla2xxx_pci_resume,
5688};
5689
5433383e 5690static struct pci_device_id qla2xxx_pci_tbl[] = {
47f5e069
AV		 5691 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) },
5692 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) },
5693 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) },
5694 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) },
5695 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) },
5696 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) },
5697 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) },
5698 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) },
5699 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) },
4d4df193 5700 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) },
47f5e069
AV		 5701 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) },
5702 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) },
c3a2f0df 5703 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) },
6246b8a1 5704 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2031) },
3a03eb79 5705 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) },
a9083016 5706 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) },
650f528f 5707 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8031) },
8ae6d9c7 5708 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISPF001) },
7ec0effd 5709 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8044) },
f73cb695 5710 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2071) },
2c5bbbb2 5711 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2271) },
5433383e
AV		 5712 { 0 },
5713};
5714MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl);
5715
fca29703 5716static struct pci_driver qla2xxx_pci_driver = {
cb63067a 5717 .name = QLA2XXX_DRIVER_NAME,
0a21ef1e
JB		 5718 .driver = {
5719 .owner = THIS_MODULE,
5720 },
fca29703 5721 .id_table = qla2xxx_pci_tbl,
7ee61397 5722 .probe = qla2x00_probe_one,
4c993f76 5723 .remove = qla2x00_remove_one,
e30d1756 5724 .shutdown = qla2x00_shutdown,
14e660e6 5725 .err_handler = &qla2xxx_err_handler,
fca29703
AV		 5726};
5727
75ef9de1 5728static const struct file_operations apidev_fops = {
6a03b4cd 5729 .owner = THIS_MODULE,
6038f373 5730 .llseek = noop_llseek,
6a03b4cd
HZ		 5731};
5732
1da177e4
LT		 5733/**
5734 * qla2x00_module_init - Module initialization.
5735 **/
5736static int __init
5737qla2x00_module_init(void)
5738{
fca29703
AV		 5739 int ret = 0;
5740
1da177e4 5741 /* Allocate cache for SRBs. */
354d6b21 5742 srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0,
20c2df83 5743 SLAB_HWCACHE_ALIGN, NULL);
1da177e4 5744 if (srb_cachep == NULL) {
7c3df132
SK		 5745 ql_log(ql_log_fatal, NULL, 0x0001,
5746 "Unable to allocate SRB cache...Failing load!.\n");
1da177e4
LT		 5747 return -ENOMEM;
5748 }
5749
2d70c103
NB		 5750 /* Initialize target kmem_cache and mem_pools */
5751 ret = qlt_init();
5752 if (ret < 0) {
5753 kmem_cache_destroy(srb_cachep);
5754 return ret;
5755 } else if (ret > 0) {
5756 /*
5757 * If initiator mode is explictly disabled by qlt_init(),
5758 * prevent scsi_transport_fc.c:fc_scsi_scan_rport() from
5759 * performing scsi_scan_target() during LOOP UP event.
5760 */
5761 qla2xxx_transport_functions.disable_target_scan = 1;
5762 qla2xxx_transport_vport_functions.disable_target_scan = 1;
5763 }
5764
1da177e4
LT		 5765 /* Derive version string. */
5766 strcpy(qla2x00_version_str, QLA2XXX_VERSION);
11010fec 5767 if (ql2xextended_error_logging)
0181944f
AV		 5768 strcat(qla2x00_version_str, "-debug");
5769
1c97a12a
AV		 5770 qla2xxx_transport_template =
5771 fc_attach_transport(&qla2xxx_transport_functions);
2c3dfe3f
SJ		 5772 if (!qla2xxx_transport_template) {
5773 kmem_cache_destroy(srb_cachep);
7c3df132
SK		 5774 ql_log(ql_log_fatal, NULL, 0x0002,
5775 "fc_attach_transport failed...Failing load!.\n");
2d70c103 5776 qlt_exit();
1da177e4 5777 return -ENODEV;
2c3dfe3f 5778 }
6a03b4cd
HZ		 5779
5780 apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops);
5781 if (apidev_major < 0) {
7c3df132
SK		 5782 ql_log(ql_log_fatal, NULL, 0x0003,
5783 "Unable to register char device %s.\n", QLA2XXX_APIDEV);
6a03b4cd
HZ		 5784 }
5785
2c3dfe3f
SJ		 5786 qla2xxx_transport_vport_template =
5787 fc_attach_transport(&qla2xxx_transport_vport_functions);
5788 if (!qla2xxx_transport_vport_template) {
5789 kmem_cache_destroy(srb_cachep);
2d70c103 5790 qlt_exit();
2c3dfe3f 5791 fc_release_transport(qla2xxx_transport_template);
7c3df132
SK		 5792 ql_log(ql_log_fatal, NULL, 0x0004,
5793 "fc_attach_transport vport failed...Failing load!.\n");
1da177e4 5794 return -ENODEV;
2c3dfe3f 5795 }
7c3df132
SK		 5796 ql_log(ql_log_info, NULL, 0x0005,
5797 "QLogic Fibre Channel HBA Driver: %s.\n",
fd9a29f0 5798 qla2x00_version_str);
7ee61397 5799 ret = pci_register_driver(&qla2xxx_pci_driver);
fca29703
AV		 5800 if (ret) {
5801 kmem_cache_destroy(srb_cachep);
2d70c103 5802 qlt_exit();
fca29703 5803 fc_release_transport(qla2xxx_transport_template);
2c3dfe3f 5804 fc_release_transport(qla2xxx_transport_vport_template);
7c3df132
SK		 5805 ql_log(ql_log_fatal, NULL, 0x0006,
5806 "pci_register_driver failed...ret=%d Failing load!.\n",
5807 ret);
fca29703
AV		 5808 }
5809 return ret;
1da177e4
LT		 5810}
5811
5812/**
5813 * qla2x00_module_exit - Module cleanup.
5814 **/
5815static void __exit
5816qla2x00_module_exit(void)
5817{
6a03b4cd 5818 unregister_chrdev(apidev_major, QLA2XXX_APIDEV);
7ee61397 5819 pci_unregister_driver(&qla2xxx_pci_driver);
5433383e 5820 qla2x00_release_firmware();
354d6b21 5821 kmem_cache_destroy(srb_cachep);
2d70c103 5822 qlt_exit();
a9083016
GM		 5823 if (ctx_cachep)
5824 kmem_cache_destroy(ctx_cachep);
1da177e4 5825 fc_release_transport(qla2xxx_transport_template);
2c3dfe3f 5826 fc_release_transport(qla2xxx_transport_vport_template);
1da177e4
LT		 5827}
5828
5829module_init(qla2x00_module_init);
5830module_exit(qla2x00_module_exit);
5831
5832MODULE_AUTHOR("QLogic Corporation");
5833MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver");
5834MODULE_LICENSE("GPL");
5835MODULE_VERSION(QLA2XXX_VERSION);
bb8ee499
AV		 5836MODULE_FIRMWARE(FW_FILE_ISP21XX);
5837MODULE_FIRMWARE(FW_FILE_ISP22XX);
5838MODULE_FIRMWARE(FW_FILE_ISP2300);
5839MODULE_FIRMWARE(FW_FILE_ISP2322);
5840MODULE_FIRMWARE(FW_FILE_ISP24XX);
61623fc3 5841MODULE_FIRMWARE(FW_FILE_ISP25XX);
f1458cda
SC		 5842MODULE_FIRMWARE(FW_FILE_ISP2031);
5843MODULE_FIRMWARE(FW_FILE_ISP8031);
5844MODULE_FIRMWARE(FW_FILE_ISP27XX);
Linux 6.x block layer and io_uring tree(s)