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scsi: qla2xxx: Report the firmware status code if a mailbox command fails
[linux-2.6-block.git] / drivers / scsi / qla2xxx / qla_os.c
CommitLineData
1da177e4 1/*
fa90c54f 2 * QLogic Fibre Channel HBA Driver
bd21eaf9 3 * Copyright (c) 2003-2014 QLogic Corporation
1da177e4 4 *
fa90c54f 5 * See LICENSE.qla2xxx for copyright and licensing details.
1da177e4
LT		 6 */
7#include "qla_def.h"
8
9#include <linux/moduleparam.h>
10#include <linux/vmalloc.h>
1da177e4 11#include <linux/delay.h>
39a11240 12#include <linux/kthread.h>
e1e82b6f 13#include <linux/mutex.h>
3420d36c 14#include <linux/kobject.h>
5a0e3ad6 15#include <linux/slab.h>
5601236b 16#include <linux/blk-mq-pci.h>
585def9b
QT		 17#include <linux/refcount.h>
18
1da177e4
LT		 19#include <scsi/scsi_tcq.h>
20#include <scsi/scsicam.h>
21#include <scsi/scsi_transport.h>
22#include <scsi/scsi_transport_fc.h>
23
2d70c103
NB		 24#include "qla_target.h"
25
1da177e4
LT		 26/*
27 * Driver version
28 */
29char qla2x00_version_str[40];
30
6a03b4cd
HZ		 31static int apidev_major;
32
1da177e4
LT		 33/*
34 * SRB allocation cache
35 */
d7459527 36struct kmem_cache *srb_cachep;
1da177e4 37
a9083016
GM		 38/*
39 * CT6 CTX allocation cache
40 */
41static struct kmem_cache *ctx_cachep;
3ce8866c
SK		 42/*
43 * error level for logging
44 */
3f006ac3 45uint ql_errlev = 0x8001;
a9083016 46
fa492630 47static int ql2xenableclass2;
2d70c103
NB		 48module_param(ql2xenableclass2, int, S_IRUGO|S_IRUSR);
49MODULE_PARM_DESC(ql2xenableclass2,
50 "Specify if Class 2 operations are supported from the very "
51 "beginning. Default is 0 - class 2 not supported.");
52
8ae6d9c7 53
1da177e4 54int ql2xlogintimeout = 20;
f2019cb1 55module_param(ql2xlogintimeout, int, S_IRUGO);
1da177e4
LT		 56MODULE_PARM_DESC(ql2xlogintimeout,
57 "Login timeout value in seconds.");
58
a7b61842 59int qlport_down_retry;
f2019cb1 60module_param(qlport_down_retry, int, S_IRUGO);
1da177e4 61MODULE_PARM_DESC(qlport_down_retry,
900d9f98 62 "Maximum number of command retries to a port that returns "
1da177e4
LT		 63 "a PORT-DOWN status.");
64
1da177e4
LT		 65int ql2xplogiabsentdevice;
66module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR);
67MODULE_PARM_DESC(ql2xplogiabsentdevice,
68 "Option to enable PLOGI to devices that are not present after "
900d9f98 69 "a Fabric scan. This is needed for several broken switches. "
0d52e642 70 "Default is 0 - no PLOGI. 1 - perform PLOGI.");
1da177e4 71
c1c7178c 72int ql2xloginretrycount;
f2019cb1 73module_param(ql2xloginretrycount, int, S_IRUGO);
1da177e4
LT		 74MODULE_PARM_DESC(ql2xloginretrycount,
75 "Specify an alternate value for the NVRAM login retry count.");
76
a7a167bf 77int ql2xallocfwdump = 1;
f2019cb1 78module_param(ql2xallocfwdump, int, S_IRUGO);
a7a167bf
AV		 79MODULE_PARM_DESC(ql2xallocfwdump,
80 "Option to enable allocation of memory for a firmware dump "
81 "during HBA initialization. Memory allocation requirements "
82 "vary by ISP type. Default is 1 - allocate memory.");
83
11010fec 84int ql2xextended_error_logging;
27d94035 85module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
a2b3e01d 86module_param_named(logging, ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
11010fec 87MODULE_PARM_DESC(ql2xextended_error_logging,
3ce8866c
SK		 88 "Option to enable extended error logging,\n"
89 "\t\tDefault is 0 - no logging. 0x40000000 - Module Init & Probe.\n"
90 "\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n"
91 "\t\t0x08000000 - IO tracing. 0x04000000 - DPC Thread.\n"
92 "\t\t0x02000000 - Async events. 0x01000000 - Timer routines.\n"
93 "\t\t0x00800000 - User space. 0x00400000 - Task Management.\n"
94 "\t\t0x00200000 - AER/EEH. 0x00100000 - Multi Q.\n"
95 "\t\t0x00080000 - P3P Specific. 0x00040000 - Virtual Port.\n"
96 "\t\t0x00020000 - Buffer Dump. 0x00010000 - Misc.\n"
29f9f90c
CD		 97 "\t\t0x00008000 - Verbose. 0x00004000 - Target.\n"
98 "\t\t0x00002000 - Target Mgmt. 0x00001000 - Target TMF.\n"
3ce8866c 99 "\t\t0x7fffffff - For enabling all logs, can be too many logs.\n"
cfb0919c
CD		 100 "\t\t0x1e400000 - Preferred value for capturing essential "
101 "debug information (equivalent to old "
102 "ql2xextended_error_logging=1).\n"
3ce8866c 103 "\t\tDo LOGICAL OR of the value to enable more than one level");
0181944f 104
a9083016 105int ql2xshiftctondsd = 6;
f2019cb1 106module_param(ql2xshiftctondsd, int, S_IRUGO);
a9083016
GM		 107MODULE_PARM_DESC(ql2xshiftctondsd,
108 "Set to control shifting of command type processing "
109 "based on total number of SG elements.");
110
58e2753c 111int ql2xfdmienable = 1;
de187df8 112module_param(ql2xfdmienable, int, S_IRUGO|S_IWUSR);
a2b3e01d 113module_param_named(fdmi, ql2xfdmienable, int, S_IRUGO|S_IWUSR);
cca5335c 114MODULE_PARM_DESC(ql2xfdmienable,
7794a5af
FW		 115 "Enables FDMI registrations. "
116 "0 - no FDMI. Default is 1 - perform FDMI.");
cca5335c 117
d213a4b7 118#define MAX_Q_DEPTH 64
50280c01 119static int ql2xmaxqdepth = MAX_Q_DEPTH;
df7baa50
AV		 120module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR);
121MODULE_PARM_DESC(ql2xmaxqdepth,
e92e4a8f 122 "Maximum queue depth to set for each LUN. "
d213a4b7 123 "Default is 64.");
df7baa50 124
e84067d7
DG		 125#if (IS_ENABLED(CONFIG_NVME_FC))
126int ql2xenabledif;
127#else
9e522cd8 128int ql2xenabledif = 2;
e84067d7 129#endif
9e522cd8 130module_param(ql2xenabledif, int, S_IRUGO);
bad75002 131MODULE_PARM_DESC(ql2xenabledif,
b97f5d0b
SM		 132 " Enable T10-CRC-DIF:\n"
133 " Default is 2.\n"
134 " 0 -- No DIF Support\n"
135 " 1 -- Enable DIF for all types\n"
136 " 2 -- Enable DIF for all types, except Type 0.\n");
bad75002 137
e84067d7
DG		 138#if (IS_ENABLED(CONFIG_NVME_FC))
139int ql2xnvmeenable = 1;
140#else
141int ql2xnvmeenable;
142#endif
143module_param(ql2xnvmeenable, int, 0644);
144MODULE_PARM_DESC(ql2xnvmeenable,
145 "Enables NVME support. "
146 "0 - no NVMe. Default is Y");
147
8cb2049c 148int ql2xenablehba_err_chk = 2;
bad75002
AE		 149module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR);
150MODULE_PARM_DESC(ql2xenablehba_err_chk,
8cb2049c 151 " Enable T10-CRC-DIF Error isolation by HBA:\n"
b97f5d0b 152 " Default is 2.\n"
8cb2049c
AE		 153 " 0 -- Error isolation disabled\n"
154 " 1 -- Error isolation enabled only for DIX Type 0\n"
155 " 2 -- Error isolation enabled for all Types\n");
bad75002 156
58e2753c 157int ql2xiidmaenable = 1;
f2019cb1 158module_param(ql2xiidmaenable, int, S_IRUGO);
e5896bd5
AV		 159MODULE_PARM_DESC(ql2xiidmaenable,
160 "Enables iIDMA settings "
161 "Default is 1 - perform iIDMA. 0 - no iIDMA.");
162
d7459527
MH		 163int ql2xmqsupport = 1;
164module_param(ql2xmqsupport, int, S_IRUGO);
165MODULE_PARM_DESC(ql2xmqsupport,
166 "Enable on demand multiple queue pairs support "
167 "Default is 1 for supported. "
168 "Set it to 0 to turn off mq qpair support.");
e337d907
AV		 169
170int ql2xfwloadbin;
86e45bf6 171module_param(ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
a2b3e01d 172module_param_named(fwload, ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
e337d907 173MODULE_PARM_DESC(ql2xfwloadbin,
7c3df132
SK		 174 "Option to specify location from which to load ISP firmware:.\n"
175 " 2 -- load firmware via the request_firmware() (hotplug).\n"
e337d907
AV		 176 " interface.\n"
177 " 1 -- load firmware from flash.\n"
178 " 0 -- use default semantics.\n");
179
ae97c91e 180int ql2xetsenable;
f2019cb1 181module_param(ql2xetsenable, int, S_IRUGO);
ae97c91e
AV		 182MODULE_PARM_DESC(ql2xetsenable,
183 "Enables firmware ETS burst."
184 "Default is 0 - skip ETS enablement.");
185
6907869d 186int ql2xdbwr = 1;
86e45bf6 187module_param(ql2xdbwr, int, S_IRUGO|S_IWUSR);
a9083016 188MODULE_PARM_DESC(ql2xdbwr,
08de2844
GM		 189 "Option to specify scheme for request queue posting.\n"
190 " 0 -- Regular doorbell.\n"
191 " 1 -- CAMRAM doorbell (faster).\n");
a9083016 192
f4c496c1 193int ql2xtargetreset = 1;
f2019cb1 194module_param(ql2xtargetreset, int, S_IRUGO);
f4c496c1
GM		 195MODULE_PARM_DESC(ql2xtargetreset,
196 "Enable target reset."
197 "Default is 1 - use hw defaults.");
198
4da26e16 199int ql2xgffidenable;
f2019cb1 200module_param(ql2xgffidenable, int, S_IRUGO);
4da26e16
CD		 201MODULE_PARM_DESC(ql2xgffidenable,
202 "Enables GFF_ID checks of port type. "
203 "Default is 0 - Do not use GFF_ID information.");
a9083016 204
043dc1d7 205int ql2xasynctmfenable = 1;
f2019cb1 206module_param(ql2xasynctmfenable, int, S_IRUGO);
3822263e
MI		 207MODULE_PARM_DESC(ql2xasynctmfenable,
208 "Enables issue of TM IOCBs asynchronously via IOCB mechanism"
84e13c45 209 "Default is 1 - Issue TM IOCBs via mailbox mechanism.");
ed0de87c
GM		 210
211int ql2xdontresethba;
86e45bf6 212module_param(ql2xdontresethba, int, S_IRUGO|S_IWUSR);
ed0de87c 213MODULE_PARM_DESC(ql2xdontresethba,
08de2844
GM		 214 "Option to specify reset behaviour.\n"
215 " 0 (Default) -- Reset on failure.\n"
216 " 1 -- Do not reset on failure.\n");
ed0de87c 217
1abf635d
HR		 218uint64_t ql2xmaxlun = MAX_LUNS;
219module_param(ql2xmaxlun, ullong, S_IRUGO);
82515920
AV		 220MODULE_PARM_DESC(ql2xmaxlun,
221 "Defines the maximum LU number to register with the SCSI "
222 "midlayer. Default is 65535.");
223
08de2844
GM		 224int ql2xmdcapmask = 0x1F;
225module_param(ql2xmdcapmask, int, S_IRUGO);
226MODULE_PARM_DESC(ql2xmdcapmask,
227 "Set the Minidump driver capture mask level. "
6e96fa7b 228 "Default is 0x1F - Can be set to 0x3, 0x7, 0xF, 0x1F, 0x7F.");
08de2844 229
3aadff35 230int ql2xmdenable = 1;
08de2844
GM		 231module_param(ql2xmdenable, int, S_IRUGO);
232MODULE_PARM_DESC(ql2xmdenable,
233 "Enable/disable MiniDump. "
3aadff35
GM		 234 "0 - MiniDump disabled. "
235 "1 (Default) - MiniDump enabled.");
08de2844 236
c1c7178c 237int ql2xexlogins;
b0d6cabd
HM		 238module_param(ql2xexlogins, uint, S_IRUGO|S_IWUSR);
239MODULE_PARM_DESC(ql2xexlogins,
240 "Number of extended Logins. "
241 "0 (Default)- Disabled.");
242
99e1b683
QT		 243int ql2xexchoffld = 1024;
244module_param(ql2xexchoffld, uint, 0644);
2f56a7f1 245MODULE_PARM_DESC(ql2xexchoffld,
99e1b683
QT		 246 "Number of target exchanges.");
247
248int ql2xiniexchg = 1024;
249module_param(ql2xiniexchg, uint, 0644);
250MODULE_PARM_DESC(ql2xiniexchg,
251 "Number of initiator exchanges.");
2f56a7f1 252
c1c7178c 253int ql2xfwholdabts;
f198cafa
HM		 254module_param(ql2xfwholdabts, int, S_IRUGO);
255MODULE_PARM_DESC(ql2xfwholdabts,
256 "Allow FW to hold status IOCB until ABTS rsp received. "
257 "0 (Default) Do not set fw option. "
258 "1 - Set fw option to hold ABTS.");
259
41dc529a
QT		 260int ql2xmvasynctoatio = 1;
261module_param(ql2xmvasynctoatio, int, S_IRUGO|S_IWUSR);
262MODULE_PARM_DESC(ql2xmvasynctoatio,
263 "Move PUREX, ABTS RX and RIDA IOCBs to ATIOQ"
264 "0 (Default). Do not move IOCBs"
265 "1 - Move IOCBs.");
266
e4e3a2ce
QT		 267int ql2xautodetectsfp = 1;
268module_param(ql2xautodetectsfp, int, 0444);
269MODULE_PARM_DESC(ql2xautodetectsfp,
270 "Detect SFP range and set appropriate distance.\n"
271 "1 (Default): Enable\n");
272
e7240af5
HM		 273int ql2xenablemsix = 1;
274module_param(ql2xenablemsix, int, 0444);
275MODULE_PARM_DESC(ql2xenablemsix,
276 "Set to enable MSI or MSI-X interrupt mechanism.\n"
277 " Default is 1, enable MSI-X interrupt mechanism.\n"
278 " 0 -- enable traditional pin-based mechanism.\n"
279 " 1 -- enable MSI-X interrupt mechanism.\n"
280 " 2 -- enable MSI interrupt mechanism.\n");
281
9ecf0b0d
QT		 282int qla2xuseresexchforels;
283module_param(qla2xuseresexchforels, int, 0444);
284MODULE_PARM_DESC(qla2xuseresexchforels,
285 "Reserve 1/2 of emergency exchanges for ELS.\n"
286 " 0 (default): disabled");
287
b3ede8ea 288static int ql2xprotmask;
7855d2ba
MP		 289module_param(ql2xprotmask, int, 0644);
290MODULE_PARM_DESC(ql2xprotmask,
291 "Override DIF/DIX protection capabilities mask\n"
292 "Default is 0 which sets protection mask based on "
293 "capabilities reported by HBA firmware.\n");
294
b3ede8ea 295static int ql2xprotguard;
7855d2ba
MP		 296module_param(ql2xprotguard, int, 0644);
297MODULE_PARM_DESC(ql2xprotguard, "Override choice of DIX checksum\n"
298 " 0 -- Let HBA firmware decide\n"
299 " 1 -- Force T10 CRC\n"
300 " 2 -- Force IP checksum\n");
301
50b81275
GM		 302int ql2xdifbundlinginternalbuffers;
303module_param(ql2xdifbundlinginternalbuffers, int, 0644);
304MODULE_PARM_DESC(ql2xdifbundlinginternalbuffers,
305 "Force using internal buffers for DIF information\n"
306 "0 (Default). Based on check.\n"
307 "1 Force using internal buffers\n");
308
1a2fbf18 309static void qla2x00_clear_drv_active(struct qla_hw_data *);
3491255e 310static void qla2x00_free_device(scsi_qla_host_t *);
5601236b 311static int qla2xxx_map_queues(struct Scsi_Host *shost);
e84067d7 312static void qla2x00_destroy_deferred_work(struct qla_hw_data *);
ce7e4af7 313
45235022 314
1da177e4 315static struct scsi_transport_template *qla2xxx_transport_template = NULL;
2c3dfe3f 316struct scsi_transport_template *qla2xxx_transport_vport_template = NULL;
1da177e4 317
1da177e4
LT		 318/* TODO Convert to inlines
319 *
320 * Timer routines
321 */
1da177e4 322
2c3dfe3f 323__inline__ void
8e5f4ba0 324qla2x00_start_timer(scsi_qla_host_t *vha, unsigned long interval)
1da177e4 325{
8e5f4ba0 326 timer_setup(&vha->timer, qla2x00_timer, 0);
e315cd28 327 vha->timer.expires = jiffies + interval * HZ;
e315cd28
AC		 328 add_timer(&vha->timer);
329 vha->timer_active = 1;
1da177e4
LT		 330}
331
332static inline void
e315cd28 333qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval)
1da177e4 334{
a9083016 335 /* Currently used for 82XX only. */
7c3df132
SK		 336 if (vha->device_flags & DFLG_DEV_FAILED) {
337 ql_dbg(ql_dbg_timer, vha, 0x600d,
338 "Device in a failed state, returning.\n");
a9083016 339 return;
7c3df132 340 }
a9083016 341
e315cd28 342 mod_timer(&vha->timer, jiffies + interval * HZ);
1da177e4
LT		 343}
344
a824ebb3 345static __inline__ void
e315cd28 346qla2x00_stop_timer(scsi_qla_host_t *vha)
1da177e4 347{
e315cd28
AC		 348 del_timer_sync(&vha->timer);
349 vha->timer_active = 0;
1da177e4
LT		 350}
351
1da177e4
LT		 352static int qla2x00_do_dpc(void *data);
353
354static void qla2x00_rst_aen(scsi_qla_host_t *);
355
73208dfd
AC		 356static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t,
357 struct req_que **, struct rsp_que **);
e30d1756 358static void qla2x00_free_fw_dump(struct qla_hw_data *);
e315cd28 359static void qla2x00_mem_free(struct qla_hw_data *);
d7459527
MH		 360int qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd,
361 struct qla_qpair *qpair);
1da177e4 362
1da177e4 363/* -------------------------------------------------------------------------- */
8abfa9e2
QT		 364static void qla_init_base_qpair(struct scsi_qla_host *vha, struct req_que *req,
365 struct rsp_que *rsp)
366{
367 struct qla_hw_data *ha = vha->hw;
bd432bb5 368
8abfa9e2
QT		 369 rsp->qpair = ha->base_qpair;
370 rsp->req = req;
0691094f 371 ha->base_qpair->hw = ha;
8abfa9e2
QT		 372 ha->base_qpair->req = req;
373 ha->base_qpair->rsp = rsp;
374 ha->base_qpair->vha = vha;
375 ha->base_qpair->qp_lock_ptr = &ha->hardware_lock;
376 ha->base_qpair->use_shadow_reg = IS_SHADOW_REG_CAPABLE(ha) ? 1 : 0;
377 ha->base_qpair->msix = &ha->msix_entries[QLA_MSIX_RSP_Q];
6a629468 378 ha->base_qpair->srb_mempool = ha->srb_mempool;
8abfa9e2
QT		 379 INIT_LIST_HEAD(&ha->base_qpair->hints_list);
380 ha->base_qpair->enable_class_2 = ql2xenableclass2;
381 /* init qpair to this cpu. Will adjust at run time. */
86531887 382 qla_cpu_update(rsp->qpair, raw_smp_processor_id());
8abfa9e2
QT		 383 ha->base_qpair->pdev = ha->pdev;
384
ecc89f25 385 if (IS_QLA27XX(ha) || IS_QLA83XX(ha) || IS_QLA28XX(ha))
8abfa9e2
QT		 386 ha->base_qpair->reqq_start_iocbs = qla_83xx_start_iocbs;
387}
388
9a347ff4
CD		 389static int qla2x00_alloc_queues(struct qla_hw_data *ha, struct req_que *req,
390 struct rsp_que *rsp)
73208dfd 391{
7c3df132 392 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
bd432bb5 393
6396bb22 394 ha->req_q_map = kcalloc(ha->max_req_queues, sizeof(struct req_que *),
73208dfd
AC		 395 GFP_KERNEL);
396 if (!ha->req_q_map) {
7c3df132
SK		 397 ql_log(ql_log_fatal, vha, 0x003b,
398 "Unable to allocate memory for request queue ptrs.\n");
73208dfd
AC		 399 goto fail_req_map;
400 }
401
6396bb22 402 ha->rsp_q_map = kcalloc(ha->max_rsp_queues, sizeof(struct rsp_que *),
73208dfd
AC		 403 GFP_KERNEL);
404 if (!ha->rsp_q_map) {
7c3df132
SK		 405 ql_log(ql_log_fatal, vha, 0x003c,
406 "Unable to allocate memory for response queue ptrs.\n");
73208dfd
AC		 407 goto fail_rsp_map;
408 }
d7459527 409
e326d22a
QT		 410 ha->base_qpair = kzalloc(sizeof(struct qla_qpair), GFP_KERNEL);
411 if (ha->base_qpair == NULL) {
412 ql_log(ql_log_warn, vha, 0x00e0,
413 "Failed to allocate base queue pair memory.\n");
414 goto fail_base_qpair;
415 }
416
8abfa9e2 417 qla_init_base_qpair(vha, req, rsp);
e326d22a 418
c38d1baf 419 if ((ql2xmqsupport || ql2xnvmeenable) && ha->max_qpairs) {
d7459527
MH		 420 ha->queue_pair_map = kcalloc(ha->max_qpairs, sizeof(struct qla_qpair *),
421 GFP_KERNEL);
422 if (!ha->queue_pair_map) {
423 ql_log(ql_log_fatal, vha, 0x0180,
424 "Unable to allocate memory for queue pair ptrs.\n");
425 goto fail_qpair_map;
426 }
d7459527
MH		 427 }
428
9a347ff4
CD		 429 /*
430 * Make sure we record at least the request and response queue zero in
431 * case we need to free them if part of the probe fails.
432 */
433 ha->rsp_q_map[0] = rsp;
434 ha->req_q_map[0] = req;
73208dfd
AC		 435 set_bit(0, ha->rsp_qid_map);
436 set_bit(0, ha->req_qid_map);
6a2cf8d3 437 return 0;
73208dfd 438
d7459527 439fail_qpair_map:
82de802a
QT		 440 kfree(ha->base_qpair);
441 ha->base_qpair = NULL;
442fail_base_qpair:
d7459527
MH		 443 kfree(ha->rsp_q_map);
444 ha->rsp_q_map = NULL;
73208dfd
AC		 445fail_rsp_map:
446 kfree(ha->req_q_map);
447 ha->req_q_map = NULL;
448fail_req_map:
449 return -ENOMEM;
450}
451
2afa19a9 452static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req)
73208dfd 453{
8ae6d9c7
GM		 454 if (IS_QLAFX00(ha)) {
455 if (req && req->ring_fx00)
456 dma_free_coherent(&ha->pdev->dev,
457 (req->length_fx00 + 1) * sizeof(request_t),
458 req->ring_fx00, req->dma_fx00);
459 } else if (req && req->ring)
73208dfd
AC		 460 dma_free_coherent(&ha->pdev->dev,
461 (req->length + 1) * sizeof(request_t),
462 req->ring, req->dma);
463
6d634067 464 if (req)
8d93f550 465 kfree(req->outstanding_cmds);
6d634067
BK		 466
467 kfree(req);
73208dfd
AC		 468}
469
2afa19a9
AC		 470static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp)
471{
8ae6d9c7 472 if (IS_QLAFX00(ha)) {
3f6c9be2 473 if (rsp && rsp->ring_fx00)
8ae6d9c7
GM		 474 dma_free_coherent(&ha->pdev->dev,
475 (rsp->length_fx00 + 1) * sizeof(request_t),
476 rsp->ring_fx00, rsp->dma_fx00);
477 } else if (rsp && rsp->ring) {
2afa19a9
AC		 478 dma_free_coherent(&ha->pdev->dev,
479 (rsp->length + 1) * sizeof(response_t),
480 rsp->ring, rsp->dma);
8ae6d9c7 481 }
6d634067 482 kfree(rsp);
2afa19a9
AC		 483}
484
73208dfd
AC		 485static void qla2x00_free_queues(struct qla_hw_data *ha)
486{
487 struct req_que *req;
488 struct rsp_que *rsp;
489 int cnt;
093df737 490 unsigned long flags;
73208dfd 491
82de802a
QT		 492 if (ha->queue_pair_map) {
493 kfree(ha->queue_pair_map);
494 ha->queue_pair_map = NULL;
495 }
496 if (ha->base_qpair) {
497 kfree(ha->base_qpair);
498 ha->base_qpair = NULL;
499 }
500
093df737 501 spin_lock_irqsave(&ha->hardware_lock, flags);
2afa19a9 502 for (cnt = 0; cnt < ha->max_req_queues; cnt++) {
cb43285f
QT		 503 if (!test_bit(cnt, ha->req_qid_map))
504 continue;
505
73208dfd 506 req = ha->req_q_map[cnt];
093df737
QT		 507 clear_bit(cnt, ha->req_qid_map);
508 ha->req_q_map[cnt] = NULL;
509
510 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2afa19a9 511 qla2x00_free_req_que(ha, req);
093df737 512 spin_lock_irqsave(&ha->hardware_lock, flags);
73208dfd 513 }
093df737
QT		 514 spin_unlock_irqrestore(&ha->hardware_lock, flags);
515
73208dfd
AC		 516 kfree(ha->req_q_map);
517 ha->req_q_map = NULL;
2afa19a9 518
093df737
QT		 519
520 spin_lock_irqsave(&ha->hardware_lock, flags);
2afa19a9 521 for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) {
cb43285f
QT		 522 if (!test_bit(cnt, ha->rsp_qid_map))
523 continue;
524
2afa19a9 525 rsp = ha->rsp_q_map[cnt];
c3c42394 526 clear_bit(cnt, ha->rsp_qid_map);
093df737
QT		 527 ha->rsp_q_map[cnt] = NULL;
528 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2afa19a9 529 qla2x00_free_rsp_que(ha, rsp);
093df737 530 spin_lock_irqsave(&ha->hardware_lock, flags);
2afa19a9 531 }
093df737
QT		 532 spin_unlock_irqrestore(&ha->hardware_lock, flags);
533
2afa19a9
AC		 534 kfree(ha->rsp_q_map);
535 ha->rsp_q_map = NULL;
73208dfd
AC		 536}
537
1da177e4 538static char *
e315cd28 539qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str)
1da177e4 540{
e315cd28 541 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 542 static char *pci_bus_modes[] = {
543 "33", "66", "100", "133",
544 };
545 uint16_t pci_bus;
546
547 strcpy(str, "PCI");
548 pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9;
549 if (pci_bus) {
550 strcat(str, "-X (");
551 strcat(str, pci_bus_modes[pci_bus]);
552 } else {
553 pci_bus = (ha->pci_attr & BIT_8) >> 8;
554 strcat(str, " (");
555 strcat(str, pci_bus_modes[pci_bus]);
556 }
557 strcat(str, " MHz)");
558
559 return (str);
560}
561
fca29703 562static char *
e315cd28 563qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str)
fca29703
AV		 564{
565 static char *pci_bus_modes[] = { "33", "66", "100", "133", };
e315cd28 566 struct qla_hw_data *ha = vha->hw;
fca29703 567 uint32_t pci_bus;
fca29703 568
62a276f8 569 if (pci_is_pcie(ha->pdev)) {
fca29703 570 char lwstr[6];
62a276f8 571 uint32_t lstat, lspeed, lwidth;
fca29703 572
62a276f8
BH		 573 pcie_capability_read_dword(ha->pdev, PCI_EXP_LNKCAP, &lstat);
574 lspeed = lstat & PCI_EXP_LNKCAP_SLS;
575 lwidth = (lstat & PCI_EXP_LNKCAP_MLW) >> 4;
fca29703
AV		 576
577 strcpy(str, "PCIe (");
49300af7
SK		 578 switch (lspeed) {
579 case 1:
c87a0d8c 580 strcat(str, "2.5GT/s ");
49300af7
SK		 581 break;
582 case 2:
c87a0d8c 583 strcat(str, "5.0GT/s ");
49300af7
SK		 584 break;
585 case 3:
586 strcat(str, "8.0GT/s ");
587 break;
588 default:
fca29703 589 strcat(str, "<unknown> ");
49300af7
SK		 590 break;
591 }
fca29703
AV		 592 snprintf(lwstr, sizeof(lwstr), "x%d)", lwidth);
593 strcat(str, lwstr);
594
595 return str;
596 }
597
598 strcpy(str, "PCI");
599 pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8;
600 if (pci_bus == 0 || pci_bus == 8) {
601 strcat(str, " (");
602 strcat(str, pci_bus_modes[pci_bus >> 3]);
603 } else {
604 strcat(str, "-X ");
605 if (pci_bus & BIT_2)
606 strcat(str, "Mode 2");
607 else
608 strcat(str, "Mode 1");
609 strcat(str, " (");
610 strcat(str, pci_bus_modes[pci_bus & ~BIT_2]);
611 }
612 strcat(str, " MHz)");
613
614 return str;
615}
616
e5f82ab8 617static char *
df57caba 618qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
1da177e4
LT		 619{
620 char un_str[10];
e315cd28 621 struct qla_hw_data *ha = vha->hw;
fa2a1ce5 622
df57caba
HM		 623 snprintf(str, size, "%d.%02d.%02d ", ha->fw_major_version,
624 ha->fw_minor_version, ha->fw_subminor_version);
1da177e4
LT		 625
626 if (ha->fw_attributes & BIT_9) {
627 strcat(str, "FLX");
628 return (str);
629 }
630
631 switch (ha->fw_attributes & 0xFF) {
632 case 0x7:
633 strcat(str, "EF");
634 break;
635 case 0x17:
636 strcat(str, "TP");
637 break;
638 case 0x37:
639 strcat(str, "IP");
640 break;
641 case 0x77:
642 strcat(str, "VI");
643 break;
644 default:
645 sprintf(un_str, "(%x)", ha->fw_attributes);
646 strcat(str, un_str);
647 break;
648 }
649 if (ha->fw_attributes & 0x100)
650 strcat(str, "X");
651
652 return (str);
653}
654
e5f82ab8 655static char *
df57caba 656qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
fca29703 657{
e315cd28 658 struct qla_hw_data *ha = vha->hw;
f0883ac6 659
df57caba 660 snprintf(str, size, "%d.%02d.%02d (%x)", ha->fw_major_version,
3a03eb79 661 ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes);
fca29703 662 return str;
fca29703
AV		 663}
664
9ba56b95 665void
25ff6af1 666qla2x00_sp_free_dma(void *ptr)
fca29703 667{
25ff6af1
JC		 668 srb_t *sp = ptr;
669 struct qla_hw_data *ha = sp->vha->hw;
9ba56b95 670 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
9ba56b95 671 void *ctx = GET_CMD_CTX_SP(sp);
fca29703 672
9ba56b95
GM		 673 if (sp->flags & SRB_DMA_VALID) {
674 scsi_dma_unmap(cmd);
675 sp->flags &= ~SRB_DMA_VALID;
7c3df132 676 }
fca29703 677
9ba56b95
GM		 678 if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
679 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
680 scsi_prot_sg_count(cmd), cmd->sc_data_direction);
681 sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
682 }
683
d5ff0eed 684 if (!ctx)
711a08d7 685 return;
d5ff0eed 686
9ba56b95
GM		 687 if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
688 /* List assured to be having elements */
d5ff0eed 689 qla2x00_clean_dsd_pool(ha, ctx);
9ba56b95
GM		 690 sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
691 }
692
693 if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
d5ff0eed
JC		 694 struct crc_context *ctx0 = ctx;
695
696 dma_pool_free(ha->dl_dma_pool, ctx0, ctx0->crc_ctx_dma);
9ba56b95
GM		 697 sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
698 }
699
700 if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
d5ff0eed 701 struct ct6_dsd *ctx1 = ctx;
fca29703 702
9ba56b95 703 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd,
d5ff0eed 704 ctx1->fcp_cmnd_dma);
9ba56b95
GM		 705 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list);
706 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt;
707 ha->gbl_dsd_avail += ctx1->dsd_use_cnt;
708 mempool_free(ctx1, ha->ctx_mempool);
9ba56b95 709 }
9ba56b95
GM		 710}
711
d7459527 712void
25ff6af1 713qla2x00_sp_compl(void *ptr, int res)
9ba56b95 714{
25ff6af1 715 srb_t *sp = ptr;
9ba56b95 716 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
219d27d7 717 struct completion *comp = sp->comp;
9ba56b95 718
db4bf822 719 if (WARN_ON_ONCE(atomic_read(&sp->ref_count) == 0))
9ba56b95 720 return;
219d27d7
BVA		 721
722 atomic_dec(&sp->ref_count);
9ba56b95 723
f3caa990 724 sp->free(sp);
740e2935 725 cmd->result = res;
711a08d7 726 CMD_SP(cmd) = NULL;
9ba56b95 727 cmd->scsi_done(cmd);
219d27d7
BVA		 728 if (comp)
729 complete(comp);
711a08d7 730 qla2x00_rel_sp(sp);
fca29703
AV		 731}
732
d7459527 733void
25ff6af1 734qla2xxx_qpair_sp_free_dma(void *ptr)
d7459527
MH		 735{
736 srb_t *sp = (srb_t *)ptr;
737 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
738 struct qla_hw_data *ha = sp->fcport->vha->hw;
739 void *ctx = GET_CMD_CTX_SP(sp);
740
741 if (sp->flags & SRB_DMA_VALID) {
742 scsi_dma_unmap(cmd);
743 sp->flags &= ~SRB_DMA_VALID;
744 }
745
746 if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
747 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
748 scsi_prot_sg_count(cmd), cmd->sc_data_direction);
749 sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
750 }
751
d5ff0eed 752 if (!ctx)
711a08d7 753 return;
d5ff0eed 754
d7459527
MH		 755 if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
756 /* List assured to be having elements */
d5ff0eed 757 qla2x00_clean_dsd_pool(ha, ctx);
d7459527
MH		 758 sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
759 }
760
50b81275 761 if (sp->flags & SRB_DIF_BUNDL_DMA_VALID) {
d8f945bf 762 struct crc_context *difctx = ctx;
50b81275
GM		 763 struct dsd_dma *dif_dsd, *nxt_dsd;
764
765 list_for_each_entry_safe(dif_dsd, nxt_dsd,
766 &difctx->ldif_dma_hndl_list, list) {
767 list_del(&dif_dsd->list);
768 dma_pool_free(ha->dif_bundl_pool, dif_dsd->dsd_addr,
769 dif_dsd->dsd_list_dma);
770 kfree(dif_dsd);
771 difctx->no_dif_bundl--;
772 }
773
774 list_for_each_entry_safe(dif_dsd, nxt_dsd,
775 &difctx->ldif_dsd_list, list) {
776 list_del(&dif_dsd->list);
777 dma_pool_free(ha->dl_dma_pool, dif_dsd->dsd_addr,
778 dif_dsd->dsd_list_dma);
779 kfree(dif_dsd);
780 difctx->no_ldif_dsd--;
781 }
782
783 if (difctx->no_ldif_dsd) {
784 ql_dbg(ql_dbg_tgt+ql_dbg_verbose, sp->vha, 0xe022,
785 "%s: difctx->no_ldif_dsd=%x\n",
786 __func__, difctx->no_ldif_dsd);
787 }
788
789 if (difctx->no_dif_bundl) {
790 ql_dbg(ql_dbg_tgt+ql_dbg_verbose, sp->vha, 0xe022,
791 "%s: difctx->no_dif_bundl=%x\n",
792 __func__, difctx->no_dif_bundl);
793 }
794 sp->flags &= ~SRB_DIF_BUNDL_DMA_VALID;
d7459527 795 }
d8f945bf
BVA		 796
797 if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
798 struct ct6_dsd *ctx1 = ctx;
799
800 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd,
801 ctx1->fcp_cmnd_dma);
802 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list);
803 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt;
804 ha->gbl_dsd_avail += ctx1->dsd_use_cnt;
805 mempool_free(ctx1, ha->ctx_mempool);
806 sp->flags &= ~SRB_FCP_CMND_DMA_VALID;
807 }
808
809 if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
810 struct crc_context *ctx0 = ctx;
811
812 dma_pool_free(ha->dl_dma_pool, ctx, ctx0->crc_ctx_dma);
813 sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
814 }
d7459527
MH		 815}
816
817void
25ff6af1 818qla2xxx_qpair_sp_compl(void *ptr, int res)
d7459527 819{
25ff6af1 820 srb_t *sp = ptr;
d7459527 821 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
219d27d7 822 struct completion *comp = sp->comp;
d7459527 823
db4bf822 824 if (WARN_ON_ONCE(atomic_read(&sp->ref_count) == 0))
d7459527 825 return;
219d27d7
BVA		 826
827 atomic_dec(&sp->ref_count);
d7459527 828
f3caa990 829 sp->free(sp);
711a08d7
GM		 830 cmd->result = res;
831 CMD_SP(cmd) = NULL;
d7459527 832 cmd->scsi_done(cmd);
219d27d7
BVA		 833 if (comp)
834 complete(comp);
711a08d7 835 qla2xxx_rel_qpair_sp(sp->qpair, sp);
d7459527
MH		 836}
837
1da177e4 838static int
f5e3e40b 839qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
fca29703 840{
134ae078 841 scsi_qla_host_t *vha = shost_priv(host);
fca29703 842 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
19a7b4ae 843 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
e315cd28
AC		 844 struct qla_hw_data *ha = vha->hw;
845 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
fca29703
AV		 846 srb_t *sp;
847 int rval;
848
2dbb02fd
BVA		 849 if (unlikely(test_bit(UNLOADING, &base_vha->dpc_flags)) ||
850 WARN_ON_ONCE(!rport)) {
04dfaa53
MFO		 851 cmd->result = DID_NO_CONNECT << 16;
852 goto qc24_fail_command;
853 }
854
5601236b 855 if (ha->mqenable) {
6d58ef05
BVA		 856 uint32_t tag;
857 uint16_t hwq;
858 struct qla_qpair *qpair = NULL;
859
f664a3cc
JA		 860 tag = blk_mq_unique_tag(cmd->request);
861 hwq = blk_mq_unique_tag_to_hwq(tag);
862 qpair = ha->queue_pair_map[hwq];
5601236b
MH		 863
864 if (qpair)
865 return qla2xxx_mqueuecommand(host, cmd, qpair);
d7459527
MH		 866 }
867
85880801 868 if (ha->flags.eeh_busy) {
7c3df132 869 if (ha->flags.pci_channel_io_perm_failure) {
5f28d2d7 870 ql_dbg(ql_dbg_aer, vha, 0x9010,
7c3df132
SK		 871 "PCI Channel IO permanent failure, exiting "
872 "cmd=%p.\n", cmd);
b9b12f73 873 cmd->result = DID_NO_CONNECT << 16;
7c3df132 874 } else {
5f28d2d7 875 ql_dbg(ql_dbg_aer, vha, 0x9011,
7c3df132 876 "EEH_Busy, Requeuing the cmd=%p.\n", cmd);
85880801 877 cmd->result = DID_REQUEUE << 16;
7c3df132 878 }
14e660e6
SJ		 879 goto qc24_fail_command;
880 }
881
19a7b4ae
JSEC		 882 rval = fc_remote_port_chkready(rport);
883 if (rval) {
884 cmd->result = rval;
5f28d2d7 885 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3003,
7c3df132
SK		 886 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
887 cmd, rval);
fca29703
AV		 888 goto qc24_fail_command;
889 }
890
bad75002
AE		 891 if (!vha->flags.difdix_supported &&
892 scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) {
7c3df132
SK		 893 ql_dbg(ql_dbg_io, vha, 0x3004,
894 "DIF Cap not reg, fail DIF capable cmd's:%p.\n",
895 cmd);
bad75002
AE		 896 cmd->result = DID_NO_CONNECT << 16;
897 goto qc24_fail_command;
898 }
aa651be8
CD		 899
900 if (!fcport) {
901 cmd->result = DID_NO_CONNECT << 16;
902 goto qc24_fail_command;
903 }
904
fca29703
AV		 905 if (atomic_read(&fcport->state) != FCS_ONLINE) {
906 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
38170fa8 907 atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
7c3df132
SK		 908 ql_dbg(ql_dbg_io, vha, 0x3005,
909 "Returning DNC, fcport_state=%d loop_state=%d.\n",
910 atomic_read(&fcport->state),
911 atomic_read(&base_vha->loop_state));
fca29703
AV		 912 cmd->result = DID_NO_CONNECT << 16;
913 goto qc24_fail_command;
914 }
7b594131 915 goto qc24_target_busy;
fca29703
AV		 916 }
917
e05fe292
CD		 918 /*
919 * Return target busy if we've received a non-zero retry_delay_timer
920 * in a FCP_RSP.
921 */
975f7d46
BP		 922 if (fcport->retry_delay_timestamp == 0) {
923 /* retry delay not set */
924 } else if (time_after(jiffies, fcport->retry_delay_timestamp))
e05fe292
CD		 925 fcport->retry_delay_timestamp = 0;
926 else
927 goto qc24_target_busy;
928
b00ee7d7 929 sp = qla2x00_get_sp(vha, fcport, GFP_ATOMIC);
50280c01 930 if (!sp)
f5e3e40b 931 goto qc24_host_busy;
fca29703 932
9ba56b95
GM		 933 sp->u.scmd.cmd = cmd;
934 sp->type = SRB_SCSI_CMD;
935 atomic_set(&sp->ref_count, 1);
936 CMD_SP(cmd) = (void *)sp;
937 sp->free = qla2x00_sp_free_dma;
938 sp->done = qla2x00_sp_compl;
939
e315cd28 940 rval = ha->isp_ops->start_scsi(sp);
7c3df132 941 if (rval != QLA_SUCCESS) {
53016ed3 942 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3013,
7c3df132 943 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
fca29703 944 goto qc24_host_busy_free_sp;
7c3df132 945 }
fca29703 946
fca29703
AV		 947 return 0;
948
949qc24_host_busy_free_sp:
f3caa990 950 sp->free(sp);
fca29703 951
f5e3e40b 952qc24_host_busy:
fca29703
AV		 953 return SCSI_MLQUEUE_HOST_BUSY;
954
7b594131
MC		 955qc24_target_busy:
956 return SCSI_MLQUEUE_TARGET_BUSY;
957
fca29703 958qc24_fail_command:
f5e3e40b 959 cmd->scsi_done(cmd);
fca29703
AV		 960
961 return 0;
962}
963
d7459527
MH		 964/* For MQ supported I/O */
965int
966qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd,
967 struct qla_qpair *qpair)
968{
969 scsi_qla_host_t *vha = shost_priv(host);
970 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
971 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
972 struct qla_hw_data *ha = vha->hw;
973 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
974 srb_t *sp;
975 int rval;
976
2dbb02fd 977 rval = rport ? fc_remote_port_chkready(rport) : FC_PORTSTATE_OFFLINE;
d7459527
MH		 978 if (rval) {
979 cmd->result = rval;
980 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3076,
981 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
982 cmd, rval);
983 goto qc24_fail_command;
984 }
985
986 if (!fcport) {
987 cmd->result = DID_NO_CONNECT << 16;
988 goto qc24_fail_command;
989 }
990
991 if (atomic_read(&fcport->state) != FCS_ONLINE) {
992 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
993 atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
994 ql_dbg(ql_dbg_io, vha, 0x3077,
995 "Returning DNC, fcport_state=%d loop_state=%d.\n",
996 atomic_read(&fcport->state),
997 atomic_read(&base_vha->loop_state));
998 cmd->result = DID_NO_CONNECT << 16;
999 goto qc24_fail_command;
1000 }
1001 goto qc24_target_busy;
1002 }
1003
1004 /*
1005 * Return target busy if we've received a non-zero retry_delay_timer
1006 * in a FCP_RSP.
1007 */
1008 if (fcport->retry_delay_timestamp == 0) {
1009 /* retry delay not set */
1010 } else if (time_after(jiffies, fcport->retry_delay_timestamp))
1011 fcport->retry_delay_timestamp = 0;
1012 else
1013 goto qc24_target_busy;
1014
6a629468 1015 sp = qla2xxx_get_qpair_sp(vha, qpair, fcport, GFP_ATOMIC);
d7459527
MH		 1016 if (!sp)
1017 goto qc24_host_busy;
1018
1019 sp->u.scmd.cmd = cmd;
1020 sp->type = SRB_SCSI_CMD;
1021 atomic_set(&sp->ref_count, 1);
1022 CMD_SP(cmd) = (void *)sp;
1023 sp->free = qla2xxx_qpair_sp_free_dma;
1024 sp->done = qla2xxx_qpair_sp_compl;
1025 sp->qpair = qpair;
1026
1027 rval = ha->isp_ops->start_scsi_mq(sp);
1028 if (rval != QLA_SUCCESS) {
1029 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3078,
1030 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
1031 if (rval == QLA_INTERFACE_ERROR)
1032 goto qc24_fail_command;
1033 goto qc24_host_busy_free_sp;
1034 }
1035
1036 return 0;
1037
1038qc24_host_busy_free_sp:
f3caa990 1039 sp->free(sp);
d7459527
MH		 1040
1041qc24_host_busy:
1042 return SCSI_MLQUEUE_HOST_BUSY;
1043
1044qc24_target_busy:
1045 return SCSI_MLQUEUE_TARGET_BUSY;
1046
1047qc24_fail_command:
1048 cmd->scsi_done(cmd);
1049
1050 return 0;
1051}
1052
1da177e4
LT		 1053/*
1054 * qla2x00_eh_wait_on_command
1055 * Waits for the command to be returned by the Firmware for some
1056 * max time.
1057 *
1058 * Input:
1da177e4 1059 * cmd = Scsi Command to wait on.
1da177e4
LT		 1060 *
1061 * Return:
1062 * Not Found : 0
1063 * Found : 1
1064 */
1065static int
e315cd28 1066qla2x00_eh_wait_on_command(struct scsi_cmnd *cmd)
1da177e4 1067{
fe74c71f 1068#define ABORT_POLLING_PERIOD 1000
478c3b03 1069#define ABORT_WAIT_ITER ((2 * 1000) / (ABORT_POLLING_PERIOD))
f4f051eb 1070 unsigned long wait_iter = ABORT_WAIT_ITER;
85880801
AV		 1071 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1072 struct qla_hw_data *ha = vha->hw;
f4f051eb 1073 int ret = QLA_SUCCESS;
1da177e4 1074
85880801 1075 if (unlikely(pci_channel_offline(ha->pdev)) || ha->flags.eeh_busy) {
7c3df132
SK		 1076 ql_dbg(ql_dbg_taskm, vha, 0x8005,
1077 "Return:eh_wait.\n");
85880801
AV		 1078 return ret;
1079 }
1080
d970432c 1081 while (CMD_SP(cmd) && wait_iter--) {
fe74c71f 1082 msleep(ABORT_POLLING_PERIOD);
f4f051eb 1083 }
1084 if (CMD_SP(cmd))
1085 ret = QLA_FUNCTION_FAILED;
1da177e4 1086
f4f051eb 1087 return ret;
1da177e4
LT		 1088}
1089
1090/*
1091 * qla2x00_wait_for_hba_online
fa2a1ce5 1092 * Wait till the HBA is online after going through
1da177e4
LT		 1093 * <= MAX_RETRIES_OF_ISP_ABORT or
1094 * finally HBA is disabled ie marked offline
1095 *
1096 * Input:
1097 * ha - pointer to host adapter structure
fa2a1ce5
AV		 1098 *
1099 * Note:
1da177e4
LT		 1100 * Does context switching-Release SPIN_LOCK
1101 * (if any) before calling this routine.
1102 *
1103 * Return:
1104 * Success (Adapter is online) : 0
1105 * Failed (Adapter is offline/disabled) : 1
1106 */
854165f4 1107int
e315cd28 1108qla2x00_wait_for_hba_online(scsi_qla_host_t *vha)
1da177e4 1109{
fca29703
AV		 1110 int return_status;
1111 unsigned long wait_online;
e315cd28
AC		 1112 struct qla_hw_data *ha = vha->hw;
1113 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4 1114
fa2a1ce5 1115 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ);
e315cd28
AC		 1116 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
1117 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
1118 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
1119 ha->dpc_active) && time_before(jiffies, wait_online)) {
1da177e4
LT		 1120
1121 msleep(1000);
1122 }
e315cd28 1123 if (base_vha->flags.online)
fa2a1ce5 1124 return_status = QLA_SUCCESS;
1da177e4
LT		 1125 else
1126 return_status = QLA_FUNCTION_FAILED;
1127
1da177e4
LT		 1128 return (return_status);
1129}
1130
726b8548
QT		 1131static inline int test_fcport_count(scsi_qla_host_t *vha)
1132{
1133 struct qla_hw_data *ha = vha->hw;
1134 unsigned long flags;
1135 int res;
1136
1137 spin_lock_irqsave(&ha->tgt.sess_lock, flags);
83548fe2
QT		 1138 ql_dbg(ql_dbg_init, vha, 0x00ec,
1139 "tgt %p, fcport_count=%d\n",
1140 vha, vha->fcport_count);
726b8548
QT		 1141 res = (vha->fcport_count == 0);
1142 spin_unlock_irqrestore(&ha->tgt.sess_lock, flags);
1143
1144 return res;
1145}
1146
1147/*
1148 * qla2x00_wait_for_sess_deletion can only be called from remove_one.
1149 * it has dependency on UNLOADING flag to stop device discovery
1150 */
efa93f48 1151void
726b8548
QT		 1152qla2x00_wait_for_sess_deletion(scsi_qla_host_t *vha)
1153{
1154 qla2x00_mark_all_devices_lost(vha, 0);
1155
b85e0957 1156 wait_event_timeout(vha->fcport_waitQ, test_fcport_count(vha), 10*HZ);
726b8548
QT		 1157}
1158
86fbee86 1159/*
638a1a01
SC		 1160 * qla2x00_wait_for_hba_ready
1161 * Wait till the HBA is ready before doing driver unload
86fbee86
LC		 1162 *
1163 * Input:
1164 * ha - pointer to host adapter structure
1165 *
1166 * Note:
1167 * Does context switching-Release SPIN_LOCK
1168 * (if any) before calling this routine.
1169 *
86fbee86 1170 */
638a1a01
SC		 1171static void
1172qla2x00_wait_for_hba_ready(scsi_qla_host_t *vha)
86fbee86 1173{
86fbee86 1174 struct qla_hw_data *ha = vha->hw;
783e0dc4 1175 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
86fbee86 1176
1d483901
DC		 1177 while ((qla2x00_reset_active(vha) || ha->dpc_active ||
1178 ha->flags.mbox_busy) ||
1179 test_bit(FX00_RESET_RECOVERY, &vha->dpc_flags) ||
1180 test_bit(FX00_TARGET_SCAN, &vha->dpc_flags)) {
1181 if (test_bit(UNLOADING, &base_vha->dpc_flags))
1182 break;
86fbee86 1183 msleep(1000);
783e0dc4 1184 }
86fbee86
LC		 1185}
1186
2533cf67
LC		 1187int
1188qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha)
1189{
1190 int return_status;
1191 unsigned long wait_reset;
1192 struct qla_hw_data *ha = vha->hw;
1193 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1194
1195 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ);
1196 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
1197 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
1198 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
1199 ha->dpc_active) && time_before(jiffies, wait_reset)) {
1200
1201 msleep(1000);
1202
1203 if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) &&
1204 ha->flags.chip_reset_done)
1205 break;
1206 }
1207 if (ha->flags.chip_reset_done)
1208 return_status = QLA_SUCCESS;
1209 else
1210 return_status = QLA_FUNCTION_FAILED;
1211
1212 return return_status;
1213}
1214
585def9b 1215static int
083a469d
GM		 1216sp_get(struct srb *sp)
1217{
845bbb09 1218 if (!refcount_inc_not_zero((refcount_t *)&sp->ref_count))
585def9b
QT		 1219 /* kref get fail */
1220 return ENXIO;
1221 else
1222 return 0;
083a469d
GM		 1223}
1224
a465537a
SC		 1225#define ISP_REG_DISCONNECT 0xffffffffU
1226/**************************************************************************
1227* qla2x00_isp_reg_stat
1228*
1229* Description:
1230* Read the host status register of ISP before aborting the command.
1231*
1232* Input:
1233* ha = pointer to host adapter structure.
1234*
1235*
1236* Returns:
1237* Either true or false.
1238*
1239* Note: Return true if there is register disconnect.
1240**************************************************************************/
1241static inline
1242uint32_t qla2x00_isp_reg_stat(struct qla_hw_data *ha)
1243{
1244 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
bf6061b1 1245 struct device_reg_82xx __iomem *reg82 = &ha->iobase->isp82;
a465537a 1246
bf6061b1
SC		 1247 if (IS_P3P_TYPE(ha))
1248 return ((RD_REG_DWORD(&reg82->host_int)) == ISP_REG_DISCONNECT);
1249 else
1250 return ((RD_REG_DWORD(&reg->host_status)) ==
1251 ISP_REG_DISCONNECT);
a465537a
SC		 1252}
1253
1da177e4
LT		 1254/**************************************************************************
1255* qla2xxx_eh_abort
1256*
1257* Description:
1258* The abort function will abort the specified command.
1259*
1260* Input:
1261* cmd = Linux SCSI command packet to be aborted.
1262*
1263* Returns:
1264* Either SUCCESS or FAILED.
1265*
1266* Note:
2ea00202 1267* Only return FAILED if command not returned by firmware.
1da177e4 1268**************************************************************************/
e5f82ab8 1269static int
1da177e4
LT		 1270qla2xxx_eh_abort(struct scsi_cmnd *cmd)
1271{
e315cd28 1272 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
8dd9593c 1273 DECLARE_COMPLETION_ONSTACK(comp);
f4f051eb 1274 srb_t *sp;
4e98d3b8 1275 int ret;
9cb78c16
HR		 1276 unsigned int id;
1277 uint64_t lun;
18e144d3 1278 unsigned long flags;
219d27d7 1279 int rval;
e315cd28 1280 struct qla_hw_data *ha = vha->hw;
585def9b 1281 struct qla_qpair *qpair;
1da177e4 1282
a465537a
SC		 1283 if (qla2x00_isp_reg_stat(ha)) {
1284 ql_log(ql_log_info, vha, 0x8042,
1285 "PCI/Register disconnect, exiting.\n");
1286 return FAILED;
1287 }
1da177e4 1288
4e98d3b8
AV		 1289 ret = fc_block_scsi_eh(cmd);
1290 if (ret != 0)
1291 return ret;
4e98d3b8 1292
170babc3 1293 sp = (srb_t *) CMD_SP(cmd);
585def9b
QT		 1294 if (!sp)
1295 return SUCCESS;
1296
1297 qpair = sp->qpair;
1298 if (!qpair)
1299 return SUCCESS;
1300
7f4374e6
QT		 1301 if (sp->fcport && sp->fcport->deleted)
1302 return SUCCESS;
1303
585def9b 1304 spin_lock_irqsave(qpair->qp_lock_ptr, flags);
219d27d7 1305 if (sp->type != SRB_SCSI_CMD || GET_CMD_SP(sp) != cmd) {
585def9b
QT		 1306 /* there's a chance an interrupt could clear
1307 the ptr as part of done & free */
1308 spin_unlock_irqrestore(qpair->qp_lock_ptr, flags);
170babc3
MC		 1309 return SUCCESS;
1310 }
1da177e4 1311
8dd9593c 1312 /* Get a reference to the sp and drop the lock. */
585def9b
QT		 1313 if (sp_get(sp)){
1314 /* ref_count is already 0 */
1315 spin_unlock_irqrestore(qpair->qp_lock_ptr, flags);
170babc3
MC		 1316 return SUCCESS;
1317 }
585def9b
QT		 1318 spin_unlock_irqrestore(qpair->qp_lock_ptr, flags);
1319
1320 id = cmd->device->id;
1321 lun = cmd->device->lun;
1da177e4 1322
7c3df132 1323 ql_dbg(ql_dbg_taskm, vha, 0x8002,
c7bc4cae
CD		 1324 "Aborting from RISC nexus=%ld:%d:%llu sp=%p cmd=%p handle=%x\n",
1325 vha->host_no, id, lun, sp, cmd, sp->handle);
17d98630 1326
f934c9d0 1327 rval = ha->isp_ops->abort_command(sp);
219d27d7
BVA		 1328 ql_dbg(ql_dbg_taskm, vha, 0x8003,
1329 "Abort command mbx cmd=%p, rval=%x.\n", cmd, rval);
f934c9d0 1330
219d27d7
BVA		 1331 switch (rval) {
1332 case QLA_SUCCESS:
711a08d7 1333 /*
219d27d7
BVA		 1334 * The command has been aborted. That means that the firmware
1335 * won't report a completion.
711a08d7 1336 */
219d27d7
BVA		 1337 sp->done(sp, DID_ABORT << 16);
1338 ret = SUCCESS;
1339 break;
8dd9593c
BVA		 1340 case QLA_FUNCTION_PARAMETER_ERROR: {
1341 /* Wait for the command completion. */
1342 uint32_t ratov = ha->r_a_tov/10;
1343 uint32_t ratov_j = msecs_to_jiffies(4 * ratov * 1000);
1344
1345 WARN_ON_ONCE(sp->comp);
1346 sp->comp = &comp;
1347 if (!wait_for_completion_timeout(&comp, ratov_j)) {
1348 ql_dbg(ql_dbg_taskm, vha, 0xffff,
1349 "%s: Abort wait timer (4 * R_A_TOV[%d]) expired\n",
1350 __func__, ha->r_a_tov);
1351 ret = FAILED;
1352 } else {
1353 ret = SUCCESS;
1354 }
1355 break;
1356 }
219d27d7
BVA		 1357 default:
1358 /*
1359 * Either abort failed or abort and completion raced. Let
1360 * the SCSI core retry the abort in the former case.
1361 */
1362 ret = FAILED;
1363 break;
1da177e4 1364 }
219d27d7 1365
8dd9593c
BVA		 1366 sp->comp = NULL;
1367 atomic_dec(&sp->ref_count);
7c3df132 1368 ql_log(ql_log_info, vha, 0x801c,
219d27d7
BVA		 1369 "Abort command issued nexus=%ld:%d:%llu -- %x.\n",
1370 vha->host_no, id, lun, ret);
1da177e4 1371
f4f051eb 1372 return ret;
1373}
1da177e4 1374
4d78c973 1375int
e315cd28 1376qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t,
9cb78c16 1377 uint64_t l, enum nexus_wait_type type)
f4f051eb 1378{
17d98630 1379 int cnt, match, status;
18e144d3 1380 unsigned long flags;
e315cd28 1381 struct qla_hw_data *ha = vha->hw;
73208dfd 1382 struct req_que *req;
4d78c973 1383 srb_t *sp;
9ba56b95 1384 struct scsi_cmnd *cmd;
1da177e4 1385
523ec773 1386 status = QLA_SUCCESS;
17d98630 1387
e315cd28 1388 spin_lock_irqsave(&ha->hardware_lock, flags);
67c2e93a 1389 req = vha->req;
17d98630 1390 for (cnt = 1; status == QLA_SUCCESS &&
8d93f550 1391 cnt < req->num_outstanding_cmds; cnt++) {
17d98630
AC		 1392 sp = req->outstanding_cmds[cnt];
1393 if (!sp)
523ec773 1394 continue;
9ba56b95 1395 if (sp->type != SRB_SCSI_CMD)
cf53b069 1396 continue;
25ff6af1 1397 if (vha->vp_idx != sp->vha->vp_idx)
17d98630
AC		 1398 continue;
1399 match = 0;
9ba56b95 1400 cmd = GET_CMD_SP(sp);
17d98630
AC		 1401 switch (type) {
1402 case WAIT_HOST:
1403 match = 1;
1404 break;
1405 case WAIT_TARGET:
9ba56b95 1406 match = cmd->device->id == t;
17d98630
AC		 1407 break;
1408 case WAIT_LUN:
9ba56b95
GM		 1409 match = (cmd->device->id == t &&
1410 cmd->device->lun == l);
17d98630 1411 break;
73208dfd 1412 }
17d98630
AC		 1413 if (!match)
1414 continue;
1415
1416 spin_unlock_irqrestore(&ha->hardware_lock, flags);
9ba56b95 1417 status = qla2x00_eh_wait_on_command(cmd);
17d98630 1418 spin_lock_irqsave(&ha->hardware_lock, flags);
1da177e4 1419 }
e315cd28 1420 spin_unlock_irqrestore(&ha->hardware_lock, flags);
523ec773
AV		 1421
1422 return status;
1da177e4
LT		 1423}
1424
523ec773
AV		 1425static char *reset_errors[] = {
1426 "HBA not online",
1427 "HBA not ready",
1428 "Task management failed",
1429 "Waiting for command completions",
1430};
1da177e4 1431
e5f82ab8 1432static int
523ec773 1433__qla2xxx_eh_generic_reset(char *name, enum nexus_wait_type type,
9cb78c16 1434 struct scsi_cmnd *cmd, int (*do_reset)(struct fc_port *, uint64_t, int))
1da177e4 1435{
e315cd28 1436 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
bdf79621 1437 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
523ec773 1438 int err;
1da177e4 1439
7c3df132 1440 if (!fcport) {
523ec773 1441 return FAILED;
7c3df132 1442 }
1da177e4 1443
4e98d3b8
AV		 1444 err = fc_block_scsi_eh(cmd);
1445 if (err != 0)
1446 return err;
1447
7f4374e6
QT		 1448 if (fcport->deleted)
1449 return SUCCESS;
1450
7c3df132 1451 ql_log(ql_log_info, vha, 0x8009,
9cb78c16 1452 "%s RESET ISSUED nexus=%ld:%d:%llu cmd=%p.\n", name, vha->host_no,
7c3df132 1453 cmd->device->id, cmd->device->lun, cmd);
1da177e4 1454
523ec773 1455 err = 0;
7c3df132
SK		 1456 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1457 ql_log(ql_log_warn, vha, 0x800a,
1458 "Wait for hba online failed for cmd=%p.\n", cmd);
523ec773 1459 goto eh_reset_failed;
7c3df132 1460 }
523ec773 1461 err = 2;
ac444b4f 1462 if (do_reset(fcport, cmd->device->lun, 1)
7c3df132
SK		 1463 != QLA_SUCCESS) {
1464 ql_log(ql_log_warn, vha, 0x800c,
1465 "do_reset failed for cmd=%p.\n", cmd);
523ec773 1466 goto eh_reset_failed;
7c3df132 1467 }
523ec773 1468 err = 3;
e315cd28 1469 if (qla2x00_eh_wait_for_pending_commands(vha, cmd->device->id,
7c3df132
SK		 1470 cmd->device->lun, type) != QLA_SUCCESS) {
1471 ql_log(ql_log_warn, vha, 0x800d,
d6a03581 1472 "wait for pending cmds failed for cmd=%p.\n", cmd);
523ec773 1473 goto eh_reset_failed;
7c3df132 1474 }
523ec773 1475
7c3df132 1476 ql_log(ql_log_info, vha, 0x800e,
9cb78c16 1477 "%s RESET SUCCEEDED nexus:%ld:%d:%llu cmd=%p.\n", name,
cfb0919c 1478 vha->host_no, cmd->device->id, cmd->device->lun, cmd);
523ec773
AV		 1479
1480 return SUCCESS;
1481
4d78c973 1482eh_reset_failed:
7c3df132 1483 ql_log(ql_log_info, vha, 0x800f,
9cb78c16 1484 "%s RESET FAILED: %s nexus=%ld:%d:%llu cmd=%p.\n", name,
cfb0919c
CD		 1485 reset_errors[err], vha->host_no, cmd->device->id, cmd->device->lun,
1486 cmd);
523ec773
AV		 1487 return FAILED;
1488}
1da177e4 1489
523ec773
AV		 1490static int
1491qla2xxx_eh_device_reset(struct scsi_cmnd *cmd)
1492{
e315cd28
AC		 1493 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1494 struct qla_hw_data *ha = vha->hw;
1da177e4 1495
a465537a
SC		 1496 if (qla2x00_isp_reg_stat(ha)) {
1497 ql_log(ql_log_info, vha, 0x803e,
1498 "PCI/Register disconnect, exiting.\n");
1499 return FAILED;
1500 }
1501
523ec773
AV		 1502 return __qla2xxx_eh_generic_reset("DEVICE", WAIT_LUN, cmd,
1503 ha->isp_ops->lun_reset);
1da177e4
LT		 1504}
1505
1da177e4 1506static int
523ec773 1507qla2xxx_eh_target_reset(struct scsi_cmnd *cmd)
1da177e4 1508{
e315cd28
AC		 1509 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1510 struct qla_hw_data *ha = vha->hw;
1da177e4 1511
a465537a
SC		 1512 if (qla2x00_isp_reg_stat(ha)) {
1513 ql_log(ql_log_info, vha, 0x803f,
1514 "PCI/Register disconnect, exiting.\n");
1515 return FAILED;
1516 }
1517
523ec773
AV		 1518 return __qla2xxx_eh_generic_reset("TARGET", WAIT_TARGET, cmd,
1519 ha->isp_ops->target_reset);
1da177e4
LT		 1520}
1521
1da177e4
LT		 1522/**************************************************************************
1523* qla2xxx_eh_bus_reset
1524*
1525* Description:
1526* The bus reset function will reset the bus and abort any executing
1527* commands.
1528*
1529* Input:
1530* cmd = Linux SCSI command packet of the command that cause the
1531* bus reset.
1532*
1533* Returns:
1534* SUCCESS/FAILURE (defined as macro in scsi.h).
1535*
1536**************************************************************************/
e5f82ab8 1537static int
1da177e4
LT		 1538qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd)
1539{
e315cd28 1540 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
bdf79621 1541 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
2c3dfe3f 1542 int ret = FAILED;
9cb78c16
HR		 1543 unsigned int id;
1544 uint64_t lun;
a465537a
SC		 1545 struct qla_hw_data *ha = vha->hw;
1546
1547 if (qla2x00_isp_reg_stat(ha)) {
1548 ql_log(ql_log_info, vha, 0x8040,
1549 "PCI/Register disconnect, exiting.\n");
1550 return FAILED;
1551 }
f4f051eb 1552
f4f051eb 1553 id = cmd->device->id;
1554 lun = cmd->device->lun;
1da177e4 1555
7c3df132 1556 if (!fcport) {
f4f051eb 1557 return ret;
7c3df132 1558 }
1da177e4 1559
4e98d3b8
AV		 1560 ret = fc_block_scsi_eh(cmd);
1561 if (ret != 0)
1562 return ret;
1563 ret = FAILED;
1564
7f4374e6
QT		 1565 if (qla2x00_chip_is_down(vha))
1566 return ret;
1567
7c3df132 1568 ql_log(ql_log_info, vha, 0x8012,
9cb78c16 1569 "BUS RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun);
1da177e4 1570
e315cd28 1571 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
7c3df132
SK		 1572 ql_log(ql_log_fatal, vha, 0x8013,
1573 "Wait for hba online failed board disabled.\n");
f4f051eb 1574 goto eh_bus_reset_done;
1da177e4
LT		 1575 }
1576
ad537689
SK		 1577 if (qla2x00_loop_reset(vha) == QLA_SUCCESS)
1578 ret = SUCCESS;
1579
f4f051eb 1580 if (ret == FAILED)
1581 goto eh_bus_reset_done;
1da177e4 1582
9a41a62b 1583 /* Flush outstanding commands. */
4d78c973 1584 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) !=
7c3df132
SK		 1585 QLA_SUCCESS) {
1586 ql_log(ql_log_warn, vha, 0x8014,
1587 "Wait for pending commands failed.\n");
9a41a62b 1588 ret = FAILED;
7c3df132 1589 }
1da177e4 1590
f4f051eb 1591eh_bus_reset_done:
7c3df132 1592 ql_log(ql_log_warn, vha, 0x802b,
9cb78c16 1593 "BUS RESET %s nexus=%ld:%d:%llu.\n",
d6a03581 1594 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1da177e4 1595
f4f051eb 1596 return ret;
1da177e4
LT		 1597}
1598
1599/**************************************************************************
1600* qla2xxx_eh_host_reset
1601*
1602* Description:
1603* The reset function will reset the Adapter.
1604*
1605* Input:
1606* cmd = Linux SCSI command packet of the command that cause the
1607* adapter reset.
1608*
1609* Returns:
1610* Either SUCCESS or FAILED.
1611*
1612* Note:
1613**************************************************************************/
e5f82ab8 1614static int
1da177e4
LT		 1615qla2xxx_eh_host_reset(struct scsi_cmnd *cmd)
1616{
e315cd28 1617 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
e315cd28 1618 struct qla_hw_data *ha = vha->hw;
2c3dfe3f 1619 int ret = FAILED;
9cb78c16
HR		 1620 unsigned int id;
1621 uint64_t lun;
e315cd28 1622 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4 1623
a465537a
SC		 1624 if (qla2x00_isp_reg_stat(ha)) {
1625 ql_log(ql_log_info, vha, 0x8041,
1626 "PCI/Register disconnect, exiting.\n");
1627 schedule_work(&ha->board_disable);
1628 return SUCCESS;
1629 }
1630
f4f051eb 1631 id = cmd->device->id;
1632 lun = cmd->device->lun;
f4f051eb 1633
7c3df132 1634 ql_log(ql_log_info, vha, 0x8018,
9cb78c16 1635 "ADAPTER RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun);
1da177e4 1636
63ee7072
CD		 1637 /*
1638 * No point in issuing another reset if one is active. Also do not
1639 * attempt a reset if we are updating flash.
1640 */
1641 if (qla2x00_reset_active(vha) || ha->optrom_state != QLA_SWAITING)
f4f051eb 1642 goto eh_host_reset_lock;
1da177e4 1643
e315cd28
AC		 1644 if (vha != base_vha) {
1645 if (qla2x00_vp_abort_isp(vha))
f4f051eb 1646 goto eh_host_reset_lock;
e315cd28 1647 } else {
7ec0effd 1648 if (IS_P3P_TYPE(vha->hw)) {
a9083016
GM		 1649 if (!qla82xx_fcoe_ctx_reset(vha)) {
1650 /* Ctx reset success */
1651 ret = SUCCESS;
1652 goto eh_host_reset_lock;
1653 }
1654 /* fall thru if ctx reset failed */
1655 }
68ca949c
AC		 1656 if (ha->wq)
1657 flush_workqueue(ha->wq);
1658
e315cd28 1659 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
a9083016 1660 if (ha->isp_ops->abort_isp(base_vha)) {
e315cd28
AC		 1661 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1662 /* failed. schedule dpc to try */
1663 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
1664
7c3df132
SK		 1665 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1666 ql_log(ql_log_warn, vha, 0x802a,
1667 "wait for hba online failed.\n");
e315cd28 1668 goto eh_host_reset_lock;
7c3df132 1669 }
e315cd28
AC		 1670 }
1671 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
fa2a1ce5 1672 }
1da177e4 1673
e315cd28 1674 /* Waiting for command to be returned to OS.*/
4d78c973 1675 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) ==
e315cd28 1676 QLA_SUCCESS)
f4f051eb 1677 ret = SUCCESS;
1da177e4 1678
f4f051eb 1679eh_host_reset_lock:
cfb0919c 1680 ql_log(ql_log_info, vha, 0x8017,
9cb78c16 1681 "ADAPTER RESET %s nexus=%ld:%d:%llu.\n",
cfb0919c 1682 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1da177e4 1683
f4f051eb 1684 return ret;
1685}
1da177e4
LT		 1686
1687/*
1688* qla2x00_loop_reset
1689* Issue loop reset.
1690*
1691* Input:
1692* ha = adapter block pointer.
1693*
1694* Returns:
1695* 0 = success
1696*/
a4722cf2 1697int
e315cd28 1698qla2x00_loop_reset(scsi_qla_host_t *vha)
1da177e4 1699{
0c8c39af 1700 int ret;
bdf79621 1701 struct fc_port *fcport;
e315cd28 1702 struct qla_hw_data *ha = vha->hw;
1da177e4 1703
5854771e
AB		 1704 if (IS_QLAFX00(ha)) {
1705 return qlafx00_loop_reset(vha);
1706 }
1707
f4c496c1 1708 if (ql2xtargetreset == 1 && ha->flags.enable_target_reset) {
55e5ed27
AV		 1709 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1710 if (fcport->port_type != FCT_TARGET)
1711 continue;
1712
1713 ret = ha->isp_ops->target_reset(fcport, 0, 0);
1714 if (ret != QLA_SUCCESS) {
7c3df132 1715 ql_dbg(ql_dbg_taskm, vha, 0x802c,
5854771e 1716 "Bus Reset failed: Reset=%d "
7c3df132 1717 "d_id=%x.\n", ret, fcport->d_id.b24);
55e5ed27
AV		 1718 }
1719 }
1720 }
1721
8ae6d9c7 1722
6246b8a1 1723 if (ha->flags.enable_lip_full_login && !IS_CNA_CAPABLE(ha)) {
0b7e7c53
AV		 1724 atomic_set(&vha->loop_state, LOOP_DOWN);
1725 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
1726 qla2x00_mark_all_devices_lost(vha, 0);
e315cd28 1727 ret = qla2x00_full_login_lip(vha);
0c8c39af 1728 if (ret != QLA_SUCCESS) {
7c3df132
SK		 1729 ql_dbg(ql_dbg_taskm, vha, 0x802d,
1730 "full_login_lip=%d.\n", ret);
749af3d5 1731 }
0c8c39af
AV		 1732 }
1733
0d6e61bc 1734 if (ha->flags.enable_lip_reset) {
e315cd28 1735 ret = qla2x00_lip_reset(vha);
ad537689 1736 if (ret != QLA_SUCCESS)
7c3df132
SK		 1737 ql_dbg(ql_dbg_taskm, vha, 0x802e,
1738 "lip_reset failed (%d).\n", ret);
1da177e4
LT		 1739 }
1740
1da177e4 1741 /* Issue marker command only when we are going to start the I/O */
e315cd28 1742 vha->marker_needed = 1;
1da177e4 1743
0c8c39af 1744 return QLA_SUCCESS;
1da177e4
LT		 1745}
1746
c4e521b6
BVA		 1747static void qla2x00_abort_srb(struct qla_qpair *qp, srb_t *sp, const int res,
1748 unsigned long *flags)
1749 __releases(qp->qp_lock_ptr)
1750 __acquires(qp->qp_lock_ptr)
1751{
219d27d7 1752 DECLARE_COMPLETION_ONSTACK(comp);
c4e521b6
BVA		 1753 scsi_qla_host_t *vha = qp->vha;
1754 struct qla_hw_data *ha = vha->hw;
219d27d7 1755 int rval;
c4e521b6 1756
219d27d7
BVA		 1757 if (sp_get(sp))
1758 return;
1759
1760 if (sp->type == SRB_NVME_CMD || sp->type == SRB_NVME_LS ||
1761 (sp->type == SRB_SCSI_CMD && !ha->flags.eeh_busy &&
1762 !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) &&
1763 !qla2x00_isp_reg_stat(ha))) {
1764 sp->comp = &comp;
219d27d7 1765 spin_unlock_irqrestore(qp->qp_lock_ptr, *flags);
5589b08e 1766 rval = ha->isp_ops->abort_command(sp);
219d27d7
BVA		 1767
1768 switch (rval) {
1769 case QLA_SUCCESS:
1770 sp->done(sp, res);
1771 break;
1772 case QLA_FUNCTION_PARAMETER_ERROR:
1773 wait_for_completion(&comp);
1774 break;
c4e521b6 1775 }
219d27d7
BVA		 1776
1777 spin_lock_irqsave(qp->qp_lock_ptr, *flags);
1778 sp->comp = NULL;
c4e521b6 1779 }
d2d2b5a5
BVA		 1780
1781 atomic_dec(&sp->ref_count);
c4e521b6
BVA		 1782}
1783
bbead493
QT		 1784static void
1785__qla2x00_abort_all_cmds(struct qla_qpair *qp, int res)
df4bf0bb 1786{
eb023220 1787 int cnt;
df4bf0bb
AV		 1788 unsigned long flags;
1789 srb_t *sp;
bbead493 1790 scsi_qla_host_t *vha = qp->vha;
e315cd28 1791 struct qla_hw_data *ha = vha->hw;
73208dfd 1792 struct req_que *req;
c5419e26
QT		 1793 struct qla_tgt *tgt = vha->vha_tgt.qla_tgt;
1794 struct qla_tgt_cmd *cmd;
c0cb4496 1795
6a2cf8d3
BK		 1796 if (!ha->req_q_map)
1797 return;
bbead493
QT		 1798 spin_lock_irqsave(qp->qp_lock_ptr, flags);
1799 req = qp->req;
1800 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) {
1801 sp = req->outstanding_cmds[cnt];
1802 if (sp) {
1803 req->outstanding_cmds[cnt] = NULL;
6b0431d6
QT		 1804 switch (sp->cmd_type) {
1805 case TYPE_SRB:
c4e521b6 1806 qla2x00_abort_srb(qp, sp, res, &flags);
585def9b
QT		 1807 break;
1808 case TYPE_TGT_CMD:
bbead493
QT		 1809 if (!vha->hw->tgt.tgt_ops || !tgt ||
1810 qla_ini_mode_enabled(vha)) {
585def9b
QT		 1811 ql_dbg(ql_dbg_tgt_mgt, vha, 0xf003,
1812 "HOST-ABORT-HNDLR: dpc_flags=%lx. Target mode disabled\n",
1813 vha->dpc_flags);
bbead493 1814 continue;
c733ab35 1815 }
bbead493 1816 cmd = (struct qla_tgt_cmd *)sp;
aefed3e5 1817 cmd->aborted = 1;
585def9b
QT		 1818 break;
1819 case TYPE_TGT_TMCMD:
aefed3e5 1820 /* Skip task management functions. */
585def9b
QT		 1821 break;
1822 default:
1823 break;
73208dfd 1824 }
df4bf0bb
AV		 1825 }
1826 }
bbead493
QT		 1827 spin_unlock_irqrestore(qp->qp_lock_ptr, flags);
1828}
1829
1830void
1831qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res)
1832{
1833 int que;
1834 struct qla_hw_data *ha = vha->hw;
1835
26a77799
AV		 1836 /* Continue only if initialization complete. */
1837 if (!ha->base_qpair)
1838 return;
bbead493
QT		 1839 __qla2x00_abort_all_cmds(ha->base_qpair, res);
1840
26a77799
AV		 1841 if (!ha->queue_pair_map)
1842 return;
bbead493
QT		 1843 for (que = 0; que < ha->max_qpairs; que++) {
1844 if (!ha->queue_pair_map[que])
1845 continue;
1846
1847 __qla2x00_abort_all_cmds(ha->queue_pair_map[que], res);
1848 }
df4bf0bb
AV		 1849}
1850
f4f051eb 1851static int
1852qla2xxx_slave_alloc(struct scsi_device *sdev)
1da177e4 1853{
bdf79621 1854 struct fc_rport *rport = starget_to_rport(scsi_target(sdev));
1da177e4 1855
19a7b4ae 1856 if (!rport || fc_remote_port_chkready(rport))
f4f051eb 1857 return -ENXIO;
bdf79621 1858
19a7b4ae 1859 sdev->hostdata = *(fc_port_t **)rport->dd_data;
1da177e4 1860
f4f051eb 1861 return 0;
1862}
1da177e4 1863
f4f051eb 1864static int
1865qla2xxx_slave_configure(struct scsi_device *sdev)
1866{
e315cd28 1867 scsi_qla_host_t *vha = shost_priv(sdev->host);
2afa19a9 1868 struct req_que *req = vha->req;
8482e118 1869
9e522cd8
AE		 1870 if (IS_T10_PI_CAPABLE(vha->hw))
1871 blk_queue_update_dma_alignment(sdev->request_queue, 0x7);
1872
db5ed4df 1873 scsi_change_queue_depth(sdev, req->max_q_depth);
f4f051eb 1874 return 0;
1875}
1da177e4 1876
f4f051eb 1877static void
1878qla2xxx_slave_destroy(struct scsi_device *sdev)
1879{
1880 sdev->hostdata = NULL;
1da177e4
LT		 1881}
1882
1883/**
1884 * qla2x00_config_dma_addressing() - Configure OS DMA addressing method.
1885 * @ha: HA context
1886 *
1887 * At exit, the @ha's flags.enable_64bit_addressing set to indicated
1888 * supported addressing method.
1889 */
1890static void
53303c42 1891qla2x00_config_dma_addressing(struct qla_hw_data *ha)
1da177e4 1892{
7524f9b9 1893 /* Assume a 32bit DMA mask. */
1da177e4 1894 ha->flags.enable_64bit_addressing = 0;
1da177e4 1895
6a35528a 1896 if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) {
7524f9b9
AV		 1897 /* Any upper-dword bits set? */
1898 if (MSD(dma_get_required_mask(&ha->pdev->dev)) &&
6a35528a 1899 !pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(64))) {
7524f9b9 1900 /* Ok, a 64bit DMA mask is applicable. */
1da177e4 1901 ha->flags.enable_64bit_addressing = 1;
fd34f556
AV		 1902 ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64;
1903 ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64;
7524f9b9 1904 return;
1da177e4 1905 }
1da177e4 1906 }
7524f9b9 1907
284901a9
YH		 1908 dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32));
1909 pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(32));
1da177e4
LT		 1910}
1911
fd34f556 1912static void
e315cd28 1913qla2x00_enable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1914{
1915 unsigned long flags = 0;
1916 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1917
1918 spin_lock_irqsave(&ha->hardware_lock, flags);
1919 ha->interrupts_on = 1;
1920 /* enable risc and host interrupts */
1921 WRT_REG_WORD(&reg->ictrl, ICR_EN_INT | ICR_EN_RISC);
1922 RD_REG_WORD(&reg->ictrl);
1923 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1924
1925}
1926
1927static void
e315cd28 1928qla2x00_disable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1929{
1930 unsigned long flags = 0;
1931 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1932
1933 spin_lock_irqsave(&ha->hardware_lock, flags);
1934 ha->interrupts_on = 0;
1935 /* disable risc and host interrupts */
1936 WRT_REG_WORD(&reg->ictrl, 0);
1937 RD_REG_WORD(&reg->ictrl);
1938 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1939}
1940
1941static void
e315cd28 1942qla24xx_enable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1943{
1944 unsigned long flags = 0;
1945 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1946
1947 spin_lock_irqsave(&ha->hardware_lock, flags);
1948 ha->interrupts_on = 1;
1949 WRT_REG_DWORD(&reg->ictrl, ICRX_EN_RISC_INT);
1950 RD_REG_DWORD(&reg->ictrl);
1951 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1952}
1953
1954static void
e315cd28 1955qla24xx_disable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1956{
1957 unsigned long flags = 0;
1958 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1959
124f85e6
AV		 1960 if (IS_NOPOLLING_TYPE(ha))
1961 return;
fd34f556
AV		 1962 spin_lock_irqsave(&ha->hardware_lock, flags);
1963 ha->interrupts_on = 0;
1964 WRT_REG_DWORD(&reg->ictrl, 0);
1965 RD_REG_DWORD(&reg->ictrl);
1966 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1967}
1968
706f457d
GM		 1969static int
1970qla2x00_iospace_config(struct qla_hw_data *ha)
1971{
1972 resource_size_t pio;
1973 uint16_t msix;
706f457d 1974
706f457d
GM		 1975 if (pci_request_selected_regions(ha->pdev, ha->bars,
1976 QLA2XXX_DRIVER_NAME)) {
1977 ql_log_pci(ql_log_fatal, ha->pdev, 0x0011,
1978 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
1979 pci_name(ha->pdev));
1980 goto iospace_error_exit;
1981 }
1982 if (!(ha->bars & 1))
1983 goto skip_pio;
1984
1985 /* We only need PIO for Flash operations on ISP2312 v2 chips. */
1986 pio = pci_resource_start(ha->pdev, 0);
1987 if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) {
1988 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
1989 ql_log_pci(ql_log_warn, ha->pdev, 0x0012,
1990 "Invalid pci I/O region size (%s).\n",
1991 pci_name(ha->pdev));
1992 pio = 0;
1993 }
1994 } else {
1995 ql_log_pci(ql_log_warn, ha->pdev, 0x0013,
1996 "Region #0 no a PIO resource (%s).\n",
1997 pci_name(ha->pdev));
1998 pio = 0;
1999 }
2000 ha->pio_address = pio;
2001 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014,
2002 "PIO address=%llu.\n",
2003 (unsigned long long)ha->pio_address);
2004
2005skip_pio:
2006 /* Use MMIO operations for all accesses. */
2007 if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) {
2008 ql_log_pci(ql_log_fatal, ha->pdev, 0x0015,
2009 "Region #1 not an MMIO resource (%s), aborting.\n",
2010 pci_name(ha->pdev));
2011 goto iospace_error_exit;
2012 }
2013 if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) {
2014 ql_log_pci(ql_log_fatal, ha->pdev, 0x0016,
2015 "Invalid PCI mem region size (%s), aborting.\n",
2016 pci_name(ha->pdev));
2017 goto iospace_error_exit;
2018 }
2019
2020 ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN);
2021 if (!ha->iobase) {
2022 ql_log_pci(ql_log_fatal, ha->pdev, 0x0017,
2023 "Cannot remap MMIO (%s), aborting.\n",
2024 pci_name(ha->pdev));
2025 goto iospace_error_exit;
2026 }
2027
2028 /* Determine queue resources */
2029 ha->max_req_queues = ha->max_rsp_queues = 1;
f54f2cb5 2030 ha->msix_count = QLA_BASE_VECTORS;
c38d1baf
HM		 2031 if (!ql2xmqsupport || !ql2xnvmeenable ||
2032 (!IS_QLA25XX(ha) && !IS_QLA81XX(ha)))
706f457d
GM		 2033 goto mqiobase_exit;
2034
2035 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3),
2036 pci_resource_len(ha->pdev, 3));
2037 if (ha->mqiobase) {
2038 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018,
2039 "MQIO Base=%p.\n", ha->mqiobase);
2040 /* Read MSIX vector size of the board */
2041 pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix);
d7459527 2042 ha->msix_count = msix + 1;
706f457d 2043 /* Max queues are bounded by available msix vectors */
d7459527
MH		 2044 /* MB interrupt uses 1 vector */
2045 ha->max_req_queues = ha->msix_count - 1;
2046 ha->max_rsp_queues = ha->max_req_queues;
2047 /* Queue pairs is the max value minus the base queue pair */
2048 ha->max_qpairs = ha->max_rsp_queues - 1;
2049 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0188,
2050 "Max no of queues pairs: %d.\n", ha->max_qpairs);
2051
706f457d 2052 ql_log_pci(ql_log_info, ha->pdev, 0x001a,
d7459527 2053 "MSI-X vector count: %d.\n", ha->msix_count);
706f457d
GM		 2054 } else
2055 ql_log_pci(ql_log_info, ha->pdev, 0x001b,
2056 "BAR 3 not enabled.\n");
2057
2058mqiobase_exit:
706f457d 2059 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c,
f54f2cb5 2060 "MSIX Count: %d.\n", ha->msix_count);
706f457d
GM		 2061 return (0);
2062
2063iospace_error_exit:
2064 return (-ENOMEM);
2065}
2066
2067
6246b8a1
GM		 2068static int
2069qla83xx_iospace_config(struct qla_hw_data *ha)
2070{
2071 uint16_t msix;
6246b8a1
GM		 2072
2073 if (pci_request_selected_regions(ha->pdev, ha->bars,
2074 QLA2XXX_DRIVER_NAME)) {
2075 ql_log_pci(ql_log_fatal, ha->pdev, 0x0117,
2076 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
2077 pci_name(ha->pdev));
2078
2079 goto iospace_error_exit;
2080 }
2081
2082 /* Use MMIO operations for all accesses. */
2083 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) {
2084 ql_log_pci(ql_log_warn, ha->pdev, 0x0118,
2085 "Invalid pci I/O region size (%s).\n",
2086 pci_name(ha->pdev));
2087 goto iospace_error_exit;
2088 }
2089 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
2090 ql_log_pci(ql_log_warn, ha->pdev, 0x0119,
2091 "Invalid PCI mem region size (%s), aborting\n",
2092 pci_name(ha->pdev));
2093 goto iospace_error_exit;
2094 }
2095
2096 ha->iobase = ioremap(pci_resource_start(ha->pdev, 0), MIN_IOBASE_LEN);
2097 if (!ha->iobase) {
2098 ql_log_pci(ql_log_fatal, ha->pdev, 0x011a,
2099 "Cannot remap MMIO (%s), aborting.\n",
2100 pci_name(ha->pdev));
2101 goto iospace_error_exit;
2102 }
2103
2104 /* 64bit PCI BAR - BAR2 will correspoond to region 4 */
2105 /* 83XX 26XX always use MQ type access for queues
2106 * - mbar 2, a.k.a region 4 */
2107 ha->max_req_queues = ha->max_rsp_queues = 1;
f54f2cb5 2108 ha->msix_count = QLA_BASE_VECTORS;
6246b8a1
GM		 2109 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 4),
2110 pci_resource_len(ha->pdev, 4));
2111
2112 if (!ha->mqiobase) {
2113 ql_log_pci(ql_log_fatal, ha->pdev, 0x011d,
2114 "BAR2/region4 not enabled\n");
2115 goto mqiobase_exit;
2116 }
2117
2118 ha->msixbase = ioremap(pci_resource_start(ha->pdev, 2),
2119 pci_resource_len(ha->pdev, 2));
2120 if (ha->msixbase) {
2121 /* Read MSIX vector size of the board */
2122 pci_read_config_word(ha->pdev,
2123 QLA_83XX_PCI_MSIX_CONTROL, &msix);
e326d22a 2124 ha->msix_count = (msix & PCI_MSIX_FLAGS_QSIZE) + 1;
093df737
QT		 2125 /*
2126 * By default, driver uses at least two msix vectors
2127 * (default & rspq)
2128 */
c38d1baf 2129 if (ql2xmqsupport || ql2xnvmeenable) {
d7459527
MH		 2130 /* MB interrupt uses 1 vector */
2131 ha->max_req_queues = ha->msix_count - 1;
093df737
QT		 2132
2133 /* ATIOQ needs 1 vector. That's 1 less QPair */
2134 if (QLA_TGT_MODE_ENABLED())
2135 ha->max_req_queues--;
2136
d0d2c68b
MH		 2137 ha->max_rsp_queues = ha->max_req_queues;
2138
d7459527
MH		 2139 /* Queue pairs is the max value minus
2140 * the base queue pair */
2141 ha->max_qpairs = ha->max_req_queues - 1;
83548fe2 2142 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x00e3,
d7459527 2143 "Max no of queues pairs: %d.\n", ha->max_qpairs);
6246b8a1
GM		 2144 }
2145 ql_log_pci(ql_log_info, ha->pdev, 0x011c,
d7459527 2146 "MSI-X vector count: %d.\n", ha->msix_count);
6246b8a1
GM		 2147 } else
2148 ql_log_pci(ql_log_info, ha->pdev, 0x011e,
2149 "BAR 1 not enabled.\n");
2150
2151mqiobase_exit:
6246b8a1 2152 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011f,
f54f2cb5 2153 "MSIX Count: %d.\n", ha->msix_count);
6246b8a1
GM		 2154 return 0;
2155
2156iospace_error_exit:
2157 return -ENOMEM;
2158}
2159
fd34f556
AV		 2160static struct isp_operations qla2100_isp_ops = {
2161 .pci_config = qla2100_pci_config,
2162 .reset_chip = qla2x00_reset_chip,
2163 .chip_diag = qla2x00_chip_diag,
2164 .config_rings = qla2x00_config_rings,
2165 .reset_adapter = qla2x00_reset_adapter,
2166 .nvram_config = qla2x00_nvram_config,
2167 .update_fw_options = qla2x00_update_fw_options,
2168 .load_risc = qla2x00_load_risc,
2169 .pci_info_str = qla2x00_pci_info_str,
2170 .fw_version_str = qla2x00_fw_version_str,
2171 .intr_handler = qla2100_intr_handler,
2172 .enable_intrs = qla2x00_enable_intrs,
2173 .disable_intrs = qla2x00_disable_intrs,
2174 .abort_command = qla2x00_abort_command,
523ec773
AV		 2175 .target_reset = qla2x00_abort_target,
2176 .lun_reset = qla2x00_lun_reset,
fd34f556
AV		 2177 .fabric_login = qla2x00_login_fabric,
2178 .fabric_logout = qla2x00_fabric_logout,
2179 .calc_req_entries = qla2x00_calc_iocbs_32,
2180 .build_iocbs = qla2x00_build_scsi_iocbs_32,
2181 .prep_ms_iocb = qla2x00_prep_ms_iocb,
2182 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
2183 .read_nvram = qla2x00_read_nvram_data,
2184 .write_nvram = qla2x00_write_nvram_data,
2185 .fw_dump = qla2100_fw_dump,
2186 .beacon_on = NULL,
2187 .beacon_off = NULL,
2188 .beacon_blink = NULL,
2189 .read_optrom = qla2x00_read_optrom_data,
2190 .write_optrom = qla2x00_write_optrom_data,
2191 .get_flash_version = qla2x00_get_flash_version,
e315cd28 2192 .start_scsi = qla2x00_start_scsi,
d7459527 2193 .start_scsi_mq = NULL,
a9083016 2194 .abort_isp = qla2x00_abort_isp,
706f457d 2195 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2196 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 2197};
2198
2199static struct isp_operations qla2300_isp_ops = {
2200 .pci_config = qla2300_pci_config,
2201 .reset_chip = qla2x00_reset_chip,
2202 .chip_diag = qla2x00_chip_diag,
2203 .config_rings = qla2x00_config_rings,
2204 .reset_adapter = qla2x00_reset_adapter,
2205 .nvram_config = qla2x00_nvram_config,
2206 .update_fw_options = qla2x00_update_fw_options,
2207 .load_risc = qla2x00_load_risc,
2208 .pci_info_str = qla2x00_pci_info_str,
2209 .fw_version_str = qla2x00_fw_version_str,
2210 .intr_handler = qla2300_intr_handler,
2211 .enable_intrs = qla2x00_enable_intrs,
2212 .disable_intrs = qla2x00_disable_intrs,
2213 .abort_command = qla2x00_abort_command,
523ec773
AV		 2214 .target_reset = qla2x00_abort_target,
2215 .lun_reset = qla2x00_lun_reset,
fd34f556
AV		 2216 .fabric_login = qla2x00_login_fabric,
2217 .fabric_logout = qla2x00_fabric_logout,
2218 .calc_req_entries = qla2x00_calc_iocbs_32,
2219 .build_iocbs = qla2x00_build_scsi_iocbs_32,
2220 .prep_ms_iocb = qla2x00_prep_ms_iocb,
2221 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
2222 .read_nvram = qla2x00_read_nvram_data,
2223 .write_nvram = qla2x00_write_nvram_data,
2224 .fw_dump = qla2300_fw_dump,
2225 .beacon_on = qla2x00_beacon_on,
2226 .beacon_off = qla2x00_beacon_off,
2227 .beacon_blink = qla2x00_beacon_blink,
2228 .read_optrom = qla2x00_read_optrom_data,
2229 .write_optrom = qla2x00_write_optrom_data,
2230 .get_flash_version = qla2x00_get_flash_version,
e315cd28 2231 .start_scsi = qla2x00_start_scsi,
d7459527 2232 .start_scsi_mq = NULL,
a9083016 2233 .abort_isp = qla2x00_abort_isp,
7ec0effd 2234 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2235 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 2236};
2237
2238static struct isp_operations qla24xx_isp_ops = {
2239 .pci_config = qla24xx_pci_config,
2240 .reset_chip = qla24xx_reset_chip,
2241 .chip_diag = qla24xx_chip_diag,
2242 .config_rings = qla24xx_config_rings,
2243 .reset_adapter = qla24xx_reset_adapter,
2244 .nvram_config = qla24xx_nvram_config,
2245 .update_fw_options = qla24xx_update_fw_options,
2246 .load_risc = qla24xx_load_risc,
2247 .pci_info_str = qla24xx_pci_info_str,
2248 .fw_version_str = qla24xx_fw_version_str,
2249 .intr_handler = qla24xx_intr_handler,
2250 .enable_intrs = qla24xx_enable_intrs,
2251 .disable_intrs = qla24xx_disable_intrs,
2252 .abort_command = qla24xx_abort_command,
523ec773
AV		 2253 .target_reset = qla24xx_abort_target,
2254 .lun_reset = qla24xx_lun_reset,
fd34f556
AV		 2255 .fabric_login = qla24xx_login_fabric,
2256 .fabric_logout = qla24xx_fabric_logout,
2257 .calc_req_entries = NULL,
2258 .build_iocbs = NULL,
2259 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2260 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2261 .read_nvram = qla24xx_read_nvram_data,
2262 .write_nvram = qla24xx_write_nvram_data,
2263 .fw_dump = qla24xx_fw_dump,
2264 .beacon_on = qla24xx_beacon_on,
2265 .beacon_off = qla24xx_beacon_off,
2266 .beacon_blink = qla24xx_beacon_blink,
2267 .read_optrom = qla24xx_read_optrom_data,
2268 .write_optrom = qla24xx_write_optrom_data,
2269 .get_flash_version = qla24xx_get_flash_version,
e315cd28 2270 .start_scsi = qla24xx_start_scsi,
d7459527 2271 .start_scsi_mq = NULL,
a9083016 2272 .abort_isp = qla2x00_abort_isp,
7ec0effd 2273 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2274 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 2275};
2276
c3a2f0df
AV		 2277static struct isp_operations qla25xx_isp_ops = {
2278 .pci_config = qla25xx_pci_config,
2279 .reset_chip = qla24xx_reset_chip,
2280 .chip_diag = qla24xx_chip_diag,
2281 .config_rings = qla24xx_config_rings,
2282 .reset_adapter = qla24xx_reset_adapter,
2283 .nvram_config = qla24xx_nvram_config,
2284 .update_fw_options = qla24xx_update_fw_options,
2285 .load_risc = qla24xx_load_risc,
2286 .pci_info_str = qla24xx_pci_info_str,
2287 .fw_version_str = qla24xx_fw_version_str,
2288 .intr_handler = qla24xx_intr_handler,
2289 .enable_intrs = qla24xx_enable_intrs,
2290 .disable_intrs = qla24xx_disable_intrs,
2291 .abort_command = qla24xx_abort_command,
523ec773
AV		 2292 .target_reset = qla24xx_abort_target,
2293 .lun_reset = qla24xx_lun_reset,
c3a2f0df
AV		 2294 .fabric_login = qla24xx_login_fabric,
2295 .fabric_logout = qla24xx_fabric_logout,
2296 .calc_req_entries = NULL,
2297 .build_iocbs = NULL,
2298 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2299 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2300 .read_nvram = qla25xx_read_nvram_data,
2301 .write_nvram = qla25xx_write_nvram_data,
2302 .fw_dump = qla25xx_fw_dump,
2303 .beacon_on = qla24xx_beacon_on,
2304 .beacon_off = qla24xx_beacon_off,
2305 .beacon_blink = qla24xx_beacon_blink,
338c9161 2306 .read_optrom = qla25xx_read_optrom_data,
c3a2f0df
AV		 2307 .write_optrom = qla24xx_write_optrom_data,
2308 .get_flash_version = qla24xx_get_flash_version,
bad75002 2309 .start_scsi = qla24xx_dif_start_scsi,
d7459527 2310 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
a9083016 2311 .abort_isp = qla2x00_abort_isp,
7ec0effd 2312 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2313 .initialize_adapter = qla2x00_initialize_adapter,
c3a2f0df
AV		 2314};
2315
3a03eb79
AV		 2316static struct isp_operations qla81xx_isp_ops = {
2317 .pci_config = qla25xx_pci_config,
2318 .reset_chip = qla24xx_reset_chip,
2319 .chip_diag = qla24xx_chip_diag,
2320 .config_rings = qla24xx_config_rings,
2321 .reset_adapter = qla24xx_reset_adapter,
2322 .nvram_config = qla81xx_nvram_config,
2323 .update_fw_options = qla81xx_update_fw_options,
eaac30be 2324 .load_risc = qla81xx_load_risc,
3a03eb79
AV		 2325 .pci_info_str = qla24xx_pci_info_str,
2326 .fw_version_str = qla24xx_fw_version_str,
2327 .intr_handler = qla24xx_intr_handler,
2328 .enable_intrs = qla24xx_enable_intrs,
2329 .disable_intrs = qla24xx_disable_intrs,
2330 .abort_command = qla24xx_abort_command,
2331 .target_reset = qla24xx_abort_target,
2332 .lun_reset = qla24xx_lun_reset,
2333 .fabric_login = qla24xx_login_fabric,
2334 .fabric_logout = qla24xx_fabric_logout,
2335 .calc_req_entries = NULL,
2336 .build_iocbs = NULL,
2337 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2338 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
3d79038f
AV		 2339 .read_nvram = NULL,
2340 .write_nvram = NULL,
3a03eb79
AV		 2341 .fw_dump = qla81xx_fw_dump,
2342 .beacon_on = qla24xx_beacon_on,
2343 .beacon_off = qla24xx_beacon_off,
6246b8a1 2344 .beacon_blink = qla83xx_beacon_blink,
3a03eb79
AV		 2345 .read_optrom = qla25xx_read_optrom_data,
2346 .write_optrom = qla24xx_write_optrom_data,
2347 .get_flash_version = qla24xx_get_flash_version,
ba77ef53 2348 .start_scsi = qla24xx_dif_start_scsi,
d7459527 2349 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
a9083016 2350 .abort_isp = qla2x00_abort_isp,
7ec0effd 2351 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2352 .initialize_adapter = qla2x00_initialize_adapter,
a9083016
GM		 2353};
2354
2355static struct isp_operations qla82xx_isp_ops = {
2356 .pci_config = qla82xx_pci_config,
2357 .reset_chip = qla82xx_reset_chip,
2358 .chip_diag = qla24xx_chip_diag,
2359 .config_rings = qla82xx_config_rings,
2360 .reset_adapter = qla24xx_reset_adapter,
2361 .nvram_config = qla81xx_nvram_config,
2362 .update_fw_options = qla24xx_update_fw_options,
2363 .load_risc = qla82xx_load_risc,
9d55ca66 2364 .pci_info_str = qla24xx_pci_info_str,
a9083016
GM		 2365 .fw_version_str = qla24xx_fw_version_str,
2366 .intr_handler = qla82xx_intr_handler,
2367 .enable_intrs = qla82xx_enable_intrs,
2368 .disable_intrs = qla82xx_disable_intrs,
2369 .abort_command = qla24xx_abort_command,
2370 .target_reset = qla24xx_abort_target,
2371 .lun_reset = qla24xx_lun_reset,
2372 .fabric_login = qla24xx_login_fabric,
2373 .fabric_logout = qla24xx_fabric_logout,
2374 .calc_req_entries = NULL,
2375 .build_iocbs = NULL,
2376 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2377 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2378 .read_nvram = qla24xx_read_nvram_data,
2379 .write_nvram = qla24xx_write_nvram_data,
a1b23c5a 2380 .fw_dump = qla82xx_fw_dump,
999916dc
SK		 2381 .beacon_on = qla82xx_beacon_on,
2382 .beacon_off = qla82xx_beacon_off,
2383 .beacon_blink = NULL,
a9083016
GM		 2384 .read_optrom = qla82xx_read_optrom_data,
2385 .write_optrom = qla82xx_write_optrom_data,
7ec0effd 2386 .get_flash_version = qla82xx_get_flash_version,
a9083016 2387 .start_scsi = qla82xx_start_scsi,
d7459527 2388 .start_scsi_mq = NULL,
a9083016 2389 .abort_isp = qla82xx_abort_isp,
706f457d 2390 .iospace_config = qla82xx_iospace_config,
8ae6d9c7 2391 .initialize_adapter = qla2x00_initialize_adapter,
3a03eb79
AV		 2392};
2393
7ec0effd
AD		 2394static struct isp_operations qla8044_isp_ops = {
2395 .pci_config = qla82xx_pci_config,
2396 .reset_chip = qla82xx_reset_chip,
2397 .chip_diag = qla24xx_chip_diag,
2398 .config_rings = qla82xx_config_rings,
2399 .reset_adapter = qla24xx_reset_adapter,
2400 .nvram_config = qla81xx_nvram_config,
2401 .update_fw_options = qla24xx_update_fw_options,
2402 .load_risc = qla82xx_load_risc,
2403 .pci_info_str = qla24xx_pci_info_str,
2404 .fw_version_str = qla24xx_fw_version_str,
2405 .intr_handler = qla8044_intr_handler,
2406 .enable_intrs = qla82xx_enable_intrs,
2407 .disable_intrs = qla82xx_disable_intrs,
2408 .abort_command = qla24xx_abort_command,
2409 .target_reset = qla24xx_abort_target,
2410 .lun_reset = qla24xx_lun_reset,
2411 .fabric_login = qla24xx_login_fabric,
2412 .fabric_logout = qla24xx_fabric_logout,
2413 .calc_req_entries = NULL,
2414 .build_iocbs = NULL,
2415 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2416 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2417 .read_nvram = NULL,
2418 .write_nvram = NULL,
a1b23c5a 2419 .fw_dump = qla8044_fw_dump,
7ec0effd
AD		 2420 .beacon_on = qla82xx_beacon_on,
2421 .beacon_off = qla82xx_beacon_off,
2422 .beacon_blink = NULL,
888e639d 2423 .read_optrom = qla8044_read_optrom_data,
7ec0effd
AD		 2424 .write_optrom = qla8044_write_optrom_data,
2425 .get_flash_version = qla82xx_get_flash_version,
2426 .start_scsi = qla82xx_start_scsi,
d7459527 2427 .start_scsi_mq = NULL,
7ec0effd
AD		 2428 .abort_isp = qla8044_abort_isp,
2429 .iospace_config = qla82xx_iospace_config,
2430 .initialize_adapter = qla2x00_initialize_adapter,
2431};
2432
6246b8a1
GM		 2433static struct isp_operations qla83xx_isp_ops = {
2434 .pci_config = qla25xx_pci_config,
2435 .reset_chip = qla24xx_reset_chip,
2436 .chip_diag = qla24xx_chip_diag,
2437 .config_rings = qla24xx_config_rings,
2438 .reset_adapter = qla24xx_reset_adapter,
2439 .nvram_config = qla81xx_nvram_config,
2440 .update_fw_options = qla81xx_update_fw_options,
2441 .load_risc = qla81xx_load_risc,
2442 .pci_info_str = qla24xx_pci_info_str,
2443 .fw_version_str = qla24xx_fw_version_str,
2444 .intr_handler = qla24xx_intr_handler,
2445 .enable_intrs = qla24xx_enable_intrs,
2446 .disable_intrs = qla24xx_disable_intrs,
2447 .abort_command = qla24xx_abort_command,
2448 .target_reset = qla24xx_abort_target,
2449 .lun_reset = qla24xx_lun_reset,
2450 .fabric_login = qla24xx_login_fabric,
2451 .fabric_logout = qla24xx_fabric_logout,
2452 .calc_req_entries = NULL,
2453 .build_iocbs = NULL,
2454 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2455 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2456 .read_nvram = NULL,
2457 .write_nvram = NULL,
2458 .fw_dump = qla83xx_fw_dump,
2459 .beacon_on = qla24xx_beacon_on,
2460 .beacon_off = qla24xx_beacon_off,
2461 .beacon_blink = qla83xx_beacon_blink,
2462 .read_optrom = qla25xx_read_optrom_data,
2463 .write_optrom = qla24xx_write_optrom_data,
2464 .get_flash_version = qla24xx_get_flash_version,
2465 .start_scsi = qla24xx_dif_start_scsi,
d7459527 2466 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
6246b8a1
GM		 2467 .abort_isp = qla2x00_abort_isp,
2468 .iospace_config = qla83xx_iospace_config,
8ae6d9c7
GM		 2469 .initialize_adapter = qla2x00_initialize_adapter,
2470};
2471
2472static struct isp_operations qlafx00_isp_ops = {
2473 .pci_config = qlafx00_pci_config,
2474 .reset_chip = qlafx00_soft_reset,
2475 .chip_diag = qlafx00_chip_diag,
2476 .config_rings = qlafx00_config_rings,
2477 .reset_adapter = qlafx00_soft_reset,
2478 .nvram_config = NULL,
2479 .update_fw_options = NULL,
2480 .load_risc = NULL,
2481 .pci_info_str = qlafx00_pci_info_str,
2482 .fw_version_str = qlafx00_fw_version_str,
2483 .intr_handler = qlafx00_intr_handler,
2484 .enable_intrs = qlafx00_enable_intrs,
2485 .disable_intrs = qlafx00_disable_intrs,
4440e46d 2486 .abort_command = qla24xx_async_abort_command,
8ae6d9c7
GM		 2487 .target_reset = qlafx00_abort_target,
2488 .lun_reset = qlafx00_lun_reset,
2489 .fabric_login = NULL,
2490 .fabric_logout = NULL,
2491 .calc_req_entries = NULL,
2492 .build_iocbs = NULL,
2493 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2494 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2495 .read_nvram = qla24xx_read_nvram_data,
2496 .write_nvram = qla24xx_write_nvram_data,
2497 .fw_dump = NULL,
2498 .beacon_on = qla24xx_beacon_on,
2499 .beacon_off = qla24xx_beacon_off,
2500 .beacon_blink = NULL,
2501 .read_optrom = qla24xx_read_optrom_data,
2502 .write_optrom = qla24xx_write_optrom_data,
2503 .get_flash_version = qla24xx_get_flash_version,
2504 .start_scsi = qlafx00_start_scsi,
d7459527 2505 .start_scsi_mq = NULL,
8ae6d9c7
GM		 2506 .abort_isp = qlafx00_abort_isp,
2507 .iospace_config = qlafx00_iospace_config,
2508 .initialize_adapter = qlafx00_initialize_adapter,
6246b8a1
GM		 2509};
2510
f73cb695
CD		 2511static struct isp_operations qla27xx_isp_ops = {
2512 .pci_config = qla25xx_pci_config,
2513 .reset_chip = qla24xx_reset_chip,
2514 .chip_diag = qla24xx_chip_diag,
2515 .config_rings = qla24xx_config_rings,
2516 .reset_adapter = qla24xx_reset_adapter,
2517 .nvram_config = qla81xx_nvram_config,
a36f1443 2518 .update_fw_options = qla24xx_update_fw_options,
f73cb695
CD		 2519 .load_risc = qla81xx_load_risc,
2520 .pci_info_str = qla24xx_pci_info_str,
2521 .fw_version_str = qla24xx_fw_version_str,
2522 .intr_handler = qla24xx_intr_handler,
2523 .enable_intrs = qla24xx_enable_intrs,
2524 .disable_intrs = qla24xx_disable_intrs,
2525 .abort_command = qla24xx_abort_command,
2526 .target_reset = qla24xx_abort_target,
2527 .lun_reset = qla24xx_lun_reset,
2528 .fabric_login = qla24xx_login_fabric,
2529 .fabric_logout = qla24xx_fabric_logout,
2530 .calc_req_entries = NULL,
2531 .build_iocbs = NULL,
2532 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2533 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2534 .read_nvram = NULL,
2535 .write_nvram = NULL,
2536 .fw_dump = qla27xx_fwdump,
2537 .beacon_on = qla24xx_beacon_on,
2538 .beacon_off = qla24xx_beacon_off,
2539 .beacon_blink = qla83xx_beacon_blink,
2540 .read_optrom = qla25xx_read_optrom_data,
2541 .write_optrom = qla24xx_write_optrom_data,
2542 .get_flash_version = qla24xx_get_flash_version,
2543 .start_scsi = qla24xx_dif_start_scsi,
d7459527 2544 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
f73cb695
CD		 2545 .abort_isp = qla2x00_abort_isp,
2546 .iospace_config = qla83xx_iospace_config,
2547 .initialize_adapter = qla2x00_initialize_adapter,
2548};
2549
ea5b6382 2550static inline void
e315cd28 2551qla2x00_set_isp_flags(struct qla_hw_data *ha)
ea5b6382 2552{
2553 ha->device_type = DT_EXTENDED_IDS;
2554 switch (ha->pdev->device) {
2555 case PCI_DEVICE_ID_QLOGIC_ISP2100:
9e052e2d 2556 ha->isp_type |= DT_ISP2100;
ea5b6382 2557 ha->device_type &= ~DT_EXTENDED_IDS;
441d1072 2558 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
ea5b6382 2559 break;
2560 case PCI_DEVICE_ID_QLOGIC_ISP2200:
9e052e2d 2561 ha->isp_type |= DT_ISP2200;
ea5b6382 2562 ha->device_type &= ~DT_EXTENDED_IDS;
441d1072 2563 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
ea5b6382 2564 break;
2565 case PCI_DEVICE_ID_QLOGIC_ISP2300:
9e052e2d 2566 ha->isp_type |= DT_ISP2300;
4a59f71d 2567 ha->device_type |= DT_ZIO_SUPPORTED;
441d1072 2568 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 2569 break;
2570 case PCI_DEVICE_ID_QLOGIC_ISP2312:
9e052e2d 2571 ha->isp_type |= DT_ISP2312;
4a59f71d 2572 ha->device_type |= DT_ZIO_SUPPORTED;
441d1072 2573 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 2574 break;
2575 case PCI_DEVICE_ID_QLOGIC_ISP2322:
9e052e2d 2576 ha->isp_type |= DT_ISP2322;
4a59f71d 2577 ha->device_type |= DT_ZIO_SUPPORTED;
ea5b6382 2578 if (ha->pdev->subsystem_vendor == 0x1028 &&
2579 ha->pdev->subsystem_device == 0x0170)
2580 ha->device_type |= DT_OEM_001;
441d1072 2581 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 2582 break;
2583 case PCI_DEVICE_ID_QLOGIC_ISP6312:
9e052e2d 2584 ha->isp_type |= DT_ISP6312;
441d1072 2585 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 2586 break;
2587 case PCI_DEVICE_ID_QLOGIC_ISP6322:
9e052e2d 2588 ha->isp_type |= DT_ISP6322;
441d1072 2589 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 2590 break;
2591 case PCI_DEVICE_ID_QLOGIC_ISP2422:
9e052e2d 2592 ha->isp_type |= DT_ISP2422;
4a59f71d 2593 ha->device_type |= DT_ZIO_SUPPORTED;
e428924c 2594 ha->device_type |= DT_FWI2;
c76f2c01 2595 ha->device_type |= DT_IIDMA;
441d1072 2596 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2597 break;
2598 case PCI_DEVICE_ID_QLOGIC_ISP2432:
9e052e2d 2599 ha->isp_type |= DT_ISP2432;
4a59f71d 2600 ha->device_type |= DT_ZIO_SUPPORTED;
e428924c 2601 ha->device_type |= DT_FWI2;
c76f2c01 2602 ha->device_type |= DT_IIDMA;
441d1072 2603 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2604 break;
4d4df193 2605 case PCI_DEVICE_ID_QLOGIC_ISP8432:
9e052e2d 2606 ha->isp_type |= DT_ISP8432;
4d4df193
HK		 2607 ha->device_type |= DT_ZIO_SUPPORTED;
2608 ha->device_type |= DT_FWI2;
2609 ha->device_type |= DT_IIDMA;
2610 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2611 break;
044cc6c8 2612 case PCI_DEVICE_ID_QLOGIC_ISP5422:
9e052e2d 2613 ha->isp_type |= DT_ISP5422;
e428924c 2614 ha->device_type |= DT_FWI2;
441d1072 2615 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2616 break;
044cc6c8 2617 case PCI_DEVICE_ID_QLOGIC_ISP5432:
9e052e2d 2618 ha->isp_type |= DT_ISP5432;
e428924c 2619 ha->device_type |= DT_FWI2;
441d1072 2620 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2621 break;
c3a2f0df 2622 case PCI_DEVICE_ID_QLOGIC_ISP2532:
9e052e2d 2623 ha->isp_type |= DT_ISP2532;
c3a2f0df
AV		 2624 ha->device_type |= DT_ZIO_SUPPORTED;
2625 ha->device_type |= DT_FWI2;
2626 ha->device_type |= DT_IIDMA;
441d1072 2627 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2628 break;
3a03eb79 2629 case PCI_DEVICE_ID_QLOGIC_ISP8001:
9e052e2d 2630 ha->isp_type |= DT_ISP8001;
3a03eb79
AV		 2631 ha->device_type |= DT_ZIO_SUPPORTED;
2632 ha->device_type |= DT_FWI2;
2633 ha->device_type |= DT_IIDMA;
2634 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2635 break;
a9083016 2636 case PCI_DEVICE_ID_QLOGIC_ISP8021:
9e052e2d 2637 ha->isp_type |= DT_ISP8021;
a9083016
GM		 2638 ha->device_type |= DT_ZIO_SUPPORTED;
2639 ha->device_type |= DT_FWI2;
2640 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2641 /* Initialize 82XX ISP flags */
2642 qla82xx_init_flags(ha);
2643 break;
7ec0effd 2644 case PCI_DEVICE_ID_QLOGIC_ISP8044:
9e052e2d 2645 ha->isp_type |= DT_ISP8044;
7ec0effd
AD		 2646 ha->device_type |= DT_ZIO_SUPPORTED;
2647 ha->device_type |= DT_FWI2;
2648 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2649 /* Initialize 82XX ISP flags */
2650 qla82xx_init_flags(ha);
2651 break;
6246b8a1 2652 case PCI_DEVICE_ID_QLOGIC_ISP2031:
9e052e2d 2653 ha->isp_type |= DT_ISP2031;
6246b8a1
GM		 2654 ha->device_type |= DT_ZIO_SUPPORTED;
2655 ha->device_type |= DT_FWI2;
2656 ha->device_type |= DT_IIDMA;
2657 ha->device_type |= DT_T10_PI;
2658 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2659 break;
2660 case PCI_DEVICE_ID_QLOGIC_ISP8031:
9e052e2d 2661 ha->isp_type |= DT_ISP8031;
6246b8a1
GM		 2662 ha->device_type |= DT_ZIO_SUPPORTED;
2663 ha->device_type |= DT_FWI2;
2664 ha->device_type |= DT_IIDMA;
2665 ha->device_type |= DT_T10_PI;
2666 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2667 break;
8ae6d9c7 2668 case PCI_DEVICE_ID_QLOGIC_ISPF001:
9e052e2d 2669 ha->isp_type |= DT_ISPFX00;
8ae6d9c7 2670 break;
f73cb695 2671 case PCI_DEVICE_ID_QLOGIC_ISP2071:
9e052e2d 2672 ha->isp_type |= DT_ISP2071;
f73cb695
CD		 2673 ha->device_type |= DT_ZIO_SUPPORTED;
2674 ha->device_type |= DT_FWI2;
2675 ha->device_type |= DT_IIDMA;
8ce3f570 2676 ha->device_type |= DT_T10_PI;
f73cb695
CD		 2677 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2678 break;
2c5bbbb2 2679 case PCI_DEVICE_ID_QLOGIC_ISP2271:
9e052e2d 2680 ha->isp_type |= DT_ISP2271;
2c5bbbb2
JC		 2681 ha->device_type |= DT_ZIO_SUPPORTED;
2682 ha->device_type |= DT_FWI2;
2683 ha->device_type |= DT_IIDMA;
8ce3f570 2684 ha->device_type |= DT_T10_PI;
2c5bbbb2
JC		 2685 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2686 break;
2b48992f 2687 case PCI_DEVICE_ID_QLOGIC_ISP2261:
9e052e2d 2688 ha->isp_type |= DT_ISP2261;
2b48992f
SC		 2689 ha->device_type |= DT_ZIO_SUPPORTED;
2690 ha->device_type |= DT_FWI2;
2691 ha->device_type |= DT_IIDMA;
8ce3f570 2692 ha->device_type |= DT_T10_PI;
2b48992f
SC		 2693 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2694 break;
ecc89f25
JC		 2695 case PCI_DEVICE_ID_QLOGIC_ISP2081:
2696 case PCI_DEVICE_ID_QLOGIC_ISP2089:
2697 ha->isp_type |= DT_ISP2081;
2698 ha->device_type |= DT_ZIO_SUPPORTED;
2699 ha->device_type |= DT_FWI2;
2700 ha->device_type |= DT_IIDMA;
2701 ha->device_type |= DT_T10_PI;
2702 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2703 break;
2704 case PCI_DEVICE_ID_QLOGIC_ISP2281:
2705 case PCI_DEVICE_ID_QLOGIC_ISP2289:
2706 ha->isp_type |= DT_ISP2281;
2707 ha->device_type |= DT_ZIO_SUPPORTED;
2708 ha->device_type |= DT_FWI2;
2709 ha->device_type |= DT_IIDMA;
2710 ha->device_type |= DT_T10_PI;
2711 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2712 break;
ea5b6382 2713 }
e5b68a61 2714
a9083016 2715 if (IS_QLA82XX(ha))
43a9c38b 2716 ha->port_no = ha->portnum & 1;
f73cb695 2717 else {
a9083016
GM		 2718 /* Get adapter physical port no from interrupt pin register. */
2719 pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no);
ecc89f25
JC		 2720 if (IS_QLA25XX(ha) || IS_QLA2031(ha) ||
2721 IS_QLA27XX(ha) || IS_QLA28XX(ha))
f73cb695
CD		 2722 ha->port_no--;
2723 else
2724 ha->port_no = !(ha->port_no & 1);
2725 }
a9083016 2726
7c3df132 2727 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b,
d8424f68 2728 "device_type=0x%x port=%d fw_srisc_address=0x%x.\n",
f73cb695 2729 ha->device_type, ha->port_no, ha->fw_srisc_address);
ea5b6382 2730}
2731
1e99e33a
AV		 2732static void
2733qla2xxx_scan_start(struct Scsi_Host *shost)
2734{
e315cd28 2735 scsi_qla_host_t *vha = shost_priv(shost);
1e99e33a 2736
cbc8eb67
AV		 2737 if (vha->hw->flags.running_gold_fw)
2738 return;
2739
e315cd28
AC		 2740 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
2741 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
2742 set_bit(RSCN_UPDATE, &vha->dpc_flags);
2743 set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags);
1e99e33a
AV		 2744}
2745
2746static int
2747qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time)
2748{
e315cd28 2749 scsi_qla_host_t *vha = shost_priv(shost);
1e99e33a 2750
a5dd506e
BK		 2751 if (test_bit(UNLOADING, &vha->dpc_flags))
2752 return 1;
e315cd28 2753 if (!vha->host)
1e99e33a 2754 return 1;
e315cd28 2755 if (time > vha->hw->loop_reset_delay * HZ)
1e99e33a
AV		 2756 return 1;
2757
e315cd28 2758 return atomic_read(&vha->loop_state) == LOOP_READY;
1e99e33a
AV		 2759}
2760
ec7193e2
QT		 2761static void qla2x00_iocb_work_fn(struct work_struct *work)
2762{
2763 struct scsi_qla_host *vha = container_of(work,
2764 struct scsi_qla_host, iocb_work);
9b3e0f4d
QT		 2765 struct qla_hw_data *ha = vha->hw;
2766 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
0aca7784 2767 int i = 2;
9b3e0f4d
QT		 2768 unsigned long flags;
2769
2770 if (test_bit(UNLOADING, &base_vha->dpc_flags))
2771 return;
ec7193e2 2772
9b3e0f4d 2773 while (!list_empty(&vha->work_list) && i > 0) {
ec7193e2 2774 qla2x00_do_work(vha);
9b3e0f4d 2775 i--;
ec7193e2 2776 }
9b3e0f4d
QT		 2777
2778 spin_lock_irqsave(&vha->work_lock, flags);
2779 clear_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags);
2780 spin_unlock_irqrestore(&vha->work_lock, flags);
ec7193e2
QT		 2781}
2782
1da177e4
LT		 2783/*
2784 * PCI driver interface
2785 */
6f039790 2786static int
7ee61397 2787qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
1da177e4 2788{
a1541d5a 2789 int ret = -ENODEV;
1da177e4 2790 struct Scsi_Host *host;
e315cd28
AC		 2791 scsi_qla_host_t *base_vha = NULL;
2792 struct qla_hw_data *ha;
29856e28 2793 char pci_info[30];
7d613ac6 2794 char fw_str[30], wq_name[30];
5433383e 2795 struct scsi_host_template *sht;
642ef983 2796 int bars, mem_only = 0;
e315cd28 2797 uint16_t req_length = 0, rsp_length = 0;
73208dfd
AC		 2798 struct req_que *req = NULL;
2799 struct rsp_que *rsp = NULL;
5601236b 2800 int i;
d7459527 2801
285d0321 2802 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO);
a5326f86 2803 sht = &qla2xxx_driver_template;
5433383e 2804 if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 ||
8bc69e7d 2805 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 ||
4d4df193 2806 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 ||
8bc69e7d 2807 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 ||
c3a2f0df 2808 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 ||
3a03eb79 2809 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 ||
a9083016 2810 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 ||
6246b8a1
GM		 2811 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021 ||
2812 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2031 ||
8ae6d9c7 2813 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8031 ||
7ec0effd 2814 pdev->device == PCI_DEVICE_ID_QLOGIC_ISPF001 ||
f73cb695 2815 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8044 ||
2c5bbbb2 2816 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2071 ||
2b48992f 2817 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2271 ||
ecc89f25
JC		 2818 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2261 ||
2819 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2081 ||
2820 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2281 ||
2821 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2089 ||
2822 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2289) {
285d0321 2823 bars = pci_select_bars(pdev, IORESOURCE_MEM);
09483916 2824 mem_only = 1;
7c3df132
SK		 2825 ql_dbg_pci(ql_dbg_init, pdev, 0x0007,
2826 "Mem only adapter.\n");
285d0321 2827 }
7c3df132
SK		 2828 ql_dbg_pci(ql_dbg_init, pdev, 0x0008,
2829 "Bars=%d.\n", bars);
285d0321 2830
09483916
BH		 2831 if (mem_only) {
2832 if (pci_enable_device_mem(pdev))
ddff7ed4 2833 return ret;
09483916
BH		 2834 } else {
2835 if (pci_enable_device(pdev))
ddff7ed4 2836 return ret;
09483916 2837 }
285d0321 2838
0927678f
JB		 2839 /* This may fail but that's ok */
2840 pci_enable_pcie_error_reporting(pdev);
285d0321 2841
5da05a26
GM		 2842 /* Turn off T10-DIF when FC-NVMe is enabled */
2843 if (ql2xnvmeenable)
2844 ql2xenabledif = 0;
2845
e315cd28
AC		 2846 ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL);
2847 if (!ha) {
7c3df132
SK		 2848 ql_log_pci(ql_log_fatal, pdev, 0x0009,
2849 "Unable to allocate memory for ha.\n");
ddff7ed4 2850 goto disable_device;
1da177e4 2851 }
7c3df132
SK		 2852 ql_dbg_pci(ql_dbg_init, pdev, 0x000a,
2853 "Memory allocated for ha=%p.\n", ha);
e315cd28 2854 ha->pdev = pdev;
33e79977
QT		 2855 INIT_LIST_HEAD(&ha->tgt.q_full_list);
2856 spin_lock_init(&ha->tgt.q_full_lock);
7560151b 2857 spin_lock_init(&ha->tgt.sess_lock);
2f424b9b
QT		 2858 spin_lock_init(&ha->tgt.atio_lock);
2859
deeae7a6 2860 atomic_set(&ha->nvme_active_aen_cnt, 0);
1da177e4
LT		 2861
2862 /* Clear our data area */
285d0321 2863 ha->bars = bars;
09483916 2864 ha->mem_only = mem_only;
df4bf0bb 2865 spin_lock_init(&ha->hardware_lock);
339aa70e 2866 spin_lock_init(&ha->vport_slock);
a9b6f722 2867 mutex_init(&ha->selflogin_lock);
7a8ab9c8 2868 mutex_init(&ha->optrom_mutex);
1da177e4 2869
ea5b6382 2870 /* Set ISP-type information. */
2871 qla2x00_set_isp_flags(ha);
ca79cf66
DG		 2872
2873 /* Set EEH reset type to fundamental if required by hba */
95676112 2874 if (IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha) ||
ecc89f25 2875 IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))
ca79cf66 2876 pdev->needs_freset = 1;
ca79cf66 2877
cba1e47f
CD		 2878 ha->prev_topology = 0;
2879 ha->init_cb_size = sizeof(init_cb_t);
2880 ha->link_data_rate = PORT_SPEED_UNKNOWN;
2881 ha->optrom_size = OPTROM_SIZE_2300;
d1e3635a 2882 ha->max_exchg = FW_MAX_EXCHANGES_CNT;
b2000805
QT		 2883 atomic_set(&ha->num_pend_mbx_stage1, 0);
2884 atomic_set(&ha->num_pend_mbx_stage2, 0);
2885 atomic_set(&ha->num_pend_mbx_stage3, 0);
8b4673ba
QT		 2886 atomic_set(&ha->zio_threshold, DEFAULT_ZIO_THRESHOLD);
2887 ha->last_zio_threshold = DEFAULT_ZIO_THRESHOLD;
cba1e47f 2888
abbd8870 2889 /* Assign ISP specific operations. */
1da177e4 2890 if (IS_QLA2100(ha)) {
642ef983 2891 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
1da177e4 2892 ha->mbx_count = MAILBOX_REGISTER_COUNT_2100;
e315cd28
AC		 2893 req_length = REQUEST_ENTRY_CNT_2100;
2894 rsp_length = RESPONSE_ENTRY_CNT_2100;
2895 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
abbd8870 2896 ha->gid_list_info_size = 4;
3a03eb79
AV		 2897 ha->flash_conf_off = ~0;
2898 ha->flash_data_off = ~0;
2899 ha->nvram_conf_off = ~0;
2900 ha->nvram_data_off = ~0;
fd34f556 2901 ha->isp_ops = &qla2100_isp_ops;
1da177e4 2902 } else if (IS_QLA2200(ha)) {
642ef983 2903 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
67ddda35 2904 ha->mbx_count = MAILBOX_REGISTER_COUNT_2200;
e315cd28
AC		 2905 req_length = REQUEST_ENTRY_CNT_2200;
2906 rsp_length = RESPONSE_ENTRY_CNT_2100;
2907 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
abbd8870 2908 ha->gid_list_info_size = 4;
3a03eb79
AV		 2909 ha->flash_conf_off = ~0;
2910 ha->flash_data_off = ~0;
2911 ha->nvram_conf_off = ~0;
2912 ha->nvram_data_off = ~0;
fd34f556 2913 ha->isp_ops = &qla2100_isp_ops;
fca29703 2914 } else if (IS_QLA23XX(ha)) {
642ef983 2915 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
1da177e4 2916 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2917 req_length = REQUEST_ENTRY_CNT_2200;
2918 rsp_length = RESPONSE_ENTRY_CNT_2300;
2919 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
abbd8870 2920 ha->gid_list_info_size = 6;
854165f4 2921 if (IS_QLA2322(ha) || IS_QLA6322(ha))
2922 ha->optrom_size = OPTROM_SIZE_2322;
3a03eb79
AV		 2923 ha->flash_conf_off = ~0;
2924 ha->flash_data_off = ~0;
2925 ha->nvram_conf_off = ~0;
2926 ha->nvram_data_off = ~0;
fd34f556 2927 ha->isp_ops = &qla2300_isp_ops;
4d4df193 2928 } else if (IS_QLA24XX_TYPE(ha)) {
642ef983 2929 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
fca29703 2930 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2931 req_length = REQUEST_ENTRY_CNT_24XX;
2932 rsp_length = RESPONSE_ENTRY_CNT_2300;
2d70c103 2933 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
e315cd28 2934 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2c3dfe3f 2935 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
fca29703 2936 ha->gid_list_info_size = 8;
854165f4 2937 ha->optrom_size = OPTROM_SIZE_24XX;
73208dfd 2938 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX;
fd34f556 2939 ha->isp_ops = &qla24xx_isp_ops;
3a03eb79
AV		 2940 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2941 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2942 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2943 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
c3a2f0df 2944 } else if (IS_QLA25XX(ha)) {
642ef983 2945 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
c3a2f0df 2946 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2947 req_length = REQUEST_ENTRY_CNT_24XX;
2948 rsp_length = RESPONSE_ENTRY_CNT_2300;
2d70c103 2949 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
e315cd28 2950 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
c3a2f0df 2951 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
c3a2f0df
AV		 2952 ha->gid_list_info_size = 8;
2953 ha->optrom_size = OPTROM_SIZE_25XX;
73208dfd 2954 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
c3a2f0df 2955 ha->isp_ops = &qla25xx_isp_ops;
3a03eb79
AV		 2956 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2957 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2958 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2959 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
2960 } else if (IS_QLA81XX(ha)) {
642ef983 2961 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3a03eb79
AV		 2962 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2963 req_length = REQUEST_ENTRY_CNT_24XX;
2964 rsp_length = RESPONSE_ENTRY_CNT_2300;
aa230bc5 2965 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
3a03eb79
AV		 2966 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2967 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2968 ha->gid_list_info_size = 8;
2969 ha->optrom_size = OPTROM_SIZE_81XX;
40859ae5 2970 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3a03eb79
AV		 2971 ha->isp_ops = &qla81xx_isp_ops;
2972 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2973 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2974 ha->nvram_conf_off = ~0;
2975 ha->nvram_data_off = ~0;
a9083016 2976 } else if (IS_QLA82XX(ha)) {
642ef983 2977 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
a9083016
GM		 2978 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2979 req_length = REQUEST_ENTRY_CNT_82XX;
2980 rsp_length = RESPONSE_ENTRY_CNT_82XX;
2981 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2982 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2983 ha->gid_list_info_size = 8;
2984 ha->optrom_size = OPTROM_SIZE_82XX;
087c621e 2985 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
a9083016
GM		 2986 ha->isp_ops = &qla82xx_isp_ops;
2987 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2988 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2989 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2990 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
7ec0effd
AD		 2991 } else if (IS_QLA8044(ha)) {
2992 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2993 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2994 req_length = REQUEST_ENTRY_CNT_82XX;
2995 rsp_length = RESPONSE_ENTRY_CNT_82XX;
2996 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2997 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2998 ha->gid_list_info_size = 8;
2999 ha->optrom_size = OPTROM_SIZE_83XX;
3000 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3001 ha->isp_ops = &qla8044_isp_ops;
3002 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
3003 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
3004 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
3005 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
6246b8a1 3006 } else if (IS_QLA83XX(ha)) {
7d613ac6 3007 ha->portnum = PCI_FUNC(ha->pdev->devfn);
642ef983 3008 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
6246b8a1 3009 ha->mbx_count = MAILBOX_REGISTER_COUNT;
f2ea653f 3010 req_length = REQUEST_ENTRY_CNT_83XX;
e7b42e33 3011 rsp_length = RESPONSE_ENTRY_CNT_83XX;
b8aa4bdf 3012 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
6246b8a1
GM		 3013 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
3014 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
3015 ha->gid_list_info_size = 8;
3016 ha->optrom_size = OPTROM_SIZE_83XX;
3017 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3018 ha->isp_ops = &qla83xx_isp_ops;
3019 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
3020 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
3021 ha->nvram_conf_off = ~0;
3022 ha->nvram_data_off = ~0;
8ae6d9c7
GM		 3023 } else if (IS_QLAFX00(ha)) {
3024 ha->max_fibre_devices = MAX_FIBRE_DEVICES_FX00;
3025 ha->mbx_count = MAILBOX_REGISTER_COUNT_FX00;
3026 ha->aen_mbx_count = AEN_MAILBOX_REGISTER_COUNT_FX00;
3027 req_length = REQUEST_ENTRY_CNT_FX00;
3028 rsp_length = RESPONSE_ENTRY_CNT_FX00;
8ae6d9c7
GM		 3029 ha->isp_ops = &qlafx00_isp_ops;
3030 ha->port_down_retry_count = 30; /* default value */
3031 ha->mr.fw_hbt_cnt = QLAFX00_HEARTBEAT_INTERVAL;
3032 ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL;
71e56003 3033 ha->mr.fw_critemp_timer_tick = QLAFX00_CRITEMP_INTERVAL;
8ae6d9c7 3034 ha->mr.fw_hbt_en = 1;
e8f5e95d
AB		 3035 ha->mr.host_info_resend = false;
3036 ha->mr.hinfo_resend_timer_tick = QLAFX00_HINFO_RESEND_INTERVAL;
f73cb695
CD		 3037 } else if (IS_QLA27XX(ha)) {
3038 ha->portnum = PCI_FUNC(ha->pdev->devfn);
3039 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3040 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e7b42e33
QT		 3041 req_length = REQUEST_ENTRY_CNT_83XX;
3042 rsp_length = RESPONSE_ENTRY_CNT_83XX;
b20f02e1 3043 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
f73cb695
CD		 3044 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
3045 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
3046 ha->gid_list_info_size = 8;
3047 ha->optrom_size = OPTROM_SIZE_83XX;
3048 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3049 ha->isp_ops = &qla27xx_isp_ops;
3050 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
3051 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
3052 ha->nvram_conf_off = ~0;
3053 ha->nvram_data_off = ~0;
ecc89f25
JC		 3054 } else if (IS_QLA28XX(ha)) {
3055 ha->portnum = PCI_FUNC(ha->pdev->devfn);
3056 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3057 ha->mbx_count = MAILBOX_REGISTER_COUNT;
3058 req_length = REQUEST_ENTRY_CNT_24XX;
3059 rsp_length = RESPONSE_ENTRY_CNT_2300;
3060 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
3061 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
3062 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
3063 ha->gid_list_info_size = 8;
3064 ha->optrom_size = OPTROM_SIZE_28XX;
3065 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3066 ha->isp_ops = &qla27xx_isp_ops;
3067 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_28XX;
3068 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_28XX;
3069 ha->nvram_conf_off = ~0;
3070 ha->nvram_data_off = ~0;
1da177e4 3071 }
6246b8a1 3072
7c3df132
SK		 3073 ql_dbg_pci(ql_dbg_init, pdev, 0x001e,
3074 "mbx_count=%d, req_length=%d, "
3075 "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, "
642ef983
CD		 3076 "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, "
3077 "max_fibre_devices=%d.\n",
7c3df132
SK		 3078 ha->mbx_count, req_length, rsp_length, ha->max_loop_id,
3079 ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size,
642ef983 3080 ha->nvram_npiv_size, ha->max_fibre_devices);
7c3df132
SK		 3081 ql_dbg_pci(ql_dbg_init, pdev, 0x001f,
3082 "isp_ops=%p, flash_conf_off=%d, "
3083 "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n",
3084 ha->isp_ops, ha->flash_conf_off, ha->flash_data_off,
3085 ha->nvram_conf_off, ha->nvram_data_off);
706f457d
GM		 3086
3087 /* Configure PCI I/O space */
3088 ret = ha->isp_ops->iospace_config(ha);
3089 if (ret)
0a63ad12 3090 goto iospace_config_failed;
706f457d
GM		 3091
3092 ql_log_pci(ql_log_info, pdev, 0x001d,
3093 "Found an ISP%04X irq %d iobase 0x%p.\n",
3094 pdev->device, pdev->irq, ha->iobase);
6c2f527c 3095 mutex_init(&ha->vport_lock);
d7459527 3096 mutex_init(&ha->mq_lock);
0b05a1f0
MB		 3097 init_completion(&ha->mbx_cmd_comp);
3098 complete(&ha->mbx_cmd_comp);
3099 init_completion(&ha->mbx_intr_comp);
23f2ebd1 3100 init_completion(&ha->dcbx_comp);
f356bef1 3101 init_completion(&ha->lb_portup_comp);
1da177e4 3102
2c3dfe3f 3103 set_bit(0, (unsigned long *) ha->vp_idx_map);
1da177e4 3104
53303c42 3105 qla2x00_config_dma_addressing(ha);
7c3df132
SK		 3106 ql_dbg_pci(ql_dbg_init, pdev, 0x0020,
3107 "64 Bit addressing is %s.\n",
3108 ha->flags.enable_64bit_addressing ? "enable" :
3109 "disable");
73208dfd 3110 ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp);
b2a72ec3 3111 if (ret) {
7c3df132
SK		 3112 ql_log_pci(ql_log_fatal, pdev, 0x0031,
3113 "Failed to allocate memory for adapter, aborting.\n");
1da177e4 3114
e315cd28
AC		 3115 goto probe_hw_failed;
3116 }
3117
73208dfd 3118 req->max_q_depth = MAX_Q_DEPTH;
e315cd28 3119 if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU)
73208dfd
AC		 3120 req->max_q_depth = ql2xmaxqdepth;
3121
e315cd28
AC		 3122
3123 base_vha = qla2x00_create_host(sht, ha);
3124 if (!base_vha) {
a1541d5a 3125 ret = -ENOMEM;
e315cd28 3126 goto probe_hw_failed;
1da177e4
LT		 3127 }
3128
e315cd28 3129 pci_set_drvdata(pdev, base_vha);
6b383979 3130 set_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags);
e315cd28 3131
e315cd28 3132 host = base_vha->host;
2afa19a9 3133 base_vha->req = req;
73208dfd 3134 if (IS_QLA2XXX_MIDTYPE(ha))
f6602f3b
QT		 3135 base_vha->mgmt_svr_loop_id =
3136 qla2x00_reserve_mgmt_server_loop_id(base_vha);
73208dfd 3137 else
e315cd28
AC		 3138 base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER +
3139 base_vha->vp_idx;
58548cb5 3140
8ae6d9c7
GM		 3141 /* Setup fcport template structure. */
3142 ha->mr.fcport.vha = base_vha;
3143 ha->mr.fcport.port_type = FCT_UNKNOWN;
3144 ha->mr.fcport.loop_id = FC_NO_LOOP_ID;
3145 qla2x00_set_fcport_state(&ha->mr.fcport, FCS_UNCONFIGURED);
3146 ha->mr.fcport.supported_classes = FC_COS_UNSPECIFIED;
3147 ha->mr.fcport.scan_state = 1;
3148
58548cb5
GM		 3149 /* Set the SG table size based on ISP type */
3150 if (!IS_FWI2_CAPABLE(ha)) {
3151 if (IS_QLA2100(ha))
3152 host->sg_tablesize = 32;
3153 } else {
3154 if (!IS_QLA82XX(ha))
3155 host->sg_tablesize = QLA_SG_ALL;
3156 }
642ef983 3157 host->max_id = ha->max_fibre_devices;
e315cd28
AC		 3158 host->cmd_per_lun = 3;
3159 host->unique_id = host->host_no;
e02587d7 3160 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif)
0c470874
AE		 3161 host->max_cmd_len = 32;
3162 else
3163 host->max_cmd_len = MAX_CMDSZ;
e315cd28 3164 host->max_channel = MAX_BUSES - 1;
755f516b
HR		 3165 /* Older HBAs support only 16-bit LUNs */
3166 if (!IS_QLAFX00(ha) && !IS_FWI2_CAPABLE(ha) &&
3167 ql2xmaxlun > 0xffff)
3168 host->max_lun = 0xffff;
3169 else
3170 host->max_lun = ql2xmaxlun;
e315cd28 3171 host->transportt = qla2xxx_transport_template;
9a069e19 3172 sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC);
e315cd28 3173
7c3df132
SK		 3174 ql_dbg(ql_dbg_init, base_vha, 0x0033,
3175 "max_id=%d this_id=%d "
3176 "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d "
1abf635d 3177 "max_lun=%llu transportt=%p, vendor_id=%llu.\n", host->max_id,
7c3df132
SK		 3178 host->this_id, host->cmd_per_lun, host->unique_id,
3179 host->max_cmd_len, host->max_channel, host->max_lun,
3180 host->transportt, sht->vendor_id);
3181
1010f21e
HM		 3182 INIT_WORK(&base_vha->iocb_work, qla2x00_iocb_work_fn);
3183
d7459527
MH		 3184 /* Set up the irqs */
3185 ret = qla2x00_request_irqs(ha, rsp);
3186 if (ret)
6a2cf8d3 3187 goto probe_failed;
d7459527 3188
9a347ff4 3189 /* Alloc arrays of request and response ring ptrs */
6d634067
BK		 3190 ret = qla2x00_alloc_queues(ha, req, rsp);
3191 if (ret) {
9a347ff4
CD		 3192 ql_log(ql_log_fatal, base_vha, 0x003d,
3193 "Failed to allocate memory for queue pointers..."
3194 "aborting.\n");
26a77799 3195 ret = -ENODEV;
6a2cf8d3 3196 goto probe_failed;
9a347ff4
CD		 3197 }
3198
f664a3cc 3199 if (ha->mqenable) {
5601236b
MH		 3200 /* number of hardware queues supported by blk/scsi-mq*/
3201 host->nr_hw_queues = ha->max_qpairs;
3202
3203 ql_dbg(ql_dbg_init, base_vha, 0x0192,
3204 "blk/scsi-mq enabled, HW queues = %d.\n", host->nr_hw_queues);
c38d1baf
HM		 3205 } else {
3206 if (ql2xnvmeenable) {
3207 host->nr_hw_queues = ha->max_qpairs;
3208 ql_dbg(ql_dbg_init, base_vha, 0x0194,
3209 "FC-NVMe support is enabled, HW queues=%d\n",
3210 host->nr_hw_queues);
3211 } else {
3212 ql_dbg(ql_dbg_init, base_vha, 0x0193,
3213 "blk/scsi-mq disabled.\n");
3214 }
3215 }
5601236b 3216
2d70c103 3217 qlt_probe_one_stage1(base_vha, ha);
9a347ff4 3218
90a86fc0
JC		 3219 pci_save_state(pdev);
3220
9a347ff4 3221 /* Assign back pointers */
2afa19a9
AC		 3222 rsp->req = req;
3223 req->rsp = rsp;
9a347ff4 3224
8ae6d9c7
GM		 3225 if (IS_QLAFX00(ha)) {
3226 ha->rsp_q_map[0] = rsp;
3227 ha->req_q_map[0] = req;
3228 set_bit(0, ha->req_qid_map);
3229 set_bit(0, ha->rsp_qid_map);
3230 }
3231
08029990
AV		 3232 /* FWI2-capable only. */
3233 req->req_q_in = &ha->iobase->isp24.req_q_in;
3234 req->req_q_out = &ha->iobase->isp24.req_q_out;
3235 rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in;
3236 rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out;
ecc89f25
JC		 3237 if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha) ||
3238 IS_QLA28XX(ha)) {
08029990
AV		 3239 req->req_q_in = &ha->mqiobase->isp25mq.req_q_in;
3240 req->req_q_out = &ha->mqiobase->isp25mq.req_q_out;
3241 rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in;
3242 rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out;
17d98630
AC		 3243 }
3244
8ae6d9c7
GM		 3245 if (IS_QLAFX00(ha)) {
3246 req->req_q_in = &ha->iobase->ispfx00.req_q_in;
3247 req->req_q_out = &ha->iobase->ispfx00.req_q_out;
3248 rsp->rsp_q_in = &ha->iobase->ispfx00.rsp_q_in;
3249 rsp->rsp_q_out = &ha->iobase->ispfx00.rsp_q_out;
3250 }
3251
7ec0effd 3252 if (IS_P3P_TYPE(ha)) {
a9083016
GM		 3253 req->req_q_out = &ha->iobase->isp82.req_q_out[0];
3254 rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0];
3255 rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0];
3256 }
3257
7c3df132
SK		 3258 ql_dbg(ql_dbg_multiq, base_vha, 0xc009,
3259 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
3260 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
3261 ql_dbg(ql_dbg_multiq, base_vha, 0xc00a,
3262 "req->req_q_in=%p req->req_q_out=%p "
3263 "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
3264 req->req_q_in, req->req_q_out,
3265 rsp->rsp_q_in, rsp->rsp_q_out);
3266 ql_dbg(ql_dbg_init, base_vha, 0x003e,
3267 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
3268 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
3269 ql_dbg(ql_dbg_init, base_vha, 0x003f,
3270 "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
3271 req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out);
1da177e4 3272
d48cc67c 3273 ha->wq = alloc_workqueue("qla2xxx_wq", 0, 0);
3274
8ae6d9c7 3275 if (ha->isp_ops->initialize_adapter(base_vha)) {
7c3df132
SK		 3276 ql_log(ql_log_fatal, base_vha, 0x00d6,
3277 "Failed to initialize adapter - Adapter flags %x.\n",
3278 base_vha->device_flags);
1da177e4 3279
a9083016
GM		 3280 if (IS_QLA82XX(ha)) {
3281 qla82xx_idc_lock(ha);
3282 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 3283 QLA8XXX_DEV_FAILED);
a9083016 3284 qla82xx_idc_unlock(ha);
7c3df132
SK		 3285 ql_log(ql_log_fatal, base_vha, 0x00d7,
3286 "HW State: FAILED.\n");
7ec0effd
AD		 3287 } else if (IS_QLA8044(ha)) {
3288 qla8044_idc_lock(ha);
3289 qla8044_wr_direct(base_vha,
3290 QLA8044_CRB_DEV_STATE_INDEX,
3291 QLA8XXX_DEV_FAILED);
3292 qla8044_idc_unlock(ha);
3293 ql_log(ql_log_fatal, base_vha, 0x0150,
3294 "HW State: FAILED.\n");
a9083016
GM		 3295 }
3296
a1541d5a 3297 ret = -ENODEV;
1da177e4
LT		 3298 goto probe_failed;
3299 }
3300
3b1bef64
CD		 3301 if (IS_QLAFX00(ha))
3302 host->can_queue = QLAFX00_MAX_CANQUEUE;
3303 else
3304 host->can_queue = req->num_outstanding_cmds - 10;
3305
3306 ql_dbg(ql_dbg_init, base_vha, 0x0032,
3307 "can_queue=%d, req=%p, mgmt_svr_loop_id=%d, sg_tablesize=%d.\n",
3308 host->can_queue, base_vha->req,
3309 base_vha->mgmt_svr_loop_id, host->sg_tablesize);
3310
e326d22a 3311 if (ha->mqenable) {
e326d22a 3312 bool startit = false;
e326d22a 3313
f664a3cc 3314 if (QLA_TGT_MODE_ENABLED())
e326d22a 3315 startit = false;
e326d22a 3316
f664a3cc 3317 if (ql2x_ini_mode == QLA2XXX_INI_MODE_ENABLED)
e326d22a 3318 startit = true;
e326d22a 3319
f664a3cc
JA		 3320 /* Create start of day qpairs for Block MQ */
3321 for (i = 0; i < ha->max_qpairs; i++)
3322 qla2xxx_create_qpair(base_vha, 5, 0, startit);
5601236b 3323 }
68ca949c 3324
cbc8eb67
AV		 3325 if (ha->flags.running_gold_fw)
3326 goto skip_dpc;
3327
1da177e4
LT		 3328 /*
3329 * Startup the kernel thread for this host adapter
3330 */
39a11240 3331 ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha,
7c3df132 3332 "%s_dpc", base_vha->host_str);
39a11240 3333 if (IS_ERR(ha->dpc_thread)) {
7c3df132
SK		 3334 ql_log(ql_log_fatal, base_vha, 0x00ed,
3335 "Failed to start DPC thread.\n");
39a11240 3336 ret = PTR_ERR(ha->dpc_thread);
e2532b4a 3337 ha->dpc_thread = NULL;
1da177e4
LT		 3338 goto probe_failed;
3339 }
7c3df132
SK		 3340 ql_dbg(ql_dbg_init, base_vha, 0x00ee,
3341 "DPC thread started successfully.\n");
1da177e4 3342
2d70c103
NB		 3343 /*
3344 * If we're not coming up in initiator mode, we might sit for
3345 * a while without waking up the dpc thread, which leads to a
3346 * stuck process warning. So just kick the dpc once here and
3347 * let the kthread start (and go back to sleep in qla2x00_do_dpc).
3348 */
3349 qla2xxx_wake_dpc(base_vha);
3350
f3ddac19
CD		 3351 INIT_WORK(&ha->board_disable, qla2x00_disable_board_on_pci_error);
3352
81178772
SK		 3353 if (IS_QLA8031(ha) || IS_MCTP_CAPABLE(ha)) {
3354 sprintf(wq_name, "qla2xxx_%lu_dpc_lp_wq", base_vha->host_no);
3355 ha->dpc_lp_wq = create_singlethread_workqueue(wq_name);
3356 INIT_WORK(&ha->idc_aen, qla83xx_service_idc_aen);
3357
3358 sprintf(wq_name, "qla2xxx_%lu_dpc_hp_wq", base_vha->host_no);
3359 ha->dpc_hp_wq = create_singlethread_workqueue(wq_name);
3360 INIT_WORK(&ha->nic_core_reset, qla83xx_nic_core_reset_work);
3361 INIT_WORK(&ha->idc_state_handler,
3362 qla83xx_idc_state_handler_work);
3363 INIT_WORK(&ha->nic_core_unrecoverable,
3364 qla83xx_nic_core_unrecoverable_work);
3365 }
3366
cbc8eb67 3367skip_dpc:
e315cd28
AC		 3368 list_add_tail(&base_vha->list, &ha->vp_list);
3369 base_vha->host->irq = ha->pdev->irq;
1da177e4
LT		 3370
3371 /* Initialized the timer */
8e5f4ba0 3372 qla2x00_start_timer(base_vha, WATCH_INTERVAL);
7c3df132
SK		 3373 ql_dbg(ql_dbg_init, base_vha, 0x00ef,
3374 "Started qla2x00_timer with "
3375 "interval=%d.\n", WATCH_INTERVAL);
3376 ql_dbg(ql_dbg_init, base_vha, 0x00f0,
3377 "Detected hba at address=%p.\n",
3378 ha);
d19044c3 3379
e02587d7 3380 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) {
bad75002 3381 if (ha->fw_attributes & BIT_4) {
9e522cd8 3382 int prot = 0, guard;
bd432bb5 3383
bad75002 3384 base_vha->flags.difdix_supported = 1;
7c3df132
SK		 3385 ql_dbg(ql_dbg_init, base_vha, 0x00f1,
3386 "Registering for DIF/DIX type 1 and 3 protection.\n");
8cb2049c
AE		 3387 if (ql2xenabledif == 1)
3388 prot = SHOST_DIX_TYPE0_PROTECTION;
7855d2ba
MP		 3389 if (ql2xprotmask)
3390 scsi_host_set_prot(host, ql2xprotmask);
3391 else
3392 scsi_host_set_prot(host,
3393 prot | SHOST_DIF_TYPE1_PROTECTION
3394 | SHOST_DIF_TYPE2_PROTECTION
3395 | SHOST_DIF_TYPE3_PROTECTION
3396 | SHOST_DIX_TYPE1_PROTECTION
3397 | SHOST_DIX_TYPE2_PROTECTION
3398 | SHOST_DIX_TYPE3_PROTECTION);
9e522cd8
AE		 3399
3400 guard = SHOST_DIX_GUARD_CRC;
3401
3402 if (IS_PI_IPGUARD_CAPABLE(ha) &&
3403 (ql2xenabledif > 1 || IS_PI_DIFB_DIX0_CAPABLE(ha)))
3404 guard |= SHOST_DIX_GUARD_IP;
3405
7855d2ba
MP		 3406 if (ql2xprotguard)
3407 scsi_host_set_guard(host, ql2xprotguard);
3408 else
3409 scsi_host_set_guard(host, guard);
bad75002
AE		 3410 } else
3411 base_vha->flags.difdix_supported = 0;
3412 }
3413
a9083016
GM		 3414 ha->isp_ops->enable_intrs(ha);
3415
1fe19ee4
AB		 3416 if (IS_QLAFX00(ha)) {
3417 ret = qlafx00_fx_disc(base_vha,
3418 &base_vha->hw->mr.fcport, FXDISC_GET_CONFIG_INFO);
3419 host->sg_tablesize = (ha->mr.extended_io_enabled) ?
3420 QLA_SG_ALL : 128;
3421 }
3422
a1541d5a
AV		 3423 ret = scsi_add_host(host, &pdev->dev);
3424 if (ret)
3425 goto probe_failed;
3426
1486400f
MR		 3427 base_vha->flags.init_done = 1;
3428 base_vha->flags.online = 1;
edaa5c74 3429 ha->prev_minidump_failed = 0;
1486400f 3430
7c3df132
SK		 3431 ql_dbg(ql_dbg_init, base_vha, 0x00f2,
3432 "Init done and hba is online.\n");
3433
726b8548
QT		 3434 if (qla_ini_mode_enabled(base_vha) ||
3435 qla_dual_mode_enabled(base_vha))
2d70c103
NB		 3436 scsi_scan_host(host);
3437 else
3438 ql_dbg(ql_dbg_init, base_vha, 0x0122,
3439 "skipping scsi_scan_host() for non-initiator port\n");
1e99e33a 3440
e315cd28 3441 qla2x00_alloc_sysfs_attr(base_vha);
a1541d5a 3442
8ae6d9c7 3443 if (IS_QLAFX00(ha)) {
8ae6d9c7
GM		 3444 ret = qlafx00_fx_disc(base_vha,
3445 &base_vha->hw->mr.fcport, FXDISC_GET_PORT_INFO);
3446
3447 /* Register system information */
3448 ret = qlafx00_fx_disc(base_vha,
3449 &base_vha->hw->mr.fcport, FXDISC_REG_HOST_INFO);
3450 }
3451
e315cd28 3452 qla2x00_init_host_attr(base_vha);
a1541d5a 3453
e315cd28 3454 qla2x00_dfs_setup(base_vha);
df613b96 3455
03eb912a
AB		 3456 ql_log(ql_log_info, base_vha, 0x00fb,
3457 "QLogic %s - %s.\n", ha->model_number, ha->model_desc);
7c3df132
SK		 3458 ql_log(ql_log_info, base_vha, 0x00fc,
3459 "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n",
3460 pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info),
3461 pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-',
3462 base_vha->host_no,
df57caba 3463 ha->isp_ops->fw_version_str(base_vha, fw_str, sizeof(fw_str)));
1da177e4 3464
2d70c103
NB		 3465 qlt_add_target(ha, base_vha);
3466
6b383979 3467 clear_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags);
a29b3dd7
JC		 3468
3469 if (test_bit(UNLOADING, &base_vha->dpc_flags))
3470 return -ENODEV;
3471
e4e3a2ce
QT		 3472 if (ha->flags.detected_lr_sfp) {
3473 ql_log(ql_log_info, base_vha, 0xffff,
3474 "Reset chip to pick up LR SFP setting\n");
3475 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
3476 qla2xxx_wake_dpc(base_vha);
3477 }
3478
1da177e4
LT		 3479 return 0;
3480
3481probe_failed:
b9978769
AV		 3482 if (base_vha->timer_active)
3483 qla2x00_stop_timer(base_vha);
3484 base_vha->flags.online = 0;
3485 if (ha->dpc_thread) {
3486 struct task_struct *t = ha->dpc_thread;
3487
3488 ha->dpc_thread = NULL;
3489 kthread_stop(t);
3490 }
3491
e315cd28 3492 qla2x00_free_device(base_vha);
e315cd28 3493 scsi_host_put(base_vha->host);
6d634067
BK		 3494 /*
3495 * Need to NULL out local req/rsp after
3496 * qla2x00_free_device => qla2x00_free_queues frees
3497 * what these are pointing to. Or else we'll
3498 * fall over below in qla2x00_free_req/rsp_que.
3499 */
3500 req = NULL;
3501 rsp = NULL;
1da177e4 3502
e315cd28 3503probe_hw_failed:
d64d6c56 3504 qla2x00_mem_free(ha);
3505 qla2x00_free_req_que(ha, req);
3506 qla2x00_free_rsp_que(ha, rsp);
1a2fbf18
JL		 3507 qla2x00_clear_drv_active(ha);
3508
0a63ad12 3509iospace_config_failed:
7ec0effd 3510 if (IS_P3P_TYPE(ha)) {
0a63ad12 3511 if (!ha->nx_pcibase)
f73cb695 3512 iounmap((device_reg_t *)ha->nx_pcibase);
a9083016 3513 if (!ql2xdbwr)
f73cb695 3514 iounmap((device_reg_t *)ha->nxdb_wr_ptr);
a9083016
GM		 3515 } else {
3516 if (ha->iobase)
3517 iounmap(ha->iobase);
8ae6d9c7
GM		 3518 if (ha->cregbase)
3519 iounmap(ha->cregbase);
a9083016 3520 }
e315cd28
AC		 3521 pci_release_selected_regions(ha->pdev, ha->bars);
3522 kfree(ha);
1da177e4 3523
ddff7ed4 3524disable_device:
e315cd28 3525 pci_disable_device(pdev);
a1541d5a 3526 return ret;
1da177e4 3527}
1da177e4 3528
e30d1756
MI		 3529static void
3530qla2x00_shutdown(struct pci_dev *pdev)
3531{
3532 scsi_qla_host_t *vha;
3533 struct qla_hw_data *ha;
3534
3535 vha = pci_get_drvdata(pdev);
3536 ha = vha->hw;
3537
efdb5760
SC		 3538 ql_log(ql_log_info, vha, 0xfffa,
3539 "Adapter shutdown\n");
3540
3541 /*
3542 * Prevent future board_disable and wait
3543 * until any pending board_disable has completed.
3544 */
3545 set_bit(PFLG_DRIVER_REMOVING, &vha->pci_flags);
3546 cancel_work_sync(&ha->board_disable);
3547
3548 if (!atomic_read(&pdev->enable_cnt))
3549 return;
3550
42479343
AB		 3551 /* Notify ISPFX00 firmware */
3552 if (IS_QLAFX00(ha))
3553 qlafx00_driver_shutdown(vha, 20);
3554
e30d1756
MI		 3555 /* Turn-off FCE trace */
3556 if (ha->flags.fce_enabled) {
3557 qla2x00_disable_fce_trace(vha, NULL, NULL);
3558 ha->flags.fce_enabled = 0;
3559 }
3560
3561 /* Turn-off EFT trace */
3562 if (ha->eft)
3563 qla2x00_disable_eft_trace(vha);
3564
ecc89f25
JC		 3565 if (IS_QLA25XX(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) ||
3566 IS_QLA28XX(ha)) {
3407fc37
QT		 3567 if (ha->flags.fw_started)
3568 qla2x00_abort_isp_cleanup(vha);
3569 } else {
3570 /* Stop currently executing firmware. */
3571 qla2x00_try_to_stop_firmware(vha);
3572 }
e30d1756
MI		 3573
3574 /* Turn adapter off line */
3575 vha->flags.online = 0;
3576
3577 /* turn-off interrupts on the card */
3578 if (ha->interrupts_on) {
3579 vha->flags.init_done = 0;
3580 ha->isp_ops->disable_intrs(ha);
3581 }
3582
3583 qla2x00_free_irqs(vha);
3584
3585 qla2x00_free_fw_dump(ha);
61d41f61 3586
61d41f61 3587 pci_disable_device(pdev);
efdb5760
SC		 3588 ql_log(ql_log_info, vha, 0xfffe,
3589 "Adapter shutdown successfully.\n");
e30d1756
MI		 3590}
3591
fe1b806f 3592/* Deletes all the virtual ports for a given ha */
4c993f76 3593static void
fe1b806f 3594qla2x00_delete_all_vps(struct qla_hw_data *ha, scsi_qla_host_t *base_vha)
1da177e4 3595{
fe1b806f 3596 scsi_qla_host_t *vha;
feafb7b1 3597 unsigned long flags;
e315cd28 3598
43ebf16d
AE		 3599 mutex_lock(&ha->vport_lock);
3600 while (ha->cur_vport_count) {
43ebf16d 3601 spin_lock_irqsave(&ha->vport_slock, flags);
feafb7b1 3602
43ebf16d
AE		 3603 BUG_ON(base_vha->list.next == &ha->vp_list);
3604 /* This assumes first entry in ha->vp_list is always base vha */
3605 vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list);
52c82823 3606 scsi_host_get(vha->host);
feafb7b1 3607
43ebf16d
AE		 3608 spin_unlock_irqrestore(&ha->vport_slock, flags);
3609 mutex_unlock(&ha->vport_lock);
3610
5e6803b4
HM		 3611 qla_nvme_delete(vha);
3612
43ebf16d
AE		 3613 fc_vport_terminate(vha->fc_vport);
3614 scsi_host_put(vha->host);
feafb7b1 3615
43ebf16d 3616 mutex_lock(&ha->vport_lock);
e315cd28 3617 }
43ebf16d 3618 mutex_unlock(&ha->vport_lock);
fe1b806f 3619}
1da177e4 3620
fe1b806f
CD		 3621/* Stops all deferred work threads */
3622static void
3623qla2x00_destroy_deferred_work(struct qla_hw_data *ha)
3624{
7d613ac6
SV		 3625 /* Cancel all work and destroy DPC workqueues */
3626 if (ha->dpc_lp_wq) {
3627 cancel_work_sync(&ha->idc_aen);
3628 destroy_workqueue(ha->dpc_lp_wq);
3629 ha->dpc_lp_wq = NULL;
3630 }
3631
3632 if (ha->dpc_hp_wq) {
3633 cancel_work_sync(&ha->nic_core_reset);
3634 cancel_work_sync(&ha->idc_state_handler);
3635 cancel_work_sync(&ha->nic_core_unrecoverable);
3636 destroy_workqueue(ha->dpc_hp_wq);
3637 ha->dpc_hp_wq = NULL;
3638 }
3639
b9978769
AV		 3640 /* Kill the kernel thread for this host */
3641 if (ha->dpc_thread) {
3642 struct task_struct *t = ha->dpc_thread;
3643
3644 /*
3645 * qla2xxx_wake_dpc checks for ->dpc_thread
3646 * so we need to zero it out.
3647 */
3648 ha->dpc_thread = NULL;
3649 kthread_stop(t);
3650 }
fe1b806f 3651}
1da177e4 3652
fe1b806f
CD		 3653static void
3654qla2x00_unmap_iobases(struct qla_hw_data *ha)
3655{
a9083016 3656 if (IS_QLA82XX(ha)) {
b963752f 3657
f73cb695 3658 iounmap((device_reg_t *)ha->nx_pcibase);
a9083016 3659 if (!ql2xdbwr)
f73cb695 3660 iounmap((device_reg_t *)ha->nxdb_wr_ptr);
a9083016
GM		 3661 } else {
3662 if (ha->iobase)
3663 iounmap(ha->iobase);
1da177e4 3664
8ae6d9c7
GM		 3665 if (ha->cregbase)
3666 iounmap(ha->cregbase);
3667
a9083016
GM		 3668 if (ha->mqiobase)
3669 iounmap(ha->mqiobase);
6246b8a1 3670
ecc89f25
JC		 3671 if ((IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) &&
3672 ha->msixbase)
6246b8a1 3673 iounmap(ha->msixbase);
a9083016 3674 }
fe1b806f
CD		 3675}
3676
3677static void
db7157d4 3678qla2x00_clear_drv_active(struct qla_hw_data *ha)
fe1b806f 3679{
fe1b806f
CD		 3680 if (IS_QLA8044(ha)) {
3681 qla8044_idc_lock(ha);
c41afc9a 3682 qla8044_clear_drv_active(ha);
fe1b806f
CD		 3683 qla8044_idc_unlock(ha);
3684 } else if (IS_QLA82XX(ha)) {
3685 qla82xx_idc_lock(ha);
3686 qla82xx_clear_drv_active(ha);
3687 qla82xx_idc_unlock(ha);
3688 }
3689}
3690
3691static void
3692qla2x00_remove_one(struct pci_dev *pdev)
3693{
3694 scsi_qla_host_t *base_vha;
3695 struct qla_hw_data *ha;
3696
beb9e315
JL		 3697 base_vha = pci_get_drvdata(pdev);
3698 ha = base_vha->hw;
45235022
QT		 3699 ql_log(ql_log_info, base_vha, 0xb079,
3700 "Removing driver\n");
beb9e315
JL		 3701
3702 /* Indicate device removal to prevent future board_disable and wait
3703 * until any pending board_disable has completed. */
3704 set_bit(PFLG_DRIVER_REMOVING, &base_vha->pci_flags);
3705 cancel_work_sync(&ha->board_disable);
3706
fe1b806f 3707 /*
beb9e315
JL		 3708 * If the PCI device is disabled then there was a PCI-disconnect and
3709 * qla2x00_disable_board_on_pci_error has taken care of most of the
3710 * resources.
fe1b806f 3711 */
beb9e315 3712 if (!atomic_read(&pdev->enable_cnt)) {
726b8548
QT		 3713 dma_free_coherent(&ha->pdev->dev, base_vha->gnl.size,
3714 base_vha->gnl.l, base_vha->gnl.ldma);
3715
beb9e315
JL		 3716 scsi_host_put(base_vha->host);
3717 kfree(ha);
3718 pci_set_drvdata(pdev, NULL);
fe1b806f 3719 return;
beb9e315 3720 }
638a1a01
SC		 3721 qla2x00_wait_for_hba_ready(base_vha);
3722
ecc89f25
JC		 3723 if (IS_QLA25XX(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) ||
3724 IS_QLA28XX(ha)) {
45235022
QT		 3725 if (ha->flags.fw_started)
3726 qla2x00_abort_isp_cleanup(base_vha);
3727 } else if (!IS_QLAFX00(ha)) {
3728 if (IS_QLA8031(ha)) {
3729 ql_dbg(ql_dbg_p3p, base_vha, 0xb07e,
3730 "Clearing fcoe driver presence.\n");
3731 if (qla83xx_clear_drv_presence(base_vha) != QLA_SUCCESS)
3732 ql_dbg(ql_dbg_p3p, base_vha, 0xb079,
3733 "Error while clearing DRV-Presence.\n");
3734 }
3735
3736 qla2x00_try_to_stop_firmware(base_vha);
3737 }
3738
2ce87cc5
QT		 3739 qla2x00_wait_for_sess_deletion(base_vha);
3740
726b8548
QT		 3741 /*
3742 * if UNLOAD flag is already set, then continue unload,
783e0dc4
SC		 3743 * where it was set first.
3744 */
3745 if (test_bit(UNLOADING, &base_vha->dpc_flags))
3746 return;
3747
fe1b806f 3748 set_bit(UNLOADING, &base_vha->dpc_flags);
e84067d7
DG		 3749
3750 qla_nvme_delete(base_vha);
3751
726b8548
QT		 3752 dma_free_coherent(&ha->pdev->dev,
3753 base_vha->gnl.size, base_vha->gnl.l, base_vha->gnl.ldma);
fe1b806f 3754
a4239945
QT		 3755 vfree(base_vha->scan.l);
3756
fe1b806f
CD		 3757 if (IS_QLAFX00(ha))
3758 qlafx00_driver_shutdown(base_vha, 20);
3759
3760 qla2x00_delete_all_vps(ha, base_vha);
3761
fe1b806f
CD		 3762 qla2x00_dfs_remove(base_vha);
3763
3764 qla84xx_put_chip(base_vha);
3765
3766 /* Disable timer */
3767 if (base_vha->timer_active)
3768 qla2x00_stop_timer(base_vha);
3769
3770 base_vha->flags.online = 0;
3771
b0d6cabd
HM		 3772 /* free DMA memory */
3773 if (ha->exlogin_buf)
3774 qla2x00_free_exlogin_buffer(ha);
3775
2f56a7f1
HM		 3776 /* free DMA memory */
3777 if (ha->exchoffld_buf)
3778 qla2x00_free_exchoffld_buffer(ha);
3779
fe1b806f
CD		 3780 qla2x00_destroy_deferred_work(ha);
3781
3782 qlt_remove_target(ha, base_vha);
3783
3784 qla2x00_free_sysfs_attr(base_vha, true);
3785
3786 fc_remove_host(base_vha->host);
482c9dc7 3787 qlt_remove_target_resources(ha);
fe1b806f
CD		 3788
3789 scsi_remove_host(base_vha->host);
3790
3791 qla2x00_free_device(base_vha);
3792
db7157d4 3793 qla2x00_clear_drv_active(ha);
fe1b806f 3794
d2749ffa
AE		 3795 scsi_host_put(base_vha->host);
3796
fe1b806f 3797 qla2x00_unmap_iobases(ha);
73208dfd 3798
e315cd28
AC		 3799 pci_release_selected_regions(ha->pdev, ha->bars);
3800 kfree(ha);
1da177e4 3801
90a86fc0
JC		 3802 pci_disable_pcie_error_reporting(pdev);
3803
665db93b 3804 pci_disable_device(pdev);
1da177e4 3805}
1da177e4
LT		 3806
3807static void
e315cd28 3808qla2x00_free_device(scsi_qla_host_t *vha)
1da177e4 3809{
e315cd28 3810 struct qla_hw_data *ha = vha->hw;
1da177e4 3811
85880801
AV		 3812 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
3813
3814 /* Disable timer */
3815 if (vha->timer_active)
3816 qla2x00_stop_timer(vha);
3817
2afa19a9 3818 qla25xx_delete_queues(vha);
85880801
AV		 3819 vha->flags.online = 0;
3820
f6ef3b18 3821 /* turn-off interrupts on the card */
a9083016
GM		 3822 if (ha->interrupts_on) {
3823 vha->flags.init_done = 0;
fd34f556 3824 ha->isp_ops->disable_intrs(ha);
a9083016 3825 }
f6ef3b18 3826
093df737
QT		 3827 qla2x00_free_fcports(vha);
3828
e315cd28 3829 qla2x00_free_irqs(vha);
1da177e4 3830
093df737
QT		 3831 /* Flush the work queue and remove it */
3832 if (ha->wq) {
3833 flush_workqueue(ha->wq);
3834 destroy_workqueue(ha->wq);
3835 ha->wq = NULL;
3836 }
3837
8867048b 3838
e315cd28 3839 qla2x00_mem_free(ha);
73208dfd 3840
08de2844
GM		 3841 qla82xx_md_free(vha);
3842
73208dfd 3843 qla2x00_free_queues(ha);
1da177e4
LT		 3844}
3845
8867048b
CD		 3846void qla2x00_free_fcports(struct scsi_qla_host *vha)
3847{
3848 fc_port_t *fcport, *tfcport;
3849
ffbc6476
QT		 3850 list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list)
3851 qla2x00_free_fcport(fcport);
8867048b
CD		 3852}
3853
d97994dc 3854static inline void
e315cd28 3855qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport,
d97994dc 3856 int defer)
3857{
d97994dc 3858 struct fc_rport *rport;
67becc00 3859 scsi_qla_host_t *base_vha;
044d78e1 3860 unsigned long flags;
d97994dc 3861
3862 if (!fcport->rport)
3863 return;
3864
3865 rport = fcport->rport;
3866 if (defer) {
67becc00 3867 base_vha = pci_get_drvdata(vha->hw->pdev);
044d78e1 3868 spin_lock_irqsave(vha->host->host_lock, flags);
d97994dc 3869 fcport->drport = rport;
044d78e1 3870 spin_unlock_irqrestore(vha->host->host_lock, flags);
df673274 3871 qlt_do_generation_tick(vha, &base_vha->total_fcport_update_gen);
67becc00
AV		 3872 set_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags);
3873 qla2xxx_wake_dpc(base_vha);
2d70c103 3874 } else {
df673274 3875 int now;
bd432bb5 3876
726b8548 3877 if (rport) {
83548fe2
QT		 3878 ql_dbg(ql_dbg_disc, fcport->vha, 0x2109,
3879 "%s %8phN. rport %p roles %x\n",
3880 __func__, fcport->port_name, rport,
3881 rport->roles);
d20ed91b 3882 fc_remote_port_delete(rport);
726b8548 3883 }
df673274 3884 qlt_do_generation_tick(vha, &now);
2d70c103 3885 }
d97994dc 3886}
3887
1da177e4
LT		 3888/*
3889 * qla2x00_mark_device_lost Updates fcport state when device goes offline.
3890 *
3891 * Input: ha = adapter block pointer. fcport = port structure pointer.
3892 *
3893 * Return: None.
3894 *
3895 * Context:
3896 */
e315cd28 3897void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport,
d97994dc 3898 int do_login, int defer)
1da177e4 3899{
8ae6d9c7
GM		 3900 if (IS_QLAFX00(vha->hw)) {
3901 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
3902 qla2x00_schedule_rport_del(vha, fcport, defer);
3903 return;
3904 }
3905
2c3dfe3f 3906 if (atomic_read(&fcport->state) == FCS_ONLINE &&
c6d39e23 3907 vha->vp_idx == fcport->vha->vp_idx) {
ec426e10 3908 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
e315cd28
AC		 3909 qla2x00_schedule_rport_del(vha, fcport, defer);
3910 }
fa2a1ce5 3911 /*
1da177e4
LT		 3912 * We may need to retry the login, so don't change the state of the
3913 * port but do the retries.
3914 */
3915 if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD)
ec426e10 3916 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
1da177e4
LT		 3917
3918 if (!do_login)
3919 return;
3920
a1d0285e 3921 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
1da177e4
LT		 3922}
3923
3924/*
3925 * qla2x00_mark_all_devices_lost
3926 * Updates fcport state when device goes offline.
3927 *
3928 * Input:
3929 * ha = adapter block pointer.
3930 * fcport = port structure pointer.
3931 *
3932 * Return:
3933 * None.
3934 *
3935 * Context:
3936 */
3937void
e315cd28 3938qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha, int defer)
1da177e4
LT		 3939{
3940 fc_port_t *fcport;
3941
83548fe2
QT		 3942 ql_dbg(ql_dbg_disc, vha, 0x20f1,
3943 "Mark all dev lost\n");
726b8548 3944
e315cd28 3945 list_for_each_entry(fcport, &vha->vp_fcports, list) {
726b8548 3946 fcport->scan_state = 0;
d8630bb9 3947 qlt_schedule_sess_for_deletion(fcport);
726b8548 3948
c6d39e23 3949 if (vha->vp_idx != 0 && vha->vp_idx != fcport->vha->vp_idx)
1da177e4 3950 continue;
0d6e61bc 3951
1da177e4
LT		 3952 /*
3953 * No point in marking the device as lost, if the device is
3954 * already DEAD.
3955 */
3956 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD)
3957 continue;
e315cd28 3958 if (atomic_read(&fcport->state) == FCS_ONLINE) {
ec426e10 3959 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
0d6e61bc
AV		 3960 if (defer)
3961 qla2x00_schedule_rport_del(vha, fcport, defer);
c6d39e23 3962 else if (vha->vp_idx == fcport->vha->vp_idx)
0d6e61bc
AV		 3963 qla2x00_schedule_rport_del(vha, fcport, defer);
3964 }
1da177e4
LT		 3965 }
3966}
3967
0e145a59
BVA		 3968static void qla2x00_set_reserved_loop_ids(struct qla_hw_data *ha)
3969{
3970 int i;
3971
3972 if (IS_FWI2_CAPABLE(ha))
3973 return;
3974
3975 for (i = 0; i < SNS_FIRST_LOOP_ID; i++)
3976 set_bit(i, ha->loop_id_map);
3977 set_bit(MANAGEMENT_SERVER, ha->loop_id_map);
3978 set_bit(BROADCAST, ha->loop_id_map);
3979}
3980
1da177e4
LT		 3981/*
3982* qla2x00_mem_alloc
3983* Allocates adapter memory.
3984*
3985* Returns:
3986* 0 = success.
e8711085 3987* !0 = failure.
1da177e4 3988*/
e8711085 3989static int
73208dfd
AC		 3990qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len,
3991 struct req_que **req, struct rsp_que **rsp)
1da177e4
LT		 3992{
3993 char name[16];
1da177e4 3994
e8711085 3995 ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size,
e315cd28 3996 &ha->init_cb_dma, GFP_KERNEL);
e8711085 3997 if (!ha->init_cb)
e315cd28 3998 goto fail;
e8711085 3999
2d70c103
NB		 4000 if (qlt_mem_alloc(ha) < 0)
4001 goto fail_free_init_cb;
4002
642ef983
CD		 4003 ha->gid_list = dma_alloc_coherent(&ha->pdev->dev,
4004 qla2x00_gid_list_size(ha), &ha->gid_list_dma, GFP_KERNEL);
e315cd28 4005 if (!ha->gid_list)
2d70c103 4006 goto fail_free_tgt_mem;
1da177e4 4007
e8711085
AV		 4008 ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep);
4009 if (!ha->srb_mempool)
e315cd28 4010 goto fail_free_gid_list;
e8711085 4011
7ec0effd 4012 if (IS_P3P_TYPE(ha)) {
a9083016
GM		 4013 /* Allocate cache for CT6 Ctx. */
4014 if (!ctx_cachep) {
4015 ctx_cachep = kmem_cache_create("qla2xxx_ctx",
4016 sizeof(struct ct6_dsd), 0,
4017 SLAB_HWCACHE_ALIGN, NULL);
4018 if (!ctx_cachep)
fc1ffd6c 4019 goto fail_free_srb_mempool;
a9083016
GM		 4020 }
4021 ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ,
4022 ctx_cachep);
4023 if (!ha->ctx_mempool)
4024 goto fail_free_srb_mempool;
7c3df132
SK		 4025 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021,
4026 "ctx_cachep=%p ctx_mempool=%p.\n",
4027 ctx_cachep, ha->ctx_mempool);
a9083016
GM		 4028 }
4029
e8711085
AV		 4030 /* Get memory for cached NVRAM */
4031 ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL);
4032 if (!ha->nvram)
a9083016 4033 goto fail_free_ctx_mempool;
e8711085 4034
e315cd28
AC		 4035 snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME,
4036 ha->pdev->device);
4037 ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev,
4038 DMA_POOL_SIZE, 8, 0);
4039 if (!ha->s_dma_pool)
4040 goto fail_free_nvram;
4041
7c3df132
SK		 4042 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022,
4043 "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n",
4044 ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool);
4045
7ec0effd 4046 if (IS_P3P_TYPE(ha) || ql2xenabledif) {
a9083016
GM		 4047 ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev,
4048 DSD_LIST_DMA_POOL_SIZE, 8, 0);
4049 if (!ha->dl_dma_pool) {
7c3df132
SK		 4050 ql_log_pci(ql_log_fatal, ha->pdev, 0x0023,
4051 "Failed to allocate memory for dl_dma_pool.\n");
a9083016
GM		 4052 goto fail_s_dma_pool;
4053 }
4054
4055 ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev,
4056 FCP_CMND_DMA_POOL_SIZE, 8, 0);
4057 if (!ha->fcp_cmnd_dma_pool) {
7c3df132
SK		 4058 ql_log_pci(ql_log_fatal, ha->pdev, 0x0024,
4059 "Failed to allocate memory for fcp_cmnd_dma_pool.\n");
a9083016
GM		 4060 goto fail_dl_dma_pool;
4061 }
50b81275
GM		 4062
4063 if (ql2xenabledif) {
4064 u64 bufsize = DIF_BUNDLING_DMA_POOL_SIZE;
4065 struct dsd_dma *dsd, *nxt;
4066 uint i;
4067 /* Creata a DMA pool of buffers for DIF bundling */
4068 ha->dif_bundl_pool = dma_pool_create(name,
4069 &ha->pdev->dev, DIF_BUNDLING_DMA_POOL_SIZE, 8, 0);
4070 if (!ha->dif_bundl_pool) {
4071 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0024,
4072 "%s: failed create dif_bundl_pool\n",
4073 __func__);
4074 goto fail_dif_bundl_dma_pool;
4075 }
4076
4077 INIT_LIST_HEAD(&ha->pool.good.head);
4078 INIT_LIST_HEAD(&ha->pool.unusable.head);
4079 ha->pool.good.count = 0;
4080 ha->pool.unusable.count = 0;
4081 for (i = 0; i < 128; i++) {
4082 dsd = kzalloc(sizeof(*dsd), GFP_ATOMIC);
4083 if (!dsd) {
4084 ql_dbg_pci(ql_dbg_init, ha->pdev,
4085 0xe0ee, "%s: failed alloc dsd\n",
4086 __func__);
4087 return 1;
4088 }
4089 ha->dif_bundle_kallocs++;
4090
4091 dsd->dsd_addr = dma_pool_alloc(
4092 ha->dif_bundl_pool, GFP_ATOMIC,
4093 &dsd->dsd_list_dma);
4094 if (!dsd->dsd_addr) {
4095 ql_dbg_pci(ql_dbg_init, ha->pdev,
4096 0xe0ee,
4097 "%s: failed alloc ->dsd_addr\n",
4098 __func__);
4099 kfree(dsd);
4100 ha->dif_bundle_kallocs--;
4101 continue;
4102 }
4103 ha->dif_bundle_dma_allocs++;
4104
4105 /*
4106 * if DMA buffer crosses 4G boundary,
4107 * put it on bad list
4108 */
4109 if (MSD(dsd->dsd_list_dma) ^
4110 MSD(dsd->dsd_list_dma + bufsize)) {
4111 list_add_tail(&dsd->list,
4112 &ha->pool.unusable.head);
4113 ha->pool.unusable.count++;
4114 } else {
4115 list_add_tail(&dsd->list,
4116 &ha->pool.good.head);
4117 ha->pool.good.count++;
4118 }
4119 }
4120
4121 /* return the good ones back to the pool */
4122 list_for_each_entry_safe(dsd, nxt,
4123 &ha->pool.good.head, list) {
4124 list_del(&dsd->list);
4125 dma_pool_free(ha->dif_bundl_pool,
4126 dsd->dsd_addr, dsd->dsd_list_dma);
4127 ha->dif_bundle_dma_allocs--;
4128 kfree(dsd);
4129 ha->dif_bundle_kallocs--;
4130 }
4131
4132 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0024,
4133 "%s: dif dma pool (good=%u unusable=%u)\n",
4134 __func__, ha->pool.good.count,
4135 ha->pool.unusable.count);
4136 }
4137
7c3df132 4138 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025,
50b81275
GM		 4139 "dl_dma_pool=%p fcp_cmnd_dma_pool=%p dif_bundl_pool=%p.\n",
4140 ha->dl_dma_pool, ha->fcp_cmnd_dma_pool,
4141 ha->dif_bundl_pool);
a9083016
GM		 4142 }
4143
e8711085
AV		 4144 /* Allocate memory for SNS commands */
4145 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
e315cd28 4146 /* Get consistent memory allocated for SNS commands */
e8711085 4147 ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev,
e315cd28 4148 sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL);
e8711085 4149 if (!ha->sns_cmd)
e315cd28 4150 goto fail_dma_pool;
7c3df132 4151 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026,
d8424f68 4152 "sns_cmd: %p.\n", ha->sns_cmd);
e8711085 4153 } else {
e315cd28 4154 /* Get consistent memory allocated for MS IOCB */
e8711085 4155 ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
e315cd28 4156 &ha->ms_iocb_dma);
e8711085 4157 if (!ha->ms_iocb)
e315cd28
AC		 4158 goto fail_dma_pool;
4159 /* Get consistent memory allocated for CT SNS commands */
e8711085 4160 ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev,
e315cd28 4161 sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL);
e8711085
AV		 4162 if (!ha->ct_sns)
4163 goto fail_free_ms_iocb;
7c3df132
SK		 4164 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027,
4165 "ms_iocb=%p ct_sns=%p.\n",
4166 ha->ms_iocb, ha->ct_sns);
1da177e4
LT		 4167 }
4168
e315cd28 4169 /* Allocate memory for request ring */
73208dfd
AC		 4170 *req = kzalloc(sizeof(struct req_que), GFP_KERNEL);
4171 if (!*req) {
7c3df132
SK		 4172 ql_log_pci(ql_log_fatal, ha->pdev, 0x0028,
4173 "Failed to allocate memory for req.\n");
e315cd28
AC		 4174 goto fail_req;
4175 }
73208dfd
AC		 4176 (*req)->length = req_len;
4177 (*req)->ring = dma_alloc_coherent(&ha->pdev->dev,
4178 ((*req)->length + 1) * sizeof(request_t),
4179 &(*req)->dma, GFP_KERNEL);
4180 if (!(*req)->ring) {
7c3df132
SK		 4181 ql_log_pci(ql_log_fatal, ha->pdev, 0x0029,
4182 "Failed to allocate memory for req_ring.\n");
e315cd28
AC		 4183 goto fail_req_ring;
4184 }
4185 /* Allocate memory for response ring */
73208dfd
AC		 4186 *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL);
4187 if (!*rsp) {
7c3df132
SK		 4188 ql_log_pci(ql_log_fatal, ha->pdev, 0x002a,
4189 "Failed to allocate memory for rsp.\n");
e315cd28
AC		 4190 goto fail_rsp;
4191 }
73208dfd
AC		 4192 (*rsp)->hw = ha;
4193 (*rsp)->length = rsp_len;
4194 (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev,
4195 ((*rsp)->length + 1) * sizeof(response_t),
4196 &(*rsp)->dma, GFP_KERNEL);
4197 if (!(*rsp)->ring) {
7c3df132
SK		 4198 ql_log_pci(ql_log_fatal, ha->pdev, 0x002b,
4199 "Failed to allocate memory for rsp_ring.\n");
e315cd28
AC		 4200 goto fail_rsp_ring;
4201 }
73208dfd
AC		 4202 (*req)->rsp = *rsp;
4203 (*rsp)->req = *req;
7c3df132
SK		 4204 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c,
4205 "req=%p req->length=%d req->ring=%p rsp=%p "
4206 "rsp->length=%d rsp->ring=%p.\n",
4207 *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length,
4208 (*rsp)->ring);
73208dfd
AC		 4209 /* Allocate memory for NVRAM data for vports */
4210 if (ha->nvram_npiv_size) {
6396bb22
KC		 4211 ha->npiv_info = kcalloc(ha->nvram_npiv_size,
4212 sizeof(struct qla_npiv_entry),
4213 GFP_KERNEL);
73208dfd 4214 if (!ha->npiv_info) {
7c3df132
SK		 4215 ql_log_pci(ql_log_fatal, ha->pdev, 0x002d,
4216 "Failed to allocate memory for npiv_info.\n");
73208dfd
AC		 4217 goto fail_npiv_info;
4218 }
4219 } else
4220 ha->npiv_info = NULL;
e8711085 4221
b64b0e8f 4222 /* Get consistent memory allocated for EX-INIT-CB. */
ecc89f25
JC		 4223 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) ||
4224 IS_QLA28XX(ha)) {
b64b0e8f
AV		 4225 ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
4226 &ha->ex_init_cb_dma);
4227 if (!ha->ex_init_cb)
4228 goto fail_ex_init_cb;
7c3df132
SK		 4229 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e,
4230 "ex_init_cb=%p.\n", ha->ex_init_cb);
b64b0e8f
AV		 4231 }
4232
a9083016
GM		 4233 INIT_LIST_HEAD(&ha->gbl_dsd_list);
4234
5ff1d584
AV		 4235 /* Get consistent memory allocated for Async Port-Database. */
4236 if (!IS_FWI2_CAPABLE(ha)) {
4237 ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
4238 &ha->async_pd_dma);
4239 if (!ha->async_pd)
4240 goto fail_async_pd;
7c3df132
SK		 4241 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f,
4242 "async_pd=%p.\n", ha->async_pd);
5ff1d584
AV		 4243 }
4244
e315cd28 4245 INIT_LIST_HEAD(&ha->vp_list);
5f16b331
CD		 4246
4247 /* Allocate memory for our loop_id bitmap */
6396bb22
KC		 4248 ha->loop_id_map = kcalloc(BITS_TO_LONGS(LOOPID_MAP_SIZE),
4249 sizeof(long),
4250 GFP_KERNEL);
5f16b331 4251 if (!ha->loop_id_map)
fc1ffd6c 4252 goto fail_loop_id_map;
5f16b331
CD		 4253 else {
4254 qla2x00_set_reserved_loop_ids(ha);
4255 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0123,
b2a72ec3 4256 "loop_id_map=%p.\n", ha->loop_id_map);
5f16b331
CD		 4257 }
4258
e4e3a2ce
QT		 4259 ha->sfp_data = dma_alloc_coherent(&ha->pdev->dev,
4260 SFP_DEV_SIZE, &ha->sfp_data_dma, GFP_KERNEL);
4261 if (!ha->sfp_data) {
4262 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b,
4263 "Unable to allocate memory for SFP read-data.\n");
4264 goto fail_sfp_data;
4265 }
4266
3f006ac3
MH		 4267 ha->flt = dma_alloc_coherent(&ha->pdev->dev,
4268 sizeof(struct qla_flt_header) + FLT_REGIONS_SIZE, &ha->flt_dma,
4269 GFP_KERNEL);
4270 if (!ha->flt) {
4271 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b,
4272 "Unable to allocate memory for FLT.\n");
4273 goto fail_flt_buffer;
4274 }
4275
b2a72ec3 4276 return 0;
e315cd28 4277
3f006ac3
MH		 4278fail_flt_buffer:
4279 dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE,
4280 ha->sfp_data, ha->sfp_data_dma);
e4e3a2ce
QT		 4281fail_sfp_data:
4282 kfree(ha->loop_id_map);
fc1ffd6c
QT		 4283fail_loop_id_map:
4284 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
5ff1d584
AV		 4285fail_async_pd:
4286 dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma);
b64b0e8f
AV		 4287fail_ex_init_cb:
4288 kfree(ha->npiv_info);
73208dfd
AC		 4289fail_npiv_info:
4290 dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) *
4291 sizeof(response_t), (*rsp)->ring, (*rsp)->dma);
4292 (*rsp)->ring = NULL;
4293 (*rsp)->dma = 0;
e315cd28 4294fail_rsp_ring:
73208dfd 4295 kfree(*rsp);
6d634067 4296 *rsp = NULL;
e315cd28 4297fail_rsp:
73208dfd
AC		 4298 dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) *
4299 sizeof(request_t), (*req)->ring, (*req)->dma);
4300 (*req)->ring = NULL;
4301 (*req)->dma = 0;
e315cd28 4302fail_req_ring:
73208dfd 4303 kfree(*req);
6d634067 4304 *req = NULL;
e315cd28
AC		 4305fail_req:
4306 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
4307 ha->ct_sns, ha->ct_sns_dma);
4308 ha->ct_sns = NULL;
4309 ha->ct_sns_dma = 0;
e8711085
AV		 4310fail_free_ms_iocb:
4311 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
4312 ha->ms_iocb = NULL;
4313 ha->ms_iocb_dma = 0;
fc1ffd6c
QT		 4314
4315 if (ha->sns_cmd)
4316 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
4317 ha->sns_cmd, ha->sns_cmd_dma);
e315cd28 4318fail_dma_pool:
50b81275
GM		 4319 if (ql2xenabledif) {
4320 struct dsd_dma *dsd, *nxt;
4321
4322 list_for_each_entry_safe(dsd, nxt, &ha->pool.unusable.head,
4323 list) {
4324 list_del(&dsd->list);
4325 dma_pool_free(ha->dif_bundl_pool, dsd->dsd_addr,
4326 dsd->dsd_list_dma);
4327 ha->dif_bundle_dma_allocs--;
4328 kfree(dsd);
4329 ha->dif_bundle_kallocs--;
4330 ha->pool.unusable.count--;
4331 }
4332 dma_pool_destroy(ha->dif_bundl_pool);
4333 ha->dif_bundl_pool = NULL;
4334 }
4335
4336fail_dif_bundl_dma_pool:
bad75002 4337 if (IS_QLA82XX(ha) || ql2xenabledif) {
a9083016
GM		 4338 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
4339 ha->fcp_cmnd_dma_pool = NULL;
4340 }
4341fail_dl_dma_pool:
bad75002 4342 if (IS_QLA82XX(ha) || ql2xenabledif) {
a9083016
GM		 4343 dma_pool_destroy(ha->dl_dma_pool);
4344 ha->dl_dma_pool = NULL;
4345 }
4346fail_s_dma_pool:
e315cd28
AC		 4347 dma_pool_destroy(ha->s_dma_pool);
4348 ha->s_dma_pool = NULL;
e8711085
AV		 4349fail_free_nvram:
4350 kfree(ha->nvram);
4351 ha->nvram = NULL;
a9083016 4352fail_free_ctx_mempool:
75c1d48a 4353 mempool_destroy(ha->ctx_mempool);
a9083016 4354 ha->ctx_mempool = NULL;
e8711085 4355fail_free_srb_mempool:
75c1d48a 4356 mempool_destroy(ha->srb_mempool);
e8711085 4357 ha->srb_mempool = NULL;
e8711085 4358fail_free_gid_list:
642ef983
CD		 4359 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
4360 ha->gid_list,
e315cd28 4361 ha->gid_list_dma);
e8711085
AV		 4362 ha->gid_list = NULL;
4363 ha->gid_list_dma = 0;
2d70c103
NB		 4364fail_free_tgt_mem:
4365 qlt_mem_free(ha);
e315cd28
AC		 4366fail_free_init_cb:
4367 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb,
4368 ha->init_cb_dma);
4369 ha->init_cb = NULL;
4370 ha->init_cb_dma = 0;
e8711085 4371fail:
7c3df132
SK		 4372 ql_log(ql_log_fatal, NULL, 0x0030,
4373 "Memory allocation failure.\n");
e8711085 4374 return -ENOMEM;
1da177e4
LT		 4375}
4376
b0d6cabd
HM		 4377int
4378qla2x00_set_exlogins_buffer(scsi_qla_host_t *vha)
4379{
4380 int rval;
4381 uint16_t size, max_cnt, temp;
4382 struct qla_hw_data *ha = vha->hw;
4383
4384 /* Return if we don't need to alloacate any extended logins */
4385 if (!ql2xexlogins)
4386 return QLA_SUCCESS;
4387
99e1b683
QT		 4388 if (!IS_EXLOGIN_OFFLD_CAPABLE(ha))
4389 return QLA_SUCCESS;
4390
b0d6cabd
HM		 4391 ql_log(ql_log_info, vha, 0xd021, "EXLOGIN count: %d.\n", ql2xexlogins);
4392 max_cnt = 0;
4393 rval = qla_get_exlogin_status(vha, &size, &max_cnt);
4394 if (rval != QLA_SUCCESS) {
4395 ql_log_pci(ql_log_fatal, ha->pdev, 0xd029,
4396 "Failed to get exlogin status.\n");
4397 return rval;
4398 }
4399
4400 temp = (ql2xexlogins > max_cnt) ? max_cnt : ql2xexlogins;
99e1b683
QT		 4401 temp *= size;
4402
4403 if (temp != ha->exlogin_size) {
4404 qla2x00_free_exlogin_buffer(ha);
4405 ha->exlogin_size = temp;
4406
4407 ql_log(ql_log_info, vha, 0xd024,
4408 "EXLOGIN: max_logins=%d, portdb=0x%x, total=%d.\n",
4409 max_cnt, size, temp);
4410
4411 ql_log(ql_log_info, vha, 0xd025,
4412 "EXLOGIN: requested size=0x%x\n", ha->exlogin_size);
4413
4414 /* Get consistent memory for extended logins */
4415 ha->exlogin_buf = dma_alloc_coherent(&ha->pdev->dev,
4416 ha->exlogin_size, &ha->exlogin_buf_dma, GFP_KERNEL);
4417 if (!ha->exlogin_buf) {
4418 ql_log_pci(ql_log_fatal, ha->pdev, 0xd02a,
b0d6cabd 4419 "Failed to allocate memory for exlogin_buf_dma.\n");
99e1b683
QT		 4420 return -ENOMEM;
4421 }
b0d6cabd
HM		 4422 }
4423
4424 /* Now configure the dma buffer */
4425 rval = qla_set_exlogin_mem_cfg(vha, ha->exlogin_buf_dma);
4426 if (rval) {
83548fe2 4427 ql_log(ql_log_fatal, vha, 0xd033,
b0d6cabd
HM		 4428 "Setup extended login buffer ****FAILED****.\n");
4429 qla2x00_free_exlogin_buffer(ha);
4430 }
4431
4432 return rval;
4433}
4434
4435/*
4436* qla2x00_free_exlogin_buffer
4437*
4438* Input:
4439* ha = adapter block pointer
4440*/
4441void
4442qla2x00_free_exlogin_buffer(struct qla_hw_data *ha)
4443{
4444 if (ha->exlogin_buf) {
4445 dma_free_coherent(&ha->pdev->dev, ha->exlogin_size,
4446 ha->exlogin_buf, ha->exlogin_buf_dma);
4447 ha->exlogin_buf = NULL;
4448 ha->exlogin_size = 0;
4449 }
4450}
4451
99e1b683
QT		 4452static void
4453qla2x00_number_of_exch(scsi_qla_host_t *vha, u32 *ret_cnt, u16 max_cnt)
4454{
4455 u32 temp;
0645cb83 4456 struct init_cb_81xx *icb = (struct init_cb_81xx *)&vha->hw->init_cb;
99e1b683
QT		 4457 *ret_cnt = FW_DEF_EXCHANGES_CNT;
4458
d1e3635a
QT		 4459 if (max_cnt > vha->hw->max_exchg)
4460 max_cnt = vha->hw->max_exchg;
4461
99e1b683 4462 if (qla_ini_mode_enabled(vha)) {
0645cb83
QT		 4463 if (vha->ql2xiniexchg > max_cnt)
4464 vha->ql2xiniexchg = max_cnt;
4465
4466 if (vha->ql2xiniexchg > FW_DEF_EXCHANGES_CNT)
4467 *ret_cnt = vha->ql2xiniexchg;
99e1b683 4468
99e1b683 4469 } else if (qla_tgt_mode_enabled(vha)) {
0645cb83
QT		 4470 if (vha->ql2xexchoffld > max_cnt) {
4471 vha->ql2xexchoffld = max_cnt;
4472 icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld);
4473 }
99e1b683 4474
0645cb83
QT		 4475 if (vha->ql2xexchoffld > FW_DEF_EXCHANGES_CNT)
4476 *ret_cnt = vha->ql2xexchoffld;
99e1b683 4477 } else if (qla_dual_mode_enabled(vha)) {
0645cb83 4478 temp = vha->ql2xiniexchg + vha->ql2xexchoffld;
99e1b683 4479 if (temp > max_cnt) {
0645cb83
QT		 4480 vha->ql2xiniexchg -= (temp - max_cnt)/2;
4481 vha->ql2xexchoffld -= (((temp - max_cnt)/2) + 1);
99e1b683 4482 temp = max_cnt;
0645cb83 4483 icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld);
99e1b683
QT		 4484 }
4485
4486 if (temp > FW_DEF_EXCHANGES_CNT)
4487 *ret_cnt = temp;
4488 }
4489}
4490
2f56a7f1
HM		 4491int
4492qla2x00_set_exchoffld_buffer(scsi_qla_host_t *vha)
4493{
4494 int rval;
d1e3635a
QT		 4495 u16 size, max_cnt;
4496 u32 actual_cnt, totsz;
2f56a7f1
HM		 4497 struct qla_hw_data *ha = vha->hw;
4498
99e1b683
QT		 4499 if (!ha->flags.exchoffld_enabled)
4500 return QLA_SUCCESS;
4501
4502 if (!IS_EXCHG_OFFLD_CAPABLE(ha))
2f56a7f1
HM		 4503 return QLA_SUCCESS;
4504
2f56a7f1
HM		 4505 max_cnt = 0;
4506 rval = qla_get_exchoffld_status(vha, &size, &max_cnt);
4507 if (rval != QLA_SUCCESS) {
4508 ql_log_pci(ql_log_fatal, ha->pdev, 0xd012,
4509 "Failed to get exlogin status.\n");
4510 return rval;
4511 }
4512
d1e3635a
QT		 4513 qla2x00_number_of_exch(vha, &actual_cnt, max_cnt);
4514 ql_log(ql_log_info, vha, 0xd014,
4515 "Actual exchange offload count: %d.\n", actual_cnt);
4516
4517 totsz = actual_cnt * size;
2f56a7f1 4518
d1e3635a 4519 if (totsz != ha->exchoffld_size) {
99e1b683 4520 qla2x00_free_exchoffld_buffer(ha);
0645cb83
QT		 4521 if (actual_cnt <= FW_DEF_EXCHANGES_CNT) {
4522 ha->exchoffld_size = 0;
4523 ha->flags.exchoffld_enabled = 0;
4524 return QLA_SUCCESS;
4525 }
4526
d1e3635a 4527 ha->exchoffld_size = totsz;
99e1b683
QT		 4528
4529 ql_log(ql_log_info, vha, 0xd016,
d1e3635a
QT		 4530 "Exchange offload: max_count=%d, actual count=%d entry sz=0x%x, total sz=0x%x\n",
4531 max_cnt, actual_cnt, size, totsz);
99e1b683
QT		 4532
4533 ql_log(ql_log_info, vha, 0xd017,
4534 "Exchange Buffers requested size = 0x%x\n",
4535 ha->exchoffld_size);
4536
4537 /* Get consistent memory for extended logins */
4538 ha->exchoffld_buf = dma_alloc_coherent(&ha->pdev->dev,
4539 ha->exchoffld_size, &ha->exchoffld_buf_dma, GFP_KERNEL);
4540 if (!ha->exchoffld_buf) {
4541 ql_log_pci(ql_log_fatal, ha->pdev, 0xd013,
d1e3635a
QT		 4542 "Failed to allocate memory for Exchange Offload.\n");
4543
4544 if (ha->max_exchg >
4545 (FW_DEF_EXCHANGES_CNT + REDUCE_EXCHANGES_CNT)) {
4546 ha->max_exchg -= REDUCE_EXCHANGES_CNT;
4547 } else if (ha->max_exchg >
4548 (FW_DEF_EXCHANGES_CNT + 512)) {
4549 ha->max_exchg -= 512;
4550 } else {
4551 ha->flags.exchoffld_enabled = 0;
4552 ql_log_pci(ql_log_fatal, ha->pdev, 0xd013,
4553 "Disabling Exchange offload due to lack of memory\n");
4554 }
4555 ha->exchoffld_size = 0;
4556
99e1b683
QT		 4557 return -ENOMEM;
4558 }
0645cb83
QT		 4559 } else if (!ha->exchoffld_buf || (actual_cnt <= FW_DEF_EXCHANGES_CNT)) {
4560 /* pathological case */
4561 qla2x00_free_exchoffld_buffer(ha);
4562 ha->exchoffld_size = 0;
4563 ha->flags.exchoffld_enabled = 0;
4564 ql_log(ql_log_info, vha, 0xd016,
4565 "Exchange offload not enable: offld size=%d, actual count=%d entry sz=0x%x, total sz=0x%x.\n",
4566 ha->exchoffld_size, actual_cnt, size, totsz);
4567 return 0;
2f56a7f1
HM		 4568 }
4569
4570 /* Now configure the dma buffer */
99e1b683 4571 rval = qla_set_exchoffld_mem_cfg(vha);
2f56a7f1
HM		 4572 if (rval) {
4573 ql_log(ql_log_fatal, vha, 0xd02e,
4574 "Setup exchange offload buffer ****FAILED****.\n");
4575 qla2x00_free_exchoffld_buffer(ha);
99e1b683
QT		 4576 } else {
4577 /* re-adjust number of target exchange */
4578 struct init_cb_81xx *icb = (struct init_cb_81xx *)ha->init_cb;
4579
4580 if (qla_ini_mode_enabled(vha))
4581 icb->exchange_count = 0;
4582 else
0645cb83 4583 icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld);
2f56a7f1
HM		 4584 }
4585
4586 return rval;
4587}
4588
4589/*
4590* qla2x00_free_exchoffld_buffer
4591*
4592* Input:
4593* ha = adapter block pointer
4594*/
4595void
4596qla2x00_free_exchoffld_buffer(struct qla_hw_data *ha)
4597{
4598 if (ha->exchoffld_buf) {
4599 dma_free_coherent(&ha->pdev->dev, ha->exchoffld_size,
4600 ha->exchoffld_buf, ha->exchoffld_buf_dma);
4601 ha->exchoffld_buf = NULL;
4602 ha->exchoffld_size = 0;
4603 }
4604}
4605
1da177e4 4606/*
e30d1756
MI		 4607* qla2x00_free_fw_dump
4608* Frees fw dump stuff.
1da177e4
LT		 4609*
4610* Input:
7ec0effd 4611* ha = adapter block pointer
1da177e4 4612*/
a824ebb3 4613static void
e30d1756 4614qla2x00_free_fw_dump(struct qla_hw_data *ha)
1da177e4 4615{
a28d9e4e
JC		 4616 struct fwdt *fwdt = ha->fwdt;
4617 uint j;
4618
df613b96 4619 if (ha->fce)
f73cb695
CD		 4620 dma_free_coherent(&ha->pdev->dev,
4621 FCE_SIZE, ha->fce, ha->fce_dma);
df613b96 4622
f73cb695
CD		 4623 if (ha->eft)
4624 dma_free_coherent(&ha->pdev->dev,
4625 EFT_SIZE, ha->eft, ha->eft_dma);
4626
4627 if (ha->fw_dump)
a7a167bf 4628 vfree(ha->fw_dump);
f73cb695 4629
e30d1756
MI		 4630 ha->fce = NULL;
4631 ha->fce_dma = 0;
4632 ha->eft = NULL;
4633 ha->eft_dma = 0;
e30d1756 4634 ha->fw_dumped = 0;
61f098dd 4635 ha->fw_dump_cap_flags = 0;
e30d1756 4636 ha->fw_dump_reading = 0;
f73cb695
CD		 4637 ha->fw_dump = NULL;
4638 ha->fw_dump_len = 0;
a28d9e4e
JC		 4639
4640 for (j = 0; j < 2; j++, fwdt++) {
4641 if (fwdt->template)
4642 vfree(fwdt->template);
4643 fwdt->template = NULL;
4644 fwdt->length = 0;
4645 }
e30d1756
MI		 4646}
4647
4648/*
4649* qla2x00_mem_free
4650* Frees all adapter allocated memory.
4651*
4652* Input:
4653* ha = adapter block pointer.
4654*/
4655static void
4656qla2x00_mem_free(struct qla_hw_data *ha)
4657{
4658 qla2x00_free_fw_dump(ha);
4659
81178772
SK		 4660 if (ha->mctp_dump)
4661 dma_free_coherent(&ha->pdev->dev, MCTP_DUMP_SIZE, ha->mctp_dump,
4662 ha->mctp_dump_dma);
5365bf99 4663 ha->mctp_dump = NULL;
81178772 4664
75c1d48a 4665 mempool_destroy(ha->srb_mempool);
5365bf99 4666 ha->srb_mempool = NULL;
a7a167bf 4667
11bbc1d8
AV		 4668 if (ha->dcbx_tlv)
4669 dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE,
4670 ha->dcbx_tlv, ha->dcbx_tlv_dma);
5365bf99 4671 ha->dcbx_tlv = NULL;
11bbc1d8 4672
ce0423f4
AV		 4673 if (ha->xgmac_data)
4674 dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE,
4675 ha->xgmac_data, ha->xgmac_data_dma);
5365bf99 4676 ha->xgmac_data = NULL;
ce0423f4 4677
1da177e4
LT		 4678 if (ha->sns_cmd)
4679 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
e315cd28 4680 ha->sns_cmd, ha->sns_cmd_dma);
5365bf99
BVA		 4681 ha->sns_cmd = NULL;
4682 ha->sns_cmd_dma = 0;
1da177e4
LT		 4683
4684 if (ha->ct_sns)
4685 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
e315cd28 4686 ha->ct_sns, ha->ct_sns_dma);
5365bf99
BVA		 4687 ha->ct_sns = NULL;
4688 ha->ct_sns_dma = 0;
1da177e4 4689
88729e53 4690 if (ha->sfp_data)
e4e3a2ce
QT		 4691 dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE, ha->sfp_data,
4692 ha->sfp_data_dma);
5365bf99 4693 ha->sfp_data = NULL;
88729e53 4694
3f006ac3
MH		 4695 if (ha->flt)
4696 dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE,
4697 ha->flt, ha->flt_dma);
dc035d4e
BVA		 4698 ha->flt = NULL;
4699 ha->flt_dma = 0;
3f006ac3 4700
1da177e4
LT		 4701 if (ha->ms_iocb)
4702 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
5365bf99
BVA		 4703 ha->ms_iocb = NULL;
4704 ha->ms_iocb_dma = 0;
1da177e4 4705
b64b0e8f 4706 if (ha->ex_init_cb)
a9083016
GM		 4707 dma_pool_free(ha->s_dma_pool,
4708 ha->ex_init_cb, ha->ex_init_cb_dma);
5365bf99
BVA		 4709 ha->ex_init_cb = NULL;
4710 ha->ex_init_cb_dma = 0;
b64b0e8f 4711
5ff1d584
AV		 4712 if (ha->async_pd)
4713 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
5365bf99
BVA		 4714 ha->async_pd = NULL;
4715 ha->async_pd_dma = 0;
5ff1d584 4716
75c1d48a 4717 dma_pool_destroy(ha->s_dma_pool);
5365bf99 4718 ha->s_dma_pool = NULL;
1da177e4 4719
1da177e4 4720 if (ha->gid_list)
642ef983
CD		 4721 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
4722 ha->gid_list, ha->gid_list_dma);
5365bf99
BVA		 4723 ha->gid_list = NULL;
4724 ha->gid_list_dma = 0;
1da177e4 4725
a9083016
GM		 4726 if (IS_QLA82XX(ha)) {
4727 if (!list_empty(&ha->gbl_dsd_list)) {
4728 struct dsd_dma *dsd_ptr, *tdsd_ptr;
4729
4730 /* clean up allocated prev pool */
4731 list_for_each_entry_safe(dsd_ptr,
4732 tdsd_ptr, &ha->gbl_dsd_list, list) {
4733 dma_pool_free(ha->dl_dma_pool,
4734 dsd_ptr->dsd_addr, dsd_ptr->dsd_list_dma);
4735 list_del(&dsd_ptr->list);
4736 kfree(dsd_ptr);
4737 }
4738 }
4739 }
4740
75c1d48a 4741 dma_pool_destroy(ha->dl_dma_pool);
5365bf99 4742 ha->dl_dma_pool = NULL;
a9083016 4743
75c1d48a 4744 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
5365bf99 4745 ha->fcp_cmnd_dma_pool = NULL;
a9083016 4746
75c1d48a 4747 mempool_destroy(ha->ctx_mempool);
5365bf99 4748 ha->ctx_mempool = NULL;
a9083016 4749
26a77799 4750 if (ql2xenabledif && ha->dif_bundl_pool) {
50b81275
GM		 4751 struct dsd_dma *dsd, *nxt;
4752
4753 list_for_each_entry_safe(dsd, nxt, &ha->pool.unusable.head,
4754 list) {
4755 list_del(&dsd->list);
4756 dma_pool_free(ha->dif_bundl_pool, dsd->dsd_addr,
4757 dsd->dsd_list_dma);
4758 ha->dif_bundle_dma_allocs--;
4759 kfree(dsd);
4760 ha->dif_bundle_kallocs--;
4761 ha->pool.unusable.count--;
4762 }
4763 list_for_each_entry_safe(dsd, nxt, &ha->pool.good.head, list) {
4764 list_del(&dsd->list);
4765 dma_pool_free(ha->dif_bundl_pool, dsd->dsd_addr,
4766 dsd->dsd_list_dma);
4767 ha->dif_bundle_dma_allocs--;
4768 kfree(dsd);
4769 ha->dif_bundle_kallocs--;
4770 }
4771 }
4772
0b3b6fe2 4773 dma_pool_destroy(ha->dif_bundl_pool);
dc035d4e 4774 ha->dif_bundl_pool = NULL;
50b81275 4775
2d70c103
NB		 4776 qlt_mem_free(ha);
4777
e315cd28
AC		 4778 if (ha->init_cb)
4779 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size,
a9083016 4780 ha->init_cb, ha->init_cb_dma);
5365bf99
BVA		 4781 ha->init_cb = NULL;
4782 ha->init_cb_dma = 0;
6a2cf8d3 4783
6d634067 4784 vfree(ha->optrom_buffer);
5365bf99 4785 ha->optrom_buffer = NULL;
6d634067 4786 kfree(ha->nvram);
5365bf99 4787 ha->nvram = NULL;
6d634067 4788 kfree(ha->npiv_info);
5365bf99 4789 ha->npiv_info = NULL;
6d634067 4790 kfree(ha->swl);
5365bf99 4791 ha->swl = NULL;
6d634067 4792 kfree(ha->loop_id_map);
6a2cf8d3 4793 ha->loop_id_map = NULL;
e315cd28 4794}
1da177e4 4795
e315cd28
AC		 4796struct scsi_qla_host *qla2x00_create_host(struct scsi_host_template *sht,
4797 struct qla_hw_data *ha)
4798{
4799 struct Scsi_Host *host;
4800 struct scsi_qla_host *vha = NULL;
854165f4 4801
e315cd28 4802 host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t));
41dc529a 4803 if (!host) {
7c3df132
SK		 4804 ql_log_pci(ql_log_fatal, ha->pdev, 0x0107,
4805 "Failed to allocate host from the scsi layer, aborting.\n");
41dc529a 4806 return NULL;
e315cd28
AC		 4807 }
4808
4809 /* Clear our data area */
4810 vha = shost_priv(host);
4811 memset(vha, 0, sizeof(scsi_qla_host_t));
4812
4813 vha->host = host;
4814 vha->host_no = host->host_no;
4815 vha->hw = ha;
4816
0645cb83
QT		 4817 vha->qlini_mode = ql2x_ini_mode;
4818 vha->ql2xexchoffld = ql2xexchoffld;
4819 vha->ql2xiniexchg = ql2xiniexchg;
4820
e315cd28
AC		 4821 INIT_LIST_HEAD(&vha->vp_fcports);
4822 INIT_LIST_HEAD(&vha->work_list);
4823 INIT_LIST_HEAD(&vha->list);
8b2f5ff3
SN		 4824 INIT_LIST_HEAD(&vha->qla_cmd_list);
4825 INIT_LIST_HEAD(&vha->qla_sess_op_cmd_list);
71cdc079 4826 INIT_LIST_HEAD(&vha->logo_list);
b7bd104e 4827 INIT_LIST_HEAD(&vha->plogi_ack_list);
d7459527 4828 INIT_LIST_HEAD(&vha->qp_list);
41dc529a 4829 INIT_LIST_HEAD(&vha->gnl.fcports);
2d73ac61 4830 INIT_LIST_HEAD(&vha->gpnid_list);
9b3e0f4d 4831 INIT_WORK(&vha->iocb_work, qla2x00_iocb_work_fn);
e315cd28 4832
f999f4c1 4833 spin_lock_init(&vha->work_lock);
8b2f5ff3 4834 spin_lock_init(&vha->cmd_list_lock);
726b8548 4835 init_waitqueue_head(&vha->fcport_waitQ);
c4a9b538 4836 init_waitqueue_head(&vha->vref_waitq);
f999f4c1 4837
2fdbc65e
BVA		 4838 vha->gnl.size = sizeof(struct get_name_list_extended) *
4839 (ha->max_loop_id + 1);
41dc529a
QT		 4840 vha->gnl.l = dma_alloc_coherent(&ha->pdev->dev,
4841 vha->gnl.size, &vha->gnl.ldma, GFP_KERNEL);
4842 if (!vha->gnl.l) {
83548fe2 4843 ql_log(ql_log_fatal, vha, 0xd04a,
41dc529a 4844 "Alloc failed for name list.\n");
26a77799 4845 scsi_host_put(vha->host);
41dc529a
QT		 4846 return NULL;
4847 }
f999f4c1 4848
a4239945
QT		 4849 /* todo: what about ext login? */
4850 vha->scan.size = ha->max_fibre_devices * sizeof(struct fab_scan_rp);
4851 vha->scan.l = vmalloc(vha->scan.size);
4852 if (!vha->scan.l) {
4853 ql_log(ql_log_fatal, vha, 0xd04a,
4854 "Alloc failed for scan database.\n");
4855 dma_free_coherent(&ha->pdev->dev, vha->gnl.size,
4856 vha->gnl.l, vha->gnl.ldma);
26a77799 4857 scsi_host_put(vha->host);
a4239945
QT		 4858 return NULL;
4859 }
f352eeb7 4860 INIT_DELAYED_WORK(&vha->scan.scan_work, qla_scan_work_fn);
a4239945 4861
e315cd28 4862 sprintf(vha->host_str, "%s_%ld", QLA2XXX_DRIVER_NAME, vha->host_no);
7c3df132
SK		 4863 ql_dbg(ql_dbg_init, vha, 0x0041,
4864 "Allocated the host=%p hw=%p vha=%p dev_name=%s",
4865 vha->host, vha->hw, vha,
4866 dev_name(&(ha->pdev->dev)));
4867
e315cd28 4868 return vha;
1da177e4
LT		 4869}
4870
726b8548 4871struct qla_work_evt *
f999f4c1 4872qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type)
0971de7f
AV		 4873{
4874 struct qla_work_evt *e;
feafb7b1
AE		 4875 uint8_t bail;
4876
4877 QLA_VHA_MARK_BUSY(vha, bail);
4878 if (bail)
4879 return NULL;
0971de7f 4880
f999f4c1 4881 e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC);
feafb7b1
AE		 4882 if (!e) {
4883 QLA_VHA_MARK_NOT_BUSY(vha);
0971de7f 4884 return NULL;
feafb7b1 4885 }
0971de7f
AV		 4886
4887 INIT_LIST_HEAD(&e->list);
4888 e->type = type;
4889 e->flags = QLA_EVT_FLAG_FREE;
4890 return e;
4891}
4892
726b8548 4893int
f999f4c1 4894qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e)
0971de7f 4895{
f999f4c1 4896 unsigned long flags;
9b3e0f4d 4897 bool q = false;
0971de7f 4898
f999f4c1 4899 spin_lock_irqsave(&vha->work_lock, flags);
e315cd28 4900 list_add_tail(&e->list, &vha->work_list);
9b3e0f4d
QT		 4901
4902 if (!test_and_set_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags))
4903 q = true;
4904
f999f4c1 4905 spin_unlock_irqrestore(&vha->work_lock, flags);
ec7193e2 4906
9b3e0f4d
QT		 4907 if (q)
4908 queue_work(vha->hw->wq, &vha->iocb_work);
f999f4c1 4909
0971de7f
AV		 4910 return QLA_SUCCESS;
4911}
4912
4913int
e315cd28 4914qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code,
0971de7f
AV		 4915 u32 data)
4916{
4917 struct qla_work_evt *e;
4918
f999f4c1 4919 e = qla2x00_alloc_work(vha, QLA_EVT_AEN);
0971de7f
AV		 4920 if (!e)
4921 return QLA_FUNCTION_FAILED;
4922
4923 e->u.aen.code = code;
4924 e->u.aen.data = data;
f999f4c1 4925 return qla2x00_post_work(vha, e);
0971de7f
AV		 4926}
4927
8a659571
AV		 4928int
4929qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb)
4930{
4931 struct qla_work_evt *e;
4932
f999f4c1 4933 e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK);
8a659571
AV		 4934 if (!e)
4935 return QLA_FUNCTION_FAILED;
4936
4937 memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t));
f999f4c1 4938 return qla2x00_post_work(vha, e);
8a659571
AV		 4939}
4940
ac280b67
AV		 4941#define qla2x00_post_async_work(name, type) \
4942int qla2x00_post_async_##name##_work( \
4943 struct scsi_qla_host *vha, \
4944 fc_port_t *fcport, uint16_t *data) \
4945{ \
4946 struct qla_work_evt *e; \
4947 \
4948 e = qla2x00_alloc_work(vha, type); \
4949 if (!e) \
4950 return QLA_FUNCTION_FAILED; \
4951 \
4952 e->u.logio.fcport = fcport; \
4953 if (data) { \
4954 e->u.logio.data[0] = data[0]; \
4955 e->u.logio.data[1] = data[1]; \
4956 } \
6d674927 4957 fcport->flags |= FCF_ASYNC_ACTIVE; \
ac280b67
AV		 4958 return qla2x00_post_work(vha, e); \
4959}
4960
4961qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN);
ac280b67
AV		 4962qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT);
4963qla2x00_post_async_work(logout_done, QLA_EVT_ASYNC_LOGOUT_DONE);
5ff1d584 4964qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC);
11aea16a
QT		 4965qla2x00_post_async_work(prlo, QLA_EVT_ASYNC_PRLO);
4966qla2x00_post_async_work(prlo_done, QLA_EVT_ASYNC_PRLO_DONE);
ac280b67 4967
3420d36c
AV		 4968int
4969qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code)
4970{
4971 struct qla_work_evt *e;
4972
4973 e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT);
4974 if (!e)
4975 return QLA_FUNCTION_FAILED;
4976
4977 e->u.uevent.code = code;
4978 return qla2x00_post_work(vha, e);
4979}
4980
4981static void
4982qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code)
4983{
4984 char event_string[40];
4985 char *envp[] = { event_string, NULL };
4986
4987 switch (code) {
4988 case QLA_UEVENT_CODE_FW_DUMP:
4989 snprintf(event_string, sizeof(event_string), "FW_DUMP=%ld",
4990 vha->host_no);
4991 break;
4992 default:
4993 /* do nothing */
4994 break;
4995 }
4996 kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp);
4997}
4998
8ae6d9c7
GM		 4999int
5000qlafx00_post_aenfx_work(struct scsi_qla_host *vha, uint32_t evtcode,
5001 uint32_t *data, int cnt)
5002{
5003 struct qla_work_evt *e;
5004
5005 e = qla2x00_alloc_work(vha, QLA_EVT_AENFX);
5006 if (!e)
5007 return QLA_FUNCTION_FAILED;
5008
5009 e->u.aenfx.evtcode = evtcode;
5010 e->u.aenfx.count = cnt;
5011 memcpy(e->u.aenfx.mbx, data, sizeof(*data) * cnt);
5012 return qla2x00_post_work(vha, e);
5013}
5014
cd4ed6b4 5015void qla24xx_sched_upd_fcport(fc_port_t *fcport)
726b8548 5016{
cd4ed6b4 5017 unsigned long flags;
726b8548 5018
cd4ed6b4
QT		 5019 if (IS_SW_RESV_ADDR(fcport->d_id))
5020 return;
726b8548 5021
cd4ed6b4
QT		 5022 spin_lock_irqsave(&fcport->vha->work_lock, flags);
5023 if (fcport->disc_state == DSC_UPD_FCPORT) {
5024 spin_unlock_irqrestore(&fcport->vha->work_lock, flags);
5025 return;
5026 }
5027 fcport->jiffies_at_registration = jiffies;
5028 fcport->sec_since_registration = 0;
5029 fcport->next_disc_state = DSC_DELETED;
5030 fcport->disc_state = DSC_UPD_FCPORT;
5031 spin_unlock_irqrestore(&fcport->vha->work_lock, flags);
5032
5033 queue_work(system_unbound_wq, &fcport->reg_work);
726b8548
QT		 5034}
5035
5036static
5037void qla24xx_create_new_sess(struct scsi_qla_host *vha, struct qla_work_evt *e)
5038{
5039 unsigned long flags;
b5d15312 5040 fc_port_t *fcport = NULL, *tfcp;
726b8548
QT		 5041 struct qlt_plogi_ack_t *pla =
5042 (struct qlt_plogi_ack_t *)e->u.new_sess.pla;
b5d15312 5043 uint8_t free_fcport = 0;
726b8548 5044
9cd883f0
QT		 5045 ql_dbg(ql_dbg_disc, vha, 0xffff,
5046 "%s %d %8phC enter\n",
5047 __func__, __LINE__, e->u.new_sess.port_name);
5048
726b8548
QT		 5049 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
5050 fcport = qla2x00_find_fcport_by_wwpn(vha, e->u.new_sess.port_name, 1);
5051 if (fcport) {
5052 fcport->d_id = e->u.new_sess.id;
5053 if (pla) {
5054 fcport->fw_login_state = DSC_LS_PLOGI_PEND;
9b3e0f4d
QT		 5055 memcpy(fcport->node_name,
5056 pla->iocb.u.isp24.u.plogi.node_name,
5057 WWN_SIZE);
726b8548
QT		 5058 qlt_plogi_ack_link(vha, pla, fcport, QLT_PLOGI_LINK_SAME_WWN);
5059 /* we took an extra ref_count to prevent PLOGI ACK when
5060 * fcport/sess has not been created.
5061 */
5062 pla->ref_count--;
5063 }
5064 } else {
b5d15312 5065 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
726b8548
QT		 5066 fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
5067 if (fcport) {
5068 fcport->d_id = e->u.new_sess.id;
726b8548
QT		 5069 fcport->flags |= FCF_FABRIC_DEVICE;
5070 fcport->fw_login_state = DSC_LS_PLOGI_PEND;
c64a87f9 5071 if (e->u.new_sess.fc4_type == FS_FC4TYPE_FCP)
a4239945 5072 fcport->fc4_type = FC4_TYPE_FCP_SCSI;
726b8548 5073
c64a87f9 5074 if (e->u.new_sess.fc4_type == FS_FC4TYPE_NVME) {
2b5b9647
DT		 5075 fcport->fc4_type = FC4_TYPE_OTHER;
5076 fcport->fc4f_nvme = FC4_TYPE_NVME;
5077 }
33b28357 5078
726b8548
QT		 5079 memcpy(fcport->port_name, e->u.new_sess.port_name,
5080 WWN_SIZE);
b5d15312
QT		 5081 } else {
5082 ql_dbg(ql_dbg_disc, vha, 0xffff,
5083 "%s %8phC mem alloc fail.\n",
5084 __func__, e->u.new_sess.port_name);
5085
5086 if (pla)
5087 kmem_cache_free(qla_tgt_plogi_cachep, pla);
5088 return;
5089 }
5090
5091 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
a4239945 5092 /* search again to make sure no one else got ahead */
b5d15312
QT		 5093 tfcp = qla2x00_find_fcport_by_wwpn(vha,
5094 e->u.new_sess.port_name, 1);
5095 if (tfcp) {
5096 /* should rarily happen */
5097 ql_dbg(ql_dbg_disc, vha, 0xffff,
5098 "%s %8phC found existing fcport b4 add. DS %d LS %d\n",
5099 __func__, tfcp->port_name, tfcp->disc_state,
5100 tfcp->fw_login_state);
5101
5102 free_fcport = 1;
5103 } else {
726b8548
QT		 5104 list_add_tail(&fcport->list, &vha->vp_fcports);
5105
19759033
QT		 5106 }
5107 if (pla) {
5108 qlt_plogi_ack_link(vha, pla, fcport,
5109 QLT_PLOGI_LINK_SAME_WWN);
5110 pla->ref_count--;
726b8548
QT		 5111 }
5112 }
5113 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
5114
5115 if (fcport) {
a4239945
QT		 5116 fcport->id_changed = 1;
5117 fcport->scan_state = QLA_FCPORT_FOUND;
8b5292bc 5118 fcport->chip_reset = vha->hw->base_qpair->chip_reset;
a4239945
QT		 5119 memcpy(fcport->node_name, e->u.new_sess.node_name, WWN_SIZE);
5120
5ef696aa 5121 if (pla) {
9cd883f0
QT		 5122 if (pla->iocb.u.isp24.status_subcode == ELS_PRLI) {
5123 u16 wd3_lo;
5124
5125 fcport->fw_login_state = DSC_LS_PRLI_PEND;
5126 fcport->local = 0;
5127 fcport->loop_id =
5128 le16_to_cpu(
5129 pla->iocb.u.isp24.nport_handle);
5130 fcport->fw_login_state = DSC_LS_PRLI_PEND;
5131 wd3_lo =
5132 le16_to_cpu(
5133 pla->iocb.u.isp24.u.prli.wd3_lo);
5134
5135 if (wd3_lo & BIT_7)
5136 fcport->conf_compl_supported = 1;
5137
5138 if ((wd3_lo & BIT_4) == 0)
5139 fcport->port_type = FCT_INITIATOR;
5140 else
5141 fcport->port_type = FCT_TARGET;
5142 }
726b8548 5143 qlt_plogi_ack_unref(vha, pla);
5ef696aa 5144 } else {
1c6cacf4
HR		 5145 fc_port_t *dfcp = NULL;
5146
5ef696aa
QT		 5147 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
5148 tfcp = qla2x00_find_fcport_by_nportid(vha,
5149 &e->u.new_sess.id, 1);
5150 if (tfcp && (tfcp != fcport)) {
5151 /*
5152 * We have a conflict fcport with same NportID.
5153 */
5154 ql_dbg(ql_dbg_disc, vha, 0xffff,
5155 "%s %8phC found conflict b4 add. DS %d LS %d\n",
5156 __func__, tfcp->port_name, tfcp->disc_state,
5157 tfcp->fw_login_state);
5158
5159 switch (tfcp->disc_state) {
5160 case DSC_DELETED:
5161 break;
5162 case DSC_DELETE_PEND:
5163 fcport->login_pause = 1;
5164 tfcp->conflict = fcport;
5165 break;
5166 default:
5167 fcport->login_pause = 1;
5168 tfcp->conflict = fcport;
1c6cacf4 5169 dfcp = tfcp;
5ef696aa
QT		 5170 break;
5171 }
5172 }
5173 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
1c6cacf4
HR		 5174 if (dfcp)
5175 qlt_schedule_sess_for_deletion(tfcp);
a4239945 5176
a4239945 5177
8777e431
QT		 5178 if (N2N_TOPO(vha->hw))
5179 fcport->flags &= ~FCF_FABRIC_DEVICE;
5180
5181 if (N2N_TOPO(vha->hw)) {
5182 if (vha->flags.nvme_enabled) {
5183 fcport->fc4f_nvme = 1;
5184 fcport->n2n_flag = 1;
5185 }
5186 fcport->fw_login_state = 0;
5187 /*
5188 * wait link init done before sending login
5189 */
5190 } else {
5191 qla24xx_fcport_handle_login(vha, fcport);
5192 }
5ef696aa 5193 }
726b8548 5194 }
b5d15312
QT		 5195
5196 if (free_fcport) {
5197 qla2x00_free_fcport(fcport);
5198 if (pla)
5199 kmem_cache_free(qla_tgt_plogi_cachep, pla);
5200 }
726b8548
QT		 5201}
5202
e374f9f5
QT		 5203static void qla_sp_retry(struct scsi_qla_host *vha, struct qla_work_evt *e)
5204{
5205 struct srb *sp = e->u.iosb.sp;
5206 int rval;
5207
5208 rval = qla2x00_start_sp(sp);
5209 if (rval != QLA_SUCCESS) {
5210 ql_dbg(ql_dbg_disc, vha, 0x2043,
5211 "%s: %s: Re-issue IOCB failed (%d).\n",
5212 __func__, sp->name, rval);
5213 qla24xx_sp_unmap(vha, sp);
5214 }
5215}
5216
ac280b67 5217void
e315cd28 5218qla2x00_do_work(struct scsi_qla_host *vha)
0971de7f 5219{
f999f4c1
AV		 5220 struct qla_work_evt *e, *tmp;
5221 unsigned long flags;
5222 LIST_HEAD(work);
80676d05 5223 int rc;
0971de7f 5224
f999f4c1
AV		 5225 spin_lock_irqsave(&vha->work_lock, flags);
5226 list_splice_init(&vha->work_list, &work);
5227 spin_unlock_irqrestore(&vha->work_lock, flags);
5228
5229 list_for_each_entry_safe(e, tmp, &work, list) {
80676d05 5230 rc = QLA_SUCCESS;
0971de7f
AV		 5231 switch (e->type) {
5232 case QLA_EVT_AEN:
e315cd28 5233 fc_host_post_event(vha->host, fc_get_event_number(),
0971de7f
AV		 5234 e->u.aen.code, e->u.aen.data);
5235 break;
8a659571
AV		 5236 case QLA_EVT_IDC_ACK:
5237 qla81xx_idc_ack(vha, e->u.idc_ack.mb);
5238 break;
ac280b67
AV		 5239 case QLA_EVT_ASYNC_LOGIN:
5240 qla2x00_async_login(vha, e->u.logio.fcport,
5241 e->u.logio.data);
5242 break;
ac280b67 5243 case QLA_EVT_ASYNC_LOGOUT:
80676d05 5244 rc = qla2x00_async_logout(vha, e->u.logio.fcport);
ac280b67
AV		 5245 break;
5246 case QLA_EVT_ASYNC_LOGOUT_DONE:
5247 qla2x00_async_logout_done(vha, e->u.logio.fcport,
5248 e->u.logio.data);
5249 break;
5ff1d584
AV		 5250 case QLA_EVT_ASYNC_ADISC:
5251 qla2x00_async_adisc(vha, e->u.logio.fcport,
5252 e->u.logio.data);
5253 break;
3420d36c
AV		 5254 case QLA_EVT_UEVENT:
5255 qla2x00_uevent_emit(vha, e->u.uevent.code);
5256 break;
8ae6d9c7
GM		 5257 case QLA_EVT_AENFX:
5258 qlafx00_process_aen(vha, e);
5259 break;
726b8548
QT		 5260 case QLA_EVT_GPNID:
5261 qla24xx_async_gpnid(vha, &e->u.gpnid.id);
5262 break;
e374f9f5
QT		 5263 case QLA_EVT_UNMAP:
5264 qla24xx_sp_unmap(vha, e->u.iosb.sp);
726b8548 5265 break;
9b3e0f4d
QT		 5266 case QLA_EVT_RELOGIN:
5267 qla2x00_relogin(vha);
5268 break;
726b8548
QT		 5269 case QLA_EVT_NEW_SESS:
5270 qla24xx_create_new_sess(vha, e);
5271 break;
5272 case QLA_EVT_GPDB:
5273 qla24xx_async_gpdb(vha, e->u.fcport.fcport,
5274 e->u.fcport.opt);
5275 break;
a5d42f4c
DG		 5276 case QLA_EVT_PRLI:
5277 qla24xx_async_prli(vha, e->u.fcport.fcport);
5278 break;
726b8548
QT		 5279 case QLA_EVT_GPSC:
5280 qla24xx_async_gpsc(vha, e->u.fcport.fcport);
5281 break;
726b8548
QT		 5282 case QLA_EVT_GNL:
5283 qla24xx_async_gnl(vha, e->u.fcport.fcport);
5284 break;
5285 case QLA_EVT_NACK:
5286 qla24xx_do_nack_work(vha, e);
5287 break;
11aea16a 5288 case QLA_EVT_ASYNC_PRLO:
80676d05 5289 rc = qla2x00_async_prlo(vha, e->u.logio.fcport);
11aea16a
QT		 5290 break;
5291 case QLA_EVT_ASYNC_PRLO_DONE:
5292 qla2x00_async_prlo_done(vha, e->u.logio.fcport,
5293 e->u.logio.data);
5294 break;
a4239945 5295 case QLA_EVT_GPNFT:
33b28357
QT		 5296 qla24xx_async_gpnft(vha, e->u.gpnft.fc4_type,
5297 e->u.gpnft.sp);
a4239945
QT		 5298 break;
5299 case QLA_EVT_GPNFT_DONE:
5300 qla24xx_async_gpnft_done(vha, e->u.iosb.sp);
5301 break;
5302 case QLA_EVT_GNNFT_DONE:
5303 qla24xx_async_gnnft_done(vha, e->u.iosb.sp);
5304 break;
5305 case QLA_EVT_GNNID:
5306 qla24xx_async_gnnid(vha, e->u.fcport.fcport);
5307 break;
5308 case QLA_EVT_GFPNID:
5309 qla24xx_async_gfpnid(vha, e->u.fcport.fcport);
5310 break;
e374f9f5
QT		 5311 case QLA_EVT_SP_RETRY:
5312 qla_sp_retry(vha, e);
cc28e0ac
QT		 5313 break;
5314 case QLA_EVT_IIDMA:
5315 qla_do_iidma_work(vha, e->u.fcport.fcport);
5316 break;
8777e431
QT		 5317 case QLA_EVT_ELS_PLOGI:
5318 qla24xx_els_dcmd2_iocb(vha, ELS_DCMD_PLOGI,
5319 e->u.fcport.fcport, false);
5320 break;
0971de7f 5321 }
80676d05
QT		 5322
5323 if (rc == EAGAIN) {
5324 /* put 'work' at head of 'vha->work_list' */
5325 spin_lock_irqsave(&vha->work_lock, flags);
5326 list_splice(&work, &vha->work_list);
5327 spin_unlock_irqrestore(&vha->work_lock, flags);
5328 break;
5329 }
5330 list_del_init(&e->list);
0971de7f
AV		 5331 if (e->flags & QLA_EVT_FLAG_FREE)
5332 kfree(e);
feafb7b1
AE		 5333
5334 /* For each work completed decrement vha ref count */
5335 QLA_VHA_MARK_NOT_BUSY(vha);
e315cd28 5336 }
e315cd28 5337}
f999f4c1 5338
9b3e0f4d
QT		 5339int qla24xx_post_relogin_work(struct scsi_qla_host *vha)
5340{
5341 struct qla_work_evt *e;
5342
5343 e = qla2x00_alloc_work(vha, QLA_EVT_RELOGIN);
5344
5345 if (!e) {
5346 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
5347 return QLA_FUNCTION_FAILED;
5348 }
5349
5350 return qla2x00_post_work(vha, e);
5351}
5352
e315cd28
AC		 5353/* Relogins all the fcports of a vport
5354 * Context: dpc thread
5355 */
5356void qla2x00_relogin(struct scsi_qla_host *vha)
5357{
5358 fc_port_t *fcport;
23dd98a6 5359 int status, relogin_needed = 0;
726b8548 5360 struct event_arg ea;
e315cd28
AC		 5361
5362 list_for_each_entry(fcport, &vha->vp_fcports, list) {
9cd883f0
QT		 5363 /*
5364 * If the port is not ONLINE then try to login
5365 * to it if we haven't run out of retries.
5366 */
5ff1d584 5367 if (atomic_read(&fcport->state) != FCS_ONLINE &&
23dd98a6
QT		 5368 fcport->login_retry) {
5369 if (fcport->scan_state != QLA_FCPORT_FOUND ||
5370 fcport->disc_state == DSC_LOGIN_COMPLETE)
5371 continue;
e315cd28 5372
23dd98a6
QT		 5373 if (fcport->flags & (FCF_ASYNC_SENT|FCF_ASYNC_ACTIVE) ||
5374 fcport->disc_state == DSC_DELETE_PEND) {
5375 relogin_needed = 1;
5376 } else {
5377 if (vha->hw->current_topology != ISP_CFG_NL) {
5378 memset(&ea, 0, sizeof(ea));
5379 ea.event = FCME_RELOGIN;
5380 ea.fcport = fcport;
5381 qla2x00_fcport_event_handler(vha, &ea);
5382 } else if (vha->hw->current_topology ==
5383 ISP_CFG_NL) {
5384 fcport->login_retry--;
5385 status =
5386 qla2x00_local_device_login(vha,
5387 fcport);
5388 if (status == QLA_SUCCESS) {
5389 fcport->old_loop_id =
5390 fcport->loop_id;
5391 ql_dbg(ql_dbg_disc, vha, 0x2003,
5392 "Port login OK: logged in ID 0x%x.\n",
5393 fcport->loop_id);
5394 qla2x00_update_fcport
5395 (vha, fcport);
5396 } else if (status == 1) {
5397 set_bit(RELOGIN_NEEDED,
5398 &vha->dpc_flags);
5399 /* retry the login again */
5400 ql_dbg(ql_dbg_disc, vha, 0x2007,
5401 "Retrying %d login again loop_id 0x%x.\n",
5402 fcport->login_retry,
5403 fcport->loop_id);
5404 } else {
5405 fcport->login_retry = 0;
5406 }
e315cd28 5407
23dd98a6
QT		 5408 if (fcport->login_retry == 0 &&
5409 status != QLA_SUCCESS)
5410 qla2x00_clear_loop_id(fcport);
5411 }
e315cd28 5412 }
e315cd28
AC		 5413 }
5414 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
5415 break;
0971de7f 5416 }
9b3e0f4d 5417
23dd98a6
QT		 5418 if (relogin_needed)
5419 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
5420
9b3e0f4d
QT		 5421 ql_dbg(ql_dbg_disc, vha, 0x400e,
5422 "Relogin end.\n");
0971de7f
AV		 5423}
5424
7d613ac6
SV		 5425/* Schedule work on any of the dpc-workqueues */
5426void
5427qla83xx_schedule_work(scsi_qla_host_t *base_vha, int work_code)
5428{
5429 struct qla_hw_data *ha = base_vha->hw;
5430
5431 switch (work_code) {
5432 case MBA_IDC_AEN: /* 0x8200 */
5433 if (ha->dpc_lp_wq)
5434 queue_work(ha->dpc_lp_wq, &ha->idc_aen);
5435 break;
5436
5437 case QLA83XX_NIC_CORE_RESET: /* 0x1 */
5438 if (!ha->flags.nic_core_reset_hdlr_active) {
5439 if (ha->dpc_hp_wq)
5440 queue_work(ha->dpc_hp_wq, &ha->nic_core_reset);
5441 } else
5442 ql_dbg(ql_dbg_p3p, base_vha, 0xb05e,
5443 "NIC Core reset is already active. Skip "
5444 "scheduling it again.\n");
5445 break;
5446 case QLA83XX_IDC_STATE_HANDLER: /* 0x2 */
5447 if (ha->dpc_hp_wq)
5448 queue_work(ha->dpc_hp_wq, &ha->idc_state_handler);
5449 break;
5450 case QLA83XX_NIC_CORE_UNRECOVERABLE: /* 0x3 */
5451 if (ha->dpc_hp_wq)
5452 queue_work(ha->dpc_hp_wq, &ha->nic_core_unrecoverable);
5453 break;
5454 default:
5455 ql_log(ql_log_warn, base_vha, 0xb05f,
d939be3a 5456 "Unknown work-code=0x%x.\n", work_code);
7d613ac6
SV		 5457 }
5458
5459 return;
5460}
5461
5462/* Work: Perform NIC Core Unrecoverable state handling */
5463void
5464qla83xx_nic_core_unrecoverable_work(struct work_struct *work)
5465{
5466 struct qla_hw_data *ha =
2ad1b67c 5467 container_of(work, struct qla_hw_data, nic_core_unrecoverable);
7d613ac6
SV		 5468 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5469 uint32_t dev_state = 0;
5470
5471 qla83xx_idc_lock(base_vha, 0);
5472 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
5473 qla83xx_reset_ownership(base_vha);
5474 if (ha->flags.nic_core_reset_owner) {
5475 ha->flags.nic_core_reset_owner = 0;
5476 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
5477 QLA8XXX_DEV_FAILED);
5478 ql_log(ql_log_info, base_vha, 0xb060, "HW State: FAILED.\n");
5479 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
5480 }
5481 qla83xx_idc_unlock(base_vha, 0);
5482}
5483
5484/* Work: Execute IDC state handler */
5485void
5486qla83xx_idc_state_handler_work(struct work_struct *work)
5487{
5488 struct qla_hw_data *ha =
2ad1b67c 5489 container_of(work, struct qla_hw_data, idc_state_handler);
7d613ac6
SV		 5490 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5491 uint32_t dev_state = 0;
5492
5493 qla83xx_idc_lock(base_vha, 0);
5494 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
5495 if (dev_state == QLA8XXX_DEV_FAILED ||
5496 dev_state == QLA8XXX_DEV_NEED_QUIESCENT)
5497 qla83xx_idc_state_handler(base_vha);
5498 qla83xx_idc_unlock(base_vha, 0);
5499}
5500
fa492630 5501static int
7d613ac6
SV		 5502qla83xx_check_nic_core_fw_alive(scsi_qla_host_t *base_vha)
5503{
5504 int rval = QLA_SUCCESS;
5505 unsigned long heart_beat_wait = jiffies + (1 * HZ);
5506 uint32_t heart_beat_counter1, heart_beat_counter2;
5507
5508 do {
5509 if (time_after(jiffies, heart_beat_wait)) {
5510 ql_dbg(ql_dbg_p3p, base_vha, 0xb07c,
5511 "Nic Core f/w is not alive.\n");
5512 rval = QLA_FUNCTION_FAILED;
5513 break;
5514 }
5515
5516 qla83xx_idc_lock(base_vha, 0);
5517 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
5518 &heart_beat_counter1);
5519 qla83xx_idc_unlock(base_vha, 0);
5520 msleep(100);
5521 qla83xx_idc_lock(base_vha, 0);
5522 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
5523 &heart_beat_counter2);
5524 qla83xx_idc_unlock(base_vha, 0);
5525 } while (heart_beat_counter1 == heart_beat_counter2);
5526
5527 return rval;
5528}
5529
5530/* Work: Perform NIC Core Reset handling */
5531void
5532qla83xx_nic_core_reset_work(struct work_struct *work)
5533{
5534 struct qla_hw_data *ha =
5535 container_of(work, struct qla_hw_data, nic_core_reset);
5536 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5537 uint32_t dev_state = 0;
5538
81178772
SK		 5539 if (IS_QLA2031(ha)) {
5540 if (qla2xxx_mctp_dump(base_vha) != QLA_SUCCESS)
5541 ql_log(ql_log_warn, base_vha, 0xb081,
5542 "Failed to dump mctp\n");
5543 return;
5544 }
5545
7d613ac6
SV		 5546 if (!ha->flags.nic_core_reset_hdlr_active) {
5547 if (qla83xx_check_nic_core_fw_alive(base_vha) == QLA_SUCCESS) {
5548 qla83xx_idc_lock(base_vha, 0);
5549 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE,
5550 &dev_state);
5551 qla83xx_idc_unlock(base_vha, 0);
5552 if (dev_state != QLA8XXX_DEV_NEED_RESET) {
5553 ql_dbg(ql_dbg_p3p, base_vha, 0xb07a,
5554 "Nic Core f/w is alive.\n");
5555 return;
5556 }
5557 }
5558
5559 ha->flags.nic_core_reset_hdlr_active = 1;
5560 if (qla83xx_nic_core_reset(base_vha)) {
5561 /* NIC Core reset failed. */
5562 ql_dbg(ql_dbg_p3p, base_vha, 0xb061,
5563 "NIC Core reset failed.\n");
5564 }
5565 ha->flags.nic_core_reset_hdlr_active = 0;
5566 }
5567}
5568
5569/* Work: Handle 8200 IDC aens */
5570void
5571qla83xx_service_idc_aen(struct work_struct *work)
5572{
5573 struct qla_hw_data *ha =
5574 container_of(work, struct qla_hw_data, idc_aen);
5575 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5576 uint32_t dev_state, idc_control;
5577
5578 qla83xx_idc_lock(base_vha, 0);
5579 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
5580 qla83xx_rd_reg(base_vha, QLA83XX_IDC_CONTROL, &idc_control);
5581 qla83xx_idc_unlock(base_vha, 0);
5582 if (dev_state == QLA8XXX_DEV_NEED_RESET) {
5583 if (idc_control & QLA83XX_IDC_GRACEFUL_RESET) {
5584 ql_dbg(ql_dbg_p3p, base_vha, 0xb062,
5585 "Application requested NIC Core Reset.\n");
5586 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
5587 } else if (qla83xx_check_nic_core_fw_alive(base_vha) ==
5588 QLA_SUCCESS) {
5589 ql_dbg(ql_dbg_p3p, base_vha, 0xb07b,
5590 "Other protocol driver requested NIC Core Reset.\n");
5591 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
5592 }
5593 } else if (dev_state == QLA8XXX_DEV_FAILED ||
5594 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) {
5595 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
5596 }
5597}
5598
5599static void
5600qla83xx_wait_logic(void)
5601{
5602 int i;
5603
5604 /* Yield CPU */
5605 if (!in_interrupt()) {
5606 /*
5607 * Wait about 200ms before retrying again.
5608 * This controls the number of retries for single
5609 * lock operation.
5610 */
5611 msleep(100);
5612 schedule();
5613 } else {
5614 for (i = 0; i < 20; i++)
5615 cpu_relax(); /* This a nop instr on i386 */
5616 }
5617}
5618
fa492630 5619static int
7d613ac6
SV		 5620qla83xx_force_lock_recovery(scsi_qla_host_t *base_vha)
5621{
5622 int rval;
5623 uint32_t data;
5624 uint32_t idc_lck_rcvry_stage_mask = 0x3;
5625 uint32_t idc_lck_rcvry_owner_mask = 0x3c;
5626 struct qla_hw_data *ha = base_vha->hw;
bd432bb5 5627
6c315553
SK		 5628 ql_dbg(ql_dbg_p3p, base_vha, 0xb086,
5629 "Trying force recovery of the IDC lock.\n");
7d613ac6
SV		 5630
5631 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, &data);
5632 if (rval)
5633 return rval;
5634
5635 if ((data & idc_lck_rcvry_stage_mask) > 0) {
5636 return QLA_SUCCESS;
5637 } else {
5638 data = (IDC_LOCK_RECOVERY_STAGE1) | (ha->portnum << 2);
5639 rval = qla83xx_wr_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
5640 data);
5641 if (rval)
5642 return rval;
5643
5644 msleep(200);
5645
5646 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
5647 &data);
5648 if (rval)
5649 return rval;
5650
5651 if (((data & idc_lck_rcvry_owner_mask) >> 2) == ha->portnum) {
5652 data &= (IDC_LOCK_RECOVERY_STAGE2 |
5653 ~(idc_lck_rcvry_stage_mask));
5654 rval = qla83xx_wr_reg(base_vha,
5655 QLA83XX_IDC_LOCK_RECOVERY, data);
5656 if (rval)
5657 return rval;
5658
5659 /* Forcefully perform IDC UnLock */
5660 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK,
5661 &data);
5662 if (rval)
5663 return rval;
5664 /* Clear lock-id by setting 0xff */
5665 rval = qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
5666 0xff);
5667 if (rval)
5668 return rval;
5669 /* Clear lock-recovery by setting 0x0 */
5670 rval = qla83xx_wr_reg(base_vha,
5671 QLA83XX_IDC_LOCK_RECOVERY, 0x0);
5672 if (rval)
5673 return rval;
5674 } else
5675 return QLA_SUCCESS;
5676 }
5677
5678 return rval;
5679}
5680
fa492630 5681static int
7d613ac6
SV		 5682qla83xx_idc_lock_recovery(scsi_qla_host_t *base_vha)
5683{
5684 int rval = QLA_SUCCESS;
5685 uint32_t o_drv_lockid, n_drv_lockid;
5686 unsigned long lock_recovery_timeout;
5687
5688 lock_recovery_timeout = jiffies + QLA83XX_MAX_LOCK_RECOVERY_WAIT;
5689retry_lockid:
5690 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &o_drv_lockid);
5691 if (rval)
5692 goto exit;
5693
5694 /* MAX wait time before forcing IDC Lock recovery = 2 secs */
5695 if (time_after_eq(jiffies, lock_recovery_timeout)) {
5696 if (qla83xx_force_lock_recovery(base_vha) == QLA_SUCCESS)
5697 return QLA_SUCCESS;
5698 else
5699 return QLA_FUNCTION_FAILED;
5700 }
5701
5702 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &n_drv_lockid);
5703 if (rval)
5704 goto exit;
5705
5706 if (o_drv_lockid == n_drv_lockid) {
5707 qla83xx_wait_logic();
5708 goto retry_lockid;
5709 } else
5710 return QLA_SUCCESS;
5711
5712exit:
5713 return rval;
5714}
5715
5716void
5717qla83xx_idc_lock(scsi_qla_host_t *base_vha, uint16_t requester_id)
5718{
5719 uint16_t options = (requester_id << 15) | BIT_6;
5720 uint32_t data;
6c315553 5721 uint32_t lock_owner;
7d613ac6
SV		 5722 struct qla_hw_data *ha = base_vha->hw;
5723
5724 /* IDC-lock implementation using driver-lock/lock-id remote registers */
5725retry_lock:
5726 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCK, &data)
5727 == QLA_SUCCESS) {
5728 if (data) {
5729 /* Setting lock-id to our function-number */
5730 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
5731 ha->portnum);
5732 } else {
6c315553
SK		 5733 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID,
5734 &lock_owner);
7d613ac6 5735 ql_dbg(ql_dbg_p3p, base_vha, 0xb063,
6c315553
SK		 5736 "Failed to acquire IDC lock, acquired by %d, "
5737 "retrying...\n", lock_owner);
7d613ac6
SV		 5738
5739 /* Retry/Perform IDC-Lock recovery */
5740 if (qla83xx_idc_lock_recovery(base_vha)
5741 == QLA_SUCCESS) {
5742 qla83xx_wait_logic();
5743 goto retry_lock;
5744 } else
5745 ql_log(ql_log_warn, base_vha, 0xb075,
5746 "IDC Lock recovery FAILED.\n");
5747 }
5748
5749 }
5750
5751 return;
5752
5753 /* XXX: IDC-lock implementation using access-control mbx */
5754retry_lock2:
5755 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
5756 ql_dbg(ql_dbg_p3p, base_vha, 0xb072,
5757 "Failed to acquire IDC lock. retrying...\n");
5758 /* Retry/Perform IDC-Lock recovery */
5759 if (qla83xx_idc_lock_recovery(base_vha) == QLA_SUCCESS) {
5760 qla83xx_wait_logic();
5761 goto retry_lock2;
5762 } else
5763 ql_log(ql_log_warn, base_vha, 0xb076,
5764 "IDC Lock recovery FAILED.\n");
5765 }
5766
5767 return;
5768}
5769
5770void
5771qla83xx_idc_unlock(scsi_qla_host_t *base_vha, uint16_t requester_id)
5772{
5897cb2f
BVA		 5773#if 0
5774 uint16_t options = (requester_id << 15) | BIT_7;
5775#endif
5776 uint16_t retry;
7d613ac6
SV		 5777 uint32_t data;
5778 struct qla_hw_data *ha = base_vha->hw;
5779
5780 /* IDC-unlock implementation using driver-unlock/lock-id
5781 * remote registers
5782 */
5783 retry = 0;
5784retry_unlock:
5785 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &data)
5786 == QLA_SUCCESS) {
5787 if (data == ha->portnum) {
5788 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, &data);
5789 /* Clearing lock-id by setting 0xff */
5790 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 0xff);
5791 } else if (retry < 10) {
5792 /* SV: XXX: IDC unlock retrying needed here? */
5793
5794 /* Retry for IDC-unlock */
5795 qla83xx_wait_logic();
5796 retry++;
5797 ql_dbg(ql_dbg_p3p, base_vha, 0xb064,
ee6a8773 5798 "Failed to release IDC lock, retrying=%d\n", retry);
7d613ac6
SV		 5799 goto retry_unlock;
5800 }
5801 } else if (retry < 10) {
5802 /* Retry for IDC-unlock */
5803 qla83xx_wait_logic();
5804 retry++;
5805 ql_dbg(ql_dbg_p3p, base_vha, 0xb065,
ee6a8773 5806 "Failed to read drv-lockid, retrying=%d\n", retry);
7d613ac6
SV		 5807 goto retry_unlock;
5808 }
5809
5810 return;
5811
5897cb2f 5812#if 0
7d613ac6
SV		 5813 /* XXX: IDC-unlock implementation using access-control mbx */
5814 retry = 0;
5815retry_unlock2:
5816 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
5817 if (retry < 10) {
5818 /* Retry for IDC-unlock */
5819 qla83xx_wait_logic();
5820 retry++;
5821 ql_dbg(ql_dbg_p3p, base_vha, 0xb066,
ee6a8773 5822 "Failed to release IDC lock, retrying=%d\n", retry);
7d613ac6
SV		 5823 goto retry_unlock2;
5824 }
5825 }
5826
5827 return;
5897cb2f 5828#endif
7d613ac6
SV		 5829}
5830
5831int
5832__qla83xx_set_drv_presence(scsi_qla_host_t *vha)
5833{
5834 int rval = QLA_SUCCESS;
5835 struct qla_hw_data *ha = vha->hw;
5836 uint32_t drv_presence;
5837
5838 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
5839 if (rval == QLA_SUCCESS) {
5840 drv_presence |= (1 << ha->portnum);
5841 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
5842 drv_presence);
5843 }
5844
5845 return rval;
5846}
5847
5848int
5849qla83xx_set_drv_presence(scsi_qla_host_t *vha)
5850{
5851 int rval = QLA_SUCCESS;
5852
5853 qla83xx_idc_lock(vha, 0);
5854 rval = __qla83xx_set_drv_presence(vha);
5855 qla83xx_idc_unlock(vha, 0);
5856
5857 return rval;
5858}
5859
5860int
5861__qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
5862{
5863 int rval = QLA_SUCCESS;
5864 struct qla_hw_data *ha = vha->hw;
5865 uint32_t drv_presence;
5866
5867 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
5868 if (rval == QLA_SUCCESS) {
5869 drv_presence &= ~(1 << ha->portnum);
5870 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
5871 drv_presence);
5872 }
5873
5874 return rval;
5875}
5876
5877int
5878qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
5879{
5880 int rval = QLA_SUCCESS;
5881
5882 qla83xx_idc_lock(vha, 0);
5883 rval = __qla83xx_clear_drv_presence(vha);
5884 qla83xx_idc_unlock(vha, 0);
5885
5886 return rval;
5887}
5888
fa492630 5889static void
7d613ac6
SV		 5890qla83xx_need_reset_handler(scsi_qla_host_t *vha)
5891{
5892 struct qla_hw_data *ha = vha->hw;
5893 uint32_t drv_ack, drv_presence;
5894 unsigned long ack_timeout;
5895
5896 /* Wait for IDC ACK from all functions (DRV-ACK == DRV-PRESENCE) */
5897 ack_timeout = jiffies + (ha->fcoe_reset_timeout * HZ);
5898 while (1) {
5899 qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
5900 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
807fb6d8 5901 if ((drv_ack & drv_presence) == drv_presence)
7d613ac6
SV		 5902 break;
5903
5904 if (time_after_eq(jiffies, ack_timeout)) {
5905 ql_log(ql_log_warn, vha, 0xb067,
5906 "RESET ACK TIMEOUT! drv_presence=0x%x "
5907 "drv_ack=0x%x\n", drv_presence, drv_ack);
5908 /*
5909 * The function(s) which did not ack in time are forced
5910 * to withdraw any further participation in the IDC
5911 * reset.
5912 */
5913 if (drv_ack != drv_presence)
5914 qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
5915 drv_ack);
5916 break;
5917 }
5918
5919 qla83xx_idc_unlock(vha, 0);
5920 msleep(1000);
5921 qla83xx_idc_lock(vha, 0);
5922 }
5923
5924 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_COLD);
5925 ql_log(ql_log_info, vha, 0xb068, "HW State: COLD/RE-INIT.\n");
5926}
5927
fa492630 5928static int
7d613ac6
SV		 5929qla83xx_device_bootstrap(scsi_qla_host_t *vha)
5930{
5931 int rval = QLA_SUCCESS;
5932 uint32_t idc_control;
5933
5934 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_INITIALIZING);
5935 ql_log(ql_log_info, vha, 0xb069, "HW State: INITIALIZING.\n");
5936
5937 /* Clearing IDC-Control Graceful-Reset Bit before resetting f/w */
5938 __qla83xx_get_idc_control(vha, &idc_control);
5939 idc_control &= ~QLA83XX_IDC_GRACEFUL_RESET;
5940 __qla83xx_set_idc_control(vha, 0);
5941
5942 qla83xx_idc_unlock(vha, 0);
5943 rval = qla83xx_restart_nic_firmware(vha);
5944 qla83xx_idc_lock(vha, 0);
5945
5946 if (rval != QLA_SUCCESS) {
5947 ql_log(ql_log_fatal, vha, 0xb06a,
5948 "Failed to restart NIC f/w.\n");
5949 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_FAILED);
5950 ql_log(ql_log_info, vha, 0xb06b, "HW State: FAILED.\n");
5951 } else {
5952 ql_dbg(ql_dbg_p3p, vha, 0xb06c,
5953 "Success in restarting nic f/w.\n");
5954 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_READY);
5955 ql_log(ql_log_info, vha, 0xb06d, "HW State: READY.\n");
5956 }
5957
5958 return rval;
5959}
5960
5961/* Assumes idc_lock always held on entry */
5962int
5963qla83xx_idc_state_handler(scsi_qla_host_t *base_vha)
5964{
5965 struct qla_hw_data *ha = base_vha->hw;
5966 int rval = QLA_SUCCESS;
5967 unsigned long dev_init_timeout;
5968 uint32_t dev_state;
5969
5970 /* Wait for MAX-INIT-TIMEOUT for the device to go ready */
5971 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ);
5972
5973 while (1) {
5974
5975 if (time_after_eq(jiffies, dev_init_timeout)) {
5976 ql_log(ql_log_warn, base_vha, 0xb06e,
5977 "Initialization TIMEOUT!\n");
5978 /* Init timeout. Disable further NIC Core
5979 * communication.
5980 */
5981 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
5982 QLA8XXX_DEV_FAILED);
5983 ql_log(ql_log_info, base_vha, 0xb06f,
5984 "HW State: FAILED.\n");
5985 }
5986
5987 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
5988 switch (dev_state) {
5989 case QLA8XXX_DEV_READY:
5990 if (ha->flags.nic_core_reset_owner)
5991 qla83xx_idc_audit(base_vha,
5992 IDC_AUDIT_COMPLETION);
5993 ha->flags.nic_core_reset_owner = 0;
5994 ql_dbg(ql_dbg_p3p, base_vha, 0xb070,
5995 "Reset_owner reset by 0x%x.\n",
5996 ha->portnum);
5997 goto exit;
5998 case QLA8XXX_DEV_COLD:
5999 if (ha->flags.nic_core_reset_owner)
6000 rval = qla83xx_device_bootstrap(base_vha);
6001 else {
6002 /* Wait for AEN to change device-state */
6003 qla83xx_idc_unlock(base_vha, 0);
6004 msleep(1000);
6005 qla83xx_idc_lock(base_vha, 0);
6006 }
6007 break;
6008 case QLA8XXX_DEV_INITIALIZING:
6009 /* Wait for AEN to change device-state */
6010 qla83xx_idc_unlock(base_vha, 0);
6011 msleep(1000);
6012 qla83xx_idc_lock(base_vha, 0);
6013 break;
6014 case QLA8XXX_DEV_NEED_RESET:
6015 if (!ql2xdontresethba && ha->flags.nic_core_reset_owner)
6016 qla83xx_need_reset_handler(base_vha);
6017 else {
6018 /* Wait for AEN to change device-state */
6019 qla83xx_idc_unlock(base_vha, 0);
6020 msleep(1000);
6021 qla83xx_idc_lock(base_vha, 0);
6022 }
6023 /* reset timeout value after need reset handler */
6024 dev_init_timeout = jiffies +
6025 (ha->fcoe_dev_init_timeout * HZ);
6026 break;
6027 case QLA8XXX_DEV_NEED_QUIESCENT:
6028 /* XXX: DEBUG for now */
6029 qla83xx_idc_unlock(base_vha, 0);
6030 msleep(1000);
6031 qla83xx_idc_lock(base_vha, 0);
6032 break;
6033 case QLA8XXX_DEV_QUIESCENT:
6034 /* XXX: DEBUG for now */
6035 if (ha->flags.quiesce_owner)
6036 goto exit;
6037
6038 qla83xx_idc_unlock(base_vha, 0);
6039 msleep(1000);
6040 qla83xx_idc_lock(base_vha, 0);
6041 dev_init_timeout = jiffies +
6042 (ha->fcoe_dev_init_timeout * HZ);
6043 break;
6044 case QLA8XXX_DEV_FAILED:
6045 if (ha->flags.nic_core_reset_owner)
6046 qla83xx_idc_audit(base_vha,
6047 IDC_AUDIT_COMPLETION);
6048 ha->flags.nic_core_reset_owner = 0;
6049 __qla83xx_clear_drv_presence(base_vha);
6050 qla83xx_idc_unlock(base_vha, 0);
6051 qla8xxx_dev_failed_handler(base_vha);
6052 rval = QLA_FUNCTION_FAILED;
6053 qla83xx_idc_lock(base_vha, 0);
6054 goto exit;
6055 case QLA8XXX_BAD_VALUE:
6056 qla83xx_idc_unlock(base_vha, 0);
6057 msleep(1000);
6058 qla83xx_idc_lock(base_vha, 0);
6059 break;
6060 default:
6061 ql_log(ql_log_warn, base_vha, 0xb071,
d939be3a 6062 "Unknown Device State: %x.\n", dev_state);
7d613ac6
SV		 6063 qla83xx_idc_unlock(base_vha, 0);
6064 qla8xxx_dev_failed_handler(base_vha);
6065 rval = QLA_FUNCTION_FAILED;
6066 qla83xx_idc_lock(base_vha, 0);
6067 goto exit;
6068 }
6069 }
6070
6071exit:
6072 return rval;
6073}
6074
f3ddac19
CD		 6075void
6076qla2x00_disable_board_on_pci_error(struct work_struct *work)
6077{
6078 struct qla_hw_data *ha = container_of(work, struct qla_hw_data,
6079 board_disable);
6080 struct pci_dev *pdev = ha->pdev;
6081 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
6082
726b8548
QT		 6083 /*
6084 * if UNLOAD flag is already set, then continue unload,
783e0dc4
SC		 6085 * where it was set first.
6086 */
6087 if (test_bit(UNLOADING, &base_vha->dpc_flags))
6088 return;
6089
f3ddac19
CD		 6090 ql_log(ql_log_warn, base_vha, 0x015b,
6091 "Disabling adapter.\n");
6092
efdb5760
SC		 6093 if (!atomic_read(&pdev->enable_cnt)) {
6094 ql_log(ql_log_info, base_vha, 0xfffc,
6095 "PCI device disabled, no action req for PCI error=%lx\n",
6096 base_vha->pci_flags);
6097 return;
6098 }
6099
726b8548
QT		 6100 qla2x00_wait_for_sess_deletion(base_vha);
6101
f3ddac19
CD		 6102 set_bit(UNLOADING, &base_vha->dpc_flags);
6103
6104 qla2x00_delete_all_vps(ha, base_vha);
6105
6106 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
6107
6108 qla2x00_dfs_remove(base_vha);
6109
6110 qla84xx_put_chip(base_vha);
6111
6112 if (base_vha->timer_active)
6113 qla2x00_stop_timer(base_vha);
6114
6115 base_vha->flags.online = 0;
6116
6117 qla2x00_destroy_deferred_work(ha);
6118
6119 /*
6120 * Do not try to stop beacon blink as it will issue a mailbox
6121 * command.
6122 */
6123 qla2x00_free_sysfs_attr(base_vha, false);
6124
6125 fc_remove_host(base_vha->host);
6126
6127 scsi_remove_host(base_vha->host);
6128
6129 base_vha->flags.init_done = 0;
6130 qla25xx_delete_queues(base_vha);
f3ddac19 6131 qla2x00_free_fcports(base_vha);
093df737 6132 qla2x00_free_irqs(base_vha);
f3ddac19
CD		 6133 qla2x00_mem_free(ha);
6134 qla82xx_md_free(base_vha);
6135 qla2x00_free_queues(ha);
6136
f3ddac19
CD		 6137 qla2x00_unmap_iobases(ha);
6138
6139 pci_release_selected_regions(ha->pdev, ha->bars);
f3ddac19
CD		 6140 pci_disable_pcie_error_reporting(pdev);
6141 pci_disable_device(pdev);
f3ddac19 6142
beb9e315
JL		 6143 /*
6144 * Let qla2x00_remove_one cleanup qla_hw_data on device removal.
6145 */
f3ddac19
CD		 6146}
6147
1da177e4
LT		 6148/**************************************************************************
6149* qla2x00_do_dpc
6150* This kernel thread is a task that is schedule by the interrupt handler
6151* to perform the background processing for interrupts.
6152*
6153* Notes:
6154* This task always run in the context of a kernel thread. It
6155* is kick-off by the driver's detect code and starts up
6156* up one per adapter. It immediately goes to sleep and waits for
6157* some fibre event. When either the interrupt handler or
6158* the timer routine detects a event it will one of the task
6159* bits then wake us up.
6160**************************************************************************/
6161static int
6162qla2x00_do_dpc(void *data)
6163{
e315cd28
AC		 6164 scsi_qla_host_t *base_vha;
6165 struct qla_hw_data *ha;
d7459527
MH		 6166 uint32_t online;
6167 struct qla_qpair *qpair;
1da177e4 6168
e315cd28
AC		 6169 ha = (struct qla_hw_data *)data;
6170 base_vha = pci_get_drvdata(ha->pdev);
1da177e4 6171
8698a745 6172 set_user_nice(current, MIN_NICE);
1da177e4 6173
563585ec 6174 set_current_state(TASK_INTERRUPTIBLE);
39a11240 6175 while (!kthread_should_stop()) {
7c3df132
SK		 6176 ql_dbg(ql_dbg_dpc, base_vha, 0x4000,
6177 "DPC handler sleeping.\n");
1da177e4 6178
39a11240 6179 schedule();
1da177e4 6180
c142caf0
AV		 6181 if (!base_vha->flags.init_done || ha->flags.mbox_busy)
6182 goto end_loop;
1da177e4 6183
85880801 6184 if (ha->flags.eeh_busy) {
7c3df132
SK		 6185 ql_dbg(ql_dbg_dpc, base_vha, 0x4003,
6186 "eeh_busy=%d.\n", ha->flags.eeh_busy);
c142caf0 6187 goto end_loop;
85880801
AV		 6188 }
6189
1da177e4
LT		 6190 ha->dpc_active = 1;
6191
5f28d2d7
SK		 6192 ql_dbg(ql_dbg_dpc + ql_dbg_verbose, base_vha, 0x4001,
6193 "DPC handler waking up, dpc_flags=0x%lx.\n",
6194 base_vha->dpc_flags);
1da177e4 6195
a29b3dd7
JC		 6196 if (test_bit(UNLOADING, &base_vha->dpc_flags))
6197 break;
6198
7ec0effd
AD		 6199 if (IS_P3P_TYPE(ha)) {
6200 if (IS_QLA8044(ha)) {
6201 if (test_and_clear_bit(ISP_UNRECOVERABLE,
6202 &base_vha->dpc_flags)) {
6203 qla8044_idc_lock(ha);
6204 qla8044_wr_direct(base_vha,
6205 QLA8044_CRB_DEV_STATE_INDEX,
6206 QLA8XXX_DEV_FAILED);
6207 qla8044_idc_unlock(ha);
6208 ql_log(ql_log_info, base_vha, 0x4004,
6209 "HW State: FAILED.\n");
6210 qla8044_device_state_handler(base_vha);
6211 continue;
6212 }
6213
6214 } else {
6215 if (test_and_clear_bit(ISP_UNRECOVERABLE,
6216 &base_vha->dpc_flags)) {
6217 qla82xx_idc_lock(ha);
6218 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
6219 QLA8XXX_DEV_FAILED);
6220 qla82xx_idc_unlock(ha);
6221 ql_log(ql_log_info, base_vha, 0x0151,
6222 "HW State: FAILED.\n");
6223 qla82xx_device_state_handler(base_vha);
6224 continue;
6225 }
a9083016
GM		 6226 }
6227
6228 if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED,
6229 &base_vha->dpc_flags)) {
6230
7c3df132
SK		 6231 ql_dbg(ql_dbg_dpc, base_vha, 0x4005,
6232 "FCoE context reset scheduled.\n");
a9083016
GM		 6233 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
6234 &base_vha->dpc_flags))) {
6235 if (qla82xx_fcoe_ctx_reset(base_vha)) {
6236 /* FCoE-ctx reset failed.
6237 * Escalate to chip-reset
6238 */
6239 set_bit(ISP_ABORT_NEEDED,
6240 &base_vha->dpc_flags);
6241 }
6242 clear_bit(ABORT_ISP_ACTIVE,
6243 &base_vha->dpc_flags);
6244 }
6245
7c3df132
SK		 6246 ql_dbg(ql_dbg_dpc, base_vha, 0x4006,
6247 "FCoE context reset end.\n");
a9083016 6248 }
8ae6d9c7
GM		 6249 } else if (IS_QLAFX00(ha)) {
6250 if (test_and_clear_bit(ISP_UNRECOVERABLE,
6251 &base_vha->dpc_flags)) {
6252 ql_dbg(ql_dbg_dpc, base_vha, 0x4020,
6253 "Firmware Reset Recovery\n");
6254 if (qlafx00_reset_initialize(base_vha)) {
6255 /* Failed. Abort isp later. */
6256 if (!test_bit(UNLOADING,
f92f82d6 6257 &base_vha->dpc_flags)) {
8ae6d9c7
GM		 6258 set_bit(ISP_UNRECOVERABLE,
6259 &base_vha->dpc_flags);
6260 ql_dbg(ql_dbg_dpc, base_vha,
6261 0x4021,
6262 "Reset Recovery Failed\n");
f92f82d6 6263 }
8ae6d9c7
GM		 6264 }
6265 }
6266
6267 if (test_and_clear_bit(FX00_TARGET_SCAN,
6268 &base_vha->dpc_flags)) {
6269 ql_dbg(ql_dbg_dpc, base_vha, 0x4022,
6270 "ISPFx00 Target Scan scheduled\n");
6271 if (qlafx00_rescan_isp(base_vha)) {
6272 if (!test_bit(UNLOADING,
6273 &base_vha->dpc_flags))
6274 set_bit(ISP_UNRECOVERABLE,
6275 &base_vha->dpc_flags);
6276 ql_dbg(ql_dbg_dpc, base_vha, 0x401e,
6277 "ISPFx00 Target Scan Failed\n");
6278 }
6279 ql_dbg(ql_dbg_dpc, base_vha, 0x401f,
6280 "ISPFx00 Target Scan End\n");
6281 }
e8f5e95d
AB		 6282 if (test_and_clear_bit(FX00_HOST_INFO_RESEND,
6283 &base_vha->dpc_flags)) {
6284 ql_dbg(ql_dbg_dpc, base_vha, 0x4023,
6285 "ISPFx00 Host Info resend scheduled\n");
6286 qlafx00_fx_disc(base_vha,
6287 &base_vha->hw->mr.fcport,
6288 FXDISC_REG_HOST_INFO);
6289 }
a9083016
GM		 6290 }
6291
e4e3a2ce
QT		 6292 if (test_and_clear_bit(DETECT_SFP_CHANGE,
6293 &base_vha->dpc_flags) &&
6294 !test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) {
6295 qla24xx_detect_sfp(base_vha);
6296
6297 if (ha->flags.detected_lr_sfp !=
6298 ha->flags.using_lr_setting)
6299 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
6300 }
6301
b08abbd9
QT		 6302 if (test_and_clear_bit
6303 (ISP_ABORT_NEEDED, &base_vha->dpc_flags) &&
6304 !test_bit(UNLOADING, &base_vha->dpc_flags)) {
93eca613
QT		 6305 bool do_reset = true;
6306
0645cb83 6307 switch (base_vha->qlini_mode) {
93eca613
QT		 6308 case QLA2XXX_INI_MODE_ENABLED:
6309 break;
6310 case QLA2XXX_INI_MODE_DISABLED:
0645cb83
QT		 6311 if (!qla_tgt_mode_enabled(base_vha) &&
6312 !ha->flags.fw_started)
93eca613
QT		 6313 do_reset = false;
6314 break;
6315 case QLA2XXX_INI_MODE_DUAL:
0645cb83
QT		 6316 if (!qla_dual_mode_enabled(base_vha) &&
6317 !ha->flags.fw_started)
93eca613
QT		 6318 do_reset = false;
6319 break;
6320 default:
6321 break;
6322 }
1da177e4 6323
93eca613 6324 if (do_reset && !(test_and_set_bit(ABORT_ISP_ACTIVE,
e315cd28 6325 &base_vha->dpc_flags))) {
93eca613
QT		 6326 ql_dbg(ql_dbg_dpc, base_vha, 0x4007,
6327 "ISP abort scheduled.\n");
a9083016 6328 if (ha->isp_ops->abort_isp(base_vha)) {
1da177e4
LT		 6329 /* failed. retry later */
6330 set_bit(ISP_ABORT_NEEDED,
e315cd28 6331 &base_vha->dpc_flags);
99363ef8 6332 }
e315cd28
AC		 6333 clear_bit(ABORT_ISP_ACTIVE,
6334 &base_vha->dpc_flags);
93eca613
QT		 6335 ql_dbg(ql_dbg_dpc, base_vha, 0x4008,
6336 "ISP abort end.\n");
99363ef8 6337 }
1da177e4
LT		 6338 }
6339
a394aac8
DJ		 6340 if (test_and_clear_bit(FCPORT_UPDATE_NEEDED,
6341 &base_vha->dpc_flags)) {
e315cd28 6342 qla2x00_update_fcports(base_vha);
c9c5ced9 6343 }
d97994dc 6344
8ae6d9c7
GM		 6345 if (IS_QLAFX00(ha))
6346 goto loop_resync_check;
6347
579d12b5 6348 if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) {
7c3df132
SK		 6349 ql_dbg(ql_dbg_dpc, base_vha, 0x4009,
6350 "Quiescence mode scheduled.\n");
7ec0effd
AD		 6351 if (IS_P3P_TYPE(ha)) {
6352 if (IS_QLA82XX(ha))
6353 qla82xx_device_state_handler(base_vha);
6354 if (IS_QLA8044(ha))
6355 qla8044_device_state_handler(base_vha);
8fcd6b8b
CD		 6356 clear_bit(ISP_QUIESCE_NEEDED,
6357 &base_vha->dpc_flags);
6358 if (!ha->flags.quiesce_owner) {
6359 qla2x00_perform_loop_resync(base_vha);
7ec0effd
AD		 6360 if (IS_QLA82XX(ha)) {
6361 qla82xx_idc_lock(ha);
6362 qla82xx_clear_qsnt_ready(
6363 base_vha);
6364 qla82xx_idc_unlock(ha);
6365 } else if (IS_QLA8044(ha)) {
6366 qla8044_idc_lock(ha);
6367 qla8044_clear_qsnt_ready(
6368 base_vha);
6369 qla8044_idc_unlock(ha);
6370 }
8fcd6b8b
CD		 6371 }
6372 } else {
6373 clear_bit(ISP_QUIESCE_NEEDED,
6374 &base_vha->dpc_flags);
6375 qla2x00_quiesce_io(base_vha);
579d12b5 6376 }
7c3df132
SK		 6377 ql_dbg(ql_dbg_dpc, base_vha, 0x400a,
6378 "Quiescence mode end.\n");
579d12b5
SK		 6379 }
6380
e315cd28 6381 if (test_and_clear_bit(RESET_MARKER_NEEDED,
8ae6d9c7 6382 &base_vha->dpc_flags) &&
e315cd28 6383 (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) {
1da177e4 6384
7c3df132
SK		 6385 ql_dbg(ql_dbg_dpc, base_vha, 0x400b,
6386 "Reset marker scheduled.\n");
e315cd28
AC		 6387 qla2x00_rst_aen(base_vha);
6388 clear_bit(RESET_ACTIVE, &base_vha->dpc_flags);
7c3df132
SK		 6389 ql_dbg(ql_dbg_dpc, base_vha, 0x400c,
6390 "Reset marker end.\n");
1da177e4
LT		 6391 }
6392
6393 /* Retry each device up to login retry count */
4005a995 6394 if (test_bit(RELOGIN_NEEDED, &base_vha->dpc_flags) &&
e315cd28
AC		 6395 !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) &&
6396 atomic_read(&base_vha->loop_state) != LOOP_DOWN) {
1da177e4 6397
4005a995
QT		 6398 if (!base_vha->relogin_jif ||
6399 time_after_eq(jiffies, base_vha->relogin_jif)) {
6400 base_vha->relogin_jif = jiffies + HZ;
6401 clear_bit(RELOGIN_NEEDED, &base_vha->dpc_flags);
6402
9b3e0f4d 6403 ql_dbg(ql_dbg_disc, base_vha, 0x400d,
4005a995 6404 "Relogin scheduled.\n");
9b3e0f4d 6405 qla24xx_post_relogin_work(base_vha);
4005a995 6406 }
1da177e4 6407 }
8ae6d9c7 6408loop_resync_check:
e315cd28 6409 if (test_and_clear_bit(LOOP_RESYNC_NEEDED,
8ae6d9c7 6410 &base_vha->dpc_flags)) {
1da177e4 6411
7c3df132
SK		 6412 ql_dbg(ql_dbg_dpc, base_vha, 0x400f,
6413 "Loop resync scheduled.\n");
1da177e4
LT		 6414
6415 if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE,
e315cd28 6416 &base_vha->dpc_flags))) {
1da177e4 6417
52c82823 6418 qla2x00_loop_resync(base_vha);
1da177e4 6419
e315cd28
AC		 6420 clear_bit(LOOP_RESYNC_ACTIVE,
6421 &base_vha->dpc_flags);
1da177e4
LT		 6422 }
6423
7c3df132
SK		 6424 ql_dbg(ql_dbg_dpc, base_vha, 0x4010,
6425 "Loop resync end.\n");
1da177e4
LT		 6426 }
6427
8ae6d9c7
GM		 6428 if (IS_QLAFX00(ha))
6429 goto intr_on_check;
6430
e315cd28
AC		 6431 if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) &&
6432 atomic_read(&base_vha->loop_state) == LOOP_READY) {
6433 clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags);
6434 qla2xxx_flash_npiv_conf(base_vha);
272976ca
AV		 6435 }
6436
8ae6d9c7 6437intr_on_check:
1da177e4 6438 if (!ha->interrupts_on)
fd34f556 6439 ha->isp_ops->enable_intrs(ha);
1da177e4 6440
e315cd28 6441 if (test_and_clear_bit(BEACON_BLINK_NEEDED,
90b604f2
HM		 6442 &base_vha->dpc_flags)) {
6443 if (ha->beacon_blink_led == 1)
6444 ha->isp_ops->beacon_blink(base_vha);
6445 }
f6df144c 6446
d7459527
MH		 6447 /* qpair online check */
6448 if (test_and_clear_bit(QPAIR_ONLINE_CHECK_NEEDED,
6449 &base_vha->dpc_flags)) {
6450 if (ha->flags.eeh_busy ||
6451 ha->flags.pci_channel_io_perm_failure)
6452 online = 0;
6453 else
6454 online = 1;
6455
6456 mutex_lock(&ha->mq_lock);
6457 list_for_each_entry(qpair, &base_vha->qp_list,
6458 qp_list_elem)
6459 qpair->online = online;
6460 mutex_unlock(&ha->mq_lock);
6461 }
6462
8b4673ba
QT		 6463 if (test_and_clear_bit(SET_NVME_ZIO_THRESHOLD_NEEDED,
6464 &base_vha->dpc_flags)) {
deeae7a6
DG		 6465 ql_log(ql_log_info, base_vha, 0xffffff,
6466 "nvme: SET ZIO Activity exchange threshold to %d.\n",
6467 ha->nvme_last_rptd_aen);
8b4673ba
QT		 6468 if (qla27xx_set_zio_threshold(base_vha,
6469 ha->nvme_last_rptd_aen)) {
deeae7a6 6470 ql_log(ql_log_info, base_vha, 0xffffff,
8b4673ba
QT		 6471 "nvme: Unable to SET ZIO Activity exchange threshold to %d.\n",
6472 ha->nvme_last_rptd_aen);
deeae7a6
DG		 6473 }
6474 }
6475
8b4673ba
QT		 6476 if (test_and_clear_bit(SET_ZIO_THRESHOLD_NEEDED,
6477 &base_vha->dpc_flags)) {
6478 ql_log(ql_log_info, base_vha, 0xffffff,
6479 "SET ZIO Activity exchange threshold to %d.\n",
6480 ha->last_zio_threshold);
6481 qla27xx_set_zio_threshold(base_vha,
6482 ha->last_zio_threshold);
6483 }
6484
8ae6d9c7
GM		 6485 if (!IS_QLAFX00(ha))
6486 qla2x00_do_dpc_all_vps(base_vha);
2c3dfe3f 6487
48acad09
QT		 6488 if (test_and_clear_bit(N2N_LINK_RESET,
6489 &base_vha->dpc_flags)) {
6490 qla2x00_lip_reset(base_vha);
6491 }
6492
1da177e4 6493 ha->dpc_active = 0;
c142caf0 6494end_loop:
563585ec 6495 set_current_state(TASK_INTERRUPTIBLE);
1da177e4 6496 } /* End of while(1) */
563585ec 6497 __set_current_state(TASK_RUNNING);
1da177e4 6498
7c3df132
SK		 6499 ql_dbg(ql_dbg_dpc, base_vha, 0x4011,
6500 "DPC handler exiting.\n");
1da177e4
LT		 6501
6502 /*
6503 * Make sure that nobody tries to wake us up again.
6504 */
1da177e4
LT		 6505 ha->dpc_active = 0;
6506
ac280b67
AV		 6507 /* Cleanup any residual CTX SRBs. */
6508 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
6509
39a11240
CH		 6510 return 0;
6511}
6512
6513void
e315cd28 6514qla2xxx_wake_dpc(struct scsi_qla_host *vha)
39a11240 6515{
e315cd28 6516 struct qla_hw_data *ha = vha->hw;
c795c1e4
AV		 6517 struct task_struct *t = ha->dpc_thread;
6518
e315cd28 6519 if (!test_bit(UNLOADING, &vha->dpc_flags) && t)
c795c1e4 6520 wake_up_process(t);
1da177e4
LT		 6521}
6522
1da177e4
LT		 6523/*
6524* qla2x00_rst_aen
6525* Processes asynchronous reset.
6526*
6527* Input:
6528* ha = adapter block pointer.
6529*/
6530static void
e315cd28 6531qla2x00_rst_aen(scsi_qla_host_t *vha)
1da177e4 6532{
e315cd28
AC		 6533 if (vha->flags.online && !vha->flags.reset_active &&
6534 !atomic_read(&vha->loop_down_timer) &&
6535 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) {
1da177e4 6536 do {
e315cd28 6537 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
1da177e4
LT		 6538
6539 /*
6540 * Issue marker command only when we are going to start
6541 * the I/O.
6542 */
e315cd28
AC		 6543 vha->marker_needed = 1;
6544 } while (!atomic_read(&vha->loop_down_timer) &&
6545 (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)));
1da177e4
LT		 6546 }
6547}
6548
1da177e4
LT		 6549/**************************************************************************
6550* qla2x00_timer
6551*
6552* Description:
6553* One second timer
6554*
6555* Context: Interrupt
6556***************************************************************************/
2c3dfe3f 6557void
8e5f4ba0 6558qla2x00_timer(struct timer_list *t)
1da177e4 6559{
8e5f4ba0 6560 scsi_qla_host_t *vha = from_timer(vha, t, timer);
1da177e4 6561 unsigned long cpu_flags = 0;
1da177e4
LT		 6562 int start_dpc = 0;
6563 int index;
6564 srb_t *sp;
85880801 6565 uint16_t w;
e315cd28 6566 struct qla_hw_data *ha = vha->hw;
73208dfd 6567 struct req_que *req;
85880801 6568
a5b36321 6569 if (ha->flags.eeh_busy) {
7c3df132
SK		 6570 ql_dbg(ql_dbg_timer, vha, 0x6000,
6571 "EEH = %d, restarting timer.\n",
6572 ha->flags.eeh_busy);
a5b36321
LC		 6573 qla2x00_restart_timer(vha, WATCH_INTERVAL);
6574 return;
6575 }
6576
f3ddac19
CD		 6577 /*
6578 * Hardware read to raise pending EEH errors during mailbox waits. If
6579 * the read returns -1 then disable the board.
6580 */
6581 if (!pci_channel_offline(ha->pdev)) {
85880801 6582 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w);
c821e0d5 6583 qla2x00_check_reg16_for_disconnect(vha, w);
f3ddac19 6584 }
1da177e4 6585
cefcaba6 6586 /* Make sure qla82xx_watchdog is run only for physical port */
7ec0effd 6587 if (!vha->vp_idx && IS_P3P_TYPE(ha)) {
579d12b5
SK		 6588 if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags))
6589 start_dpc++;
7ec0effd
AD		 6590 if (IS_QLA82XX(ha))
6591 qla82xx_watchdog(vha);
6592 else if (IS_QLA8044(ha))
6593 qla8044_watchdog(vha);
579d12b5
SK		 6594 }
6595
8ae6d9c7
GM		 6596 if (!vha->vp_idx && IS_QLAFX00(ha))
6597 qlafx00_timer_routine(vha);
6598
1da177e4 6599 /* Loop down handler. */
e315cd28 6600 if (atomic_read(&vha->loop_down_timer) > 0 &&
8f7daead
GM		 6601 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) &&
6602 !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags))
e315cd28 6603 && vha->flags.online) {
1da177e4 6604
e315cd28
AC		 6605 if (atomic_read(&vha->loop_down_timer) ==
6606 vha->loop_down_abort_time) {
1da177e4 6607
7c3df132
SK		 6608 ql_log(ql_log_info, vha, 0x6008,
6609 "Loop down - aborting the queues before time expires.\n");
1da177e4 6610
e315cd28
AC		 6611 if (!IS_QLA2100(ha) && vha->link_down_timeout)
6612 atomic_set(&vha->loop_state, LOOP_DEAD);
1da177e4 6613
f08b7251
AV		 6614 /*
6615 * Schedule an ISP abort to return any FCP2-device
6616 * commands.
6617 */
2c3dfe3f 6618 /* NPIV - scan physical port only */
e315cd28 6619 if (!vha->vp_idx) {
2c3dfe3f
SJ		 6620 spin_lock_irqsave(&ha->hardware_lock,
6621 cpu_flags);
73208dfd 6622 req = ha->req_q_map[0];
2c3dfe3f 6623 for (index = 1;
8d93f550 6624 index < req->num_outstanding_cmds;
2c3dfe3f
SJ		 6625 index++) {
6626 fc_port_t *sfcp;
6627
e315cd28 6628 sp = req->outstanding_cmds[index];
2c3dfe3f
SJ		 6629 if (!sp)
6630 continue;
c5419e26
QT		 6631 if (sp->cmd_type != TYPE_SRB)
6632 continue;
9ba56b95 6633 if (sp->type != SRB_SCSI_CMD)
cf53b069 6634 continue;
2c3dfe3f 6635 sfcp = sp->fcport;
f08b7251 6636 if (!(sfcp->flags & FCF_FCP2_DEVICE))
2c3dfe3f 6637 continue;
bdf79621 6638
8f7daead
GM		 6639 if (IS_QLA82XX(ha))
6640 set_bit(FCOE_CTX_RESET_NEEDED,
6641 &vha->dpc_flags);
6642 else
6643 set_bit(ISP_ABORT_NEEDED,
e315cd28 6644 &vha->dpc_flags);
2c3dfe3f
SJ		 6645 break;
6646 }
6647 spin_unlock_irqrestore(&ha->hardware_lock,
e315cd28 6648 cpu_flags);
1da177e4 6649 }
1da177e4
LT		 6650 start_dpc++;
6651 }
6652
6653 /* if the loop has been down for 4 minutes, reinit adapter */
e315cd28 6654 if (atomic_dec_and_test(&vha->loop_down_timer) != 0) {
0d6e61bc 6655 if (!(vha->device_flags & DFLG_NO_CABLE)) {
7c3df132 6656 ql_log(ql_log_warn, vha, 0x6009,
1da177e4
LT		 6657 "Loop down - aborting ISP.\n");
6658
8f7daead
GM		 6659 if (IS_QLA82XX(ha))
6660 set_bit(FCOE_CTX_RESET_NEEDED,
6661 &vha->dpc_flags);
6662 else
6663 set_bit(ISP_ABORT_NEEDED,
6664 &vha->dpc_flags);
1da177e4
LT		 6665 }
6666 }
7c3df132
SK		 6667 ql_dbg(ql_dbg_timer, vha, 0x600a,
6668 "Loop down - seconds remaining %d.\n",
6669 atomic_read(&vha->loop_down_timer));
1da177e4 6670 }
cefcaba6
SK		 6671 /* Check if beacon LED needs to be blinked for physical host only */
6672 if (!vha->vp_idx && (ha->beacon_blink_led == 1)) {
999916dc 6673 /* There is no beacon_blink function for ISP82xx */
7ec0effd 6674 if (!IS_P3P_TYPE(ha)) {
999916dc
SK		 6675 set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags);
6676 start_dpc++;
6677 }
f6df144c 6678 }
6679
550bf57d 6680 /* Process any deferred work. */
9b3e0f4d
QT		 6681 if (!list_empty(&vha->work_list)) {
6682 unsigned long flags;
6683 bool q = false;
6684
6685 spin_lock_irqsave(&vha->work_lock, flags);
6686 if (!test_and_set_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags))
6687 q = true;
6688 spin_unlock_irqrestore(&vha->work_lock, flags);
6689 if (q)
6690 queue_work(vha->hw->wq, &vha->iocb_work);
6691 }
550bf57d 6692
7401bc18
DG		 6693 /*
6694 * FC-NVME
6695 * see if the active AEN count has changed from what was last reported.
6696 */
b2d1453a
GM		 6697 if (!vha->vp_idx &&
6698 (atomic_read(&ha->nvme_active_aen_cnt) != ha->nvme_last_rptd_aen) &&
6699 ha->zio_mode == QLA_ZIO_MODE_6 &&
6700 !ha->flags.host_shutting_down) {
7401bc18 6701 ql_log(ql_log_info, vha, 0x3002,
8b4673ba
QT		 6702 "nvme: Sched: Set ZIO exchange threshold to %d.\n",
6703 ha->nvme_last_rptd_aen);
deeae7a6 6704 ha->nvme_last_rptd_aen = atomic_read(&ha->nvme_active_aen_cnt);
8b4673ba
QT		 6705 set_bit(SET_NVME_ZIO_THRESHOLD_NEEDED, &vha->dpc_flags);
6706 start_dpc++;
6707 }
6708
6709 if (!vha->vp_idx &&
6710 (atomic_read(&ha->zio_threshold) != ha->last_zio_threshold) &&
6711 (ha->zio_mode == QLA_ZIO_MODE_6) &&
ecc89f25 6712 (IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))) {
8b4673ba
QT		 6713 ql_log(ql_log_info, vha, 0x3002,
6714 "Sched: Set ZIO exchange threshold to %d.\n",
6715 ha->last_zio_threshold);
6716 ha->last_zio_threshold = atomic_read(&ha->zio_threshold);
deeae7a6
DG		 6717 set_bit(SET_ZIO_THRESHOLD_NEEDED, &vha->dpc_flags);
6718 start_dpc++;
7401bc18
DG		 6719 }
6720
1da177e4 6721 /* Schedule the DPC routine if needed */
e315cd28
AC		 6722 if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) ||
6723 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) ||
6724 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags) ||
1da177e4 6725 start_dpc ||
e315cd28
AC		 6726 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) ||
6727 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) ||
a9083016
GM		 6728 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) ||
6729 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) ||
e315cd28 6730 test_bit(VP_DPC_NEEDED, &vha->dpc_flags) ||
50280c01 6731 test_bit(RELOGIN_NEEDED, &vha->dpc_flags))) {
7c3df132
SK		 6732 ql_dbg(ql_dbg_timer, vha, 0x600b,
6733 "isp_abort_needed=%d loop_resync_needed=%d "
6734 "fcport_update_needed=%d start_dpc=%d "
6735 "reset_marker_needed=%d",
6736 test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags),
6737 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags),
6738 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags),
6739 start_dpc,
6740 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags));
6741 ql_dbg(ql_dbg_timer, vha, 0x600c,
6742 "beacon_blink_needed=%d isp_unrecoverable=%d "
6743 "fcoe_ctx_reset_needed=%d vp_dpc_needed=%d "
50280c01 6744 "relogin_needed=%d.\n",
7c3df132
SK		 6745 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags),
6746 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags),
6747 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags),
6748 test_bit(VP_DPC_NEEDED, &vha->dpc_flags),
50280c01 6749 test_bit(RELOGIN_NEEDED, &vha->dpc_flags));
e315cd28 6750 qla2xxx_wake_dpc(vha);
7c3df132 6751 }
1da177e4 6752
e315cd28 6753 qla2x00_restart_timer(vha, WATCH_INTERVAL);
1da177e4
LT		 6754}
6755
5433383e
AV		 6756/* Firmware interface routines. */
6757
5433383e
AV		 6758#define FW_ISP21XX 0
6759#define FW_ISP22XX 1
6760#define FW_ISP2300 2
6761#define FW_ISP2322 3
48c02fde 6762#define FW_ISP24XX 4
c3a2f0df 6763#define FW_ISP25XX 5
3a03eb79 6764#define FW_ISP81XX 6
a9083016 6765#define FW_ISP82XX 7
6246b8a1
GM		 6766#define FW_ISP2031 8
6767#define FW_ISP8031 9
2c5bbbb2 6768#define FW_ISP27XX 10
ecc89f25 6769#define FW_ISP28XX 11
5433383e 6770
bb8ee499
AV		 6771#define FW_FILE_ISP21XX "ql2100_fw.bin"
6772#define FW_FILE_ISP22XX "ql2200_fw.bin"
6773#define FW_FILE_ISP2300 "ql2300_fw.bin"
6774#define FW_FILE_ISP2322 "ql2322_fw.bin"
6775#define FW_FILE_ISP24XX "ql2400_fw.bin"
c3a2f0df 6776#define FW_FILE_ISP25XX "ql2500_fw.bin"
3a03eb79 6777#define FW_FILE_ISP81XX "ql8100_fw.bin"
a9083016 6778#define FW_FILE_ISP82XX "ql8200_fw.bin"
6246b8a1
GM		 6779#define FW_FILE_ISP2031 "ql2600_fw.bin"
6780#define FW_FILE_ISP8031 "ql8300_fw.bin"
2c5bbbb2 6781#define FW_FILE_ISP27XX "ql2700_fw.bin"
ecc89f25 6782#define FW_FILE_ISP28XX "ql2800_fw.bin"
f73cb695 6783
bb8ee499 6784
e1e82b6f 6785static DEFINE_MUTEX(qla_fw_lock);
5433383e 6786
ecc89f25 6787static struct fw_blob qla_fw_blobs[] = {
bb8ee499
AV		 6788 { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, },
6789 { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, },
6790 { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, },
6791 { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, },
6792 { .name = FW_FILE_ISP24XX, },
c3a2f0df 6793 { .name = FW_FILE_ISP25XX, },
3a03eb79 6794 { .name = FW_FILE_ISP81XX, },
a9083016 6795 { .name = FW_FILE_ISP82XX, },
6246b8a1
GM		 6796 { .name = FW_FILE_ISP2031, },
6797 { .name = FW_FILE_ISP8031, },
2c5bbbb2 6798 { .name = FW_FILE_ISP27XX, },
ecc89f25
JC		 6799 { .name = FW_FILE_ISP28XX, },
6800 { .name = NULL, },
5433383e
AV		 6801};
6802
6803struct fw_blob *
e315cd28 6804qla2x00_request_firmware(scsi_qla_host_t *vha)
5433383e 6805{
e315cd28 6806 struct qla_hw_data *ha = vha->hw;
5433383e
AV		 6807 struct fw_blob *blob;
6808
5433383e
AV		 6809 if (IS_QLA2100(ha)) {
6810 blob = &qla_fw_blobs[FW_ISP21XX];
6811 } else if (IS_QLA2200(ha)) {
6812 blob = &qla_fw_blobs[FW_ISP22XX];
48c02fde 6813 } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
5433383e 6814 blob = &qla_fw_blobs[FW_ISP2300];
48c02fde 6815 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
5433383e 6816 blob = &qla_fw_blobs[FW_ISP2322];
4d4df193 6817 } else if (IS_QLA24XX_TYPE(ha)) {
5433383e 6818 blob = &qla_fw_blobs[FW_ISP24XX];
c3a2f0df
AV		 6819 } else if (IS_QLA25XX(ha)) {
6820 blob = &qla_fw_blobs[FW_ISP25XX];
3a03eb79
AV		 6821 } else if (IS_QLA81XX(ha)) {
6822 blob = &qla_fw_blobs[FW_ISP81XX];
a9083016
GM		 6823 } else if (IS_QLA82XX(ha)) {
6824 blob = &qla_fw_blobs[FW_ISP82XX];
6246b8a1
GM		 6825 } else if (IS_QLA2031(ha)) {
6826 blob = &qla_fw_blobs[FW_ISP2031];
6827 } else if (IS_QLA8031(ha)) {
6828 blob = &qla_fw_blobs[FW_ISP8031];
2c5bbbb2
JC		 6829 } else if (IS_QLA27XX(ha)) {
6830 blob = &qla_fw_blobs[FW_ISP27XX];
ecc89f25
JC		 6831 } else if (IS_QLA28XX(ha)) {
6832 blob = &qla_fw_blobs[FW_ISP28XX];
8a655229
DC		 6833 } else {
6834 return NULL;
5433383e
AV		 6835 }
6836
ecc89f25
JC		 6837 if (!blob->name)
6838 return NULL;
6839
e1e82b6f 6840 mutex_lock(&qla_fw_lock);
5433383e
AV		 6841 if (blob->fw)
6842 goto out;
6843
6844 if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) {
7c3df132
SK		 6845 ql_log(ql_log_warn, vha, 0x0063,
6846 "Failed to load firmware image (%s).\n", blob->name);
5433383e
AV		 6847 blob->fw = NULL;
6848 blob = NULL;
5433383e
AV		 6849 }
6850
6851out:
e1e82b6f 6852 mutex_unlock(&qla_fw_lock);
5433383e
AV		 6853 return blob;
6854}
6855
6856static void
6857qla2x00_release_firmware(void)
6858{
ecc89f25 6859 struct fw_blob *blob;
5433383e 6860
e1e82b6f 6861 mutex_lock(&qla_fw_lock);
ecc89f25
JC		 6862 for (blob = qla_fw_blobs; blob->name; blob++)
6863 release_firmware(blob->fw);
e1e82b6f 6864 mutex_unlock(&qla_fw_lock);
5433383e
AV		 6865}
6866
5386a4e6
QT		 6867static void qla_pci_error_cleanup(scsi_qla_host_t *vha)
6868{
6869 struct qla_hw_data *ha = vha->hw;
6870 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
6871 struct qla_qpair *qpair = NULL;
6872 struct scsi_qla_host *vp;
6873 fc_port_t *fcport;
6874 int i;
6875 unsigned long flags;
6876
6877 ha->chip_reset++;
6878
6879 ha->base_qpair->chip_reset = ha->chip_reset;
6880 for (i = 0; i < ha->max_qpairs; i++) {
6881 if (ha->queue_pair_map[i])
6882 ha->queue_pair_map[i]->chip_reset =
6883 ha->base_qpair->chip_reset;
6884 }
6885
6886 /* purge MBox commands */
6887 if (atomic_read(&ha->num_pend_mbx_stage3)) {
6888 clear_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags);
6889 complete(&ha->mbx_intr_comp);
6890 }
6891
6892 i = 0;
6893
6894 while (atomic_read(&ha->num_pend_mbx_stage3) ||
6895 atomic_read(&ha->num_pend_mbx_stage2) ||
6896 atomic_read(&ha->num_pend_mbx_stage1)) {
6897 msleep(20);
6898 i++;
6899 if (i > 50)
6900 break;
6901 }
6902
6903 ha->flags.purge_mbox = 0;
6904
6905 mutex_lock(&ha->mq_lock);
6906 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem)
6907 qpair->online = 0;
6908 mutex_unlock(&ha->mq_lock);
6909
6910 qla2x00_mark_all_devices_lost(vha, 0);
6911
6912 spin_lock_irqsave(&ha->vport_slock, flags);
6913 list_for_each_entry(vp, &ha->vp_list, list) {
6914 atomic_inc(&vp->vref_count);
6915 spin_unlock_irqrestore(&ha->vport_slock, flags);
6916 qla2x00_mark_all_devices_lost(vp, 0);
6917 spin_lock_irqsave(&ha->vport_slock, flags);
6918 atomic_dec(&vp->vref_count);
6919 }
6920 spin_unlock_irqrestore(&ha->vport_slock, flags);
6921
6922 /* Clear all async request states across all VPs. */
6923 list_for_each_entry(fcport, &vha->vp_fcports, list)
6924 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
6925
6926 spin_lock_irqsave(&ha->vport_slock, flags);
6927 list_for_each_entry(vp, &ha->vp_list, list) {
6928 atomic_inc(&vp->vref_count);
6929 spin_unlock_irqrestore(&ha->vport_slock, flags);
6930 list_for_each_entry(fcport, &vp->vp_fcports, list)
6931 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
6932 spin_lock_irqsave(&ha->vport_slock, flags);
6933 atomic_dec(&vp->vref_count);
6934 }
6935 spin_unlock_irqrestore(&ha->vport_slock, flags);
6936}
6937
6938
14e660e6
SJ		 6939static pci_ers_result_t
6940qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
6941{
85880801
AV		 6942 scsi_qla_host_t *vha = pci_get_drvdata(pdev);
6943 struct qla_hw_data *ha = vha->hw;
6944
7c3df132
SK		 6945 ql_dbg(ql_dbg_aer, vha, 0x9000,
6946 "PCI error detected, state %x.\n", state);
b9b12f73 6947
efdb5760
SC		 6948 if (!atomic_read(&pdev->enable_cnt)) {
6949 ql_log(ql_log_info, vha, 0xffff,
6950 "PCI device is disabled,state %x\n", state);
6951 return PCI_ERS_RESULT_NEED_RESET;
6952 }
6953
14e660e6
SJ		 6954 switch (state) {
6955 case pci_channel_io_normal:
85880801 6956 ha->flags.eeh_busy = 0;
c38d1baf 6957 if (ql2xmqsupport || ql2xnvmeenable) {
d7459527
MH		 6958 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags);
6959 qla2xxx_wake_dpc(vha);
6960 }
14e660e6
SJ		 6961 return PCI_ERS_RESULT_CAN_RECOVER;
6962 case pci_channel_io_frozen:
85880801 6963 ha->flags.eeh_busy = 1;
5386a4e6 6964 qla_pci_error_cleanup(vha);
14e660e6
SJ		 6965 return PCI_ERS_RESULT_NEED_RESET;
6966 case pci_channel_io_perm_failure:
85880801
AV		 6967 ha->flags.pci_channel_io_perm_failure = 1;
6968 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
c38d1baf 6969 if (ql2xmqsupport || ql2xnvmeenable) {
d7459527
MH		 6970 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags);
6971 qla2xxx_wake_dpc(vha);
6972 }
14e660e6
SJ		 6973 return PCI_ERS_RESULT_DISCONNECT;
6974 }
6975 return PCI_ERS_RESULT_NEED_RESET;
6976}
6977
6978static pci_ers_result_t
6979qla2xxx_pci_mmio_enabled(struct pci_dev *pdev)
6980{
6981 int risc_paused = 0;
6982 uint32_t stat;
6983 unsigned long flags;
e315cd28
AC		 6984 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
6985 struct qla_hw_data *ha = base_vha->hw;
14e660e6
SJ		 6986 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
6987 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
6988
bcc5b6d3
SK		 6989 if (IS_QLA82XX(ha))
6990 return PCI_ERS_RESULT_RECOVERED;
6991
14e660e6
SJ		 6992 spin_lock_irqsave(&ha->hardware_lock, flags);
6993 if (IS_QLA2100(ha) || IS_QLA2200(ha)){
6994 stat = RD_REG_DWORD(&reg->hccr);
6995 if (stat & HCCR_RISC_PAUSE)
6996 risc_paused = 1;
6997 } else if (IS_QLA23XX(ha)) {
6998 stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
6999 if (stat & HSR_RISC_PAUSED)
7000 risc_paused = 1;
7001 } else if (IS_FWI2_CAPABLE(ha)) {
7002 stat = RD_REG_DWORD(&reg24->host_status);
7003 if (stat & HSRX_RISC_PAUSED)
7004 risc_paused = 1;
7005 }
7006 spin_unlock_irqrestore(&ha->hardware_lock, flags);
7007
7008 if (risc_paused) {
7c3df132
SK		 7009 ql_log(ql_log_info, base_vha, 0x9003,
7010 "RISC paused -- mmio_enabled, Dumping firmware.\n");
e315cd28 7011 ha->isp_ops->fw_dump(base_vha, 0);
14e660e6
SJ		 7012
7013 return PCI_ERS_RESULT_NEED_RESET;
7014 } else
7015 return PCI_ERS_RESULT_RECOVERED;
7016}
7017
7018static pci_ers_result_t
7019qla2xxx_pci_slot_reset(struct pci_dev *pdev)
7020{
7021 pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT;
e315cd28
AC		 7022 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
7023 struct qla_hw_data *ha = base_vha->hw;
5386a4e6
QT		 7024 int rc;
7025 struct qla_qpair *qpair = NULL;
09483916 7026
7c3df132
SK		 7027 ql_dbg(ql_dbg_aer, base_vha, 0x9004,
7028 "Slot Reset.\n");
85880801 7029
90a86fc0
JC		 7030 /* Workaround: qla2xxx driver which access hardware earlier
7031 * needs error state to be pci_channel_io_online.
7032 * Otherwise mailbox command timesout.
7033 */
7034 pdev->error_state = pci_channel_io_normal;
7035
7036 pci_restore_state(pdev);
7037
8c1496bd
RL		 7038 /* pci_restore_state() clears the saved_state flag of the device
7039 * save restored state which resets saved_state flag
7040 */
7041 pci_save_state(pdev);
7042
09483916
BH		 7043 if (ha->mem_only)
7044 rc = pci_enable_device_mem(pdev);
7045 else
7046 rc = pci_enable_device(pdev);
14e660e6 7047
09483916 7048 if (rc) {
7c3df132 7049 ql_log(ql_log_warn, base_vha, 0x9005,
14e660e6 7050 "Can't re-enable PCI device after reset.\n");
a5b36321 7051 goto exit_slot_reset;
14e660e6 7052 }
14e660e6 7053
90a86fc0 7054
e315cd28 7055 if (ha->isp_ops->pci_config(base_vha))
a5b36321
LC		 7056 goto exit_slot_reset;
7057
5386a4e6
QT		 7058 mutex_lock(&ha->mq_lock);
7059 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem)
7060 qpair->online = 1;
7061 mutex_unlock(&ha->mq_lock);
85880801 7062
5386a4e6 7063 base_vha->flags.online = 1;
e315cd28 7064 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
a9083016 7065 if (ha->isp_ops->abort_isp(base_vha) == QLA_SUCCESS)
14e660e6 7066 ret = PCI_ERS_RESULT_RECOVERED;
e315cd28 7067 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
14e660e6 7068
90a86fc0 7069
a5b36321 7070exit_slot_reset:
7c3df132
SK		 7071 ql_dbg(ql_dbg_aer, base_vha, 0x900e,
7072 "slot_reset return %x.\n", ret);
85880801 7073
14e660e6
SJ		 7074 return ret;
7075}
7076
7077static void
7078qla2xxx_pci_resume(struct pci_dev *pdev)
7079{
e315cd28
AC		 7080 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
7081 struct qla_hw_data *ha = base_vha->hw;
14e660e6
SJ		 7082 int ret;
7083
7c3df132
SK		 7084 ql_dbg(ql_dbg_aer, base_vha, 0x900f,
7085 "pci_resume.\n");
85880801 7086
5386a4e6
QT		 7087 ha->flags.eeh_busy = 0;
7088
e315cd28 7089 ret = qla2x00_wait_for_hba_online(base_vha);
14e660e6 7090 if (ret != QLA_SUCCESS) {
7c3df132
SK		 7091 ql_log(ql_log_fatal, base_vha, 0x9002,
7092 "The device failed to resume I/O from slot/link_reset.\n");
14e660e6 7093 }
14e660e6
SJ		 7094}
7095
590f806d
QT		 7096static void
7097qla_pci_reset_prepare(struct pci_dev *pdev)
7098{
7099 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
7100 struct qla_hw_data *ha = base_vha->hw;
7101 struct qla_qpair *qpair;
7102
7103 ql_log(ql_log_warn, base_vha, 0xffff,
7104 "%s.\n", __func__);
7105
7106 /*
7107 * PCI FLR/function reset is about to reset the
7108 * slot. Stop the chip to stop all DMA access.
7109 * It is assumed that pci_reset_done will be called
7110 * after FLR to resume Chip operation.
7111 */
7112 ha->flags.eeh_busy = 1;
7113 mutex_lock(&ha->mq_lock);
7114 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem)
7115 qpair->online = 0;
7116 mutex_unlock(&ha->mq_lock);
7117
7118 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
7119 qla2x00_abort_isp_cleanup(base_vha);
7120 qla2x00_abort_all_cmds(base_vha, DID_RESET << 16);
7121}
7122
7123static void
7124qla_pci_reset_done(struct pci_dev *pdev)
7125{
7126 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
7127 struct qla_hw_data *ha = base_vha->hw;
7128 struct qla_qpair *qpair;
7129
7130 ql_log(ql_log_warn, base_vha, 0xffff,
7131 "%s.\n", __func__);
7132
7133 /*
7134 * FLR just completed by PCI layer. Resume adapter
7135 */
7136 ha->flags.eeh_busy = 0;
7137 mutex_lock(&ha->mq_lock);
7138 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem)
7139 qpair->online = 1;
7140 mutex_unlock(&ha->mq_lock);
7141
7142 base_vha->flags.online = 1;
7143 ha->isp_ops->abort_isp(base_vha);
7144 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
7145}
7146
5601236b
MH		 7147static int qla2xxx_map_queues(struct Scsi_Host *shost)
7148{
d68b850e 7149 int rc;
5601236b 7150 scsi_qla_host_t *vha = (scsi_qla_host_t *)shost->hostdata;
485b0eca 7151 struct blk_mq_queue_map *qmap = &shost->tag_set.map[HCTX_TYPE_DEFAULT];
5601236b 7152
f3e02695 7153 if (USER_CTRL_IRQ(vha->hw) || !vha->hw->mqiobase)
ed76e329 7154 rc = blk_mq_map_queues(qmap);
d68b850e 7155 else
f0783d43 7156 rc = blk_mq_pci_map_queues(qmap, vha->hw->pdev, vha->irq_offset);
d68b850e 7157 return rc;
5601236b
MH		 7158}
7159
6515ad71
BVA		 7160struct scsi_host_template qla2xxx_driver_template = {
7161 .module = THIS_MODULE,
7162 .name = QLA2XXX_DRIVER_NAME,
7163 .queuecommand = qla2xxx_queuecommand,
7164
7165 .eh_timed_out = fc_eh_timed_out,
7166 .eh_abort_handler = qla2xxx_eh_abort,
7167 .eh_device_reset_handler = qla2xxx_eh_device_reset,
7168 .eh_target_reset_handler = qla2xxx_eh_target_reset,
7169 .eh_bus_reset_handler = qla2xxx_eh_bus_reset,
7170 .eh_host_reset_handler = qla2xxx_eh_host_reset,
7171
7172 .slave_configure = qla2xxx_slave_configure,
7173
7174 .slave_alloc = qla2xxx_slave_alloc,
7175 .slave_destroy = qla2xxx_slave_destroy,
7176 .scan_finished = qla2xxx_scan_finished,
7177 .scan_start = qla2xxx_scan_start,
7178 .change_queue_depth = scsi_change_queue_depth,
7179 .map_queues = qla2xxx_map_queues,
7180 .this_id = -1,
7181 .cmd_per_lun = 3,
7182 .sg_tablesize = SG_ALL,
7183
7184 .max_sectors = 0xFFFF,
7185 .shost_attrs = qla2x00_host_attrs,
7186
7187 .supported_mode = MODE_INITIATOR,
7188 .track_queue_depth = 1,
7189};
7190
a55b2d21 7191static const struct pci_error_handlers qla2xxx_err_handler = {
14e660e6
SJ		 7192 .error_detected = qla2xxx_pci_error_detected,
7193 .mmio_enabled = qla2xxx_pci_mmio_enabled,
7194 .slot_reset = qla2xxx_pci_slot_reset,
7195 .resume = qla2xxx_pci_resume,
590f806d
QT		 7196 .reset_prepare = qla_pci_reset_prepare,
7197 .reset_done = qla_pci_reset_done,
14e660e6
SJ		 7198};
7199
5433383e 7200static struct pci_device_id qla2xxx_pci_tbl[] = {
47f5e069
AV		 7201 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) },
7202 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) },
7203 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) },
7204 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) },
7205 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) },
7206 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) },
7207 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) },
7208 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) },
7209 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) },
4d4df193 7210 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) },
47f5e069
AV		 7211 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) },
7212 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) },
c3a2f0df 7213 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) },
6246b8a1 7214 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2031) },
3a03eb79 7215 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) },
a9083016 7216 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) },
650f528f 7217 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8031) },
8ae6d9c7 7218 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISPF001) },
7ec0effd 7219 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8044) },
f73cb695 7220 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2071) },
2c5bbbb2 7221 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2271) },
2b48992f 7222 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2261) },
ecc89f25
JC		 7223 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2061) },
7224 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2081) },
7225 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2281) },
7226 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2089) },
7227 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2289) },
5433383e
AV		 7228 { 0 },
7229};
7230MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl);
7231
fca29703 7232static struct pci_driver qla2xxx_pci_driver = {
cb63067a 7233 .name = QLA2XXX_DRIVER_NAME,
0a21ef1e
JB		 7234 .driver = {
7235 .owner = THIS_MODULE,
7236 },
fca29703 7237 .id_table = qla2xxx_pci_tbl,
7ee61397 7238 .probe = qla2x00_probe_one,
4c993f76 7239 .remove = qla2x00_remove_one,
e30d1756 7240 .shutdown = qla2x00_shutdown,
14e660e6 7241 .err_handler = &qla2xxx_err_handler,
fca29703
AV		 7242};
7243
75ef9de1 7244static const struct file_operations apidev_fops = {
6a03b4cd 7245 .owner = THIS_MODULE,
6038f373 7246 .llseek = noop_llseek,
6a03b4cd
HZ		 7247};
7248
1da177e4
LT		 7249/**
7250 * qla2x00_module_init - Module initialization.
7251 **/
7252static int __init
7253qla2x00_module_init(void)
7254{
fca29703
AV		 7255 int ret = 0;
7256
bc04459c
BVA		 7257 BUILD_BUG_ON(sizeof(cmd_entry_t) != 64);
7258 BUILD_BUG_ON(sizeof(cont_a64_entry_t) != 64);
7259 BUILD_BUG_ON(sizeof(cont_entry_t) != 64);
7260 BUILD_BUG_ON(sizeof(init_cb_t) != 96);
7261 BUILD_BUG_ON(sizeof(ms_iocb_entry_t) != 64);
7262 BUILD_BUG_ON(sizeof(request_t) != 64);
7263 BUILD_BUG_ON(sizeof(struct access_chip_84xx) != 64);
7264 BUILD_BUG_ON(sizeof(struct cmd_bidir) != 64);
7265 BUILD_BUG_ON(sizeof(struct cmd_nvme) != 64);
7266 BUILD_BUG_ON(sizeof(struct cmd_type_6) != 64);
7267 BUILD_BUG_ON(sizeof(struct cmd_type_7) != 64);
7268 BUILD_BUG_ON(sizeof(struct cmd_type_7_fx00) != 64);
7269 BUILD_BUG_ON(sizeof(struct cmd_type_crc_2) != 64);
7270 BUILD_BUG_ON(sizeof(struct ct_entry_24xx) != 64);
7271 BUILD_BUG_ON(sizeof(struct ctio_crc2_to_fw) != 64);
7272 BUILD_BUG_ON(sizeof(struct els_entry_24xx) != 64);
7273 BUILD_BUG_ON(sizeof(struct fxdisc_entry_fx00) != 64);
7274 BUILD_BUG_ON(sizeof(struct init_cb_24xx) != 128);
7275 BUILD_BUG_ON(sizeof(struct init_cb_81xx) != 128);
7276 BUILD_BUG_ON(sizeof(struct pt_ls4_request) != 64);
7277 BUILD_BUG_ON(sizeof(struct sns_cmd_pkt) != 2064);
7278 BUILD_BUG_ON(sizeof(struct verify_chip_entry_84xx) != 64);
7279 BUILD_BUG_ON(sizeof(struct vf_evfp_entry_24xx) != 56);
7280
1da177e4 7281 /* Allocate cache for SRBs. */
354d6b21 7282 srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0,
20c2df83 7283 SLAB_HWCACHE_ALIGN, NULL);
1da177e4 7284 if (srb_cachep == NULL) {
7c3df132
SK		 7285 ql_log(ql_log_fatal, NULL, 0x0001,
7286 "Unable to allocate SRB cache...Failing load!.\n");
1da177e4
LT		 7287 return -ENOMEM;
7288 }
7289
2d70c103
NB		 7290 /* Initialize target kmem_cache and mem_pools */
7291 ret = qlt_init();
7292 if (ret < 0) {
c794d24e 7293 goto destroy_cache;
2d70c103
NB		 7294 } else if (ret > 0) {
7295 /*
7296 * If initiator mode is explictly disabled by qlt_init(),
7297 * prevent scsi_transport_fc.c:fc_scsi_scan_rport() from
7298 * performing scsi_scan_target() during LOOP UP event.
7299 */
7300 qla2xxx_transport_functions.disable_target_scan = 1;
7301 qla2xxx_transport_vport_functions.disable_target_scan = 1;
7302 }
7303
1da177e4
LT		 7304 /* Derive version string. */
7305 strcpy(qla2x00_version_str, QLA2XXX_VERSION);
11010fec 7306 if (ql2xextended_error_logging)
0181944f 7307 strcat(qla2x00_version_str, "-debug");
fed0f68a
JC		 7308 if (ql2xextended_error_logging == 1)
7309 ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK;
0181944f 7310
0645cb83
QT		 7311 if (ql2x_ini_mode == QLA2XXX_INI_MODE_DUAL)
7312 qla_insert_tgt_attrs();
7313
1c97a12a
AV		 7314 qla2xxx_transport_template =
7315 fc_attach_transport(&qla2xxx_transport_functions);
2c3dfe3f 7316 if (!qla2xxx_transport_template) {
7c3df132
SK		 7317 ql_log(ql_log_fatal, NULL, 0x0002,
7318 "fc_attach_transport failed...Failing load!.\n");
c794d24e
BVA		 7319 ret = -ENODEV;
7320 goto qlt_exit;
2c3dfe3f 7321 }
6a03b4cd
HZ		 7322
7323 apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops);
7324 if (apidev_major < 0) {
7c3df132
SK		 7325 ql_log(ql_log_fatal, NULL, 0x0003,
7326 "Unable to register char device %s.\n", QLA2XXX_APIDEV);
6a03b4cd
HZ		 7327 }
7328
2c3dfe3f
SJ		 7329 qla2xxx_transport_vport_template =
7330 fc_attach_transport(&qla2xxx_transport_vport_functions);
7331 if (!qla2xxx_transport_vport_template) {
7c3df132
SK		 7332 ql_log(ql_log_fatal, NULL, 0x0004,
7333 "fc_attach_transport vport failed...Failing load!.\n");
c794d24e
BVA		 7334 ret = -ENODEV;
7335 goto unreg_chrdev;
2c3dfe3f 7336 }
7c3df132
SK		 7337 ql_log(ql_log_info, NULL, 0x0005,
7338 "QLogic Fibre Channel HBA Driver: %s.\n",
fd9a29f0 7339 qla2x00_version_str);
7ee61397 7340 ret = pci_register_driver(&qla2xxx_pci_driver);
fca29703 7341 if (ret) {
7c3df132
SK		 7342 ql_log(ql_log_fatal, NULL, 0x0006,
7343 "pci_register_driver failed...ret=%d Failing load!.\n",
7344 ret);
c794d24e 7345 goto release_vport_transport;
fca29703
AV		 7346 }
7347 return ret;
c794d24e
BVA		 7348
7349release_vport_transport:
7350 fc_release_transport(qla2xxx_transport_vport_template);
7351
7352unreg_chrdev:
7353 if (apidev_major >= 0)
7354 unregister_chrdev(apidev_major, QLA2XXX_APIDEV);
7355 fc_release_transport(qla2xxx_transport_template);
7356
7357qlt_exit:
7358 qlt_exit();
7359
7360destroy_cache:
7361 kmem_cache_destroy(srb_cachep);
7362 return ret;
1da177e4
LT		 7363}
7364
7365/**
7366 * qla2x00_module_exit - Module cleanup.
7367 **/
7368static void __exit
7369qla2x00_module_exit(void)
7370{
7ee61397 7371 pci_unregister_driver(&qla2xxx_pci_driver);
5433383e 7372 qla2x00_release_firmware();
75c1d48a 7373 kmem_cache_destroy(ctx_cachep);
2c3dfe3f 7374 fc_release_transport(qla2xxx_transport_vport_template);
59c209a6
BVA		 7375 if (apidev_major >= 0)
7376 unregister_chrdev(apidev_major, QLA2XXX_APIDEV);
7377 fc_release_transport(qla2xxx_transport_template);
7378 qlt_exit();
7379 kmem_cache_destroy(srb_cachep);
1da177e4
LT		 7380}
7381
7382module_init(qla2x00_module_init);
7383module_exit(qla2x00_module_exit);
7384
7385MODULE_AUTHOR("QLogic Corporation");
7386MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver");
7387MODULE_LICENSE("GPL");
7388MODULE_VERSION(QLA2XXX_VERSION);
bb8ee499
AV		 7389MODULE_FIRMWARE(FW_FILE_ISP21XX);
7390MODULE_FIRMWARE(FW_FILE_ISP22XX);
7391MODULE_FIRMWARE(FW_FILE_ISP2300);
7392MODULE_FIRMWARE(FW_FILE_ISP2322);
7393MODULE_FIRMWARE(FW_FILE_ISP24XX);
61623fc3 7394MODULE_FIRMWARE(FW_FILE_ISP25XX);
Linux 6.x block layer and io_uring tree(s)