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scsi: qla2xxx: Flush mailbox commands on chip reset
[linux-2.6-block.git] / drivers / scsi / qla2xxx / qla_os.c
CommitLineData
1da177e4 1/*
fa90c54f 2 * QLogic Fibre Channel HBA Driver
bd21eaf9 3 * Copyright (c) 2003-2014 QLogic Corporation
1da177e4 4 *
fa90c54f 5 * See LICENSE.qla2xxx for copyright and licensing details.
1da177e4
LT		 6 */
7#include "qla_def.h"
8
9#include <linux/moduleparam.h>
10#include <linux/vmalloc.h>
1da177e4 11#include <linux/delay.h>
39a11240 12#include <linux/kthread.h>
e1e82b6f 13#include <linux/mutex.h>
3420d36c 14#include <linux/kobject.h>
5a0e3ad6 15#include <linux/slab.h>
5601236b 16#include <linux/blk-mq-pci.h>
1da177e4
LT		 17#include <scsi/scsi_tcq.h>
18#include <scsi/scsicam.h>
19#include <scsi/scsi_transport.h>
20#include <scsi/scsi_transport_fc.h>
21
2d70c103
NB		 22#include "qla_target.h"
23
1da177e4
LT		 24/*
25 * Driver version
26 */
27char qla2x00_version_str[40];
28
6a03b4cd
HZ		 29static int apidev_major;
30
1da177e4
LT		 31/*
32 * SRB allocation cache
33 */
d7459527 34struct kmem_cache *srb_cachep;
1da177e4 35
a9083016
GM		 36/*
37 * CT6 CTX allocation cache
38 */
39static struct kmem_cache *ctx_cachep;
3ce8866c
SK		 40/*
41 * error level for logging
42 */
43int ql_errlev = ql_log_all;
a9083016 44
fa492630 45static int ql2xenableclass2;
2d70c103
NB		 46module_param(ql2xenableclass2, int, S_IRUGO|S_IRUSR);
47MODULE_PARM_DESC(ql2xenableclass2,
48 "Specify if Class 2 operations are supported from the very "
49 "beginning. Default is 0 - class 2 not supported.");
50
8ae6d9c7 51
1da177e4 52int ql2xlogintimeout = 20;
f2019cb1 53module_param(ql2xlogintimeout, int, S_IRUGO);
1da177e4
LT		 54MODULE_PARM_DESC(ql2xlogintimeout,
55 "Login timeout value in seconds.");
56
a7b61842 57int qlport_down_retry;
f2019cb1 58module_param(qlport_down_retry, int, S_IRUGO);
1da177e4 59MODULE_PARM_DESC(qlport_down_retry,
900d9f98 60 "Maximum number of command retries to a port that returns "
1da177e4
LT		 61 "a PORT-DOWN status.");
62
1da177e4
LT		 63int ql2xplogiabsentdevice;
64module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR);
65MODULE_PARM_DESC(ql2xplogiabsentdevice,
66 "Option to enable PLOGI to devices that are not present after "
900d9f98 67 "a Fabric scan. This is needed for several broken switches. "
1da177e4
LT		 68 "Default is 0 - no PLOGI. 1 - perfom PLOGI.");
69
1da177e4 70int ql2xloginretrycount = 0;
f2019cb1 71module_param(ql2xloginretrycount, int, S_IRUGO);
1da177e4
LT		 72MODULE_PARM_DESC(ql2xloginretrycount,
73 "Specify an alternate value for the NVRAM login retry count.");
74
a7a167bf 75int ql2xallocfwdump = 1;
f2019cb1 76module_param(ql2xallocfwdump, int, S_IRUGO);
a7a167bf
AV		 77MODULE_PARM_DESC(ql2xallocfwdump,
78 "Option to enable allocation of memory for a firmware dump "
79 "during HBA initialization. Memory allocation requirements "
80 "vary by ISP type. Default is 1 - allocate memory.");
81
11010fec 82int ql2xextended_error_logging;
27d94035 83module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
a2b3e01d 84module_param_named(logging, ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
11010fec 85MODULE_PARM_DESC(ql2xextended_error_logging,
3ce8866c
SK		 86 "Option to enable extended error logging,\n"
87 "\t\tDefault is 0 - no logging. 0x40000000 - Module Init & Probe.\n"
88 "\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n"
89 "\t\t0x08000000 - IO tracing. 0x04000000 - DPC Thread.\n"
90 "\t\t0x02000000 - Async events. 0x01000000 - Timer routines.\n"
91 "\t\t0x00800000 - User space. 0x00400000 - Task Management.\n"
92 "\t\t0x00200000 - AER/EEH. 0x00100000 - Multi Q.\n"
93 "\t\t0x00080000 - P3P Specific. 0x00040000 - Virtual Port.\n"
94 "\t\t0x00020000 - Buffer Dump. 0x00010000 - Misc.\n"
29f9f90c
CD		 95 "\t\t0x00008000 - Verbose. 0x00004000 - Target.\n"
96 "\t\t0x00002000 - Target Mgmt. 0x00001000 - Target TMF.\n"
3ce8866c 97 "\t\t0x7fffffff - For enabling all logs, can be too many logs.\n"
cfb0919c
CD		 98 "\t\t0x1e400000 - Preferred value for capturing essential "
99 "debug information (equivalent to old "
100 "ql2xextended_error_logging=1).\n"
3ce8866c 101 "\t\tDo LOGICAL OR of the value to enable more than one level");
0181944f 102
a9083016 103int ql2xshiftctondsd = 6;
f2019cb1 104module_param(ql2xshiftctondsd, int, S_IRUGO);
a9083016
GM		 105MODULE_PARM_DESC(ql2xshiftctondsd,
106 "Set to control shifting of command type processing "
107 "based on total number of SG elements.");
108
7e47e5ca 109int ql2xfdmienable=1;
de187df8 110module_param(ql2xfdmienable, int, S_IRUGO|S_IWUSR);
a2b3e01d 111module_param_named(fdmi, ql2xfdmienable, int, S_IRUGO|S_IWUSR);
cca5335c 112MODULE_PARM_DESC(ql2xfdmienable,
7794a5af
FW		 113 "Enables FDMI registrations. "
114 "0 - no FDMI. Default is 1 - perform FDMI.");
cca5335c 115
d213a4b7 116#define MAX_Q_DEPTH 64
50280c01 117static int ql2xmaxqdepth = MAX_Q_DEPTH;
df7baa50
AV		 118module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR);
119MODULE_PARM_DESC(ql2xmaxqdepth,
e92e4a8f 120 "Maximum queue depth to set for each LUN. "
d213a4b7 121 "Default is 64.");
df7baa50 122
e84067d7
DG		 123#if (IS_ENABLED(CONFIG_NVME_FC))
124int ql2xenabledif;
125#else
9e522cd8 126int ql2xenabledif = 2;
e84067d7 127#endif
9e522cd8 128module_param(ql2xenabledif, int, S_IRUGO);
bad75002 129MODULE_PARM_DESC(ql2xenabledif,
b97f5d0b
SM		 130 " Enable T10-CRC-DIF:\n"
131 " Default is 2.\n"
132 " 0 -- No DIF Support\n"
133 " 1 -- Enable DIF for all types\n"
134 " 2 -- Enable DIF for all types, except Type 0.\n");
bad75002 135
e84067d7
DG		 136#if (IS_ENABLED(CONFIG_NVME_FC))
137int ql2xnvmeenable = 1;
138#else
139int ql2xnvmeenable;
140#endif
141module_param(ql2xnvmeenable, int, 0644);
142MODULE_PARM_DESC(ql2xnvmeenable,
143 "Enables NVME support. "
144 "0 - no NVMe. Default is Y");
145
8cb2049c 146int ql2xenablehba_err_chk = 2;
bad75002
AE		 147module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR);
148MODULE_PARM_DESC(ql2xenablehba_err_chk,
8cb2049c 149 " Enable T10-CRC-DIF Error isolation by HBA:\n"
b97f5d0b 150 " Default is 2.\n"
8cb2049c
AE		 151 " 0 -- Error isolation disabled\n"
152 " 1 -- Error isolation enabled only for DIX Type 0\n"
153 " 2 -- Error isolation enabled for all Types\n");
bad75002 154
e5896bd5 155int ql2xiidmaenable=1;
f2019cb1 156module_param(ql2xiidmaenable, int, S_IRUGO);
e5896bd5
AV		 157MODULE_PARM_DESC(ql2xiidmaenable,
158 "Enables iIDMA settings "
159 "Default is 1 - perform iIDMA. 0 - no iIDMA.");
160
d7459527
MH		 161int ql2xmqsupport = 1;
162module_param(ql2xmqsupport, int, S_IRUGO);
163MODULE_PARM_DESC(ql2xmqsupport,
164 "Enable on demand multiple queue pairs support "
165 "Default is 1 for supported. "
166 "Set it to 0 to turn off mq qpair support.");
e337d907
AV		 167
168int ql2xfwloadbin;
86e45bf6 169module_param(ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
a2b3e01d 170module_param_named(fwload, ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
e337d907 171MODULE_PARM_DESC(ql2xfwloadbin,
7c3df132
SK		 172 "Option to specify location from which to load ISP firmware:.\n"
173 " 2 -- load firmware via the request_firmware() (hotplug).\n"
e337d907
AV		 174 " interface.\n"
175 " 1 -- load firmware from flash.\n"
176 " 0 -- use default semantics.\n");
177
ae97c91e 178int ql2xetsenable;
f2019cb1 179module_param(ql2xetsenable, int, S_IRUGO);
ae97c91e
AV		 180MODULE_PARM_DESC(ql2xetsenable,
181 "Enables firmware ETS burst."
182 "Default is 0 - skip ETS enablement.");
183
6907869d 184int ql2xdbwr = 1;
86e45bf6 185module_param(ql2xdbwr, int, S_IRUGO|S_IWUSR);
a9083016 186MODULE_PARM_DESC(ql2xdbwr,
08de2844
GM		 187 "Option to specify scheme for request queue posting.\n"
188 " 0 -- Regular doorbell.\n"
189 " 1 -- CAMRAM doorbell (faster).\n");
a9083016 190
f4c496c1 191int ql2xtargetreset = 1;
f2019cb1 192module_param(ql2xtargetreset, int, S_IRUGO);
f4c496c1
GM		 193MODULE_PARM_DESC(ql2xtargetreset,
194 "Enable target reset."
195 "Default is 1 - use hw defaults.");
196
4da26e16 197int ql2xgffidenable;
f2019cb1 198module_param(ql2xgffidenable, int, S_IRUGO);
4da26e16
CD		 199MODULE_PARM_DESC(ql2xgffidenable,
200 "Enables GFF_ID checks of port type. "
201 "Default is 0 - Do not use GFF_ID information.");
a9083016 202
043dc1d7 203int ql2xasynctmfenable = 1;
f2019cb1 204module_param(ql2xasynctmfenable, int, S_IRUGO);
3822263e
MI		 205MODULE_PARM_DESC(ql2xasynctmfenable,
206 "Enables issue of TM IOCBs asynchronously via IOCB mechanism"
207 "Default is 0 - Issue TM IOCBs via mailbox mechanism.");
ed0de87c
GM		 208
209int ql2xdontresethba;
86e45bf6 210module_param(ql2xdontresethba, int, S_IRUGO|S_IWUSR);
ed0de87c 211MODULE_PARM_DESC(ql2xdontresethba,
08de2844
GM		 212 "Option to specify reset behaviour.\n"
213 " 0 (Default) -- Reset on failure.\n"
214 " 1 -- Do not reset on failure.\n");
ed0de87c 215
1abf635d
HR		 216uint64_t ql2xmaxlun = MAX_LUNS;
217module_param(ql2xmaxlun, ullong, S_IRUGO);
82515920
AV		 218MODULE_PARM_DESC(ql2xmaxlun,
219 "Defines the maximum LU number to register with the SCSI "
220 "midlayer. Default is 65535.");
221
08de2844
GM		 222int ql2xmdcapmask = 0x1F;
223module_param(ql2xmdcapmask, int, S_IRUGO);
224MODULE_PARM_DESC(ql2xmdcapmask,
225 "Set the Minidump driver capture mask level. "
6e96fa7b 226 "Default is 0x1F - Can be set to 0x3, 0x7, 0xF, 0x1F, 0x7F.");
08de2844 227
3aadff35 228int ql2xmdenable = 1;
08de2844
GM		 229module_param(ql2xmdenable, int, S_IRUGO);
230MODULE_PARM_DESC(ql2xmdenable,
231 "Enable/disable MiniDump. "
3aadff35
GM		 232 "0 - MiniDump disabled. "
233 "1 (Default) - MiniDump enabled.");
08de2844 234
b0d6cabd
HM		 235int ql2xexlogins = 0;
236module_param(ql2xexlogins, uint, S_IRUGO|S_IWUSR);
237MODULE_PARM_DESC(ql2xexlogins,
238 "Number of extended Logins. "
239 "0 (Default)- Disabled.");
240
99e1b683
QT		 241int ql2xexchoffld = 1024;
242module_param(ql2xexchoffld, uint, 0644);
2f56a7f1 243MODULE_PARM_DESC(ql2xexchoffld,
99e1b683
QT		 244 "Number of target exchanges.");
245
246int ql2xiniexchg = 1024;
247module_param(ql2xiniexchg, uint, 0644);
248MODULE_PARM_DESC(ql2xiniexchg,
249 "Number of initiator exchanges.");
2f56a7f1 250
f198cafa
HM		 251int ql2xfwholdabts = 0;
252module_param(ql2xfwholdabts, int, S_IRUGO);
253MODULE_PARM_DESC(ql2xfwholdabts,
254 "Allow FW to hold status IOCB until ABTS rsp received. "
255 "0 (Default) Do not set fw option. "
256 "1 - Set fw option to hold ABTS.");
257
41dc529a
QT		 258int ql2xmvasynctoatio = 1;
259module_param(ql2xmvasynctoatio, int, S_IRUGO|S_IWUSR);
260MODULE_PARM_DESC(ql2xmvasynctoatio,
261 "Move PUREX, ABTS RX and RIDA IOCBs to ATIOQ"
262 "0 (Default). Do not move IOCBs"
263 "1 - Move IOCBs.");
264
e4e3a2ce
QT		 265int ql2xautodetectsfp = 1;
266module_param(ql2xautodetectsfp, int, 0444);
267MODULE_PARM_DESC(ql2xautodetectsfp,
268 "Detect SFP range and set appropriate distance.\n"
269 "1 (Default): Enable\n");
270
e7240af5
HM		 271int ql2xenablemsix = 1;
272module_param(ql2xenablemsix, int, 0444);
273MODULE_PARM_DESC(ql2xenablemsix,
274 "Set to enable MSI or MSI-X interrupt mechanism.\n"
275 " Default is 1, enable MSI-X interrupt mechanism.\n"
276 " 0 -- enable traditional pin-based mechanism.\n"
277 " 1 -- enable MSI-X interrupt mechanism.\n"
278 " 2 -- enable MSI interrupt mechanism.\n");
279
9ecf0b0d
QT		 280int qla2xuseresexchforels;
281module_param(qla2xuseresexchforels, int, 0444);
282MODULE_PARM_DESC(qla2xuseresexchforels,
283 "Reserve 1/2 of emergency exchanges for ELS.\n"
284 " 0 (default): disabled");
285
1da177e4 286/*
fa2a1ce5 287 * SCSI host template entry points
1da177e4
LT		 288 */
289static int qla2xxx_slave_configure(struct scsi_device * device);
f4f051eb 290static int qla2xxx_slave_alloc(struct scsi_device *);
1e99e33a
AV		 291static int qla2xxx_scan_finished(struct Scsi_Host *, unsigned long time);
292static void qla2xxx_scan_start(struct Scsi_Host *);
f4f051eb 293static void qla2xxx_slave_destroy(struct scsi_device *);
f281233d 294static int qla2xxx_queuecommand(struct Scsi_Host *h, struct scsi_cmnd *cmd);
1da177e4
LT		 295static int qla2xxx_eh_abort(struct scsi_cmnd *);
296static int qla2xxx_eh_device_reset(struct scsi_cmnd *);
523ec773 297static int qla2xxx_eh_target_reset(struct scsi_cmnd *);
1da177e4
LT		 298static int qla2xxx_eh_bus_reset(struct scsi_cmnd *);
299static int qla2xxx_eh_host_reset(struct scsi_cmnd *);
1da177e4 300
1a2fbf18 301static void qla2x00_clear_drv_active(struct qla_hw_data *);
3491255e 302static void qla2x00_free_device(scsi_qla_host_t *);
5601236b 303static int qla2xxx_map_queues(struct Scsi_Host *shost);
e84067d7 304static void qla2x00_destroy_deferred_work(struct qla_hw_data *);
ce7e4af7 305
a5326f86 306struct scsi_host_template qla2xxx_driver_template = {
1da177e4 307 .module = THIS_MODULE,
cb63067a 308 .name = QLA2XXX_DRIVER_NAME,
a5326f86 309 .queuecommand = qla2xxx_queuecommand,
fca29703 310
b6a05c82 311 .eh_timed_out = fc_eh_timed_out,
fca29703
AV		 312 .eh_abort_handler = qla2xxx_eh_abort,
313 .eh_device_reset_handler = qla2xxx_eh_device_reset,
523ec773 314 .eh_target_reset_handler = qla2xxx_eh_target_reset,
fca29703
AV		 315 .eh_bus_reset_handler = qla2xxx_eh_bus_reset,
316 .eh_host_reset_handler = qla2xxx_eh_host_reset,
317
318 .slave_configure = qla2xxx_slave_configure,
319
320 .slave_alloc = qla2xxx_slave_alloc,
321 .slave_destroy = qla2xxx_slave_destroy,
ed677086
AV		 322 .scan_finished = qla2xxx_scan_finished,
323 .scan_start = qla2xxx_scan_start,
db5ed4df 324 .change_queue_depth = scsi_change_queue_depth,
5601236b 325 .map_queues = qla2xxx_map_queues,
fca29703
AV		 326 .this_id = -1,
327 .cmd_per_lun = 3,
328 .use_clustering = ENABLE_CLUSTERING,
329 .sg_tablesize = SG_ALL,
330
331 .max_sectors = 0xFFFF,
afb046e2 332 .shost_attrs = qla2x00_host_attrs,
2d70c103
NB		 333
334 .supported_mode = MODE_INITIATOR,
c40ecc12 335 .track_queue_depth = 1,
fca29703
AV		 336};
337
1da177e4 338static struct scsi_transport_template *qla2xxx_transport_template = NULL;
2c3dfe3f 339struct scsi_transport_template *qla2xxx_transport_vport_template = NULL;
1da177e4 340
1da177e4
LT		 341/* TODO Convert to inlines
342 *
343 * Timer routines
344 */
1da177e4 345
2c3dfe3f 346__inline__ void
8e5f4ba0 347qla2x00_start_timer(scsi_qla_host_t *vha, unsigned long interval)
1da177e4 348{
8e5f4ba0 349 timer_setup(&vha->timer, qla2x00_timer, 0);
e315cd28 350 vha->timer.expires = jiffies + interval * HZ;
e315cd28
AC		 351 add_timer(&vha->timer);
352 vha->timer_active = 1;
1da177e4
LT		 353}
354
355static inline void
e315cd28 356qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval)
1da177e4 357{
a9083016 358 /* Currently used for 82XX only. */
7c3df132
SK		 359 if (vha->device_flags & DFLG_DEV_FAILED) {
360 ql_dbg(ql_dbg_timer, vha, 0x600d,
361 "Device in a failed state, returning.\n");
a9083016 362 return;
7c3df132 363 }
a9083016 364
e315cd28 365 mod_timer(&vha->timer, jiffies + interval * HZ);
1da177e4
LT		 366}
367
a824ebb3 368static __inline__ void
e315cd28 369qla2x00_stop_timer(scsi_qla_host_t *vha)
1da177e4 370{
e315cd28
AC		 371 del_timer_sync(&vha->timer);
372 vha->timer_active = 0;
1da177e4
LT		 373}
374
1da177e4
LT		 375static int qla2x00_do_dpc(void *data);
376
377static void qla2x00_rst_aen(scsi_qla_host_t *);
378
73208dfd
AC		 379static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t,
380 struct req_que **, struct rsp_que **);
e30d1756 381static void qla2x00_free_fw_dump(struct qla_hw_data *);
e315cd28 382static void qla2x00_mem_free(struct qla_hw_data *);
d7459527
MH		 383int qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd,
384 struct qla_qpair *qpair);
1da177e4 385
1da177e4 386/* -------------------------------------------------------------------------- */
8abfa9e2
QT		 387static void qla_init_base_qpair(struct scsi_qla_host *vha, struct req_que *req,
388 struct rsp_que *rsp)
389{
390 struct qla_hw_data *ha = vha->hw;
391 rsp->qpair = ha->base_qpair;
392 rsp->req = req;
393 ha->base_qpair->req = req;
394 ha->base_qpair->rsp = rsp;
395 ha->base_qpair->vha = vha;
396 ha->base_qpair->qp_lock_ptr = &ha->hardware_lock;
397 ha->base_qpair->use_shadow_reg = IS_SHADOW_REG_CAPABLE(ha) ? 1 : 0;
398 ha->base_qpair->msix = &ha->msix_entries[QLA_MSIX_RSP_Q];
399 INIT_LIST_HEAD(&ha->base_qpair->hints_list);
400 ha->base_qpair->enable_class_2 = ql2xenableclass2;
401 /* init qpair to this cpu. Will adjust at run time. */
86531887 402 qla_cpu_update(rsp->qpair, raw_smp_processor_id());
8abfa9e2
QT		 403 ha->base_qpair->pdev = ha->pdev;
404
405 if (IS_QLA27XX(ha) || IS_QLA83XX(ha))
406 ha->base_qpair->reqq_start_iocbs = qla_83xx_start_iocbs;
407}
408
9a347ff4
CD		 409static int qla2x00_alloc_queues(struct qla_hw_data *ha, struct req_que *req,
410 struct rsp_que *rsp)
73208dfd 411{
7c3df132 412 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
6396bb22 413 ha->req_q_map = kcalloc(ha->max_req_queues, sizeof(struct req_que *),
73208dfd
AC		 414 GFP_KERNEL);
415 if (!ha->req_q_map) {
7c3df132
SK		 416 ql_log(ql_log_fatal, vha, 0x003b,
417 "Unable to allocate memory for request queue ptrs.\n");
73208dfd
AC		 418 goto fail_req_map;
419 }
420
6396bb22 421 ha->rsp_q_map = kcalloc(ha->max_rsp_queues, sizeof(struct rsp_que *),
73208dfd
AC		 422 GFP_KERNEL);
423 if (!ha->rsp_q_map) {
7c3df132
SK		 424 ql_log(ql_log_fatal, vha, 0x003c,
425 "Unable to allocate memory for response queue ptrs.\n");
73208dfd
AC		 426 goto fail_rsp_map;
427 }
d7459527 428
e326d22a
QT		 429 ha->base_qpair = kzalloc(sizeof(struct qla_qpair), GFP_KERNEL);
430 if (ha->base_qpair == NULL) {
431 ql_log(ql_log_warn, vha, 0x00e0,
432 "Failed to allocate base queue pair memory.\n");
433 goto fail_base_qpair;
434 }
435
8abfa9e2 436 qla_init_base_qpair(vha, req, rsp);
e326d22a 437
c38d1baf 438 if ((ql2xmqsupport || ql2xnvmeenable) && ha->max_qpairs) {
d7459527
MH		 439 ha->queue_pair_map = kcalloc(ha->max_qpairs, sizeof(struct qla_qpair *),
440 GFP_KERNEL);
441 if (!ha->queue_pair_map) {
442 ql_log(ql_log_fatal, vha, 0x0180,
443 "Unable to allocate memory for queue pair ptrs.\n");
444 goto fail_qpair_map;
445 }
d7459527
MH		 446 }
447
9a347ff4
CD		 448 /*
449 * Make sure we record at least the request and response queue zero in
450 * case we need to free them if part of the probe fails.
451 */
452 ha->rsp_q_map[0] = rsp;
453 ha->req_q_map[0] = req;
73208dfd
AC		 454 set_bit(0, ha->rsp_qid_map);
455 set_bit(0, ha->req_qid_map);
6a2cf8d3 456 return 0;
73208dfd 457
d7459527 458fail_qpair_map:
82de802a
QT		 459 kfree(ha->base_qpair);
460 ha->base_qpair = NULL;
461fail_base_qpair:
d7459527
MH		 462 kfree(ha->rsp_q_map);
463 ha->rsp_q_map = NULL;
73208dfd
AC		 464fail_rsp_map:
465 kfree(ha->req_q_map);
466 ha->req_q_map = NULL;
467fail_req_map:
468 return -ENOMEM;
469}
470
2afa19a9 471static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req)
73208dfd 472{
8ae6d9c7
GM		 473 if (IS_QLAFX00(ha)) {
474 if (req && req->ring_fx00)
475 dma_free_coherent(&ha->pdev->dev,
476 (req->length_fx00 + 1) * sizeof(request_t),
477 req->ring_fx00, req->dma_fx00);
478 } else if (req && req->ring)
73208dfd
AC		 479 dma_free_coherent(&ha->pdev->dev,
480 (req->length + 1) * sizeof(request_t),
481 req->ring, req->dma);
482
6d634067 483 if (req)
8d93f550 484 kfree(req->outstanding_cmds);
6d634067
BK		 485
486 kfree(req);
73208dfd
AC		 487}
488
2afa19a9
AC		 489static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp)
490{
8ae6d9c7 491 if (IS_QLAFX00(ha)) {
3f6c9be2 492 if (rsp && rsp->ring_fx00)
8ae6d9c7
GM		 493 dma_free_coherent(&ha->pdev->dev,
494 (rsp->length_fx00 + 1) * sizeof(request_t),
495 rsp->ring_fx00, rsp->dma_fx00);
496 } else if (rsp && rsp->ring) {
2afa19a9
AC		 497 dma_free_coherent(&ha->pdev->dev,
498 (rsp->length + 1) * sizeof(response_t),
499 rsp->ring, rsp->dma);
8ae6d9c7 500 }
6d634067 501 kfree(rsp);
2afa19a9
AC		 502}
503
73208dfd
AC		 504static void qla2x00_free_queues(struct qla_hw_data *ha)
505{
506 struct req_que *req;
507 struct rsp_que *rsp;
508 int cnt;
093df737 509 unsigned long flags;
73208dfd 510
82de802a
QT		 511 if (ha->queue_pair_map) {
512 kfree(ha->queue_pair_map);
513 ha->queue_pair_map = NULL;
514 }
515 if (ha->base_qpair) {
516 kfree(ha->base_qpair);
517 ha->base_qpair = NULL;
518 }
519
093df737 520 spin_lock_irqsave(&ha->hardware_lock, flags);
2afa19a9 521 for (cnt = 0; cnt < ha->max_req_queues; cnt++) {
cb43285f
QT		 522 if (!test_bit(cnt, ha->req_qid_map))
523 continue;
524
73208dfd 525 req = ha->req_q_map[cnt];
093df737
QT		 526 clear_bit(cnt, ha->req_qid_map);
527 ha->req_q_map[cnt] = NULL;
528
529 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2afa19a9 530 qla2x00_free_req_que(ha, req);
093df737 531 spin_lock_irqsave(&ha->hardware_lock, flags);
73208dfd 532 }
093df737
QT		 533 spin_unlock_irqrestore(&ha->hardware_lock, flags);
534
73208dfd
AC		 535 kfree(ha->req_q_map);
536 ha->req_q_map = NULL;
2afa19a9 537
093df737
QT		 538
539 spin_lock_irqsave(&ha->hardware_lock, flags);
2afa19a9 540 for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) {
cb43285f
QT		 541 if (!test_bit(cnt, ha->rsp_qid_map))
542 continue;
543
2afa19a9 544 rsp = ha->rsp_q_map[cnt];
c3c42394 545 clear_bit(cnt, ha->rsp_qid_map);
093df737
QT		 546 ha->rsp_q_map[cnt] = NULL;
547 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2afa19a9 548 qla2x00_free_rsp_que(ha, rsp);
093df737 549 spin_lock_irqsave(&ha->hardware_lock, flags);
2afa19a9 550 }
093df737
QT		 551 spin_unlock_irqrestore(&ha->hardware_lock, flags);
552
2afa19a9
AC		 553 kfree(ha->rsp_q_map);
554 ha->rsp_q_map = NULL;
73208dfd
AC		 555}
556
1da177e4 557static char *
e315cd28 558qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str)
1da177e4 559{
e315cd28 560 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 561 static char *pci_bus_modes[] = {
562 "33", "66", "100", "133",
563 };
564 uint16_t pci_bus;
565
566 strcpy(str, "PCI");
567 pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9;
568 if (pci_bus) {
569 strcat(str, "-X (");
570 strcat(str, pci_bus_modes[pci_bus]);
571 } else {
572 pci_bus = (ha->pci_attr & BIT_8) >> 8;
573 strcat(str, " (");
574 strcat(str, pci_bus_modes[pci_bus]);
575 }
576 strcat(str, " MHz)");
577
578 return (str);
579}
580
fca29703 581static char *
e315cd28 582qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str)
fca29703
AV		 583{
584 static char *pci_bus_modes[] = { "33", "66", "100", "133", };
e315cd28 585 struct qla_hw_data *ha = vha->hw;
fca29703 586 uint32_t pci_bus;
fca29703 587
62a276f8 588 if (pci_is_pcie(ha->pdev)) {
fca29703 589 char lwstr[6];
62a276f8 590 uint32_t lstat, lspeed, lwidth;
fca29703 591
62a276f8
BH		 592 pcie_capability_read_dword(ha->pdev, PCI_EXP_LNKCAP, &lstat);
593 lspeed = lstat & PCI_EXP_LNKCAP_SLS;
594 lwidth = (lstat & PCI_EXP_LNKCAP_MLW) >> 4;
fca29703
AV		 595
596 strcpy(str, "PCIe (");
49300af7
SK		 597 switch (lspeed) {
598 case 1:
c87a0d8c 599 strcat(str, "2.5GT/s ");
49300af7
SK		 600 break;
601 case 2:
c87a0d8c 602 strcat(str, "5.0GT/s ");
49300af7
SK		 603 break;
604 case 3:
605 strcat(str, "8.0GT/s ");
606 break;
607 default:
fca29703 608 strcat(str, "<unknown> ");
49300af7
SK		 609 break;
610 }
fca29703
AV		 611 snprintf(lwstr, sizeof(lwstr), "x%d)", lwidth);
612 strcat(str, lwstr);
613
614 return str;
615 }
616
617 strcpy(str, "PCI");
618 pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8;
619 if (pci_bus == 0 || pci_bus == 8) {
620 strcat(str, " (");
621 strcat(str, pci_bus_modes[pci_bus >> 3]);
622 } else {
623 strcat(str, "-X ");
624 if (pci_bus & BIT_2)
625 strcat(str, "Mode 2");
626 else
627 strcat(str, "Mode 1");
628 strcat(str, " (");
629 strcat(str, pci_bus_modes[pci_bus & ~BIT_2]);
630 }
631 strcat(str, " MHz)");
632
633 return str;
634}
635
e5f82ab8 636static char *
df57caba 637qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
1da177e4
LT		 638{
639 char un_str[10];
e315cd28 640 struct qla_hw_data *ha = vha->hw;
fa2a1ce5 641
df57caba
HM		 642 snprintf(str, size, "%d.%02d.%02d ", ha->fw_major_version,
643 ha->fw_minor_version, ha->fw_subminor_version);
1da177e4
LT		 644
645 if (ha->fw_attributes & BIT_9) {
646 strcat(str, "FLX");
647 return (str);
648 }
649
650 switch (ha->fw_attributes & 0xFF) {
651 case 0x7:
652 strcat(str, "EF");
653 break;
654 case 0x17:
655 strcat(str, "TP");
656 break;
657 case 0x37:
658 strcat(str, "IP");
659 break;
660 case 0x77:
661 strcat(str, "VI");
662 break;
663 default:
664 sprintf(un_str, "(%x)", ha->fw_attributes);
665 strcat(str, un_str);
666 break;
667 }
668 if (ha->fw_attributes & 0x100)
669 strcat(str, "X");
670
671 return (str);
672}
673
e5f82ab8 674static char *
df57caba 675qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
fca29703 676{
e315cd28 677 struct qla_hw_data *ha = vha->hw;
f0883ac6 678
df57caba 679 snprintf(str, size, "%d.%02d.%02d (%x)", ha->fw_major_version,
3a03eb79 680 ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes);
fca29703 681 return str;
fca29703
AV		 682}
683
9ba56b95 684void
25ff6af1 685qla2x00_sp_free_dma(void *ptr)
fca29703 686{
25ff6af1
JC		 687 srb_t *sp = ptr;
688 struct qla_hw_data *ha = sp->vha->hw;
9ba56b95 689 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
9ba56b95 690 void *ctx = GET_CMD_CTX_SP(sp);
fca29703 691
9ba56b95
GM		 692 if (sp->flags & SRB_DMA_VALID) {
693 scsi_dma_unmap(cmd);
694 sp->flags &= ~SRB_DMA_VALID;
7c3df132 695 }
fca29703 696
9ba56b95
GM		 697 if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
698 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
699 scsi_prot_sg_count(cmd), cmd->sc_data_direction);
700 sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
701 }
702
d5ff0eed
JC		 703 if (!ctx)
704 goto end;
705
9ba56b95
GM		 706 if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
707 /* List assured to be having elements */
d5ff0eed 708 qla2x00_clean_dsd_pool(ha, ctx);
9ba56b95
GM		 709 sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
710 }
711
712 if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
d5ff0eed
JC		 713 struct crc_context *ctx0 = ctx;
714
715 dma_pool_free(ha->dl_dma_pool, ctx0, ctx0->crc_ctx_dma);
9ba56b95
GM		 716 sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
717 }
718
719 if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
d5ff0eed 720 struct ct6_dsd *ctx1 = ctx;
fca29703 721
9ba56b95 722 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd,
d5ff0eed 723 ctx1->fcp_cmnd_dma);
9ba56b95
GM		 724 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list);
725 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt;
726 ha->gbl_dsd_avail += ctx1->dsd_use_cnt;
727 mempool_free(ctx1, ha->ctx_mempool);
9ba56b95
GM		 728 }
729
d5ff0eed 730end:
6fcd98fd 731 if (sp->type != SRB_NVME_CMD && sp->type != SRB_NVME_LS) {
7401bc18
DG		 732 CMD_SP(cmd) = NULL;
733 qla2x00_rel_sp(sp);
734 }
9ba56b95
GM		 735}
736
d7459527 737void
25ff6af1 738qla2x00_sp_compl(void *ptr, int res)
9ba56b95 739{
25ff6af1 740 srb_t *sp = ptr;
9ba56b95
GM		 741 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
742
743 cmd->result = res;
744
745 if (atomic_read(&sp->ref_count) == 0) {
25ff6af1 746 ql_dbg(ql_dbg_io, sp->vha, 0x3015,
9ba56b95
GM		 747 "SP reference-count to ZERO -- sp=%p cmd=%p.\n",
748 sp, GET_CMD_SP(sp));
749 if (ql2xextended_error_logging & ql_dbg_io)
8fbdac8c 750 WARN_ON(atomic_read(&sp->ref_count) == 0);
9ba56b95
GM		 751 return;
752 }
753 if (!atomic_dec_and_test(&sp->ref_count))
754 return;
755
f3caa990 756 sp->free(sp);
9ba56b95 757 cmd->scsi_done(cmd);
fca29703
AV		 758}
759
d7459527 760void
25ff6af1 761qla2xxx_qpair_sp_free_dma(void *ptr)
d7459527
MH		 762{
763 srb_t *sp = (srb_t *)ptr;
764 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
765 struct qla_hw_data *ha = sp->fcport->vha->hw;
766 void *ctx = GET_CMD_CTX_SP(sp);
767
768 if (sp->flags & SRB_DMA_VALID) {
769 scsi_dma_unmap(cmd);
770 sp->flags &= ~SRB_DMA_VALID;
771 }
772
773 if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
774 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
775 scsi_prot_sg_count(cmd), cmd->sc_data_direction);
776 sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
777 }
778
d5ff0eed
JC		 779 if (!ctx)
780 goto end;
781
d7459527
MH		 782 if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
783 /* List assured to be having elements */
d5ff0eed 784 qla2x00_clean_dsd_pool(ha, ctx);
d7459527
MH		 785 sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
786 }
787
788 if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
d5ff0eed
JC		 789 struct crc_context *ctx0 = ctx;
790
791 dma_pool_free(ha->dl_dma_pool, ctx, ctx0->crc_ctx_dma);
d7459527
MH		 792 sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
793 }
794
795 if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
d5ff0eed 796 struct ct6_dsd *ctx1 = ctx;
d7459527
MH		 797 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd,
798 ctx1->fcp_cmnd_dma);
799 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list);
800 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt;
801 ha->gbl_dsd_avail += ctx1->dsd_use_cnt;
802 mempool_free(ctx1, ha->ctx_mempool);
803 }
d5ff0eed 804end:
d7459527
MH		 805 CMD_SP(cmd) = NULL;
806 qla2xxx_rel_qpair_sp(sp->qpair, sp);
807}
808
809void
25ff6af1 810qla2xxx_qpair_sp_compl(void *ptr, int res)
d7459527 811{
25ff6af1 812 srb_t *sp = ptr;
d7459527
MH		 813 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
814
815 cmd->result = res;
816
817 if (atomic_read(&sp->ref_count) == 0) {
818 ql_dbg(ql_dbg_io, sp->fcport->vha, 0x3079,
819 "SP reference-count to ZERO -- sp=%p cmd=%p.\n",
820 sp, GET_CMD_SP(sp));
821 if (ql2xextended_error_logging & ql_dbg_io)
822 WARN_ON(atomic_read(&sp->ref_count) == 0);
823 return;
824 }
825 if (!atomic_dec_and_test(&sp->ref_count))
826 return;
827
f3caa990 828 sp->free(sp);
d7459527
MH		 829 cmd->scsi_done(cmd);
830}
831
8ae6d9c7
GM		 832/* If we are SP1 here, we need to still take and release the host_lock as SP1
833 * does not have the changes necessary to avoid taking host->host_lock.
834 */
1da177e4 835static int
f5e3e40b 836qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
fca29703 837{
134ae078 838 scsi_qla_host_t *vha = shost_priv(host);
fca29703 839 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
19a7b4ae 840 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
e315cd28
AC		 841 struct qla_hw_data *ha = vha->hw;
842 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
fca29703
AV		 843 srb_t *sp;
844 int rval;
5601236b
MH		 845 struct qla_qpair *qpair = NULL;
846 uint32_t tag;
847 uint16_t hwq;
fca29703 848
04dfaa53
MFO		 849 if (unlikely(test_bit(UNLOADING, &base_vha->dpc_flags))) {
850 cmd->result = DID_NO_CONNECT << 16;
851 goto qc24_fail_command;
852 }
853
5601236b
MH		 854 if (ha->mqenable) {
855 if (shost_use_blk_mq(vha->host)) {
856 tag = blk_mq_unique_tag(cmd->request);
857 hwq = blk_mq_unique_tag_to_hwq(tag);
858 qpair = ha->queue_pair_map[hwq];
859 } else if (vha->vp_idx && vha->qpair) {
860 qpair = vha->qpair;
861 }
862
863 if (qpair)
864 return qla2xxx_mqueuecommand(host, cmd, qpair);
d7459527
MH		 865 }
866
85880801 867 if (ha->flags.eeh_busy) {
7c3df132 868 if (ha->flags.pci_channel_io_perm_failure) {
5f28d2d7 869 ql_dbg(ql_dbg_aer, vha, 0x9010,
7c3df132
SK		 870 "PCI Channel IO permanent failure, exiting "
871 "cmd=%p.\n", cmd);
b9b12f73 872 cmd->result = DID_NO_CONNECT << 16;
7c3df132 873 } else {
5f28d2d7 874 ql_dbg(ql_dbg_aer, vha, 0x9011,
7c3df132 875 "EEH_Busy, Requeuing the cmd=%p.\n", cmd);
85880801 876 cmd->result = DID_REQUEUE << 16;
7c3df132 877 }
14e660e6
SJ		 878 goto qc24_fail_command;
879 }
880
19a7b4ae
JSEC		 881 rval = fc_remote_port_chkready(rport);
882 if (rval) {
883 cmd->result = rval;
5f28d2d7 884 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3003,
7c3df132
SK		 885 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
886 cmd, rval);
fca29703
AV		 887 goto qc24_fail_command;
888 }
889
bad75002
AE		 890 if (!vha->flags.difdix_supported &&
891 scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) {
7c3df132
SK		 892 ql_dbg(ql_dbg_io, vha, 0x3004,
893 "DIF Cap not reg, fail DIF capable cmd's:%p.\n",
894 cmd);
bad75002
AE		 895 cmd->result = DID_NO_CONNECT << 16;
896 goto qc24_fail_command;
897 }
aa651be8
CD		 898
899 if (!fcport) {
900 cmd->result = DID_NO_CONNECT << 16;
901 goto qc24_fail_command;
902 }
903
fca29703
AV		 904 if (atomic_read(&fcport->state) != FCS_ONLINE) {
905 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
38170fa8 906 atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
7c3df132
SK		 907 ql_dbg(ql_dbg_io, vha, 0x3005,
908 "Returning DNC, fcport_state=%d loop_state=%d.\n",
909 atomic_read(&fcport->state),
910 atomic_read(&base_vha->loop_state));
fca29703
AV		 911 cmd->result = DID_NO_CONNECT << 16;
912 goto qc24_fail_command;
913 }
7b594131 914 goto qc24_target_busy;
fca29703
AV		 915 }
916
e05fe292
CD		 917 /*
918 * Return target busy if we've received a non-zero retry_delay_timer
919 * in a FCP_RSP.
920 */
975f7d46
BP		 921 if (fcport->retry_delay_timestamp == 0) {
922 /* retry delay not set */
923 } else if (time_after(jiffies, fcport->retry_delay_timestamp))
e05fe292
CD		 924 fcport->retry_delay_timestamp = 0;
925 else
926 goto qc24_target_busy;
927
b00ee7d7 928 sp = qla2x00_get_sp(vha, fcport, GFP_ATOMIC);
50280c01 929 if (!sp)
f5e3e40b 930 goto qc24_host_busy;
fca29703 931
9ba56b95
GM		 932 sp->u.scmd.cmd = cmd;
933 sp->type = SRB_SCSI_CMD;
934 atomic_set(&sp->ref_count, 1);
935 CMD_SP(cmd) = (void *)sp;
936 sp->free = qla2x00_sp_free_dma;
937 sp->done = qla2x00_sp_compl;
938
e315cd28 939 rval = ha->isp_ops->start_scsi(sp);
7c3df132 940 if (rval != QLA_SUCCESS) {
53016ed3 941 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3013,
7c3df132 942 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
fca29703 943 goto qc24_host_busy_free_sp;
7c3df132 944 }
fca29703 945
fca29703
AV		 946 return 0;
947
948qc24_host_busy_free_sp:
f3caa990 949 sp->free(sp);
fca29703 950
f5e3e40b 951qc24_host_busy:
fca29703
AV		 952 return SCSI_MLQUEUE_HOST_BUSY;
953
7b594131
MC		 954qc24_target_busy:
955 return SCSI_MLQUEUE_TARGET_BUSY;
956
fca29703 957qc24_fail_command:
f5e3e40b 958 cmd->scsi_done(cmd);
fca29703
AV		 959
960 return 0;
961}
962
d7459527
MH		 963/* For MQ supported I/O */
964int
965qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd,
966 struct qla_qpair *qpair)
967{
968 scsi_qla_host_t *vha = shost_priv(host);
969 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
970 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
971 struct qla_hw_data *ha = vha->hw;
972 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
973 srb_t *sp;
974 int rval;
975
976 rval = fc_remote_port_chkready(rport);
977 if (rval) {
978 cmd->result = rval;
979 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3076,
980 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
981 cmd, rval);
982 goto qc24_fail_command;
983 }
984
985 if (!fcport) {
986 cmd->result = DID_NO_CONNECT << 16;
987 goto qc24_fail_command;
988 }
989
990 if (atomic_read(&fcport->state) != FCS_ONLINE) {
991 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
992 atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
993 ql_dbg(ql_dbg_io, vha, 0x3077,
994 "Returning DNC, fcport_state=%d loop_state=%d.\n",
995 atomic_read(&fcport->state),
996 atomic_read(&base_vha->loop_state));
997 cmd->result = DID_NO_CONNECT << 16;
998 goto qc24_fail_command;
999 }
1000 goto qc24_target_busy;
1001 }
1002
1003 /*
1004 * Return target busy if we've received a non-zero retry_delay_timer
1005 * in a FCP_RSP.
1006 */
1007 if (fcport->retry_delay_timestamp == 0) {
1008 /* retry delay not set */
1009 } else if (time_after(jiffies, fcport->retry_delay_timestamp))
1010 fcport->retry_delay_timestamp = 0;
1011 else
1012 goto qc24_target_busy;
1013
1014 sp = qla2xxx_get_qpair_sp(qpair, fcport, GFP_ATOMIC);
1015 if (!sp)
1016 goto qc24_host_busy;
1017
1018 sp->u.scmd.cmd = cmd;
1019 sp->type = SRB_SCSI_CMD;
1020 atomic_set(&sp->ref_count, 1);
1021 CMD_SP(cmd) = (void *)sp;
1022 sp->free = qla2xxx_qpair_sp_free_dma;
1023 sp->done = qla2xxx_qpair_sp_compl;
1024 sp->qpair = qpair;
1025
1026 rval = ha->isp_ops->start_scsi_mq(sp);
1027 if (rval != QLA_SUCCESS) {
1028 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3078,
1029 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
1030 if (rval == QLA_INTERFACE_ERROR)
1031 goto qc24_fail_command;
1032 goto qc24_host_busy_free_sp;
1033 }
1034
1035 return 0;
1036
1037qc24_host_busy_free_sp:
f3caa990 1038 sp->free(sp);
d7459527
MH		 1039
1040qc24_host_busy:
1041 return SCSI_MLQUEUE_HOST_BUSY;
1042
1043qc24_target_busy:
1044 return SCSI_MLQUEUE_TARGET_BUSY;
1045
1046qc24_fail_command:
1047 cmd->scsi_done(cmd);
1048
1049 return 0;
1050}
1051
1da177e4
LT		 1052/*
1053 * qla2x00_eh_wait_on_command
1054 * Waits for the command to be returned by the Firmware for some
1055 * max time.
1056 *
1057 * Input:
1da177e4 1058 * cmd = Scsi Command to wait on.
1da177e4
LT		 1059 *
1060 * Return:
1061 * Not Found : 0
1062 * Found : 1
1063 */
1064static int
e315cd28 1065qla2x00_eh_wait_on_command(struct scsi_cmnd *cmd)
1da177e4 1066{
fe74c71f 1067#define ABORT_POLLING_PERIOD 1000
478c3b03 1068#define ABORT_WAIT_ITER ((2 * 1000) / (ABORT_POLLING_PERIOD))
f4f051eb 1069 unsigned long wait_iter = ABORT_WAIT_ITER;
85880801
AV		 1070 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1071 struct qla_hw_data *ha = vha->hw;
f4f051eb 1072 int ret = QLA_SUCCESS;
1da177e4 1073
85880801 1074 if (unlikely(pci_channel_offline(ha->pdev)) || ha->flags.eeh_busy) {
7c3df132
SK		 1075 ql_dbg(ql_dbg_taskm, vha, 0x8005,
1076 "Return:eh_wait.\n");
85880801
AV		 1077 return ret;
1078 }
1079
d970432c 1080 while (CMD_SP(cmd) && wait_iter--) {
fe74c71f 1081 msleep(ABORT_POLLING_PERIOD);
f4f051eb 1082 }
1083 if (CMD_SP(cmd))
1084 ret = QLA_FUNCTION_FAILED;
1da177e4 1085
f4f051eb 1086 return ret;
1da177e4
LT		 1087}
1088
1089/*
1090 * qla2x00_wait_for_hba_online
fa2a1ce5 1091 * Wait till the HBA is online after going through
1da177e4
LT		 1092 * <= MAX_RETRIES_OF_ISP_ABORT or
1093 * finally HBA is disabled ie marked offline
1094 *
1095 * Input:
1096 * ha - pointer to host adapter structure
fa2a1ce5
AV		 1097 *
1098 * Note:
1da177e4
LT		 1099 * Does context switching-Release SPIN_LOCK
1100 * (if any) before calling this routine.
1101 *
1102 * Return:
1103 * Success (Adapter is online) : 0
1104 * Failed (Adapter is offline/disabled) : 1
1105 */
854165f4 1106int
e315cd28 1107qla2x00_wait_for_hba_online(scsi_qla_host_t *vha)
1da177e4 1108{
fca29703
AV		 1109 int return_status;
1110 unsigned long wait_online;
e315cd28
AC		 1111 struct qla_hw_data *ha = vha->hw;
1112 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4 1113
fa2a1ce5 1114 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ);
e315cd28
AC		 1115 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
1116 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
1117 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
1118 ha->dpc_active) && time_before(jiffies, wait_online)) {
1da177e4
LT		 1119
1120 msleep(1000);
1121 }
e315cd28 1122 if (base_vha->flags.online)
fa2a1ce5 1123 return_status = QLA_SUCCESS;
1da177e4
LT		 1124 else
1125 return_status = QLA_FUNCTION_FAILED;
1126
1da177e4
LT		 1127 return (return_status);
1128}
1129
726b8548
QT		 1130static inline int test_fcport_count(scsi_qla_host_t *vha)
1131{
1132 struct qla_hw_data *ha = vha->hw;
1133 unsigned long flags;
1134 int res;
1135
1136 spin_lock_irqsave(&ha->tgt.sess_lock, flags);
83548fe2
QT		 1137 ql_dbg(ql_dbg_init, vha, 0x00ec,
1138 "tgt %p, fcport_count=%d\n",
1139 vha, vha->fcport_count);
726b8548
QT		 1140 res = (vha->fcport_count == 0);
1141 spin_unlock_irqrestore(&ha->tgt.sess_lock, flags);
1142
1143 return res;
1144}
1145
1146/*
1147 * qla2x00_wait_for_sess_deletion can only be called from remove_one.
1148 * it has dependency on UNLOADING flag to stop device discovery
1149 */
1150static void
1151qla2x00_wait_for_sess_deletion(scsi_qla_host_t *vha)
1152{
1153 qla2x00_mark_all_devices_lost(vha, 0);
1154
b85e0957 1155 wait_event_timeout(vha->fcport_waitQ, test_fcport_count(vha), 10*HZ);
726b8548
QT		 1156}
1157
86fbee86 1158/*
638a1a01
SC		 1159 * qla2x00_wait_for_hba_ready
1160 * Wait till the HBA is ready before doing driver unload
86fbee86
LC		 1161 *
1162 * Input:
1163 * ha - pointer to host adapter structure
1164 *
1165 * Note:
1166 * Does context switching-Release SPIN_LOCK
1167 * (if any) before calling this routine.
1168 *
86fbee86 1169 */
638a1a01
SC		 1170static void
1171qla2x00_wait_for_hba_ready(scsi_qla_host_t *vha)
86fbee86 1172{
86fbee86 1173 struct qla_hw_data *ha = vha->hw;
783e0dc4 1174 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
86fbee86 1175
1d483901
DC		 1176 while ((qla2x00_reset_active(vha) || ha->dpc_active ||
1177 ha->flags.mbox_busy) ||
1178 test_bit(FX00_RESET_RECOVERY, &vha->dpc_flags) ||
1179 test_bit(FX00_TARGET_SCAN, &vha->dpc_flags)) {
1180 if (test_bit(UNLOADING, &base_vha->dpc_flags))
1181 break;
86fbee86 1182 msleep(1000);
783e0dc4 1183 }
86fbee86
LC		 1184}
1185
2533cf67
LC		 1186int
1187qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha)
1188{
1189 int return_status;
1190 unsigned long wait_reset;
1191 struct qla_hw_data *ha = vha->hw;
1192 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1193
1194 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ);
1195 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
1196 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
1197 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
1198 ha->dpc_active) && time_before(jiffies, wait_reset)) {
1199
1200 msleep(1000);
1201
1202 if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) &&
1203 ha->flags.chip_reset_done)
1204 break;
1205 }
1206 if (ha->flags.chip_reset_done)
1207 return_status = QLA_SUCCESS;
1208 else
1209 return_status = QLA_FUNCTION_FAILED;
1210
1211 return return_status;
1212}
1213
083a469d
GM		 1214static void
1215sp_get(struct srb *sp)
1216{
1217 atomic_inc(&sp->ref_count);
1218}
1219
a465537a
SC		 1220#define ISP_REG_DISCONNECT 0xffffffffU
1221/**************************************************************************
1222* qla2x00_isp_reg_stat
1223*
1224* Description:
1225* Read the host status register of ISP before aborting the command.
1226*
1227* Input:
1228* ha = pointer to host adapter structure.
1229*
1230*
1231* Returns:
1232* Either true or false.
1233*
1234* Note: Return true if there is register disconnect.
1235**************************************************************************/
1236static inline
1237uint32_t qla2x00_isp_reg_stat(struct qla_hw_data *ha)
1238{
1239 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
bf6061b1 1240 struct device_reg_82xx __iomem *reg82 = &ha->iobase->isp82;
a465537a 1241
bf6061b1
SC		 1242 if (IS_P3P_TYPE(ha))
1243 return ((RD_REG_DWORD(&reg82->host_int)) == ISP_REG_DISCONNECT);
1244 else
1245 return ((RD_REG_DWORD(&reg->host_status)) ==
1246 ISP_REG_DISCONNECT);
a465537a
SC		 1247}
1248
1da177e4
LT		 1249/**************************************************************************
1250* qla2xxx_eh_abort
1251*
1252* Description:
1253* The abort function will abort the specified command.
1254*
1255* Input:
1256* cmd = Linux SCSI command packet to be aborted.
1257*
1258* Returns:
1259* Either SUCCESS or FAILED.
1260*
1261* Note:
2ea00202 1262* Only return FAILED if command not returned by firmware.
1da177e4 1263**************************************************************************/
e5f82ab8 1264static int
1da177e4
LT		 1265qla2xxx_eh_abort(struct scsi_cmnd *cmd)
1266{
e315cd28 1267 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
f4f051eb 1268 srb_t *sp;
4e98d3b8 1269 int ret;
9cb78c16
HR		 1270 unsigned int id;
1271 uint64_t lun;
18e144d3 1272 unsigned long flags;
f934c9d0 1273 int rval, wait = 0;
e315cd28 1274 struct qla_hw_data *ha = vha->hw;
1da177e4 1275
a465537a
SC		 1276 if (qla2x00_isp_reg_stat(ha)) {
1277 ql_log(ql_log_info, vha, 0x8042,
1278 "PCI/Register disconnect, exiting.\n");
1279 return FAILED;
1280 }
f4f051eb 1281 if (!CMD_SP(cmd))
2ea00202 1282 return SUCCESS;
1da177e4 1283
4e98d3b8
AV		 1284 ret = fc_block_scsi_eh(cmd);
1285 if (ret != 0)
1286 return ret;
1287 ret = SUCCESS;
1288
f4f051eb 1289 id = cmd->device->id;
1290 lun = cmd->device->lun;
1da177e4 1291
e315cd28 1292 spin_lock_irqsave(&ha->hardware_lock, flags);
170babc3
MC		 1293 sp = (srb_t *) CMD_SP(cmd);
1294 if (!sp) {
1295 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1296 return SUCCESS;
1297 }
1da177e4 1298
7c3df132 1299 ql_dbg(ql_dbg_taskm, vha, 0x8002,
c7bc4cae
CD		 1300 "Aborting from RISC nexus=%ld:%d:%llu sp=%p cmd=%p handle=%x\n",
1301 vha->host_no, id, lun, sp, cmd, sp->handle);
17d98630 1302
170babc3
MC		 1303 /* Get a reference to the sp and drop the lock.*/
1304 sp_get(sp);
083a469d 1305
e315cd28 1306 spin_unlock_irqrestore(&ha->hardware_lock, flags);
f934c9d0
CD		 1307 rval = ha->isp_ops->abort_command(sp);
1308 if (rval) {
96219424 1309 if (rval == QLA_FUNCTION_PARAMETER_ERROR)
f934c9d0 1310 ret = SUCCESS;
96219424 1311 else
f934c9d0
CD		 1312 ret = FAILED;
1313
7c3df132 1314 ql_dbg(ql_dbg_taskm, vha, 0x8003,
f934c9d0 1315 "Abort command mbx failed cmd=%p, rval=%x.\n", cmd, rval);
170babc3 1316 } else {
7c3df132 1317 ql_dbg(ql_dbg_taskm, vha, 0x8004,
cfb0919c 1318 "Abort command mbx success cmd=%p.\n", cmd);
170babc3
MC		 1319 wait = 1;
1320 }
75942064
SK		 1321
1322 spin_lock_irqsave(&ha->hardware_lock, flags);
25ff6af1 1323 sp->done(sp, 0);
75942064 1324 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1da177e4 1325
bc91ade9
CD		 1326 /* Did the command return during mailbox execution? */
1327 if (ret == FAILED && !CMD_SP(cmd))
1328 ret = SUCCESS;
1329
f4f051eb 1330 /* Wait for the command to be returned. */
2ea00202 1331 if (wait) {
e315cd28 1332 if (qla2x00_eh_wait_on_command(cmd) != QLA_SUCCESS) {
7c3df132 1333 ql_log(ql_log_warn, vha, 0x8006,
cfb0919c 1334 "Abort handler timed out cmd=%p.\n", cmd);
2ea00202 1335 ret = FAILED;
f4f051eb 1336 }
1da177e4 1337 }
1da177e4 1338
7c3df132 1339 ql_log(ql_log_info, vha, 0x801c,
9cb78c16 1340 "Abort command issued nexus=%ld:%d:%llu -- %d %x.\n",
cfb0919c 1341 vha->host_no, id, lun, wait, ret);
1da177e4 1342
f4f051eb 1343 return ret;
1344}
1da177e4 1345
4d78c973 1346int
e315cd28 1347qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t,
9cb78c16 1348 uint64_t l, enum nexus_wait_type type)
f4f051eb 1349{
17d98630 1350 int cnt, match, status;
18e144d3 1351 unsigned long flags;
e315cd28 1352 struct qla_hw_data *ha = vha->hw;
73208dfd 1353 struct req_que *req;
4d78c973 1354 srb_t *sp;
9ba56b95 1355 struct scsi_cmnd *cmd;
1da177e4 1356
523ec773 1357 status = QLA_SUCCESS;
17d98630 1358
e315cd28 1359 spin_lock_irqsave(&ha->hardware_lock, flags);
67c2e93a 1360 req = vha->req;
17d98630 1361 for (cnt = 1; status == QLA_SUCCESS &&
8d93f550 1362 cnt < req->num_outstanding_cmds; cnt++) {
17d98630
AC		 1363 sp = req->outstanding_cmds[cnt];
1364 if (!sp)
523ec773 1365 continue;
9ba56b95 1366 if (sp->type != SRB_SCSI_CMD)
cf53b069 1367 continue;
25ff6af1 1368 if (vha->vp_idx != sp->vha->vp_idx)
17d98630
AC		 1369 continue;
1370 match = 0;
9ba56b95 1371 cmd = GET_CMD_SP(sp);
17d98630
AC		 1372 switch (type) {
1373 case WAIT_HOST:
1374 match = 1;
1375 break;
1376 case WAIT_TARGET:
9ba56b95 1377 match = cmd->device->id == t;
17d98630
AC		 1378 break;
1379 case WAIT_LUN:
9ba56b95
GM		 1380 match = (cmd->device->id == t &&
1381 cmd->device->lun == l);
17d98630 1382 break;
73208dfd 1383 }
17d98630
AC		 1384 if (!match)
1385 continue;
1386
1387 spin_unlock_irqrestore(&ha->hardware_lock, flags);
9ba56b95 1388 status = qla2x00_eh_wait_on_command(cmd);
17d98630 1389 spin_lock_irqsave(&ha->hardware_lock, flags);
1da177e4 1390 }
e315cd28 1391 spin_unlock_irqrestore(&ha->hardware_lock, flags);
523ec773
AV		 1392
1393 return status;
1da177e4
LT		 1394}
1395
523ec773
AV		 1396static char *reset_errors[] = {
1397 "HBA not online",
1398 "HBA not ready",
1399 "Task management failed",
1400 "Waiting for command completions",
1401};
1da177e4 1402
e5f82ab8 1403static int
523ec773 1404__qla2xxx_eh_generic_reset(char *name, enum nexus_wait_type type,
9cb78c16 1405 struct scsi_cmnd *cmd, int (*do_reset)(struct fc_port *, uint64_t, int))
1da177e4 1406{
e315cd28 1407 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
bdf79621 1408 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
523ec773 1409 int err;
1da177e4 1410
7c3df132 1411 if (!fcport) {
523ec773 1412 return FAILED;
7c3df132 1413 }
1da177e4 1414
4e98d3b8
AV		 1415 err = fc_block_scsi_eh(cmd);
1416 if (err != 0)
1417 return err;
1418
7c3df132 1419 ql_log(ql_log_info, vha, 0x8009,
9cb78c16 1420 "%s RESET ISSUED nexus=%ld:%d:%llu cmd=%p.\n", name, vha->host_no,
7c3df132 1421 cmd->device->id, cmd->device->lun, cmd);
1da177e4 1422
523ec773 1423 err = 0;
7c3df132
SK		 1424 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1425 ql_log(ql_log_warn, vha, 0x800a,
1426 "Wait for hba online failed for cmd=%p.\n", cmd);
523ec773 1427 goto eh_reset_failed;
7c3df132 1428 }
523ec773 1429 err = 2;
2afa19a9 1430 if (do_reset(fcport, cmd->device->lun, cmd->request->cpu + 1)
7c3df132
SK		 1431 != QLA_SUCCESS) {
1432 ql_log(ql_log_warn, vha, 0x800c,
1433 "do_reset failed for cmd=%p.\n", cmd);
523ec773 1434 goto eh_reset_failed;
7c3df132 1435 }
523ec773 1436 err = 3;
e315cd28 1437 if (qla2x00_eh_wait_for_pending_commands(vha, cmd->device->id,
7c3df132
SK		 1438 cmd->device->lun, type) != QLA_SUCCESS) {
1439 ql_log(ql_log_warn, vha, 0x800d,
d6a03581 1440 "wait for pending cmds failed for cmd=%p.\n", cmd);
523ec773 1441 goto eh_reset_failed;
7c3df132 1442 }
523ec773 1443
7c3df132 1444 ql_log(ql_log_info, vha, 0x800e,
9cb78c16 1445 "%s RESET SUCCEEDED nexus:%ld:%d:%llu cmd=%p.\n", name,
cfb0919c 1446 vha->host_no, cmd->device->id, cmd->device->lun, cmd);
523ec773
AV		 1447
1448 return SUCCESS;
1449
4d78c973 1450eh_reset_failed:
7c3df132 1451 ql_log(ql_log_info, vha, 0x800f,
9cb78c16 1452 "%s RESET FAILED: %s nexus=%ld:%d:%llu cmd=%p.\n", name,
cfb0919c
CD		 1453 reset_errors[err], vha->host_no, cmd->device->id, cmd->device->lun,
1454 cmd);
523ec773
AV		 1455 return FAILED;
1456}
1da177e4 1457
523ec773
AV		 1458static int
1459qla2xxx_eh_device_reset(struct scsi_cmnd *cmd)
1460{
e315cd28
AC		 1461 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1462 struct qla_hw_data *ha = vha->hw;
1da177e4 1463
a465537a
SC		 1464 if (qla2x00_isp_reg_stat(ha)) {
1465 ql_log(ql_log_info, vha, 0x803e,
1466 "PCI/Register disconnect, exiting.\n");
1467 return FAILED;
1468 }
1469
523ec773
AV		 1470 return __qla2xxx_eh_generic_reset("DEVICE", WAIT_LUN, cmd,
1471 ha->isp_ops->lun_reset);
1da177e4
LT		 1472}
1473
1da177e4 1474static int
523ec773 1475qla2xxx_eh_target_reset(struct scsi_cmnd *cmd)
1da177e4 1476{
e315cd28
AC		 1477 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1478 struct qla_hw_data *ha = vha->hw;
1da177e4 1479
a465537a
SC		 1480 if (qla2x00_isp_reg_stat(ha)) {
1481 ql_log(ql_log_info, vha, 0x803f,
1482 "PCI/Register disconnect, exiting.\n");
1483 return FAILED;
1484 }
1485
523ec773
AV		 1486 return __qla2xxx_eh_generic_reset("TARGET", WAIT_TARGET, cmd,
1487 ha->isp_ops->target_reset);
1da177e4
LT		 1488}
1489
1da177e4
LT		 1490/**************************************************************************
1491* qla2xxx_eh_bus_reset
1492*
1493* Description:
1494* The bus reset function will reset the bus and abort any executing
1495* commands.
1496*
1497* Input:
1498* cmd = Linux SCSI command packet of the command that cause the
1499* bus reset.
1500*
1501* Returns:
1502* SUCCESS/FAILURE (defined as macro in scsi.h).
1503*
1504**************************************************************************/
e5f82ab8 1505static int
1da177e4
LT		 1506qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd)
1507{
e315cd28 1508 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
bdf79621 1509 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
2c3dfe3f 1510 int ret = FAILED;
9cb78c16
HR		 1511 unsigned int id;
1512 uint64_t lun;
a465537a
SC		 1513 struct qla_hw_data *ha = vha->hw;
1514
1515 if (qla2x00_isp_reg_stat(ha)) {
1516 ql_log(ql_log_info, vha, 0x8040,
1517 "PCI/Register disconnect, exiting.\n");
1518 return FAILED;
1519 }
f4f051eb 1520
f4f051eb 1521 id = cmd->device->id;
1522 lun = cmd->device->lun;
1da177e4 1523
7c3df132 1524 if (!fcport) {
f4f051eb 1525 return ret;
7c3df132 1526 }
1da177e4 1527
4e98d3b8
AV		 1528 ret = fc_block_scsi_eh(cmd);
1529 if (ret != 0)
1530 return ret;
1531 ret = FAILED;
1532
7c3df132 1533 ql_log(ql_log_info, vha, 0x8012,
9cb78c16 1534 "BUS RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun);
1da177e4 1535
e315cd28 1536 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
7c3df132
SK		 1537 ql_log(ql_log_fatal, vha, 0x8013,
1538 "Wait for hba online failed board disabled.\n");
f4f051eb 1539 goto eh_bus_reset_done;
1da177e4
LT		 1540 }
1541
ad537689
SK		 1542 if (qla2x00_loop_reset(vha) == QLA_SUCCESS)
1543 ret = SUCCESS;
1544
f4f051eb 1545 if (ret == FAILED)
1546 goto eh_bus_reset_done;
1da177e4 1547
9a41a62b 1548 /* Flush outstanding commands. */
4d78c973 1549 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) !=
7c3df132
SK		 1550 QLA_SUCCESS) {
1551 ql_log(ql_log_warn, vha, 0x8014,
1552 "Wait for pending commands failed.\n");
9a41a62b 1553 ret = FAILED;
7c3df132 1554 }
1da177e4 1555
f4f051eb 1556eh_bus_reset_done:
7c3df132 1557 ql_log(ql_log_warn, vha, 0x802b,
9cb78c16 1558 "BUS RESET %s nexus=%ld:%d:%llu.\n",
d6a03581 1559 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1da177e4 1560
f4f051eb 1561 return ret;
1da177e4
LT		 1562}
1563
1564/**************************************************************************
1565* qla2xxx_eh_host_reset
1566*
1567* Description:
1568* The reset function will reset the Adapter.
1569*
1570* Input:
1571* cmd = Linux SCSI command packet of the command that cause the
1572* adapter reset.
1573*
1574* Returns:
1575* Either SUCCESS or FAILED.
1576*
1577* Note:
1578**************************************************************************/
e5f82ab8 1579static int
1da177e4
LT		 1580qla2xxx_eh_host_reset(struct scsi_cmnd *cmd)
1581{
e315cd28 1582 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
e315cd28 1583 struct qla_hw_data *ha = vha->hw;
2c3dfe3f 1584 int ret = FAILED;
9cb78c16
HR		 1585 unsigned int id;
1586 uint64_t lun;
e315cd28 1587 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4 1588
a465537a
SC		 1589 if (qla2x00_isp_reg_stat(ha)) {
1590 ql_log(ql_log_info, vha, 0x8041,
1591 "PCI/Register disconnect, exiting.\n");
1592 schedule_work(&ha->board_disable);
1593 return SUCCESS;
1594 }
1595
f4f051eb 1596 id = cmd->device->id;
1597 lun = cmd->device->lun;
f4f051eb 1598
7c3df132 1599 ql_log(ql_log_info, vha, 0x8018,
9cb78c16 1600 "ADAPTER RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun);
1da177e4 1601
63ee7072
CD		 1602 /*
1603 * No point in issuing another reset if one is active. Also do not
1604 * attempt a reset if we are updating flash.
1605 */
1606 if (qla2x00_reset_active(vha) || ha->optrom_state != QLA_SWAITING)
f4f051eb 1607 goto eh_host_reset_lock;
1da177e4 1608
e315cd28
AC		 1609 if (vha != base_vha) {
1610 if (qla2x00_vp_abort_isp(vha))
f4f051eb 1611 goto eh_host_reset_lock;
e315cd28 1612 } else {
7ec0effd 1613 if (IS_P3P_TYPE(vha->hw)) {
a9083016
GM		 1614 if (!qla82xx_fcoe_ctx_reset(vha)) {
1615 /* Ctx reset success */
1616 ret = SUCCESS;
1617 goto eh_host_reset_lock;
1618 }
1619 /* fall thru if ctx reset failed */
1620 }
68ca949c
AC		 1621 if (ha->wq)
1622 flush_workqueue(ha->wq);
1623
e315cd28 1624 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
a9083016 1625 if (ha->isp_ops->abort_isp(base_vha)) {
e315cd28
AC		 1626 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1627 /* failed. schedule dpc to try */
1628 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
1629
7c3df132
SK		 1630 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1631 ql_log(ql_log_warn, vha, 0x802a,
1632 "wait for hba online failed.\n");
e315cd28 1633 goto eh_host_reset_lock;
7c3df132 1634 }
e315cd28
AC		 1635 }
1636 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
fa2a1ce5 1637 }
1da177e4 1638
e315cd28 1639 /* Waiting for command to be returned to OS.*/
4d78c973 1640 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) ==
e315cd28 1641 QLA_SUCCESS)
f4f051eb 1642 ret = SUCCESS;
1da177e4 1643
f4f051eb 1644eh_host_reset_lock:
cfb0919c 1645 ql_log(ql_log_info, vha, 0x8017,
9cb78c16 1646 "ADAPTER RESET %s nexus=%ld:%d:%llu.\n",
cfb0919c 1647 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1da177e4 1648
f4f051eb 1649 return ret;
1650}
1da177e4
LT		 1651
1652/*
1653* qla2x00_loop_reset
1654* Issue loop reset.
1655*
1656* Input:
1657* ha = adapter block pointer.
1658*
1659* Returns:
1660* 0 = success
1661*/
a4722cf2 1662int
e315cd28 1663qla2x00_loop_reset(scsi_qla_host_t *vha)
1da177e4 1664{
0c8c39af 1665 int ret;
bdf79621 1666 struct fc_port *fcport;
e315cd28 1667 struct qla_hw_data *ha = vha->hw;
1da177e4 1668
5854771e
AB		 1669 if (IS_QLAFX00(ha)) {
1670 return qlafx00_loop_reset(vha);
1671 }
1672
f4c496c1 1673 if (ql2xtargetreset == 1 && ha->flags.enable_target_reset) {
55e5ed27
AV		 1674 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1675 if (fcport->port_type != FCT_TARGET)
1676 continue;
1677
1678 ret = ha->isp_ops->target_reset(fcport, 0, 0);
1679 if (ret != QLA_SUCCESS) {
7c3df132 1680 ql_dbg(ql_dbg_taskm, vha, 0x802c,
5854771e 1681 "Bus Reset failed: Reset=%d "
7c3df132 1682 "d_id=%x.\n", ret, fcport->d_id.b24);
55e5ed27
AV		 1683 }
1684 }
1685 }
1686
8ae6d9c7 1687
6246b8a1 1688 if (ha->flags.enable_lip_full_login && !IS_CNA_CAPABLE(ha)) {
0b7e7c53
AV		 1689 atomic_set(&vha->loop_state, LOOP_DOWN);
1690 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
1691 qla2x00_mark_all_devices_lost(vha, 0);
e315cd28 1692 ret = qla2x00_full_login_lip(vha);
0c8c39af 1693 if (ret != QLA_SUCCESS) {
7c3df132
SK		 1694 ql_dbg(ql_dbg_taskm, vha, 0x802d,
1695 "full_login_lip=%d.\n", ret);
749af3d5 1696 }
0c8c39af
AV		 1697 }
1698
0d6e61bc 1699 if (ha->flags.enable_lip_reset) {
e315cd28 1700 ret = qla2x00_lip_reset(vha);
ad537689 1701 if (ret != QLA_SUCCESS)
7c3df132
SK		 1702 ql_dbg(ql_dbg_taskm, vha, 0x802e,
1703 "lip_reset failed (%d).\n", ret);
1da177e4
LT		 1704 }
1705
1da177e4 1706 /* Issue marker command only when we are going to start the I/O */
e315cd28 1707 vha->marker_needed = 1;
1da177e4 1708
0c8c39af 1709 return QLA_SUCCESS;
1da177e4
LT		 1710}
1711
bbead493
QT		 1712static void
1713__qla2x00_abort_all_cmds(struct qla_qpair *qp, int res)
df4bf0bb 1714{
bbead493 1715 int cnt, status;
df4bf0bb
AV		 1716 unsigned long flags;
1717 srb_t *sp;
bbead493 1718 scsi_qla_host_t *vha = qp->vha;
e315cd28 1719 struct qla_hw_data *ha = vha->hw;
73208dfd 1720 struct req_que *req;
c5419e26
QT		 1721 struct qla_tgt *tgt = vha->vha_tgt.qla_tgt;
1722 struct qla_tgt_cmd *cmd;
1723 uint8_t trace = 0;
c0cb4496 1724
6a2cf8d3
BK		 1725 if (!ha->req_q_map)
1726 return;
bbead493
QT		 1727 spin_lock_irqsave(qp->qp_lock_ptr, flags);
1728 req = qp->req;
1729 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) {
1730 sp = req->outstanding_cmds[cnt];
1731 if (sp) {
1732 req->outstanding_cmds[cnt] = NULL;
1733 if (sp->cmd_type == TYPE_SRB) {
1734 if (sp->type == SRB_NVME_CMD ||
1735 sp->type == SRB_NVME_LS) {
1736 sp_get(sp);
1737 spin_unlock_irqrestore(qp->qp_lock_ptr,
1738 flags);
623ee824 1739 qla_nvme_abort(ha, sp, res);
bbead493
QT		 1740 spin_lock_irqsave(qp->qp_lock_ptr,
1741 flags);
1742 } else if (GET_CMD_SP(sp) &&
1743 !ha->flags.eeh_busy &&
1744 (!test_bit(ABORT_ISP_ACTIVE,
1745 &vha->dpc_flags)) &&
1746 (sp->type == SRB_SCSI_CMD)) {
1747 /*
1748 * Don't abort commands in
1749 * adapter during EEH
1750 * recovery as it's not
1751 * accessible/responding.
1752 *
1753 * Get a reference to the sp
1754 * and drop the lock. The
1755 * reference ensures this
1756 * sp->done() call and not the
1757 * call in qla2xxx_eh_abort()
1758 * ends the SCSI command (with
1759 * result 'res').
1760 */
1761 sp_get(sp);
1762 spin_unlock_irqrestore(qp->qp_lock_ptr,
1763 flags);
1764 status = qla2xxx_eh_abort(
1765 GET_CMD_SP(sp));
1766 spin_lock_irqsave(qp->qp_lock_ptr,
1767 flags);
1768 /*
1769 * Get rid of extra reference
1770 * if immediate exit from
1771 * ql2xxx_eh_abort
1772 */
1773 if (status == FAILED &&
1774 (qla2x00_isp_reg_stat(ha)))
1775 atomic_dec(
1776 &sp->ref_count);
1777 }
1778 sp->done(sp, res);
1779 } else {
1780 if (!vha->hw->tgt.tgt_ops || !tgt ||
1781 qla_ini_mode_enabled(vha)) {
1782 if (!trace)
1783 ql_dbg(ql_dbg_tgt_mgt,
1784 vha, 0xf003,
1785 "HOST-ABORT-HNDLR: dpc_flags=%lx. Target mode disabled\n",
1786 vha->dpc_flags);
1787 continue;
c733ab35 1788 }
bbead493
QT		 1789 cmd = (struct qla_tgt_cmd *)sp;
1790 qlt_abort_cmd_on_host_reset(cmd->vha, cmd);
73208dfd 1791 }
df4bf0bb
AV		 1792 }
1793 }
bbead493
QT		 1794 spin_unlock_irqrestore(qp->qp_lock_ptr, flags);
1795}
1796
1797void
1798qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res)
1799{
1800 int que;
1801 struct qla_hw_data *ha = vha->hw;
1802
1803 __qla2x00_abort_all_cmds(ha->base_qpair, res);
1804
1805 for (que = 0; que < ha->max_qpairs; que++) {
1806 if (!ha->queue_pair_map[que])
1807 continue;
1808
1809 __qla2x00_abort_all_cmds(ha->queue_pair_map[que], res);
1810 }
df4bf0bb
AV		 1811}
1812
f4f051eb 1813static int
1814qla2xxx_slave_alloc(struct scsi_device *sdev)
1da177e4 1815{
bdf79621 1816 struct fc_rport *rport = starget_to_rport(scsi_target(sdev));
1da177e4 1817
19a7b4ae 1818 if (!rport || fc_remote_port_chkready(rport))
f4f051eb 1819 return -ENXIO;
bdf79621 1820
19a7b4ae 1821 sdev->hostdata = *(fc_port_t **)rport->dd_data;
1da177e4 1822
f4f051eb 1823 return 0;
1824}
1da177e4 1825
f4f051eb 1826static int
1827qla2xxx_slave_configure(struct scsi_device *sdev)
1828{
e315cd28 1829 scsi_qla_host_t *vha = shost_priv(sdev->host);
2afa19a9 1830 struct req_que *req = vha->req;
8482e118 1831
9e522cd8
AE		 1832 if (IS_T10_PI_CAPABLE(vha->hw))
1833 blk_queue_update_dma_alignment(sdev->request_queue, 0x7);
1834
db5ed4df 1835 scsi_change_queue_depth(sdev, req->max_q_depth);
f4f051eb 1836 return 0;
1837}
1da177e4 1838
f4f051eb 1839static void
1840qla2xxx_slave_destroy(struct scsi_device *sdev)
1841{
1842 sdev->hostdata = NULL;
1da177e4
LT		 1843}
1844
1845/**
1846 * qla2x00_config_dma_addressing() - Configure OS DMA addressing method.
1847 * @ha: HA context
1848 *
1849 * At exit, the @ha's flags.enable_64bit_addressing set to indicated
1850 * supported addressing method.
1851 */
1852static void
53303c42 1853qla2x00_config_dma_addressing(struct qla_hw_data *ha)
1da177e4 1854{
7524f9b9 1855 /* Assume a 32bit DMA mask. */
1da177e4 1856 ha->flags.enable_64bit_addressing = 0;
1da177e4 1857
6a35528a 1858 if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) {
7524f9b9
AV		 1859 /* Any upper-dword bits set? */
1860 if (MSD(dma_get_required_mask(&ha->pdev->dev)) &&
6a35528a 1861 !pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(64))) {
7524f9b9 1862 /* Ok, a 64bit DMA mask is applicable. */
1da177e4 1863 ha->flags.enable_64bit_addressing = 1;
fd34f556
AV		 1864 ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64;
1865 ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64;
7524f9b9 1866 return;
1da177e4 1867 }
1da177e4 1868 }
7524f9b9 1869
284901a9
YH		 1870 dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32));
1871 pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(32));
1da177e4
LT		 1872}
1873
fd34f556 1874static void
e315cd28 1875qla2x00_enable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1876{
1877 unsigned long flags = 0;
1878 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1879
1880 spin_lock_irqsave(&ha->hardware_lock, flags);
1881 ha->interrupts_on = 1;
1882 /* enable risc and host interrupts */
1883 WRT_REG_WORD(&reg->ictrl, ICR_EN_INT | ICR_EN_RISC);
1884 RD_REG_WORD(&reg->ictrl);
1885 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1886
1887}
1888
1889static void
e315cd28 1890qla2x00_disable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1891{
1892 unsigned long flags = 0;
1893 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1894
1895 spin_lock_irqsave(&ha->hardware_lock, flags);
1896 ha->interrupts_on = 0;
1897 /* disable risc and host interrupts */
1898 WRT_REG_WORD(&reg->ictrl, 0);
1899 RD_REG_WORD(&reg->ictrl);
1900 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1901}
1902
1903static void
e315cd28 1904qla24xx_enable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1905{
1906 unsigned long flags = 0;
1907 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1908
1909 spin_lock_irqsave(&ha->hardware_lock, flags);
1910 ha->interrupts_on = 1;
1911 WRT_REG_DWORD(&reg->ictrl, ICRX_EN_RISC_INT);
1912 RD_REG_DWORD(&reg->ictrl);
1913 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1914}
1915
1916static void
e315cd28 1917qla24xx_disable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1918{
1919 unsigned long flags = 0;
1920 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1921
124f85e6
AV		 1922 if (IS_NOPOLLING_TYPE(ha))
1923 return;
fd34f556
AV		 1924 spin_lock_irqsave(&ha->hardware_lock, flags);
1925 ha->interrupts_on = 0;
1926 WRT_REG_DWORD(&reg->ictrl, 0);
1927 RD_REG_DWORD(&reg->ictrl);
1928 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1929}
1930
706f457d
GM		 1931static int
1932qla2x00_iospace_config(struct qla_hw_data *ha)
1933{
1934 resource_size_t pio;
1935 uint16_t msix;
706f457d 1936
706f457d
GM		 1937 if (pci_request_selected_regions(ha->pdev, ha->bars,
1938 QLA2XXX_DRIVER_NAME)) {
1939 ql_log_pci(ql_log_fatal, ha->pdev, 0x0011,
1940 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
1941 pci_name(ha->pdev));
1942 goto iospace_error_exit;
1943 }
1944 if (!(ha->bars & 1))
1945 goto skip_pio;
1946
1947 /* We only need PIO for Flash operations on ISP2312 v2 chips. */
1948 pio = pci_resource_start(ha->pdev, 0);
1949 if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) {
1950 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
1951 ql_log_pci(ql_log_warn, ha->pdev, 0x0012,
1952 "Invalid pci I/O region size (%s).\n",
1953 pci_name(ha->pdev));
1954 pio = 0;
1955 }
1956 } else {
1957 ql_log_pci(ql_log_warn, ha->pdev, 0x0013,
1958 "Region #0 no a PIO resource (%s).\n",
1959 pci_name(ha->pdev));
1960 pio = 0;
1961 }
1962 ha->pio_address = pio;
1963 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014,
1964 "PIO address=%llu.\n",
1965 (unsigned long long)ha->pio_address);
1966
1967skip_pio:
1968 /* Use MMIO operations for all accesses. */
1969 if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) {
1970 ql_log_pci(ql_log_fatal, ha->pdev, 0x0015,
1971 "Region #1 not an MMIO resource (%s), aborting.\n",
1972 pci_name(ha->pdev));
1973 goto iospace_error_exit;
1974 }
1975 if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) {
1976 ql_log_pci(ql_log_fatal, ha->pdev, 0x0016,
1977 "Invalid PCI mem region size (%s), aborting.\n",
1978 pci_name(ha->pdev));
1979 goto iospace_error_exit;
1980 }
1981
1982 ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN);
1983 if (!ha->iobase) {
1984 ql_log_pci(ql_log_fatal, ha->pdev, 0x0017,
1985 "Cannot remap MMIO (%s), aborting.\n",
1986 pci_name(ha->pdev));
1987 goto iospace_error_exit;
1988 }
1989
1990 /* Determine queue resources */
1991 ha->max_req_queues = ha->max_rsp_queues = 1;
f54f2cb5 1992 ha->msix_count = QLA_BASE_VECTORS;
c38d1baf
HM		 1993 if (!ql2xmqsupport || !ql2xnvmeenable ||
1994 (!IS_QLA25XX(ha) && !IS_QLA81XX(ha)))
706f457d
GM		 1995 goto mqiobase_exit;
1996
1997 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3),
1998 pci_resource_len(ha->pdev, 3));
1999 if (ha->mqiobase) {
2000 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018,
2001 "MQIO Base=%p.\n", ha->mqiobase);
2002 /* Read MSIX vector size of the board */
2003 pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix);
d7459527 2004 ha->msix_count = msix + 1;
706f457d 2005 /* Max queues are bounded by available msix vectors */
d7459527
MH		 2006 /* MB interrupt uses 1 vector */
2007 ha->max_req_queues = ha->msix_count - 1;
2008 ha->max_rsp_queues = ha->max_req_queues;
2009 /* Queue pairs is the max value minus the base queue pair */
2010 ha->max_qpairs = ha->max_rsp_queues - 1;
2011 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0188,
2012 "Max no of queues pairs: %d.\n", ha->max_qpairs);
2013
706f457d 2014 ql_log_pci(ql_log_info, ha->pdev, 0x001a,
d7459527 2015 "MSI-X vector count: %d.\n", ha->msix_count);
706f457d
GM		 2016 } else
2017 ql_log_pci(ql_log_info, ha->pdev, 0x001b,
2018 "BAR 3 not enabled.\n");
2019
2020mqiobase_exit:
706f457d 2021 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c,
f54f2cb5 2022 "MSIX Count: %d.\n", ha->msix_count);
706f457d
GM		 2023 return (0);
2024
2025iospace_error_exit:
2026 return (-ENOMEM);
2027}
2028
2029
6246b8a1
GM		 2030static int
2031qla83xx_iospace_config(struct qla_hw_data *ha)
2032{
2033 uint16_t msix;
6246b8a1
GM		 2034
2035 if (pci_request_selected_regions(ha->pdev, ha->bars,
2036 QLA2XXX_DRIVER_NAME)) {
2037 ql_log_pci(ql_log_fatal, ha->pdev, 0x0117,
2038 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
2039 pci_name(ha->pdev));
2040
2041 goto iospace_error_exit;
2042 }
2043
2044 /* Use MMIO operations for all accesses. */
2045 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) {
2046 ql_log_pci(ql_log_warn, ha->pdev, 0x0118,
2047 "Invalid pci I/O region size (%s).\n",
2048 pci_name(ha->pdev));
2049 goto iospace_error_exit;
2050 }
2051 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
2052 ql_log_pci(ql_log_warn, ha->pdev, 0x0119,
2053 "Invalid PCI mem region size (%s), aborting\n",
2054 pci_name(ha->pdev));
2055 goto iospace_error_exit;
2056 }
2057
2058 ha->iobase = ioremap(pci_resource_start(ha->pdev, 0), MIN_IOBASE_LEN);
2059 if (!ha->iobase) {
2060 ql_log_pci(ql_log_fatal, ha->pdev, 0x011a,
2061 "Cannot remap MMIO (%s), aborting.\n",
2062 pci_name(ha->pdev));
2063 goto iospace_error_exit;
2064 }
2065
2066 /* 64bit PCI BAR - BAR2 will correspoond to region 4 */
2067 /* 83XX 26XX always use MQ type access for queues
2068 * - mbar 2, a.k.a region 4 */
2069 ha->max_req_queues = ha->max_rsp_queues = 1;
f54f2cb5 2070 ha->msix_count = QLA_BASE_VECTORS;
6246b8a1
GM		 2071 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 4),
2072 pci_resource_len(ha->pdev, 4));
2073
2074 if (!ha->mqiobase) {
2075 ql_log_pci(ql_log_fatal, ha->pdev, 0x011d,
2076 "BAR2/region4 not enabled\n");
2077 goto mqiobase_exit;
2078 }
2079
2080 ha->msixbase = ioremap(pci_resource_start(ha->pdev, 2),
2081 pci_resource_len(ha->pdev, 2));
2082 if (ha->msixbase) {
2083 /* Read MSIX vector size of the board */
2084 pci_read_config_word(ha->pdev,
2085 QLA_83XX_PCI_MSIX_CONTROL, &msix);
e326d22a 2086 ha->msix_count = (msix & PCI_MSIX_FLAGS_QSIZE) + 1;
093df737
QT		 2087 /*
2088 * By default, driver uses at least two msix vectors
2089 * (default & rspq)
2090 */
c38d1baf 2091 if (ql2xmqsupport || ql2xnvmeenable) {
d7459527
MH		 2092 /* MB interrupt uses 1 vector */
2093 ha->max_req_queues = ha->msix_count - 1;
093df737
QT		 2094
2095 /* ATIOQ needs 1 vector. That's 1 less QPair */
2096 if (QLA_TGT_MODE_ENABLED())
2097 ha->max_req_queues--;
2098
d0d2c68b
MH		 2099 ha->max_rsp_queues = ha->max_req_queues;
2100
d7459527
MH		 2101 /* Queue pairs is the max value minus
2102 * the base queue pair */
2103 ha->max_qpairs = ha->max_req_queues - 1;
83548fe2 2104 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x00e3,
d7459527 2105 "Max no of queues pairs: %d.\n", ha->max_qpairs);
6246b8a1
GM		 2106 }
2107 ql_log_pci(ql_log_info, ha->pdev, 0x011c,
d7459527 2108 "MSI-X vector count: %d.\n", ha->msix_count);
6246b8a1
GM		 2109 } else
2110 ql_log_pci(ql_log_info, ha->pdev, 0x011e,
2111 "BAR 1 not enabled.\n");
2112
2113mqiobase_exit:
6246b8a1 2114 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011f,
f54f2cb5 2115 "MSIX Count: %d.\n", ha->msix_count);
6246b8a1
GM		 2116 return 0;
2117
2118iospace_error_exit:
2119 return -ENOMEM;
2120}
2121
fd34f556
AV		 2122static struct isp_operations qla2100_isp_ops = {
2123 .pci_config = qla2100_pci_config,
2124 .reset_chip = qla2x00_reset_chip,
2125 .chip_diag = qla2x00_chip_diag,
2126 .config_rings = qla2x00_config_rings,
2127 .reset_adapter = qla2x00_reset_adapter,
2128 .nvram_config = qla2x00_nvram_config,
2129 .update_fw_options = qla2x00_update_fw_options,
2130 .load_risc = qla2x00_load_risc,
2131 .pci_info_str = qla2x00_pci_info_str,
2132 .fw_version_str = qla2x00_fw_version_str,
2133 .intr_handler = qla2100_intr_handler,
2134 .enable_intrs = qla2x00_enable_intrs,
2135 .disable_intrs = qla2x00_disable_intrs,
2136 .abort_command = qla2x00_abort_command,
523ec773
AV		 2137 .target_reset = qla2x00_abort_target,
2138 .lun_reset = qla2x00_lun_reset,
fd34f556
AV		 2139 .fabric_login = qla2x00_login_fabric,
2140 .fabric_logout = qla2x00_fabric_logout,
2141 .calc_req_entries = qla2x00_calc_iocbs_32,
2142 .build_iocbs = qla2x00_build_scsi_iocbs_32,
2143 .prep_ms_iocb = qla2x00_prep_ms_iocb,
2144 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
2145 .read_nvram = qla2x00_read_nvram_data,
2146 .write_nvram = qla2x00_write_nvram_data,
2147 .fw_dump = qla2100_fw_dump,
2148 .beacon_on = NULL,
2149 .beacon_off = NULL,
2150 .beacon_blink = NULL,
2151 .read_optrom = qla2x00_read_optrom_data,
2152 .write_optrom = qla2x00_write_optrom_data,
2153 .get_flash_version = qla2x00_get_flash_version,
e315cd28 2154 .start_scsi = qla2x00_start_scsi,
d7459527 2155 .start_scsi_mq = NULL,
a9083016 2156 .abort_isp = qla2x00_abort_isp,
706f457d 2157 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2158 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 2159};
2160
2161static struct isp_operations qla2300_isp_ops = {
2162 .pci_config = qla2300_pci_config,
2163 .reset_chip = qla2x00_reset_chip,
2164 .chip_diag = qla2x00_chip_diag,
2165 .config_rings = qla2x00_config_rings,
2166 .reset_adapter = qla2x00_reset_adapter,
2167 .nvram_config = qla2x00_nvram_config,
2168 .update_fw_options = qla2x00_update_fw_options,
2169 .load_risc = qla2x00_load_risc,
2170 .pci_info_str = qla2x00_pci_info_str,
2171 .fw_version_str = qla2x00_fw_version_str,
2172 .intr_handler = qla2300_intr_handler,
2173 .enable_intrs = qla2x00_enable_intrs,
2174 .disable_intrs = qla2x00_disable_intrs,
2175 .abort_command = qla2x00_abort_command,
523ec773
AV		 2176 .target_reset = qla2x00_abort_target,
2177 .lun_reset = qla2x00_lun_reset,
fd34f556
AV		 2178 .fabric_login = qla2x00_login_fabric,
2179 .fabric_logout = qla2x00_fabric_logout,
2180 .calc_req_entries = qla2x00_calc_iocbs_32,
2181 .build_iocbs = qla2x00_build_scsi_iocbs_32,
2182 .prep_ms_iocb = qla2x00_prep_ms_iocb,
2183 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
2184 .read_nvram = qla2x00_read_nvram_data,
2185 .write_nvram = qla2x00_write_nvram_data,
2186 .fw_dump = qla2300_fw_dump,
2187 .beacon_on = qla2x00_beacon_on,
2188 .beacon_off = qla2x00_beacon_off,
2189 .beacon_blink = qla2x00_beacon_blink,
2190 .read_optrom = qla2x00_read_optrom_data,
2191 .write_optrom = qla2x00_write_optrom_data,
2192 .get_flash_version = qla2x00_get_flash_version,
e315cd28 2193 .start_scsi = qla2x00_start_scsi,
d7459527 2194 .start_scsi_mq = NULL,
a9083016 2195 .abort_isp = qla2x00_abort_isp,
7ec0effd 2196 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2197 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 2198};
2199
2200static struct isp_operations qla24xx_isp_ops = {
2201 .pci_config = qla24xx_pci_config,
2202 .reset_chip = qla24xx_reset_chip,
2203 .chip_diag = qla24xx_chip_diag,
2204 .config_rings = qla24xx_config_rings,
2205 .reset_adapter = qla24xx_reset_adapter,
2206 .nvram_config = qla24xx_nvram_config,
2207 .update_fw_options = qla24xx_update_fw_options,
2208 .load_risc = qla24xx_load_risc,
2209 .pci_info_str = qla24xx_pci_info_str,
2210 .fw_version_str = qla24xx_fw_version_str,
2211 .intr_handler = qla24xx_intr_handler,
2212 .enable_intrs = qla24xx_enable_intrs,
2213 .disable_intrs = qla24xx_disable_intrs,
2214 .abort_command = qla24xx_abort_command,
523ec773
AV		 2215 .target_reset = qla24xx_abort_target,
2216 .lun_reset = qla24xx_lun_reset,
fd34f556
AV		 2217 .fabric_login = qla24xx_login_fabric,
2218 .fabric_logout = qla24xx_fabric_logout,
2219 .calc_req_entries = NULL,
2220 .build_iocbs = NULL,
2221 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2222 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2223 .read_nvram = qla24xx_read_nvram_data,
2224 .write_nvram = qla24xx_write_nvram_data,
2225 .fw_dump = qla24xx_fw_dump,
2226 .beacon_on = qla24xx_beacon_on,
2227 .beacon_off = qla24xx_beacon_off,
2228 .beacon_blink = qla24xx_beacon_blink,
2229 .read_optrom = qla24xx_read_optrom_data,
2230 .write_optrom = qla24xx_write_optrom_data,
2231 .get_flash_version = qla24xx_get_flash_version,
e315cd28 2232 .start_scsi = qla24xx_start_scsi,
d7459527 2233 .start_scsi_mq = NULL,
a9083016 2234 .abort_isp = qla2x00_abort_isp,
7ec0effd 2235 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2236 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 2237};
2238
c3a2f0df
AV		 2239static struct isp_operations qla25xx_isp_ops = {
2240 .pci_config = qla25xx_pci_config,
2241 .reset_chip = qla24xx_reset_chip,
2242 .chip_diag = qla24xx_chip_diag,
2243 .config_rings = qla24xx_config_rings,
2244 .reset_adapter = qla24xx_reset_adapter,
2245 .nvram_config = qla24xx_nvram_config,
2246 .update_fw_options = qla24xx_update_fw_options,
2247 .load_risc = qla24xx_load_risc,
2248 .pci_info_str = qla24xx_pci_info_str,
2249 .fw_version_str = qla24xx_fw_version_str,
2250 .intr_handler = qla24xx_intr_handler,
2251 .enable_intrs = qla24xx_enable_intrs,
2252 .disable_intrs = qla24xx_disable_intrs,
2253 .abort_command = qla24xx_abort_command,
523ec773
AV		 2254 .target_reset = qla24xx_abort_target,
2255 .lun_reset = qla24xx_lun_reset,
c3a2f0df
AV		 2256 .fabric_login = qla24xx_login_fabric,
2257 .fabric_logout = qla24xx_fabric_logout,
2258 .calc_req_entries = NULL,
2259 .build_iocbs = NULL,
2260 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2261 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2262 .read_nvram = qla25xx_read_nvram_data,
2263 .write_nvram = qla25xx_write_nvram_data,
2264 .fw_dump = qla25xx_fw_dump,
2265 .beacon_on = qla24xx_beacon_on,
2266 .beacon_off = qla24xx_beacon_off,
2267 .beacon_blink = qla24xx_beacon_blink,
338c9161 2268 .read_optrom = qla25xx_read_optrom_data,
c3a2f0df
AV		 2269 .write_optrom = qla24xx_write_optrom_data,
2270 .get_flash_version = qla24xx_get_flash_version,
bad75002 2271 .start_scsi = qla24xx_dif_start_scsi,
d7459527 2272 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
a9083016 2273 .abort_isp = qla2x00_abort_isp,
7ec0effd 2274 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2275 .initialize_adapter = qla2x00_initialize_adapter,
c3a2f0df
AV		 2276};
2277
3a03eb79
AV		 2278static struct isp_operations qla81xx_isp_ops = {
2279 .pci_config = qla25xx_pci_config,
2280 .reset_chip = qla24xx_reset_chip,
2281 .chip_diag = qla24xx_chip_diag,
2282 .config_rings = qla24xx_config_rings,
2283 .reset_adapter = qla24xx_reset_adapter,
2284 .nvram_config = qla81xx_nvram_config,
2285 .update_fw_options = qla81xx_update_fw_options,
eaac30be 2286 .load_risc = qla81xx_load_risc,
3a03eb79
AV		 2287 .pci_info_str = qla24xx_pci_info_str,
2288 .fw_version_str = qla24xx_fw_version_str,
2289 .intr_handler = qla24xx_intr_handler,
2290 .enable_intrs = qla24xx_enable_intrs,
2291 .disable_intrs = qla24xx_disable_intrs,
2292 .abort_command = qla24xx_abort_command,
2293 .target_reset = qla24xx_abort_target,
2294 .lun_reset = qla24xx_lun_reset,
2295 .fabric_login = qla24xx_login_fabric,
2296 .fabric_logout = qla24xx_fabric_logout,
2297 .calc_req_entries = NULL,
2298 .build_iocbs = NULL,
2299 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2300 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
3d79038f
AV		 2301 .read_nvram = NULL,
2302 .write_nvram = NULL,
3a03eb79
AV		 2303 .fw_dump = qla81xx_fw_dump,
2304 .beacon_on = qla24xx_beacon_on,
2305 .beacon_off = qla24xx_beacon_off,
6246b8a1 2306 .beacon_blink = qla83xx_beacon_blink,
3a03eb79
AV		 2307 .read_optrom = qla25xx_read_optrom_data,
2308 .write_optrom = qla24xx_write_optrom_data,
2309 .get_flash_version = qla24xx_get_flash_version,
ba77ef53 2310 .start_scsi = qla24xx_dif_start_scsi,
d7459527 2311 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
a9083016 2312 .abort_isp = qla2x00_abort_isp,
7ec0effd 2313 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2314 .initialize_adapter = qla2x00_initialize_adapter,
a9083016
GM		 2315};
2316
2317static struct isp_operations qla82xx_isp_ops = {
2318 .pci_config = qla82xx_pci_config,
2319 .reset_chip = qla82xx_reset_chip,
2320 .chip_diag = qla24xx_chip_diag,
2321 .config_rings = qla82xx_config_rings,
2322 .reset_adapter = qla24xx_reset_adapter,
2323 .nvram_config = qla81xx_nvram_config,
2324 .update_fw_options = qla24xx_update_fw_options,
2325 .load_risc = qla82xx_load_risc,
9d55ca66 2326 .pci_info_str = qla24xx_pci_info_str,
a9083016
GM		 2327 .fw_version_str = qla24xx_fw_version_str,
2328 .intr_handler = qla82xx_intr_handler,
2329 .enable_intrs = qla82xx_enable_intrs,
2330 .disable_intrs = qla82xx_disable_intrs,
2331 .abort_command = qla24xx_abort_command,
2332 .target_reset = qla24xx_abort_target,
2333 .lun_reset = qla24xx_lun_reset,
2334 .fabric_login = qla24xx_login_fabric,
2335 .fabric_logout = qla24xx_fabric_logout,
2336 .calc_req_entries = NULL,
2337 .build_iocbs = NULL,
2338 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2339 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2340 .read_nvram = qla24xx_read_nvram_data,
2341 .write_nvram = qla24xx_write_nvram_data,
a1b23c5a 2342 .fw_dump = qla82xx_fw_dump,
999916dc
SK		 2343 .beacon_on = qla82xx_beacon_on,
2344 .beacon_off = qla82xx_beacon_off,
2345 .beacon_blink = NULL,
a9083016
GM		 2346 .read_optrom = qla82xx_read_optrom_data,
2347 .write_optrom = qla82xx_write_optrom_data,
7ec0effd 2348 .get_flash_version = qla82xx_get_flash_version,
a9083016 2349 .start_scsi = qla82xx_start_scsi,
d7459527 2350 .start_scsi_mq = NULL,
a9083016 2351 .abort_isp = qla82xx_abort_isp,
706f457d 2352 .iospace_config = qla82xx_iospace_config,
8ae6d9c7 2353 .initialize_adapter = qla2x00_initialize_adapter,
3a03eb79
AV		 2354};
2355
7ec0effd
AD		 2356static struct isp_operations qla8044_isp_ops = {
2357 .pci_config = qla82xx_pci_config,
2358 .reset_chip = qla82xx_reset_chip,
2359 .chip_diag = qla24xx_chip_diag,
2360 .config_rings = qla82xx_config_rings,
2361 .reset_adapter = qla24xx_reset_adapter,
2362 .nvram_config = qla81xx_nvram_config,
2363 .update_fw_options = qla24xx_update_fw_options,
2364 .load_risc = qla82xx_load_risc,
2365 .pci_info_str = qla24xx_pci_info_str,
2366 .fw_version_str = qla24xx_fw_version_str,
2367 .intr_handler = qla8044_intr_handler,
2368 .enable_intrs = qla82xx_enable_intrs,
2369 .disable_intrs = qla82xx_disable_intrs,
2370 .abort_command = qla24xx_abort_command,
2371 .target_reset = qla24xx_abort_target,
2372 .lun_reset = qla24xx_lun_reset,
2373 .fabric_login = qla24xx_login_fabric,
2374 .fabric_logout = qla24xx_fabric_logout,
2375 .calc_req_entries = NULL,
2376 .build_iocbs = NULL,
2377 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2378 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2379 .read_nvram = NULL,
2380 .write_nvram = NULL,
a1b23c5a 2381 .fw_dump = qla8044_fw_dump,
7ec0effd
AD		 2382 .beacon_on = qla82xx_beacon_on,
2383 .beacon_off = qla82xx_beacon_off,
2384 .beacon_blink = NULL,
888e639d 2385 .read_optrom = qla8044_read_optrom_data,
7ec0effd
AD		 2386 .write_optrom = qla8044_write_optrom_data,
2387 .get_flash_version = qla82xx_get_flash_version,
2388 .start_scsi = qla82xx_start_scsi,
d7459527 2389 .start_scsi_mq = NULL,
7ec0effd
AD		 2390 .abort_isp = qla8044_abort_isp,
2391 .iospace_config = qla82xx_iospace_config,
2392 .initialize_adapter = qla2x00_initialize_adapter,
2393};
2394
6246b8a1
GM		 2395static struct isp_operations qla83xx_isp_ops = {
2396 .pci_config = qla25xx_pci_config,
2397 .reset_chip = qla24xx_reset_chip,
2398 .chip_diag = qla24xx_chip_diag,
2399 .config_rings = qla24xx_config_rings,
2400 .reset_adapter = qla24xx_reset_adapter,
2401 .nvram_config = qla81xx_nvram_config,
2402 .update_fw_options = qla81xx_update_fw_options,
2403 .load_risc = qla81xx_load_risc,
2404 .pci_info_str = qla24xx_pci_info_str,
2405 .fw_version_str = qla24xx_fw_version_str,
2406 .intr_handler = qla24xx_intr_handler,
2407 .enable_intrs = qla24xx_enable_intrs,
2408 .disable_intrs = qla24xx_disable_intrs,
2409 .abort_command = qla24xx_abort_command,
2410 .target_reset = qla24xx_abort_target,
2411 .lun_reset = qla24xx_lun_reset,
2412 .fabric_login = qla24xx_login_fabric,
2413 .fabric_logout = qla24xx_fabric_logout,
2414 .calc_req_entries = NULL,
2415 .build_iocbs = NULL,
2416 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2417 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2418 .read_nvram = NULL,
2419 .write_nvram = NULL,
2420 .fw_dump = qla83xx_fw_dump,
2421 .beacon_on = qla24xx_beacon_on,
2422 .beacon_off = qla24xx_beacon_off,
2423 .beacon_blink = qla83xx_beacon_blink,
2424 .read_optrom = qla25xx_read_optrom_data,
2425 .write_optrom = qla24xx_write_optrom_data,
2426 .get_flash_version = qla24xx_get_flash_version,
2427 .start_scsi = qla24xx_dif_start_scsi,
d7459527 2428 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
6246b8a1
GM		 2429 .abort_isp = qla2x00_abort_isp,
2430 .iospace_config = qla83xx_iospace_config,
8ae6d9c7
GM		 2431 .initialize_adapter = qla2x00_initialize_adapter,
2432};
2433
2434static struct isp_operations qlafx00_isp_ops = {
2435 .pci_config = qlafx00_pci_config,
2436 .reset_chip = qlafx00_soft_reset,
2437 .chip_diag = qlafx00_chip_diag,
2438 .config_rings = qlafx00_config_rings,
2439 .reset_adapter = qlafx00_soft_reset,
2440 .nvram_config = NULL,
2441 .update_fw_options = NULL,
2442 .load_risc = NULL,
2443 .pci_info_str = qlafx00_pci_info_str,
2444 .fw_version_str = qlafx00_fw_version_str,
2445 .intr_handler = qlafx00_intr_handler,
2446 .enable_intrs = qlafx00_enable_intrs,
2447 .disable_intrs = qlafx00_disable_intrs,
4440e46d 2448 .abort_command = qla24xx_async_abort_command,
8ae6d9c7
GM		 2449 .target_reset = qlafx00_abort_target,
2450 .lun_reset = qlafx00_lun_reset,
2451 .fabric_login = NULL,
2452 .fabric_logout = NULL,
2453 .calc_req_entries = NULL,
2454 .build_iocbs = NULL,
2455 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2456 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2457 .read_nvram = qla24xx_read_nvram_data,
2458 .write_nvram = qla24xx_write_nvram_data,
2459 .fw_dump = NULL,
2460 .beacon_on = qla24xx_beacon_on,
2461 .beacon_off = qla24xx_beacon_off,
2462 .beacon_blink = NULL,
2463 .read_optrom = qla24xx_read_optrom_data,
2464 .write_optrom = qla24xx_write_optrom_data,
2465 .get_flash_version = qla24xx_get_flash_version,
2466 .start_scsi = qlafx00_start_scsi,
d7459527 2467 .start_scsi_mq = NULL,
8ae6d9c7
GM		 2468 .abort_isp = qlafx00_abort_isp,
2469 .iospace_config = qlafx00_iospace_config,
2470 .initialize_adapter = qlafx00_initialize_adapter,
6246b8a1
GM		 2471};
2472
f73cb695
CD		 2473static struct isp_operations qla27xx_isp_ops = {
2474 .pci_config = qla25xx_pci_config,
2475 .reset_chip = qla24xx_reset_chip,
2476 .chip_diag = qla24xx_chip_diag,
2477 .config_rings = qla24xx_config_rings,
2478 .reset_adapter = qla24xx_reset_adapter,
2479 .nvram_config = qla81xx_nvram_config,
2480 .update_fw_options = qla81xx_update_fw_options,
2481 .load_risc = qla81xx_load_risc,
2482 .pci_info_str = qla24xx_pci_info_str,
2483 .fw_version_str = qla24xx_fw_version_str,
2484 .intr_handler = qla24xx_intr_handler,
2485 .enable_intrs = qla24xx_enable_intrs,
2486 .disable_intrs = qla24xx_disable_intrs,
2487 .abort_command = qla24xx_abort_command,
2488 .target_reset = qla24xx_abort_target,
2489 .lun_reset = qla24xx_lun_reset,
2490 .fabric_login = qla24xx_login_fabric,
2491 .fabric_logout = qla24xx_fabric_logout,
2492 .calc_req_entries = NULL,
2493 .build_iocbs = NULL,
2494 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2495 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2496 .read_nvram = NULL,
2497 .write_nvram = NULL,
2498 .fw_dump = qla27xx_fwdump,
2499 .beacon_on = qla24xx_beacon_on,
2500 .beacon_off = qla24xx_beacon_off,
2501 .beacon_blink = qla83xx_beacon_blink,
2502 .read_optrom = qla25xx_read_optrom_data,
2503 .write_optrom = qla24xx_write_optrom_data,
2504 .get_flash_version = qla24xx_get_flash_version,
2505 .start_scsi = qla24xx_dif_start_scsi,
d7459527 2506 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
f73cb695
CD		 2507 .abort_isp = qla2x00_abort_isp,
2508 .iospace_config = qla83xx_iospace_config,
2509 .initialize_adapter = qla2x00_initialize_adapter,
2510};
2511
ea5b6382 2512static inline void
e315cd28 2513qla2x00_set_isp_flags(struct qla_hw_data *ha)
ea5b6382 2514{
2515 ha->device_type = DT_EXTENDED_IDS;
2516 switch (ha->pdev->device) {
2517 case PCI_DEVICE_ID_QLOGIC_ISP2100:
9e052e2d 2518 ha->isp_type |= DT_ISP2100;
ea5b6382 2519 ha->device_type &= ~DT_EXTENDED_IDS;
441d1072 2520 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
ea5b6382 2521 break;
2522 case PCI_DEVICE_ID_QLOGIC_ISP2200:
9e052e2d 2523 ha->isp_type |= DT_ISP2200;
ea5b6382 2524 ha->device_type &= ~DT_EXTENDED_IDS;
441d1072 2525 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
ea5b6382 2526 break;
2527 case PCI_DEVICE_ID_QLOGIC_ISP2300:
9e052e2d 2528 ha->isp_type |= DT_ISP2300;
4a59f71d 2529 ha->device_type |= DT_ZIO_SUPPORTED;
441d1072 2530 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 2531 break;
2532 case PCI_DEVICE_ID_QLOGIC_ISP2312:
9e052e2d 2533 ha->isp_type |= DT_ISP2312;
4a59f71d 2534 ha->device_type |= DT_ZIO_SUPPORTED;
441d1072 2535 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 2536 break;
2537 case PCI_DEVICE_ID_QLOGIC_ISP2322:
9e052e2d 2538 ha->isp_type |= DT_ISP2322;
4a59f71d 2539 ha->device_type |= DT_ZIO_SUPPORTED;
ea5b6382 2540 if (ha->pdev->subsystem_vendor == 0x1028 &&
2541 ha->pdev->subsystem_device == 0x0170)
2542 ha->device_type |= DT_OEM_001;
441d1072 2543 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 2544 break;
2545 case PCI_DEVICE_ID_QLOGIC_ISP6312:
9e052e2d 2546 ha->isp_type |= DT_ISP6312;
441d1072 2547 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 2548 break;
2549 case PCI_DEVICE_ID_QLOGIC_ISP6322:
9e052e2d 2550 ha->isp_type |= DT_ISP6322;
441d1072 2551 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 2552 break;
2553 case PCI_DEVICE_ID_QLOGIC_ISP2422:
9e052e2d 2554 ha->isp_type |= DT_ISP2422;
4a59f71d 2555 ha->device_type |= DT_ZIO_SUPPORTED;
e428924c 2556 ha->device_type |= DT_FWI2;
c76f2c01 2557 ha->device_type |= DT_IIDMA;
441d1072 2558 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2559 break;
2560 case PCI_DEVICE_ID_QLOGIC_ISP2432:
9e052e2d 2561 ha->isp_type |= DT_ISP2432;
4a59f71d 2562 ha->device_type |= DT_ZIO_SUPPORTED;
e428924c 2563 ha->device_type |= DT_FWI2;
c76f2c01 2564 ha->device_type |= DT_IIDMA;
441d1072 2565 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2566 break;
4d4df193 2567 case PCI_DEVICE_ID_QLOGIC_ISP8432:
9e052e2d 2568 ha->isp_type |= DT_ISP8432;
4d4df193
HK		 2569 ha->device_type |= DT_ZIO_SUPPORTED;
2570 ha->device_type |= DT_FWI2;
2571 ha->device_type |= DT_IIDMA;
2572 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2573 break;
044cc6c8 2574 case PCI_DEVICE_ID_QLOGIC_ISP5422:
9e052e2d 2575 ha->isp_type |= DT_ISP5422;
e428924c 2576 ha->device_type |= DT_FWI2;
441d1072 2577 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2578 break;
044cc6c8 2579 case PCI_DEVICE_ID_QLOGIC_ISP5432:
9e052e2d 2580 ha->isp_type |= DT_ISP5432;
e428924c 2581 ha->device_type |= DT_FWI2;
441d1072 2582 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2583 break;
c3a2f0df 2584 case PCI_DEVICE_ID_QLOGIC_ISP2532:
9e052e2d 2585 ha->isp_type |= DT_ISP2532;
c3a2f0df
AV		 2586 ha->device_type |= DT_ZIO_SUPPORTED;
2587 ha->device_type |= DT_FWI2;
2588 ha->device_type |= DT_IIDMA;
441d1072 2589 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2590 break;
3a03eb79 2591 case PCI_DEVICE_ID_QLOGIC_ISP8001:
9e052e2d 2592 ha->isp_type |= DT_ISP8001;
3a03eb79
AV		 2593 ha->device_type |= DT_ZIO_SUPPORTED;
2594 ha->device_type |= DT_FWI2;
2595 ha->device_type |= DT_IIDMA;
2596 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2597 break;
a9083016 2598 case PCI_DEVICE_ID_QLOGIC_ISP8021:
9e052e2d 2599 ha->isp_type |= DT_ISP8021;
a9083016
GM		 2600 ha->device_type |= DT_ZIO_SUPPORTED;
2601 ha->device_type |= DT_FWI2;
2602 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2603 /* Initialize 82XX ISP flags */
2604 qla82xx_init_flags(ha);
2605 break;
7ec0effd 2606 case PCI_DEVICE_ID_QLOGIC_ISP8044:
9e052e2d 2607 ha->isp_type |= DT_ISP8044;
7ec0effd
AD		 2608 ha->device_type |= DT_ZIO_SUPPORTED;
2609 ha->device_type |= DT_FWI2;
2610 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2611 /* Initialize 82XX ISP flags */
2612 qla82xx_init_flags(ha);
2613 break;
6246b8a1 2614 case PCI_DEVICE_ID_QLOGIC_ISP2031:
9e052e2d 2615 ha->isp_type |= DT_ISP2031;
6246b8a1
GM		 2616 ha->device_type |= DT_ZIO_SUPPORTED;
2617 ha->device_type |= DT_FWI2;
2618 ha->device_type |= DT_IIDMA;
2619 ha->device_type |= DT_T10_PI;
2620 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2621 break;
2622 case PCI_DEVICE_ID_QLOGIC_ISP8031:
9e052e2d 2623 ha->isp_type |= DT_ISP8031;
6246b8a1
GM		 2624 ha->device_type |= DT_ZIO_SUPPORTED;
2625 ha->device_type |= DT_FWI2;
2626 ha->device_type |= DT_IIDMA;
2627 ha->device_type |= DT_T10_PI;
2628 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2629 break;
8ae6d9c7 2630 case PCI_DEVICE_ID_QLOGIC_ISPF001:
9e052e2d 2631 ha->isp_type |= DT_ISPFX00;
8ae6d9c7 2632 break;
f73cb695 2633 case PCI_DEVICE_ID_QLOGIC_ISP2071:
9e052e2d 2634 ha->isp_type |= DT_ISP2071;
f73cb695
CD		 2635 ha->device_type |= DT_ZIO_SUPPORTED;
2636 ha->device_type |= DT_FWI2;
2637 ha->device_type |= DT_IIDMA;
8ce3f570 2638 ha->device_type |= DT_T10_PI;
f73cb695
CD		 2639 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2640 break;
2c5bbbb2 2641 case PCI_DEVICE_ID_QLOGIC_ISP2271:
9e052e2d 2642 ha->isp_type |= DT_ISP2271;
2c5bbbb2
JC		 2643 ha->device_type |= DT_ZIO_SUPPORTED;
2644 ha->device_type |= DT_FWI2;
2645 ha->device_type |= DT_IIDMA;
8ce3f570 2646 ha->device_type |= DT_T10_PI;
2c5bbbb2
JC		 2647 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2648 break;
2b48992f 2649 case PCI_DEVICE_ID_QLOGIC_ISP2261:
9e052e2d 2650 ha->isp_type |= DT_ISP2261;
2b48992f
SC		 2651 ha->device_type |= DT_ZIO_SUPPORTED;
2652 ha->device_type |= DT_FWI2;
2653 ha->device_type |= DT_IIDMA;
8ce3f570 2654 ha->device_type |= DT_T10_PI;
2b48992f
SC		 2655 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2656 break;
ea5b6382 2657 }
e5b68a61 2658
a9083016 2659 if (IS_QLA82XX(ha))
43a9c38b 2660 ha->port_no = ha->portnum & 1;
f73cb695 2661 else {
a9083016
GM		 2662 /* Get adapter physical port no from interrupt pin register. */
2663 pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no);
f73cb695
CD		 2664 if (IS_QLA27XX(ha))
2665 ha->port_no--;
2666 else
2667 ha->port_no = !(ha->port_no & 1);
2668 }
a9083016 2669
7c3df132 2670 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b,
d8424f68 2671 "device_type=0x%x port=%d fw_srisc_address=0x%x.\n",
f73cb695 2672 ha->device_type, ha->port_no, ha->fw_srisc_address);
ea5b6382 2673}
2674
1e99e33a
AV		 2675static void
2676qla2xxx_scan_start(struct Scsi_Host *shost)
2677{
e315cd28 2678 scsi_qla_host_t *vha = shost_priv(shost);
1e99e33a 2679
cbc8eb67
AV		 2680 if (vha->hw->flags.running_gold_fw)
2681 return;
2682
e315cd28
AC		 2683 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
2684 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
2685 set_bit(RSCN_UPDATE, &vha->dpc_flags);
2686 set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags);
1e99e33a
AV		 2687}
2688
2689static int
2690qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time)
2691{
e315cd28 2692 scsi_qla_host_t *vha = shost_priv(shost);
1e99e33a 2693
a5dd506e
BK		 2694 if (test_bit(UNLOADING, &vha->dpc_flags))
2695 return 1;
e315cd28 2696 if (!vha->host)
1e99e33a 2697 return 1;
e315cd28 2698 if (time > vha->hw->loop_reset_delay * HZ)
1e99e33a
AV		 2699 return 1;
2700
e315cd28 2701 return atomic_read(&vha->loop_state) == LOOP_READY;
1e99e33a
AV		 2702}
2703
ec7193e2
QT		 2704static void qla2x00_iocb_work_fn(struct work_struct *work)
2705{
2706 struct scsi_qla_host *vha = container_of(work,
2707 struct scsi_qla_host, iocb_work);
9b3e0f4d
QT		 2708 struct qla_hw_data *ha = vha->hw;
2709 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
2710 int i = 20;
2711 unsigned long flags;
2712
2713 if (test_bit(UNLOADING, &base_vha->dpc_flags))
2714 return;
ec7193e2 2715
9b3e0f4d 2716 while (!list_empty(&vha->work_list) && i > 0) {
ec7193e2 2717 qla2x00_do_work(vha);
9b3e0f4d 2718 i--;
ec7193e2 2719 }
9b3e0f4d
QT		 2720
2721 spin_lock_irqsave(&vha->work_lock, flags);
2722 clear_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags);
2723 spin_unlock_irqrestore(&vha->work_lock, flags);
ec7193e2
QT		 2724}
2725
1da177e4
LT		 2726/*
2727 * PCI driver interface
2728 */
6f039790 2729static int
7ee61397 2730qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
1da177e4 2731{
a1541d5a 2732 int ret = -ENODEV;
1da177e4 2733 struct Scsi_Host *host;
e315cd28
AC		 2734 scsi_qla_host_t *base_vha = NULL;
2735 struct qla_hw_data *ha;
29856e28 2736 char pci_info[30];
7d613ac6 2737 char fw_str[30], wq_name[30];
5433383e 2738 struct scsi_host_template *sht;
642ef983 2739 int bars, mem_only = 0;
e315cd28 2740 uint16_t req_length = 0, rsp_length = 0;
73208dfd
AC		 2741 struct req_que *req = NULL;
2742 struct rsp_que *rsp = NULL;
5601236b 2743 int i;
d7459527 2744
285d0321 2745 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO);
a5326f86 2746 sht = &qla2xxx_driver_template;
5433383e 2747 if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 ||
8bc69e7d 2748 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 ||
4d4df193 2749 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 ||
8bc69e7d 2750 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 ||
c3a2f0df 2751 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 ||
3a03eb79 2752 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 ||
a9083016 2753 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 ||
6246b8a1
GM		 2754 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021 ||
2755 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2031 ||
8ae6d9c7 2756 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8031 ||
7ec0effd 2757 pdev->device == PCI_DEVICE_ID_QLOGIC_ISPF001 ||
f73cb695 2758 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8044 ||
2c5bbbb2 2759 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2071 ||
2b48992f
SC		 2760 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2271 ||
2761 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2261) {
285d0321 2762 bars = pci_select_bars(pdev, IORESOURCE_MEM);
09483916 2763 mem_only = 1;
7c3df132
SK		 2764 ql_dbg_pci(ql_dbg_init, pdev, 0x0007,
2765 "Mem only adapter.\n");
285d0321 2766 }
7c3df132
SK		 2767 ql_dbg_pci(ql_dbg_init, pdev, 0x0008,
2768 "Bars=%d.\n", bars);
285d0321 2769
09483916
BH		 2770 if (mem_only) {
2771 if (pci_enable_device_mem(pdev))
ddff7ed4 2772 return ret;
09483916
BH		 2773 } else {
2774 if (pci_enable_device(pdev))
ddff7ed4 2775 return ret;
09483916 2776 }
285d0321 2777
0927678f
JB		 2778 /* This may fail but that's ok */
2779 pci_enable_pcie_error_reporting(pdev);
285d0321 2780
e315cd28
AC		 2781 ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL);
2782 if (!ha) {
7c3df132
SK		 2783 ql_log_pci(ql_log_fatal, pdev, 0x0009,
2784 "Unable to allocate memory for ha.\n");
ddff7ed4 2785 goto disable_device;
1da177e4 2786 }
7c3df132
SK		 2787 ql_dbg_pci(ql_dbg_init, pdev, 0x000a,
2788 "Memory allocated for ha=%p.\n", ha);
e315cd28 2789 ha->pdev = pdev;
33e79977
QT		 2790 INIT_LIST_HEAD(&ha->tgt.q_full_list);
2791 spin_lock_init(&ha->tgt.q_full_lock);
7560151b 2792 spin_lock_init(&ha->tgt.sess_lock);
2f424b9b
QT		 2793 spin_lock_init(&ha->tgt.atio_lock);
2794
deeae7a6 2795 atomic_set(&ha->nvme_active_aen_cnt, 0);
1da177e4
LT		 2796
2797 /* Clear our data area */
285d0321 2798 ha->bars = bars;
09483916 2799 ha->mem_only = mem_only;
df4bf0bb 2800 spin_lock_init(&ha->hardware_lock);
339aa70e 2801 spin_lock_init(&ha->vport_slock);
a9b6f722 2802 mutex_init(&ha->selflogin_lock);
7a8ab9c8 2803 mutex_init(&ha->optrom_mutex);
1da177e4 2804
ea5b6382 2805 /* Set ISP-type information. */
2806 qla2x00_set_isp_flags(ha);
ca79cf66
DG		 2807
2808 /* Set EEH reset type to fundamental if required by hba */
95676112 2809 if (IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha) ||
f73cb695 2810 IS_QLA83XX(ha) || IS_QLA27XX(ha))
ca79cf66 2811 pdev->needs_freset = 1;
ca79cf66 2812
cba1e47f
CD		 2813 ha->prev_topology = 0;
2814 ha->init_cb_size = sizeof(init_cb_t);
2815 ha->link_data_rate = PORT_SPEED_UNKNOWN;
2816 ha->optrom_size = OPTROM_SIZE_2300;
d1e3635a 2817 ha->max_exchg = FW_MAX_EXCHANGES_CNT;
b2000805
QT		 2818 atomic_set(&ha->num_pend_mbx_stage1, 0);
2819 atomic_set(&ha->num_pend_mbx_stage2, 0);
2820 atomic_set(&ha->num_pend_mbx_stage3, 0);
cba1e47f 2821
abbd8870 2822 /* Assign ISP specific operations. */
1da177e4 2823 if (IS_QLA2100(ha)) {
642ef983 2824 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
1da177e4 2825 ha->mbx_count = MAILBOX_REGISTER_COUNT_2100;
e315cd28
AC		 2826 req_length = REQUEST_ENTRY_CNT_2100;
2827 rsp_length = RESPONSE_ENTRY_CNT_2100;
2828 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
abbd8870 2829 ha->gid_list_info_size = 4;
3a03eb79
AV		 2830 ha->flash_conf_off = ~0;
2831 ha->flash_data_off = ~0;
2832 ha->nvram_conf_off = ~0;
2833 ha->nvram_data_off = ~0;
fd34f556 2834 ha->isp_ops = &qla2100_isp_ops;
1da177e4 2835 } else if (IS_QLA2200(ha)) {
642ef983 2836 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
67ddda35 2837 ha->mbx_count = MAILBOX_REGISTER_COUNT_2200;
e315cd28
AC		 2838 req_length = REQUEST_ENTRY_CNT_2200;
2839 rsp_length = RESPONSE_ENTRY_CNT_2100;
2840 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
abbd8870 2841 ha->gid_list_info_size = 4;
3a03eb79
AV		 2842 ha->flash_conf_off = ~0;
2843 ha->flash_data_off = ~0;
2844 ha->nvram_conf_off = ~0;
2845 ha->nvram_data_off = ~0;
fd34f556 2846 ha->isp_ops = &qla2100_isp_ops;
fca29703 2847 } else if (IS_QLA23XX(ha)) {
642ef983 2848 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
1da177e4 2849 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2850 req_length = REQUEST_ENTRY_CNT_2200;
2851 rsp_length = RESPONSE_ENTRY_CNT_2300;
2852 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
abbd8870 2853 ha->gid_list_info_size = 6;
854165f4 2854 if (IS_QLA2322(ha) || IS_QLA6322(ha))
2855 ha->optrom_size = OPTROM_SIZE_2322;
3a03eb79
AV		 2856 ha->flash_conf_off = ~0;
2857 ha->flash_data_off = ~0;
2858 ha->nvram_conf_off = ~0;
2859 ha->nvram_data_off = ~0;
fd34f556 2860 ha->isp_ops = &qla2300_isp_ops;
4d4df193 2861 } else if (IS_QLA24XX_TYPE(ha)) {
642ef983 2862 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
fca29703 2863 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2864 req_length = REQUEST_ENTRY_CNT_24XX;
2865 rsp_length = RESPONSE_ENTRY_CNT_2300;
2d70c103 2866 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
e315cd28 2867 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2c3dfe3f 2868 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
fca29703 2869 ha->gid_list_info_size = 8;
854165f4 2870 ha->optrom_size = OPTROM_SIZE_24XX;
73208dfd 2871 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX;
fd34f556 2872 ha->isp_ops = &qla24xx_isp_ops;
3a03eb79
AV		 2873 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2874 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2875 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2876 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
c3a2f0df 2877 } else if (IS_QLA25XX(ha)) {
642ef983 2878 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
c3a2f0df 2879 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2880 req_length = REQUEST_ENTRY_CNT_24XX;
2881 rsp_length = RESPONSE_ENTRY_CNT_2300;
2d70c103 2882 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
e315cd28 2883 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
c3a2f0df 2884 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
c3a2f0df
AV		 2885 ha->gid_list_info_size = 8;
2886 ha->optrom_size = OPTROM_SIZE_25XX;
73208dfd 2887 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
c3a2f0df 2888 ha->isp_ops = &qla25xx_isp_ops;
3a03eb79
AV		 2889 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2890 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2891 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2892 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
2893 } else if (IS_QLA81XX(ha)) {
642ef983 2894 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3a03eb79
AV		 2895 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2896 req_length = REQUEST_ENTRY_CNT_24XX;
2897 rsp_length = RESPONSE_ENTRY_CNT_2300;
aa230bc5 2898 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
3a03eb79
AV		 2899 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2900 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2901 ha->gid_list_info_size = 8;
2902 ha->optrom_size = OPTROM_SIZE_81XX;
40859ae5 2903 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3a03eb79
AV		 2904 ha->isp_ops = &qla81xx_isp_ops;
2905 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2906 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2907 ha->nvram_conf_off = ~0;
2908 ha->nvram_data_off = ~0;
a9083016 2909 } else if (IS_QLA82XX(ha)) {
642ef983 2910 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
a9083016
GM		 2911 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2912 req_length = REQUEST_ENTRY_CNT_82XX;
2913 rsp_length = RESPONSE_ENTRY_CNT_82XX;
2914 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2915 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2916 ha->gid_list_info_size = 8;
2917 ha->optrom_size = OPTROM_SIZE_82XX;
087c621e 2918 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
a9083016
GM		 2919 ha->isp_ops = &qla82xx_isp_ops;
2920 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2921 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2922 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2923 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
7ec0effd
AD		 2924 } else if (IS_QLA8044(ha)) {
2925 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2926 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2927 req_length = REQUEST_ENTRY_CNT_82XX;
2928 rsp_length = RESPONSE_ENTRY_CNT_82XX;
2929 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2930 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2931 ha->gid_list_info_size = 8;
2932 ha->optrom_size = OPTROM_SIZE_83XX;
2933 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2934 ha->isp_ops = &qla8044_isp_ops;
2935 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2936 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2937 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2938 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
6246b8a1 2939 } else if (IS_QLA83XX(ha)) {
7d613ac6 2940 ha->portnum = PCI_FUNC(ha->pdev->devfn);
642ef983 2941 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
6246b8a1 2942 ha->mbx_count = MAILBOX_REGISTER_COUNT;
f2ea653f 2943 req_length = REQUEST_ENTRY_CNT_83XX;
e7b42e33 2944 rsp_length = RESPONSE_ENTRY_CNT_83XX;
b8aa4bdf 2945 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
6246b8a1
GM		 2946 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2947 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2948 ha->gid_list_info_size = 8;
2949 ha->optrom_size = OPTROM_SIZE_83XX;
2950 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2951 ha->isp_ops = &qla83xx_isp_ops;
2952 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2953 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2954 ha->nvram_conf_off = ~0;
2955 ha->nvram_data_off = ~0;
8ae6d9c7
GM		 2956 } else if (IS_QLAFX00(ha)) {
2957 ha->max_fibre_devices = MAX_FIBRE_DEVICES_FX00;
2958 ha->mbx_count = MAILBOX_REGISTER_COUNT_FX00;
2959 ha->aen_mbx_count = AEN_MAILBOX_REGISTER_COUNT_FX00;
2960 req_length = REQUEST_ENTRY_CNT_FX00;
2961 rsp_length = RESPONSE_ENTRY_CNT_FX00;
8ae6d9c7
GM		 2962 ha->isp_ops = &qlafx00_isp_ops;
2963 ha->port_down_retry_count = 30; /* default value */
2964 ha->mr.fw_hbt_cnt = QLAFX00_HEARTBEAT_INTERVAL;
2965 ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL;
71e56003 2966 ha->mr.fw_critemp_timer_tick = QLAFX00_CRITEMP_INTERVAL;
8ae6d9c7 2967 ha->mr.fw_hbt_en = 1;
e8f5e95d
AB		 2968 ha->mr.host_info_resend = false;
2969 ha->mr.hinfo_resend_timer_tick = QLAFX00_HINFO_RESEND_INTERVAL;
f73cb695
CD		 2970 } else if (IS_QLA27XX(ha)) {
2971 ha->portnum = PCI_FUNC(ha->pdev->devfn);
2972 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2973 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e7b42e33
QT		 2974 req_length = REQUEST_ENTRY_CNT_83XX;
2975 rsp_length = RESPONSE_ENTRY_CNT_83XX;
b20f02e1 2976 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
f73cb695
CD		 2977 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2978 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2979 ha->gid_list_info_size = 8;
2980 ha->optrom_size = OPTROM_SIZE_83XX;
2981 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2982 ha->isp_ops = &qla27xx_isp_ops;
2983 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2984 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2985 ha->nvram_conf_off = ~0;
2986 ha->nvram_data_off = ~0;
1da177e4 2987 }
6246b8a1 2988
7c3df132
SK		 2989 ql_dbg_pci(ql_dbg_init, pdev, 0x001e,
2990 "mbx_count=%d, req_length=%d, "
2991 "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, "
642ef983
CD		 2992 "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, "
2993 "max_fibre_devices=%d.\n",
7c3df132
SK		 2994 ha->mbx_count, req_length, rsp_length, ha->max_loop_id,
2995 ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size,
642ef983 2996 ha->nvram_npiv_size, ha->max_fibre_devices);
7c3df132
SK		 2997 ql_dbg_pci(ql_dbg_init, pdev, 0x001f,
2998 "isp_ops=%p, flash_conf_off=%d, "
2999 "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n",
3000 ha->isp_ops, ha->flash_conf_off, ha->flash_data_off,
3001 ha->nvram_conf_off, ha->nvram_data_off);
706f457d
GM		 3002
3003 /* Configure PCI I/O space */
3004 ret = ha->isp_ops->iospace_config(ha);
3005 if (ret)
0a63ad12 3006 goto iospace_config_failed;
706f457d
GM		 3007
3008 ql_log_pci(ql_log_info, pdev, 0x001d,
3009 "Found an ISP%04X irq %d iobase 0x%p.\n",
3010 pdev->device, pdev->irq, ha->iobase);
6c2f527c 3011 mutex_init(&ha->vport_lock);
d7459527 3012 mutex_init(&ha->mq_lock);
0b05a1f0
MB		 3013 init_completion(&ha->mbx_cmd_comp);
3014 complete(&ha->mbx_cmd_comp);
3015 init_completion(&ha->mbx_intr_comp);
23f2ebd1 3016 init_completion(&ha->dcbx_comp);
f356bef1 3017 init_completion(&ha->lb_portup_comp);
1da177e4 3018
2c3dfe3f 3019 set_bit(0, (unsigned long *) ha->vp_idx_map);
1da177e4 3020
53303c42 3021 qla2x00_config_dma_addressing(ha);
7c3df132
SK		 3022 ql_dbg_pci(ql_dbg_init, pdev, 0x0020,
3023 "64 Bit addressing is %s.\n",
3024 ha->flags.enable_64bit_addressing ? "enable" :
3025 "disable");
73208dfd 3026 ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp);
b2a72ec3 3027 if (ret) {
7c3df132
SK		 3028 ql_log_pci(ql_log_fatal, pdev, 0x0031,
3029 "Failed to allocate memory for adapter, aborting.\n");
1da177e4 3030
e315cd28
AC		 3031 goto probe_hw_failed;
3032 }
3033
73208dfd 3034 req->max_q_depth = MAX_Q_DEPTH;
e315cd28 3035 if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU)
73208dfd
AC		 3036 req->max_q_depth = ql2xmaxqdepth;
3037
e315cd28
AC		 3038
3039 base_vha = qla2x00_create_host(sht, ha);
3040 if (!base_vha) {
a1541d5a 3041 ret = -ENOMEM;
e315cd28 3042 goto probe_hw_failed;
1da177e4
LT		 3043 }
3044
e315cd28 3045 pci_set_drvdata(pdev, base_vha);
6b383979 3046 set_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags);
e315cd28 3047
e315cd28 3048 host = base_vha->host;
2afa19a9 3049 base_vha->req = req;
73208dfd 3050 if (IS_QLA2XXX_MIDTYPE(ha))
1429f044 3051 base_vha->mgmt_svr_loop_id = NPH_MGMT_SERVER;
73208dfd 3052 else
e315cd28
AC		 3053 base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER +
3054 base_vha->vp_idx;
58548cb5 3055
8ae6d9c7
GM		 3056 /* Setup fcport template structure. */
3057 ha->mr.fcport.vha = base_vha;
3058 ha->mr.fcport.port_type = FCT_UNKNOWN;
3059 ha->mr.fcport.loop_id = FC_NO_LOOP_ID;
3060 qla2x00_set_fcport_state(&ha->mr.fcport, FCS_UNCONFIGURED);
3061 ha->mr.fcport.supported_classes = FC_COS_UNSPECIFIED;
3062 ha->mr.fcport.scan_state = 1;
3063
58548cb5
GM		 3064 /* Set the SG table size based on ISP type */
3065 if (!IS_FWI2_CAPABLE(ha)) {
3066 if (IS_QLA2100(ha))
3067 host->sg_tablesize = 32;
3068 } else {
3069 if (!IS_QLA82XX(ha))
3070 host->sg_tablesize = QLA_SG_ALL;
3071 }
642ef983 3072 host->max_id = ha->max_fibre_devices;
e315cd28
AC		 3073 host->cmd_per_lun = 3;
3074 host->unique_id = host->host_no;
e02587d7 3075 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif)
0c470874
AE		 3076 host->max_cmd_len = 32;
3077 else
3078 host->max_cmd_len = MAX_CMDSZ;
e315cd28 3079 host->max_channel = MAX_BUSES - 1;
755f516b
HR		 3080 /* Older HBAs support only 16-bit LUNs */
3081 if (!IS_QLAFX00(ha) && !IS_FWI2_CAPABLE(ha) &&
3082 ql2xmaxlun > 0xffff)
3083 host->max_lun = 0xffff;
3084 else
3085 host->max_lun = ql2xmaxlun;
e315cd28 3086 host->transportt = qla2xxx_transport_template;
9a069e19 3087 sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC);
e315cd28 3088
7c3df132
SK		 3089 ql_dbg(ql_dbg_init, base_vha, 0x0033,
3090 "max_id=%d this_id=%d "
3091 "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d "
1abf635d 3092 "max_lun=%llu transportt=%p, vendor_id=%llu.\n", host->max_id,
7c3df132
SK		 3093 host->this_id, host->cmd_per_lun, host->unique_id,
3094 host->max_cmd_len, host->max_channel, host->max_lun,
3095 host->transportt, sht->vendor_id);
3096
1010f21e
HM		 3097 INIT_WORK(&base_vha->iocb_work, qla2x00_iocb_work_fn);
3098
d7459527
MH		 3099 /* Set up the irqs */
3100 ret = qla2x00_request_irqs(ha, rsp);
3101 if (ret)
6a2cf8d3 3102 goto probe_failed;
d7459527 3103
9a347ff4 3104 /* Alloc arrays of request and response ring ptrs */
6d634067
BK		 3105 ret = qla2x00_alloc_queues(ha, req, rsp);
3106 if (ret) {
9a347ff4
CD		 3107 ql_log(ql_log_fatal, base_vha, 0x003d,
3108 "Failed to allocate memory for queue pointers..."
3109 "aborting.\n");
6a2cf8d3 3110 goto probe_failed;
9a347ff4
CD		 3111 }
3112
5601236b
MH		 3113 if (ha->mqenable && shost_use_blk_mq(host)) {
3114 /* number of hardware queues supported by blk/scsi-mq*/
3115 host->nr_hw_queues = ha->max_qpairs;
3116
3117 ql_dbg(ql_dbg_init, base_vha, 0x0192,
3118 "blk/scsi-mq enabled, HW queues = %d.\n", host->nr_hw_queues);
c38d1baf
HM		 3119 } else {
3120 if (ql2xnvmeenable) {
3121 host->nr_hw_queues = ha->max_qpairs;
3122 ql_dbg(ql_dbg_init, base_vha, 0x0194,
3123 "FC-NVMe support is enabled, HW queues=%d\n",
3124 host->nr_hw_queues);
3125 } else {
3126 ql_dbg(ql_dbg_init, base_vha, 0x0193,
3127 "blk/scsi-mq disabled.\n");
3128 }
3129 }
5601236b 3130
2d70c103 3131 qlt_probe_one_stage1(base_vha, ha);
9a347ff4 3132
90a86fc0
JC		 3133 pci_save_state(pdev);
3134
9a347ff4 3135 /* Assign back pointers */
2afa19a9
AC		 3136 rsp->req = req;
3137 req->rsp = rsp;
9a347ff4 3138
8ae6d9c7
GM		 3139 if (IS_QLAFX00(ha)) {
3140 ha->rsp_q_map[0] = rsp;
3141 ha->req_q_map[0] = req;
3142 set_bit(0, ha->req_qid_map);
3143 set_bit(0, ha->rsp_qid_map);
3144 }
3145
08029990
AV		 3146 /* FWI2-capable only. */
3147 req->req_q_in = &ha->iobase->isp24.req_q_in;
3148 req->req_q_out = &ha->iobase->isp24.req_q_out;
3149 rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in;
3150 rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out;
f73cb695 3151 if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
08029990
AV		 3152 req->req_q_in = &ha->mqiobase->isp25mq.req_q_in;
3153 req->req_q_out = &ha->mqiobase->isp25mq.req_q_out;
3154 rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in;
3155 rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out;
17d98630
AC		 3156 }
3157
8ae6d9c7
GM		 3158 if (IS_QLAFX00(ha)) {
3159 req->req_q_in = &ha->iobase->ispfx00.req_q_in;
3160 req->req_q_out = &ha->iobase->ispfx00.req_q_out;
3161 rsp->rsp_q_in = &ha->iobase->ispfx00.rsp_q_in;
3162 rsp->rsp_q_out = &ha->iobase->ispfx00.rsp_q_out;
3163 }
3164
7ec0effd 3165 if (IS_P3P_TYPE(ha)) {
a9083016
GM		 3166 req->req_q_out = &ha->iobase->isp82.req_q_out[0];
3167 rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0];
3168 rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0];
3169 }
3170
7c3df132
SK		 3171 ql_dbg(ql_dbg_multiq, base_vha, 0xc009,
3172 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
3173 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
3174 ql_dbg(ql_dbg_multiq, base_vha, 0xc00a,
3175 "req->req_q_in=%p req->req_q_out=%p "
3176 "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
3177 req->req_q_in, req->req_q_out,
3178 rsp->rsp_q_in, rsp->rsp_q_out);
3179 ql_dbg(ql_dbg_init, base_vha, 0x003e,
3180 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
3181 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
3182 ql_dbg(ql_dbg_init, base_vha, 0x003f,
3183 "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
3184 req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out);
1da177e4 3185
8ae6d9c7 3186 if (ha->isp_ops->initialize_adapter(base_vha)) {
7c3df132
SK		 3187 ql_log(ql_log_fatal, base_vha, 0x00d6,
3188 "Failed to initialize adapter - Adapter flags %x.\n",
3189 base_vha->device_flags);
1da177e4 3190
a9083016
GM		 3191 if (IS_QLA82XX(ha)) {
3192 qla82xx_idc_lock(ha);
3193 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 3194 QLA8XXX_DEV_FAILED);
a9083016 3195 qla82xx_idc_unlock(ha);
7c3df132
SK		 3196 ql_log(ql_log_fatal, base_vha, 0x00d7,
3197 "HW State: FAILED.\n");
7ec0effd
AD		 3198 } else if (IS_QLA8044(ha)) {
3199 qla8044_idc_lock(ha);
3200 qla8044_wr_direct(base_vha,
3201 QLA8044_CRB_DEV_STATE_INDEX,
3202 QLA8XXX_DEV_FAILED);
3203 qla8044_idc_unlock(ha);
3204 ql_log(ql_log_fatal, base_vha, 0x0150,
3205 "HW State: FAILED.\n");
a9083016
GM		 3206 }
3207
a1541d5a 3208 ret = -ENODEV;
1da177e4
LT		 3209 goto probe_failed;
3210 }
3211
3b1bef64
CD		 3212 if (IS_QLAFX00(ha))
3213 host->can_queue = QLAFX00_MAX_CANQUEUE;
3214 else
3215 host->can_queue = req->num_outstanding_cmds - 10;
3216
3217 ql_dbg(ql_dbg_init, base_vha, 0x0032,
3218 "can_queue=%d, req=%p, mgmt_svr_loop_id=%d, sg_tablesize=%d.\n",
3219 host->can_queue, base_vha->req,
3220 base_vha->mgmt_svr_loop_id, host->sg_tablesize);
3221
9b3e0f4d 3222 ha->wq = alloc_workqueue("qla2xxx_wq", 0, 0);
a01c77d2 3223
e326d22a
QT		 3224 if (ha->mqenable) {
3225 bool mq = false;
3226 bool startit = false;
e326d22a
QT		 3227
3228 if (QLA_TGT_MODE_ENABLED()) {
3229 mq = true;
3230 startit = false;
3231 }
3232
3233 if ((ql2x_ini_mode == QLA2XXX_INI_MODE_ENABLED) &&
3234 shost_use_blk_mq(host)) {
3235 mq = true;
3236 startit = true;
3237 }
3238
3239 if (mq) {
3240 /* Create start of day qpairs for Block MQ */
5601236b 3241 for (i = 0; i < ha->max_qpairs; i++)
e326d22a 3242 qla2xxx_create_qpair(base_vha, 5, 0, startit);
5601236b
MH		 3243 }
3244 }
68ca949c 3245
cbc8eb67
AV		 3246 if (ha->flags.running_gold_fw)
3247 goto skip_dpc;
3248
1da177e4
LT		 3249 /*
3250 * Startup the kernel thread for this host adapter
3251 */
39a11240 3252 ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha,
7c3df132 3253 "%s_dpc", base_vha->host_str);
39a11240 3254 if (IS_ERR(ha->dpc_thread)) {
7c3df132
SK		 3255 ql_log(ql_log_fatal, base_vha, 0x00ed,
3256 "Failed to start DPC thread.\n");
39a11240 3257 ret = PTR_ERR(ha->dpc_thread);
e2532b4a 3258 ha->dpc_thread = NULL;
1da177e4
LT		 3259 goto probe_failed;
3260 }
7c3df132
SK		 3261 ql_dbg(ql_dbg_init, base_vha, 0x00ee,
3262 "DPC thread started successfully.\n");
1da177e4 3263
2d70c103
NB		 3264 /*
3265 * If we're not coming up in initiator mode, we might sit for
3266 * a while without waking up the dpc thread, which leads to a
3267 * stuck process warning. So just kick the dpc once here and
3268 * let the kthread start (and go back to sleep in qla2x00_do_dpc).
3269 */
3270 qla2xxx_wake_dpc(base_vha);
3271
f3ddac19
CD		 3272 INIT_WORK(&ha->board_disable, qla2x00_disable_board_on_pci_error);
3273
81178772
SK		 3274 if (IS_QLA8031(ha) || IS_MCTP_CAPABLE(ha)) {
3275 sprintf(wq_name, "qla2xxx_%lu_dpc_lp_wq", base_vha->host_no);
3276 ha->dpc_lp_wq = create_singlethread_workqueue(wq_name);
3277 INIT_WORK(&ha->idc_aen, qla83xx_service_idc_aen);
3278
3279 sprintf(wq_name, "qla2xxx_%lu_dpc_hp_wq", base_vha->host_no);
3280 ha->dpc_hp_wq = create_singlethread_workqueue(wq_name);
3281 INIT_WORK(&ha->nic_core_reset, qla83xx_nic_core_reset_work);
3282 INIT_WORK(&ha->idc_state_handler,
3283 qla83xx_idc_state_handler_work);
3284 INIT_WORK(&ha->nic_core_unrecoverable,
3285 qla83xx_nic_core_unrecoverable_work);
3286 }
3287
cbc8eb67 3288skip_dpc:
e315cd28
AC		 3289 list_add_tail(&base_vha->list, &ha->vp_list);
3290 base_vha->host->irq = ha->pdev->irq;
1da177e4
LT		 3291
3292 /* Initialized the timer */
8e5f4ba0 3293 qla2x00_start_timer(base_vha, WATCH_INTERVAL);
7c3df132
SK		 3294 ql_dbg(ql_dbg_init, base_vha, 0x00ef,
3295 "Started qla2x00_timer with "
3296 "interval=%d.\n", WATCH_INTERVAL);
3297 ql_dbg(ql_dbg_init, base_vha, 0x00f0,
3298 "Detected hba at address=%p.\n",
3299 ha);
d19044c3 3300
e02587d7 3301 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) {
bad75002 3302 if (ha->fw_attributes & BIT_4) {
9e522cd8 3303 int prot = 0, guard;
bad75002 3304 base_vha->flags.difdix_supported = 1;
7c3df132
SK		 3305 ql_dbg(ql_dbg_init, base_vha, 0x00f1,
3306 "Registering for DIF/DIX type 1 and 3 protection.\n");
8cb2049c
AE		 3307 if (ql2xenabledif == 1)
3308 prot = SHOST_DIX_TYPE0_PROTECTION;
bad75002 3309 scsi_host_set_prot(host,
8cb2049c 3310 prot | SHOST_DIF_TYPE1_PROTECTION
0c470874 3311 | SHOST_DIF_TYPE2_PROTECTION
bad75002
AE		 3312 | SHOST_DIF_TYPE3_PROTECTION
3313 | SHOST_DIX_TYPE1_PROTECTION
0c470874 3314 | SHOST_DIX_TYPE2_PROTECTION
bad75002 3315 | SHOST_DIX_TYPE3_PROTECTION);
9e522cd8
AE		 3316
3317 guard = SHOST_DIX_GUARD_CRC;
3318
3319 if (IS_PI_IPGUARD_CAPABLE(ha) &&
3320 (ql2xenabledif > 1 || IS_PI_DIFB_DIX0_CAPABLE(ha)))
3321 guard |= SHOST_DIX_GUARD_IP;
3322
3323 scsi_host_set_guard(host, guard);
bad75002
AE		 3324 } else
3325 base_vha->flags.difdix_supported = 0;
3326 }
3327
a9083016
GM		 3328 ha->isp_ops->enable_intrs(ha);
3329
1fe19ee4
AB		 3330 if (IS_QLAFX00(ha)) {
3331 ret = qlafx00_fx_disc(base_vha,
3332 &base_vha->hw->mr.fcport, FXDISC_GET_CONFIG_INFO);
3333 host->sg_tablesize = (ha->mr.extended_io_enabled) ?
3334 QLA_SG_ALL : 128;
3335 }
3336
a1541d5a
AV		 3337 ret = scsi_add_host(host, &pdev->dev);
3338 if (ret)
3339 goto probe_failed;
3340
1486400f
MR		 3341 base_vha->flags.init_done = 1;
3342 base_vha->flags.online = 1;
edaa5c74 3343 ha->prev_minidump_failed = 0;
1486400f 3344
7c3df132
SK		 3345 ql_dbg(ql_dbg_init, base_vha, 0x00f2,
3346 "Init done and hba is online.\n");
3347
726b8548
QT		 3348 if (qla_ini_mode_enabled(base_vha) ||
3349 qla_dual_mode_enabled(base_vha))
2d70c103
NB		 3350 scsi_scan_host(host);
3351 else
3352 ql_dbg(ql_dbg_init, base_vha, 0x0122,
3353 "skipping scsi_scan_host() for non-initiator port\n");
1e99e33a 3354
e315cd28 3355 qla2x00_alloc_sysfs_attr(base_vha);
a1541d5a 3356
8ae6d9c7 3357 if (IS_QLAFX00(ha)) {
8ae6d9c7
GM		 3358 ret = qlafx00_fx_disc(base_vha,
3359 &base_vha->hw->mr.fcport, FXDISC_GET_PORT_INFO);
3360
3361 /* Register system information */
3362 ret = qlafx00_fx_disc(base_vha,
3363 &base_vha->hw->mr.fcport, FXDISC_REG_HOST_INFO);
3364 }
3365
e315cd28 3366 qla2x00_init_host_attr(base_vha);
a1541d5a 3367
e315cd28 3368 qla2x00_dfs_setup(base_vha);
df613b96 3369
03eb912a
AB		 3370 ql_log(ql_log_info, base_vha, 0x00fb,
3371 "QLogic %s - %s.\n", ha->model_number, ha->model_desc);
7c3df132
SK		 3372 ql_log(ql_log_info, base_vha, 0x00fc,
3373 "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n",
3374 pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info),
3375 pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-',
3376 base_vha->host_no,
df57caba 3377 ha->isp_ops->fw_version_str(base_vha, fw_str, sizeof(fw_str)));
1da177e4 3378
2d70c103
NB		 3379 qlt_add_target(ha, base_vha);
3380
6b383979 3381 clear_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags);
a29b3dd7
JC		 3382
3383 if (test_bit(UNLOADING, &base_vha->dpc_flags))
3384 return -ENODEV;
3385
e4e3a2ce
QT		 3386 if (ha->flags.detected_lr_sfp) {
3387 ql_log(ql_log_info, base_vha, 0xffff,
3388 "Reset chip to pick up LR SFP setting\n");
3389 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
3390 qla2xxx_wake_dpc(base_vha);
3391 }
3392
1da177e4
LT		 3393 return 0;
3394
3395probe_failed:
b9978769
AV		 3396 if (base_vha->timer_active)
3397 qla2x00_stop_timer(base_vha);
3398 base_vha->flags.online = 0;
3399 if (ha->dpc_thread) {
3400 struct task_struct *t = ha->dpc_thread;
3401
3402 ha->dpc_thread = NULL;
3403 kthread_stop(t);
3404 }
3405
e315cd28 3406 qla2x00_free_device(base_vha);
e315cd28 3407 scsi_host_put(base_vha->host);
6d634067
BK		 3408 /*
3409 * Need to NULL out local req/rsp after
3410 * qla2x00_free_device => qla2x00_free_queues frees
3411 * what these are pointing to. Or else we'll
3412 * fall over below in qla2x00_free_req/rsp_que.
3413 */
3414 req = NULL;
3415 rsp = NULL;
1da177e4 3416
e315cd28 3417probe_hw_failed:
d64d6c56 3418 qla2x00_mem_free(ha);
3419 qla2x00_free_req_que(ha, req);
3420 qla2x00_free_rsp_que(ha, rsp);
1a2fbf18
JL		 3421 qla2x00_clear_drv_active(ha);
3422
0a63ad12 3423iospace_config_failed:
7ec0effd 3424 if (IS_P3P_TYPE(ha)) {
0a63ad12 3425 if (!ha->nx_pcibase)
f73cb695 3426 iounmap((device_reg_t *)ha->nx_pcibase);
a9083016 3427 if (!ql2xdbwr)
f73cb695 3428 iounmap((device_reg_t *)ha->nxdb_wr_ptr);
a9083016
GM		 3429 } else {
3430 if (ha->iobase)
3431 iounmap(ha->iobase);
8ae6d9c7
GM		 3432 if (ha->cregbase)
3433 iounmap(ha->cregbase);
a9083016 3434 }
e315cd28
AC		 3435 pci_release_selected_regions(ha->pdev, ha->bars);
3436 kfree(ha);
1da177e4 3437
ddff7ed4 3438disable_device:
e315cd28 3439 pci_disable_device(pdev);
a1541d5a 3440 return ret;
1da177e4 3441}
1da177e4 3442
e30d1756
MI		 3443static void
3444qla2x00_shutdown(struct pci_dev *pdev)
3445{
3446 scsi_qla_host_t *vha;
3447 struct qla_hw_data *ha;
3448
3449 vha = pci_get_drvdata(pdev);
3450 ha = vha->hw;
3451
efdb5760
SC		 3452 ql_log(ql_log_info, vha, 0xfffa,
3453 "Adapter shutdown\n");
3454
3455 /*
3456 * Prevent future board_disable and wait
3457 * until any pending board_disable has completed.
3458 */
3459 set_bit(PFLG_DRIVER_REMOVING, &vha->pci_flags);
3460 cancel_work_sync(&ha->board_disable);
3461
3462 if (!atomic_read(&pdev->enable_cnt))
3463 return;
3464
42479343
AB		 3465 /* Notify ISPFX00 firmware */
3466 if (IS_QLAFX00(ha))
3467 qlafx00_driver_shutdown(vha, 20);
3468
e30d1756
MI		 3469 /* Turn-off FCE trace */
3470 if (ha->flags.fce_enabled) {
3471 qla2x00_disable_fce_trace(vha, NULL, NULL);
3472 ha->flags.fce_enabled = 0;
3473 }
3474
3475 /* Turn-off EFT trace */
3476 if (ha->eft)
3477 qla2x00_disable_eft_trace(vha);
3478
3407fc37
QT		 3479 if (IS_QLA25XX(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha)) {
3480 if (ha->flags.fw_started)
3481 qla2x00_abort_isp_cleanup(vha);
3482 } else {
3483 /* Stop currently executing firmware. */
3484 qla2x00_try_to_stop_firmware(vha);
3485 }
e30d1756
MI		 3486
3487 /* Turn adapter off line */
3488 vha->flags.online = 0;
3489
3490 /* turn-off interrupts on the card */
3491 if (ha->interrupts_on) {
3492 vha->flags.init_done = 0;
3493 ha->isp_ops->disable_intrs(ha);
3494 }
3495
3496 qla2x00_free_irqs(vha);
3497
3498 qla2x00_free_fw_dump(ha);
61d41f61 3499
61d41f61 3500 pci_disable_device(pdev);
efdb5760
SC		 3501 ql_log(ql_log_info, vha, 0xfffe,
3502 "Adapter shutdown successfully.\n");
e30d1756
MI		 3503}
3504
fe1b806f 3505/* Deletes all the virtual ports for a given ha */
4c993f76 3506static void
fe1b806f 3507qla2x00_delete_all_vps(struct qla_hw_data *ha, scsi_qla_host_t *base_vha)
1da177e4 3508{
fe1b806f 3509 scsi_qla_host_t *vha;
feafb7b1 3510 unsigned long flags;
e315cd28 3511
43ebf16d
AE		 3512 mutex_lock(&ha->vport_lock);
3513 while (ha->cur_vport_count) {
43ebf16d 3514 spin_lock_irqsave(&ha->vport_slock, flags);
feafb7b1 3515
43ebf16d
AE		 3516 BUG_ON(base_vha->list.next == &ha->vp_list);
3517 /* This assumes first entry in ha->vp_list is always base vha */
3518 vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list);
52c82823 3519 scsi_host_get(vha->host);
feafb7b1 3520
43ebf16d
AE		 3521 spin_unlock_irqrestore(&ha->vport_slock, flags);
3522 mutex_unlock(&ha->vport_lock);
3523
3524 fc_vport_terminate(vha->fc_vport);
3525 scsi_host_put(vha->host);
feafb7b1 3526
43ebf16d 3527 mutex_lock(&ha->vport_lock);
e315cd28 3528 }
43ebf16d 3529 mutex_unlock(&ha->vport_lock);
fe1b806f 3530}
1da177e4 3531
fe1b806f
CD		 3532/* Stops all deferred work threads */
3533static void
3534qla2x00_destroy_deferred_work(struct qla_hw_data *ha)
3535{
7d613ac6
SV		 3536 /* Cancel all work and destroy DPC workqueues */
3537 if (ha->dpc_lp_wq) {
3538 cancel_work_sync(&ha->idc_aen);
3539 destroy_workqueue(ha->dpc_lp_wq);
3540 ha->dpc_lp_wq = NULL;
3541 }
3542
3543 if (ha->dpc_hp_wq) {
3544 cancel_work_sync(&ha->nic_core_reset);
3545 cancel_work_sync(&ha->idc_state_handler);
3546 cancel_work_sync(&ha->nic_core_unrecoverable);
3547 destroy_workqueue(ha->dpc_hp_wq);
3548 ha->dpc_hp_wq = NULL;
3549 }
3550
b9978769
AV		 3551 /* Kill the kernel thread for this host */
3552 if (ha->dpc_thread) {
3553 struct task_struct *t = ha->dpc_thread;
3554
3555 /*
3556 * qla2xxx_wake_dpc checks for ->dpc_thread
3557 * so we need to zero it out.
3558 */
3559 ha->dpc_thread = NULL;
3560 kthread_stop(t);
3561 }
fe1b806f 3562}
1da177e4 3563
fe1b806f
CD		 3564static void
3565qla2x00_unmap_iobases(struct qla_hw_data *ha)
3566{
a9083016 3567 if (IS_QLA82XX(ha)) {
b963752f 3568
f73cb695 3569 iounmap((device_reg_t *)ha->nx_pcibase);
a9083016 3570 if (!ql2xdbwr)
f73cb695 3571 iounmap((device_reg_t *)ha->nxdb_wr_ptr);
a9083016
GM		 3572 } else {
3573 if (ha->iobase)
3574 iounmap(ha->iobase);
1da177e4 3575
8ae6d9c7
GM		 3576 if (ha->cregbase)
3577 iounmap(ha->cregbase);
3578
a9083016
GM		 3579 if (ha->mqiobase)
3580 iounmap(ha->mqiobase);
6246b8a1 3581
f73cb695 3582 if ((IS_QLA83XX(ha) || IS_QLA27XX(ha)) && ha->msixbase)
6246b8a1 3583 iounmap(ha->msixbase);
a9083016 3584 }
fe1b806f
CD		 3585}
3586
3587static void
db7157d4 3588qla2x00_clear_drv_active(struct qla_hw_data *ha)
fe1b806f 3589{
fe1b806f
CD		 3590 if (IS_QLA8044(ha)) {
3591 qla8044_idc_lock(ha);
c41afc9a 3592 qla8044_clear_drv_active(ha);
fe1b806f
CD		 3593 qla8044_idc_unlock(ha);
3594 } else if (IS_QLA82XX(ha)) {
3595 qla82xx_idc_lock(ha);
3596 qla82xx_clear_drv_active(ha);
3597 qla82xx_idc_unlock(ha);
3598 }
3599}
3600
3601static void
3602qla2x00_remove_one(struct pci_dev *pdev)
3603{
3604 scsi_qla_host_t *base_vha;
3605 struct qla_hw_data *ha;
3606
beb9e315
JL		 3607 base_vha = pci_get_drvdata(pdev);
3608 ha = base_vha->hw;
3609
3610 /* Indicate device removal to prevent future board_disable and wait
3611 * until any pending board_disable has completed. */
3612 set_bit(PFLG_DRIVER_REMOVING, &base_vha->pci_flags);
3613 cancel_work_sync(&ha->board_disable);
3614
fe1b806f 3615 /*
beb9e315
JL		 3616 * If the PCI device is disabled then there was a PCI-disconnect and
3617 * qla2x00_disable_board_on_pci_error has taken care of most of the
3618 * resources.
fe1b806f 3619 */
beb9e315 3620 if (!atomic_read(&pdev->enable_cnt)) {
726b8548
QT		 3621 dma_free_coherent(&ha->pdev->dev, base_vha->gnl.size,
3622 base_vha->gnl.l, base_vha->gnl.ldma);
3623
beb9e315
JL		 3624 scsi_host_put(base_vha->host);
3625 kfree(ha);
3626 pci_set_drvdata(pdev, NULL);
fe1b806f 3627 return;
beb9e315 3628 }
638a1a01
SC		 3629 qla2x00_wait_for_hba_ready(base_vha);
3630
2ce87cc5
QT		 3631 qla2x00_wait_for_sess_deletion(base_vha);
3632
726b8548
QT		 3633 /*
3634 * if UNLOAD flag is already set, then continue unload,
783e0dc4
SC		 3635 * where it was set first.
3636 */
3637 if (test_bit(UNLOADING, &base_vha->dpc_flags))
3638 return;
3639
fe1b806f 3640 set_bit(UNLOADING, &base_vha->dpc_flags);
e84067d7
DG		 3641
3642 qla_nvme_delete(base_vha);
3643
726b8548
QT		 3644 dma_free_coherent(&ha->pdev->dev,
3645 base_vha->gnl.size, base_vha->gnl.l, base_vha->gnl.ldma);
fe1b806f 3646
a4239945
QT		 3647 vfree(base_vha->scan.l);
3648
fe1b806f
CD		 3649 if (IS_QLAFX00(ha))
3650 qlafx00_driver_shutdown(base_vha, 20);
3651
3652 qla2x00_delete_all_vps(ha, base_vha);
3653
3654 if (IS_QLA8031(ha)) {
3655 ql_dbg(ql_dbg_p3p, base_vha, 0xb07e,
3656 "Clearing fcoe driver presence.\n");
3657 if (qla83xx_clear_drv_presence(base_vha) != QLA_SUCCESS)
3658 ql_dbg(ql_dbg_p3p, base_vha, 0xb079,
3659 "Error while clearing DRV-Presence.\n");
3660 }
3661
3662 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
3663
3664 qla2x00_dfs_remove(base_vha);
3665
3666 qla84xx_put_chip(base_vha);
3667
3668 /* Disable timer */
3669 if (base_vha->timer_active)
3670 qla2x00_stop_timer(base_vha);
3671
3672 base_vha->flags.online = 0;
3673
b0d6cabd
HM		 3674 /* free DMA memory */
3675 if (ha->exlogin_buf)
3676 qla2x00_free_exlogin_buffer(ha);
3677
2f56a7f1
HM		 3678 /* free DMA memory */
3679 if (ha->exchoffld_buf)
3680 qla2x00_free_exchoffld_buffer(ha);
3681
fe1b806f
CD		 3682 qla2x00_destroy_deferred_work(ha);
3683
3684 qlt_remove_target(ha, base_vha);
3685
3686 qla2x00_free_sysfs_attr(base_vha, true);
3687
3688 fc_remove_host(base_vha->host);
482c9dc7 3689 qlt_remove_target_resources(ha);
fe1b806f
CD		 3690
3691 scsi_remove_host(base_vha->host);
3692
3693 qla2x00_free_device(base_vha);
3694
db7157d4 3695 qla2x00_clear_drv_active(ha);
fe1b806f 3696
d2749ffa
AE		 3697 scsi_host_put(base_vha->host);
3698
fe1b806f 3699 qla2x00_unmap_iobases(ha);
73208dfd 3700
e315cd28
AC		 3701 pci_release_selected_regions(ha->pdev, ha->bars);
3702 kfree(ha);
1da177e4 3703
90a86fc0
JC		 3704 pci_disable_pcie_error_reporting(pdev);
3705
665db93b 3706 pci_disable_device(pdev);
1da177e4 3707}
1da177e4
LT		 3708
3709static void
e315cd28 3710qla2x00_free_device(scsi_qla_host_t *vha)
1da177e4 3711{
e315cd28 3712 struct qla_hw_data *ha = vha->hw;
1da177e4 3713
85880801
AV		 3714 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
3715
3716 /* Disable timer */
3717 if (vha->timer_active)
3718 qla2x00_stop_timer(vha);
3719
2afa19a9 3720 qla25xx_delete_queues(vha);
fe1b806f 3721
df613b96 3722 if (ha->flags.fce_enabled)
e315cd28 3723 qla2x00_disable_fce_trace(vha, NULL, NULL);
df613b96 3724
a7a167bf 3725 if (ha->eft)
e315cd28 3726 qla2x00_disable_eft_trace(vha);
a7a167bf 3727
3407fc37
QT		 3728 if (IS_QLA25XX(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha)) {
3729 if (ha->flags.fw_started)
3730 qla2x00_abort_isp_cleanup(vha);
3731 } else {
3732 if (ha->flags.fw_started) {
3733 /* Stop currently executing firmware. */
3734 qla2x00_try_to_stop_firmware(vha);
3735 ha->flags.fw_started = 0;
3736 }
3737 }
1da177e4 3738
85880801
AV		 3739 vha->flags.online = 0;
3740
f6ef3b18 3741 /* turn-off interrupts on the card */
a9083016
GM		 3742 if (ha->interrupts_on) {
3743 vha->flags.init_done = 0;
fd34f556 3744 ha->isp_ops->disable_intrs(ha);
a9083016 3745 }
f6ef3b18 3746
093df737
QT		 3747 qla2x00_free_fcports(vha);
3748
e315cd28 3749 qla2x00_free_irqs(vha);
1da177e4 3750
093df737
QT		 3751 /* Flush the work queue and remove it */
3752 if (ha->wq) {
3753 flush_workqueue(ha->wq);
3754 destroy_workqueue(ha->wq);
3755 ha->wq = NULL;
3756 }
3757
8867048b 3758
e315cd28 3759 qla2x00_mem_free(ha);
73208dfd 3760
08de2844
GM		 3761 qla82xx_md_free(vha);
3762
73208dfd 3763 qla2x00_free_queues(ha);
1da177e4
LT		 3764}
3765
8867048b
CD		 3766void qla2x00_free_fcports(struct scsi_qla_host *vha)
3767{
3768 fc_port_t *fcport, *tfcport;
3769
3770 list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list) {
3771 list_del(&fcport->list);
5f16b331 3772 qla2x00_clear_loop_id(fcport);
8867048b 3773 kfree(fcport);
8867048b
CD		 3774 }
3775}
3776
d97994dc 3777static inline void
e315cd28 3778qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport,
d97994dc 3779 int defer)
3780{
d97994dc 3781 struct fc_rport *rport;
67becc00 3782 scsi_qla_host_t *base_vha;
044d78e1 3783 unsigned long flags;
d97994dc 3784
3785 if (!fcport->rport)
3786 return;
3787
3788 rport = fcport->rport;
3789 if (defer) {
67becc00 3790 base_vha = pci_get_drvdata(vha->hw->pdev);
044d78e1 3791 spin_lock_irqsave(vha->host->host_lock, flags);
d97994dc 3792 fcport->drport = rport;
044d78e1 3793 spin_unlock_irqrestore(vha->host->host_lock, flags);
df673274 3794 qlt_do_generation_tick(vha, &base_vha->total_fcport_update_gen);
67becc00
AV		 3795 set_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags);
3796 qla2xxx_wake_dpc(base_vha);
2d70c103 3797 } else {
df673274 3798 int now;
726b8548 3799 if (rport) {
83548fe2
QT		 3800 ql_dbg(ql_dbg_disc, fcport->vha, 0x2109,
3801 "%s %8phN. rport %p roles %x\n",
3802 __func__, fcport->port_name, rport,
3803 rport->roles);
d20ed91b 3804 fc_remote_port_delete(rport);
726b8548 3805 }
df673274 3806 qlt_do_generation_tick(vha, &now);
2d70c103 3807 }
d97994dc 3808}
3809
1da177e4
LT		 3810/*
3811 * qla2x00_mark_device_lost Updates fcport state when device goes offline.
3812 *
3813 * Input: ha = adapter block pointer. fcport = port structure pointer.
3814 *
3815 * Return: None.
3816 *
3817 * Context:
3818 */
e315cd28 3819void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport,
d97994dc 3820 int do_login, int defer)
1da177e4 3821{
8ae6d9c7
GM		 3822 if (IS_QLAFX00(vha->hw)) {
3823 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
3824 qla2x00_schedule_rport_del(vha, fcport, defer);
3825 return;
3826 }
3827
2c3dfe3f 3828 if (atomic_read(&fcport->state) == FCS_ONLINE &&
c6d39e23 3829 vha->vp_idx == fcport->vha->vp_idx) {
ec426e10 3830 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
e315cd28
AC		 3831 qla2x00_schedule_rport_del(vha, fcport, defer);
3832 }
fa2a1ce5 3833 /*
1da177e4
LT		 3834 * We may need to retry the login, so don't change the state of the
3835 * port but do the retries.
3836 */
3837 if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD)
ec426e10 3838 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
1da177e4
LT		 3839
3840 if (!do_login)
3841 return;
3842
a1d0285e 3843 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
1da177e4
LT		 3844}
3845
3846/*
3847 * qla2x00_mark_all_devices_lost
3848 * Updates fcport state when device goes offline.
3849 *
3850 * Input:
3851 * ha = adapter block pointer.
3852 * fcport = port structure pointer.
3853 *
3854 * Return:
3855 * None.
3856 *
3857 * Context:
3858 */
3859void
e315cd28 3860qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha, int defer)
1da177e4
LT		 3861{
3862 fc_port_t *fcport;
3863
83548fe2
QT		 3864 ql_dbg(ql_dbg_disc, vha, 0x20f1,
3865 "Mark all dev lost\n");
726b8548 3866
e315cd28 3867 list_for_each_entry(fcport, &vha->vp_fcports, list) {
726b8548 3868 fcport->scan_state = 0;
d8630bb9 3869 qlt_schedule_sess_for_deletion(fcport);
726b8548 3870
c6d39e23 3871 if (vha->vp_idx != 0 && vha->vp_idx != fcport->vha->vp_idx)
1da177e4 3872 continue;
0d6e61bc 3873
1da177e4
LT		 3874 /*
3875 * No point in marking the device as lost, if the device is
3876 * already DEAD.
3877 */
3878 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD)
3879 continue;
e315cd28 3880 if (atomic_read(&fcport->state) == FCS_ONLINE) {
ec426e10 3881 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
0d6e61bc
AV		 3882 if (defer)
3883 qla2x00_schedule_rport_del(vha, fcport, defer);
c6d39e23 3884 else if (vha->vp_idx == fcport->vha->vp_idx)
0d6e61bc
AV		 3885 qla2x00_schedule_rport_del(vha, fcport, defer);
3886 }
1da177e4
LT		 3887 }
3888}
3889
3890/*
3891* qla2x00_mem_alloc
3892* Allocates adapter memory.
3893*
3894* Returns:
3895* 0 = success.
e8711085 3896* !0 = failure.
1da177e4 3897*/
e8711085 3898static int
73208dfd
AC		 3899qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len,
3900 struct req_que **req, struct rsp_que **rsp)
1da177e4
LT		 3901{
3902 char name[16];
1da177e4 3903
e8711085 3904 ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size,
e315cd28 3905 &ha->init_cb_dma, GFP_KERNEL);
e8711085 3906 if (!ha->init_cb)
e315cd28 3907 goto fail;
e8711085 3908
2d70c103
NB		 3909 if (qlt_mem_alloc(ha) < 0)
3910 goto fail_free_init_cb;
3911
642ef983
CD		 3912 ha->gid_list = dma_alloc_coherent(&ha->pdev->dev,
3913 qla2x00_gid_list_size(ha), &ha->gid_list_dma, GFP_KERNEL);
e315cd28 3914 if (!ha->gid_list)
2d70c103 3915 goto fail_free_tgt_mem;
1da177e4 3916
e8711085
AV		 3917 ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep);
3918 if (!ha->srb_mempool)
e315cd28 3919 goto fail_free_gid_list;
e8711085 3920
7ec0effd 3921 if (IS_P3P_TYPE(ha)) {
a9083016
GM		 3922 /* Allocate cache for CT6 Ctx. */
3923 if (!ctx_cachep) {
3924 ctx_cachep = kmem_cache_create("qla2xxx_ctx",
3925 sizeof(struct ct6_dsd), 0,
3926 SLAB_HWCACHE_ALIGN, NULL);
3927 if (!ctx_cachep)
fc1ffd6c 3928 goto fail_free_srb_mempool;
a9083016
GM		 3929 }
3930 ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ,
3931 ctx_cachep);
3932 if (!ha->ctx_mempool)
3933 goto fail_free_srb_mempool;
7c3df132
SK		 3934 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021,
3935 "ctx_cachep=%p ctx_mempool=%p.\n",
3936 ctx_cachep, ha->ctx_mempool);
a9083016
GM		 3937 }
3938
e8711085
AV		 3939 /* Get memory for cached NVRAM */
3940 ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL);
3941 if (!ha->nvram)
a9083016 3942 goto fail_free_ctx_mempool;
e8711085 3943
e315cd28
AC		 3944 snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME,
3945 ha->pdev->device);
3946 ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3947 DMA_POOL_SIZE, 8, 0);
3948 if (!ha->s_dma_pool)
3949 goto fail_free_nvram;
3950
7c3df132
SK		 3951 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022,
3952 "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n",
3953 ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool);
3954
7ec0effd 3955 if (IS_P3P_TYPE(ha) || ql2xenabledif) {
a9083016
GM		 3956 ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3957 DSD_LIST_DMA_POOL_SIZE, 8, 0);
3958 if (!ha->dl_dma_pool) {
7c3df132
SK		 3959 ql_log_pci(ql_log_fatal, ha->pdev, 0x0023,
3960 "Failed to allocate memory for dl_dma_pool.\n");
a9083016
GM		 3961 goto fail_s_dma_pool;
3962 }
3963
3964 ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3965 FCP_CMND_DMA_POOL_SIZE, 8, 0);
3966 if (!ha->fcp_cmnd_dma_pool) {
7c3df132
SK		 3967 ql_log_pci(ql_log_fatal, ha->pdev, 0x0024,
3968 "Failed to allocate memory for fcp_cmnd_dma_pool.\n");
a9083016
GM		 3969 goto fail_dl_dma_pool;
3970 }
7c3df132
SK		 3971 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025,
3972 "dl_dma_pool=%p fcp_cmnd_dma_pool=%p.\n",
3973 ha->dl_dma_pool, ha->fcp_cmnd_dma_pool);
a9083016
GM		 3974 }
3975
e8711085
AV		 3976 /* Allocate memory for SNS commands */
3977 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
e315cd28 3978 /* Get consistent memory allocated for SNS commands */
e8711085 3979 ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev,
e315cd28 3980 sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL);
e8711085 3981 if (!ha->sns_cmd)
e315cd28 3982 goto fail_dma_pool;
7c3df132 3983 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026,
d8424f68 3984 "sns_cmd: %p.\n", ha->sns_cmd);
e8711085 3985 } else {
e315cd28 3986 /* Get consistent memory allocated for MS IOCB */
e8711085 3987 ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
e315cd28 3988 &ha->ms_iocb_dma);
e8711085 3989 if (!ha->ms_iocb)
e315cd28
AC		 3990 goto fail_dma_pool;
3991 /* Get consistent memory allocated for CT SNS commands */
e8711085 3992 ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev,
e315cd28 3993 sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL);
e8711085
AV		 3994 if (!ha->ct_sns)
3995 goto fail_free_ms_iocb;
7c3df132
SK		 3996 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027,
3997 "ms_iocb=%p ct_sns=%p.\n",
3998 ha->ms_iocb, ha->ct_sns);
1da177e4
LT		 3999 }
4000
e315cd28 4001 /* Allocate memory for request ring */
73208dfd
AC		 4002 *req = kzalloc(sizeof(struct req_que), GFP_KERNEL);
4003 if (!*req) {
7c3df132
SK		 4004 ql_log_pci(ql_log_fatal, ha->pdev, 0x0028,
4005 "Failed to allocate memory for req.\n");
e315cd28
AC		 4006 goto fail_req;
4007 }
73208dfd
AC		 4008 (*req)->length = req_len;
4009 (*req)->ring = dma_alloc_coherent(&ha->pdev->dev,
4010 ((*req)->length + 1) * sizeof(request_t),
4011 &(*req)->dma, GFP_KERNEL);
4012 if (!(*req)->ring) {
7c3df132
SK		 4013 ql_log_pci(ql_log_fatal, ha->pdev, 0x0029,
4014 "Failed to allocate memory for req_ring.\n");
e315cd28
AC		 4015 goto fail_req_ring;
4016 }
4017 /* Allocate memory for response ring */
73208dfd
AC		 4018 *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL);
4019 if (!*rsp) {
7c3df132
SK		 4020 ql_log_pci(ql_log_fatal, ha->pdev, 0x002a,
4021 "Failed to allocate memory for rsp.\n");
e315cd28
AC		 4022 goto fail_rsp;
4023 }
73208dfd
AC		 4024 (*rsp)->hw = ha;
4025 (*rsp)->length = rsp_len;
4026 (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev,
4027 ((*rsp)->length + 1) * sizeof(response_t),
4028 &(*rsp)->dma, GFP_KERNEL);
4029 if (!(*rsp)->ring) {
7c3df132
SK		 4030 ql_log_pci(ql_log_fatal, ha->pdev, 0x002b,
4031 "Failed to allocate memory for rsp_ring.\n");
e315cd28
AC		 4032 goto fail_rsp_ring;
4033 }
73208dfd
AC		 4034 (*req)->rsp = *rsp;
4035 (*rsp)->req = *req;
7c3df132
SK		 4036 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c,
4037 "req=%p req->length=%d req->ring=%p rsp=%p "
4038 "rsp->length=%d rsp->ring=%p.\n",
4039 *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length,
4040 (*rsp)->ring);
73208dfd
AC		 4041 /* Allocate memory for NVRAM data for vports */
4042 if (ha->nvram_npiv_size) {
6396bb22
KC		 4043 ha->npiv_info = kcalloc(ha->nvram_npiv_size,
4044 sizeof(struct qla_npiv_entry),
4045 GFP_KERNEL);
73208dfd 4046 if (!ha->npiv_info) {
7c3df132
SK		 4047 ql_log_pci(ql_log_fatal, ha->pdev, 0x002d,
4048 "Failed to allocate memory for npiv_info.\n");
73208dfd
AC		 4049 goto fail_npiv_info;
4050 }
4051 } else
4052 ha->npiv_info = NULL;
e8711085 4053
b64b0e8f 4054 /* Get consistent memory allocated for EX-INIT-CB. */
f73cb695 4055 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha)) {
b64b0e8f
AV		 4056 ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
4057 &ha->ex_init_cb_dma);
4058 if (!ha->ex_init_cb)
4059 goto fail_ex_init_cb;
7c3df132
SK		 4060 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e,
4061 "ex_init_cb=%p.\n", ha->ex_init_cb);
b64b0e8f
AV		 4062 }
4063
a9083016
GM		 4064 INIT_LIST_HEAD(&ha->gbl_dsd_list);
4065
5ff1d584
AV		 4066 /* Get consistent memory allocated for Async Port-Database. */
4067 if (!IS_FWI2_CAPABLE(ha)) {
4068 ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
4069 &ha->async_pd_dma);
4070 if (!ha->async_pd)
4071 goto fail_async_pd;
7c3df132
SK		 4072 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f,
4073 "async_pd=%p.\n", ha->async_pd);
5ff1d584
AV		 4074 }
4075
e315cd28 4076 INIT_LIST_HEAD(&ha->vp_list);
5f16b331
CD		 4077
4078 /* Allocate memory for our loop_id bitmap */
6396bb22
KC		 4079 ha->loop_id_map = kcalloc(BITS_TO_LONGS(LOOPID_MAP_SIZE),
4080 sizeof(long),
4081 GFP_KERNEL);
5f16b331 4082 if (!ha->loop_id_map)
fc1ffd6c 4083 goto fail_loop_id_map;
5f16b331
CD		 4084 else {
4085 qla2x00_set_reserved_loop_ids(ha);
4086 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0123,
b2a72ec3 4087 "loop_id_map=%p.\n", ha->loop_id_map);
5f16b331
CD		 4088 }
4089
e4e3a2ce
QT		 4090 ha->sfp_data = dma_alloc_coherent(&ha->pdev->dev,
4091 SFP_DEV_SIZE, &ha->sfp_data_dma, GFP_KERNEL);
4092 if (!ha->sfp_data) {
4093 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b,
4094 "Unable to allocate memory for SFP read-data.\n");
4095 goto fail_sfp_data;
4096 }
4097
b2a72ec3 4098 return 0;
e315cd28 4099
e4e3a2ce
QT		 4100fail_sfp_data:
4101 kfree(ha->loop_id_map);
fc1ffd6c
QT		 4102fail_loop_id_map:
4103 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
5ff1d584
AV		 4104fail_async_pd:
4105 dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma);
b64b0e8f
AV		 4106fail_ex_init_cb:
4107 kfree(ha->npiv_info);
73208dfd
AC		 4108fail_npiv_info:
4109 dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) *
4110 sizeof(response_t), (*rsp)->ring, (*rsp)->dma);
4111 (*rsp)->ring = NULL;
4112 (*rsp)->dma = 0;
e315cd28 4113fail_rsp_ring:
73208dfd 4114 kfree(*rsp);
6d634067 4115 *rsp = NULL;
e315cd28 4116fail_rsp:
73208dfd
AC		 4117 dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) *
4118 sizeof(request_t), (*req)->ring, (*req)->dma);
4119 (*req)->ring = NULL;
4120 (*req)->dma = 0;
e315cd28 4121fail_req_ring:
73208dfd 4122 kfree(*req);
6d634067 4123 *req = NULL;
e315cd28
AC		 4124fail_req:
4125 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
4126 ha->ct_sns, ha->ct_sns_dma);
4127 ha->ct_sns = NULL;
4128 ha->ct_sns_dma = 0;
e8711085
AV		 4129fail_free_ms_iocb:
4130 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
4131 ha->ms_iocb = NULL;
4132 ha->ms_iocb_dma = 0;
fc1ffd6c
QT		 4133
4134 if (ha->sns_cmd)
4135 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
4136 ha->sns_cmd, ha->sns_cmd_dma);
e315cd28 4137fail_dma_pool:
bad75002 4138 if (IS_QLA82XX(ha) || ql2xenabledif) {
a9083016
GM		 4139 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
4140 ha->fcp_cmnd_dma_pool = NULL;
4141 }
4142fail_dl_dma_pool:
bad75002 4143 if (IS_QLA82XX(ha) || ql2xenabledif) {
a9083016
GM		 4144 dma_pool_destroy(ha->dl_dma_pool);
4145 ha->dl_dma_pool = NULL;
4146 }
4147fail_s_dma_pool:
e315cd28
AC		 4148 dma_pool_destroy(ha->s_dma_pool);
4149 ha->s_dma_pool = NULL;
e8711085
AV		 4150fail_free_nvram:
4151 kfree(ha->nvram);
4152 ha->nvram = NULL;
a9083016 4153fail_free_ctx_mempool:
fc1ffd6c
QT		 4154 if (ha->ctx_mempool)
4155 mempool_destroy(ha->ctx_mempool);
a9083016 4156 ha->ctx_mempool = NULL;
e8711085 4157fail_free_srb_mempool:
fc1ffd6c
QT		 4158 if (ha->srb_mempool)
4159 mempool_destroy(ha->srb_mempool);
e8711085 4160 ha->srb_mempool = NULL;
e8711085 4161fail_free_gid_list:
642ef983
CD		 4162 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
4163 ha->gid_list,
e315cd28 4164 ha->gid_list_dma);
e8711085
AV		 4165 ha->gid_list = NULL;
4166 ha->gid_list_dma = 0;
2d70c103
NB		 4167fail_free_tgt_mem:
4168 qlt_mem_free(ha);
e315cd28
AC		 4169fail_free_init_cb:
4170 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb,
4171 ha->init_cb_dma);
4172 ha->init_cb = NULL;
4173 ha->init_cb_dma = 0;
e8711085 4174fail:
7c3df132
SK		 4175 ql_log(ql_log_fatal, NULL, 0x0030,
4176 "Memory allocation failure.\n");
e8711085 4177 return -ENOMEM;
1da177e4
LT		 4178}
4179
b0d6cabd
HM		 4180int
4181qla2x00_set_exlogins_buffer(scsi_qla_host_t *vha)
4182{
4183 int rval;
4184 uint16_t size, max_cnt, temp;
4185 struct qla_hw_data *ha = vha->hw;
4186
4187 /* Return if we don't need to alloacate any extended logins */
4188 if (!ql2xexlogins)
4189 return QLA_SUCCESS;
4190
99e1b683
QT		 4191 if (!IS_EXLOGIN_OFFLD_CAPABLE(ha))
4192 return QLA_SUCCESS;
4193
b0d6cabd
HM		 4194 ql_log(ql_log_info, vha, 0xd021, "EXLOGIN count: %d.\n", ql2xexlogins);
4195 max_cnt = 0;
4196 rval = qla_get_exlogin_status(vha, &size, &max_cnt);
4197 if (rval != QLA_SUCCESS) {
4198 ql_log_pci(ql_log_fatal, ha->pdev, 0xd029,
4199 "Failed to get exlogin status.\n");
4200 return rval;
4201 }
4202
4203 temp = (ql2xexlogins > max_cnt) ? max_cnt : ql2xexlogins;
99e1b683
QT		 4204 temp *= size;
4205
4206 if (temp != ha->exlogin_size) {
4207 qla2x00_free_exlogin_buffer(ha);
4208 ha->exlogin_size = temp;
4209
4210 ql_log(ql_log_info, vha, 0xd024,
4211 "EXLOGIN: max_logins=%d, portdb=0x%x, total=%d.\n",
4212 max_cnt, size, temp);
4213
4214 ql_log(ql_log_info, vha, 0xd025,
4215 "EXLOGIN: requested size=0x%x\n", ha->exlogin_size);
4216
4217 /* Get consistent memory for extended logins */
4218 ha->exlogin_buf = dma_alloc_coherent(&ha->pdev->dev,
4219 ha->exlogin_size, &ha->exlogin_buf_dma, GFP_KERNEL);
4220 if (!ha->exlogin_buf) {
4221 ql_log_pci(ql_log_fatal, ha->pdev, 0xd02a,
b0d6cabd 4222 "Failed to allocate memory for exlogin_buf_dma.\n");
99e1b683
QT		 4223 return -ENOMEM;
4224 }
b0d6cabd
HM		 4225 }
4226
4227 /* Now configure the dma buffer */
4228 rval = qla_set_exlogin_mem_cfg(vha, ha->exlogin_buf_dma);
4229 if (rval) {
83548fe2 4230 ql_log(ql_log_fatal, vha, 0xd033,
b0d6cabd
HM		 4231 "Setup extended login buffer ****FAILED****.\n");
4232 qla2x00_free_exlogin_buffer(ha);
4233 }
4234
4235 return rval;
4236}
4237
4238/*
4239* qla2x00_free_exlogin_buffer
4240*
4241* Input:
4242* ha = adapter block pointer
4243*/
4244void
4245qla2x00_free_exlogin_buffer(struct qla_hw_data *ha)
4246{
4247 if (ha->exlogin_buf) {
4248 dma_free_coherent(&ha->pdev->dev, ha->exlogin_size,
4249 ha->exlogin_buf, ha->exlogin_buf_dma);
4250 ha->exlogin_buf = NULL;
4251 ha->exlogin_size = 0;
4252 }
4253}
4254
99e1b683
QT		 4255static void
4256qla2x00_number_of_exch(scsi_qla_host_t *vha, u32 *ret_cnt, u16 max_cnt)
4257{
4258 u32 temp;
4259 *ret_cnt = FW_DEF_EXCHANGES_CNT;
4260
d1e3635a
QT		 4261 if (max_cnt > vha->hw->max_exchg)
4262 max_cnt = vha->hw->max_exchg;
4263
99e1b683
QT		 4264 if (qla_ini_mode_enabled(vha)) {
4265 if (ql2xiniexchg > max_cnt)
4266 ql2xiniexchg = max_cnt;
4267
4268 if (ql2xiniexchg > FW_DEF_EXCHANGES_CNT)
4269 *ret_cnt = ql2xiniexchg;
4270 } else if (qla_tgt_mode_enabled(vha)) {
4271 if (ql2xexchoffld > max_cnt)
4272 ql2xexchoffld = max_cnt;
4273
4274 if (ql2xexchoffld > FW_DEF_EXCHANGES_CNT)
4275 *ret_cnt = ql2xexchoffld;
4276 } else if (qla_dual_mode_enabled(vha)) {
4277 temp = ql2xiniexchg + ql2xexchoffld;
4278 if (temp > max_cnt) {
4279 ql2xiniexchg -= (temp - max_cnt)/2;
4280 ql2xexchoffld -= (((temp - max_cnt)/2) + 1);
4281 temp = max_cnt;
4282 }
4283
4284 if (temp > FW_DEF_EXCHANGES_CNT)
4285 *ret_cnt = temp;
4286 }
4287}
4288
2f56a7f1
HM		 4289int
4290qla2x00_set_exchoffld_buffer(scsi_qla_host_t *vha)
4291{
4292 int rval;
d1e3635a
QT		 4293 u16 size, max_cnt;
4294 u32 actual_cnt, totsz;
2f56a7f1
HM		 4295 struct qla_hw_data *ha = vha->hw;
4296
99e1b683
QT		 4297 if (!ha->flags.exchoffld_enabled)
4298 return QLA_SUCCESS;
4299
4300 if (!IS_EXCHG_OFFLD_CAPABLE(ha))
2f56a7f1
HM		 4301 return QLA_SUCCESS;
4302
2f56a7f1
HM		 4303 max_cnt = 0;
4304 rval = qla_get_exchoffld_status(vha, &size, &max_cnt);
4305 if (rval != QLA_SUCCESS) {
4306 ql_log_pci(ql_log_fatal, ha->pdev, 0xd012,
4307 "Failed to get exlogin status.\n");
4308 return rval;
4309 }
4310
d1e3635a
QT		 4311 qla2x00_number_of_exch(vha, &actual_cnt, max_cnt);
4312 ql_log(ql_log_info, vha, 0xd014,
4313 "Actual exchange offload count: %d.\n", actual_cnt);
4314
4315 totsz = actual_cnt * size;
2f56a7f1 4316
d1e3635a 4317 if (totsz != ha->exchoffld_size) {
99e1b683 4318 qla2x00_free_exchoffld_buffer(ha);
d1e3635a 4319 ha->exchoffld_size = totsz;
99e1b683
QT		 4320
4321 ql_log(ql_log_info, vha, 0xd016,
d1e3635a
QT		 4322 "Exchange offload: max_count=%d, actual count=%d entry sz=0x%x, total sz=0x%x\n",
4323 max_cnt, actual_cnt, size, totsz);
99e1b683
QT		 4324
4325 ql_log(ql_log_info, vha, 0xd017,
4326 "Exchange Buffers requested size = 0x%x\n",
4327 ha->exchoffld_size);
4328
4329 /* Get consistent memory for extended logins */
4330 ha->exchoffld_buf = dma_alloc_coherent(&ha->pdev->dev,
4331 ha->exchoffld_size, &ha->exchoffld_buf_dma, GFP_KERNEL);
4332 if (!ha->exchoffld_buf) {
4333 ql_log_pci(ql_log_fatal, ha->pdev, 0xd013,
d1e3635a
QT		 4334 "Failed to allocate memory for Exchange Offload.\n");
4335
4336 if (ha->max_exchg >
4337 (FW_DEF_EXCHANGES_CNT + REDUCE_EXCHANGES_CNT)) {
4338 ha->max_exchg -= REDUCE_EXCHANGES_CNT;
4339 } else if (ha->max_exchg >
4340 (FW_DEF_EXCHANGES_CNT + 512)) {
4341 ha->max_exchg -= 512;
4342 } else {
4343 ha->flags.exchoffld_enabled = 0;
4344 ql_log_pci(ql_log_fatal, ha->pdev, 0xd013,
4345 "Disabling Exchange offload due to lack of memory\n");
4346 }
4347 ha->exchoffld_size = 0;
4348
99e1b683
QT		 4349 return -ENOMEM;
4350 }
2f56a7f1
HM		 4351 }
4352
4353 /* Now configure the dma buffer */
99e1b683 4354 rval = qla_set_exchoffld_mem_cfg(vha);
2f56a7f1
HM		 4355 if (rval) {
4356 ql_log(ql_log_fatal, vha, 0xd02e,
4357 "Setup exchange offload buffer ****FAILED****.\n");
4358 qla2x00_free_exchoffld_buffer(ha);
99e1b683
QT		 4359 } else {
4360 /* re-adjust number of target exchange */
4361 struct init_cb_81xx *icb = (struct init_cb_81xx *)ha->init_cb;
4362
4363 if (qla_ini_mode_enabled(vha))
4364 icb->exchange_count = 0;
4365 else
4366 icb->exchange_count = cpu_to_le16(ql2xexchoffld);
2f56a7f1
HM		 4367 }
4368
4369 return rval;
4370}
4371
4372/*
4373* qla2x00_free_exchoffld_buffer
4374*
4375* Input:
4376* ha = adapter block pointer
4377*/
4378void
4379qla2x00_free_exchoffld_buffer(struct qla_hw_data *ha)
4380{
4381 if (ha->exchoffld_buf) {
4382 dma_free_coherent(&ha->pdev->dev, ha->exchoffld_size,
4383 ha->exchoffld_buf, ha->exchoffld_buf_dma);
4384 ha->exchoffld_buf = NULL;
4385 ha->exchoffld_size = 0;
4386 }
4387}
4388
1da177e4 4389/*
e30d1756
MI		 4390* qla2x00_free_fw_dump
4391* Frees fw dump stuff.
1da177e4
LT		 4392*
4393* Input:
7ec0effd 4394* ha = adapter block pointer
1da177e4 4395*/
a824ebb3 4396static void
e30d1756 4397qla2x00_free_fw_dump(struct qla_hw_data *ha)
1da177e4 4398{
df613b96 4399 if (ha->fce)
f73cb695
CD		 4400 dma_free_coherent(&ha->pdev->dev,
4401 FCE_SIZE, ha->fce, ha->fce_dma);
df613b96 4402
f73cb695
CD		 4403 if (ha->eft)
4404 dma_free_coherent(&ha->pdev->dev,
4405 EFT_SIZE, ha->eft, ha->eft_dma);
4406
4407 if (ha->fw_dump)
a7a167bf 4408 vfree(ha->fw_dump);
f73cb695
CD		 4409 if (ha->fw_dump_template)
4410 vfree(ha->fw_dump_template);
4411
e30d1756
MI		 4412 ha->fce = NULL;
4413 ha->fce_dma = 0;
4414 ha->eft = NULL;
4415 ha->eft_dma = 0;
e30d1756 4416 ha->fw_dumped = 0;
61f098dd 4417 ha->fw_dump_cap_flags = 0;
e30d1756 4418 ha->fw_dump_reading = 0;
f73cb695
CD		 4419 ha->fw_dump = NULL;
4420 ha->fw_dump_len = 0;
4421 ha->fw_dump_template = NULL;
4422 ha->fw_dump_template_len = 0;
e30d1756
MI		 4423}
4424
4425/*
4426* qla2x00_mem_free
4427* Frees all adapter allocated memory.
4428*
4429* Input:
4430* ha = adapter block pointer.
4431*/
4432static void
4433qla2x00_mem_free(struct qla_hw_data *ha)
4434{
4435 qla2x00_free_fw_dump(ha);
4436
81178772
SK		 4437 if (ha->mctp_dump)
4438 dma_free_coherent(&ha->pdev->dev, MCTP_DUMP_SIZE, ha->mctp_dump,
4439 ha->mctp_dump_dma);
4440
e30d1756
MI		 4441 if (ha->srb_mempool)
4442 mempool_destroy(ha->srb_mempool);
a7a167bf 4443
11bbc1d8
AV		 4444 if (ha->dcbx_tlv)
4445 dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE,
4446 ha->dcbx_tlv, ha->dcbx_tlv_dma);
4447
ce0423f4
AV		 4448 if (ha->xgmac_data)
4449 dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE,
4450 ha->xgmac_data, ha->xgmac_data_dma);
4451
1da177e4
LT		 4452 if (ha->sns_cmd)
4453 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
e315cd28 4454 ha->sns_cmd, ha->sns_cmd_dma);
1da177e4
LT		 4455
4456 if (ha->ct_sns)
4457 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
e315cd28 4458 ha->ct_sns, ha->ct_sns_dma);
1da177e4 4459
88729e53 4460 if (ha->sfp_data)
e4e3a2ce
QT		 4461 dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE, ha->sfp_data,
4462 ha->sfp_data_dma);
88729e53 4463
1da177e4
LT		 4464 if (ha->ms_iocb)
4465 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
4466
b64b0e8f 4467 if (ha->ex_init_cb)
a9083016
GM		 4468 dma_pool_free(ha->s_dma_pool,
4469 ha->ex_init_cb, ha->ex_init_cb_dma);
b64b0e8f 4470
5ff1d584
AV		 4471 if (ha->async_pd)
4472 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
4473
1da177e4
LT		 4474 if (ha->s_dma_pool)
4475 dma_pool_destroy(ha->s_dma_pool);
4476
1da177e4 4477 if (ha->gid_list)
642ef983
CD		 4478 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
4479 ha->gid_list, ha->gid_list_dma);
1da177e4 4480
a9083016
GM		 4481 if (IS_QLA82XX(ha)) {
4482 if (!list_empty(&ha->gbl_dsd_list)) {
4483 struct dsd_dma *dsd_ptr, *tdsd_ptr;
4484
4485 /* clean up allocated prev pool */
4486 list_for_each_entry_safe(dsd_ptr,
4487 tdsd_ptr, &ha->gbl_dsd_list, list) {
4488 dma_pool_free(ha->dl_dma_pool,
4489 dsd_ptr->dsd_addr, dsd_ptr->dsd_list_dma);
4490 list_del(&dsd_ptr->list);
4491 kfree(dsd_ptr);
4492 }
4493 }
4494 }
4495
4496 if (ha->dl_dma_pool)
4497 dma_pool_destroy(ha->dl_dma_pool);
4498
4499 if (ha->fcp_cmnd_dma_pool)
4500 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
4501
4502 if (ha->ctx_mempool)
4503 mempool_destroy(ha->ctx_mempool);
4504
2d70c103
NB		 4505 qlt_mem_free(ha);
4506
e315cd28
AC		 4507 if (ha->init_cb)
4508 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size,
a9083016 4509 ha->init_cb, ha->init_cb_dma);
6a2cf8d3 4510
6d634067
BK		 4511 vfree(ha->optrom_buffer);
4512 kfree(ha->nvram);
4513 kfree(ha->npiv_info);
4514 kfree(ha->swl);
4515 kfree(ha->loop_id_map);
1da177e4 4516
e8711085 4517 ha->srb_mempool = NULL;
a9083016 4518 ha->ctx_mempool = NULL;
1da177e4
LT		 4519 ha->sns_cmd = NULL;
4520 ha->sns_cmd_dma = 0;
4521 ha->ct_sns = NULL;
4522 ha->ct_sns_dma = 0;
4523 ha->ms_iocb = NULL;
4524 ha->ms_iocb_dma = 0;
1da177e4
LT		 4525 ha->init_cb = NULL;
4526 ha->init_cb_dma = 0;
b64b0e8f
AV		 4527 ha->ex_init_cb = NULL;
4528 ha->ex_init_cb_dma = 0;
5ff1d584
AV		 4529 ha->async_pd = NULL;
4530 ha->async_pd_dma = 0;
6a2cf8d3
BK		 4531 ha->loop_id_map = NULL;
4532 ha->npiv_info = NULL;
4533 ha->optrom_buffer = NULL;
4534 ha->swl = NULL;
4535 ha->nvram = NULL;
4536 ha->mctp_dump = NULL;
4537 ha->dcbx_tlv = NULL;
4538 ha->xgmac_data = NULL;
4539 ha->sfp_data = NULL;
1da177e4
LT		 4540
4541 ha->s_dma_pool = NULL;
a9083016
GM		 4542 ha->dl_dma_pool = NULL;
4543 ha->fcp_cmnd_dma_pool = NULL;
1da177e4 4544
1da177e4
LT		 4545 ha->gid_list = NULL;
4546 ha->gid_list_dma = 0;
2d70c103
NB		 4547
4548 ha->tgt.atio_ring = NULL;
4549 ha->tgt.atio_dma = 0;
4550 ha->tgt.tgt_vp_map = NULL;
e315cd28 4551}
1da177e4 4552
e315cd28
AC		 4553struct scsi_qla_host *qla2x00_create_host(struct scsi_host_template *sht,
4554 struct qla_hw_data *ha)
4555{
4556 struct Scsi_Host *host;
4557 struct scsi_qla_host *vha = NULL;
854165f4 4558
e315cd28 4559 host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t));
41dc529a 4560 if (!host) {
7c3df132
SK		 4561 ql_log_pci(ql_log_fatal, ha->pdev, 0x0107,
4562 "Failed to allocate host from the scsi layer, aborting.\n");
41dc529a 4563 return NULL;
e315cd28
AC		 4564 }
4565
4566 /* Clear our data area */
4567 vha = shost_priv(host);
4568 memset(vha, 0, sizeof(scsi_qla_host_t));
4569
4570 vha->host = host;
4571 vha->host_no = host->host_no;
4572 vha->hw = ha;
4573
4574 INIT_LIST_HEAD(&vha->vp_fcports);
4575 INIT_LIST_HEAD(&vha->work_list);
4576 INIT_LIST_HEAD(&vha->list);
8b2f5ff3
SN		 4577 INIT_LIST_HEAD(&vha->qla_cmd_list);
4578 INIT_LIST_HEAD(&vha->qla_sess_op_cmd_list);
71cdc079 4579 INIT_LIST_HEAD(&vha->logo_list);
b7bd104e 4580 INIT_LIST_HEAD(&vha->plogi_ack_list);
d7459527 4581 INIT_LIST_HEAD(&vha->qp_list);
41dc529a 4582 INIT_LIST_HEAD(&vha->gnl.fcports);
a5d42f4c 4583 INIT_LIST_HEAD(&vha->nvme_rport_list);
2d73ac61 4584 INIT_LIST_HEAD(&vha->gpnid_list);
9b3e0f4d 4585 INIT_WORK(&vha->iocb_work, qla2x00_iocb_work_fn);
e315cd28 4586
f999f4c1 4587 spin_lock_init(&vha->work_lock);
8b2f5ff3 4588 spin_lock_init(&vha->cmd_list_lock);
1c6cacf4 4589 spin_lock_init(&vha->gnl.fcports_lock);
726b8548 4590 init_waitqueue_head(&vha->fcport_waitQ);
c4a9b538 4591 init_waitqueue_head(&vha->vref_waitq);
f999f4c1 4592
2fdbc65e
BVA		 4593 vha->gnl.size = sizeof(struct get_name_list_extended) *
4594 (ha->max_loop_id + 1);
41dc529a
QT		 4595 vha->gnl.l = dma_alloc_coherent(&ha->pdev->dev,
4596 vha->gnl.size, &vha->gnl.ldma, GFP_KERNEL);
4597 if (!vha->gnl.l) {
83548fe2 4598 ql_log(ql_log_fatal, vha, 0xd04a,
41dc529a
QT		 4599 "Alloc failed for name list.\n");
4600 scsi_remove_host(vha->host);
4601 return NULL;
4602 }
f999f4c1 4603
a4239945
QT		 4604 /* todo: what about ext login? */
4605 vha->scan.size = ha->max_fibre_devices * sizeof(struct fab_scan_rp);
4606 vha->scan.l = vmalloc(vha->scan.size);
4607 if (!vha->scan.l) {
4608 ql_log(ql_log_fatal, vha, 0xd04a,
4609 "Alloc failed for scan database.\n");
4610 dma_free_coherent(&ha->pdev->dev, vha->gnl.size,
4611 vha->gnl.l, vha->gnl.ldma);
4612 scsi_remove_host(vha->host);
4613 return NULL;
4614 }
f352eeb7 4615 INIT_DELAYED_WORK(&vha->scan.scan_work, qla_scan_work_fn);
a4239945 4616
e315cd28 4617 sprintf(vha->host_str, "%s_%ld", QLA2XXX_DRIVER_NAME, vha->host_no);
7c3df132
SK		 4618 ql_dbg(ql_dbg_init, vha, 0x0041,
4619 "Allocated the host=%p hw=%p vha=%p dev_name=%s",
4620 vha->host, vha->hw, vha,
4621 dev_name(&(ha->pdev->dev)));
4622
e315cd28 4623 return vha;
1da177e4
LT		 4624}
4625
726b8548 4626struct qla_work_evt *
f999f4c1 4627qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type)
0971de7f
AV		 4628{
4629 struct qla_work_evt *e;
feafb7b1
AE		 4630 uint8_t bail;
4631
4632 QLA_VHA_MARK_BUSY(vha, bail);
4633 if (bail)
4634 return NULL;
0971de7f 4635
f999f4c1 4636 e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC);
feafb7b1
AE		 4637 if (!e) {
4638 QLA_VHA_MARK_NOT_BUSY(vha);
0971de7f 4639 return NULL;
feafb7b1 4640 }
0971de7f
AV		 4641
4642 INIT_LIST_HEAD(&e->list);
4643 e->type = type;
4644 e->flags = QLA_EVT_FLAG_FREE;
4645 return e;
4646}
4647
726b8548 4648int
f999f4c1 4649qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e)
0971de7f 4650{
f999f4c1 4651 unsigned long flags;
9b3e0f4d 4652 bool q = false;
0971de7f 4653
f999f4c1 4654 spin_lock_irqsave(&vha->work_lock, flags);
e315cd28 4655 list_add_tail(&e->list, &vha->work_list);
9b3e0f4d
QT		 4656
4657 if (!test_and_set_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags))
4658 q = true;
4659
f999f4c1 4660 spin_unlock_irqrestore(&vha->work_lock, flags);
ec7193e2 4661
9b3e0f4d
QT		 4662 if (q)
4663 queue_work(vha->hw->wq, &vha->iocb_work);
f999f4c1 4664
0971de7f
AV		 4665 return QLA_SUCCESS;
4666}
4667
4668int
e315cd28 4669qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code,
0971de7f
AV		 4670 u32 data)
4671{
4672 struct qla_work_evt *e;
4673
f999f4c1 4674 e = qla2x00_alloc_work(vha, QLA_EVT_AEN);
0971de7f
AV		 4675 if (!e)
4676 return QLA_FUNCTION_FAILED;
4677
4678 e->u.aen.code = code;
4679 e->u.aen.data = data;
f999f4c1 4680 return qla2x00_post_work(vha, e);
0971de7f
AV		 4681}
4682
8a659571
AV		 4683int
4684qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb)
4685{
4686 struct qla_work_evt *e;
4687
f999f4c1 4688 e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK);
8a659571
AV		 4689 if (!e)
4690 return QLA_FUNCTION_FAILED;
4691
4692 memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t));
f999f4c1 4693 return qla2x00_post_work(vha, e);
8a659571
AV		 4694}
4695
ac280b67
AV		 4696#define qla2x00_post_async_work(name, type) \
4697int qla2x00_post_async_##name##_work( \
4698 struct scsi_qla_host *vha, \
4699 fc_port_t *fcport, uint16_t *data) \
4700{ \
4701 struct qla_work_evt *e; \
4702 \
4703 e = qla2x00_alloc_work(vha, type); \
4704 if (!e) \
4705 return QLA_FUNCTION_FAILED; \
4706 \
4707 e->u.logio.fcport = fcport; \
4708 if (data) { \
4709 e->u.logio.data[0] = data[0]; \
4710 e->u.logio.data[1] = data[1]; \
4711 } \
6d674927 4712 fcport->flags |= FCF_ASYNC_ACTIVE; \
ac280b67
AV		 4713 return qla2x00_post_work(vha, e); \
4714}
4715
4716qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN);
ac280b67
AV		 4717qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT);
4718qla2x00_post_async_work(logout_done, QLA_EVT_ASYNC_LOGOUT_DONE);
5ff1d584
AV		 4719qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC);
4720qla2x00_post_async_work(adisc_done, QLA_EVT_ASYNC_ADISC_DONE);
11aea16a
QT		 4721qla2x00_post_async_work(prlo, QLA_EVT_ASYNC_PRLO);
4722qla2x00_post_async_work(prlo_done, QLA_EVT_ASYNC_PRLO_DONE);
ac280b67 4723
3420d36c
AV		 4724int
4725qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code)
4726{
4727 struct qla_work_evt *e;
4728
4729 e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT);
4730 if (!e)
4731 return QLA_FUNCTION_FAILED;
4732
4733 e->u.uevent.code = code;
4734 return qla2x00_post_work(vha, e);
4735}
4736
4737static void
4738qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code)
4739{
4740 char event_string[40];
4741 char *envp[] = { event_string, NULL };
4742
4743 switch (code) {
4744 case QLA_UEVENT_CODE_FW_DUMP:
4745 snprintf(event_string, sizeof(event_string), "FW_DUMP=%ld",
4746 vha->host_no);
4747 break;
4748 default:
4749 /* do nothing */
4750 break;
4751 }
4752 kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp);
4753}
4754
8ae6d9c7
GM		 4755int
4756qlafx00_post_aenfx_work(struct scsi_qla_host *vha, uint32_t evtcode,
4757 uint32_t *data, int cnt)
4758{
4759 struct qla_work_evt *e;
4760
4761 e = qla2x00_alloc_work(vha, QLA_EVT_AENFX);
4762 if (!e)
4763 return QLA_FUNCTION_FAILED;
4764
4765 e->u.aenfx.evtcode = evtcode;
4766 e->u.aenfx.count = cnt;
4767 memcpy(e->u.aenfx.mbx, data, sizeof(*data) * cnt);
4768 return qla2x00_post_work(vha, e);
4769}
4770
726b8548
QT		 4771int qla24xx_post_upd_fcport_work(struct scsi_qla_host *vha, fc_port_t *fcport)
4772{
4773 struct qla_work_evt *e;
4774
4775 e = qla2x00_alloc_work(vha, QLA_EVT_UPD_FCPORT);
4776 if (!e)
4777 return QLA_FUNCTION_FAILED;
4778
4779 e->u.fcport.fcport = fcport;
4780 return qla2x00_post_work(vha, e);
4781}
4782
4783static
4784void qla24xx_create_new_sess(struct scsi_qla_host *vha, struct qla_work_evt *e)
4785{
4786 unsigned long flags;
b5d15312 4787 fc_port_t *fcport = NULL, *tfcp;
726b8548
QT		 4788 struct qlt_plogi_ack_t *pla =
4789 (struct qlt_plogi_ack_t *)e->u.new_sess.pla;
b5d15312 4790 uint8_t free_fcport = 0;
a4239945 4791 u64 wwn;
726b8548 4792
9cd883f0
QT		 4793 ql_dbg(ql_dbg_disc, vha, 0xffff,
4794 "%s %d %8phC enter\n",
4795 __func__, __LINE__, e->u.new_sess.port_name);
4796
726b8548
QT		 4797 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
4798 fcport = qla2x00_find_fcport_by_wwpn(vha, e->u.new_sess.port_name, 1);
4799 if (fcport) {
4800 fcport->d_id = e->u.new_sess.id;
4801 if (pla) {
4802 fcport->fw_login_state = DSC_LS_PLOGI_PEND;
9b3e0f4d
QT		 4803 memcpy(fcport->node_name,
4804 pla->iocb.u.isp24.u.plogi.node_name,
4805 WWN_SIZE);
726b8548
QT		 4806 qlt_plogi_ack_link(vha, pla, fcport, QLT_PLOGI_LINK_SAME_WWN);
4807 /* we took an extra ref_count to prevent PLOGI ACK when
4808 * fcport/sess has not been created.
4809 */
4810 pla->ref_count--;
4811 }
4812 } else {
b5d15312 4813 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
726b8548
QT		 4814 fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
4815 if (fcport) {
4816 fcport->d_id = e->u.new_sess.id;
726b8548
QT		 4817 fcport->flags |= FCF_FABRIC_DEVICE;
4818 fcport->fw_login_state = DSC_LS_PLOGI_PEND;
33b28357 4819 if (e->u.new_sess.fc4_type & FS_FC4TYPE_FCP)
a4239945 4820 fcport->fc4_type = FC4_TYPE_FCP_SCSI;
726b8548 4821
33b28357 4822 if (e->u.new_sess.fc4_type & FS_FC4TYPE_NVME) {
2b5b9647
DT		 4823 fcport->fc4_type = FC4_TYPE_OTHER;
4824 fcport->fc4f_nvme = FC4_TYPE_NVME;
4825 }
33b28357 4826
726b8548
QT		 4827 memcpy(fcport->port_name, e->u.new_sess.port_name,
4828 WWN_SIZE);
b5d15312
QT		 4829 } else {
4830 ql_dbg(ql_dbg_disc, vha, 0xffff,
4831 "%s %8phC mem alloc fail.\n",
4832 __func__, e->u.new_sess.port_name);
4833
4834 if (pla)
4835 kmem_cache_free(qla_tgt_plogi_cachep, pla);
4836 return;
4837 }
4838
4839 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
a4239945 4840 /* search again to make sure no one else got ahead */
b5d15312
QT		 4841 tfcp = qla2x00_find_fcport_by_wwpn(vha,
4842 e->u.new_sess.port_name, 1);
4843 if (tfcp) {
4844 /* should rarily happen */
4845 ql_dbg(ql_dbg_disc, vha, 0xffff,
4846 "%s %8phC found existing fcport b4 add. DS %d LS %d\n",
4847 __func__, tfcp->port_name, tfcp->disc_state,
4848 tfcp->fw_login_state);
4849
4850 free_fcport = 1;
4851 } else {
726b8548
QT		 4852 list_add_tail(&fcport->list, &vha->vp_fcports);
4853
19759033
QT		 4854 }
4855 if (pla) {
4856 qlt_plogi_ack_link(vha, pla, fcport,
4857 QLT_PLOGI_LINK_SAME_WWN);
4858 pla->ref_count--;
726b8548
QT		 4859 }
4860 }
4861 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
4862
4863 if (fcport) {
9cd883f0
QT		 4864 if (N2N_TOPO(vha->hw))
4865 fcport->flags &= ~FCF_FABRIC_DEVICE;
4866
a4239945
QT		 4867 fcport->id_changed = 1;
4868 fcport->scan_state = QLA_FCPORT_FOUND;
4869 memcpy(fcport->node_name, e->u.new_sess.node_name, WWN_SIZE);
4870
5ef696aa 4871 if (pla) {
9cd883f0
QT		 4872 if (pla->iocb.u.isp24.status_subcode == ELS_PRLI) {
4873 u16 wd3_lo;
4874
4875 fcport->fw_login_state = DSC_LS_PRLI_PEND;
4876 fcport->local = 0;
4877 fcport->loop_id =
4878 le16_to_cpu(
4879 pla->iocb.u.isp24.nport_handle);
4880 fcport->fw_login_state = DSC_LS_PRLI_PEND;
4881 wd3_lo =
4882 le16_to_cpu(
4883 pla->iocb.u.isp24.u.prli.wd3_lo);
4884
4885 if (wd3_lo & BIT_7)
4886 fcport->conf_compl_supported = 1;
4887
4888 if ((wd3_lo & BIT_4) == 0)
4889 fcport->port_type = FCT_INITIATOR;
4890 else
4891 fcport->port_type = FCT_TARGET;
4892 }
726b8548 4893 qlt_plogi_ack_unref(vha, pla);
5ef696aa 4894 } else {
1c6cacf4
HR		 4895 fc_port_t *dfcp = NULL;
4896
5ef696aa
QT		 4897 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
4898 tfcp = qla2x00_find_fcport_by_nportid(vha,
4899 &e->u.new_sess.id, 1);
4900 if (tfcp && (tfcp != fcport)) {
4901 /*
4902 * We have a conflict fcport with same NportID.
4903 */
4904 ql_dbg(ql_dbg_disc, vha, 0xffff,
4905 "%s %8phC found conflict b4 add. DS %d LS %d\n",
4906 __func__, tfcp->port_name, tfcp->disc_state,
4907 tfcp->fw_login_state);
4908
4909 switch (tfcp->disc_state) {
4910 case DSC_DELETED:
4911 break;
4912 case DSC_DELETE_PEND:
4913 fcport->login_pause = 1;
4914 tfcp->conflict = fcport;
4915 break;
4916 default:
4917 fcport->login_pause = 1;
4918 tfcp->conflict = fcport;
1c6cacf4 4919 dfcp = tfcp;
5ef696aa
QT		 4920 break;
4921 }
4922 }
4923 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
1c6cacf4
HR		 4924 if (dfcp)
4925 qlt_schedule_sess_for_deletion(tfcp);
a4239945
QT		 4926
4927 wwn = wwn_to_u64(fcport->node_name);
4928
4929 if (!wwn)
4930 qla24xx_async_gnnid(vha, fcport);
4931 else
4932 qla24xx_async_gnl(vha, fcport);
5ef696aa 4933 }
726b8548 4934 }
b5d15312
QT		 4935
4936 if (free_fcport) {
4937 qla2x00_free_fcport(fcport);
4938 if (pla)
4939 kmem_cache_free(qla_tgt_plogi_cachep, pla);
4940 }
726b8548
QT		 4941}
4942
e374f9f5
QT		 4943static void qla_sp_retry(struct scsi_qla_host *vha, struct qla_work_evt *e)
4944{
4945 struct srb *sp = e->u.iosb.sp;
4946 int rval;
4947
4948 rval = qla2x00_start_sp(sp);
4949 if (rval != QLA_SUCCESS) {
4950 ql_dbg(ql_dbg_disc, vha, 0x2043,
4951 "%s: %s: Re-issue IOCB failed (%d).\n",
4952 __func__, sp->name, rval);
4953 qla24xx_sp_unmap(vha, sp);
4954 }
4955}
4956
ac280b67 4957void
e315cd28 4958qla2x00_do_work(struct scsi_qla_host *vha)
0971de7f 4959{
f999f4c1
AV		 4960 struct qla_work_evt *e, *tmp;
4961 unsigned long flags;
4962 LIST_HEAD(work);
0971de7f 4963
f999f4c1
AV		 4964 spin_lock_irqsave(&vha->work_lock, flags);
4965 list_splice_init(&vha->work_list, &work);
4966 spin_unlock_irqrestore(&vha->work_lock, flags);
4967
4968 list_for_each_entry_safe(e, tmp, &work, list) {
0971de7f 4969 list_del_init(&e->list);
0971de7f
AV		 4970
4971 switch (e->type) {
4972 case QLA_EVT_AEN:
e315cd28 4973 fc_host_post_event(vha->host, fc_get_event_number(),
0971de7f
AV		 4974 e->u.aen.code, e->u.aen.data);
4975 break;
8a659571
AV		 4976 case QLA_EVT_IDC_ACK:
4977 qla81xx_idc_ack(vha, e->u.idc_ack.mb);
4978 break;
ac280b67
AV		 4979 case QLA_EVT_ASYNC_LOGIN:
4980 qla2x00_async_login(vha, e->u.logio.fcport,
4981 e->u.logio.data);
4982 break;
ac280b67
AV		 4983 case QLA_EVT_ASYNC_LOGOUT:
4984 qla2x00_async_logout(vha, e->u.logio.fcport);
4985 break;
4986 case QLA_EVT_ASYNC_LOGOUT_DONE:
4987 qla2x00_async_logout_done(vha, e->u.logio.fcport,
4988 e->u.logio.data);
4989 break;
5ff1d584
AV		 4990 case QLA_EVT_ASYNC_ADISC:
4991 qla2x00_async_adisc(vha, e->u.logio.fcport,
4992 e->u.logio.data);
4993 break;
4994 case QLA_EVT_ASYNC_ADISC_DONE:
4995 qla2x00_async_adisc_done(vha, e->u.logio.fcport,
4996 e->u.logio.data);
4997 break;
3420d36c
AV		 4998 case QLA_EVT_UEVENT:
4999 qla2x00_uevent_emit(vha, e->u.uevent.code);
5000 break;
8ae6d9c7
GM		 5001 case QLA_EVT_AENFX:
5002 qlafx00_process_aen(vha, e);
5003 break;
726b8548
QT		 5004 case QLA_EVT_GIDPN:
5005 qla24xx_async_gidpn(vha, e->u.fcport.fcport);
5006 break;
5007 case QLA_EVT_GPNID:
5008 qla24xx_async_gpnid(vha, &e->u.gpnid.id);
5009 break;
e374f9f5
QT		 5010 case QLA_EVT_UNMAP:
5011 qla24xx_sp_unmap(vha, e->u.iosb.sp);
726b8548 5012 break;
9b3e0f4d
QT		 5013 case QLA_EVT_RELOGIN:
5014 qla2x00_relogin(vha);
5015 break;
726b8548
QT		 5016 case QLA_EVT_NEW_SESS:
5017 qla24xx_create_new_sess(vha, e);
5018 break;
5019 case QLA_EVT_GPDB:
5020 qla24xx_async_gpdb(vha, e->u.fcport.fcport,
5021 e->u.fcport.opt);
5022 break;
a5d42f4c
DG		 5023 case QLA_EVT_PRLI:
5024 qla24xx_async_prli(vha, e->u.fcport.fcport);
5025 break;
726b8548
QT		 5026 case QLA_EVT_GPSC:
5027 qla24xx_async_gpsc(vha, e->u.fcport.fcport);
5028 break;
5029 case QLA_EVT_UPD_FCPORT:
5030 qla2x00_update_fcport(vha, e->u.fcport.fcport);
5031 break;
5032 case QLA_EVT_GNL:
5033 qla24xx_async_gnl(vha, e->u.fcport.fcport);
5034 break;
5035 case QLA_EVT_NACK:
5036 qla24xx_do_nack_work(vha, e);
5037 break;
11aea16a
QT		 5038 case QLA_EVT_ASYNC_PRLO:
5039 qla2x00_async_prlo(vha, e->u.logio.fcport);
5040 break;
5041 case QLA_EVT_ASYNC_PRLO_DONE:
5042 qla2x00_async_prlo_done(vha, e->u.logio.fcport,
5043 e->u.logio.data);
5044 break;
a4239945 5045 case QLA_EVT_GPNFT:
33b28357
QT		 5046 qla24xx_async_gpnft(vha, e->u.gpnft.fc4_type,
5047 e->u.gpnft.sp);
a4239945
QT		 5048 break;
5049 case QLA_EVT_GPNFT_DONE:
5050 qla24xx_async_gpnft_done(vha, e->u.iosb.sp);
5051 break;
5052 case QLA_EVT_GNNFT_DONE:
5053 qla24xx_async_gnnft_done(vha, e->u.iosb.sp);
5054 break;
5055 case QLA_EVT_GNNID:
5056 qla24xx_async_gnnid(vha, e->u.fcport.fcport);
5057 break;
5058 case QLA_EVT_GFPNID:
5059 qla24xx_async_gfpnid(vha, e->u.fcport.fcport);
5060 break;
e374f9f5
QT		 5061 case QLA_EVT_SP_RETRY:
5062 qla_sp_retry(vha, e);
cc28e0ac
QT		 5063 break;
5064 case QLA_EVT_IIDMA:
5065 qla_do_iidma_work(vha, e->u.fcport.fcport);
5066 break;
0971de7f
AV		 5067 }
5068 if (e->flags & QLA_EVT_FLAG_FREE)
5069 kfree(e);
feafb7b1
AE		 5070
5071 /* For each work completed decrement vha ref count */
5072 QLA_VHA_MARK_NOT_BUSY(vha);
e315cd28 5073 }
e315cd28 5074}
f999f4c1 5075
9b3e0f4d
QT		 5076int qla24xx_post_relogin_work(struct scsi_qla_host *vha)
5077{
5078 struct qla_work_evt *e;
5079
5080 e = qla2x00_alloc_work(vha, QLA_EVT_RELOGIN);
5081
5082 if (!e) {
5083 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
5084 return QLA_FUNCTION_FAILED;
5085 }
5086
5087 return qla2x00_post_work(vha, e);
5088}
5089
e315cd28
AC		 5090/* Relogins all the fcports of a vport
5091 * Context: dpc thread
5092 */
5093void qla2x00_relogin(struct scsi_qla_host *vha)
5094{
5095 fc_port_t *fcport;
23dd98a6 5096 int status, relogin_needed = 0;
726b8548 5097 struct event_arg ea;
e315cd28
AC		 5098
5099 list_for_each_entry(fcport, &vha->vp_fcports, list) {
9cd883f0
QT		 5100 /*
5101 * If the port is not ONLINE then try to login
5102 * to it if we haven't run out of retries.
5103 */
5ff1d584 5104 if (atomic_read(&fcport->state) != FCS_ONLINE &&
23dd98a6
QT		 5105 fcport->login_retry) {
5106 if (fcport->scan_state != QLA_FCPORT_FOUND ||
5107 fcport->disc_state == DSC_LOGIN_COMPLETE)
5108 continue;
e315cd28 5109
23dd98a6
QT		 5110 if (fcport->flags & (FCF_ASYNC_SENT|FCF_ASYNC_ACTIVE) ||
5111 fcport->disc_state == DSC_DELETE_PEND) {
5112 relogin_needed = 1;
5113 } else {
5114 if (vha->hw->current_topology != ISP_CFG_NL) {
5115 memset(&ea, 0, sizeof(ea));
5116 ea.event = FCME_RELOGIN;
5117 ea.fcport = fcport;
5118 qla2x00_fcport_event_handler(vha, &ea);
5119 } else if (vha->hw->current_topology ==
5120 ISP_CFG_NL) {
5121 fcport->login_retry--;
5122 status =
5123 qla2x00_local_device_login(vha,
5124 fcport);
5125 if (status == QLA_SUCCESS) {
5126 fcport->old_loop_id =
5127 fcport->loop_id;
5128 ql_dbg(ql_dbg_disc, vha, 0x2003,
5129 "Port login OK: logged in ID 0x%x.\n",
5130 fcport->loop_id);
5131 qla2x00_update_fcport
5132 (vha, fcport);
5133 } else if (status == 1) {
5134 set_bit(RELOGIN_NEEDED,
5135 &vha->dpc_flags);
5136 /* retry the login again */
5137 ql_dbg(ql_dbg_disc, vha, 0x2007,
5138 "Retrying %d login again loop_id 0x%x.\n",
5139 fcport->login_retry,
5140 fcport->loop_id);
5141 } else {
5142 fcport->login_retry = 0;
5143 }
5144
5145 if (fcport->login_retry == 0 &&
5146 status != QLA_SUCCESS)
5147 qla2x00_clear_loop_id(fcport);
5148 }
e315cd28 5149 }
e315cd28
AC		 5150 }
5151 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
5152 break;
0971de7f 5153 }
9b3e0f4d 5154
23dd98a6
QT		 5155 if (relogin_needed)
5156 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
5157
9b3e0f4d
QT		 5158 ql_dbg(ql_dbg_disc, vha, 0x400e,
5159 "Relogin end.\n");
0971de7f
AV		 5160}
5161
7d613ac6
SV		 5162/* Schedule work on any of the dpc-workqueues */
5163void
5164qla83xx_schedule_work(scsi_qla_host_t *base_vha, int work_code)
5165{
5166 struct qla_hw_data *ha = base_vha->hw;
5167
5168 switch (work_code) {
5169 case MBA_IDC_AEN: /* 0x8200 */
5170 if (ha->dpc_lp_wq)
5171 queue_work(ha->dpc_lp_wq, &ha->idc_aen);
5172 break;
5173
5174 case QLA83XX_NIC_CORE_RESET: /* 0x1 */
5175 if (!ha->flags.nic_core_reset_hdlr_active) {
5176 if (ha->dpc_hp_wq)
5177 queue_work(ha->dpc_hp_wq, &ha->nic_core_reset);
5178 } else
5179 ql_dbg(ql_dbg_p3p, base_vha, 0xb05e,
5180 "NIC Core reset is already active. Skip "
5181 "scheduling it again.\n");
5182 break;
5183 case QLA83XX_IDC_STATE_HANDLER: /* 0x2 */
5184 if (ha->dpc_hp_wq)
5185 queue_work(ha->dpc_hp_wq, &ha->idc_state_handler);
5186 break;
5187 case QLA83XX_NIC_CORE_UNRECOVERABLE: /* 0x3 */
5188 if (ha->dpc_hp_wq)
5189 queue_work(ha->dpc_hp_wq, &ha->nic_core_unrecoverable);
5190 break;
5191 default:
5192 ql_log(ql_log_warn, base_vha, 0xb05f,
d939be3a 5193 "Unknown work-code=0x%x.\n", work_code);
7d613ac6
SV		 5194 }
5195
5196 return;
5197}
5198
5199/* Work: Perform NIC Core Unrecoverable state handling */
5200void
5201qla83xx_nic_core_unrecoverable_work(struct work_struct *work)
5202{
5203 struct qla_hw_data *ha =
2ad1b67c 5204 container_of(work, struct qla_hw_data, nic_core_unrecoverable);
7d613ac6
SV		 5205 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5206 uint32_t dev_state = 0;
5207
5208 qla83xx_idc_lock(base_vha, 0);
5209 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
5210 qla83xx_reset_ownership(base_vha);
5211 if (ha->flags.nic_core_reset_owner) {
5212 ha->flags.nic_core_reset_owner = 0;
5213 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
5214 QLA8XXX_DEV_FAILED);
5215 ql_log(ql_log_info, base_vha, 0xb060, "HW State: FAILED.\n");
5216 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
5217 }
5218 qla83xx_idc_unlock(base_vha, 0);
5219}
5220
5221/* Work: Execute IDC state handler */
5222void
5223qla83xx_idc_state_handler_work(struct work_struct *work)
5224{
5225 struct qla_hw_data *ha =
2ad1b67c 5226 container_of(work, struct qla_hw_data, idc_state_handler);
7d613ac6
SV		 5227 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5228 uint32_t dev_state = 0;
5229
5230 qla83xx_idc_lock(base_vha, 0);
5231 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
5232 if (dev_state == QLA8XXX_DEV_FAILED ||
5233 dev_state == QLA8XXX_DEV_NEED_QUIESCENT)
5234 qla83xx_idc_state_handler(base_vha);
5235 qla83xx_idc_unlock(base_vha, 0);
5236}
5237
fa492630 5238static int
7d613ac6
SV		 5239qla83xx_check_nic_core_fw_alive(scsi_qla_host_t *base_vha)
5240{
5241 int rval = QLA_SUCCESS;
5242 unsigned long heart_beat_wait = jiffies + (1 * HZ);
5243 uint32_t heart_beat_counter1, heart_beat_counter2;
5244
5245 do {
5246 if (time_after(jiffies, heart_beat_wait)) {
5247 ql_dbg(ql_dbg_p3p, base_vha, 0xb07c,
5248 "Nic Core f/w is not alive.\n");
5249 rval = QLA_FUNCTION_FAILED;
5250 break;
5251 }
5252
5253 qla83xx_idc_lock(base_vha, 0);
5254 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
5255 &heart_beat_counter1);
5256 qla83xx_idc_unlock(base_vha, 0);
5257 msleep(100);
5258 qla83xx_idc_lock(base_vha, 0);
5259 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
5260 &heart_beat_counter2);
5261 qla83xx_idc_unlock(base_vha, 0);
5262 } while (heart_beat_counter1 == heart_beat_counter2);
5263
5264 return rval;
5265}
5266
5267/* Work: Perform NIC Core Reset handling */
5268void
5269qla83xx_nic_core_reset_work(struct work_struct *work)
5270{
5271 struct qla_hw_data *ha =
5272 container_of(work, struct qla_hw_data, nic_core_reset);
5273 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5274 uint32_t dev_state = 0;
5275
81178772
SK		 5276 if (IS_QLA2031(ha)) {
5277 if (qla2xxx_mctp_dump(base_vha) != QLA_SUCCESS)
5278 ql_log(ql_log_warn, base_vha, 0xb081,
5279 "Failed to dump mctp\n");
5280 return;
5281 }
5282
7d613ac6
SV		 5283 if (!ha->flags.nic_core_reset_hdlr_active) {
5284 if (qla83xx_check_nic_core_fw_alive(base_vha) == QLA_SUCCESS) {
5285 qla83xx_idc_lock(base_vha, 0);
5286 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE,
5287 &dev_state);
5288 qla83xx_idc_unlock(base_vha, 0);
5289 if (dev_state != QLA8XXX_DEV_NEED_RESET) {
5290 ql_dbg(ql_dbg_p3p, base_vha, 0xb07a,
5291 "Nic Core f/w is alive.\n");
5292 return;
5293 }
5294 }
5295
5296 ha->flags.nic_core_reset_hdlr_active = 1;
5297 if (qla83xx_nic_core_reset(base_vha)) {
5298 /* NIC Core reset failed. */
5299 ql_dbg(ql_dbg_p3p, base_vha, 0xb061,
5300 "NIC Core reset failed.\n");
5301 }
5302 ha->flags.nic_core_reset_hdlr_active = 0;
5303 }
5304}
5305
5306/* Work: Handle 8200 IDC aens */
5307void
5308qla83xx_service_idc_aen(struct work_struct *work)
5309{
5310 struct qla_hw_data *ha =
5311 container_of(work, struct qla_hw_data, idc_aen);
5312 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5313 uint32_t dev_state, idc_control;
5314
5315 qla83xx_idc_lock(base_vha, 0);
5316 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
5317 qla83xx_rd_reg(base_vha, QLA83XX_IDC_CONTROL, &idc_control);
5318 qla83xx_idc_unlock(base_vha, 0);
5319 if (dev_state == QLA8XXX_DEV_NEED_RESET) {
5320 if (idc_control & QLA83XX_IDC_GRACEFUL_RESET) {
5321 ql_dbg(ql_dbg_p3p, base_vha, 0xb062,
5322 "Application requested NIC Core Reset.\n");
5323 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
5324 } else if (qla83xx_check_nic_core_fw_alive(base_vha) ==
5325 QLA_SUCCESS) {
5326 ql_dbg(ql_dbg_p3p, base_vha, 0xb07b,
5327 "Other protocol driver requested NIC Core Reset.\n");
5328 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
5329 }
5330 } else if (dev_state == QLA8XXX_DEV_FAILED ||
5331 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) {
5332 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
5333 }
5334}
5335
5336static void
5337qla83xx_wait_logic(void)
5338{
5339 int i;
5340
5341 /* Yield CPU */
5342 if (!in_interrupt()) {
5343 /*
5344 * Wait about 200ms before retrying again.
5345 * This controls the number of retries for single
5346 * lock operation.
5347 */
5348 msleep(100);
5349 schedule();
5350 } else {
5351 for (i = 0; i < 20; i++)
5352 cpu_relax(); /* This a nop instr on i386 */
5353 }
5354}
5355
fa492630 5356static int
7d613ac6
SV		 5357qla83xx_force_lock_recovery(scsi_qla_host_t *base_vha)
5358{
5359 int rval;
5360 uint32_t data;
5361 uint32_t idc_lck_rcvry_stage_mask = 0x3;
5362 uint32_t idc_lck_rcvry_owner_mask = 0x3c;
5363 struct qla_hw_data *ha = base_vha->hw;
6c315553
SK		 5364 ql_dbg(ql_dbg_p3p, base_vha, 0xb086,
5365 "Trying force recovery of the IDC lock.\n");
7d613ac6
SV		 5366
5367 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, &data);
5368 if (rval)
5369 return rval;
5370
5371 if ((data & idc_lck_rcvry_stage_mask) > 0) {
5372 return QLA_SUCCESS;
5373 } else {
5374 data = (IDC_LOCK_RECOVERY_STAGE1) | (ha->portnum << 2);
5375 rval = qla83xx_wr_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
5376 data);
5377 if (rval)
5378 return rval;
5379
5380 msleep(200);
5381
5382 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
5383 &data);
5384 if (rval)
5385 return rval;
5386
5387 if (((data & idc_lck_rcvry_owner_mask) >> 2) == ha->portnum) {
5388 data &= (IDC_LOCK_RECOVERY_STAGE2 |
5389 ~(idc_lck_rcvry_stage_mask));
5390 rval = qla83xx_wr_reg(base_vha,
5391 QLA83XX_IDC_LOCK_RECOVERY, data);
5392 if (rval)
5393 return rval;
5394
5395 /* Forcefully perform IDC UnLock */
5396 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK,
5397 &data);
5398 if (rval)
5399 return rval;
5400 /* Clear lock-id by setting 0xff */
5401 rval = qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
5402 0xff);
5403 if (rval)
5404 return rval;
5405 /* Clear lock-recovery by setting 0x0 */
5406 rval = qla83xx_wr_reg(base_vha,
5407 QLA83XX_IDC_LOCK_RECOVERY, 0x0);
5408 if (rval)
5409 return rval;
5410 } else
5411 return QLA_SUCCESS;
5412 }
5413
5414 return rval;
5415}
5416
fa492630 5417static int
7d613ac6
SV		 5418qla83xx_idc_lock_recovery(scsi_qla_host_t *base_vha)
5419{
5420 int rval = QLA_SUCCESS;
5421 uint32_t o_drv_lockid, n_drv_lockid;
5422 unsigned long lock_recovery_timeout;
5423
5424 lock_recovery_timeout = jiffies + QLA83XX_MAX_LOCK_RECOVERY_WAIT;
5425retry_lockid:
5426 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &o_drv_lockid);
5427 if (rval)
5428 goto exit;
5429
5430 /* MAX wait time before forcing IDC Lock recovery = 2 secs */
5431 if (time_after_eq(jiffies, lock_recovery_timeout)) {
5432 if (qla83xx_force_lock_recovery(base_vha) == QLA_SUCCESS)
5433 return QLA_SUCCESS;
5434 else
5435 return QLA_FUNCTION_FAILED;
5436 }
5437
5438 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &n_drv_lockid);
5439 if (rval)
5440 goto exit;
5441
5442 if (o_drv_lockid == n_drv_lockid) {
5443 qla83xx_wait_logic();
5444 goto retry_lockid;
5445 } else
5446 return QLA_SUCCESS;
5447
5448exit:
5449 return rval;
5450}
5451
5452void
5453qla83xx_idc_lock(scsi_qla_host_t *base_vha, uint16_t requester_id)
5454{
5455 uint16_t options = (requester_id << 15) | BIT_6;
5456 uint32_t data;
6c315553 5457 uint32_t lock_owner;
7d613ac6
SV		 5458 struct qla_hw_data *ha = base_vha->hw;
5459
5460 /* IDC-lock implementation using driver-lock/lock-id remote registers */
5461retry_lock:
5462 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCK, &data)
5463 == QLA_SUCCESS) {
5464 if (data) {
5465 /* Setting lock-id to our function-number */
5466 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
5467 ha->portnum);
5468 } else {
6c315553
SK		 5469 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID,
5470 &lock_owner);
7d613ac6 5471 ql_dbg(ql_dbg_p3p, base_vha, 0xb063,
6c315553
SK		 5472 "Failed to acquire IDC lock, acquired by %d, "
5473 "retrying...\n", lock_owner);
7d613ac6
SV		 5474
5475 /* Retry/Perform IDC-Lock recovery */
5476 if (qla83xx_idc_lock_recovery(base_vha)
5477 == QLA_SUCCESS) {
5478 qla83xx_wait_logic();
5479 goto retry_lock;
5480 } else
5481 ql_log(ql_log_warn, base_vha, 0xb075,
5482 "IDC Lock recovery FAILED.\n");
5483 }
5484
5485 }
5486
5487 return;
5488
5489 /* XXX: IDC-lock implementation using access-control mbx */
5490retry_lock2:
5491 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
5492 ql_dbg(ql_dbg_p3p, base_vha, 0xb072,
5493 "Failed to acquire IDC lock. retrying...\n");
5494 /* Retry/Perform IDC-Lock recovery */
5495 if (qla83xx_idc_lock_recovery(base_vha) == QLA_SUCCESS) {
5496 qla83xx_wait_logic();
5497 goto retry_lock2;
5498 } else
5499 ql_log(ql_log_warn, base_vha, 0xb076,
5500 "IDC Lock recovery FAILED.\n");
5501 }
5502
5503 return;
5504}
5505
5506void
5507qla83xx_idc_unlock(scsi_qla_host_t *base_vha, uint16_t requester_id)
5508{
5897cb2f
BVA		 5509#if 0
5510 uint16_t options = (requester_id << 15) | BIT_7;
5511#endif
5512 uint16_t retry;
7d613ac6
SV		 5513 uint32_t data;
5514 struct qla_hw_data *ha = base_vha->hw;
5515
5516 /* IDC-unlock implementation using driver-unlock/lock-id
5517 * remote registers
5518 */
5519 retry = 0;
5520retry_unlock:
5521 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &data)
5522 == QLA_SUCCESS) {
5523 if (data == ha->portnum) {
5524 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, &data);
5525 /* Clearing lock-id by setting 0xff */
5526 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 0xff);
5527 } else if (retry < 10) {
5528 /* SV: XXX: IDC unlock retrying needed here? */
5529
5530 /* Retry for IDC-unlock */
5531 qla83xx_wait_logic();
5532 retry++;
5533 ql_dbg(ql_dbg_p3p, base_vha, 0xb064,
ee6a8773 5534 "Failed to release IDC lock, retrying=%d\n", retry);
7d613ac6
SV		 5535 goto retry_unlock;
5536 }
5537 } else if (retry < 10) {
5538 /* Retry for IDC-unlock */
5539 qla83xx_wait_logic();
5540 retry++;
5541 ql_dbg(ql_dbg_p3p, base_vha, 0xb065,
ee6a8773 5542 "Failed to read drv-lockid, retrying=%d\n", retry);
7d613ac6
SV		 5543 goto retry_unlock;
5544 }
5545
5546 return;
5547
5897cb2f 5548#if 0
7d613ac6
SV		 5549 /* XXX: IDC-unlock implementation using access-control mbx */
5550 retry = 0;
5551retry_unlock2:
5552 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
5553 if (retry < 10) {
5554 /* Retry for IDC-unlock */
5555 qla83xx_wait_logic();
5556 retry++;
5557 ql_dbg(ql_dbg_p3p, base_vha, 0xb066,
ee6a8773 5558 "Failed to release IDC lock, retrying=%d\n", retry);
7d613ac6
SV		 5559 goto retry_unlock2;
5560 }
5561 }
5562
5563 return;
5897cb2f 5564#endif
7d613ac6
SV		 5565}
5566
5567int
5568__qla83xx_set_drv_presence(scsi_qla_host_t *vha)
5569{
5570 int rval = QLA_SUCCESS;
5571 struct qla_hw_data *ha = vha->hw;
5572 uint32_t drv_presence;
5573
5574 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
5575 if (rval == QLA_SUCCESS) {
5576 drv_presence |= (1 << ha->portnum);
5577 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
5578 drv_presence);
5579 }
5580
5581 return rval;
5582}
5583
5584int
5585qla83xx_set_drv_presence(scsi_qla_host_t *vha)
5586{
5587 int rval = QLA_SUCCESS;
5588
5589 qla83xx_idc_lock(vha, 0);
5590 rval = __qla83xx_set_drv_presence(vha);
5591 qla83xx_idc_unlock(vha, 0);
5592
5593 return rval;
5594}
5595
5596int
5597__qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
5598{
5599 int rval = QLA_SUCCESS;
5600 struct qla_hw_data *ha = vha->hw;
5601 uint32_t drv_presence;
5602
5603 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
5604 if (rval == QLA_SUCCESS) {
5605 drv_presence &= ~(1 << ha->portnum);
5606 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
5607 drv_presence);
5608 }
5609
5610 return rval;
5611}
5612
5613int
5614qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
5615{
5616 int rval = QLA_SUCCESS;
5617
5618 qla83xx_idc_lock(vha, 0);
5619 rval = __qla83xx_clear_drv_presence(vha);
5620 qla83xx_idc_unlock(vha, 0);
5621
5622 return rval;
5623}
5624
fa492630 5625static void
7d613ac6
SV		 5626qla83xx_need_reset_handler(scsi_qla_host_t *vha)
5627{
5628 struct qla_hw_data *ha = vha->hw;
5629 uint32_t drv_ack, drv_presence;
5630 unsigned long ack_timeout;
5631
5632 /* Wait for IDC ACK from all functions (DRV-ACK == DRV-PRESENCE) */
5633 ack_timeout = jiffies + (ha->fcoe_reset_timeout * HZ);
5634 while (1) {
5635 qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
5636 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
807fb6d8 5637 if ((drv_ack & drv_presence) == drv_presence)
7d613ac6
SV		 5638 break;
5639
5640 if (time_after_eq(jiffies, ack_timeout)) {
5641 ql_log(ql_log_warn, vha, 0xb067,
5642 "RESET ACK TIMEOUT! drv_presence=0x%x "
5643 "drv_ack=0x%x\n", drv_presence, drv_ack);
5644 /*
5645 * The function(s) which did not ack in time are forced
5646 * to withdraw any further participation in the IDC
5647 * reset.
5648 */
5649 if (drv_ack != drv_presence)
5650 qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
5651 drv_ack);
5652 break;
5653 }
5654
5655 qla83xx_idc_unlock(vha, 0);
5656 msleep(1000);
5657 qla83xx_idc_lock(vha, 0);
5658 }
5659
5660 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_COLD);
5661 ql_log(ql_log_info, vha, 0xb068, "HW State: COLD/RE-INIT.\n");
5662}
5663
fa492630 5664static int
7d613ac6
SV		 5665qla83xx_device_bootstrap(scsi_qla_host_t *vha)
5666{
5667 int rval = QLA_SUCCESS;
5668 uint32_t idc_control;
5669
5670 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_INITIALIZING);
5671 ql_log(ql_log_info, vha, 0xb069, "HW State: INITIALIZING.\n");
5672
5673 /* Clearing IDC-Control Graceful-Reset Bit before resetting f/w */
5674 __qla83xx_get_idc_control(vha, &idc_control);
5675 idc_control &= ~QLA83XX_IDC_GRACEFUL_RESET;
5676 __qla83xx_set_idc_control(vha, 0);
5677
5678 qla83xx_idc_unlock(vha, 0);
5679 rval = qla83xx_restart_nic_firmware(vha);
5680 qla83xx_idc_lock(vha, 0);
5681
5682 if (rval != QLA_SUCCESS) {
5683 ql_log(ql_log_fatal, vha, 0xb06a,
5684 "Failed to restart NIC f/w.\n");
5685 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_FAILED);
5686 ql_log(ql_log_info, vha, 0xb06b, "HW State: FAILED.\n");
5687 } else {
5688 ql_dbg(ql_dbg_p3p, vha, 0xb06c,
5689 "Success in restarting nic f/w.\n");
5690 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_READY);
5691 ql_log(ql_log_info, vha, 0xb06d, "HW State: READY.\n");
5692 }
5693
5694 return rval;
5695}
5696
5697/* Assumes idc_lock always held on entry */
5698int
5699qla83xx_idc_state_handler(scsi_qla_host_t *base_vha)
5700{
5701 struct qla_hw_data *ha = base_vha->hw;
5702 int rval = QLA_SUCCESS;
5703 unsigned long dev_init_timeout;
5704 uint32_t dev_state;
5705
5706 /* Wait for MAX-INIT-TIMEOUT for the device to go ready */
5707 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ);
5708
5709 while (1) {
5710
5711 if (time_after_eq(jiffies, dev_init_timeout)) {
5712 ql_log(ql_log_warn, base_vha, 0xb06e,
5713 "Initialization TIMEOUT!\n");
5714 /* Init timeout. Disable further NIC Core
5715 * communication.
5716 */
5717 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
5718 QLA8XXX_DEV_FAILED);
5719 ql_log(ql_log_info, base_vha, 0xb06f,
5720 "HW State: FAILED.\n");
5721 }
5722
5723 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
5724 switch (dev_state) {
5725 case QLA8XXX_DEV_READY:
5726 if (ha->flags.nic_core_reset_owner)
5727 qla83xx_idc_audit(base_vha,
5728 IDC_AUDIT_COMPLETION);
5729 ha->flags.nic_core_reset_owner = 0;
5730 ql_dbg(ql_dbg_p3p, base_vha, 0xb070,
5731 "Reset_owner reset by 0x%x.\n",
5732 ha->portnum);
5733 goto exit;
5734 case QLA8XXX_DEV_COLD:
5735 if (ha->flags.nic_core_reset_owner)
5736 rval = qla83xx_device_bootstrap(base_vha);
5737 else {
5738 /* Wait for AEN to change device-state */
5739 qla83xx_idc_unlock(base_vha, 0);
5740 msleep(1000);
5741 qla83xx_idc_lock(base_vha, 0);
5742 }
5743 break;
5744 case QLA8XXX_DEV_INITIALIZING:
5745 /* Wait for AEN to change device-state */
5746 qla83xx_idc_unlock(base_vha, 0);
5747 msleep(1000);
5748 qla83xx_idc_lock(base_vha, 0);
5749 break;
5750 case QLA8XXX_DEV_NEED_RESET:
5751 if (!ql2xdontresethba && ha->flags.nic_core_reset_owner)
5752 qla83xx_need_reset_handler(base_vha);
5753 else {
5754 /* Wait for AEN to change device-state */
5755 qla83xx_idc_unlock(base_vha, 0);
5756 msleep(1000);
5757 qla83xx_idc_lock(base_vha, 0);
5758 }
5759 /* reset timeout value after need reset handler */
5760 dev_init_timeout = jiffies +
5761 (ha->fcoe_dev_init_timeout * HZ);
5762 break;
5763 case QLA8XXX_DEV_NEED_QUIESCENT:
5764 /* XXX: DEBUG for now */
5765 qla83xx_idc_unlock(base_vha, 0);
5766 msleep(1000);
5767 qla83xx_idc_lock(base_vha, 0);
5768 break;
5769 case QLA8XXX_DEV_QUIESCENT:
5770 /* XXX: DEBUG for now */
5771 if (ha->flags.quiesce_owner)
5772 goto exit;
5773
5774 qla83xx_idc_unlock(base_vha, 0);
5775 msleep(1000);
5776 qla83xx_idc_lock(base_vha, 0);
5777 dev_init_timeout = jiffies +
5778 (ha->fcoe_dev_init_timeout * HZ);
5779 break;
5780 case QLA8XXX_DEV_FAILED:
5781 if (ha->flags.nic_core_reset_owner)
5782 qla83xx_idc_audit(base_vha,
5783 IDC_AUDIT_COMPLETION);
5784 ha->flags.nic_core_reset_owner = 0;
5785 __qla83xx_clear_drv_presence(base_vha);
5786 qla83xx_idc_unlock(base_vha, 0);
5787 qla8xxx_dev_failed_handler(base_vha);
5788 rval = QLA_FUNCTION_FAILED;
5789 qla83xx_idc_lock(base_vha, 0);
5790 goto exit;
5791 case QLA8XXX_BAD_VALUE:
5792 qla83xx_idc_unlock(base_vha, 0);
5793 msleep(1000);
5794 qla83xx_idc_lock(base_vha, 0);
5795 break;
5796 default:
5797 ql_log(ql_log_warn, base_vha, 0xb071,
d939be3a 5798 "Unknown Device State: %x.\n", dev_state);
7d613ac6
SV		 5799 qla83xx_idc_unlock(base_vha, 0);
5800 qla8xxx_dev_failed_handler(base_vha);
5801 rval = QLA_FUNCTION_FAILED;
5802 qla83xx_idc_lock(base_vha, 0);
5803 goto exit;
5804 }
5805 }
5806
5807exit:
5808 return rval;
5809}
5810
f3ddac19
CD		 5811void
5812qla2x00_disable_board_on_pci_error(struct work_struct *work)
5813{
5814 struct qla_hw_data *ha = container_of(work, struct qla_hw_data,
5815 board_disable);
5816 struct pci_dev *pdev = ha->pdev;
5817 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5818
726b8548
QT		 5819 /*
5820 * if UNLOAD flag is already set, then continue unload,
783e0dc4
SC		 5821 * where it was set first.
5822 */
5823 if (test_bit(UNLOADING, &base_vha->dpc_flags))
5824 return;
5825
f3ddac19
CD		 5826 ql_log(ql_log_warn, base_vha, 0x015b,
5827 "Disabling adapter.\n");
5828
efdb5760
SC		 5829 if (!atomic_read(&pdev->enable_cnt)) {
5830 ql_log(ql_log_info, base_vha, 0xfffc,
5831 "PCI device disabled, no action req for PCI error=%lx\n",
5832 base_vha->pci_flags);
5833 return;
5834 }
5835
726b8548
QT		 5836 qla2x00_wait_for_sess_deletion(base_vha);
5837
f3ddac19
CD		 5838 set_bit(UNLOADING, &base_vha->dpc_flags);
5839
5840 qla2x00_delete_all_vps(ha, base_vha);
5841
5842 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
5843
5844 qla2x00_dfs_remove(base_vha);
5845
5846 qla84xx_put_chip(base_vha);
5847
5848 if (base_vha->timer_active)
5849 qla2x00_stop_timer(base_vha);
5850
5851 base_vha->flags.online = 0;
5852
5853 qla2x00_destroy_deferred_work(ha);
5854
5855 /*
5856 * Do not try to stop beacon blink as it will issue a mailbox
5857 * command.
5858 */
5859 qla2x00_free_sysfs_attr(base_vha, false);
5860
5861 fc_remove_host(base_vha->host);
5862
5863 scsi_remove_host(base_vha->host);
5864
5865 base_vha->flags.init_done = 0;
5866 qla25xx_delete_queues(base_vha);
f3ddac19 5867 qla2x00_free_fcports(base_vha);
093df737 5868 qla2x00_free_irqs(base_vha);
f3ddac19
CD		 5869 qla2x00_mem_free(ha);
5870 qla82xx_md_free(base_vha);
5871 qla2x00_free_queues(ha);
5872
f3ddac19
CD		 5873 qla2x00_unmap_iobases(ha);
5874
5875 pci_release_selected_regions(ha->pdev, ha->bars);
f3ddac19
CD		 5876 pci_disable_pcie_error_reporting(pdev);
5877 pci_disable_device(pdev);
f3ddac19 5878
beb9e315
JL		 5879 /*
5880 * Let qla2x00_remove_one cleanup qla_hw_data on device removal.
5881 */
f3ddac19
CD		 5882}
5883
1da177e4
LT		 5884/**************************************************************************
5885* qla2x00_do_dpc
5886* This kernel thread is a task that is schedule by the interrupt handler
5887* to perform the background processing for interrupts.
5888*
5889* Notes:
5890* This task always run in the context of a kernel thread. It
5891* is kick-off by the driver's detect code and starts up
5892* up one per adapter. It immediately goes to sleep and waits for
5893* some fibre event. When either the interrupt handler or
5894* the timer routine detects a event it will one of the task
5895* bits then wake us up.
5896**************************************************************************/
5897static int
5898qla2x00_do_dpc(void *data)
5899{
e315cd28
AC		 5900 scsi_qla_host_t *base_vha;
5901 struct qla_hw_data *ha;
d7459527
MH		 5902 uint32_t online;
5903 struct qla_qpair *qpair;
1da177e4 5904
e315cd28
AC		 5905 ha = (struct qla_hw_data *)data;
5906 base_vha = pci_get_drvdata(ha->pdev);
1da177e4 5907
8698a745 5908 set_user_nice(current, MIN_NICE);
1da177e4 5909
563585ec 5910 set_current_state(TASK_INTERRUPTIBLE);
39a11240 5911 while (!kthread_should_stop()) {
7c3df132
SK		 5912 ql_dbg(ql_dbg_dpc, base_vha, 0x4000,
5913 "DPC handler sleeping.\n");
1da177e4 5914
39a11240 5915 schedule();
1da177e4 5916
c142caf0
AV		 5917 if (!base_vha->flags.init_done || ha->flags.mbox_busy)
5918 goto end_loop;
1da177e4 5919
85880801 5920 if (ha->flags.eeh_busy) {
7c3df132
SK		 5921 ql_dbg(ql_dbg_dpc, base_vha, 0x4003,
5922 "eeh_busy=%d.\n", ha->flags.eeh_busy);
c142caf0 5923 goto end_loop;
85880801
AV		 5924 }
5925
1da177e4
LT		 5926 ha->dpc_active = 1;
5927
5f28d2d7
SK		 5928 ql_dbg(ql_dbg_dpc + ql_dbg_verbose, base_vha, 0x4001,
5929 "DPC handler waking up, dpc_flags=0x%lx.\n",
5930 base_vha->dpc_flags);
1da177e4 5931
a29b3dd7
JC		 5932 if (test_bit(UNLOADING, &base_vha->dpc_flags))
5933 break;
5934
7ec0effd
AD		 5935 if (IS_P3P_TYPE(ha)) {
5936 if (IS_QLA8044(ha)) {
5937 if (test_and_clear_bit(ISP_UNRECOVERABLE,
5938 &base_vha->dpc_flags)) {
5939 qla8044_idc_lock(ha);
5940 qla8044_wr_direct(base_vha,
5941 QLA8044_CRB_DEV_STATE_INDEX,
5942 QLA8XXX_DEV_FAILED);
5943 qla8044_idc_unlock(ha);
5944 ql_log(ql_log_info, base_vha, 0x4004,
5945 "HW State: FAILED.\n");
5946 qla8044_device_state_handler(base_vha);
5947 continue;
5948 }
5949
5950 } else {
5951 if (test_and_clear_bit(ISP_UNRECOVERABLE,
5952 &base_vha->dpc_flags)) {
5953 qla82xx_idc_lock(ha);
5954 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
5955 QLA8XXX_DEV_FAILED);
5956 qla82xx_idc_unlock(ha);
5957 ql_log(ql_log_info, base_vha, 0x0151,
5958 "HW State: FAILED.\n");
5959 qla82xx_device_state_handler(base_vha);
5960 continue;
5961 }
a9083016
GM		 5962 }
5963
5964 if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED,
5965 &base_vha->dpc_flags)) {
5966
7c3df132
SK		 5967 ql_dbg(ql_dbg_dpc, base_vha, 0x4005,
5968 "FCoE context reset scheduled.\n");
a9083016
GM		 5969 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
5970 &base_vha->dpc_flags))) {
5971 if (qla82xx_fcoe_ctx_reset(base_vha)) {
5972 /* FCoE-ctx reset failed.
5973 * Escalate to chip-reset
5974 */
5975 set_bit(ISP_ABORT_NEEDED,
5976 &base_vha->dpc_flags);
5977 }
5978 clear_bit(ABORT_ISP_ACTIVE,
5979 &base_vha->dpc_flags);
5980 }
5981
7c3df132
SK		 5982 ql_dbg(ql_dbg_dpc, base_vha, 0x4006,
5983 "FCoE context reset end.\n");
a9083016 5984 }
8ae6d9c7
GM		 5985 } else if (IS_QLAFX00(ha)) {
5986 if (test_and_clear_bit(ISP_UNRECOVERABLE,
5987 &base_vha->dpc_flags)) {
5988 ql_dbg(ql_dbg_dpc, base_vha, 0x4020,
5989 "Firmware Reset Recovery\n");
5990 if (qlafx00_reset_initialize(base_vha)) {
5991 /* Failed. Abort isp later. */
5992 if (!test_bit(UNLOADING,
f92f82d6 5993 &base_vha->dpc_flags)) {
8ae6d9c7
GM		 5994 set_bit(ISP_UNRECOVERABLE,
5995 &base_vha->dpc_flags);
5996 ql_dbg(ql_dbg_dpc, base_vha,
5997 0x4021,
5998 "Reset Recovery Failed\n");
f92f82d6 5999 }
8ae6d9c7
GM		 6000 }
6001 }
6002
6003 if (test_and_clear_bit(FX00_TARGET_SCAN,
6004 &base_vha->dpc_flags)) {
6005 ql_dbg(ql_dbg_dpc, base_vha, 0x4022,
6006 "ISPFx00 Target Scan scheduled\n");
6007 if (qlafx00_rescan_isp(base_vha)) {
6008 if (!test_bit(UNLOADING,
6009 &base_vha->dpc_flags))
6010 set_bit(ISP_UNRECOVERABLE,
6011 &base_vha->dpc_flags);
6012 ql_dbg(ql_dbg_dpc, base_vha, 0x401e,
6013 "ISPFx00 Target Scan Failed\n");
6014 }
6015 ql_dbg(ql_dbg_dpc, base_vha, 0x401f,
6016 "ISPFx00 Target Scan End\n");
6017 }
e8f5e95d
AB		 6018 if (test_and_clear_bit(FX00_HOST_INFO_RESEND,
6019 &base_vha->dpc_flags)) {
6020 ql_dbg(ql_dbg_dpc, base_vha, 0x4023,
6021 "ISPFx00 Host Info resend scheduled\n");
6022 qlafx00_fx_disc(base_vha,
6023 &base_vha->hw->mr.fcport,
6024 FXDISC_REG_HOST_INFO);
6025 }
a9083016
GM		 6026 }
6027
e4e3a2ce
QT		 6028 if (test_and_clear_bit(DETECT_SFP_CHANGE,
6029 &base_vha->dpc_flags) &&
6030 !test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) {
6031 qla24xx_detect_sfp(base_vha);
6032
6033 if (ha->flags.detected_lr_sfp !=
6034 ha->flags.using_lr_setting)
6035 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
6036 }
6037
e315cd28
AC		 6038 if (test_and_clear_bit(ISP_ABORT_NEEDED,
6039 &base_vha->dpc_flags)) {
1da177e4 6040
7c3df132
SK		 6041 ql_dbg(ql_dbg_dpc, base_vha, 0x4007,
6042 "ISP abort scheduled.\n");
1da177e4 6043 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
e315cd28 6044 &base_vha->dpc_flags))) {
1da177e4 6045
a9083016 6046 if (ha->isp_ops->abort_isp(base_vha)) {
1da177e4
LT		 6047 /* failed. retry later */
6048 set_bit(ISP_ABORT_NEEDED,
e315cd28 6049 &base_vha->dpc_flags);
99363ef8 6050 }
e315cd28
AC		 6051 clear_bit(ABORT_ISP_ACTIVE,
6052 &base_vha->dpc_flags);
99363ef8
SJ		 6053 }
6054
7c3df132
SK		 6055 ql_dbg(ql_dbg_dpc, base_vha, 0x4008,
6056 "ISP abort end.\n");
1da177e4
LT		 6057 }
6058
a394aac8
DJ		 6059 if (test_and_clear_bit(FCPORT_UPDATE_NEEDED,
6060 &base_vha->dpc_flags)) {
e315cd28 6061 qla2x00_update_fcports(base_vha);
c9c5ced9 6062 }
d97994dc 6063
8ae6d9c7
GM		 6064 if (IS_QLAFX00(ha))
6065 goto loop_resync_check;
6066
579d12b5 6067 if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) {
7c3df132
SK		 6068 ql_dbg(ql_dbg_dpc, base_vha, 0x4009,
6069 "Quiescence mode scheduled.\n");
7ec0effd
AD		 6070 if (IS_P3P_TYPE(ha)) {
6071 if (IS_QLA82XX(ha))
6072 qla82xx_device_state_handler(base_vha);
6073 if (IS_QLA8044(ha))
6074 qla8044_device_state_handler(base_vha);
8fcd6b8b
CD		 6075 clear_bit(ISP_QUIESCE_NEEDED,
6076 &base_vha->dpc_flags);
6077 if (!ha->flags.quiesce_owner) {
6078 qla2x00_perform_loop_resync(base_vha);
7ec0effd
AD		 6079 if (IS_QLA82XX(ha)) {
6080 qla82xx_idc_lock(ha);
6081 qla82xx_clear_qsnt_ready(
6082 base_vha);
6083 qla82xx_idc_unlock(ha);
6084 } else if (IS_QLA8044(ha)) {
6085 qla8044_idc_lock(ha);
6086 qla8044_clear_qsnt_ready(
6087 base_vha);
6088 qla8044_idc_unlock(ha);
6089 }
8fcd6b8b
CD		 6090 }
6091 } else {
6092 clear_bit(ISP_QUIESCE_NEEDED,
6093 &base_vha->dpc_flags);
6094 qla2x00_quiesce_io(base_vha);
579d12b5 6095 }
7c3df132
SK		 6096 ql_dbg(ql_dbg_dpc, base_vha, 0x400a,
6097 "Quiescence mode end.\n");
579d12b5
SK		 6098 }
6099
e315cd28 6100 if (test_and_clear_bit(RESET_MARKER_NEEDED,
8ae6d9c7 6101 &base_vha->dpc_flags) &&
e315cd28 6102 (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) {
1da177e4 6103
7c3df132
SK		 6104 ql_dbg(ql_dbg_dpc, base_vha, 0x400b,
6105 "Reset marker scheduled.\n");
e315cd28
AC		 6106 qla2x00_rst_aen(base_vha);
6107 clear_bit(RESET_ACTIVE, &base_vha->dpc_flags);
7c3df132
SK		 6108 ql_dbg(ql_dbg_dpc, base_vha, 0x400c,
6109 "Reset marker end.\n");
1da177e4
LT		 6110 }
6111
6112 /* Retry each device up to login retry count */
4005a995 6113 if (test_bit(RELOGIN_NEEDED, &base_vha->dpc_flags) &&
e315cd28
AC		 6114 !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) &&
6115 atomic_read(&base_vha->loop_state) != LOOP_DOWN) {
1da177e4 6116
4005a995
QT		 6117 if (!base_vha->relogin_jif ||
6118 time_after_eq(jiffies, base_vha->relogin_jif)) {
6119 base_vha->relogin_jif = jiffies + HZ;
6120 clear_bit(RELOGIN_NEEDED, &base_vha->dpc_flags);
6121
9b3e0f4d 6122 ql_dbg(ql_dbg_disc, base_vha, 0x400d,
4005a995 6123 "Relogin scheduled.\n");
9b3e0f4d 6124 qla24xx_post_relogin_work(base_vha);
4005a995 6125 }
1da177e4 6126 }
8ae6d9c7 6127loop_resync_check:
e315cd28 6128 if (test_and_clear_bit(LOOP_RESYNC_NEEDED,
8ae6d9c7 6129 &base_vha->dpc_flags)) {
1da177e4 6130
7c3df132
SK		 6131 ql_dbg(ql_dbg_dpc, base_vha, 0x400f,
6132 "Loop resync scheduled.\n");
1da177e4
LT		 6133
6134 if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE,
e315cd28 6135 &base_vha->dpc_flags))) {
1da177e4 6136
52c82823 6137 qla2x00_loop_resync(base_vha);
1da177e4 6138
e315cd28
AC		 6139 clear_bit(LOOP_RESYNC_ACTIVE,
6140 &base_vha->dpc_flags);
1da177e4
LT		 6141 }
6142
7c3df132
SK		 6143 ql_dbg(ql_dbg_dpc, base_vha, 0x4010,
6144 "Loop resync end.\n");
1da177e4
LT		 6145 }
6146
8ae6d9c7
GM		 6147 if (IS_QLAFX00(ha))
6148 goto intr_on_check;
6149
e315cd28
AC		 6150 if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) &&
6151 atomic_read(&base_vha->loop_state) == LOOP_READY) {
6152 clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags);
6153 qla2xxx_flash_npiv_conf(base_vha);
272976ca
AV		 6154 }
6155
8ae6d9c7 6156intr_on_check:
1da177e4 6157 if (!ha->interrupts_on)
fd34f556 6158 ha->isp_ops->enable_intrs(ha);
1da177e4 6159
e315cd28 6160 if (test_and_clear_bit(BEACON_BLINK_NEEDED,
90b604f2
HM		 6161 &base_vha->dpc_flags)) {
6162 if (ha->beacon_blink_led == 1)
6163 ha->isp_ops->beacon_blink(base_vha);
6164 }
f6df144c 6165
d7459527
MH		 6166 /* qpair online check */
6167 if (test_and_clear_bit(QPAIR_ONLINE_CHECK_NEEDED,
6168 &base_vha->dpc_flags)) {
6169 if (ha->flags.eeh_busy ||
6170 ha->flags.pci_channel_io_perm_failure)
6171 online = 0;
6172 else
6173 online = 1;
6174
6175 mutex_lock(&ha->mq_lock);
6176 list_for_each_entry(qpair, &base_vha->qp_list,
6177 qp_list_elem)
6178 qpair->online = online;
6179 mutex_unlock(&ha->mq_lock);
6180 }
6181
deeae7a6
DG		 6182 if (test_and_clear_bit(SET_ZIO_THRESHOLD_NEEDED, &base_vha->dpc_flags)) {
6183 ql_log(ql_log_info, base_vha, 0xffffff,
6184 "nvme: SET ZIO Activity exchange threshold to %d.\n",
6185 ha->nvme_last_rptd_aen);
6186 if (qla27xx_set_zio_threshold(base_vha, ha->nvme_last_rptd_aen)) {
6187 ql_log(ql_log_info, base_vha, 0xffffff,
6188 "nvme: Unable to SET ZIO Activity exchange threshold to %d.\n",
6189 ha->nvme_last_rptd_aen);
6190 }
6191 }
6192
8ae6d9c7
GM		 6193 if (!IS_QLAFX00(ha))
6194 qla2x00_do_dpc_all_vps(base_vha);
2c3dfe3f 6195
48acad09
QT		 6196 if (test_and_clear_bit(N2N_LINK_RESET,
6197 &base_vha->dpc_flags)) {
6198 qla2x00_lip_reset(base_vha);
6199 }
6200
1da177e4 6201 ha->dpc_active = 0;
c142caf0 6202end_loop:
563585ec 6203 set_current_state(TASK_INTERRUPTIBLE);
1da177e4 6204 } /* End of while(1) */
563585ec 6205 __set_current_state(TASK_RUNNING);
1da177e4 6206
7c3df132
SK		 6207 ql_dbg(ql_dbg_dpc, base_vha, 0x4011,
6208 "DPC handler exiting.\n");
1da177e4
LT		 6209
6210 /*
6211 * Make sure that nobody tries to wake us up again.
6212 */
1da177e4
LT		 6213 ha->dpc_active = 0;
6214
ac280b67
AV		 6215 /* Cleanup any residual CTX SRBs. */
6216 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
6217
39a11240
CH		 6218 return 0;
6219}
6220
6221void
e315cd28 6222qla2xxx_wake_dpc(struct scsi_qla_host *vha)
39a11240 6223{
e315cd28 6224 struct qla_hw_data *ha = vha->hw;
c795c1e4
AV		 6225 struct task_struct *t = ha->dpc_thread;
6226
e315cd28 6227 if (!test_bit(UNLOADING, &vha->dpc_flags) && t)
c795c1e4 6228 wake_up_process(t);
1da177e4
LT		 6229}
6230
1da177e4
LT		 6231/*
6232* qla2x00_rst_aen
6233* Processes asynchronous reset.
6234*
6235* Input:
6236* ha = adapter block pointer.
6237*/
6238static void
e315cd28 6239qla2x00_rst_aen(scsi_qla_host_t *vha)
1da177e4 6240{
e315cd28
AC		 6241 if (vha->flags.online && !vha->flags.reset_active &&
6242 !atomic_read(&vha->loop_down_timer) &&
6243 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) {
1da177e4 6244 do {
e315cd28 6245 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
1da177e4
LT		 6246
6247 /*
6248 * Issue marker command only when we are going to start
6249 * the I/O.
6250 */
e315cd28
AC		 6251 vha->marker_needed = 1;
6252 } while (!atomic_read(&vha->loop_down_timer) &&
6253 (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)));
1da177e4
LT		 6254 }
6255}
6256
1da177e4
LT		 6257/**************************************************************************
6258* qla2x00_timer
6259*
6260* Description:
6261* One second timer
6262*
6263* Context: Interrupt
6264***************************************************************************/
2c3dfe3f 6265void
8e5f4ba0 6266qla2x00_timer(struct timer_list *t)
1da177e4 6267{
8e5f4ba0 6268 scsi_qla_host_t *vha = from_timer(vha, t, timer);
1da177e4 6269 unsigned long cpu_flags = 0;
1da177e4
LT		 6270 int start_dpc = 0;
6271 int index;
6272 srb_t *sp;
85880801 6273 uint16_t w;
e315cd28 6274 struct qla_hw_data *ha = vha->hw;
73208dfd 6275 struct req_que *req;
85880801 6276
a5b36321 6277 if (ha->flags.eeh_busy) {
7c3df132
SK		 6278 ql_dbg(ql_dbg_timer, vha, 0x6000,
6279 "EEH = %d, restarting timer.\n",
6280 ha->flags.eeh_busy);
a5b36321
LC		 6281 qla2x00_restart_timer(vha, WATCH_INTERVAL);
6282 return;
6283 }
6284
f3ddac19
CD		 6285 /*
6286 * Hardware read to raise pending EEH errors during mailbox waits. If
6287 * the read returns -1 then disable the board.
6288 */
6289 if (!pci_channel_offline(ha->pdev)) {
85880801 6290 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w);
c821e0d5 6291 qla2x00_check_reg16_for_disconnect(vha, w);
f3ddac19 6292 }
1da177e4 6293
cefcaba6 6294 /* Make sure qla82xx_watchdog is run only for physical port */
7ec0effd 6295 if (!vha->vp_idx && IS_P3P_TYPE(ha)) {
579d12b5
SK		 6296 if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags))
6297 start_dpc++;
7ec0effd
AD		 6298 if (IS_QLA82XX(ha))
6299 qla82xx_watchdog(vha);
6300 else if (IS_QLA8044(ha))
6301 qla8044_watchdog(vha);
579d12b5
SK		 6302 }
6303
8ae6d9c7
GM		 6304 if (!vha->vp_idx && IS_QLAFX00(ha))
6305 qlafx00_timer_routine(vha);
6306
1da177e4 6307 /* Loop down handler. */
e315cd28 6308 if (atomic_read(&vha->loop_down_timer) > 0 &&
8f7daead
GM		 6309 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) &&
6310 !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags))
e315cd28 6311 && vha->flags.online) {
1da177e4 6312
e315cd28
AC		 6313 if (atomic_read(&vha->loop_down_timer) ==
6314 vha->loop_down_abort_time) {
1da177e4 6315
7c3df132
SK		 6316 ql_log(ql_log_info, vha, 0x6008,
6317 "Loop down - aborting the queues before time expires.\n");
1da177e4 6318
e315cd28
AC		 6319 if (!IS_QLA2100(ha) && vha->link_down_timeout)
6320 atomic_set(&vha->loop_state, LOOP_DEAD);
1da177e4 6321
f08b7251
AV		 6322 /*
6323 * Schedule an ISP abort to return any FCP2-device
6324 * commands.
6325 */
2c3dfe3f 6326 /* NPIV - scan physical port only */
e315cd28 6327 if (!vha->vp_idx) {
2c3dfe3f
SJ		 6328 spin_lock_irqsave(&ha->hardware_lock,
6329 cpu_flags);
73208dfd 6330 req = ha->req_q_map[0];
2c3dfe3f 6331 for (index = 1;
8d93f550 6332 index < req->num_outstanding_cmds;
2c3dfe3f
SJ		 6333 index++) {
6334 fc_port_t *sfcp;
6335
e315cd28 6336 sp = req->outstanding_cmds[index];
2c3dfe3f
SJ		 6337 if (!sp)
6338 continue;
c5419e26
QT		 6339 if (sp->cmd_type != TYPE_SRB)
6340 continue;
9ba56b95 6341 if (sp->type != SRB_SCSI_CMD)
cf53b069 6342 continue;
2c3dfe3f 6343 sfcp = sp->fcport;
f08b7251 6344 if (!(sfcp->flags & FCF_FCP2_DEVICE))
2c3dfe3f 6345 continue;
bdf79621 6346
8f7daead
GM		 6347 if (IS_QLA82XX(ha))
6348 set_bit(FCOE_CTX_RESET_NEEDED,
6349 &vha->dpc_flags);
6350 else
6351 set_bit(ISP_ABORT_NEEDED,
e315cd28 6352 &vha->dpc_flags);
2c3dfe3f
SJ		 6353 break;
6354 }
6355 spin_unlock_irqrestore(&ha->hardware_lock,
e315cd28 6356 cpu_flags);
1da177e4 6357 }
1da177e4
LT		 6358 start_dpc++;
6359 }
6360
6361 /* if the loop has been down for 4 minutes, reinit adapter */
e315cd28 6362 if (atomic_dec_and_test(&vha->loop_down_timer) != 0) {
0d6e61bc 6363 if (!(vha->device_flags & DFLG_NO_CABLE)) {
7c3df132 6364 ql_log(ql_log_warn, vha, 0x6009,
1da177e4
LT		 6365 "Loop down - aborting ISP.\n");
6366
8f7daead
GM		 6367 if (IS_QLA82XX(ha))
6368 set_bit(FCOE_CTX_RESET_NEEDED,
6369 &vha->dpc_flags);
6370 else
6371 set_bit(ISP_ABORT_NEEDED,
6372 &vha->dpc_flags);
1da177e4
LT		 6373 }
6374 }
7c3df132
SK		 6375 ql_dbg(ql_dbg_timer, vha, 0x600a,
6376 "Loop down - seconds remaining %d.\n",
6377 atomic_read(&vha->loop_down_timer));
1da177e4 6378 }
cefcaba6
SK		 6379 /* Check if beacon LED needs to be blinked for physical host only */
6380 if (!vha->vp_idx && (ha->beacon_blink_led == 1)) {
999916dc 6381 /* There is no beacon_blink function for ISP82xx */
7ec0effd 6382 if (!IS_P3P_TYPE(ha)) {
999916dc
SK		 6383 set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags);
6384 start_dpc++;
6385 }
f6df144c 6386 }
6387
550bf57d 6388 /* Process any deferred work. */
9b3e0f4d
QT		 6389 if (!list_empty(&vha->work_list)) {
6390 unsigned long flags;
6391 bool q = false;
6392
6393 spin_lock_irqsave(&vha->work_lock, flags);
6394 if (!test_and_set_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags))
6395 q = true;
6396 spin_unlock_irqrestore(&vha->work_lock, flags);
6397 if (q)
6398 queue_work(vha->hw->wq, &vha->iocb_work);
6399 }
550bf57d 6400
7401bc18
DG		 6401 /*
6402 * FC-NVME
6403 * see if the active AEN count has changed from what was last reported.
6404 */
deeae7a6
DG		 6405 if (!vha->vp_idx &&
6406 atomic_read(&ha->nvme_active_aen_cnt) != ha->nvme_last_rptd_aen &&
6407 ha->zio_mode == QLA_ZIO_MODE_6) {
7401bc18 6408 ql_log(ql_log_info, vha, 0x3002,
deeae7a6
DG		 6409 "nvme: Sched: Set ZIO exchange threshold to %d.\n",
6410 ha->nvme_last_rptd_aen);
6411 ha->nvme_last_rptd_aen = atomic_read(&ha->nvme_active_aen_cnt);
6412 set_bit(SET_ZIO_THRESHOLD_NEEDED, &vha->dpc_flags);
6413 start_dpc++;
7401bc18
DG		 6414 }
6415
1da177e4 6416 /* Schedule the DPC routine if needed */
e315cd28
AC		 6417 if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) ||
6418 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) ||
6419 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags) ||
1da177e4 6420 start_dpc ||
e315cd28
AC		 6421 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) ||
6422 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) ||
a9083016
GM		 6423 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) ||
6424 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) ||
e315cd28 6425 test_bit(VP_DPC_NEEDED, &vha->dpc_flags) ||
50280c01 6426 test_bit(RELOGIN_NEEDED, &vha->dpc_flags))) {
7c3df132
SK		 6427 ql_dbg(ql_dbg_timer, vha, 0x600b,
6428 "isp_abort_needed=%d loop_resync_needed=%d "
6429 "fcport_update_needed=%d start_dpc=%d "
6430 "reset_marker_needed=%d",
6431 test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags),
6432 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags),
6433 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags),
6434 start_dpc,
6435 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags));
6436 ql_dbg(ql_dbg_timer, vha, 0x600c,
6437 "beacon_blink_needed=%d isp_unrecoverable=%d "
6438 "fcoe_ctx_reset_needed=%d vp_dpc_needed=%d "
50280c01 6439 "relogin_needed=%d.\n",
7c3df132
SK		 6440 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags),
6441 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags),
6442 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags),
6443 test_bit(VP_DPC_NEEDED, &vha->dpc_flags),
50280c01 6444 test_bit(RELOGIN_NEEDED, &vha->dpc_flags));
e315cd28 6445 qla2xxx_wake_dpc(vha);
7c3df132 6446 }
1da177e4 6447
e315cd28 6448 qla2x00_restart_timer(vha, WATCH_INTERVAL);
1da177e4
LT		 6449}
6450
5433383e
AV		 6451/* Firmware interface routines. */
6452
f73cb695 6453#define FW_BLOBS 11
5433383e
AV		 6454#define FW_ISP21XX 0
6455#define FW_ISP22XX 1
6456#define FW_ISP2300 2
6457#define FW_ISP2322 3
48c02fde 6458#define FW_ISP24XX 4
c3a2f0df 6459#define FW_ISP25XX 5
3a03eb79 6460#define FW_ISP81XX 6
a9083016 6461#define FW_ISP82XX 7
6246b8a1
GM		 6462#define FW_ISP2031 8
6463#define FW_ISP8031 9
2c5bbbb2 6464#define FW_ISP27XX 10
5433383e 6465
bb8ee499
AV		 6466#define FW_FILE_ISP21XX "ql2100_fw.bin"
6467#define FW_FILE_ISP22XX "ql2200_fw.bin"
6468#define FW_FILE_ISP2300 "ql2300_fw.bin"
6469#define FW_FILE_ISP2322 "ql2322_fw.bin"
6470#define FW_FILE_ISP24XX "ql2400_fw.bin"
c3a2f0df 6471#define FW_FILE_ISP25XX "ql2500_fw.bin"
3a03eb79 6472#define FW_FILE_ISP81XX "ql8100_fw.bin"
a9083016 6473#define FW_FILE_ISP82XX "ql8200_fw.bin"
6246b8a1
GM		 6474#define FW_FILE_ISP2031 "ql2600_fw.bin"
6475#define FW_FILE_ISP8031 "ql8300_fw.bin"
2c5bbbb2 6476#define FW_FILE_ISP27XX "ql2700_fw.bin"
f73cb695 6477
bb8ee499 6478
e1e82b6f 6479static DEFINE_MUTEX(qla_fw_lock);
5433383e
AV		 6480
6481static struct fw_blob qla_fw_blobs[FW_BLOBS] = {
bb8ee499
AV		 6482 { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, },
6483 { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, },
6484 { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, },
6485 { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, },
6486 { .name = FW_FILE_ISP24XX, },
c3a2f0df 6487 { .name = FW_FILE_ISP25XX, },
3a03eb79 6488 { .name = FW_FILE_ISP81XX, },
a9083016 6489 { .name = FW_FILE_ISP82XX, },
6246b8a1
GM		 6490 { .name = FW_FILE_ISP2031, },
6491 { .name = FW_FILE_ISP8031, },
2c5bbbb2 6492 { .name = FW_FILE_ISP27XX, },
5433383e
AV		 6493};
6494
6495struct fw_blob *
e315cd28 6496qla2x00_request_firmware(scsi_qla_host_t *vha)
5433383e 6497{
e315cd28 6498 struct qla_hw_data *ha = vha->hw;
5433383e
AV		 6499 struct fw_blob *blob;
6500
5433383e
AV		 6501 if (IS_QLA2100(ha)) {
6502 blob = &qla_fw_blobs[FW_ISP21XX];
6503 } else if (IS_QLA2200(ha)) {
6504 blob = &qla_fw_blobs[FW_ISP22XX];
48c02fde 6505 } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
5433383e 6506 blob = &qla_fw_blobs[FW_ISP2300];
48c02fde 6507 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
5433383e 6508 blob = &qla_fw_blobs[FW_ISP2322];
4d4df193 6509 } else if (IS_QLA24XX_TYPE(ha)) {
5433383e 6510 blob = &qla_fw_blobs[FW_ISP24XX];
c3a2f0df
AV		 6511 } else if (IS_QLA25XX(ha)) {
6512 blob = &qla_fw_blobs[FW_ISP25XX];
3a03eb79
AV		 6513 } else if (IS_QLA81XX(ha)) {
6514 blob = &qla_fw_blobs[FW_ISP81XX];
a9083016
GM		 6515 } else if (IS_QLA82XX(ha)) {
6516 blob = &qla_fw_blobs[FW_ISP82XX];
6246b8a1
GM		 6517 } else if (IS_QLA2031(ha)) {
6518 blob = &qla_fw_blobs[FW_ISP2031];
6519 } else if (IS_QLA8031(ha)) {
6520 blob = &qla_fw_blobs[FW_ISP8031];
2c5bbbb2
JC		 6521 } else if (IS_QLA27XX(ha)) {
6522 blob = &qla_fw_blobs[FW_ISP27XX];
8a655229
DC		 6523 } else {
6524 return NULL;
5433383e
AV		 6525 }
6526
e1e82b6f 6527 mutex_lock(&qla_fw_lock);
5433383e
AV		 6528 if (blob->fw)
6529 goto out;
6530
6531 if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) {
7c3df132
SK		 6532 ql_log(ql_log_warn, vha, 0x0063,
6533 "Failed to load firmware image (%s).\n", blob->name);
5433383e
AV		 6534 blob->fw = NULL;
6535 blob = NULL;
6536 goto out;
6537 }
6538
6539out:
e1e82b6f 6540 mutex_unlock(&qla_fw_lock);
5433383e
AV		 6541 return blob;
6542}
6543
6544static void
6545qla2x00_release_firmware(void)
6546{
6547 int idx;
6548
e1e82b6f 6549 mutex_lock(&qla_fw_lock);
5433383e 6550 for (idx = 0; idx < FW_BLOBS; idx++)
cf92549f 6551 release_firmware(qla_fw_blobs[idx].fw);
e1e82b6f 6552 mutex_unlock(&qla_fw_lock);
5433383e
AV		 6553}
6554
14e660e6
SJ		 6555static pci_ers_result_t
6556qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
6557{
85880801
AV		 6558 scsi_qla_host_t *vha = pci_get_drvdata(pdev);
6559 struct qla_hw_data *ha = vha->hw;
6560
7c3df132
SK		 6561 ql_dbg(ql_dbg_aer, vha, 0x9000,
6562 "PCI error detected, state %x.\n", state);
b9b12f73 6563
efdb5760
SC		 6564 if (!atomic_read(&pdev->enable_cnt)) {
6565 ql_log(ql_log_info, vha, 0xffff,
6566 "PCI device is disabled,state %x\n", state);
6567 return PCI_ERS_RESULT_NEED_RESET;
6568 }
6569
14e660e6
SJ		 6570 switch (state) {
6571 case pci_channel_io_normal:
85880801 6572 ha->flags.eeh_busy = 0;
c38d1baf 6573 if (ql2xmqsupport || ql2xnvmeenable) {
d7459527
MH		 6574 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags);
6575 qla2xxx_wake_dpc(vha);
6576 }
14e660e6
SJ		 6577 return PCI_ERS_RESULT_CAN_RECOVER;
6578 case pci_channel_io_frozen:
85880801 6579 ha->flags.eeh_busy = 1;
a5b36321
LC		 6580 /* For ISP82XX complete any pending mailbox cmd */
6581 if (IS_QLA82XX(ha)) {
7190575f 6582 ha->flags.isp82xx_fw_hung = 1;
c8f6544e
CD		 6583 ql_dbg(ql_dbg_aer, vha, 0x9001, "Pci channel io frozen\n");
6584 qla82xx_clear_pending_mbx(vha);
a5b36321 6585 }
90a86fc0 6586 qla2x00_free_irqs(vha);
14e660e6 6587 pci_disable_device(pdev);
bddd2d65
LC		 6588 /* Return back all IOs */
6589 qla2x00_abort_all_cmds(vha, DID_RESET << 16);
c38d1baf 6590 if (ql2xmqsupport || ql2xnvmeenable) {
d7459527
MH		 6591 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags);
6592 qla2xxx_wake_dpc(vha);
6593 }
14e660e6
SJ		 6594 return PCI_ERS_RESULT_NEED_RESET;
6595 case pci_channel_io_perm_failure:
85880801
AV		 6596 ha->flags.pci_channel_io_perm_failure = 1;
6597 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
c38d1baf 6598 if (ql2xmqsupport || ql2xnvmeenable) {
d7459527
MH		 6599 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags);
6600 qla2xxx_wake_dpc(vha);
6601 }
14e660e6
SJ		 6602 return PCI_ERS_RESULT_DISCONNECT;
6603 }
6604 return PCI_ERS_RESULT_NEED_RESET;
6605}
6606
6607static pci_ers_result_t
6608qla2xxx_pci_mmio_enabled(struct pci_dev *pdev)
6609{
6610 int risc_paused = 0;
6611 uint32_t stat;
6612 unsigned long flags;
e315cd28
AC		 6613 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
6614 struct qla_hw_data *ha = base_vha->hw;
14e660e6
SJ		 6615 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
6616 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
6617
bcc5b6d3
SK		 6618 if (IS_QLA82XX(ha))
6619 return PCI_ERS_RESULT_RECOVERED;
6620
14e660e6
SJ		 6621 spin_lock_irqsave(&ha->hardware_lock, flags);
6622 if (IS_QLA2100(ha) || IS_QLA2200(ha)){
6623 stat = RD_REG_DWORD(&reg->hccr);
6624 if (stat & HCCR_RISC_PAUSE)
6625 risc_paused = 1;
6626 } else if (IS_QLA23XX(ha)) {
6627 stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
6628 if (stat & HSR_RISC_PAUSED)
6629 risc_paused = 1;
6630 } else if (IS_FWI2_CAPABLE(ha)) {
6631 stat = RD_REG_DWORD(&reg24->host_status);
6632 if (stat & HSRX_RISC_PAUSED)
6633 risc_paused = 1;
6634 }
6635 spin_unlock_irqrestore(&ha->hardware_lock, flags);
6636
6637 if (risc_paused) {
7c3df132
SK		 6638 ql_log(ql_log_info, base_vha, 0x9003,
6639 "RISC paused -- mmio_enabled, Dumping firmware.\n");
e315cd28 6640 ha->isp_ops->fw_dump(base_vha, 0);
14e660e6
SJ		 6641
6642 return PCI_ERS_RESULT_NEED_RESET;
6643 } else
6644 return PCI_ERS_RESULT_RECOVERED;
6645}
6646
fa492630
SK		 6647static uint32_t
6648qla82xx_error_recovery(scsi_qla_host_t *base_vha)
a5b36321
LC		 6649{
6650 uint32_t rval = QLA_FUNCTION_FAILED;
6651 uint32_t drv_active = 0;
6652 struct qla_hw_data *ha = base_vha->hw;
6653 int fn;
6654 struct pci_dev *other_pdev = NULL;
6655
7c3df132
SK		 6656 ql_dbg(ql_dbg_aer, base_vha, 0x9006,
6657 "Entered %s.\n", __func__);
a5b36321
LC		 6658
6659 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
6660
6661 if (base_vha->flags.online) {
6662 /* Abort all outstanding commands,
6663 * so as to be requeued later */
6664 qla2x00_abort_isp_cleanup(base_vha);
6665 }
6666
6667
6668 fn = PCI_FUNC(ha->pdev->devfn);
6669 while (fn > 0) {
6670 fn--;
7c3df132
SK		 6671 ql_dbg(ql_dbg_aer, base_vha, 0x9007,
6672 "Finding pci device at function = 0x%x.\n", fn);
a5b36321
LC		 6673 other_pdev =
6674 pci_get_domain_bus_and_slot(pci_domain_nr(ha->pdev->bus),
6675 ha->pdev->bus->number, PCI_DEVFN(PCI_SLOT(ha->pdev->devfn),
6676 fn));
6677
6678 if (!other_pdev)
6679 continue;
6680 if (atomic_read(&other_pdev->enable_cnt)) {
7c3df132
SK		 6681 ql_dbg(ql_dbg_aer, base_vha, 0x9008,
6682 "Found PCI func available and enable at 0x%x.\n",
6683 fn);
a5b36321
LC		 6684 pci_dev_put(other_pdev);
6685 break;
6686 }
6687 pci_dev_put(other_pdev);
6688 }
6689
6690 if (!fn) {
6691 /* Reset owner */
7c3df132
SK		 6692 ql_dbg(ql_dbg_aer, base_vha, 0x9009,
6693 "This devfn is reset owner = 0x%x.\n",
6694 ha->pdev->devfn);
a5b36321
LC		 6695 qla82xx_idc_lock(ha);
6696
6697 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 6698 QLA8XXX_DEV_INITIALIZING);
a5b36321
LC		 6699
6700 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION,
6701 QLA82XX_IDC_VERSION);
6702
6703 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
7c3df132
SK		 6704 ql_dbg(ql_dbg_aer, base_vha, 0x900a,
6705 "drv_active = 0x%x.\n", drv_active);
a5b36321
LC		 6706
6707 qla82xx_idc_unlock(ha);
6708 /* Reset if device is not already reset
6709 * drv_active would be 0 if a reset has already been done
6710 */
6711 if (drv_active)
6712 rval = qla82xx_start_firmware(base_vha);
6713 else
6714 rval = QLA_SUCCESS;
6715 qla82xx_idc_lock(ha);
6716
6717 if (rval != QLA_SUCCESS) {
7c3df132
SK		 6718 ql_log(ql_log_info, base_vha, 0x900b,
6719 "HW State: FAILED.\n");
a5b36321
LC		 6720 qla82xx_clear_drv_active(ha);
6721 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 6722 QLA8XXX_DEV_FAILED);
a5b36321 6723 } else {
7c3df132
SK		 6724 ql_log(ql_log_info, base_vha, 0x900c,
6725 "HW State: READY.\n");
a5b36321 6726 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 6727 QLA8XXX_DEV_READY);
a5b36321 6728 qla82xx_idc_unlock(ha);
7190575f 6729 ha->flags.isp82xx_fw_hung = 0;
a5b36321
LC		 6730 rval = qla82xx_restart_isp(base_vha);
6731 qla82xx_idc_lock(ha);
6732 /* Clear driver state register */
6733 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, 0);
6734 qla82xx_set_drv_active(base_vha);
6735 }
6736 qla82xx_idc_unlock(ha);
6737 } else {
7c3df132
SK		 6738 ql_dbg(ql_dbg_aer, base_vha, 0x900d,
6739 "This devfn is not reset owner = 0x%x.\n",
6740 ha->pdev->devfn);
a5b36321 6741 if ((qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE) ==
7d613ac6 6742 QLA8XXX_DEV_READY)) {
7190575f 6743 ha->flags.isp82xx_fw_hung = 0;
a5b36321
LC		 6744 rval = qla82xx_restart_isp(base_vha);
6745 qla82xx_idc_lock(ha);
6746 qla82xx_set_drv_active(base_vha);
6747 qla82xx_idc_unlock(ha);
6748 }
6749 }
6750 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
6751
6752 return rval;
6753}
6754
14e660e6
SJ		 6755static pci_ers_result_t
6756qla2xxx_pci_slot_reset(struct pci_dev *pdev)
6757{
6758 pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT;
e315cd28
AC		 6759 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
6760 struct qla_hw_data *ha = base_vha->hw;
90a86fc0
JC		 6761 struct rsp_que *rsp;
6762 int rc, retries = 10;
09483916 6763
7c3df132
SK		 6764 ql_dbg(ql_dbg_aer, base_vha, 0x9004,
6765 "Slot Reset.\n");
85880801 6766
90a86fc0
JC		 6767 /* Workaround: qla2xxx driver which access hardware earlier
6768 * needs error state to be pci_channel_io_online.
6769 * Otherwise mailbox command timesout.
6770 */
6771 pdev->error_state = pci_channel_io_normal;
6772
6773 pci_restore_state(pdev);
6774
8c1496bd
RL		 6775 /* pci_restore_state() clears the saved_state flag of the device
6776 * save restored state which resets saved_state flag
6777 */
6778 pci_save_state(pdev);
6779
09483916
BH		 6780 if (ha->mem_only)
6781 rc = pci_enable_device_mem(pdev);
6782 else
6783 rc = pci_enable_device(pdev);
14e660e6 6784
09483916 6785 if (rc) {
7c3df132 6786 ql_log(ql_log_warn, base_vha, 0x9005,
14e660e6 6787 "Can't re-enable PCI device after reset.\n");
a5b36321 6788 goto exit_slot_reset;
14e660e6 6789 }
14e660e6 6790
90a86fc0
JC		 6791 rsp = ha->rsp_q_map[0];
6792 if (qla2x00_request_irqs(ha, rsp))
a5b36321 6793 goto exit_slot_reset;
90a86fc0 6794
e315cd28 6795 if (ha->isp_ops->pci_config(base_vha))
a5b36321
LC		 6796 goto exit_slot_reset;
6797
6798 if (IS_QLA82XX(ha)) {
6799 if (qla82xx_error_recovery(base_vha) == QLA_SUCCESS) {
6800 ret = PCI_ERS_RESULT_RECOVERED;
6801 goto exit_slot_reset;
6802 } else
6803 goto exit_slot_reset;
6804 }
14e660e6 6805
90a86fc0
JC		 6806 while (ha->flags.mbox_busy && retries--)
6807 msleep(1000);
85880801 6808
e315cd28 6809 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
a9083016 6810 if (ha->isp_ops->abort_isp(base_vha) == QLA_SUCCESS)
14e660e6 6811 ret = PCI_ERS_RESULT_RECOVERED;
e315cd28 6812 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
14e660e6 6813
90a86fc0 6814
a5b36321 6815exit_slot_reset:
7c3df132
SK		 6816 ql_dbg(ql_dbg_aer, base_vha, 0x900e,
6817 "slot_reset return %x.\n", ret);
85880801 6818
14e660e6
SJ		 6819 return ret;
6820}
6821
6822static void
6823qla2xxx_pci_resume(struct pci_dev *pdev)
6824{
e315cd28
AC		 6825 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
6826 struct qla_hw_data *ha = base_vha->hw;
14e660e6
SJ		 6827 int ret;
6828
7c3df132
SK		 6829 ql_dbg(ql_dbg_aer, base_vha, 0x900f,
6830 "pci_resume.\n");
85880801 6831
e315cd28 6832 ret = qla2x00_wait_for_hba_online(base_vha);
14e660e6 6833 if (ret != QLA_SUCCESS) {
7c3df132
SK		 6834 ql_log(ql_log_fatal, base_vha, 0x9002,
6835 "The device failed to resume I/O from slot/link_reset.\n");
14e660e6 6836 }
85880801 6837
3e46f031
LC		 6838 pci_cleanup_aer_uncorrect_error_status(pdev);
6839
85880801 6840 ha->flags.eeh_busy = 0;
14e660e6
SJ		 6841}
6842
5601236b
MH		 6843static int qla2xxx_map_queues(struct Scsi_Host *shost)
6844{
d68b850e 6845 int rc;
5601236b
MH		 6846 scsi_qla_host_t *vha = (scsi_qla_host_t *)shost->hostdata;
6847
d68b850e
QT		 6848 if (USER_CTRL_IRQ(vha->hw))
6849 rc = blk_mq_map_queues(&shost->tag_set);
6850 else
f23f5bec 6851 rc = blk_mq_pci_map_queues(&shost->tag_set, vha->hw->pdev, 0);
d68b850e 6852 return rc;
5601236b
MH		 6853}
6854
a55b2d21 6855static const struct pci_error_handlers qla2xxx_err_handler = {
14e660e6
SJ		 6856 .error_detected = qla2xxx_pci_error_detected,
6857 .mmio_enabled = qla2xxx_pci_mmio_enabled,
6858 .slot_reset = qla2xxx_pci_slot_reset,
6859 .resume = qla2xxx_pci_resume,
6860};
6861
5433383e 6862static struct pci_device_id qla2xxx_pci_tbl[] = {
47f5e069
AV		 6863 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) },
6864 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) },
6865 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) },
6866 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) },
6867 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) },
6868 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) },
6869 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) },
6870 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) },
6871 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) },
4d4df193 6872 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) },
47f5e069
AV		 6873 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) },
6874 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) },
c3a2f0df 6875 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) },
6246b8a1 6876 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2031) },
3a03eb79 6877 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) },
a9083016 6878 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) },
650f528f 6879 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8031) },
8ae6d9c7 6880 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISPF001) },
7ec0effd 6881 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8044) },
f73cb695 6882 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2071) },
2c5bbbb2 6883 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2271) },
2b48992f 6884 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2261) },
5433383e
AV		 6885 { 0 },
6886};
6887MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl);
6888
fca29703 6889static struct pci_driver qla2xxx_pci_driver = {
cb63067a 6890 .name = QLA2XXX_DRIVER_NAME,
0a21ef1e
JB		 6891 .driver = {
6892 .owner = THIS_MODULE,
6893 },
fca29703 6894 .id_table = qla2xxx_pci_tbl,
7ee61397 6895 .probe = qla2x00_probe_one,
4c993f76 6896 .remove = qla2x00_remove_one,
e30d1756 6897 .shutdown = qla2x00_shutdown,
14e660e6 6898 .err_handler = &qla2xxx_err_handler,
fca29703
AV		 6899};
6900
75ef9de1 6901static const struct file_operations apidev_fops = {
6a03b4cd 6902 .owner = THIS_MODULE,
6038f373 6903 .llseek = noop_llseek,
6a03b4cd
HZ		 6904};
6905
1da177e4
LT		 6906/**
6907 * qla2x00_module_init - Module initialization.
6908 **/
6909static int __init
6910qla2x00_module_init(void)
6911{
fca29703
AV		 6912 int ret = 0;
6913
1da177e4 6914 /* Allocate cache for SRBs. */
354d6b21 6915 srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0,
20c2df83 6916 SLAB_HWCACHE_ALIGN, NULL);
1da177e4 6917 if (srb_cachep == NULL) {
7c3df132
SK		 6918 ql_log(ql_log_fatal, NULL, 0x0001,
6919 "Unable to allocate SRB cache...Failing load!.\n");
1da177e4
LT		 6920 return -ENOMEM;
6921 }
6922
2d70c103
NB		 6923 /* Initialize target kmem_cache and mem_pools */
6924 ret = qlt_init();
6925 if (ret < 0) {
6926 kmem_cache_destroy(srb_cachep);
6927 return ret;
6928 } else if (ret > 0) {
6929 /*
6930 * If initiator mode is explictly disabled by qlt_init(),
6931 * prevent scsi_transport_fc.c:fc_scsi_scan_rport() from
6932 * performing scsi_scan_target() during LOOP UP event.
6933 */
6934 qla2xxx_transport_functions.disable_target_scan = 1;
6935 qla2xxx_transport_vport_functions.disable_target_scan = 1;
6936 }
6937
1da177e4
LT		 6938 /* Derive version string. */
6939 strcpy(qla2x00_version_str, QLA2XXX_VERSION);
11010fec 6940 if (ql2xextended_error_logging)
0181944f 6941 strcat(qla2x00_version_str, "-debug");
fed0f68a
JC		 6942 if (ql2xextended_error_logging == 1)
6943 ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK;
0181944f 6944
1c97a12a
AV		 6945 qla2xxx_transport_template =
6946 fc_attach_transport(&qla2xxx_transport_functions);
2c3dfe3f
SJ		 6947 if (!qla2xxx_transport_template) {
6948 kmem_cache_destroy(srb_cachep);
7c3df132
SK		 6949 ql_log(ql_log_fatal, NULL, 0x0002,
6950 "fc_attach_transport failed...Failing load!.\n");
2d70c103 6951 qlt_exit();
1da177e4 6952 return -ENODEV;
2c3dfe3f 6953 }
6a03b4cd
HZ		 6954
6955 apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops);
6956 if (apidev_major < 0) {
7c3df132
SK		 6957 ql_log(ql_log_fatal, NULL, 0x0003,
6958 "Unable to register char device %s.\n", QLA2XXX_APIDEV);
6a03b4cd
HZ		 6959 }
6960
2c3dfe3f
SJ		 6961 qla2xxx_transport_vport_template =
6962 fc_attach_transport(&qla2xxx_transport_vport_functions);
6963 if (!qla2xxx_transport_vport_template) {
6964 kmem_cache_destroy(srb_cachep);
2d70c103 6965 qlt_exit();
2c3dfe3f 6966 fc_release_transport(qla2xxx_transport_template);
7c3df132
SK		 6967 ql_log(ql_log_fatal, NULL, 0x0004,
6968 "fc_attach_transport vport failed...Failing load!.\n");
1da177e4 6969 return -ENODEV;
2c3dfe3f 6970 }
7c3df132
SK		 6971 ql_log(ql_log_info, NULL, 0x0005,
6972 "QLogic Fibre Channel HBA Driver: %s.\n",
fd9a29f0 6973 qla2x00_version_str);
7ee61397 6974 ret = pci_register_driver(&qla2xxx_pci_driver);
fca29703
AV		 6975 if (ret) {
6976 kmem_cache_destroy(srb_cachep);
2d70c103 6977 qlt_exit();
fca29703 6978 fc_release_transport(qla2xxx_transport_template);
2c3dfe3f 6979 fc_release_transport(qla2xxx_transport_vport_template);
7c3df132
SK		 6980 ql_log(ql_log_fatal, NULL, 0x0006,
6981 "pci_register_driver failed...ret=%d Failing load!.\n",
6982 ret);
fca29703
AV		 6983 }
6984 return ret;
1da177e4
LT		 6985}
6986
6987/**
6988 * qla2x00_module_exit - Module cleanup.
6989 **/
6990static void __exit
6991qla2x00_module_exit(void)
6992{
6a03b4cd 6993 unregister_chrdev(apidev_major, QLA2XXX_APIDEV);
7ee61397 6994 pci_unregister_driver(&qla2xxx_pci_driver);
5433383e 6995 qla2x00_release_firmware();
354d6b21 6996 kmem_cache_destroy(srb_cachep);
2d70c103 6997 qlt_exit();
a9083016
GM		 6998 if (ctx_cachep)
6999 kmem_cache_destroy(ctx_cachep);
1da177e4 7000 fc_release_transport(qla2xxx_transport_template);
2c3dfe3f 7001 fc_release_transport(qla2xxx_transport_vport_template);
1da177e4
LT		 7002}
7003
7004module_init(qla2x00_module_init);
7005module_exit(qla2x00_module_exit);
7006
7007MODULE_AUTHOR("QLogic Corporation");
7008MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver");
7009MODULE_LICENSE("GPL");
7010MODULE_VERSION(QLA2XXX_VERSION);
bb8ee499
AV		 7011MODULE_FIRMWARE(FW_FILE_ISP21XX);
7012MODULE_FIRMWARE(FW_FILE_ISP22XX);
7013MODULE_FIRMWARE(FW_FILE_ISP2300);
7014MODULE_FIRMWARE(FW_FILE_ISP2322);
7015MODULE_FIRMWARE(FW_FILE_ISP24XX);
61623fc3 7016MODULE_FIRMWARE(FW_FILE_ISP25XX);
Linux 6.x block layer and io_uring tree(s)