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PCI: Fix comment typo, remove unnecessary !! in pci_is_pcie()
[linux-2.6-block.git] / drivers / scsi / qla2xxx / qla_os.c
CommitLineData
1da177e4 1/*
fa90c54f 2 * QLogic Fibre Channel HBA Driver
1e63395c 3 * Copyright (c) 2003-2013 QLogic Corporation
1da177e4 4 *
fa90c54f 5 * See LICENSE.qla2xxx for copyright and licensing details.
1da177e4
LT		 6 */
7#include "qla_def.h"
8
9#include <linux/moduleparam.h>
10#include <linux/vmalloc.h>
1da177e4 11#include <linux/delay.h>
39a11240 12#include <linux/kthread.h>
e1e82b6f 13#include <linux/mutex.h>
3420d36c 14#include <linux/kobject.h>
5a0e3ad6 15#include <linux/slab.h>
1da177e4
LT		 16#include <scsi/scsi_tcq.h>
17#include <scsi/scsicam.h>
18#include <scsi/scsi_transport.h>
19#include <scsi/scsi_transport_fc.h>
20
2d70c103
NB		 21#include "qla_target.h"
22
1da177e4
LT		 23/*
24 * Driver version
25 */
26char qla2x00_version_str[40];
27
6a03b4cd
HZ		 28static int apidev_major;
29
1da177e4
LT		 30/*
31 * SRB allocation cache
32 */
e18b890b 33static struct kmem_cache *srb_cachep;
1da177e4 34
a9083016
GM		 35/*
36 * CT6 CTX allocation cache
37 */
38static struct kmem_cache *ctx_cachep;
3ce8866c
SK		 39/*
40 * error level for logging
41 */
42int ql_errlev = ql_log_all;
a9083016 43
fa492630 44static int ql2xenableclass2;
2d70c103
NB		 45module_param(ql2xenableclass2, int, S_IRUGO|S_IRUSR);
46MODULE_PARM_DESC(ql2xenableclass2,
47 "Specify if Class 2 operations are supported from the very "
48 "beginning. Default is 0 - class 2 not supported.");
49
8ae6d9c7 50
1da177e4 51int ql2xlogintimeout = 20;
f2019cb1 52module_param(ql2xlogintimeout, int, S_IRUGO);
1da177e4
LT		 53MODULE_PARM_DESC(ql2xlogintimeout,
54 "Login timeout value in seconds.");
55
a7b61842 56int qlport_down_retry;
f2019cb1 57module_param(qlport_down_retry, int, S_IRUGO);
1da177e4 58MODULE_PARM_DESC(qlport_down_retry,
900d9f98 59 "Maximum number of command retries to a port that returns "
1da177e4
LT		 60 "a PORT-DOWN status.");
61
1da177e4
LT		 62int ql2xplogiabsentdevice;
63module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR);
64MODULE_PARM_DESC(ql2xplogiabsentdevice,
65 "Option to enable PLOGI to devices that are not present after "
900d9f98 66 "a Fabric scan. This is needed for several broken switches. "
1da177e4
LT		 67 "Default is 0 - no PLOGI. 1 - perfom PLOGI.");
68
1da177e4 69int ql2xloginretrycount = 0;
f2019cb1 70module_param(ql2xloginretrycount, int, S_IRUGO);
1da177e4
LT		 71MODULE_PARM_DESC(ql2xloginretrycount,
72 "Specify an alternate value for the NVRAM login retry count.");
73
a7a167bf 74int ql2xallocfwdump = 1;
f2019cb1 75module_param(ql2xallocfwdump, int, S_IRUGO);
a7a167bf
AV		 76MODULE_PARM_DESC(ql2xallocfwdump,
77 "Option to enable allocation of memory for a firmware dump "
78 "during HBA initialization. Memory allocation requirements "
79 "vary by ISP type. Default is 1 - allocate memory.");
80
11010fec 81int ql2xextended_error_logging;
27d94035 82module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
11010fec 83MODULE_PARM_DESC(ql2xextended_error_logging,
3ce8866c
SK		 84 "Option to enable extended error logging,\n"
85 "\t\tDefault is 0 - no logging. 0x40000000 - Module Init & Probe.\n"
86 "\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n"
87 "\t\t0x08000000 - IO tracing. 0x04000000 - DPC Thread.\n"
88 "\t\t0x02000000 - Async events. 0x01000000 - Timer routines.\n"
89 "\t\t0x00800000 - User space. 0x00400000 - Task Management.\n"
90 "\t\t0x00200000 - AER/EEH. 0x00100000 - Multi Q.\n"
91 "\t\t0x00080000 - P3P Specific. 0x00040000 - Virtual Port.\n"
92 "\t\t0x00020000 - Buffer Dump. 0x00010000 - Misc.\n"
29f9f90c
CD		 93 "\t\t0x00008000 - Verbose. 0x00004000 - Target.\n"
94 "\t\t0x00002000 - Target Mgmt. 0x00001000 - Target TMF.\n"
3ce8866c 95 "\t\t0x7fffffff - For enabling all logs, can be too many logs.\n"
cfb0919c
CD		 96 "\t\t0x1e400000 - Preferred value for capturing essential "
97 "debug information (equivalent to old "
98 "ql2xextended_error_logging=1).\n"
3ce8866c 99 "\t\tDo LOGICAL OR of the value to enable more than one level");
0181944f 100
a9083016 101int ql2xshiftctondsd = 6;
f2019cb1 102module_param(ql2xshiftctondsd, int, S_IRUGO);
a9083016
GM		 103MODULE_PARM_DESC(ql2xshiftctondsd,
104 "Set to control shifting of command type processing "
105 "based on total number of SG elements.");
106
7e47e5ca 107int ql2xfdmienable=1;
f2019cb1 108module_param(ql2xfdmienable, int, S_IRUGO);
cca5335c 109MODULE_PARM_DESC(ql2xfdmienable,
7794a5af
FW		 110 "Enables FDMI registrations. "
111 "0 - no FDMI. Default is 1 - perform FDMI.");
cca5335c 112
3c290d0b 113int ql2xmaxqdepth = MAX_Q_DEPTH;
df7baa50
AV		 114module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR);
115MODULE_PARM_DESC(ql2xmaxqdepth,
e92e4a8f
CD		 116 "Maximum queue depth to set for each LUN. "
117 "Default is 32.");
df7baa50 118
9e522cd8
AE		 119int ql2xenabledif = 2;
120module_param(ql2xenabledif, int, S_IRUGO);
bad75002
AE		 121MODULE_PARM_DESC(ql2xenabledif,
122 " Enable T10-CRC-DIF "
8cb2049c
AE		 123 " Default is 0 - No DIF Support. 1 - Enable it"
124 ", 2 - Enable DIF for all types, except Type 0.");
bad75002 125
8cb2049c 126int ql2xenablehba_err_chk = 2;
bad75002
AE		 127module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR);
128MODULE_PARM_DESC(ql2xenablehba_err_chk,
8cb2049c
AE		 129 " Enable T10-CRC-DIF Error isolation by HBA:\n"
130 " Default is 1.\n"
131 " 0 -- Error isolation disabled\n"
132 " 1 -- Error isolation enabled only for DIX Type 0\n"
133 " 2 -- Error isolation enabled for all Types\n");
bad75002 134
e5896bd5 135int ql2xiidmaenable=1;
f2019cb1 136module_param(ql2xiidmaenable, int, S_IRUGO);
e5896bd5
AV		 137MODULE_PARM_DESC(ql2xiidmaenable,
138 "Enables iIDMA settings "
139 "Default is 1 - perform iIDMA. 0 - no iIDMA.");
140
73208dfd 141int ql2xmaxqueues = 1;
f2019cb1 142module_param(ql2xmaxqueues, int, S_IRUGO);
73208dfd
AC		 143MODULE_PARM_DESC(ql2xmaxqueues,
144 "Enables MQ settings "
ae68230c
JP		 145 "Default is 1 for single queue. Set it to number "
146 "of queues in MQ mode.");
68ca949c
AC		 147
148int ql2xmultique_tag;
f2019cb1 149module_param(ql2xmultique_tag, int, S_IRUGO);
68ca949c
AC		 150MODULE_PARM_DESC(ql2xmultique_tag,
151 "Enables CPU affinity settings for the driver "
152 "Default is 0 for no affinity of request and response IO. "
153 "Set it to 1 to turn on the cpu affinity.");
e337d907
AV		 154
155int ql2xfwloadbin;
86e45bf6 156module_param(ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
e337d907 157MODULE_PARM_DESC(ql2xfwloadbin,
7c3df132
SK		 158 "Option to specify location from which to load ISP firmware:.\n"
159 " 2 -- load firmware via the request_firmware() (hotplug).\n"
e337d907
AV		 160 " interface.\n"
161 " 1 -- load firmware from flash.\n"
162 " 0 -- use default semantics.\n");
163
ae97c91e 164int ql2xetsenable;
f2019cb1 165module_param(ql2xetsenable, int, S_IRUGO);
ae97c91e
AV		 166MODULE_PARM_DESC(ql2xetsenable,
167 "Enables firmware ETS burst."
168 "Default is 0 - skip ETS enablement.");
169
6907869d 170int ql2xdbwr = 1;
86e45bf6 171module_param(ql2xdbwr, int, S_IRUGO|S_IWUSR);
a9083016 172MODULE_PARM_DESC(ql2xdbwr,
08de2844
GM		 173 "Option to specify scheme for request queue posting.\n"
174 " 0 -- Regular doorbell.\n"
175 " 1 -- CAMRAM doorbell (faster).\n");
a9083016 176
f4c496c1 177int ql2xtargetreset = 1;
f2019cb1 178module_param(ql2xtargetreset, int, S_IRUGO);
f4c496c1
GM		 179MODULE_PARM_DESC(ql2xtargetreset,
180 "Enable target reset."
181 "Default is 1 - use hw defaults.");
182
4da26e16 183int ql2xgffidenable;
f2019cb1 184module_param(ql2xgffidenable, int, S_IRUGO);
4da26e16
CD		 185MODULE_PARM_DESC(ql2xgffidenable,
186 "Enables GFF_ID checks of port type. "
187 "Default is 0 - Do not use GFF_ID information.");
a9083016 188
3822263e 189int ql2xasynctmfenable;
f2019cb1 190module_param(ql2xasynctmfenable, int, S_IRUGO);
3822263e
MI		 191MODULE_PARM_DESC(ql2xasynctmfenable,
192 "Enables issue of TM IOCBs asynchronously via IOCB mechanism"
193 "Default is 0 - Issue TM IOCBs via mailbox mechanism.");
ed0de87c
GM		 194
195int ql2xdontresethba;
86e45bf6 196module_param(ql2xdontresethba, int, S_IRUGO|S_IWUSR);
ed0de87c 197MODULE_PARM_DESC(ql2xdontresethba,
08de2844
GM		 198 "Option to specify reset behaviour.\n"
199 " 0 (Default) -- Reset on failure.\n"
200 " 1 -- Do not reset on failure.\n");
ed0de87c 201
82515920
AV		 202uint ql2xmaxlun = MAX_LUNS;
203module_param(ql2xmaxlun, uint, S_IRUGO);
204MODULE_PARM_DESC(ql2xmaxlun,
205 "Defines the maximum LU number to register with the SCSI "
206 "midlayer. Default is 65535.");
207
08de2844
GM		 208int ql2xmdcapmask = 0x1F;
209module_param(ql2xmdcapmask, int, S_IRUGO);
210MODULE_PARM_DESC(ql2xmdcapmask,
211 "Set the Minidump driver capture mask level. "
6e96fa7b 212 "Default is 0x1F - Can be set to 0x3, 0x7, 0xF, 0x1F, 0x7F.");
08de2844 213
3aadff35 214int ql2xmdenable = 1;
08de2844
GM		 215module_param(ql2xmdenable, int, S_IRUGO);
216MODULE_PARM_DESC(ql2xmdenable,
217 "Enable/disable MiniDump. "
3aadff35
GM		 218 "0 - MiniDump disabled. "
219 "1 (Default) - MiniDump enabled.");
08de2844 220
1da177e4 221/*
fa2a1ce5 222 * SCSI host template entry points
1da177e4
LT		 223 */
224static int qla2xxx_slave_configure(struct scsi_device * device);
f4f051eb 225static int qla2xxx_slave_alloc(struct scsi_device *);
1e99e33a
AV		 226static int qla2xxx_scan_finished(struct Scsi_Host *, unsigned long time);
227static void qla2xxx_scan_start(struct Scsi_Host *);
f4f051eb 228static void qla2xxx_slave_destroy(struct scsi_device *);
f281233d 229static int qla2xxx_queuecommand(struct Scsi_Host *h, struct scsi_cmnd *cmd);
1da177e4
LT		 230static int qla2xxx_eh_abort(struct scsi_cmnd *);
231static int qla2xxx_eh_device_reset(struct scsi_cmnd *);
523ec773 232static int qla2xxx_eh_target_reset(struct scsi_cmnd *);
1da177e4
LT		 233static int qla2xxx_eh_bus_reset(struct scsi_cmnd *);
234static int qla2xxx_eh_host_reset(struct scsi_cmnd *);
1da177e4 235
e881a172 236static int qla2x00_change_queue_depth(struct scsi_device *, int, int);
ce7e4af7 237static int qla2x00_change_queue_type(struct scsi_device *, int);
3491255e 238static void qla2x00_free_device(scsi_qla_host_t *);
ce7e4af7 239
a5326f86 240struct scsi_host_template qla2xxx_driver_template = {
1da177e4 241 .module = THIS_MODULE,
cb63067a 242 .name = QLA2XXX_DRIVER_NAME,
a5326f86 243 .queuecommand = qla2xxx_queuecommand,
fca29703
AV		 244
245 .eh_abort_handler = qla2xxx_eh_abort,
246 .eh_device_reset_handler = qla2xxx_eh_device_reset,
523ec773 247 .eh_target_reset_handler = qla2xxx_eh_target_reset,
fca29703
AV		 248 .eh_bus_reset_handler = qla2xxx_eh_bus_reset,
249 .eh_host_reset_handler = qla2xxx_eh_host_reset,
250
251 .slave_configure = qla2xxx_slave_configure,
252
253 .slave_alloc = qla2xxx_slave_alloc,
254 .slave_destroy = qla2xxx_slave_destroy,
ed677086
AV		 255 .scan_finished = qla2xxx_scan_finished,
256 .scan_start = qla2xxx_scan_start,
ce7e4af7
AV		 257 .change_queue_depth = qla2x00_change_queue_depth,
258 .change_queue_type = qla2x00_change_queue_type,
fca29703
AV		 259 .this_id = -1,
260 .cmd_per_lun = 3,
261 .use_clustering = ENABLE_CLUSTERING,
262 .sg_tablesize = SG_ALL,
263
264 .max_sectors = 0xFFFF,
afb046e2 265 .shost_attrs = qla2x00_host_attrs,
2d70c103
NB		 266
267 .supported_mode = MODE_INITIATOR,
fca29703
AV		 268};
269
1da177e4 270static struct scsi_transport_template *qla2xxx_transport_template = NULL;
2c3dfe3f 271struct scsi_transport_template *qla2xxx_transport_vport_template = NULL;
1da177e4 272
1da177e4
LT		 273/* TODO Convert to inlines
274 *
275 * Timer routines
276 */
1da177e4 277
2c3dfe3f 278__inline__ void
e315cd28 279qla2x00_start_timer(scsi_qla_host_t *vha, void *func, unsigned long interval)
1da177e4 280{
e315cd28
AC		 281 init_timer(&vha->timer);
282 vha->timer.expires = jiffies + interval * HZ;
283 vha->timer.data = (unsigned long)vha;
284 vha->timer.function = (void (*)(unsigned long))func;
285 add_timer(&vha->timer);
286 vha->timer_active = 1;
1da177e4
LT		 287}
288
289static inline void
e315cd28 290qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval)
1da177e4 291{
a9083016 292 /* Currently used for 82XX only. */
7c3df132
SK		 293 if (vha->device_flags & DFLG_DEV_FAILED) {
294 ql_dbg(ql_dbg_timer, vha, 0x600d,
295 "Device in a failed state, returning.\n");
a9083016 296 return;
7c3df132 297 }
a9083016 298
e315cd28 299 mod_timer(&vha->timer, jiffies + interval * HZ);
1da177e4
LT		 300}
301
a824ebb3 302static __inline__ void
e315cd28 303qla2x00_stop_timer(scsi_qla_host_t *vha)
1da177e4 304{
e315cd28
AC		 305 del_timer_sync(&vha->timer);
306 vha->timer_active = 0;
1da177e4
LT		 307}
308
1da177e4
LT		 309static int qla2x00_do_dpc(void *data);
310
311static void qla2x00_rst_aen(scsi_qla_host_t *);
312
73208dfd
AC		 313static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t,
314 struct req_que **, struct rsp_que **);
e30d1756 315static void qla2x00_free_fw_dump(struct qla_hw_data *);
e315cd28 316static void qla2x00_mem_free(struct qla_hw_data *);
1da177e4 317
1da177e4 318/* -------------------------------------------------------------------------- */
9a347ff4
CD		 319static int qla2x00_alloc_queues(struct qla_hw_data *ha, struct req_que *req,
320 struct rsp_que *rsp)
73208dfd 321{
7c3df132 322 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2afa19a9 323 ha->req_q_map = kzalloc(sizeof(struct req_que *) * ha->max_req_queues,
73208dfd
AC		 324 GFP_KERNEL);
325 if (!ha->req_q_map) {
7c3df132
SK		 326 ql_log(ql_log_fatal, vha, 0x003b,
327 "Unable to allocate memory for request queue ptrs.\n");
73208dfd
AC		 328 goto fail_req_map;
329 }
330
2afa19a9 331 ha->rsp_q_map = kzalloc(sizeof(struct rsp_que *) * ha->max_rsp_queues,
73208dfd
AC		 332 GFP_KERNEL);
333 if (!ha->rsp_q_map) {
7c3df132
SK		 334 ql_log(ql_log_fatal, vha, 0x003c,
335 "Unable to allocate memory for response queue ptrs.\n");
73208dfd
AC		 336 goto fail_rsp_map;
337 }
9a347ff4
CD		 338 /*
339 * Make sure we record at least the request and response queue zero in
340 * case we need to free them if part of the probe fails.
341 */
342 ha->rsp_q_map[0] = rsp;
343 ha->req_q_map[0] = req;
73208dfd
AC		 344 set_bit(0, ha->rsp_qid_map);
345 set_bit(0, ha->req_qid_map);
346 return 1;
347
348fail_rsp_map:
349 kfree(ha->req_q_map);
350 ha->req_q_map = NULL;
351fail_req_map:
352 return -ENOMEM;
353}
354
2afa19a9 355static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req)
73208dfd 356{
8ae6d9c7
GM		 357 if (IS_QLAFX00(ha)) {
358 if (req && req->ring_fx00)
359 dma_free_coherent(&ha->pdev->dev,
360 (req->length_fx00 + 1) * sizeof(request_t),
361 req->ring_fx00, req->dma_fx00);
362 } else if (req && req->ring)
73208dfd
AC		 363 dma_free_coherent(&ha->pdev->dev,
364 (req->length + 1) * sizeof(request_t),
365 req->ring, req->dma);
366
8d93f550
CD		 367 if (req)
368 kfree(req->outstanding_cmds);
369
73208dfd
AC		 370 kfree(req);
371 req = NULL;
372}
373
2afa19a9
AC		 374static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp)
375{
8ae6d9c7
GM		 376 if (IS_QLAFX00(ha)) {
377 if (rsp && rsp->ring)
378 dma_free_coherent(&ha->pdev->dev,
379 (rsp->length_fx00 + 1) * sizeof(request_t),
380 rsp->ring_fx00, rsp->dma_fx00);
381 } else if (rsp && rsp->ring) {
2afa19a9
AC		 382 dma_free_coherent(&ha->pdev->dev,
383 (rsp->length + 1) * sizeof(response_t),
384 rsp->ring, rsp->dma);
8ae6d9c7 385 }
2afa19a9
AC		 386 kfree(rsp);
387 rsp = NULL;
388}
389
73208dfd
AC		 390static void qla2x00_free_queues(struct qla_hw_data *ha)
391{
392 struct req_que *req;
393 struct rsp_que *rsp;
394 int cnt;
395
2afa19a9 396 for (cnt = 0; cnt < ha->max_req_queues; cnt++) {
73208dfd 397 req = ha->req_q_map[cnt];
2afa19a9 398 qla2x00_free_req_que(ha, req);
73208dfd 399 }
73208dfd
AC		 400 kfree(ha->req_q_map);
401 ha->req_q_map = NULL;
2afa19a9
AC		 402
403 for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) {
404 rsp = ha->rsp_q_map[cnt];
405 qla2x00_free_rsp_que(ha, rsp);
406 }
407 kfree(ha->rsp_q_map);
408 ha->rsp_q_map = NULL;
73208dfd
AC		 409}
410
68ca949c
AC		 411static int qla25xx_setup_mode(struct scsi_qla_host *vha)
412{
413 uint16_t options = 0;
414 int ques, req, ret;
415 struct qla_hw_data *ha = vha->hw;
416
7163ea81 417 if (!(ha->fw_attributes & BIT_6)) {
7c3df132
SK		 418 ql_log(ql_log_warn, vha, 0x00d8,
419 "Firmware is not multi-queue capable.\n");
7163ea81
AC		 420 goto fail;
421 }
68ca949c 422 if (ql2xmultique_tag) {
68ca949c
AC		 423 /* create a request queue for IO */
424 options |= BIT_7;
425 req = qla25xx_create_req_que(ha, options, 0, 0, -1,
426 QLA_DEFAULT_QUE_QOS);
427 if (!req) {
7c3df132
SK		 428 ql_log(ql_log_warn, vha, 0x00e0,
429 "Failed to create request queue.\n");
68ca949c
AC		 430 goto fail;
431 }
278274d5 432 ha->wq = alloc_workqueue("qla2xxx_wq", WQ_MEM_RECLAIM, 1);
68ca949c
AC		 433 vha->req = ha->req_q_map[req];
434 options |= BIT_1;
435 for (ques = 1; ques < ha->max_rsp_queues; ques++) {
436 ret = qla25xx_create_rsp_que(ha, options, 0, 0, req);
437 if (!ret) {
7c3df132
SK		 438 ql_log(ql_log_warn, vha, 0x00e8,
439 "Failed to create response queue.\n");
68ca949c
AC		 440 goto fail2;
441 }
442 }
7163ea81 443 ha->flags.cpu_affinity_enabled = 1;
7c3df132
SK		 444 ql_dbg(ql_dbg_multiq, vha, 0xc007,
445 "CPU affinity mode enalbed, "
446 "no. of response queues:%d no. of request queues:%d.\n",
447 ha->max_rsp_queues, ha->max_req_queues);
448 ql_dbg(ql_dbg_init, vha, 0x00e9,
449 "CPU affinity mode enalbed, "
450 "no. of response queues:%d no. of request queues:%d.\n",
451 ha->max_rsp_queues, ha->max_req_queues);
68ca949c
AC		 452 }
453 return 0;
454fail2:
455 qla25xx_delete_queues(vha);
7163ea81
AC		 456 destroy_workqueue(ha->wq);
457 ha->wq = NULL;
0cd33fcf 458 vha->req = ha->req_q_map[0];
68ca949c
AC		 459fail:
460 ha->mqenable = 0;
7163ea81
AC		 461 kfree(ha->req_q_map);
462 kfree(ha->rsp_q_map);
463 ha->max_req_queues = ha->max_rsp_queues = 1;
68ca949c
AC		 464 return 1;
465}
466
1da177e4 467static char *
e315cd28 468qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str)
1da177e4 469{
e315cd28 470 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 471 static char *pci_bus_modes[] = {
472 "33", "66", "100", "133",
473 };
474 uint16_t pci_bus;
475
476 strcpy(str, "PCI");
477 pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9;
478 if (pci_bus) {
479 strcat(str, "-X (");
480 strcat(str, pci_bus_modes[pci_bus]);
481 } else {
482 pci_bus = (ha->pci_attr & BIT_8) >> 8;
483 strcat(str, " (");
484 strcat(str, pci_bus_modes[pci_bus]);
485 }
486 strcat(str, " MHz)");
487
488 return (str);
489}
490
fca29703 491static char *
e315cd28 492qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str)
fca29703
AV		 493{
494 static char *pci_bus_modes[] = { "33", "66", "100", "133", };
e315cd28 495 struct qla_hw_data *ha = vha->hw;
fca29703
AV		 496 uint32_t pci_bus;
497 int pcie_reg;
498
e67f1321 499 pcie_reg = pci_pcie_cap(ha->pdev);
fca29703
AV		 500 if (pcie_reg) {
501 char lwstr[6];
502 uint16_t pcie_lstat, lspeed, lwidth;
503
e67f1321 504 pcie_reg += PCI_EXP_LNKCAP;
fca29703
AV		 505 pci_read_config_word(ha->pdev, pcie_reg, &pcie_lstat);
506 lspeed = pcie_lstat & (BIT_0 | BIT_1 | BIT_2 | BIT_3);
507 lwidth = (pcie_lstat &
508 (BIT_4 | BIT_5 | BIT_6 | BIT_7 | BIT_8 | BIT_9)) >> 4;
509
510 strcpy(str, "PCIe (");
49300af7
SK		 511 switch (lspeed) {
512 case 1:
c87a0d8c 513 strcat(str, "2.5GT/s ");
49300af7
SK		 514 break;
515 case 2:
c87a0d8c 516 strcat(str, "5.0GT/s ");
49300af7
SK		 517 break;
518 case 3:
519 strcat(str, "8.0GT/s ");
520 break;
521 default:
fca29703 522 strcat(str, "<unknown> ");
49300af7
SK		 523 break;
524 }
fca29703
AV		 525 snprintf(lwstr, sizeof(lwstr), "x%d)", lwidth);
526 strcat(str, lwstr);
527
528 return str;
529 }
530
531 strcpy(str, "PCI");
532 pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8;
533 if (pci_bus == 0 || pci_bus == 8) {
534 strcat(str, " (");
535 strcat(str, pci_bus_modes[pci_bus >> 3]);
536 } else {
537 strcat(str, "-X ");
538 if (pci_bus & BIT_2)
539 strcat(str, "Mode 2");
540 else
541 strcat(str, "Mode 1");
542 strcat(str, " (");
543 strcat(str, pci_bus_modes[pci_bus & ~BIT_2]);
544 }
545 strcat(str, " MHz)");
546
547 return str;
548}
549
e5f82ab8 550static char *
e315cd28 551qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str)
1da177e4
LT		 552{
553 char un_str[10];
e315cd28 554 struct qla_hw_data *ha = vha->hw;
fa2a1ce5 555
1da177e4
LT		 556 sprintf(str, "%d.%02d.%02d ", ha->fw_major_version,
557 ha->fw_minor_version,
558 ha->fw_subminor_version);
559
560 if (ha->fw_attributes & BIT_9) {
561 strcat(str, "FLX");
562 return (str);
563 }
564
565 switch (ha->fw_attributes & 0xFF) {
566 case 0x7:
567 strcat(str, "EF");
568 break;
569 case 0x17:
570 strcat(str, "TP");
571 break;
572 case 0x37:
573 strcat(str, "IP");
574 break;
575 case 0x77:
576 strcat(str, "VI");
577 break;
578 default:
579 sprintf(un_str, "(%x)", ha->fw_attributes);
580 strcat(str, un_str);
581 break;
582 }
583 if (ha->fw_attributes & 0x100)
584 strcat(str, "X");
585
586 return (str);
587}
588
e5f82ab8 589static char *
e315cd28 590qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str)
fca29703 591{
e315cd28 592 struct qla_hw_data *ha = vha->hw;
f0883ac6 593
3a03eb79
AV		 594 sprintf(str, "%d.%02d.%02d (%x)", ha->fw_major_version,
595 ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes);
fca29703 596 return str;
fca29703
AV		 597}
598
9ba56b95
GM		 599void
600qla2x00_sp_free_dma(void *vha, void *ptr)
fca29703 601{
9ba56b95
GM		 602 srb_t *sp = (srb_t *)ptr;
603 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
604 struct qla_hw_data *ha = sp->fcport->vha->hw;
605 void *ctx = GET_CMD_CTX_SP(sp);
fca29703 606
9ba56b95
GM		 607 if (sp->flags & SRB_DMA_VALID) {
608 scsi_dma_unmap(cmd);
609 sp->flags &= ~SRB_DMA_VALID;
7c3df132 610 }
fca29703 611
9ba56b95
GM		 612 if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
613 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
614 scsi_prot_sg_count(cmd), cmd->sc_data_direction);
615 sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
616 }
617
618 if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
619 /* List assured to be having elements */
620 qla2x00_clean_dsd_pool(ha, sp);
621 sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
622 }
623
624 if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
625 dma_pool_free(ha->dl_dma_pool, ctx,
626 ((struct crc_context *)ctx)->crc_ctx_dma);
627 sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
628 }
629
630 if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
631 struct ct6_dsd *ctx1 = (struct ct6_dsd *)ctx;
fca29703 632
9ba56b95
GM		 633 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd,
634 ctx1->fcp_cmnd_dma);
635 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list);
636 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt;
637 ha->gbl_dsd_avail += ctx1->dsd_use_cnt;
638 mempool_free(ctx1, ha->ctx_mempool);
639 ctx1 = NULL;
640 }
641
642 CMD_SP(cmd) = NULL;
b00ee7d7 643 qla2x00_rel_sp(sp->fcport->vha, sp);
9ba56b95
GM		 644}
645
14b06808 646static void
9ba56b95
GM		 647qla2x00_sp_compl(void *data, void *ptr, int res)
648{
649 struct qla_hw_data *ha = (struct qla_hw_data *)data;
650 srb_t *sp = (srb_t *)ptr;
651 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
652
653 cmd->result = res;
654
655 if (atomic_read(&sp->ref_count) == 0) {
656 ql_dbg(ql_dbg_io, sp->fcport->vha, 0x3015,
657 "SP reference-count to ZERO -- sp=%p cmd=%p.\n",
658 sp, GET_CMD_SP(sp));
659 if (ql2xextended_error_logging & ql_dbg_io)
660 BUG();
661 return;
662 }
663 if (!atomic_dec_and_test(&sp->ref_count))
664 return;
665
666 qla2x00_sp_free_dma(ha, sp);
667 cmd->scsi_done(cmd);
fca29703
AV		 668}
669
8ae6d9c7
GM		 670/* If we are SP1 here, we need to still take and release the host_lock as SP1
671 * does not have the changes necessary to avoid taking host->host_lock.
672 */
1da177e4 673static int
f5e3e40b 674qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
fca29703 675{
134ae078 676 scsi_qla_host_t *vha = shost_priv(host);
fca29703 677 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
19a7b4ae 678 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
e315cd28
AC		 679 struct qla_hw_data *ha = vha->hw;
680 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
fca29703
AV		 681 srb_t *sp;
682 int rval;
683
85880801 684 if (ha->flags.eeh_busy) {
7c3df132 685 if (ha->flags.pci_channel_io_perm_failure) {
5f28d2d7 686 ql_dbg(ql_dbg_aer, vha, 0x9010,
7c3df132
SK		 687 "PCI Channel IO permanent failure, exiting "
688 "cmd=%p.\n", cmd);
b9b12f73 689 cmd->result = DID_NO_CONNECT << 16;
7c3df132 690 } else {
5f28d2d7 691 ql_dbg(ql_dbg_aer, vha, 0x9011,
7c3df132 692 "EEH_Busy, Requeuing the cmd=%p.\n", cmd);
85880801 693 cmd->result = DID_REQUEUE << 16;
7c3df132 694 }
14e660e6
SJ		 695 goto qc24_fail_command;
696 }
697
19a7b4ae
JSEC		 698 rval = fc_remote_port_chkready(rport);
699 if (rval) {
700 cmd->result = rval;
5f28d2d7 701 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3003,
7c3df132
SK		 702 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
703 cmd, rval);
fca29703
AV		 704 goto qc24_fail_command;
705 }
706
bad75002
AE		 707 if (!vha->flags.difdix_supported &&
708 scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) {
7c3df132
SK		 709 ql_dbg(ql_dbg_io, vha, 0x3004,
710 "DIF Cap not reg, fail DIF capable cmd's:%p.\n",
711 cmd);
bad75002
AE		 712 cmd->result = DID_NO_CONNECT << 16;
713 goto qc24_fail_command;
714 }
aa651be8
CD		 715
716 if (!fcport) {
717 cmd->result = DID_NO_CONNECT << 16;
718 goto qc24_fail_command;
719 }
720
fca29703
AV		 721 if (atomic_read(&fcport->state) != FCS_ONLINE) {
722 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
38170fa8 723 atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
7c3df132
SK		 724 ql_dbg(ql_dbg_io, vha, 0x3005,
725 "Returning DNC, fcport_state=%d loop_state=%d.\n",
726 atomic_read(&fcport->state),
727 atomic_read(&base_vha->loop_state));
fca29703
AV		 728 cmd->result = DID_NO_CONNECT << 16;
729 goto qc24_fail_command;
730 }
7b594131 731 goto qc24_target_busy;
fca29703
AV		 732 }
733
b00ee7d7 734 sp = qla2x00_get_sp(vha, fcport, GFP_ATOMIC);
3c290d0b
CD		 735 if (!sp) {
736 set_bit(HOST_RAMP_DOWN_QUEUE_DEPTH, &vha->dpc_flags);
f5e3e40b 737 goto qc24_host_busy;
3c290d0b 738 }
fca29703 739
9ba56b95
GM		 740 sp->u.scmd.cmd = cmd;
741 sp->type = SRB_SCSI_CMD;
742 atomic_set(&sp->ref_count, 1);
743 CMD_SP(cmd) = (void *)sp;
744 sp->free = qla2x00_sp_free_dma;
745 sp->done = qla2x00_sp_compl;
746
e315cd28 747 rval = ha->isp_ops->start_scsi(sp);
7c3df132 748 if (rval != QLA_SUCCESS) {
53016ed3 749 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3013,
7c3df132 750 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
3c290d0b 751 set_bit(HOST_RAMP_DOWN_QUEUE_DEPTH, &vha->dpc_flags);
fca29703 752 goto qc24_host_busy_free_sp;
7c3df132 753 }
fca29703 754
fca29703
AV		 755 return 0;
756
757qc24_host_busy_free_sp:
9ba56b95 758 qla2x00_sp_free_dma(ha, sp);
fca29703 759
f5e3e40b 760qc24_host_busy:
fca29703
AV		 761 return SCSI_MLQUEUE_HOST_BUSY;
762
7b594131
MC		 763qc24_target_busy:
764 return SCSI_MLQUEUE_TARGET_BUSY;
765
fca29703 766qc24_fail_command:
f5e3e40b 767 cmd->scsi_done(cmd);
fca29703
AV		 768
769 return 0;
770}
771
1da177e4
LT		 772/*
773 * qla2x00_eh_wait_on_command
774 * Waits for the command to be returned by the Firmware for some
775 * max time.
776 *
777 * Input:
1da177e4 778 * cmd = Scsi Command to wait on.
1da177e4
LT		 779 *
780 * Return:
781 * Not Found : 0
782 * Found : 1
783 */
784static int
e315cd28 785qla2x00_eh_wait_on_command(struct scsi_cmnd *cmd)
1da177e4 786{
fe74c71f
AV		 787#define ABORT_POLLING_PERIOD 1000
788#define ABORT_WAIT_ITER ((10 * 1000) / (ABORT_POLLING_PERIOD))
f4f051eb 789 unsigned long wait_iter = ABORT_WAIT_ITER;
85880801
AV		 790 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
791 struct qla_hw_data *ha = vha->hw;
f4f051eb 792 int ret = QLA_SUCCESS;
1da177e4 793
85880801 794 if (unlikely(pci_channel_offline(ha->pdev)) || ha->flags.eeh_busy) {
7c3df132
SK		 795 ql_dbg(ql_dbg_taskm, vha, 0x8005,
796 "Return:eh_wait.\n");
85880801
AV		 797 return ret;
798 }
799
d970432c 800 while (CMD_SP(cmd) && wait_iter--) {
fe74c71f 801 msleep(ABORT_POLLING_PERIOD);
f4f051eb 802 }
803 if (CMD_SP(cmd))
804 ret = QLA_FUNCTION_FAILED;
1da177e4 805
f4f051eb 806 return ret;
1da177e4
LT		 807}
808
809/*
810 * qla2x00_wait_for_hba_online
fa2a1ce5 811 * Wait till the HBA is online after going through
1da177e4
LT		 812 * <= MAX_RETRIES_OF_ISP_ABORT or
813 * finally HBA is disabled ie marked offline
814 *
815 * Input:
816 * ha - pointer to host adapter structure
fa2a1ce5
AV		 817 *
818 * Note:
1da177e4
LT		 819 * Does context switching-Release SPIN_LOCK
820 * (if any) before calling this routine.
821 *
822 * Return:
823 * Success (Adapter is online) : 0
824 * Failed (Adapter is offline/disabled) : 1
825 */
854165f4 826int
e315cd28 827qla2x00_wait_for_hba_online(scsi_qla_host_t *vha)
1da177e4 828{
fca29703
AV		 829 int return_status;
830 unsigned long wait_online;
e315cd28
AC		 831 struct qla_hw_data *ha = vha->hw;
832 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4 833
fa2a1ce5 834 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ);
e315cd28
AC		 835 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
836 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
837 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
838 ha->dpc_active) && time_before(jiffies, wait_online)) {
1da177e4
LT		 839
840 msleep(1000);
841 }
e315cd28 842 if (base_vha->flags.online)
fa2a1ce5 843 return_status = QLA_SUCCESS;
1da177e4
LT		 844 else
845 return_status = QLA_FUNCTION_FAILED;
846
1da177e4
LT		 847 return (return_status);
848}
849
86fbee86
LC		 850/*
851 * qla2x00_wait_for_reset_ready
852 * Wait till the HBA is online after going through
853 * <= MAX_RETRIES_OF_ISP_ABORT or
854 * finally HBA is disabled ie marked offline or flash
855 * operations are in progress.
856 *
857 * Input:
858 * ha - pointer to host adapter structure
859 *
860 * Note:
861 * Does context switching-Release SPIN_LOCK
862 * (if any) before calling this routine.
863 *
864 * Return:
865 * Success (Adapter is online/no flash ops) : 0
866 * Failed (Adapter is offline/disabled/flash ops in progress) : 1
867 */
3dbe756a 868static int
86fbee86
LC		 869qla2x00_wait_for_reset_ready(scsi_qla_host_t *vha)
870{
871 int return_status;
872 unsigned long wait_online;
873 struct qla_hw_data *ha = vha->hw;
874 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
875
876 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ);
877 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
878 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
879 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
880 ha->optrom_state != QLA_SWAITING ||
881 ha->dpc_active) && time_before(jiffies, wait_online))
882 msleep(1000);
883
884 if (base_vha->flags.online && ha->optrom_state == QLA_SWAITING)
885 return_status = QLA_SUCCESS;
886 else
887 return_status = QLA_FUNCTION_FAILED;
888
7c3df132
SK		 889 ql_dbg(ql_dbg_taskm, vha, 0x8019,
890 "%s return status=%d.\n", __func__, return_status);
86fbee86
LC		 891
892 return return_status;
893}
894
2533cf67
LC		 895int
896qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha)
897{
898 int return_status;
899 unsigned long wait_reset;
900 struct qla_hw_data *ha = vha->hw;
901 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
902
903 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ);
904 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
905 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
906 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
907 ha->dpc_active) && time_before(jiffies, wait_reset)) {
908
909 msleep(1000);
910
911 if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) &&
912 ha->flags.chip_reset_done)
913 break;
914 }
915 if (ha->flags.chip_reset_done)
916 return_status = QLA_SUCCESS;
917 else
918 return_status = QLA_FUNCTION_FAILED;
919
920 return return_status;
921}
922
083a469d
GM		 923static void
924sp_get(struct srb *sp)
925{
926 atomic_inc(&sp->ref_count);
927}
928
1da177e4
LT		 929/**************************************************************************
930* qla2xxx_eh_abort
931*
932* Description:
933* The abort function will abort the specified command.
934*
935* Input:
936* cmd = Linux SCSI command packet to be aborted.
937*
938* Returns:
939* Either SUCCESS or FAILED.
940*
941* Note:
2ea00202 942* Only return FAILED if command not returned by firmware.
1da177e4 943**************************************************************************/
e5f82ab8 944static int
1da177e4
LT		 945qla2xxx_eh_abort(struct scsi_cmnd *cmd)
946{
e315cd28 947 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
f4f051eb 948 srb_t *sp;
4e98d3b8 949 int ret;
f4f051eb 950 unsigned int id, lun;
18e144d3 951 unsigned long flags;
2ea00202 952 int wait = 0;
e315cd28 953 struct qla_hw_data *ha = vha->hw;
1da177e4 954
f4f051eb 955 if (!CMD_SP(cmd))
2ea00202 956 return SUCCESS;
1da177e4 957
4e98d3b8
AV		 958 ret = fc_block_scsi_eh(cmd);
959 if (ret != 0)
960 return ret;
961 ret = SUCCESS;
962
f4f051eb 963 id = cmd->device->id;
964 lun = cmd->device->lun;
1da177e4 965
e315cd28 966 spin_lock_irqsave(&ha->hardware_lock, flags);
170babc3
MC		 967 sp = (srb_t *) CMD_SP(cmd);
968 if (!sp) {
969 spin_unlock_irqrestore(&ha->hardware_lock, flags);
970 return SUCCESS;
971 }
1da177e4 972
7c3df132 973 ql_dbg(ql_dbg_taskm, vha, 0x8002,
cfb0919c
CD		 974 "Aborting from RISC nexus=%ld:%d:%d sp=%p cmd=%p\n",
975 vha->host_no, id, lun, sp, cmd);
17d98630 976
170babc3
MC		 977 /* Get a reference to the sp and drop the lock.*/
978 sp_get(sp);
083a469d 979
e315cd28 980 spin_unlock_irqrestore(&ha->hardware_lock, flags);
170babc3 981 if (ha->isp_ops->abort_command(sp)) {
a55aac79 982 ret = FAILED;
7c3df132 983 ql_dbg(ql_dbg_taskm, vha, 0x8003,
cfb0919c 984 "Abort command mbx failed cmd=%p.\n", cmd);
170babc3 985 } else {
7c3df132 986 ql_dbg(ql_dbg_taskm, vha, 0x8004,
cfb0919c 987 "Abort command mbx success cmd=%p.\n", cmd);
170babc3
MC		 988 wait = 1;
989 }
75942064
SK		 990
991 spin_lock_irqsave(&ha->hardware_lock, flags);
9ba56b95 992 sp->done(ha, sp, 0);
75942064 993 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1da177e4 994
bc91ade9
CD		 995 /* Did the command return during mailbox execution? */
996 if (ret == FAILED && !CMD_SP(cmd))
997 ret = SUCCESS;
998
f4f051eb 999 /* Wait for the command to be returned. */
2ea00202 1000 if (wait) {
e315cd28 1001 if (qla2x00_eh_wait_on_command(cmd) != QLA_SUCCESS) {
7c3df132 1002 ql_log(ql_log_warn, vha, 0x8006,
cfb0919c 1003 "Abort handler timed out cmd=%p.\n", cmd);
2ea00202 1004 ret = FAILED;
f4f051eb 1005 }
1da177e4 1006 }
1da177e4 1007
7c3df132 1008 ql_log(ql_log_info, vha, 0x801c,
cfb0919c
CD		 1009 "Abort command issued nexus=%ld:%d:%d -- %d %x.\n",
1010 vha->host_no, id, lun, wait, ret);
1da177e4 1011
f4f051eb 1012 return ret;
1013}
1da177e4 1014
4d78c973 1015int
e315cd28 1016qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t,
4d78c973 1017 unsigned int l, enum nexus_wait_type type)
f4f051eb 1018{
17d98630 1019 int cnt, match, status;
18e144d3 1020 unsigned long flags;
e315cd28 1021 struct qla_hw_data *ha = vha->hw;
73208dfd 1022 struct req_que *req;
4d78c973 1023 srb_t *sp;
9ba56b95 1024 struct scsi_cmnd *cmd;
1da177e4 1025
523ec773 1026 status = QLA_SUCCESS;
17d98630 1027
e315cd28 1028 spin_lock_irqsave(&ha->hardware_lock, flags);
67c2e93a 1029 req = vha->req;
17d98630 1030 for (cnt = 1; status == QLA_SUCCESS &&
8d93f550 1031 cnt < req->num_outstanding_cmds; cnt++) {
17d98630
AC		 1032 sp = req->outstanding_cmds[cnt];
1033 if (!sp)
523ec773 1034 continue;
9ba56b95 1035 if (sp->type != SRB_SCSI_CMD)
cf53b069 1036 continue;
17d98630
AC		 1037 if (vha->vp_idx != sp->fcport->vha->vp_idx)
1038 continue;
1039 match = 0;
9ba56b95 1040 cmd = GET_CMD_SP(sp);
17d98630
AC		 1041 switch (type) {
1042 case WAIT_HOST:
1043 match = 1;
1044 break;
1045 case WAIT_TARGET:
9ba56b95 1046 match = cmd->device->id == t;
17d98630
AC		 1047 break;
1048 case WAIT_LUN:
9ba56b95
GM		 1049 match = (cmd->device->id == t &&
1050 cmd->device->lun == l);
17d98630 1051 break;
73208dfd 1052 }
17d98630
AC		 1053 if (!match)
1054 continue;
1055
1056 spin_unlock_irqrestore(&ha->hardware_lock, flags);
9ba56b95 1057 status = qla2x00_eh_wait_on_command(cmd);
17d98630 1058 spin_lock_irqsave(&ha->hardware_lock, flags);
1da177e4 1059 }
e315cd28 1060 spin_unlock_irqrestore(&ha->hardware_lock, flags);
523ec773
AV		 1061
1062 return status;
1da177e4
LT		 1063}
1064
523ec773
AV		 1065static char *reset_errors[] = {
1066 "HBA not online",
1067 "HBA not ready",
1068 "Task management failed",
1069 "Waiting for command completions",
1070};
1da177e4 1071
e5f82ab8 1072static int
523ec773 1073__qla2xxx_eh_generic_reset(char *name, enum nexus_wait_type type,
2afa19a9 1074 struct scsi_cmnd *cmd, int (*do_reset)(struct fc_port *, unsigned int, int))
1da177e4 1075{
e315cd28 1076 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
bdf79621 1077 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
523ec773 1078 int err;
1da177e4 1079
7c3df132 1080 if (!fcport) {
523ec773 1081 return FAILED;
7c3df132 1082 }
1da177e4 1083
4e98d3b8
AV		 1084 err = fc_block_scsi_eh(cmd);
1085 if (err != 0)
1086 return err;
1087
7c3df132 1088 ql_log(ql_log_info, vha, 0x8009,
cfb0919c 1089 "%s RESET ISSUED nexus=%ld:%d:%d cmd=%p.\n", name, vha->host_no,
7c3df132 1090 cmd->device->id, cmd->device->lun, cmd);
1da177e4 1091
523ec773 1092 err = 0;
7c3df132
SK		 1093 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1094 ql_log(ql_log_warn, vha, 0x800a,
1095 "Wait for hba online failed for cmd=%p.\n", cmd);
523ec773 1096 goto eh_reset_failed;
7c3df132 1097 }
523ec773 1098 err = 2;
2afa19a9 1099 if (do_reset(fcport, cmd->device->lun, cmd->request->cpu + 1)
7c3df132
SK		 1100 != QLA_SUCCESS) {
1101 ql_log(ql_log_warn, vha, 0x800c,
1102 "do_reset failed for cmd=%p.\n", cmd);
523ec773 1103 goto eh_reset_failed;
7c3df132 1104 }
523ec773 1105 err = 3;
e315cd28 1106 if (qla2x00_eh_wait_for_pending_commands(vha, cmd->device->id,
7c3df132
SK		 1107 cmd->device->lun, type) != QLA_SUCCESS) {
1108 ql_log(ql_log_warn, vha, 0x800d,
d6a03581 1109 "wait for pending cmds failed for cmd=%p.\n", cmd);
523ec773 1110 goto eh_reset_failed;
7c3df132 1111 }
523ec773 1112
7c3df132 1113 ql_log(ql_log_info, vha, 0x800e,
cfb0919c
CD		 1114 "%s RESET SUCCEEDED nexus:%ld:%d:%d cmd=%p.\n", name,
1115 vha->host_no, cmd->device->id, cmd->device->lun, cmd);
523ec773
AV		 1116
1117 return SUCCESS;
1118
4d78c973 1119eh_reset_failed:
7c3df132 1120 ql_log(ql_log_info, vha, 0x800f,
cfb0919c
CD		 1121 "%s RESET FAILED: %s nexus=%ld:%d:%d cmd=%p.\n", name,
1122 reset_errors[err], vha->host_no, cmd->device->id, cmd->device->lun,
1123 cmd);
523ec773
AV		 1124 return FAILED;
1125}
1da177e4 1126
523ec773
AV		 1127static int
1128qla2xxx_eh_device_reset(struct scsi_cmnd *cmd)
1129{
e315cd28
AC		 1130 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1131 struct qla_hw_data *ha = vha->hw;
1da177e4 1132
523ec773
AV		 1133 return __qla2xxx_eh_generic_reset("DEVICE", WAIT_LUN, cmd,
1134 ha->isp_ops->lun_reset);
1da177e4
LT		 1135}
1136
1da177e4 1137static int
523ec773 1138qla2xxx_eh_target_reset(struct scsi_cmnd *cmd)
1da177e4 1139{
e315cd28
AC		 1140 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1141 struct qla_hw_data *ha = vha->hw;
1da177e4 1142
523ec773
AV		 1143 return __qla2xxx_eh_generic_reset("TARGET", WAIT_TARGET, cmd,
1144 ha->isp_ops->target_reset);
1da177e4
LT		 1145}
1146
1da177e4
LT		 1147/**************************************************************************
1148* qla2xxx_eh_bus_reset
1149*
1150* Description:
1151* The bus reset function will reset the bus and abort any executing
1152* commands.
1153*
1154* Input:
1155* cmd = Linux SCSI command packet of the command that cause the
1156* bus reset.
1157*
1158* Returns:
1159* SUCCESS/FAILURE (defined as macro in scsi.h).
1160*
1161**************************************************************************/
e5f82ab8 1162static int
1da177e4
LT		 1163qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd)
1164{
e315cd28 1165 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
bdf79621 1166 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
2c3dfe3f 1167 int ret = FAILED;
f4f051eb 1168 unsigned int id, lun;
f4f051eb 1169
f4f051eb 1170 id = cmd->device->id;
1171 lun = cmd->device->lun;
1da177e4 1172
7c3df132 1173 if (!fcport) {
f4f051eb 1174 return ret;
7c3df132 1175 }
1da177e4 1176
4e98d3b8
AV		 1177 ret = fc_block_scsi_eh(cmd);
1178 if (ret != 0)
1179 return ret;
1180 ret = FAILED;
1181
7c3df132 1182 ql_log(ql_log_info, vha, 0x8012,
46270afe 1183 "BUS RESET ISSUED nexus=%ld:%d:%d.\n", vha->host_no, id, lun);
1da177e4 1184
e315cd28 1185 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
7c3df132
SK		 1186 ql_log(ql_log_fatal, vha, 0x8013,
1187 "Wait for hba online failed board disabled.\n");
f4f051eb 1188 goto eh_bus_reset_done;
1da177e4
LT		 1189 }
1190
ad537689
SK		 1191 if (qla2x00_loop_reset(vha) == QLA_SUCCESS)
1192 ret = SUCCESS;
1193
f4f051eb 1194 if (ret == FAILED)
1195 goto eh_bus_reset_done;
1da177e4 1196
9a41a62b 1197 /* Flush outstanding commands. */
4d78c973 1198 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) !=
7c3df132
SK		 1199 QLA_SUCCESS) {
1200 ql_log(ql_log_warn, vha, 0x8014,
1201 "Wait for pending commands failed.\n");
9a41a62b 1202 ret = FAILED;
7c3df132 1203 }
1da177e4 1204
f4f051eb 1205eh_bus_reset_done:
7c3df132 1206 ql_log(ql_log_warn, vha, 0x802b,
cfb0919c 1207 "BUS RESET %s nexus=%ld:%d:%d.\n",
d6a03581 1208 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1da177e4 1209
f4f051eb 1210 return ret;
1da177e4
LT		 1211}
1212
1213/**************************************************************************
1214* qla2xxx_eh_host_reset
1215*
1216* Description:
1217* The reset function will reset the Adapter.
1218*
1219* Input:
1220* cmd = Linux SCSI command packet of the command that cause the
1221* adapter reset.
1222*
1223* Returns:
1224* Either SUCCESS or FAILED.
1225*
1226* Note:
1227**************************************************************************/
e5f82ab8 1228static int
1da177e4
LT		 1229qla2xxx_eh_host_reset(struct scsi_cmnd *cmd)
1230{
e315cd28 1231 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
e315cd28 1232 struct qla_hw_data *ha = vha->hw;
2c3dfe3f 1233 int ret = FAILED;
f4f051eb 1234 unsigned int id, lun;
e315cd28 1235 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4 1236
f4f051eb 1237 id = cmd->device->id;
1238 lun = cmd->device->lun;
f4f051eb 1239
7c3df132 1240 ql_log(ql_log_info, vha, 0x8018,
cfb0919c 1241 "ADAPTER RESET ISSUED nexus=%ld:%d:%d.\n", vha->host_no, id, lun);
1da177e4 1242
86fbee86 1243 if (qla2x00_wait_for_reset_ready(vha) != QLA_SUCCESS)
f4f051eb 1244 goto eh_host_reset_lock;
1da177e4 1245
e315cd28
AC		 1246 if (vha != base_vha) {
1247 if (qla2x00_vp_abort_isp(vha))
f4f051eb 1248 goto eh_host_reset_lock;
e315cd28 1249 } else {
7ec0effd 1250 if (IS_P3P_TYPE(vha->hw)) {
a9083016
GM		 1251 if (!qla82xx_fcoe_ctx_reset(vha)) {
1252 /* Ctx reset success */
1253 ret = SUCCESS;
1254 goto eh_host_reset_lock;
1255 }
1256 /* fall thru if ctx reset failed */
1257 }
68ca949c
AC		 1258 if (ha->wq)
1259 flush_workqueue(ha->wq);
1260
e315cd28 1261 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
a9083016 1262 if (ha->isp_ops->abort_isp(base_vha)) {
e315cd28
AC		 1263 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1264 /* failed. schedule dpc to try */
1265 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
1266
7c3df132
SK		 1267 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1268 ql_log(ql_log_warn, vha, 0x802a,
1269 "wait for hba online failed.\n");
e315cd28 1270 goto eh_host_reset_lock;
7c3df132 1271 }
e315cd28
AC		 1272 }
1273 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
fa2a1ce5 1274 }
1da177e4 1275
e315cd28 1276 /* Waiting for command to be returned to OS.*/
4d78c973 1277 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) ==
e315cd28 1278 QLA_SUCCESS)
f4f051eb 1279 ret = SUCCESS;
1da177e4 1280
f4f051eb 1281eh_host_reset_lock:
cfb0919c
CD		 1282 ql_log(ql_log_info, vha, 0x8017,
1283 "ADAPTER RESET %s nexus=%ld:%d:%d.\n",
1284 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1da177e4 1285
f4f051eb 1286 return ret;
1287}
1da177e4
LT		 1288
1289/*
1290* qla2x00_loop_reset
1291* Issue loop reset.
1292*
1293* Input:
1294* ha = adapter block pointer.
1295*
1296* Returns:
1297* 0 = success
1298*/
a4722cf2 1299int
e315cd28 1300qla2x00_loop_reset(scsi_qla_host_t *vha)
1da177e4 1301{
0c8c39af 1302 int ret;
bdf79621 1303 struct fc_port *fcport;
e315cd28 1304 struct qla_hw_data *ha = vha->hw;
1da177e4 1305
5854771e
AB		 1306 if (IS_QLAFX00(ha)) {
1307 return qlafx00_loop_reset(vha);
1308 }
1309
f4c496c1 1310 if (ql2xtargetreset == 1 && ha->flags.enable_target_reset) {
55e5ed27
AV		 1311 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1312 if (fcport->port_type != FCT_TARGET)
1313 continue;
1314
1315 ret = ha->isp_ops->target_reset(fcport, 0, 0);
1316 if (ret != QLA_SUCCESS) {
7c3df132 1317 ql_dbg(ql_dbg_taskm, vha, 0x802c,
5854771e 1318 "Bus Reset failed: Reset=%d "
7c3df132 1319 "d_id=%x.\n", ret, fcport->d_id.b24);
55e5ed27
AV		 1320 }
1321 }
1322 }
1323
8ae6d9c7 1324
6246b8a1 1325 if (ha->flags.enable_lip_full_login && !IS_CNA_CAPABLE(ha)) {
0b7e7c53
AV		 1326 atomic_set(&vha->loop_state, LOOP_DOWN);
1327 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
1328 qla2x00_mark_all_devices_lost(vha, 0);
e315cd28 1329 ret = qla2x00_full_login_lip(vha);
0c8c39af 1330 if (ret != QLA_SUCCESS) {
7c3df132
SK		 1331 ql_dbg(ql_dbg_taskm, vha, 0x802d,
1332 "full_login_lip=%d.\n", ret);
749af3d5 1333 }
0c8c39af
AV		 1334 }
1335
0d6e61bc 1336 if (ha->flags.enable_lip_reset) {
e315cd28 1337 ret = qla2x00_lip_reset(vha);
ad537689 1338 if (ret != QLA_SUCCESS)
7c3df132
SK		 1339 ql_dbg(ql_dbg_taskm, vha, 0x802e,
1340 "lip_reset failed (%d).\n", ret);
1da177e4
LT		 1341 }
1342
1da177e4 1343 /* Issue marker command only when we are going to start the I/O */
e315cd28 1344 vha->marker_needed = 1;
1da177e4 1345
0c8c39af 1346 return QLA_SUCCESS;
1da177e4
LT		 1347}
1348
df4bf0bb 1349void
e315cd28 1350qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res)
df4bf0bb 1351{
73208dfd 1352 int que, cnt;
df4bf0bb
AV		 1353 unsigned long flags;
1354 srb_t *sp;
e315cd28 1355 struct qla_hw_data *ha = vha->hw;
73208dfd 1356 struct req_que *req;
df4bf0bb
AV		 1357
1358 spin_lock_irqsave(&ha->hardware_lock, flags);
2afa19a9 1359 for (que = 0; que < ha->max_req_queues; que++) {
29bdccbe 1360 req = ha->req_q_map[que];
73208dfd
AC		 1361 if (!req)
1362 continue;
8d93f550
CD		 1363 if (!req->outstanding_cmds)
1364 continue;
1365 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) {
73208dfd 1366 sp = req->outstanding_cmds[cnt];
e612d465 1367 if (sp) {
73208dfd 1368 req->outstanding_cmds[cnt] = NULL;
9ba56b95 1369 sp->done(vha, sp, res);
73208dfd 1370 }
df4bf0bb
AV		 1371 }
1372 }
1373 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1374}
1375
f4f051eb 1376static int
1377qla2xxx_slave_alloc(struct scsi_device *sdev)
1da177e4 1378{
bdf79621 1379 struct fc_rport *rport = starget_to_rport(scsi_target(sdev));
1da177e4 1380
19a7b4ae 1381 if (!rport || fc_remote_port_chkready(rport))
f4f051eb 1382 return -ENXIO;
bdf79621 1383
19a7b4ae 1384 sdev->hostdata = *(fc_port_t **)rport->dd_data;
1da177e4 1385
f4f051eb 1386 return 0;
1387}
1da177e4 1388
f4f051eb 1389static int
1390qla2xxx_slave_configure(struct scsi_device *sdev)
1391{
e315cd28 1392 scsi_qla_host_t *vha = shost_priv(sdev->host);
2afa19a9 1393 struct req_que *req = vha->req;
8482e118 1394
9e522cd8
AE		 1395 if (IS_T10_PI_CAPABLE(vha->hw))
1396 blk_queue_update_dma_alignment(sdev->request_queue, 0x7);
1397
f4f051eb 1398 if (sdev->tagged_supported)
73208dfd 1399 scsi_activate_tcq(sdev, req->max_q_depth);
f4f051eb 1400 else
73208dfd 1401 scsi_deactivate_tcq(sdev, req->max_q_depth);
f4f051eb 1402 return 0;
1403}
1da177e4 1404
f4f051eb 1405static void
1406qla2xxx_slave_destroy(struct scsi_device *sdev)
1407{
1408 sdev->hostdata = NULL;
1da177e4
LT		 1409}
1410
c45dd305
GM		 1411static void qla2x00_handle_queue_full(struct scsi_device *sdev, int qdepth)
1412{
1413 fc_port_t *fcport = (struct fc_port *) sdev->hostdata;
1414
1415 if (!scsi_track_queue_full(sdev, qdepth))
1416 return;
1417
7c3df132 1418 ql_dbg(ql_dbg_io, fcport->vha, 0x3029,
cfb0919c
CD		 1419 "Queue depth adjusted-down to %d for nexus=%ld:%d:%d.\n",
1420 sdev->queue_depth, fcport->vha->host_no, sdev->id, sdev->lun);
c45dd305
GM		 1421}
1422
1423static void qla2x00_adjust_sdev_qdepth_up(struct scsi_device *sdev, int qdepth)
1424{
1425 fc_port_t *fcport = sdev->hostdata;
1426 struct scsi_qla_host *vha = fcport->vha;
c45dd305
GM		 1427 struct req_que *req = NULL;
1428
1429 req = vha->req;
1430 if (!req)
1431 return;
1432
1433 if (req->max_q_depth <= sdev->queue_depth || req->max_q_depth < qdepth)
1434 return;
1435
1436 if (sdev->ordered_tags)
1437 scsi_adjust_queue_depth(sdev, MSG_ORDERED_TAG, qdepth);
1438 else
1439 scsi_adjust_queue_depth(sdev, MSG_SIMPLE_TAG, qdepth);
1440
7c3df132 1441 ql_dbg(ql_dbg_io, vha, 0x302a,
cfb0919c
CD		 1442 "Queue depth adjusted-up to %d for nexus=%ld:%d:%d.\n",
1443 sdev->queue_depth, fcport->vha->host_no, sdev->id, sdev->lun);
c45dd305
GM		 1444}
1445
ce7e4af7 1446static int
e881a172 1447qla2x00_change_queue_depth(struct scsi_device *sdev, int qdepth, int reason)
ce7e4af7 1448{
c45dd305
GM		 1449 switch (reason) {
1450 case SCSI_QDEPTH_DEFAULT:
1451 scsi_adjust_queue_depth(sdev, scsi_get_tag_type(sdev), qdepth);
1452 break;
1453 case SCSI_QDEPTH_QFULL:
1454 qla2x00_handle_queue_full(sdev, qdepth);
1455 break;
1456 case SCSI_QDEPTH_RAMP_UP:
1457 qla2x00_adjust_sdev_qdepth_up(sdev, qdepth);
1458 break;
1459 default:
08002af2 1460 return -EOPNOTSUPP;
c45dd305 1461 }
e881a172 1462
ce7e4af7
AV		 1463 return sdev->queue_depth;
1464}
1465
1466static int
1467qla2x00_change_queue_type(struct scsi_device *sdev, int tag_type)
1468{
1469 if (sdev->tagged_supported) {
1470 scsi_set_tag_type(sdev, tag_type);
1471 if (tag_type)
1472 scsi_activate_tcq(sdev, sdev->queue_depth);
1473 else
1474 scsi_deactivate_tcq(sdev, sdev->queue_depth);
1475 } else
1476 tag_type = 0;
1477
1478 return tag_type;
1479}
1480
3c290d0b
CD		 1481static void
1482qla2x00_host_ramp_down_queuedepth(scsi_qla_host_t *vha)
1483{
1484 scsi_qla_host_t *vp;
1485 struct Scsi_Host *shost;
1486 struct scsi_device *sdev;
1487 struct qla_hw_data *ha = vha->hw;
1488 unsigned long flags;
1489
1490 ha->host_last_rampdown_time = jiffies;
1491
1492 if (ha->cfg_lun_q_depth <= vha->host->cmd_per_lun)
1493 return;
1494
1495 if ((ha->cfg_lun_q_depth / 2) < vha->host->cmd_per_lun)
1496 ha->cfg_lun_q_depth = vha->host->cmd_per_lun;
1497 else
1498 ha->cfg_lun_q_depth = ha->cfg_lun_q_depth / 2;
1499
1500 /*
1501 * Geometrically ramp down the queue depth for all devices on this
1502 * adapter
1503 */
1504 spin_lock_irqsave(&ha->vport_slock, flags);
1505 list_for_each_entry(vp, &ha->vp_list, list) {
1506 shost = vp->host;
1507 shost_for_each_device(sdev, shost) {
1508 if (sdev->queue_depth > shost->cmd_per_lun) {
1509 if (sdev->queue_depth < ha->cfg_lun_q_depth)
1510 continue;
353d9449 1511 ql_dbg(ql_dbg_io, vp, 0x3031,
3c290d0b
CD		 1512 "%ld:%d:%d: Ramping down queue depth to %d",
1513 vp->host_no, sdev->id, sdev->lun,
1514 ha->cfg_lun_q_depth);
1515 qla2x00_change_queue_depth(sdev,
1516 ha->cfg_lun_q_depth, SCSI_QDEPTH_DEFAULT);
1517 }
1518 }
1519 }
1520 spin_unlock_irqrestore(&ha->vport_slock, flags);
1521
1522 return;
1523}
1524
1525static void
1526qla2x00_host_ramp_up_queuedepth(scsi_qla_host_t *vha)
1527{
1528 scsi_qla_host_t *vp;
1529 struct Scsi_Host *shost;
1530 struct scsi_device *sdev;
1531 struct qla_hw_data *ha = vha->hw;
1532 unsigned long flags;
1533
1534 ha->host_last_rampup_time = jiffies;
1535 ha->cfg_lun_q_depth++;
1536
1537 /*
1538 * Linearly ramp up the queue depth for all devices on this
1539 * adapter
1540 */
1541 spin_lock_irqsave(&ha->vport_slock, flags);
1542 list_for_each_entry(vp, &ha->vp_list, list) {
1543 shost = vp->host;
1544 shost_for_each_device(sdev, shost) {
1545 if (sdev->queue_depth > ha->cfg_lun_q_depth)
1546 continue;
1547 qla2x00_change_queue_depth(sdev, ha->cfg_lun_q_depth,
1548 SCSI_QDEPTH_RAMP_UP);
1549 }
1550 }
1551 spin_unlock_irqrestore(&ha->vport_slock, flags);
1552
1553 return;
1554}
1555
1da177e4
LT		 1556/**
1557 * qla2x00_config_dma_addressing() - Configure OS DMA addressing method.
1558 * @ha: HA context
1559 *
1560 * At exit, the @ha's flags.enable_64bit_addressing set to indicated
1561 * supported addressing method.
1562 */
1563static void
53303c42 1564qla2x00_config_dma_addressing(struct qla_hw_data *ha)
1da177e4 1565{
7524f9b9 1566 /* Assume a 32bit DMA mask. */
1da177e4 1567 ha->flags.enable_64bit_addressing = 0;
1da177e4 1568
6a35528a 1569 if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) {
7524f9b9
AV		 1570 /* Any upper-dword bits set? */
1571 if (MSD(dma_get_required_mask(&ha->pdev->dev)) &&
6a35528a 1572 !pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(64))) {
7524f9b9 1573 /* Ok, a 64bit DMA mask is applicable. */
1da177e4 1574 ha->flags.enable_64bit_addressing = 1;
fd34f556
AV		 1575 ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64;
1576 ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64;
7524f9b9 1577 return;
1da177e4 1578 }
1da177e4 1579 }
7524f9b9 1580
284901a9
YH		 1581 dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32));
1582 pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(32));
1da177e4
LT		 1583}
1584
fd34f556 1585static void
e315cd28 1586qla2x00_enable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1587{
1588 unsigned long flags = 0;
1589 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1590
1591 spin_lock_irqsave(&ha->hardware_lock, flags);
1592 ha->interrupts_on = 1;
1593 /* enable risc and host interrupts */
1594 WRT_REG_WORD(&reg->ictrl, ICR_EN_INT | ICR_EN_RISC);
1595 RD_REG_WORD(&reg->ictrl);
1596 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1597
1598}
1599
1600static void
e315cd28 1601qla2x00_disable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1602{
1603 unsigned long flags = 0;
1604 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1605
1606 spin_lock_irqsave(&ha->hardware_lock, flags);
1607 ha->interrupts_on = 0;
1608 /* disable risc and host interrupts */
1609 WRT_REG_WORD(&reg->ictrl, 0);
1610 RD_REG_WORD(&reg->ictrl);
1611 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1612}
1613
1614static void
e315cd28 1615qla24xx_enable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1616{
1617 unsigned long flags = 0;
1618 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1619
1620 spin_lock_irqsave(&ha->hardware_lock, flags);
1621 ha->interrupts_on = 1;
1622 WRT_REG_DWORD(&reg->ictrl, ICRX_EN_RISC_INT);
1623 RD_REG_DWORD(&reg->ictrl);
1624 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1625}
1626
1627static void
e315cd28 1628qla24xx_disable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1629{
1630 unsigned long flags = 0;
1631 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1632
124f85e6
AV		 1633 if (IS_NOPOLLING_TYPE(ha))
1634 return;
fd34f556
AV		 1635 spin_lock_irqsave(&ha->hardware_lock, flags);
1636 ha->interrupts_on = 0;
1637 WRT_REG_DWORD(&reg->ictrl, 0);
1638 RD_REG_DWORD(&reg->ictrl);
1639 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1640}
1641
706f457d
GM		 1642static int
1643qla2x00_iospace_config(struct qla_hw_data *ha)
1644{
1645 resource_size_t pio;
1646 uint16_t msix;
1647 int cpus;
1648
706f457d
GM		 1649 if (pci_request_selected_regions(ha->pdev, ha->bars,
1650 QLA2XXX_DRIVER_NAME)) {
1651 ql_log_pci(ql_log_fatal, ha->pdev, 0x0011,
1652 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
1653 pci_name(ha->pdev));
1654 goto iospace_error_exit;
1655 }
1656 if (!(ha->bars & 1))
1657 goto skip_pio;
1658
1659 /* We only need PIO for Flash operations on ISP2312 v2 chips. */
1660 pio = pci_resource_start(ha->pdev, 0);
1661 if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) {
1662 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
1663 ql_log_pci(ql_log_warn, ha->pdev, 0x0012,
1664 "Invalid pci I/O region size (%s).\n",
1665 pci_name(ha->pdev));
1666 pio = 0;
1667 }
1668 } else {
1669 ql_log_pci(ql_log_warn, ha->pdev, 0x0013,
1670 "Region #0 no a PIO resource (%s).\n",
1671 pci_name(ha->pdev));
1672 pio = 0;
1673 }
1674 ha->pio_address = pio;
1675 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014,
1676 "PIO address=%llu.\n",
1677 (unsigned long long)ha->pio_address);
1678
1679skip_pio:
1680 /* Use MMIO operations for all accesses. */
1681 if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) {
1682 ql_log_pci(ql_log_fatal, ha->pdev, 0x0015,
1683 "Region #1 not an MMIO resource (%s), aborting.\n",
1684 pci_name(ha->pdev));
1685 goto iospace_error_exit;
1686 }
1687 if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) {
1688 ql_log_pci(ql_log_fatal, ha->pdev, 0x0016,
1689 "Invalid PCI mem region size (%s), aborting.\n",
1690 pci_name(ha->pdev));
1691 goto iospace_error_exit;
1692 }
1693
1694 ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN);
1695 if (!ha->iobase) {
1696 ql_log_pci(ql_log_fatal, ha->pdev, 0x0017,
1697 "Cannot remap MMIO (%s), aborting.\n",
1698 pci_name(ha->pdev));
1699 goto iospace_error_exit;
1700 }
1701
1702 /* Determine queue resources */
1703 ha->max_req_queues = ha->max_rsp_queues = 1;
1704 if ((ql2xmaxqueues <= 1 && !ql2xmultique_tag) ||
1705 (ql2xmaxqueues > 1 && ql2xmultique_tag) ||
1706 (!IS_QLA25XX(ha) && !IS_QLA81XX(ha)))
1707 goto mqiobase_exit;
1708
1709 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3),
1710 pci_resource_len(ha->pdev, 3));
1711 if (ha->mqiobase) {
1712 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018,
1713 "MQIO Base=%p.\n", ha->mqiobase);
1714 /* Read MSIX vector size of the board */
1715 pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix);
1716 ha->msix_count = msix;
1717 /* Max queues are bounded by available msix vectors */
1718 /* queue 0 uses two msix vectors */
1719 if (ql2xmultique_tag) {
1720 cpus = num_online_cpus();
1721 ha->max_rsp_queues = (ha->msix_count - 1 > cpus) ?
1722 (cpus + 1) : (ha->msix_count - 1);
1723 ha->max_req_queues = 2;
1724 } else if (ql2xmaxqueues > 1) {
1725 ha->max_req_queues = ql2xmaxqueues > QLA_MQ_SIZE ?
1726 QLA_MQ_SIZE : ql2xmaxqueues;
1727 ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc008,
1728 "QoS mode set, max no of request queues:%d.\n",
1729 ha->max_req_queues);
1730 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0019,
1731 "QoS mode set, max no of request queues:%d.\n",
1732 ha->max_req_queues);
1733 }
1734 ql_log_pci(ql_log_info, ha->pdev, 0x001a,
1735 "MSI-X vector count: %d.\n", msix);
1736 } else
1737 ql_log_pci(ql_log_info, ha->pdev, 0x001b,
1738 "BAR 3 not enabled.\n");
1739
1740mqiobase_exit:
1741 ha->msix_count = ha->max_rsp_queues + 1;
1742 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c,
1743 "MSIX Count:%d.\n", ha->msix_count);
1744 return (0);
1745
1746iospace_error_exit:
1747 return (-ENOMEM);
1748}
1749
1750
6246b8a1
GM		 1751static int
1752qla83xx_iospace_config(struct qla_hw_data *ha)
1753{
1754 uint16_t msix;
1755 int cpus;
1756
1757 if (pci_request_selected_regions(ha->pdev, ha->bars,
1758 QLA2XXX_DRIVER_NAME)) {
1759 ql_log_pci(ql_log_fatal, ha->pdev, 0x0117,
1760 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
1761 pci_name(ha->pdev));
1762
1763 goto iospace_error_exit;
1764 }
1765
1766 /* Use MMIO operations for all accesses. */
1767 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) {
1768 ql_log_pci(ql_log_warn, ha->pdev, 0x0118,
1769 "Invalid pci I/O region size (%s).\n",
1770 pci_name(ha->pdev));
1771 goto iospace_error_exit;
1772 }
1773 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
1774 ql_log_pci(ql_log_warn, ha->pdev, 0x0119,
1775 "Invalid PCI mem region size (%s), aborting\n",
1776 pci_name(ha->pdev));
1777 goto iospace_error_exit;
1778 }
1779
1780 ha->iobase = ioremap(pci_resource_start(ha->pdev, 0), MIN_IOBASE_LEN);
1781 if (!ha->iobase) {
1782 ql_log_pci(ql_log_fatal, ha->pdev, 0x011a,
1783 "Cannot remap MMIO (%s), aborting.\n",
1784 pci_name(ha->pdev));
1785 goto iospace_error_exit;
1786 }
1787
1788 /* 64bit PCI BAR - BAR2 will correspoond to region 4 */
1789 /* 83XX 26XX always use MQ type access for queues
1790 * - mbar 2, a.k.a region 4 */
1791 ha->max_req_queues = ha->max_rsp_queues = 1;
1792 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 4),
1793 pci_resource_len(ha->pdev, 4));
1794
1795 if (!ha->mqiobase) {
1796 ql_log_pci(ql_log_fatal, ha->pdev, 0x011d,
1797 "BAR2/region4 not enabled\n");
1798 goto mqiobase_exit;
1799 }
1800
1801 ha->msixbase = ioremap(pci_resource_start(ha->pdev, 2),
1802 pci_resource_len(ha->pdev, 2));
1803 if (ha->msixbase) {
1804 /* Read MSIX vector size of the board */
1805 pci_read_config_word(ha->pdev,
1806 QLA_83XX_PCI_MSIX_CONTROL, &msix);
1807 ha->msix_count = msix;
1808 /* Max queues are bounded by available msix vectors */
1809 /* queue 0 uses two msix vectors */
1810 if (ql2xmultique_tag) {
1811 cpus = num_online_cpus();
1812 ha->max_rsp_queues = (ha->msix_count - 1 > cpus) ?
1813 (cpus + 1) : (ha->msix_count - 1);
1814 ha->max_req_queues = 2;
1815 } else if (ql2xmaxqueues > 1) {
1816 ha->max_req_queues = ql2xmaxqueues > QLA_MQ_SIZE ?
1817 QLA_MQ_SIZE : ql2xmaxqueues;
1818 ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc00c,
1819 "QoS mode set, max no of request queues:%d.\n",
1820 ha->max_req_queues);
1821 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b,
1822 "QoS mode set, max no of request queues:%d.\n",
1823 ha->max_req_queues);
1824 }
1825 ql_log_pci(ql_log_info, ha->pdev, 0x011c,
1826 "MSI-X vector count: %d.\n", msix);
1827 } else
1828 ql_log_pci(ql_log_info, ha->pdev, 0x011e,
1829 "BAR 1 not enabled.\n");
1830
1831mqiobase_exit:
1832 ha->msix_count = ha->max_rsp_queues + 1;
aa230bc5
AE		 1833
1834 qlt_83xx_iospace_config(ha);
1835
6246b8a1
GM		 1836 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011f,
1837 "MSIX Count:%d.\n", ha->msix_count);
1838 return 0;
1839
1840iospace_error_exit:
1841 return -ENOMEM;
1842}
1843
fd34f556
AV		 1844static struct isp_operations qla2100_isp_ops = {
1845 .pci_config = qla2100_pci_config,
1846 .reset_chip = qla2x00_reset_chip,
1847 .chip_diag = qla2x00_chip_diag,
1848 .config_rings = qla2x00_config_rings,
1849 .reset_adapter = qla2x00_reset_adapter,
1850 .nvram_config = qla2x00_nvram_config,
1851 .update_fw_options = qla2x00_update_fw_options,
1852 .load_risc = qla2x00_load_risc,
1853 .pci_info_str = qla2x00_pci_info_str,
1854 .fw_version_str = qla2x00_fw_version_str,
1855 .intr_handler = qla2100_intr_handler,
1856 .enable_intrs = qla2x00_enable_intrs,
1857 .disable_intrs = qla2x00_disable_intrs,
1858 .abort_command = qla2x00_abort_command,
523ec773
AV		 1859 .target_reset = qla2x00_abort_target,
1860 .lun_reset = qla2x00_lun_reset,
fd34f556
AV		 1861 .fabric_login = qla2x00_login_fabric,
1862 .fabric_logout = qla2x00_fabric_logout,
1863 .calc_req_entries = qla2x00_calc_iocbs_32,
1864 .build_iocbs = qla2x00_build_scsi_iocbs_32,
1865 .prep_ms_iocb = qla2x00_prep_ms_iocb,
1866 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
1867 .read_nvram = qla2x00_read_nvram_data,
1868 .write_nvram = qla2x00_write_nvram_data,
1869 .fw_dump = qla2100_fw_dump,
1870 .beacon_on = NULL,
1871 .beacon_off = NULL,
1872 .beacon_blink = NULL,
1873 .read_optrom = qla2x00_read_optrom_data,
1874 .write_optrom = qla2x00_write_optrom_data,
1875 .get_flash_version = qla2x00_get_flash_version,
e315cd28 1876 .start_scsi = qla2x00_start_scsi,
a9083016 1877 .abort_isp = qla2x00_abort_isp,
706f457d 1878 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 1879 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 1880};
1881
1882static struct isp_operations qla2300_isp_ops = {
1883 .pci_config = qla2300_pci_config,
1884 .reset_chip = qla2x00_reset_chip,
1885 .chip_diag = qla2x00_chip_diag,
1886 .config_rings = qla2x00_config_rings,
1887 .reset_adapter = qla2x00_reset_adapter,
1888 .nvram_config = qla2x00_nvram_config,
1889 .update_fw_options = qla2x00_update_fw_options,
1890 .load_risc = qla2x00_load_risc,
1891 .pci_info_str = qla2x00_pci_info_str,
1892 .fw_version_str = qla2x00_fw_version_str,
1893 .intr_handler = qla2300_intr_handler,
1894 .enable_intrs = qla2x00_enable_intrs,
1895 .disable_intrs = qla2x00_disable_intrs,
1896 .abort_command = qla2x00_abort_command,
523ec773
AV		 1897 .target_reset = qla2x00_abort_target,
1898 .lun_reset = qla2x00_lun_reset,
fd34f556
AV		 1899 .fabric_login = qla2x00_login_fabric,
1900 .fabric_logout = qla2x00_fabric_logout,
1901 .calc_req_entries = qla2x00_calc_iocbs_32,
1902 .build_iocbs = qla2x00_build_scsi_iocbs_32,
1903 .prep_ms_iocb = qla2x00_prep_ms_iocb,
1904 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
1905 .read_nvram = qla2x00_read_nvram_data,
1906 .write_nvram = qla2x00_write_nvram_data,
1907 .fw_dump = qla2300_fw_dump,
1908 .beacon_on = qla2x00_beacon_on,
1909 .beacon_off = qla2x00_beacon_off,
1910 .beacon_blink = qla2x00_beacon_blink,
1911 .read_optrom = qla2x00_read_optrom_data,
1912 .write_optrom = qla2x00_write_optrom_data,
1913 .get_flash_version = qla2x00_get_flash_version,
e315cd28 1914 .start_scsi = qla2x00_start_scsi,
a9083016 1915 .abort_isp = qla2x00_abort_isp,
7ec0effd 1916 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 1917 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 1918};
1919
1920static struct isp_operations qla24xx_isp_ops = {
1921 .pci_config = qla24xx_pci_config,
1922 .reset_chip = qla24xx_reset_chip,
1923 .chip_diag = qla24xx_chip_diag,
1924 .config_rings = qla24xx_config_rings,
1925 .reset_adapter = qla24xx_reset_adapter,
1926 .nvram_config = qla24xx_nvram_config,
1927 .update_fw_options = qla24xx_update_fw_options,
1928 .load_risc = qla24xx_load_risc,
1929 .pci_info_str = qla24xx_pci_info_str,
1930 .fw_version_str = qla24xx_fw_version_str,
1931 .intr_handler = qla24xx_intr_handler,
1932 .enable_intrs = qla24xx_enable_intrs,
1933 .disable_intrs = qla24xx_disable_intrs,
1934 .abort_command = qla24xx_abort_command,
523ec773
AV		 1935 .target_reset = qla24xx_abort_target,
1936 .lun_reset = qla24xx_lun_reset,
fd34f556
AV		 1937 .fabric_login = qla24xx_login_fabric,
1938 .fabric_logout = qla24xx_fabric_logout,
1939 .calc_req_entries = NULL,
1940 .build_iocbs = NULL,
1941 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1942 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1943 .read_nvram = qla24xx_read_nvram_data,
1944 .write_nvram = qla24xx_write_nvram_data,
1945 .fw_dump = qla24xx_fw_dump,
1946 .beacon_on = qla24xx_beacon_on,
1947 .beacon_off = qla24xx_beacon_off,
1948 .beacon_blink = qla24xx_beacon_blink,
1949 .read_optrom = qla24xx_read_optrom_data,
1950 .write_optrom = qla24xx_write_optrom_data,
1951 .get_flash_version = qla24xx_get_flash_version,
e315cd28 1952 .start_scsi = qla24xx_start_scsi,
a9083016 1953 .abort_isp = qla2x00_abort_isp,
7ec0effd 1954 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 1955 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 1956};
1957
c3a2f0df
AV		 1958static struct isp_operations qla25xx_isp_ops = {
1959 .pci_config = qla25xx_pci_config,
1960 .reset_chip = qla24xx_reset_chip,
1961 .chip_diag = qla24xx_chip_diag,
1962 .config_rings = qla24xx_config_rings,
1963 .reset_adapter = qla24xx_reset_adapter,
1964 .nvram_config = qla24xx_nvram_config,
1965 .update_fw_options = qla24xx_update_fw_options,
1966 .load_risc = qla24xx_load_risc,
1967 .pci_info_str = qla24xx_pci_info_str,
1968 .fw_version_str = qla24xx_fw_version_str,
1969 .intr_handler = qla24xx_intr_handler,
1970 .enable_intrs = qla24xx_enable_intrs,
1971 .disable_intrs = qla24xx_disable_intrs,
1972 .abort_command = qla24xx_abort_command,
523ec773
AV		 1973 .target_reset = qla24xx_abort_target,
1974 .lun_reset = qla24xx_lun_reset,
c3a2f0df
AV		 1975 .fabric_login = qla24xx_login_fabric,
1976 .fabric_logout = qla24xx_fabric_logout,
1977 .calc_req_entries = NULL,
1978 .build_iocbs = NULL,
1979 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1980 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1981 .read_nvram = qla25xx_read_nvram_data,
1982 .write_nvram = qla25xx_write_nvram_data,
1983 .fw_dump = qla25xx_fw_dump,
1984 .beacon_on = qla24xx_beacon_on,
1985 .beacon_off = qla24xx_beacon_off,
1986 .beacon_blink = qla24xx_beacon_blink,
338c9161 1987 .read_optrom = qla25xx_read_optrom_data,
c3a2f0df
AV		 1988 .write_optrom = qla24xx_write_optrom_data,
1989 .get_flash_version = qla24xx_get_flash_version,
bad75002 1990 .start_scsi = qla24xx_dif_start_scsi,
a9083016 1991 .abort_isp = qla2x00_abort_isp,
7ec0effd 1992 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 1993 .initialize_adapter = qla2x00_initialize_adapter,
c3a2f0df
AV		 1994};
1995
3a03eb79
AV		 1996static struct isp_operations qla81xx_isp_ops = {
1997 .pci_config = qla25xx_pci_config,
1998 .reset_chip = qla24xx_reset_chip,
1999 .chip_diag = qla24xx_chip_diag,
2000 .config_rings = qla24xx_config_rings,
2001 .reset_adapter = qla24xx_reset_adapter,
2002 .nvram_config = qla81xx_nvram_config,
2003 .update_fw_options = qla81xx_update_fw_options,
eaac30be 2004 .load_risc = qla81xx_load_risc,
3a03eb79
AV		 2005 .pci_info_str = qla24xx_pci_info_str,
2006 .fw_version_str = qla24xx_fw_version_str,
2007 .intr_handler = qla24xx_intr_handler,
2008 .enable_intrs = qla24xx_enable_intrs,
2009 .disable_intrs = qla24xx_disable_intrs,
2010 .abort_command = qla24xx_abort_command,
2011 .target_reset = qla24xx_abort_target,
2012 .lun_reset = qla24xx_lun_reset,
2013 .fabric_login = qla24xx_login_fabric,
2014 .fabric_logout = qla24xx_fabric_logout,
2015 .calc_req_entries = NULL,
2016 .build_iocbs = NULL,
2017 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2018 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
3d79038f
AV		 2019 .read_nvram = NULL,
2020 .write_nvram = NULL,
3a03eb79
AV		 2021 .fw_dump = qla81xx_fw_dump,
2022 .beacon_on = qla24xx_beacon_on,
2023 .beacon_off = qla24xx_beacon_off,
6246b8a1 2024 .beacon_blink = qla83xx_beacon_blink,
3a03eb79
AV		 2025 .read_optrom = qla25xx_read_optrom_data,
2026 .write_optrom = qla24xx_write_optrom_data,
2027 .get_flash_version = qla24xx_get_flash_version,
ba77ef53 2028 .start_scsi = qla24xx_dif_start_scsi,
a9083016 2029 .abort_isp = qla2x00_abort_isp,
7ec0effd 2030 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2031 .initialize_adapter = qla2x00_initialize_adapter,
a9083016
GM		 2032};
2033
2034static struct isp_operations qla82xx_isp_ops = {
2035 .pci_config = qla82xx_pci_config,
2036 .reset_chip = qla82xx_reset_chip,
2037 .chip_diag = qla24xx_chip_diag,
2038 .config_rings = qla82xx_config_rings,
2039 .reset_adapter = qla24xx_reset_adapter,
2040 .nvram_config = qla81xx_nvram_config,
2041 .update_fw_options = qla24xx_update_fw_options,
2042 .load_risc = qla82xx_load_risc,
9d55ca66 2043 .pci_info_str = qla24xx_pci_info_str,
a9083016
GM		 2044 .fw_version_str = qla24xx_fw_version_str,
2045 .intr_handler = qla82xx_intr_handler,
2046 .enable_intrs = qla82xx_enable_intrs,
2047 .disable_intrs = qla82xx_disable_intrs,
2048 .abort_command = qla24xx_abort_command,
2049 .target_reset = qla24xx_abort_target,
2050 .lun_reset = qla24xx_lun_reset,
2051 .fabric_login = qla24xx_login_fabric,
2052 .fabric_logout = qla24xx_fabric_logout,
2053 .calc_req_entries = NULL,
2054 .build_iocbs = NULL,
2055 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2056 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2057 .read_nvram = qla24xx_read_nvram_data,
2058 .write_nvram = qla24xx_write_nvram_data,
2059 .fw_dump = qla24xx_fw_dump,
999916dc
SK		 2060 .beacon_on = qla82xx_beacon_on,
2061 .beacon_off = qla82xx_beacon_off,
2062 .beacon_blink = NULL,
a9083016
GM		 2063 .read_optrom = qla82xx_read_optrom_data,
2064 .write_optrom = qla82xx_write_optrom_data,
7ec0effd 2065 .get_flash_version = qla82xx_get_flash_version,
a9083016
GM		 2066 .start_scsi = qla82xx_start_scsi,
2067 .abort_isp = qla82xx_abort_isp,
706f457d 2068 .iospace_config = qla82xx_iospace_config,
8ae6d9c7 2069 .initialize_adapter = qla2x00_initialize_adapter,
3a03eb79
AV		 2070};
2071
7ec0effd
AD		 2072static struct isp_operations qla8044_isp_ops = {
2073 .pci_config = qla82xx_pci_config,
2074 .reset_chip = qla82xx_reset_chip,
2075 .chip_diag = qla24xx_chip_diag,
2076 .config_rings = qla82xx_config_rings,
2077 .reset_adapter = qla24xx_reset_adapter,
2078 .nvram_config = qla81xx_nvram_config,
2079 .update_fw_options = qla24xx_update_fw_options,
2080 .load_risc = qla82xx_load_risc,
2081 .pci_info_str = qla24xx_pci_info_str,
2082 .fw_version_str = qla24xx_fw_version_str,
2083 .intr_handler = qla8044_intr_handler,
2084 .enable_intrs = qla82xx_enable_intrs,
2085 .disable_intrs = qla82xx_disable_intrs,
2086 .abort_command = qla24xx_abort_command,
2087 .target_reset = qla24xx_abort_target,
2088 .lun_reset = qla24xx_lun_reset,
2089 .fabric_login = qla24xx_login_fabric,
2090 .fabric_logout = qla24xx_fabric_logout,
2091 .calc_req_entries = NULL,
2092 .build_iocbs = NULL,
2093 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2094 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2095 .read_nvram = NULL,
2096 .write_nvram = NULL,
2097 .fw_dump = qla24xx_fw_dump,
2098 .beacon_on = qla82xx_beacon_on,
2099 .beacon_off = qla82xx_beacon_off,
2100 .beacon_blink = NULL,
2101 .read_optrom = qla82xx_read_optrom_data,
2102 .write_optrom = qla8044_write_optrom_data,
2103 .get_flash_version = qla82xx_get_flash_version,
2104 .start_scsi = qla82xx_start_scsi,
2105 .abort_isp = qla8044_abort_isp,
2106 .iospace_config = qla82xx_iospace_config,
2107 .initialize_adapter = qla2x00_initialize_adapter,
2108};
2109
6246b8a1
GM		 2110static struct isp_operations qla83xx_isp_ops = {
2111 .pci_config = qla25xx_pci_config,
2112 .reset_chip = qla24xx_reset_chip,
2113 .chip_diag = qla24xx_chip_diag,
2114 .config_rings = qla24xx_config_rings,
2115 .reset_adapter = qla24xx_reset_adapter,
2116 .nvram_config = qla81xx_nvram_config,
2117 .update_fw_options = qla81xx_update_fw_options,
2118 .load_risc = qla81xx_load_risc,
2119 .pci_info_str = qla24xx_pci_info_str,
2120 .fw_version_str = qla24xx_fw_version_str,
2121 .intr_handler = qla24xx_intr_handler,
2122 .enable_intrs = qla24xx_enable_intrs,
2123 .disable_intrs = qla24xx_disable_intrs,
2124 .abort_command = qla24xx_abort_command,
2125 .target_reset = qla24xx_abort_target,
2126 .lun_reset = qla24xx_lun_reset,
2127 .fabric_login = qla24xx_login_fabric,
2128 .fabric_logout = qla24xx_fabric_logout,
2129 .calc_req_entries = NULL,
2130 .build_iocbs = NULL,
2131 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2132 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2133 .read_nvram = NULL,
2134 .write_nvram = NULL,
2135 .fw_dump = qla83xx_fw_dump,
2136 .beacon_on = qla24xx_beacon_on,
2137 .beacon_off = qla24xx_beacon_off,
2138 .beacon_blink = qla83xx_beacon_blink,
2139 .read_optrom = qla25xx_read_optrom_data,
2140 .write_optrom = qla24xx_write_optrom_data,
2141 .get_flash_version = qla24xx_get_flash_version,
2142 .start_scsi = qla24xx_dif_start_scsi,
2143 .abort_isp = qla2x00_abort_isp,
2144 .iospace_config = qla83xx_iospace_config,
8ae6d9c7
GM		 2145 .initialize_adapter = qla2x00_initialize_adapter,
2146};
2147
2148static struct isp_operations qlafx00_isp_ops = {
2149 .pci_config = qlafx00_pci_config,
2150 .reset_chip = qlafx00_soft_reset,
2151 .chip_diag = qlafx00_chip_diag,
2152 .config_rings = qlafx00_config_rings,
2153 .reset_adapter = qlafx00_soft_reset,
2154 .nvram_config = NULL,
2155 .update_fw_options = NULL,
2156 .load_risc = NULL,
2157 .pci_info_str = qlafx00_pci_info_str,
2158 .fw_version_str = qlafx00_fw_version_str,
2159 .intr_handler = qlafx00_intr_handler,
2160 .enable_intrs = qlafx00_enable_intrs,
2161 .disable_intrs = qlafx00_disable_intrs,
2162 .abort_command = qlafx00_abort_command,
2163 .target_reset = qlafx00_abort_target,
2164 .lun_reset = qlafx00_lun_reset,
2165 .fabric_login = NULL,
2166 .fabric_logout = NULL,
2167 .calc_req_entries = NULL,
2168 .build_iocbs = NULL,
2169 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2170 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2171 .read_nvram = qla24xx_read_nvram_data,
2172 .write_nvram = qla24xx_write_nvram_data,
2173 .fw_dump = NULL,
2174 .beacon_on = qla24xx_beacon_on,
2175 .beacon_off = qla24xx_beacon_off,
2176 .beacon_blink = NULL,
2177 .read_optrom = qla24xx_read_optrom_data,
2178 .write_optrom = qla24xx_write_optrom_data,
2179 .get_flash_version = qla24xx_get_flash_version,
2180 .start_scsi = qlafx00_start_scsi,
2181 .abort_isp = qlafx00_abort_isp,
2182 .iospace_config = qlafx00_iospace_config,
2183 .initialize_adapter = qlafx00_initialize_adapter,
6246b8a1
GM		 2184};
2185
ea5b6382 2186static inline void
e315cd28 2187qla2x00_set_isp_flags(struct qla_hw_data *ha)
ea5b6382 2188{
2189 ha->device_type = DT_EXTENDED_IDS;
2190 switch (ha->pdev->device) {
2191 case PCI_DEVICE_ID_QLOGIC_ISP2100:
2192 ha->device_type |= DT_ISP2100;
2193 ha->device_type &= ~DT_EXTENDED_IDS;
441d1072 2194 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
ea5b6382 2195 break;
2196 case PCI_DEVICE_ID_QLOGIC_ISP2200:
2197 ha->device_type |= DT_ISP2200;
2198 ha->device_type &= ~DT_EXTENDED_IDS;
441d1072 2199 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
ea5b6382 2200 break;
2201 case PCI_DEVICE_ID_QLOGIC_ISP2300:
2202 ha->device_type |= DT_ISP2300;
4a59f71d 2203 ha->device_type |= DT_ZIO_SUPPORTED;
441d1072 2204 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 2205 break;
2206 case PCI_DEVICE_ID_QLOGIC_ISP2312:
2207 ha->device_type |= DT_ISP2312;
4a59f71d 2208 ha->device_type |= DT_ZIO_SUPPORTED;
441d1072 2209 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 2210 break;
2211 case PCI_DEVICE_ID_QLOGIC_ISP2322:
2212 ha->device_type |= DT_ISP2322;
4a59f71d 2213 ha->device_type |= DT_ZIO_SUPPORTED;
ea5b6382 2214 if (ha->pdev->subsystem_vendor == 0x1028 &&
2215 ha->pdev->subsystem_device == 0x0170)
2216 ha->device_type |= DT_OEM_001;
441d1072 2217 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 2218 break;
2219 case PCI_DEVICE_ID_QLOGIC_ISP6312:
2220 ha->device_type |= DT_ISP6312;
441d1072 2221 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 2222 break;
2223 case PCI_DEVICE_ID_QLOGIC_ISP6322:
2224 ha->device_type |= DT_ISP6322;
441d1072 2225 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 2226 break;
2227 case PCI_DEVICE_ID_QLOGIC_ISP2422:
2228 ha->device_type |= DT_ISP2422;
4a59f71d 2229 ha->device_type |= DT_ZIO_SUPPORTED;
e428924c 2230 ha->device_type |= DT_FWI2;
c76f2c01 2231 ha->device_type |= DT_IIDMA;
441d1072 2232 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2233 break;
2234 case PCI_DEVICE_ID_QLOGIC_ISP2432:
2235 ha->device_type |= DT_ISP2432;
4a59f71d 2236 ha->device_type |= DT_ZIO_SUPPORTED;
e428924c 2237 ha->device_type |= DT_FWI2;
c76f2c01 2238 ha->device_type |= DT_IIDMA;
441d1072 2239 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2240 break;
4d4df193
HK		 2241 case PCI_DEVICE_ID_QLOGIC_ISP8432:
2242 ha->device_type |= DT_ISP8432;
2243 ha->device_type |= DT_ZIO_SUPPORTED;
2244 ha->device_type |= DT_FWI2;
2245 ha->device_type |= DT_IIDMA;
2246 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2247 break;
044cc6c8 2248 case PCI_DEVICE_ID_QLOGIC_ISP5422:
2249 ha->device_type |= DT_ISP5422;
e428924c 2250 ha->device_type |= DT_FWI2;
441d1072 2251 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2252 break;
044cc6c8 2253 case PCI_DEVICE_ID_QLOGIC_ISP5432:
2254 ha->device_type |= DT_ISP5432;
e428924c 2255 ha->device_type |= DT_FWI2;
441d1072 2256 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2257 break;
c3a2f0df
AV		 2258 case PCI_DEVICE_ID_QLOGIC_ISP2532:
2259 ha->device_type |= DT_ISP2532;
2260 ha->device_type |= DT_ZIO_SUPPORTED;
2261 ha->device_type |= DT_FWI2;
2262 ha->device_type |= DT_IIDMA;
441d1072 2263 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2264 break;
3a03eb79
AV		 2265 case PCI_DEVICE_ID_QLOGIC_ISP8001:
2266 ha->device_type |= DT_ISP8001;
2267 ha->device_type |= DT_ZIO_SUPPORTED;
2268 ha->device_type |= DT_FWI2;
2269 ha->device_type |= DT_IIDMA;
2270 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2271 break;
a9083016
GM		 2272 case PCI_DEVICE_ID_QLOGIC_ISP8021:
2273 ha->device_type |= DT_ISP8021;
2274 ha->device_type |= DT_ZIO_SUPPORTED;
2275 ha->device_type |= DT_FWI2;
2276 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2277 /* Initialize 82XX ISP flags */
2278 qla82xx_init_flags(ha);
2279 break;
7ec0effd
AD		 2280 case PCI_DEVICE_ID_QLOGIC_ISP8044:
2281 ha->device_type |= DT_ISP8044;
2282 ha->device_type |= DT_ZIO_SUPPORTED;
2283 ha->device_type |= DT_FWI2;
2284 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2285 /* Initialize 82XX ISP flags */
2286 qla82xx_init_flags(ha);
2287 break;
6246b8a1
GM		 2288 case PCI_DEVICE_ID_QLOGIC_ISP2031:
2289 ha->device_type |= DT_ISP2031;
2290 ha->device_type |= DT_ZIO_SUPPORTED;
2291 ha->device_type |= DT_FWI2;
2292 ha->device_type |= DT_IIDMA;
2293 ha->device_type |= DT_T10_PI;
2294 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2295 break;
2296 case PCI_DEVICE_ID_QLOGIC_ISP8031:
2297 ha->device_type |= DT_ISP8031;
2298 ha->device_type |= DT_ZIO_SUPPORTED;
2299 ha->device_type |= DT_FWI2;
2300 ha->device_type |= DT_IIDMA;
2301 ha->device_type |= DT_T10_PI;
2302 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2303 break;
8ae6d9c7
GM		 2304 case PCI_DEVICE_ID_QLOGIC_ISPF001:
2305 ha->device_type |= DT_ISPFX00;
2306 break;
ea5b6382 2307 }
e5b68a61 2308
a9083016
GM		 2309 if (IS_QLA82XX(ha))
2310 ha->port_no = !(ha->portnum & 1);
2311 else
2312 /* Get adapter physical port no from interrupt pin register. */
2313 pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no);
2314
e5b68a61
AC		 2315 if (ha->port_no & 1)
2316 ha->flags.port0 = 1;
2317 else
2318 ha->flags.port0 = 0;
7c3df132 2319 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b,
d8424f68 2320 "device_type=0x%x port=%d fw_srisc_address=0x%x.\n",
7c3df132 2321 ha->device_type, ha->flags.port0, ha->fw_srisc_address);
ea5b6382 2322}
2323
1e99e33a
AV		 2324static void
2325qla2xxx_scan_start(struct Scsi_Host *shost)
2326{
e315cd28 2327 scsi_qla_host_t *vha = shost_priv(shost);
1e99e33a 2328
cbc8eb67
AV		 2329 if (vha->hw->flags.running_gold_fw)
2330 return;
2331
e315cd28
AC		 2332 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
2333 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
2334 set_bit(RSCN_UPDATE, &vha->dpc_flags);
2335 set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags);
1e99e33a
AV		 2336}
2337
2338static int
2339qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time)
2340{
e315cd28 2341 scsi_qla_host_t *vha = shost_priv(shost);
1e99e33a 2342
e315cd28 2343 if (!vha->host)
1e99e33a 2344 return 1;
e315cd28 2345 if (time > vha->hw->loop_reset_delay * HZ)
1e99e33a
AV		 2346 return 1;
2347
e315cd28 2348 return atomic_read(&vha->loop_state) == LOOP_READY;
1e99e33a
AV		 2349}
2350
1da177e4
LT		 2351/*
2352 * PCI driver interface
2353 */
6f039790 2354static int
7ee61397 2355qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
1da177e4 2356{
a1541d5a 2357 int ret = -ENODEV;
1da177e4 2358 struct Scsi_Host *host;
e315cd28
AC		 2359 scsi_qla_host_t *base_vha = NULL;
2360 struct qla_hw_data *ha;
29856e28 2361 char pci_info[30];
7d613ac6 2362 char fw_str[30], wq_name[30];
5433383e 2363 struct scsi_host_template *sht;
642ef983 2364 int bars, mem_only = 0;
e315cd28 2365 uint16_t req_length = 0, rsp_length = 0;
73208dfd
AC		 2366 struct req_que *req = NULL;
2367 struct rsp_que *rsp = NULL;
285d0321 2368 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO);
a5326f86 2369 sht = &qla2xxx_driver_template;
5433383e 2370 if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 ||
8bc69e7d 2371 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 ||
4d4df193 2372 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 ||
8bc69e7d 2373 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 ||
c3a2f0df 2374 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 ||
3a03eb79 2375 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 ||
a9083016 2376 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 ||
6246b8a1
GM		 2377 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021 ||
2378 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2031 ||
8ae6d9c7 2379 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8031 ||
7ec0effd
AD		 2380 pdev->device == PCI_DEVICE_ID_QLOGIC_ISPF001 ||
2381 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8044) {
285d0321 2382 bars = pci_select_bars(pdev, IORESOURCE_MEM);
09483916 2383 mem_only = 1;
7c3df132
SK		 2384 ql_dbg_pci(ql_dbg_init, pdev, 0x0007,
2385 "Mem only adapter.\n");
285d0321 2386 }
7c3df132
SK		 2387 ql_dbg_pci(ql_dbg_init, pdev, 0x0008,
2388 "Bars=%d.\n", bars);
285d0321 2389
09483916
BH		 2390 if (mem_only) {
2391 if (pci_enable_device_mem(pdev))
2392 goto probe_out;
2393 } else {
2394 if (pci_enable_device(pdev))
2395 goto probe_out;
2396 }
285d0321 2397
0927678f
JB		 2398 /* This may fail but that's ok */
2399 pci_enable_pcie_error_reporting(pdev);
285d0321 2400
e315cd28
AC		 2401 ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL);
2402 if (!ha) {
7c3df132
SK		 2403 ql_log_pci(ql_log_fatal, pdev, 0x0009,
2404 "Unable to allocate memory for ha.\n");
e315cd28 2405 goto probe_out;
1da177e4 2406 }
7c3df132
SK		 2407 ql_dbg_pci(ql_dbg_init, pdev, 0x000a,
2408 "Memory allocated for ha=%p.\n", ha);
e315cd28 2409 ha->pdev = pdev;
2d70c103 2410 ha->tgt.enable_class_2 = ql2xenableclass2;
1da177e4
LT		 2411
2412 /* Clear our data area */
285d0321 2413 ha->bars = bars;
09483916 2414 ha->mem_only = mem_only;
df4bf0bb 2415 spin_lock_init(&ha->hardware_lock);
339aa70e 2416 spin_lock_init(&ha->vport_slock);
a9b6f722 2417 mutex_init(&ha->selflogin_lock);
1da177e4 2418
ea5b6382 2419 /* Set ISP-type information. */
2420 qla2x00_set_isp_flags(ha);
ca79cf66
DG		 2421
2422 /* Set EEH reset type to fundamental if required by hba */
95676112
JC		 2423 if (IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha) ||
2424 IS_QLA83XX(ha))
ca79cf66 2425 pdev->needs_freset = 1;
ca79cf66 2426
cba1e47f
CD		 2427 ha->prev_topology = 0;
2428 ha->init_cb_size = sizeof(init_cb_t);
2429 ha->link_data_rate = PORT_SPEED_UNKNOWN;
2430 ha->optrom_size = OPTROM_SIZE_2300;
3c290d0b 2431 ha->cfg_lun_q_depth = ql2xmaxqdepth;
cba1e47f 2432
abbd8870 2433 /* Assign ISP specific operations. */
1da177e4 2434 if (IS_QLA2100(ha)) {
642ef983 2435 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
1da177e4 2436 ha->mbx_count = MAILBOX_REGISTER_COUNT_2100;
e315cd28
AC		 2437 req_length = REQUEST_ENTRY_CNT_2100;
2438 rsp_length = RESPONSE_ENTRY_CNT_2100;
2439 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
abbd8870 2440 ha->gid_list_info_size = 4;
3a03eb79
AV		 2441 ha->flash_conf_off = ~0;
2442 ha->flash_data_off = ~0;
2443 ha->nvram_conf_off = ~0;
2444 ha->nvram_data_off = ~0;
fd34f556 2445 ha->isp_ops = &qla2100_isp_ops;
1da177e4 2446 } else if (IS_QLA2200(ha)) {
642ef983 2447 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
67ddda35 2448 ha->mbx_count = MAILBOX_REGISTER_COUNT_2200;
e315cd28
AC		 2449 req_length = REQUEST_ENTRY_CNT_2200;
2450 rsp_length = RESPONSE_ENTRY_CNT_2100;
2451 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
abbd8870 2452 ha->gid_list_info_size = 4;
3a03eb79
AV		 2453 ha->flash_conf_off = ~0;
2454 ha->flash_data_off = ~0;
2455 ha->nvram_conf_off = ~0;
2456 ha->nvram_data_off = ~0;
fd34f556 2457 ha->isp_ops = &qla2100_isp_ops;
fca29703 2458 } else if (IS_QLA23XX(ha)) {
642ef983 2459 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
1da177e4 2460 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2461 req_length = REQUEST_ENTRY_CNT_2200;
2462 rsp_length = RESPONSE_ENTRY_CNT_2300;
2463 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
abbd8870 2464 ha->gid_list_info_size = 6;
854165f4 2465 if (IS_QLA2322(ha) || IS_QLA6322(ha))
2466 ha->optrom_size = OPTROM_SIZE_2322;
3a03eb79
AV		 2467 ha->flash_conf_off = ~0;
2468 ha->flash_data_off = ~0;
2469 ha->nvram_conf_off = ~0;
2470 ha->nvram_data_off = ~0;
fd34f556 2471 ha->isp_ops = &qla2300_isp_ops;
4d4df193 2472 } else if (IS_QLA24XX_TYPE(ha)) {
642ef983 2473 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
fca29703 2474 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2475 req_length = REQUEST_ENTRY_CNT_24XX;
2476 rsp_length = RESPONSE_ENTRY_CNT_2300;
2d70c103 2477 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
e315cd28 2478 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2c3dfe3f 2479 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
fca29703 2480 ha->gid_list_info_size = 8;
854165f4 2481 ha->optrom_size = OPTROM_SIZE_24XX;
73208dfd 2482 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX;
fd34f556 2483 ha->isp_ops = &qla24xx_isp_ops;
3a03eb79
AV		 2484 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2485 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2486 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2487 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
c3a2f0df 2488 } else if (IS_QLA25XX(ha)) {
642ef983 2489 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
c3a2f0df 2490 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2491 req_length = REQUEST_ENTRY_CNT_24XX;
2492 rsp_length = RESPONSE_ENTRY_CNT_2300;
2d70c103 2493 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
e315cd28 2494 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
c3a2f0df 2495 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
c3a2f0df
AV		 2496 ha->gid_list_info_size = 8;
2497 ha->optrom_size = OPTROM_SIZE_25XX;
73208dfd 2498 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
c3a2f0df 2499 ha->isp_ops = &qla25xx_isp_ops;
3a03eb79
AV		 2500 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2501 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2502 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2503 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
2504 } else if (IS_QLA81XX(ha)) {
642ef983 2505 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3a03eb79
AV		 2506 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2507 req_length = REQUEST_ENTRY_CNT_24XX;
2508 rsp_length = RESPONSE_ENTRY_CNT_2300;
aa230bc5 2509 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
3a03eb79
AV		 2510 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2511 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2512 ha->gid_list_info_size = 8;
2513 ha->optrom_size = OPTROM_SIZE_81XX;
40859ae5 2514 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3a03eb79
AV		 2515 ha->isp_ops = &qla81xx_isp_ops;
2516 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2517 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2518 ha->nvram_conf_off = ~0;
2519 ha->nvram_data_off = ~0;
a9083016 2520 } else if (IS_QLA82XX(ha)) {
642ef983 2521 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
a9083016
GM		 2522 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2523 req_length = REQUEST_ENTRY_CNT_82XX;
2524 rsp_length = RESPONSE_ENTRY_CNT_82XX;
2525 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2526 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2527 ha->gid_list_info_size = 8;
2528 ha->optrom_size = OPTROM_SIZE_82XX;
087c621e 2529 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
a9083016
GM		 2530 ha->isp_ops = &qla82xx_isp_ops;
2531 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2532 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2533 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2534 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
7ec0effd
AD		 2535 } else if (IS_QLA8044(ha)) {
2536 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2537 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2538 req_length = REQUEST_ENTRY_CNT_82XX;
2539 rsp_length = RESPONSE_ENTRY_CNT_82XX;
2540 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2541 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2542 ha->gid_list_info_size = 8;
2543 ha->optrom_size = OPTROM_SIZE_83XX;
2544 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2545 ha->isp_ops = &qla8044_isp_ops;
2546 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2547 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2548 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2549 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
6246b8a1 2550 } else if (IS_QLA83XX(ha)) {
7d613ac6 2551 ha->portnum = PCI_FUNC(ha->pdev->devfn);
642ef983 2552 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
6246b8a1
GM		 2553 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2554 req_length = REQUEST_ENTRY_CNT_24XX;
2555 rsp_length = RESPONSE_ENTRY_CNT_2300;
b8aa4bdf 2556 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
6246b8a1
GM		 2557 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2558 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2559 ha->gid_list_info_size = 8;
2560 ha->optrom_size = OPTROM_SIZE_83XX;
2561 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2562 ha->isp_ops = &qla83xx_isp_ops;
2563 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2564 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2565 ha->nvram_conf_off = ~0;
2566 ha->nvram_data_off = ~0;
8ae6d9c7
GM		 2567 } else if (IS_QLAFX00(ha)) {
2568 ha->max_fibre_devices = MAX_FIBRE_DEVICES_FX00;
2569 ha->mbx_count = MAILBOX_REGISTER_COUNT_FX00;
2570 ha->aen_mbx_count = AEN_MAILBOX_REGISTER_COUNT_FX00;
2571 req_length = REQUEST_ENTRY_CNT_FX00;
2572 rsp_length = RESPONSE_ENTRY_CNT_FX00;
2573 ha->init_cb_size = sizeof(struct init_cb_fx);
2574 ha->isp_ops = &qlafx00_isp_ops;
2575 ha->port_down_retry_count = 30; /* default value */
2576 ha->mr.fw_hbt_cnt = QLAFX00_HEARTBEAT_INTERVAL;
2577 ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL;
71e56003 2578 ha->mr.fw_critemp_timer_tick = QLAFX00_CRITEMP_INTERVAL;
8ae6d9c7 2579 ha->mr.fw_hbt_en = 1;
1da177e4 2580 }
6246b8a1 2581
7c3df132
SK		 2582 ql_dbg_pci(ql_dbg_init, pdev, 0x001e,
2583 "mbx_count=%d, req_length=%d, "
2584 "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, "
642ef983
CD		 2585 "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, "
2586 "max_fibre_devices=%d.\n",
7c3df132
SK		 2587 ha->mbx_count, req_length, rsp_length, ha->max_loop_id,
2588 ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size,
642ef983 2589 ha->nvram_npiv_size, ha->max_fibre_devices);
7c3df132
SK		 2590 ql_dbg_pci(ql_dbg_init, pdev, 0x001f,
2591 "isp_ops=%p, flash_conf_off=%d, "
2592 "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n",
2593 ha->isp_ops, ha->flash_conf_off, ha->flash_data_off,
2594 ha->nvram_conf_off, ha->nvram_data_off);
706f457d
GM		 2595
2596 /* Configure PCI I/O space */
2597 ret = ha->isp_ops->iospace_config(ha);
2598 if (ret)
0a63ad12 2599 goto iospace_config_failed;
706f457d
GM		 2600
2601 ql_log_pci(ql_log_info, pdev, 0x001d,
2602 "Found an ISP%04X irq %d iobase 0x%p.\n",
2603 pdev->device, pdev->irq, ha->iobase);
6c2f527c 2604 mutex_init(&ha->vport_lock);
0b05a1f0
MB		 2605 init_completion(&ha->mbx_cmd_comp);
2606 complete(&ha->mbx_cmd_comp);
2607 init_completion(&ha->mbx_intr_comp);
23f2ebd1 2608 init_completion(&ha->dcbx_comp);
f356bef1 2609 init_completion(&ha->lb_portup_comp);
1da177e4 2610
2c3dfe3f 2611 set_bit(0, (unsigned long *) ha->vp_idx_map);
1da177e4 2612
53303c42 2613 qla2x00_config_dma_addressing(ha);
7c3df132
SK		 2614 ql_dbg_pci(ql_dbg_init, pdev, 0x0020,
2615 "64 Bit addressing is %s.\n",
2616 ha->flags.enable_64bit_addressing ? "enable" :
2617 "disable");
73208dfd 2618 ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp);
e315cd28 2619 if (!ret) {
7c3df132
SK		 2620 ql_log_pci(ql_log_fatal, pdev, 0x0031,
2621 "Failed to allocate memory for adapter, aborting.\n");
1da177e4 2622
e315cd28
AC		 2623 goto probe_hw_failed;
2624 }
2625
73208dfd 2626 req->max_q_depth = MAX_Q_DEPTH;
e315cd28 2627 if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU)
73208dfd
AC		 2628 req->max_q_depth = ql2xmaxqdepth;
2629
e315cd28
AC		 2630
2631 base_vha = qla2x00_create_host(sht, ha);
2632 if (!base_vha) {
a1541d5a 2633 ret = -ENOMEM;
6e9f21f3 2634 qla2x00_mem_free(ha);
2afa19a9
AC		 2635 qla2x00_free_req_que(ha, req);
2636 qla2x00_free_rsp_que(ha, rsp);
e315cd28 2637 goto probe_hw_failed;
1da177e4
LT		 2638 }
2639
e315cd28
AC		 2640 pci_set_drvdata(pdev, base_vha);
2641
e315cd28 2642 host = base_vha->host;
2afa19a9 2643 base_vha->req = req;
8ae6d9c7
GM		 2644 if (IS_QLAFX00(ha))
2645 host->can_queue = 1024;
2646 else
2647 host->can_queue = req->length + 128;
73208dfd 2648 if (IS_QLA2XXX_MIDTYPE(ha))
e315cd28 2649 base_vha->mgmt_svr_loop_id = 10 + base_vha->vp_idx;
73208dfd 2650 else
e315cd28
AC		 2651 base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER +
2652 base_vha->vp_idx;
58548cb5 2653
8ae6d9c7
GM		 2654 /* Setup fcport template structure. */
2655 ha->mr.fcport.vha = base_vha;
2656 ha->mr.fcport.port_type = FCT_UNKNOWN;
2657 ha->mr.fcport.loop_id = FC_NO_LOOP_ID;
2658 qla2x00_set_fcport_state(&ha->mr.fcport, FCS_UNCONFIGURED);
2659 ha->mr.fcport.supported_classes = FC_COS_UNSPECIFIED;
2660 ha->mr.fcport.scan_state = 1;
2661
58548cb5
GM		 2662 /* Set the SG table size based on ISP type */
2663 if (!IS_FWI2_CAPABLE(ha)) {
2664 if (IS_QLA2100(ha))
2665 host->sg_tablesize = 32;
2666 } else {
2667 if (!IS_QLA82XX(ha))
2668 host->sg_tablesize = QLA_SG_ALL;
2669 }
7c3df132
SK		 2670 ql_dbg(ql_dbg_init, base_vha, 0x0032,
2671 "can_queue=%d, req=%p, "
2672 "mgmt_svr_loop_id=%d, sg_tablesize=%d.\n",
2673 host->can_queue, base_vha->req,
2674 base_vha->mgmt_svr_loop_id, host->sg_tablesize);
642ef983 2675 host->max_id = ha->max_fibre_devices;
e315cd28
AC		 2676 host->cmd_per_lun = 3;
2677 host->unique_id = host->host_no;
e02587d7 2678 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif)
0c470874
AE		 2679 host->max_cmd_len = 32;
2680 else
2681 host->max_cmd_len = MAX_CMDSZ;
e315cd28 2682 host->max_channel = MAX_BUSES - 1;
82515920 2683 host->max_lun = ql2xmaxlun;
e315cd28 2684 host->transportt = qla2xxx_transport_template;
9a069e19 2685 sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC);
e315cd28 2686
7c3df132
SK		 2687 ql_dbg(ql_dbg_init, base_vha, 0x0033,
2688 "max_id=%d this_id=%d "
2689 "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d "
d8424f68 2690 "max_lun=%d transportt=%p, vendor_id=%llu.\n", host->max_id,
7c3df132
SK		 2691 host->this_id, host->cmd_per_lun, host->unique_id,
2692 host->max_cmd_len, host->max_channel, host->max_lun,
2693 host->transportt, sht->vendor_id);
2694
9a347ff4
CD		 2695que_init:
2696 /* Alloc arrays of request and response ring ptrs */
2697 if (!qla2x00_alloc_queues(ha, req, rsp)) {
2698 ql_log(ql_log_fatal, base_vha, 0x003d,
2699 "Failed to allocate memory for queue pointers..."
2700 "aborting.\n");
2701 goto probe_init_failed;
2702 }
2703
2d70c103 2704 qlt_probe_one_stage1(base_vha, ha);
9a347ff4 2705
73208dfd
AC		 2706 /* Set up the irqs */
2707 ret = qla2x00_request_irqs(ha, rsp);
2708 if (ret)
6e9f21f3 2709 goto probe_init_failed;
90a86fc0
JC		 2710
2711 pci_save_state(pdev);
2712
9a347ff4 2713 /* Assign back pointers */
2afa19a9
AC		 2714 rsp->req = req;
2715 req->rsp = rsp;
9a347ff4 2716
8ae6d9c7
GM		 2717 if (IS_QLAFX00(ha)) {
2718 ha->rsp_q_map[0] = rsp;
2719 ha->req_q_map[0] = req;
2720 set_bit(0, ha->req_qid_map);
2721 set_bit(0, ha->rsp_qid_map);
2722 }
2723
08029990
AV		 2724 /* FWI2-capable only. */
2725 req->req_q_in = &ha->iobase->isp24.req_q_in;
2726 req->req_q_out = &ha->iobase->isp24.req_q_out;
2727 rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in;
2728 rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out;
6246b8a1 2729 if (ha->mqenable || IS_QLA83XX(ha)) {
08029990
AV		 2730 req->req_q_in = &ha->mqiobase->isp25mq.req_q_in;
2731 req->req_q_out = &ha->mqiobase->isp25mq.req_q_out;
2732 rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in;
2733 rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out;
17d98630
AC		 2734 }
2735
8ae6d9c7
GM		 2736 if (IS_QLAFX00(ha)) {
2737 req->req_q_in = &ha->iobase->ispfx00.req_q_in;
2738 req->req_q_out = &ha->iobase->ispfx00.req_q_out;
2739 rsp->rsp_q_in = &ha->iobase->ispfx00.rsp_q_in;
2740 rsp->rsp_q_out = &ha->iobase->ispfx00.rsp_q_out;
2741 }
2742
7ec0effd 2743 if (IS_P3P_TYPE(ha)) {
a9083016
GM		 2744 req->req_q_out = &ha->iobase->isp82.req_q_out[0];
2745 rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0];
2746 rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0];
2747 }
2748
7c3df132
SK		 2749 ql_dbg(ql_dbg_multiq, base_vha, 0xc009,
2750 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
2751 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
2752 ql_dbg(ql_dbg_multiq, base_vha, 0xc00a,
2753 "req->req_q_in=%p req->req_q_out=%p "
2754 "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
2755 req->req_q_in, req->req_q_out,
2756 rsp->rsp_q_in, rsp->rsp_q_out);
2757 ql_dbg(ql_dbg_init, base_vha, 0x003e,
2758 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
2759 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
2760 ql_dbg(ql_dbg_init, base_vha, 0x003f,
2761 "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
2762 req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out);
1da177e4 2763
8ae6d9c7 2764 if (ha->isp_ops->initialize_adapter(base_vha)) {
7c3df132
SK		 2765 ql_log(ql_log_fatal, base_vha, 0x00d6,
2766 "Failed to initialize adapter - Adapter flags %x.\n",
2767 base_vha->device_flags);
1da177e4 2768
a9083016
GM		 2769 if (IS_QLA82XX(ha)) {
2770 qla82xx_idc_lock(ha);
2771 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 2772 QLA8XXX_DEV_FAILED);
a9083016 2773 qla82xx_idc_unlock(ha);
7c3df132
SK		 2774 ql_log(ql_log_fatal, base_vha, 0x00d7,
2775 "HW State: FAILED.\n");
7ec0effd
AD		 2776 } else if (IS_QLA8044(ha)) {
2777 qla8044_idc_lock(ha);
2778 qla8044_wr_direct(base_vha,
2779 QLA8044_CRB_DEV_STATE_INDEX,
2780 QLA8XXX_DEV_FAILED);
2781 qla8044_idc_unlock(ha);
2782 ql_log(ql_log_fatal, base_vha, 0x0150,
2783 "HW State: FAILED.\n");
a9083016
GM		 2784 }
2785
a1541d5a 2786 ret = -ENODEV;
1da177e4
LT		 2787 goto probe_failed;
2788 }
2789
7163ea81
AC		 2790 if (ha->mqenable) {
2791 if (qla25xx_setup_mode(base_vha)) {
7c3df132
SK		 2792 ql_log(ql_log_warn, base_vha, 0x00ec,
2793 "Failed to create queues, falling back to single queue mode.\n");
7163ea81
AC		 2794 goto que_init;
2795 }
2796 }
68ca949c 2797
cbc8eb67
AV		 2798 if (ha->flags.running_gold_fw)
2799 goto skip_dpc;
2800
1da177e4
LT		 2801 /*
2802 * Startup the kernel thread for this host adapter
2803 */
39a11240 2804 ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha,
7c3df132 2805 "%s_dpc", base_vha->host_str);
39a11240 2806 if (IS_ERR(ha->dpc_thread)) {
7c3df132
SK		 2807 ql_log(ql_log_fatal, base_vha, 0x00ed,
2808 "Failed to start DPC thread.\n");
39a11240 2809 ret = PTR_ERR(ha->dpc_thread);
1da177e4
LT		 2810 goto probe_failed;
2811 }
7c3df132
SK		 2812 ql_dbg(ql_dbg_init, base_vha, 0x00ee,
2813 "DPC thread started successfully.\n");
1da177e4 2814
2d70c103
NB		 2815 /*
2816 * If we're not coming up in initiator mode, we might sit for
2817 * a while without waking up the dpc thread, which leads to a
2818 * stuck process warning. So just kick the dpc once here and
2819 * let the kthread start (and go back to sleep in qla2x00_do_dpc).
2820 */
2821 qla2xxx_wake_dpc(base_vha);
2822
81178772
SK		 2823 if (IS_QLA8031(ha) || IS_MCTP_CAPABLE(ha)) {
2824 sprintf(wq_name, "qla2xxx_%lu_dpc_lp_wq", base_vha->host_no);
2825 ha->dpc_lp_wq = create_singlethread_workqueue(wq_name);
2826 INIT_WORK(&ha->idc_aen, qla83xx_service_idc_aen);
2827
2828 sprintf(wq_name, "qla2xxx_%lu_dpc_hp_wq", base_vha->host_no);
2829 ha->dpc_hp_wq = create_singlethread_workqueue(wq_name);
2830 INIT_WORK(&ha->nic_core_reset, qla83xx_nic_core_reset_work);
2831 INIT_WORK(&ha->idc_state_handler,
2832 qla83xx_idc_state_handler_work);
2833 INIT_WORK(&ha->nic_core_unrecoverable,
2834 qla83xx_nic_core_unrecoverable_work);
2835 }
2836
cbc8eb67 2837skip_dpc:
e315cd28
AC		 2838 list_add_tail(&base_vha->list, &ha->vp_list);
2839 base_vha->host->irq = ha->pdev->irq;
1da177e4
LT		 2840
2841 /* Initialized the timer */
e315cd28 2842 qla2x00_start_timer(base_vha, qla2x00_timer, WATCH_INTERVAL);
7c3df132
SK		 2843 ql_dbg(ql_dbg_init, base_vha, 0x00ef,
2844 "Started qla2x00_timer with "
2845 "interval=%d.\n", WATCH_INTERVAL);
2846 ql_dbg(ql_dbg_init, base_vha, 0x00f0,
2847 "Detected hba at address=%p.\n",
2848 ha);
d19044c3 2849
e02587d7 2850 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) {
bad75002 2851 if (ha->fw_attributes & BIT_4) {
9e522cd8 2852 int prot = 0, guard;
bad75002 2853 base_vha->flags.difdix_supported = 1;
7c3df132
SK		 2854 ql_dbg(ql_dbg_init, base_vha, 0x00f1,
2855 "Registering for DIF/DIX type 1 and 3 protection.\n");
8cb2049c
AE		 2856 if (ql2xenabledif == 1)
2857 prot = SHOST_DIX_TYPE0_PROTECTION;
bad75002 2858 scsi_host_set_prot(host,
8cb2049c 2859 prot | SHOST_DIF_TYPE1_PROTECTION
0c470874 2860 | SHOST_DIF_TYPE2_PROTECTION
bad75002
AE		 2861 | SHOST_DIF_TYPE3_PROTECTION
2862 | SHOST_DIX_TYPE1_PROTECTION
0c470874 2863 | SHOST_DIX_TYPE2_PROTECTION
bad75002 2864 | SHOST_DIX_TYPE3_PROTECTION);
9e522cd8
AE		 2865
2866 guard = SHOST_DIX_GUARD_CRC;
2867
2868 if (IS_PI_IPGUARD_CAPABLE(ha) &&
2869 (ql2xenabledif > 1 || IS_PI_DIFB_DIX0_CAPABLE(ha)))
2870 guard |= SHOST_DIX_GUARD_IP;
2871
2872 scsi_host_set_guard(host, guard);
bad75002
AE		 2873 } else
2874 base_vha->flags.difdix_supported = 0;
2875 }
2876
a9083016
GM		 2877 ha->isp_ops->enable_intrs(ha);
2878
1fe19ee4
AB		 2879 if (IS_QLAFX00(ha)) {
2880 ret = qlafx00_fx_disc(base_vha,
2881 &base_vha->hw->mr.fcport, FXDISC_GET_CONFIG_INFO);
2882 host->sg_tablesize = (ha->mr.extended_io_enabled) ?
2883 QLA_SG_ALL : 128;
2884 }
2885
a1541d5a
AV		 2886 ret = scsi_add_host(host, &pdev->dev);
2887 if (ret)
2888 goto probe_failed;
2889
1486400f
MR		 2890 base_vha->flags.init_done = 1;
2891 base_vha->flags.online = 1;
2892
7c3df132
SK		 2893 ql_dbg(ql_dbg_init, base_vha, 0x00f2,
2894 "Init done and hba is online.\n");
2895
2d70c103
NB		 2896 if (qla_ini_mode_enabled(base_vha))
2897 scsi_scan_host(host);
2898 else
2899 ql_dbg(ql_dbg_init, base_vha, 0x0122,
2900 "skipping scsi_scan_host() for non-initiator port\n");
1e99e33a 2901
e315cd28 2902 qla2x00_alloc_sysfs_attr(base_vha);
a1541d5a 2903
8ae6d9c7 2904 if (IS_QLAFX00(ha)) {
8ae6d9c7
GM		 2905 ret = qlafx00_fx_disc(base_vha,
2906 &base_vha->hw->mr.fcport, FXDISC_GET_PORT_INFO);
2907
2908 /* Register system information */
2909 ret = qlafx00_fx_disc(base_vha,
2910 &base_vha->hw->mr.fcport, FXDISC_REG_HOST_INFO);
2911 }
2912
e315cd28 2913 qla2x00_init_host_attr(base_vha);
a1541d5a 2914
e315cd28 2915 qla2x00_dfs_setup(base_vha);
df613b96 2916
7c3df132 2917 ql_log(ql_log_info, base_vha, 0x00fb,
c5dcfaac 2918 "QLogic %s - %s.\n", ha->model_number, ha->model_desc);
7c3df132
SK		 2919 ql_log(ql_log_info, base_vha, 0x00fc,
2920 "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n",
2921 pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info),
2922 pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-',
2923 base_vha->host_no,
e315cd28 2924 ha->isp_ops->fw_version_str(base_vha, fw_str));
1da177e4 2925
2d70c103
NB		 2926 qlt_add_target(ha, base_vha);
2927
1da177e4
LT		 2928 return 0;
2929
6e9f21f3 2930probe_init_failed:
2afa19a9 2931 qla2x00_free_req_que(ha, req);
9a347ff4
CD		 2932 ha->req_q_map[0] = NULL;
2933 clear_bit(0, ha->req_qid_map);
2afa19a9 2934 qla2x00_free_rsp_que(ha, rsp);
9a347ff4
CD		 2935 ha->rsp_q_map[0] = NULL;
2936 clear_bit(0, ha->rsp_qid_map);
2afa19a9 2937 ha->max_req_queues = ha->max_rsp_queues = 0;
6e9f21f3 2938
1da177e4 2939probe_failed:
b9978769
AV		 2940 if (base_vha->timer_active)
2941 qla2x00_stop_timer(base_vha);
2942 base_vha->flags.online = 0;
2943 if (ha->dpc_thread) {
2944 struct task_struct *t = ha->dpc_thread;
2945
2946 ha->dpc_thread = NULL;
2947 kthread_stop(t);
2948 }
2949
e315cd28 2950 qla2x00_free_device(base_vha);
1da177e4 2951
e315cd28 2952 scsi_host_put(base_vha->host);
1da177e4 2953
e315cd28 2954probe_hw_failed:
a9083016
GM		 2955 if (IS_QLA82XX(ha)) {
2956 qla82xx_idc_lock(ha);
2957 qla82xx_clear_drv_active(ha);
2958 qla82xx_idc_unlock(ha);
0a63ad12 2959 }
7ec0effd
AD		 2960 if (IS_QLA8044(ha)) {
2961 qla8044_idc_lock(ha);
2962 qla8044_clear_drv_active(base_vha);
2963 qla8044_idc_unlock(ha);
2964 }
0a63ad12 2965iospace_config_failed:
7ec0effd 2966 if (IS_P3P_TYPE(ha)) {
0a63ad12
SK		 2967 if (!ha->nx_pcibase)
2968 iounmap((device_reg_t __iomem *)ha->nx_pcibase);
a9083016
GM		 2969 if (!ql2xdbwr)
2970 iounmap((device_reg_t __iomem *)ha->nxdb_wr_ptr);
2971 } else {
2972 if (ha->iobase)
2973 iounmap(ha->iobase);
8ae6d9c7
GM		 2974 if (ha->cregbase)
2975 iounmap(ha->cregbase);
a9083016 2976 }
e315cd28
AC		 2977 pci_release_selected_regions(ha->pdev, ha->bars);
2978 kfree(ha);
2979 ha = NULL;
1da177e4 2980
a1541d5a 2981probe_out:
e315cd28 2982 pci_disable_device(pdev);
a1541d5a 2983 return ret;
1da177e4 2984}
1da177e4 2985
2d70c103
NB		 2986static void
2987qla2x00_stop_dpc_thread(scsi_qla_host_t *vha)
2988{
2989 struct qla_hw_data *ha = vha->hw;
2990 struct task_struct *t = ha->dpc_thread;
2991
2992 if (ha->dpc_thread == NULL)
2993 return;
2994 /*
2995 * qla2xxx_wake_dpc checks for ->dpc_thread
2996 * so we need to zero it out.
2997 */
2998 ha->dpc_thread = NULL;
2999 kthread_stop(t);
3000}
3001
e30d1756
MI		 3002static void
3003qla2x00_shutdown(struct pci_dev *pdev)
3004{
3005 scsi_qla_host_t *vha;
3006 struct qla_hw_data *ha;
3007
552f3f9a
MI		 3008 if (!atomic_read(&pdev->enable_cnt))
3009 return;
3010
e30d1756
MI		 3011 vha = pci_get_drvdata(pdev);
3012 ha = vha->hw;
3013
42479343
AB		 3014 /* Notify ISPFX00 firmware */
3015 if (IS_QLAFX00(ha))
3016 qlafx00_driver_shutdown(vha, 20);
3017
e30d1756
MI		 3018 /* Turn-off FCE trace */
3019 if (ha->flags.fce_enabled) {
3020 qla2x00_disable_fce_trace(vha, NULL, NULL);
3021 ha->flags.fce_enabled = 0;
3022 }
3023
3024 /* Turn-off EFT trace */
3025 if (ha->eft)
3026 qla2x00_disable_eft_trace(vha);
3027
3028 /* Stop currently executing firmware. */
3029 qla2x00_try_to_stop_firmware(vha);
3030
3031 /* Turn adapter off line */
3032 vha->flags.online = 0;
3033
3034 /* turn-off interrupts on the card */
3035 if (ha->interrupts_on) {
3036 vha->flags.init_done = 0;
3037 ha->isp_ops->disable_intrs(ha);
3038 }
3039
3040 qla2x00_free_irqs(vha);
3041
3042 qla2x00_free_fw_dump(ha);
3043}
3044
4c993f76 3045static void
7ee61397 3046qla2x00_remove_one(struct pci_dev *pdev)
1da177e4 3047{
feafb7b1 3048 scsi_qla_host_t *base_vha, *vha;
e315cd28 3049 struct qla_hw_data *ha;
feafb7b1 3050 unsigned long flags;
e315cd28 3051
9a347ff4
CD		 3052 /*
3053 * If the PCI device is disabled that means that probe failed and any
3054 * resources should be have cleaned up on probe exit.
3055 */
3056 if (!atomic_read(&pdev->enable_cnt))
3057 return;
3058
e315cd28
AC		 3059 base_vha = pci_get_drvdata(pdev);
3060 ha = base_vha->hw;
3061
2d70c103
NB		 3062 ha->flags.host_shutting_down = 1;
3063
220d36b4 3064 set_bit(UNLOADING, &base_vha->dpc_flags);
42479343
AB		 3065 if (IS_QLAFX00(ha))
3066 qlafx00_driver_shutdown(base_vha, 20);
3067
43ebf16d
AE		 3068 mutex_lock(&ha->vport_lock);
3069 while (ha->cur_vport_count) {
43ebf16d 3070 spin_lock_irqsave(&ha->vport_slock, flags);
feafb7b1 3071
43ebf16d
AE		 3072 BUG_ON(base_vha->list.next == &ha->vp_list);
3073 /* This assumes first entry in ha->vp_list is always base vha */
3074 vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list);
6e97c9d5 3075 scsi_host_get(vha->host);
feafb7b1 3076
43ebf16d
AE		 3077 spin_unlock_irqrestore(&ha->vport_slock, flags);
3078 mutex_unlock(&ha->vport_lock);
3079
3080 fc_vport_terminate(vha->fc_vport);
3081 scsi_host_put(vha->host);
feafb7b1 3082
43ebf16d 3083 mutex_lock(&ha->vport_lock);
e315cd28 3084 }
43ebf16d 3085 mutex_unlock(&ha->vport_lock);
1da177e4 3086
7d613ac6
SV		 3087 if (IS_QLA8031(ha)) {
3088 ql_dbg(ql_dbg_p3p, base_vha, 0xb07e,
3089 "Clearing fcoe driver presence.\n");
3090 if (qla83xx_clear_drv_presence(base_vha) != QLA_SUCCESS)
3091 ql_dbg(ql_dbg_p3p, base_vha, 0xb079,
3092 "Error while clearing DRV-Presence.\n");
3093 }
3094
b9978769
AV		 3095 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
3096
e315cd28 3097 qla2x00_dfs_remove(base_vha);
c795c1e4 3098
e315cd28 3099 qla84xx_put_chip(base_vha);
c795c1e4 3100
b9978769
AV		 3101 /* Disable timer */
3102 if (base_vha->timer_active)
3103 qla2x00_stop_timer(base_vha);
3104
3105 base_vha->flags.online = 0;
3106
68ca949c
AC		 3107 /* Flush the work queue and remove it */
3108 if (ha->wq) {
3109 flush_workqueue(ha->wq);
3110 destroy_workqueue(ha->wq);
3111 ha->wq = NULL;
3112 }
3113
7d613ac6
SV		 3114 /* Cancel all work and destroy DPC workqueues */
3115 if (ha->dpc_lp_wq) {
3116 cancel_work_sync(&ha->idc_aen);
3117 destroy_workqueue(ha->dpc_lp_wq);
3118 ha->dpc_lp_wq = NULL;
3119 }
3120
3121 if (ha->dpc_hp_wq) {
3122 cancel_work_sync(&ha->nic_core_reset);
3123 cancel_work_sync(&ha->idc_state_handler);
3124 cancel_work_sync(&ha->nic_core_unrecoverable);
3125 destroy_workqueue(ha->dpc_hp_wq);
3126 ha->dpc_hp_wq = NULL;
3127 }
3128
b9978769
AV		 3129 /* Kill the kernel thread for this host */
3130 if (ha->dpc_thread) {
3131 struct task_struct *t = ha->dpc_thread;
3132
3133 /*
3134 * qla2xxx_wake_dpc checks for ->dpc_thread
3135 * so we need to zero it out.
3136 */
3137 ha->dpc_thread = NULL;
3138 kthread_stop(t);
3139 }
2d70c103 3140 qlt_remove_target(ha, base_vha);
b9978769 3141
e315cd28 3142 qla2x00_free_sysfs_attr(base_vha);
df613b96 3143
e315cd28 3144 fc_remove_host(base_vha->host);
4d4df193 3145
e315cd28 3146 scsi_remove_host(base_vha->host);
1da177e4 3147
e315cd28 3148 qla2x00_free_device(base_vha);
bdf79621 3149
e315cd28 3150 scsi_host_put(base_vha->host);
1da177e4 3151
7ec0effd
AD		 3152 if (IS_QLA8044(ha)) {
3153 qla8044_idc_lock(ha);
3154 qla8044_clear_drv_active(base_vha);
3155 qla8044_idc_unlock(ha);
3156 }
a9083016 3157 if (IS_QLA82XX(ha)) {
b963752f
GM		 3158 qla82xx_idc_lock(ha);
3159 qla82xx_clear_drv_active(ha);
3160 qla82xx_idc_unlock(ha);
3161
a9083016
GM		 3162 iounmap((device_reg_t __iomem *)ha->nx_pcibase);
3163 if (!ql2xdbwr)
3164 iounmap((device_reg_t __iomem *)ha->nxdb_wr_ptr);
3165 } else {
3166 if (ha->iobase)
3167 iounmap(ha->iobase);
1da177e4 3168
8ae6d9c7
GM		 3169 if (ha->cregbase)
3170 iounmap(ha->cregbase);
3171
a9083016
GM		 3172 if (ha->mqiobase)
3173 iounmap(ha->mqiobase);
6246b8a1
GM		 3174
3175 if (IS_QLA83XX(ha) && ha->msixbase)
3176 iounmap(ha->msixbase);
a9083016 3177 }
73208dfd 3178
e315cd28
AC		 3179 pci_release_selected_regions(ha->pdev, ha->bars);
3180 kfree(ha);
3181 ha = NULL;
1da177e4 3182
90a86fc0
JC		 3183 pci_disable_pcie_error_reporting(pdev);
3184
665db93b 3185 pci_disable_device(pdev);
1da177e4
LT		 3186 pci_set_drvdata(pdev, NULL);
3187}
1da177e4
LT		 3188
3189static void
e315cd28 3190qla2x00_free_device(scsi_qla_host_t *vha)
1da177e4 3191{
e315cd28 3192 struct qla_hw_data *ha = vha->hw;
1da177e4 3193
85880801
AV		 3194 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
3195
3196 /* Disable timer */
3197 if (vha->timer_active)
3198 qla2x00_stop_timer(vha);
3199
2d70c103 3200 qla2x00_stop_dpc_thread(vha);
85880801 3201
2afa19a9 3202 qla25xx_delete_queues(vha);
df613b96 3203 if (ha->flags.fce_enabled)
e315cd28 3204 qla2x00_disable_fce_trace(vha, NULL, NULL);
df613b96 3205
a7a167bf 3206 if (ha->eft)
e315cd28 3207 qla2x00_disable_eft_trace(vha);
a7a167bf 3208
f6ef3b18 3209 /* Stop currently executing firmware. */
e315cd28 3210 qla2x00_try_to_stop_firmware(vha);
1da177e4 3211
85880801
AV		 3212 vha->flags.online = 0;
3213
f6ef3b18 3214 /* turn-off interrupts on the card */
a9083016
GM		 3215 if (ha->interrupts_on) {
3216 vha->flags.init_done = 0;
fd34f556 3217 ha->isp_ops->disable_intrs(ha);
a9083016 3218 }
f6ef3b18 3219
e315cd28 3220 qla2x00_free_irqs(vha);
1da177e4 3221
8867048b
CD		 3222 qla2x00_free_fcports(vha);
3223
e315cd28 3224 qla2x00_mem_free(ha);
73208dfd 3225
08de2844
GM		 3226 qla82xx_md_free(vha);
3227
73208dfd 3228 qla2x00_free_queues(ha);
1da177e4
LT		 3229}
3230
8867048b
CD		 3231void qla2x00_free_fcports(struct scsi_qla_host *vha)
3232{
3233 fc_port_t *fcport, *tfcport;
3234
3235 list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list) {
3236 list_del(&fcport->list);
5f16b331 3237 qla2x00_clear_loop_id(fcport);
8867048b
CD		 3238 kfree(fcport);
3239 fcport = NULL;
3240 }
3241}
3242
d97994dc 3243static inline void
e315cd28 3244qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport,
d97994dc 3245 int defer)
3246{
d97994dc 3247 struct fc_rport *rport;
67becc00 3248 scsi_qla_host_t *base_vha;
044d78e1 3249 unsigned long flags;
d97994dc 3250
3251 if (!fcport->rport)
3252 return;
3253
3254 rport = fcport->rport;
3255 if (defer) {
67becc00 3256 base_vha = pci_get_drvdata(vha->hw->pdev);
044d78e1 3257 spin_lock_irqsave(vha->host->host_lock, flags);
d97994dc 3258 fcport->drport = rport;
044d78e1 3259 spin_unlock_irqrestore(vha->host->host_lock, flags);
67becc00
AV		 3260 set_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags);
3261 qla2xxx_wake_dpc(base_vha);
2d70c103 3262 } else {
d97994dc 3263 fc_remote_port_delete(rport);
2d70c103
NB		 3264 qlt_fc_port_deleted(vha, fcport);
3265 }
d97994dc 3266}
3267
1da177e4
LT		 3268/*
3269 * qla2x00_mark_device_lost Updates fcport state when device goes offline.
3270 *
3271 * Input: ha = adapter block pointer. fcport = port structure pointer.
3272 *
3273 * Return: None.
3274 *
3275 * Context:
3276 */
e315cd28 3277void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport,
d97994dc 3278 int do_login, int defer)
1da177e4 3279{
8ae6d9c7
GM		 3280 if (IS_QLAFX00(vha->hw)) {
3281 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
3282 qla2x00_schedule_rport_del(vha, fcport, defer);
3283 return;
3284 }
3285
2c3dfe3f 3286 if (atomic_read(&fcport->state) == FCS_ONLINE &&
c6d39e23 3287 vha->vp_idx == fcport->vha->vp_idx) {
ec426e10 3288 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
e315cd28
AC		 3289 qla2x00_schedule_rport_del(vha, fcport, defer);
3290 }
fa2a1ce5 3291 /*
1da177e4
LT		 3292 * We may need to retry the login, so don't change the state of the
3293 * port but do the retries.
3294 */
3295 if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD)
ec426e10 3296 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
1da177e4
LT		 3297
3298 if (!do_login)
3299 return;
3300
3301 if (fcport->login_retry == 0) {
e315cd28
AC		 3302 fcport->login_retry = vha->hw->login_retry_count;
3303 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
1da177e4 3304
7c3df132 3305 ql_dbg(ql_dbg_disc, vha, 0x2067,
7b833558
OK		 3306 "Port login retry %8phN, id = 0x%04x retry cnt=%d.\n",
3307 fcport->port_name, fcport->loop_id, fcport->login_retry);
1da177e4
LT		 3308 }
3309}
3310
3311/*
3312 * qla2x00_mark_all_devices_lost
3313 * Updates fcport state when device goes offline.
3314 *
3315 * Input:
3316 * ha = adapter block pointer.
3317 * fcport = port structure pointer.
3318 *
3319 * Return:
3320 * None.
3321 *
3322 * Context:
3323 */
3324void
e315cd28 3325qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha, int defer)
1da177e4
LT		 3326{
3327 fc_port_t *fcport;
3328
e315cd28 3329 list_for_each_entry(fcport, &vha->vp_fcports, list) {
c6d39e23 3330 if (vha->vp_idx != 0 && vha->vp_idx != fcport->vha->vp_idx)
1da177e4 3331 continue;
0d6e61bc 3332
1da177e4
LT		 3333 /*
3334 * No point in marking the device as lost, if the device is
3335 * already DEAD.
3336 */
3337 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD)
3338 continue;
e315cd28 3339 if (atomic_read(&fcport->state) == FCS_ONLINE) {
ec426e10 3340 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
0d6e61bc
AV		 3341 if (defer)
3342 qla2x00_schedule_rport_del(vha, fcport, defer);
c6d39e23 3343 else if (vha->vp_idx == fcport->vha->vp_idx)
0d6e61bc
AV		 3344 qla2x00_schedule_rport_del(vha, fcport, defer);
3345 }
1da177e4
LT		 3346 }
3347}
3348
3349/*
3350* qla2x00_mem_alloc
3351* Allocates adapter memory.
3352*
3353* Returns:
3354* 0 = success.
e8711085 3355* !0 = failure.
1da177e4 3356*/
e8711085 3357static int
73208dfd
AC		 3358qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len,
3359 struct req_que **req, struct rsp_que **rsp)
1da177e4
LT		 3360{
3361 char name[16];
1da177e4 3362
e8711085 3363 ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size,
e315cd28 3364 &ha->init_cb_dma, GFP_KERNEL);
e8711085 3365 if (!ha->init_cb)
e315cd28 3366 goto fail;
e8711085 3367
2d70c103
NB		 3368 if (qlt_mem_alloc(ha) < 0)
3369 goto fail_free_init_cb;
3370
642ef983
CD		 3371 ha->gid_list = dma_alloc_coherent(&ha->pdev->dev,
3372 qla2x00_gid_list_size(ha), &ha->gid_list_dma, GFP_KERNEL);
e315cd28 3373 if (!ha->gid_list)
2d70c103 3374 goto fail_free_tgt_mem;
1da177e4 3375
e8711085
AV		 3376 ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep);
3377 if (!ha->srb_mempool)
e315cd28 3378 goto fail_free_gid_list;
e8711085 3379
7ec0effd 3380 if (IS_P3P_TYPE(ha)) {
a9083016
GM		 3381 /* Allocate cache for CT6 Ctx. */
3382 if (!ctx_cachep) {
3383 ctx_cachep = kmem_cache_create("qla2xxx_ctx",
3384 sizeof(struct ct6_dsd), 0,
3385 SLAB_HWCACHE_ALIGN, NULL);
3386 if (!ctx_cachep)
3387 goto fail_free_gid_list;
3388 }
3389 ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ,
3390 ctx_cachep);
3391 if (!ha->ctx_mempool)
3392 goto fail_free_srb_mempool;
7c3df132
SK		 3393 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021,
3394 "ctx_cachep=%p ctx_mempool=%p.\n",
3395 ctx_cachep, ha->ctx_mempool);
a9083016
GM		 3396 }
3397
e8711085
AV		 3398 /* Get memory for cached NVRAM */
3399 ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL);
3400 if (!ha->nvram)
a9083016 3401 goto fail_free_ctx_mempool;
e8711085 3402
e315cd28
AC		 3403 snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME,
3404 ha->pdev->device);
3405 ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3406 DMA_POOL_SIZE, 8, 0);
3407 if (!ha->s_dma_pool)
3408 goto fail_free_nvram;
3409
7c3df132
SK		 3410 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022,
3411 "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n",
3412 ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool);
3413
7ec0effd 3414 if (IS_P3P_TYPE(ha) || ql2xenabledif) {
a9083016
GM		 3415 ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3416 DSD_LIST_DMA_POOL_SIZE, 8, 0);
3417 if (!ha->dl_dma_pool) {
7c3df132
SK		 3418 ql_log_pci(ql_log_fatal, ha->pdev, 0x0023,
3419 "Failed to allocate memory for dl_dma_pool.\n");
a9083016
GM		 3420 goto fail_s_dma_pool;
3421 }
3422
3423 ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3424 FCP_CMND_DMA_POOL_SIZE, 8, 0);
3425 if (!ha->fcp_cmnd_dma_pool) {
7c3df132
SK		 3426 ql_log_pci(ql_log_fatal, ha->pdev, 0x0024,
3427 "Failed to allocate memory for fcp_cmnd_dma_pool.\n");
a9083016
GM		 3428 goto fail_dl_dma_pool;
3429 }
7c3df132
SK		 3430 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025,
3431 "dl_dma_pool=%p fcp_cmnd_dma_pool=%p.\n",
3432 ha->dl_dma_pool, ha->fcp_cmnd_dma_pool);
a9083016
GM		 3433 }
3434
e8711085
AV		 3435 /* Allocate memory for SNS commands */
3436 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
e315cd28 3437 /* Get consistent memory allocated for SNS commands */
e8711085 3438 ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev,
e315cd28 3439 sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL);
e8711085 3440 if (!ha->sns_cmd)
e315cd28 3441 goto fail_dma_pool;
7c3df132 3442 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026,
d8424f68 3443 "sns_cmd: %p.\n", ha->sns_cmd);
e8711085 3444 } else {
e315cd28 3445 /* Get consistent memory allocated for MS IOCB */
e8711085 3446 ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
e315cd28 3447 &ha->ms_iocb_dma);
e8711085 3448 if (!ha->ms_iocb)
e315cd28
AC		 3449 goto fail_dma_pool;
3450 /* Get consistent memory allocated for CT SNS commands */
e8711085 3451 ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev,
e315cd28 3452 sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL);
e8711085
AV		 3453 if (!ha->ct_sns)
3454 goto fail_free_ms_iocb;
7c3df132
SK		 3455 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027,
3456 "ms_iocb=%p ct_sns=%p.\n",
3457 ha->ms_iocb, ha->ct_sns);
1da177e4
LT		 3458 }
3459
e315cd28 3460 /* Allocate memory for request ring */
73208dfd
AC		 3461 *req = kzalloc(sizeof(struct req_que), GFP_KERNEL);
3462 if (!*req) {
7c3df132
SK		 3463 ql_log_pci(ql_log_fatal, ha->pdev, 0x0028,
3464 "Failed to allocate memory for req.\n");
e315cd28
AC		 3465 goto fail_req;
3466 }
73208dfd
AC		 3467 (*req)->length = req_len;
3468 (*req)->ring = dma_alloc_coherent(&ha->pdev->dev,
3469 ((*req)->length + 1) * sizeof(request_t),
3470 &(*req)->dma, GFP_KERNEL);
3471 if (!(*req)->ring) {
7c3df132
SK		 3472 ql_log_pci(ql_log_fatal, ha->pdev, 0x0029,
3473 "Failed to allocate memory for req_ring.\n");
e315cd28
AC		 3474 goto fail_req_ring;
3475 }
3476 /* Allocate memory for response ring */
73208dfd
AC		 3477 *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL);
3478 if (!*rsp) {
7c3df132
SK		 3479 ql_log_pci(ql_log_fatal, ha->pdev, 0x002a,
3480 "Failed to allocate memory for rsp.\n");
e315cd28
AC		 3481 goto fail_rsp;
3482 }
73208dfd
AC		 3483 (*rsp)->hw = ha;
3484 (*rsp)->length = rsp_len;
3485 (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev,
3486 ((*rsp)->length + 1) * sizeof(response_t),
3487 &(*rsp)->dma, GFP_KERNEL);
3488 if (!(*rsp)->ring) {
7c3df132
SK		 3489 ql_log_pci(ql_log_fatal, ha->pdev, 0x002b,
3490 "Failed to allocate memory for rsp_ring.\n");
e315cd28
AC		 3491 goto fail_rsp_ring;
3492 }
73208dfd
AC		 3493 (*req)->rsp = *rsp;
3494 (*rsp)->req = *req;
7c3df132
SK		 3495 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c,
3496 "req=%p req->length=%d req->ring=%p rsp=%p "
3497 "rsp->length=%d rsp->ring=%p.\n",
3498 *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length,
3499 (*rsp)->ring);
73208dfd
AC		 3500 /* Allocate memory for NVRAM data for vports */
3501 if (ha->nvram_npiv_size) {
3502 ha->npiv_info = kzalloc(sizeof(struct qla_npiv_entry) *
7c3df132 3503 ha->nvram_npiv_size, GFP_KERNEL);
73208dfd 3504 if (!ha->npiv_info) {
7c3df132
SK		 3505 ql_log_pci(ql_log_fatal, ha->pdev, 0x002d,
3506 "Failed to allocate memory for npiv_info.\n");
73208dfd
AC		 3507 goto fail_npiv_info;
3508 }
3509 } else
3510 ha->npiv_info = NULL;
e8711085 3511
b64b0e8f 3512 /* Get consistent memory allocated for EX-INIT-CB. */
6246b8a1 3513 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha)) {
b64b0e8f
AV		 3514 ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
3515 &ha->ex_init_cb_dma);
3516 if (!ha->ex_init_cb)
3517 goto fail_ex_init_cb;
7c3df132
SK		 3518 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e,
3519 "ex_init_cb=%p.\n", ha->ex_init_cb);
b64b0e8f
AV		 3520 }
3521
a9083016
GM		 3522 INIT_LIST_HEAD(&ha->gbl_dsd_list);
3523
5ff1d584
AV		 3524 /* Get consistent memory allocated for Async Port-Database. */
3525 if (!IS_FWI2_CAPABLE(ha)) {
3526 ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
3527 &ha->async_pd_dma);
3528 if (!ha->async_pd)
3529 goto fail_async_pd;
7c3df132
SK		 3530 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f,
3531 "async_pd=%p.\n", ha->async_pd);
5ff1d584
AV		 3532 }
3533
e315cd28 3534 INIT_LIST_HEAD(&ha->vp_list);
5f16b331
CD		 3535
3536 /* Allocate memory for our loop_id bitmap */
3537 ha->loop_id_map = kzalloc(BITS_TO_LONGS(LOOPID_MAP_SIZE) * sizeof(long),
3538 GFP_KERNEL);
3539 if (!ha->loop_id_map)
3540 goto fail_async_pd;
3541 else {
3542 qla2x00_set_reserved_loop_ids(ha);
3543 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0123,
3544 "loop_id_map=%p. \n", ha->loop_id_map);
3545 }
3546
e315cd28
AC		 3547 return 1;
3548
5ff1d584
AV		 3549fail_async_pd:
3550 dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma);
b64b0e8f
AV		 3551fail_ex_init_cb:
3552 kfree(ha->npiv_info);
73208dfd
AC		 3553fail_npiv_info:
3554 dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) *
3555 sizeof(response_t), (*rsp)->ring, (*rsp)->dma);
3556 (*rsp)->ring = NULL;
3557 (*rsp)->dma = 0;
e315cd28 3558fail_rsp_ring:
73208dfd 3559 kfree(*rsp);
e315cd28 3560fail_rsp:
73208dfd
AC		 3561 dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) *
3562 sizeof(request_t), (*req)->ring, (*req)->dma);
3563 (*req)->ring = NULL;
3564 (*req)->dma = 0;
e315cd28 3565fail_req_ring:
73208dfd 3566 kfree(*req);
e315cd28
AC		 3567fail_req:
3568 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
3569 ha->ct_sns, ha->ct_sns_dma);
3570 ha->ct_sns = NULL;
3571 ha->ct_sns_dma = 0;
e8711085
AV		 3572fail_free_ms_iocb:
3573 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
3574 ha->ms_iocb = NULL;
3575 ha->ms_iocb_dma = 0;
e315cd28 3576fail_dma_pool:
bad75002 3577 if (IS_QLA82XX(ha) || ql2xenabledif) {
a9083016
GM		 3578 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
3579 ha->fcp_cmnd_dma_pool = NULL;
3580 }
3581fail_dl_dma_pool:
bad75002 3582 if (IS_QLA82XX(ha) || ql2xenabledif) {
a9083016
GM		 3583 dma_pool_destroy(ha->dl_dma_pool);
3584 ha->dl_dma_pool = NULL;
3585 }
3586fail_s_dma_pool:
e315cd28
AC		 3587 dma_pool_destroy(ha->s_dma_pool);
3588 ha->s_dma_pool = NULL;
e8711085
AV		 3589fail_free_nvram:
3590 kfree(ha->nvram);
3591 ha->nvram = NULL;
a9083016
GM		 3592fail_free_ctx_mempool:
3593 mempool_destroy(ha->ctx_mempool);
3594 ha->ctx_mempool = NULL;
e8711085
AV		 3595fail_free_srb_mempool:
3596 mempool_destroy(ha->srb_mempool);
3597 ha->srb_mempool = NULL;
e8711085 3598fail_free_gid_list:
642ef983
CD		 3599 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
3600 ha->gid_list,
e315cd28 3601 ha->gid_list_dma);
e8711085
AV		 3602 ha->gid_list = NULL;
3603 ha->gid_list_dma = 0;
2d70c103
NB		 3604fail_free_tgt_mem:
3605 qlt_mem_free(ha);
e315cd28
AC		 3606fail_free_init_cb:
3607 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb,
3608 ha->init_cb_dma);
3609 ha->init_cb = NULL;
3610 ha->init_cb_dma = 0;
e8711085 3611fail:
7c3df132
SK		 3612 ql_log(ql_log_fatal, NULL, 0x0030,
3613 "Memory allocation failure.\n");
e8711085 3614 return -ENOMEM;
1da177e4
LT		 3615}
3616
3617/*
e30d1756
MI		 3618* qla2x00_free_fw_dump
3619* Frees fw dump stuff.
1da177e4
LT		 3620*
3621* Input:
7ec0effd 3622* ha = adapter block pointer
1da177e4 3623*/
a824ebb3 3624static void
e30d1756 3625qla2x00_free_fw_dump(struct qla_hw_data *ha)
1da177e4 3626{
df613b96
AV		 3627 if (ha->fce)
3628 dma_free_coherent(&ha->pdev->dev, FCE_SIZE, ha->fce,
e30d1756 3629 ha->fce_dma);
df613b96 3630
a7a167bf
AV		 3631 if (ha->fw_dump) {
3632 if (ha->eft)
3633 dma_free_coherent(&ha->pdev->dev,
e30d1756 3634 ntohl(ha->fw_dump->eft_size), ha->eft, ha->eft_dma);
a7a167bf
AV		 3635 vfree(ha->fw_dump);
3636 }
e30d1756
MI		 3637 ha->fce = NULL;
3638 ha->fce_dma = 0;
3639 ha->eft = NULL;
3640 ha->eft_dma = 0;
3641 ha->fw_dump = NULL;
3642 ha->fw_dumped = 0;
3643 ha->fw_dump_reading = 0;
3644}
3645
3646/*
3647* qla2x00_mem_free
3648* Frees all adapter allocated memory.
3649*
3650* Input:
3651* ha = adapter block pointer.
3652*/
3653static void
3654qla2x00_mem_free(struct qla_hw_data *ha)
3655{
3656 qla2x00_free_fw_dump(ha);
3657
81178772
SK		 3658 if (ha->mctp_dump)
3659 dma_free_coherent(&ha->pdev->dev, MCTP_DUMP_SIZE, ha->mctp_dump,
3660 ha->mctp_dump_dma);
3661
e30d1756
MI		 3662 if (ha->srb_mempool)
3663 mempool_destroy(ha->srb_mempool);
a7a167bf 3664
11bbc1d8
AV		 3665 if (ha->dcbx_tlv)
3666 dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE,
3667 ha->dcbx_tlv, ha->dcbx_tlv_dma);
3668
ce0423f4
AV		 3669 if (ha->xgmac_data)
3670 dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE,
3671 ha->xgmac_data, ha->xgmac_data_dma);
3672
1da177e4
LT		 3673 if (ha->sns_cmd)
3674 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
e315cd28 3675 ha->sns_cmd, ha->sns_cmd_dma);
1da177e4
LT		 3676
3677 if (ha->ct_sns)
3678 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
e315cd28 3679 ha->ct_sns, ha->ct_sns_dma);
1da177e4 3680
88729e53
AV		 3681 if (ha->sfp_data)
3682 dma_pool_free(ha->s_dma_pool, ha->sfp_data, ha->sfp_data_dma);
3683
1da177e4
LT		 3684 if (ha->ms_iocb)
3685 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
3686
b64b0e8f 3687 if (ha->ex_init_cb)
a9083016
GM		 3688 dma_pool_free(ha->s_dma_pool,
3689 ha->ex_init_cb, ha->ex_init_cb_dma);
b64b0e8f 3690
5ff1d584
AV		 3691 if (ha->async_pd)
3692 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
3693
1da177e4
LT		 3694 if (ha->s_dma_pool)
3695 dma_pool_destroy(ha->s_dma_pool);
3696
1da177e4 3697 if (ha->gid_list)
642ef983
CD		 3698 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
3699 ha->gid_list, ha->gid_list_dma);
1da177e4 3700
a9083016
GM		 3701 if (IS_QLA82XX(ha)) {
3702 if (!list_empty(&ha->gbl_dsd_list)) {
3703 struct dsd_dma *dsd_ptr, *tdsd_ptr;
3704
3705 /* clean up allocated prev pool */
3706 list_for_each_entry_safe(dsd_ptr,
3707 tdsd_ptr, &ha->gbl_dsd_list, list) {
3708 dma_pool_free(ha->dl_dma_pool,
3709 dsd_ptr->dsd_addr, dsd_ptr->dsd_list_dma);
3710 list_del(&dsd_ptr->list);
3711 kfree(dsd_ptr);
3712 }
3713 }
3714 }
3715
3716 if (ha->dl_dma_pool)
3717 dma_pool_destroy(ha->dl_dma_pool);
3718
3719 if (ha->fcp_cmnd_dma_pool)
3720 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
3721
3722 if (ha->ctx_mempool)
3723 mempool_destroy(ha->ctx_mempool);
3724
2d70c103
NB		 3725 qlt_mem_free(ha);
3726
e315cd28
AC		 3727 if (ha->init_cb)
3728 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size,
a9083016 3729 ha->init_cb, ha->init_cb_dma);
e315cd28
AC		 3730 vfree(ha->optrom_buffer);
3731 kfree(ha->nvram);
73208dfd 3732 kfree(ha->npiv_info);
7a67735b 3733 kfree(ha->swl);
5f16b331 3734 kfree(ha->loop_id_map);
1da177e4 3735
e8711085 3736 ha->srb_mempool = NULL;
a9083016 3737 ha->ctx_mempool = NULL;
1da177e4
LT		 3738 ha->sns_cmd = NULL;
3739 ha->sns_cmd_dma = 0;
3740 ha->ct_sns = NULL;
3741 ha->ct_sns_dma = 0;
3742 ha->ms_iocb = NULL;
3743 ha->ms_iocb_dma = 0;
1da177e4
LT		 3744 ha->init_cb = NULL;
3745 ha->init_cb_dma = 0;
b64b0e8f
AV		 3746 ha->ex_init_cb = NULL;
3747 ha->ex_init_cb_dma = 0;
5ff1d584
AV		 3748 ha->async_pd = NULL;
3749 ha->async_pd_dma = 0;
1da177e4
LT		 3750
3751 ha->s_dma_pool = NULL;
a9083016
GM		 3752 ha->dl_dma_pool = NULL;
3753 ha->fcp_cmnd_dma_pool = NULL;
1da177e4 3754
1da177e4
LT		 3755 ha->gid_list = NULL;
3756 ha->gid_list_dma = 0;
2d70c103
NB		 3757
3758 ha->tgt.atio_ring = NULL;
3759 ha->tgt.atio_dma = 0;
3760 ha->tgt.tgt_vp_map = NULL;
e315cd28 3761}
1da177e4 3762
e315cd28
AC		 3763struct scsi_qla_host *qla2x00_create_host(struct scsi_host_template *sht,
3764 struct qla_hw_data *ha)
3765{
3766 struct Scsi_Host *host;
3767 struct scsi_qla_host *vha = NULL;
854165f4 3768
e315cd28
AC		 3769 host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t));
3770 if (host == NULL) {
7c3df132
SK		 3771 ql_log_pci(ql_log_fatal, ha->pdev, 0x0107,
3772 "Failed to allocate host from the scsi layer, aborting.\n");
e315cd28
AC		 3773 goto fail;
3774 }
3775
3776 /* Clear our data area */
3777 vha = shost_priv(host);
3778 memset(vha, 0, sizeof(scsi_qla_host_t));
3779
3780 vha->host = host;
3781 vha->host_no = host->host_no;
3782 vha->hw = ha;
3783
3784 INIT_LIST_HEAD(&vha->vp_fcports);
3785 INIT_LIST_HEAD(&vha->work_list);
3786 INIT_LIST_HEAD(&vha->list);
3787
f999f4c1
AV		 3788 spin_lock_init(&vha->work_lock);
3789
e315cd28 3790 sprintf(vha->host_str, "%s_%ld", QLA2XXX_DRIVER_NAME, vha->host_no);
7c3df132
SK		 3791 ql_dbg(ql_dbg_init, vha, 0x0041,
3792 "Allocated the host=%p hw=%p vha=%p dev_name=%s",
3793 vha->host, vha->hw, vha,
3794 dev_name(&(ha->pdev->dev)));
3795
e315cd28
AC		 3796 return vha;
3797
3798fail:
3799 return vha;
1da177e4
LT		 3800}
3801
01ef66bb 3802static struct qla_work_evt *
f999f4c1 3803qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type)
0971de7f
AV		 3804{
3805 struct qla_work_evt *e;
feafb7b1
AE		 3806 uint8_t bail;
3807
3808 QLA_VHA_MARK_BUSY(vha, bail);
3809 if (bail)
3810 return NULL;
0971de7f 3811
f999f4c1 3812 e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC);
feafb7b1
AE		 3813 if (!e) {
3814 QLA_VHA_MARK_NOT_BUSY(vha);
0971de7f 3815 return NULL;
feafb7b1 3816 }
0971de7f
AV		 3817
3818 INIT_LIST_HEAD(&e->list);
3819 e->type = type;
3820 e->flags = QLA_EVT_FLAG_FREE;
3821 return e;
3822}
3823
01ef66bb 3824static int
f999f4c1 3825qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e)
0971de7f 3826{
f999f4c1 3827 unsigned long flags;
0971de7f 3828
f999f4c1 3829 spin_lock_irqsave(&vha->work_lock, flags);
e315cd28 3830 list_add_tail(&e->list, &vha->work_list);
f999f4c1 3831 spin_unlock_irqrestore(&vha->work_lock, flags);
e315cd28 3832 qla2xxx_wake_dpc(vha);
f999f4c1 3833
0971de7f
AV		 3834 return QLA_SUCCESS;
3835}
3836
3837int
e315cd28 3838qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code,
0971de7f
AV		 3839 u32 data)
3840{
3841 struct qla_work_evt *e;
3842
f999f4c1 3843 e = qla2x00_alloc_work(vha, QLA_EVT_AEN);
0971de7f
AV		 3844 if (!e)
3845 return QLA_FUNCTION_FAILED;
3846
3847 e->u.aen.code = code;
3848 e->u.aen.data = data;
f999f4c1 3849 return qla2x00_post_work(vha, e);
0971de7f
AV		 3850}
3851
8a659571
AV		 3852int
3853qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb)
3854{
3855 struct qla_work_evt *e;
3856
f999f4c1 3857 e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK);
8a659571
AV		 3858 if (!e)
3859 return QLA_FUNCTION_FAILED;
3860
3861 memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t));
f999f4c1 3862 return qla2x00_post_work(vha, e);
8a659571
AV		 3863}
3864
ac280b67
AV		 3865#define qla2x00_post_async_work(name, type) \
3866int qla2x00_post_async_##name##_work( \
3867 struct scsi_qla_host *vha, \
3868 fc_port_t *fcport, uint16_t *data) \
3869{ \
3870 struct qla_work_evt *e; \
3871 \
3872 e = qla2x00_alloc_work(vha, type); \
3873 if (!e) \
3874 return QLA_FUNCTION_FAILED; \
3875 \
3876 e->u.logio.fcport = fcport; \
3877 if (data) { \
3878 e->u.logio.data[0] = data[0]; \
3879 e->u.logio.data[1] = data[1]; \
3880 } \
3881 return qla2x00_post_work(vha, e); \
3882}
3883
3884qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN);
3885qla2x00_post_async_work(login_done, QLA_EVT_ASYNC_LOGIN_DONE);
3886qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT);
3887qla2x00_post_async_work(logout_done, QLA_EVT_ASYNC_LOGOUT_DONE);
5ff1d584
AV		 3888qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC);
3889qla2x00_post_async_work(adisc_done, QLA_EVT_ASYNC_ADISC_DONE);
ac280b67 3890
3420d36c
AV		 3891int
3892qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code)
3893{
3894 struct qla_work_evt *e;
3895
3896 e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT);
3897 if (!e)
3898 return QLA_FUNCTION_FAILED;
3899
3900 e->u.uevent.code = code;
3901 return qla2x00_post_work(vha, e);
3902}
3903
3904static void
3905qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code)
3906{
3907 char event_string[40];
3908 char *envp[] = { event_string, NULL };
3909
3910 switch (code) {
3911 case QLA_UEVENT_CODE_FW_DUMP:
3912 snprintf(event_string, sizeof(event_string), "FW_DUMP=%ld",
3913 vha->host_no);
3914 break;
3915 default:
3916 /* do nothing */
3917 break;
3918 }
3919 kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp);
3920}
3921
8ae6d9c7
GM		 3922int
3923qlafx00_post_aenfx_work(struct scsi_qla_host *vha, uint32_t evtcode,
3924 uint32_t *data, int cnt)
3925{
3926 struct qla_work_evt *e;
3927
3928 e = qla2x00_alloc_work(vha, QLA_EVT_AENFX);
3929 if (!e)
3930 return QLA_FUNCTION_FAILED;
3931
3932 e->u.aenfx.evtcode = evtcode;
3933 e->u.aenfx.count = cnt;
3934 memcpy(e->u.aenfx.mbx, data, sizeof(*data) * cnt);
3935 return qla2x00_post_work(vha, e);
3936}
3937
ac280b67 3938void
e315cd28 3939qla2x00_do_work(struct scsi_qla_host *vha)
0971de7f 3940{
f999f4c1
AV		 3941 struct qla_work_evt *e, *tmp;
3942 unsigned long flags;
3943 LIST_HEAD(work);
0971de7f 3944
f999f4c1
AV		 3945 spin_lock_irqsave(&vha->work_lock, flags);
3946 list_splice_init(&vha->work_list, &work);
3947 spin_unlock_irqrestore(&vha->work_lock, flags);
3948
3949 list_for_each_entry_safe(e, tmp, &work, list) {
0971de7f 3950 list_del_init(&e->list);
0971de7f
AV		 3951
3952 switch (e->type) {
3953 case QLA_EVT_AEN:
e315cd28 3954 fc_host_post_event(vha->host, fc_get_event_number(),
0971de7f
AV		 3955 e->u.aen.code, e->u.aen.data);
3956 break;
8a659571
AV		 3957 case QLA_EVT_IDC_ACK:
3958 qla81xx_idc_ack(vha, e->u.idc_ack.mb);
3959 break;
ac280b67
AV		 3960 case QLA_EVT_ASYNC_LOGIN:
3961 qla2x00_async_login(vha, e->u.logio.fcport,
3962 e->u.logio.data);
3963 break;
3964 case QLA_EVT_ASYNC_LOGIN_DONE:
3965 qla2x00_async_login_done(vha, e->u.logio.fcport,
3966 e->u.logio.data);
3967 break;
3968 case QLA_EVT_ASYNC_LOGOUT:
3969 qla2x00_async_logout(vha, e->u.logio.fcport);
3970 break;
3971 case QLA_EVT_ASYNC_LOGOUT_DONE:
3972 qla2x00_async_logout_done(vha, e->u.logio.fcport,
3973 e->u.logio.data);
3974 break;
5ff1d584
AV		 3975 case QLA_EVT_ASYNC_ADISC:
3976 qla2x00_async_adisc(vha, e->u.logio.fcport,
3977 e->u.logio.data);
3978 break;
3979 case QLA_EVT_ASYNC_ADISC_DONE:
3980 qla2x00_async_adisc_done(vha, e->u.logio.fcport,
3981 e->u.logio.data);
3982 break;
3420d36c
AV		 3983 case QLA_EVT_UEVENT:
3984 qla2x00_uevent_emit(vha, e->u.uevent.code);
3985 break;
8ae6d9c7
GM		 3986 case QLA_EVT_AENFX:
3987 qlafx00_process_aen(vha, e);
3988 break;
0971de7f
AV		 3989 }
3990 if (e->flags & QLA_EVT_FLAG_FREE)
3991 kfree(e);
feafb7b1
AE		 3992
3993 /* For each work completed decrement vha ref count */
3994 QLA_VHA_MARK_NOT_BUSY(vha);
e315cd28 3995 }
e315cd28 3996}
f999f4c1 3997
e315cd28
AC		 3998/* Relogins all the fcports of a vport
3999 * Context: dpc thread
4000 */
4001void qla2x00_relogin(struct scsi_qla_host *vha)
4002{
4003 fc_port_t *fcport;
c6b2fca8 4004 int status;
e315cd28
AC		 4005 uint16_t next_loopid = 0;
4006 struct qla_hw_data *ha = vha->hw;
ac280b67 4007 uint16_t data[2];
e315cd28
AC		 4008
4009 list_for_each_entry(fcport, &vha->vp_fcports, list) {
4010 /*
4011 * If the port is not ONLINE then try to login
4012 * to it if we haven't run out of retries.
4013 */
5ff1d584
AV		 4014 if (atomic_read(&fcport->state) != FCS_ONLINE &&
4015 fcport->login_retry && !(fcport->flags & FCF_ASYNC_SENT)) {
ac280b67 4016 fcport->login_retry--;
e315cd28 4017 if (fcport->flags & FCF_FABRIC_DEVICE) {
f08b7251 4018 if (fcport->flags & FCF_FCP2_DEVICE)
e315cd28
AC		 4019 ha->isp_ops->fabric_logout(vha,
4020 fcport->loop_id,
4021 fcport->d_id.b.domain,
4022 fcport->d_id.b.area,
4023 fcport->d_id.b.al_pa);
4024
03bcfb57
JC		 4025 if (fcport->loop_id == FC_NO_LOOP_ID) {
4026 fcport->loop_id = next_loopid =
4027 ha->min_external_loopid;
4028 status = qla2x00_find_new_loop_id(
4029 vha, fcport);
4030 if (status != QLA_SUCCESS) {
4031 /* Ran out of IDs to use */
4032 break;
4033 }
4034 }
4035
ac280b67 4036 if (IS_ALOGIO_CAPABLE(ha)) {
5ff1d584 4037 fcport->flags |= FCF_ASYNC_SENT;
ac280b67
AV		 4038 data[0] = 0;
4039 data[1] = QLA_LOGIO_LOGIN_RETRIED;
4040 status = qla2x00_post_async_login_work(
4041 vha, fcport, data);
4042 if (status == QLA_SUCCESS)
4043 continue;
4044 /* Attempt a retry. */
4045 status = 1;
aaf4d3e2 4046 } else {
ac280b67
AV		 4047 status = qla2x00_fabric_login(vha,
4048 fcport, &next_loopid);
aaf4d3e2
SK		 4049 if (status == QLA_SUCCESS) {
4050 int status2;
4051 uint8_t opts;
4052
4053 opts = 0;
4054 if (fcport->flags &
4055 FCF_FCP2_DEVICE)
4056 opts |= BIT_1;
03003960
SK		 4057 status2 =
4058 qla2x00_get_port_database(
4059 vha, fcport, opts);
aaf4d3e2
SK		 4060 if (status2 != QLA_SUCCESS)
4061 status = 1;
4062 }
4063 }
e315cd28
AC		 4064 } else
4065 status = qla2x00_local_device_login(vha,
4066 fcport);
4067
e315cd28
AC		 4068 if (status == QLA_SUCCESS) {
4069 fcport->old_loop_id = fcport->loop_id;
4070
7c3df132
SK		 4071 ql_dbg(ql_dbg_disc, vha, 0x2003,
4072 "Port login OK: logged in ID 0x%x.\n",
4073 fcport->loop_id);
e315cd28
AC		 4074
4075 qla2x00_update_fcport(vha, fcport);
4076
4077 } else if (status == 1) {
4078 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
4079 /* retry the login again */
7c3df132
SK		 4080 ql_dbg(ql_dbg_disc, vha, 0x2007,
4081 "Retrying %d login again loop_id 0x%x.\n",
4082 fcport->login_retry, fcport->loop_id);
e315cd28
AC		 4083 } else {
4084 fcport->login_retry = 0;
4085 }
4086
4087 if (fcport->login_retry == 0 && status != QLA_SUCCESS)
5f16b331 4088 qla2x00_clear_loop_id(fcport);
e315cd28
AC		 4089 }
4090 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
4091 break;
0971de7f 4092 }
0971de7f
AV		 4093}
4094
7d613ac6
SV		 4095/* Schedule work on any of the dpc-workqueues */
4096void
4097qla83xx_schedule_work(scsi_qla_host_t *base_vha, int work_code)
4098{
4099 struct qla_hw_data *ha = base_vha->hw;
4100
4101 switch (work_code) {
4102 case MBA_IDC_AEN: /* 0x8200 */
4103 if (ha->dpc_lp_wq)
4104 queue_work(ha->dpc_lp_wq, &ha->idc_aen);
4105 break;
4106
4107 case QLA83XX_NIC_CORE_RESET: /* 0x1 */
4108 if (!ha->flags.nic_core_reset_hdlr_active) {
4109 if (ha->dpc_hp_wq)
4110 queue_work(ha->dpc_hp_wq, &ha->nic_core_reset);
4111 } else
4112 ql_dbg(ql_dbg_p3p, base_vha, 0xb05e,
4113 "NIC Core reset is already active. Skip "
4114 "scheduling it again.\n");
4115 break;
4116 case QLA83XX_IDC_STATE_HANDLER: /* 0x2 */
4117 if (ha->dpc_hp_wq)
4118 queue_work(ha->dpc_hp_wq, &ha->idc_state_handler);
4119 break;
4120 case QLA83XX_NIC_CORE_UNRECOVERABLE: /* 0x3 */
4121 if (ha->dpc_hp_wq)
4122 queue_work(ha->dpc_hp_wq, &ha->nic_core_unrecoverable);
4123 break;
4124 default:
4125 ql_log(ql_log_warn, base_vha, 0xb05f,
4126 "Unknow work-code=0x%x.\n", work_code);
4127 }
4128
4129 return;
4130}
4131
4132/* Work: Perform NIC Core Unrecoverable state handling */
4133void
4134qla83xx_nic_core_unrecoverable_work(struct work_struct *work)
4135{
4136 struct qla_hw_data *ha =
2ad1b67c 4137 container_of(work, struct qla_hw_data, nic_core_unrecoverable);
7d613ac6
SV		 4138 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4139 uint32_t dev_state = 0;
4140
4141 qla83xx_idc_lock(base_vha, 0);
4142 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4143 qla83xx_reset_ownership(base_vha);
4144 if (ha->flags.nic_core_reset_owner) {
4145 ha->flags.nic_core_reset_owner = 0;
4146 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
4147 QLA8XXX_DEV_FAILED);
4148 ql_log(ql_log_info, base_vha, 0xb060, "HW State: FAILED.\n");
4149 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
4150 }
4151 qla83xx_idc_unlock(base_vha, 0);
4152}
4153
4154/* Work: Execute IDC state handler */
4155void
4156qla83xx_idc_state_handler_work(struct work_struct *work)
4157{
4158 struct qla_hw_data *ha =
2ad1b67c 4159 container_of(work, struct qla_hw_data, idc_state_handler);
7d613ac6
SV		 4160 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4161 uint32_t dev_state = 0;
4162
4163 qla83xx_idc_lock(base_vha, 0);
4164 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4165 if (dev_state == QLA8XXX_DEV_FAILED ||
4166 dev_state == QLA8XXX_DEV_NEED_QUIESCENT)
4167 qla83xx_idc_state_handler(base_vha);
4168 qla83xx_idc_unlock(base_vha, 0);
4169}
4170
fa492630 4171static int
7d613ac6
SV		 4172qla83xx_check_nic_core_fw_alive(scsi_qla_host_t *base_vha)
4173{
4174 int rval = QLA_SUCCESS;
4175 unsigned long heart_beat_wait = jiffies + (1 * HZ);
4176 uint32_t heart_beat_counter1, heart_beat_counter2;
4177
4178 do {
4179 if (time_after(jiffies, heart_beat_wait)) {
4180 ql_dbg(ql_dbg_p3p, base_vha, 0xb07c,
4181 "Nic Core f/w is not alive.\n");
4182 rval = QLA_FUNCTION_FAILED;
4183 break;
4184 }
4185
4186 qla83xx_idc_lock(base_vha, 0);
4187 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
4188 &heart_beat_counter1);
4189 qla83xx_idc_unlock(base_vha, 0);
4190 msleep(100);
4191 qla83xx_idc_lock(base_vha, 0);
4192 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
4193 &heart_beat_counter2);
4194 qla83xx_idc_unlock(base_vha, 0);
4195 } while (heart_beat_counter1 == heart_beat_counter2);
4196
4197 return rval;
4198}
4199
4200/* Work: Perform NIC Core Reset handling */
4201void
4202qla83xx_nic_core_reset_work(struct work_struct *work)
4203{
4204 struct qla_hw_data *ha =
4205 container_of(work, struct qla_hw_data, nic_core_reset);
4206 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4207 uint32_t dev_state = 0;
4208
81178772
SK		 4209 if (IS_QLA2031(ha)) {
4210 if (qla2xxx_mctp_dump(base_vha) != QLA_SUCCESS)
4211 ql_log(ql_log_warn, base_vha, 0xb081,
4212 "Failed to dump mctp\n");
4213 return;
4214 }
4215
7d613ac6
SV		 4216 if (!ha->flags.nic_core_reset_hdlr_active) {
4217 if (qla83xx_check_nic_core_fw_alive(base_vha) == QLA_SUCCESS) {
4218 qla83xx_idc_lock(base_vha, 0);
4219 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE,
4220 &dev_state);
4221 qla83xx_idc_unlock(base_vha, 0);
4222 if (dev_state != QLA8XXX_DEV_NEED_RESET) {
4223 ql_dbg(ql_dbg_p3p, base_vha, 0xb07a,
4224 "Nic Core f/w is alive.\n");
4225 return;
4226 }
4227 }
4228
4229 ha->flags.nic_core_reset_hdlr_active = 1;
4230 if (qla83xx_nic_core_reset(base_vha)) {
4231 /* NIC Core reset failed. */
4232 ql_dbg(ql_dbg_p3p, base_vha, 0xb061,
4233 "NIC Core reset failed.\n");
4234 }
4235 ha->flags.nic_core_reset_hdlr_active = 0;
4236 }
4237}
4238
4239/* Work: Handle 8200 IDC aens */
4240void
4241qla83xx_service_idc_aen(struct work_struct *work)
4242{
4243 struct qla_hw_data *ha =
4244 container_of(work, struct qla_hw_data, idc_aen);
4245 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4246 uint32_t dev_state, idc_control;
4247
4248 qla83xx_idc_lock(base_vha, 0);
4249 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4250 qla83xx_rd_reg(base_vha, QLA83XX_IDC_CONTROL, &idc_control);
4251 qla83xx_idc_unlock(base_vha, 0);
4252 if (dev_state == QLA8XXX_DEV_NEED_RESET) {
4253 if (idc_control & QLA83XX_IDC_GRACEFUL_RESET) {
4254 ql_dbg(ql_dbg_p3p, base_vha, 0xb062,
4255 "Application requested NIC Core Reset.\n");
4256 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
4257 } else if (qla83xx_check_nic_core_fw_alive(base_vha) ==
4258 QLA_SUCCESS) {
4259 ql_dbg(ql_dbg_p3p, base_vha, 0xb07b,
4260 "Other protocol driver requested NIC Core Reset.\n");
4261 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
4262 }
4263 } else if (dev_state == QLA8XXX_DEV_FAILED ||
4264 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) {
4265 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
4266 }
4267}
4268
4269static void
4270qla83xx_wait_logic(void)
4271{
4272 int i;
4273
4274 /* Yield CPU */
4275 if (!in_interrupt()) {
4276 /*
4277 * Wait about 200ms before retrying again.
4278 * This controls the number of retries for single
4279 * lock operation.
4280 */
4281 msleep(100);
4282 schedule();
4283 } else {
4284 for (i = 0; i < 20; i++)
4285 cpu_relax(); /* This a nop instr on i386 */
4286 }
4287}
4288
fa492630 4289static int
7d613ac6
SV		 4290qla83xx_force_lock_recovery(scsi_qla_host_t *base_vha)
4291{
4292 int rval;
4293 uint32_t data;
4294 uint32_t idc_lck_rcvry_stage_mask = 0x3;
4295 uint32_t idc_lck_rcvry_owner_mask = 0x3c;
4296 struct qla_hw_data *ha = base_vha->hw;
6c315553
SK		 4297 ql_dbg(ql_dbg_p3p, base_vha, 0xb086,
4298 "Trying force recovery of the IDC lock.\n");
7d613ac6
SV		 4299
4300 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, &data);
4301 if (rval)
4302 return rval;
4303
4304 if ((data & idc_lck_rcvry_stage_mask) > 0) {
4305 return QLA_SUCCESS;
4306 } else {
4307 data = (IDC_LOCK_RECOVERY_STAGE1) | (ha->portnum << 2);
4308 rval = qla83xx_wr_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
4309 data);
4310 if (rval)
4311 return rval;
4312
4313 msleep(200);
4314
4315 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
4316 &data);
4317 if (rval)
4318 return rval;
4319
4320 if (((data & idc_lck_rcvry_owner_mask) >> 2) == ha->portnum) {
4321 data &= (IDC_LOCK_RECOVERY_STAGE2 |
4322 ~(idc_lck_rcvry_stage_mask));
4323 rval = qla83xx_wr_reg(base_vha,
4324 QLA83XX_IDC_LOCK_RECOVERY, data);
4325 if (rval)
4326 return rval;
4327
4328 /* Forcefully perform IDC UnLock */
4329 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK,
4330 &data);
4331 if (rval)
4332 return rval;
4333 /* Clear lock-id by setting 0xff */
4334 rval = qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
4335 0xff);
4336 if (rval)
4337 return rval;
4338 /* Clear lock-recovery by setting 0x0 */
4339 rval = qla83xx_wr_reg(base_vha,
4340 QLA83XX_IDC_LOCK_RECOVERY, 0x0);
4341 if (rval)
4342 return rval;
4343 } else
4344 return QLA_SUCCESS;
4345 }
4346
4347 return rval;
4348}
4349
fa492630 4350static int
7d613ac6
SV		 4351qla83xx_idc_lock_recovery(scsi_qla_host_t *base_vha)
4352{
4353 int rval = QLA_SUCCESS;
4354 uint32_t o_drv_lockid, n_drv_lockid;
4355 unsigned long lock_recovery_timeout;
4356
4357 lock_recovery_timeout = jiffies + QLA83XX_MAX_LOCK_RECOVERY_WAIT;
4358retry_lockid:
4359 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &o_drv_lockid);
4360 if (rval)
4361 goto exit;
4362
4363 /* MAX wait time before forcing IDC Lock recovery = 2 secs */
4364 if (time_after_eq(jiffies, lock_recovery_timeout)) {
4365 if (qla83xx_force_lock_recovery(base_vha) == QLA_SUCCESS)
4366 return QLA_SUCCESS;
4367 else
4368 return QLA_FUNCTION_FAILED;
4369 }
4370
4371 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &n_drv_lockid);
4372 if (rval)
4373 goto exit;
4374
4375 if (o_drv_lockid == n_drv_lockid) {
4376 qla83xx_wait_logic();
4377 goto retry_lockid;
4378 } else
4379 return QLA_SUCCESS;
4380
4381exit:
4382 return rval;
4383}
4384
4385void
4386qla83xx_idc_lock(scsi_qla_host_t *base_vha, uint16_t requester_id)
4387{
4388 uint16_t options = (requester_id << 15) | BIT_6;
4389 uint32_t data;
6c315553 4390 uint32_t lock_owner;
7d613ac6
SV		 4391 struct qla_hw_data *ha = base_vha->hw;
4392
4393 /* IDC-lock implementation using driver-lock/lock-id remote registers */
4394retry_lock:
4395 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCK, &data)
4396 == QLA_SUCCESS) {
4397 if (data) {
4398 /* Setting lock-id to our function-number */
4399 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
4400 ha->portnum);
4401 } else {
6c315553
SK		 4402 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID,
4403 &lock_owner);
7d613ac6 4404 ql_dbg(ql_dbg_p3p, base_vha, 0xb063,
6c315553
SK		 4405 "Failed to acquire IDC lock, acquired by %d, "
4406 "retrying...\n", lock_owner);
7d613ac6
SV		 4407
4408 /* Retry/Perform IDC-Lock recovery */
4409 if (qla83xx_idc_lock_recovery(base_vha)
4410 == QLA_SUCCESS) {
4411 qla83xx_wait_logic();
4412 goto retry_lock;
4413 } else
4414 ql_log(ql_log_warn, base_vha, 0xb075,
4415 "IDC Lock recovery FAILED.\n");
4416 }
4417
4418 }
4419
4420 return;
4421
4422 /* XXX: IDC-lock implementation using access-control mbx */
4423retry_lock2:
4424 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
4425 ql_dbg(ql_dbg_p3p, base_vha, 0xb072,
4426 "Failed to acquire IDC lock. retrying...\n");
4427 /* Retry/Perform IDC-Lock recovery */
4428 if (qla83xx_idc_lock_recovery(base_vha) == QLA_SUCCESS) {
4429 qla83xx_wait_logic();
4430 goto retry_lock2;
4431 } else
4432 ql_log(ql_log_warn, base_vha, 0xb076,
4433 "IDC Lock recovery FAILED.\n");
4434 }
4435
4436 return;
4437}
4438
4439void
4440qla83xx_idc_unlock(scsi_qla_host_t *base_vha, uint16_t requester_id)
4441{
4442 uint16_t options = (requester_id << 15) | BIT_7, retry;
4443 uint32_t data;
4444 struct qla_hw_data *ha = base_vha->hw;
4445
4446 /* IDC-unlock implementation using driver-unlock/lock-id
4447 * remote registers
4448 */
4449 retry = 0;
4450retry_unlock:
4451 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &data)
4452 == QLA_SUCCESS) {
4453 if (data == ha->portnum) {
4454 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, &data);
4455 /* Clearing lock-id by setting 0xff */
4456 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 0xff);
4457 } else if (retry < 10) {
4458 /* SV: XXX: IDC unlock retrying needed here? */
4459
4460 /* Retry for IDC-unlock */
4461 qla83xx_wait_logic();
4462 retry++;
4463 ql_dbg(ql_dbg_p3p, base_vha, 0xb064,
4464 "Failed to release IDC lock, retyring=%d\n", retry);
4465 goto retry_unlock;
4466 }
4467 } else if (retry < 10) {
4468 /* Retry for IDC-unlock */
4469 qla83xx_wait_logic();
4470 retry++;
4471 ql_dbg(ql_dbg_p3p, base_vha, 0xb065,
4472 "Failed to read drv-lockid, retyring=%d\n", retry);
4473 goto retry_unlock;
4474 }
4475
4476 return;
4477
4478 /* XXX: IDC-unlock implementation using access-control mbx */
4479 retry = 0;
4480retry_unlock2:
4481 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
4482 if (retry < 10) {
4483 /* Retry for IDC-unlock */
4484 qla83xx_wait_logic();
4485 retry++;
4486 ql_dbg(ql_dbg_p3p, base_vha, 0xb066,
4487 "Failed to release IDC lock, retyring=%d\n", retry);
4488 goto retry_unlock2;
4489 }
4490 }
4491
4492 return;
4493}
4494
4495int
4496__qla83xx_set_drv_presence(scsi_qla_host_t *vha)
4497{
4498 int rval = QLA_SUCCESS;
4499 struct qla_hw_data *ha = vha->hw;
4500 uint32_t drv_presence;
4501
4502 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
4503 if (rval == QLA_SUCCESS) {
4504 drv_presence |= (1 << ha->portnum);
4505 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
4506 drv_presence);
4507 }
4508
4509 return rval;
4510}
4511
4512int
4513qla83xx_set_drv_presence(scsi_qla_host_t *vha)
4514{
4515 int rval = QLA_SUCCESS;
4516
4517 qla83xx_idc_lock(vha, 0);
4518 rval = __qla83xx_set_drv_presence(vha);
4519 qla83xx_idc_unlock(vha, 0);
4520
4521 return rval;
4522}
4523
4524int
4525__qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
4526{
4527 int rval = QLA_SUCCESS;
4528 struct qla_hw_data *ha = vha->hw;
4529 uint32_t drv_presence;
4530
4531 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
4532 if (rval == QLA_SUCCESS) {
4533 drv_presence &= ~(1 << ha->portnum);
4534 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
4535 drv_presence);
4536 }
4537
4538 return rval;
4539}
4540
4541int
4542qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
4543{
4544 int rval = QLA_SUCCESS;
4545
4546 qla83xx_idc_lock(vha, 0);
4547 rval = __qla83xx_clear_drv_presence(vha);
4548 qla83xx_idc_unlock(vha, 0);
4549
4550 return rval;
4551}
4552
fa492630 4553static void
7d613ac6
SV		 4554qla83xx_need_reset_handler(scsi_qla_host_t *vha)
4555{
4556 struct qla_hw_data *ha = vha->hw;
4557 uint32_t drv_ack, drv_presence;
4558 unsigned long ack_timeout;
4559
4560 /* Wait for IDC ACK from all functions (DRV-ACK == DRV-PRESENCE) */
4561 ack_timeout = jiffies + (ha->fcoe_reset_timeout * HZ);
4562 while (1) {
4563 qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
4564 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
807fb6d8 4565 if ((drv_ack & drv_presence) == drv_presence)
7d613ac6
SV		 4566 break;
4567
4568 if (time_after_eq(jiffies, ack_timeout)) {
4569 ql_log(ql_log_warn, vha, 0xb067,
4570 "RESET ACK TIMEOUT! drv_presence=0x%x "
4571 "drv_ack=0x%x\n", drv_presence, drv_ack);
4572 /*
4573 * The function(s) which did not ack in time are forced
4574 * to withdraw any further participation in the IDC
4575 * reset.
4576 */
4577 if (drv_ack != drv_presence)
4578 qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
4579 drv_ack);
4580 break;
4581 }
4582
4583 qla83xx_idc_unlock(vha, 0);
4584 msleep(1000);
4585 qla83xx_idc_lock(vha, 0);
4586 }
4587
4588 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_COLD);
4589 ql_log(ql_log_info, vha, 0xb068, "HW State: COLD/RE-INIT.\n");
4590}
4591
fa492630 4592static int
7d613ac6
SV		 4593qla83xx_device_bootstrap(scsi_qla_host_t *vha)
4594{
4595 int rval = QLA_SUCCESS;
4596 uint32_t idc_control;
4597
4598 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_INITIALIZING);
4599 ql_log(ql_log_info, vha, 0xb069, "HW State: INITIALIZING.\n");
4600
4601 /* Clearing IDC-Control Graceful-Reset Bit before resetting f/w */
4602 __qla83xx_get_idc_control(vha, &idc_control);
4603 idc_control &= ~QLA83XX_IDC_GRACEFUL_RESET;
4604 __qla83xx_set_idc_control(vha, 0);
4605
4606 qla83xx_idc_unlock(vha, 0);
4607 rval = qla83xx_restart_nic_firmware(vha);
4608 qla83xx_idc_lock(vha, 0);
4609
4610 if (rval != QLA_SUCCESS) {
4611 ql_log(ql_log_fatal, vha, 0xb06a,
4612 "Failed to restart NIC f/w.\n");
4613 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_FAILED);
4614 ql_log(ql_log_info, vha, 0xb06b, "HW State: FAILED.\n");
4615 } else {
4616 ql_dbg(ql_dbg_p3p, vha, 0xb06c,
4617 "Success in restarting nic f/w.\n");
4618 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_READY);
4619 ql_log(ql_log_info, vha, 0xb06d, "HW State: READY.\n");
4620 }
4621
4622 return rval;
4623}
4624
4625/* Assumes idc_lock always held on entry */
4626int
4627qla83xx_idc_state_handler(scsi_qla_host_t *base_vha)
4628{
4629 struct qla_hw_data *ha = base_vha->hw;
4630 int rval = QLA_SUCCESS;
4631 unsigned long dev_init_timeout;
4632 uint32_t dev_state;
4633
4634 /* Wait for MAX-INIT-TIMEOUT for the device to go ready */
4635 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ);
4636
4637 while (1) {
4638
4639 if (time_after_eq(jiffies, dev_init_timeout)) {
4640 ql_log(ql_log_warn, base_vha, 0xb06e,
4641 "Initialization TIMEOUT!\n");
4642 /* Init timeout. Disable further NIC Core
4643 * communication.
4644 */
4645 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
4646 QLA8XXX_DEV_FAILED);
4647 ql_log(ql_log_info, base_vha, 0xb06f,
4648 "HW State: FAILED.\n");
4649 }
4650
4651 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4652 switch (dev_state) {
4653 case QLA8XXX_DEV_READY:
4654 if (ha->flags.nic_core_reset_owner)
4655 qla83xx_idc_audit(base_vha,
4656 IDC_AUDIT_COMPLETION);
4657 ha->flags.nic_core_reset_owner = 0;
4658 ql_dbg(ql_dbg_p3p, base_vha, 0xb070,
4659 "Reset_owner reset by 0x%x.\n",
4660 ha->portnum);
4661 goto exit;
4662 case QLA8XXX_DEV_COLD:
4663 if (ha->flags.nic_core_reset_owner)
4664 rval = qla83xx_device_bootstrap(base_vha);
4665 else {
4666 /* Wait for AEN to change device-state */
4667 qla83xx_idc_unlock(base_vha, 0);
4668 msleep(1000);
4669 qla83xx_idc_lock(base_vha, 0);
4670 }
4671 break;
4672 case QLA8XXX_DEV_INITIALIZING:
4673 /* Wait for AEN to change device-state */
4674 qla83xx_idc_unlock(base_vha, 0);
4675 msleep(1000);
4676 qla83xx_idc_lock(base_vha, 0);
4677 break;
4678 case QLA8XXX_DEV_NEED_RESET:
4679 if (!ql2xdontresethba && ha->flags.nic_core_reset_owner)
4680 qla83xx_need_reset_handler(base_vha);
4681 else {
4682 /* Wait for AEN to change device-state */
4683 qla83xx_idc_unlock(base_vha, 0);
4684 msleep(1000);
4685 qla83xx_idc_lock(base_vha, 0);
4686 }
4687 /* reset timeout value after need reset handler */
4688 dev_init_timeout = jiffies +
4689 (ha->fcoe_dev_init_timeout * HZ);
4690 break;
4691 case QLA8XXX_DEV_NEED_QUIESCENT:
4692 /* XXX: DEBUG for now */
4693 qla83xx_idc_unlock(base_vha, 0);
4694 msleep(1000);
4695 qla83xx_idc_lock(base_vha, 0);
4696 break;
4697 case QLA8XXX_DEV_QUIESCENT:
4698 /* XXX: DEBUG for now */
4699 if (ha->flags.quiesce_owner)
4700 goto exit;
4701
4702 qla83xx_idc_unlock(base_vha, 0);
4703 msleep(1000);
4704 qla83xx_idc_lock(base_vha, 0);
4705 dev_init_timeout = jiffies +
4706 (ha->fcoe_dev_init_timeout * HZ);
4707 break;
4708 case QLA8XXX_DEV_FAILED:
4709 if (ha->flags.nic_core_reset_owner)
4710 qla83xx_idc_audit(base_vha,
4711 IDC_AUDIT_COMPLETION);
4712 ha->flags.nic_core_reset_owner = 0;
4713 __qla83xx_clear_drv_presence(base_vha);
4714 qla83xx_idc_unlock(base_vha, 0);
4715 qla8xxx_dev_failed_handler(base_vha);
4716 rval = QLA_FUNCTION_FAILED;
4717 qla83xx_idc_lock(base_vha, 0);
4718 goto exit;
4719 case QLA8XXX_BAD_VALUE:
4720 qla83xx_idc_unlock(base_vha, 0);
4721 msleep(1000);
4722 qla83xx_idc_lock(base_vha, 0);
4723 break;
4724 default:
4725 ql_log(ql_log_warn, base_vha, 0xb071,
4726 "Unknow Device State: %x.\n", dev_state);
4727 qla83xx_idc_unlock(base_vha, 0);
4728 qla8xxx_dev_failed_handler(base_vha);
4729 rval = QLA_FUNCTION_FAILED;
4730 qla83xx_idc_lock(base_vha, 0);
4731 goto exit;
4732 }
4733 }
4734
4735exit:
4736 return rval;
4737}
4738
1da177e4
LT		 4739/**************************************************************************
4740* qla2x00_do_dpc
4741* This kernel thread is a task that is schedule by the interrupt handler
4742* to perform the background processing for interrupts.
4743*
4744* Notes:
4745* This task always run in the context of a kernel thread. It
4746* is kick-off by the driver's detect code and starts up
4747* up one per adapter. It immediately goes to sleep and waits for
4748* some fibre event. When either the interrupt handler or
4749* the timer routine detects a event it will one of the task
4750* bits then wake us up.
4751**************************************************************************/
4752static int
4753qla2x00_do_dpc(void *data)
4754{
2c3dfe3f 4755 int rval;
e315cd28
AC		 4756 scsi_qla_host_t *base_vha;
4757 struct qla_hw_data *ha;
1da177e4 4758
e315cd28
AC		 4759 ha = (struct qla_hw_data *)data;
4760 base_vha = pci_get_drvdata(ha->pdev);
1da177e4 4761
1da177e4
LT		 4762 set_user_nice(current, -20);
4763
563585ec 4764 set_current_state(TASK_INTERRUPTIBLE);
39a11240 4765 while (!kthread_should_stop()) {
7c3df132
SK		 4766 ql_dbg(ql_dbg_dpc, base_vha, 0x4000,
4767 "DPC handler sleeping.\n");
1da177e4 4768
39a11240
CH		 4769 schedule();
4770 __set_current_state(TASK_RUNNING);
1da177e4 4771
c142caf0
AV		 4772 if (!base_vha->flags.init_done || ha->flags.mbox_busy)
4773 goto end_loop;
1da177e4 4774
85880801 4775 if (ha->flags.eeh_busy) {
7c3df132
SK		 4776 ql_dbg(ql_dbg_dpc, base_vha, 0x4003,
4777 "eeh_busy=%d.\n", ha->flags.eeh_busy);
c142caf0 4778 goto end_loop;
85880801
AV		 4779 }
4780
1da177e4
LT		 4781 ha->dpc_active = 1;
4782
5f28d2d7
SK		 4783 ql_dbg(ql_dbg_dpc + ql_dbg_verbose, base_vha, 0x4001,
4784 "DPC handler waking up, dpc_flags=0x%lx.\n",
4785 base_vha->dpc_flags);
1da177e4 4786
e315cd28 4787 qla2x00_do_work(base_vha);
0971de7f 4788
7ec0effd
AD		 4789 if (IS_P3P_TYPE(ha)) {
4790 if (IS_QLA8044(ha)) {
4791 if (test_and_clear_bit(ISP_UNRECOVERABLE,
4792 &base_vha->dpc_flags)) {
4793 qla8044_idc_lock(ha);
4794 qla8044_wr_direct(base_vha,
4795 QLA8044_CRB_DEV_STATE_INDEX,
4796 QLA8XXX_DEV_FAILED);
4797 qla8044_idc_unlock(ha);
4798 ql_log(ql_log_info, base_vha, 0x4004,
4799 "HW State: FAILED.\n");
4800 qla8044_device_state_handler(base_vha);
4801 continue;
4802 }
4803
4804 } else {
4805 if (test_and_clear_bit(ISP_UNRECOVERABLE,
4806 &base_vha->dpc_flags)) {
4807 qla82xx_idc_lock(ha);
4808 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
4809 QLA8XXX_DEV_FAILED);
4810 qla82xx_idc_unlock(ha);
4811 ql_log(ql_log_info, base_vha, 0x0151,
4812 "HW State: FAILED.\n");
4813 qla82xx_device_state_handler(base_vha);
4814 continue;
4815 }
a9083016
GM		 4816 }
4817
4818 if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED,
4819 &base_vha->dpc_flags)) {
4820
7c3df132
SK		 4821 ql_dbg(ql_dbg_dpc, base_vha, 0x4005,
4822 "FCoE context reset scheduled.\n");
a9083016
GM		 4823 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
4824 &base_vha->dpc_flags))) {
4825 if (qla82xx_fcoe_ctx_reset(base_vha)) {
4826 /* FCoE-ctx reset failed.
4827 * Escalate to chip-reset
4828 */
4829 set_bit(ISP_ABORT_NEEDED,
4830 &base_vha->dpc_flags);
4831 }
4832 clear_bit(ABORT_ISP_ACTIVE,
4833 &base_vha->dpc_flags);
4834 }
4835
7c3df132
SK		 4836 ql_dbg(ql_dbg_dpc, base_vha, 0x4006,
4837 "FCoE context reset end.\n");
a9083016 4838 }
8ae6d9c7
GM		 4839 } else if (IS_QLAFX00(ha)) {
4840 if (test_and_clear_bit(ISP_UNRECOVERABLE,
4841 &base_vha->dpc_flags)) {
4842 ql_dbg(ql_dbg_dpc, base_vha, 0x4020,
4843 "Firmware Reset Recovery\n");
4844 if (qlafx00_reset_initialize(base_vha)) {
4845 /* Failed. Abort isp later. */
4846 if (!test_bit(UNLOADING,
4847 &base_vha->dpc_flags))
4848 set_bit(ISP_UNRECOVERABLE,
4849 &base_vha->dpc_flags);
4850 ql_dbg(ql_dbg_dpc, base_vha,
4851 0x4021,
4852 "Reset Recovery Failed\n");
4853 }
4854 }
4855
4856 if (test_and_clear_bit(FX00_TARGET_SCAN,
4857 &base_vha->dpc_flags)) {
4858 ql_dbg(ql_dbg_dpc, base_vha, 0x4022,
4859 "ISPFx00 Target Scan scheduled\n");
4860 if (qlafx00_rescan_isp(base_vha)) {
4861 if (!test_bit(UNLOADING,
4862 &base_vha->dpc_flags))
4863 set_bit(ISP_UNRECOVERABLE,
4864 &base_vha->dpc_flags);
4865 ql_dbg(ql_dbg_dpc, base_vha, 0x401e,
4866 "ISPFx00 Target Scan Failed\n");
4867 }
4868 ql_dbg(ql_dbg_dpc, base_vha, 0x401f,
4869 "ISPFx00 Target Scan End\n");
4870 }
a9083016
GM		 4871 }
4872
e315cd28
AC		 4873 if (test_and_clear_bit(ISP_ABORT_NEEDED,
4874 &base_vha->dpc_flags)) {
1da177e4 4875
7c3df132
SK		 4876 ql_dbg(ql_dbg_dpc, base_vha, 0x4007,
4877 "ISP abort scheduled.\n");
1da177e4 4878 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
e315cd28 4879 &base_vha->dpc_flags))) {
1da177e4 4880
a9083016 4881 if (ha->isp_ops->abort_isp(base_vha)) {
1da177e4
LT		 4882 /* failed. retry later */
4883 set_bit(ISP_ABORT_NEEDED,
e315cd28 4884 &base_vha->dpc_flags);
99363ef8 4885 }
e315cd28
AC		 4886 clear_bit(ABORT_ISP_ACTIVE,
4887 &base_vha->dpc_flags);
99363ef8
SJ		 4888 }
4889
7c3df132
SK		 4890 ql_dbg(ql_dbg_dpc, base_vha, 0x4008,
4891 "ISP abort end.\n");
1da177e4
LT		 4892 }
4893
a394aac8
DJ		 4894 if (test_and_clear_bit(FCPORT_UPDATE_NEEDED,
4895 &base_vha->dpc_flags)) {
e315cd28 4896 qla2x00_update_fcports(base_vha);
c9c5ced9 4897 }
d97994dc 4898
2d70c103
NB		 4899 if (test_bit(SCR_PENDING, &base_vha->dpc_flags)) {
4900 int ret;
4901 ret = qla2x00_send_change_request(base_vha, 0x3, 0);
4902 if (ret != QLA_SUCCESS)
4903 ql_log(ql_log_warn, base_vha, 0x121,
4904 "Failed to enable receiving of RSCN "
4905 "requests: 0x%x.\n", ret);
4906 clear_bit(SCR_PENDING, &base_vha->dpc_flags);
4907 }
4908
8ae6d9c7
GM		 4909 if (IS_QLAFX00(ha))
4910 goto loop_resync_check;
4911
579d12b5 4912 if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) {
7c3df132
SK		 4913 ql_dbg(ql_dbg_dpc, base_vha, 0x4009,
4914 "Quiescence mode scheduled.\n");
7ec0effd
AD		 4915 if (IS_P3P_TYPE(ha)) {
4916 if (IS_QLA82XX(ha))
4917 qla82xx_device_state_handler(base_vha);
4918 if (IS_QLA8044(ha))
4919 qla8044_device_state_handler(base_vha);
8fcd6b8b
CD		 4920 clear_bit(ISP_QUIESCE_NEEDED,
4921 &base_vha->dpc_flags);
4922 if (!ha->flags.quiesce_owner) {
4923 qla2x00_perform_loop_resync(base_vha);
7ec0effd
AD		 4924 if (IS_QLA82XX(ha)) {
4925 qla82xx_idc_lock(ha);
4926 qla82xx_clear_qsnt_ready(
4927 base_vha);
4928 qla82xx_idc_unlock(ha);
4929 } else if (IS_QLA8044(ha)) {
4930 qla8044_idc_lock(ha);
4931 qla8044_clear_qsnt_ready(
4932 base_vha);
4933 qla8044_idc_unlock(ha);
4934 }
8fcd6b8b
CD		 4935 }
4936 } else {
4937 clear_bit(ISP_QUIESCE_NEEDED,
4938 &base_vha->dpc_flags);
4939 qla2x00_quiesce_io(base_vha);
579d12b5 4940 }
7c3df132
SK		 4941 ql_dbg(ql_dbg_dpc, base_vha, 0x400a,
4942 "Quiescence mode end.\n");
579d12b5
SK		 4943 }
4944
e315cd28 4945 if (test_and_clear_bit(RESET_MARKER_NEEDED,
8ae6d9c7 4946 &base_vha->dpc_flags) &&
e315cd28 4947 (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) {
1da177e4 4948
7c3df132
SK		 4949 ql_dbg(ql_dbg_dpc, base_vha, 0x400b,
4950 "Reset marker scheduled.\n");
e315cd28
AC		 4951 qla2x00_rst_aen(base_vha);
4952 clear_bit(RESET_ACTIVE, &base_vha->dpc_flags);
7c3df132
SK		 4953 ql_dbg(ql_dbg_dpc, base_vha, 0x400c,
4954 "Reset marker end.\n");
1da177e4
LT		 4955 }
4956
4957 /* Retry each device up to login retry count */
e315cd28
AC		 4958 if ((test_and_clear_bit(RELOGIN_NEEDED,
4959 &base_vha->dpc_flags)) &&
4960 !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) &&
4961 atomic_read(&base_vha->loop_state) != LOOP_DOWN) {
1da177e4 4962
7c3df132
SK		 4963 ql_dbg(ql_dbg_dpc, base_vha, 0x400d,
4964 "Relogin scheduled.\n");
e315cd28 4965 qla2x00_relogin(base_vha);
7c3df132
SK		 4966 ql_dbg(ql_dbg_dpc, base_vha, 0x400e,
4967 "Relogin end.\n");
1da177e4 4968 }
8ae6d9c7 4969loop_resync_check:
e315cd28 4970 if (test_and_clear_bit(LOOP_RESYNC_NEEDED,
8ae6d9c7 4971 &base_vha->dpc_flags)) {
1da177e4 4972
7c3df132
SK		 4973 ql_dbg(ql_dbg_dpc, base_vha, 0x400f,
4974 "Loop resync scheduled.\n");
1da177e4
LT		 4975
4976 if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE,
e315cd28 4977 &base_vha->dpc_flags))) {
1da177e4 4978
e315cd28 4979 rval = qla2x00_loop_resync(base_vha);
1da177e4 4980
e315cd28
AC		 4981 clear_bit(LOOP_RESYNC_ACTIVE,
4982 &base_vha->dpc_flags);
1da177e4
LT		 4983 }
4984
7c3df132
SK		 4985 ql_dbg(ql_dbg_dpc, base_vha, 0x4010,
4986 "Loop resync end.\n");
1da177e4
LT		 4987 }
4988
8ae6d9c7
GM		 4989 if (IS_QLAFX00(ha))
4990 goto intr_on_check;
4991
e315cd28
AC		 4992 if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) &&
4993 atomic_read(&base_vha->loop_state) == LOOP_READY) {
4994 clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags);
4995 qla2xxx_flash_npiv_conf(base_vha);
272976ca
AV		 4996 }
4997
3c290d0b
CD		 4998 if (test_and_clear_bit(HOST_RAMP_DOWN_QUEUE_DEPTH,
4999 &base_vha->dpc_flags)) {
5000 /* Prevents simultaneous ramp up and down */
5001 clear_bit(HOST_RAMP_UP_QUEUE_DEPTH,
5002 &base_vha->dpc_flags);
5003 qla2x00_host_ramp_down_queuedepth(base_vha);
5004 }
5005
5006 if (test_and_clear_bit(HOST_RAMP_UP_QUEUE_DEPTH,
5007 &base_vha->dpc_flags))
5008 qla2x00_host_ramp_up_queuedepth(base_vha);
8ae6d9c7 5009intr_on_check:
1da177e4 5010 if (!ha->interrupts_on)
fd34f556 5011 ha->isp_ops->enable_intrs(ha);
1da177e4 5012
e315cd28
AC		 5013 if (test_and_clear_bit(BEACON_BLINK_NEEDED,
5014 &base_vha->dpc_flags))
5015 ha->isp_ops->beacon_blink(base_vha);
f6df144c 5016
8ae6d9c7
GM		 5017 if (!IS_QLAFX00(ha))
5018 qla2x00_do_dpc_all_vps(base_vha);
2c3dfe3f 5019
1da177e4 5020 ha->dpc_active = 0;
c142caf0 5021end_loop:
563585ec 5022 set_current_state(TASK_INTERRUPTIBLE);
1da177e4 5023 } /* End of while(1) */
563585ec 5024 __set_current_state(TASK_RUNNING);
1da177e4 5025
7c3df132
SK		 5026 ql_dbg(ql_dbg_dpc, base_vha, 0x4011,
5027 "DPC handler exiting.\n");
1da177e4
LT		 5028
5029 /*
5030 * Make sure that nobody tries to wake us up again.
5031 */
1da177e4
LT		 5032 ha->dpc_active = 0;
5033
ac280b67
AV		 5034 /* Cleanup any residual CTX SRBs. */
5035 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
5036
39a11240
CH		 5037 return 0;
5038}
5039
5040void
e315cd28 5041qla2xxx_wake_dpc(struct scsi_qla_host *vha)
39a11240 5042{
e315cd28 5043 struct qla_hw_data *ha = vha->hw;
c795c1e4
AV		 5044 struct task_struct *t = ha->dpc_thread;
5045
e315cd28 5046 if (!test_bit(UNLOADING, &vha->dpc_flags) && t)
c795c1e4 5047 wake_up_process(t);
1da177e4
LT		 5048}
5049
1da177e4
LT		 5050/*
5051* qla2x00_rst_aen
5052* Processes asynchronous reset.
5053*
5054* Input:
5055* ha = adapter block pointer.
5056*/
5057static void
e315cd28 5058qla2x00_rst_aen(scsi_qla_host_t *vha)
1da177e4 5059{
e315cd28
AC		 5060 if (vha->flags.online && !vha->flags.reset_active &&
5061 !atomic_read(&vha->loop_down_timer) &&
5062 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) {
1da177e4 5063 do {
e315cd28 5064 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
1da177e4
LT		 5065
5066 /*
5067 * Issue marker command only when we are going to start
5068 * the I/O.
5069 */
e315cd28
AC		 5070 vha->marker_needed = 1;
5071 } while (!atomic_read(&vha->loop_down_timer) &&
5072 (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)));
1da177e4
LT		 5073 }
5074}
5075
1da177e4
LT		 5076/**************************************************************************
5077* qla2x00_timer
5078*
5079* Description:
5080* One second timer
5081*
5082* Context: Interrupt
5083***************************************************************************/
2c3dfe3f 5084void
e315cd28 5085qla2x00_timer(scsi_qla_host_t *vha)
1da177e4 5086{
1da177e4 5087 unsigned long cpu_flags = 0;
1da177e4
LT		 5088 int start_dpc = 0;
5089 int index;
5090 srb_t *sp;
85880801 5091 uint16_t w;
e315cd28 5092 struct qla_hw_data *ha = vha->hw;
73208dfd 5093 struct req_que *req;
85880801 5094
a5b36321 5095 if (ha->flags.eeh_busy) {
7c3df132
SK		 5096 ql_dbg(ql_dbg_timer, vha, 0x6000,
5097 "EEH = %d, restarting timer.\n",
5098 ha->flags.eeh_busy);
a5b36321
LC		 5099 qla2x00_restart_timer(vha, WATCH_INTERVAL);
5100 return;
5101 }
5102
85880801
AV		 5103 /* Hardware read to raise pending EEH errors during mailbox waits. */
5104 if (!pci_channel_offline(ha->pdev))
5105 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w);
1da177e4 5106
cefcaba6 5107 /* Make sure qla82xx_watchdog is run only for physical port */
7ec0effd 5108 if (!vha->vp_idx && IS_P3P_TYPE(ha)) {
579d12b5
SK		 5109 if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags))
5110 start_dpc++;
7ec0effd
AD		 5111 if (IS_QLA82XX(ha))
5112 qla82xx_watchdog(vha);
5113 else if (IS_QLA8044(ha))
5114 qla8044_watchdog(vha);
579d12b5
SK		 5115 }
5116
8ae6d9c7
GM		 5117 if (!vha->vp_idx && IS_QLAFX00(ha))
5118 qlafx00_timer_routine(vha);
5119
1da177e4 5120 /* Loop down handler. */
e315cd28 5121 if (atomic_read(&vha->loop_down_timer) > 0 &&
8f7daead
GM		 5122 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) &&
5123 !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags))
e315cd28 5124 && vha->flags.online) {
1da177e4 5125
e315cd28
AC		 5126 if (atomic_read(&vha->loop_down_timer) ==
5127 vha->loop_down_abort_time) {
1da177e4 5128
7c3df132
SK		 5129 ql_log(ql_log_info, vha, 0x6008,
5130 "Loop down - aborting the queues before time expires.\n");
1da177e4 5131
e315cd28
AC		 5132 if (!IS_QLA2100(ha) && vha->link_down_timeout)
5133 atomic_set(&vha->loop_state, LOOP_DEAD);
1da177e4 5134
f08b7251
AV		 5135 /*
5136 * Schedule an ISP abort to return any FCP2-device
5137 * commands.
5138 */
2c3dfe3f 5139 /* NPIV - scan physical port only */
e315cd28 5140 if (!vha->vp_idx) {
2c3dfe3f
SJ		 5141 spin_lock_irqsave(&ha->hardware_lock,
5142 cpu_flags);
73208dfd 5143 req = ha->req_q_map[0];
2c3dfe3f 5144 for (index = 1;
8d93f550 5145 index < req->num_outstanding_cmds;
2c3dfe3f
SJ		 5146 index++) {
5147 fc_port_t *sfcp;
5148
e315cd28 5149 sp = req->outstanding_cmds[index];
2c3dfe3f
SJ		 5150 if (!sp)
5151 continue;
9ba56b95 5152 if (sp->type != SRB_SCSI_CMD)
cf53b069 5153 continue;
2c3dfe3f 5154 sfcp = sp->fcport;
f08b7251 5155 if (!(sfcp->flags & FCF_FCP2_DEVICE))
2c3dfe3f 5156 continue;
bdf79621 5157
8f7daead
GM		 5158 if (IS_QLA82XX(ha))
5159 set_bit(FCOE_CTX_RESET_NEEDED,
5160 &vha->dpc_flags);
5161 else
5162 set_bit(ISP_ABORT_NEEDED,
e315cd28 5163 &vha->dpc_flags);
2c3dfe3f
SJ		 5164 break;
5165 }
5166 spin_unlock_irqrestore(&ha->hardware_lock,
e315cd28 5167 cpu_flags);
1da177e4 5168 }
1da177e4
LT		 5169 start_dpc++;
5170 }
5171
5172 /* if the loop has been down for 4 minutes, reinit adapter */
e315cd28 5173 if (atomic_dec_and_test(&vha->loop_down_timer) != 0) {
0d6e61bc 5174 if (!(vha->device_flags & DFLG_NO_CABLE)) {
7c3df132 5175 ql_log(ql_log_warn, vha, 0x6009,
1da177e4
LT		 5176 "Loop down - aborting ISP.\n");
5177
8f7daead
GM		 5178 if (IS_QLA82XX(ha))
5179 set_bit(FCOE_CTX_RESET_NEEDED,
5180 &vha->dpc_flags);
5181 else
5182 set_bit(ISP_ABORT_NEEDED,
5183 &vha->dpc_flags);
1da177e4
LT		 5184 }
5185 }
7c3df132
SK		 5186 ql_dbg(ql_dbg_timer, vha, 0x600a,
5187 "Loop down - seconds remaining %d.\n",
5188 atomic_read(&vha->loop_down_timer));
1da177e4
LT		 5189 }
5190
cefcaba6
SK		 5191 /* Check if beacon LED needs to be blinked for physical host only */
5192 if (!vha->vp_idx && (ha->beacon_blink_led == 1)) {
999916dc 5193 /* There is no beacon_blink function for ISP82xx */
7ec0effd 5194 if (!IS_P3P_TYPE(ha)) {
999916dc
SK		 5195 set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags);
5196 start_dpc++;
5197 }
f6df144c 5198 }
5199
550bf57d 5200 /* Process any deferred work. */
e315cd28 5201 if (!list_empty(&vha->work_list))
550bf57d
AV		 5202 start_dpc++;
5203
1da177e4 5204 /* Schedule the DPC routine if needed */
e315cd28
AC		 5205 if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) ||
5206 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) ||
5207 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags) ||
1da177e4 5208 start_dpc ||
e315cd28
AC		 5209 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) ||
5210 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) ||
a9083016
GM		 5211 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) ||
5212 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) ||
e315cd28 5213 test_bit(VP_DPC_NEEDED, &vha->dpc_flags) ||
3c290d0b
CD		 5214 test_bit(RELOGIN_NEEDED, &vha->dpc_flags) ||
5215 test_bit(HOST_RAMP_DOWN_QUEUE_DEPTH, &vha->dpc_flags) ||
5216 test_bit(HOST_RAMP_UP_QUEUE_DEPTH, &vha->dpc_flags))) {
7c3df132
SK		 5217 ql_dbg(ql_dbg_timer, vha, 0x600b,
5218 "isp_abort_needed=%d loop_resync_needed=%d "
5219 "fcport_update_needed=%d start_dpc=%d "
5220 "reset_marker_needed=%d",
5221 test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags),
5222 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags),
5223 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags),
5224 start_dpc,
5225 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags));
5226 ql_dbg(ql_dbg_timer, vha, 0x600c,
5227 "beacon_blink_needed=%d isp_unrecoverable=%d "
5228 "fcoe_ctx_reset_needed=%d vp_dpc_needed=%d "
3c290d0b
CD		 5229 "relogin_needed=%d, host_ramp_down_needed=%d "
5230 "host_ramp_up_needed=%d.\n",
7c3df132
SK		 5231 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags),
5232 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags),
5233 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags),
5234 test_bit(VP_DPC_NEEDED, &vha->dpc_flags),
3c290d0b
CD		 5235 test_bit(RELOGIN_NEEDED, &vha->dpc_flags),
5236 test_bit(HOST_RAMP_UP_QUEUE_DEPTH, &vha->dpc_flags),
5237 test_bit(HOST_RAMP_DOWN_QUEUE_DEPTH, &vha->dpc_flags));
e315cd28 5238 qla2xxx_wake_dpc(vha);
7c3df132 5239 }
1da177e4 5240
e315cd28 5241 qla2x00_restart_timer(vha, WATCH_INTERVAL);
1da177e4
LT		 5242}
5243
5433383e
AV		 5244/* Firmware interface routines. */
5245
6246b8a1 5246#define FW_BLOBS 10
5433383e
AV		 5247#define FW_ISP21XX 0
5248#define FW_ISP22XX 1
5249#define FW_ISP2300 2
5250#define FW_ISP2322 3
48c02fde 5251#define FW_ISP24XX 4
c3a2f0df 5252#define FW_ISP25XX 5
3a03eb79 5253#define FW_ISP81XX 6
a9083016 5254#define FW_ISP82XX 7
6246b8a1
GM		 5255#define FW_ISP2031 8
5256#define FW_ISP8031 9
5433383e 5257
bb8ee499
AV		 5258#define FW_FILE_ISP21XX "ql2100_fw.bin"
5259#define FW_FILE_ISP22XX "ql2200_fw.bin"
5260#define FW_FILE_ISP2300 "ql2300_fw.bin"
5261#define FW_FILE_ISP2322 "ql2322_fw.bin"
5262#define FW_FILE_ISP24XX "ql2400_fw.bin"
c3a2f0df 5263#define FW_FILE_ISP25XX "ql2500_fw.bin"
3a03eb79 5264#define FW_FILE_ISP81XX "ql8100_fw.bin"
a9083016 5265#define FW_FILE_ISP82XX "ql8200_fw.bin"
6246b8a1
GM		 5266#define FW_FILE_ISP2031 "ql2600_fw.bin"
5267#define FW_FILE_ISP8031 "ql8300_fw.bin"
bb8ee499 5268
e1e82b6f 5269static DEFINE_MUTEX(qla_fw_lock);
5433383e
AV		 5270
5271static struct fw_blob qla_fw_blobs[FW_BLOBS] = {
bb8ee499
AV		 5272 { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, },
5273 { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, },
5274 { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, },
5275 { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, },
5276 { .name = FW_FILE_ISP24XX, },
c3a2f0df 5277 { .name = FW_FILE_ISP25XX, },
3a03eb79 5278 { .name = FW_FILE_ISP81XX, },
a9083016 5279 { .name = FW_FILE_ISP82XX, },
6246b8a1
GM		 5280 { .name = FW_FILE_ISP2031, },
5281 { .name = FW_FILE_ISP8031, },
5433383e
AV		 5282};
5283
5284struct fw_blob *
e315cd28 5285qla2x00_request_firmware(scsi_qla_host_t *vha)
5433383e 5286{
e315cd28 5287 struct qla_hw_data *ha = vha->hw;
5433383e
AV		 5288 struct fw_blob *blob;
5289
5433383e
AV		 5290 if (IS_QLA2100(ha)) {
5291 blob = &qla_fw_blobs[FW_ISP21XX];
5292 } else if (IS_QLA2200(ha)) {
5293 blob = &qla_fw_blobs[FW_ISP22XX];
48c02fde 5294 } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
5433383e 5295 blob = &qla_fw_blobs[FW_ISP2300];
48c02fde 5296 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
5433383e 5297 blob = &qla_fw_blobs[FW_ISP2322];
4d4df193 5298 } else if (IS_QLA24XX_TYPE(ha)) {
5433383e 5299 blob = &qla_fw_blobs[FW_ISP24XX];
c3a2f0df
AV		 5300 } else if (IS_QLA25XX(ha)) {
5301 blob = &qla_fw_blobs[FW_ISP25XX];
3a03eb79
AV		 5302 } else if (IS_QLA81XX(ha)) {
5303 blob = &qla_fw_blobs[FW_ISP81XX];
a9083016
GM		 5304 } else if (IS_QLA82XX(ha)) {
5305 blob = &qla_fw_blobs[FW_ISP82XX];
6246b8a1
GM		 5306 } else if (IS_QLA2031(ha)) {
5307 blob = &qla_fw_blobs[FW_ISP2031];
5308 } else if (IS_QLA8031(ha)) {
5309 blob = &qla_fw_blobs[FW_ISP8031];
8a655229
DC		 5310 } else {
5311 return NULL;
5433383e
AV		 5312 }
5313
e1e82b6f 5314 mutex_lock(&qla_fw_lock);
5433383e
AV		 5315 if (blob->fw)
5316 goto out;
5317
5318 if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) {
7c3df132
SK		 5319 ql_log(ql_log_warn, vha, 0x0063,
5320 "Failed to load firmware image (%s).\n", blob->name);
5433383e
AV		 5321 blob->fw = NULL;
5322 blob = NULL;
5323 goto out;
5324 }
5325
5326out:
e1e82b6f 5327 mutex_unlock(&qla_fw_lock);
5433383e
AV		 5328 return blob;
5329}
5330
5331static void
5332qla2x00_release_firmware(void)
5333{
5334 int idx;
5335
e1e82b6f 5336 mutex_lock(&qla_fw_lock);
5433383e 5337 for (idx = 0; idx < FW_BLOBS; idx++)
cf92549f 5338 release_firmware(qla_fw_blobs[idx].fw);
e1e82b6f 5339 mutex_unlock(&qla_fw_lock);
5433383e
AV		 5340}
5341
14e660e6
SJ		 5342static pci_ers_result_t
5343qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
5344{
85880801
AV		 5345 scsi_qla_host_t *vha = pci_get_drvdata(pdev);
5346 struct qla_hw_data *ha = vha->hw;
5347
7c3df132
SK		 5348 ql_dbg(ql_dbg_aer, vha, 0x9000,
5349 "PCI error detected, state %x.\n", state);
b9b12f73 5350
14e660e6
SJ		 5351 switch (state) {
5352 case pci_channel_io_normal:
85880801 5353 ha->flags.eeh_busy = 0;
14e660e6
SJ		 5354 return PCI_ERS_RESULT_CAN_RECOVER;
5355 case pci_channel_io_frozen:
85880801 5356 ha->flags.eeh_busy = 1;
a5b36321
LC		 5357 /* For ISP82XX complete any pending mailbox cmd */
5358 if (IS_QLA82XX(ha)) {
7190575f 5359 ha->flags.isp82xx_fw_hung = 1;
c8f6544e
CD		 5360 ql_dbg(ql_dbg_aer, vha, 0x9001, "Pci channel io frozen\n");
5361 qla82xx_clear_pending_mbx(vha);
a5b36321 5362 }
90a86fc0 5363 qla2x00_free_irqs(vha);
14e660e6 5364 pci_disable_device(pdev);
bddd2d65
LC		 5365 /* Return back all IOs */
5366 qla2x00_abort_all_cmds(vha, DID_RESET << 16);
14e660e6
SJ		 5367 return PCI_ERS_RESULT_NEED_RESET;
5368 case pci_channel_io_perm_failure:
85880801
AV		 5369 ha->flags.pci_channel_io_perm_failure = 1;
5370 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
14e660e6
SJ		 5371 return PCI_ERS_RESULT_DISCONNECT;
5372 }
5373 return PCI_ERS_RESULT_NEED_RESET;
5374}
5375
5376static pci_ers_result_t
5377qla2xxx_pci_mmio_enabled(struct pci_dev *pdev)
5378{
5379 int risc_paused = 0;
5380 uint32_t stat;
5381 unsigned long flags;
e315cd28
AC		 5382 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
5383 struct qla_hw_data *ha = base_vha->hw;
14e660e6
SJ		 5384 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
5385 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
5386
bcc5b6d3
SK		 5387 if (IS_QLA82XX(ha))
5388 return PCI_ERS_RESULT_RECOVERED;
5389
14e660e6
SJ		 5390 spin_lock_irqsave(&ha->hardware_lock, flags);
5391 if (IS_QLA2100(ha) || IS_QLA2200(ha)){
5392 stat = RD_REG_DWORD(&reg->hccr);
5393 if (stat & HCCR_RISC_PAUSE)
5394 risc_paused = 1;
5395 } else if (IS_QLA23XX(ha)) {
5396 stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
5397 if (stat & HSR_RISC_PAUSED)
5398 risc_paused = 1;
5399 } else if (IS_FWI2_CAPABLE(ha)) {
5400 stat = RD_REG_DWORD(&reg24->host_status);
5401 if (stat & HSRX_RISC_PAUSED)
5402 risc_paused = 1;
5403 }
5404 spin_unlock_irqrestore(&ha->hardware_lock, flags);
5405
5406 if (risc_paused) {
7c3df132
SK		 5407 ql_log(ql_log_info, base_vha, 0x9003,
5408 "RISC paused -- mmio_enabled, Dumping firmware.\n");
e315cd28 5409 ha->isp_ops->fw_dump(base_vha, 0);
14e660e6
SJ		 5410
5411 return PCI_ERS_RESULT_NEED_RESET;
5412 } else
5413 return PCI_ERS_RESULT_RECOVERED;
5414}
5415
fa492630
SK		 5416static uint32_t
5417qla82xx_error_recovery(scsi_qla_host_t *base_vha)
a5b36321
LC		 5418{
5419 uint32_t rval = QLA_FUNCTION_FAILED;
5420 uint32_t drv_active = 0;
5421 struct qla_hw_data *ha = base_vha->hw;
5422 int fn;
5423 struct pci_dev *other_pdev = NULL;
5424
7c3df132
SK		 5425 ql_dbg(ql_dbg_aer, base_vha, 0x9006,
5426 "Entered %s.\n", __func__);
a5b36321
LC		 5427
5428 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
5429
5430 if (base_vha->flags.online) {
5431 /* Abort all outstanding commands,
5432 * so as to be requeued later */
5433 qla2x00_abort_isp_cleanup(base_vha);
5434 }
5435
5436
5437 fn = PCI_FUNC(ha->pdev->devfn);
5438 while (fn > 0) {
5439 fn--;
7c3df132
SK		 5440 ql_dbg(ql_dbg_aer, base_vha, 0x9007,
5441 "Finding pci device at function = 0x%x.\n", fn);
a5b36321
LC		 5442 other_pdev =
5443 pci_get_domain_bus_and_slot(pci_domain_nr(ha->pdev->bus),
5444 ha->pdev->bus->number, PCI_DEVFN(PCI_SLOT(ha->pdev->devfn),
5445 fn));
5446
5447 if (!other_pdev)
5448 continue;
5449 if (atomic_read(&other_pdev->enable_cnt)) {
7c3df132
SK		 5450 ql_dbg(ql_dbg_aer, base_vha, 0x9008,
5451 "Found PCI func available and enable at 0x%x.\n",
5452 fn);
a5b36321
LC		 5453 pci_dev_put(other_pdev);
5454 break;
5455 }
5456 pci_dev_put(other_pdev);
5457 }
5458
5459 if (!fn) {
5460 /* Reset owner */
7c3df132
SK		 5461 ql_dbg(ql_dbg_aer, base_vha, 0x9009,
5462 "This devfn is reset owner = 0x%x.\n",
5463 ha->pdev->devfn);
a5b36321
LC		 5464 qla82xx_idc_lock(ha);
5465
5466 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 5467 QLA8XXX_DEV_INITIALIZING);
a5b36321
LC		 5468
5469 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION,
5470 QLA82XX_IDC_VERSION);
5471
5472 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
7c3df132
SK		 5473 ql_dbg(ql_dbg_aer, base_vha, 0x900a,
5474 "drv_active = 0x%x.\n", drv_active);
a5b36321
LC		 5475
5476 qla82xx_idc_unlock(ha);
5477 /* Reset if device is not already reset
5478 * drv_active would be 0 if a reset has already been done
5479 */
5480 if (drv_active)
5481 rval = qla82xx_start_firmware(base_vha);
5482 else
5483 rval = QLA_SUCCESS;
5484 qla82xx_idc_lock(ha);
5485
5486 if (rval != QLA_SUCCESS) {
7c3df132
SK		 5487 ql_log(ql_log_info, base_vha, 0x900b,
5488 "HW State: FAILED.\n");
a5b36321
LC		 5489 qla82xx_clear_drv_active(ha);
5490 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 5491 QLA8XXX_DEV_FAILED);
a5b36321 5492 } else {
7c3df132
SK		 5493 ql_log(ql_log_info, base_vha, 0x900c,
5494 "HW State: READY.\n");
a5b36321 5495 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 5496 QLA8XXX_DEV_READY);
a5b36321 5497 qla82xx_idc_unlock(ha);
7190575f 5498 ha->flags.isp82xx_fw_hung = 0;
a5b36321
LC		 5499 rval = qla82xx_restart_isp(base_vha);
5500 qla82xx_idc_lock(ha);
5501 /* Clear driver state register */
5502 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, 0);
5503 qla82xx_set_drv_active(base_vha);
5504 }
5505 qla82xx_idc_unlock(ha);
5506 } else {
7c3df132
SK		 5507 ql_dbg(ql_dbg_aer, base_vha, 0x900d,
5508 "This devfn is not reset owner = 0x%x.\n",
5509 ha->pdev->devfn);
a5b36321 5510 if ((qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE) ==
7d613ac6 5511 QLA8XXX_DEV_READY)) {
7190575f 5512 ha->flags.isp82xx_fw_hung = 0;
a5b36321
LC		 5513 rval = qla82xx_restart_isp(base_vha);
5514 qla82xx_idc_lock(ha);
5515 qla82xx_set_drv_active(base_vha);
5516 qla82xx_idc_unlock(ha);
5517 }
5518 }
5519 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
5520
5521 return rval;
5522}
5523
14e660e6
SJ		 5524static pci_ers_result_t
5525qla2xxx_pci_slot_reset(struct pci_dev *pdev)
5526{
5527 pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT;
e315cd28
AC		 5528 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
5529 struct qla_hw_data *ha = base_vha->hw;
90a86fc0
JC		 5530 struct rsp_que *rsp;
5531 int rc, retries = 10;
09483916 5532
7c3df132
SK		 5533 ql_dbg(ql_dbg_aer, base_vha, 0x9004,
5534 "Slot Reset.\n");
85880801 5535
90a86fc0
JC		 5536 /* Workaround: qla2xxx driver which access hardware earlier
5537 * needs error state to be pci_channel_io_online.
5538 * Otherwise mailbox command timesout.
5539 */
5540 pdev->error_state = pci_channel_io_normal;
5541
5542 pci_restore_state(pdev);
5543
8c1496bd
RL		 5544 /* pci_restore_state() clears the saved_state flag of the device
5545 * save restored state which resets saved_state flag
5546 */
5547 pci_save_state(pdev);
5548
09483916
BH		 5549 if (ha->mem_only)
5550 rc = pci_enable_device_mem(pdev);
5551 else
5552 rc = pci_enable_device(pdev);
14e660e6 5553
09483916 5554 if (rc) {
7c3df132 5555 ql_log(ql_log_warn, base_vha, 0x9005,
14e660e6 5556 "Can't re-enable PCI device after reset.\n");
a5b36321 5557 goto exit_slot_reset;
14e660e6 5558 }
14e660e6 5559
90a86fc0
JC		 5560 rsp = ha->rsp_q_map[0];
5561 if (qla2x00_request_irqs(ha, rsp))
a5b36321 5562 goto exit_slot_reset;
90a86fc0 5563
e315cd28 5564 if (ha->isp_ops->pci_config(base_vha))
a5b36321
LC		 5565 goto exit_slot_reset;
5566
5567 if (IS_QLA82XX(ha)) {
5568 if (qla82xx_error_recovery(base_vha) == QLA_SUCCESS) {
5569 ret = PCI_ERS_RESULT_RECOVERED;
5570 goto exit_slot_reset;
5571 } else
5572 goto exit_slot_reset;
5573 }
14e660e6 5574
90a86fc0
JC		 5575 while (ha->flags.mbox_busy && retries--)
5576 msleep(1000);
85880801 5577
e315cd28 5578 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
a9083016 5579 if (ha->isp_ops->abort_isp(base_vha) == QLA_SUCCESS)
14e660e6 5580 ret = PCI_ERS_RESULT_RECOVERED;
e315cd28 5581 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
14e660e6 5582
90a86fc0 5583
a5b36321 5584exit_slot_reset:
7c3df132
SK		 5585 ql_dbg(ql_dbg_aer, base_vha, 0x900e,
5586 "slot_reset return %x.\n", ret);
85880801 5587
14e660e6
SJ		 5588 return ret;
5589}
5590
5591static void
5592qla2xxx_pci_resume(struct pci_dev *pdev)
5593{
e315cd28
AC		 5594 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
5595 struct qla_hw_data *ha = base_vha->hw;
14e660e6
SJ		 5596 int ret;
5597
7c3df132
SK		 5598 ql_dbg(ql_dbg_aer, base_vha, 0x900f,
5599 "pci_resume.\n");
85880801 5600
e315cd28 5601 ret = qla2x00_wait_for_hba_online(base_vha);
14e660e6 5602 if (ret != QLA_SUCCESS) {
7c3df132
SK		 5603 ql_log(ql_log_fatal, base_vha, 0x9002,
5604 "The device failed to resume I/O from slot/link_reset.\n");
14e660e6 5605 }
85880801 5606
3e46f031
LC		 5607 pci_cleanup_aer_uncorrect_error_status(pdev);
5608
85880801 5609 ha->flags.eeh_busy = 0;
14e660e6
SJ		 5610}
5611
a55b2d21 5612static const struct pci_error_handlers qla2xxx_err_handler = {
14e660e6
SJ		 5613 .error_detected = qla2xxx_pci_error_detected,
5614 .mmio_enabled = qla2xxx_pci_mmio_enabled,
5615 .slot_reset = qla2xxx_pci_slot_reset,
5616 .resume = qla2xxx_pci_resume,
5617};
5618
5433383e 5619static struct pci_device_id qla2xxx_pci_tbl[] = {
47f5e069
AV		 5620 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) },
5621 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) },
5622 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) },
5623 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) },
5624 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) },
5625 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) },
5626 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) },
5627 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) },
5628 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) },
4d4df193 5629 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) },
47f5e069
AV		 5630 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) },
5631 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) },
c3a2f0df 5632 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) },
6246b8a1 5633 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2031) },
3a03eb79 5634 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) },
a9083016 5635 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) },
650f528f 5636 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8031) },
8ae6d9c7 5637 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISPF001) },
7ec0effd 5638 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8044) },
5433383e
AV		 5639 { 0 },
5640};
5641MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl);
5642
fca29703 5643static struct pci_driver qla2xxx_pci_driver = {
cb63067a 5644 .name = QLA2XXX_DRIVER_NAME,
0a21ef1e
JB		 5645 .driver = {
5646 .owner = THIS_MODULE,
5647 },
fca29703 5648 .id_table = qla2xxx_pci_tbl,
7ee61397 5649 .probe = qla2x00_probe_one,
4c993f76 5650 .remove = qla2x00_remove_one,
e30d1756 5651 .shutdown = qla2x00_shutdown,
14e660e6 5652 .err_handler = &qla2xxx_err_handler,
fca29703
AV		 5653};
5654
75ef9de1 5655static const struct file_operations apidev_fops = {
6a03b4cd 5656 .owner = THIS_MODULE,
6038f373 5657 .llseek = noop_llseek,
6a03b4cd
HZ		 5658};
5659
1da177e4
LT		 5660/**
5661 * qla2x00_module_init - Module initialization.
5662 **/
5663static int __init
5664qla2x00_module_init(void)
5665{
fca29703
AV		 5666 int ret = 0;
5667
1da177e4 5668 /* Allocate cache for SRBs. */
354d6b21 5669 srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0,
20c2df83 5670 SLAB_HWCACHE_ALIGN, NULL);
1da177e4 5671 if (srb_cachep == NULL) {
7c3df132
SK		 5672 ql_log(ql_log_fatal, NULL, 0x0001,
5673 "Unable to allocate SRB cache...Failing load!.\n");
1da177e4
LT		 5674 return -ENOMEM;
5675 }
5676
2d70c103
NB		 5677 /* Initialize target kmem_cache and mem_pools */
5678 ret = qlt_init();
5679 if (ret < 0) {
5680 kmem_cache_destroy(srb_cachep);
5681 return ret;
5682 } else if (ret > 0) {
5683 /*
5684 * If initiator mode is explictly disabled by qlt_init(),
5685 * prevent scsi_transport_fc.c:fc_scsi_scan_rport() from
5686 * performing scsi_scan_target() during LOOP UP event.
5687 */
5688 qla2xxx_transport_functions.disable_target_scan = 1;
5689 qla2xxx_transport_vport_functions.disable_target_scan = 1;
5690 }
5691
1da177e4
LT		 5692 /* Derive version string. */
5693 strcpy(qla2x00_version_str, QLA2XXX_VERSION);
11010fec 5694 if (ql2xextended_error_logging)
0181944f
AV		 5695 strcat(qla2x00_version_str, "-debug");
5696
1c97a12a
AV		 5697 qla2xxx_transport_template =
5698 fc_attach_transport(&qla2xxx_transport_functions);
2c3dfe3f
SJ		 5699 if (!qla2xxx_transport_template) {
5700 kmem_cache_destroy(srb_cachep);
7c3df132
SK		 5701 ql_log(ql_log_fatal, NULL, 0x0002,
5702 "fc_attach_transport failed...Failing load!.\n");
2d70c103 5703 qlt_exit();
1da177e4 5704 return -ENODEV;
2c3dfe3f 5705 }
6a03b4cd
HZ		 5706
5707 apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops);
5708 if (apidev_major < 0) {
7c3df132
SK		 5709 ql_log(ql_log_fatal, NULL, 0x0003,
5710 "Unable to register char device %s.\n", QLA2XXX_APIDEV);
6a03b4cd
HZ		 5711 }
5712
2c3dfe3f
SJ		 5713 qla2xxx_transport_vport_template =
5714 fc_attach_transport(&qla2xxx_transport_vport_functions);
5715 if (!qla2xxx_transport_vport_template) {
5716 kmem_cache_destroy(srb_cachep);
2d70c103 5717 qlt_exit();
2c3dfe3f 5718 fc_release_transport(qla2xxx_transport_template);
7c3df132
SK		 5719 ql_log(ql_log_fatal, NULL, 0x0004,
5720 "fc_attach_transport vport failed...Failing load!.\n");
1da177e4 5721 return -ENODEV;
2c3dfe3f 5722 }
7c3df132
SK		 5723 ql_log(ql_log_info, NULL, 0x0005,
5724 "QLogic Fibre Channel HBA Driver: %s.\n",
fd9a29f0 5725 qla2x00_version_str);
7ee61397 5726 ret = pci_register_driver(&qla2xxx_pci_driver);
fca29703
AV		 5727 if (ret) {
5728 kmem_cache_destroy(srb_cachep);
2d70c103 5729 qlt_exit();
fca29703 5730 fc_release_transport(qla2xxx_transport_template);
2c3dfe3f 5731 fc_release_transport(qla2xxx_transport_vport_template);
7c3df132
SK		 5732 ql_log(ql_log_fatal, NULL, 0x0006,
5733 "pci_register_driver failed...ret=%d Failing load!.\n",
5734 ret);
fca29703
AV		 5735 }
5736 return ret;
1da177e4
LT		 5737}
5738
5739/**
5740 * qla2x00_module_exit - Module cleanup.
5741 **/
5742static void __exit
5743qla2x00_module_exit(void)
5744{
6a03b4cd 5745 unregister_chrdev(apidev_major, QLA2XXX_APIDEV);
7ee61397 5746 pci_unregister_driver(&qla2xxx_pci_driver);
5433383e 5747 qla2x00_release_firmware();
354d6b21 5748 kmem_cache_destroy(srb_cachep);
2d70c103 5749 qlt_exit();
a9083016
GM		 5750 if (ctx_cachep)
5751 kmem_cache_destroy(ctx_cachep);
1da177e4 5752 fc_release_transport(qla2xxx_transport_template);
2c3dfe3f 5753 fc_release_transport(qla2xxx_transport_vport_template);
1da177e4
LT		 5754}
5755
5756module_init(qla2x00_module_init);
5757module_exit(qla2x00_module_exit);
5758
5759MODULE_AUTHOR("QLogic Corporation");
5760MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver");
5761MODULE_LICENSE("GPL");
5762MODULE_VERSION(QLA2XXX_VERSION);
bb8ee499
AV		 5763MODULE_FIRMWARE(FW_FILE_ISP21XX);
5764MODULE_FIRMWARE(FW_FILE_ISP22XX);
5765MODULE_FIRMWARE(FW_FILE_ISP2300);
5766MODULE_FIRMWARE(FW_FILE_ISP2322);
5767MODULE_FIRMWARE(FW_FILE_ISP24XX);
61623fc3 5768MODULE_FIRMWARE(FW_FILE_ISP25XX);
Linux 6.x block layer and io_uring tree(s)