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scsi: qla2xxx: Use mutex protection during qla2x00_sysfs_read_fw_dump()
[linux-2.6-block.git] / drivers / scsi / qla2xxx / qla_os.c
CommitLineData
1da177e4 1/*
fa90c54f 2 * QLogic Fibre Channel HBA Driver
bd21eaf9 3 * Copyright (c) 2003-2014 QLogic Corporation
1da177e4 4 *
fa90c54f 5 * See LICENSE.qla2xxx for copyright and licensing details.
1da177e4
LT		 6 */
7#include "qla_def.h"
8
9#include <linux/moduleparam.h>
10#include <linux/vmalloc.h>
1da177e4 11#include <linux/delay.h>
39a11240 12#include <linux/kthread.h>
e1e82b6f 13#include <linux/mutex.h>
3420d36c 14#include <linux/kobject.h>
5a0e3ad6 15#include <linux/slab.h>
5601236b 16#include <linux/blk-mq-pci.h>
585def9b
QT		 17#include <linux/refcount.h>
18
1da177e4
LT		 19#include <scsi/scsi_tcq.h>
20#include <scsi/scsicam.h>
21#include <scsi/scsi_transport.h>
22#include <scsi/scsi_transport_fc.h>
23
2d70c103
NB		 24#include "qla_target.h"
25
1da177e4
LT		 26/*
27 * Driver version
28 */
29char qla2x00_version_str[40];
30
6a03b4cd
HZ		 31static int apidev_major;
32
1da177e4
LT		 33/*
34 * SRB allocation cache
35 */
d7459527 36struct kmem_cache *srb_cachep;
1da177e4 37
a9083016
GM		 38/*
39 * CT6 CTX allocation cache
40 */
41static struct kmem_cache *ctx_cachep;
3ce8866c
SK		 42/*
43 * error level for logging
44 */
3f006ac3 45uint ql_errlev = 0x8001;
a9083016 46
fa492630 47static int ql2xenableclass2;
2d70c103
NB		 48module_param(ql2xenableclass2, int, S_IRUGO|S_IRUSR);
49MODULE_PARM_DESC(ql2xenableclass2,
50 "Specify if Class 2 operations are supported from the very "
51 "beginning. Default is 0 - class 2 not supported.");
52
8ae6d9c7 53
1da177e4 54int ql2xlogintimeout = 20;
f2019cb1 55module_param(ql2xlogintimeout, int, S_IRUGO);
1da177e4
LT		 56MODULE_PARM_DESC(ql2xlogintimeout,
57 "Login timeout value in seconds.");
58
a7b61842 59int qlport_down_retry;
f2019cb1 60module_param(qlport_down_retry, int, S_IRUGO);
1da177e4 61MODULE_PARM_DESC(qlport_down_retry,
900d9f98 62 "Maximum number of command retries to a port that returns "
1da177e4
LT		 63 "a PORT-DOWN status.");
64
1da177e4
LT		 65int ql2xplogiabsentdevice;
66module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR);
67MODULE_PARM_DESC(ql2xplogiabsentdevice,
68 "Option to enable PLOGI to devices that are not present after "
900d9f98 69 "a Fabric scan. This is needed for several broken switches. "
0d52e642 70 "Default is 0 - no PLOGI. 1 - perform PLOGI.");
1da177e4 71
1da177e4 72int ql2xloginretrycount = 0;
f2019cb1 73module_param(ql2xloginretrycount, int, S_IRUGO);
1da177e4
LT		 74MODULE_PARM_DESC(ql2xloginretrycount,
75 "Specify an alternate value for the NVRAM login retry count.");
76
a7a167bf 77int ql2xallocfwdump = 1;
f2019cb1 78module_param(ql2xallocfwdump, int, S_IRUGO);
a7a167bf
AV		 79MODULE_PARM_DESC(ql2xallocfwdump,
80 "Option to enable allocation of memory for a firmware dump "
81 "during HBA initialization. Memory allocation requirements "
82 "vary by ISP type. Default is 1 - allocate memory.");
83
11010fec 84int ql2xextended_error_logging;
27d94035 85module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
a2b3e01d 86module_param_named(logging, ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
11010fec 87MODULE_PARM_DESC(ql2xextended_error_logging,
3ce8866c
SK		 88 "Option to enable extended error logging,\n"
89 "\t\tDefault is 0 - no logging. 0x40000000 - Module Init & Probe.\n"
90 "\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n"
91 "\t\t0x08000000 - IO tracing. 0x04000000 - DPC Thread.\n"
92 "\t\t0x02000000 - Async events. 0x01000000 - Timer routines.\n"
93 "\t\t0x00800000 - User space. 0x00400000 - Task Management.\n"
94 "\t\t0x00200000 - AER/EEH. 0x00100000 - Multi Q.\n"
95 "\t\t0x00080000 - P3P Specific. 0x00040000 - Virtual Port.\n"
96 "\t\t0x00020000 - Buffer Dump. 0x00010000 - Misc.\n"
29f9f90c
CD		 97 "\t\t0x00008000 - Verbose. 0x00004000 - Target.\n"
98 "\t\t0x00002000 - Target Mgmt. 0x00001000 - Target TMF.\n"
3ce8866c 99 "\t\t0x7fffffff - For enabling all logs, can be too many logs.\n"
cfb0919c
CD		 100 "\t\t0x1e400000 - Preferred value for capturing essential "
101 "debug information (equivalent to old "
102 "ql2xextended_error_logging=1).\n"
3ce8866c 103 "\t\tDo LOGICAL OR of the value to enable more than one level");
0181944f 104
a9083016 105int ql2xshiftctondsd = 6;
f2019cb1 106module_param(ql2xshiftctondsd, int, S_IRUGO);
a9083016
GM		 107MODULE_PARM_DESC(ql2xshiftctondsd,
108 "Set to control shifting of command type processing "
109 "based on total number of SG elements.");
110
7e47e5ca 111int ql2xfdmienable=1;
de187df8 112module_param(ql2xfdmienable, int, S_IRUGO|S_IWUSR);
a2b3e01d 113module_param_named(fdmi, ql2xfdmienable, int, S_IRUGO|S_IWUSR);
cca5335c 114MODULE_PARM_DESC(ql2xfdmienable,
7794a5af
FW		 115 "Enables FDMI registrations. "
116 "0 - no FDMI. Default is 1 - perform FDMI.");
cca5335c 117
d213a4b7 118#define MAX_Q_DEPTH 64
50280c01 119static int ql2xmaxqdepth = MAX_Q_DEPTH;
df7baa50
AV		 120module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR);
121MODULE_PARM_DESC(ql2xmaxqdepth,
e92e4a8f 122 "Maximum queue depth to set for each LUN. "
d213a4b7 123 "Default is 64.");
df7baa50 124
e84067d7
DG		 125#if (IS_ENABLED(CONFIG_NVME_FC))
126int ql2xenabledif;
127#else
9e522cd8 128int ql2xenabledif = 2;
e84067d7 129#endif
9e522cd8 130module_param(ql2xenabledif, int, S_IRUGO);
bad75002 131MODULE_PARM_DESC(ql2xenabledif,
b97f5d0b
SM		 132 " Enable T10-CRC-DIF:\n"
133 " Default is 2.\n"
134 " 0 -- No DIF Support\n"
135 " 1 -- Enable DIF for all types\n"
136 " 2 -- Enable DIF for all types, except Type 0.\n");
bad75002 137
e84067d7
DG		 138#if (IS_ENABLED(CONFIG_NVME_FC))
139int ql2xnvmeenable = 1;
140#else
141int ql2xnvmeenable;
142#endif
143module_param(ql2xnvmeenable, int, 0644);
144MODULE_PARM_DESC(ql2xnvmeenable,
145 "Enables NVME support. "
146 "0 - no NVMe. Default is Y");
147
8cb2049c 148int ql2xenablehba_err_chk = 2;
bad75002
AE		 149module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR);
150MODULE_PARM_DESC(ql2xenablehba_err_chk,
8cb2049c 151 " Enable T10-CRC-DIF Error isolation by HBA:\n"
b97f5d0b 152 " Default is 2.\n"
8cb2049c
AE		 153 " 0 -- Error isolation disabled\n"
154 " 1 -- Error isolation enabled only for DIX Type 0\n"
155 " 2 -- Error isolation enabled for all Types\n");
bad75002 156
e5896bd5 157int ql2xiidmaenable=1;
f2019cb1 158module_param(ql2xiidmaenable, int, S_IRUGO);
e5896bd5
AV		 159MODULE_PARM_DESC(ql2xiidmaenable,
160 "Enables iIDMA settings "
161 "Default is 1 - perform iIDMA. 0 - no iIDMA.");
162
d7459527
MH		 163int ql2xmqsupport = 1;
164module_param(ql2xmqsupport, int, S_IRUGO);
165MODULE_PARM_DESC(ql2xmqsupport,
166 "Enable on demand multiple queue pairs support "
167 "Default is 1 for supported. "
168 "Set it to 0 to turn off mq qpair support.");
e337d907
AV		 169
170int ql2xfwloadbin;
86e45bf6 171module_param(ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
a2b3e01d 172module_param_named(fwload, ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
e337d907 173MODULE_PARM_DESC(ql2xfwloadbin,
7c3df132
SK		 174 "Option to specify location from which to load ISP firmware:.\n"
175 " 2 -- load firmware via the request_firmware() (hotplug).\n"
e337d907
AV		 176 " interface.\n"
177 " 1 -- load firmware from flash.\n"
178 " 0 -- use default semantics.\n");
179
ae97c91e 180int ql2xetsenable;
f2019cb1 181module_param(ql2xetsenable, int, S_IRUGO);
ae97c91e
AV		 182MODULE_PARM_DESC(ql2xetsenable,
183 "Enables firmware ETS burst."
184 "Default is 0 - skip ETS enablement.");
185
6907869d 186int ql2xdbwr = 1;
86e45bf6 187module_param(ql2xdbwr, int, S_IRUGO|S_IWUSR);
a9083016 188MODULE_PARM_DESC(ql2xdbwr,
08de2844
GM		 189 "Option to specify scheme for request queue posting.\n"
190 " 0 -- Regular doorbell.\n"
191 " 1 -- CAMRAM doorbell (faster).\n");
a9083016 192
f4c496c1 193int ql2xtargetreset = 1;
f2019cb1 194module_param(ql2xtargetreset, int, S_IRUGO);
f4c496c1
GM		 195MODULE_PARM_DESC(ql2xtargetreset,
196 "Enable target reset."
197 "Default is 1 - use hw defaults.");
198
4da26e16 199int ql2xgffidenable;
f2019cb1 200module_param(ql2xgffidenable, int, S_IRUGO);
4da26e16
CD		 201MODULE_PARM_DESC(ql2xgffidenable,
202 "Enables GFF_ID checks of port type. "
203 "Default is 0 - Do not use GFF_ID information.");
a9083016 204
043dc1d7 205int ql2xasynctmfenable = 1;
f2019cb1 206module_param(ql2xasynctmfenable, int, S_IRUGO);
3822263e
MI		 207MODULE_PARM_DESC(ql2xasynctmfenable,
208 "Enables issue of TM IOCBs asynchronously via IOCB mechanism"
84e13c45 209 "Default is 1 - Issue TM IOCBs via mailbox mechanism.");
ed0de87c
GM		 210
211int ql2xdontresethba;
86e45bf6 212module_param(ql2xdontresethba, int, S_IRUGO|S_IWUSR);
ed0de87c 213MODULE_PARM_DESC(ql2xdontresethba,
08de2844
GM		 214 "Option to specify reset behaviour.\n"
215 " 0 (Default) -- Reset on failure.\n"
216 " 1 -- Do not reset on failure.\n");
ed0de87c 217
1abf635d
HR		 218uint64_t ql2xmaxlun = MAX_LUNS;
219module_param(ql2xmaxlun, ullong, S_IRUGO);
82515920
AV		 220MODULE_PARM_DESC(ql2xmaxlun,
221 "Defines the maximum LU number to register with the SCSI "
222 "midlayer. Default is 65535.");
223
08de2844
GM		 224int ql2xmdcapmask = 0x1F;
225module_param(ql2xmdcapmask, int, S_IRUGO);
226MODULE_PARM_DESC(ql2xmdcapmask,
227 "Set the Minidump driver capture mask level. "
6e96fa7b 228 "Default is 0x1F - Can be set to 0x3, 0x7, 0xF, 0x1F, 0x7F.");
08de2844 229
3aadff35 230int ql2xmdenable = 1;
08de2844
GM		 231module_param(ql2xmdenable, int, S_IRUGO);
232MODULE_PARM_DESC(ql2xmdenable,
233 "Enable/disable MiniDump. "
3aadff35
GM		 234 "0 - MiniDump disabled. "
235 "1 (Default) - MiniDump enabled.");
08de2844 236
b0d6cabd
HM		 237int ql2xexlogins = 0;
238module_param(ql2xexlogins, uint, S_IRUGO|S_IWUSR);
239MODULE_PARM_DESC(ql2xexlogins,
240 "Number of extended Logins. "
241 "0 (Default)- Disabled.");
242
99e1b683
QT		 243int ql2xexchoffld = 1024;
244module_param(ql2xexchoffld, uint, 0644);
2f56a7f1 245MODULE_PARM_DESC(ql2xexchoffld,
99e1b683
QT		 246 "Number of target exchanges.");
247
248int ql2xiniexchg = 1024;
249module_param(ql2xiniexchg, uint, 0644);
250MODULE_PARM_DESC(ql2xiniexchg,
251 "Number of initiator exchanges.");
2f56a7f1 252
f198cafa
HM		 253int ql2xfwholdabts = 0;
254module_param(ql2xfwholdabts, int, S_IRUGO);
255MODULE_PARM_DESC(ql2xfwholdabts,
256 "Allow FW to hold status IOCB until ABTS rsp received. "
257 "0 (Default) Do not set fw option. "
258 "1 - Set fw option to hold ABTS.");
259
41dc529a
QT		 260int ql2xmvasynctoatio = 1;
261module_param(ql2xmvasynctoatio, int, S_IRUGO|S_IWUSR);
262MODULE_PARM_DESC(ql2xmvasynctoatio,
263 "Move PUREX, ABTS RX and RIDA IOCBs to ATIOQ"
264 "0 (Default). Do not move IOCBs"
265 "1 - Move IOCBs.");
266
e4e3a2ce
QT		 267int ql2xautodetectsfp = 1;
268module_param(ql2xautodetectsfp, int, 0444);
269MODULE_PARM_DESC(ql2xautodetectsfp,
270 "Detect SFP range and set appropriate distance.\n"
271 "1 (Default): Enable\n");
272
e7240af5
HM		 273int ql2xenablemsix = 1;
274module_param(ql2xenablemsix, int, 0444);
275MODULE_PARM_DESC(ql2xenablemsix,
276 "Set to enable MSI or MSI-X interrupt mechanism.\n"
277 " Default is 1, enable MSI-X interrupt mechanism.\n"
278 " 0 -- enable traditional pin-based mechanism.\n"
279 " 1 -- enable MSI-X interrupt mechanism.\n"
280 " 2 -- enable MSI interrupt mechanism.\n");
281
9ecf0b0d
QT		 282int qla2xuseresexchforels;
283module_param(qla2xuseresexchforels, int, 0444);
284MODULE_PARM_DESC(qla2xuseresexchforels,
285 "Reserve 1/2 of emergency exchanges for ELS.\n"
286 " 0 (default): disabled");
287
7855d2ba
MP		 288int ql2xprotmask;
289module_param(ql2xprotmask, int, 0644);
290MODULE_PARM_DESC(ql2xprotmask,
291 "Override DIF/DIX protection capabilities mask\n"
292 "Default is 0 which sets protection mask based on "
293 "capabilities reported by HBA firmware.\n");
294
295int ql2xprotguard;
296module_param(ql2xprotguard, int, 0644);
297MODULE_PARM_DESC(ql2xprotguard, "Override choice of DIX checksum\n"
298 " 0 -- Let HBA firmware decide\n"
299 " 1 -- Force T10 CRC\n"
300 " 2 -- Force IP checksum\n");
301
50b81275
GM		 302int ql2xdifbundlinginternalbuffers;
303module_param(ql2xdifbundlinginternalbuffers, int, 0644);
304MODULE_PARM_DESC(ql2xdifbundlinginternalbuffers,
305 "Force using internal buffers for DIF information\n"
306 "0 (Default). Based on check.\n"
307 "1 Force using internal buffers\n");
308
1da177e4 309/*
fa2a1ce5 310 * SCSI host template entry points
1da177e4
LT		 311 */
312static int qla2xxx_slave_configure(struct scsi_device * device);
f4f051eb 313static int qla2xxx_slave_alloc(struct scsi_device *);
1e99e33a
AV		 314static int qla2xxx_scan_finished(struct Scsi_Host *, unsigned long time);
315static void qla2xxx_scan_start(struct Scsi_Host *);
f4f051eb 316static void qla2xxx_slave_destroy(struct scsi_device *);
f281233d 317static int qla2xxx_queuecommand(struct Scsi_Host *h, struct scsi_cmnd *cmd);
1da177e4
LT		 318static int qla2xxx_eh_abort(struct scsi_cmnd *);
319static int qla2xxx_eh_device_reset(struct scsi_cmnd *);
523ec773 320static int qla2xxx_eh_target_reset(struct scsi_cmnd *);
1da177e4
LT		 321static int qla2xxx_eh_bus_reset(struct scsi_cmnd *);
322static int qla2xxx_eh_host_reset(struct scsi_cmnd *);
1da177e4 323
1a2fbf18 324static void qla2x00_clear_drv_active(struct qla_hw_data *);
3491255e 325static void qla2x00_free_device(scsi_qla_host_t *);
5601236b 326static int qla2xxx_map_queues(struct Scsi_Host *shost);
e84067d7 327static void qla2x00_destroy_deferred_work(struct qla_hw_data *);
ce7e4af7 328
45235022 329
a5326f86 330struct scsi_host_template qla2xxx_driver_template = {
1da177e4 331 .module = THIS_MODULE,
cb63067a 332 .name = QLA2XXX_DRIVER_NAME,
a5326f86 333 .queuecommand = qla2xxx_queuecommand,
fca29703 334
b6a05c82 335 .eh_timed_out = fc_eh_timed_out,
fca29703
AV		 336 .eh_abort_handler = qla2xxx_eh_abort,
337 .eh_device_reset_handler = qla2xxx_eh_device_reset,
523ec773 338 .eh_target_reset_handler = qla2xxx_eh_target_reset,
fca29703
AV		 339 .eh_bus_reset_handler = qla2xxx_eh_bus_reset,
340 .eh_host_reset_handler = qla2xxx_eh_host_reset,
341
342 .slave_configure = qla2xxx_slave_configure,
343
344 .slave_alloc = qla2xxx_slave_alloc,
345 .slave_destroy = qla2xxx_slave_destroy,
ed677086
AV		 346 .scan_finished = qla2xxx_scan_finished,
347 .scan_start = qla2xxx_scan_start,
db5ed4df 348 .change_queue_depth = scsi_change_queue_depth,
5601236b 349 .map_queues = qla2xxx_map_queues,
fca29703
AV		 350 .this_id = -1,
351 .cmd_per_lun = 3,
fca29703
AV		 352 .sg_tablesize = SG_ALL,
353
354 .max_sectors = 0xFFFF,
afb046e2 355 .shost_attrs = qla2x00_host_attrs,
2d70c103
NB		 356
357 .supported_mode = MODE_INITIATOR,
c40ecc12 358 .track_queue_depth = 1,
fca29703
AV		 359};
360
1da177e4 361static struct scsi_transport_template *qla2xxx_transport_template = NULL;
2c3dfe3f 362struct scsi_transport_template *qla2xxx_transport_vport_template = NULL;
1da177e4 363
1da177e4
LT		 364/* TODO Convert to inlines
365 *
366 * Timer routines
367 */
1da177e4 368
2c3dfe3f 369__inline__ void
8e5f4ba0 370qla2x00_start_timer(scsi_qla_host_t *vha, unsigned long interval)
1da177e4 371{
8e5f4ba0 372 timer_setup(&vha->timer, qla2x00_timer, 0);
e315cd28 373 vha->timer.expires = jiffies + interval * HZ;
e315cd28
AC		 374 add_timer(&vha->timer);
375 vha->timer_active = 1;
1da177e4
LT		 376}
377
378static inline void
e315cd28 379qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval)
1da177e4 380{
a9083016 381 /* Currently used for 82XX only. */
7c3df132
SK		 382 if (vha->device_flags & DFLG_DEV_FAILED) {
383 ql_dbg(ql_dbg_timer, vha, 0x600d,
384 "Device in a failed state, returning.\n");
a9083016 385 return;
7c3df132 386 }
a9083016 387
e315cd28 388 mod_timer(&vha->timer, jiffies + interval * HZ);
1da177e4
LT		 389}
390
a824ebb3 391static __inline__ void
e315cd28 392qla2x00_stop_timer(scsi_qla_host_t *vha)
1da177e4 393{
e315cd28
AC		 394 del_timer_sync(&vha->timer);
395 vha->timer_active = 0;
1da177e4
LT		 396}
397
1da177e4
LT		 398static int qla2x00_do_dpc(void *data);
399
400static void qla2x00_rst_aen(scsi_qla_host_t *);
401
73208dfd
AC		 402static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t,
403 struct req_que **, struct rsp_que **);
e30d1756 404static void qla2x00_free_fw_dump(struct qla_hw_data *);
e315cd28 405static void qla2x00_mem_free(struct qla_hw_data *);
d7459527
MH		 406int qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd,
407 struct qla_qpair *qpair);
1da177e4 408
1da177e4 409/* -------------------------------------------------------------------------- */
8abfa9e2
QT		 410static void qla_init_base_qpair(struct scsi_qla_host *vha, struct req_que *req,
411 struct rsp_que *rsp)
412{
413 struct qla_hw_data *ha = vha->hw;
414 rsp->qpair = ha->base_qpair;
415 rsp->req = req;
0691094f 416 ha->base_qpair->hw = ha;
8abfa9e2
QT		 417 ha->base_qpair->req = req;
418 ha->base_qpair->rsp = rsp;
419 ha->base_qpair->vha = vha;
420 ha->base_qpair->qp_lock_ptr = &ha->hardware_lock;
421 ha->base_qpair->use_shadow_reg = IS_SHADOW_REG_CAPABLE(ha) ? 1 : 0;
422 ha->base_qpair->msix = &ha->msix_entries[QLA_MSIX_RSP_Q];
6a629468 423 ha->base_qpair->srb_mempool = ha->srb_mempool;
8abfa9e2
QT		 424 INIT_LIST_HEAD(&ha->base_qpair->hints_list);
425 ha->base_qpair->enable_class_2 = ql2xenableclass2;
426 /* init qpair to this cpu. Will adjust at run time. */
86531887 427 qla_cpu_update(rsp->qpair, raw_smp_processor_id());
8abfa9e2
QT		 428 ha->base_qpair->pdev = ha->pdev;
429
ecc89f25 430 if (IS_QLA27XX(ha) || IS_QLA83XX(ha) || IS_QLA28XX(ha))
8abfa9e2
QT		 431 ha->base_qpair->reqq_start_iocbs = qla_83xx_start_iocbs;
432}
433
9a347ff4
CD		 434static int qla2x00_alloc_queues(struct qla_hw_data *ha, struct req_que *req,
435 struct rsp_que *rsp)
73208dfd 436{
7c3df132 437 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
6396bb22 438 ha->req_q_map = kcalloc(ha->max_req_queues, sizeof(struct req_que *),
73208dfd
AC		 439 GFP_KERNEL);
440 if (!ha->req_q_map) {
7c3df132
SK		 441 ql_log(ql_log_fatal, vha, 0x003b,
442 "Unable to allocate memory for request queue ptrs.\n");
73208dfd
AC		 443 goto fail_req_map;
444 }
445
6396bb22 446 ha->rsp_q_map = kcalloc(ha->max_rsp_queues, sizeof(struct rsp_que *),
73208dfd
AC		 447 GFP_KERNEL);
448 if (!ha->rsp_q_map) {
7c3df132
SK		 449 ql_log(ql_log_fatal, vha, 0x003c,
450 "Unable to allocate memory for response queue ptrs.\n");
73208dfd
AC		 451 goto fail_rsp_map;
452 }
d7459527 453
e326d22a
QT		 454 ha->base_qpair = kzalloc(sizeof(struct qla_qpair), GFP_KERNEL);
455 if (ha->base_qpair == NULL) {
456 ql_log(ql_log_warn, vha, 0x00e0,
457 "Failed to allocate base queue pair memory.\n");
458 goto fail_base_qpair;
459 }
460
8abfa9e2 461 qla_init_base_qpair(vha, req, rsp);
e326d22a 462
c38d1baf 463 if ((ql2xmqsupport || ql2xnvmeenable) && ha->max_qpairs) {
d7459527
MH		 464 ha->queue_pair_map = kcalloc(ha->max_qpairs, sizeof(struct qla_qpair *),
465 GFP_KERNEL);
466 if (!ha->queue_pair_map) {
467 ql_log(ql_log_fatal, vha, 0x0180,
468 "Unable to allocate memory for queue pair ptrs.\n");
469 goto fail_qpair_map;
470 }
d7459527
MH		 471 }
472
9a347ff4
CD		 473 /*
474 * Make sure we record at least the request and response queue zero in
475 * case we need to free them if part of the probe fails.
476 */
477 ha->rsp_q_map[0] = rsp;
478 ha->req_q_map[0] = req;
73208dfd
AC		 479 set_bit(0, ha->rsp_qid_map);
480 set_bit(0, ha->req_qid_map);
6a2cf8d3 481 return 0;
73208dfd 482
d7459527 483fail_qpair_map:
82de802a
QT		 484 kfree(ha->base_qpair);
485 ha->base_qpair = NULL;
486fail_base_qpair:
d7459527
MH		 487 kfree(ha->rsp_q_map);
488 ha->rsp_q_map = NULL;
73208dfd
AC		 489fail_rsp_map:
490 kfree(ha->req_q_map);
491 ha->req_q_map = NULL;
492fail_req_map:
493 return -ENOMEM;
494}
495
2afa19a9 496static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req)
73208dfd 497{
8ae6d9c7
GM		 498 if (IS_QLAFX00(ha)) {
499 if (req && req->ring_fx00)
500 dma_free_coherent(&ha->pdev->dev,
501 (req->length_fx00 + 1) * sizeof(request_t),
502 req->ring_fx00, req->dma_fx00);
503 } else if (req && req->ring)
73208dfd
AC		 504 dma_free_coherent(&ha->pdev->dev,
505 (req->length + 1) * sizeof(request_t),
506 req->ring, req->dma);
507
6d634067 508 if (req)
8d93f550 509 kfree(req->outstanding_cmds);
6d634067
BK		 510
511 kfree(req);
73208dfd
AC		 512}
513
2afa19a9
AC		 514static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp)
515{
8ae6d9c7 516 if (IS_QLAFX00(ha)) {
3f6c9be2 517 if (rsp && rsp->ring_fx00)
8ae6d9c7
GM		 518 dma_free_coherent(&ha->pdev->dev,
519 (rsp->length_fx00 + 1) * sizeof(request_t),
520 rsp->ring_fx00, rsp->dma_fx00);
521 } else if (rsp && rsp->ring) {
2afa19a9
AC		 522 dma_free_coherent(&ha->pdev->dev,
523 (rsp->length + 1) * sizeof(response_t),
524 rsp->ring, rsp->dma);
8ae6d9c7 525 }
6d634067 526 kfree(rsp);
2afa19a9
AC		 527}
528
73208dfd
AC		 529static void qla2x00_free_queues(struct qla_hw_data *ha)
530{
531 struct req_que *req;
532 struct rsp_que *rsp;
533 int cnt;
093df737 534 unsigned long flags;
73208dfd 535
82de802a
QT		 536 if (ha->queue_pair_map) {
537 kfree(ha->queue_pair_map);
538 ha->queue_pair_map = NULL;
539 }
540 if (ha->base_qpair) {
541 kfree(ha->base_qpair);
542 ha->base_qpair = NULL;
543 }
544
093df737 545 spin_lock_irqsave(&ha->hardware_lock, flags);
2afa19a9 546 for (cnt = 0; cnt < ha->max_req_queues; cnt++) {
cb43285f
QT		 547 if (!test_bit(cnt, ha->req_qid_map))
548 continue;
549
73208dfd 550 req = ha->req_q_map[cnt];
093df737
QT		 551 clear_bit(cnt, ha->req_qid_map);
552 ha->req_q_map[cnt] = NULL;
553
554 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2afa19a9 555 qla2x00_free_req_que(ha, req);
093df737 556 spin_lock_irqsave(&ha->hardware_lock, flags);
73208dfd 557 }
093df737
QT		 558 spin_unlock_irqrestore(&ha->hardware_lock, flags);
559
73208dfd
AC		 560 kfree(ha->req_q_map);
561 ha->req_q_map = NULL;
2afa19a9 562
093df737
QT		 563
564 spin_lock_irqsave(&ha->hardware_lock, flags);
2afa19a9 565 for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) {
cb43285f
QT		 566 if (!test_bit(cnt, ha->rsp_qid_map))
567 continue;
568
2afa19a9 569 rsp = ha->rsp_q_map[cnt];
c3c42394 570 clear_bit(cnt, ha->rsp_qid_map);
093df737
QT		 571 ha->rsp_q_map[cnt] = NULL;
572 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2afa19a9 573 qla2x00_free_rsp_que(ha, rsp);
093df737 574 spin_lock_irqsave(&ha->hardware_lock, flags);
2afa19a9 575 }
093df737
QT		 576 spin_unlock_irqrestore(&ha->hardware_lock, flags);
577
2afa19a9
AC		 578 kfree(ha->rsp_q_map);
579 ha->rsp_q_map = NULL;
73208dfd
AC		 580}
581
1da177e4 582static char *
e315cd28 583qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str)
1da177e4 584{
e315cd28 585 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 586 static char *pci_bus_modes[] = {
587 "33", "66", "100", "133",
588 };
589 uint16_t pci_bus;
590
591 strcpy(str, "PCI");
592 pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9;
593 if (pci_bus) {
594 strcat(str, "-X (");
595 strcat(str, pci_bus_modes[pci_bus]);
596 } else {
597 pci_bus = (ha->pci_attr & BIT_8) >> 8;
598 strcat(str, " (");
599 strcat(str, pci_bus_modes[pci_bus]);
600 }
601 strcat(str, " MHz)");
602
603 return (str);
604}
605
fca29703 606static char *
e315cd28 607qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str)
fca29703
AV		 608{
609 static char *pci_bus_modes[] = { "33", "66", "100", "133", };
e315cd28 610 struct qla_hw_data *ha = vha->hw;
fca29703 611 uint32_t pci_bus;
fca29703 612
62a276f8 613 if (pci_is_pcie(ha->pdev)) {
fca29703 614 char lwstr[6];
62a276f8 615 uint32_t lstat, lspeed, lwidth;
fca29703 616
62a276f8
BH		 617 pcie_capability_read_dword(ha->pdev, PCI_EXP_LNKCAP, &lstat);
618 lspeed = lstat & PCI_EXP_LNKCAP_SLS;
619 lwidth = (lstat & PCI_EXP_LNKCAP_MLW) >> 4;
fca29703
AV		 620
621 strcpy(str, "PCIe (");
49300af7
SK		 622 switch (lspeed) {
623 case 1:
c87a0d8c 624 strcat(str, "2.5GT/s ");
49300af7
SK		 625 break;
626 case 2:
c87a0d8c 627 strcat(str, "5.0GT/s ");
49300af7
SK		 628 break;
629 case 3:
630 strcat(str, "8.0GT/s ");
631 break;
632 default:
fca29703 633 strcat(str, "<unknown> ");
49300af7
SK		 634 break;
635 }
fca29703
AV		 636 snprintf(lwstr, sizeof(lwstr), "x%d)", lwidth);
637 strcat(str, lwstr);
638
639 return str;
640 }
641
642 strcpy(str, "PCI");
643 pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8;
644 if (pci_bus == 0 || pci_bus == 8) {
645 strcat(str, " (");
646 strcat(str, pci_bus_modes[pci_bus >> 3]);
647 } else {
648 strcat(str, "-X ");
649 if (pci_bus & BIT_2)
650 strcat(str, "Mode 2");
651 else
652 strcat(str, "Mode 1");
653 strcat(str, " (");
654 strcat(str, pci_bus_modes[pci_bus & ~BIT_2]);
655 }
656 strcat(str, " MHz)");
657
658 return str;
659}
660
e5f82ab8 661static char *
df57caba 662qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
1da177e4
LT		 663{
664 char un_str[10];
e315cd28 665 struct qla_hw_data *ha = vha->hw;
fa2a1ce5 666
df57caba
HM		 667 snprintf(str, size, "%d.%02d.%02d ", ha->fw_major_version,
668 ha->fw_minor_version, ha->fw_subminor_version);
1da177e4
LT		 669
670 if (ha->fw_attributes & BIT_9) {
671 strcat(str, "FLX");
672 return (str);
673 }
674
675 switch (ha->fw_attributes & 0xFF) {
676 case 0x7:
677 strcat(str, "EF");
678 break;
679 case 0x17:
680 strcat(str, "TP");
681 break;
682 case 0x37:
683 strcat(str, "IP");
684 break;
685 case 0x77:
686 strcat(str, "VI");
687 break;
688 default:
689 sprintf(un_str, "(%x)", ha->fw_attributes);
690 strcat(str, un_str);
691 break;
692 }
693 if (ha->fw_attributes & 0x100)
694 strcat(str, "X");
695
696 return (str);
697}
698
e5f82ab8 699static char *
df57caba 700qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
fca29703 701{
e315cd28 702 struct qla_hw_data *ha = vha->hw;
f0883ac6 703
df57caba 704 snprintf(str, size, "%d.%02d.%02d (%x)", ha->fw_major_version,
3a03eb79 705 ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes);
fca29703 706 return str;
fca29703
AV		 707}
708
9ba56b95 709void
25ff6af1 710qla2x00_sp_free_dma(void *ptr)
fca29703 711{
25ff6af1
JC		 712 srb_t *sp = ptr;
713 struct qla_hw_data *ha = sp->vha->hw;
9ba56b95 714 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
9ba56b95 715 void *ctx = GET_CMD_CTX_SP(sp);
fca29703 716
9ba56b95
GM		 717 if (sp->flags & SRB_DMA_VALID) {
718 scsi_dma_unmap(cmd);
719 sp->flags &= ~SRB_DMA_VALID;
7c3df132 720 }
fca29703 721
9ba56b95
GM		 722 if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
723 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
724 scsi_prot_sg_count(cmd), cmd->sc_data_direction);
725 sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
726 }
727
d5ff0eed
JC		 728 if (!ctx)
729 goto end;
730
9ba56b95
GM		 731 if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
732 /* List assured to be having elements */
d5ff0eed 733 qla2x00_clean_dsd_pool(ha, ctx);
9ba56b95
GM		 734 sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
735 }
736
737 if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
d5ff0eed
JC		 738 struct crc_context *ctx0 = ctx;
739
740 dma_pool_free(ha->dl_dma_pool, ctx0, ctx0->crc_ctx_dma);
9ba56b95
GM		 741 sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
742 }
743
744 if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
d5ff0eed 745 struct ct6_dsd *ctx1 = ctx;
fca29703 746
9ba56b95 747 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd,
d5ff0eed 748 ctx1->fcp_cmnd_dma);
9ba56b95
GM		 749 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list);
750 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt;
751 ha->gbl_dsd_avail += ctx1->dsd_use_cnt;
752 mempool_free(ctx1, ha->ctx_mempool);
9ba56b95
GM		 753 }
754
d5ff0eed 755end:
6fcd98fd 756 if (sp->type != SRB_NVME_CMD && sp->type != SRB_NVME_LS) {
7401bc18
DG		 757 CMD_SP(cmd) = NULL;
758 qla2x00_rel_sp(sp);
759 }
9ba56b95
GM		 760}
761
d7459527 762void
25ff6af1 763qla2x00_sp_compl(void *ptr, int res)
9ba56b95 764{
25ff6af1 765 srb_t *sp = ptr;
9ba56b95
GM		 766 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
767
9ba56b95 768 if (atomic_read(&sp->ref_count) == 0) {
25ff6af1 769 ql_dbg(ql_dbg_io, sp->vha, 0x3015,
9ba56b95
GM		 770 "SP reference-count to ZERO -- sp=%p cmd=%p.\n",
771 sp, GET_CMD_SP(sp));
772 if (ql2xextended_error_logging & ql_dbg_io)
8fbdac8c 773 WARN_ON(atomic_read(&sp->ref_count) == 0);
9ba56b95
GM		 774 return;
775 }
776 if (!atomic_dec_and_test(&sp->ref_count))
777 return;
778
f3caa990 779 sp->free(sp);
740e2935 780 cmd->result = res;
9ba56b95 781 cmd->scsi_done(cmd);
fca29703
AV		 782}
783
d7459527 784void
25ff6af1 785qla2xxx_qpair_sp_free_dma(void *ptr)
d7459527
MH		 786{
787 srb_t *sp = (srb_t *)ptr;
788 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
789 struct qla_hw_data *ha = sp->fcport->vha->hw;
790 void *ctx = GET_CMD_CTX_SP(sp);
791
792 if (sp->flags & SRB_DMA_VALID) {
793 scsi_dma_unmap(cmd);
794 sp->flags &= ~SRB_DMA_VALID;
795 }
796
797 if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
798 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
799 scsi_prot_sg_count(cmd), cmd->sc_data_direction);
800 sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
801 }
802
d5ff0eed
JC		 803 if (!ctx)
804 goto end;
805
d7459527
MH		 806 if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
807 /* List assured to be having elements */
d5ff0eed 808 qla2x00_clean_dsd_pool(ha, ctx);
d7459527
MH		 809 sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
810 }
811
812 if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
d5ff0eed
JC		 813 struct crc_context *ctx0 = ctx;
814
815 dma_pool_free(ha->dl_dma_pool, ctx, ctx0->crc_ctx_dma);
d7459527
MH		 816 sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
817 }
818
819 if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
d5ff0eed 820 struct ct6_dsd *ctx1 = ctx;
d7459527
MH		 821 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd,
822 ctx1->fcp_cmnd_dma);
823 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list);
824 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt;
825 ha->gbl_dsd_avail += ctx1->dsd_use_cnt;
826 mempool_free(ctx1, ha->ctx_mempool);
50b81275
GM		 827 sp->flags &= ~SRB_FCP_CMND_DMA_VALID;
828 }
829 if (sp->flags & SRB_DIF_BUNDL_DMA_VALID) {
830 struct crc_context *difctx = sp->u.scmd.ctx;
831 struct dsd_dma *dif_dsd, *nxt_dsd;
832
833 list_for_each_entry_safe(dif_dsd, nxt_dsd,
834 &difctx->ldif_dma_hndl_list, list) {
835 list_del(&dif_dsd->list);
836 dma_pool_free(ha->dif_bundl_pool, dif_dsd->dsd_addr,
837 dif_dsd->dsd_list_dma);
838 kfree(dif_dsd);
839 difctx->no_dif_bundl--;
840 }
841
842 list_for_each_entry_safe(dif_dsd, nxt_dsd,
843 &difctx->ldif_dsd_list, list) {
844 list_del(&dif_dsd->list);
845 dma_pool_free(ha->dl_dma_pool, dif_dsd->dsd_addr,
846 dif_dsd->dsd_list_dma);
847 kfree(dif_dsd);
848 difctx->no_ldif_dsd--;
849 }
850
851 if (difctx->no_ldif_dsd) {
852 ql_dbg(ql_dbg_tgt+ql_dbg_verbose, sp->vha, 0xe022,
853 "%s: difctx->no_ldif_dsd=%x\n",
854 __func__, difctx->no_ldif_dsd);
855 }
856
857 if (difctx->no_dif_bundl) {
858 ql_dbg(ql_dbg_tgt+ql_dbg_verbose, sp->vha, 0xe022,
859 "%s: difctx->no_dif_bundl=%x\n",
860 __func__, difctx->no_dif_bundl);
861 }
862 sp->flags &= ~SRB_DIF_BUNDL_DMA_VALID;
d7459527 863 }
50b81275 864
d5ff0eed 865end:
d7459527
MH		 866 CMD_SP(cmd) = NULL;
867 qla2xxx_rel_qpair_sp(sp->qpair, sp);
868}
869
870void
25ff6af1 871qla2xxx_qpair_sp_compl(void *ptr, int res)
d7459527 872{
25ff6af1 873 srb_t *sp = ptr;
d7459527
MH		 874 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
875
876 cmd->result = res;
877
878 if (atomic_read(&sp->ref_count) == 0) {
879 ql_dbg(ql_dbg_io, sp->fcport->vha, 0x3079,
880 "SP reference-count to ZERO -- sp=%p cmd=%p.\n",
881 sp, GET_CMD_SP(sp));
882 if (ql2xextended_error_logging & ql_dbg_io)
883 WARN_ON(atomic_read(&sp->ref_count) == 0);
884 return;
885 }
886 if (!atomic_dec_and_test(&sp->ref_count))
887 return;
888
f3caa990 889 sp->free(sp);
d7459527
MH		 890 cmd->scsi_done(cmd);
891}
892
8ae6d9c7
GM		 893/* If we are SP1 here, we need to still take and release the host_lock as SP1
894 * does not have the changes necessary to avoid taking host->host_lock.
895 */
1da177e4 896static int
f5e3e40b 897qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
fca29703 898{
134ae078 899 scsi_qla_host_t *vha = shost_priv(host);
fca29703 900 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
19a7b4ae 901 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
e315cd28
AC		 902 struct qla_hw_data *ha = vha->hw;
903 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
fca29703
AV		 904 srb_t *sp;
905 int rval;
5601236b
MH		 906 struct qla_qpair *qpair = NULL;
907 uint32_t tag;
908 uint16_t hwq;
fca29703 909
04dfaa53
MFO		 910 if (unlikely(test_bit(UNLOADING, &base_vha->dpc_flags))) {
911 cmd->result = DID_NO_CONNECT << 16;
912 goto qc24_fail_command;
913 }
914
5601236b 915 if (ha->mqenable) {
f664a3cc
JA		 916 tag = blk_mq_unique_tag(cmd->request);
917 hwq = blk_mq_unique_tag_to_hwq(tag);
918 qpair = ha->queue_pair_map[hwq];
5601236b
MH		 919
920 if (qpair)
921 return qla2xxx_mqueuecommand(host, cmd, qpair);
d7459527
MH		 922 }
923
85880801 924 if (ha->flags.eeh_busy) {
7c3df132 925 if (ha->flags.pci_channel_io_perm_failure) {
5f28d2d7 926 ql_dbg(ql_dbg_aer, vha, 0x9010,
7c3df132
SK		 927 "PCI Channel IO permanent failure, exiting "
928 "cmd=%p.\n", cmd);
b9b12f73 929 cmd->result = DID_NO_CONNECT << 16;
7c3df132 930 } else {
5f28d2d7 931 ql_dbg(ql_dbg_aer, vha, 0x9011,
7c3df132 932 "EEH_Busy, Requeuing the cmd=%p.\n", cmd);
85880801 933 cmd->result = DID_REQUEUE << 16;
7c3df132 934 }
14e660e6
SJ		 935 goto qc24_fail_command;
936 }
937
19a7b4ae
JSEC		 938 rval = fc_remote_port_chkready(rport);
939 if (rval) {
940 cmd->result = rval;
5f28d2d7 941 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3003,
7c3df132
SK		 942 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
943 cmd, rval);
fca29703
AV		 944 goto qc24_fail_command;
945 }
946
bad75002
AE		 947 if (!vha->flags.difdix_supported &&
948 scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) {
7c3df132
SK		 949 ql_dbg(ql_dbg_io, vha, 0x3004,
950 "DIF Cap not reg, fail DIF capable cmd's:%p.\n",
951 cmd);
bad75002
AE		 952 cmd->result = DID_NO_CONNECT << 16;
953 goto qc24_fail_command;
954 }
aa651be8
CD		 955
956 if (!fcport) {
957 cmd->result = DID_NO_CONNECT << 16;
958 goto qc24_fail_command;
959 }
960
fca29703
AV		 961 if (atomic_read(&fcport->state) != FCS_ONLINE) {
962 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
38170fa8 963 atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
7c3df132
SK		 964 ql_dbg(ql_dbg_io, vha, 0x3005,
965 "Returning DNC, fcport_state=%d loop_state=%d.\n",
966 atomic_read(&fcport->state),
967 atomic_read(&base_vha->loop_state));
fca29703
AV		 968 cmd->result = DID_NO_CONNECT << 16;
969 goto qc24_fail_command;
970 }
7b594131 971 goto qc24_target_busy;
fca29703
AV		 972 }
973
e05fe292
CD		 974 /*
975 * Return target busy if we've received a non-zero retry_delay_timer
976 * in a FCP_RSP.
977 */
975f7d46
BP		 978 if (fcport->retry_delay_timestamp == 0) {
979 /* retry delay not set */
980 } else if (time_after(jiffies, fcport->retry_delay_timestamp))
e05fe292
CD		 981 fcport->retry_delay_timestamp = 0;
982 else
983 goto qc24_target_busy;
984
b00ee7d7 985 sp = qla2x00_get_sp(vha, fcport, GFP_ATOMIC);
50280c01 986 if (!sp)
f5e3e40b 987 goto qc24_host_busy;
fca29703 988
9ba56b95
GM		 989 sp->u.scmd.cmd = cmd;
990 sp->type = SRB_SCSI_CMD;
991 atomic_set(&sp->ref_count, 1);
992 CMD_SP(cmd) = (void *)sp;
993 sp->free = qla2x00_sp_free_dma;
994 sp->done = qla2x00_sp_compl;
995
e315cd28 996 rval = ha->isp_ops->start_scsi(sp);
7c3df132 997 if (rval != QLA_SUCCESS) {
53016ed3 998 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3013,
7c3df132 999 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
fca29703 1000 goto qc24_host_busy_free_sp;
7c3df132 1001 }
fca29703 1002
fca29703
AV		 1003 return 0;
1004
1005qc24_host_busy_free_sp:
f3caa990 1006 sp->free(sp);
fca29703 1007
f5e3e40b 1008qc24_host_busy:
fca29703
AV		 1009 return SCSI_MLQUEUE_HOST_BUSY;
1010
7b594131
MC		 1011qc24_target_busy:
1012 return SCSI_MLQUEUE_TARGET_BUSY;
1013
fca29703 1014qc24_fail_command:
f5e3e40b 1015 cmd->scsi_done(cmd);
fca29703
AV		 1016
1017 return 0;
1018}
1019
d7459527
MH		 1020/* For MQ supported I/O */
1021int
1022qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd,
1023 struct qla_qpair *qpair)
1024{
1025 scsi_qla_host_t *vha = shost_priv(host);
1026 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
1027 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
1028 struct qla_hw_data *ha = vha->hw;
1029 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
1030 srb_t *sp;
1031 int rval;
1032
1033 rval = fc_remote_port_chkready(rport);
1034 if (rval) {
1035 cmd->result = rval;
1036 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3076,
1037 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
1038 cmd, rval);
1039 goto qc24_fail_command;
1040 }
1041
1042 if (!fcport) {
1043 cmd->result = DID_NO_CONNECT << 16;
1044 goto qc24_fail_command;
1045 }
1046
1047 if (atomic_read(&fcport->state) != FCS_ONLINE) {
1048 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
1049 atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
1050 ql_dbg(ql_dbg_io, vha, 0x3077,
1051 "Returning DNC, fcport_state=%d loop_state=%d.\n",
1052 atomic_read(&fcport->state),
1053 atomic_read(&base_vha->loop_state));
1054 cmd->result = DID_NO_CONNECT << 16;
1055 goto qc24_fail_command;
1056 }
1057 goto qc24_target_busy;
1058 }
1059
1060 /*
1061 * Return target busy if we've received a non-zero retry_delay_timer
1062 * in a FCP_RSP.
1063 */
1064 if (fcport->retry_delay_timestamp == 0) {
1065 /* retry delay not set */
1066 } else if (time_after(jiffies, fcport->retry_delay_timestamp))
1067 fcport->retry_delay_timestamp = 0;
1068 else
1069 goto qc24_target_busy;
1070
6a629468 1071 sp = qla2xxx_get_qpair_sp(vha, qpair, fcport, GFP_ATOMIC);
d7459527
MH		 1072 if (!sp)
1073 goto qc24_host_busy;
1074
1075 sp->u.scmd.cmd = cmd;
1076 sp->type = SRB_SCSI_CMD;
1077 atomic_set(&sp->ref_count, 1);
1078 CMD_SP(cmd) = (void *)sp;
1079 sp->free = qla2xxx_qpair_sp_free_dma;
1080 sp->done = qla2xxx_qpair_sp_compl;
1081 sp->qpair = qpair;
1082
1083 rval = ha->isp_ops->start_scsi_mq(sp);
1084 if (rval != QLA_SUCCESS) {
1085 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3078,
1086 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
1087 if (rval == QLA_INTERFACE_ERROR)
1088 goto qc24_fail_command;
1089 goto qc24_host_busy_free_sp;
1090 }
1091
1092 return 0;
1093
1094qc24_host_busy_free_sp:
f3caa990 1095 sp->free(sp);
d7459527
MH		 1096
1097qc24_host_busy:
1098 return SCSI_MLQUEUE_HOST_BUSY;
1099
1100qc24_target_busy:
1101 return SCSI_MLQUEUE_TARGET_BUSY;
1102
1103qc24_fail_command:
1104 cmd->scsi_done(cmd);
1105
1106 return 0;
1107}
1108
1da177e4
LT		 1109/*
1110 * qla2x00_eh_wait_on_command
1111 * Waits for the command to be returned by the Firmware for some
1112 * max time.
1113 *
1114 * Input:
1da177e4 1115 * cmd = Scsi Command to wait on.
1da177e4
LT		 1116 *
1117 * Return:
1118 * Not Found : 0
1119 * Found : 1
1120 */
1121static int
e315cd28 1122qla2x00_eh_wait_on_command(struct scsi_cmnd *cmd)
1da177e4 1123{
fe74c71f 1124#define ABORT_POLLING_PERIOD 1000
478c3b03 1125#define ABORT_WAIT_ITER ((2 * 1000) / (ABORT_POLLING_PERIOD))
f4f051eb 1126 unsigned long wait_iter = ABORT_WAIT_ITER;
85880801
AV		 1127 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1128 struct qla_hw_data *ha = vha->hw;
f4f051eb 1129 int ret = QLA_SUCCESS;
1da177e4 1130
85880801 1131 if (unlikely(pci_channel_offline(ha->pdev)) || ha->flags.eeh_busy) {
7c3df132
SK		 1132 ql_dbg(ql_dbg_taskm, vha, 0x8005,
1133 "Return:eh_wait.\n");
85880801
AV		 1134 return ret;
1135 }
1136
d970432c 1137 while (CMD_SP(cmd) && wait_iter--) {
fe74c71f 1138 msleep(ABORT_POLLING_PERIOD);
f4f051eb 1139 }
1140 if (CMD_SP(cmd))
1141 ret = QLA_FUNCTION_FAILED;
1da177e4 1142
f4f051eb 1143 return ret;
1da177e4
LT		 1144}
1145
1146/*
1147 * qla2x00_wait_for_hba_online
fa2a1ce5 1148 * Wait till the HBA is online after going through
1da177e4
LT		 1149 * <= MAX_RETRIES_OF_ISP_ABORT or
1150 * finally HBA is disabled ie marked offline
1151 *
1152 * Input:
1153 * ha - pointer to host adapter structure
fa2a1ce5
AV		 1154 *
1155 * Note:
1da177e4
LT		 1156 * Does context switching-Release SPIN_LOCK
1157 * (if any) before calling this routine.
1158 *
1159 * Return:
1160 * Success (Adapter is online) : 0
1161 * Failed (Adapter is offline/disabled) : 1
1162 */
854165f4 1163int
e315cd28 1164qla2x00_wait_for_hba_online(scsi_qla_host_t *vha)
1da177e4 1165{
fca29703
AV		 1166 int return_status;
1167 unsigned long wait_online;
e315cd28
AC		 1168 struct qla_hw_data *ha = vha->hw;
1169 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4 1170
fa2a1ce5 1171 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ);
e315cd28
AC		 1172 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
1173 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
1174 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
1175 ha->dpc_active) && time_before(jiffies, wait_online)) {
1da177e4
LT		 1176
1177 msleep(1000);
1178 }
e315cd28 1179 if (base_vha->flags.online)
fa2a1ce5 1180 return_status = QLA_SUCCESS;
1da177e4
LT		 1181 else
1182 return_status = QLA_FUNCTION_FAILED;
1183
1da177e4
LT		 1184 return (return_status);
1185}
1186
726b8548
QT		 1187static inline int test_fcport_count(scsi_qla_host_t *vha)
1188{
1189 struct qla_hw_data *ha = vha->hw;
1190 unsigned long flags;
1191 int res;
1192
1193 spin_lock_irqsave(&ha->tgt.sess_lock, flags);
83548fe2
QT		 1194 ql_dbg(ql_dbg_init, vha, 0x00ec,
1195 "tgt %p, fcport_count=%d\n",
1196 vha, vha->fcport_count);
726b8548
QT		 1197 res = (vha->fcport_count == 0);
1198 spin_unlock_irqrestore(&ha->tgt.sess_lock, flags);
1199
1200 return res;
1201}
1202
1203/*
1204 * qla2x00_wait_for_sess_deletion can only be called from remove_one.
1205 * it has dependency on UNLOADING flag to stop device discovery
1206 */
efa93f48 1207void
726b8548
QT		 1208qla2x00_wait_for_sess_deletion(scsi_qla_host_t *vha)
1209{
1210 qla2x00_mark_all_devices_lost(vha, 0);
1211
b85e0957 1212 wait_event_timeout(vha->fcport_waitQ, test_fcport_count(vha), 10*HZ);
726b8548
QT		 1213}
1214
86fbee86 1215/*
638a1a01
SC		 1216 * qla2x00_wait_for_hba_ready
1217 * Wait till the HBA is ready before doing driver unload
86fbee86
LC		 1218 *
1219 * Input:
1220 * ha - pointer to host adapter structure
1221 *
1222 * Note:
1223 * Does context switching-Release SPIN_LOCK
1224 * (if any) before calling this routine.
1225 *
86fbee86 1226 */
638a1a01
SC		 1227static void
1228qla2x00_wait_for_hba_ready(scsi_qla_host_t *vha)
86fbee86 1229{
86fbee86 1230 struct qla_hw_data *ha = vha->hw;
783e0dc4 1231 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
86fbee86 1232
1d483901
DC		 1233 while ((qla2x00_reset_active(vha) || ha->dpc_active ||
1234 ha->flags.mbox_busy) ||
1235 test_bit(FX00_RESET_RECOVERY, &vha->dpc_flags) ||
1236 test_bit(FX00_TARGET_SCAN, &vha->dpc_flags)) {
1237 if (test_bit(UNLOADING, &base_vha->dpc_flags))
1238 break;
86fbee86 1239 msleep(1000);
783e0dc4 1240 }
86fbee86
LC		 1241}
1242
2533cf67
LC		 1243int
1244qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha)
1245{
1246 int return_status;
1247 unsigned long wait_reset;
1248 struct qla_hw_data *ha = vha->hw;
1249 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1250
1251 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ);
1252 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
1253 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
1254 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
1255 ha->dpc_active) && time_before(jiffies, wait_reset)) {
1256
1257 msleep(1000);
1258
1259 if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) &&
1260 ha->flags.chip_reset_done)
1261 break;
1262 }
1263 if (ha->flags.chip_reset_done)
1264 return_status = QLA_SUCCESS;
1265 else
1266 return_status = QLA_FUNCTION_FAILED;
1267
1268 return return_status;
1269}
1270
585def9b 1271static int
083a469d
GM		 1272sp_get(struct srb *sp)
1273{
585def9b
QT		 1274 if (!refcount_inc_not_zero((refcount_t*)&sp->ref_count))
1275 /* kref get fail */
1276 return ENXIO;
1277 else
1278 return 0;
083a469d
GM		 1279}
1280
a465537a
SC		 1281#define ISP_REG_DISCONNECT 0xffffffffU
1282/**************************************************************************
1283* qla2x00_isp_reg_stat
1284*
1285* Description:
1286* Read the host status register of ISP before aborting the command.
1287*
1288* Input:
1289* ha = pointer to host adapter structure.
1290*
1291*
1292* Returns:
1293* Either true or false.
1294*
1295* Note: Return true if there is register disconnect.
1296**************************************************************************/
1297static inline
1298uint32_t qla2x00_isp_reg_stat(struct qla_hw_data *ha)
1299{
1300 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
bf6061b1 1301 struct device_reg_82xx __iomem *reg82 = &ha->iobase->isp82;
a465537a 1302
bf6061b1
SC		 1303 if (IS_P3P_TYPE(ha))
1304 return ((RD_REG_DWORD(&reg82->host_int)) == ISP_REG_DISCONNECT);
1305 else
1306 return ((RD_REG_DWORD(&reg->host_status)) ==
1307 ISP_REG_DISCONNECT);
a465537a
SC		 1308}
1309
1da177e4
LT		 1310/**************************************************************************
1311* qla2xxx_eh_abort
1312*
1313* Description:
1314* The abort function will abort the specified command.
1315*
1316* Input:
1317* cmd = Linux SCSI command packet to be aborted.
1318*
1319* Returns:
1320* Either SUCCESS or FAILED.
1321*
1322* Note:
2ea00202 1323* Only return FAILED if command not returned by firmware.
1da177e4 1324**************************************************************************/
e5f82ab8 1325static int
1da177e4
LT		 1326qla2xxx_eh_abort(struct scsi_cmnd *cmd)
1327{
e315cd28 1328 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
f4f051eb 1329 srb_t *sp;
4e98d3b8 1330 int ret;
9cb78c16
HR		 1331 unsigned int id;
1332 uint64_t lun;
18e144d3 1333 unsigned long flags;
f934c9d0 1334 int rval, wait = 0;
e315cd28 1335 struct qla_hw_data *ha = vha->hw;
585def9b 1336 struct qla_qpair *qpair;
1da177e4 1337
a465537a
SC		 1338 if (qla2x00_isp_reg_stat(ha)) {
1339 ql_log(ql_log_info, vha, 0x8042,
1340 "PCI/Register disconnect, exiting.\n");
1341 return FAILED;
1342 }
1da177e4 1343
4e98d3b8
AV		 1344 ret = fc_block_scsi_eh(cmd);
1345 if (ret != 0)
1346 return ret;
1347 ret = SUCCESS;
1348
170babc3 1349 sp = (srb_t *) CMD_SP(cmd);
585def9b
QT		 1350 if (!sp)
1351 return SUCCESS;
1352
1353 qpair = sp->qpair;
1354 if (!qpair)
1355 return SUCCESS;
1356
1357 spin_lock_irqsave(qpair->qp_lock_ptr, flags);
1358 if (!CMD_SP(cmd)) {
1359 /* there's a chance an interrupt could clear
1360 the ptr as part of done & free */
1361 spin_unlock_irqrestore(qpair->qp_lock_ptr, flags);
170babc3
MC		 1362 return SUCCESS;
1363 }
1da177e4 1364
585def9b
QT		 1365 if (sp_get(sp)){
1366 /* ref_count is already 0 */
1367 spin_unlock_irqrestore(qpair->qp_lock_ptr, flags);
170babc3
MC		 1368 return SUCCESS;
1369 }
585def9b
QT		 1370 spin_unlock_irqrestore(qpair->qp_lock_ptr, flags);
1371
1372 id = cmd->device->id;
1373 lun = cmd->device->lun;
1da177e4 1374
7c3df132 1375 ql_dbg(ql_dbg_taskm, vha, 0x8002,
c7bc4cae
CD		 1376 "Aborting from RISC nexus=%ld:%d:%llu sp=%p cmd=%p handle=%x\n",
1377 vha->host_no, id, lun, sp, cmd, sp->handle);
17d98630 1378
170babc3 1379 /* Get a reference to the sp and drop the lock.*/
083a469d 1380
f934c9d0
CD		 1381 rval = ha->isp_ops->abort_command(sp);
1382 if (rval) {
96219424 1383 if (rval == QLA_FUNCTION_PARAMETER_ERROR)
f934c9d0 1384 ret = SUCCESS;
96219424 1385 else
f934c9d0
CD		 1386 ret = FAILED;
1387
7c3df132 1388 ql_dbg(ql_dbg_taskm, vha, 0x8003,
f934c9d0 1389 "Abort command mbx failed cmd=%p, rval=%x.\n", cmd, rval);
170babc3 1390 } else {
7c3df132 1391 ql_dbg(ql_dbg_taskm, vha, 0x8004,
cfb0919c 1392 "Abort command mbx success cmd=%p.\n", cmd);
170babc3
MC		 1393 wait = 1;
1394 }
75942064 1395
585def9b
QT		 1396 spin_lock_irqsave(qpair->qp_lock_ptr, flags);
1397 /*
1398 * Clear the slot in the oustanding_cmds array if we can't find the
1399 * command to reclaim the resources.
1400 */
1401 if (rval == QLA_FUNCTION_PARAMETER_ERROR)
1402 vha->req->outstanding_cmds[sp->handle] = NULL;
1403
1404 /*
1405 * sp->done will do ref_count--
1406 * sp_get() took an extra count above
1407 */
1408 sp->done(sp, DID_RESET << 16);
1da177e4 1409
bc91ade9
CD		 1410 /* Did the command return during mailbox execution? */
1411 if (ret == FAILED && !CMD_SP(cmd))
1412 ret = SUCCESS;
1413
585def9b
QT		 1414 if (!CMD_SP(cmd))
1415 wait = 0;
1416
1417 spin_unlock_irqrestore(qpair->qp_lock_ptr, flags);
1418
f4f051eb 1419 /* Wait for the command to be returned. */
2ea00202 1420 if (wait) {
e315cd28 1421 if (qla2x00_eh_wait_on_command(cmd) != QLA_SUCCESS) {
7c3df132 1422 ql_log(ql_log_warn, vha, 0x8006,
cfb0919c 1423 "Abort handler timed out cmd=%p.\n", cmd);
2ea00202 1424 ret = FAILED;
f4f051eb 1425 }
1da177e4 1426 }
1da177e4 1427
7c3df132 1428 ql_log(ql_log_info, vha, 0x801c,
9cb78c16 1429 "Abort command issued nexus=%ld:%d:%llu -- %d %x.\n",
cfb0919c 1430 vha->host_no, id, lun, wait, ret);
1da177e4 1431
f4f051eb 1432 return ret;
1433}
1da177e4 1434
4d78c973 1435int
e315cd28 1436qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t,
9cb78c16 1437 uint64_t l, enum nexus_wait_type type)
f4f051eb 1438{
17d98630 1439 int cnt, match, status;
18e144d3 1440 unsigned long flags;
e315cd28 1441 struct qla_hw_data *ha = vha->hw;
73208dfd 1442 struct req_que *req;
4d78c973 1443 srb_t *sp;
9ba56b95 1444 struct scsi_cmnd *cmd;
1da177e4 1445
523ec773 1446 status = QLA_SUCCESS;
17d98630 1447
e315cd28 1448 spin_lock_irqsave(&ha->hardware_lock, flags);
67c2e93a 1449 req = vha->req;
17d98630 1450 for (cnt = 1; status == QLA_SUCCESS &&
8d93f550 1451 cnt < req->num_outstanding_cmds; cnt++) {
17d98630
AC		 1452 sp = req->outstanding_cmds[cnt];
1453 if (!sp)
523ec773 1454 continue;
9ba56b95 1455 if (sp->type != SRB_SCSI_CMD)
cf53b069 1456 continue;
25ff6af1 1457 if (vha->vp_idx != sp->vha->vp_idx)
17d98630
AC		 1458 continue;
1459 match = 0;
9ba56b95 1460 cmd = GET_CMD_SP(sp);
17d98630
AC		 1461 switch (type) {
1462 case WAIT_HOST:
1463 match = 1;
1464 break;
1465 case WAIT_TARGET:
9ba56b95 1466 match = cmd->device->id == t;
17d98630
AC		 1467 break;
1468 case WAIT_LUN:
9ba56b95
GM		 1469 match = (cmd->device->id == t &&
1470 cmd->device->lun == l);
17d98630 1471 break;
73208dfd 1472 }
17d98630
AC		 1473 if (!match)
1474 continue;
1475
1476 spin_unlock_irqrestore(&ha->hardware_lock, flags);
9ba56b95 1477 status = qla2x00_eh_wait_on_command(cmd);
17d98630 1478 spin_lock_irqsave(&ha->hardware_lock, flags);
1da177e4 1479 }
e315cd28 1480 spin_unlock_irqrestore(&ha->hardware_lock, flags);
523ec773
AV		 1481
1482 return status;
1da177e4
LT		 1483}
1484
523ec773
AV		 1485static char *reset_errors[] = {
1486 "HBA not online",
1487 "HBA not ready",
1488 "Task management failed",
1489 "Waiting for command completions",
1490};
1da177e4 1491
e5f82ab8 1492static int
523ec773 1493__qla2xxx_eh_generic_reset(char *name, enum nexus_wait_type type,
9cb78c16 1494 struct scsi_cmnd *cmd, int (*do_reset)(struct fc_port *, uint64_t, int))
1da177e4 1495{
e315cd28 1496 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
bdf79621 1497 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
523ec773 1498 int err;
1da177e4 1499
7c3df132 1500 if (!fcport) {
523ec773 1501 return FAILED;
7c3df132 1502 }
1da177e4 1503
4e98d3b8
AV		 1504 err = fc_block_scsi_eh(cmd);
1505 if (err != 0)
1506 return err;
1507
7c3df132 1508 ql_log(ql_log_info, vha, 0x8009,
9cb78c16 1509 "%s RESET ISSUED nexus=%ld:%d:%llu cmd=%p.\n", name, vha->host_no,
7c3df132 1510 cmd->device->id, cmd->device->lun, cmd);
1da177e4 1511
523ec773 1512 err = 0;
7c3df132
SK		 1513 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1514 ql_log(ql_log_warn, vha, 0x800a,
1515 "Wait for hba online failed for cmd=%p.\n", cmd);
523ec773 1516 goto eh_reset_failed;
7c3df132 1517 }
523ec773 1518 err = 2;
9cf2bab6 1519 if (do_reset(fcport, cmd->device->lun, blk_mq_rq_cpu(cmd->request) + 1)
7c3df132
SK		 1520 != QLA_SUCCESS) {
1521 ql_log(ql_log_warn, vha, 0x800c,
1522 "do_reset failed for cmd=%p.\n", cmd);
523ec773 1523 goto eh_reset_failed;
7c3df132 1524 }
523ec773 1525 err = 3;
e315cd28 1526 if (qla2x00_eh_wait_for_pending_commands(vha, cmd->device->id,
7c3df132
SK		 1527 cmd->device->lun, type) != QLA_SUCCESS) {
1528 ql_log(ql_log_warn, vha, 0x800d,
d6a03581 1529 "wait for pending cmds failed for cmd=%p.\n", cmd);
523ec773 1530 goto eh_reset_failed;
7c3df132 1531 }
523ec773 1532
7c3df132 1533 ql_log(ql_log_info, vha, 0x800e,
9cb78c16 1534 "%s RESET SUCCEEDED nexus:%ld:%d:%llu cmd=%p.\n", name,
cfb0919c 1535 vha->host_no, cmd->device->id, cmd->device->lun, cmd);
523ec773
AV		 1536
1537 return SUCCESS;
1538
4d78c973 1539eh_reset_failed:
7c3df132 1540 ql_log(ql_log_info, vha, 0x800f,
9cb78c16 1541 "%s RESET FAILED: %s nexus=%ld:%d:%llu cmd=%p.\n", name,
cfb0919c
CD		 1542 reset_errors[err], vha->host_no, cmd->device->id, cmd->device->lun,
1543 cmd);
523ec773
AV		 1544 return FAILED;
1545}
1da177e4 1546
523ec773
AV		 1547static int
1548qla2xxx_eh_device_reset(struct scsi_cmnd *cmd)
1549{
e315cd28
AC		 1550 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1551 struct qla_hw_data *ha = vha->hw;
1da177e4 1552
a465537a
SC		 1553 if (qla2x00_isp_reg_stat(ha)) {
1554 ql_log(ql_log_info, vha, 0x803e,
1555 "PCI/Register disconnect, exiting.\n");
1556 return FAILED;
1557 }
1558
523ec773
AV		 1559 return __qla2xxx_eh_generic_reset("DEVICE", WAIT_LUN, cmd,
1560 ha->isp_ops->lun_reset);
1da177e4
LT		 1561}
1562
1da177e4 1563static int
523ec773 1564qla2xxx_eh_target_reset(struct scsi_cmnd *cmd)
1da177e4 1565{
e315cd28
AC		 1566 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1567 struct qla_hw_data *ha = vha->hw;
1da177e4 1568
a465537a
SC		 1569 if (qla2x00_isp_reg_stat(ha)) {
1570 ql_log(ql_log_info, vha, 0x803f,
1571 "PCI/Register disconnect, exiting.\n");
1572 return FAILED;
1573 }
1574
523ec773
AV		 1575 return __qla2xxx_eh_generic_reset("TARGET", WAIT_TARGET, cmd,
1576 ha->isp_ops->target_reset);
1da177e4
LT		 1577}
1578
1da177e4
LT		 1579/**************************************************************************
1580* qla2xxx_eh_bus_reset
1581*
1582* Description:
1583* The bus reset function will reset the bus and abort any executing
1584* commands.
1585*
1586* Input:
1587* cmd = Linux SCSI command packet of the command that cause the
1588* bus reset.
1589*
1590* Returns:
1591* SUCCESS/FAILURE (defined as macro in scsi.h).
1592*
1593**************************************************************************/
e5f82ab8 1594static int
1da177e4
LT		 1595qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd)
1596{
e315cd28 1597 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
bdf79621 1598 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
2c3dfe3f 1599 int ret = FAILED;
9cb78c16
HR		 1600 unsigned int id;
1601 uint64_t lun;
a465537a
SC		 1602 struct qla_hw_data *ha = vha->hw;
1603
1604 if (qla2x00_isp_reg_stat(ha)) {
1605 ql_log(ql_log_info, vha, 0x8040,
1606 "PCI/Register disconnect, exiting.\n");
1607 return FAILED;
1608 }
f4f051eb 1609
f4f051eb 1610 id = cmd->device->id;
1611 lun = cmd->device->lun;
1da177e4 1612
7c3df132 1613 if (!fcport) {
f4f051eb 1614 return ret;
7c3df132 1615 }
1da177e4 1616
4e98d3b8
AV		 1617 ret = fc_block_scsi_eh(cmd);
1618 if (ret != 0)
1619 return ret;
1620 ret = FAILED;
1621
7c3df132 1622 ql_log(ql_log_info, vha, 0x8012,
9cb78c16 1623 "BUS RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun);
1da177e4 1624
e315cd28 1625 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
7c3df132
SK		 1626 ql_log(ql_log_fatal, vha, 0x8013,
1627 "Wait for hba online failed board disabled.\n");
f4f051eb 1628 goto eh_bus_reset_done;
1da177e4
LT		 1629 }
1630
ad537689
SK		 1631 if (qla2x00_loop_reset(vha) == QLA_SUCCESS)
1632 ret = SUCCESS;
1633
f4f051eb 1634 if (ret == FAILED)
1635 goto eh_bus_reset_done;
1da177e4 1636
9a41a62b 1637 /* Flush outstanding commands. */
4d78c973 1638 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) !=
7c3df132
SK		 1639 QLA_SUCCESS) {
1640 ql_log(ql_log_warn, vha, 0x8014,
1641 "Wait for pending commands failed.\n");
9a41a62b 1642 ret = FAILED;
7c3df132 1643 }
1da177e4 1644
f4f051eb 1645eh_bus_reset_done:
7c3df132 1646 ql_log(ql_log_warn, vha, 0x802b,
9cb78c16 1647 "BUS RESET %s nexus=%ld:%d:%llu.\n",
d6a03581 1648 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1da177e4 1649
f4f051eb 1650 return ret;
1da177e4
LT		 1651}
1652
1653/**************************************************************************
1654* qla2xxx_eh_host_reset
1655*
1656* Description:
1657* The reset function will reset the Adapter.
1658*
1659* Input:
1660* cmd = Linux SCSI command packet of the command that cause the
1661* adapter reset.
1662*
1663* Returns:
1664* Either SUCCESS or FAILED.
1665*
1666* Note:
1667**************************************************************************/
e5f82ab8 1668static int
1da177e4
LT		 1669qla2xxx_eh_host_reset(struct scsi_cmnd *cmd)
1670{
e315cd28 1671 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
e315cd28 1672 struct qla_hw_data *ha = vha->hw;
2c3dfe3f 1673 int ret = FAILED;
9cb78c16
HR		 1674 unsigned int id;
1675 uint64_t lun;
e315cd28 1676 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4 1677
a465537a
SC		 1678 if (qla2x00_isp_reg_stat(ha)) {
1679 ql_log(ql_log_info, vha, 0x8041,
1680 "PCI/Register disconnect, exiting.\n");
1681 schedule_work(&ha->board_disable);
1682 return SUCCESS;
1683 }
1684
f4f051eb 1685 id = cmd->device->id;
1686 lun = cmd->device->lun;
f4f051eb 1687
7c3df132 1688 ql_log(ql_log_info, vha, 0x8018,
9cb78c16 1689 "ADAPTER RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun);
1da177e4 1690
63ee7072
CD		 1691 /*
1692 * No point in issuing another reset if one is active. Also do not
1693 * attempt a reset if we are updating flash.
1694 */
1695 if (qla2x00_reset_active(vha) || ha->optrom_state != QLA_SWAITING)
f4f051eb 1696 goto eh_host_reset_lock;
1da177e4 1697
e315cd28
AC		 1698 if (vha != base_vha) {
1699 if (qla2x00_vp_abort_isp(vha))
f4f051eb 1700 goto eh_host_reset_lock;
e315cd28 1701 } else {
7ec0effd 1702 if (IS_P3P_TYPE(vha->hw)) {
a9083016
GM		 1703 if (!qla82xx_fcoe_ctx_reset(vha)) {
1704 /* Ctx reset success */
1705 ret = SUCCESS;
1706 goto eh_host_reset_lock;
1707 }
1708 /* fall thru if ctx reset failed */
1709 }
68ca949c
AC		 1710 if (ha->wq)
1711 flush_workqueue(ha->wq);
1712
e315cd28 1713 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
a9083016 1714 if (ha->isp_ops->abort_isp(base_vha)) {
e315cd28
AC		 1715 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1716 /* failed. schedule dpc to try */
1717 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
1718
7c3df132
SK		 1719 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1720 ql_log(ql_log_warn, vha, 0x802a,
1721 "wait for hba online failed.\n");
e315cd28 1722 goto eh_host_reset_lock;
7c3df132 1723 }
e315cd28
AC		 1724 }
1725 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
fa2a1ce5 1726 }
1da177e4 1727
e315cd28 1728 /* Waiting for command to be returned to OS.*/
4d78c973 1729 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) ==
e315cd28 1730 QLA_SUCCESS)
f4f051eb 1731 ret = SUCCESS;
1da177e4 1732
f4f051eb 1733eh_host_reset_lock:
cfb0919c 1734 ql_log(ql_log_info, vha, 0x8017,
9cb78c16 1735 "ADAPTER RESET %s nexus=%ld:%d:%llu.\n",
cfb0919c 1736 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1da177e4 1737
f4f051eb 1738 return ret;
1739}
1da177e4
LT		 1740
1741/*
1742* qla2x00_loop_reset
1743* Issue loop reset.
1744*
1745* Input:
1746* ha = adapter block pointer.
1747*
1748* Returns:
1749* 0 = success
1750*/
a4722cf2 1751int
e315cd28 1752qla2x00_loop_reset(scsi_qla_host_t *vha)
1da177e4 1753{
0c8c39af 1754 int ret;
bdf79621 1755 struct fc_port *fcport;
e315cd28 1756 struct qla_hw_data *ha = vha->hw;
1da177e4 1757
5854771e
AB		 1758 if (IS_QLAFX00(ha)) {
1759 return qlafx00_loop_reset(vha);
1760 }
1761
f4c496c1 1762 if (ql2xtargetreset == 1 && ha->flags.enable_target_reset) {
55e5ed27
AV		 1763 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1764 if (fcport->port_type != FCT_TARGET)
1765 continue;
1766
1767 ret = ha->isp_ops->target_reset(fcport, 0, 0);
1768 if (ret != QLA_SUCCESS) {
7c3df132 1769 ql_dbg(ql_dbg_taskm, vha, 0x802c,
5854771e 1770 "Bus Reset failed: Reset=%d "
7c3df132 1771 "d_id=%x.\n", ret, fcport->d_id.b24);
55e5ed27
AV		 1772 }
1773 }
1774 }
1775
8ae6d9c7 1776
6246b8a1 1777 if (ha->flags.enable_lip_full_login && !IS_CNA_CAPABLE(ha)) {
0b7e7c53
AV		 1778 atomic_set(&vha->loop_state, LOOP_DOWN);
1779 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
1780 qla2x00_mark_all_devices_lost(vha, 0);
e315cd28 1781 ret = qla2x00_full_login_lip(vha);
0c8c39af 1782 if (ret != QLA_SUCCESS) {
7c3df132
SK		 1783 ql_dbg(ql_dbg_taskm, vha, 0x802d,
1784 "full_login_lip=%d.\n", ret);
749af3d5 1785 }
0c8c39af
AV		 1786 }
1787
0d6e61bc 1788 if (ha->flags.enable_lip_reset) {
e315cd28 1789 ret = qla2x00_lip_reset(vha);
ad537689 1790 if (ret != QLA_SUCCESS)
7c3df132
SK		 1791 ql_dbg(ql_dbg_taskm, vha, 0x802e,
1792 "lip_reset failed (%d).\n", ret);
1da177e4
LT		 1793 }
1794
1da177e4 1795 /* Issue marker command only when we are going to start the I/O */
e315cd28 1796 vha->marker_needed = 1;
1da177e4 1797
0c8c39af 1798 return QLA_SUCCESS;
1da177e4
LT		 1799}
1800
c4e521b6
BVA		 1801static void qla2x00_abort_srb(struct qla_qpair *qp, srb_t *sp, const int res,
1802 unsigned long *flags)
1803 __releases(qp->qp_lock_ptr)
1804 __acquires(qp->qp_lock_ptr)
1805{
1806 scsi_qla_host_t *vha = qp->vha;
1807 struct qla_hw_data *ha = vha->hw;
1808
1809 if (sp->type == SRB_NVME_CMD || sp->type == SRB_NVME_LS) {
1810 if (!sp_get(sp)) {
1811 /* got sp */
1812 spin_unlock_irqrestore(qp->qp_lock_ptr, *flags);
1813 qla_nvme_abort(ha, sp, res);
1814 spin_lock_irqsave(qp->qp_lock_ptr, *flags);
1815 }
1816 } else if (GET_CMD_SP(sp) && !ha->flags.eeh_busy &&
1817 !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) &&
1818 !qla2x00_isp_reg_stat(ha) && sp->type == SRB_SCSI_CMD) {
1819 /*
1820 * Don't abort commands in adapter during EEH recovery as it's
1821 * not accessible/responding.
1822 *
1823 * Get a reference to the sp and drop the lock. The reference
1824 * ensures this sp->done() call and not the call in
1825 * qla2xxx_eh_abort() ends the SCSI cmd (with result 'res').
1826 */
1827 if (!sp_get(sp)) {
938edb8a
LT		 1828 int status;
1829
c4e521b6 1830 spin_unlock_irqrestore(qp->qp_lock_ptr, *flags);
938edb8a 1831 status = qla2xxx_eh_abort(GET_CMD_SP(sp));
c4e521b6 1832 spin_lock_irqsave(qp->qp_lock_ptr, *flags);
938edb8a
LT		 1833 /*
1834 * Get rid of extra reference caused
1835 * by early exit from qla2xxx_eh_abort
1836 */
1837 if (status == FAST_IO_FAIL)
1838 atomic_dec(&sp->ref_count);
c4e521b6
BVA		 1839 }
1840 }
1841 sp->done(sp, res);
1842}
1843
bbead493
QT		 1844static void
1845__qla2x00_abort_all_cmds(struct qla_qpair *qp, int res)
df4bf0bb 1846{
eb023220 1847 int cnt;
df4bf0bb
AV		 1848 unsigned long flags;
1849 srb_t *sp;
bbead493 1850 scsi_qla_host_t *vha = qp->vha;
e315cd28 1851 struct qla_hw_data *ha = vha->hw;
73208dfd 1852 struct req_que *req;
c5419e26
QT		 1853 struct qla_tgt *tgt = vha->vha_tgt.qla_tgt;
1854 struct qla_tgt_cmd *cmd;
c0cb4496 1855
6a2cf8d3
BK		 1856 if (!ha->req_q_map)
1857 return;
bbead493
QT		 1858 spin_lock_irqsave(qp->qp_lock_ptr, flags);
1859 req = qp->req;
1860 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) {
1861 sp = req->outstanding_cmds[cnt];
1862 if (sp) {
1863 req->outstanding_cmds[cnt] = NULL;
6b0431d6
QT		 1864 switch (sp->cmd_type) {
1865 case TYPE_SRB:
c4e521b6 1866 qla2x00_abort_srb(qp, sp, res, &flags);
585def9b
QT		 1867 break;
1868 case TYPE_TGT_CMD:
bbead493
QT		 1869 if (!vha->hw->tgt.tgt_ops || !tgt ||
1870 qla_ini_mode_enabled(vha)) {
585def9b
QT		 1871 ql_dbg(ql_dbg_tgt_mgt, vha, 0xf003,
1872 "HOST-ABORT-HNDLR: dpc_flags=%lx. Target mode disabled\n",
1873 vha->dpc_flags);
bbead493 1874 continue;
c733ab35 1875 }
bbead493
QT		 1876 cmd = (struct qla_tgt_cmd *)sp;
1877 qlt_abort_cmd_on_host_reset(cmd->vha, cmd);
585def9b
QT		 1878 break;
1879 case TYPE_TGT_TMCMD:
1880 /*
1881 * Currently, only ABTS response gets on the
1882 * outstanding_cmds[]
1883 */
1884 ha->tgt.tgt_ops->free_mcmd(
1885 (struct qla_tgt_mgmt_cmd *)sp);
1886 break;
1887 default:
1888 break;
73208dfd 1889 }
df4bf0bb
AV		 1890 }
1891 }
bbead493
QT		 1892 spin_unlock_irqrestore(qp->qp_lock_ptr, flags);
1893}
1894
1895void
1896qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res)
1897{
1898 int que;
1899 struct qla_hw_data *ha = vha->hw;
1900
1901 __qla2x00_abort_all_cmds(ha->base_qpair, res);
1902
1903 for (que = 0; que < ha->max_qpairs; que++) {
1904 if (!ha->queue_pair_map[que])
1905 continue;
1906
1907 __qla2x00_abort_all_cmds(ha->queue_pair_map[que], res);
1908 }
df4bf0bb
AV		 1909}
1910
f4f051eb 1911static int
1912qla2xxx_slave_alloc(struct scsi_device *sdev)
1da177e4 1913{
bdf79621 1914 struct fc_rport *rport = starget_to_rport(scsi_target(sdev));
1da177e4 1915
19a7b4ae 1916 if (!rport || fc_remote_port_chkready(rport))
f4f051eb 1917 return -ENXIO;
bdf79621 1918
19a7b4ae 1919 sdev->hostdata = *(fc_port_t **)rport->dd_data;
1da177e4 1920
f4f051eb 1921 return 0;
1922}
1da177e4 1923
f4f051eb 1924static int
1925qla2xxx_slave_configure(struct scsi_device *sdev)
1926{
e315cd28 1927 scsi_qla_host_t *vha = shost_priv(sdev->host);
2afa19a9 1928 struct req_que *req = vha->req;
8482e118 1929
9e522cd8
AE		 1930 if (IS_T10_PI_CAPABLE(vha->hw))
1931 blk_queue_update_dma_alignment(sdev->request_queue, 0x7);
1932
db5ed4df 1933 scsi_change_queue_depth(sdev, req->max_q_depth);
f4f051eb 1934 return 0;
1935}
1da177e4 1936
f4f051eb 1937static void
1938qla2xxx_slave_destroy(struct scsi_device *sdev)
1939{
1940 sdev->hostdata = NULL;
1da177e4
LT		 1941}
1942
1943/**
1944 * qla2x00_config_dma_addressing() - Configure OS DMA addressing method.
1945 * @ha: HA context
1946 *
1947 * At exit, the @ha's flags.enable_64bit_addressing set to indicated
1948 * supported addressing method.
1949 */
1950static void
53303c42 1951qla2x00_config_dma_addressing(struct qla_hw_data *ha)
1da177e4 1952{
7524f9b9 1953 /* Assume a 32bit DMA mask. */
1da177e4 1954 ha->flags.enable_64bit_addressing = 0;
1da177e4 1955
6a35528a 1956 if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) {
7524f9b9
AV		 1957 /* Any upper-dword bits set? */
1958 if (MSD(dma_get_required_mask(&ha->pdev->dev)) &&
6a35528a 1959 !pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(64))) {
7524f9b9 1960 /* Ok, a 64bit DMA mask is applicable. */
1da177e4 1961 ha->flags.enable_64bit_addressing = 1;
fd34f556
AV		 1962 ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64;
1963 ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64;
7524f9b9 1964 return;
1da177e4 1965 }
1da177e4 1966 }
7524f9b9 1967
284901a9
YH		 1968 dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32));
1969 pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(32));
1da177e4
LT		 1970}
1971
fd34f556 1972static void
e315cd28 1973qla2x00_enable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1974{
1975 unsigned long flags = 0;
1976 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1977
1978 spin_lock_irqsave(&ha->hardware_lock, flags);
1979 ha->interrupts_on = 1;
1980 /* enable risc and host interrupts */
1981 WRT_REG_WORD(&reg->ictrl, ICR_EN_INT | ICR_EN_RISC);
1982 RD_REG_WORD(&reg->ictrl);
1983 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1984
1985}
1986
1987static void
e315cd28 1988qla2x00_disable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1989{
1990 unsigned long flags = 0;
1991 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1992
1993 spin_lock_irqsave(&ha->hardware_lock, flags);
1994 ha->interrupts_on = 0;
1995 /* disable risc and host interrupts */
1996 WRT_REG_WORD(&reg->ictrl, 0);
1997 RD_REG_WORD(&reg->ictrl);
1998 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1999}
2000
2001static void
e315cd28 2002qla24xx_enable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 2003{
2004 unsigned long flags = 0;
2005 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
2006
2007 spin_lock_irqsave(&ha->hardware_lock, flags);
2008 ha->interrupts_on = 1;
2009 WRT_REG_DWORD(&reg->ictrl, ICRX_EN_RISC_INT);
2010 RD_REG_DWORD(&reg->ictrl);
2011 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2012}
2013
2014static void
e315cd28 2015qla24xx_disable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 2016{
2017 unsigned long flags = 0;
2018 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
2019
124f85e6
AV		 2020 if (IS_NOPOLLING_TYPE(ha))
2021 return;
fd34f556
AV		 2022 spin_lock_irqsave(&ha->hardware_lock, flags);
2023 ha->interrupts_on = 0;
2024 WRT_REG_DWORD(&reg->ictrl, 0);
2025 RD_REG_DWORD(&reg->ictrl);
2026 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2027}
2028
706f457d
GM		 2029static int
2030qla2x00_iospace_config(struct qla_hw_data *ha)
2031{
2032 resource_size_t pio;
2033 uint16_t msix;
706f457d 2034
706f457d
GM		 2035 if (pci_request_selected_regions(ha->pdev, ha->bars,
2036 QLA2XXX_DRIVER_NAME)) {
2037 ql_log_pci(ql_log_fatal, ha->pdev, 0x0011,
2038 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
2039 pci_name(ha->pdev));
2040 goto iospace_error_exit;
2041 }
2042 if (!(ha->bars & 1))
2043 goto skip_pio;
2044
2045 /* We only need PIO for Flash operations on ISP2312 v2 chips. */
2046 pio = pci_resource_start(ha->pdev, 0);
2047 if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) {
2048 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
2049 ql_log_pci(ql_log_warn, ha->pdev, 0x0012,
2050 "Invalid pci I/O region size (%s).\n",
2051 pci_name(ha->pdev));
2052 pio = 0;
2053 }
2054 } else {
2055 ql_log_pci(ql_log_warn, ha->pdev, 0x0013,
2056 "Region #0 no a PIO resource (%s).\n",
2057 pci_name(ha->pdev));
2058 pio = 0;
2059 }
2060 ha->pio_address = pio;
2061 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014,
2062 "PIO address=%llu.\n",
2063 (unsigned long long)ha->pio_address);
2064
2065skip_pio:
2066 /* Use MMIO operations for all accesses. */
2067 if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) {
2068 ql_log_pci(ql_log_fatal, ha->pdev, 0x0015,
2069 "Region #1 not an MMIO resource (%s), aborting.\n",
2070 pci_name(ha->pdev));
2071 goto iospace_error_exit;
2072 }
2073 if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) {
2074 ql_log_pci(ql_log_fatal, ha->pdev, 0x0016,
2075 "Invalid PCI mem region size (%s), aborting.\n",
2076 pci_name(ha->pdev));
2077 goto iospace_error_exit;
2078 }
2079
2080 ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN);
2081 if (!ha->iobase) {
2082 ql_log_pci(ql_log_fatal, ha->pdev, 0x0017,
2083 "Cannot remap MMIO (%s), aborting.\n",
2084 pci_name(ha->pdev));
2085 goto iospace_error_exit;
2086 }
2087
2088 /* Determine queue resources */
2089 ha->max_req_queues = ha->max_rsp_queues = 1;
f54f2cb5 2090 ha->msix_count = QLA_BASE_VECTORS;
c38d1baf
HM		 2091 if (!ql2xmqsupport || !ql2xnvmeenable ||
2092 (!IS_QLA25XX(ha) && !IS_QLA81XX(ha)))
706f457d
GM		 2093 goto mqiobase_exit;
2094
2095 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3),
2096 pci_resource_len(ha->pdev, 3));
2097 if (ha->mqiobase) {
2098 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018,
2099 "MQIO Base=%p.\n", ha->mqiobase);
2100 /* Read MSIX vector size of the board */
2101 pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix);
d7459527 2102 ha->msix_count = msix + 1;
706f457d 2103 /* Max queues are bounded by available msix vectors */
d7459527
MH		 2104 /* MB interrupt uses 1 vector */
2105 ha->max_req_queues = ha->msix_count - 1;
2106 ha->max_rsp_queues = ha->max_req_queues;
2107 /* Queue pairs is the max value minus the base queue pair */
2108 ha->max_qpairs = ha->max_rsp_queues - 1;
2109 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0188,
2110 "Max no of queues pairs: %d.\n", ha->max_qpairs);
2111
706f457d 2112 ql_log_pci(ql_log_info, ha->pdev, 0x001a,
d7459527 2113 "MSI-X vector count: %d.\n", ha->msix_count);
706f457d
GM		 2114 } else
2115 ql_log_pci(ql_log_info, ha->pdev, 0x001b,
2116 "BAR 3 not enabled.\n");
2117
2118mqiobase_exit:
706f457d 2119 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c,
f54f2cb5 2120 "MSIX Count: %d.\n", ha->msix_count);
706f457d
GM		 2121 return (0);
2122
2123iospace_error_exit:
2124 return (-ENOMEM);
2125}
2126
2127
6246b8a1
GM		 2128static int
2129qla83xx_iospace_config(struct qla_hw_data *ha)
2130{
2131 uint16_t msix;
6246b8a1
GM		 2132
2133 if (pci_request_selected_regions(ha->pdev, ha->bars,
2134 QLA2XXX_DRIVER_NAME)) {
2135 ql_log_pci(ql_log_fatal, ha->pdev, 0x0117,
2136 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
2137 pci_name(ha->pdev));
2138
2139 goto iospace_error_exit;
2140 }
2141
2142 /* Use MMIO operations for all accesses. */
2143 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) {
2144 ql_log_pci(ql_log_warn, ha->pdev, 0x0118,
2145 "Invalid pci I/O region size (%s).\n",
2146 pci_name(ha->pdev));
2147 goto iospace_error_exit;
2148 }
2149 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
2150 ql_log_pci(ql_log_warn, ha->pdev, 0x0119,
2151 "Invalid PCI mem region size (%s), aborting\n",
2152 pci_name(ha->pdev));
2153 goto iospace_error_exit;
2154 }
2155
2156 ha->iobase = ioremap(pci_resource_start(ha->pdev, 0), MIN_IOBASE_LEN);
2157 if (!ha->iobase) {
2158 ql_log_pci(ql_log_fatal, ha->pdev, 0x011a,
2159 "Cannot remap MMIO (%s), aborting.\n",
2160 pci_name(ha->pdev));
2161 goto iospace_error_exit;
2162 }
2163
2164 /* 64bit PCI BAR - BAR2 will correspoond to region 4 */
2165 /* 83XX 26XX always use MQ type access for queues
2166 * - mbar 2, a.k.a region 4 */
2167 ha->max_req_queues = ha->max_rsp_queues = 1;
f54f2cb5 2168 ha->msix_count = QLA_BASE_VECTORS;
6246b8a1
GM		 2169 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 4),
2170 pci_resource_len(ha->pdev, 4));
2171
2172 if (!ha->mqiobase) {
2173 ql_log_pci(ql_log_fatal, ha->pdev, 0x011d,
2174 "BAR2/region4 not enabled\n");
2175 goto mqiobase_exit;
2176 }
2177
2178 ha->msixbase = ioremap(pci_resource_start(ha->pdev, 2),
2179 pci_resource_len(ha->pdev, 2));
2180 if (ha->msixbase) {
2181 /* Read MSIX vector size of the board */
2182 pci_read_config_word(ha->pdev,
2183 QLA_83XX_PCI_MSIX_CONTROL, &msix);
e326d22a 2184 ha->msix_count = (msix & PCI_MSIX_FLAGS_QSIZE) + 1;
093df737
QT		 2185 /*
2186 * By default, driver uses at least two msix vectors
2187 * (default & rspq)
2188 */
c38d1baf 2189 if (ql2xmqsupport || ql2xnvmeenable) {
d7459527
MH		 2190 /* MB interrupt uses 1 vector */
2191 ha->max_req_queues = ha->msix_count - 1;
093df737
QT		 2192
2193 /* ATIOQ needs 1 vector. That's 1 less QPair */
2194 if (QLA_TGT_MODE_ENABLED())
2195 ha->max_req_queues--;
2196
d0d2c68b
MH		 2197 ha->max_rsp_queues = ha->max_req_queues;
2198
d7459527
MH		 2199 /* Queue pairs is the max value minus
2200 * the base queue pair */
2201 ha->max_qpairs = ha->max_req_queues - 1;
83548fe2 2202 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x00e3,
d7459527 2203 "Max no of queues pairs: %d.\n", ha->max_qpairs);
6246b8a1
GM		 2204 }
2205 ql_log_pci(ql_log_info, ha->pdev, 0x011c,
d7459527 2206 "MSI-X vector count: %d.\n", ha->msix_count);
6246b8a1
GM		 2207 } else
2208 ql_log_pci(ql_log_info, ha->pdev, 0x011e,
2209 "BAR 1 not enabled.\n");
2210
2211mqiobase_exit:
6246b8a1 2212 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011f,
f54f2cb5 2213 "MSIX Count: %d.\n", ha->msix_count);
6246b8a1
GM		 2214 return 0;
2215
2216iospace_error_exit:
2217 return -ENOMEM;
2218}
2219
fd34f556
AV		 2220static struct isp_operations qla2100_isp_ops = {
2221 .pci_config = qla2100_pci_config,
2222 .reset_chip = qla2x00_reset_chip,
2223 .chip_diag = qla2x00_chip_diag,
2224 .config_rings = qla2x00_config_rings,
2225 .reset_adapter = qla2x00_reset_adapter,
2226 .nvram_config = qla2x00_nvram_config,
2227 .update_fw_options = qla2x00_update_fw_options,
2228 .load_risc = qla2x00_load_risc,
2229 .pci_info_str = qla2x00_pci_info_str,
2230 .fw_version_str = qla2x00_fw_version_str,
2231 .intr_handler = qla2100_intr_handler,
2232 .enable_intrs = qla2x00_enable_intrs,
2233 .disable_intrs = qla2x00_disable_intrs,
2234 .abort_command = qla2x00_abort_command,
523ec773
AV		 2235 .target_reset = qla2x00_abort_target,
2236 .lun_reset = qla2x00_lun_reset,
fd34f556
AV		 2237 .fabric_login = qla2x00_login_fabric,
2238 .fabric_logout = qla2x00_fabric_logout,
2239 .calc_req_entries = qla2x00_calc_iocbs_32,
2240 .build_iocbs = qla2x00_build_scsi_iocbs_32,
2241 .prep_ms_iocb = qla2x00_prep_ms_iocb,
2242 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
2243 .read_nvram = qla2x00_read_nvram_data,
2244 .write_nvram = qla2x00_write_nvram_data,
2245 .fw_dump = qla2100_fw_dump,
2246 .beacon_on = NULL,
2247 .beacon_off = NULL,
2248 .beacon_blink = NULL,
2249 .read_optrom = qla2x00_read_optrom_data,
2250 .write_optrom = qla2x00_write_optrom_data,
2251 .get_flash_version = qla2x00_get_flash_version,
e315cd28 2252 .start_scsi = qla2x00_start_scsi,
d7459527 2253 .start_scsi_mq = NULL,
a9083016 2254 .abort_isp = qla2x00_abort_isp,
706f457d 2255 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2256 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 2257};
2258
2259static struct isp_operations qla2300_isp_ops = {
2260 .pci_config = qla2300_pci_config,
2261 .reset_chip = qla2x00_reset_chip,
2262 .chip_diag = qla2x00_chip_diag,
2263 .config_rings = qla2x00_config_rings,
2264 .reset_adapter = qla2x00_reset_adapter,
2265 .nvram_config = qla2x00_nvram_config,
2266 .update_fw_options = qla2x00_update_fw_options,
2267 .load_risc = qla2x00_load_risc,
2268 .pci_info_str = qla2x00_pci_info_str,
2269 .fw_version_str = qla2x00_fw_version_str,
2270 .intr_handler = qla2300_intr_handler,
2271 .enable_intrs = qla2x00_enable_intrs,
2272 .disable_intrs = qla2x00_disable_intrs,
2273 .abort_command = qla2x00_abort_command,
523ec773
AV		 2274 .target_reset = qla2x00_abort_target,
2275 .lun_reset = qla2x00_lun_reset,
fd34f556
AV		 2276 .fabric_login = qla2x00_login_fabric,
2277 .fabric_logout = qla2x00_fabric_logout,
2278 .calc_req_entries = qla2x00_calc_iocbs_32,
2279 .build_iocbs = qla2x00_build_scsi_iocbs_32,
2280 .prep_ms_iocb = qla2x00_prep_ms_iocb,
2281 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
2282 .read_nvram = qla2x00_read_nvram_data,
2283 .write_nvram = qla2x00_write_nvram_data,
2284 .fw_dump = qla2300_fw_dump,
2285 .beacon_on = qla2x00_beacon_on,
2286 .beacon_off = qla2x00_beacon_off,
2287 .beacon_blink = qla2x00_beacon_blink,
2288 .read_optrom = qla2x00_read_optrom_data,
2289 .write_optrom = qla2x00_write_optrom_data,
2290 .get_flash_version = qla2x00_get_flash_version,
e315cd28 2291 .start_scsi = qla2x00_start_scsi,
d7459527 2292 .start_scsi_mq = NULL,
a9083016 2293 .abort_isp = qla2x00_abort_isp,
7ec0effd 2294 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2295 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 2296};
2297
2298static struct isp_operations qla24xx_isp_ops = {
2299 .pci_config = qla24xx_pci_config,
2300 .reset_chip = qla24xx_reset_chip,
2301 .chip_diag = qla24xx_chip_diag,
2302 .config_rings = qla24xx_config_rings,
2303 .reset_adapter = qla24xx_reset_adapter,
2304 .nvram_config = qla24xx_nvram_config,
2305 .update_fw_options = qla24xx_update_fw_options,
2306 .load_risc = qla24xx_load_risc,
2307 .pci_info_str = qla24xx_pci_info_str,
2308 .fw_version_str = qla24xx_fw_version_str,
2309 .intr_handler = qla24xx_intr_handler,
2310 .enable_intrs = qla24xx_enable_intrs,
2311 .disable_intrs = qla24xx_disable_intrs,
2312 .abort_command = qla24xx_abort_command,
523ec773
AV		 2313 .target_reset = qla24xx_abort_target,
2314 .lun_reset = qla24xx_lun_reset,
fd34f556
AV		 2315 .fabric_login = qla24xx_login_fabric,
2316 .fabric_logout = qla24xx_fabric_logout,
2317 .calc_req_entries = NULL,
2318 .build_iocbs = NULL,
2319 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2320 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2321 .read_nvram = qla24xx_read_nvram_data,
2322 .write_nvram = qla24xx_write_nvram_data,
2323 .fw_dump = qla24xx_fw_dump,
2324 .beacon_on = qla24xx_beacon_on,
2325 .beacon_off = qla24xx_beacon_off,
2326 .beacon_blink = qla24xx_beacon_blink,
2327 .read_optrom = qla24xx_read_optrom_data,
2328 .write_optrom = qla24xx_write_optrom_data,
2329 .get_flash_version = qla24xx_get_flash_version,
e315cd28 2330 .start_scsi = qla24xx_start_scsi,
d7459527 2331 .start_scsi_mq = NULL,
a9083016 2332 .abort_isp = qla2x00_abort_isp,
7ec0effd 2333 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2334 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 2335};
2336
c3a2f0df
AV		 2337static struct isp_operations qla25xx_isp_ops = {
2338 .pci_config = qla25xx_pci_config,
2339 .reset_chip = qla24xx_reset_chip,
2340 .chip_diag = qla24xx_chip_diag,
2341 .config_rings = qla24xx_config_rings,
2342 .reset_adapter = qla24xx_reset_adapter,
2343 .nvram_config = qla24xx_nvram_config,
2344 .update_fw_options = qla24xx_update_fw_options,
2345 .load_risc = qla24xx_load_risc,
2346 .pci_info_str = qla24xx_pci_info_str,
2347 .fw_version_str = qla24xx_fw_version_str,
2348 .intr_handler = qla24xx_intr_handler,
2349 .enable_intrs = qla24xx_enable_intrs,
2350 .disable_intrs = qla24xx_disable_intrs,
2351 .abort_command = qla24xx_abort_command,
523ec773
AV		 2352 .target_reset = qla24xx_abort_target,
2353 .lun_reset = qla24xx_lun_reset,
c3a2f0df
AV		 2354 .fabric_login = qla24xx_login_fabric,
2355 .fabric_logout = qla24xx_fabric_logout,
2356 .calc_req_entries = NULL,
2357 .build_iocbs = NULL,
2358 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2359 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2360 .read_nvram = qla25xx_read_nvram_data,
2361 .write_nvram = qla25xx_write_nvram_data,
2362 .fw_dump = qla25xx_fw_dump,
2363 .beacon_on = qla24xx_beacon_on,
2364 .beacon_off = qla24xx_beacon_off,
2365 .beacon_blink = qla24xx_beacon_blink,
338c9161 2366 .read_optrom = qla25xx_read_optrom_data,
c3a2f0df
AV		 2367 .write_optrom = qla24xx_write_optrom_data,
2368 .get_flash_version = qla24xx_get_flash_version,
bad75002 2369 .start_scsi = qla24xx_dif_start_scsi,
d7459527 2370 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
a9083016 2371 .abort_isp = qla2x00_abort_isp,
7ec0effd 2372 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2373 .initialize_adapter = qla2x00_initialize_adapter,
c3a2f0df
AV		 2374};
2375
3a03eb79
AV		 2376static struct isp_operations qla81xx_isp_ops = {
2377 .pci_config = qla25xx_pci_config,
2378 .reset_chip = qla24xx_reset_chip,
2379 .chip_diag = qla24xx_chip_diag,
2380 .config_rings = qla24xx_config_rings,
2381 .reset_adapter = qla24xx_reset_adapter,
2382 .nvram_config = qla81xx_nvram_config,
2383 .update_fw_options = qla81xx_update_fw_options,
eaac30be 2384 .load_risc = qla81xx_load_risc,
3a03eb79
AV		 2385 .pci_info_str = qla24xx_pci_info_str,
2386 .fw_version_str = qla24xx_fw_version_str,
2387 .intr_handler = qla24xx_intr_handler,
2388 .enable_intrs = qla24xx_enable_intrs,
2389 .disable_intrs = qla24xx_disable_intrs,
2390 .abort_command = qla24xx_abort_command,
2391 .target_reset = qla24xx_abort_target,
2392 .lun_reset = qla24xx_lun_reset,
2393 .fabric_login = qla24xx_login_fabric,
2394 .fabric_logout = qla24xx_fabric_logout,
2395 .calc_req_entries = NULL,
2396 .build_iocbs = NULL,
2397 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2398 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
3d79038f
AV		 2399 .read_nvram = NULL,
2400 .write_nvram = NULL,
3a03eb79
AV		 2401 .fw_dump = qla81xx_fw_dump,
2402 .beacon_on = qla24xx_beacon_on,
2403 .beacon_off = qla24xx_beacon_off,
6246b8a1 2404 .beacon_blink = qla83xx_beacon_blink,
3a03eb79
AV		 2405 .read_optrom = qla25xx_read_optrom_data,
2406 .write_optrom = qla24xx_write_optrom_data,
2407 .get_flash_version = qla24xx_get_flash_version,
ba77ef53 2408 .start_scsi = qla24xx_dif_start_scsi,
d7459527 2409 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
a9083016 2410 .abort_isp = qla2x00_abort_isp,
7ec0effd 2411 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2412 .initialize_adapter = qla2x00_initialize_adapter,
a9083016
GM		 2413};
2414
2415static struct isp_operations qla82xx_isp_ops = {
2416 .pci_config = qla82xx_pci_config,
2417 .reset_chip = qla82xx_reset_chip,
2418 .chip_diag = qla24xx_chip_diag,
2419 .config_rings = qla82xx_config_rings,
2420 .reset_adapter = qla24xx_reset_adapter,
2421 .nvram_config = qla81xx_nvram_config,
2422 .update_fw_options = qla24xx_update_fw_options,
2423 .load_risc = qla82xx_load_risc,
9d55ca66 2424 .pci_info_str = qla24xx_pci_info_str,
a9083016
GM		 2425 .fw_version_str = qla24xx_fw_version_str,
2426 .intr_handler = qla82xx_intr_handler,
2427 .enable_intrs = qla82xx_enable_intrs,
2428 .disable_intrs = qla82xx_disable_intrs,
2429 .abort_command = qla24xx_abort_command,
2430 .target_reset = qla24xx_abort_target,
2431 .lun_reset = qla24xx_lun_reset,
2432 .fabric_login = qla24xx_login_fabric,
2433 .fabric_logout = qla24xx_fabric_logout,
2434 .calc_req_entries = NULL,
2435 .build_iocbs = NULL,
2436 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2437 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2438 .read_nvram = qla24xx_read_nvram_data,
2439 .write_nvram = qla24xx_write_nvram_data,
a1b23c5a 2440 .fw_dump = qla82xx_fw_dump,
999916dc
SK		 2441 .beacon_on = qla82xx_beacon_on,
2442 .beacon_off = qla82xx_beacon_off,
2443 .beacon_blink = NULL,
a9083016
GM		 2444 .read_optrom = qla82xx_read_optrom_data,
2445 .write_optrom = qla82xx_write_optrom_data,
7ec0effd 2446 .get_flash_version = qla82xx_get_flash_version,
a9083016 2447 .start_scsi = qla82xx_start_scsi,
d7459527 2448 .start_scsi_mq = NULL,
a9083016 2449 .abort_isp = qla82xx_abort_isp,
706f457d 2450 .iospace_config = qla82xx_iospace_config,
8ae6d9c7 2451 .initialize_adapter = qla2x00_initialize_adapter,
3a03eb79
AV		 2452};
2453
7ec0effd
AD		 2454static struct isp_operations qla8044_isp_ops = {
2455 .pci_config = qla82xx_pci_config,
2456 .reset_chip = qla82xx_reset_chip,
2457 .chip_diag = qla24xx_chip_diag,
2458 .config_rings = qla82xx_config_rings,
2459 .reset_adapter = qla24xx_reset_adapter,
2460 .nvram_config = qla81xx_nvram_config,
2461 .update_fw_options = qla24xx_update_fw_options,
2462 .load_risc = qla82xx_load_risc,
2463 .pci_info_str = qla24xx_pci_info_str,
2464 .fw_version_str = qla24xx_fw_version_str,
2465 .intr_handler = qla8044_intr_handler,
2466 .enable_intrs = qla82xx_enable_intrs,
2467 .disable_intrs = qla82xx_disable_intrs,
2468 .abort_command = qla24xx_abort_command,
2469 .target_reset = qla24xx_abort_target,
2470 .lun_reset = qla24xx_lun_reset,
2471 .fabric_login = qla24xx_login_fabric,
2472 .fabric_logout = qla24xx_fabric_logout,
2473 .calc_req_entries = NULL,
2474 .build_iocbs = NULL,
2475 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2476 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2477 .read_nvram = NULL,
2478 .write_nvram = NULL,
a1b23c5a 2479 .fw_dump = qla8044_fw_dump,
7ec0effd
AD		 2480 .beacon_on = qla82xx_beacon_on,
2481 .beacon_off = qla82xx_beacon_off,
2482 .beacon_blink = NULL,
888e639d 2483 .read_optrom = qla8044_read_optrom_data,
7ec0effd
AD		 2484 .write_optrom = qla8044_write_optrom_data,
2485 .get_flash_version = qla82xx_get_flash_version,
2486 .start_scsi = qla82xx_start_scsi,
d7459527 2487 .start_scsi_mq = NULL,
7ec0effd
AD		 2488 .abort_isp = qla8044_abort_isp,
2489 .iospace_config = qla82xx_iospace_config,
2490 .initialize_adapter = qla2x00_initialize_adapter,
2491};
2492
6246b8a1
GM		 2493static struct isp_operations qla83xx_isp_ops = {
2494 .pci_config = qla25xx_pci_config,
2495 .reset_chip = qla24xx_reset_chip,
2496 .chip_diag = qla24xx_chip_diag,
2497 .config_rings = qla24xx_config_rings,
2498 .reset_adapter = qla24xx_reset_adapter,
2499 .nvram_config = qla81xx_nvram_config,
2500 .update_fw_options = qla81xx_update_fw_options,
2501 .load_risc = qla81xx_load_risc,
2502 .pci_info_str = qla24xx_pci_info_str,
2503 .fw_version_str = qla24xx_fw_version_str,
2504 .intr_handler = qla24xx_intr_handler,
2505 .enable_intrs = qla24xx_enable_intrs,
2506 .disable_intrs = qla24xx_disable_intrs,
2507 .abort_command = qla24xx_abort_command,
2508 .target_reset = qla24xx_abort_target,
2509 .lun_reset = qla24xx_lun_reset,
2510 .fabric_login = qla24xx_login_fabric,
2511 .fabric_logout = qla24xx_fabric_logout,
2512 .calc_req_entries = NULL,
2513 .build_iocbs = NULL,
2514 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2515 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2516 .read_nvram = NULL,
2517 .write_nvram = NULL,
2518 .fw_dump = qla83xx_fw_dump,
2519 .beacon_on = qla24xx_beacon_on,
2520 .beacon_off = qla24xx_beacon_off,
2521 .beacon_blink = qla83xx_beacon_blink,
2522 .read_optrom = qla25xx_read_optrom_data,
2523 .write_optrom = qla24xx_write_optrom_data,
2524 .get_flash_version = qla24xx_get_flash_version,
2525 .start_scsi = qla24xx_dif_start_scsi,
d7459527 2526 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
6246b8a1
GM		 2527 .abort_isp = qla2x00_abort_isp,
2528 .iospace_config = qla83xx_iospace_config,
8ae6d9c7
GM		 2529 .initialize_adapter = qla2x00_initialize_adapter,
2530};
2531
2532static struct isp_operations qlafx00_isp_ops = {
2533 .pci_config = qlafx00_pci_config,
2534 .reset_chip = qlafx00_soft_reset,
2535 .chip_diag = qlafx00_chip_diag,
2536 .config_rings = qlafx00_config_rings,
2537 .reset_adapter = qlafx00_soft_reset,
2538 .nvram_config = NULL,
2539 .update_fw_options = NULL,
2540 .load_risc = NULL,
2541 .pci_info_str = qlafx00_pci_info_str,
2542 .fw_version_str = qlafx00_fw_version_str,
2543 .intr_handler = qlafx00_intr_handler,
2544 .enable_intrs = qlafx00_enable_intrs,
2545 .disable_intrs = qlafx00_disable_intrs,
4440e46d 2546 .abort_command = qla24xx_async_abort_command,
8ae6d9c7
GM		 2547 .target_reset = qlafx00_abort_target,
2548 .lun_reset = qlafx00_lun_reset,
2549 .fabric_login = NULL,
2550 .fabric_logout = NULL,
2551 .calc_req_entries = NULL,
2552 .build_iocbs = NULL,
2553 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2554 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2555 .read_nvram = qla24xx_read_nvram_data,
2556 .write_nvram = qla24xx_write_nvram_data,
2557 .fw_dump = NULL,
2558 .beacon_on = qla24xx_beacon_on,
2559 .beacon_off = qla24xx_beacon_off,
2560 .beacon_blink = NULL,
2561 .read_optrom = qla24xx_read_optrom_data,
2562 .write_optrom = qla24xx_write_optrom_data,
2563 .get_flash_version = qla24xx_get_flash_version,
2564 .start_scsi = qlafx00_start_scsi,
d7459527 2565 .start_scsi_mq = NULL,
8ae6d9c7
GM		 2566 .abort_isp = qlafx00_abort_isp,
2567 .iospace_config = qlafx00_iospace_config,
2568 .initialize_adapter = qlafx00_initialize_adapter,
6246b8a1
GM		 2569};
2570
f73cb695
CD		 2571static struct isp_operations qla27xx_isp_ops = {
2572 .pci_config = qla25xx_pci_config,
2573 .reset_chip = qla24xx_reset_chip,
2574 .chip_diag = qla24xx_chip_diag,
2575 .config_rings = qla24xx_config_rings,
2576 .reset_adapter = qla24xx_reset_adapter,
2577 .nvram_config = qla81xx_nvram_config,
2578 .update_fw_options = qla81xx_update_fw_options,
2579 .load_risc = qla81xx_load_risc,
2580 .pci_info_str = qla24xx_pci_info_str,
2581 .fw_version_str = qla24xx_fw_version_str,
2582 .intr_handler = qla24xx_intr_handler,
2583 .enable_intrs = qla24xx_enable_intrs,
2584 .disable_intrs = qla24xx_disable_intrs,
2585 .abort_command = qla24xx_abort_command,
2586 .target_reset = qla24xx_abort_target,
2587 .lun_reset = qla24xx_lun_reset,
2588 .fabric_login = qla24xx_login_fabric,
2589 .fabric_logout = qla24xx_fabric_logout,
2590 .calc_req_entries = NULL,
2591 .build_iocbs = NULL,
2592 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2593 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2594 .read_nvram = NULL,
2595 .write_nvram = NULL,
2596 .fw_dump = qla27xx_fwdump,
2597 .beacon_on = qla24xx_beacon_on,
2598 .beacon_off = qla24xx_beacon_off,
2599 .beacon_blink = qla83xx_beacon_blink,
2600 .read_optrom = qla25xx_read_optrom_data,
2601 .write_optrom = qla24xx_write_optrom_data,
2602 .get_flash_version = qla24xx_get_flash_version,
2603 .start_scsi = qla24xx_dif_start_scsi,
d7459527 2604 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
f73cb695
CD		 2605 .abort_isp = qla2x00_abort_isp,
2606 .iospace_config = qla83xx_iospace_config,
2607 .initialize_adapter = qla2x00_initialize_adapter,
2608};
2609
ea5b6382 2610static inline void
e315cd28 2611qla2x00_set_isp_flags(struct qla_hw_data *ha)
ea5b6382 2612{
2613 ha->device_type = DT_EXTENDED_IDS;
2614 switch (ha->pdev->device) {
2615 case PCI_DEVICE_ID_QLOGIC_ISP2100:
9e052e2d 2616 ha->isp_type |= DT_ISP2100;
ea5b6382 2617 ha->device_type &= ~DT_EXTENDED_IDS;
441d1072 2618 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
ea5b6382 2619 break;
2620 case PCI_DEVICE_ID_QLOGIC_ISP2200:
9e052e2d 2621 ha->isp_type |= DT_ISP2200;
ea5b6382 2622 ha->device_type &= ~DT_EXTENDED_IDS;
441d1072 2623 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
ea5b6382 2624 break;
2625 case PCI_DEVICE_ID_QLOGIC_ISP2300:
9e052e2d 2626 ha->isp_type |= DT_ISP2300;
4a59f71d 2627 ha->device_type |= DT_ZIO_SUPPORTED;
441d1072 2628 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 2629 break;
2630 case PCI_DEVICE_ID_QLOGIC_ISP2312:
9e052e2d 2631 ha->isp_type |= DT_ISP2312;
4a59f71d 2632 ha->device_type |= DT_ZIO_SUPPORTED;
441d1072 2633 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 2634 break;
2635 case PCI_DEVICE_ID_QLOGIC_ISP2322:
9e052e2d 2636 ha->isp_type |= DT_ISP2322;
4a59f71d 2637 ha->device_type |= DT_ZIO_SUPPORTED;
ea5b6382 2638 if (ha->pdev->subsystem_vendor == 0x1028 &&
2639 ha->pdev->subsystem_device == 0x0170)
2640 ha->device_type |= DT_OEM_001;
441d1072 2641 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 2642 break;
2643 case PCI_DEVICE_ID_QLOGIC_ISP6312:
9e052e2d 2644 ha->isp_type |= DT_ISP6312;
441d1072 2645 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 2646 break;
2647 case PCI_DEVICE_ID_QLOGIC_ISP6322:
9e052e2d 2648 ha->isp_type |= DT_ISP6322;
441d1072 2649 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 2650 break;
2651 case PCI_DEVICE_ID_QLOGIC_ISP2422:
9e052e2d 2652 ha->isp_type |= DT_ISP2422;
4a59f71d 2653 ha->device_type |= DT_ZIO_SUPPORTED;
e428924c 2654 ha->device_type |= DT_FWI2;
c76f2c01 2655 ha->device_type |= DT_IIDMA;
441d1072 2656 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2657 break;
2658 case PCI_DEVICE_ID_QLOGIC_ISP2432:
9e052e2d 2659 ha->isp_type |= DT_ISP2432;
4a59f71d 2660 ha->device_type |= DT_ZIO_SUPPORTED;
e428924c 2661 ha->device_type |= DT_FWI2;
c76f2c01 2662 ha->device_type |= DT_IIDMA;
441d1072 2663 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2664 break;
4d4df193 2665 case PCI_DEVICE_ID_QLOGIC_ISP8432:
9e052e2d 2666 ha->isp_type |= DT_ISP8432;
4d4df193
HK		 2667 ha->device_type |= DT_ZIO_SUPPORTED;
2668 ha->device_type |= DT_FWI2;
2669 ha->device_type |= DT_IIDMA;
2670 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2671 break;
044cc6c8 2672 case PCI_DEVICE_ID_QLOGIC_ISP5422:
9e052e2d 2673 ha->isp_type |= DT_ISP5422;
e428924c 2674 ha->device_type |= DT_FWI2;
441d1072 2675 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2676 break;
044cc6c8 2677 case PCI_DEVICE_ID_QLOGIC_ISP5432:
9e052e2d 2678 ha->isp_type |= DT_ISP5432;
e428924c 2679 ha->device_type |= DT_FWI2;
441d1072 2680 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2681 break;
c3a2f0df 2682 case PCI_DEVICE_ID_QLOGIC_ISP2532:
9e052e2d 2683 ha->isp_type |= DT_ISP2532;
c3a2f0df
AV		 2684 ha->device_type |= DT_ZIO_SUPPORTED;
2685 ha->device_type |= DT_FWI2;
2686 ha->device_type |= DT_IIDMA;
441d1072 2687 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2688 break;
3a03eb79 2689 case PCI_DEVICE_ID_QLOGIC_ISP8001:
9e052e2d 2690 ha->isp_type |= DT_ISP8001;
3a03eb79
AV		 2691 ha->device_type |= DT_ZIO_SUPPORTED;
2692 ha->device_type |= DT_FWI2;
2693 ha->device_type |= DT_IIDMA;
2694 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2695 break;
a9083016 2696 case PCI_DEVICE_ID_QLOGIC_ISP8021:
9e052e2d 2697 ha->isp_type |= DT_ISP8021;
a9083016
GM		 2698 ha->device_type |= DT_ZIO_SUPPORTED;
2699 ha->device_type |= DT_FWI2;
2700 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2701 /* Initialize 82XX ISP flags */
2702 qla82xx_init_flags(ha);
2703 break;
7ec0effd 2704 case PCI_DEVICE_ID_QLOGIC_ISP8044:
9e052e2d 2705 ha->isp_type |= DT_ISP8044;
7ec0effd
AD		 2706 ha->device_type |= DT_ZIO_SUPPORTED;
2707 ha->device_type |= DT_FWI2;
2708 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2709 /* Initialize 82XX ISP flags */
2710 qla82xx_init_flags(ha);
2711 break;
6246b8a1 2712 case PCI_DEVICE_ID_QLOGIC_ISP2031:
9e052e2d 2713 ha->isp_type |= DT_ISP2031;
6246b8a1
GM		 2714 ha->device_type |= DT_ZIO_SUPPORTED;
2715 ha->device_type |= DT_FWI2;
2716 ha->device_type |= DT_IIDMA;
2717 ha->device_type |= DT_T10_PI;
2718 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2719 break;
2720 case PCI_DEVICE_ID_QLOGIC_ISP8031:
9e052e2d 2721 ha->isp_type |= DT_ISP8031;
6246b8a1
GM		 2722 ha->device_type |= DT_ZIO_SUPPORTED;
2723 ha->device_type |= DT_FWI2;
2724 ha->device_type |= DT_IIDMA;
2725 ha->device_type |= DT_T10_PI;
2726 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2727 break;
8ae6d9c7 2728 case PCI_DEVICE_ID_QLOGIC_ISPF001:
9e052e2d 2729 ha->isp_type |= DT_ISPFX00;
8ae6d9c7 2730 break;
f73cb695 2731 case PCI_DEVICE_ID_QLOGIC_ISP2071:
9e052e2d 2732 ha->isp_type |= DT_ISP2071;
f73cb695
CD		 2733 ha->device_type |= DT_ZIO_SUPPORTED;
2734 ha->device_type |= DT_FWI2;
2735 ha->device_type |= DT_IIDMA;
8ce3f570 2736 ha->device_type |= DT_T10_PI;
f73cb695
CD		 2737 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2738 break;
2c5bbbb2 2739 case PCI_DEVICE_ID_QLOGIC_ISP2271:
9e052e2d 2740 ha->isp_type |= DT_ISP2271;
2c5bbbb2
JC		 2741 ha->device_type |= DT_ZIO_SUPPORTED;
2742 ha->device_type |= DT_FWI2;
2743 ha->device_type |= DT_IIDMA;
8ce3f570 2744 ha->device_type |= DT_T10_PI;
2c5bbbb2
JC		 2745 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2746 break;
2b48992f 2747 case PCI_DEVICE_ID_QLOGIC_ISP2261:
9e052e2d 2748 ha->isp_type |= DT_ISP2261;
2b48992f
SC		 2749 ha->device_type |= DT_ZIO_SUPPORTED;
2750 ha->device_type |= DT_FWI2;
2751 ha->device_type |= DT_IIDMA;
8ce3f570 2752 ha->device_type |= DT_T10_PI;
2b48992f
SC		 2753 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2754 break;
ecc89f25
JC		 2755 case PCI_DEVICE_ID_QLOGIC_ISP2081:
2756 case PCI_DEVICE_ID_QLOGIC_ISP2089:
2757 ha->isp_type |= DT_ISP2081;
2758 ha->device_type |= DT_ZIO_SUPPORTED;
2759 ha->device_type |= DT_FWI2;
2760 ha->device_type |= DT_IIDMA;
2761 ha->device_type |= DT_T10_PI;
2762 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2763 break;
2764 case PCI_DEVICE_ID_QLOGIC_ISP2281:
2765 case PCI_DEVICE_ID_QLOGIC_ISP2289:
2766 ha->isp_type |= DT_ISP2281;
2767 ha->device_type |= DT_ZIO_SUPPORTED;
2768 ha->device_type |= DT_FWI2;
2769 ha->device_type |= DT_IIDMA;
2770 ha->device_type |= DT_T10_PI;
2771 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2772 break;
ea5b6382 2773 }
e5b68a61 2774
a9083016 2775 if (IS_QLA82XX(ha))
43a9c38b 2776 ha->port_no = ha->portnum & 1;
f73cb695 2777 else {
a9083016
GM		 2778 /* Get adapter physical port no from interrupt pin register. */
2779 pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no);
ecc89f25
JC		 2780 if (IS_QLA25XX(ha) || IS_QLA2031(ha) ||
2781 IS_QLA27XX(ha) || IS_QLA28XX(ha))
f73cb695
CD		 2782 ha->port_no--;
2783 else
2784 ha->port_no = !(ha->port_no & 1);
2785 }
a9083016 2786
7c3df132 2787 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b,
d8424f68 2788 "device_type=0x%x port=%d fw_srisc_address=0x%x.\n",
f73cb695 2789 ha->device_type, ha->port_no, ha->fw_srisc_address);
ea5b6382 2790}
2791
1e99e33a
AV		 2792static void
2793qla2xxx_scan_start(struct Scsi_Host *shost)
2794{
e315cd28 2795 scsi_qla_host_t *vha = shost_priv(shost);
1e99e33a 2796
cbc8eb67
AV		 2797 if (vha->hw->flags.running_gold_fw)
2798 return;
2799
e315cd28
AC		 2800 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
2801 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
2802 set_bit(RSCN_UPDATE, &vha->dpc_flags);
2803 set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags);
1e99e33a
AV		 2804}
2805
2806static int
2807qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time)
2808{
e315cd28 2809 scsi_qla_host_t *vha = shost_priv(shost);
1e99e33a 2810
a5dd506e
BK		 2811 if (test_bit(UNLOADING, &vha->dpc_flags))
2812 return 1;
e315cd28 2813 if (!vha->host)
1e99e33a 2814 return 1;
e315cd28 2815 if (time > vha->hw->loop_reset_delay * HZ)
1e99e33a
AV		 2816 return 1;
2817
e315cd28 2818 return atomic_read(&vha->loop_state) == LOOP_READY;
1e99e33a
AV		 2819}
2820
ec7193e2
QT		 2821static void qla2x00_iocb_work_fn(struct work_struct *work)
2822{
2823 struct scsi_qla_host *vha = container_of(work,
2824 struct scsi_qla_host, iocb_work);
9b3e0f4d
QT		 2825 struct qla_hw_data *ha = vha->hw;
2826 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
0aca7784 2827 int i = 2;
9b3e0f4d
QT		 2828 unsigned long flags;
2829
2830 if (test_bit(UNLOADING, &base_vha->dpc_flags))
2831 return;
ec7193e2 2832
9b3e0f4d 2833 while (!list_empty(&vha->work_list) && i > 0) {
ec7193e2 2834 qla2x00_do_work(vha);
9b3e0f4d 2835 i--;
ec7193e2 2836 }
9b3e0f4d
QT		 2837
2838 spin_lock_irqsave(&vha->work_lock, flags);
2839 clear_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags);
2840 spin_unlock_irqrestore(&vha->work_lock, flags);
ec7193e2
QT		 2841}
2842
1da177e4
LT		 2843/*
2844 * PCI driver interface
2845 */
6f039790 2846static int
7ee61397 2847qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
1da177e4 2848{
a1541d5a 2849 int ret = -ENODEV;
1da177e4 2850 struct Scsi_Host *host;
e315cd28
AC		 2851 scsi_qla_host_t *base_vha = NULL;
2852 struct qla_hw_data *ha;
29856e28 2853 char pci_info[30];
7d613ac6 2854 char fw_str[30], wq_name[30];
5433383e 2855 struct scsi_host_template *sht;
642ef983 2856 int bars, mem_only = 0;
e315cd28 2857 uint16_t req_length = 0, rsp_length = 0;
73208dfd
AC		 2858 struct req_que *req = NULL;
2859 struct rsp_que *rsp = NULL;
5601236b 2860 int i;
d7459527 2861
285d0321 2862 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO);
a5326f86 2863 sht = &qla2xxx_driver_template;
5433383e 2864 if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 ||
8bc69e7d 2865 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 ||
4d4df193 2866 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 ||
8bc69e7d 2867 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 ||
c3a2f0df 2868 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 ||
3a03eb79 2869 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 ||
a9083016 2870 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 ||
6246b8a1
GM		 2871 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021 ||
2872 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2031 ||
8ae6d9c7 2873 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8031 ||
7ec0effd 2874 pdev->device == PCI_DEVICE_ID_QLOGIC_ISPF001 ||
f73cb695 2875 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8044 ||
2c5bbbb2 2876 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2071 ||
2b48992f 2877 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2271 ||
ecc89f25
JC		 2878 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2261 ||
2879 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2081 ||
2880 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2281 ||
2881 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2089 ||
2882 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2289) {
285d0321 2883 bars = pci_select_bars(pdev, IORESOURCE_MEM);
09483916 2884 mem_only = 1;
7c3df132
SK		 2885 ql_dbg_pci(ql_dbg_init, pdev, 0x0007,
2886 "Mem only adapter.\n");
285d0321 2887 }
7c3df132
SK		 2888 ql_dbg_pci(ql_dbg_init, pdev, 0x0008,
2889 "Bars=%d.\n", bars);
285d0321 2890
09483916
BH		 2891 if (mem_only) {
2892 if (pci_enable_device_mem(pdev))
ddff7ed4 2893 return ret;
09483916
BH		 2894 } else {
2895 if (pci_enable_device(pdev))
ddff7ed4 2896 return ret;
09483916 2897 }
285d0321 2898
0927678f
JB		 2899 /* This may fail but that's ok */
2900 pci_enable_pcie_error_reporting(pdev);
285d0321 2901
5da05a26
GM		 2902 /* Turn off T10-DIF when FC-NVMe is enabled */
2903 if (ql2xnvmeenable)
2904 ql2xenabledif = 0;
2905
e315cd28
AC		 2906 ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL);
2907 if (!ha) {
7c3df132
SK		 2908 ql_log_pci(ql_log_fatal, pdev, 0x0009,
2909 "Unable to allocate memory for ha.\n");
ddff7ed4 2910 goto disable_device;
1da177e4 2911 }
7c3df132
SK		 2912 ql_dbg_pci(ql_dbg_init, pdev, 0x000a,
2913 "Memory allocated for ha=%p.\n", ha);
e315cd28 2914 ha->pdev = pdev;
33e79977
QT		 2915 INIT_LIST_HEAD(&ha->tgt.q_full_list);
2916 spin_lock_init(&ha->tgt.q_full_lock);
7560151b 2917 spin_lock_init(&ha->tgt.sess_lock);
2f424b9b
QT		 2918 spin_lock_init(&ha->tgt.atio_lock);
2919
deeae7a6 2920 atomic_set(&ha->nvme_active_aen_cnt, 0);
1da177e4
LT		 2921
2922 /* Clear our data area */
285d0321 2923 ha->bars = bars;
09483916 2924 ha->mem_only = mem_only;
df4bf0bb 2925 spin_lock_init(&ha->hardware_lock);
339aa70e 2926 spin_lock_init(&ha->vport_slock);
a9b6f722 2927 mutex_init(&ha->selflogin_lock);
7a8ab9c8 2928 mutex_init(&ha->optrom_mutex);
1da177e4 2929
ea5b6382 2930 /* Set ISP-type information. */
2931 qla2x00_set_isp_flags(ha);
ca79cf66
DG		 2932
2933 /* Set EEH reset type to fundamental if required by hba */
95676112 2934 if (IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha) ||
ecc89f25 2935 IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))
ca79cf66 2936 pdev->needs_freset = 1;
ca79cf66 2937
cba1e47f
CD		 2938 ha->prev_topology = 0;
2939 ha->init_cb_size = sizeof(init_cb_t);
2940 ha->link_data_rate = PORT_SPEED_UNKNOWN;
2941 ha->optrom_size = OPTROM_SIZE_2300;
d1e3635a 2942 ha->max_exchg = FW_MAX_EXCHANGES_CNT;
b2000805
QT		 2943 atomic_set(&ha->num_pend_mbx_stage1, 0);
2944 atomic_set(&ha->num_pend_mbx_stage2, 0);
2945 atomic_set(&ha->num_pend_mbx_stage3, 0);
8b4673ba
QT		 2946 atomic_set(&ha->zio_threshold, DEFAULT_ZIO_THRESHOLD);
2947 ha->last_zio_threshold = DEFAULT_ZIO_THRESHOLD;
cba1e47f 2948
abbd8870 2949 /* Assign ISP specific operations. */
1da177e4 2950 if (IS_QLA2100(ha)) {
642ef983 2951 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
1da177e4 2952 ha->mbx_count = MAILBOX_REGISTER_COUNT_2100;
e315cd28
AC		 2953 req_length = REQUEST_ENTRY_CNT_2100;
2954 rsp_length = RESPONSE_ENTRY_CNT_2100;
2955 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
abbd8870 2956 ha->gid_list_info_size = 4;
3a03eb79
AV		 2957 ha->flash_conf_off = ~0;
2958 ha->flash_data_off = ~0;
2959 ha->nvram_conf_off = ~0;
2960 ha->nvram_data_off = ~0;
fd34f556 2961 ha->isp_ops = &qla2100_isp_ops;
1da177e4 2962 } else if (IS_QLA2200(ha)) {
642ef983 2963 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
67ddda35 2964 ha->mbx_count = MAILBOX_REGISTER_COUNT_2200;
e315cd28
AC		 2965 req_length = REQUEST_ENTRY_CNT_2200;
2966 rsp_length = RESPONSE_ENTRY_CNT_2100;
2967 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
abbd8870 2968 ha->gid_list_info_size = 4;
3a03eb79
AV		 2969 ha->flash_conf_off = ~0;
2970 ha->flash_data_off = ~0;
2971 ha->nvram_conf_off = ~0;
2972 ha->nvram_data_off = ~0;
fd34f556 2973 ha->isp_ops = &qla2100_isp_ops;
fca29703 2974 } else if (IS_QLA23XX(ha)) {
642ef983 2975 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
1da177e4 2976 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2977 req_length = REQUEST_ENTRY_CNT_2200;
2978 rsp_length = RESPONSE_ENTRY_CNT_2300;
2979 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
abbd8870 2980 ha->gid_list_info_size = 6;
854165f4 2981 if (IS_QLA2322(ha) || IS_QLA6322(ha))
2982 ha->optrom_size = OPTROM_SIZE_2322;
3a03eb79
AV		 2983 ha->flash_conf_off = ~0;
2984 ha->flash_data_off = ~0;
2985 ha->nvram_conf_off = ~0;
2986 ha->nvram_data_off = ~0;
fd34f556 2987 ha->isp_ops = &qla2300_isp_ops;
4d4df193 2988 } else if (IS_QLA24XX_TYPE(ha)) {
642ef983 2989 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
fca29703 2990 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2991 req_length = REQUEST_ENTRY_CNT_24XX;
2992 rsp_length = RESPONSE_ENTRY_CNT_2300;
2d70c103 2993 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
e315cd28 2994 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2c3dfe3f 2995 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
fca29703 2996 ha->gid_list_info_size = 8;
854165f4 2997 ha->optrom_size = OPTROM_SIZE_24XX;
73208dfd 2998 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX;
fd34f556 2999 ha->isp_ops = &qla24xx_isp_ops;
3a03eb79
AV		 3000 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
3001 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
3002 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
3003 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
c3a2f0df 3004 } else if (IS_QLA25XX(ha)) {
642ef983 3005 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
c3a2f0df 3006 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 3007 req_length = REQUEST_ENTRY_CNT_24XX;
3008 rsp_length = RESPONSE_ENTRY_CNT_2300;
2d70c103 3009 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
e315cd28 3010 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
c3a2f0df 3011 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
c3a2f0df
AV		 3012 ha->gid_list_info_size = 8;
3013 ha->optrom_size = OPTROM_SIZE_25XX;
73208dfd 3014 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
c3a2f0df 3015 ha->isp_ops = &qla25xx_isp_ops;
3a03eb79
AV		 3016 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
3017 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
3018 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
3019 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
3020 } else if (IS_QLA81XX(ha)) {
642ef983 3021 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3a03eb79
AV		 3022 ha->mbx_count = MAILBOX_REGISTER_COUNT;
3023 req_length = REQUEST_ENTRY_CNT_24XX;
3024 rsp_length = RESPONSE_ENTRY_CNT_2300;
aa230bc5 3025 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
3a03eb79
AV		 3026 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
3027 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
3028 ha->gid_list_info_size = 8;
3029 ha->optrom_size = OPTROM_SIZE_81XX;
40859ae5 3030 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3a03eb79
AV		 3031 ha->isp_ops = &qla81xx_isp_ops;
3032 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
3033 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
3034 ha->nvram_conf_off = ~0;
3035 ha->nvram_data_off = ~0;
a9083016 3036 } else if (IS_QLA82XX(ha)) {
642ef983 3037 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
a9083016
GM		 3038 ha->mbx_count = MAILBOX_REGISTER_COUNT;
3039 req_length = REQUEST_ENTRY_CNT_82XX;
3040 rsp_length = RESPONSE_ENTRY_CNT_82XX;
3041 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
3042 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
3043 ha->gid_list_info_size = 8;
3044 ha->optrom_size = OPTROM_SIZE_82XX;
087c621e 3045 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
a9083016
GM		 3046 ha->isp_ops = &qla82xx_isp_ops;
3047 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
3048 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
3049 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
3050 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
7ec0effd
AD		 3051 } else if (IS_QLA8044(ha)) {
3052 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3053 ha->mbx_count = MAILBOX_REGISTER_COUNT;
3054 req_length = REQUEST_ENTRY_CNT_82XX;
3055 rsp_length = RESPONSE_ENTRY_CNT_82XX;
3056 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
3057 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
3058 ha->gid_list_info_size = 8;
3059 ha->optrom_size = OPTROM_SIZE_83XX;
3060 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3061 ha->isp_ops = &qla8044_isp_ops;
3062 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
3063 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
3064 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
3065 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
6246b8a1 3066 } else if (IS_QLA83XX(ha)) {
7d613ac6 3067 ha->portnum = PCI_FUNC(ha->pdev->devfn);
642ef983 3068 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
6246b8a1 3069 ha->mbx_count = MAILBOX_REGISTER_COUNT;
f2ea653f 3070 req_length = REQUEST_ENTRY_CNT_83XX;
e7b42e33 3071 rsp_length = RESPONSE_ENTRY_CNT_83XX;
b8aa4bdf 3072 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
6246b8a1
GM		 3073 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
3074 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
3075 ha->gid_list_info_size = 8;
3076 ha->optrom_size = OPTROM_SIZE_83XX;
3077 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3078 ha->isp_ops = &qla83xx_isp_ops;
3079 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
3080 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
3081 ha->nvram_conf_off = ~0;
3082 ha->nvram_data_off = ~0;
8ae6d9c7
GM		 3083 } else if (IS_QLAFX00(ha)) {
3084 ha->max_fibre_devices = MAX_FIBRE_DEVICES_FX00;
3085 ha->mbx_count = MAILBOX_REGISTER_COUNT_FX00;
3086 ha->aen_mbx_count = AEN_MAILBOX_REGISTER_COUNT_FX00;
3087 req_length = REQUEST_ENTRY_CNT_FX00;
3088 rsp_length = RESPONSE_ENTRY_CNT_FX00;
8ae6d9c7
GM		 3089 ha->isp_ops = &qlafx00_isp_ops;
3090 ha->port_down_retry_count = 30; /* default value */
3091 ha->mr.fw_hbt_cnt = QLAFX00_HEARTBEAT_INTERVAL;
3092 ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL;
71e56003 3093 ha->mr.fw_critemp_timer_tick = QLAFX00_CRITEMP_INTERVAL;
8ae6d9c7 3094 ha->mr.fw_hbt_en = 1;
e8f5e95d
AB		 3095 ha->mr.host_info_resend = false;
3096 ha->mr.hinfo_resend_timer_tick = QLAFX00_HINFO_RESEND_INTERVAL;
f73cb695
CD		 3097 } else if (IS_QLA27XX(ha)) {
3098 ha->portnum = PCI_FUNC(ha->pdev->devfn);
3099 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3100 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e7b42e33
QT		 3101 req_length = REQUEST_ENTRY_CNT_83XX;
3102 rsp_length = RESPONSE_ENTRY_CNT_83XX;
b20f02e1 3103 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
f73cb695
CD		 3104 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
3105 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
3106 ha->gid_list_info_size = 8;
3107 ha->optrom_size = OPTROM_SIZE_83XX;
3108 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3109 ha->isp_ops = &qla27xx_isp_ops;
3110 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
3111 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
3112 ha->nvram_conf_off = ~0;
3113 ha->nvram_data_off = ~0;
ecc89f25
JC		 3114 } else if (IS_QLA28XX(ha)) {
3115 ha->portnum = PCI_FUNC(ha->pdev->devfn);
3116 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3117 ha->mbx_count = MAILBOX_REGISTER_COUNT;
3118 req_length = REQUEST_ENTRY_CNT_24XX;
3119 rsp_length = RESPONSE_ENTRY_CNT_2300;
3120 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
3121 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
3122 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
3123 ha->gid_list_info_size = 8;
3124 ha->optrom_size = OPTROM_SIZE_28XX;
3125 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3126 ha->isp_ops = &qla27xx_isp_ops;
3127 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_28XX;
3128 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_28XX;
3129 ha->nvram_conf_off = ~0;
3130 ha->nvram_data_off = ~0;
1da177e4 3131 }
6246b8a1 3132
7c3df132
SK		 3133 ql_dbg_pci(ql_dbg_init, pdev, 0x001e,
3134 "mbx_count=%d, req_length=%d, "
3135 "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, "
642ef983
CD		 3136 "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, "
3137 "max_fibre_devices=%d.\n",
7c3df132
SK		 3138 ha->mbx_count, req_length, rsp_length, ha->max_loop_id,
3139 ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size,
642ef983 3140 ha->nvram_npiv_size, ha->max_fibre_devices);
7c3df132
SK		 3141 ql_dbg_pci(ql_dbg_init, pdev, 0x001f,
3142 "isp_ops=%p, flash_conf_off=%d, "
3143 "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n",
3144 ha->isp_ops, ha->flash_conf_off, ha->flash_data_off,
3145 ha->nvram_conf_off, ha->nvram_data_off);
706f457d
GM		 3146
3147 /* Configure PCI I/O space */
3148 ret = ha->isp_ops->iospace_config(ha);
3149 if (ret)
0a63ad12 3150 goto iospace_config_failed;
706f457d
GM		 3151
3152 ql_log_pci(ql_log_info, pdev, 0x001d,
3153 "Found an ISP%04X irq %d iobase 0x%p.\n",
3154 pdev->device, pdev->irq, ha->iobase);
6c2f527c 3155 mutex_init(&ha->vport_lock);
d7459527 3156 mutex_init(&ha->mq_lock);
0b05a1f0
MB		 3157 init_completion(&ha->mbx_cmd_comp);
3158 complete(&ha->mbx_cmd_comp);
3159 init_completion(&ha->mbx_intr_comp);
23f2ebd1 3160 init_completion(&ha->dcbx_comp);
f356bef1 3161 init_completion(&ha->lb_portup_comp);
1da177e4 3162
2c3dfe3f 3163 set_bit(0, (unsigned long *) ha->vp_idx_map);
1da177e4 3164
53303c42 3165 qla2x00_config_dma_addressing(ha);
7c3df132
SK		 3166 ql_dbg_pci(ql_dbg_init, pdev, 0x0020,
3167 "64 Bit addressing is %s.\n",
3168 ha->flags.enable_64bit_addressing ? "enable" :
3169 "disable");
73208dfd 3170 ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp);
b2a72ec3 3171 if (ret) {
7c3df132
SK		 3172 ql_log_pci(ql_log_fatal, pdev, 0x0031,
3173 "Failed to allocate memory for adapter, aborting.\n");
1da177e4 3174
e315cd28
AC		 3175 goto probe_hw_failed;
3176 }
3177
73208dfd 3178 req->max_q_depth = MAX_Q_DEPTH;
e315cd28 3179 if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU)
73208dfd
AC		 3180 req->max_q_depth = ql2xmaxqdepth;
3181
e315cd28
AC		 3182
3183 base_vha = qla2x00_create_host(sht, ha);
3184 if (!base_vha) {
a1541d5a 3185 ret = -ENOMEM;
e315cd28 3186 goto probe_hw_failed;
1da177e4
LT		 3187 }
3188
e315cd28 3189 pci_set_drvdata(pdev, base_vha);
6b383979 3190 set_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags);
e315cd28 3191
e315cd28 3192 host = base_vha->host;
2afa19a9 3193 base_vha->req = req;
73208dfd 3194 if (IS_QLA2XXX_MIDTYPE(ha))
f6602f3b
QT		 3195 base_vha->mgmt_svr_loop_id =
3196 qla2x00_reserve_mgmt_server_loop_id(base_vha);
73208dfd 3197 else
e315cd28
AC		 3198 base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER +
3199 base_vha->vp_idx;
58548cb5 3200
8ae6d9c7
GM		 3201 /* Setup fcport template structure. */
3202 ha->mr.fcport.vha = base_vha;
3203 ha->mr.fcport.port_type = FCT_UNKNOWN;
3204 ha->mr.fcport.loop_id = FC_NO_LOOP_ID;
3205 qla2x00_set_fcport_state(&ha->mr.fcport, FCS_UNCONFIGURED);
3206 ha->mr.fcport.supported_classes = FC_COS_UNSPECIFIED;
3207 ha->mr.fcport.scan_state = 1;
3208
58548cb5
GM		 3209 /* Set the SG table size based on ISP type */
3210 if (!IS_FWI2_CAPABLE(ha)) {
3211 if (IS_QLA2100(ha))
3212 host->sg_tablesize = 32;
3213 } else {
3214 if (!IS_QLA82XX(ha))
3215 host->sg_tablesize = QLA_SG_ALL;
3216 }
642ef983 3217 host->max_id = ha->max_fibre_devices;
e315cd28
AC		 3218 host->cmd_per_lun = 3;
3219 host->unique_id = host->host_no;
e02587d7 3220 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif)
0c470874
AE		 3221 host->max_cmd_len = 32;
3222 else
3223 host->max_cmd_len = MAX_CMDSZ;
e315cd28 3224 host->max_channel = MAX_BUSES - 1;
755f516b
HR		 3225 /* Older HBAs support only 16-bit LUNs */
3226 if (!IS_QLAFX00(ha) && !IS_FWI2_CAPABLE(ha) &&
3227 ql2xmaxlun > 0xffff)
3228 host->max_lun = 0xffff;
3229 else
3230 host->max_lun = ql2xmaxlun;
e315cd28 3231 host->transportt = qla2xxx_transport_template;
9a069e19 3232 sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC);
e315cd28 3233
7c3df132
SK		 3234 ql_dbg(ql_dbg_init, base_vha, 0x0033,
3235 "max_id=%d this_id=%d "
3236 "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d "
1abf635d 3237 "max_lun=%llu transportt=%p, vendor_id=%llu.\n", host->max_id,
7c3df132
SK		 3238 host->this_id, host->cmd_per_lun, host->unique_id,
3239 host->max_cmd_len, host->max_channel, host->max_lun,
3240 host->transportt, sht->vendor_id);
3241
1010f21e
HM		 3242 INIT_WORK(&base_vha->iocb_work, qla2x00_iocb_work_fn);
3243
d7459527
MH		 3244 /* Set up the irqs */
3245 ret = qla2x00_request_irqs(ha, rsp);
3246 if (ret)
6a2cf8d3 3247 goto probe_failed;
d7459527 3248
9a347ff4 3249 /* Alloc arrays of request and response ring ptrs */
6d634067
BK		 3250 ret = qla2x00_alloc_queues(ha, req, rsp);
3251 if (ret) {
9a347ff4
CD		 3252 ql_log(ql_log_fatal, base_vha, 0x003d,
3253 "Failed to allocate memory for queue pointers..."
3254 "aborting.\n");
6a2cf8d3 3255 goto probe_failed;
9a347ff4
CD		 3256 }
3257
f664a3cc 3258 if (ha->mqenable) {
5601236b
MH		 3259 /* number of hardware queues supported by blk/scsi-mq*/
3260 host->nr_hw_queues = ha->max_qpairs;
3261
3262 ql_dbg(ql_dbg_init, base_vha, 0x0192,
3263 "blk/scsi-mq enabled, HW queues = %d.\n", host->nr_hw_queues);
c38d1baf
HM		 3264 } else {
3265 if (ql2xnvmeenable) {
3266 host->nr_hw_queues = ha->max_qpairs;
3267 ql_dbg(ql_dbg_init, base_vha, 0x0194,
3268 "FC-NVMe support is enabled, HW queues=%d\n",
3269 host->nr_hw_queues);
3270 } else {
3271 ql_dbg(ql_dbg_init, base_vha, 0x0193,
3272 "blk/scsi-mq disabled.\n");
3273 }
3274 }
5601236b 3275
2d70c103 3276 qlt_probe_one_stage1(base_vha, ha);
9a347ff4 3277
90a86fc0
JC		 3278 pci_save_state(pdev);
3279
9a347ff4 3280 /* Assign back pointers */
2afa19a9
AC		 3281 rsp->req = req;
3282 req->rsp = rsp;
9a347ff4 3283
8ae6d9c7
GM		 3284 if (IS_QLAFX00(ha)) {
3285 ha->rsp_q_map[0] = rsp;
3286 ha->req_q_map[0] = req;
3287 set_bit(0, ha->req_qid_map);
3288 set_bit(0, ha->rsp_qid_map);
3289 }
3290
08029990
AV		 3291 /* FWI2-capable only. */
3292 req->req_q_in = &ha->iobase->isp24.req_q_in;
3293 req->req_q_out = &ha->iobase->isp24.req_q_out;
3294 rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in;
3295 rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out;
ecc89f25
JC		 3296 if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha) ||
3297 IS_QLA28XX(ha)) {
08029990
AV		 3298 req->req_q_in = &ha->mqiobase->isp25mq.req_q_in;
3299 req->req_q_out = &ha->mqiobase->isp25mq.req_q_out;
3300 rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in;
3301 rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out;
17d98630
AC		 3302 }
3303
8ae6d9c7
GM		 3304 if (IS_QLAFX00(ha)) {
3305 req->req_q_in = &ha->iobase->ispfx00.req_q_in;
3306 req->req_q_out = &ha->iobase->ispfx00.req_q_out;
3307 rsp->rsp_q_in = &ha->iobase->ispfx00.rsp_q_in;
3308 rsp->rsp_q_out = &ha->iobase->ispfx00.rsp_q_out;
3309 }
3310
7ec0effd 3311 if (IS_P3P_TYPE(ha)) {
a9083016
GM		 3312 req->req_q_out = &ha->iobase->isp82.req_q_out[0];
3313 rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0];
3314 rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0];
3315 }
3316
7c3df132
SK		 3317 ql_dbg(ql_dbg_multiq, base_vha, 0xc009,
3318 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
3319 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
3320 ql_dbg(ql_dbg_multiq, base_vha, 0xc00a,
3321 "req->req_q_in=%p req->req_q_out=%p "
3322 "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
3323 req->req_q_in, req->req_q_out,
3324 rsp->rsp_q_in, rsp->rsp_q_out);
3325 ql_dbg(ql_dbg_init, base_vha, 0x003e,
3326 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
3327 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
3328 ql_dbg(ql_dbg_init, base_vha, 0x003f,
3329 "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
3330 req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out);
1da177e4 3331
d48cc67c 3332 ha->wq = alloc_workqueue("qla2xxx_wq", 0, 0);
3333
8ae6d9c7 3334 if (ha->isp_ops->initialize_adapter(base_vha)) {
7c3df132
SK		 3335 ql_log(ql_log_fatal, base_vha, 0x00d6,
3336 "Failed to initialize adapter - Adapter flags %x.\n",
3337 base_vha->device_flags);
1da177e4 3338
a9083016
GM		 3339 if (IS_QLA82XX(ha)) {
3340 qla82xx_idc_lock(ha);
3341 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 3342 QLA8XXX_DEV_FAILED);
a9083016 3343 qla82xx_idc_unlock(ha);
7c3df132
SK		 3344 ql_log(ql_log_fatal, base_vha, 0x00d7,
3345 "HW State: FAILED.\n");
7ec0effd
AD		 3346 } else if (IS_QLA8044(ha)) {
3347 qla8044_idc_lock(ha);
3348 qla8044_wr_direct(base_vha,
3349 QLA8044_CRB_DEV_STATE_INDEX,
3350 QLA8XXX_DEV_FAILED);
3351 qla8044_idc_unlock(ha);
3352 ql_log(ql_log_fatal, base_vha, 0x0150,
3353 "HW State: FAILED.\n");
a9083016
GM		 3354 }
3355
a1541d5a 3356 ret = -ENODEV;
1da177e4
LT		 3357 goto probe_failed;
3358 }
3359
3b1bef64
CD		 3360 if (IS_QLAFX00(ha))
3361 host->can_queue = QLAFX00_MAX_CANQUEUE;
3362 else
3363 host->can_queue = req->num_outstanding_cmds - 10;
3364
3365 ql_dbg(ql_dbg_init, base_vha, 0x0032,
3366 "can_queue=%d, req=%p, mgmt_svr_loop_id=%d, sg_tablesize=%d.\n",
3367 host->can_queue, base_vha->req,
3368 base_vha->mgmt_svr_loop_id, host->sg_tablesize);
3369
e326d22a 3370 if (ha->mqenable) {
e326d22a 3371 bool startit = false;
e326d22a 3372
f664a3cc 3373 if (QLA_TGT_MODE_ENABLED())
e326d22a 3374 startit = false;
e326d22a 3375
f664a3cc 3376 if (ql2x_ini_mode == QLA2XXX_INI_MODE_ENABLED)
e326d22a 3377 startit = true;
e326d22a 3378
f664a3cc
JA		 3379 /* Create start of day qpairs for Block MQ */
3380 for (i = 0; i < ha->max_qpairs; i++)
3381 qla2xxx_create_qpair(base_vha, 5, 0, startit);
5601236b 3382 }
68ca949c 3383
cbc8eb67
AV		 3384 if (ha->flags.running_gold_fw)
3385 goto skip_dpc;
3386
1da177e4
LT		 3387 /*
3388 * Startup the kernel thread for this host adapter
3389 */
39a11240 3390 ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha,
7c3df132 3391 "%s_dpc", base_vha->host_str);
39a11240 3392 if (IS_ERR(ha->dpc_thread)) {
7c3df132
SK		 3393 ql_log(ql_log_fatal, base_vha, 0x00ed,
3394 "Failed to start DPC thread.\n");
39a11240 3395 ret = PTR_ERR(ha->dpc_thread);
e2532b4a 3396 ha->dpc_thread = NULL;
1da177e4
LT		 3397 goto probe_failed;
3398 }
7c3df132
SK		 3399 ql_dbg(ql_dbg_init, base_vha, 0x00ee,
3400 "DPC thread started successfully.\n");
1da177e4 3401
2d70c103
NB		 3402 /*
3403 * If we're not coming up in initiator mode, we might sit for
3404 * a while without waking up the dpc thread, which leads to a
3405 * stuck process warning. So just kick the dpc once here and
3406 * let the kthread start (and go back to sleep in qla2x00_do_dpc).
3407 */
3408 qla2xxx_wake_dpc(base_vha);
3409
f3ddac19
CD		 3410 INIT_WORK(&ha->board_disable, qla2x00_disable_board_on_pci_error);
3411
81178772
SK		 3412 if (IS_QLA8031(ha) || IS_MCTP_CAPABLE(ha)) {
3413 sprintf(wq_name, "qla2xxx_%lu_dpc_lp_wq", base_vha->host_no);
3414 ha->dpc_lp_wq = create_singlethread_workqueue(wq_name);
3415 INIT_WORK(&ha->idc_aen, qla83xx_service_idc_aen);
3416
3417 sprintf(wq_name, "qla2xxx_%lu_dpc_hp_wq", base_vha->host_no);
3418 ha->dpc_hp_wq = create_singlethread_workqueue(wq_name);
3419 INIT_WORK(&ha->nic_core_reset, qla83xx_nic_core_reset_work);
3420 INIT_WORK(&ha->idc_state_handler,
3421 qla83xx_idc_state_handler_work);
3422 INIT_WORK(&ha->nic_core_unrecoverable,
3423 qla83xx_nic_core_unrecoverable_work);
3424 }
3425
cbc8eb67 3426skip_dpc:
e315cd28
AC		 3427 list_add_tail(&base_vha->list, &ha->vp_list);
3428 base_vha->host->irq = ha->pdev->irq;
1da177e4
LT		 3429
3430 /* Initialized the timer */
8e5f4ba0 3431 qla2x00_start_timer(base_vha, WATCH_INTERVAL);
7c3df132
SK		 3432 ql_dbg(ql_dbg_init, base_vha, 0x00ef,
3433 "Started qla2x00_timer with "
3434 "interval=%d.\n", WATCH_INTERVAL);
3435 ql_dbg(ql_dbg_init, base_vha, 0x00f0,
3436 "Detected hba at address=%p.\n",
3437 ha);
d19044c3 3438
e02587d7 3439 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) {
bad75002 3440 if (ha->fw_attributes & BIT_4) {
9e522cd8 3441 int prot = 0, guard;
bad75002 3442 base_vha->flags.difdix_supported = 1;
7c3df132
SK		 3443 ql_dbg(ql_dbg_init, base_vha, 0x00f1,
3444 "Registering for DIF/DIX type 1 and 3 protection.\n");
8cb2049c
AE		 3445 if (ql2xenabledif == 1)
3446 prot = SHOST_DIX_TYPE0_PROTECTION;
7855d2ba
MP		 3447 if (ql2xprotmask)
3448 scsi_host_set_prot(host, ql2xprotmask);
3449 else
3450 scsi_host_set_prot(host,
3451 prot | SHOST_DIF_TYPE1_PROTECTION
3452 | SHOST_DIF_TYPE2_PROTECTION
3453 | SHOST_DIF_TYPE3_PROTECTION
3454 | SHOST_DIX_TYPE1_PROTECTION
3455 | SHOST_DIX_TYPE2_PROTECTION
3456 | SHOST_DIX_TYPE3_PROTECTION);
9e522cd8
AE		 3457
3458 guard = SHOST_DIX_GUARD_CRC;
3459
3460 if (IS_PI_IPGUARD_CAPABLE(ha) &&
3461 (ql2xenabledif > 1 || IS_PI_DIFB_DIX0_CAPABLE(ha)))
3462 guard |= SHOST_DIX_GUARD_IP;
3463
7855d2ba
MP		 3464 if (ql2xprotguard)
3465 scsi_host_set_guard(host, ql2xprotguard);
3466 else
3467 scsi_host_set_guard(host, guard);
bad75002
AE		 3468 } else
3469 base_vha->flags.difdix_supported = 0;
3470 }
3471
a9083016
GM		 3472 ha->isp_ops->enable_intrs(ha);
3473
1fe19ee4
AB		 3474 if (IS_QLAFX00(ha)) {
3475 ret = qlafx00_fx_disc(base_vha,
3476 &base_vha->hw->mr.fcport, FXDISC_GET_CONFIG_INFO);
3477 host->sg_tablesize = (ha->mr.extended_io_enabled) ?
3478 QLA_SG_ALL : 128;
3479 }
3480
a1541d5a
AV		 3481 ret = scsi_add_host(host, &pdev->dev);
3482 if (ret)
3483 goto probe_failed;
3484
1486400f
MR		 3485 base_vha->flags.init_done = 1;
3486 base_vha->flags.online = 1;
edaa5c74 3487 ha->prev_minidump_failed = 0;
1486400f 3488
7c3df132
SK		 3489 ql_dbg(ql_dbg_init, base_vha, 0x00f2,
3490 "Init done and hba is online.\n");
3491
726b8548
QT		 3492 if (qla_ini_mode_enabled(base_vha) ||
3493 qla_dual_mode_enabled(base_vha))
2d70c103
NB		 3494 scsi_scan_host(host);
3495 else
3496 ql_dbg(ql_dbg_init, base_vha, 0x0122,
3497 "skipping scsi_scan_host() for non-initiator port\n");
1e99e33a 3498
e315cd28 3499 qla2x00_alloc_sysfs_attr(base_vha);
a1541d5a 3500
8ae6d9c7 3501 if (IS_QLAFX00(ha)) {
8ae6d9c7
GM		 3502 ret = qlafx00_fx_disc(base_vha,
3503 &base_vha->hw->mr.fcport, FXDISC_GET_PORT_INFO);
3504
3505 /* Register system information */
3506 ret = qlafx00_fx_disc(base_vha,
3507 &base_vha->hw->mr.fcport, FXDISC_REG_HOST_INFO);
3508 }
3509
e315cd28 3510 qla2x00_init_host_attr(base_vha);
a1541d5a 3511
e315cd28 3512 qla2x00_dfs_setup(base_vha);
df613b96 3513
03eb912a
AB		 3514 ql_log(ql_log_info, base_vha, 0x00fb,
3515 "QLogic %s - %s.\n", ha->model_number, ha->model_desc);
7c3df132
SK		 3516 ql_log(ql_log_info, base_vha, 0x00fc,
3517 "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n",
3518 pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info),
3519 pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-',
3520 base_vha->host_no,
df57caba 3521 ha->isp_ops->fw_version_str(base_vha, fw_str, sizeof(fw_str)));
1da177e4 3522
2d70c103
NB		 3523 qlt_add_target(ha, base_vha);
3524
6b383979 3525 clear_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags);
a29b3dd7
JC		 3526
3527 if (test_bit(UNLOADING, &base_vha->dpc_flags))
3528 return -ENODEV;
3529
e4e3a2ce
QT		 3530 if (ha->flags.detected_lr_sfp) {
3531 ql_log(ql_log_info, base_vha, 0xffff,
3532 "Reset chip to pick up LR SFP setting\n");
3533 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
3534 qla2xxx_wake_dpc(base_vha);
3535 }
3536
1da177e4
LT		 3537 return 0;
3538
3539probe_failed:
b9978769
AV		 3540 if (base_vha->timer_active)
3541 qla2x00_stop_timer(base_vha);
3542 base_vha->flags.online = 0;
3543 if (ha->dpc_thread) {
3544 struct task_struct *t = ha->dpc_thread;
3545
3546 ha->dpc_thread = NULL;
3547 kthread_stop(t);
3548 }
3549
e315cd28 3550 qla2x00_free_device(base_vha);
e315cd28 3551 scsi_host_put(base_vha->host);
6d634067
BK		 3552 /*
3553 * Need to NULL out local req/rsp after
3554 * qla2x00_free_device => qla2x00_free_queues frees
3555 * what these are pointing to. Or else we'll
3556 * fall over below in qla2x00_free_req/rsp_que.
3557 */
3558 req = NULL;
3559 rsp = NULL;
1da177e4 3560
e315cd28 3561probe_hw_failed:
d64d6c56 3562 qla2x00_mem_free(ha);
3563 qla2x00_free_req_que(ha, req);
3564 qla2x00_free_rsp_que(ha, rsp);
1a2fbf18
JL		 3565 qla2x00_clear_drv_active(ha);
3566
0a63ad12 3567iospace_config_failed:
7ec0effd 3568 if (IS_P3P_TYPE(ha)) {
0a63ad12 3569 if (!ha->nx_pcibase)
f73cb695 3570 iounmap((device_reg_t *)ha->nx_pcibase);
a9083016 3571 if (!ql2xdbwr)
f73cb695 3572 iounmap((device_reg_t *)ha->nxdb_wr_ptr);
a9083016
GM		 3573 } else {
3574 if (ha->iobase)
3575 iounmap(ha->iobase);
8ae6d9c7
GM		 3576 if (ha->cregbase)
3577 iounmap(ha->cregbase);
a9083016 3578 }
e315cd28
AC		 3579 pci_release_selected_regions(ha->pdev, ha->bars);
3580 kfree(ha);
1da177e4 3581
ddff7ed4 3582disable_device:
e315cd28 3583 pci_disable_device(pdev);
a1541d5a 3584 return ret;
1da177e4 3585}
1da177e4 3586
e30d1756
MI		 3587static void
3588qla2x00_shutdown(struct pci_dev *pdev)
3589{
3590 scsi_qla_host_t *vha;
3591 struct qla_hw_data *ha;
3592
3593 vha = pci_get_drvdata(pdev);
3594 ha = vha->hw;
3595
efdb5760
SC		 3596 ql_log(ql_log_info, vha, 0xfffa,
3597 "Adapter shutdown\n");
3598
3599 /*
3600 * Prevent future board_disable and wait
3601 * until any pending board_disable has completed.
3602 */
3603 set_bit(PFLG_DRIVER_REMOVING, &vha->pci_flags);
3604 cancel_work_sync(&ha->board_disable);
3605
3606 if (!atomic_read(&pdev->enable_cnt))
3607 return;
3608
42479343
AB		 3609 /* Notify ISPFX00 firmware */
3610 if (IS_QLAFX00(ha))
3611 qlafx00_driver_shutdown(vha, 20);
3612
e30d1756
MI		 3613 /* Turn-off FCE trace */
3614 if (ha->flags.fce_enabled) {
3615 qla2x00_disable_fce_trace(vha, NULL, NULL);
3616 ha->flags.fce_enabled = 0;
3617 }
3618
3619 /* Turn-off EFT trace */
3620 if (ha->eft)
3621 qla2x00_disable_eft_trace(vha);
3622
ecc89f25
JC		 3623 if (IS_QLA25XX(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) ||
3624 IS_QLA28XX(ha)) {
3407fc37
QT		 3625 if (ha->flags.fw_started)
3626 qla2x00_abort_isp_cleanup(vha);
3627 } else {
3628 /* Stop currently executing firmware. */
3629 qla2x00_try_to_stop_firmware(vha);
3630 }
e30d1756
MI		 3631
3632 /* Turn adapter off line */
3633 vha->flags.online = 0;
3634
3635 /* turn-off interrupts on the card */
3636 if (ha->interrupts_on) {
3637 vha->flags.init_done = 0;
3638 ha->isp_ops->disable_intrs(ha);
3639 }
3640
3641 qla2x00_free_irqs(vha);
3642
3643 qla2x00_free_fw_dump(ha);
61d41f61 3644
61d41f61 3645 pci_disable_device(pdev);
efdb5760
SC		 3646 ql_log(ql_log_info, vha, 0xfffe,
3647 "Adapter shutdown successfully.\n");
e30d1756
MI		 3648}
3649
fe1b806f 3650/* Deletes all the virtual ports for a given ha */
4c993f76 3651static void
fe1b806f 3652qla2x00_delete_all_vps(struct qla_hw_data *ha, scsi_qla_host_t *base_vha)
1da177e4 3653{
fe1b806f 3654 scsi_qla_host_t *vha;
feafb7b1 3655 unsigned long flags;
e315cd28 3656
43ebf16d
AE		 3657 mutex_lock(&ha->vport_lock);
3658 while (ha->cur_vport_count) {
43ebf16d 3659 spin_lock_irqsave(&ha->vport_slock, flags);
feafb7b1 3660
43ebf16d
AE		 3661 BUG_ON(base_vha->list.next == &ha->vp_list);
3662 /* This assumes first entry in ha->vp_list is always base vha */
3663 vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list);
52c82823 3664 scsi_host_get(vha->host);
feafb7b1 3665
43ebf16d
AE		 3666 spin_unlock_irqrestore(&ha->vport_slock, flags);
3667 mutex_unlock(&ha->vport_lock);
3668
5e6803b4
HM		 3669 qla_nvme_delete(vha);
3670
43ebf16d
AE		 3671 fc_vport_terminate(vha->fc_vport);
3672 scsi_host_put(vha->host);
feafb7b1 3673
43ebf16d 3674 mutex_lock(&ha->vport_lock);
e315cd28 3675 }
43ebf16d 3676 mutex_unlock(&ha->vport_lock);
fe1b806f 3677}
1da177e4 3678
fe1b806f
CD		 3679/* Stops all deferred work threads */
3680static void
3681qla2x00_destroy_deferred_work(struct qla_hw_data *ha)
3682{
7d613ac6
SV		 3683 /* Cancel all work and destroy DPC workqueues */
3684 if (ha->dpc_lp_wq) {
3685 cancel_work_sync(&ha->idc_aen);
3686 destroy_workqueue(ha->dpc_lp_wq);
3687 ha->dpc_lp_wq = NULL;
3688 }
3689
3690 if (ha->dpc_hp_wq) {
3691 cancel_work_sync(&ha->nic_core_reset);
3692 cancel_work_sync(&ha->idc_state_handler);
3693 cancel_work_sync(&ha->nic_core_unrecoverable);
3694 destroy_workqueue(ha->dpc_hp_wq);
3695 ha->dpc_hp_wq = NULL;
3696 }
3697
b9978769
AV		 3698 /* Kill the kernel thread for this host */
3699 if (ha->dpc_thread) {
3700 struct task_struct *t = ha->dpc_thread;
3701
3702 /*
3703 * qla2xxx_wake_dpc checks for ->dpc_thread
3704 * so we need to zero it out.
3705 */
3706 ha->dpc_thread = NULL;
3707 kthread_stop(t);
3708 }
fe1b806f 3709}
1da177e4 3710
fe1b806f
CD		 3711static void
3712qla2x00_unmap_iobases(struct qla_hw_data *ha)
3713{
a9083016 3714 if (IS_QLA82XX(ha)) {
b963752f 3715
f73cb695 3716 iounmap((device_reg_t *)ha->nx_pcibase);
a9083016 3717 if (!ql2xdbwr)
f73cb695 3718 iounmap((device_reg_t *)ha->nxdb_wr_ptr);
a9083016
GM		 3719 } else {
3720 if (ha->iobase)
3721 iounmap(ha->iobase);
1da177e4 3722
8ae6d9c7
GM		 3723 if (ha->cregbase)
3724 iounmap(ha->cregbase);
3725
a9083016
GM		 3726 if (ha->mqiobase)
3727 iounmap(ha->mqiobase);
6246b8a1 3728
ecc89f25
JC		 3729 if ((IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) &&
3730 ha->msixbase)
6246b8a1 3731 iounmap(ha->msixbase);
a9083016 3732 }
fe1b806f
CD		 3733}
3734
3735static void
db7157d4 3736qla2x00_clear_drv_active(struct qla_hw_data *ha)
fe1b806f 3737{
fe1b806f
CD		 3738 if (IS_QLA8044(ha)) {
3739 qla8044_idc_lock(ha);
c41afc9a 3740 qla8044_clear_drv_active(ha);
fe1b806f
CD		 3741 qla8044_idc_unlock(ha);
3742 } else if (IS_QLA82XX(ha)) {
3743 qla82xx_idc_lock(ha);
3744 qla82xx_clear_drv_active(ha);
3745 qla82xx_idc_unlock(ha);
3746 }
3747}
3748
3749static void
3750qla2x00_remove_one(struct pci_dev *pdev)
3751{
3752 scsi_qla_host_t *base_vha;
3753 struct qla_hw_data *ha;
3754
beb9e315
JL		 3755 base_vha = pci_get_drvdata(pdev);
3756 ha = base_vha->hw;
45235022
QT		 3757 ql_log(ql_log_info, base_vha, 0xb079,
3758 "Removing driver\n");
beb9e315
JL		 3759
3760 /* Indicate device removal to prevent future board_disable and wait
3761 * until any pending board_disable has completed. */
3762 set_bit(PFLG_DRIVER_REMOVING, &base_vha->pci_flags);
3763 cancel_work_sync(&ha->board_disable);
3764
fe1b806f 3765 /*
beb9e315
JL		 3766 * If the PCI device is disabled then there was a PCI-disconnect and
3767 * qla2x00_disable_board_on_pci_error has taken care of most of the
3768 * resources.
fe1b806f 3769 */
beb9e315 3770 if (!atomic_read(&pdev->enable_cnt)) {
726b8548
QT		 3771 dma_free_coherent(&ha->pdev->dev, base_vha->gnl.size,
3772 base_vha->gnl.l, base_vha->gnl.ldma);
3773
beb9e315
JL		 3774 scsi_host_put(base_vha->host);
3775 kfree(ha);
3776 pci_set_drvdata(pdev, NULL);
fe1b806f 3777 return;
beb9e315 3778 }
638a1a01
SC		 3779 qla2x00_wait_for_hba_ready(base_vha);
3780
ecc89f25
JC		 3781 if (IS_QLA25XX(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) ||
3782 IS_QLA28XX(ha)) {
45235022
QT		 3783 if (ha->flags.fw_started)
3784 qla2x00_abort_isp_cleanup(base_vha);
3785 } else if (!IS_QLAFX00(ha)) {
3786 if (IS_QLA8031(ha)) {
3787 ql_dbg(ql_dbg_p3p, base_vha, 0xb07e,
3788 "Clearing fcoe driver presence.\n");
3789 if (qla83xx_clear_drv_presence(base_vha) != QLA_SUCCESS)
3790 ql_dbg(ql_dbg_p3p, base_vha, 0xb079,
3791 "Error while clearing DRV-Presence.\n");
3792 }
3793
3794 qla2x00_try_to_stop_firmware(base_vha);
3795 }
3796
2ce87cc5
QT		 3797 qla2x00_wait_for_sess_deletion(base_vha);
3798
726b8548
QT		 3799 /*
3800 * if UNLOAD flag is already set, then continue unload,
783e0dc4
SC		 3801 * where it was set first.
3802 */
3803 if (test_bit(UNLOADING, &base_vha->dpc_flags))
3804 return;
3805
fe1b806f 3806 set_bit(UNLOADING, &base_vha->dpc_flags);
e84067d7
DG		 3807
3808 qla_nvme_delete(base_vha);
3809
726b8548
QT		 3810 dma_free_coherent(&ha->pdev->dev,
3811 base_vha->gnl.size, base_vha->gnl.l, base_vha->gnl.ldma);
fe1b806f 3812
a4239945
QT		 3813 vfree(base_vha->scan.l);
3814
fe1b806f
CD		 3815 if (IS_QLAFX00(ha))
3816 qlafx00_driver_shutdown(base_vha, 20);
3817
3818 qla2x00_delete_all_vps(ha, base_vha);
3819
fe1b806f
CD		 3820 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
3821
3822 qla2x00_dfs_remove(base_vha);
3823
3824 qla84xx_put_chip(base_vha);
3825
3826 /* Disable timer */
3827 if (base_vha->timer_active)
3828 qla2x00_stop_timer(base_vha);
3829
3830 base_vha->flags.online = 0;
3831
b0d6cabd
HM		 3832 /* free DMA memory */
3833 if (ha->exlogin_buf)
3834 qla2x00_free_exlogin_buffer(ha);
3835
2f56a7f1
HM		 3836 /* free DMA memory */
3837 if (ha->exchoffld_buf)
3838 qla2x00_free_exchoffld_buffer(ha);
3839
fe1b806f
CD		 3840 qla2x00_destroy_deferred_work(ha);
3841
3842 qlt_remove_target(ha, base_vha);
3843
3844 qla2x00_free_sysfs_attr(base_vha, true);
3845
3846 fc_remove_host(base_vha->host);
482c9dc7 3847 qlt_remove_target_resources(ha);
fe1b806f
CD		 3848
3849 scsi_remove_host(base_vha->host);
3850
3851 qla2x00_free_device(base_vha);
3852
db7157d4 3853 qla2x00_clear_drv_active(ha);
fe1b806f 3854
d2749ffa
AE		 3855 scsi_host_put(base_vha->host);
3856
fe1b806f 3857 qla2x00_unmap_iobases(ha);
73208dfd 3858
e315cd28
AC		 3859 pci_release_selected_regions(ha->pdev, ha->bars);
3860 kfree(ha);
1da177e4 3861
90a86fc0
JC		 3862 pci_disable_pcie_error_reporting(pdev);
3863
665db93b 3864 pci_disable_device(pdev);
1da177e4 3865}
1da177e4
LT		 3866
3867static void
e315cd28 3868qla2x00_free_device(scsi_qla_host_t *vha)
1da177e4 3869{
e315cd28 3870 struct qla_hw_data *ha = vha->hw;
1da177e4 3871
85880801
AV		 3872 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
3873
3874 /* Disable timer */
3875 if (vha->timer_active)
3876 qla2x00_stop_timer(vha);
3877
2afa19a9 3878 qla25xx_delete_queues(vha);
85880801
AV		 3879 vha->flags.online = 0;
3880
f6ef3b18 3881 /* turn-off interrupts on the card */
a9083016
GM		 3882 if (ha->interrupts_on) {
3883 vha->flags.init_done = 0;
fd34f556 3884 ha->isp_ops->disable_intrs(ha);
a9083016 3885 }
f6ef3b18 3886
093df737
QT		 3887 qla2x00_free_fcports(vha);
3888
e315cd28 3889 qla2x00_free_irqs(vha);
1da177e4 3890
093df737
QT		 3891 /* Flush the work queue and remove it */
3892 if (ha->wq) {
3893 flush_workqueue(ha->wq);
3894 destroy_workqueue(ha->wq);
3895 ha->wq = NULL;
3896 }
3897
8867048b 3898
e315cd28 3899 qla2x00_mem_free(ha);
73208dfd 3900
08de2844
GM		 3901 qla82xx_md_free(vha);
3902
73208dfd 3903 qla2x00_free_queues(ha);
1da177e4
LT		 3904}
3905
8867048b
CD		 3906void qla2x00_free_fcports(struct scsi_qla_host *vha)
3907{
3908 fc_port_t *fcport, *tfcport;
3909
3910 list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list) {
3911 list_del(&fcport->list);
5f16b331 3912 qla2x00_clear_loop_id(fcport);
8867048b 3913 kfree(fcport);
8867048b
CD		 3914 }
3915}
3916
d97994dc 3917static inline void
e315cd28 3918qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport,
d97994dc 3919 int defer)
3920{
d97994dc 3921 struct fc_rport *rport;
67becc00 3922 scsi_qla_host_t *base_vha;
044d78e1 3923 unsigned long flags;
d97994dc 3924
3925 if (!fcport->rport)
3926 return;
3927
3928 rport = fcport->rport;
3929 if (defer) {
67becc00 3930 base_vha = pci_get_drvdata(vha->hw->pdev);
044d78e1 3931 spin_lock_irqsave(vha->host->host_lock, flags);
d97994dc 3932 fcport->drport = rport;
044d78e1 3933 spin_unlock_irqrestore(vha->host->host_lock, flags);
df673274 3934 qlt_do_generation_tick(vha, &base_vha->total_fcport_update_gen);
67becc00
AV		 3935 set_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags);
3936 qla2xxx_wake_dpc(base_vha);
2d70c103 3937 } else {
df673274 3938 int now;
726b8548 3939 if (rport) {
83548fe2
QT		 3940 ql_dbg(ql_dbg_disc, fcport->vha, 0x2109,
3941 "%s %8phN. rport %p roles %x\n",
3942 __func__, fcport->port_name, rport,
3943 rport->roles);
d20ed91b 3944 fc_remote_port_delete(rport);
726b8548 3945 }
df673274 3946 qlt_do_generation_tick(vha, &now);
2d70c103 3947 }
d97994dc 3948}
3949
1da177e4
LT		 3950/*
3951 * qla2x00_mark_device_lost Updates fcport state when device goes offline.
3952 *
3953 * Input: ha = adapter block pointer. fcport = port structure pointer.
3954 *
3955 * Return: None.
3956 *
3957 * Context:
3958 */
e315cd28 3959void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport,
d97994dc 3960 int do_login, int defer)
1da177e4 3961{
8ae6d9c7
GM		 3962 if (IS_QLAFX00(vha->hw)) {
3963 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
3964 qla2x00_schedule_rport_del(vha, fcport, defer);
3965 return;
3966 }
3967
2c3dfe3f 3968 if (atomic_read(&fcport->state) == FCS_ONLINE &&
c6d39e23 3969 vha->vp_idx == fcport->vha->vp_idx) {
ec426e10 3970 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
e315cd28
AC		 3971 qla2x00_schedule_rport_del(vha, fcport, defer);
3972 }
fa2a1ce5 3973 /*
1da177e4
LT		 3974 * We may need to retry the login, so don't change the state of the
3975 * port but do the retries.
3976 */
3977 if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD)
ec426e10 3978 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
1da177e4
LT		 3979
3980 if (!do_login)
3981 return;
3982
a1d0285e 3983 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
1da177e4
LT		 3984}
3985
3986/*
3987 * qla2x00_mark_all_devices_lost
3988 * Updates fcport state when device goes offline.
3989 *
3990 * Input:
3991 * ha = adapter block pointer.
3992 * fcport = port structure pointer.
3993 *
3994 * Return:
3995 * None.
3996 *
3997 * Context:
3998 */
3999void
e315cd28 4000qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha, int defer)
1da177e4
LT		 4001{
4002 fc_port_t *fcport;
4003
83548fe2
QT		 4004 ql_dbg(ql_dbg_disc, vha, 0x20f1,
4005 "Mark all dev lost\n");
726b8548 4006
e315cd28 4007 list_for_each_entry(fcport, &vha->vp_fcports, list) {
726b8548 4008 fcport->scan_state = 0;
d8630bb9 4009 qlt_schedule_sess_for_deletion(fcport);
726b8548 4010
c6d39e23 4011 if (vha->vp_idx != 0 && vha->vp_idx != fcport->vha->vp_idx)
1da177e4 4012 continue;
0d6e61bc 4013
1da177e4
LT		 4014 /*
4015 * No point in marking the device as lost, if the device is
4016 * already DEAD.
4017 */
4018 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD)
4019 continue;
e315cd28 4020 if (atomic_read(&fcport->state) == FCS_ONLINE) {
ec426e10 4021 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
0d6e61bc
AV		 4022 if (defer)
4023 qla2x00_schedule_rport_del(vha, fcport, defer);
c6d39e23 4024 else if (vha->vp_idx == fcport->vha->vp_idx)
0d6e61bc
AV		 4025 qla2x00_schedule_rport_del(vha, fcport, defer);
4026 }
1da177e4
LT		 4027 }
4028}
4029
4030/*
4031* qla2x00_mem_alloc
4032* Allocates adapter memory.
4033*
4034* Returns:
4035* 0 = success.
e8711085 4036* !0 = failure.
1da177e4 4037*/
e8711085 4038static int
73208dfd
AC		 4039qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len,
4040 struct req_que **req, struct rsp_que **rsp)
1da177e4
LT		 4041{
4042 char name[16];
1da177e4 4043
e8711085 4044 ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size,
e315cd28 4045 &ha->init_cb_dma, GFP_KERNEL);
e8711085 4046 if (!ha->init_cb)
e315cd28 4047 goto fail;
e8711085 4048
2d70c103
NB		 4049 if (qlt_mem_alloc(ha) < 0)
4050 goto fail_free_init_cb;
4051
642ef983
CD		 4052 ha->gid_list = dma_alloc_coherent(&ha->pdev->dev,
4053 qla2x00_gid_list_size(ha), &ha->gid_list_dma, GFP_KERNEL);
e315cd28 4054 if (!ha->gid_list)
2d70c103 4055 goto fail_free_tgt_mem;
1da177e4 4056
e8711085
AV		 4057 ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep);
4058 if (!ha->srb_mempool)
e315cd28 4059 goto fail_free_gid_list;
e8711085 4060
7ec0effd 4061 if (IS_P3P_TYPE(ha)) {
a9083016
GM		 4062 /* Allocate cache for CT6 Ctx. */
4063 if (!ctx_cachep) {
4064 ctx_cachep = kmem_cache_create("qla2xxx_ctx",
4065 sizeof(struct ct6_dsd), 0,
4066 SLAB_HWCACHE_ALIGN, NULL);
4067 if (!ctx_cachep)
fc1ffd6c 4068 goto fail_free_srb_mempool;
a9083016
GM		 4069 }
4070 ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ,
4071 ctx_cachep);
4072 if (!ha->ctx_mempool)
4073 goto fail_free_srb_mempool;
7c3df132
SK		 4074 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021,
4075 "ctx_cachep=%p ctx_mempool=%p.\n",
4076 ctx_cachep, ha->ctx_mempool);
a9083016
GM		 4077 }
4078
e8711085
AV		 4079 /* Get memory for cached NVRAM */
4080 ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL);
4081 if (!ha->nvram)
a9083016 4082 goto fail_free_ctx_mempool;
e8711085 4083
e315cd28
AC		 4084 snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME,
4085 ha->pdev->device);
4086 ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev,
4087 DMA_POOL_SIZE, 8, 0);
4088 if (!ha->s_dma_pool)
4089 goto fail_free_nvram;
4090
7c3df132
SK		 4091 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022,
4092 "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n",
4093 ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool);
4094
7ec0effd 4095 if (IS_P3P_TYPE(ha) || ql2xenabledif) {
a9083016
GM		 4096 ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev,
4097 DSD_LIST_DMA_POOL_SIZE, 8, 0);
4098 if (!ha->dl_dma_pool) {
7c3df132
SK		 4099 ql_log_pci(ql_log_fatal, ha->pdev, 0x0023,
4100 "Failed to allocate memory for dl_dma_pool.\n");
a9083016
GM		 4101 goto fail_s_dma_pool;
4102 }
4103
4104 ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev,
4105 FCP_CMND_DMA_POOL_SIZE, 8, 0);
4106 if (!ha->fcp_cmnd_dma_pool) {
7c3df132
SK		 4107 ql_log_pci(ql_log_fatal, ha->pdev, 0x0024,
4108 "Failed to allocate memory for fcp_cmnd_dma_pool.\n");
a9083016
GM		 4109 goto fail_dl_dma_pool;
4110 }
50b81275
GM		 4111
4112 if (ql2xenabledif) {
4113 u64 bufsize = DIF_BUNDLING_DMA_POOL_SIZE;
4114 struct dsd_dma *dsd, *nxt;
4115 uint i;
4116 /* Creata a DMA pool of buffers for DIF bundling */
4117 ha->dif_bundl_pool = dma_pool_create(name,
4118 &ha->pdev->dev, DIF_BUNDLING_DMA_POOL_SIZE, 8, 0);
4119 if (!ha->dif_bundl_pool) {
4120 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0024,
4121 "%s: failed create dif_bundl_pool\n",
4122 __func__);
4123 goto fail_dif_bundl_dma_pool;
4124 }
4125
4126 INIT_LIST_HEAD(&ha->pool.good.head);
4127 INIT_LIST_HEAD(&ha->pool.unusable.head);
4128 ha->pool.good.count = 0;
4129 ha->pool.unusable.count = 0;
4130 for (i = 0; i < 128; i++) {
4131 dsd = kzalloc(sizeof(*dsd), GFP_ATOMIC);
4132 if (!dsd) {
4133 ql_dbg_pci(ql_dbg_init, ha->pdev,
4134 0xe0ee, "%s: failed alloc dsd\n",
4135 __func__);
4136 return 1;
4137 }
4138 ha->dif_bundle_kallocs++;
4139
4140 dsd->dsd_addr = dma_pool_alloc(
4141 ha->dif_bundl_pool, GFP_ATOMIC,
4142 &dsd->dsd_list_dma);
4143 if (!dsd->dsd_addr) {
4144 ql_dbg_pci(ql_dbg_init, ha->pdev,
4145 0xe0ee,
4146 "%s: failed alloc ->dsd_addr\n",
4147 __func__);
4148 kfree(dsd);
4149 ha->dif_bundle_kallocs--;
4150 continue;
4151 }
4152 ha->dif_bundle_dma_allocs++;
4153
4154 /*
4155 * if DMA buffer crosses 4G boundary,
4156 * put it on bad list
4157 */
4158 if (MSD(dsd->dsd_list_dma) ^
4159 MSD(dsd->dsd_list_dma + bufsize)) {
4160 list_add_tail(&dsd->list,
4161 &ha->pool.unusable.head);
4162 ha->pool.unusable.count++;
4163 } else {
4164 list_add_tail(&dsd->list,
4165 &ha->pool.good.head);
4166 ha->pool.good.count++;
4167 }
4168 }
4169
4170 /* return the good ones back to the pool */
4171 list_for_each_entry_safe(dsd, nxt,
4172 &ha->pool.good.head, list) {
4173 list_del(&dsd->list);
4174 dma_pool_free(ha->dif_bundl_pool,
4175 dsd->dsd_addr, dsd->dsd_list_dma);
4176 ha->dif_bundle_dma_allocs--;
4177 kfree(dsd);
4178 ha->dif_bundle_kallocs--;
4179 }
4180
4181 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0024,
4182 "%s: dif dma pool (good=%u unusable=%u)\n",
4183 __func__, ha->pool.good.count,
4184 ha->pool.unusable.count);
4185 }
4186
7c3df132 4187 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025,
50b81275
GM		 4188 "dl_dma_pool=%p fcp_cmnd_dma_pool=%p dif_bundl_pool=%p.\n",
4189 ha->dl_dma_pool, ha->fcp_cmnd_dma_pool,
4190 ha->dif_bundl_pool);
a9083016
GM		 4191 }
4192
e8711085
AV		 4193 /* Allocate memory for SNS commands */
4194 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
e315cd28 4195 /* Get consistent memory allocated for SNS commands */
e8711085 4196 ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev,
e315cd28 4197 sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL);
e8711085 4198 if (!ha->sns_cmd)
e315cd28 4199 goto fail_dma_pool;
7c3df132 4200 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026,
d8424f68 4201 "sns_cmd: %p.\n", ha->sns_cmd);
e8711085 4202 } else {
e315cd28 4203 /* Get consistent memory allocated for MS IOCB */
e8711085 4204 ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
e315cd28 4205 &ha->ms_iocb_dma);
e8711085 4206 if (!ha->ms_iocb)
e315cd28
AC		 4207 goto fail_dma_pool;
4208 /* Get consistent memory allocated for CT SNS commands */
e8711085 4209 ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev,
e315cd28 4210 sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL);
e8711085
AV		 4211 if (!ha->ct_sns)
4212 goto fail_free_ms_iocb;
7c3df132
SK		 4213 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027,
4214 "ms_iocb=%p ct_sns=%p.\n",
4215 ha->ms_iocb, ha->ct_sns);
1da177e4
LT		 4216 }
4217
e315cd28 4218 /* Allocate memory for request ring */
73208dfd
AC		 4219 *req = kzalloc(sizeof(struct req_que), GFP_KERNEL);
4220 if (!*req) {
7c3df132
SK		 4221 ql_log_pci(ql_log_fatal, ha->pdev, 0x0028,
4222 "Failed to allocate memory for req.\n");
e315cd28
AC		 4223 goto fail_req;
4224 }
73208dfd
AC		 4225 (*req)->length = req_len;
4226 (*req)->ring = dma_alloc_coherent(&ha->pdev->dev,
4227 ((*req)->length + 1) * sizeof(request_t),
4228 &(*req)->dma, GFP_KERNEL);
4229 if (!(*req)->ring) {
7c3df132
SK		 4230 ql_log_pci(ql_log_fatal, ha->pdev, 0x0029,
4231 "Failed to allocate memory for req_ring.\n");
e315cd28
AC		 4232 goto fail_req_ring;
4233 }
4234 /* Allocate memory for response ring */
73208dfd
AC		 4235 *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL);
4236 if (!*rsp) {
7c3df132
SK		 4237 ql_log_pci(ql_log_fatal, ha->pdev, 0x002a,
4238 "Failed to allocate memory for rsp.\n");
e315cd28
AC		 4239 goto fail_rsp;
4240 }
73208dfd
AC		 4241 (*rsp)->hw = ha;
4242 (*rsp)->length = rsp_len;
4243 (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev,
4244 ((*rsp)->length + 1) * sizeof(response_t),
4245 &(*rsp)->dma, GFP_KERNEL);
4246 if (!(*rsp)->ring) {
7c3df132
SK		 4247 ql_log_pci(ql_log_fatal, ha->pdev, 0x002b,
4248 "Failed to allocate memory for rsp_ring.\n");
e315cd28
AC		 4249 goto fail_rsp_ring;
4250 }
73208dfd
AC		 4251 (*req)->rsp = *rsp;
4252 (*rsp)->req = *req;
7c3df132
SK		 4253 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c,
4254 "req=%p req->length=%d req->ring=%p rsp=%p "
4255 "rsp->length=%d rsp->ring=%p.\n",
4256 *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length,
4257 (*rsp)->ring);
73208dfd
AC		 4258 /* Allocate memory for NVRAM data for vports */
4259 if (ha->nvram_npiv_size) {
6396bb22
KC		 4260 ha->npiv_info = kcalloc(ha->nvram_npiv_size,
4261 sizeof(struct qla_npiv_entry),
4262 GFP_KERNEL);
73208dfd 4263 if (!ha->npiv_info) {
7c3df132
SK		 4264 ql_log_pci(ql_log_fatal, ha->pdev, 0x002d,
4265 "Failed to allocate memory for npiv_info.\n");
73208dfd
AC		 4266 goto fail_npiv_info;
4267 }
4268 } else
4269 ha->npiv_info = NULL;
e8711085 4270
b64b0e8f 4271 /* Get consistent memory allocated for EX-INIT-CB. */
ecc89f25
JC		 4272 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) ||
4273 IS_QLA28XX(ha)) {
b64b0e8f
AV		 4274 ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
4275 &ha->ex_init_cb_dma);
4276 if (!ha->ex_init_cb)
4277 goto fail_ex_init_cb;
7c3df132
SK		 4278 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e,
4279 "ex_init_cb=%p.\n", ha->ex_init_cb);
b64b0e8f
AV		 4280 }
4281
a9083016
GM		 4282 INIT_LIST_HEAD(&ha->gbl_dsd_list);
4283
5ff1d584
AV		 4284 /* Get consistent memory allocated for Async Port-Database. */
4285 if (!IS_FWI2_CAPABLE(ha)) {
4286 ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
4287 &ha->async_pd_dma);
4288 if (!ha->async_pd)
4289 goto fail_async_pd;
7c3df132
SK		 4290 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f,
4291 "async_pd=%p.\n", ha->async_pd);
5ff1d584
AV		 4292 }
4293
e315cd28 4294 INIT_LIST_HEAD(&ha->vp_list);
5f16b331
CD		 4295
4296 /* Allocate memory for our loop_id bitmap */
6396bb22
KC		 4297 ha->loop_id_map = kcalloc(BITS_TO_LONGS(LOOPID_MAP_SIZE),
4298 sizeof(long),
4299 GFP_KERNEL);
5f16b331 4300 if (!ha->loop_id_map)
fc1ffd6c 4301 goto fail_loop_id_map;
5f16b331
CD		 4302 else {
4303 qla2x00_set_reserved_loop_ids(ha);
4304 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0123,
b2a72ec3 4305 "loop_id_map=%p.\n", ha->loop_id_map);
5f16b331
CD		 4306 }
4307
e4e3a2ce
QT		 4308 ha->sfp_data = dma_alloc_coherent(&ha->pdev->dev,
4309 SFP_DEV_SIZE, &ha->sfp_data_dma, GFP_KERNEL);
4310 if (!ha->sfp_data) {
4311 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b,
4312 "Unable to allocate memory for SFP read-data.\n");
4313 goto fail_sfp_data;
4314 }
4315
3f006ac3
MH		 4316 ha->flt = dma_alloc_coherent(&ha->pdev->dev,
4317 sizeof(struct qla_flt_header) + FLT_REGIONS_SIZE, &ha->flt_dma,
4318 GFP_KERNEL);
4319 if (!ha->flt) {
4320 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b,
4321 "Unable to allocate memory for FLT.\n");
4322 goto fail_flt_buffer;
4323 }
4324
b2a72ec3 4325 return 0;
e315cd28 4326
3f006ac3
MH		 4327fail_flt_buffer:
4328 dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE,
4329 ha->sfp_data, ha->sfp_data_dma);
e4e3a2ce
QT		 4330fail_sfp_data:
4331 kfree(ha->loop_id_map);
fc1ffd6c
QT		 4332fail_loop_id_map:
4333 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
5ff1d584
AV		 4334fail_async_pd:
4335 dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma);
b64b0e8f
AV		 4336fail_ex_init_cb:
4337 kfree(ha->npiv_info);
73208dfd
AC		 4338fail_npiv_info:
4339 dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) *
4340 sizeof(response_t), (*rsp)->ring, (*rsp)->dma);
4341 (*rsp)->ring = NULL;
4342 (*rsp)->dma = 0;
e315cd28 4343fail_rsp_ring:
73208dfd 4344 kfree(*rsp);
6d634067 4345 *rsp = NULL;
e315cd28 4346fail_rsp:
73208dfd
AC		 4347 dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) *
4348 sizeof(request_t), (*req)->ring, (*req)->dma);
4349 (*req)->ring = NULL;
4350 (*req)->dma = 0;
e315cd28 4351fail_req_ring:
73208dfd 4352 kfree(*req);
6d634067 4353 *req = NULL;
e315cd28
AC		 4354fail_req:
4355 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
4356 ha->ct_sns, ha->ct_sns_dma);
4357 ha->ct_sns = NULL;
4358 ha->ct_sns_dma = 0;
e8711085
AV		 4359fail_free_ms_iocb:
4360 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
4361 ha->ms_iocb = NULL;
4362 ha->ms_iocb_dma = 0;
fc1ffd6c
QT		 4363
4364 if (ha->sns_cmd)
4365 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
4366 ha->sns_cmd, ha->sns_cmd_dma);
e315cd28 4367fail_dma_pool:
50b81275
GM		 4368 if (ql2xenabledif) {
4369 struct dsd_dma *dsd, *nxt;
4370
4371 list_for_each_entry_safe(dsd, nxt, &ha->pool.unusable.head,
4372 list) {
4373 list_del(&dsd->list);
4374 dma_pool_free(ha->dif_bundl_pool, dsd->dsd_addr,
4375 dsd->dsd_list_dma);
4376 ha->dif_bundle_dma_allocs--;
4377 kfree(dsd);
4378 ha->dif_bundle_kallocs--;
4379 ha->pool.unusable.count--;
4380 }
4381 dma_pool_destroy(ha->dif_bundl_pool);
4382 ha->dif_bundl_pool = NULL;
4383 }
4384
4385fail_dif_bundl_dma_pool:
bad75002 4386 if (IS_QLA82XX(ha) || ql2xenabledif) {
a9083016
GM		 4387 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
4388 ha->fcp_cmnd_dma_pool = NULL;
4389 }
4390fail_dl_dma_pool:
bad75002 4391 if (IS_QLA82XX(ha) || ql2xenabledif) {
a9083016
GM		 4392 dma_pool_destroy(ha->dl_dma_pool);
4393 ha->dl_dma_pool = NULL;
4394 }
4395fail_s_dma_pool:
e315cd28
AC		 4396 dma_pool_destroy(ha->s_dma_pool);
4397 ha->s_dma_pool = NULL;
e8711085
AV		 4398fail_free_nvram:
4399 kfree(ha->nvram);
4400 ha->nvram = NULL;
a9083016 4401fail_free_ctx_mempool:
75c1d48a 4402 mempool_destroy(ha->ctx_mempool);
a9083016 4403 ha->ctx_mempool = NULL;
e8711085 4404fail_free_srb_mempool:
75c1d48a 4405 mempool_destroy(ha->srb_mempool);
e8711085 4406 ha->srb_mempool = NULL;
e8711085 4407fail_free_gid_list:
642ef983
CD		 4408 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
4409 ha->gid_list,
e315cd28 4410 ha->gid_list_dma);
e8711085
AV		 4411 ha->gid_list = NULL;
4412 ha->gid_list_dma = 0;
2d70c103
NB		 4413fail_free_tgt_mem:
4414 qlt_mem_free(ha);
e315cd28
AC		 4415fail_free_init_cb:
4416 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb,
4417 ha->init_cb_dma);
4418 ha->init_cb = NULL;
4419 ha->init_cb_dma = 0;
e8711085 4420fail:
7c3df132
SK		 4421 ql_log(ql_log_fatal, NULL, 0x0030,
4422 "Memory allocation failure.\n");
e8711085 4423 return -ENOMEM;
1da177e4
LT		 4424}
4425
b0d6cabd
HM		 4426int
4427qla2x00_set_exlogins_buffer(scsi_qla_host_t *vha)
4428{
4429 int rval;
4430 uint16_t size, max_cnt, temp;
4431 struct qla_hw_data *ha = vha->hw;
4432
4433 /* Return if we don't need to alloacate any extended logins */
4434 if (!ql2xexlogins)
4435 return QLA_SUCCESS;
4436
99e1b683
QT		 4437 if (!IS_EXLOGIN_OFFLD_CAPABLE(ha))
4438 return QLA_SUCCESS;
4439
b0d6cabd
HM		 4440 ql_log(ql_log_info, vha, 0xd021, "EXLOGIN count: %d.\n", ql2xexlogins);
4441 max_cnt = 0;
4442 rval = qla_get_exlogin_status(vha, &size, &max_cnt);
4443 if (rval != QLA_SUCCESS) {
4444 ql_log_pci(ql_log_fatal, ha->pdev, 0xd029,
4445 "Failed to get exlogin status.\n");
4446 return rval;
4447 }
4448
4449 temp = (ql2xexlogins > max_cnt) ? max_cnt : ql2xexlogins;
99e1b683
QT		 4450 temp *= size;
4451
4452 if (temp != ha->exlogin_size) {
4453 qla2x00_free_exlogin_buffer(ha);
4454 ha->exlogin_size = temp;
4455
4456 ql_log(ql_log_info, vha, 0xd024,
4457 "EXLOGIN: max_logins=%d, portdb=0x%x, total=%d.\n",
4458 max_cnt, size, temp);
4459
4460 ql_log(ql_log_info, vha, 0xd025,
4461 "EXLOGIN: requested size=0x%x\n", ha->exlogin_size);
4462
4463 /* Get consistent memory for extended logins */
4464 ha->exlogin_buf = dma_alloc_coherent(&ha->pdev->dev,
4465 ha->exlogin_size, &ha->exlogin_buf_dma, GFP_KERNEL);
4466 if (!ha->exlogin_buf) {
4467 ql_log_pci(ql_log_fatal, ha->pdev, 0xd02a,
b0d6cabd 4468 "Failed to allocate memory for exlogin_buf_dma.\n");
99e1b683
QT		 4469 return -ENOMEM;
4470 }
b0d6cabd
HM		 4471 }
4472
4473 /* Now configure the dma buffer */
4474 rval = qla_set_exlogin_mem_cfg(vha, ha->exlogin_buf_dma);
4475 if (rval) {
83548fe2 4476 ql_log(ql_log_fatal, vha, 0xd033,
b0d6cabd
HM		 4477 "Setup extended login buffer ****FAILED****.\n");
4478 qla2x00_free_exlogin_buffer(ha);
4479 }
4480
4481 return rval;
4482}
4483
4484/*
4485* qla2x00_free_exlogin_buffer
4486*
4487* Input:
4488* ha = adapter block pointer
4489*/
4490void
4491qla2x00_free_exlogin_buffer(struct qla_hw_data *ha)
4492{
4493 if (ha->exlogin_buf) {
4494 dma_free_coherent(&ha->pdev->dev, ha->exlogin_size,
4495 ha->exlogin_buf, ha->exlogin_buf_dma);
4496 ha->exlogin_buf = NULL;
4497 ha->exlogin_size = 0;
4498 }
4499}
4500
99e1b683
QT		 4501static void
4502qla2x00_number_of_exch(scsi_qla_host_t *vha, u32 *ret_cnt, u16 max_cnt)
4503{
4504 u32 temp;
0645cb83 4505 struct init_cb_81xx *icb = (struct init_cb_81xx *)&vha->hw->init_cb;
99e1b683
QT		 4506 *ret_cnt = FW_DEF_EXCHANGES_CNT;
4507
d1e3635a
QT		 4508 if (max_cnt > vha->hw->max_exchg)
4509 max_cnt = vha->hw->max_exchg;
4510
99e1b683 4511 if (qla_ini_mode_enabled(vha)) {
0645cb83
QT		 4512 if (vha->ql2xiniexchg > max_cnt)
4513 vha->ql2xiniexchg = max_cnt;
4514
4515 if (vha->ql2xiniexchg > FW_DEF_EXCHANGES_CNT)
4516 *ret_cnt = vha->ql2xiniexchg;
99e1b683 4517
99e1b683 4518 } else if (qla_tgt_mode_enabled(vha)) {
0645cb83
QT		 4519 if (vha->ql2xexchoffld > max_cnt) {
4520 vha->ql2xexchoffld = max_cnt;
4521 icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld);
4522 }
99e1b683 4523
0645cb83
QT		 4524 if (vha->ql2xexchoffld > FW_DEF_EXCHANGES_CNT)
4525 *ret_cnt = vha->ql2xexchoffld;
99e1b683 4526 } else if (qla_dual_mode_enabled(vha)) {
0645cb83 4527 temp = vha->ql2xiniexchg + vha->ql2xexchoffld;
99e1b683 4528 if (temp > max_cnt) {
0645cb83
QT		 4529 vha->ql2xiniexchg -= (temp - max_cnt)/2;
4530 vha->ql2xexchoffld -= (((temp - max_cnt)/2) + 1);
99e1b683 4531 temp = max_cnt;
0645cb83 4532 icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld);
99e1b683
QT		 4533 }
4534
4535 if (temp > FW_DEF_EXCHANGES_CNT)
4536 *ret_cnt = temp;
4537 }
4538}
4539
2f56a7f1
HM		 4540int
4541qla2x00_set_exchoffld_buffer(scsi_qla_host_t *vha)
4542{
4543 int rval;
d1e3635a
QT		 4544 u16 size, max_cnt;
4545 u32 actual_cnt, totsz;
2f56a7f1
HM		 4546 struct qla_hw_data *ha = vha->hw;
4547
99e1b683
QT		 4548 if (!ha->flags.exchoffld_enabled)
4549 return QLA_SUCCESS;
4550
4551 if (!IS_EXCHG_OFFLD_CAPABLE(ha))
2f56a7f1
HM		 4552 return QLA_SUCCESS;
4553
2f56a7f1
HM		 4554 max_cnt = 0;
4555 rval = qla_get_exchoffld_status(vha, &size, &max_cnt);
4556 if (rval != QLA_SUCCESS) {
4557 ql_log_pci(ql_log_fatal, ha->pdev, 0xd012,
4558 "Failed to get exlogin status.\n");
4559 return rval;
4560 }
4561
d1e3635a
QT		 4562 qla2x00_number_of_exch(vha, &actual_cnt, max_cnt);
4563 ql_log(ql_log_info, vha, 0xd014,
4564 "Actual exchange offload count: %d.\n", actual_cnt);
4565
4566 totsz = actual_cnt * size;
2f56a7f1 4567
d1e3635a 4568 if (totsz != ha->exchoffld_size) {
99e1b683 4569 qla2x00_free_exchoffld_buffer(ha);
0645cb83
QT		 4570 if (actual_cnt <= FW_DEF_EXCHANGES_CNT) {
4571 ha->exchoffld_size = 0;
4572 ha->flags.exchoffld_enabled = 0;
4573 return QLA_SUCCESS;
4574 }
4575
d1e3635a 4576 ha->exchoffld_size = totsz;
99e1b683
QT		 4577
4578 ql_log(ql_log_info, vha, 0xd016,
d1e3635a
QT		 4579 "Exchange offload: max_count=%d, actual count=%d entry sz=0x%x, total sz=0x%x\n",
4580 max_cnt, actual_cnt, size, totsz);
99e1b683
QT		 4581
4582 ql_log(ql_log_info, vha, 0xd017,
4583 "Exchange Buffers requested size = 0x%x\n",
4584 ha->exchoffld_size);
4585
4586 /* Get consistent memory for extended logins */
4587 ha->exchoffld_buf = dma_alloc_coherent(&ha->pdev->dev,
4588 ha->exchoffld_size, &ha->exchoffld_buf_dma, GFP_KERNEL);
4589 if (!ha->exchoffld_buf) {
4590 ql_log_pci(ql_log_fatal, ha->pdev, 0xd013,
d1e3635a
QT		 4591 "Failed to allocate memory for Exchange Offload.\n");
4592
4593 if (ha->max_exchg >
4594 (FW_DEF_EXCHANGES_CNT + REDUCE_EXCHANGES_CNT)) {
4595 ha->max_exchg -= REDUCE_EXCHANGES_CNT;
4596 } else if (ha->max_exchg >
4597 (FW_DEF_EXCHANGES_CNT + 512)) {
4598 ha->max_exchg -= 512;
4599 } else {
4600 ha->flags.exchoffld_enabled = 0;
4601 ql_log_pci(ql_log_fatal, ha->pdev, 0xd013,
4602 "Disabling Exchange offload due to lack of memory\n");
4603 }
4604 ha->exchoffld_size = 0;
4605
99e1b683
QT		 4606 return -ENOMEM;
4607 }
0645cb83
QT		 4608 } else if (!ha->exchoffld_buf || (actual_cnt <= FW_DEF_EXCHANGES_CNT)) {
4609 /* pathological case */
4610 qla2x00_free_exchoffld_buffer(ha);
4611 ha->exchoffld_size = 0;
4612 ha->flags.exchoffld_enabled = 0;
4613 ql_log(ql_log_info, vha, 0xd016,
4614 "Exchange offload not enable: offld size=%d, actual count=%d entry sz=0x%x, total sz=0x%x.\n",
4615 ha->exchoffld_size, actual_cnt, size, totsz);
4616 return 0;
2f56a7f1
HM		 4617 }
4618
4619 /* Now configure the dma buffer */
99e1b683 4620 rval = qla_set_exchoffld_mem_cfg(vha);
2f56a7f1
HM		 4621 if (rval) {
4622 ql_log(ql_log_fatal, vha, 0xd02e,
4623 "Setup exchange offload buffer ****FAILED****.\n");
4624 qla2x00_free_exchoffld_buffer(ha);
99e1b683
QT		 4625 } else {
4626 /* re-adjust number of target exchange */
4627 struct init_cb_81xx *icb = (struct init_cb_81xx *)ha->init_cb;
4628
4629 if (qla_ini_mode_enabled(vha))
4630 icb->exchange_count = 0;
4631 else
0645cb83 4632 icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld);
2f56a7f1
HM		 4633 }
4634
4635 return rval;
4636}
4637
4638/*
4639* qla2x00_free_exchoffld_buffer
4640*
4641* Input:
4642* ha = adapter block pointer
4643*/
4644void
4645qla2x00_free_exchoffld_buffer(struct qla_hw_data *ha)
4646{
4647 if (ha->exchoffld_buf) {
4648 dma_free_coherent(&ha->pdev->dev, ha->exchoffld_size,
4649 ha->exchoffld_buf, ha->exchoffld_buf_dma);
4650 ha->exchoffld_buf = NULL;
4651 ha->exchoffld_size = 0;
4652 }
4653}
4654
1da177e4 4655/*
e30d1756
MI		 4656* qla2x00_free_fw_dump
4657* Frees fw dump stuff.
1da177e4
LT		 4658*
4659* Input:
7ec0effd 4660* ha = adapter block pointer
1da177e4 4661*/
a824ebb3 4662static void
e30d1756 4663qla2x00_free_fw_dump(struct qla_hw_data *ha)
1da177e4 4664{
a28d9e4e
JC		 4665 struct fwdt *fwdt = ha->fwdt;
4666 uint j;
4667
df613b96 4668 if (ha->fce)
f73cb695
CD		 4669 dma_free_coherent(&ha->pdev->dev,
4670 FCE_SIZE, ha->fce, ha->fce_dma);
df613b96 4671
f73cb695
CD		 4672 if (ha->eft)
4673 dma_free_coherent(&ha->pdev->dev,
4674 EFT_SIZE, ha->eft, ha->eft_dma);
4675
4676 if (ha->fw_dump)
a7a167bf 4677 vfree(ha->fw_dump);
f73cb695 4678
e30d1756
MI		 4679 ha->fce = NULL;
4680 ha->fce_dma = 0;
4681 ha->eft = NULL;
4682 ha->eft_dma = 0;
e30d1756 4683 ha->fw_dumped = 0;
61f098dd 4684 ha->fw_dump_cap_flags = 0;
e30d1756 4685 ha->fw_dump_reading = 0;
f73cb695
CD		 4686 ha->fw_dump = NULL;
4687 ha->fw_dump_len = 0;
a28d9e4e
JC		 4688
4689 for (j = 0; j < 2; j++, fwdt++) {
4690 if (fwdt->template)
4691 vfree(fwdt->template);
4692 fwdt->template = NULL;
4693 fwdt->length = 0;
4694 }
e30d1756
MI		 4695}
4696
4697/*
4698* qla2x00_mem_free
4699* Frees all adapter allocated memory.
4700*
4701* Input:
4702* ha = adapter block pointer.
4703*/
4704static void
4705qla2x00_mem_free(struct qla_hw_data *ha)
4706{
4707 qla2x00_free_fw_dump(ha);
4708
81178772
SK		 4709 if (ha->mctp_dump)
4710 dma_free_coherent(&ha->pdev->dev, MCTP_DUMP_SIZE, ha->mctp_dump,
4711 ha->mctp_dump_dma);
4712
75c1d48a 4713 mempool_destroy(ha->srb_mempool);
a7a167bf 4714
11bbc1d8
AV		 4715 if (ha->dcbx_tlv)
4716 dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE,
4717 ha->dcbx_tlv, ha->dcbx_tlv_dma);
4718
ce0423f4
AV		 4719 if (ha->xgmac_data)
4720 dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE,
4721 ha->xgmac_data, ha->xgmac_data_dma);
4722
1da177e4
LT		 4723 if (ha->sns_cmd)
4724 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
e315cd28 4725 ha->sns_cmd, ha->sns_cmd_dma);
1da177e4
LT		 4726
4727 if (ha->ct_sns)
4728 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
e315cd28 4729 ha->ct_sns, ha->ct_sns_dma);
1da177e4 4730
88729e53 4731 if (ha->sfp_data)
e4e3a2ce
QT		 4732 dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE, ha->sfp_data,
4733 ha->sfp_data_dma);
88729e53 4734
3f006ac3
MH		 4735 if (ha->flt)
4736 dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE,
4737 ha->flt, ha->flt_dma);
4738
1da177e4
LT		 4739 if (ha->ms_iocb)
4740 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
4741
b64b0e8f 4742 if (ha->ex_init_cb)
a9083016
GM		 4743 dma_pool_free(ha->s_dma_pool,
4744 ha->ex_init_cb, ha->ex_init_cb_dma);
b64b0e8f 4745
5ff1d584
AV		 4746 if (ha->async_pd)
4747 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
4748
75c1d48a 4749 dma_pool_destroy(ha->s_dma_pool);
1da177e4 4750
1da177e4 4751 if (ha->gid_list)
642ef983
CD		 4752 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
4753 ha->gid_list, ha->gid_list_dma);
1da177e4 4754
a9083016
GM		 4755 if (IS_QLA82XX(ha)) {
4756 if (!list_empty(&ha->gbl_dsd_list)) {
4757 struct dsd_dma *dsd_ptr, *tdsd_ptr;
4758
4759 /* clean up allocated prev pool */
4760 list_for_each_entry_safe(dsd_ptr,
4761 tdsd_ptr, &ha->gbl_dsd_list, list) {
4762 dma_pool_free(ha->dl_dma_pool,
4763 dsd_ptr->dsd_addr, dsd_ptr->dsd_list_dma);
4764 list_del(&dsd_ptr->list);
4765 kfree(dsd_ptr);
4766 }
4767 }
4768 }
4769
75c1d48a 4770 dma_pool_destroy(ha->dl_dma_pool);
a9083016 4771
75c1d48a 4772 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
a9083016 4773
75c1d48a 4774 mempool_destroy(ha->ctx_mempool);
a9083016 4775
50b81275
GM		 4776 if (ql2xenabledif) {
4777 struct dsd_dma *dsd, *nxt;
4778
4779 list_for_each_entry_safe(dsd, nxt, &ha->pool.unusable.head,
4780 list) {
4781 list_del(&dsd->list);
4782 dma_pool_free(ha->dif_bundl_pool, dsd->dsd_addr,
4783 dsd->dsd_list_dma);
4784 ha->dif_bundle_dma_allocs--;
4785 kfree(dsd);
4786 ha->dif_bundle_kallocs--;
4787 ha->pool.unusable.count--;
4788 }
4789 list_for_each_entry_safe(dsd, nxt, &ha->pool.good.head, list) {
4790 list_del(&dsd->list);
4791 dma_pool_free(ha->dif_bundl_pool, dsd->dsd_addr,
4792 dsd->dsd_list_dma);
4793 ha->dif_bundle_dma_allocs--;
4794 kfree(dsd);
4795 ha->dif_bundle_kallocs--;
4796 }
4797 }
4798
4799 if (ha->dif_bundl_pool)
4800 dma_pool_destroy(ha->dif_bundl_pool);
4801
2d70c103
NB		 4802 qlt_mem_free(ha);
4803
e315cd28
AC		 4804 if (ha->init_cb)
4805 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size,
a9083016 4806 ha->init_cb, ha->init_cb_dma);
6a2cf8d3 4807
6d634067
BK		 4808 vfree(ha->optrom_buffer);
4809 kfree(ha->nvram);
4810 kfree(ha->npiv_info);
4811 kfree(ha->swl);
4812 kfree(ha->loop_id_map);
1da177e4 4813
e8711085 4814 ha->srb_mempool = NULL;
a9083016 4815 ha->ctx_mempool = NULL;
1da177e4
LT		 4816 ha->sns_cmd = NULL;
4817 ha->sns_cmd_dma = 0;
4818 ha->ct_sns = NULL;
4819 ha->ct_sns_dma = 0;
4820 ha->ms_iocb = NULL;
4821 ha->ms_iocb_dma = 0;
1da177e4
LT		 4822 ha->init_cb = NULL;
4823 ha->init_cb_dma = 0;
b64b0e8f
AV		 4824 ha->ex_init_cb = NULL;
4825 ha->ex_init_cb_dma = 0;
5ff1d584
AV		 4826 ha->async_pd = NULL;
4827 ha->async_pd_dma = 0;
6a2cf8d3
BK		 4828 ha->loop_id_map = NULL;
4829 ha->npiv_info = NULL;
4830 ha->optrom_buffer = NULL;
4831 ha->swl = NULL;
4832 ha->nvram = NULL;
4833 ha->mctp_dump = NULL;
4834 ha->dcbx_tlv = NULL;
4835 ha->xgmac_data = NULL;
4836 ha->sfp_data = NULL;
1da177e4
LT		 4837
4838 ha->s_dma_pool = NULL;
a9083016
GM		 4839 ha->dl_dma_pool = NULL;
4840 ha->fcp_cmnd_dma_pool = NULL;
1da177e4 4841
1da177e4
LT		 4842 ha->gid_list = NULL;
4843 ha->gid_list_dma = 0;
2d70c103
NB		 4844
4845 ha->tgt.atio_ring = NULL;
4846 ha->tgt.atio_dma = 0;
4847 ha->tgt.tgt_vp_map = NULL;
e315cd28 4848}
1da177e4 4849
e315cd28
AC		 4850struct scsi_qla_host *qla2x00_create_host(struct scsi_host_template *sht,
4851 struct qla_hw_data *ha)
4852{
4853 struct Scsi_Host *host;
4854 struct scsi_qla_host *vha = NULL;
854165f4 4855
e315cd28 4856 host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t));
41dc529a 4857 if (!host) {
7c3df132
SK		 4858 ql_log_pci(ql_log_fatal, ha->pdev, 0x0107,
4859 "Failed to allocate host from the scsi layer, aborting.\n");
41dc529a 4860 return NULL;
e315cd28
AC		 4861 }
4862
4863 /* Clear our data area */
4864 vha = shost_priv(host);
4865 memset(vha, 0, sizeof(scsi_qla_host_t));
4866
4867 vha->host = host;
4868 vha->host_no = host->host_no;
4869 vha->hw = ha;
4870
0645cb83
QT		 4871 vha->qlini_mode = ql2x_ini_mode;
4872 vha->ql2xexchoffld = ql2xexchoffld;
4873 vha->ql2xiniexchg = ql2xiniexchg;
4874
e315cd28
AC		 4875 INIT_LIST_HEAD(&vha->vp_fcports);
4876 INIT_LIST_HEAD(&vha->work_list);
4877 INIT_LIST_HEAD(&vha->list);
8b2f5ff3
SN		 4878 INIT_LIST_HEAD(&vha->qla_cmd_list);
4879 INIT_LIST_HEAD(&vha->qla_sess_op_cmd_list);
71cdc079 4880 INIT_LIST_HEAD(&vha->logo_list);
b7bd104e 4881 INIT_LIST_HEAD(&vha->plogi_ack_list);
d7459527 4882 INIT_LIST_HEAD(&vha->qp_list);
41dc529a 4883 INIT_LIST_HEAD(&vha->gnl.fcports);
a5d42f4c 4884 INIT_LIST_HEAD(&vha->nvme_rport_list);
2d73ac61 4885 INIT_LIST_HEAD(&vha->gpnid_list);
9b3e0f4d 4886 INIT_WORK(&vha->iocb_work, qla2x00_iocb_work_fn);
e315cd28 4887
f999f4c1 4888 spin_lock_init(&vha->work_lock);
8b2f5ff3 4889 spin_lock_init(&vha->cmd_list_lock);
726b8548 4890 init_waitqueue_head(&vha->fcport_waitQ);
c4a9b538 4891 init_waitqueue_head(&vha->vref_waitq);
f999f4c1 4892
2fdbc65e
BVA		 4893 vha->gnl.size = sizeof(struct get_name_list_extended) *
4894 (ha->max_loop_id + 1);
41dc529a
QT		 4895 vha->gnl.l = dma_alloc_coherent(&ha->pdev->dev,
4896 vha->gnl.size, &vha->gnl.ldma, GFP_KERNEL);
4897 if (!vha->gnl.l) {
83548fe2 4898 ql_log(ql_log_fatal, vha, 0xd04a,
41dc529a
QT		 4899 "Alloc failed for name list.\n");
4900 scsi_remove_host(vha->host);
4901 return NULL;
4902 }
f999f4c1 4903
a4239945
QT		 4904 /* todo: what about ext login? */
4905 vha->scan.size = ha->max_fibre_devices * sizeof(struct fab_scan_rp);
4906 vha->scan.l = vmalloc(vha->scan.size);
4907 if (!vha->scan.l) {
4908 ql_log(ql_log_fatal, vha, 0xd04a,
4909 "Alloc failed for scan database.\n");
4910 dma_free_coherent(&ha->pdev->dev, vha->gnl.size,
4911 vha->gnl.l, vha->gnl.ldma);
4912 scsi_remove_host(vha->host);
4913 return NULL;
4914 }
f352eeb7 4915 INIT_DELAYED_WORK(&vha->scan.scan_work, qla_scan_work_fn);
a4239945 4916
e315cd28 4917 sprintf(vha->host_str, "%s_%ld", QLA2XXX_DRIVER_NAME, vha->host_no);
7c3df132
SK		 4918 ql_dbg(ql_dbg_init, vha, 0x0041,
4919 "Allocated the host=%p hw=%p vha=%p dev_name=%s",
4920 vha->host, vha->hw, vha,
4921 dev_name(&(ha->pdev->dev)));
4922
e315cd28 4923 return vha;
1da177e4
LT		 4924}
4925
726b8548 4926struct qla_work_evt *
f999f4c1 4927qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type)
0971de7f
AV		 4928{
4929 struct qla_work_evt *e;
feafb7b1
AE		 4930 uint8_t bail;
4931
4932 QLA_VHA_MARK_BUSY(vha, bail);
4933 if (bail)
4934 return NULL;
0971de7f 4935
f999f4c1 4936 e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC);
feafb7b1
AE		 4937 if (!e) {
4938 QLA_VHA_MARK_NOT_BUSY(vha);
0971de7f 4939 return NULL;
feafb7b1 4940 }
0971de7f
AV		 4941
4942 INIT_LIST_HEAD(&e->list);
4943 e->type = type;
4944 e->flags = QLA_EVT_FLAG_FREE;
4945 return e;
4946}
4947
726b8548 4948int
f999f4c1 4949qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e)
0971de7f 4950{
f999f4c1 4951 unsigned long flags;
9b3e0f4d 4952 bool q = false;
0971de7f 4953
f999f4c1 4954 spin_lock_irqsave(&vha->work_lock, flags);
e315cd28 4955 list_add_tail(&e->list, &vha->work_list);
9b3e0f4d
QT		 4956
4957 if (!test_and_set_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags))
4958 q = true;
4959
f999f4c1 4960 spin_unlock_irqrestore(&vha->work_lock, flags);
ec7193e2 4961
9b3e0f4d
QT		 4962 if (q)
4963 queue_work(vha->hw->wq, &vha->iocb_work);
f999f4c1 4964
0971de7f
AV		 4965 return QLA_SUCCESS;
4966}
4967
4968int
e315cd28 4969qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code,
0971de7f
AV		 4970 u32 data)
4971{
4972 struct qla_work_evt *e;
4973
f999f4c1 4974 e = qla2x00_alloc_work(vha, QLA_EVT_AEN);
0971de7f
AV		 4975 if (!e)
4976 return QLA_FUNCTION_FAILED;
4977
4978 e->u.aen.code = code;
4979 e->u.aen.data = data;
f999f4c1 4980 return qla2x00_post_work(vha, e);
0971de7f
AV		 4981}
4982
8a659571
AV		 4983int
4984qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb)
4985{
4986 struct qla_work_evt *e;
4987
f999f4c1 4988 e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK);
8a659571
AV		 4989 if (!e)
4990 return QLA_FUNCTION_FAILED;
4991
4992 memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t));
f999f4c1 4993 return qla2x00_post_work(vha, e);
8a659571
AV		 4994}
4995
ac280b67
AV		 4996#define qla2x00_post_async_work(name, type) \
4997int qla2x00_post_async_##name##_work( \
4998 struct scsi_qla_host *vha, \
4999 fc_port_t *fcport, uint16_t *data) \
5000{ \
5001 struct qla_work_evt *e; \
5002 \
5003 e = qla2x00_alloc_work(vha, type); \
5004 if (!e) \
5005 return QLA_FUNCTION_FAILED; \
5006 \
5007 e->u.logio.fcport = fcport; \
5008 if (data) { \
5009 e->u.logio.data[0] = data[0]; \
5010 e->u.logio.data[1] = data[1]; \
5011 } \
6d674927 5012 fcport->flags |= FCF_ASYNC_ACTIVE; \
ac280b67
AV		 5013 return qla2x00_post_work(vha, e); \
5014}
5015
5016qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN);
ac280b67
AV		 5017qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT);
5018qla2x00_post_async_work(logout_done, QLA_EVT_ASYNC_LOGOUT_DONE);
5ff1d584 5019qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC);
11aea16a
QT		 5020qla2x00_post_async_work(prlo, QLA_EVT_ASYNC_PRLO);
5021qla2x00_post_async_work(prlo_done, QLA_EVT_ASYNC_PRLO_DONE);
ac280b67 5022
3420d36c
AV		 5023int
5024qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code)
5025{
5026 struct qla_work_evt *e;
5027
5028 e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT);
5029 if (!e)
5030 return QLA_FUNCTION_FAILED;
5031
5032 e->u.uevent.code = code;
5033 return qla2x00_post_work(vha, e);
5034}
5035
5036static void
5037qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code)
5038{
5039 char event_string[40];
5040 char *envp[] = { event_string, NULL };
5041
5042 switch (code) {
5043 case QLA_UEVENT_CODE_FW_DUMP:
5044 snprintf(event_string, sizeof(event_string), "FW_DUMP=%ld",
5045 vha->host_no);
5046 break;
5047 default:
5048 /* do nothing */
5049 break;
5050 }
5051 kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp);
5052}
5053
8ae6d9c7
GM		 5054int
5055qlafx00_post_aenfx_work(struct scsi_qla_host *vha, uint32_t evtcode,
5056 uint32_t *data, int cnt)
5057{
5058 struct qla_work_evt *e;
5059
5060 e = qla2x00_alloc_work(vha, QLA_EVT_AENFX);
5061 if (!e)
5062 return QLA_FUNCTION_FAILED;
5063
5064 e->u.aenfx.evtcode = evtcode;
5065 e->u.aenfx.count = cnt;
5066 memcpy(e->u.aenfx.mbx, data, sizeof(*data) * cnt);
5067 return qla2x00_post_work(vha, e);
5068}
5069
cd4ed6b4 5070void qla24xx_sched_upd_fcport(fc_port_t *fcport)
726b8548 5071{
cd4ed6b4 5072 unsigned long flags;
726b8548 5073
cd4ed6b4
QT		 5074 if (IS_SW_RESV_ADDR(fcport->d_id))
5075 return;
726b8548 5076
cd4ed6b4
QT		 5077 spin_lock_irqsave(&fcport->vha->work_lock, flags);
5078 if (fcport->disc_state == DSC_UPD_FCPORT) {
5079 spin_unlock_irqrestore(&fcport->vha->work_lock, flags);
5080 return;
5081 }
5082 fcport->jiffies_at_registration = jiffies;
5083 fcport->sec_since_registration = 0;
5084 fcport->next_disc_state = DSC_DELETED;
5085 fcport->disc_state = DSC_UPD_FCPORT;
5086 spin_unlock_irqrestore(&fcport->vha->work_lock, flags);
5087
5088 queue_work(system_unbound_wq, &fcport->reg_work);
726b8548
QT		 5089}
5090
5091static
5092void qla24xx_create_new_sess(struct scsi_qla_host *vha, struct qla_work_evt *e)
5093{
5094 unsigned long flags;
b5d15312 5095 fc_port_t *fcport = NULL, *tfcp;
726b8548
QT		 5096 struct qlt_plogi_ack_t *pla =
5097 (struct qlt_plogi_ack_t *)e->u.new_sess.pla;
b5d15312 5098 uint8_t free_fcport = 0;
726b8548 5099
9cd883f0
QT		 5100 ql_dbg(ql_dbg_disc, vha, 0xffff,
5101 "%s %d %8phC enter\n",
5102 __func__, __LINE__, e->u.new_sess.port_name);
5103
726b8548
QT		 5104 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
5105 fcport = qla2x00_find_fcport_by_wwpn(vha, e->u.new_sess.port_name, 1);
5106 if (fcport) {
5107 fcport->d_id = e->u.new_sess.id;
5108 if (pla) {
5109 fcport->fw_login_state = DSC_LS_PLOGI_PEND;
9b3e0f4d
QT		 5110 memcpy(fcport->node_name,
5111 pla->iocb.u.isp24.u.plogi.node_name,
5112 WWN_SIZE);
726b8548
QT		 5113 qlt_plogi_ack_link(vha, pla, fcport, QLT_PLOGI_LINK_SAME_WWN);
5114 /* we took an extra ref_count to prevent PLOGI ACK when
5115 * fcport/sess has not been created.
5116 */
5117 pla->ref_count--;
5118 }
5119 } else {
b5d15312 5120 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
726b8548
QT		 5121 fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
5122 if (fcport) {
5123 fcport->d_id = e->u.new_sess.id;
726b8548
QT		 5124 fcport->flags |= FCF_FABRIC_DEVICE;
5125 fcport->fw_login_state = DSC_LS_PLOGI_PEND;
c64a87f9 5126 if (e->u.new_sess.fc4_type == FS_FC4TYPE_FCP)
a4239945 5127 fcport->fc4_type = FC4_TYPE_FCP_SCSI;
726b8548 5128
c64a87f9 5129 if (e->u.new_sess.fc4_type == FS_FC4TYPE_NVME) {
2b5b9647
DT		 5130 fcport->fc4_type = FC4_TYPE_OTHER;
5131 fcport->fc4f_nvme = FC4_TYPE_NVME;
5132 }
33b28357 5133
726b8548
QT		 5134 memcpy(fcport->port_name, e->u.new_sess.port_name,
5135 WWN_SIZE);
b5d15312
QT		 5136 } else {
5137 ql_dbg(ql_dbg_disc, vha, 0xffff,
5138 "%s %8phC mem alloc fail.\n",
5139 __func__, e->u.new_sess.port_name);
5140
5141 if (pla)
5142 kmem_cache_free(qla_tgt_plogi_cachep, pla);
5143 return;
5144 }
5145
5146 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
a4239945 5147 /* search again to make sure no one else got ahead */
b5d15312
QT		 5148 tfcp = qla2x00_find_fcport_by_wwpn(vha,
5149 e->u.new_sess.port_name, 1);
5150 if (tfcp) {
5151 /* should rarily happen */
5152 ql_dbg(ql_dbg_disc, vha, 0xffff,
5153 "%s %8phC found existing fcport b4 add. DS %d LS %d\n",
5154 __func__, tfcp->port_name, tfcp->disc_state,
5155 tfcp->fw_login_state);
5156
5157 free_fcport = 1;
5158 } else {
726b8548
QT		 5159 list_add_tail(&fcport->list, &vha->vp_fcports);
5160
19759033
QT		 5161 }
5162 if (pla) {
5163 qlt_plogi_ack_link(vha, pla, fcport,
5164 QLT_PLOGI_LINK_SAME_WWN);
5165 pla->ref_count--;
726b8548
QT		 5166 }
5167 }
5168 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
5169
5170 if (fcport) {
a4239945
QT		 5171 fcport->id_changed = 1;
5172 fcport->scan_state = QLA_FCPORT_FOUND;
5173 memcpy(fcport->node_name, e->u.new_sess.node_name, WWN_SIZE);
5174
5ef696aa 5175 if (pla) {
9cd883f0
QT		 5176 if (pla->iocb.u.isp24.status_subcode == ELS_PRLI) {
5177 u16 wd3_lo;
5178
5179 fcport->fw_login_state = DSC_LS_PRLI_PEND;
5180 fcport->local = 0;
5181 fcport->loop_id =
5182 le16_to_cpu(
5183 pla->iocb.u.isp24.nport_handle);
5184 fcport->fw_login_state = DSC_LS_PRLI_PEND;
5185 wd3_lo =
5186 le16_to_cpu(
5187 pla->iocb.u.isp24.u.prli.wd3_lo);
5188
5189 if (wd3_lo & BIT_7)
5190 fcport->conf_compl_supported = 1;
5191
5192 if ((wd3_lo & BIT_4) == 0)
5193 fcport->port_type = FCT_INITIATOR;
5194 else
5195 fcport->port_type = FCT_TARGET;
5196 }
726b8548 5197 qlt_plogi_ack_unref(vha, pla);
5ef696aa 5198 } else {
1c6cacf4
HR		 5199 fc_port_t *dfcp = NULL;
5200
5ef696aa
QT		 5201 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
5202 tfcp = qla2x00_find_fcport_by_nportid(vha,
5203 &e->u.new_sess.id, 1);
5204 if (tfcp && (tfcp != fcport)) {
5205 /*
5206 * We have a conflict fcport with same NportID.
5207 */
5208 ql_dbg(ql_dbg_disc, vha, 0xffff,
5209 "%s %8phC found conflict b4 add. DS %d LS %d\n",
5210 __func__, tfcp->port_name, tfcp->disc_state,
5211 tfcp->fw_login_state);
5212
5213 switch (tfcp->disc_state) {
5214 case DSC_DELETED:
5215 break;
5216 case DSC_DELETE_PEND:
5217 fcport->login_pause = 1;
5218 tfcp->conflict = fcport;
5219 break;
5220 default:
5221 fcport->login_pause = 1;
5222 tfcp->conflict = fcport;
1c6cacf4 5223 dfcp = tfcp;
5ef696aa
QT		 5224 break;
5225 }
5226 }
5227 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
1c6cacf4
HR		 5228 if (dfcp)
5229 qlt_schedule_sess_for_deletion(tfcp);
a4239945 5230
a4239945 5231
8777e431
QT		 5232 if (N2N_TOPO(vha->hw))
5233 fcport->flags &= ~FCF_FABRIC_DEVICE;
5234
5235 if (N2N_TOPO(vha->hw)) {
5236 if (vha->flags.nvme_enabled) {
5237 fcport->fc4f_nvme = 1;
5238 fcport->n2n_flag = 1;
5239 }
5240 fcport->fw_login_state = 0;
5241 /*
5242 * wait link init done before sending login
5243 */
5244 } else {
5245 qla24xx_fcport_handle_login(vha, fcport);
5246 }
5ef696aa 5247 }
726b8548 5248 }
b5d15312
QT		 5249
5250 if (free_fcport) {
5251 qla2x00_free_fcport(fcport);
5252 if (pla)
5253 kmem_cache_free(qla_tgt_plogi_cachep, pla);
5254 }
726b8548
QT		 5255}
5256
e374f9f5
QT		 5257static void qla_sp_retry(struct scsi_qla_host *vha, struct qla_work_evt *e)
5258{
5259 struct srb *sp = e->u.iosb.sp;
5260 int rval;
5261
5262 rval = qla2x00_start_sp(sp);
5263 if (rval != QLA_SUCCESS) {
5264 ql_dbg(ql_dbg_disc, vha, 0x2043,
5265 "%s: %s: Re-issue IOCB failed (%d).\n",
5266 __func__, sp->name, rval);
5267 qla24xx_sp_unmap(vha, sp);
5268 }
5269}
5270
ac280b67 5271void
e315cd28 5272qla2x00_do_work(struct scsi_qla_host *vha)
0971de7f 5273{
f999f4c1
AV		 5274 struct qla_work_evt *e, *tmp;
5275 unsigned long flags;
5276 LIST_HEAD(work);
80676d05 5277 int rc;
0971de7f 5278
f999f4c1
AV		 5279 spin_lock_irqsave(&vha->work_lock, flags);
5280 list_splice_init(&vha->work_list, &work);
5281 spin_unlock_irqrestore(&vha->work_lock, flags);
5282
5283 list_for_each_entry_safe(e, tmp, &work, list) {
80676d05 5284 rc = QLA_SUCCESS;
0971de7f
AV		 5285 switch (e->type) {
5286 case QLA_EVT_AEN:
e315cd28 5287 fc_host_post_event(vha->host, fc_get_event_number(),
0971de7f
AV		 5288 e->u.aen.code, e->u.aen.data);
5289 break;
8a659571
AV		 5290 case QLA_EVT_IDC_ACK:
5291 qla81xx_idc_ack(vha, e->u.idc_ack.mb);
5292 break;
ac280b67
AV		 5293 case QLA_EVT_ASYNC_LOGIN:
5294 qla2x00_async_login(vha, e->u.logio.fcport,
5295 e->u.logio.data);
5296 break;
ac280b67 5297 case QLA_EVT_ASYNC_LOGOUT:
80676d05 5298 rc = qla2x00_async_logout(vha, e->u.logio.fcport);
ac280b67
AV		 5299 break;
5300 case QLA_EVT_ASYNC_LOGOUT_DONE:
5301 qla2x00_async_logout_done(vha, e->u.logio.fcport,
5302 e->u.logio.data);
5303 break;
5ff1d584
AV		 5304 case QLA_EVT_ASYNC_ADISC:
5305 qla2x00_async_adisc(vha, e->u.logio.fcport,
5306 e->u.logio.data);
5307 break;
3420d36c
AV		 5308 case QLA_EVT_UEVENT:
5309 qla2x00_uevent_emit(vha, e->u.uevent.code);
5310 break;
8ae6d9c7
GM		 5311 case QLA_EVT_AENFX:
5312 qlafx00_process_aen(vha, e);
5313 break;
726b8548
QT		 5314 case QLA_EVT_GPNID:
5315 qla24xx_async_gpnid(vha, &e->u.gpnid.id);
5316 break;
e374f9f5
QT		 5317 case QLA_EVT_UNMAP:
5318 qla24xx_sp_unmap(vha, e->u.iosb.sp);
726b8548 5319 break;
9b3e0f4d
QT		 5320 case QLA_EVT_RELOGIN:
5321 qla2x00_relogin(vha);
5322 break;
726b8548
QT		 5323 case QLA_EVT_NEW_SESS:
5324 qla24xx_create_new_sess(vha, e);
5325 break;
5326 case QLA_EVT_GPDB:
5327 qla24xx_async_gpdb(vha, e->u.fcport.fcport,
5328 e->u.fcport.opt);
5329 break;
a5d42f4c
DG		 5330 case QLA_EVT_PRLI:
5331 qla24xx_async_prli(vha, e->u.fcport.fcport);
5332 break;
726b8548
QT		 5333 case QLA_EVT_GPSC:
5334 qla24xx_async_gpsc(vha, e->u.fcport.fcport);
5335 break;
726b8548
QT		 5336 case QLA_EVT_GNL:
5337 qla24xx_async_gnl(vha, e->u.fcport.fcport);
5338 break;
5339 case QLA_EVT_NACK:
5340 qla24xx_do_nack_work(vha, e);
5341 break;
11aea16a 5342 case QLA_EVT_ASYNC_PRLO:
80676d05 5343 rc = qla2x00_async_prlo(vha, e->u.logio.fcport);
11aea16a
QT		 5344 break;
5345 case QLA_EVT_ASYNC_PRLO_DONE:
5346 qla2x00_async_prlo_done(vha, e->u.logio.fcport,
5347 e->u.logio.data);
5348 break;
a4239945 5349 case QLA_EVT_GPNFT:
33b28357
QT		 5350 qla24xx_async_gpnft(vha, e->u.gpnft.fc4_type,
5351 e->u.gpnft.sp);
a4239945
QT		 5352 break;
5353 case QLA_EVT_GPNFT_DONE:
5354 qla24xx_async_gpnft_done(vha, e->u.iosb.sp);
5355 break;
5356 case QLA_EVT_GNNFT_DONE:
5357 qla24xx_async_gnnft_done(vha, e->u.iosb.sp);
5358 break;
5359 case QLA_EVT_GNNID:
5360 qla24xx_async_gnnid(vha, e->u.fcport.fcport);
5361 break;
5362 case QLA_EVT_GFPNID:
5363 qla24xx_async_gfpnid(vha, e->u.fcport.fcport);
5364 break;
e374f9f5
QT		 5365 case QLA_EVT_SP_RETRY:
5366 qla_sp_retry(vha, e);
cc28e0ac
QT		 5367 break;
5368 case QLA_EVT_IIDMA:
5369 qla_do_iidma_work(vha, e->u.fcport.fcport);
5370 break;
8777e431
QT		 5371 case QLA_EVT_ELS_PLOGI:
5372 qla24xx_els_dcmd2_iocb(vha, ELS_DCMD_PLOGI,
5373 e->u.fcport.fcport, false);
5374 break;
0971de7f 5375 }
80676d05
QT		 5376
5377 if (rc == EAGAIN) {
5378 /* put 'work' at head of 'vha->work_list' */
5379 spin_lock_irqsave(&vha->work_lock, flags);
5380 list_splice(&work, &vha->work_list);
5381 spin_unlock_irqrestore(&vha->work_lock, flags);
5382 break;
5383 }
5384 list_del_init(&e->list);
0971de7f
AV		 5385 if (e->flags & QLA_EVT_FLAG_FREE)
5386 kfree(e);
feafb7b1
AE		 5387
5388 /* For each work completed decrement vha ref count */
5389 QLA_VHA_MARK_NOT_BUSY(vha);
e315cd28 5390 }
e315cd28 5391}
f999f4c1 5392
9b3e0f4d
QT		 5393int qla24xx_post_relogin_work(struct scsi_qla_host *vha)
5394{
5395 struct qla_work_evt *e;
5396
5397 e = qla2x00_alloc_work(vha, QLA_EVT_RELOGIN);
5398
5399 if (!e) {
5400 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
5401 return QLA_FUNCTION_FAILED;
5402 }
5403
5404 return qla2x00_post_work(vha, e);
5405}
5406
e315cd28
AC		 5407/* Relogins all the fcports of a vport
5408 * Context: dpc thread
5409 */
5410void qla2x00_relogin(struct scsi_qla_host *vha)
5411{
5412 fc_port_t *fcport;
23dd98a6 5413 int status, relogin_needed = 0;
726b8548 5414 struct event_arg ea;
e315cd28
AC		 5415
5416 list_for_each_entry(fcport, &vha->vp_fcports, list) {
9cd883f0
QT		 5417 /*
5418 * If the port is not ONLINE then try to login
5419 * to it if we haven't run out of retries.
5420 */
5ff1d584 5421 if (atomic_read(&fcport->state) != FCS_ONLINE &&
23dd98a6
QT		 5422 fcport->login_retry) {
5423 if (fcport->scan_state != QLA_FCPORT_FOUND ||
5424 fcport->disc_state == DSC_LOGIN_COMPLETE)
5425 continue;
e315cd28 5426
23dd98a6
QT		 5427 if (fcport->flags & (FCF_ASYNC_SENT|FCF_ASYNC_ACTIVE) ||
5428 fcport->disc_state == DSC_DELETE_PEND) {
5429 relogin_needed = 1;
5430 } else {
5431 if (vha->hw->current_topology != ISP_CFG_NL) {
5432 memset(&ea, 0, sizeof(ea));
5433 ea.event = FCME_RELOGIN;
5434 ea.fcport = fcport;
5435 qla2x00_fcport_event_handler(vha, &ea);
5436 } else if (vha->hw->current_topology ==
5437 ISP_CFG_NL) {
5438 fcport->login_retry--;
5439 status =
5440 qla2x00_local_device_login(vha,
5441 fcport);
5442 if (status == QLA_SUCCESS) {
5443 fcport->old_loop_id =
5444 fcport->loop_id;
5445 ql_dbg(ql_dbg_disc, vha, 0x2003,
5446 "Port login OK: logged in ID 0x%x.\n",
5447 fcport->loop_id);
5448 qla2x00_update_fcport
5449 (vha, fcport);
5450 } else if (status == 1) {
5451 set_bit(RELOGIN_NEEDED,
5452 &vha->dpc_flags);
5453 /* retry the login again */
5454 ql_dbg(ql_dbg_disc, vha, 0x2007,
5455 "Retrying %d login again loop_id 0x%x.\n",
5456 fcport->login_retry,
5457 fcport->loop_id);
5458 } else {
5459 fcport->login_retry = 0;
5460 }
e315cd28 5461
23dd98a6
QT		 5462 if (fcport->login_retry == 0 &&
5463 status != QLA_SUCCESS)
5464 qla2x00_clear_loop_id(fcport);
5465 }
e315cd28 5466 }
e315cd28
AC		 5467 }
5468 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
5469 break;
0971de7f 5470 }
9b3e0f4d 5471
23dd98a6
QT		 5472 if (relogin_needed)
5473 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
5474
9b3e0f4d
QT		 5475 ql_dbg(ql_dbg_disc, vha, 0x400e,
5476 "Relogin end.\n");
0971de7f
AV		 5477}
5478
7d613ac6
SV		 5479/* Schedule work on any of the dpc-workqueues */
5480void
5481qla83xx_schedule_work(scsi_qla_host_t *base_vha, int work_code)
5482{
5483 struct qla_hw_data *ha = base_vha->hw;
5484
5485 switch (work_code) {
5486 case MBA_IDC_AEN: /* 0x8200 */
5487 if (ha->dpc_lp_wq)
5488 queue_work(ha->dpc_lp_wq, &ha->idc_aen);
5489 break;
5490
5491 case QLA83XX_NIC_CORE_RESET: /* 0x1 */
5492 if (!ha->flags.nic_core_reset_hdlr_active) {
5493 if (ha->dpc_hp_wq)
5494 queue_work(ha->dpc_hp_wq, &ha->nic_core_reset);
5495 } else
5496 ql_dbg(ql_dbg_p3p, base_vha, 0xb05e,
5497 "NIC Core reset is already active. Skip "
5498 "scheduling it again.\n");
5499 break;
5500 case QLA83XX_IDC_STATE_HANDLER: /* 0x2 */
5501 if (ha->dpc_hp_wq)
5502 queue_work(ha->dpc_hp_wq, &ha->idc_state_handler);
5503 break;
5504 case QLA83XX_NIC_CORE_UNRECOVERABLE: /* 0x3 */
5505 if (ha->dpc_hp_wq)
5506 queue_work(ha->dpc_hp_wq, &ha->nic_core_unrecoverable);
5507 break;
5508 default:
5509 ql_log(ql_log_warn, base_vha, 0xb05f,
d939be3a 5510 "Unknown work-code=0x%x.\n", work_code);
7d613ac6
SV		 5511 }
5512
5513 return;
5514}
5515
5516/* Work: Perform NIC Core Unrecoverable state handling */
5517void
5518qla83xx_nic_core_unrecoverable_work(struct work_struct *work)
5519{
5520 struct qla_hw_data *ha =
2ad1b67c 5521 container_of(work, struct qla_hw_data, nic_core_unrecoverable);
7d613ac6
SV		 5522 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5523 uint32_t dev_state = 0;
5524
5525 qla83xx_idc_lock(base_vha, 0);
5526 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
5527 qla83xx_reset_ownership(base_vha);
5528 if (ha->flags.nic_core_reset_owner) {
5529 ha->flags.nic_core_reset_owner = 0;
5530 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
5531 QLA8XXX_DEV_FAILED);
5532 ql_log(ql_log_info, base_vha, 0xb060, "HW State: FAILED.\n");
5533 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
5534 }
5535 qla83xx_idc_unlock(base_vha, 0);
5536}
5537
5538/* Work: Execute IDC state handler */
5539void
5540qla83xx_idc_state_handler_work(struct work_struct *work)
5541{
5542 struct qla_hw_data *ha =
2ad1b67c 5543 container_of(work, struct qla_hw_data, idc_state_handler);
7d613ac6
SV		 5544 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5545 uint32_t dev_state = 0;
5546
5547 qla83xx_idc_lock(base_vha, 0);
5548 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
5549 if (dev_state == QLA8XXX_DEV_FAILED ||
5550 dev_state == QLA8XXX_DEV_NEED_QUIESCENT)
5551 qla83xx_idc_state_handler(base_vha);
5552 qla83xx_idc_unlock(base_vha, 0);
5553}
5554
fa492630 5555static int
7d613ac6
SV		 5556qla83xx_check_nic_core_fw_alive(scsi_qla_host_t *base_vha)
5557{
5558 int rval = QLA_SUCCESS;
5559 unsigned long heart_beat_wait = jiffies + (1 * HZ);
5560 uint32_t heart_beat_counter1, heart_beat_counter2;
5561
5562 do {
5563 if (time_after(jiffies, heart_beat_wait)) {
5564 ql_dbg(ql_dbg_p3p, base_vha, 0xb07c,
5565 "Nic Core f/w is not alive.\n");
5566 rval = QLA_FUNCTION_FAILED;
5567 break;
5568 }
5569
5570 qla83xx_idc_lock(base_vha, 0);
5571 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
5572 &heart_beat_counter1);
5573 qla83xx_idc_unlock(base_vha, 0);
5574 msleep(100);
5575 qla83xx_idc_lock(base_vha, 0);
5576 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
5577 &heart_beat_counter2);
5578 qla83xx_idc_unlock(base_vha, 0);
5579 } while (heart_beat_counter1 == heart_beat_counter2);
5580
5581 return rval;
5582}
5583
5584/* Work: Perform NIC Core Reset handling */
5585void
5586qla83xx_nic_core_reset_work(struct work_struct *work)
5587{
5588 struct qla_hw_data *ha =
5589 container_of(work, struct qla_hw_data, nic_core_reset);
5590 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5591 uint32_t dev_state = 0;
5592
81178772
SK		 5593 if (IS_QLA2031(ha)) {
5594 if (qla2xxx_mctp_dump(base_vha) != QLA_SUCCESS)
5595 ql_log(ql_log_warn, base_vha, 0xb081,
5596 "Failed to dump mctp\n");
5597 return;
5598 }
5599
7d613ac6
SV		 5600 if (!ha->flags.nic_core_reset_hdlr_active) {
5601 if (qla83xx_check_nic_core_fw_alive(base_vha) == QLA_SUCCESS) {
5602 qla83xx_idc_lock(base_vha, 0);
5603 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE,
5604 &dev_state);
5605 qla83xx_idc_unlock(base_vha, 0);
5606 if (dev_state != QLA8XXX_DEV_NEED_RESET) {
5607 ql_dbg(ql_dbg_p3p, base_vha, 0xb07a,
5608 "Nic Core f/w is alive.\n");
5609 return;
5610 }
5611 }
5612
5613 ha->flags.nic_core_reset_hdlr_active = 1;
5614 if (qla83xx_nic_core_reset(base_vha)) {
5615 /* NIC Core reset failed. */
5616 ql_dbg(ql_dbg_p3p, base_vha, 0xb061,
5617 "NIC Core reset failed.\n");
5618 }
5619 ha->flags.nic_core_reset_hdlr_active = 0;
5620 }
5621}
5622
5623/* Work: Handle 8200 IDC aens */
5624void
5625qla83xx_service_idc_aen(struct work_struct *work)
5626{
5627 struct qla_hw_data *ha =
5628 container_of(work, struct qla_hw_data, idc_aen);
5629 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5630 uint32_t dev_state, idc_control;
5631
5632 qla83xx_idc_lock(base_vha, 0);
5633 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
5634 qla83xx_rd_reg(base_vha, QLA83XX_IDC_CONTROL, &idc_control);
5635 qla83xx_idc_unlock(base_vha, 0);
5636 if (dev_state == QLA8XXX_DEV_NEED_RESET) {
5637 if (idc_control & QLA83XX_IDC_GRACEFUL_RESET) {
5638 ql_dbg(ql_dbg_p3p, base_vha, 0xb062,
5639 "Application requested NIC Core Reset.\n");
5640 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
5641 } else if (qla83xx_check_nic_core_fw_alive(base_vha) ==
5642 QLA_SUCCESS) {
5643 ql_dbg(ql_dbg_p3p, base_vha, 0xb07b,
5644 "Other protocol driver requested NIC Core Reset.\n");
5645 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
5646 }
5647 } else if (dev_state == QLA8XXX_DEV_FAILED ||
5648 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) {
5649 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
5650 }
5651}
5652
5653static void
5654qla83xx_wait_logic(void)
5655{
5656 int i;
5657
5658 /* Yield CPU */
5659 if (!in_interrupt()) {
5660 /*
5661 * Wait about 200ms before retrying again.
5662 * This controls the number of retries for single
5663 * lock operation.
5664 */
5665 msleep(100);
5666 schedule();
5667 } else {
5668 for (i = 0; i < 20; i++)
5669 cpu_relax(); /* This a nop instr on i386 */
5670 }
5671}
5672
fa492630 5673static int
7d613ac6
SV		 5674qla83xx_force_lock_recovery(scsi_qla_host_t *base_vha)
5675{
5676 int rval;
5677 uint32_t data;
5678 uint32_t idc_lck_rcvry_stage_mask = 0x3;
5679 uint32_t idc_lck_rcvry_owner_mask = 0x3c;
5680 struct qla_hw_data *ha = base_vha->hw;
6c315553
SK		 5681 ql_dbg(ql_dbg_p3p, base_vha, 0xb086,
5682 "Trying force recovery of the IDC lock.\n");
7d613ac6
SV		 5683
5684 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, &data);
5685 if (rval)
5686 return rval;
5687
5688 if ((data & idc_lck_rcvry_stage_mask) > 0) {
5689 return QLA_SUCCESS;
5690 } else {
5691 data = (IDC_LOCK_RECOVERY_STAGE1) | (ha->portnum << 2);
5692 rval = qla83xx_wr_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
5693 data);
5694 if (rval)
5695 return rval;
5696
5697 msleep(200);
5698
5699 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
5700 &data);
5701 if (rval)
5702 return rval;
5703
5704 if (((data & idc_lck_rcvry_owner_mask) >> 2) == ha->portnum) {
5705 data &= (IDC_LOCK_RECOVERY_STAGE2 |
5706 ~(idc_lck_rcvry_stage_mask));
5707 rval = qla83xx_wr_reg(base_vha,
5708 QLA83XX_IDC_LOCK_RECOVERY, data);
5709 if (rval)
5710 return rval;
5711
5712 /* Forcefully perform IDC UnLock */
5713 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK,
5714 &data);
5715 if (rval)
5716 return rval;
5717 /* Clear lock-id by setting 0xff */
5718 rval = qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
5719 0xff);
5720 if (rval)
5721 return rval;
5722 /* Clear lock-recovery by setting 0x0 */
5723 rval = qla83xx_wr_reg(base_vha,
5724 QLA83XX_IDC_LOCK_RECOVERY, 0x0);
5725 if (rval)
5726 return rval;
5727 } else
5728 return QLA_SUCCESS;
5729 }
5730
5731 return rval;
5732}
5733
fa492630 5734static int
7d613ac6
SV		 5735qla83xx_idc_lock_recovery(scsi_qla_host_t *base_vha)
5736{
5737 int rval = QLA_SUCCESS;
5738 uint32_t o_drv_lockid, n_drv_lockid;
5739 unsigned long lock_recovery_timeout;
5740
5741 lock_recovery_timeout = jiffies + QLA83XX_MAX_LOCK_RECOVERY_WAIT;
5742retry_lockid:
5743 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &o_drv_lockid);
5744 if (rval)
5745 goto exit;
5746
5747 /* MAX wait time before forcing IDC Lock recovery = 2 secs */
5748 if (time_after_eq(jiffies, lock_recovery_timeout)) {
5749 if (qla83xx_force_lock_recovery(base_vha) == QLA_SUCCESS)
5750 return QLA_SUCCESS;
5751 else
5752 return QLA_FUNCTION_FAILED;
5753 }
5754
5755 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &n_drv_lockid);
5756 if (rval)
5757 goto exit;
5758
5759 if (o_drv_lockid == n_drv_lockid) {
5760 qla83xx_wait_logic();
5761 goto retry_lockid;
5762 } else
5763 return QLA_SUCCESS;
5764
5765exit:
5766 return rval;
5767}
5768
5769void
5770qla83xx_idc_lock(scsi_qla_host_t *base_vha, uint16_t requester_id)
5771{
5772 uint16_t options = (requester_id << 15) | BIT_6;
5773 uint32_t data;
6c315553 5774 uint32_t lock_owner;
7d613ac6
SV		 5775 struct qla_hw_data *ha = base_vha->hw;
5776
5777 /* IDC-lock implementation using driver-lock/lock-id remote registers */
5778retry_lock:
5779 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCK, &data)
5780 == QLA_SUCCESS) {
5781 if (data) {
5782 /* Setting lock-id to our function-number */
5783 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
5784 ha->portnum);
5785 } else {
6c315553
SK		 5786 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID,
5787 &lock_owner);
7d613ac6 5788 ql_dbg(ql_dbg_p3p, base_vha, 0xb063,
6c315553
SK		 5789 "Failed to acquire IDC lock, acquired by %d, "
5790 "retrying...\n", lock_owner);
7d613ac6
SV		 5791
5792 /* Retry/Perform IDC-Lock recovery */
5793 if (qla83xx_idc_lock_recovery(base_vha)
5794 == QLA_SUCCESS) {
5795 qla83xx_wait_logic();
5796 goto retry_lock;
5797 } else
5798 ql_log(ql_log_warn, base_vha, 0xb075,
5799 "IDC Lock recovery FAILED.\n");
5800 }
5801
5802 }
5803
5804 return;
5805
5806 /* XXX: IDC-lock implementation using access-control mbx */
5807retry_lock2:
5808 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
5809 ql_dbg(ql_dbg_p3p, base_vha, 0xb072,
5810 "Failed to acquire IDC lock. retrying...\n");
5811 /* Retry/Perform IDC-Lock recovery */
5812 if (qla83xx_idc_lock_recovery(base_vha) == QLA_SUCCESS) {
5813 qla83xx_wait_logic();
5814 goto retry_lock2;
5815 } else
5816 ql_log(ql_log_warn, base_vha, 0xb076,
5817 "IDC Lock recovery FAILED.\n");
5818 }
5819
5820 return;
5821}
5822
5823void
5824qla83xx_idc_unlock(scsi_qla_host_t *base_vha, uint16_t requester_id)
5825{
5897cb2f
BVA		 5826#if 0
5827 uint16_t options = (requester_id << 15) | BIT_7;
5828#endif
5829 uint16_t retry;
7d613ac6
SV		 5830 uint32_t data;
5831 struct qla_hw_data *ha = base_vha->hw;
5832
5833 /* IDC-unlock implementation using driver-unlock/lock-id
5834 * remote registers
5835 */
5836 retry = 0;
5837retry_unlock:
5838 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &data)
5839 == QLA_SUCCESS) {
5840 if (data == ha->portnum) {
5841 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, &data);
5842 /* Clearing lock-id by setting 0xff */
5843 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 0xff);
5844 } else if (retry < 10) {
5845 /* SV: XXX: IDC unlock retrying needed here? */
5846
5847 /* Retry for IDC-unlock */
5848 qla83xx_wait_logic();
5849 retry++;
5850 ql_dbg(ql_dbg_p3p, base_vha, 0xb064,
ee6a8773 5851 "Failed to release IDC lock, retrying=%d\n", retry);
7d613ac6
SV		 5852 goto retry_unlock;
5853 }
5854 } else if (retry < 10) {
5855 /* Retry for IDC-unlock */
5856 qla83xx_wait_logic();
5857 retry++;
5858 ql_dbg(ql_dbg_p3p, base_vha, 0xb065,
ee6a8773 5859 "Failed to read drv-lockid, retrying=%d\n", retry);
7d613ac6
SV		 5860 goto retry_unlock;
5861 }
5862
5863 return;
5864
5897cb2f 5865#if 0
7d613ac6
SV		 5866 /* XXX: IDC-unlock implementation using access-control mbx */
5867 retry = 0;
5868retry_unlock2:
5869 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
5870 if (retry < 10) {
5871 /* Retry for IDC-unlock */
5872 qla83xx_wait_logic();
5873 retry++;
5874 ql_dbg(ql_dbg_p3p, base_vha, 0xb066,
ee6a8773 5875 "Failed to release IDC lock, retrying=%d\n", retry);
7d613ac6
SV		 5876 goto retry_unlock2;
5877 }
5878 }
5879
5880 return;
5897cb2f 5881#endif
7d613ac6
SV		 5882}
5883
5884int
5885__qla83xx_set_drv_presence(scsi_qla_host_t *vha)
5886{
5887 int rval = QLA_SUCCESS;
5888 struct qla_hw_data *ha = vha->hw;
5889 uint32_t drv_presence;
5890
5891 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
5892 if (rval == QLA_SUCCESS) {
5893 drv_presence |= (1 << ha->portnum);
5894 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
5895 drv_presence);
5896 }
5897
5898 return rval;
5899}
5900
5901int
5902qla83xx_set_drv_presence(scsi_qla_host_t *vha)
5903{
5904 int rval = QLA_SUCCESS;
5905
5906 qla83xx_idc_lock(vha, 0);
5907 rval = __qla83xx_set_drv_presence(vha);
5908 qla83xx_idc_unlock(vha, 0);
5909
5910 return rval;
5911}
5912
5913int
5914__qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
5915{
5916 int rval = QLA_SUCCESS;
5917 struct qla_hw_data *ha = vha->hw;
5918 uint32_t drv_presence;
5919
5920 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
5921 if (rval == QLA_SUCCESS) {
5922 drv_presence &= ~(1 << ha->portnum);
5923 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
5924 drv_presence);
5925 }
5926
5927 return rval;
5928}
5929
5930int
5931qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
5932{
5933 int rval = QLA_SUCCESS;
5934
5935 qla83xx_idc_lock(vha, 0);
5936 rval = __qla83xx_clear_drv_presence(vha);
5937 qla83xx_idc_unlock(vha, 0);
5938
5939 return rval;
5940}
5941
fa492630 5942static void
7d613ac6
SV		 5943qla83xx_need_reset_handler(scsi_qla_host_t *vha)
5944{
5945 struct qla_hw_data *ha = vha->hw;
5946 uint32_t drv_ack, drv_presence;
5947 unsigned long ack_timeout;
5948
5949 /* Wait for IDC ACK from all functions (DRV-ACK == DRV-PRESENCE) */
5950 ack_timeout = jiffies + (ha->fcoe_reset_timeout * HZ);
5951 while (1) {
5952 qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
5953 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
807fb6d8 5954 if ((drv_ack & drv_presence) == drv_presence)
7d613ac6
SV		 5955 break;
5956
5957 if (time_after_eq(jiffies, ack_timeout)) {
5958 ql_log(ql_log_warn, vha, 0xb067,
5959 "RESET ACK TIMEOUT! drv_presence=0x%x "
5960 "drv_ack=0x%x\n", drv_presence, drv_ack);
5961 /*
5962 * The function(s) which did not ack in time are forced
5963 * to withdraw any further participation in the IDC
5964 * reset.
5965 */
5966 if (drv_ack != drv_presence)
5967 qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
5968 drv_ack);
5969 break;
5970 }
5971
5972 qla83xx_idc_unlock(vha, 0);
5973 msleep(1000);
5974 qla83xx_idc_lock(vha, 0);
5975 }
5976
5977 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_COLD);
5978 ql_log(ql_log_info, vha, 0xb068, "HW State: COLD/RE-INIT.\n");
5979}
5980
fa492630 5981static int
7d613ac6
SV		 5982qla83xx_device_bootstrap(scsi_qla_host_t *vha)
5983{
5984 int rval = QLA_SUCCESS;
5985 uint32_t idc_control;
5986
5987 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_INITIALIZING);
5988 ql_log(ql_log_info, vha, 0xb069, "HW State: INITIALIZING.\n");
5989
5990 /* Clearing IDC-Control Graceful-Reset Bit before resetting f/w */
5991 __qla83xx_get_idc_control(vha, &idc_control);
5992 idc_control &= ~QLA83XX_IDC_GRACEFUL_RESET;
5993 __qla83xx_set_idc_control(vha, 0);
5994
5995 qla83xx_idc_unlock(vha, 0);
5996 rval = qla83xx_restart_nic_firmware(vha);
5997 qla83xx_idc_lock(vha, 0);
5998
5999 if (rval != QLA_SUCCESS) {
6000 ql_log(ql_log_fatal, vha, 0xb06a,
6001 "Failed to restart NIC f/w.\n");
6002 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_FAILED);
6003 ql_log(ql_log_info, vha, 0xb06b, "HW State: FAILED.\n");
6004 } else {
6005 ql_dbg(ql_dbg_p3p, vha, 0xb06c,
6006 "Success in restarting nic f/w.\n");
6007 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_READY);
6008 ql_log(ql_log_info, vha, 0xb06d, "HW State: READY.\n");
6009 }
6010
6011 return rval;
6012}
6013
6014/* Assumes idc_lock always held on entry */
6015int
6016qla83xx_idc_state_handler(scsi_qla_host_t *base_vha)
6017{
6018 struct qla_hw_data *ha = base_vha->hw;
6019 int rval = QLA_SUCCESS;
6020 unsigned long dev_init_timeout;
6021 uint32_t dev_state;
6022
6023 /* Wait for MAX-INIT-TIMEOUT for the device to go ready */
6024 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ);
6025
6026 while (1) {
6027
6028 if (time_after_eq(jiffies, dev_init_timeout)) {
6029 ql_log(ql_log_warn, base_vha, 0xb06e,
6030 "Initialization TIMEOUT!\n");
6031 /* Init timeout. Disable further NIC Core
6032 * communication.
6033 */
6034 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
6035 QLA8XXX_DEV_FAILED);
6036 ql_log(ql_log_info, base_vha, 0xb06f,
6037 "HW State: FAILED.\n");
6038 }
6039
6040 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
6041 switch (dev_state) {
6042 case QLA8XXX_DEV_READY:
6043 if (ha->flags.nic_core_reset_owner)
6044 qla83xx_idc_audit(base_vha,
6045 IDC_AUDIT_COMPLETION);
6046 ha->flags.nic_core_reset_owner = 0;
6047 ql_dbg(ql_dbg_p3p, base_vha, 0xb070,
6048 "Reset_owner reset by 0x%x.\n",
6049 ha->portnum);
6050 goto exit;
6051 case QLA8XXX_DEV_COLD:
6052 if (ha->flags.nic_core_reset_owner)
6053 rval = qla83xx_device_bootstrap(base_vha);
6054 else {
6055 /* Wait for AEN to change device-state */
6056 qla83xx_idc_unlock(base_vha, 0);
6057 msleep(1000);
6058 qla83xx_idc_lock(base_vha, 0);
6059 }
6060 break;
6061 case QLA8XXX_DEV_INITIALIZING:
6062 /* Wait for AEN to change device-state */
6063 qla83xx_idc_unlock(base_vha, 0);
6064 msleep(1000);
6065 qla83xx_idc_lock(base_vha, 0);
6066 break;
6067 case QLA8XXX_DEV_NEED_RESET:
6068 if (!ql2xdontresethba && ha->flags.nic_core_reset_owner)
6069 qla83xx_need_reset_handler(base_vha);
6070 else {
6071 /* Wait for AEN to change device-state */
6072 qla83xx_idc_unlock(base_vha, 0);
6073 msleep(1000);
6074 qla83xx_idc_lock(base_vha, 0);
6075 }
6076 /* reset timeout value after need reset handler */
6077 dev_init_timeout = jiffies +
6078 (ha->fcoe_dev_init_timeout * HZ);
6079 break;
6080 case QLA8XXX_DEV_NEED_QUIESCENT:
6081 /* XXX: DEBUG for now */
6082 qla83xx_idc_unlock(base_vha, 0);
6083 msleep(1000);
6084 qla83xx_idc_lock(base_vha, 0);
6085 break;
6086 case QLA8XXX_DEV_QUIESCENT:
6087 /* XXX: DEBUG for now */
6088 if (ha->flags.quiesce_owner)
6089 goto exit;
6090
6091 qla83xx_idc_unlock(base_vha, 0);
6092 msleep(1000);
6093 qla83xx_idc_lock(base_vha, 0);
6094 dev_init_timeout = jiffies +
6095 (ha->fcoe_dev_init_timeout * HZ);
6096 break;
6097 case QLA8XXX_DEV_FAILED:
6098 if (ha->flags.nic_core_reset_owner)
6099 qla83xx_idc_audit(base_vha,
6100 IDC_AUDIT_COMPLETION);
6101 ha->flags.nic_core_reset_owner = 0;
6102 __qla83xx_clear_drv_presence(base_vha);
6103 qla83xx_idc_unlock(base_vha, 0);
6104 qla8xxx_dev_failed_handler(base_vha);
6105 rval = QLA_FUNCTION_FAILED;
6106 qla83xx_idc_lock(base_vha, 0);
6107 goto exit;
6108 case QLA8XXX_BAD_VALUE:
6109 qla83xx_idc_unlock(base_vha, 0);
6110 msleep(1000);
6111 qla83xx_idc_lock(base_vha, 0);
6112 break;
6113 default:
6114 ql_log(ql_log_warn, base_vha, 0xb071,
d939be3a 6115 "Unknown Device State: %x.\n", dev_state);
7d613ac6
SV		 6116 qla83xx_idc_unlock(base_vha, 0);
6117 qla8xxx_dev_failed_handler(base_vha);
6118 rval = QLA_FUNCTION_FAILED;
6119 qla83xx_idc_lock(base_vha, 0);
6120 goto exit;
6121 }
6122 }
6123
6124exit:
6125 return rval;
6126}
6127
f3ddac19
CD		 6128void
6129qla2x00_disable_board_on_pci_error(struct work_struct *work)
6130{
6131 struct qla_hw_data *ha = container_of(work, struct qla_hw_data,
6132 board_disable);
6133 struct pci_dev *pdev = ha->pdev;
6134 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
6135
726b8548
QT		 6136 /*
6137 * if UNLOAD flag is already set, then continue unload,
783e0dc4
SC		 6138 * where it was set first.
6139 */
6140 if (test_bit(UNLOADING, &base_vha->dpc_flags))
6141 return;
6142
f3ddac19
CD		 6143 ql_log(ql_log_warn, base_vha, 0x015b,
6144 "Disabling adapter.\n");
6145
efdb5760
SC		 6146 if (!atomic_read(&pdev->enable_cnt)) {
6147 ql_log(ql_log_info, base_vha, 0xfffc,
6148 "PCI device disabled, no action req for PCI error=%lx\n",
6149 base_vha->pci_flags);
6150 return;
6151 }
6152
726b8548
QT		 6153 qla2x00_wait_for_sess_deletion(base_vha);
6154
f3ddac19
CD		 6155 set_bit(UNLOADING, &base_vha->dpc_flags);
6156
6157 qla2x00_delete_all_vps(ha, base_vha);
6158
6159 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
6160
6161 qla2x00_dfs_remove(base_vha);
6162
6163 qla84xx_put_chip(base_vha);
6164
6165 if (base_vha->timer_active)
6166 qla2x00_stop_timer(base_vha);
6167
6168 base_vha->flags.online = 0;
6169
6170 qla2x00_destroy_deferred_work(ha);
6171
6172 /*
6173 * Do not try to stop beacon blink as it will issue a mailbox
6174 * command.
6175 */
6176 qla2x00_free_sysfs_attr(base_vha, false);
6177
6178 fc_remove_host(base_vha->host);
6179
6180 scsi_remove_host(base_vha->host);
6181
6182 base_vha->flags.init_done = 0;
6183 qla25xx_delete_queues(base_vha);
f3ddac19 6184 qla2x00_free_fcports(base_vha);
093df737 6185 qla2x00_free_irqs(base_vha);
f3ddac19
CD		 6186 qla2x00_mem_free(ha);
6187 qla82xx_md_free(base_vha);
6188 qla2x00_free_queues(ha);
6189
f3ddac19
CD		 6190 qla2x00_unmap_iobases(ha);
6191
6192 pci_release_selected_regions(ha->pdev, ha->bars);
f3ddac19
CD		 6193 pci_disable_pcie_error_reporting(pdev);
6194 pci_disable_device(pdev);
f3ddac19 6195
beb9e315
JL		 6196 /*
6197 * Let qla2x00_remove_one cleanup qla_hw_data on device removal.
6198 */
f3ddac19
CD		 6199}
6200
1da177e4
LT		 6201/**************************************************************************
6202* qla2x00_do_dpc
6203* This kernel thread is a task that is schedule by the interrupt handler
6204* to perform the background processing for interrupts.
6205*
6206* Notes:
6207* This task always run in the context of a kernel thread. It
6208* is kick-off by the driver's detect code and starts up
6209* up one per adapter. It immediately goes to sleep and waits for
6210* some fibre event. When either the interrupt handler or
6211* the timer routine detects a event it will one of the task
6212* bits then wake us up.
6213**************************************************************************/
6214static int
6215qla2x00_do_dpc(void *data)
6216{
e315cd28
AC		 6217 scsi_qla_host_t *base_vha;
6218 struct qla_hw_data *ha;
d7459527
MH		 6219 uint32_t online;
6220 struct qla_qpair *qpair;
1da177e4 6221
e315cd28
AC		 6222 ha = (struct qla_hw_data *)data;
6223 base_vha = pci_get_drvdata(ha->pdev);
1da177e4 6224
8698a745 6225 set_user_nice(current, MIN_NICE);
1da177e4 6226
563585ec 6227 set_current_state(TASK_INTERRUPTIBLE);
39a11240 6228 while (!kthread_should_stop()) {
7c3df132
SK		 6229 ql_dbg(ql_dbg_dpc, base_vha, 0x4000,
6230 "DPC handler sleeping.\n");
1da177e4 6231
39a11240 6232 schedule();
1da177e4 6233
c142caf0
AV		 6234 if (!base_vha->flags.init_done || ha->flags.mbox_busy)
6235 goto end_loop;
1da177e4 6236
85880801 6237 if (ha->flags.eeh_busy) {
7c3df132
SK		 6238 ql_dbg(ql_dbg_dpc, base_vha, 0x4003,
6239 "eeh_busy=%d.\n", ha->flags.eeh_busy);
c142caf0 6240 goto end_loop;
85880801
AV		 6241 }
6242
1da177e4
LT		 6243 ha->dpc_active = 1;
6244
5f28d2d7
SK		 6245 ql_dbg(ql_dbg_dpc + ql_dbg_verbose, base_vha, 0x4001,
6246 "DPC handler waking up, dpc_flags=0x%lx.\n",
6247 base_vha->dpc_flags);
1da177e4 6248
a29b3dd7
JC		 6249 if (test_bit(UNLOADING, &base_vha->dpc_flags))
6250 break;
6251
7ec0effd
AD		 6252 if (IS_P3P_TYPE(ha)) {
6253 if (IS_QLA8044(ha)) {
6254 if (test_and_clear_bit(ISP_UNRECOVERABLE,
6255 &base_vha->dpc_flags)) {
6256 qla8044_idc_lock(ha);
6257 qla8044_wr_direct(base_vha,
6258 QLA8044_CRB_DEV_STATE_INDEX,
6259 QLA8XXX_DEV_FAILED);
6260 qla8044_idc_unlock(ha);
6261 ql_log(ql_log_info, base_vha, 0x4004,
6262 "HW State: FAILED.\n");
6263 qla8044_device_state_handler(base_vha);
6264 continue;
6265 }
6266
6267 } else {
6268 if (test_and_clear_bit(ISP_UNRECOVERABLE,
6269 &base_vha->dpc_flags)) {
6270 qla82xx_idc_lock(ha);
6271 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
6272 QLA8XXX_DEV_FAILED);
6273 qla82xx_idc_unlock(ha);
6274 ql_log(ql_log_info, base_vha, 0x0151,
6275 "HW State: FAILED.\n");
6276 qla82xx_device_state_handler(base_vha);
6277 continue;
6278 }
a9083016
GM		 6279 }
6280
6281 if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED,
6282 &base_vha->dpc_flags)) {
6283
7c3df132
SK		 6284 ql_dbg(ql_dbg_dpc, base_vha, 0x4005,
6285 "FCoE context reset scheduled.\n");
a9083016
GM		 6286 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
6287 &base_vha->dpc_flags))) {
6288 if (qla82xx_fcoe_ctx_reset(base_vha)) {
6289 /* FCoE-ctx reset failed.
6290 * Escalate to chip-reset
6291 */
6292 set_bit(ISP_ABORT_NEEDED,
6293 &base_vha->dpc_flags);
6294 }
6295 clear_bit(ABORT_ISP_ACTIVE,
6296 &base_vha->dpc_flags);
6297 }
6298
7c3df132
SK		 6299 ql_dbg(ql_dbg_dpc, base_vha, 0x4006,
6300 "FCoE context reset end.\n");
a9083016 6301 }
8ae6d9c7
GM		 6302 } else if (IS_QLAFX00(ha)) {
6303 if (test_and_clear_bit(ISP_UNRECOVERABLE,
6304 &base_vha->dpc_flags)) {
6305 ql_dbg(ql_dbg_dpc, base_vha, 0x4020,
6306 "Firmware Reset Recovery\n");
6307 if (qlafx00_reset_initialize(base_vha)) {
6308 /* Failed. Abort isp later. */
6309 if (!test_bit(UNLOADING,
f92f82d6 6310 &base_vha->dpc_flags)) {
8ae6d9c7
GM		 6311 set_bit(ISP_UNRECOVERABLE,
6312 &base_vha->dpc_flags);
6313 ql_dbg(ql_dbg_dpc, base_vha,
6314 0x4021,
6315 "Reset Recovery Failed\n");
f92f82d6 6316 }
8ae6d9c7
GM		 6317 }
6318 }
6319
6320 if (test_and_clear_bit(FX00_TARGET_SCAN,
6321 &base_vha->dpc_flags)) {
6322 ql_dbg(ql_dbg_dpc, base_vha, 0x4022,
6323 "ISPFx00 Target Scan scheduled\n");
6324 if (qlafx00_rescan_isp(base_vha)) {
6325 if (!test_bit(UNLOADING,
6326 &base_vha->dpc_flags))
6327 set_bit(ISP_UNRECOVERABLE,
6328 &base_vha->dpc_flags);
6329 ql_dbg(ql_dbg_dpc, base_vha, 0x401e,
6330 "ISPFx00 Target Scan Failed\n");
6331 }
6332 ql_dbg(ql_dbg_dpc, base_vha, 0x401f,
6333 "ISPFx00 Target Scan End\n");
6334 }
e8f5e95d
AB		 6335 if (test_and_clear_bit(FX00_HOST_INFO_RESEND,
6336 &base_vha->dpc_flags)) {
6337 ql_dbg(ql_dbg_dpc, base_vha, 0x4023,
6338 "ISPFx00 Host Info resend scheduled\n");
6339 qlafx00_fx_disc(base_vha,
6340 &base_vha->hw->mr.fcport,
6341 FXDISC_REG_HOST_INFO);
6342 }
a9083016
GM		 6343 }
6344
e4e3a2ce
QT		 6345 if (test_and_clear_bit(DETECT_SFP_CHANGE,
6346 &base_vha->dpc_flags) &&
6347 !test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) {
6348 qla24xx_detect_sfp(base_vha);
6349
6350 if (ha->flags.detected_lr_sfp !=
6351 ha->flags.using_lr_setting)
6352 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
6353 }
6354
b08abbd9
QT		 6355 if (test_and_clear_bit
6356 (ISP_ABORT_NEEDED, &base_vha->dpc_flags) &&
6357 !test_bit(UNLOADING, &base_vha->dpc_flags)) {
93eca613
QT		 6358 bool do_reset = true;
6359
0645cb83 6360 switch (base_vha->qlini_mode) {
93eca613
QT		 6361 case QLA2XXX_INI_MODE_ENABLED:
6362 break;
6363 case QLA2XXX_INI_MODE_DISABLED:
0645cb83
QT		 6364 if (!qla_tgt_mode_enabled(base_vha) &&
6365 !ha->flags.fw_started)
93eca613
QT		 6366 do_reset = false;
6367 break;
6368 case QLA2XXX_INI_MODE_DUAL:
0645cb83
QT		 6369 if (!qla_dual_mode_enabled(base_vha) &&
6370 !ha->flags.fw_started)
93eca613
QT		 6371 do_reset = false;
6372 break;
6373 default:
6374 break;
6375 }
1da177e4 6376
93eca613 6377 if (do_reset && !(test_and_set_bit(ABORT_ISP_ACTIVE,
e315cd28 6378 &base_vha->dpc_flags))) {
93eca613
QT		 6379 ql_dbg(ql_dbg_dpc, base_vha, 0x4007,
6380 "ISP abort scheduled.\n");
a9083016 6381 if (ha->isp_ops->abort_isp(base_vha)) {
1da177e4
LT		 6382 /* failed. retry later */
6383 set_bit(ISP_ABORT_NEEDED,
e315cd28 6384 &base_vha->dpc_flags);
99363ef8 6385 }
e315cd28
AC		 6386 clear_bit(ABORT_ISP_ACTIVE,
6387 &base_vha->dpc_flags);
93eca613
QT		 6388 ql_dbg(ql_dbg_dpc, base_vha, 0x4008,
6389 "ISP abort end.\n");
99363ef8 6390 }
1da177e4
LT		 6391 }
6392
a394aac8
DJ		 6393 if (test_and_clear_bit(FCPORT_UPDATE_NEEDED,
6394 &base_vha->dpc_flags)) {
e315cd28 6395 qla2x00_update_fcports(base_vha);
c9c5ced9 6396 }
d97994dc 6397
8ae6d9c7
GM		 6398 if (IS_QLAFX00(ha))
6399 goto loop_resync_check;
6400
579d12b5 6401 if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) {
7c3df132
SK		 6402 ql_dbg(ql_dbg_dpc, base_vha, 0x4009,
6403 "Quiescence mode scheduled.\n");
7ec0effd
AD		 6404 if (IS_P3P_TYPE(ha)) {
6405 if (IS_QLA82XX(ha))
6406 qla82xx_device_state_handler(base_vha);
6407 if (IS_QLA8044(ha))
6408 qla8044_device_state_handler(base_vha);
8fcd6b8b
CD		 6409 clear_bit(ISP_QUIESCE_NEEDED,
6410 &base_vha->dpc_flags);
6411 if (!ha->flags.quiesce_owner) {
6412 qla2x00_perform_loop_resync(base_vha);
7ec0effd
AD		 6413 if (IS_QLA82XX(ha)) {
6414 qla82xx_idc_lock(ha);
6415 qla82xx_clear_qsnt_ready(
6416 base_vha);
6417 qla82xx_idc_unlock(ha);
6418 } else if (IS_QLA8044(ha)) {
6419 qla8044_idc_lock(ha);
6420 qla8044_clear_qsnt_ready(
6421 base_vha);
6422 qla8044_idc_unlock(ha);
6423 }
8fcd6b8b
CD		 6424 }
6425 } else {
6426 clear_bit(ISP_QUIESCE_NEEDED,
6427 &base_vha->dpc_flags);
6428 qla2x00_quiesce_io(base_vha);
579d12b5 6429 }
7c3df132
SK		 6430 ql_dbg(ql_dbg_dpc, base_vha, 0x400a,
6431 "Quiescence mode end.\n");
579d12b5
SK		 6432 }
6433
e315cd28 6434 if (test_and_clear_bit(RESET_MARKER_NEEDED,
8ae6d9c7 6435 &base_vha->dpc_flags) &&
e315cd28 6436 (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) {
1da177e4 6437
7c3df132
SK		 6438 ql_dbg(ql_dbg_dpc, base_vha, 0x400b,
6439 "Reset marker scheduled.\n");
e315cd28
AC		 6440 qla2x00_rst_aen(base_vha);
6441 clear_bit(RESET_ACTIVE, &base_vha->dpc_flags);
7c3df132
SK		 6442 ql_dbg(ql_dbg_dpc, base_vha, 0x400c,
6443 "Reset marker end.\n");
1da177e4
LT		 6444 }
6445
6446 /* Retry each device up to login retry count */
4005a995 6447 if (test_bit(RELOGIN_NEEDED, &base_vha->dpc_flags) &&
e315cd28
AC		 6448 !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) &&
6449 atomic_read(&base_vha->loop_state) != LOOP_DOWN) {
1da177e4 6450
4005a995
QT		 6451 if (!base_vha->relogin_jif ||
6452 time_after_eq(jiffies, base_vha->relogin_jif)) {
6453 base_vha->relogin_jif = jiffies + HZ;
6454 clear_bit(RELOGIN_NEEDED, &base_vha->dpc_flags);
6455
9b3e0f4d 6456 ql_dbg(ql_dbg_disc, base_vha, 0x400d,
4005a995 6457 "Relogin scheduled.\n");
9b3e0f4d 6458 qla24xx_post_relogin_work(base_vha);
4005a995 6459 }
1da177e4 6460 }
8ae6d9c7 6461loop_resync_check:
e315cd28 6462 if (test_and_clear_bit(LOOP_RESYNC_NEEDED,
8ae6d9c7 6463 &base_vha->dpc_flags)) {
1da177e4 6464
7c3df132
SK		 6465 ql_dbg(ql_dbg_dpc, base_vha, 0x400f,
6466 "Loop resync scheduled.\n");
1da177e4
LT		 6467
6468 if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE,
e315cd28 6469 &base_vha->dpc_flags))) {
1da177e4 6470
52c82823 6471 qla2x00_loop_resync(base_vha);
1da177e4 6472
e315cd28
AC		 6473 clear_bit(LOOP_RESYNC_ACTIVE,
6474 &base_vha->dpc_flags);
1da177e4
LT		 6475 }
6476
7c3df132
SK		 6477 ql_dbg(ql_dbg_dpc, base_vha, 0x4010,
6478 "Loop resync end.\n");
1da177e4
LT		 6479 }
6480
8ae6d9c7
GM		 6481 if (IS_QLAFX00(ha))
6482 goto intr_on_check;
6483
e315cd28
AC		 6484 if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) &&
6485 atomic_read(&base_vha->loop_state) == LOOP_READY) {
6486 clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags);
6487 qla2xxx_flash_npiv_conf(base_vha);
272976ca
AV		 6488 }
6489
8ae6d9c7 6490intr_on_check:
1da177e4 6491 if (!ha->interrupts_on)
fd34f556 6492 ha->isp_ops->enable_intrs(ha);
1da177e4 6493
e315cd28 6494 if (test_and_clear_bit(BEACON_BLINK_NEEDED,
90b604f2
HM		 6495 &base_vha->dpc_flags)) {
6496 if (ha->beacon_blink_led == 1)
6497 ha->isp_ops->beacon_blink(base_vha);
6498 }
f6df144c 6499
d7459527
MH		 6500 /* qpair online check */
6501 if (test_and_clear_bit(QPAIR_ONLINE_CHECK_NEEDED,
6502 &base_vha->dpc_flags)) {
6503 if (ha->flags.eeh_busy ||
6504 ha->flags.pci_channel_io_perm_failure)
6505 online = 0;
6506 else
6507 online = 1;
6508
6509 mutex_lock(&ha->mq_lock);
6510 list_for_each_entry(qpair, &base_vha->qp_list,
6511 qp_list_elem)
6512 qpair->online = online;
6513 mutex_unlock(&ha->mq_lock);
6514 }
6515
8b4673ba
QT		 6516 if (test_and_clear_bit(SET_NVME_ZIO_THRESHOLD_NEEDED,
6517 &base_vha->dpc_flags)) {
deeae7a6
DG		 6518 ql_log(ql_log_info, base_vha, 0xffffff,
6519 "nvme: SET ZIO Activity exchange threshold to %d.\n",
6520 ha->nvme_last_rptd_aen);
8b4673ba
QT		 6521 if (qla27xx_set_zio_threshold(base_vha,
6522 ha->nvme_last_rptd_aen)) {
deeae7a6 6523 ql_log(ql_log_info, base_vha, 0xffffff,
8b4673ba
QT		 6524 "nvme: Unable to SET ZIO Activity exchange threshold to %d.\n",
6525 ha->nvme_last_rptd_aen);
deeae7a6
DG		 6526 }
6527 }
6528
8b4673ba
QT		 6529 if (test_and_clear_bit(SET_ZIO_THRESHOLD_NEEDED,
6530 &base_vha->dpc_flags)) {
6531 ql_log(ql_log_info, base_vha, 0xffffff,
6532 "SET ZIO Activity exchange threshold to %d.\n",
6533 ha->last_zio_threshold);
6534 qla27xx_set_zio_threshold(base_vha,
6535 ha->last_zio_threshold);
6536 }
6537
8ae6d9c7
GM		 6538 if (!IS_QLAFX00(ha))
6539 qla2x00_do_dpc_all_vps(base_vha);
2c3dfe3f 6540
48acad09
QT		 6541 if (test_and_clear_bit(N2N_LINK_RESET,
6542 &base_vha->dpc_flags)) {
6543 qla2x00_lip_reset(base_vha);
6544 }
6545
1da177e4 6546 ha->dpc_active = 0;
c142caf0 6547end_loop:
563585ec 6548 set_current_state(TASK_INTERRUPTIBLE);
1da177e4 6549 } /* End of while(1) */
563585ec 6550 __set_current_state(TASK_RUNNING);
1da177e4 6551
7c3df132
SK		 6552 ql_dbg(ql_dbg_dpc, base_vha, 0x4011,
6553 "DPC handler exiting.\n");
1da177e4
LT		 6554
6555 /*
6556 * Make sure that nobody tries to wake us up again.
6557 */
1da177e4
LT		 6558 ha->dpc_active = 0;
6559
ac280b67
AV		 6560 /* Cleanup any residual CTX SRBs. */
6561 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
6562
39a11240
CH		 6563 return 0;
6564}
6565
6566void
e315cd28 6567qla2xxx_wake_dpc(struct scsi_qla_host *vha)
39a11240 6568{
e315cd28 6569 struct qla_hw_data *ha = vha->hw;
c795c1e4
AV		 6570 struct task_struct *t = ha->dpc_thread;
6571
e315cd28 6572 if (!test_bit(UNLOADING, &vha->dpc_flags) && t)
c795c1e4 6573 wake_up_process(t);
1da177e4
LT		 6574}
6575
1da177e4
LT		 6576/*
6577* qla2x00_rst_aen
6578* Processes asynchronous reset.
6579*
6580* Input:
6581* ha = adapter block pointer.
6582*/
6583static void
e315cd28 6584qla2x00_rst_aen(scsi_qla_host_t *vha)
1da177e4 6585{
e315cd28
AC		 6586 if (vha->flags.online && !vha->flags.reset_active &&
6587 !atomic_read(&vha->loop_down_timer) &&
6588 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) {
1da177e4 6589 do {
e315cd28 6590 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
1da177e4
LT		 6591
6592 /*
6593 * Issue marker command only when we are going to start
6594 * the I/O.
6595 */
e315cd28
AC		 6596 vha->marker_needed = 1;
6597 } while (!atomic_read(&vha->loop_down_timer) &&
6598 (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)));
1da177e4
LT		 6599 }
6600}
6601
1da177e4
LT		 6602/**************************************************************************
6603* qla2x00_timer
6604*
6605* Description:
6606* One second timer
6607*
6608* Context: Interrupt
6609***************************************************************************/
2c3dfe3f 6610void
8e5f4ba0 6611qla2x00_timer(struct timer_list *t)
1da177e4 6612{
8e5f4ba0 6613 scsi_qla_host_t *vha = from_timer(vha, t, timer);
1da177e4 6614 unsigned long cpu_flags = 0;
1da177e4
LT		 6615 int start_dpc = 0;
6616 int index;
6617 srb_t *sp;
85880801 6618 uint16_t w;
e315cd28 6619 struct qla_hw_data *ha = vha->hw;
73208dfd 6620 struct req_que *req;
85880801 6621
a5b36321 6622 if (ha->flags.eeh_busy) {
7c3df132
SK		 6623 ql_dbg(ql_dbg_timer, vha, 0x6000,
6624 "EEH = %d, restarting timer.\n",
6625 ha->flags.eeh_busy);
a5b36321
LC		 6626 qla2x00_restart_timer(vha, WATCH_INTERVAL);
6627 return;
6628 }
6629
f3ddac19
CD		 6630 /*
6631 * Hardware read to raise pending EEH errors during mailbox waits. If
6632 * the read returns -1 then disable the board.
6633 */
6634 if (!pci_channel_offline(ha->pdev)) {
85880801 6635 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w);
c821e0d5 6636 qla2x00_check_reg16_for_disconnect(vha, w);
f3ddac19 6637 }
1da177e4 6638
cefcaba6 6639 /* Make sure qla82xx_watchdog is run only for physical port */
7ec0effd 6640 if (!vha->vp_idx && IS_P3P_TYPE(ha)) {
579d12b5
SK		 6641 if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags))
6642 start_dpc++;
7ec0effd
AD		 6643 if (IS_QLA82XX(ha))
6644 qla82xx_watchdog(vha);
6645 else if (IS_QLA8044(ha))
6646 qla8044_watchdog(vha);
579d12b5
SK		 6647 }
6648
8ae6d9c7
GM		 6649 if (!vha->vp_idx && IS_QLAFX00(ha))
6650 qlafx00_timer_routine(vha);
6651
1da177e4 6652 /* Loop down handler. */
e315cd28 6653 if (atomic_read(&vha->loop_down_timer) > 0 &&
8f7daead
GM		 6654 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) &&
6655 !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags))
e315cd28 6656 && vha->flags.online) {
1da177e4 6657
e315cd28
AC		 6658 if (atomic_read(&vha->loop_down_timer) ==
6659 vha->loop_down_abort_time) {
1da177e4 6660
7c3df132
SK		 6661 ql_log(ql_log_info, vha, 0x6008,
6662 "Loop down - aborting the queues before time expires.\n");
1da177e4 6663
e315cd28
AC		 6664 if (!IS_QLA2100(ha) && vha->link_down_timeout)
6665 atomic_set(&vha->loop_state, LOOP_DEAD);
1da177e4 6666
f08b7251
AV		 6667 /*
6668 * Schedule an ISP abort to return any FCP2-device
6669 * commands.
6670 */
2c3dfe3f 6671 /* NPIV - scan physical port only */
e315cd28 6672 if (!vha->vp_idx) {
2c3dfe3f
SJ		 6673 spin_lock_irqsave(&ha->hardware_lock,
6674 cpu_flags);
73208dfd 6675 req = ha->req_q_map[0];
2c3dfe3f 6676 for (index = 1;
8d93f550 6677 index < req->num_outstanding_cmds;
2c3dfe3f
SJ		 6678 index++) {
6679 fc_port_t *sfcp;
6680
e315cd28 6681 sp = req->outstanding_cmds[index];
2c3dfe3f
SJ		 6682 if (!sp)
6683 continue;
c5419e26
QT		 6684 if (sp->cmd_type != TYPE_SRB)
6685 continue;
9ba56b95 6686 if (sp->type != SRB_SCSI_CMD)
cf53b069 6687 continue;
2c3dfe3f 6688 sfcp = sp->fcport;
f08b7251 6689 if (!(sfcp->flags & FCF_FCP2_DEVICE))
2c3dfe3f 6690 continue;
bdf79621 6691
8f7daead
GM		 6692 if (IS_QLA82XX(ha))
6693 set_bit(FCOE_CTX_RESET_NEEDED,
6694 &vha->dpc_flags);
6695 else
6696 set_bit(ISP_ABORT_NEEDED,
e315cd28 6697 &vha->dpc_flags);
2c3dfe3f
SJ		 6698 break;
6699 }
6700 spin_unlock_irqrestore(&ha->hardware_lock,
e315cd28 6701 cpu_flags);
1da177e4 6702 }
1da177e4
LT		 6703 start_dpc++;
6704 }
6705
6706 /* if the loop has been down for 4 minutes, reinit adapter */
e315cd28 6707 if (atomic_dec_and_test(&vha->loop_down_timer) != 0) {
0d6e61bc 6708 if (!(vha->device_flags & DFLG_NO_CABLE)) {
7c3df132 6709 ql_log(ql_log_warn, vha, 0x6009,
1da177e4
LT		 6710 "Loop down - aborting ISP.\n");
6711
8f7daead
GM		 6712 if (IS_QLA82XX(ha))
6713 set_bit(FCOE_CTX_RESET_NEEDED,
6714 &vha->dpc_flags);
6715 else
6716 set_bit(ISP_ABORT_NEEDED,
6717 &vha->dpc_flags);
1da177e4
LT		 6718 }
6719 }
7c3df132
SK		 6720 ql_dbg(ql_dbg_timer, vha, 0x600a,
6721 "Loop down - seconds remaining %d.\n",
6722 atomic_read(&vha->loop_down_timer));
1da177e4 6723 }
cefcaba6
SK		 6724 /* Check if beacon LED needs to be blinked for physical host only */
6725 if (!vha->vp_idx && (ha->beacon_blink_led == 1)) {
999916dc 6726 /* There is no beacon_blink function for ISP82xx */
7ec0effd 6727 if (!IS_P3P_TYPE(ha)) {
999916dc
SK		 6728 set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags);
6729 start_dpc++;
6730 }
f6df144c 6731 }
6732
550bf57d 6733 /* Process any deferred work. */
9b3e0f4d
QT		 6734 if (!list_empty(&vha->work_list)) {
6735 unsigned long flags;
6736 bool q = false;
6737
6738 spin_lock_irqsave(&vha->work_lock, flags);
6739 if (!test_and_set_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags))
6740 q = true;
6741 spin_unlock_irqrestore(&vha->work_lock, flags);
6742 if (q)
6743 queue_work(vha->hw->wq, &vha->iocb_work);
6744 }
550bf57d 6745
7401bc18
DG		 6746 /*
6747 * FC-NVME
6748 * see if the active AEN count has changed from what was last reported.
6749 */
8b4673ba
QT		 6750 if (!vha->vp_idx && (atomic_read(&ha->nvme_active_aen_cnt) !=
6751 ha->nvme_last_rptd_aen) && ha->zio_mode == QLA_ZIO_MODE_6) {
7401bc18 6752 ql_log(ql_log_info, vha, 0x3002,
8b4673ba
QT		 6753 "nvme: Sched: Set ZIO exchange threshold to %d.\n",
6754 ha->nvme_last_rptd_aen);
deeae7a6 6755 ha->nvme_last_rptd_aen = atomic_read(&ha->nvme_active_aen_cnt);
8b4673ba
QT		 6756 set_bit(SET_NVME_ZIO_THRESHOLD_NEEDED, &vha->dpc_flags);
6757 start_dpc++;
6758 }
6759
6760 if (!vha->vp_idx &&
6761 (atomic_read(&ha->zio_threshold) != ha->last_zio_threshold) &&
6762 (ha->zio_mode == QLA_ZIO_MODE_6) &&
ecc89f25 6763 (IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))) {
8b4673ba
QT		 6764 ql_log(ql_log_info, vha, 0x3002,
6765 "Sched: Set ZIO exchange threshold to %d.\n",
6766 ha->last_zio_threshold);
6767 ha->last_zio_threshold = atomic_read(&ha->zio_threshold);
deeae7a6
DG		 6768 set_bit(SET_ZIO_THRESHOLD_NEEDED, &vha->dpc_flags);
6769 start_dpc++;
7401bc18
DG		 6770 }
6771
1da177e4 6772 /* Schedule the DPC routine if needed */
e315cd28
AC		 6773 if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) ||
6774 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) ||
6775 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags) ||
1da177e4 6776 start_dpc ||
e315cd28
AC		 6777 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) ||
6778 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) ||
a9083016
GM		 6779 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) ||
6780 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) ||
e315cd28 6781 test_bit(VP_DPC_NEEDED, &vha->dpc_flags) ||
50280c01 6782 test_bit(RELOGIN_NEEDED, &vha->dpc_flags))) {
7c3df132
SK		 6783 ql_dbg(ql_dbg_timer, vha, 0x600b,
6784 "isp_abort_needed=%d loop_resync_needed=%d "
6785 "fcport_update_needed=%d start_dpc=%d "
6786 "reset_marker_needed=%d",
6787 test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags),
6788 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags),
6789 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags),
6790 start_dpc,
6791 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags));
6792 ql_dbg(ql_dbg_timer, vha, 0x600c,
6793 "beacon_blink_needed=%d isp_unrecoverable=%d "
6794 "fcoe_ctx_reset_needed=%d vp_dpc_needed=%d "
50280c01 6795 "relogin_needed=%d.\n",
7c3df132
SK		 6796 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags),
6797 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags),
6798 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags),
6799 test_bit(VP_DPC_NEEDED, &vha->dpc_flags),
50280c01 6800 test_bit(RELOGIN_NEEDED, &vha->dpc_flags));
e315cd28 6801 qla2xxx_wake_dpc(vha);
7c3df132 6802 }
1da177e4 6803
e315cd28 6804 qla2x00_restart_timer(vha, WATCH_INTERVAL);
1da177e4
LT		 6805}
6806
5433383e
AV		 6807/* Firmware interface routines. */
6808
5433383e
AV		 6809#define FW_ISP21XX 0
6810#define FW_ISP22XX 1
6811#define FW_ISP2300 2
6812#define FW_ISP2322 3
48c02fde 6813#define FW_ISP24XX 4
c3a2f0df 6814#define FW_ISP25XX 5
3a03eb79 6815#define FW_ISP81XX 6
a9083016 6816#define FW_ISP82XX 7
6246b8a1
GM		 6817#define FW_ISP2031 8
6818#define FW_ISP8031 9
2c5bbbb2 6819#define FW_ISP27XX 10
ecc89f25 6820#define FW_ISP28XX 11
5433383e 6821
bb8ee499
AV		 6822#define FW_FILE_ISP21XX "ql2100_fw.bin"
6823#define FW_FILE_ISP22XX "ql2200_fw.bin"
6824#define FW_FILE_ISP2300 "ql2300_fw.bin"
6825#define FW_FILE_ISP2322 "ql2322_fw.bin"
6826#define FW_FILE_ISP24XX "ql2400_fw.bin"
c3a2f0df 6827#define FW_FILE_ISP25XX "ql2500_fw.bin"
3a03eb79 6828#define FW_FILE_ISP81XX "ql8100_fw.bin"
a9083016 6829#define FW_FILE_ISP82XX "ql8200_fw.bin"
6246b8a1
GM		 6830#define FW_FILE_ISP2031 "ql2600_fw.bin"
6831#define FW_FILE_ISP8031 "ql8300_fw.bin"
2c5bbbb2 6832#define FW_FILE_ISP27XX "ql2700_fw.bin"
ecc89f25 6833#define FW_FILE_ISP28XX "ql2800_fw.bin"
f73cb695 6834
bb8ee499 6835
e1e82b6f 6836static DEFINE_MUTEX(qla_fw_lock);
5433383e 6837
ecc89f25 6838static struct fw_blob qla_fw_blobs[] = {
bb8ee499
AV		 6839 { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, },
6840 { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, },
6841 { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, },
6842 { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, },
6843 { .name = FW_FILE_ISP24XX, },
c3a2f0df 6844 { .name = FW_FILE_ISP25XX, },
3a03eb79 6845 { .name = FW_FILE_ISP81XX, },
a9083016 6846 { .name = FW_FILE_ISP82XX, },
6246b8a1
GM		 6847 { .name = FW_FILE_ISP2031, },
6848 { .name = FW_FILE_ISP8031, },
2c5bbbb2 6849 { .name = FW_FILE_ISP27XX, },
ecc89f25
JC		 6850 { .name = FW_FILE_ISP28XX, },
6851 { .name = NULL, },
5433383e
AV		 6852};
6853
6854struct fw_blob *
e315cd28 6855qla2x00_request_firmware(scsi_qla_host_t *vha)
5433383e 6856{
e315cd28 6857 struct qla_hw_data *ha = vha->hw;
5433383e
AV		 6858 struct fw_blob *blob;
6859
5433383e
AV		 6860 if (IS_QLA2100(ha)) {
6861 blob = &qla_fw_blobs[FW_ISP21XX];
6862 } else if (IS_QLA2200(ha)) {
6863 blob = &qla_fw_blobs[FW_ISP22XX];
48c02fde 6864 } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
5433383e 6865 blob = &qla_fw_blobs[FW_ISP2300];
48c02fde 6866 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
5433383e 6867 blob = &qla_fw_blobs[FW_ISP2322];
4d4df193 6868 } else if (IS_QLA24XX_TYPE(ha)) {
5433383e 6869 blob = &qla_fw_blobs[FW_ISP24XX];
c3a2f0df
AV		 6870 } else if (IS_QLA25XX(ha)) {
6871 blob = &qla_fw_blobs[FW_ISP25XX];
3a03eb79
AV		 6872 } else if (IS_QLA81XX(ha)) {
6873 blob = &qla_fw_blobs[FW_ISP81XX];
a9083016
GM		 6874 } else if (IS_QLA82XX(ha)) {
6875 blob = &qla_fw_blobs[FW_ISP82XX];
6246b8a1
GM		 6876 } else if (IS_QLA2031(ha)) {
6877 blob = &qla_fw_blobs[FW_ISP2031];
6878 } else if (IS_QLA8031(ha)) {
6879 blob = &qla_fw_blobs[FW_ISP8031];
2c5bbbb2
JC		 6880 } else if (IS_QLA27XX(ha)) {
6881 blob = &qla_fw_blobs[FW_ISP27XX];
ecc89f25
JC		 6882 } else if (IS_QLA28XX(ha)) {
6883 blob = &qla_fw_blobs[FW_ISP28XX];
8a655229
DC		 6884 } else {
6885 return NULL;
5433383e
AV		 6886 }
6887
ecc89f25
JC		 6888 if (!blob->name)
6889 return NULL;
6890
e1e82b6f 6891 mutex_lock(&qla_fw_lock);
5433383e
AV		 6892 if (blob->fw)
6893 goto out;
6894
6895 if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) {
7c3df132
SK		 6896 ql_log(ql_log_warn, vha, 0x0063,
6897 "Failed to load firmware image (%s).\n", blob->name);
5433383e
AV		 6898 blob->fw = NULL;
6899 blob = NULL;
5433383e
AV		 6900 }
6901
6902out:
e1e82b6f 6903 mutex_unlock(&qla_fw_lock);
5433383e
AV		 6904 return blob;
6905}
6906
6907static void
6908qla2x00_release_firmware(void)
6909{
ecc89f25 6910 struct fw_blob *blob;
5433383e 6911
e1e82b6f 6912 mutex_lock(&qla_fw_lock);
ecc89f25
JC		 6913 for (blob = qla_fw_blobs; blob->name; blob++)
6914 release_firmware(blob->fw);
e1e82b6f 6915 mutex_unlock(&qla_fw_lock);
5433383e
AV		 6916}
6917
14e660e6
SJ		 6918static pci_ers_result_t
6919qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
6920{
85880801
AV		 6921 scsi_qla_host_t *vha = pci_get_drvdata(pdev);
6922 struct qla_hw_data *ha = vha->hw;
6923
7c3df132
SK		 6924 ql_dbg(ql_dbg_aer, vha, 0x9000,
6925 "PCI error detected, state %x.\n", state);
b9b12f73 6926
efdb5760
SC		 6927 if (!atomic_read(&pdev->enable_cnt)) {
6928 ql_log(ql_log_info, vha, 0xffff,
6929 "PCI device is disabled,state %x\n", state);
6930 return PCI_ERS_RESULT_NEED_RESET;
6931 }
6932
14e660e6
SJ		 6933 switch (state) {
6934 case pci_channel_io_normal:
85880801 6935 ha->flags.eeh_busy = 0;
c38d1baf 6936 if (ql2xmqsupport || ql2xnvmeenable) {
d7459527
MH		 6937 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags);
6938 qla2xxx_wake_dpc(vha);
6939 }
14e660e6
SJ		 6940 return PCI_ERS_RESULT_CAN_RECOVER;
6941 case pci_channel_io_frozen:
85880801 6942 ha->flags.eeh_busy = 1;
a5b36321
LC		 6943 /* For ISP82XX complete any pending mailbox cmd */
6944 if (IS_QLA82XX(ha)) {
7190575f 6945 ha->flags.isp82xx_fw_hung = 1;
c8f6544e
CD		 6946 ql_dbg(ql_dbg_aer, vha, 0x9001, "Pci channel io frozen\n");
6947 qla82xx_clear_pending_mbx(vha);
a5b36321 6948 }
90a86fc0 6949 qla2x00_free_irqs(vha);
14e660e6 6950 pci_disable_device(pdev);
bddd2d65
LC		 6951 /* Return back all IOs */
6952 qla2x00_abort_all_cmds(vha, DID_RESET << 16);
c38d1baf 6953 if (ql2xmqsupport || ql2xnvmeenable) {
d7459527
MH		 6954 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags);
6955 qla2xxx_wake_dpc(vha);
6956 }
14e660e6
SJ		 6957 return PCI_ERS_RESULT_NEED_RESET;
6958 case pci_channel_io_perm_failure:
85880801
AV		 6959 ha->flags.pci_channel_io_perm_failure = 1;
6960 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
c38d1baf 6961 if (ql2xmqsupport || ql2xnvmeenable) {
d7459527
MH		 6962 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags);
6963 qla2xxx_wake_dpc(vha);
6964 }
14e660e6
SJ		 6965 return PCI_ERS_RESULT_DISCONNECT;
6966 }
6967 return PCI_ERS_RESULT_NEED_RESET;
6968}
6969
6970static pci_ers_result_t
6971qla2xxx_pci_mmio_enabled(struct pci_dev *pdev)
6972{
6973 int risc_paused = 0;
6974 uint32_t stat;
6975 unsigned long flags;
e315cd28
AC		 6976 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
6977 struct qla_hw_data *ha = base_vha->hw;
14e660e6
SJ		 6978 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
6979 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
6980
bcc5b6d3
SK		 6981 if (IS_QLA82XX(ha))
6982 return PCI_ERS_RESULT_RECOVERED;
6983
14e660e6
SJ		 6984 spin_lock_irqsave(&ha->hardware_lock, flags);
6985 if (IS_QLA2100(ha) || IS_QLA2200(ha)){
6986 stat = RD_REG_DWORD(&reg->hccr);
6987 if (stat & HCCR_RISC_PAUSE)
6988 risc_paused = 1;
6989 } else if (IS_QLA23XX(ha)) {
6990 stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
6991 if (stat & HSR_RISC_PAUSED)
6992 risc_paused = 1;
6993 } else if (IS_FWI2_CAPABLE(ha)) {
6994 stat = RD_REG_DWORD(&reg24->host_status);
6995 if (stat & HSRX_RISC_PAUSED)
6996 risc_paused = 1;
6997 }
6998 spin_unlock_irqrestore(&ha->hardware_lock, flags);
6999
7000 if (risc_paused) {
7c3df132
SK		 7001 ql_log(ql_log_info, base_vha, 0x9003,
7002 "RISC paused -- mmio_enabled, Dumping firmware.\n");
e315cd28 7003 ha->isp_ops->fw_dump(base_vha, 0);
14e660e6
SJ		 7004
7005 return PCI_ERS_RESULT_NEED_RESET;
7006 } else
7007 return PCI_ERS_RESULT_RECOVERED;
7008}
7009
fa492630
SK		 7010static uint32_t
7011qla82xx_error_recovery(scsi_qla_host_t *base_vha)
a5b36321
LC		 7012{
7013 uint32_t rval = QLA_FUNCTION_FAILED;
7014 uint32_t drv_active = 0;
7015 struct qla_hw_data *ha = base_vha->hw;
7016 int fn;
7017 struct pci_dev *other_pdev = NULL;
7018
7c3df132
SK		 7019 ql_dbg(ql_dbg_aer, base_vha, 0x9006,
7020 "Entered %s.\n", __func__);
a5b36321
LC		 7021
7022 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
7023
7024 if (base_vha->flags.online) {
7025 /* Abort all outstanding commands,
7026 * so as to be requeued later */
7027 qla2x00_abort_isp_cleanup(base_vha);
7028 }
7029
7030
7031 fn = PCI_FUNC(ha->pdev->devfn);
7032 while (fn > 0) {
7033 fn--;
7c3df132
SK		 7034 ql_dbg(ql_dbg_aer, base_vha, 0x9007,
7035 "Finding pci device at function = 0x%x.\n", fn);
a5b36321
LC		 7036 other_pdev =
7037 pci_get_domain_bus_and_slot(pci_domain_nr(ha->pdev->bus),
7038 ha->pdev->bus->number, PCI_DEVFN(PCI_SLOT(ha->pdev->devfn),
7039 fn));
7040
7041 if (!other_pdev)
7042 continue;
7043 if (atomic_read(&other_pdev->enable_cnt)) {
7c3df132
SK		 7044 ql_dbg(ql_dbg_aer, base_vha, 0x9008,
7045 "Found PCI func available and enable at 0x%x.\n",
7046 fn);
a5b36321
LC		 7047 pci_dev_put(other_pdev);
7048 break;
7049 }
7050 pci_dev_put(other_pdev);
7051 }
7052
7053 if (!fn) {
7054 /* Reset owner */
7c3df132
SK		 7055 ql_dbg(ql_dbg_aer, base_vha, 0x9009,
7056 "This devfn is reset owner = 0x%x.\n",
7057 ha->pdev->devfn);
a5b36321
LC		 7058 qla82xx_idc_lock(ha);
7059
7060 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 7061 QLA8XXX_DEV_INITIALIZING);
a5b36321
LC		 7062
7063 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION,
7064 QLA82XX_IDC_VERSION);
7065
7066 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
7c3df132
SK		 7067 ql_dbg(ql_dbg_aer, base_vha, 0x900a,
7068 "drv_active = 0x%x.\n", drv_active);
a5b36321
LC		 7069
7070 qla82xx_idc_unlock(ha);
7071 /* Reset if device is not already reset
7072 * drv_active would be 0 if a reset has already been done
7073 */
7074 if (drv_active)
7075 rval = qla82xx_start_firmware(base_vha);
7076 else
7077 rval = QLA_SUCCESS;
7078 qla82xx_idc_lock(ha);
7079
7080 if (rval != QLA_SUCCESS) {
7c3df132
SK		 7081 ql_log(ql_log_info, base_vha, 0x900b,
7082 "HW State: FAILED.\n");
a5b36321
LC		 7083 qla82xx_clear_drv_active(ha);
7084 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 7085 QLA8XXX_DEV_FAILED);
a5b36321 7086 } else {
7c3df132
SK		 7087 ql_log(ql_log_info, base_vha, 0x900c,
7088 "HW State: READY.\n");
a5b36321 7089 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 7090 QLA8XXX_DEV_READY);
a5b36321 7091 qla82xx_idc_unlock(ha);
7190575f 7092 ha->flags.isp82xx_fw_hung = 0;
a5b36321
LC		 7093 rval = qla82xx_restart_isp(base_vha);
7094 qla82xx_idc_lock(ha);
7095 /* Clear driver state register */
7096 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, 0);
7097 qla82xx_set_drv_active(base_vha);
7098 }
7099 qla82xx_idc_unlock(ha);
7100 } else {
7c3df132
SK		 7101 ql_dbg(ql_dbg_aer, base_vha, 0x900d,
7102 "This devfn is not reset owner = 0x%x.\n",
7103 ha->pdev->devfn);
a5b36321 7104 if ((qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE) ==
7d613ac6 7105 QLA8XXX_DEV_READY)) {
7190575f 7106 ha->flags.isp82xx_fw_hung = 0;
a5b36321
LC		 7107 rval = qla82xx_restart_isp(base_vha);
7108 qla82xx_idc_lock(ha);
7109 qla82xx_set_drv_active(base_vha);
7110 qla82xx_idc_unlock(ha);
7111 }
7112 }
7113 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
7114
7115 return rval;
7116}
7117
14e660e6
SJ		 7118static pci_ers_result_t
7119qla2xxx_pci_slot_reset(struct pci_dev *pdev)
7120{
7121 pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT;
e315cd28
AC		 7122 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
7123 struct qla_hw_data *ha = base_vha->hw;
90a86fc0
JC		 7124 struct rsp_que *rsp;
7125 int rc, retries = 10;
09483916 7126
7c3df132
SK		 7127 ql_dbg(ql_dbg_aer, base_vha, 0x9004,
7128 "Slot Reset.\n");
85880801 7129
90a86fc0
JC		 7130 /* Workaround: qla2xxx driver which access hardware earlier
7131 * needs error state to be pci_channel_io_online.
7132 * Otherwise mailbox command timesout.
7133 */
7134 pdev->error_state = pci_channel_io_normal;
7135
7136 pci_restore_state(pdev);
7137
8c1496bd
RL		 7138 /* pci_restore_state() clears the saved_state flag of the device
7139 * save restored state which resets saved_state flag
7140 */
7141 pci_save_state(pdev);
7142
09483916
BH		 7143 if (ha->mem_only)
7144 rc = pci_enable_device_mem(pdev);
7145 else
7146 rc = pci_enable_device(pdev);
14e660e6 7147
09483916 7148 if (rc) {
7c3df132 7149 ql_log(ql_log_warn, base_vha, 0x9005,
14e660e6 7150 "Can't re-enable PCI device after reset.\n");
a5b36321 7151 goto exit_slot_reset;
14e660e6 7152 }
14e660e6 7153
90a86fc0
JC		 7154 rsp = ha->rsp_q_map[0];
7155 if (qla2x00_request_irqs(ha, rsp))
a5b36321 7156 goto exit_slot_reset;
90a86fc0 7157
e315cd28 7158 if (ha->isp_ops->pci_config(base_vha))
a5b36321
LC		 7159 goto exit_slot_reset;
7160
7161 if (IS_QLA82XX(ha)) {
7162 if (qla82xx_error_recovery(base_vha) == QLA_SUCCESS) {
7163 ret = PCI_ERS_RESULT_RECOVERED;
7164 goto exit_slot_reset;
7165 } else
7166 goto exit_slot_reset;
7167 }
14e660e6 7168
90a86fc0
JC		 7169 while (ha->flags.mbox_busy && retries--)
7170 msleep(1000);
85880801 7171
e315cd28 7172 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
a9083016 7173 if (ha->isp_ops->abort_isp(base_vha) == QLA_SUCCESS)
14e660e6 7174 ret = PCI_ERS_RESULT_RECOVERED;
e315cd28 7175 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
14e660e6 7176
90a86fc0 7177
a5b36321 7178exit_slot_reset:
7c3df132
SK		 7179 ql_dbg(ql_dbg_aer, base_vha, 0x900e,
7180 "slot_reset return %x.\n", ret);
85880801 7181
14e660e6
SJ		 7182 return ret;
7183}
7184
7185static void
7186qla2xxx_pci_resume(struct pci_dev *pdev)
7187{
e315cd28
AC		 7188 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
7189 struct qla_hw_data *ha = base_vha->hw;
14e660e6
SJ		 7190 int ret;
7191
7c3df132
SK		 7192 ql_dbg(ql_dbg_aer, base_vha, 0x900f,
7193 "pci_resume.\n");
85880801 7194
e315cd28 7195 ret = qla2x00_wait_for_hba_online(base_vha);
14e660e6 7196 if (ret != QLA_SUCCESS) {
7c3df132
SK		 7197 ql_log(ql_log_fatal, base_vha, 0x9002,
7198 "The device failed to resume I/O from slot/link_reset.\n");
14e660e6 7199 }
85880801
AV		 7200
7201 ha->flags.eeh_busy = 0;
14e660e6
SJ		 7202}
7203
590f806d
QT		 7204static void
7205qla_pci_reset_prepare(struct pci_dev *pdev)
7206{
7207 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
7208 struct qla_hw_data *ha = base_vha->hw;
7209 struct qla_qpair *qpair;
7210
7211 ql_log(ql_log_warn, base_vha, 0xffff,
7212 "%s.\n", __func__);
7213
7214 /*
7215 * PCI FLR/function reset is about to reset the
7216 * slot. Stop the chip to stop all DMA access.
7217 * It is assumed that pci_reset_done will be called
7218 * after FLR to resume Chip operation.
7219 */
7220 ha->flags.eeh_busy = 1;
7221 mutex_lock(&ha->mq_lock);
7222 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem)
7223 qpair->online = 0;
7224 mutex_unlock(&ha->mq_lock);
7225
7226 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
7227 qla2x00_abort_isp_cleanup(base_vha);
7228 qla2x00_abort_all_cmds(base_vha, DID_RESET << 16);
7229}
7230
7231static void
7232qla_pci_reset_done(struct pci_dev *pdev)
7233{
7234 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
7235 struct qla_hw_data *ha = base_vha->hw;
7236 struct qla_qpair *qpair;
7237
7238 ql_log(ql_log_warn, base_vha, 0xffff,
7239 "%s.\n", __func__);
7240
7241 /*
7242 * FLR just completed by PCI layer. Resume adapter
7243 */
7244 ha->flags.eeh_busy = 0;
7245 mutex_lock(&ha->mq_lock);
7246 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem)
7247 qpair->online = 1;
7248 mutex_unlock(&ha->mq_lock);
7249
7250 base_vha->flags.online = 1;
7251 ha->isp_ops->abort_isp(base_vha);
7252 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
7253}
7254
5601236b
MH		 7255static int qla2xxx_map_queues(struct Scsi_Host *shost)
7256{
d68b850e 7257 int rc;
5601236b 7258 scsi_qla_host_t *vha = (scsi_qla_host_t *)shost->hostdata;
485b0eca 7259 struct blk_mq_queue_map *qmap = &shost->tag_set.map[HCTX_TYPE_DEFAULT];
5601236b 7260
f3e02695 7261 if (USER_CTRL_IRQ(vha->hw) || !vha->hw->mqiobase)
ed76e329 7262 rc = blk_mq_map_queues(qmap);
d68b850e 7263 else
f0783d43 7264 rc = blk_mq_pci_map_queues(qmap, vha->hw->pdev, vha->irq_offset);
d68b850e 7265 return rc;
5601236b
MH		 7266}
7267
a55b2d21 7268static const struct pci_error_handlers qla2xxx_err_handler = {
14e660e6
SJ		 7269 .error_detected = qla2xxx_pci_error_detected,
7270 .mmio_enabled = qla2xxx_pci_mmio_enabled,
7271 .slot_reset = qla2xxx_pci_slot_reset,
7272 .resume = qla2xxx_pci_resume,
590f806d
QT		 7273 .reset_prepare = qla_pci_reset_prepare,
7274 .reset_done = qla_pci_reset_done,
14e660e6
SJ		 7275};
7276
5433383e 7277static struct pci_device_id qla2xxx_pci_tbl[] = {
47f5e069
AV		 7278 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) },
7279 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) },
7280 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) },
7281 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) },
7282 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) },
7283 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) },
7284 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) },
7285 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) },
7286 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) },
4d4df193 7287 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) },
47f5e069
AV		 7288 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) },
7289 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) },
c3a2f0df 7290 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) },
6246b8a1 7291 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2031) },
3a03eb79 7292 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) },
a9083016 7293 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) },
650f528f 7294 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8031) },
8ae6d9c7 7295 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISPF001) },
7ec0effd 7296 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8044) },
f73cb695 7297 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2071) },
2c5bbbb2 7298 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2271) },
2b48992f 7299 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2261) },
ecc89f25
JC		 7300 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2061) },
7301 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2081) },
7302 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2281) },
7303 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2089) },
7304 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2289) },
5433383e
AV		 7305 { 0 },
7306};
7307MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl);
7308
fca29703 7309static struct pci_driver qla2xxx_pci_driver = {
cb63067a 7310 .name = QLA2XXX_DRIVER_NAME,
0a21ef1e
JB		 7311 .driver = {
7312 .owner = THIS_MODULE,
7313 },
fca29703 7314 .id_table = qla2xxx_pci_tbl,
7ee61397 7315 .probe = qla2x00_probe_one,
4c993f76 7316 .remove = qla2x00_remove_one,
e30d1756 7317 .shutdown = qla2x00_shutdown,
14e660e6 7318 .err_handler = &qla2xxx_err_handler,
fca29703
AV		 7319};
7320
75ef9de1 7321static const struct file_operations apidev_fops = {
6a03b4cd 7322 .owner = THIS_MODULE,
6038f373 7323 .llseek = noop_llseek,
6a03b4cd
HZ		 7324};
7325
1da177e4
LT		 7326/**
7327 * qla2x00_module_init - Module initialization.
7328 **/
7329static int __init
7330qla2x00_module_init(void)
7331{
fca29703
AV		 7332 int ret = 0;
7333
1da177e4 7334 /* Allocate cache for SRBs. */
354d6b21 7335 srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0,
20c2df83 7336 SLAB_HWCACHE_ALIGN, NULL);
1da177e4 7337 if (srb_cachep == NULL) {
7c3df132
SK		 7338 ql_log(ql_log_fatal, NULL, 0x0001,
7339 "Unable to allocate SRB cache...Failing load!.\n");
1da177e4
LT		 7340 return -ENOMEM;
7341 }
7342
2d70c103
NB		 7343 /* Initialize target kmem_cache and mem_pools */
7344 ret = qlt_init();
7345 if (ret < 0) {
7346 kmem_cache_destroy(srb_cachep);
7347 return ret;
7348 } else if (ret > 0) {
7349 /*
7350 * If initiator mode is explictly disabled by qlt_init(),
7351 * prevent scsi_transport_fc.c:fc_scsi_scan_rport() from
7352 * performing scsi_scan_target() during LOOP UP event.
7353 */
7354 qla2xxx_transport_functions.disable_target_scan = 1;
7355 qla2xxx_transport_vport_functions.disable_target_scan = 1;
7356 }
7357
1da177e4
LT		 7358 /* Derive version string. */
7359 strcpy(qla2x00_version_str, QLA2XXX_VERSION);
11010fec 7360 if (ql2xextended_error_logging)
0181944f 7361 strcat(qla2x00_version_str, "-debug");
fed0f68a
JC		 7362 if (ql2xextended_error_logging == 1)
7363 ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK;
0181944f 7364
0645cb83
QT		 7365 if (ql2x_ini_mode == QLA2XXX_INI_MODE_DUAL)
7366 qla_insert_tgt_attrs();
7367
1c97a12a
AV		 7368 qla2xxx_transport_template =
7369 fc_attach_transport(&qla2xxx_transport_functions);
2c3dfe3f
SJ		 7370 if (!qla2xxx_transport_template) {
7371 kmem_cache_destroy(srb_cachep);
7c3df132
SK		 7372 ql_log(ql_log_fatal, NULL, 0x0002,
7373 "fc_attach_transport failed...Failing load!.\n");
2d70c103 7374 qlt_exit();
1da177e4 7375 return -ENODEV;
2c3dfe3f 7376 }
6a03b4cd
HZ		 7377
7378 apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops);
7379 if (apidev_major < 0) {
7c3df132
SK		 7380 ql_log(ql_log_fatal, NULL, 0x0003,
7381 "Unable to register char device %s.\n", QLA2XXX_APIDEV);
6a03b4cd
HZ		 7382 }
7383
2c3dfe3f
SJ		 7384 qla2xxx_transport_vport_template =
7385 fc_attach_transport(&qla2xxx_transport_vport_functions);
7386 if (!qla2xxx_transport_vport_template) {
7387 kmem_cache_destroy(srb_cachep);
2d70c103 7388 qlt_exit();
2c3dfe3f 7389 fc_release_transport(qla2xxx_transport_template);
7c3df132
SK		 7390 ql_log(ql_log_fatal, NULL, 0x0004,
7391 "fc_attach_transport vport failed...Failing load!.\n");
1da177e4 7392 return -ENODEV;
2c3dfe3f 7393 }
7c3df132
SK		 7394 ql_log(ql_log_info, NULL, 0x0005,
7395 "QLogic Fibre Channel HBA Driver: %s.\n",
fd9a29f0 7396 qla2x00_version_str);
7ee61397 7397 ret = pci_register_driver(&qla2xxx_pci_driver);
fca29703
AV		 7398 if (ret) {
7399 kmem_cache_destroy(srb_cachep);
2d70c103 7400 qlt_exit();
fca29703 7401 fc_release_transport(qla2xxx_transport_template);
2c3dfe3f 7402 fc_release_transport(qla2xxx_transport_vport_template);
7c3df132
SK		 7403 ql_log(ql_log_fatal, NULL, 0x0006,
7404 "pci_register_driver failed...ret=%d Failing load!.\n",
7405 ret);
fca29703
AV		 7406 }
7407 return ret;
1da177e4
LT		 7408}
7409
7410/**
7411 * qla2x00_module_exit - Module cleanup.
7412 **/
7413static void __exit
7414qla2x00_module_exit(void)
7415{
6a03b4cd 7416 unregister_chrdev(apidev_major, QLA2XXX_APIDEV);
7ee61397 7417 pci_unregister_driver(&qla2xxx_pci_driver);
5433383e 7418 qla2x00_release_firmware();
354d6b21 7419 kmem_cache_destroy(srb_cachep);
2d70c103 7420 qlt_exit();
75c1d48a 7421 kmem_cache_destroy(ctx_cachep);
1da177e4 7422 fc_release_transport(qla2xxx_transport_template);
2c3dfe3f 7423 fc_release_transport(qla2xxx_transport_vport_template);
1da177e4
LT		 7424}
7425
7426module_init(qla2x00_module_init);
7427module_exit(qla2x00_module_exit);
7428
7429MODULE_AUTHOR("QLogic Corporation");
7430MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver");
7431MODULE_LICENSE("GPL");
7432MODULE_VERSION(QLA2XXX_VERSION);
bb8ee499
AV		 7433MODULE_FIRMWARE(FW_FILE_ISP21XX);
7434MODULE_FIRMWARE(FW_FILE_ISP22XX);
7435MODULE_FIRMWARE(FW_FILE_ISP2300);
7436MODULE_FIRMWARE(FW_FILE_ISP2322);
7437MODULE_FIRMWARE(FW_FILE_ISP24XX);
61623fc3 7438MODULE_FIRMWARE(FW_FILE_ISP25XX);
Linux 6.x block layer and io_uring tree(s)