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scsi: qla2xxx: Change the return type of qla2x00_update_ms_fdmi_iocb() into void
[linux-2.6-block.git] / drivers / scsi / qla2xxx / qla_os.c
CommitLineData
1da177e4 1/*
fa90c54f 2 * QLogic Fibre Channel HBA Driver
bd21eaf9 3 * Copyright (c) 2003-2014 QLogic Corporation
1da177e4 4 *
fa90c54f 5 * See LICENSE.qla2xxx for copyright and licensing details.
1da177e4
LT		 6 */
7#include "qla_def.h"
8
9#include <linux/moduleparam.h>
10#include <linux/vmalloc.h>
1da177e4 11#include <linux/delay.h>
39a11240 12#include <linux/kthread.h>
e1e82b6f 13#include <linux/mutex.h>
3420d36c 14#include <linux/kobject.h>
5a0e3ad6 15#include <linux/slab.h>
5601236b 16#include <linux/blk-mq-pci.h>
585def9b
QT		 17#include <linux/refcount.h>
18
1da177e4
LT		 19#include <scsi/scsi_tcq.h>
20#include <scsi/scsicam.h>
21#include <scsi/scsi_transport.h>
22#include <scsi/scsi_transport_fc.h>
23
2d70c103
NB		 24#include "qla_target.h"
25
1da177e4
LT		 26/*
27 * Driver version
28 */
29char qla2x00_version_str[40];
30
6a03b4cd
HZ		 31static int apidev_major;
32
1da177e4
LT		 33/*
34 * SRB allocation cache
35 */
d7459527 36struct kmem_cache *srb_cachep;
1da177e4 37
a9083016
GM		 38/*
39 * CT6 CTX allocation cache
40 */
41static struct kmem_cache *ctx_cachep;
3ce8866c
SK		 42/*
43 * error level for logging
44 */
3f006ac3 45uint ql_errlev = 0x8001;
a9083016 46
fa492630 47static int ql2xenableclass2;
2d70c103
NB		 48module_param(ql2xenableclass2, int, S_IRUGO|S_IRUSR);
49MODULE_PARM_DESC(ql2xenableclass2,
50 "Specify if Class 2 operations are supported from the very "
51 "beginning. Default is 0 - class 2 not supported.");
52
8ae6d9c7 53
1da177e4 54int ql2xlogintimeout = 20;
f2019cb1 55module_param(ql2xlogintimeout, int, S_IRUGO);
1da177e4
LT		 56MODULE_PARM_DESC(ql2xlogintimeout,
57 "Login timeout value in seconds.");
58
a7b61842 59int qlport_down_retry;
f2019cb1 60module_param(qlport_down_retry, int, S_IRUGO);
1da177e4 61MODULE_PARM_DESC(qlport_down_retry,
900d9f98 62 "Maximum number of command retries to a port that returns "
1da177e4
LT		 63 "a PORT-DOWN status.");
64
1da177e4
LT		 65int ql2xplogiabsentdevice;
66module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR);
67MODULE_PARM_DESC(ql2xplogiabsentdevice,
68 "Option to enable PLOGI to devices that are not present after "
900d9f98 69 "a Fabric scan. This is needed for several broken switches. "
0d52e642 70 "Default is 0 - no PLOGI. 1 - perform PLOGI.");
1da177e4 71
c1c7178c 72int ql2xloginretrycount;
f2019cb1 73module_param(ql2xloginretrycount, int, S_IRUGO);
1da177e4
LT		 74MODULE_PARM_DESC(ql2xloginretrycount,
75 "Specify an alternate value for the NVRAM login retry count.");
76
a7a167bf 77int ql2xallocfwdump = 1;
f2019cb1 78module_param(ql2xallocfwdump, int, S_IRUGO);
a7a167bf
AV		 79MODULE_PARM_DESC(ql2xallocfwdump,
80 "Option to enable allocation of memory for a firmware dump "
81 "during HBA initialization. Memory allocation requirements "
82 "vary by ISP type. Default is 1 - allocate memory.");
83
11010fec 84int ql2xextended_error_logging;
27d94035 85module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
a2b3e01d 86module_param_named(logging, ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
11010fec 87MODULE_PARM_DESC(ql2xextended_error_logging,
3ce8866c
SK		 88 "Option to enable extended error logging,\n"
89 "\t\tDefault is 0 - no logging. 0x40000000 - Module Init & Probe.\n"
90 "\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n"
91 "\t\t0x08000000 - IO tracing. 0x04000000 - DPC Thread.\n"
92 "\t\t0x02000000 - Async events. 0x01000000 - Timer routines.\n"
93 "\t\t0x00800000 - User space. 0x00400000 - Task Management.\n"
94 "\t\t0x00200000 - AER/EEH. 0x00100000 - Multi Q.\n"
95 "\t\t0x00080000 - P3P Specific. 0x00040000 - Virtual Port.\n"
96 "\t\t0x00020000 - Buffer Dump. 0x00010000 - Misc.\n"
29f9f90c
CD		 97 "\t\t0x00008000 - Verbose. 0x00004000 - Target.\n"
98 "\t\t0x00002000 - Target Mgmt. 0x00001000 - Target TMF.\n"
3ce8866c 99 "\t\t0x7fffffff - For enabling all logs, can be too many logs.\n"
cfb0919c
CD		 100 "\t\t0x1e400000 - Preferred value for capturing essential "
101 "debug information (equivalent to old "
102 "ql2xextended_error_logging=1).\n"
3ce8866c 103 "\t\tDo LOGICAL OR of the value to enable more than one level");
0181944f 104
a9083016 105int ql2xshiftctondsd = 6;
f2019cb1 106module_param(ql2xshiftctondsd, int, S_IRUGO);
a9083016
GM		 107MODULE_PARM_DESC(ql2xshiftctondsd,
108 "Set to control shifting of command type processing "
109 "based on total number of SG elements.");
110
58e2753c 111int ql2xfdmienable = 1;
de187df8 112module_param(ql2xfdmienable, int, S_IRUGO|S_IWUSR);
a2b3e01d 113module_param_named(fdmi, ql2xfdmienable, int, S_IRUGO|S_IWUSR);
cca5335c 114MODULE_PARM_DESC(ql2xfdmienable,
7794a5af
FW		 115 "Enables FDMI registrations. "
116 "0 - no FDMI. Default is 1 - perform FDMI.");
cca5335c 117
d213a4b7 118#define MAX_Q_DEPTH 64
50280c01 119static int ql2xmaxqdepth = MAX_Q_DEPTH;
df7baa50
AV		 120module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR);
121MODULE_PARM_DESC(ql2xmaxqdepth,
e92e4a8f 122 "Maximum queue depth to set for each LUN. "
d213a4b7 123 "Default is 64.");
df7baa50 124
e84067d7
DG		 125#if (IS_ENABLED(CONFIG_NVME_FC))
126int ql2xenabledif;
127#else
9e522cd8 128int ql2xenabledif = 2;
e84067d7 129#endif
9e522cd8 130module_param(ql2xenabledif, int, S_IRUGO);
bad75002 131MODULE_PARM_DESC(ql2xenabledif,
b97f5d0b
SM		 132 " Enable T10-CRC-DIF:\n"
133 " Default is 2.\n"
134 " 0 -- No DIF Support\n"
135 " 1 -- Enable DIF for all types\n"
136 " 2 -- Enable DIF for all types, except Type 0.\n");
bad75002 137
e84067d7
DG		 138#if (IS_ENABLED(CONFIG_NVME_FC))
139int ql2xnvmeenable = 1;
140#else
141int ql2xnvmeenable;
142#endif
143module_param(ql2xnvmeenable, int, 0644);
144MODULE_PARM_DESC(ql2xnvmeenable,
145 "Enables NVME support. "
146 "0 - no NVMe. Default is Y");
147
8cb2049c 148int ql2xenablehba_err_chk = 2;
bad75002
AE		 149module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR);
150MODULE_PARM_DESC(ql2xenablehba_err_chk,
8cb2049c 151 " Enable T10-CRC-DIF Error isolation by HBA:\n"
b97f5d0b 152 " Default is 2.\n"
8cb2049c
AE		 153 " 0 -- Error isolation disabled\n"
154 " 1 -- Error isolation enabled only for DIX Type 0\n"
155 " 2 -- Error isolation enabled for all Types\n");
bad75002 156
58e2753c 157int ql2xiidmaenable = 1;
f2019cb1 158module_param(ql2xiidmaenable, int, S_IRUGO);
e5896bd5
AV		 159MODULE_PARM_DESC(ql2xiidmaenable,
160 "Enables iIDMA settings "
161 "Default is 1 - perform iIDMA. 0 - no iIDMA.");
162
d7459527
MH		 163int ql2xmqsupport = 1;
164module_param(ql2xmqsupport, int, S_IRUGO);
165MODULE_PARM_DESC(ql2xmqsupport,
166 "Enable on demand multiple queue pairs support "
167 "Default is 1 for supported. "
168 "Set it to 0 to turn off mq qpair support.");
e337d907
AV		 169
170int ql2xfwloadbin;
86e45bf6 171module_param(ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
a2b3e01d 172module_param_named(fwload, ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
e337d907 173MODULE_PARM_DESC(ql2xfwloadbin,
7c3df132
SK		 174 "Option to specify location from which to load ISP firmware:.\n"
175 " 2 -- load firmware via the request_firmware() (hotplug).\n"
e337d907
AV		 176 " interface.\n"
177 " 1 -- load firmware from flash.\n"
178 " 0 -- use default semantics.\n");
179
ae97c91e 180int ql2xetsenable;
f2019cb1 181module_param(ql2xetsenable, int, S_IRUGO);
ae97c91e
AV		 182MODULE_PARM_DESC(ql2xetsenable,
183 "Enables firmware ETS burst."
184 "Default is 0 - skip ETS enablement.");
185
6907869d 186int ql2xdbwr = 1;
86e45bf6 187module_param(ql2xdbwr, int, S_IRUGO|S_IWUSR);
a9083016 188MODULE_PARM_DESC(ql2xdbwr,
08de2844
GM		 189 "Option to specify scheme for request queue posting.\n"
190 " 0 -- Regular doorbell.\n"
191 " 1 -- CAMRAM doorbell (faster).\n");
a9083016 192
f4c496c1 193int ql2xtargetreset = 1;
f2019cb1 194module_param(ql2xtargetreset, int, S_IRUGO);
f4c496c1
GM		 195MODULE_PARM_DESC(ql2xtargetreset,
196 "Enable target reset."
197 "Default is 1 - use hw defaults.");
198
4da26e16 199int ql2xgffidenable;
f2019cb1 200module_param(ql2xgffidenable, int, S_IRUGO);
4da26e16
CD		 201MODULE_PARM_DESC(ql2xgffidenable,
202 "Enables GFF_ID checks of port type. "
203 "Default is 0 - Do not use GFF_ID information.");
a9083016 204
043dc1d7 205int ql2xasynctmfenable = 1;
f2019cb1 206module_param(ql2xasynctmfenable, int, S_IRUGO);
3822263e
MI		 207MODULE_PARM_DESC(ql2xasynctmfenable,
208 "Enables issue of TM IOCBs asynchronously via IOCB mechanism"
84e13c45 209 "Default is 1 - Issue TM IOCBs via mailbox mechanism.");
ed0de87c
GM		 210
211int ql2xdontresethba;
86e45bf6 212module_param(ql2xdontresethba, int, S_IRUGO|S_IWUSR);
ed0de87c 213MODULE_PARM_DESC(ql2xdontresethba,
08de2844
GM		 214 "Option to specify reset behaviour.\n"
215 " 0 (Default) -- Reset on failure.\n"
216 " 1 -- Do not reset on failure.\n");
ed0de87c 217
1abf635d
HR		 218uint64_t ql2xmaxlun = MAX_LUNS;
219module_param(ql2xmaxlun, ullong, S_IRUGO);
82515920
AV		 220MODULE_PARM_DESC(ql2xmaxlun,
221 "Defines the maximum LU number to register with the SCSI "
222 "midlayer. Default is 65535.");
223
08de2844
GM		 224int ql2xmdcapmask = 0x1F;
225module_param(ql2xmdcapmask, int, S_IRUGO);
226MODULE_PARM_DESC(ql2xmdcapmask,
227 "Set the Minidump driver capture mask level. "
6e96fa7b 228 "Default is 0x1F - Can be set to 0x3, 0x7, 0xF, 0x1F, 0x7F.");
08de2844 229
3aadff35 230int ql2xmdenable = 1;
08de2844
GM		 231module_param(ql2xmdenable, int, S_IRUGO);
232MODULE_PARM_DESC(ql2xmdenable,
233 "Enable/disable MiniDump. "
3aadff35
GM		 234 "0 - MiniDump disabled. "
235 "1 (Default) - MiniDump enabled.");
08de2844 236
c1c7178c 237int ql2xexlogins;
b0d6cabd
HM		 238module_param(ql2xexlogins, uint, S_IRUGO|S_IWUSR);
239MODULE_PARM_DESC(ql2xexlogins,
240 "Number of extended Logins. "
241 "0 (Default)- Disabled.");
242
99e1b683
QT		 243int ql2xexchoffld = 1024;
244module_param(ql2xexchoffld, uint, 0644);
2f56a7f1 245MODULE_PARM_DESC(ql2xexchoffld,
99e1b683
QT		 246 "Number of target exchanges.");
247
248int ql2xiniexchg = 1024;
249module_param(ql2xiniexchg, uint, 0644);
250MODULE_PARM_DESC(ql2xiniexchg,
251 "Number of initiator exchanges.");
2f56a7f1 252
c1c7178c 253int ql2xfwholdabts;
f198cafa
HM		 254module_param(ql2xfwholdabts, int, S_IRUGO);
255MODULE_PARM_DESC(ql2xfwholdabts,
256 "Allow FW to hold status IOCB until ABTS rsp received. "
257 "0 (Default) Do not set fw option. "
258 "1 - Set fw option to hold ABTS.");
259
41dc529a
QT		 260int ql2xmvasynctoatio = 1;
261module_param(ql2xmvasynctoatio, int, S_IRUGO|S_IWUSR);
262MODULE_PARM_DESC(ql2xmvasynctoatio,
263 "Move PUREX, ABTS RX and RIDA IOCBs to ATIOQ"
264 "0 (Default). Do not move IOCBs"
265 "1 - Move IOCBs.");
266
e4e3a2ce
QT		 267int ql2xautodetectsfp = 1;
268module_param(ql2xautodetectsfp, int, 0444);
269MODULE_PARM_DESC(ql2xautodetectsfp,
270 "Detect SFP range and set appropriate distance.\n"
271 "1 (Default): Enable\n");
272
e7240af5
HM		 273int ql2xenablemsix = 1;
274module_param(ql2xenablemsix, int, 0444);
275MODULE_PARM_DESC(ql2xenablemsix,
276 "Set to enable MSI or MSI-X interrupt mechanism.\n"
277 " Default is 1, enable MSI-X interrupt mechanism.\n"
278 " 0 -- enable traditional pin-based mechanism.\n"
279 " 1 -- enable MSI-X interrupt mechanism.\n"
280 " 2 -- enable MSI interrupt mechanism.\n");
281
9ecf0b0d
QT		 282int qla2xuseresexchforels;
283module_param(qla2xuseresexchforels, int, 0444);
284MODULE_PARM_DESC(qla2xuseresexchforels,
285 "Reserve 1/2 of emergency exchanges for ELS.\n"
286 " 0 (default): disabled");
287
b3ede8ea 288static int ql2xprotmask;
7855d2ba
MP		 289module_param(ql2xprotmask, int, 0644);
290MODULE_PARM_DESC(ql2xprotmask,
291 "Override DIF/DIX protection capabilities mask\n"
292 "Default is 0 which sets protection mask based on "
293 "capabilities reported by HBA firmware.\n");
294
b3ede8ea 295static int ql2xprotguard;
7855d2ba
MP		 296module_param(ql2xprotguard, int, 0644);
297MODULE_PARM_DESC(ql2xprotguard, "Override choice of DIX checksum\n"
298 " 0 -- Let HBA firmware decide\n"
299 " 1 -- Force T10 CRC\n"
300 " 2 -- Force IP checksum\n");
301
50b81275
GM		 302int ql2xdifbundlinginternalbuffers;
303module_param(ql2xdifbundlinginternalbuffers, int, 0644);
304MODULE_PARM_DESC(ql2xdifbundlinginternalbuffers,
305 "Force using internal buffers for DIF information\n"
306 "0 (Default). Based on check.\n"
307 "1 Force using internal buffers\n");
308
1a2fbf18 309static void qla2x00_clear_drv_active(struct qla_hw_data *);
3491255e 310static void qla2x00_free_device(scsi_qla_host_t *);
5601236b 311static int qla2xxx_map_queues(struct Scsi_Host *shost);
e84067d7 312static void qla2x00_destroy_deferred_work(struct qla_hw_data *);
ce7e4af7 313
45235022 314
1da177e4 315static struct scsi_transport_template *qla2xxx_transport_template = NULL;
2c3dfe3f 316struct scsi_transport_template *qla2xxx_transport_vport_template = NULL;
1da177e4 317
1da177e4
LT		 318/* TODO Convert to inlines
319 *
320 * Timer routines
321 */
1da177e4 322
2c3dfe3f 323__inline__ void
8e5f4ba0 324qla2x00_start_timer(scsi_qla_host_t *vha, unsigned long interval)
1da177e4 325{
8e5f4ba0 326 timer_setup(&vha->timer, qla2x00_timer, 0);
e315cd28 327 vha->timer.expires = jiffies + interval * HZ;
e315cd28
AC		 328 add_timer(&vha->timer);
329 vha->timer_active = 1;
1da177e4
LT		 330}
331
332static inline void
e315cd28 333qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval)
1da177e4 334{
a9083016 335 /* Currently used for 82XX only. */
7c3df132
SK		 336 if (vha->device_flags & DFLG_DEV_FAILED) {
337 ql_dbg(ql_dbg_timer, vha, 0x600d,
338 "Device in a failed state, returning.\n");
a9083016 339 return;
7c3df132 340 }
a9083016 341
e315cd28 342 mod_timer(&vha->timer, jiffies + interval * HZ);
1da177e4
LT		 343}
344
a824ebb3 345static __inline__ void
e315cd28 346qla2x00_stop_timer(scsi_qla_host_t *vha)
1da177e4 347{
e315cd28
AC		 348 del_timer_sync(&vha->timer);
349 vha->timer_active = 0;
1da177e4
LT		 350}
351
1da177e4
LT		 352static int qla2x00_do_dpc(void *data);
353
354static void qla2x00_rst_aen(scsi_qla_host_t *);
355
73208dfd
AC		 356static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t,
357 struct req_que **, struct rsp_que **);
e30d1756 358static void qla2x00_free_fw_dump(struct qla_hw_data *);
e315cd28 359static void qla2x00_mem_free(struct qla_hw_data *);
d7459527
MH		 360int qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd,
361 struct qla_qpair *qpair);
1da177e4 362
1da177e4 363/* -------------------------------------------------------------------------- */
8abfa9e2
QT		 364static void qla_init_base_qpair(struct scsi_qla_host *vha, struct req_que *req,
365 struct rsp_que *rsp)
366{
367 struct qla_hw_data *ha = vha->hw;
bd432bb5 368
8abfa9e2
QT		 369 rsp->qpair = ha->base_qpair;
370 rsp->req = req;
0691094f 371 ha->base_qpair->hw = ha;
8abfa9e2
QT		 372 ha->base_qpair->req = req;
373 ha->base_qpair->rsp = rsp;
374 ha->base_qpair->vha = vha;
375 ha->base_qpair->qp_lock_ptr = &ha->hardware_lock;
376 ha->base_qpair->use_shadow_reg = IS_SHADOW_REG_CAPABLE(ha) ? 1 : 0;
377 ha->base_qpair->msix = &ha->msix_entries[QLA_MSIX_RSP_Q];
6a629468 378 ha->base_qpair->srb_mempool = ha->srb_mempool;
8abfa9e2
QT		 379 INIT_LIST_HEAD(&ha->base_qpair->hints_list);
380 ha->base_qpair->enable_class_2 = ql2xenableclass2;
381 /* init qpair to this cpu. Will adjust at run time. */
86531887 382 qla_cpu_update(rsp->qpair, raw_smp_processor_id());
8abfa9e2
QT		 383 ha->base_qpair->pdev = ha->pdev;
384
ecc89f25 385 if (IS_QLA27XX(ha) || IS_QLA83XX(ha) || IS_QLA28XX(ha))
8abfa9e2
QT		 386 ha->base_qpair->reqq_start_iocbs = qla_83xx_start_iocbs;
387}
388
9a347ff4
CD		 389static int qla2x00_alloc_queues(struct qla_hw_data *ha, struct req_que *req,
390 struct rsp_que *rsp)
73208dfd 391{
7c3df132 392 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
bd432bb5 393
6396bb22 394 ha->req_q_map = kcalloc(ha->max_req_queues, sizeof(struct req_que *),
73208dfd
AC		 395 GFP_KERNEL);
396 if (!ha->req_q_map) {
7c3df132
SK		 397 ql_log(ql_log_fatal, vha, 0x003b,
398 "Unable to allocate memory for request queue ptrs.\n");
73208dfd
AC		 399 goto fail_req_map;
400 }
401
6396bb22 402 ha->rsp_q_map = kcalloc(ha->max_rsp_queues, sizeof(struct rsp_que *),
73208dfd
AC		 403 GFP_KERNEL);
404 if (!ha->rsp_q_map) {
7c3df132
SK		 405 ql_log(ql_log_fatal, vha, 0x003c,
406 "Unable to allocate memory for response queue ptrs.\n");
73208dfd
AC		 407 goto fail_rsp_map;
408 }
d7459527 409
e326d22a
QT		 410 ha->base_qpair = kzalloc(sizeof(struct qla_qpair), GFP_KERNEL);
411 if (ha->base_qpair == NULL) {
412 ql_log(ql_log_warn, vha, 0x00e0,
413 "Failed to allocate base queue pair memory.\n");
414 goto fail_base_qpair;
415 }
416
8abfa9e2 417 qla_init_base_qpair(vha, req, rsp);
e326d22a 418
c38d1baf 419 if ((ql2xmqsupport || ql2xnvmeenable) && ha->max_qpairs) {
d7459527
MH		 420 ha->queue_pair_map = kcalloc(ha->max_qpairs, sizeof(struct qla_qpair *),
421 GFP_KERNEL);
422 if (!ha->queue_pair_map) {
423 ql_log(ql_log_fatal, vha, 0x0180,
424 "Unable to allocate memory for queue pair ptrs.\n");
425 goto fail_qpair_map;
426 }
d7459527
MH		 427 }
428
9a347ff4
CD		 429 /*
430 * Make sure we record at least the request and response queue zero in
431 * case we need to free them if part of the probe fails.
432 */
433 ha->rsp_q_map[0] = rsp;
434 ha->req_q_map[0] = req;
73208dfd
AC		 435 set_bit(0, ha->rsp_qid_map);
436 set_bit(0, ha->req_qid_map);
6a2cf8d3 437 return 0;
73208dfd 438
d7459527 439fail_qpair_map:
82de802a
QT		 440 kfree(ha->base_qpair);
441 ha->base_qpair = NULL;
442fail_base_qpair:
d7459527
MH		 443 kfree(ha->rsp_q_map);
444 ha->rsp_q_map = NULL;
73208dfd
AC		 445fail_rsp_map:
446 kfree(ha->req_q_map);
447 ha->req_q_map = NULL;
448fail_req_map:
449 return -ENOMEM;
450}
451
2afa19a9 452static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req)
73208dfd 453{
8ae6d9c7
GM		 454 if (IS_QLAFX00(ha)) {
455 if (req && req->ring_fx00)
456 dma_free_coherent(&ha->pdev->dev,
457 (req->length_fx00 + 1) * sizeof(request_t),
458 req->ring_fx00, req->dma_fx00);
459 } else if (req && req->ring)
73208dfd
AC		 460 dma_free_coherent(&ha->pdev->dev,
461 (req->length + 1) * sizeof(request_t),
462 req->ring, req->dma);
463
6d634067 464 if (req)
8d93f550 465 kfree(req->outstanding_cmds);
6d634067
BK		 466
467 kfree(req);
73208dfd
AC		 468}
469
2afa19a9
AC		 470static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp)
471{
8ae6d9c7 472 if (IS_QLAFX00(ha)) {
3f6c9be2 473 if (rsp && rsp->ring_fx00)
8ae6d9c7
GM		 474 dma_free_coherent(&ha->pdev->dev,
475 (rsp->length_fx00 + 1) * sizeof(request_t),
476 rsp->ring_fx00, rsp->dma_fx00);
477 } else if (rsp && rsp->ring) {
2afa19a9
AC		 478 dma_free_coherent(&ha->pdev->dev,
479 (rsp->length + 1) * sizeof(response_t),
480 rsp->ring, rsp->dma);
8ae6d9c7 481 }
6d634067 482 kfree(rsp);
2afa19a9
AC		 483}
484
73208dfd
AC		 485static void qla2x00_free_queues(struct qla_hw_data *ha)
486{
487 struct req_que *req;
488 struct rsp_que *rsp;
489 int cnt;
093df737 490 unsigned long flags;
73208dfd 491
82de802a
QT		 492 if (ha->queue_pair_map) {
493 kfree(ha->queue_pair_map);
494 ha->queue_pair_map = NULL;
495 }
496 if (ha->base_qpair) {
497 kfree(ha->base_qpair);
498 ha->base_qpair = NULL;
499 }
500
093df737 501 spin_lock_irqsave(&ha->hardware_lock, flags);
2afa19a9 502 for (cnt = 0; cnt < ha->max_req_queues; cnt++) {
cb43285f
QT		 503 if (!test_bit(cnt, ha->req_qid_map))
504 continue;
505
73208dfd 506 req = ha->req_q_map[cnt];
093df737
QT		 507 clear_bit(cnt, ha->req_qid_map);
508 ha->req_q_map[cnt] = NULL;
509
510 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2afa19a9 511 qla2x00_free_req_que(ha, req);
093df737 512 spin_lock_irqsave(&ha->hardware_lock, flags);
73208dfd 513 }
093df737
QT		 514 spin_unlock_irqrestore(&ha->hardware_lock, flags);
515
73208dfd
AC		 516 kfree(ha->req_q_map);
517 ha->req_q_map = NULL;
2afa19a9 518
093df737
QT		 519
520 spin_lock_irqsave(&ha->hardware_lock, flags);
2afa19a9 521 for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) {
cb43285f
QT		 522 if (!test_bit(cnt, ha->rsp_qid_map))
523 continue;
524
2afa19a9 525 rsp = ha->rsp_q_map[cnt];
c3c42394 526 clear_bit(cnt, ha->rsp_qid_map);
093df737
QT		 527 ha->rsp_q_map[cnt] = NULL;
528 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2afa19a9 529 qla2x00_free_rsp_que(ha, rsp);
093df737 530 spin_lock_irqsave(&ha->hardware_lock, flags);
2afa19a9 531 }
093df737
QT		 532 spin_unlock_irqrestore(&ha->hardware_lock, flags);
533
2afa19a9
AC		 534 kfree(ha->rsp_q_map);
535 ha->rsp_q_map = NULL;
73208dfd
AC		 536}
537
1da177e4 538static char *
e315cd28 539qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str)
1da177e4 540{
e315cd28 541 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 542 static char *pci_bus_modes[] = {
543 "33", "66", "100", "133",
544 };
545 uint16_t pci_bus;
546
547 strcpy(str, "PCI");
548 pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9;
549 if (pci_bus) {
550 strcat(str, "-X (");
551 strcat(str, pci_bus_modes[pci_bus]);
552 } else {
553 pci_bus = (ha->pci_attr & BIT_8) >> 8;
554 strcat(str, " (");
555 strcat(str, pci_bus_modes[pci_bus]);
556 }
557 strcat(str, " MHz)");
558
559 return (str);
560}
561
fca29703 562static char *
e315cd28 563qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str)
fca29703
AV		 564{
565 static char *pci_bus_modes[] = { "33", "66", "100", "133", };
e315cd28 566 struct qla_hw_data *ha = vha->hw;
fca29703 567 uint32_t pci_bus;
fca29703 568
62a276f8 569 if (pci_is_pcie(ha->pdev)) {
fca29703 570 char lwstr[6];
62a276f8 571 uint32_t lstat, lspeed, lwidth;
fca29703 572
62a276f8
BH		 573 pcie_capability_read_dword(ha->pdev, PCI_EXP_LNKCAP, &lstat);
574 lspeed = lstat & PCI_EXP_LNKCAP_SLS;
575 lwidth = (lstat & PCI_EXP_LNKCAP_MLW) >> 4;
fca29703
AV		 576
577 strcpy(str, "PCIe (");
49300af7
SK		 578 switch (lspeed) {
579 case 1:
c87a0d8c 580 strcat(str, "2.5GT/s ");
49300af7
SK		 581 break;
582 case 2:
c87a0d8c 583 strcat(str, "5.0GT/s ");
49300af7
SK		 584 break;
585 case 3:
586 strcat(str, "8.0GT/s ");
587 break;
588 default:
fca29703 589 strcat(str, "<unknown> ");
49300af7
SK		 590 break;
591 }
fca29703
AV		 592 snprintf(lwstr, sizeof(lwstr), "x%d)", lwidth);
593 strcat(str, lwstr);
594
595 return str;
596 }
597
598 strcpy(str, "PCI");
599 pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8;
600 if (pci_bus == 0 || pci_bus == 8) {
601 strcat(str, " (");
602 strcat(str, pci_bus_modes[pci_bus >> 3]);
603 } else {
604 strcat(str, "-X ");
605 if (pci_bus & BIT_2)
606 strcat(str, "Mode 2");
607 else
608 strcat(str, "Mode 1");
609 strcat(str, " (");
610 strcat(str, pci_bus_modes[pci_bus & ~BIT_2]);
611 }
612 strcat(str, " MHz)");
613
614 return str;
615}
616
e5f82ab8 617static char *
df57caba 618qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
1da177e4
LT		 619{
620 char un_str[10];
e315cd28 621 struct qla_hw_data *ha = vha->hw;
fa2a1ce5 622
df57caba
HM		 623 snprintf(str, size, "%d.%02d.%02d ", ha->fw_major_version,
624 ha->fw_minor_version, ha->fw_subminor_version);
1da177e4
LT		 625
626 if (ha->fw_attributes & BIT_9) {
627 strcat(str, "FLX");
628 return (str);
629 }
630
631 switch (ha->fw_attributes & 0xFF) {
632 case 0x7:
633 strcat(str, "EF");
634 break;
635 case 0x17:
636 strcat(str, "TP");
637 break;
638 case 0x37:
639 strcat(str, "IP");
640 break;
641 case 0x77:
642 strcat(str, "VI");
643 break;
644 default:
645 sprintf(un_str, "(%x)", ha->fw_attributes);
646 strcat(str, un_str);
647 break;
648 }
649 if (ha->fw_attributes & 0x100)
650 strcat(str, "X");
651
652 return (str);
653}
654
e5f82ab8 655static char *
df57caba 656qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
fca29703 657{
e315cd28 658 struct qla_hw_data *ha = vha->hw;
f0883ac6 659
df57caba 660 snprintf(str, size, "%d.%02d.%02d (%x)", ha->fw_major_version,
3a03eb79 661 ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes);
fca29703 662 return str;
fca29703
AV		 663}
664
9ba56b95 665void
25ff6af1 666qla2x00_sp_free_dma(void *ptr)
fca29703 667{
25ff6af1
JC		 668 srb_t *sp = ptr;
669 struct qla_hw_data *ha = sp->vha->hw;
9ba56b95 670 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
9ba56b95 671 void *ctx = GET_CMD_CTX_SP(sp);
fca29703 672
9ba56b95
GM		 673 if (sp->flags & SRB_DMA_VALID) {
674 scsi_dma_unmap(cmd);
675 sp->flags &= ~SRB_DMA_VALID;
7c3df132 676 }
fca29703 677
9ba56b95
GM		 678 if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
679 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
680 scsi_prot_sg_count(cmd), cmd->sc_data_direction);
681 sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
682 }
683
d5ff0eed 684 if (!ctx)
711a08d7 685 return;
d5ff0eed 686
9ba56b95
GM		 687 if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
688 /* List assured to be having elements */
d5ff0eed 689 qla2x00_clean_dsd_pool(ha, ctx);
9ba56b95
GM		 690 sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
691 }
692
693 if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
d5ff0eed
JC		 694 struct crc_context *ctx0 = ctx;
695
696 dma_pool_free(ha->dl_dma_pool, ctx0, ctx0->crc_ctx_dma);
9ba56b95
GM		 697 sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
698 }
699
700 if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
d5ff0eed 701 struct ct6_dsd *ctx1 = ctx;
fca29703 702
9ba56b95 703 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd,
d5ff0eed 704 ctx1->fcp_cmnd_dma);
9ba56b95
GM		 705 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list);
706 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt;
707 ha->gbl_dsd_avail += ctx1->dsd_use_cnt;
708 mempool_free(ctx1, ha->ctx_mempool);
9ba56b95 709 }
9ba56b95
GM		 710}
711
d7459527 712void
25ff6af1 713qla2x00_sp_compl(void *ptr, int res)
9ba56b95 714{
25ff6af1 715 srb_t *sp = ptr;
9ba56b95 716 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
219d27d7 717 struct completion *comp = sp->comp;
9ba56b95 718
db4bf822 719 if (WARN_ON_ONCE(atomic_read(&sp->ref_count) == 0))
9ba56b95 720 return;
219d27d7
BVA		 721
722 atomic_dec(&sp->ref_count);
9ba56b95 723
f3caa990 724 sp->free(sp);
740e2935 725 cmd->result = res;
711a08d7 726 CMD_SP(cmd) = NULL;
9ba56b95 727 cmd->scsi_done(cmd);
219d27d7
BVA		 728 if (comp)
729 complete(comp);
711a08d7 730 qla2x00_rel_sp(sp);
fca29703
AV		 731}
732
d7459527 733void
25ff6af1 734qla2xxx_qpair_sp_free_dma(void *ptr)
d7459527
MH		 735{
736 srb_t *sp = (srb_t *)ptr;
737 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
738 struct qla_hw_data *ha = sp->fcport->vha->hw;
739 void *ctx = GET_CMD_CTX_SP(sp);
740
741 if (sp->flags & SRB_DMA_VALID) {
742 scsi_dma_unmap(cmd);
743 sp->flags &= ~SRB_DMA_VALID;
744 }
745
746 if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
747 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
748 scsi_prot_sg_count(cmd), cmd->sc_data_direction);
749 sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
750 }
751
d5ff0eed 752 if (!ctx)
711a08d7 753 return;
d5ff0eed 754
d7459527
MH		 755 if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
756 /* List assured to be having elements */
d5ff0eed 757 qla2x00_clean_dsd_pool(ha, ctx);
d7459527
MH		 758 sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
759 }
760
50b81275 761 if (sp->flags & SRB_DIF_BUNDL_DMA_VALID) {
d8f945bf 762 struct crc_context *difctx = ctx;
50b81275
GM		 763 struct dsd_dma *dif_dsd, *nxt_dsd;
764
765 list_for_each_entry_safe(dif_dsd, nxt_dsd,
766 &difctx->ldif_dma_hndl_list, list) {
767 list_del(&dif_dsd->list);
768 dma_pool_free(ha->dif_bundl_pool, dif_dsd->dsd_addr,
769 dif_dsd->dsd_list_dma);
770 kfree(dif_dsd);
771 difctx->no_dif_bundl--;
772 }
773
774 list_for_each_entry_safe(dif_dsd, nxt_dsd,
775 &difctx->ldif_dsd_list, list) {
776 list_del(&dif_dsd->list);
777 dma_pool_free(ha->dl_dma_pool, dif_dsd->dsd_addr,
778 dif_dsd->dsd_list_dma);
779 kfree(dif_dsd);
780 difctx->no_ldif_dsd--;
781 }
782
783 if (difctx->no_ldif_dsd) {
784 ql_dbg(ql_dbg_tgt+ql_dbg_verbose, sp->vha, 0xe022,
785 "%s: difctx->no_ldif_dsd=%x\n",
786 __func__, difctx->no_ldif_dsd);
787 }
788
789 if (difctx->no_dif_bundl) {
790 ql_dbg(ql_dbg_tgt+ql_dbg_verbose, sp->vha, 0xe022,
791 "%s: difctx->no_dif_bundl=%x\n",
792 __func__, difctx->no_dif_bundl);
793 }
794 sp->flags &= ~SRB_DIF_BUNDL_DMA_VALID;
d7459527 795 }
d8f945bf
BVA		 796
797 if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
798 struct ct6_dsd *ctx1 = ctx;
799
800 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd,
801 ctx1->fcp_cmnd_dma);
802 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list);
803 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt;
804 ha->gbl_dsd_avail += ctx1->dsd_use_cnt;
805 mempool_free(ctx1, ha->ctx_mempool);
806 sp->flags &= ~SRB_FCP_CMND_DMA_VALID;
807 }
808
809 if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
810 struct crc_context *ctx0 = ctx;
811
812 dma_pool_free(ha->dl_dma_pool, ctx, ctx0->crc_ctx_dma);
813 sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
814 }
d7459527
MH		 815}
816
817void
25ff6af1 818qla2xxx_qpair_sp_compl(void *ptr, int res)
d7459527 819{
25ff6af1 820 srb_t *sp = ptr;
d7459527 821 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
219d27d7 822 struct completion *comp = sp->comp;
d7459527 823
db4bf822 824 if (WARN_ON_ONCE(atomic_read(&sp->ref_count) == 0))
d7459527 825 return;
219d27d7
BVA		 826
827 atomic_dec(&sp->ref_count);
d7459527 828
f3caa990 829 sp->free(sp);
711a08d7
GM		 830 cmd->result = res;
831 CMD_SP(cmd) = NULL;
d7459527 832 cmd->scsi_done(cmd);
219d27d7
BVA		 833 if (comp)
834 complete(comp);
711a08d7 835 qla2xxx_rel_qpair_sp(sp->qpair, sp);
d7459527
MH		 836}
837
1da177e4 838static int
f5e3e40b 839qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
fca29703 840{
134ae078 841 scsi_qla_host_t *vha = shost_priv(host);
fca29703 842 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
19a7b4ae 843 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
e315cd28
AC		 844 struct qla_hw_data *ha = vha->hw;
845 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
fca29703
AV		 846 srb_t *sp;
847 int rval;
5601236b
MH		 848 struct qla_qpair *qpair = NULL;
849 uint32_t tag;
850 uint16_t hwq;
fca29703 851
2dbb02fd
BVA		 852 if (unlikely(test_bit(UNLOADING, &base_vha->dpc_flags)) ||
853 WARN_ON_ONCE(!rport)) {
04dfaa53
MFO		 854 cmd->result = DID_NO_CONNECT << 16;
855 goto qc24_fail_command;
856 }
857
5601236b 858 if (ha->mqenable) {
f664a3cc
JA		 859 tag = blk_mq_unique_tag(cmd->request);
860 hwq = blk_mq_unique_tag_to_hwq(tag);
861 qpair = ha->queue_pair_map[hwq];
5601236b
MH		 862
863 if (qpair)
864 return qla2xxx_mqueuecommand(host, cmd, qpair);
d7459527
MH		 865 }
866
85880801 867 if (ha->flags.eeh_busy) {
7c3df132 868 if (ha->flags.pci_channel_io_perm_failure) {
5f28d2d7 869 ql_dbg(ql_dbg_aer, vha, 0x9010,
7c3df132
SK		 870 "PCI Channel IO permanent failure, exiting "
871 "cmd=%p.\n", cmd);
b9b12f73 872 cmd->result = DID_NO_CONNECT << 16;
7c3df132 873 } else {
5f28d2d7 874 ql_dbg(ql_dbg_aer, vha, 0x9011,
7c3df132 875 "EEH_Busy, Requeuing the cmd=%p.\n", cmd);
85880801 876 cmd->result = DID_REQUEUE << 16;
7c3df132 877 }
14e660e6
SJ		 878 goto qc24_fail_command;
879 }
880
19a7b4ae
JSEC		 881 rval = fc_remote_port_chkready(rport);
882 if (rval) {
883 cmd->result = rval;
5f28d2d7 884 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3003,
7c3df132
SK		 885 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
886 cmd, rval);
fca29703
AV		 887 goto qc24_fail_command;
888 }
889
bad75002
AE		 890 if (!vha->flags.difdix_supported &&
891 scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) {
7c3df132
SK		 892 ql_dbg(ql_dbg_io, vha, 0x3004,
893 "DIF Cap not reg, fail DIF capable cmd's:%p.\n",
894 cmd);
bad75002
AE		 895 cmd->result = DID_NO_CONNECT << 16;
896 goto qc24_fail_command;
897 }
aa651be8
CD		 898
899 if (!fcport) {
900 cmd->result = DID_NO_CONNECT << 16;
901 goto qc24_fail_command;
902 }
903
fca29703
AV		 904 if (atomic_read(&fcport->state) != FCS_ONLINE) {
905 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
38170fa8 906 atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
7c3df132
SK		 907 ql_dbg(ql_dbg_io, vha, 0x3005,
908 "Returning DNC, fcport_state=%d loop_state=%d.\n",
909 atomic_read(&fcport->state),
910 atomic_read(&base_vha->loop_state));
fca29703
AV		 911 cmd->result = DID_NO_CONNECT << 16;
912 goto qc24_fail_command;
913 }
7b594131 914 goto qc24_target_busy;
fca29703
AV		 915 }
916
e05fe292
CD		 917 /*
918 * Return target busy if we've received a non-zero retry_delay_timer
919 * in a FCP_RSP.
920 */
975f7d46
BP		 921 if (fcport->retry_delay_timestamp == 0) {
922 /* retry delay not set */
923 } else if (time_after(jiffies, fcport->retry_delay_timestamp))
e05fe292
CD		 924 fcport->retry_delay_timestamp = 0;
925 else
926 goto qc24_target_busy;
927
b00ee7d7 928 sp = qla2x00_get_sp(vha, fcport, GFP_ATOMIC);
50280c01 929 if (!sp)
f5e3e40b 930 goto qc24_host_busy;
fca29703 931
9ba56b95
GM		 932 sp->u.scmd.cmd = cmd;
933 sp->type = SRB_SCSI_CMD;
934 atomic_set(&sp->ref_count, 1);
935 CMD_SP(cmd) = (void *)sp;
936 sp->free = qla2x00_sp_free_dma;
937 sp->done = qla2x00_sp_compl;
938
e315cd28 939 rval = ha->isp_ops->start_scsi(sp);
7c3df132 940 if (rval != QLA_SUCCESS) {
53016ed3 941 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3013,
7c3df132 942 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
fca29703 943 goto qc24_host_busy_free_sp;
7c3df132 944 }
fca29703 945
fca29703
AV		 946 return 0;
947
948qc24_host_busy_free_sp:
f3caa990 949 sp->free(sp);
fca29703 950
f5e3e40b 951qc24_host_busy:
fca29703
AV		 952 return SCSI_MLQUEUE_HOST_BUSY;
953
7b594131
MC		 954qc24_target_busy:
955 return SCSI_MLQUEUE_TARGET_BUSY;
956
fca29703 957qc24_fail_command:
f5e3e40b 958 cmd->scsi_done(cmd);
fca29703
AV		 959
960 return 0;
961}
962
d7459527
MH		 963/* For MQ supported I/O */
964int
965qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd,
966 struct qla_qpair *qpair)
967{
968 scsi_qla_host_t *vha = shost_priv(host);
969 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
970 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
971 struct qla_hw_data *ha = vha->hw;
972 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
973 srb_t *sp;
974 int rval;
975
2dbb02fd 976 rval = rport ? fc_remote_port_chkready(rport) : FC_PORTSTATE_OFFLINE;
d7459527
MH		 977 if (rval) {
978 cmd->result = rval;
979 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3076,
980 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
981 cmd, rval);
982 goto qc24_fail_command;
983 }
984
985 if (!fcport) {
986 cmd->result = DID_NO_CONNECT << 16;
987 goto qc24_fail_command;
988 }
989
990 if (atomic_read(&fcport->state) != FCS_ONLINE) {
991 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
992 atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
993 ql_dbg(ql_dbg_io, vha, 0x3077,
994 "Returning DNC, fcport_state=%d loop_state=%d.\n",
995 atomic_read(&fcport->state),
996 atomic_read(&base_vha->loop_state));
997 cmd->result = DID_NO_CONNECT << 16;
998 goto qc24_fail_command;
999 }
1000 goto qc24_target_busy;
1001 }
1002
1003 /*
1004 * Return target busy if we've received a non-zero retry_delay_timer
1005 * in a FCP_RSP.
1006 */
1007 if (fcport->retry_delay_timestamp == 0) {
1008 /* retry delay not set */
1009 } else if (time_after(jiffies, fcport->retry_delay_timestamp))
1010 fcport->retry_delay_timestamp = 0;
1011 else
1012 goto qc24_target_busy;
1013
6a629468 1014 sp = qla2xxx_get_qpair_sp(vha, qpair, fcport, GFP_ATOMIC);
d7459527
MH		 1015 if (!sp)
1016 goto qc24_host_busy;
1017
1018 sp->u.scmd.cmd = cmd;
1019 sp->type = SRB_SCSI_CMD;
1020 atomic_set(&sp->ref_count, 1);
1021 CMD_SP(cmd) = (void *)sp;
1022 sp->free = qla2xxx_qpair_sp_free_dma;
1023 sp->done = qla2xxx_qpair_sp_compl;
1024 sp->qpair = qpair;
1025
1026 rval = ha->isp_ops->start_scsi_mq(sp);
1027 if (rval != QLA_SUCCESS) {
1028 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3078,
1029 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
1030 if (rval == QLA_INTERFACE_ERROR)
1031 goto qc24_fail_command;
1032 goto qc24_host_busy_free_sp;
1033 }
1034
1035 return 0;
1036
1037qc24_host_busy_free_sp:
f3caa990 1038 sp->free(sp);
d7459527
MH		 1039
1040qc24_host_busy:
1041 return SCSI_MLQUEUE_HOST_BUSY;
1042
1043qc24_target_busy:
1044 return SCSI_MLQUEUE_TARGET_BUSY;
1045
1046qc24_fail_command:
1047 cmd->scsi_done(cmd);
1048
1049 return 0;
1050}
1051
1da177e4
LT		 1052/*
1053 * qla2x00_eh_wait_on_command
1054 * Waits for the command to be returned by the Firmware for some
1055 * max time.
1056 *
1057 * Input:
1da177e4 1058 * cmd = Scsi Command to wait on.
1da177e4
LT		 1059 *
1060 * Return:
1061 * Not Found : 0
1062 * Found : 1
1063 */
1064static int
e315cd28 1065qla2x00_eh_wait_on_command(struct scsi_cmnd *cmd)
1da177e4 1066{
fe74c71f 1067#define ABORT_POLLING_PERIOD 1000
478c3b03 1068#define ABORT_WAIT_ITER ((2 * 1000) / (ABORT_POLLING_PERIOD))
f4f051eb 1069 unsigned long wait_iter = ABORT_WAIT_ITER;
85880801
AV		 1070 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1071 struct qla_hw_data *ha = vha->hw;
f4f051eb 1072 int ret = QLA_SUCCESS;
1da177e4 1073
85880801 1074 if (unlikely(pci_channel_offline(ha->pdev)) || ha->flags.eeh_busy) {
7c3df132
SK		 1075 ql_dbg(ql_dbg_taskm, vha, 0x8005,
1076 "Return:eh_wait.\n");
85880801
AV		 1077 return ret;
1078 }
1079
d970432c 1080 while (CMD_SP(cmd) && wait_iter--) {
fe74c71f 1081 msleep(ABORT_POLLING_PERIOD);
f4f051eb 1082 }
1083 if (CMD_SP(cmd))
1084 ret = QLA_FUNCTION_FAILED;
1da177e4 1085
f4f051eb 1086 return ret;
1da177e4
LT		 1087}
1088
1089/*
1090 * qla2x00_wait_for_hba_online
fa2a1ce5 1091 * Wait till the HBA is online after going through
1da177e4
LT		 1092 * <= MAX_RETRIES_OF_ISP_ABORT or
1093 * finally HBA is disabled ie marked offline
1094 *
1095 * Input:
1096 * ha - pointer to host adapter structure
fa2a1ce5
AV		 1097 *
1098 * Note:
1da177e4
LT		 1099 * Does context switching-Release SPIN_LOCK
1100 * (if any) before calling this routine.
1101 *
1102 * Return:
1103 * Success (Adapter is online) : 0
1104 * Failed (Adapter is offline/disabled) : 1
1105 */
854165f4 1106int
e315cd28 1107qla2x00_wait_for_hba_online(scsi_qla_host_t *vha)
1da177e4 1108{
fca29703
AV		 1109 int return_status;
1110 unsigned long wait_online;
e315cd28
AC		 1111 struct qla_hw_data *ha = vha->hw;
1112 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4 1113
fa2a1ce5 1114 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ);
e315cd28
AC		 1115 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
1116 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
1117 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
1118 ha->dpc_active) && time_before(jiffies, wait_online)) {
1da177e4
LT		 1119
1120 msleep(1000);
1121 }
e315cd28 1122 if (base_vha->flags.online)
fa2a1ce5 1123 return_status = QLA_SUCCESS;
1da177e4
LT		 1124 else
1125 return_status = QLA_FUNCTION_FAILED;
1126
1da177e4
LT		 1127 return (return_status);
1128}
1129
726b8548
QT		 1130static inline int test_fcport_count(scsi_qla_host_t *vha)
1131{
1132 struct qla_hw_data *ha = vha->hw;
1133 unsigned long flags;
1134 int res;
1135
1136 spin_lock_irqsave(&ha->tgt.sess_lock, flags);
83548fe2
QT		 1137 ql_dbg(ql_dbg_init, vha, 0x00ec,
1138 "tgt %p, fcport_count=%d\n",
1139 vha, vha->fcport_count);
726b8548
QT		 1140 res = (vha->fcport_count == 0);
1141 spin_unlock_irqrestore(&ha->tgt.sess_lock, flags);
1142
1143 return res;
1144}
1145
1146/*
1147 * qla2x00_wait_for_sess_deletion can only be called from remove_one.
1148 * it has dependency on UNLOADING flag to stop device discovery
1149 */
efa93f48 1150void
726b8548
QT		 1151qla2x00_wait_for_sess_deletion(scsi_qla_host_t *vha)
1152{
1153 qla2x00_mark_all_devices_lost(vha, 0);
1154
b85e0957 1155 wait_event_timeout(vha->fcport_waitQ, test_fcport_count(vha), 10*HZ);
726b8548
QT		 1156}
1157
86fbee86 1158/*
638a1a01
SC		 1159 * qla2x00_wait_for_hba_ready
1160 * Wait till the HBA is ready before doing driver unload
86fbee86
LC		 1161 *
1162 * Input:
1163 * ha - pointer to host adapter structure
1164 *
1165 * Note:
1166 * Does context switching-Release SPIN_LOCK
1167 * (if any) before calling this routine.
1168 *
86fbee86 1169 */
638a1a01
SC		 1170static void
1171qla2x00_wait_for_hba_ready(scsi_qla_host_t *vha)
86fbee86 1172{
86fbee86 1173 struct qla_hw_data *ha = vha->hw;
783e0dc4 1174 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
86fbee86 1175
1d483901
DC		 1176 while ((qla2x00_reset_active(vha) || ha->dpc_active ||
1177 ha->flags.mbox_busy) ||
1178 test_bit(FX00_RESET_RECOVERY, &vha->dpc_flags) ||
1179 test_bit(FX00_TARGET_SCAN, &vha->dpc_flags)) {
1180 if (test_bit(UNLOADING, &base_vha->dpc_flags))
1181 break;
86fbee86 1182 msleep(1000);
783e0dc4 1183 }
86fbee86
LC		 1184}
1185
2533cf67
LC		 1186int
1187qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha)
1188{
1189 int return_status;
1190 unsigned long wait_reset;
1191 struct qla_hw_data *ha = vha->hw;
1192 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1193
1194 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ);
1195 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
1196 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
1197 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
1198 ha->dpc_active) && time_before(jiffies, wait_reset)) {
1199
1200 msleep(1000);
1201
1202 if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) &&
1203 ha->flags.chip_reset_done)
1204 break;
1205 }
1206 if (ha->flags.chip_reset_done)
1207 return_status = QLA_SUCCESS;
1208 else
1209 return_status = QLA_FUNCTION_FAILED;
1210
1211 return return_status;
1212}
1213
585def9b 1214static int
083a469d
GM		 1215sp_get(struct srb *sp)
1216{
845bbb09 1217 if (!refcount_inc_not_zero((refcount_t *)&sp->ref_count))
585def9b
QT		 1218 /* kref get fail */
1219 return ENXIO;
1220 else
1221 return 0;
083a469d
GM		 1222}
1223
a465537a
SC		 1224#define ISP_REG_DISCONNECT 0xffffffffU
1225/**************************************************************************
1226* qla2x00_isp_reg_stat
1227*
1228* Description:
1229* Read the host status register of ISP before aborting the command.
1230*
1231* Input:
1232* ha = pointer to host adapter structure.
1233*
1234*
1235* Returns:
1236* Either true or false.
1237*
1238* Note: Return true if there is register disconnect.
1239**************************************************************************/
1240static inline
1241uint32_t qla2x00_isp_reg_stat(struct qla_hw_data *ha)
1242{
1243 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
bf6061b1 1244 struct device_reg_82xx __iomem *reg82 = &ha->iobase->isp82;
a465537a 1245
bf6061b1
SC		 1246 if (IS_P3P_TYPE(ha))
1247 return ((RD_REG_DWORD(&reg82->host_int)) == ISP_REG_DISCONNECT);
1248 else
1249 return ((RD_REG_DWORD(&reg->host_status)) ==
1250 ISP_REG_DISCONNECT);
a465537a
SC		 1251}
1252
1da177e4
LT		 1253/**************************************************************************
1254* qla2xxx_eh_abort
1255*
1256* Description:
1257* The abort function will abort the specified command.
1258*
1259* Input:
1260* cmd = Linux SCSI command packet to be aborted.
1261*
1262* Returns:
1263* Either SUCCESS or FAILED.
1264*
1265* Note:
2ea00202 1266* Only return FAILED if command not returned by firmware.
1da177e4 1267**************************************************************************/
e5f82ab8 1268static int
1da177e4
LT		 1269qla2xxx_eh_abort(struct scsi_cmnd *cmd)
1270{
e315cd28 1271 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
8dd9593c 1272 DECLARE_COMPLETION_ONSTACK(comp);
f4f051eb 1273 srb_t *sp;
4e98d3b8 1274 int ret;
9cb78c16
HR		 1275 unsigned int id;
1276 uint64_t lun;
18e144d3 1277 unsigned long flags;
219d27d7 1278 int rval;
e315cd28 1279 struct qla_hw_data *ha = vha->hw;
585def9b 1280 struct qla_qpair *qpair;
1da177e4 1281
a465537a
SC		 1282 if (qla2x00_isp_reg_stat(ha)) {
1283 ql_log(ql_log_info, vha, 0x8042,
1284 "PCI/Register disconnect, exiting.\n");
1285 return FAILED;
1286 }
1da177e4 1287
4e98d3b8
AV		 1288 ret = fc_block_scsi_eh(cmd);
1289 if (ret != 0)
1290 return ret;
4e98d3b8 1291
170babc3 1292 sp = (srb_t *) CMD_SP(cmd);
585def9b
QT		 1293 if (!sp)
1294 return SUCCESS;
1295
1296 qpair = sp->qpair;
1297 if (!qpair)
1298 return SUCCESS;
1299
7f4374e6
QT		 1300 if (sp->fcport && sp->fcport->deleted)
1301 return SUCCESS;
1302
585def9b 1303 spin_lock_irqsave(qpair->qp_lock_ptr, flags);
219d27d7 1304 if (sp->type != SRB_SCSI_CMD || GET_CMD_SP(sp) != cmd) {
585def9b
QT		 1305 /* there's a chance an interrupt could clear
1306 the ptr as part of done & free */
1307 spin_unlock_irqrestore(qpair->qp_lock_ptr, flags);
170babc3
MC		 1308 return SUCCESS;
1309 }
1da177e4 1310
8dd9593c 1311 /* Get a reference to the sp and drop the lock. */
585def9b
QT		 1312 if (sp_get(sp)){
1313 /* ref_count is already 0 */
1314 spin_unlock_irqrestore(qpair->qp_lock_ptr, flags);
170babc3
MC		 1315 return SUCCESS;
1316 }
585def9b
QT		 1317 spin_unlock_irqrestore(qpair->qp_lock_ptr, flags);
1318
1319 id = cmd->device->id;
1320 lun = cmd->device->lun;
1da177e4 1321
7c3df132 1322 ql_dbg(ql_dbg_taskm, vha, 0x8002,
c7bc4cae
CD		 1323 "Aborting from RISC nexus=%ld:%d:%llu sp=%p cmd=%p handle=%x\n",
1324 vha->host_no, id, lun, sp, cmd, sp->handle);
17d98630 1325
f934c9d0 1326 rval = ha->isp_ops->abort_command(sp);
219d27d7
BVA		 1327 ql_dbg(ql_dbg_taskm, vha, 0x8003,
1328 "Abort command mbx cmd=%p, rval=%x.\n", cmd, rval);
f934c9d0 1329
219d27d7
BVA		 1330 switch (rval) {
1331 case QLA_SUCCESS:
711a08d7 1332 /*
219d27d7
BVA		 1333 * The command has been aborted. That means that the firmware
1334 * won't report a completion.
711a08d7 1335 */
219d27d7
BVA		 1336 sp->done(sp, DID_ABORT << 16);
1337 ret = SUCCESS;
1338 break;
8dd9593c
BVA		 1339 case QLA_FUNCTION_PARAMETER_ERROR: {
1340 /* Wait for the command completion. */
1341 uint32_t ratov = ha->r_a_tov/10;
1342 uint32_t ratov_j = msecs_to_jiffies(4 * ratov * 1000);
1343
1344 WARN_ON_ONCE(sp->comp);
1345 sp->comp = &comp;
1346 if (!wait_for_completion_timeout(&comp, ratov_j)) {
1347 ql_dbg(ql_dbg_taskm, vha, 0xffff,
1348 "%s: Abort wait timer (4 * R_A_TOV[%d]) expired\n",
1349 __func__, ha->r_a_tov);
1350 ret = FAILED;
1351 } else {
1352 ret = SUCCESS;
1353 }
1354 break;
1355 }
219d27d7
BVA		 1356 default:
1357 /*
1358 * Either abort failed or abort and completion raced. Let
1359 * the SCSI core retry the abort in the former case.
1360 */
1361 ret = FAILED;
1362 break;
1da177e4 1363 }
219d27d7 1364
8dd9593c
BVA		 1365 sp->comp = NULL;
1366 atomic_dec(&sp->ref_count);
7c3df132 1367 ql_log(ql_log_info, vha, 0x801c,
219d27d7
BVA		 1368 "Abort command issued nexus=%ld:%d:%llu -- %x.\n",
1369 vha->host_no, id, lun, ret);
1da177e4 1370
f4f051eb 1371 return ret;
1372}
1da177e4 1373
4d78c973 1374int
e315cd28 1375qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t,
9cb78c16 1376 uint64_t l, enum nexus_wait_type type)
f4f051eb 1377{
17d98630 1378 int cnt, match, status;
18e144d3 1379 unsigned long flags;
e315cd28 1380 struct qla_hw_data *ha = vha->hw;
73208dfd 1381 struct req_que *req;
4d78c973 1382 srb_t *sp;
9ba56b95 1383 struct scsi_cmnd *cmd;
1da177e4 1384
523ec773 1385 status = QLA_SUCCESS;
17d98630 1386
e315cd28 1387 spin_lock_irqsave(&ha->hardware_lock, flags);
67c2e93a 1388 req = vha->req;
17d98630 1389 for (cnt = 1; status == QLA_SUCCESS &&
8d93f550 1390 cnt < req->num_outstanding_cmds; cnt++) {
17d98630
AC		 1391 sp = req->outstanding_cmds[cnt];
1392 if (!sp)
523ec773 1393 continue;
9ba56b95 1394 if (sp->type != SRB_SCSI_CMD)
cf53b069 1395 continue;
25ff6af1 1396 if (vha->vp_idx != sp->vha->vp_idx)
17d98630
AC		 1397 continue;
1398 match = 0;
9ba56b95 1399 cmd = GET_CMD_SP(sp);
17d98630
AC		 1400 switch (type) {
1401 case WAIT_HOST:
1402 match = 1;
1403 break;
1404 case WAIT_TARGET:
9ba56b95 1405 match = cmd->device->id == t;
17d98630
AC		 1406 break;
1407 case WAIT_LUN:
9ba56b95
GM		 1408 match = (cmd->device->id == t &&
1409 cmd->device->lun == l);
17d98630 1410 break;
73208dfd 1411 }
17d98630
AC		 1412 if (!match)
1413 continue;
1414
1415 spin_unlock_irqrestore(&ha->hardware_lock, flags);
9ba56b95 1416 status = qla2x00_eh_wait_on_command(cmd);
17d98630 1417 spin_lock_irqsave(&ha->hardware_lock, flags);
1da177e4 1418 }
e315cd28 1419 spin_unlock_irqrestore(&ha->hardware_lock, flags);
523ec773
AV		 1420
1421 return status;
1da177e4
LT		 1422}
1423
523ec773
AV		 1424static char *reset_errors[] = {
1425 "HBA not online",
1426 "HBA not ready",
1427 "Task management failed",
1428 "Waiting for command completions",
1429};
1da177e4 1430
e5f82ab8 1431static int
523ec773 1432__qla2xxx_eh_generic_reset(char *name, enum nexus_wait_type type,
9cb78c16 1433 struct scsi_cmnd *cmd, int (*do_reset)(struct fc_port *, uint64_t, int))
1da177e4 1434{
e315cd28 1435 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
bdf79621 1436 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
523ec773 1437 int err;
1da177e4 1438
7c3df132 1439 if (!fcport) {
523ec773 1440 return FAILED;
7c3df132 1441 }
1da177e4 1442
4e98d3b8
AV		 1443 err = fc_block_scsi_eh(cmd);
1444 if (err != 0)
1445 return err;
1446
7f4374e6
QT		 1447 if (fcport->deleted)
1448 return SUCCESS;
1449
7c3df132 1450 ql_log(ql_log_info, vha, 0x8009,
9cb78c16 1451 "%s RESET ISSUED nexus=%ld:%d:%llu cmd=%p.\n", name, vha->host_no,
7c3df132 1452 cmd->device->id, cmd->device->lun, cmd);
1da177e4 1453
523ec773 1454 err = 0;
7c3df132
SK		 1455 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1456 ql_log(ql_log_warn, vha, 0x800a,
1457 "Wait for hba online failed for cmd=%p.\n", cmd);
523ec773 1458 goto eh_reset_failed;
7c3df132 1459 }
523ec773 1460 err = 2;
ac444b4f 1461 if (do_reset(fcport, cmd->device->lun, 1)
7c3df132
SK		 1462 != QLA_SUCCESS) {
1463 ql_log(ql_log_warn, vha, 0x800c,
1464 "do_reset failed for cmd=%p.\n", cmd);
523ec773 1465 goto eh_reset_failed;
7c3df132 1466 }
523ec773 1467 err = 3;
e315cd28 1468 if (qla2x00_eh_wait_for_pending_commands(vha, cmd->device->id,
7c3df132
SK		 1469 cmd->device->lun, type) != QLA_SUCCESS) {
1470 ql_log(ql_log_warn, vha, 0x800d,
d6a03581 1471 "wait for pending cmds failed for cmd=%p.\n", cmd);
523ec773 1472 goto eh_reset_failed;
7c3df132 1473 }
523ec773 1474
7c3df132 1475 ql_log(ql_log_info, vha, 0x800e,
9cb78c16 1476 "%s RESET SUCCEEDED nexus:%ld:%d:%llu cmd=%p.\n", name,
cfb0919c 1477 vha->host_no, cmd->device->id, cmd->device->lun, cmd);
523ec773
AV		 1478
1479 return SUCCESS;
1480
4d78c973 1481eh_reset_failed:
7c3df132 1482 ql_log(ql_log_info, vha, 0x800f,
9cb78c16 1483 "%s RESET FAILED: %s nexus=%ld:%d:%llu cmd=%p.\n", name,
cfb0919c
CD		 1484 reset_errors[err], vha->host_no, cmd->device->id, cmd->device->lun,
1485 cmd);
523ec773
AV		 1486 return FAILED;
1487}
1da177e4 1488
523ec773
AV		 1489static int
1490qla2xxx_eh_device_reset(struct scsi_cmnd *cmd)
1491{
e315cd28
AC		 1492 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1493 struct qla_hw_data *ha = vha->hw;
1da177e4 1494
a465537a
SC		 1495 if (qla2x00_isp_reg_stat(ha)) {
1496 ql_log(ql_log_info, vha, 0x803e,
1497 "PCI/Register disconnect, exiting.\n");
1498 return FAILED;
1499 }
1500
523ec773
AV		 1501 return __qla2xxx_eh_generic_reset("DEVICE", WAIT_LUN, cmd,
1502 ha->isp_ops->lun_reset);
1da177e4
LT		 1503}
1504
1da177e4 1505static int
523ec773 1506qla2xxx_eh_target_reset(struct scsi_cmnd *cmd)
1da177e4 1507{
e315cd28
AC		 1508 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1509 struct qla_hw_data *ha = vha->hw;
1da177e4 1510
a465537a
SC		 1511 if (qla2x00_isp_reg_stat(ha)) {
1512 ql_log(ql_log_info, vha, 0x803f,
1513 "PCI/Register disconnect, exiting.\n");
1514 return FAILED;
1515 }
1516
523ec773
AV		 1517 return __qla2xxx_eh_generic_reset("TARGET", WAIT_TARGET, cmd,
1518 ha->isp_ops->target_reset);
1da177e4
LT		 1519}
1520
1da177e4
LT		 1521/**************************************************************************
1522* qla2xxx_eh_bus_reset
1523*
1524* Description:
1525* The bus reset function will reset the bus and abort any executing
1526* commands.
1527*
1528* Input:
1529* cmd = Linux SCSI command packet of the command that cause the
1530* bus reset.
1531*
1532* Returns:
1533* SUCCESS/FAILURE (defined as macro in scsi.h).
1534*
1535**************************************************************************/
e5f82ab8 1536static int
1da177e4
LT		 1537qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd)
1538{
e315cd28 1539 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
bdf79621 1540 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
2c3dfe3f 1541 int ret = FAILED;
9cb78c16
HR		 1542 unsigned int id;
1543 uint64_t lun;
a465537a
SC		 1544 struct qla_hw_data *ha = vha->hw;
1545
1546 if (qla2x00_isp_reg_stat(ha)) {
1547 ql_log(ql_log_info, vha, 0x8040,
1548 "PCI/Register disconnect, exiting.\n");
1549 return FAILED;
1550 }
f4f051eb 1551
f4f051eb 1552 id = cmd->device->id;
1553 lun = cmd->device->lun;
1da177e4 1554
7c3df132 1555 if (!fcport) {
f4f051eb 1556 return ret;
7c3df132 1557 }
1da177e4 1558
4e98d3b8
AV		 1559 ret = fc_block_scsi_eh(cmd);
1560 if (ret != 0)
1561 return ret;
1562 ret = FAILED;
1563
7f4374e6
QT		 1564 if (qla2x00_chip_is_down(vha))
1565 return ret;
1566
7c3df132 1567 ql_log(ql_log_info, vha, 0x8012,
9cb78c16 1568 "BUS RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun);
1da177e4 1569
e315cd28 1570 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
7c3df132
SK		 1571 ql_log(ql_log_fatal, vha, 0x8013,
1572 "Wait for hba online failed board disabled.\n");
f4f051eb 1573 goto eh_bus_reset_done;
1da177e4
LT		 1574 }
1575
ad537689
SK		 1576 if (qla2x00_loop_reset(vha) == QLA_SUCCESS)
1577 ret = SUCCESS;
1578
f4f051eb 1579 if (ret == FAILED)
1580 goto eh_bus_reset_done;
1da177e4 1581
9a41a62b 1582 /* Flush outstanding commands. */
4d78c973 1583 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) !=
7c3df132
SK		 1584 QLA_SUCCESS) {
1585 ql_log(ql_log_warn, vha, 0x8014,
1586 "Wait for pending commands failed.\n");
9a41a62b 1587 ret = FAILED;
7c3df132 1588 }
1da177e4 1589
f4f051eb 1590eh_bus_reset_done:
7c3df132 1591 ql_log(ql_log_warn, vha, 0x802b,
9cb78c16 1592 "BUS RESET %s nexus=%ld:%d:%llu.\n",
d6a03581 1593 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1da177e4 1594
f4f051eb 1595 return ret;
1da177e4
LT		 1596}
1597
1598/**************************************************************************
1599* qla2xxx_eh_host_reset
1600*
1601* Description:
1602* The reset function will reset the Adapter.
1603*
1604* Input:
1605* cmd = Linux SCSI command packet of the command that cause the
1606* adapter reset.
1607*
1608* Returns:
1609* Either SUCCESS or FAILED.
1610*
1611* Note:
1612**************************************************************************/
e5f82ab8 1613static int
1da177e4
LT		 1614qla2xxx_eh_host_reset(struct scsi_cmnd *cmd)
1615{
e315cd28 1616 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
e315cd28 1617 struct qla_hw_data *ha = vha->hw;
2c3dfe3f 1618 int ret = FAILED;
9cb78c16
HR		 1619 unsigned int id;
1620 uint64_t lun;
e315cd28 1621 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4 1622
a465537a
SC		 1623 if (qla2x00_isp_reg_stat(ha)) {
1624 ql_log(ql_log_info, vha, 0x8041,
1625 "PCI/Register disconnect, exiting.\n");
1626 schedule_work(&ha->board_disable);
1627 return SUCCESS;
1628 }
1629
f4f051eb 1630 id = cmd->device->id;
1631 lun = cmd->device->lun;
f4f051eb 1632
7c3df132 1633 ql_log(ql_log_info, vha, 0x8018,
9cb78c16 1634 "ADAPTER RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun);
1da177e4 1635
63ee7072
CD		 1636 /*
1637 * No point in issuing another reset if one is active. Also do not
1638 * attempt a reset if we are updating flash.
1639 */
1640 if (qla2x00_reset_active(vha) || ha->optrom_state != QLA_SWAITING)
f4f051eb 1641 goto eh_host_reset_lock;
1da177e4 1642
e315cd28
AC		 1643 if (vha != base_vha) {
1644 if (qla2x00_vp_abort_isp(vha))
f4f051eb 1645 goto eh_host_reset_lock;
e315cd28 1646 } else {
7ec0effd 1647 if (IS_P3P_TYPE(vha->hw)) {
a9083016
GM		 1648 if (!qla82xx_fcoe_ctx_reset(vha)) {
1649 /* Ctx reset success */
1650 ret = SUCCESS;
1651 goto eh_host_reset_lock;
1652 }
1653 /* fall thru if ctx reset failed */
1654 }
68ca949c
AC		 1655 if (ha->wq)
1656 flush_workqueue(ha->wq);
1657
e315cd28 1658 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
a9083016 1659 if (ha->isp_ops->abort_isp(base_vha)) {
e315cd28
AC		 1660 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1661 /* failed. schedule dpc to try */
1662 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
1663
7c3df132
SK		 1664 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1665 ql_log(ql_log_warn, vha, 0x802a,
1666 "wait for hba online failed.\n");
e315cd28 1667 goto eh_host_reset_lock;
7c3df132 1668 }
e315cd28
AC		 1669 }
1670 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
fa2a1ce5 1671 }
1da177e4 1672
e315cd28 1673 /* Waiting for command to be returned to OS.*/
4d78c973 1674 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) ==
e315cd28 1675 QLA_SUCCESS)
f4f051eb 1676 ret = SUCCESS;
1da177e4 1677
f4f051eb 1678eh_host_reset_lock:
cfb0919c 1679 ql_log(ql_log_info, vha, 0x8017,
9cb78c16 1680 "ADAPTER RESET %s nexus=%ld:%d:%llu.\n",
cfb0919c 1681 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1da177e4 1682
f4f051eb 1683 return ret;
1684}
1da177e4
LT		 1685
1686/*
1687* qla2x00_loop_reset
1688* Issue loop reset.
1689*
1690* Input:
1691* ha = adapter block pointer.
1692*
1693* Returns:
1694* 0 = success
1695*/
a4722cf2 1696int
e315cd28 1697qla2x00_loop_reset(scsi_qla_host_t *vha)
1da177e4 1698{
0c8c39af 1699 int ret;
bdf79621 1700 struct fc_port *fcport;
e315cd28 1701 struct qla_hw_data *ha = vha->hw;
1da177e4 1702
5854771e
AB		 1703 if (IS_QLAFX00(ha)) {
1704 return qlafx00_loop_reset(vha);
1705 }
1706
f4c496c1 1707 if (ql2xtargetreset == 1 && ha->flags.enable_target_reset) {
55e5ed27
AV		 1708 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1709 if (fcport->port_type != FCT_TARGET)
1710 continue;
1711
1712 ret = ha->isp_ops->target_reset(fcport, 0, 0);
1713 if (ret != QLA_SUCCESS) {
7c3df132 1714 ql_dbg(ql_dbg_taskm, vha, 0x802c,
5854771e 1715 "Bus Reset failed: Reset=%d "
7c3df132 1716 "d_id=%x.\n", ret, fcport->d_id.b24);
55e5ed27
AV		 1717 }
1718 }
1719 }
1720
8ae6d9c7 1721
6246b8a1 1722 if (ha->flags.enable_lip_full_login && !IS_CNA_CAPABLE(ha)) {
0b7e7c53
AV		 1723 atomic_set(&vha->loop_state, LOOP_DOWN);
1724 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
1725 qla2x00_mark_all_devices_lost(vha, 0);
e315cd28 1726 ret = qla2x00_full_login_lip(vha);
0c8c39af 1727 if (ret != QLA_SUCCESS) {
7c3df132
SK		 1728 ql_dbg(ql_dbg_taskm, vha, 0x802d,
1729 "full_login_lip=%d.\n", ret);
749af3d5 1730 }
0c8c39af
AV		 1731 }
1732
0d6e61bc 1733 if (ha->flags.enable_lip_reset) {
e315cd28 1734 ret = qla2x00_lip_reset(vha);
ad537689 1735 if (ret != QLA_SUCCESS)
7c3df132
SK		 1736 ql_dbg(ql_dbg_taskm, vha, 0x802e,
1737 "lip_reset failed (%d).\n", ret);
1da177e4
LT		 1738 }
1739
1da177e4 1740 /* Issue marker command only when we are going to start the I/O */
e315cd28 1741 vha->marker_needed = 1;
1da177e4 1742
0c8c39af 1743 return QLA_SUCCESS;
1da177e4
LT		 1744}
1745
c4e521b6
BVA		 1746static void qla2x00_abort_srb(struct qla_qpair *qp, srb_t *sp, const int res,
1747 unsigned long *flags)
1748 __releases(qp->qp_lock_ptr)
1749 __acquires(qp->qp_lock_ptr)
1750{
219d27d7 1751 DECLARE_COMPLETION_ONSTACK(comp);
c4e521b6
BVA		 1752 scsi_qla_host_t *vha = qp->vha;
1753 struct qla_hw_data *ha = vha->hw;
219d27d7 1754 int rval;
c4e521b6 1755
219d27d7
BVA		 1756 if (sp_get(sp))
1757 return;
1758
1759 if (sp->type == SRB_NVME_CMD || sp->type == SRB_NVME_LS ||
1760 (sp->type == SRB_SCSI_CMD && !ha->flags.eeh_busy &&
1761 !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) &&
1762 !qla2x00_isp_reg_stat(ha))) {
1763 sp->comp = &comp;
219d27d7 1764 spin_unlock_irqrestore(qp->qp_lock_ptr, *flags);
5589b08e 1765 rval = ha->isp_ops->abort_command(sp);
219d27d7
BVA		 1766
1767 switch (rval) {
1768 case QLA_SUCCESS:
1769 sp->done(sp, res);
1770 break;
1771 case QLA_FUNCTION_PARAMETER_ERROR:
1772 wait_for_completion(&comp);
1773 break;
c4e521b6 1774 }
219d27d7
BVA		 1775
1776 spin_lock_irqsave(qp->qp_lock_ptr, *flags);
1777 sp->comp = NULL;
c4e521b6 1778 }
d2d2b5a5
BVA		 1779
1780 atomic_dec(&sp->ref_count);
c4e521b6
BVA		 1781}
1782
bbead493
QT		 1783static void
1784__qla2x00_abort_all_cmds(struct qla_qpair *qp, int res)
df4bf0bb 1785{
eb023220 1786 int cnt;
df4bf0bb
AV		 1787 unsigned long flags;
1788 srb_t *sp;
bbead493 1789 scsi_qla_host_t *vha = qp->vha;
e315cd28 1790 struct qla_hw_data *ha = vha->hw;
73208dfd 1791 struct req_que *req;
c5419e26
QT		 1792 struct qla_tgt *tgt = vha->vha_tgt.qla_tgt;
1793 struct qla_tgt_cmd *cmd;
c0cb4496 1794
6a2cf8d3
BK		 1795 if (!ha->req_q_map)
1796 return;
bbead493
QT		 1797 spin_lock_irqsave(qp->qp_lock_ptr, flags);
1798 req = qp->req;
1799 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) {
1800 sp = req->outstanding_cmds[cnt];
1801 if (sp) {
1802 req->outstanding_cmds[cnt] = NULL;
6b0431d6
QT		 1803 switch (sp->cmd_type) {
1804 case TYPE_SRB:
c4e521b6 1805 qla2x00_abort_srb(qp, sp, res, &flags);
585def9b
QT		 1806 break;
1807 case TYPE_TGT_CMD:
bbead493
QT		 1808 if (!vha->hw->tgt.tgt_ops || !tgt ||
1809 qla_ini_mode_enabled(vha)) {
585def9b
QT		 1810 ql_dbg(ql_dbg_tgt_mgt, vha, 0xf003,
1811 "HOST-ABORT-HNDLR: dpc_flags=%lx. Target mode disabled\n",
1812 vha->dpc_flags);
bbead493 1813 continue;
c733ab35 1814 }
bbead493 1815 cmd = (struct qla_tgt_cmd *)sp;
aefed3e5 1816 cmd->aborted = 1;
585def9b
QT		 1817 break;
1818 case TYPE_TGT_TMCMD:
aefed3e5 1819 /* Skip task management functions. */
585def9b
QT		 1820 break;
1821 default:
1822 break;
73208dfd 1823 }
df4bf0bb
AV		 1824 }
1825 }
bbead493
QT		 1826 spin_unlock_irqrestore(qp->qp_lock_ptr, flags);
1827}
1828
1829void
1830qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res)
1831{
1832 int que;
1833 struct qla_hw_data *ha = vha->hw;
1834
26a77799
AV		 1835 /* Continue only if initialization complete. */
1836 if (!ha->base_qpair)
1837 return;
bbead493
QT		 1838 __qla2x00_abort_all_cmds(ha->base_qpair, res);
1839
26a77799
AV		 1840 if (!ha->queue_pair_map)
1841 return;
bbead493
QT		 1842 for (que = 0; que < ha->max_qpairs; que++) {
1843 if (!ha->queue_pair_map[que])
1844 continue;
1845
1846 __qla2x00_abort_all_cmds(ha->queue_pair_map[que], res);
1847 }
df4bf0bb
AV		 1848}
1849
f4f051eb 1850static int
1851qla2xxx_slave_alloc(struct scsi_device *sdev)
1da177e4 1852{
bdf79621 1853 struct fc_rport *rport = starget_to_rport(scsi_target(sdev));
1da177e4 1854
19a7b4ae 1855 if (!rport || fc_remote_port_chkready(rport))
f4f051eb 1856 return -ENXIO;
bdf79621 1857
19a7b4ae 1858 sdev->hostdata = *(fc_port_t **)rport->dd_data;
1da177e4 1859
f4f051eb 1860 return 0;
1861}
1da177e4 1862
f4f051eb 1863static int
1864qla2xxx_slave_configure(struct scsi_device *sdev)
1865{
e315cd28 1866 scsi_qla_host_t *vha = shost_priv(sdev->host);
2afa19a9 1867 struct req_que *req = vha->req;
8482e118 1868
9e522cd8
AE		 1869 if (IS_T10_PI_CAPABLE(vha->hw))
1870 blk_queue_update_dma_alignment(sdev->request_queue, 0x7);
1871
db5ed4df 1872 scsi_change_queue_depth(sdev, req->max_q_depth);
f4f051eb 1873 return 0;
1874}
1da177e4 1875
f4f051eb 1876static void
1877qla2xxx_slave_destroy(struct scsi_device *sdev)
1878{
1879 sdev->hostdata = NULL;
1da177e4
LT		 1880}
1881
1882/**
1883 * qla2x00_config_dma_addressing() - Configure OS DMA addressing method.
1884 * @ha: HA context
1885 *
1886 * At exit, the @ha's flags.enable_64bit_addressing set to indicated
1887 * supported addressing method.
1888 */
1889static void
53303c42 1890qla2x00_config_dma_addressing(struct qla_hw_data *ha)
1da177e4 1891{
7524f9b9 1892 /* Assume a 32bit DMA mask. */
1da177e4 1893 ha->flags.enable_64bit_addressing = 0;
1da177e4 1894
6a35528a 1895 if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) {
7524f9b9
AV		 1896 /* Any upper-dword bits set? */
1897 if (MSD(dma_get_required_mask(&ha->pdev->dev)) &&
6a35528a 1898 !pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(64))) {
7524f9b9 1899 /* Ok, a 64bit DMA mask is applicable. */
1da177e4 1900 ha->flags.enable_64bit_addressing = 1;
fd34f556
AV		 1901 ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64;
1902 ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64;
7524f9b9 1903 return;
1da177e4 1904 }
1da177e4 1905 }
7524f9b9 1906
284901a9
YH		 1907 dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32));
1908 pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(32));
1da177e4
LT		 1909}
1910
fd34f556 1911static void
e315cd28 1912qla2x00_enable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1913{
1914 unsigned long flags = 0;
1915 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1916
1917 spin_lock_irqsave(&ha->hardware_lock, flags);
1918 ha->interrupts_on = 1;
1919 /* enable risc and host interrupts */
1920 WRT_REG_WORD(&reg->ictrl, ICR_EN_INT | ICR_EN_RISC);
1921 RD_REG_WORD(&reg->ictrl);
1922 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1923
1924}
1925
1926static void
e315cd28 1927qla2x00_disable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1928{
1929 unsigned long flags = 0;
1930 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1931
1932 spin_lock_irqsave(&ha->hardware_lock, flags);
1933 ha->interrupts_on = 0;
1934 /* disable risc and host interrupts */
1935 WRT_REG_WORD(&reg->ictrl, 0);
1936 RD_REG_WORD(&reg->ictrl);
1937 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1938}
1939
1940static void
e315cd28 1941qla24xx_enable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1942{
1943 unsigned long flags = 0;
1944 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1945
1946 spin_lock_irqsave(&ha->hardware_lock, flags);
1947 ha->interrupts_on = 1;
1948 WRT_REG_DWORD(&reg->ictrl, ICRX_EN_RISC_INT);
1949 RD_REG_DWORD(&reg->ictrl);
1950 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1951}
1952
1953static void
e315cd28 1954qla24xx_disable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1955{
1956 unsigned long flags = 0;
1957 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1958
124f85e6
AV		 1959 if (IS_NOPOLLING_TYPE(ha))
1960 return;
fd34f556
AV		 1961 spin_lock_irqsave(&ha->hardware_lock, flags);
1962 ha->interrupts_on = 0;
1963 WRT_REG_DWORD(&reg->ictrl, 0);
1964 RD_REG_DWORD(&reg->ictrl);
1965 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1966}
1967
706f457d
GM		 1968static int
1969qla2x00_iospace_config(struct qla_hw_data *ha)
1970{
1971 resource_size_t pio;
1972 uint16_t msix;
706f457d 1973
706f457d
GM		 1974 if (pci_request_selected_regions(ha->pdev, ha->bars,
1975 QLA2XXX_DRIVER_NAME)) {
1976 ql_log_pci(ql_log_fatal, ha->pdev, 0x0011,
1977 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
1978 pci_name(ha->pdev));
1979 goto iospace_error_exit;
1980 }
1981 if (!(ha->bars & 1))
1982 goto skip_pio;
1983
1984 /* We only need PIO for Flash operations on ISP2312 v2 chips. */
1985 pio = pci_resource_start(ha->pdev, 0);
1986 if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) {
1987 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
1988 ql_log_pci(ql_log_warn, ha->pdev, 0x0012,
1989 "Invalid pci I/O region size (%s).\n",
1990 pci_name(ha->pdev));
1991 pio = 0;
1992 }
1993 } else {
1994 ql_log_pci(ql_log_warn, ha->pdev, 0x0013,
1995 "Region #0 no a PIO resource (%s).\n",
1996 pci_name(ha->pdev));
1997 pio = 0;
1998 }
1999 ha->pio_address = pio;
2000 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014,
2001 "PIO address=%llu.\n",
2002 (unsigned long long)ha->pio_address);
2003
2004skip_pio:
2005 /* Use MMIO operations for all accesses. */
2006 if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) {
2007 ql_log_pci(ql_log_fatal, ha->pdev, 0x0015,
2008 "Region #1 not an MMIO resource (%s), aborting.\n",
2009 pci_name(ha->pdev));
2010 goto iospace_error_exit;
2011 }
2012 if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) {
2013 ql_log_pci(ql_log_fatal, ha->pdev, 0x0016,
2014 "Invalid PCI mem region size (%s), aborting.\n",
2015 pci_name(ha->pdev));
2016 goto iospace_error_exit;
2017 }
2018
2019 ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN);
2020 if (!ha->iobase) {
2021 ql_log_pci(ql_log_fatal, ha->pdev, 0x0017,
2022 "Cannot remap MMIO (%s), aborting.\n",
2023 pci_name(ha->pdev));
2024 goto iospace_error_exit;
2025 }
2026
2027 /* Determine queue resources */
2028 ha->max_req_queues = ha->max_rsp_queues = 1;
f54f2cb5 2029 ha->msix_count = QLA_BASE_VECTORS;
c38d1baf
HM		 2030 if (!ql2xmqsupport || !ql2xnvmeenable ||
2031 (!IS_QLA25XX(ha) && !IS_QLA81XX(ha)))
706f457d
GM		 2032 goto mqiobase_exit;
2033
2034 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3),
2035 pci_resource_len(ha->pdev, 3));
2036 if (ha->mqiobase) {
2037 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018,
2038 "MQIO Base=%p.\n", ha->mqiobase);
2039 /* Read MSIX vector size of the board */
2040 pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix);
d7459527 2041 ha->msix_count = msix + 1;
706f457d 2042 /* Max queues are bounded by available msix vectors */
d7459527
MH		 2043 /* MB interrupt uses 1 vector */
2044 ha->max_req_queues = ha->msix_count - 1;
2045 ha->max_rsp_queues = ha->max_req_queues;
2046 /* Queue pairs is the max value minus the base queue pair */
2047 ha->max_qpairs = ha->max_rsp_queues - 1;
2048 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0188,
2049 "Max no of queues pairs: %d.\n", ha->max_qpairs);
2050
706f457d 2051 ql_log_pci(ql_log_info, ha->pdev, 0x001a,
d7459527 2052 "MSI-X vector count: %d.\n", ha->msix_count);
706f457d
GM		 2053 } else
2054 ql_log_pci(ql_log_info, ha->pdev, 0x001b,
2055 "BAR 3 not enabled.\n");
2056
2057mqiobase_exit:
706f457d 2058 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c,
f54f2cb5 2059 "MSIX Count: %d.\n", ha->msix_count);
706f457d
GM		 2060 return (0);
2061
2062iospace_error_exit:
2063 return (-ENOMEM);
2064}
2065
2066
6246b8a1
GM		 2067static int
2068qla83xx_iospace_config(struct qla_hw_data *ha)
2069{
2070 uint16_t msix;
6246b8a1
GM		 2071
2072 if (pci_request_selected_regions(ha->pdev, ha->bars,
2073 QLA2XXX_DRIVER_NAME)) {
2074 ql_log_pci(ql_log_fatal, ha->pdev, 0x0117,
2075 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
2076 pci_name(ha->pdev));
2077
2078 goto iospace_error_exit;
2079 }
2080
2081 /* Use MMIO operations for all accesses. */
2082 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) {
2083 ql_log_pci(ql_log_warn, ha->pdev, 0x0118,
2084 "Invalid pci I/O region size (%s).\n",
2085 pci_name(ha->pdev));
2086 goto iospace_error_exit;
2087 }
2088 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
2089 ql_log_pci(ql_log_warn, ha->pdev, 0x0119,
2090 "Invalid PCI mem region size (%s), aborting\n",
2091 pci_name(ha->pdev));
2092 goto iospace_error_exit;
2093 }
2094
2095 ha->iobase = ioremap(pci_resource_start(ha->pdev, 0), MIN_IOBASE_LEN);
2096 if (!ha->iobase) {
2097 ql_log_pci(ql_log_fatal, ha->pdev, 0x011a,
2098 "Cannot remap MMIO (%s), aborting.\n",
2099 pci_name(ha->pdev));
2100 goto iospace_error_exit;
2101 }
2102
2103 /* 64bit PCI BAR - BAR2 will correspoond to region 4 */
2104 /* 83XX 26XX always use MQ type access for queues
2105 * - mbar 2, a.k.a region 4 */
2106 ha->max_req_queues = ha->max_rsp_queues = 1;
f54f2cb5 2107 ha->msix_count = QLA_BASE_VECTORS;
6246b8a1
GM		 2108 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 4),
2109 pci_resource_len(ha->pdev, 4));
2110
2111 if (!ha->mqiobase) {
2112 ql_log_pci(ql_log_fatal, ha->pdev, 0x011d,
2113 "BAR2/region4 not enabled\n");
2114 goto mqiobase_exit;
2115 }
2116
2117 ha->msixbase = ioremap(pci_resource_start(ha->pdev, 2),
2118 pci_resource_len(ha->pdev, 2));
2119 if (ha->msixbase) {
2120 /* Read MSIX vector size of the board */
2121 pci_read_config_word(ha->pdev,
2122 QLA_83XX_PCI_MSIX_CONTROL, &msix);
e326d22a 2123 ha->msix_count = (msix & PCI_MSIX_FLAGS_QSIZE) + 1;
093df737
QT		 2124 /*
2125 * By default, driver uses at least two msix vectors
2126 * (default & rspq)
2127 */
c38d1baf 2128 if (ql2xmqsupport || ql2xnvmeenable) {
d7459527
MH		 2129 /* MB interrupt uses 1 vector */
2130 ha->max_req_queues = ha->msix_count - 1;
093df737
QT		 2131
2132 /* ATIOQ needs 1 vector. That's 1 less QPair */
2133 if (QLA_TGT_MODE_ENABLED())
2134 ha->max_req_queues--;
2135
d0d2c68b
MH		 2136 ha->max_rsp_queues = ha->max_req_queues;
2137
d7459527
MH		 2138 /* Queue pairs is the max value minus
2139 * the base queue pair */
2140 ha->max_qpairs = ha->max_req_queues - 1;
83548fe2 2141 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x00e3,
d7459527 2142 "Max no of queues pairs: %d.\n", ha->max_qpairs);
6246b8a1
GM		 2143 }
2144 ql_log_pci(ql_log_info, ha->pdev, 0x011c,
d7459527 2145 "MSI-X vector count: %d.\n", ha->msix_count);
6246b8a1
GM		 2146 } else
2147 ql_log_pci(ql_log_info, ha->pdev, 0x011e,
2148 "BAR 1 not enabled.\n");
2149
2150mqiobase_exit:
6246b8a1 2151 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011f,
f54f2cb5 2152 "MSIX Count: %d.\n", ha->msix_count);
6246b8a1
GM		 2153 return 0;
2154
2155iospace_error_exit:
2156 return -ENOMEM;
2157}
2158
fd34f556
AV		 2159static struct isp_operations qla2100_isp_ops = {
2160 .pci_config = qla2100_pci_config,
2161 .reset_chip = qla2x00_reset_chip,
2162 .chip_diag = qla2x00_chip_diag,
2163 .config_rings = qla2x00_config_rings,
2164 .reset_adapter = qla2x00_reset_adapter,
2165 .nvram_config = qla2x00_nvram_config,
2166 .update_fw_options = qla2x00_update_fw_options,
2167 .load_risc = qla2x00_load_risc,
2168 .pci_info_str = qla2x00_pci_info_str,
2169 .fw_version_str = qla2x00_fw_version_str,
2170 .intr_handler = qla2100_intr_handler,
2171 .enable_intrs = qla2x00_enable_intrs,
2172 .disable_intrs = qla2x00_disable_intrs,
2173 .abort_command = qla2x00_abort_command,
523ec773
AV		 2174 .target_reset = qla2x00_abort_target,
2175 .lun_reset = qla2x00_lun_reset,
fd34f556
AV		 2176 .fabric_login = qla2x00_login_fabric,
2177 .fabric_logout = qla2x00_fabric_logout,
2178 .calc_req_entries = qla2x00_calc_iocbs_32,
2179 .build_iocbs = qla2x00_build_scsi_iocbs_32,
2180 .prep_ms_iocb = qla2x00_prep_ms_iocb,
2181 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
2182 .read_nvram = qla2x00_read_nvram_data,
2183 .write_nvram = qla2x00_write_nvram_data,
2184 .fw_dump = qla2100_fw_dump,
2185 .beacon_on = NULL,
2186 .beacon_off = NULL,
2187 .beacon_blink = NULL,
2188 .read_optrom = qla2x00_read_optrom_data,
2189 .write_optrom = qla2x00_write_optrom_data,
2190 .get_flash_version = qla2x00_get_flash_version,
e315cd28 2191 .start_scsi = qla2x00_start_scsi,
d7459527 2192 .start_scsi_mq = NULL,
a9083016 2193 .abort_isp = qla2x00_abort_isp,
706f457d 2194 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2195 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 2196};
2197
2198static struct isp_operations qla2300_isp_ops = {
2199 .pci_config = qla2300_pci_config,
2200 .reset_chip = qla2x00_reset_chip,
2201 .chip_diag = qla2x00_chip_diag,
2202 .config_rings = qla2x00_config_rings,
2203 .reset_adapter = qla2x00_reset_adapter,
2204 .nvram_config = qla2x00_nvram_config,
2205 .update_fw_options = qla2x00_update_fw_options,
2206 .load_risc = qla2x00_load_risc,
2207 .pci_info_str = qla2x00_pci_info_str,
2208 .fw_version_str = qla2x00_fw_version_str,
2209 .intr_handler = qla2300_intr_handler,
2210 .enable_intrs = qla2x00_enable_intrs,
2211 .disable_intrs = qla2x00_disable_intrs,
2212 .abort_command = qla2x00_abort_command,
523ec773
AV		 2213 .target_reset = qla2x00_abort_target,
2214 .lun_reset = qla2x00_lun_reset,
fd34f556
AV		 2215 .fabric_login = qla2x00_login_fabric,
2216 .fabric_logout = qla2x00_fabric_logout,
2217 .calc_req_entries = qla2x00_calc_iocbs_32,
2218 .build_iocbs = qla2x00_build_scsi_iocbs_32,
2219 .prep_ms_iocb = qla2x00_prep_ms_iocb,
2220 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
2221 .read_nvram = qla2x00_read_nvram_data,
2222 .write_nvram = qla2x00_write_nvram_data,
2223 .fw_dump = qla2300_fw_dump,
2224 .beacon_on = qla2x00_beacon_on,
2225 .beacon_off = qla2x00_beacon_off,
2226 .beacon_blink = qla2x00_beacon_blink,
2227 .read_optrom = qla2x00_read_optrom_data,
2228 .write_optrom = qla2x00_write_optrom_data,
2229 .get_flash_version = qla2x00_get_flash_version,
e315cd28 2230 .start_scsi = qla2x00_start_scsi,
d7459527 2231 .start_scsi_mq = NULL,
a9083016 2232 .abort_isp = qla2x00_abort_isp,
7ec0effd 2233 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2234 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 2235};
2236
2237static struct isp_operations qla24xx_isp_ops = {
2238 .pci_config = qla24xx_pci_config,
2239 .reset_chip = qla24xx_reset_chip,
2240 .chip_diag = qla24xx_chip_diag,
2241 .config_rings = qla24xx_config_rings,
2242 .reset_adapter = qla24xx_reset_adapter,
2243 .nvram_config = qla24xx_nvram_config,
2244 .update_fw_options = qla24xx_update_fw_options,
2245 .load_risc = qla24xx_load_risc,
2246 .pci_info_str = qla24xx_pci_info_str,
2247 .fw_version_str = qla24xx_fw_version_str,
2248 .intr_handler = qla24xx_intr_handler,
2249 .enable_intrs = qla24xx_enable_intrs,
2250 .disable_intrs = qla24xx_disable_intrs,
2251 .abort_command = qla24xx_abort_command,
523ec773
AV		 2252 .target_reset = qla24xx_abort_target,
2253 .lun_reset = qla24xx_lun_reset,
fd34f556
AV		 2254 .fabric_login = qla24xx_login_fabric,
2255 .fabric_logout = qla24xx_fabric_logout,
2256 .calc_req_entries = NULL,
2257 .build_iocbs = NULL,
2258 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2259 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2260 .read_nvram = qla24xx_read_nvram_data,
2261 .write_nvram = qla24xx_write_nvram_data,
2262 .fw_dump = qla24xx_fw_dump,
2263 .beacon_on = qla24xx_beacon_on,
2264 .beacon_off = qla24xx_beacon_off,
2265 .beacon_blink = qla24xx_beacon_blink,
2266 .read_optrom = qla24xx_read_optrom_data,
2267 .write_optrom = qla24xx_write_optrom_data,
2268 .get_flash_version = qla24xx_get_flash_version,
e315cd28 2269 .start_scsi = qla24xx_start_scsi,
d7459527 2270 .start_scsi_mq = NULL,
a9083016 2271 .abort_isp = qla2x00_abort_isp,
7ec0effd 2272 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2273 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 2274};
2275
c3a2f0df
AV		 2276static struct isp_operations qla25xx_isp_ops = {
2277 .pci_config = qla25xx_pci_config,
2278 .reset_chip = qla24xx_reset_chip,
2279 .chip_diag = qla24xx_chip_diag,
2280 .config_rings = qla24xx_config_rings,
2281 .reset_adapter = qla24xx_reset_adapter,
2282 .nvram_config = qla24xx_nvram_config,
2283 .update_fw_options = qla24xx_update_fw_options,
2284 .load_risc = qla24xx_load_risc,
2285 .pci_info_str = qla24xx_pci_info_str,
2286 .fw_version_str = qla24xx_fw_version_str,
2287 .intr_handler = qla24xx_intr_handler,
2288 .enable_intrs = qla24xx_enable_intrs,
2289 .disable_intrs = qla24xx_disable_intrs,
2290 .abort_command = qla24xx_abort_command,
523ec773
AV		 2291 .target_reset = qla24xx_abort_target,
2292 .lun_reset = qla24xx_lun_reset,
c3a2f0df
AV		 2293 .fabric_login = qla24xx_login_fabric,
2294 .fabric_logout = qla24xx_fabric_logout,
2295 .calc_req_entries = NULL,
2296 .build_iocbs = NULL,
2297 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2298 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2299 .read_nvram = qla25xx_read_nvram_data,
2300 .write_nvram = qla25xx_write_nvram_data,
2301 .fw_dump = qla25xx_fw_dump,
2302 .beacon_on = qla24xx_beacon_on,
2303 .beacon_off = qla24xx_beacon_off,
2304 .beacon_blink = qla24xx_beacon_blink,
338c9161 2305 .read_optrom = qla25xx_read_optrom_data,
c3a2f0df
AV		 2306 .write_optrom = qla24xx_write_optrom_data,
2307 .get_flash_version = qla24xx_get_flash_version,
bad75002 2308 .start_scsi = qla24xx_dif_start_scsi,
d7459527 2309 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
a9083016 2310 .abort_isp = qla2x00_abort_isp,
7ec0effd 2311 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2312 .initialize_adapter = qla2x00_initialize_adapter,
c3a2f0df
AV		 2313};
2314
3a03eb79
AV		 2315static struct isp_operations qla81xx_isp_ops = {
2316 .pci_config = qla25xx_pci_config,
2317 .reset_chip = qla24xx_reset_chip,
2318 .chip_diag = qla24xx_chip_diag,
2319 .config_rings = qla24xx_config_rings,
2320 .reset_adapter = qla24xx_reset_adapter,
2321 .nvram_config = qla81xx_nvram_config,
2322 .update_fw_options = qla81xx_update_fw_options,
eaac30be 2323 .load_risc = qla81xx_load_risc,
3a03eb79
AV		 2324 .pci_info_str = qla24xx_pci_info_str,
2325 .fw_version_str = qla24xx_fw_version_str,
2326 .intr_handler = qla24xx_intr_handler,
2327 .enable_intrs = qla24xx_enable_intrs,
2328 .disable_intrs = qla24xx_disable_intrs,
2329 .abort_command = qla24xx_abort_command,
2330 .target_reset = qla24xx_abort_target,
2331 .lun_reset = qla24xx_lun_reset,
2332 .fabric_login = qla24xx_login_fabric,
2333 .fabric_logout = qla24xx_fabric_logout,
2334 .calc_req_entries = NULL,
2335 .build_iocbs = NULL,
2336 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2337 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
3d79038f
AV		 2338 .read_nvram = NULL,
2339 .write_nvram = NULL,
3a03eb79
AV		 2340 .fw_dump = qla81xx_fw_dump,
2341 .beacon_on = qla24xx_beacon_on,
2342 .beacon_off = qla24xx_beacon_off,
6246b8a1 2343 .beacon_blink = qla83xx_beacon_blink,
3a03eb79
AV		 2344 .read_optrom = qla25xx_read_optrom_data,
2345 .write_optrom = qla24xx_write_optrom_data,
2346 .get_flash_version = qla24xx_get_flash_version,
ba77ef53 2347 .start_scsi = qla24xx_dif_start_scsi,
d7459527 2348 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
a9083016 2349 .abort_isp = qla2x00_abort_isp,
7ec0effd 2350 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2351 .initialize_adapter = qla2x00_initialize_adapter,
a9083016
GM		 2352};
2353
2354static struct isp_operations qla82xx_isp_ops = {
2355 .pci_config = qla82xx_pci_config,
2356 .reset_chip = qla82xx_reset_chip,
2357 .chip_diag = qla24xx_chip_diag,
2358 .config_rings = qla82xx_config_rings,
2359 .reset_adapter = qla24xx_reset_adapter,
2360 .nvram_config = qla81xx_nvram_config,
2361 .update_fw_options = qla24xx_update_fw_options,
2362 .load_risc = qla82xx_load_risc,
9d55ca66 2363 .pci_info_str = qla24xx_pci_info_str,
a9083016
GM		 2364 .fw_version_str = qla24xx_fw_version_str,
2365 .intr_handler = qla82xx_intr_handler,
2366 .enable_intrs = qla82xx_enable_intrs,
2367 .disable_intrs = qla82xx_disable_intrs,
2368 .abort_command = qla24xx_abort_command,
2369 .target_reset = qla24xx_abort_target,
2370 .lun_reset = qla24xx_lun_reset,
2371 .fabric_login = qla24xx_login_fabric,
2372 .fabric_logout = qla24xx_fabric_logout,
2373 .calc_req_entries = NULL,
2374 .build_iocbs = NULL,
2375 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2376 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2377 .read_nvram = qla24xx_read_nvram_data,
2378 .write_nvram = qla24xx_write_nvram_data,
a1b23c5a 2379 .fw_dump = qla82xx_fw_dump,
999916dc
SK		 2380 .beacon_on = qla82xx_beacon_on,
2381 .beacon_off = qla82xx_beacon_off,
2382 .beacon_blink = NULL,
a9083016
GM		 2383 .read_optrom = qla82xx_read_optrom_data,
2384 .write_optrom = qla82xx_write_optrom_data,
7ec0effd 2385 .get_flash_version = qla82xx_get_flash_version,
a9083016 2386 .start_scsi = qla82xx_start_scsi,
d7459527 2387 .start_scsi_mq = NULL,
a9083016 2388 .abort_isp = qla82xx_abort_isp,
706f457d 2389 .iospace_config = qla82xx_iospace_config,
8ae6d9c7 2390 .initialize_adapter = qla2x00_initialize_adapter,
3a03eb79
AV		 2391};
2392
7ec0effd
AD		 2393static struct isp_operations qla8044_isp_ops = {
2394 .pci_config = qla82xx_pci_config,
2395 .reset_chip = qla82xx_reset_chip,
2396 .chip_diag = qla24xx_chip_diag,
2397 .config_rings = qla82xx_config_rings,
2398 .reset_adapter = qla24xx_reset_adapter,
2399 .nvram_config = qla81xx_nvram_config,
2400 .update_fw_options = qla24xx_update_fw_options,
2401 .load_risc = qla82xx_load_risc,
2402 .pci_info_str = qla24xx_pci_info_str,
2403 .fw_version_str = qla24xx_fw_version_str,
2404 .intr_handler = qla8044_intr_handler,
2405 .enable_intrs = qla82xx_enable_intrs,
2406 .disable_intrs = qla82xx_disable_intrs,
2407 .abort_command = qla24xx_abort_command,
2408 .target_reset = qla24xx_abort_target,
2409 .lun_reset = qla24xx_lun_reset,
2410 .fabric_login = qla24xx_login_fabric,
2411 .fabric_logout = qla24xx_fabric_logout,
2412 .calc_req_entries = NULL,
2413 .build_iocbs = NULL,
2414 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2415 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2416 .read_nvram = NULL,
2417 .write_nvram = NULL,
a1b23c5a 2418 .fw_dump = qla8044_fw_dump,
7ec0effd
AD		 2419 .beacon_on = qla82xx_beacon_on,
2420 .beacon_off = qla82xx_beacon_off,
2421 .beacon_blink = NULL,
888e639d 2422 .read_optrom = qla8044_read_optrom_data,
7ec0effd
AD		 2423 .write_optrom = qla8044_write_optrom_data,
2424 .get_flash_version = qla82xx_get_flash_version,
2425 .start_scsi = qla82xx_start_scsi,
d7459527 2426 .start_scsi_mq = NULL,
7ec0effd
AD		 2427 .abort_isp = qla8044_abort_isp,
2428 .iospace_config = qla82xx_iospace_config,
2429 .initialize_adapter = qla2x00_initialize_adapter,
2430};
2431
6246b8a1
GM		 2432static struct isp_operations qla83xx_isp_ops = {
2433 .pci_config = qla25xx_pci_config,
2434 .reset_chip = qla24xx_reset_chip,
2435 .chip_diag = qla24xx_chip_diag,
2436 .config_rings = qla24xx_config_rings,
2437 .reset_adapter = qla24xx_reset_adapter,
2438 .nvram_config = qla81xx_nvram_config,
2439 .update_fw_options = qla81xx_update_fw_options,
2440 .load_risc = qla81xx_load_risc,
2441 .pci_info_str = qla24xx_pci_info_str,
2442 .fw_version_str = qla24xx_fw_version_str,
2443 .intr_handler = qla24xx_intr_handler,
2444 .enable_intrs = qla24xx_enable_intrs,
2445 .disable_intrs = qla24xx_disable_intrs,
2446 .abort_command = qla24xx_abort_command,
2447 .target_reset = qla24xx_abort_target,
2448 .lun_reset = qla24xx_lun_reset,
2449 .fabric_login = qla24xx_login_fabric,
2450 .fabric_logout = qla24xx_fabric_logout,
2451 .calc_req_entries = NULL,
2452 .build_iocbs = NULL,
2453 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2454 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2455 .read_nvram = NULL,
2456 .write_nvram = NULL,
2457 .fw_dump = qla83xx_fw_dump,
2458 .beacon_on = qla24xx_beacon_on,
2459 .beacon_off = qla24xx_beacon_off,
2460 .beacon_blink = qla83xx_beacon_blink,
2461 .read_optrom = qla25xx_read_optrom_data,
2462 .write_optrom = qla24xx_write_optrom_data,
2463 .get_flash_version = qla24xx_get_flash_version,
2464 .start_scsi = qla24xx_dif_start_scsi,
d7459527 2465 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
6246b8a1
GM		 2466 .abort_isp = qla2x00_abort_isp,
2467 .iospace_config = qla83xx_iospace_config,
8ae6d9c7
GM		 2468 .initialize_adapter = qla2x00_initialize_adapter,
2469};
2470
2471static struct isp_operations qlafx00_isp_ops = {
2472 .pci_config = qlafx00_pci_config,
2473 .reset_chip = qlafx00_soft_reset,
2474 .chip_diag = qlafx00_chip_diag,
2475 .config_rings = qlafx00_config_rings,
2476 .reset_adapter = qlafx00_soft_reset,
2477 .nvram_config = NULL,
2478 .update_fw_options = NULL,
2479 .load_risc = NULL,
2480 .pci_info_str = qlafx00_pci_info_str,
2481 .fw_version_str = qlafx00_fw_version_str,
2482 .intr_handler = qlafx00_intr_handler,
2483 .enable_intrs = qlafx00_enable_intrs,
2484 .disable_intrs = qlafx00_disable_intrs,
4440e46d 2485 .abort_command = qla24xx_async_abort_command,
8ae6d9c7
GM		 2486 .target_reset = qlafx00_abort_target,
2487 .lun_reset = qlafx00_lun_reset,
2488 .fabric_login = NULL,
2489 .fabric_logout = NULL,
2490 .calc_req_entries = NULL,
2491 .build_iocbs = NULL,
2492 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2493 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2494 .read_nvram = qla24xx_read_nvram_data,
2495 .write_nvram = qla24xx_write_nvram_data,
2496 .fw_dump = NULL,
2497 .beacon_on = qla24xx_beacon_on,
2498 .beacon_off = qla24xx_beacon_off,
2499 .beacon_blink = NULL,
2500 .read_optrom = qla24xx_read_optrom_data,
2501 .write_optrom = qla24xx_write_optrom_data,
2502 .get_flash_version = qla24xx_get_flash_version,
2503 .start_scsi = qlafx00_start_scsi,
d7459527 2504 .start_scsi_mq = NULL,
8ae6d9c7
GM		 2505 .abort_isp = qlafx00_abort_isp,
2506 .iospace_config = qlafx00_iospace_config,
2507 .initialize_adapter = qlafx00_initialize_adapter,
6246b8a1
GM		 2508};
2509
f73cb695
CD		 2510static struct isp_operations qla27xx_isp_ops = {
2511 .pci_config = qla25xx_pci_config,
2512 .reset_chip = qla24xx_reset_chip,
2513 .chip_diag = qla24xx_chip_diag,
2514 .config_rings = qla24xx_config_rings,
2515 .reset_adapter = qla24xx_reset_adapter,
2516 .nvram_config = qla81xx_nvram_config,
a36f1443 2517 .update_fw_options = qla24xx_update_fw_options,
f73cb695
CD		 2518 .load_risc = qla81xx_load_risc,
2519 .pci_info_str = qla24xx_pci_info_str,
2520 .fw_version_str = qla24xx_fw_version_str,
2521 .intr_handler = qla24xx_intr_handler,
2522 .enable_intrs = qla24xx_enable_intrs,
2523 .disable_intrs = qla24xx_disable_intrs,
2524 .abort_command = qla24xx_abort_command,
2525 .target_reset = qla24xx_abort_target,
2526 .lun_reset = qla24xx_lun_reset,
2527 .fabric_login = qla24xx_login_fabric,
2528 .fabric_logout = qla24xx_fabric_logout,
2529 .calc_req_entries = NULL,
2530 .build_iocbs = NULL,
2531 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2532 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2533 .read_nvram = NULL,
2534 .write_nvram = NULL,
2535 .fw_dump = qla27xx_fwdump,
2536 .beacon_on = qla24xx_beacon_on,
2537 .beacon_off = qla24xx_beacon_off,
2538 .beacon_blink = qla83xx_beacon_blink,
2539 .read_optrom = qla25xx_read_optrom_data,
2540 .write_optrom = qla24xx_write_optrom_data,
2541 .get_flash_version = qla24xx_get_flash_version,
2542 .start_scsi = qla24xx_dif_start_scsi,
d7459527 2543 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
f73cb695
CD		 2544 .abort_isp = qla2x00_abort_isp,
2545 .iospace_config = qla83xx_iospace_config,
2546 .initialize_adapter = qla2x00_initialize_adapter,
2547};
2548
ea5b6382 2549static inline void
e315cd28 2550qla2x00_set_isp_flags(struct qla_hw_data *ha)
ea5b6382 2551{
2552 ha->device_type = DT_EXTENDED_IDS;
2553 switch (ha->pdev->device) {
2554 case PCI_DEVICE_ID_QLOGIC_ISP2100:
9e052e2d 2555 ha->isp_type |= DT_ISP2100;
ea5b6382 2556 ha->device_type &= ~DT_EXTENDED_IDS;
441d1072 2557 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
ea5b6382 2558 break;
2559 case PCI_DEVICE_ID_QLOGIC_ISP2200:
9e052e2d 2560 ha->isp_type |= DT_ISP2200;
ea5b6382 2561 ha->device_type &= ~DT_EXTENDED_IDS;
441d1072 2562 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
ea5b6382 2563 break;
2564 case PCI_DEVICE_ID_QLOGIC_ISP2300:
9e052e2d 2565 ha->isp_type |= DT_ISP2300;
4a59f71d 2566 ha->device_type |= DT_ZIO_SUPPORTED;
441d1072 2567 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 2568 break;
2569 case PCI_DEVICE_ID_QLOGIC_ISP2312:
9e052e2d 2570 ha->isp_type |= DT_ISP2312;
4a59f71d 2571 ha->device_type |= DT_ZIO_SUPPORTED;
441d1072 2572 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 2573 break;
2574 case PCI_DEVICE_ID_QLOGIC_ISP2322:
9e052e2d 2575 ha->isp_type |= DT_ISP2322;
4a59f71d 2576 ha->device_type |= DT_ZIO_SUPPORTED;
ea5b6382 2577 if (ha->pdev->subsystem_vendor == 0x1028 &&
2578 ha->pdev->subsystem_device == 0x0170)
2579 ha->device_type |= DT_OEM_001;
441d1072 2580 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 2581 break;
2582 case PCI_DEVICE_ID_QLOGIC_ISP6312:
9e052e2d 2583 ha->isp_type |= DT_ISP6312;
441d1072 2584 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 2585 break;
2586 case PCI_DEVICE_ID_QLOGIC_ISP6322:
9e052e2d 2587 ha->isp_type |= DT_ISP6322;
441d1072 2588 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 2589 break;
2590 case PCI_DEVICE_ID_QLOGIC_ISP2422:
9e052e2d 2591 ha->isp_type |= DT_ISP2422;
4a59f71d 2592 ha->device_type |= DT_ZIO_SUPPORTED;
e428924c 2593 ha->device_type |= DT_FWI2;
c76f2c01 2594 ha->device_type |= DT_IIDMA;
441d1072 2595 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2596 break;
2597 case PCI_DEVICE_ID_QLOGIC_ISP2432:
9e052e2d 2598 ha->isp_type |= DT_ISP2432;
4a59f71d 2599 ha->device_type |= DT_ZIO_SUPPORTED;
e428924c 2600 ha->device_type |= DT_FWI2;
c76f2c01 2601 ha->device_type |= DT_IIDMA;
441d1072 2602 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2603 break;
4d4df193 2604 case PCI_DEVICE_ID_QLOGIC_ISP8432:
9e052e2d 2605 ha->isp_type |= DT_ISP8432;
4d4df193
HK		 2606 ha->device_type |= DT_ZIO_SUPPORTED;
2607 ha->device_type |= DT_FWI2;
2608 ha->device_type |= DT_IIDMA;
2609 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2610 break;
044cc6c8 2611 case PCI_DEVICE_ID_QLOGIC_ISP5422:
9e052e2d 2612 ha->isp_type |= DT_ISP5422;
e428924c 2613 ha->device_type |= DT_FWI2;
441d1072 2614 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2615 break;
044cc6c8 2616 case PCI_DEVICE_ID_QLOGIC_ISP5432:
9e052e2d 2617 ha->isp_type |= DT_ISP5432;
e428924c 2618 ha->device_type |= DT_FWI2;
441d1072 2619 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2620 break;
c3a2f0df 2621 case PCI_DEVICE_ID_QLOGIC_ISP2532:
9e052e2d 2622 ha->isp_type |= DT_ISP2532;
c3a2f0df
AV		 2623 ha->device_type |= DT_ZIO_SUPPORTED;
2624 ha->device_type |= DT_FWI2;
2625 ha->device_type |= DT_IIDMA;
441d1072 2626 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2627 break;
3a03eb79 2628 case PCI_DEVICE_ID_QLOGIC_ISP8001:
9e052e2d 2629 ha->isp_type |= DT_ISP8001;
3a03eb79
AV		 2630 ha->device_type |= DT_ZIO_SUPPORTED;
2631 ha->device_type |= DT_FWI2;
2632 ha->device_type |= DT_IIDMA;
2633 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2634 break;
a9083016 2635 case PCI_DEVICE_ID_QLOGIC_ISP8021:
9e052e2d 2636 ha->isp_type |= DT_ISP8021;
a9083016
GM		 2637 ha->device_type |= DT_ZIO_SUPPORTED;
2638 ha->device_type |= DT_FWI2;
2639 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2640 /* Initialize 82XX ISP flags */
2641 qla82xx_init_flags(ha);
2642 break;
7ec0effd 2643 case PCI_DEVICE_ID_QLOGIC_ISP8044:
9e052e2d 2644 ha->isp_type |= DT_ISP8044;
7ec0effd
AD		 2645 ha->device_type |= DT_ZIO_SUPPORTED;
2646 ha->device_type |= DT_FWI2;
2647 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2648 /* Initialize 82XX ISP flags */
2649 qla82xx_init_flags(ha);
2650 break;
6246b8a1 2651 case PCI_DEVICE_ID_QLOGIC_ISP2031:
9e052e2d 2652 ha->isp_type |= DT_ISP2031;
6246b8a1
GM		 2653 ha->device_type |= DT_ZIO_SUPPORTED;
2654 ha->device_type |= DT_FWI2;
2655 ha->device_type |= DT_IIDMA;
2656 ha->device_type |= DT_T10_PI;
2657 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2658 break;
2659 case PCI_DEVICE_ID_QLOGIC_ISP8031:
9e052e2d 2660 ha->isp_type |= DT_ISP8031;
6246b8a1
GM		 2661 ha->device_type |= DT_ZIO_SUPPORTED;
2662 ha->device_type |= DT_FWI2;
2663 ha->device_type |= DT_IIDMA;
2664 ha->device_type |= DT_T10_PI;
2665 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2666 break;
8ae6d9c7 2667 case PCI_DEVICE_ID_QLOGIC_ISPF001:
9e052e2d 2668 ha->isp_type |= DT_ISPFX00;
8ae6d9c7 2669 break;
f73cb695 2670 case PCI_DEVICE_ID_QLOGIC_ISP2071:
9e052e2d 2671 ha->isp_type |= DT_ISP2071;
f73cb695
CD		 2672 ha->device_type |= DT_ZIO_SUPPORTED;
2673 ha->device_type |= DT_FWI2;
2674 ha->device_type |= DT_IIDMA;
8ce3f570 2675 ha->device_type |= DT_T10_PI;
f73cb695
CD		 2676 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2677 break;
2c5bbbb2 2678 case PCI_DEVICE_ID_QLOGIC_ISP2271:
9e052e2d 2679 ha->isp_type |= DT_ISP2271;
2c5bbbb2
JC		 2680 ha->device_type |= DT_ZIO_SUPPORTED;
2681 ha->device_type |= DT_FWI2;
2682 ha->device_type |= DT_IIDMA;
8ce3f570 2683 ha->device_type |= DT_T10_PI;
2c5bbbb2
JC		 2684 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2685 break;
2b48992f 2686 case PCI_DEVICE_ID_QLOGIC_ISP2261:
9e052e2d 2687 ha->isp_type |= DT_ISP2261;
2b48992f
SC		 2688 ha->device_type |= DT_ZIO_SUPPORTED;
2689 ha->device_type |= DT_FWI2;
2690 ha->device_type |= DT_IIDMA;
8ce3f570 2691 ha->device_type |= DT_T10_PI;
2b48992f
SC		 2692 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2693 break;
ecc89f25
JC		 2694 case PCI_DEVICE_ID_QLOGIC_ISP2081:
2695 case PCI_DEVICE_ID_QLOGIC_ISP2089:
2696 ha->isp_type |= DT_ISP2081;
2697 ha->device_type |= DT_ZIO_SUPPORTED;
2698 ha->device_type |= DT_FWI2;
2699 ha->device_type |= DT_IIDMA;
2700 ha->device_type |= DT_T10_PI;
2701 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2702 break;
2703 case PCI_DEVICE_ID_QLOGIC_ISP2281:
2704 case PCI_DEVICE_ID_QLOGIC_ISP2289:
2705 ha->isp_type |= DT_ISP2281;
2706 ha->device_type |= DT_ZIO_SUPPORTED;
2707 ha->device_type |= DT_FWI2;
2708 ha->device_type |= DT_IIDMA;
2709 ha->device_type |= DT_T10_PI;
2710 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2711 break;
ea5b6382 2712 }
e5b68a61 2713
a9083016 2714 if (IS_QLA82XX(ha))
43a9c38b 2715 ha->port_no = ha->portnum & 1;
f73cb695 2716 else {
a9083016
GM		 2717 /* Get adapter physical port no from interrupt pin register. */
2718 pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no);
ecc89f25
JC		 2719 if (IS_QLA25XX(ha) || IS_QLA2031(ha) ||
2720 IS_QLA27XX(ha) || IS_QLA28XX(ha))
f73cb695
CD		 2721 ha->port_no--;
2722 else
2723 ha->port_no = !(ha->port_no & 1);
2724 }
a9083016 2725
7c3df132 2726 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b,
d8424f68 2727 "device_type=0x%x port=%d fw_srisc_address=0x%x.\n",
f73cb695 2728 ha->device_type, ha->port_no, ha->fw_srisc_address);
ea5b6382 2729}
2730
1e99e33a
AV		 2731static void
2732qla2xxx_scan_start(struct Scsi_Host *shost)
2733{
e315cd28 2734 scsi_qla_host_t *vha = shost_priv(shost);
1e99e33a 2735
cbc8eb67
AV		 2736 if (vha->hw->flags.running_gold_fw)
2737 return;
2738
e315cd28
AC		 2739 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
2740 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
2741 set_bit(RSCN_UPDATE, &vha->dpc_flags);
2742 set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags);
1e99e33a
AV		 2743}
2744
2745static int
2746qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time)
2747{
e315cd28 2748 scsi_qla_host_t *vha = shost_priv(shost);
1e99e33a 2749
a5dd506e
BK		 2750 if (test_bit(UNLOADING, &vha->dpc_flags))
2751 return 1;
e315cd28 2752 if (!vha->host)
1e99e33a 2753 return 1;
e315cd28 2754 if (time > vha->hw->loop_reset_delay * HZ)
1e99e33a
AV		 2755 return 1;
2756
e315cd28 2757 return atomic_read(&vha->loop_state) == LOOP_READY;
1e99e33a
AV		 2758}
2759
ec7193e2
QT		 2760static void qla2x00_iocb_work_fn(struct work_struct *work)
2761{
2762 struct scsi_qla_host *vha = container_of(work,
2763 struct scsi_qla_host, iocb_work);
9b3e0f4d
QT		 2764 struct qla_hw_data *ha = vha->hw;
2765 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
0aca7784 2766 int i = 2;
9b3e0f4d
QT		 2767 unsigned long flags;
2768
2769 if (test_bit(UNLOADING, &base_vha->dpc_flags))
2770 return;
ec7193e2 2771
9b3e0f4d 2772 while (!list_empty(&vha->work_list) && i > 0) {
ec7193e2 2773 qla2x00_do_work(vha);
9b3e0f4d 2774 i--;
ec7193e2 2775 }
9b3e0f4d
QT		 2776
2777 spin_lock_irqsave(&vha->work_lock, flags);
2778 clear_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags);
2779 spin_unlock_irqrestore(&vha->work_lock, flags);
ec7193e2
QT		 2780}
2781
1da177e4
LT		 2782/*
2783 * PCI driver interface
2784 */
6f039790 2785static int
7ee61397 2786qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
1da177e4 2787{
a1541d5a 2788 int ret = -ENODEV;
1da177e4 2789 struct Scsi_Host *host;
e315cd28
AC		 2790 scsi_qla_host_t *base_vha = NULL;
2791 struct qla_hw_data *ha;
29856e28 2792 char pci_info[30];
7d613ac6 2793 char fw_str[30], wq_name[30];
5433383e 2794 struct scsi_host_template *sht;
642ef983 2795 int bars, mem_only = 0;
e315cd28 2796 uint16_t req_length = 0, rsp_length = 0;
73208dfd
AC		 2797 struct req_que *req = NULL;
2798 struct rsp_que *rsp = NULL;
5601236b 2799 int i;
d7459527 2800
285d0321 2801 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO);
a5326f86 2802 sht = &qla2xxx_driver_template;
5433383e 2803 if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 ||
8bc69e7d 2804 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 ||
4d4df193 2805 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 ||
8bc69e7d 2806 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 ||
c3a2f0df 2807 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 ||
3a03eb79 2808 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 ||
a9083016 2809 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 ||
6246b8a1
GM		 2810 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021 ||
2811 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2031 ||
8ae6d9c7 2812 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8031 ||
7ec0effd 2813 pdev->device == PCI_DEVICE_ID_QLOGIC_ISPF001 ||
f73cb695 2814 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8044 ||
2c5bbbb2 2815 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2071 ||
2b48992f 2816 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2271 ||
ecc89f25
JC		 2817 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2261 ||
2818 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2081 ||
2819 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2281 ||
2820 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2089 ||
2821 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2289) {
285d0321 2822 bars = pci_select_bars(pdev, IORESOURCE_MEM);
09483916 2823 mem_only = 1;
7c3df132
SK		 2824 ql_dbg_pci(ql_dbg_init, pdev, 0x0007,
2825 "Mem only adapter.\n");
285d0321 2826 }
7c3df132
SK		 2827 ql_dbg_pci(ql_dbg_init, pdev, 0x0008,
2828 "Bars=%d.\n", bars);
285d0321 2829
09483916
BH		 2830 if (mem_only) {
2831 if (pci_enable_device_mem(pdev))
ddff7ed4 2832 return ret;
09483916
BH		 2833 } else {
2834 if (pci_enable_device(pdev))
ddff7ed4 2835 return ret;
09483916 2836 }
285d0321 2837
0927678f
JB		 2838 /* This may fail but that's ok */
2839 pci_enable_pcie_error_reporting(pdev);
285d0321 2840
5da05a26
GM		 2841 /* Turn off T10-DIF when FC-NVMe is enabled */
2842 if (ql2xnvmeenable)
2843 ql2xenabledif = 0;
2844
e315cd28
AC		 2845 ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL);
2846 if (!ha) {
7c3df132
SK		 2847 ql_log_pci(ql_log_fatal, pdev, 0x0009,
2848 "Unable to allocate memory for ha.\n");
ddff7ed4 2849 goto disable_device;
1da177e4 2850 }
7c3df132
SK		 2851 ql_dbg_pci(ql_dbg_init, pdev, 0x000a,
2852 "Memory allocated for ha=%p.\n", ha);
e315cd28 2853 ha->pdev = pdev;
33e79977
QT		 2854 INIT_LIST_HEAD(&ha->tgt.q_full_list);
2855 spin_lock_init(&ha->tgt.q_full_lock);
7560151b 2856 spin_lock_init(&ha->tgt.sess_lock);
2f424b9b
QT		 2857 spin_lock_init(&ha->tgt.atio_lock);
2858
deeae7a6 2859 atomic_set(&ha->nvme_active_aen_cnt, 0);
1da177e4
LT		 2860
2861 /* Clear our data area */
285d0321 2862 ha->bars = bars;
09483916 2863 ha->mem_only = mem_only;
df4bf0bb 2864 spin_lock_init(&ha->hardware_lock);
339aa70e 2865 spin_lock_init(&ha->vport_slock);
a9b6f722 2866 mutex_init(&ha->selflogin_lock);
7a8ab9c8 2867 mutex_init(&ha->optrom_mutex);
1da177e4 2868
ea5b6382 2869 /* Set ISP-type information. */
2870 qla2x00_set_isp_flags(ha);
ca79cf66
DG		 2871
2872 /* Set EEH reset type to fundamental if required by hba */
95676112 2873 if (IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha) ||
ecc89f25 2874 IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))
ca79cf66 2875 pdev->needs_freset = 1;
ca79cf66 2876
cba1e47f
CD		 2877 ha->prev_topology = 0;
2878 ha->init_cb_size = sizeof(init_cb_t);
2879 ha->link_data_rate = PORT_SPEED_UNKNOWN;
2880 ha->optrom_size = OPTROM_SIZE_2300;
d1e3635a 2881 ha->max_exchg = FW_MAX_EXCHANGES_CNT;
b2000805
QT		 2882 atomic_set(&ha->num_pend_mbx_stage1, 0);
2883 atomic_set(&ha->num_pend_mbx_stage2, 0);
2884 atomic_set(&ha->num_pend_mbx_stage3, 0);
8b4673ba
QT		 2885 atomic_set(&ha->zio_threshold, DEFAULT_ZIO_THRESHOLD);
2886 ha->last_zio_threshold = DEFAULT_ZIO_THRESHOLD;
cba1e47f 2887
abbd8870 2888 /* Assign ISP specific operations. */
1da177e4 2889 if (IS_QLA2100(ha)) {
642ef983 2890 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
1da177e4 2891 ha->mbx_count = MAILBOX_REGISTER_COUNT_2100;
e315cd28
AC		 2892 req_length = REQUEST_ENTRY_CNT_2100;
2893 rsp_length = RESPONSE_ENTRY_CNT_2100;
2894 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
abbd8870 2895 ha->gid_list_info_size = 4;
3a03eb79
AV		 2896 ha->flash_conf_off = ~0;
2897 ha->flash_data_off = ~0;
2898 ha->nvram_conf_off = ~0;
2899 ha->nvram_data_off = ~0;
fd34f556 2900 ha->isp_ops = &qla2100_isp_ops;
1da177e4 2901 } else if (IS_QLA2200(ha)) {
642ef983 2902 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
67ddda35 2903 ha->mbx_count = MAILBOX_REGISTER_COUNT_2200;
e315cd28
AC		 2904 req_length = REQUEST_ENTRY_CNT_2200;
2905 rsp_length = RESPONSE_ENTRY_CNT_2100;
2906 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
abbd8870 2907 ha->gid_list_info_size = 4;
3a03eb79
AV		 2908 ha->flash_conf_off = ~0;
2909 ha->flash_data_off = ~0;
2910 ha->nvram_conf_off = ~0;
2911 ha->nvram_data_off = ~0;
fd34f556 2912 ha->isp_ops = &qla2100_isp_ops;
fca29703 2913 } else if (IS_QLA23XX(ha)) {
642ef983 2914 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
1da177e4 2915 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2916 req_length = REQUEST_ENTRY_CNT_2200;
2917 rsp_length = RESPONSE_ENTRY_CNT_2300;
2918 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
abbd8870 2919 ha->gid_list_info_size = 6;
854165f4 2920 if (IS_QLA2322(ha) || IS_QLA6322(ha))
2921 ha->optrom_size = OPTROM_SIZE_2322;
3a03eb79
AV		 2922 ha->flash_conf_off = ~0;
2923 ha->flash_data_off = ~0;
2924 ha->nvram_conf_off = ~0;
2925 ha->nvram_data_off = ~0;
fd34f556 2926 ha->isp_ops = &qla2300_isp_ops;
4d4df193 2927 } else if (IS_QLA24XX_TYPE(ha)) {
642ef983 2928 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
fca29703 2929 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2930 req_length = REQUEST_ENTRY_CNT_24XX;
2931 rsp_length = RESPONSE_ENTRY_CNT_2300;
2d70c103 2932 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
e315cd28 2933 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2c3dfe3f 2934 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
fca29703 2935 ha->gid_list_info_size = 8;
854165f4 2936 ha->optrom_size = OPTROM_SIZE_24XX;
73208dfd 2937 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX;
fd34f556 2938 ha->isp_ops = &qla24xx_isp_ops;
3a03eb79
AV		 2939 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2940 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2941 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2942 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
c3a2f0df 2943 } else if (IS_QLA25XX(ha)) {
642ef983 2944 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
c3a2f0df 2945 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2946 req_length = REQUEST_ENTRY_CNT_24XX;
2947 rsp_length = RESPONSE_ENTRY_CNT_2300;
2d70c103 2948 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
e315cd28 2949 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
c3a2f0df 2950 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
c3a2f0df
AV		 2951 ha->gid_list_info_size = 8;
2952 ha->optrom_size = OPTROM_SIZE_25XX;
73208dfd 2953 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
c3a2f0df 2954 ha->isp_ops = &qla25xx_isp_ops;
3a03eb79
AV		 2955 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2956 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2957 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2958 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
2959 } else if (IS_QLA81XX(ha)) {
642ef983 2960 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3a03eb79
AV		 2961 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2962 req_length = REQUEST_ENTRY_CNT_24XX;
2963 rsp_length = RESPONSE_ENTRY_CNT_2300;
aa230bc5 2964 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
3a03eb79
AV		 2965 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2966 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2967 ha->gid_list_info_size = 8;
2968 ha->optrom_size = OPTROM_SIZE_81XX;
40859ae5 2969 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3a03eb79
AV		 2970 ha->isp_ops = &qla81xx_isp_ops;
2971 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2972 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2973 ha->nvram_conf_off = ~0;
2974 ha->nvram_data_off = ~0;
a9083016 2975 } else if (IS_QLA82XX(ha)) {
642ef983 2976 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
a9083016
GM		 2977 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2978 req_length = REQUEST_ENTRY_CNT_82XX;
2979 rsp_length = RESPONSE_ENTRY_CNT_82XX;
2980 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2981 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2982 ha->gid_list_info_size = 8;
2983 ha->optrom_size = OPTROM_SIZE_82XX;
087c621e 2984 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
a9083016
GM		 2985 ha->isp_ops = &qla82xx_isp_ops;
2986 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2987 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2988 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2989 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
7ec0effd
AD		 2990 } else if (IS_QLA8044(ha)) {
2991 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2992 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2993 req_length = REQUEST_ENTRY_CNT_82XX;
2994 rsp_length = RESPONSE_ENTRY_CNT_82XX;
2995 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2996 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2997 ha->gid_list_info_size = 8;
2998 ha->optrom_size = OPTROM_SIZE_83XX;
2999 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3000 ha->isp_ops = &qla8044_isp_ops;
3001 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
3002 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
3003 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
3004 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
6246b8a1 3005 } else if (IS_QLA83XX(ha)) {
7d613ac6 3006 ha->portnum = PCI_FUNC(ha->pdev->devfn);
642ef983 3007 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
6246b8a1 3008 ha->mbx_count = MAILBOX_REGISTER_COUNT;
f2ea653f 3009 req_length = REQUEST_ENTRY_CNT_83XX;
e7b42e33 3010 rsp_length = RESPONSE_ENTRY_CNT_83XX;
b8aa4bdf 3011 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
6246b8a1
GM		 3012 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
3013 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
3014 ha->gid_list_info_size = 8;
3015 ha->optrom_size = OPTROM_SIZE_83XX;
3016 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3017 ha->isp_ops = &qla83xx_isp_ops;
3018 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
3019 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
3020 ha->nvram_conf_off = ~0;
3021 ha->nvram_data_off = ~0;
8ae6d9c7
GM		 3022 } else if (IS_QLAFX00(ha)) {
3023 ha->max_fibre_devices = MAX_FIBRE_DEVICES_FX00;
3024 ha->mbx_count = MAILBOX_REGISTER_COUNT_FX00;
3025 ha->aen_mbx_count = AEN_MAILBOX_REGISTER_COUNT_FX00;
3026 req_length = REQUEST_ENTRY_CNT_FX00;
3027 rsp_length = RESPONSE_ENTRY_CNT_FX00;
8ae6d9c7
GM		 3028 ha->isp_ops = &qlafx00_isp_ops;
3029 ha->port_down_retry_count = 30; /* default value */
3030 ha->mr.fw_hbt_cnt = QLAFX00_HEARTBEAT_INTERVAL;
3031 ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL;
71e56003 3032 ha->mr.fw_critemp_timer_tick = QLAFX00_CRITEMP_INTERVAL;
8ae6d9c7 3033 ha->mr.fw_hbt_en = 1;
e8f5e95d
AB		 3034 ha->mr.host_info_resend = false;
3035 ha->mr.hinfo_resend_timer_tick = QLAFX00_HINFO_RESEND_INTERVAL;
f73cb695
CD		 3036 } else if (IS_QLA27XX(ha)) {
3037 ha->portnum = PCI_FUNC(ha->pdev->devfn);
3038 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3039 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e7b42e33
QT		 3040 req_length = REQUEST_ENTRY_CNT_83XX;
3041 rsp_length = RESPONSE_ENTRY_CNT_83XX;
b20f02e1 3042 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
f73cb695
CD		 3043 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
3044 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
3045 ha->gid_list_info_size = 8;
3046 ha->optrom_size = OPTROM_SIZE_83XX;
3047 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3048 ha->isp_ops = &qla27xx_isp_ops;
3049 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
3050 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
3051 ha->nvram_conf_off = ~0;
3052 ha->nvram_data_off = ~0;
ecc89f25
JC		 3053 } else if (IS_QLA28XX(ha)) {
3054 ha->portnum = PCI_FUNC(ha->pdev->devfn);
3055 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3056 ha->mbx_count = MAILBOX_REGISTER_COUNT;
3057 req_length = REQUEST_ENTRY_CNT_24XX;
3058 rsp_length = RESPONSE_ENTRY_CNT_2300;
3059 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
3060 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
3061 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
3062 ha->gid_list_info_size = 8;
3063 ha->optrom_size = OPTROM_SIZE_28XX;
3064 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3065 ha->isp_ops = &qla27xx_isp_ops;
3066 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_28XX;
3067 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_28XX;
3068 ha->nvram_conf_off = ~0;
3069 ha->nvram_data_off = ~0;
1da177e4 3070 }
6246b8a1 3071
7c3df132
SK		 3072 ql_dbg_pci(ql_dbg_init, pdev, 0x001e,
3073 "mbx_count=%d, req_length=%d, "
3074 "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, "
642ef983
CD		 3075 "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, "
3076 "max_fibre_devices=%d.\n",
7c3df132
SK		 3077 ha->mbx_count, req_length, rsp_length, ha->max_loop_id,
3078 ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size,
642ef983 3079 ha->nvram_npiv_size, ha->max_fibre_devices);
7c3df132
SK		 3080 ql_dbg_pci(ql_dbg_init, pdev, 0x001f,
3081 "isp_ops=%p, flash_conf_off=%d, "
3082 "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n",
3083 ha->isp_ops, ha->flash_conf_off, ha->flash_data_off,
3084 ha->nvram_conf_off, ha->nvram_data_off);
706f457d
GM		 3085
3086 /* Configure PCI I/O space */
3087 ret = ha->isp_ops->iospace_config(ha);
3088 if (ret)
0a63ad12 3089 goto iospace_config_failed;
706f457d
GM		 3090
3091 ql_log_pci(ql_log_info, pdev, 0x001d,
3092 "Found an ISP%04X irq %d iobase 0x%p.\n",
3093 pdev->device, pdev->irq, ha->iobase);
6c2f527c 3094 mutex_init(&ha->vport_lock);
d7459527 3095 mutex_init(&ha->mq_lock);
0b05a1f0
MB		 3096 init_completion(&ha->mbx_cmd_comp);
3097 complete(&ha->mbx_cmd_comp);
3098 init_completion(&ha->mbx_intr_comp);
23f2ebd1 3099 init_completion(&ha->dcbx_comp);
f356bef1 3100 init_completion(&ha->lb_portup_comp);
1da177e4 3101
2c3dfe3f 3102 set_bit(0, (unsigned long *) ha->vp_idx_map);
1da177e4 3103
53303c42 3104 qla2x00_config_dma_addressing(ha);
7c3df132
SK		 3105 ql_dbg_pci(ql_dbg_init, pdev, 0x0020,
3106 "64 Bit addressing is %s.\n",
3107 ha->flags.enable_64bit_addressing ? "enable" :
3108 "disable");
73208dfd 3109 ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp);
b2a72ec3 3110 if (ret) {
7c3df132
SK		 3111 ql_log_pci(ql_log_fatal, pdev, 0x0031,
3112 "Failed to allocate memory for adapter, aborting.\n");
1da177e4 3113
e315cd28
AC		 3114 goto probe_hw_failed;
3115 }
3116
73208dfd 3117 req->max_q_depth = MAX_Q_DEPTH;
e315cd28 3118 if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU)
73208dfd
AC		 3119 req->max_q_depth = ql2xmaxqdepth;
3120
e315cd28
AC		 3121
3122 base_vha = qla2x00_create_host(sht, ha);
3123 if (!base_vha) {
a1541d5a 3124 ret = -ENOMEM;
e315cd28 3125 goto probe_hw_failed;
1da177e4
LT		 3126 }
3127
e315cd28 3128 pci_set_drvdata(pdev, base_vha);
6b383979 3129 set_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags);
e315cd28 3130
e315cd28 3131 host = base_vha->host;
2afa19a9 3132 base_vha->req = req;
73208dfd 3133 if (IS_QLA2XXX_MIDTYPE(ha))
f6602f3b
QT		 3134 base_vha->mgmt_svr_loop_id =
3135 qla2x00_reserve_mgmt_server_loop_id(base_vha);
73208dfd 3136 else
e315cd28
AC		 3137 base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER +
3138 base_vha->vp_idx;
58548cb5 3139
8ae6d9c7
GM		 3140 /* Setup fcport template structure. */
3141 ha->mr.fcport.vha = base_vha;
3142 ha->mr.fcport.port_type = FCT_UNKNOWN;
3143 ha->mr.fcport.loop_id = FC_NO_LOOP_ID;
3144 qla2x00_set_fcport_state(&ha->mr.fcport, FCS_UNCONFIGURED);
3145 ha->mr.fcport.supported_classes = FC_COS_UNSPECIFIED;
3146 ha->mr.fcport.scan_state = 1;
3147
58548cb5
GM		 3148 /* Set the SG table size based on ISP type */
3149 if (!IS_FWI2_CAPABLE(ha)) {
3150 if (IS_QLA2100(ha))
3151 host->sg_tablesize = 32;
3152 } else {
3153 if (!IS_QLA82XX(ha))
3154 host->sg_tablesize = QLA_SG_ALL;
3155 }
642ef983 3156 host->max_id = ha->max_fibre_devices;
e315cd28
AC		 3157 host->cmd_per_lun = 3;
3158 host->unique_id = host->host_no;
e02587d7 3159 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif)
0c470874
AE		 3160 host->max_cmd_len = 32;
3161 else
3162 host->max_cmd_len = MAX_CMDSZ;
e315cd28 3163 host->max_channel = MAX_BUSES - 1;
755f516b
HR		 3164 /* Older HBAs support only 16-bit LUNs */
3165 if (!IS_QLAFX00(ha) && !IS_FWI2_CAPABLE(ha) &&
3166 ql2xmaxlun > 0xffff)
3167 host->max_lun = 0xffff;
3168 else
3169 host->max_lun = ql2xmaxlun;
e315cd28 3170 host->transportt = qla2xxx_transport_template;
9a069e19 3171 sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC);
e315cd28 3172
7c3df132
SK		 3173 ql_dbg(ql_dbg_init, base_vha, 0x0033,
3174 "max_id=%d this_id=%d "
3175 "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d "
1abf635d 3176 "max_lun=%llu transportt=%p, vendor_id=%llu.\n", host->max_id,
7c3df132
SK		 3177 host->this_id, host->cmd_per_lun, host->unique_id,
3178 host->max_cmd_len, host->max_channel, host->max_lun,
3179 host->transportt, sht->vendor_id);
3180
1010f21e
HM		 3181 INIT_WORK(&base_vha->iocb_work, qla2x00_iocb_work_fn);
3182
d7459527
MH		 3183 /* Set up the irqs */
3184 ret = qla2x00_request_irqs(ha, rsp);
3185 if (ret)
6a2cf8d3 3186 goto probe_failed;
d7459527 3187
9a347ff4 3188 /* Alloc arrays of request and response ring ptrs */
6d634067
BK		 3189 ret = qla2x00_alloc_queues(ha, req, rsp);
3190 if (ret) {
9a347ff4
CD		 3191 ql_log(ql_log_fatal, base_vha, 0x003d,
3192 "Failed to allocate memory for queue pointers..."
3193 "aborting.\n");
26a77799 3194 ret = -ENODEV;
6a2cf8d3 3195 goto probe_failed;
9a347ff4
CD		 3196 }
3197
f664a3cc 3198 if (ha->mqenable) {
5601236b
MH		 3199 /* number of hardware queues supported by blk/scsi-mq*/
3200 host->nr_hw_queues = ha->max_qpairs;
3201
3202 ql_dbg(ql_dbg_init, base_vha, 0x0192,
3203 "blk/scsi-mq enabled, HW queues = %d.\n", host->nr_hw_queues);
c38d1baf
HM		 3204 } else {
3205 if (ql2xnvmeenable) {
3206 host->nr_hw_queues = ha->max_qpairs;
3207 ql_dbg(ql_dbg_init, base_vha, 0x0194,
3208 "FC-NVMe support is enabled, HW queues=%d\n",
3209 host->nr_hw_queues);
3210 } else {
3211 ql_dbg(ql_dbg_init, base_vha, 0x0193,
3212 "blk/scsi-mq disabled.\n");
3213 }
3214 }
5601236b 3215
2d70c103 3216 qlt_probe_one_stage1(base_vha, ha);
9a347ff4 3217
90a86fc0
JC		 3218 pci_save_state(pdev);
3219
9a347ff4 3220 /* Assign back pointers */
2afa19a9
AC		 3221 rsp->req = req;
3222 req->rsp = rsp;
9a347ff4 3223
8ae6d9c7
GM		 3224 if (IS_QLAFX00(ha)) {
3225 ha->rsp_q_map[0] = rsp;
3226 ha->req_q_map[0] = req;
3227 set_bit(0, ha->req_qid_map);
3228 set_bit(0, ha->rsp_qid_map);
3229 }
3230
08029990
AV		 3231 /* FWI2-capable only. */
3232 req->req_q_in = &ha->iobase->isp24.req_q_in;
3233 req->req_q_out = &ha->iobase->isp24.req_q_out;
3234 rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in;
3235 rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out;
ecc89f25
JC		 3236 if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha) ||
3237 IS_QLA28XX(ha)) {
08029990
AV		 3238 req->req_q_in = &ha->mqiobase->isp25mq.req_q_in;
3239 req->req_q_out = &ha->mqiobase->isp25mq.req_q_out;
3240 rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in;
3241 rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out;
17d98630
AC		 3242 }
3243
8ae6d9c7
GM		 3244 if (IS_QLAFX00(ha)) {
3245 req->req_q_in = &ha->iobase->ispfx00.req_q_in;
3246 req->req_q_out = &ha->iobase->ispfx00.req_q_out;
3247 rsp->rsp_q_in = &ha->iobase->ispfx00.rsp_q_in;
3248 rsp->rsp_q_out = &ha->iobase->ispfx00.rsp_q_out;
3249 }
3250
7ec0effd 3251 if (IS_P3P_TYPE(ha)) {
a9083016
GM		 3252 req->req_q_out = &ha->iobase->isp82.req_q_out[0];
3253 rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0];
3254 rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0];
3255 }
3256
7c3df132
SK		 3257 ql_dbg(ql_dbg_multiq, base_vha, 0xc009,
3258 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
3259 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
3260 ql_dbg(ql_dbg_multiq, base_vha, 0xc00a,
3261 "req->req_q_in=%p req->req_q_out=%p "
3262 "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
3263 req->req_q_in, req->req_q_out,
3264 rsp->rsp_q_in, rsp->rsp_q_out);
3265 ql_dbg(ql_dbg_init, base_vha, 0x003e,
3266 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
3267 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
3268 ql_dbg(ql_dbg_init, base_vha, 0x003f,
3269 "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
3270 req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out);
1da177e4 3271
d48cc67c 3272 ha->wq = alloc_workqueue("qla2xxx_wq", 0, 0);
3273
8ae6d9c7 3274 if (ha->isp_ops->initialize_adapter(base_vha)) {
7c3df132
SK		 3275 ql_log(ql_log_fatal, base_vha, 0x00d6,
3276 "Failed to initialize adapter - Adapter flags %x.\n",
3277 base_vha->device_flags);
1da177e4 3278
a9083016
GM		 3279 if (IS_QLA82XX(ha)) {
3280 qla82xx_idc_lock(ha);
3281 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 3282 QLA8XXX_DEV_FAILED);
a9083016 3283 qla82xx_idc_unlock(ha);
7c3df132
SK		 3284 ql_log(ql_log_fatal, base_vha, 0x00d7,
3285 "HW State: FAILED.\n");
7ec0effd
AD		 3286 } else if (IS_QLA8044(ha)) {
3287 qla8044_idc_lock(ha);
3288 qla8044_wr_direct(base_vha,
3289 QLA8044_CRB_DEV_STATE_INDEX,
3290 QLA8XXX_DEV_FAILED);
3291 qla8044_idc_unlock(ha);
3292 ql_log(ql_log_fatal, base_vha, 0x0150,
3293 "HW State: FAILED.\n");
a9083016
GM		 3294 }
3295
a1541d5a 3296 ret = -ENODEV;
1da177e4
LT		 3297 goto probe_failed;
3298 }
3299
3b1bef64
CD		 3300 if (IS_QLAFX00(ha))
3301 host->can_queue = QLAFX00_MAX_CANQUEUE;
3302 else
3303 host->can_queue = req->num_outstanding_cmds - 10;
3304
3305 ql_dbg(ql_dbg_init, base_vha, 0x0032,
3306 "can_queue=%d, req=%p, mgmt_svr_loop_id=%d, sg_tablesize=%d.\n",
3307 host->can_queue, base_vha->req,
3308 base_vha->mgmt_svr_loop_id, host->sg_tablesize);
3309
e326d22a 3310 if (ha->mqenable) {
e326d22a 3311 bool startit = false;
e326d22a 3312
f664a3cc 3313 if (QLA_TGT_MODE_ENABLED())
e326d22a 3314 startit = false;
e326d22a 3315
f664a3cc 3316 if (ql2x_ini_mode == QLA2XXX_INI_MODE_ENABLED)
e326d22a 3317 startit = true;
e326d22a 3318
f664a3cc
JA		 3319 /* Create start of day qpairs for Block MQ */
3320 for (i = 0; i < ha->max_qpairs; i++)
3321 qla2xxx_create_qpair(base_vha, 5, 0, startit);
5601236b 3322 }
68ca949c 3323
cbc8eb67
AV		 3324 if (ha->flags.running_gold_fw)
3325 goto skip_dpc;
3326
1da177e4
LT		 3327 /*
3328 * Startup the kernel thread for this host adapter
3329 */
39a11240 3330 ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha,
7c3df132 3331 "%s_dpc", base_vha->host_str);
39a11240 3332 if (IS_ERR(ha->dpc_thread)) {
7c3df132
SK		 3333 ql_log(ql_log_fatal, base_vha, 0x00ed,
3334 "Failed to start DPC thread.\n");
39a11240 3335 ret = PTR_ERR(ha->dpc_thread);
e2532b4a 3336 ha->dpc_thread = NULL;
1da177e4
LT		 3337 goto probe_failed;
3338 }
7c3df132
SK		 3339 ql_dbg(ql_dbg_init, base_vha, 0x00ee,
3340 "DPC thread started successfully.\n");
1da177e4 3341
2d70c103
NB		 3342 /*
3343 * If we're not coming up in initiator mode, we might sit for
3344 * a while without waking up the dpc thread, which leads to a
3345 * stuck process warning. So just kick the dpc once here and
3346 * let the kthread start (and go back to sleep in qla2x00_do_dpc).
3347 */
3348 qla2xxx_wake_dpc(base_vha);
3349
f3ddac19
CD		 3350 INIT_WORK(&ha->board_disable, qla2x00_disable_board_on_pci_error);
3351
81178772
SK		 3352 if (IS_QLA8031(ha) || IS_MCTP_CAPABLE(ha)) {
3353 sprintf(wq_name, "qla2xxx_%lu_dpc_lp_wq", base_vha->host_no);
3354 ha->dpc_lp_wq = create_singlethread_workqueue(wq_name);
3355 INIT_WORK(&ha->idc_aen, qla83xx_service_idc_aen);
3356
3357 sprintf(wq_name, "qla2xxx_%lu_dpc_hp_wq", base_vha->host_no);
3358 ha->dpc_hp_wq = create_singlethread_workqueue(wq_name);
3359 INIT_WORK(&ha->nic_core_reset, qla83xx_nic_core_reset_work);
3360 INIT_WORK(&ha->idc_state_handler,
3361 qla83xx_idc_state_handler_work);
3362 INIT_WORK(&ha->nic_core_unrecoverable,
3363 qla83xx_nic_core_unrecoverable_work);
3364 }
3365
cbc8eb67 3366skip_dpc:
e315cd28
AC		 3367 list_add_tail(&base_vha->list, &ha->vp_list);
3368 base_vha->host->irq = ha->pdev->irq;
1da177e4
LT		 3369
3370 /* Initialized the timer */
8e5f4ba0 3371 qla2x00_start_timer(base_vha, WATCH_INTERVAL);
7c3df132
SK		 3372 ql_dbg(ql_dbg_init, base_vha, 0x00ef,
3373 "Started qla2x00_timer with "
3374 "interval=%d.\n", WATCH_INTERVAL);
3375 ql_dbg(ql_dbg_init, base_vha, 0x00f0,
3376 "Detected hba at address=%p.\n",
3377 ha);
d19044c3 3378
e02587d7 3379 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) {
bad75002 3380 if (ha->fw_attributes & BIT_4) {
9e522cd8 3381 int prot = 0, guard;
bd432bb5 3382
bad75002 3383 base_vha->flags.difdix_supported = 1;
7c3df132
SK		 3384 ql_dbg(ql_dbg_init, base_vha, 0x00f1,
3385 "Registering for DIF/DIX type 1 and 3 protection.\n");
8cb2049c
AE		 3386 if (ql2xenabledif == 1)
3387 prot = SHOST_DIX_TYPE0_PROTECTION;
7855d2ba
MP		 3388 if (ql2xprotmask)
3389 scsi_host_set_prot(host, ql2xprotmask);
3390 else
3391 scsi_host_set_prot(host,
3392 prot | SHOST_DIF_TYPE1_PROTECTION
3393 | SHOST_DIF_TYPE2_PROTECTION
3394 | SHOST_DIF_TYPE3_PROTECTION
3395 | SHOST_DIX_TYPE1_PROTECTION
3396 | SHOST_DIX_TYPE2_PROTECTION
3397 | SHOST_DIX_TYPE3_PROTECTION);
9e522cd8
AE		 3398
3399 guard = SHOST_DIX_GUARD_CRC;
3400
3401 if (IS_PI_IPGUARD_CAPABLE(ha) &&
3402 (ql2xenabledif > 1 || IS_PI_DIFB_DIX0_CAPABLE(ha)))
3403 guard |= SHOST_DIX_GUARD_IP;
3404
7855d2ba
MP		 3405 if (ql2xprotguard)
3406 scsi_host_set_guard(host, ql2xprotguard);
3407 else
3408 scsi_host_set_guard(host, guard);
bad75002
AE		 3409 } else
3410 base_vha->flags.difdix_supported = 0;
3411 }
3412
a9083016
GM		 3413 ha->isp_ops->enable_intrs(ha);
3414
1fe19ee4
AB		 3415 if (IS_QLAFX00(ha)) {
3416 ret = qlafx00_fx_disc(base_vha,
3417 &base_vha->hw->mr.fcport, FXDISC_GET_CONFIG_INFO);
3418 host->sg_tablesize = (ha->mr.extended_io_enabled) ?
3419 QLA_SG_ALL : 128;
3420 }
3421
a1541d5a
AV		 3422 ret = scsi_add_host(host, &pdev->dev);
3423 if (ret)
3424 goto probe_failed;
3425
1486400f
MR		 3426 base_vha->flags.init_done = 1;
3427 base_vha->flags.online = 1;
edaa5c74 3428 ha->prev_minidump_failed = 0;
1486400f 3429
7c3df132
SK		 3430 ql_dbg(ql_dbg_init, base_vha, 0x00f2,
3431 "Init done and hba is online.\n");
3432
726b8548
QT		 3433 if (qla_ini_mode_enabled(base_vha) ||
3434 qla_dual_mode_enabled(base_vha))
2d70c103
NB		 3435 scsi_scan_host(host);
3436 else
3437 ql_dbg(ql_dbg_init, base_vha, 0x0122,
3438 "skipping scsi_scan_host() for non-initiator port\n");
1e99e33a 3439
e315cd28 3440 qla2x00_alloc_sysfs_attr(base_vha);
a1541d5a 3441
8ae6d9c7 3442 if (IS_QLAFX00(ha)) {
8ae6d9c7
GM		 3443 ret = qlafx00_fx_disc(base_vha,
3444 &base_vha->hw->mr.fcport, FXDISC_GET_PORT_INFO);
3445
3446 /* Register system information */
3447 ret = qlafx00_fx_disc(base_vha,
3448 &base_vha->hw->mr.fcport, FXDISC_REG_HOST_INFO);
3449 }
3450
e315cd28 3451 qla2x00_init_host_attr(base_vha);
a1541d5a 3452
e315cd28 3453 qla2x00_dfs_setup(base_vha);
df613b96 3454
03eb912a
AB		 3455 ql_log(ql_log_info, base_vha, 0x00fb,
3456 "QLogic %s - %s.\n", ha->model_number, ha->model_desc);
7c3df132
SK		 3457 ql_log(ql_log_info, base_vha, 0x00fc,
3458 "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n",
3459 pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info),
3460 pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-',
3461 base_vha->host_no,
df57caba 3462 ha->isp_ops->fw_version_str(base_vha, fw_str, sizeof(fw_str)));
1da177e4 3463
2d70c103
NB		 3464 qlt_add_target(ha, base_vha);
3465
6b383979 3466 clear_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags);
a29b3dd7
JC		 3467
3468 if (test_bit(UNLOADING, &base_vha->dpc_flags))
3469 return -ENODEV;
3470
e4e3a2ce
QT		 3471 if (ha->flags.detected_lr_sfp) {
3472 ql_log(ql_log_info, base_vha, 0xffff,
3473 "Reset chip to pick up LR SFP setting\n");
3474 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
3475 qla2xxx_wake_dpc(base_vha);
3476 }
3477
1da177e4
LT		 3478 return 0;
3479
3480probe_failed:
b9978769
AV		 3481 if (base_vha->timer_active)
3482 qla2x00_stop_timer(base_vha);
3483 base_vha->flags.online = 0;
3484 if (ha->dpc_thread) {
3485 struct task_struct *t = ha->dpc_thread;
3486
3487 ha->dpc_thread = NULL;
3488 kthread_stop(t);
3489 }
3490
e315cd28 3491 qla2x00_free_device(base_vha);
e315cd28 3492 scsi_host_put(base_vha->host);
6d634067
BK		 3493 /*
3494 * Need to NULL out local req/rsp after
3495 * qla2x00_free_device => qla2x00_free_queues frees
3496 * what these are pointing to. Or else we'll
3497 * fall over below in qla2x00_free_req/rsp_que.
3498 */
3499 req = NULL;
3500 rsp = NULL;
1da177e4 3501
e315cd28 3502probe_hw_failed:
d64d6c56 3503 qla2x00_mem_free(ha);
3504 qla2x00_free_req_que(ha, req);
3505 qla2x00_free_rsp_que(ha, rsp);
1a2fbf18
JL		 3506 qla2x00_clear_drv_active(ha);
3507
0a63ad12 3508iospace_config_failed:
7ec0effd 3509 if (IS_P3P_TYPE(ha)) {
0a63ad12 3510 if (!ha->nx_pcibase)
f73cb695 3511 iounmap((device_reg_t *)ha->nx_pcibase);
a9083016 3512 if (!ql2xdbwr)
f73cb695 3513 iounmap((device_reg_t *)ha->nxdb_wr_ptr);
a9083016
GM		 3514 } else {
3515 if (ha->iobase)
3516 iounmap(ha->iobase);
8ae6d9c7
GM		 3517 if (ha->cregbase)
3518 iounmap(ha->cregbase);
a9083016 3519 }
e315cd28
AC		 3520 pci_release_selected_regions(ha->pdev, ha->bars);
3521 kfree(ha);
1da177e4 3522
ddff7ed4 3523disable_device:
e315cd28 3524 pci_disable_device(pdev);
a1541d5a 3525 return ret;
1da177e4 3526}
1da177e4 3527
e30d1756
MI		 3528static void
3529qla2x00_shutdown(struct pci_dev *pdev)
3530{
3531 scsi_qla_host_t *vha;
3532 struct qla_hw_data *ha;
3533
3534 vha = pci_get_drvdata(pdev);
3535 ha = vha->hw;
3536
efdb5760
SC		 3537 ql_log(ql_log_info, vha, 0xfffa,
3538 "Adapter shutdown\n");
3539
3540 /*
3541 * Prevent future board_disable and wait
3542 * until any pending board_disable has completed.
3543 */
3544 set_bit(PFLG_DRIVER_REMOVING, &vha->pci_flags);
3545 cancel_work_sync(&ha->board_disable);
3546
3547 if (!atomic_read(&pdev->enable_cnt))
3548 return;
3549
42479343
AB		 3550 /* Notify ISPFX00 firmware */
3551 if (IS_QLAFX00(ha))
3552 qlafx00_driver_shutdown(vha, 20);
3553
e30d1756
MI		 3554 /* Turn-off FCE trace */
3555 if (ha->flags.fce_enabled) {
3556 qla2x00_disable_fce_trace(vha, NULL, NULL);
3557 ha->flags.fce_enabled = 0;
3558 }
3559
3560 /* Turn-off EFT trace */
3561 if (ha->eft)
3562 qla2x00_disable_eft_trace(vha);
3563
ecc89f25
JC		 3564 if (IS_QLA25XX(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) ||
3565 IS_QLA28XX(ha)) {
3407fc37
QT		 3566 if (ha->flags.fw_started)
3567 qla2x00_abort_isp_cleanup(vha);
3568 } else {
3569 /* Stop currently executing firmware. */
3570 qla2x00_try_to_stop_firmware(vha);
3571 }
e30d1756
MI		 3572
3573 /* Turn adapter off line */
3574 vha->flags.online = 0;
3575
3576 /* turn-off interrupts on the card */
3577 if (ha->interrupts_on) {
3578 vha->flags.init_done = 0;
3579 ha->isp_ops->disable_intrs(ha);
3580 }
3581
3582 qla2x00_free_irqs(vha);
3583
3584 qla2x00_free_fw_dump(ha);
61d41f61 3585
61d41f61 3586 pci_disable_device(pdev);
efdb5760
SC		 3587 ql_log(ql_log_info, vha, 0xfffe,
3588 "Adapter shutdown successfully.\n");
e30d1756
MI		 3589}
3590
fe1b806f 3591/* Deletes all the virtual ports for a given ha */
4c993f76 3592static void
fe1b806f 3593qla2x00_delete_all_vps(struct qla_hw_data *ha, scsi_qla_host_t *base_vha)
1da177e4 3594{
fe1b806f 3595 scsi_qla_host_t *vha;
feafb7b1 3596 unsigned long flags;
e315cd28 3597
43ebf16d
AE		 3598 mutex_lock(&ha->vport_lock);
3599 while (ha->cur_vport_count) {
43ebf16d 3600 spin_lock_irqsave(&ha->vport_slock, flags);
feafb7b1 3601
43ebf16d
AE		 3602 BUG_ON(base_vha->list.next == &ha->vp_list);
3603 /* This assumes first entry in ha->vp_list is always base vha */
3604 vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list);
52c82823 3605 scsi_host_get(vha->host);
feafb7b1 3606
43ebf16d
AE		 3607 spin_unlock_irqrestore(&ha->vport_slock, flags);
3608 mutex_unlock(&ha->vport_lock);
3609
5e6803b4
HM		 3610 qla_nvme_delete(vha);
3611
43ebf16d
AE		 3612 fc_vport_terminate(vha->fc_vport);
3613 scsi_host_put(vha->host);
feafb7b1 3614
43ebf16d 3615 mutex_lock(&ha->vport_lock);
e315cd28 3616 }
43ebf16d 3617 mutex_unlock(&ha->vport_lock);
fe1b806f 3618}
1da177e4 3619
fe1b806f
CD		 3620/* Stops all deferred work threads */
3621static void
3622qla2x00_destroy_deferred_work(struct qla_hw_data *ha)
3623{
7d613ac6
SV		 3624 /* Cancel all work and destroy DPC workqueues */
3625 if (ha->dpc_lp_wq) {
3626 cancel_work_sync(&ha->idc_aen);
3627 destroy_workqueue(ha->dpc_lp_wq);
3628 ha->dpc_lp_wq = NULL;
3629 }
3630
3631 if (ha->dpc_hp_wq) {
3632 cancel_work_sync(&ha->nic_core_reset);
3633 cancel_work_sync(&ha->idc_state_handler);
3634 cancel_work_sync(&ha->nic_core_unrecoverable);
3635 destroy_workqueue(ha->dpc_hp_wq);
3636 ha->dpc_hp_wq = NULL;
3637 }
3638
b9978769
AV		 3639 /* Kill the kernel thread for this host */
3640 if (ha->dpc_thread) {
3641 struct task_struct *t = ha->dpc_thread;
3642
3643 /*
3644 * qla2xxx_wake_dpc checks for ->dpc_thread
3645 * so we need to zero it out.
3646 */
3647 ha->dpc_thread = NULL;
3648 kthread_stop(t);
3649 }
fe1b806f 3650}
1da177e4 3651
fe1b806f
CD		 3652static void
3653qla2x00_unmap_iobases(struct qla_hw_data *ha)
3654{
a9083016 3655 if (IS_QLA82XX(ha)) {
b963752f 3656
f73cb695 3657 iounmap((device_reg_t *)ha->nx_pcibase);
a9083016 3658 if (!ql2xdbwr)
f73cb695 3659 iounmap((device_reg_t *)ha->nxdb_wr_ptr);
a9083016
GM		 3660 } else {
3661 if (ha->iobase)
3662 iounmap(ha->iobase);
1da177e4 3663
8ae6d9c7
GM		 3664 if (ha->cregbase)
3665 iounmap(ha->cregbase);
3666
a9083016
GM		 3667 if (ha->mqiobase)
3668 iounmap(ha->mqiobase);
6246b8a1 3669
ecc89f25
JC		 3670 if ((IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) &&
3671 ha->msixbase)
6246b8a1 3672 iounmap(ha->msixbase);
a9083016 3673 }
fe1b806f
CD		 3674}
3675
3676static void
db7157d4 3677qla2x00_clear_drv_active(struct qla_hw_data *ha)
fe1b806f 3678{
fe1b806f
CD		 3679 if (IS_QLA8044(ha)) {
3680 qla8044_idc_lock(ha);
c41afc9a 3681 qla8044_clear_drv_active(ha);
fe1b806f
CD		 3682 qla8044_idc_unlock(ha);
3683 } else if (IS_QLA82XX(ha)) {
3684 qla82xx_idc_lock(ha);
3685 qla82xx_clear_drv_active(ha);
3686 qla82xx_idc_unlock(ha);
3687 }
3688}
3689
3690static void
3691qla2x00_remove_one(struct pci_dev *pdev)
3692{
3693 scsi_qla_host_t *base_vha;
3694 struct qla_hw_data *ha;
3695
beb9e315
JL		 3696 base_vha = pci_get_drvdata(pdev);
3697 ha = base_vha->hw;
45235022
QT		 3698 ql_log(ql_log_info, base_vha, 0xb079,
3699 "Removing driver\n");
beb9e315
JL		 3700
3701 /* Indicate device removal to prevent future board_disable and wait
3702 * until any pending board_disable has completed. */
3703 set_bit(PFLG_DRIVER_REMOVING, &base_vha->pci_flags);
3704 cancel_work_sync(&ha->board_disable);
3705
fe1b806f 3706 /*
beb9e315
JL		 3707 * If the PCI device is disabled then there was a PCI-disconnect and
3708 * qla2x00_disable_board_on_pci_error has taken care of most of the
3709 * resources.
fe1b806f 3710 */
beb9e315 3711 if (!atomic_read(&pdev->enable_cnt)) {
726b8548
QT		 3712 dma_free_coherent(&ha->pdev->dev, base_vha->gnl.size,
3713 base_vha->gnl.l, base_vha->gnl.ldma);
3714
beb9e315
JL		 3715 scsi_host_put(base_vha->host);
3716 kfree(ha);
3717 pci_set_drvdata(pdev, NULL);
fe1b806f 3718 return;
beb9e315 3719 }
638a1a01
SC		 3720 qla2x00_wait_for_hba_ready(base_vha);
3721
ecc89f25
JC		 3722 if (IS_QLA25XX(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) ||
3723 IS_QLA28XX(ha)) {
45235022
QT		 3724 if (ha->flags.fw_started)
3725 qla2x00_abort_isp_cleanup(base_vha);
3726 } else if (!IS_QLAFX00(ha)) {
3727 if (IS_QLA8031(ha)) {
3728 ql_dbg(ql_dbg_p3p, base_vha, 0xb07e,
3729 "Clearing fcoe driver presence.\n");
3730 if (qla83xx_clear_drv_presence(base_vha) != QLA_SUCCESS)
3731 ql_dbg(ql_dbg_p3p, base_vha, 0xb079,
3732 "Error while clearing DRV-Presence.\n");
3733 }
3734
3735 qla2x00_try_to_stop_firmware(base_vha);
3736 }
3737
2ce87cc5
QT		 3738 qla2x00_wait_for_sess_deletion(base_vha);
3739
726b8548
QT		 3740 /*
3741 * if UNLOAD flag is already set, then continue unload,
783e0dc4
SC		 3742 * where it was set first.
3743 */
3744 if (test_bit(UNLOADING, &base_vha->dpc_flags))
3745 return;
3746
fe1b806f 3747 set_bit(UNLOADING, &base_vha->dpc_flags);
e84067d7
DG		 3748
3749 qla_nvme_delete(base_vha);
3750
726b8548
QT		 3751 dma_free_coherent(&ha->pdev->dev,
3752 base_vha->gnl.size, base_vha->gnl.l, base_vha->gnl.ldma);
fe1b806f 3753
a4239945
QT		 3754 vfree(base_vha->scan.l);
3755
fe1b806f
CD		 3756 if (IS_QLAFX00(ha))
3757 qlafx00_driver_shutdown(base_vha, 20);
3758
3759 qla2x00_delete_all_vps(ha, base_vha);
3760
fe1b806f
CD		 3761 qla2x00_dfs_remove(base_vha);
3762
3763 qla84xx_put_chip(base_vha);
3764
3765 /* Disable timer */
3766 if (base_vha->timer_active)
3767 qla2x00_stop_timer(base_vha);
3768
3769 base_vha->flags.online = 0;
3770
b0d6cabd
HM		 3771 /* free DMA memory */
3772 if (ha->exlogin_buf)
3773 qla2x00_free_exlogin_buffer(ha);
3774
2f56a7f1
HM		 3775 /* free DMA memory */
3776 if (ha->exchoffld_buf)
3777 qla2x00_free_exchoffld_buffer(ha);
3778
fe1b806f
CD		 3779 qla2x00_destroy_deferred_work(ha);
3780
3781 qlt_remove_target(ha, base_vha);
3782
3783 qla2x00_free_sysfs_attr(base_vha, true);
3784
3785 fc_remove_host(base_vha->host);
482c9dc7 3786 qlt_remove_target_resources(ha);
fe1b806f
CD		 3787
3788 scsi_remove_host(base_vha->host);
3789
3790 qla2x00_free_device(base_vha);
3791
db7157d4 3792 qla2x00_clear_drv_active(ha);
fe1b806f 3793
d2749ffa
AE		 3794 scsi_host_put(base_vha->host);
3795
fe1b806f 3796 qla2x00_unmap_iobases(ha);
73208dfd 3797
e315cd28
AC		 3798 pci_release_selected_regions(ha->pdev, ha->bars);
3799 kfree(ha);
1da177e4 3800
90a86fc0
JC		 3801 pci_disable_pcie_error_reporting(pdev);
3802
665db93b 3803 pci_disable_device(pdev);
1da177e4 3804}
1da177e4
LT		 3805
3806static void
e315cd28 3807qla2x00_free_device(scsi_qla_host_t *vha)
1da177e4 3808{
e315cd28 3809 struct qla_hw_data *ha = vha->hw;
1da177e4 3810
85880801
AV		 3811 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
3812
3813 /* Disable timer */
3814 if (vha->timer_active)
3815 qla2x00_stop_timer(vha);
3816
2afa19a9 3817 qla25xx_delete_queues(vha);
85880801
AV		 3818 vha->flags.online = 0;
3819
f6ef3b18 3820 /* turn-off interrupts on the card */
a9083016
GM		 3821 if (ha->interrupts_on) {
3822 vha->flags.init_done = 0;
fd34f556 3823 ha->isp_ops->disable_intrs(ha);
a9083016 3824 }
f6ef3b18 3825
093df737
QT		 3826 qla2x00_free_fcports(vha);
3827
e315cd28 3828 qla2x00_free_irqs(vha);
1da177e4 3829
093df737
QT		 3830 /* Flush the work queue and remove it */
3831 if (ha->wq) {
3832 flush_workqueue(ha->wq);
3833 destroy_workqueue(ha->wq);
3834 ha->wq = NULL;
3835 }
3836
8867048b 3837
e315cd28 3838 qla2x00_mem_free(ha);
73208dfd 3839
08de2844
GM		 3840 qla82xx_md_free(vha);
3841
73208dfd 3842 qla2x00_free_queues(ha);
1da177e4
LT		 3843}
3844
8867048b
CD		 3845void qla2x00_free_fcports(struct scsi_qla_host *vha)
3846{
3847 fc_port_t *fcport, *tfcport;
3848
ffbc6476
QT		 3849 list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list)
3850 qla2x00_free_fcport(fcport);
8867048b
CD		 3851}
3852
d97994dc 3853static inline void
e315cd28 3854qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport,
d97994dc 3855 int defer)
3856{
d97994dc 3857 struct fc_rport *rport;
67becc00 3858 scsi_qla_host_t *base_vha;
044d78e1 3859 unsigned long flags;
d97994dc 3860
3861 if (!fcport->rport)
3862 return;
3863
3864 rport = fcport->rport;
3865 if (defer) {
67becc00 3866 base_vha = pci_get_drvdata(vha->hw->pdev);
044d78e1 3867 spin_lock_irqsave(vha->host->host_lock, flags);
d97994dc 3868 fcport->drport = rport;
044d78e1 3869 spin_unlock_irqrestore(vha->host->host_lock, flags);
df673274 3870 qlt_do_generation_tick(vha, &base_vha->total_fcport_update_gen);
67becc00
AV		 3871 set_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags);
3872 qla2xxx_wake_dpc(base_vha);
2d70c103 3873 } else {
df673274 3874 int now;
bd432bb5 3875
726b8548 3876 if (rport) {
83548fe2
QT		 3877 ql_dbg(ql_dbg_disc, fcport->vha, 0x2109,
3878 "%s %8phN. rport %p roles %x\n",
3879 __func__, fcport->port_name, rport,
3880 rport->roles);
d20ed91b 3881 fc_remote_port_delete(rport);
726b8548 3882 }
df673274 3883 qlt_do_generation_tick(vha, &now);
2d70c103 3884 }
d97994dc 3885}
3886
1da177e4
LT		 3887/*
3888 * qla2x00_mark_device_lost Updates fcport state when device goes offline.
3889 *
3890 * Input: ha = adapter block pointer. fcport = port structure pointer.
3891 *
3892 * Return: None.
3893 *
3894 * Context:
3895 */
e315cd28 3896void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport,
d97994dc 3897 int do_login, int defer)
1da177e4 3898{
8ae6d9c7
GM		 3899 if (IS_QLAFX00(vha->hw)) {
3900 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
3901 qla2x00_schedule_rport_del(vha, fcport, defer);
3902 return;
3903 }
3904
2c3dfe3f 3905 if (atomic_read(&fcport->state) == FCS_ONLINE &&
c6d39e23 3906 vha->vp_idx == fcport->vha->vp_idx) {
ec426e10 3907 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
e315cd28
AC		 3908 qla2x00_schedule_rport_del(vha, fcport, defer);
3909 }
fa2a1ce5 3910 /*
1da177e4
LT		 3911 * We may need to retry the login, so don't change the state of the
3912 * port but do the retries.
3913 */
3914 if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD)
ec426e10 3915 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
1da177e4
LT		 3916
3917 if (!do_login)
3918 return;
3919
a1d0285e 3920 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
1da177e4
LT		 3921}
3922
3923/*
3924 * qla2x00_mark_all_devices_lost
3925 * Updates fcport state when device goes offline.
3926 *
3927 * Input:
3928 * ha = adapter block pointer.
3929 * fcport = port structure pointer.
3930 *
3931 * Return:
3932 * None.
3933 *
3934 * Context:
3935 */
3936void
e315cd28 3937qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha, int defer)
1da177e4
LT		 3938{
3939 fc_port_t *fcport;
3940
83548fe2
QT		 3941 ql_dbg(ql_dbg_disc, vha, 0x20f1,
3942 "Mark all dev lost\n");
726b8548 3943
e315cd28 3944 list_for_each_entry(fcport, &vha->vp_fcports, list) {
726b8548 3945 fcport->scan_state = 0;
d8630bb9 3946 qlt_schedule_sess_for_deletion(fcport);
726b8548 3947
c6d39e23 3948 if (vha->vp_idx != 0 && vha->vp_idx != fcport->vha->vp_idx)
1da177e4 3949 continue;
0d6e61bc 3950
1da177e4
LT		 3951 /*
3952 * No point in marking the device as lost, if the device is
3953 * already DEAD.
3954 */
3955 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD)
3956 continue;
e315cd28 3957 if (atomic_read(&fcport->state) == FCS_ONLINE) {
ec426e10 3958 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
0d6e61bc
AV		 3959 if (defer)
3960 qla2x00_schedule_rport_del(vha, fcport, defer);
c6d39e23 3961 else if (vha->vp_idx == fcport->vha->vp_idx)
0d6e61bc
AV		 3962 qla2x00_schedule_rport_del(vha, fcport, defer);
3963 }
1da177e4
LT		 3964 }
3965}
3966
0e145a59
BVA		 3967static void qla2x00_set_reserved_loop_ids(struct qla_hw_data *ha)
3968{
3969 int i;
3970
3971 if (IS_FWI2_CAPABLE(ha))
3972 return;
3973
3974 for (i = 0; i < SNS_FIRST_LOOP_ID; i++)
3975 set_bit(i, ha->loop_id_map);
3976 set_bit(MANAGEMENT_SERVER, ha->loop_id_map);
3977 set_bit(BROADCAST, ha->loop_id_map);
3978}
3979
1da177e4
LT		 3980/*
3981* qla2x00_mem_alloc
3982* Allocates adapter memory.
3983*
3984* Returns:
3985* 0 = success.
e8711085 3986* !0 = failure.
1da177e4 3987*/
e8711085 3988static int
73208dfd
AC		 3989qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len,
3990 struct req_que **req, struct rsp_que **rsp)
1da177e4
LT		 3991{
3992 char name[16];
1da177e4 3993
e8711085 3994 ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size,
e315cd28 3995 &ha->init_cb_dma, GFP_KERNEL);
e8711085 3996 if (!ha->init_cb)
e315cd28 3997 goto fail;
e8711085 3998
2d70c103
NB		 3999 if (qlt_mem_alloc(ha) < 0)
4000 goto fail_free_init_cb;
4001
642ef983
CD		 4002 ha->gid_list = dma_alloc_coherent(&ha->pdev->dev,
4003 qla2x00_gid_list_size(ha), &ha->gid_list_dma, GFP_KERNEL);
e315cd28 4004 if (!ha->gid_list)
2d70c103 4005 goto fail_free_tgt_mem;
1da177e4 4006
e8711085
AV		 4007 ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep);
4008 if (!ha->srb_mempool)
e315cd28 4009 goto fail_free_gid_list;
e8711085 4010
7ec0effd 4011 if (IS_P3P_TYPE(ha)) {
a9083016
GM		 4012 /* Allocate cache for CT6 Ctx. */
4013 if (!ctx_cachep) {
4014 ctx_cachep = kmem_cache_create("qla2xxx_ctx",
4015 sizeof(struct ct6_dsd), 0,
4016 SLAB_HWCACHE_ALIGN, NULL);
4017 if (!ctx_cachep)
fc1ffd6c 4018 goto fail_free_srb_mempool;
a9083016
GM		 4019 }
4020 ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ,
4021 ctx_cachep);
4022 if (!ha->ctx_mempool)
4023 goto fail_free_srb_mempool;
7c3df132
SK		 4024 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021,
4025 "ctx_cachep=%p ctx_mempool=%p.\n",
4026 ctx_cachep, ha->ctx_mempool);
a9083016
GM		 4027 }
4028
e8711085
AV		 4029 /* Get memory for cached NVRAM */
4030 ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL);
4031 if (!ha->nvram)
a9083016 4032 goto fail_free_ctx_mempool;
e8711085 4033
e315cd28
AC		 4034 snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME,
4035 ha->pdev->device);
4036 ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev,
4037 DMA_POOL_SIZE, 8, 0);
4038 if (!ha->s_dma_pool)
4039 goto fail_free_nvram;
4040
7c3df132
SK		 4041 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022,
4042 "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n",
4043 ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool);
4044
7ec0effd 4045 if (IS_P3P_TYPE(ha) || ql2xenabledif) {
a9083016
GM		 4046 ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev,
4047 DSD_LIST_DMA_POOL_SIZE, 8, 0);
4048 if (!ha->dl_dma_pool) {
7c3df132
SK		 4049 ql_log_pci(ql_log_fatal, ha->pdev, 0x0023,
4050 "Failed to allocate memory for dl_dma_pool.\n");
a9083016
GM		 4051 goto fail_s_dma_pool;
4052 }
4053
4054 ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev,
4055 FCP_CMND_DMA_POOL_SIZE, 8, 0);
4056 if (!ha->fcp_cmnd_dma_pool) {
7c3df132
SK		 4057 ql_log_pci(ql_log_fatal, ha->pdev, 0x0024,
4058 "Failed to allocate memory for fcp_cmnd_dma_pool.\n");
a9083016
GM		 4059 goto fail_dl_dma_pool;
4060 }
50b81275
GM		 4061
4062 if (ql2xenabledif) {
4063 u64 bufsize = DIF_BUNDLING_DMA_POOL_SIZE;
4064 struct dsd_dma *dsd, *nxt;
4065 uint i;
4066 /* Creata a DMA pool of buffers for DIF bundling */
4067 ha->dif_bundl_pool = dma_pool_create(name,
4068 &ha->pdev->dev, DIF_BUNDLING_DMA_POOL_SIZE, 8, 0);
4069 if (!ha->dif_bundl_pool) {
4070 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0024,
4071 "%s: failed create dif_bundl_pool\n",
4072 __func__);
4073 goto fail_dif_bundl_dma_pool;
4074 }
4075
4076 INIT_LIST_HEAD(&ha->pool.good.head);
4077 INIT_LIST_HEAD(&ha->pool.unusable.head);
4078 ha->pool.good.count = 0;
4079 ha->pool.unusable.count = 0;
4080 for (i = 0; i < 128; i++) {
4081 dsd = kzalloc(sizeof(*dsd), GFP_ATOMIC);
4082 if (!dsd) {
4083 ql_dbg_pci(ql_dbg_init, ha->pdev,
4084 0xe0ee, "%s: failed alloc dsd\n",
4085 __func__);
4086 return 1;
4087 }
4088 ha->dif_bundle_kallocs++;
4089
4090 dsd->dsd_addr = dma_pool_alloc(
4091 ha->dif_bundl_pool, GFP_ATOMIC,
4092 &dsd->dsd_list_dma);
4093 if (!dsd->dsd_addr) {
4094 ql_dbg_pci(ql_dbg_init, ha->pdev,
4095 0xe0ee,
4096 "%s: failed alloc ->dsd_addr\n",
4097 __func__);
4098 kfree(dsd);
4099 ha->dif_bundle_kallocs--;
4100 continue;
4101 }
4102 ha->dif_bundle_dma_allocs++;
4103
4104 /*
4105 * if DMA buffer crosses 4G boundary,
4106 * put it on bad list
4107 */
4108 if (MSD(dsd->dsd_list_dma) ^
4109 MSD(dsd->dsd_list_dma + bufsize)) {
4110 list_add_tail(&dsd->list,
4111 &ha->pool.unusable.head);
4112 ha->pool.unusable.count++;
4113 } else {
4114 list_add_tail(&dsd->list,
4115 &ha->pool.good.head);
4116 ha->pool.good.count++;
4117 }
4118 }
4119
4120 /* return the good ones back to the pool */
4121 list_for_each_entry_safe(dsd, nxt,
4122 &ha->pool.good.head, list) {
4123 list_del(&dsd->list);
4124 dma_pool_free(ha->dif_bundl_pool,
4125 dsd->dsd_addr, dsd->dsd_list_dma);
4126 ha->dif_bundle_dma_allocs--;
4127 kfree(dsd);
4128 ha->dif_bundle_kallocs--;
4129 }
4130
4131 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0024,
4132 "%s: dif dma pool (good=%u unusable=%u)\n",
4133 __func__, ha->pool.good.count,
4134 ha->pool.unusable.count);
4135 }
4136
7c3df132 4137 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025,
50b81275
GM		 4138 "dl_dma_pool=%p fcp_cmnd_dma_pool=%p dif_bundl_pool=%p.\n",
4139 ha->dl_dma_pool, ha->fcp_cmnd_dma_pool,
4140 ha->dif_bundl_pool);
a9083016
GM		 4141 }
4142
e8711085
AV		 4143 /* Allocate memory for SNS commands */
4144 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
e315cd28 4145 /* Get consistent memory allocated for SNS commands */
e8711085 4146 ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev,
e315cd28 4147 sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL);
e8711085 4148 if (!ha->sns_cmd)
e315cd28 4149 goto fail_dma_pool;
7c3df132 4150 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026,
d8424f68 4151 "sns_cmd: %p.\n", ha->sns_cmd);
e8711085 4152 } else {
e315cd28 4153 /* Get consistent memory allocated for MS IOCB */
e8711085 4154 ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
e315cd28 4155 &ha->ms_iocb_dma);
e8711085 4156 if (!ha->ms_iocb)
e315cd28
AC		 4157 goto fail_dma_pool;
4158 /* Get consistent memory allocated for CT SNS commands */
e8711085 4159 ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev,
e315cd28 4160 sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL);
e8711085
AV		 4161 if (!ha->ct_sns)
4162 goto fail_free_ms_iocb;
7c3df132
SK		 4163 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027,
4164 "ms_iocb=%p ct_sns=%p.\n",
4165 ha->ms_iocb, ha->ct_sns);
1da177e4
LT		 4166 }
4167
e315cd28 4168 /* Allocate memory for request ring */
73208dfd
AC		 4169 *req = kzalloc(sizeof(struct req_que), GFP_KERNEL);
4170 if (!*req) {
7c3df132
SK		 4171 ql_log_pci(ql_log_fatal, ha->pdev, 0x0028,
4172 "Failed to allocate memory for req.\n");
e315cd28
AC		 4173 goto fail_req;
4174 }
73208dfd
AC		 4175 (*req)->length = req_len;
4176 (*req)->ring = dma_alloc_coherent(&ha->pdev->dev,
4177 ((*req)->length + 1) * sizeof(request_t),
4178 &(*req)->dma, GFP_KERNEL);
4179 if (!(*req)->ring) {
7c3df132
SK		 4180 ql_log_pci(ql_log_fatal, ha->pdev, 0x0029,
4181 "Failed to allocate memory for req_ring.\n");
e315cd28
AC		 4182 goto fail_req_ring;
4183 }
4184 /* Allocate memory for response ring */
73208dfd
AC		 4185 *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL);
4186 if (!*rsp) {
7c3df132
SK		 4187 ql_log_pci(ql_log_fatal, ha->pdev, 0x002a,
4188 "Failed to allocate memory for rsp.\n");
e315cd28
AC		 4189 goto fail_rsp;
4190 }
73208dfd
AC		 4191 (*rsp)->hw = ha;
4192 (*rsp)->length = rsp_len;
4193 (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev,
4194 ((*rsp)->length + 1) * sizeof(response_t),
4195 &(*rsp)->dma, GFP_KERNEL);
4196 if (!(*rsp)->ring) {
7c3df132
SK		 4197 ql_log_pci(ql_log_fatal, ha->pdev, 0x002b,
4198 "Failed to allocate memory for rsp_ring.\n");
e315cd28
AC		 4199 goto fail_rsp_ring;
4200 }
73208dfd
AC		 4201 (*req)->rsp = *rsp;
4202 (*rsp)->req = *req;
7c3df132
SK		 4203 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c,
4204 "req=%p req->length=%d req->ring=%p rsp=%p "
4205 "rsp->length=%d rsp->ring=%p.\n",
4206 *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length,
4207 (*rsp)->ring);
73208dfd
AC		 4208 /* Allocate memory for NVRAM data for vports */
4209 if (ha->nvram_npiv_size) {
6396bb22
KC		 4210 ha->npiv_info = kcalloc(ha->nvram_npiv_size,
4211 sizeof(struct qla_npiv_entry),
4212 GFP_KERNEL);
73208dfd 4213 if (!ha->npiv_info) {
7c3df132
SK		 4214 ql_log_pci(ql_log_fatal, ha->pdev, 0x002d,
4215 "Failed to allocate memory for npiv_info.\n");
73208dfd
AC		 4216 goto fail_npiv_info;
4217 }
4218 } else
4219 ha->npiv_info = NULL;
e8711085 4220
b64b0e8f 4221 /* Get consistent memory allocated for EX-INIT-CB. */
ecc89f25
JC		 4222 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) ||
4223 IS_QLA28XX(ha)) {
b64b0e8f
AV		 4224 ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
4225 &ha->ex_init_cb_dma);
4226 if (!ha->ex_init_cb)
4227 goto fail_ex_init_cb;
7c3df132
SK		 4228 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e,
4229 "ex_init_cb=%p.\n", ha->ex_init_cb);
b64b0e8f
AV		 4230 }
4231
a9083016
GM		 4232 INIT_LIST_HEAD(&ha->gbl_dsd_list);
4233
5ff1d584
AV		 4234 /* Get consistent memory allocated for Async Port-Database. */
4235 if (!IS_FWI2_CAPABLE(ha)) {
4236 ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
4237 &ha->async_pd_dma);
4238 if (!ha->async_pd)
4239 goto fail_async_pd;
7c3df132
SK		 4240 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f,
4241 "async_pd=%p.\n", ha->async_pd);
5ff1d584
AV		 4242 }
4243
e315cd28 4244 INIT_LIST_HEAD(&ha->vp_list);
5f16b331
CD		 4245
4246 /* Allocate memory for our loop_id bitmap */
6396bb22
KC		 4247 ha->loop_id_map = kcalloc(BITS_TO_LONGS(LOOPID_MAP_SIZE),
4248 sizeof(long),
4249 GFP_KERNEL);
5f16b331 4250 if (!ha->loop_id_map)
fc1ffd6c 4251 goto fail_loop_id_map;
5f16b331
CD		 4252 else {
4253 qla2x00_set_reserved_loop_ids(ha);
4254 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0123,
b2a72ec3 4255 "loop_id_map=%p.\n", ha->loop_id_map);
5f16b331
CD		 4256 }
4257
e4e3a2ce
QT		 4258 ha->sfp_data = dma_alloc_coherent(&ha->pdev->dev,
4259 SFP_DEV_SIZE, &ha->sfp_data_dma, GFP_KERNEL);
4260 if (!ha->sfp_data) {
4261 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b,
4262 "Unable to allocate memory for SFP read-data.\n");
4263 goto fail_sfp_data;
4264 }
4265
3f006ac3
MH		 4266 ha->flt = dma_alloc_coherent(&ha->pdev->dev,
4267 sizeof(struct qla_flt_header) + FLT_REGIONS_SIZE, &ha->flt_dma,
4268 GFP_KERNEL);
4269 if (!ha->flt) {
4270 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b,
4271 "Unable to allocate memory for FLT.\n");
4272 goto fail_flt_buffer;
4273 }
4274
b2a72ec3 4275 return 0;
e315cd28 4276
3f006ac3
MH		 4277fail_flt_buffer:
4278 dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE,
4279 ha->sfp_data, ha->sfp_data_dma);
e4e3a2ce
QT		 4280fail_sfp_data:
4281 kfree(ha->loop_id_map);
fc1ffd6c
QT		 4282fail_loop_id_map:
4283 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
5ff1d584
AV		 4284fail_async_pd:
4285 dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma);
b64b0e8f
AV		 4286fail_ex_init_cb:
4287 kfree(ha->npiv_info);
73208dfd
AC		 4288fail_npiv_info:
4289 dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) *
4290 sizeof(response_t), (*rsp)->ring, (*rsp)->dma);
4291 (*rsp)->ring = NULL;
4292 (*rsp)->dma = 0;
e315cd28 4293fail_rsp_ring:
73208dfd 4294 kfree(*rsp);
6d634067 4295 *rsp = NULL;
e315cd28 4296fail_rsp:
73208dfd
AC		 4297 dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) *
4298 sizeof(request_t), (*req)->ring, (*req)->dma);
4299 (*req)->ring = NULL;
4300 (*req)->dma = 0;
e315cd28 4301fail_req_ring:
73208dfd 4302 kfree(*req);
6d634067 4303 *req = NULL;
e315cd28
AC		 4304fail_req:
4305 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
4306 ha->ct_sns, ha->ct_sns_dma);
4307 ha->ct_sns = NULL;
4308 ha->ct_sns_dma = 0;
e8711085
AV		 4309fail_free_ms_iocb:
4310 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
4311 ha->ms_iocb = NULL;
4312 ha->ms_iocb_dma = 0;
fc1ffd6c
QT		 4313
4314 if (ha->sns_cmd)
4315 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
4316 ha->sns_cmd, ha->sns_cmd_dma);
e315cd28 4317fail_dma_pool:
50b81275
GM		 4318 if (ql2xenabledif) {
4319 struct dsd_dma *dsd, *nxt;
4320
4321 list_for_each_entry_safe(dsd, nxt, &ha->pool.unusable.head,
4322 list) {
4323 list_del(&dsd->list);
4324 dma_pool_free(ha->dif_bundl_pool, dsd->dsd_addr,
4325 dsd->dsd_list_dma);
4326 ha->dif_bundle_dma_allocs--;
4327 kfree(dsd);
4328 ha->dif_bundle_kallocs--;
4329 ha->pool.unusable.count--;
4330 }
4331 dma_pool_destroy(ha->dif_bundl_pool);
4332 ha->dif_bundl_pool = NULL;
4333 }
4334
4335fail_dif_bundl_dma_pool:
bad75002 4336 if (IS_QLA82XX(ha) || ql2xenabledif) {
a9083016
GM		 4337 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
4338 ha->fcp_cmnd_dma_pool = NULL;
4339 }
4340fail_dl_dma_pool:
bad75002 4341 if (IS_QLA82XX(ha) || ql2xenabledif) {
a9083016
GM		 4342 dma_pool_destroy(ha->dl_dma_pool);
4343 ha->dl_dma_pool = NULL;
4344 }
4345fail_s_dma_pool:
e315cd28
AC		 4346 dma_pool_destroy(ha->s_dma_pool);
4347 ha->s_dma_pool = NULL;
e8711085
AV		 4348fail_free_nvram:
4349 kfree(ha->nvram);
4350 ha->nvram = NULL;
a9083016 4351fail_free_ctx_mempool:
75c1d48a 4352 mempool_destroy(ha->ctx_mempool);
a9083016 4353 ha->ctx_mempool = NULL;
e8711085 4354fail_free_srb_mempool:
75c1d48a 4355 mempool_destroy(ha->srb_mempool);
e8711085 4356 ha->srb_mempool = NULL;
e8711085 4357fail_free_gid_list:
642ef983
CD		 4358 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
4359 ha->gid_list,
e315cd28 4360 ha->gid_list_dma);
e8711085
AV		 4361 ha->gid_list = NULL;
4362 ha->gid_list_dma = 0;
2d70c103
NB		 4363fail_free_tgt_mem:
4364 qlt_mem_free(ha);
e315cd28
AC		 4365fail_free_init_cb:
4366 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb,
4367 ha->init_cb_dma);
4368 ha->init_cb = NULL;
4369 ha->init_cb_dma = 0;
e8711085 4370fail:
7c3df132
SK		 4371 ql_log(ql_log_fatal, NULL, 0x0030,
4372 "Memory allocation failure.\n");
e8711085 4373 return -ENOMEM;
1da177e4
LT		 4374}
4375
b0d6cabd
HM		 4376int
4377qla2x00_set_exlogins_buffer(scsi_qla_host_t *vha)
4378{
4379 int rval;
4380 uint16_t size, max_cnt, temp;
4381 struct qla_hw_data *ha = vha->hw;
4382
4383 /* Return if we don't need to alloacate any extended logins */
4384 if (!ql2xexlogins)
4385 return QLA_SUCCESS;
4386
99e1b683
QT		 4387 if (!IS_EXLOGIN_OFFLD_CAPABLE(ha))
4388 return QLA_SUCCESS;
4389
b0d6cabd
HM		 4390 ql_log(ql_log_info, vha, 0xd021, "EXLOGIN count: %d.\n", ql2xexlogins);
4391 max_cnt = 0;
4392 rval = qla_get_exlogin_status(vha, &size, &max_cnt);
4393 if (rval != QLA_SUCCESS) {
4394 ql_log_pci(ql_log_fatal, ha->pdev, 0xd029,
4395 "Failed to get exlogin status.\n");
4396 return rval;
4397 }
4398
4399 temp = (ql2xexlogins > max_cnt) ? max_cnt : ql2xexlogins;
99e1b683
QT		 4400 temp *= size;
4401
4402 if (temp != ha->exlogin_size) {
4403 qla2x00_free_exlogin_buffer(ha);
4404 ha->exlogin_size = temp;
4405
4406 ql_log(ql_log_info, vha, 0xd024,
4407 "EXLOGIN: max_logins=%d, portdb=0x%x, total=%d.\n",
4408 max_cnt, size, temp);
4409
4410 ql_log(ql_log_info, vha, 0xd025,
4411 "EXLOGIN: requested size=0x%x\n", ha->exlogin_size);
4412
4413 /* Get consistent memory for extended logins */
4414 ha->exlogin_buf = dma_alloc_coherent(&ha->pdev->dev,
4415 ha->exlogin_size, &ha->exlogin_buf_dma, GFP_KERNEL);
4416 if (!ha->exlogin_buf) {
4417 ql_log_pci(ql_log_fatal, ha->pdev, 0xd02a,
b0d6cabd 4418 "Failed to allocate memory for exlogin_buf_dma.\n");
99e1b683
QT		 4419 return -ENOMEM;
4420 }
b0d6cabd
HM		 4421 }
4422
4423 /* Now configure the dma buffer */
4424 rval = qla_set_exlogin_mem_cfg(vha, ha->exlogin_buf_dma);
4425 if (rval) {
83548fe2 4426 ql_log(ql_log_fatal, vha, 0xd033,
b0d6cabd
HM		 4427 "Setup extended login buffer ****FAILED****.\n");
4428 qla2x00_free_exlogin_buffer(ha);
4429 }
4430
4431 return rval;
4432}
4433
4434/*
4435* qla2x00_free_exlogin_buffer
4436*
4437* Input:
4438* ha = adapter block pointer
4439*/
4440void
4441qla2x00_free_exlogin_buffer(struct qla_hw_data *ha)
4442{
4443 if (ha->exlogin_buf) {
4444 dma_free_coherent(&ha->pdev->dev, ha->exlogin_size,
4445 ha->exlogin_buf, ha->exlogin_buf_dma);
4446 ha->exlogin_buf = NULL;
4447 ha->exlogin_size = 0;
4448 }
4449}
4450
99e1b683
QT		 4451static void
4452qla2x00_number_of_exch(scsi_qla_host_t *vha, u32 *ret_cnt, u16 max_cnt)
4453{
4454 u32 temp;
0645cb83 4455 struct init_cb_81xx *icb = (struct init_cb_81xx *)&vha->hw->init_cb;
99e1b683
QT		 4456 *ret_cnt = FW_DEF_EXCHANGES_CNT;
4457
d1e3635a
QT		 4458 if (max_cnt > vha->hw->max_exchg)
4459 max_cnt = vha->hw->max_exchg;
4460
99e1b683 4461 if (qla_ini_mode_enabled(vha)) {
0645cb83
QT		 4462 if (vha->ql2xiniexchg > max_cnt)
4463 vha->ql2xiniexchg = max_cnt;
4464
4465 if (vha->ql2xiniexchg > FW_DEF_EXCHANGES_CNT)
4466 *ret_cnt = vha->ql2xiniexchg;
99e1b683 4467
99e1b683 4468 } else if (qla_tgt_mode_enabled(vha)) {
0645cb83
QT		 4469 if (vha->ql2xexchoffld > max_cnt) {
4470 vha->ql2xexchoffld = max_cnt;
4471 icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld);
4472 }
99e1b683 4473
0645cb83
QT		 4474 if (vha->ql2xexchoffld > FW_DEF_EXCHANGES_CNT)
4475 *ret_cnt = vha->ql2xexchoffld;
99e1b683 4476 } else if (qla_dual_mode_enabled(vha)) {
0645cb83 4477 temp = vha->ql2xiniexchg + vha->ql2xexchoffld;
99e1b683 4478 if (temp > max_cnt) {
0645cb83
QT		 4479 vha->ql2xiniexchg -= (temp - max_cnt)/2;
4480 vha->ql2xexchoffld -= (((temp - max_cnt)/2) + 1);
99e1b683 4481 temp = max_cnt;
0645cb83 4482 icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld);
99e1b683
QT		 4483 }
4484
4485 if (temp > FW_DEF_EXCHANGES_CNT)
4486 *ret_cnt = temp;
4487 }
4488}
4489
2f56a7f1
HM		 4490int
4491qla2x00_set_exchoffld_buffer(scsi_qla_host_t *vha)
4492{
4493 int rval;
d1e3635a
QT		 4494 u16 size, max_cnt;
4495 u32 actual_cnt, totsz;
2f56a7f1
HM		 4496 struct qla_hw_data *ha = vha->hw;
4497
99e1b683
QT		 4498 if (!ha->flags.exchoffld_enabled)
4499 return QLA_SUCCESS;
4500
4501 if (!IS_EXCHG_OFFLD_CAPABLE(ha))
2f56a7f1
HM		 4502 return QLA_SUCCESS;
4503
2f56a7f1
HM		 4504 max_cnt = 0;
4505 rval = qla_get_exchoffld_status(vha, &size, &max_cnt);
4506 if (rval != QLA_SUCCESS) {
4507 ql_log_pci(ql_log_fatal, ha->pdev, 0xd012,
4508 "Failed to get exlogin status.\n");
4509 return rval;
4510 }
4511
d1e3635a
QT		 4512 qla2x00_number_of_exch(vha, &actual_cnt, max_cnt);
4513 ql_log(ql_log_info, vha, 0xd014,
4514 "Actual exchange offload count: %d.\n", actual_cnt);
4515
4516 totsz = actual_cnt * size;
2f56a7f1 4517
d1e3635a 4518 if (totsz != ha->exchoffld_size) {
99e1b683 4519 qla2x00_free_exchoffld_buffer(ha);
0645cb83
QT		 4520 if (actual_cnt <= FW_DEF_EXCHANGES_CNT) {
4521 ha->exchoffld_size = 0;
4522 ha->flags.exchoffld_enabled = 0;
4523 return QLA_SUCCESS;
4524 }
4525
d1e3635a 4526 ha->exchoffld_size = totsz;
99e1b683
QT		 4527
4528 ql_log(ql_log_info, vha, 0xd016,
d1e3635a
QT		 4529 "Exchange offload: max_count=%d, actual count=%d entry sz=0x%x, total sz=0x%x\n",
4530 max_cnt, actual_cnt, size, totsz);
99e1b683
QT		 4531
4532 ql_log(ql_log_info, vha, 0xd017,
4533 "Exchange Buffers requested size = 0x%x\n",
4534 ha->exchoffld_size);
4535
4536 /* Get consistent memory for extended logins */
4537 ha->exchoffld_buf = dma_alloc_coherent(&ha->pdev->dev,
4538 ha->exchoffld_size, &ha->exchoffld_buf_dma, GFP_KERNEL);
4539 if (!ha->exchoffld_buf) {
4540 ql_log_pci(ql_log_fatal, ha->pdev, 0xd013,
d1e3635a
QT		 4541 "Failed to allocate memory for Exchange Offload.\n");
4542
4543 if (ha->max_exchg >
4544 (FW_DEF_EXCHANGES_CNT + REDUCE_EXCHANGES_CNT)) {
4545 ha->max_exchg -= REDUCE_EXCHANGES_CNT;
4546 } else if (ha->max_exchg >
4547 (FW_DEF_EXCHANGES_CNT + 512)) {
4548 ha->max_exchg -= 512;
4549 } else {
4550 ha->flags.exchoffld_enabled = 0;
4551 ql_log_pci(ql_log_fatal, ha->pdev, 0xd013,
4552 "Disabling Exchange offload due to lack of memory\n");
4553 }
4554 ha->exchoffld_size = 0;
4555
99e1b683
QT		 4556 return -ENOMEM;
4557 }
0645cb83
QT		 4558 } else if (!ha->exchoffld_buf || (actual_cnt <= FW_DEF_EXCHANGES_CNT)) {
4559 /* pathological case */
4560 qla2x00_free_exchoffld_buffer(ha);
4561 ha->exchoffld_size = 0;
4562 ha->flags.exchoffld_enabled = 0;
4563 ql_log(ql_log_info, vha, 0xd016,
4564 "Exchange offload not enable: offld size=%d, actual count=%d entry sz=0x%x, total sz=0x%x.\n",
4565 ha->exchoffld_size, actual_cnt, size, totsz);
4566 return 0;
2f56a7f1
HM		 4567 }
4568
4569 /* Now configure the dma buffer */
99e1b683 4570 rval = qla_set_exchoffld_mem_cfg(vha);
2f56a7f1
HM		 4571 if (rval) {
4572 ql_log(ql_log_fatal, vha, 0xd02e,
4573 "Setup exchange offload buffer ****FAILED****.\n");
4574 qla2x00_free_exchoffld_buffer(ha);
99e1b683
QT		 4575 } else {
4576 /* re-adjust number of target exchange */
4577 struct init_cb_81xx *icb = (struct init_cb_81xx *)ha->init_cb;
4578
4579 if (qla_ini_mode_enabled(vha))
4580 icb->exchange_count = 0;
4581 else
0645cb83 4582 icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld);
2f56a7f1
HM		 4583 }
4584
4585 return rval;
4586}
4587
4588/*
4589* qla2x00_free_exchoffld_buffer
4590*
4591* Input:
4592* ha = adapter block pointer
4593*/
4594void
4595qla2x00_free_exchoffld_buffer(struct qla_hw_data *ha)
4596{
4597 if (ha->exchoffld_buf) {
4598 dma_free_coherent(&ha->pdev->dev, ha->exchoffld_size,
4599 ha->exchoffld_buf, ha->exchoffld_buf_dma);
4600 ha->exchoffld_buf = NULL;
4601 ha->exchoffld_size = 0;
4602 }
4603}
4604
1da177e4 4605/*
e30d1756
MI		 4606* qla2x00_free_fw_dump
4607* Frees fw dump stuff.
1da177e4
LT		 4608*
4609* Input:
7ec0effd 4610* ha = adapter block pointer
1da177e4 4611*/
a824ebb3 4612static void
e30d1756 4613qla2x00_free_fw_dump(struct qla_hw_data *ha)
1da177e4 4614{
a28d9e4e
JC		 4615 struct fwdt *fwdt = ha->fwdt;
4616 uint j;
4617
df613b96 4618 if (ha->fce)
f73cb695
CD		 4619 dma_free_coherent(&ha->pdev->dev,
4620 FCE_SIZE, ha->fce, ha->fce_dma);
df613b96 4621
f73cb695
CD		 4622 if (ha->eft)
4623 dma_free_coherent(&ha->pdev->dev,
4624 EFT_SIZE, ha->eft, ha->eft_dma);
4625
4626 if (ha->fw_dump)
a7a167bf 4627 vfree(ha->fw_dump);
f73cb695 4628
e30d1756
MI		 4629 ha->fce = NULL;
4630 ha->fce_dma = 0;
4631 ha->eft = NULL;
4632 ha->eft_dma = 0;
e30d1756 4633 ha->fw_dumped = 0;
61f098dd 4634 ha->fw_dump_cap_flags = 0;
e30d1756 4635 ha->fw_dump_reading = 0;
f73cb695
CD		 4636 ha->fw_dump = NULL;
4637 ha->fw_dump_len = 0;
a28d9e4e
JC		 4638
4639 for (j = 0; j < 2; j++, fwdt++) {
4640 if (fwdt->template)
4641 vfree(fwdt->template);
4642 fwdt->template = NULL;
4643 fwdt->length = 0;
4644 }
e30d1756
MI		 4645}
4646
4647/*
4648* qla2x00_mem_free
4649* Frees all adapter allocated memory.
4650*
4651* Input:
4652* ha = adapter block pointer.
4653*/
4654static void
4655qla2x00_mem_free(struct qla_hw_data *ha)
4656{
4657 qla2x00_free_fw_dump(ha);
4658
81178772
SK		 4659 if (ha->mctp_dump)
4660 dma_free_coherent(&ha->pdev->dev, MCTP_DUMP_SIZE, ha->mctp_dump,
4661 ha->mctp_dump_dma);
5365bf99 4662 ha->mctp_dump = NULL;
81178772 4663
75c1d48a 4664 mempool_destroy(ha->srb_mempool);
5365bf99 4665 ha->srb_mempool = NULL;
a7a167bf 4666
11bbc1d8
AV		 4667 if (ha->dcbx_tlv)
4668 dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE,
4669 ha->dcbx_tlv, ha->dcbx_tlv_dma);
5365bf99 4670 ha->dcbx_tlv = NULL;
11bbc1d8 4671
ce0423f4
AV		 4672 if (ha->xgmac_data)
4673 dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE,
4674 ha->xgmac_data, ha->xgmac_data_dma);
5365bf99 4675 ha->xgmac_data = NULL;
ce0423f4 4676
1da177e4
LT		 4677 if (ha->sns_cmd)
4678 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
e315cd28 4679 ha->sns_cmd, ha->sns_cmd_dma);
5365bf99
BVA		 4680 ha->sns_cmd = NULL;
4681 ha->sns_cmd_dma = 0;
1da177e4
LT		 4682
4683 if (ha->ct_sns)
4684 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
e315cd28 4685 ha->ct_sns, ha->ct_sns_dma);
5365bf99
BVA		 4686 ha->ct_sns = NULL;
4687 ha->ct_sns_dma = 0;
1da177e4 4688
88729e53 4689 if (ha->sfp_data)
e4e3a2ce
QT		 4690 dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE, ha->sfp_data,
4691 ha->sfp_data_dma);
5365bf99 4692 ha->sfp_data = NULL;
88729e53 4693
3f006ac3
MH		 4694 if (ha->flt)
4695 dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE,
4696 ha->flt, ha->flt_dma);
dc035d4e
BVA		 4697 ha->flt = NULL;
4698 ha->flt_dma = 0;
3f006ac3 4699
1da177e4
LT		 4700 if (ha->ms_iocb)
4701 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
5365bf99
BVA		 4702 ha->ms_iocb = NULL;
4703 ha->ms_iocb_dma = 0;
1da177e4 4704
b64b0e8f 4705 if (ha->ex_init_cb)
a9083016
GM		 4706 dma_pool_free(ha->s_dma_pool,
4707 ha->ex_init_cb, ha->ex_init_cb_dma);
5365bf99
BVA		 4708 ha->ex_init_cb = NULL;
4709 ha->ex_init_cb_dma = 0;
b64b0e8f 4710
5ff1d584
AV		 4711 if (ha->async_pd)
4712 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
5365bf99
BVA		 4713 ha->async_pd = NULL;
4714 ha->async_pd_dma = 0;
5ff1d584 4715
75c1d48a 4716 dma_pool_destroy(ha->s_dma_pool);
5365bf99 4717 ha->s_dma_pool = NULL;
1da177e4 4718
1da177e4 4719 if (ha->gid_list)
642ef983
CD		 4720 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
4721 ha->gid_list, ha->gid_list_dma);
5365bf99
BVA		 4722 ha->gid_list = NULL;
4723 ha->gid_list_dma = 0;
1da177e4 4724
a9083016
GM		 4725 if (IS_QLA82XX(ha)) {
4726 if (!list_empty(&ha->gbl_dsd_list)) {
4727 struct dsd_dma *dsd_ptr, *tdsd_ptr;
4728
4729 /* clean up allocated prev pool */
4730 list_for_each_entry_safe(dsd_ptr,
4731 tdsd_ptr, &ha->gbl_dsd_list, list) {
4732 dma_pool_free(ha->dl_dma_pool,
4733 dsd_ptr->dsd_addr, dsd_ptr->dsd_list_dma);
4734 list_del(&dsd_ptr->list);
4735 kfree(dsd_ptr);
4736 }
4737 }
4738 }
4739
75c1d48a 4740 dma_pool_destroy(ha->dl_dma_pool);
5365bf99 4741 ha->dl_dma_pool = NULL;
a9083016 4742
75c1d48a 4743 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
5365bf99 4744 ha->fcp_cmnd_dma_pool = NULL;
a9083016 4745
75c1d48a 4746 mempool_destroy(ha->ctx_mempool);
5365bf99 4747 ha->ctx_mempool = NULL;
a9083016 4748
26a77799 4749 if (ql2xenabledif && ha->dif_bundl_pool) {
50b81275
GM		 4750 struct dsd_dma *dsd, *nxt;
4751
4752 list_for_each_entry_safe(dsd, nxt, &ha->pool.unusable.head,
4753 list) {
4754 list_del(&dsd->list);
4755 dma_pool_free(ha->dif_bundl_pool, dsd->dsd_addr,
4756 dsd->dsd_list_dma);
4757 ha->dif_bundle_dma_allocs--;
4758 kfree(dsd);
4759 ha->dif_bundle_kallocs--;
4760 ha->pool.unusable.count--;
4761 }
4762 list_for_each_entry_safe(dsd, nxt, &ha->pool.good.head, list) {
4763 list_del(&dsd->list);
4764 dma_pool_free(ha->dif_bundl_pool, dsd->dsd_addr,
4765 dsd->dsd_list_dma);
4766 ha->dif_bundle_dma_allocs--;
4767 kfree(dsd);
4768 ha->dif_bundle_kallocs--;
4769 }
4770 }
4771
0b3b6fe2 4772 dma_pool_destroy(ha->dif_bundl_pool);
dc035d4e 4773 ha->dif_bundl_pool = NULL;
50b81275 4774
2d70c103
NB		 4775 qlt_mem_free(ha);
4776
e315cd28
AC		 4777 if (ha->init_cb)
4778 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size,
a9083016 4779 ha->init_cb, ha->init_cb_dma);
5365bf99
BVA		 4780 ha->init_cb = NULL;
4781 ha->init_cb_dma = 0;
6a2cf8d3 4782
6d634067 4783 vfree(ha->optrom_buffer);
5365bf99 4784 ha->optrom_buffer = NULL;
6d634067 4785 kfree(ha->nvram);
5365bf99 4786 ha->nvram = NULL;
6d634067 4787 kfree(ha->npiv_info);
5365bf99 4788 ha->npiv_info = NULL;
6d634067 4789 kfree(ha->swl);
5365bf99 4790 ha->swl = NULL;
6d634067 4791 kfree(ha->loop_id_map);
6a2cf8d3 4792 ha->loop_id_map = NULL;
e315cd28 4793}
1da177e4 4794
e315cd28
AC		 4795struct scsi_qla_host *qla2x00_create_host(struct scsi_host_template *sht,
4796 struct qla_hw_data *ha)
4797{
4798 struct Scsi_Host *host;
4799 struct scsi_qla_host *vha = NULL;
854165f4 4800
e315cd28 4801 host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t));
41dc529a 4802 if (!host) {
7c3df132
SK		 4803 ql_log_pci(ql_log_fatal, ha->pdev, 0x0107,
4804 "Failed to allocate host from the scsi layer, aborting.\n");
41dc529a 4805 return NULL;
e315cd28
AC		 4806 }
4807
4808 /* Clear our data area */
4809 vha = shost_priv(host);
4810 memset(vha, 0, sizeof(scsi_qla_host_t));
4811
4812 vha->host = host;
4813 vha->host_no = host->host_no;
4814 vha->hw = ha;
4815
0645cb83
QT		 4816 vha->qlini_mode = ql2x_ini_mode;
4817 vha->ql2xexchoffld = ql2xexchoffld;
4818 vha->ql2xiniexchg = ql2xiniexchg;
4819
e315cd28
AC		 4820 INIT_LIST_HEAD(&vha->vp_fcports);
4821 INIT_LIST_HEAD(&vha->work_list);
4822 INIT_LIST_HEAD(&vha->list);
8b2f5ff3
SN		 4823 INIT_LIST_HEAD(&vha->qla_cmd_list);
4824 INIT_LIST_HEAD(&vha->qla_sess_op_cmd_list);
71cdc079 4825 INIT_LIST_HEAD(&vha->logo_list);
b7bd104e 4826 INIT_LIST_HEAD(&vha->plogi_ack_list);
d7459527 4827 INIT_LIST_HEAD(&vha->qp_list);
41dc529a 4828 INIT_LIST_HEAD(&vha->gnl.fcports);
2d73ac61 4829 INIT_LIST_HEAD(&vha->gpnid_list);
9b3e0f4d 4830 INIT_WORK(&vha->iocb_work, qla2x00_iocb_work_fn);
e315cd28 4831
f999f4c1 4832 spin_lock_init(&vha->work_lock);
8b2f5ff3 4833 spin_lock_init(&vha->cmd_list_lock);
726b8548 4834 init_waitqueue_head(&vha->fcport_waitQ);
c4a9b538 4835 init_waitqueue_head(&vha->vref_waitq);
f999f4c1 4836
2fdbc65e
BVA		 4837 vha->gnl.size = sizeof(struct get_name_list_extended) *
4838 (ha->max_loop_id + 1);
41dc529a
QT		 4839 vha->gnl.l = dma_alloc_coherent(&ha->pdev->dev,
4840 vha->gnl.size, &vha->gnl.ldma, GFP_KERNEL);
4841 if (!vha->gnl.l) {
83548fe2 4842 ql_log(ql_log_fatal, vha, 0xd04a,
41dc529a 4843 "Alloc failed for name list.\n");
26a77799 4844 scsi_host_put(vha->host);
41dc529a
QT		 4845 return NULL;
4846 }
f999f4c1 4847
a4239945
QT		 4848 /* todo: what about ext login? */
4849 vha->scan.size = ha->max_fibre_devices * sizeof(struct fab_scan_rp);
4850 vha->scan.l = vmalloc(vha->scan.size);
4851 if (!vha->scan.l) {
4852 ql_log(ql_log_fatal, vha, 0xd04a,
4853 "Alloc failed for scan database.\n");
4854 dma_free_coherent(&ha->pdev->dev, vha->gnl.size,
4855 vha->gnl.l, vha->gnl.ldma);
26a77799 4856 scsi_host_put(vha->host);
a4239945
QT		 4857 return NULL;
4858 }
f352eeb7 4859 INIT_DELAYED_WORK(&vha->scan.scan_work, qla_scan_work_fn);
a4239945 4860
e315cd28 4861 sprintf(vha->host_str, "%s_%ld", QLA2XXX_DRIVER_NAME, vha->host_no);
7c3df132
SK		 4862 ql_dbg(ql_dbg_init, vha, 0x0041,
4863 "Allocated the host=%p hw=%p vha=%p dev_name=%s",
4864 vha->host, vha->hw, vha,
4865 dev_name(&(ha->pdev->dev)));
4866
e315cd28 4867 return vha;
1da177e4
LT		 4868}
4869
726b8548 4870struct qla_work_evt *
f999f4c1 4871qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type)
0971de7f
AV		 4872{
4873 struct qla_work_evt *e;
feafb7b1
AE		 4874 uint8_t bail;
4875
4876 QLA_VHA_MARK_BUSY(vha, bail);
4877 if (bail)
4878 return NULL;
0971de7f 4879
f999f4c1 4880 e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC);
feafb7b1
AE		 4881 if (!e) {
4882 QLA_VHA_MARK_NOT_BUSY(vha);
0971de7f 4883 return NULL;
feafb7b1 4884 }
0971de7f
AV		 4885
4886 INIT_LIST_HEAD(&e->list);
4887 e->type = type;
4888 e->flags = QLA_EVT_FLAG_FREE;
4889 return e;
4890}
4891
726b8548 4892int
f999f4c1 4893qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e)
0971de7f 4894{
f999f4c1 4895 unsigned long flags;
9b3e0f4d 4896 bool q = false;
0971de7f 4897
f999f4c1 4898 spin_lock_irqsave(&vha->work_lock, flags);
e315cd28 4899 list_add_tail(&e->list, &vha->work_list);
9b3e0f4d
QT		 4900
4901 if (!test_and_set_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags))
4902 q = true;
4903
f999f4c1 4904 spin_unlock_irqrestore(&vha->work_lock, flags);
ec7193e2 4905
9b3e0f4d
QT		 4906 if (q)
4907 queue_work(vha->hw->wq, &vha->iocb_work);
f999f4c1 4908
0971de7f
AV		 4909 return QLA_SUCCESS;
4910}
4911
4912int
e315cd28 4913qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code,
0971de7f
AV		 4914 u32 data)
4915{
4916 struct qla_work_evt *e;
4917
f999f4c1 4918 e = qla2x00_alloc_work(vha, QLA_EVT_AEN);
0971de7f
AV		 4919 if (!e)
4920 return QLA_FUNCTION_FAILED;
4921
4922 e->u.aen.code = code;
4923 e->u.aen.data = data;
f999f4c1 4924 return qla2x00_post_work(vha, e);
0971de7f
AV		 4925}
4926
8a659571
AV		 4927int
4928qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb)
4929{
4930 struct qla_work_evt *e;
4931
f999f4c1 4932 e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK);
8a659571
AV		 4933 if (!e)
4934 return QLA_FUNCTION_FAILED;
4935
4936 memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t));
f999f4c1 4937 return qla2x00_post_work(vha, e);
8a659571
AV		 4938}
4939
ac280b67
AV		 4940#define qla2x00_post_async_work(name, type) \
4941int qla2x00_post_async_##name##_work( \
4942 struct scsi_qla_host *vha, \
4943 fc_port_t *fcport, uint16_t *data) \
4944{ \
4945 struct qla_work_evt *e; \
4946 \
4947 e = qla2x00_alloc_work(vha, type); \
4948 if (!e) \
4949 return QLA_FUNCTION_FAILED; \
4950 \
4951 e->u.logio.fcport = fcport; \
4952 if (data) { \
4953 e->u.logio.data[0] = data[0]; \
4954 e->u.logio.data[1] = data[1]; \
4955 } \
6d674927 4956 fcport->flags |= FCF_ASYNC_ACTIVE; \
ac280b67
AV		 4957 return qla2x00_post_work(vha, e); \
4958}
4959
4960qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN);
ac280b67
AV		 4961qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT);
4962qla2x00_post_async_work(logout_done, QLA_EVT_ASYNC_LOGOUT_DONE);
5ff1d584 4963qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC);
11aea16a
QT		 4964qla2x00_post_async_work(prlo, QLA_EVT_ASYNC_PRLO);
4965qla2x00_post_async_work(prlo_done, QLA_EVT_ASYNC_PRLO_DONE);
ac280b67 4966
3420d36c
AV		 4967int
4968qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code)
4969{
4970 struct qla_work_evt *e;
4971
4972 e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT);
4973 if (!e)
4974 return QLA_FUNCTION_FAILED;
4975
4976 e->u.uevent.code = code;
4977 return qla2x00_post_work(vha, e);
4978}
4979
4980static void
4981qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code)
4982{
4983 char event_string[40];
4984 char *envp[] = { event_string, NULL };
4985
4986 switch (code) {
4987 case QLA_UEVENT_CODE_FW_DUMP:
4988 snprintf(event_string, sizeof(event_string), "FW_DUMP=%ld",
4989 vha->host_no);
4990 break;
4991 default:
4992 /* do nothing */
4993 break;
4994 }
4995 kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp);
4996}
4997
8ae6d9c7
GM		 4998int
4999qlafx00_post_aenfx_work(struct scsi_qla_host *vha, uint32_t evtcode,
5000 uint32_t *data, int cnt)
5001{
5002 struct qla_work_evt *e;
5003
5004 e = qla2x00_alloc_work(vha, QLA_EVT_AENFX);
5005 if (!e)
5006 return QLA_FUNCTION_FAILED;
5007
5008 e->u.aenfx.evtcode = evtcode;
5009 e->u.aenfx.count = cnt;
5010 memcpy(e->u.aenfx.mbx, data, sizeof(*data) * cnt);
5011 return qla2x00_post_work(vha, e);
5012}
5013
cd4ed6b4 5014void qla24xx_sched_upd_fcport(fc_port_t *fcport)
726b8548 5015{
cd4ed6b4 5016 unsigned long flags;
726b8548 5017
cd4ed6b4
QT		 5018 if (IS_SW_RESV_ADDR(fcport->d_id))
5019 return;
726b8548 5020
cd4ed6b4
QT		 5021 spin_lock_irqsave(&fcport->vha->work_lock, flags);
5022 if (fcport->disc_state == DSC_UPD_FCPORT) {
5023 spin_unlock_irqrestore(&fcport->vha->work_lock, flags);
5024 return;
5025 }
5026 fcport->jiffies_at_registration = jiffies;
5027 fcport->sec_since_registration = 0;
5028 fcport->next_disc_state = DSC_DELETED;
5029 fcport->disc_state = DSC_UPD_FCPORT;
5030 spin_unlock_irqrestore(&fcport->vha->work_lock, flags);
5031
5032 queue_work(system_unbound_wq, &fcport->reg_work);
726b8548
QT		 5033}
5034
5035static
5036void qla24xx_create_new_sess(struct scsi_qla_host *vha, struct qla_work_evt *e)
5037{
5038 unsigned long flags;
b5d15312 5039 fc_port_t *fcport = NULL, *tfcp;
726b8548
QT		 5040 struct qlt_plogi_ack_t *pla =
5041 (struct qlt_plogi_ack_t *)e->u.new_sess.pla;
b5d15312 5042 uint8_t free_fcport = 0;
726b8548 5043
9cd883f0
QT		 5044 ql_dbg(ql_dbg_disc, vha, 0xffff,
5045 "%s %d %8phC enter\n",
5046 __func__, __LINE__, e->u.new_sess.port_name);
5047
726b8548
QT		 5048 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
5049 fcport = qla2x00_find_fcport_by_wwpn(vha, e->u.new_sess.port_name, 1);
5050 if (fcport) {
5051 fcport->d_id = e->u.new_sess.id;
5052 if (pla) {
5053 fcport->fw_login_state = DSC_LS_PLOGI_PEND;
9b3e0f4d
QT		 5054 memcpy(fcport->node_name,
5055 pla->iocb.u.isp24.u.plogi.node_name,
5056 WWN_SIZE);
726b8548
QT		 5057 qlt_plogi_ack_link(vha, pla, fcport, QLT_PLOGI_LINK_SAME_WWN);
5058 /* we took an extra ref_count to prevent PLOGI ACK when
5059 * fcport/sess has not been created.
5060 */
5061 pla->ref_count--;
5062 }
5063 } else {
b5d15312 5064 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
726b8548
QT		 5065 fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
5066 if (fcport) {
5067 fcport->d_id = e->u.new_sess.id;
726b8548
QT		 5068 fcport->flags |= FCF_FABRIC_DEVICE;
5069 fcport->fw_login_state = DSC_LS_PLOGI_PEND;
c64a87f9 5070 if (e->u.new_sess.fc4_type == FS_FC4TYPE_FCP)
a4239945 5071 fcport->fc4_type = FC4_TYPE_FCP_SCSI;
726b8548 5072
c64a87f9 5073 if (e->u.new_sess.fc4_type == FS_FC4TYPE_NVME) {
2b5b9647
DT		 5074 fcport->fc4_type = FC4_TYPE_OTHER;
5075 fcport->fc4f_nvme = FC4_TYPE_NVME;
5076 }
33b28357 5077
726b8548
QT		 5078 memcpy(fcport->port_name, e->u.new_sess.port_name,
5079 WWN_SIZE);
b5d15312
QT		 5080 } else {
5081 ql_dbg(ql_dbg_disc, vha, 0xffff,
5082 "%s %8phC mem alloc fail.\n",
5083 __func__, e->u.new_sess.port_name);
5084
5085 if (pla)
5086 kmem_cache_free(qla_tgt_plogi_cachep, pla);
5087 return;
5088 }
5089
5090 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
a4239945 5091 /* search again to make sure no one else got ahead */
b5d15312
QT		 5092 tfcp = qla2x00_find_fcport_by_wwpn(vha,
5093 e->u.new_sess.port_name, 1);
5094 if (tfcp) {
5095 /* should rarily happen */
5096 ql_dbg(ql_dbg_disc, vha, 0xffff,
5097 "%s %8phC found existing fcport b4 add. DS %d LS %d\n",
5098 __func__, tfcp->port_name, tfcp->disc_state,
5099 tfcp->fw_login_state);
5100
5101 free_fcport = 1;
5102 } else {
726b8548
QT		 5103 list_add_tail(&fcport->list, &vha->vp_fcports);
5104
19759033
QT		 5105 }
5106 if (pla) {
5107 qlt_plogi_ack_link(vha, pla, fcport,
5108 QLT_PLOGI_LINK_SAME_WWN);
5109 pla->ref_count--;
726b8548
QT		 5110 }
5111 }
5112 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
5113
5114 if (fcport) {
a4239945
QT		 5115 fcport->id_changed = 1;
5116 fcport->scan_state = QLA_FCPORT_FOUND;
8b5292bc 5117 fcport->chip_reset = vha->hw->base_qpair->chip_reset;
a4239945
QT		 5118 memcpy(fcport->node_name, e->u.new_sess.node_name, WWN_SIZE);
5119
5ef696aa 5120 if (pla) {
9cd883f0
QT		 5121 if (pla->iocb.u.isp24.status_subcode == ELS_PRLI) {
5122 u16 wd3_lo;
5123
5124 fcport->fw_login_state = DSC_LS_PRLI_PEND;
5125 fcport->local = 0;
5126 fcport->loop_id =
5127 le16_to_cpu(
5128 pla->iocb.u.isp24.nport_handle);
5129 fcport->fw_login_state = DSC_LS_PRLI_PEND;
5130 wd3_lo =
5131 le16_to_cpu(
5132 pla->iocb.u.isp24.u.prli.wd3_lo);
5133
5134 if (wd3_lo & BIT_7)
5135 fcport->conf_compl_supported = 1;
5136
5137 if ((wd3_lo & BIT_4) == 0)
5138 fcport->port_type = FCT_INITIATOR;
5139 else
5140 fcport->port_type = FCT_TARGET;
5141 }
726b8548 5142 qlt_plogi_ack_unref(vha, pla);
5ef696aa 5143 } else {
1c6cacf4
HR		 5144 fc_port_t *dfcp = NULL;
5145
5ef696aa
QT		 5146 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
5147 tfcp = qla2x00_find_fcport_by_nportid(vha,
5148 &e->u.new_sess.id, 1);
5149 if (tfcp && (tfcp != fcport)) {
5150 /*
5151 * We have a conflict fcport with same NportID.
5152 */
5153 ql_dbg(ql_dbg_disc, vha, 0xffff,
5154 "%s %8phC found conflict b4 add. DS %d LS %d\n",
5155 __func__, tfcp->port_name, tfcp->disc_state,
5156 tfcp->fw_login_state);
5157
5158 switch (tfcp->disc_state) {
5159 case DSC_DELETED:
5160 break;
5161 case DSC_DELETE_PEND:
5162 fcport->login_pause = 1;
5163 tfcp->conflict = fcport;
5164 break;
5165 default:
5166 fcport->login_pause = 1;
5167 tfcp->conflict = fcport;
1c6cacf4 5168 dfcp = tfcp;
5ef696aa
QT		 5169 break;
5170 }
5171 }
5172 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
1c6cacf4
HR		 5173 if (dfcp)
5174 qlt_schedule_sess_for_deletion(tfcp);
a4239945 5175
a4239945 5176
8777e431
QT		 5177 if (N2N_TOPO(vha->hw))
5178 fcport->flags &= ~FCF_FABRIC_DEVICE;
5179
5180 if (N2N_TOPO(vha->hw)) {
5181 if (vha->flags.nvme_enabled) {
5182 fcport->fc4f_nvme = 1;
5183 fcport->n2n_flag = 1;
5184 }
5185 fcport->fw_login_state = 0;
5186 /*
5187 * wait link init done before sending login
5188 */
5189 } else {
5190 qla24xx_fcport_handle_login(vha, fcport);
5191 }
5ef696aa 5192 }
726b8548 5193 }
b5d15312
QT		 5194
5195 if (free_fcport) {
5196 qla2x00_free_fcport(fcport);
5197 if (pla)
5198 kmem_cache_free(qla_tgt_plogi_cachep, pla);
5199 }
726b8548
QT		 5200}
5201
e374f9f5
QT		 5202static void qla_sp_retry(struct scsi_qla_host *vha, struct qla_work_evt *e)
5203{
5204 struct srb *sp = e->u.iosb.sp;
5205 int rval;
5206
5207 rval = qla2x00_start_sp(sp);
5208 if (rval != QLA_SUCCESS) {
5209 ql_dbg(ql_dbg_disc, vha, 0x2043,
5210 "%s: %s: Re-issue IOCB failed (%d).\n",
5211 __func__, sp->name, rval);
5212 qla24xx_sp_unmap(vha, sp);
5213 }
5214}
5215
ac280b67 5216void
e315cd28 5217qla2x00_do_work(struct scsi_qla_host *vha)
0971de7f 5218{
f999f4c1
AV		 5219 struct qla_work_evt *e, *tmp;
5220 unsigned long flags;
5221 LIST_HEAD(work);
80676d05 5222 int rc;
0971de7f 5223
f999f4c1
AV		 5224 spin_lock_irqsave(&vha->work_lock, flags);
5225 list_splice_init(&vha->work_list, &work);
5226 spin_unlock_irqrestore(&vha->work_lock, flags);
5227
5228 list_for_each_entry_safe(e, tmp, &work, list) {
80676d05 5229 rc = QLA_SUCCESS;
0971de7f
AV		 5230 switch (e->type) {
5231 case QLA_EVT_AEN:
e315cd28 5232 fc_host_post_event(vha->host, fc_get_event_number(),
0971de7f
AV		 5233 e->u.aen.code, e->u.aen.data);
5234 break;
8a659571
AV		 5235 case QLA_EVT_IDC_ACK:
5236 qla81xx_idc_ack(vha, e->u.idc_ack.mb);
5237 break;
ac280b67
AV		 5238 case QLA_EVT_ASYNC_LOGIN:
5239 qla2x00_async_login(vha, e->u.logio.fcport,
5240 e->u.logio.data);
5241 break;
ac280b67 5242 case QLA_EVT_ASYNC_LOGOUT:
80676d05 5243 rc = qla2x00_async_logout(vha, e->u.logio.fcport);
ac280b67
AV		 5244 break;
5245 case QLA_EVT_ASYNC_LOGOUT_DONE:
5246 qla2x00_async_logout_done(vha, e->u.logio.fcport,
5247 e->u.logio.data);
5248 break;
5ff1d584
AV		 5249 case QLA_EVT_ASYNC_ADISC:
5250 qla2x00_async_adisc(vha, e->u.logio.fcport,
5251 e->u.logio.data);
5252 break;
3420d36c
AV		 5253 case QLA_EVT_UEVENT:
5254 qla2x00_uevent_emit(vha, e->u.uevent.code);
5255 break;
8ae6d9c7
GM		 5256 case QLA_EVT_AENFX:
5257 qlafx00_process_aen(vha, e);
5258 break;
726b8548
QT		 5259 case QLA_EVT_GPNID:
5260 qla24xx_async_gpnid(vha, &e->u.gpnid.id);
5261 break;
e374f9f5
QT		 5262 case QLA_EVT_UNMAP:
5263 qla24xx_sp_unmap(vha, e->u.iosb.sp);
726b8548 5264 break;
9b3e0f4d
QT		 5265 case QLA_EVT_RELOGIN:
5266 qla2x00_relogin(vha);
5267 break;
726b8548
QT		 5268 case QLA_EVT_NEW_SESS:
5269 qla24xx_create_new_sess(vha, e);
5270 break;
5271 case QLA_EVT_GPDB:
5272 qla24xx_async_gpdb(vha, e->u.fcport.fcport,
5273 e->u.fcport.opt);
5274 break;
a5d42f4c
DG		 5275 case QLA_EVT_PRLI:
5276 qla24xx_async_prli(vha, e->u.fcport.fcport);
5277 break;
726b8548
QT		 5278 case QLA_EVT_GPSC:
5279 qla24xx_async_gpsc(vha, e->u.fcport.fcport);
5280 break;
726b8548
QT		 5281 case QLA_EVT_GNL:
5282 qla24xx_async_gnl(vha, e->u.fcport.fcport);
5283 break;
5284 case QLA_EVT_NACK:
5285 qla24xx_do_nack_work(vha, e);
5286 break;
11aea16a 5287 case QLA_EVT_ASYNC_PRLO:
80676d05 5288 rc = qla2x00_async_prlo(vha, e->u.logio.fcport);
11aea16a
QT		 5289 break;
5290 case QLA_EVT_ASYNC_PRLO_DONE:
5291 qla2x00_async_prlo_done(vha, e->u.logio.fcport,
5292 e->u.logio.data);
5293 break;
a4239945 5294 case QLA_EVT_GPNFT:
33b28357
QT		 5295 qla24xx_async_gpnft(vha, e->u.gpnft.fc4_type,
5296 e->u.gpnft.sp);
a4239945
QT		 5297 break;
5298 case QLA_EVT_GPNFT_DONE:
5299 qla24xx_async_gpnft_done(vha, e->u.iosb.sp);
5300 break;
5301 case QLA_EVT_GNNFT_DONE:
5302 qla24xx_async_gnnft_done(vha, e->u.iosb.sp);
5303 break;
5304 case QLA_EVT_GNNID:
5305 qla24xx_async_gnnid(vha, e->u.fcport.fcport);
5306 break;
5307 case QLA_EVT_GFPNID:
5308 qla24xx_async_gfpnid(vha, e->u.fcport.fcport);
5309 break;
e374f9f5
QT		 5310 case QLA_EVT_SP_RETRY:
5311 qla_sp_retry(vha, e);
cc28e0ac
QT		 5312 break;
5313 case QLA_EVT_IIDMA:
5314 qla_do_iidma_work(vha, e->u.fcport.fcport);
5315 break;
8777e431
QT		 5316 case QLA_EVT_ELS_PLOGI:
5317 qla24xx_els_dcmd2_iocb(vha, ELS_DCMD_PLOGI,
5318 e->u.fcport.fcport, false);
5319 break;
0971de7f 5320 }
80676d05
QT		 5321
5322 if (rc == EAGAIN) {
5323 /* put 'work' at head of 'vha->work_list' */
5324 spin_lock_irqsave(&vha->work_lock, flags);
5325 list_splice(&work, &vha->work_list);
5326 spin_unlock_irqrestore(&vha->work_lock, flags);
5327 break;
5328 }
5329 list_del_init(&e->list);
0971de7f
AV		 5330 if (e->flags & QLA_EVT_FLAG_FREE)
5331 kfree(e);
feafb7b1
AE		 5332
5333 /* For each work completed decrement vha ref count */
5334 QLA_VHA_MARK_NOT_BUSY(vha);
e315cd28 5335 }
e315cd28 5336}
f999f4c1 5337
9b3e0f4d
QT		 5338int qla24xx_post_relogin_work(struct scsi_qla_host *vha)
5339{
5340 struct qla_work_evt *e;
5341
5342 e = qla2x00_alloc_work(vha, QLA_EVT_RELOGIN);
5343
5344 if (!e) {
5345 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
5346 return QLA_FUNCTION_FAILED;
5347 }
5348
5349 return qla2x00_post_work(vha, e);
5350}
5351
e315cd28
AC		 5352/* Relogins all the fcports of a vport
5353 * Context: dpc thread
5354 */
5355void qla2x00_relogin(struct scsi_qla_host *vha)
5356{
5357 fc_port_t *fcport;
23dd98a6 5358 int status, relogin_needed = 0;
726b8548 5359 struct event_arg ea;
e315cd28
AC		 5360
5361 list_for_each_entry(fcport, &vha->vp_fcports, list) {
9cd883f0
QT		 5362 /*
5363 * If the port is not ONLINE then try to login
5364 * to it if we haven't run out of retries.
5365 */
5ff1d584 5366 if (atomic_read(&fcport->state) != FCS_ONLINE &&
23dd98a6
QT		 5367 fcport->login_retry) {
5368 if (fcport->scan_state != QLA_FCPORT_FOUND ||
5369 fcport->disc_state == DSC_LOGIN_COMPLETE)
5370 continue;
e315cd28 5371
23dd98a6
QT		 5372 if (fcport->flags & (FCF_ASYNC_SENT|FCF_ASYNC_ACTIVE) ||
5373 fcport->disc_state == DSC_DELETE_PEND) {
5374 relogin_needed = 1;
5375 } else {
5376 if (vha->hw->current_topology != ISP_CFG_NL) {
5377 memset(&ea, 0, sizeof(ea));
5378 ea.event = FCME_RELOGIN;
5379 ea.fcport = fcport;
5380 qla2x00_fcport_event_handler(vha, &ea);
5381 } else if (vha->hw->current_topology ==
5382 ISP_CFG_NL) {
5383 fcport->login_retry--;
5384 status =
5385 qla2x00_local_device_login(vha,
5386 fcport);
5387 if (status == QLA_SUCCESS) {
5388 fcport->old_loop_id =
5389 fcport->loop_id;
5390 ql_dbg(ql_dbg_disc, vha, 0x2003,
5391 "Port login OK: logged in ID 0x%x.\n",
5392 fcport->loop_id);
5393 qla2x00_update_fcport
5394 (vha, fcport);
5395 } else if (status == 1) {
5396 set_bit(RELOGIN_NEEDED,
5397 &vha->dpc_flags);
5398 /* retry the login again */
5399 ql_dbg(ql_dbg_disc, vha, 0x2007,
5400 "Retrying %d login again loop_id 0x%x.\n",
5401 fcport->login_retry,
5402 fcport->loop_id);
5403 } else {
5404 fcport->login_retry = 0;
5405 }
e315cd28 5406
23dd98a6
QT		 5407 if (fcport->login_retry == 0 &&
5408 status != QLA_SUCCESS)
5409 qla2x00_clear_loop_id(fcport);
5410 }
e315cd28 5411 }
e315cd28
AC		 5412 }
5413 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
5414 break;
0971de7f 5415 }
9b3e0f4d 5416
23dd98a6
QT		 5417 if (relogin_needed)
5418 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
5419
9b3e0f4d
QT		 5420 ql_dbg(ql_dbg_disc, vha, 0x400e,
5421 "Relogin end.\n");
0971de7f
AV		 5422}
5423
7d613ac6
SV		 5424/* Schedule work on any of the dpc-workqueues */
5425void
5426qla83xx_schedule_work(scsi_qla_host_t *base_vha, int work_code)
5427{
5428 struct qla_hw_data *ha = base_vha->hw;
5429
5430 switch (work_code) {
5431 case MBA_IDC_AEN: /* 0x8200 */
5432 if (ha->dpc_lp_wq)
5433 queue_work(ha->dpc_lp_wq, &ha->idc_aen);
5434 break;
5435
5436 case QLA83XX_NIC_CORE_RESET: /* 0x1 */
5437 if (!ha->flags.nic_core_reset_hdlr_active) {
5438 if (ha->dpc_hp_wq)
5439 queue_work(ha->dpc_hp_wq, &ha->nic_core_reset);
5440 } else
5441 ql_dbg(ql_dbg_p3p, base_vha, 0xb05e,
5442 "NIC Core reset is already active. Skip "
5443 "scheduling it again.\n");
5444 break;
5445 case QLA83XX_IDC_STATE_HANDLER: /* 0x2 */
5446 if (ha->dpc_hp_wq)
5447 queue_work(ha->dpc_hp_wq, &ha->idc_state_handler);
5448 break;
5449 case QLA83XX_NIC_CORE_UNRECOVERABLE: /* 0x3 */
5450 if (ha->dpc_hp_wq)
5451 queue_work(ha->dpc_hp_wq, &ha->nic_core_unrecoverable);
5452 break;
5453 default:
5454 ql_log(ql_log_warn, base_vha, 0xb05f,
d939be3a 5455 "Unknown work-code=0x%x.\n", work_code);
7d613ac6
SV		 5456 }
5457
5458 return;
5459}
5460
5461/* Work: Perform NIC Core Unrecoverable state handling */
5462void
5463qla83xx_nic_core_unrecoverable_work(struct work_struct *work)
5464{
5465 struct qla_hw_data *ha =
2ad1b67c 5466 container_of(work, struct qla_hw_data, nic_core_unrecoverable);
7d613ac6
SV		 5467 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5468 uint32_t dev_state = 0;
5469
5470 qla83xx_idc_lock(base_vha, 0);
5471 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
5472 qla83xx_reset_ownership(base_vha);
5473 if (ha->flags.nic_core_reset_owner) {
5474 ha->flags.nic_core_reset_owner = 0;
5475 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
5476 QLA8XXX_DEV_FAILED);
5477 ql_log(ql_log_info, base_vha, 0xb060, "HW State: FAILED.\n");
5478 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
5479 }
5480 qla83xx_idc_unlock(base_vha, 0);
5481}
5482
5483/* Work: Execute IDC state handler */
5484void
5485qla83xx_idc_state_handler_work(struct work_struct *work)
5486{
5487 struct qla_hw_data *ha =
2ad1b67c 5488 container_of(work, struct qla_hw_data, idc_state_handler);
7d613ac6
SV		 5489 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5490 uint32_t dev_state = 0;
5491
5492 qla83xx_idc_lock(base_vha, 0);
5493 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
5494 if (dev_state == QLA8XXX_DEV_FAILED ||
5495 dev_state == QLA8XXX_DEV_NEED_QUIESCENT)
5496 qla83xx_idc_state_handler(base_vha);
5497 qla83xx_idc_unlock(base_vha, 0);
5498}
5499
fa492630 5500static int
7d613ac6
SV		 5501qla83xx_check_nic_core_fw_alive(scsi_qla_host_t *base_vha)
5502{
5503 int rval = QLA_SUCCESS;
5504 unsigned long heart_beat_wait = jiffies + (1 * HZ);
5505 uint32_t heart_beat_counter1, heart_beat_counter2;
5506
5507 do {
5508 if (time_after(jiffies, heart_beat_wait)) {
5509 ql_dbg(ql_dbg_p3p, base_vha, 0xb07c,
5510 "Nic Core f/w is not alive.\n");
5511 rval = QLA_FUNCTION_FAILED;
5512 break;
5513 }
5514
5515 qla83xx_idc_lock(base_vha, 0);
5516 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
5517 &heart_beat_counter1);
5518 qla83xx_idc_unlock(base_vha, 0);
5519 msleep(100);
5520 qla83xx_idc_lock(base_vha, 0);
5521 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
5522 &heart_beat_counter2);
5523 qla83xx_idc_unlock(base_vha, 0);
5524 } while (heart_beat_counter1 == heart_beat_counter2);
5525
5526 return rval;
5527}
5528
5529/* Work: Perform NIC Core Reset handling */
5530void
5531qla83xx_nic_core_reset_work(struct work_struct *work)
5532{
5533 struct qla_hw_data *ha =
5534 container_of(work, struct qla_hw_data, nic_core_reset);
5535 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5536 uint32_t dev_state = 0;
5537
81178772
SK		 5538 if (IS_QLA2031(ha)) {
5539 if (qla2xxx_mctp_dump(base_vha) != QLA_SUCCESS)
5540 ql_log(ql_log_warn, base_vha, 0xb081,
5541 "Failed to dump mctp\n");
5542 return;
5543 }
5544
7d613ac6
SV		 5545 if (!ha->flags.nic_core_reset_hdlr_active) {
5546 if (qla83xx_check_nic_core_fw_alive(base_vha) == QLA_SUCCESS) {
5547 qla83xx_idc_lock(base_vha, 0);
5548 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE,
5549 &dev_state);
5550 qla83xx_idc_unlock(base_vha, 0);
5551 if (dev_state != QLA8XXX_DEV_NEED_RESET) {
5552 ql_dbg(ql_dbg_p3p, base_vha, 0xb07a,
5553 "Nic Core f/w is alive.\n");
5554 return;
5555 }
5556 }
5557
5558 ha->flags.nic_core_reset_hdlr_active = 1;
5559 if (qla83xx_nic_core_reset(base_vha)) {
5560 /* NIC Core reset failed. */
5561 ql_dbg(ql_dbg_p3p, base_vha, 0xb061,
5562 "NIC Core reset failed.\n");
5563 }
5564 ha->flags.nic_core_reset_hdlr_active = 0;
5565 }
5566}
5567
5568/* Work: Handle 8200 IDC aens */
5569void
5570qla83xx_service_idc_aen(struct work_struct *work)
5571{
5572 struct qla_hw_data *ha =
5573 container_of(work, struct qla_hw_data, idc_aen);
5574 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5575 uint32_t dev_state, idc_control;
5576
5577 qla83xx_idc_lock(base_vha, 0);
5578 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
5579 qla83xx_rd_reg(base_vha, QLA83XX_IDC_CONTROL, &idc_control);
5580 qla83xx_idc_unlock(base_vha, 0);
5581 if (dev_state == QLA8XXX_DEV_NEED_RESET) {
5582 if (idc_control & QLA83XX_IDC_GRACEFUL_RESET) {
5583 ql_dbg(ql_dbg_p3p, base_vha, 0xb062,
5584 "Application requested NIC Core Reset.\n");
5585 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
5586 } else if (qla83xx_check_nic_core_fw_alive(base_vha) ==
5587 QLA_SUCCESS) {
5588 ql_dbg(ql_dbg_p3p, base_vha, 0xb07b,
5589 "Other protocol driver requested NIC Core Reset.\n");
5590 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
5591 }
5592 } else if (dev_state == QLA8XXX_DEV_FAILED ||
5593 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) {
5594 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
5595 }
5596}
5597
5598static void
5599qla83xx_wait_logic(void)
5600{
5601 int i;
5602
5603 /* Yield CPU */
5604 if (!in_interrupt()) {
5605 /*
5606 * Wait about 200ms before retrying again.
5607 * This controls the number of retries for single
5608 * lock operation.
5609 */
5610 msleep(100);
5611 schedule();
5612 } else {
5613 for (i = 0; i < 20; i++)
5614 cpu_relax(); /* This a nop instr on i386 */
5615 }
5616}
5617
fa492630 5618static int
7d613ac6
SV		 5619qla83xx_force_lock_recovery(scsi_qla_host_t *base_vha)
5620{
5621 int rval;
5622 uint32_t data;
5623 uint32_t idc_lck_rcvry_stage_mask = 0x3;
5624 uint32_t idc_lck_rcvry_owner_mask = 0x3c;
5625 struct qla_hw_data *ha = base_vha->hw;
bd432bb5 5626
6c315553
SK		 5627 ql_dbg(ql_dbg_p3p, base_vha, 0xb086,
5628 "Trying force recovery of the IDC lock.\n");
7d613ac6
SV		 5629
5630 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, &data);
5631 if (rval)
5632 return rval;
5633
5634 if ((data & idc_lck_rcvry_stage_mask) > 0) {
5635 return QLA_SUCCESS;
5636 } else {
5637 data = (IDC_LOCK_RECOVERY_STAGE1) | (ha->portnum << 2);
5638 rval = qla83xx_wr_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
5639 data);
5640 if (rval)
5641 return rval;
5642
5643 msleep(200);
5644
5645 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
5646 &data);
5647 if (rval)
5648 return rval;
5649
5650 if (((data & idc_lck_rcvry_owner_mask) >> 2) == ha->portnum) {
5651 data &= (IDC_LOCK_RECOVERY_STAGE2 |
5652 ~(idc_lck_rcvry_stage_mask));
5653 rval = qla83xx_wr_reg(base_vha,
5654 QLA83XX_IDC_LOCK_RECOVERY, data);
5655 if (rval)
5656 return rval;
5657
5658 /* Forcefully perform IDC UnLock */
5659 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK,
5660 &data);
5661 if (rval)
5662 return rval;
5663 /* Clear lock-id by setting 0xff */
5664 rval = qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
5665 0xff);
5666 if (rval)
5667 return rval;
5668 /* Clear lock-recovery by setting 0x0 */
5669 rval = qla83xx_wr_reg(base_vha,
5670 QLA83XX_IDC_LOCK_RECOVERY, 0x0);
5671 if (rval)
5672 return rval;
5673 } else
5674 return QLA_SUCCESS;
5675 }
5676
5677 return rval;
5678}
5679
fa492630 5680static int
7d613ac6
SV		 5681qla83xx_idc_lock_recovery(scsi_qla_host_t *base_vha)
5682{
5683 int rval = QLA_SUCCESS;
5684 uint32_t o_drv_lockid, n_drv_lockid;
5685 unsigned long lock_recovery_timeout;
5686
5687 lock_recovery_timeout = jiffies + QLA83XX_MAX_LOCK_RECOVERY_WAIT;
5688retry_lockid:
5689 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &o_drv_lockid);
5690 if (rval)
5691 goto exit;
5692
5693 /* MAX wait time before forcing IDC Lock recovery = 2 secs */
5694 if (time_after_eq(jiffies, lock_recovery_timeout)) {
5695 if (qla83xx_force_lock_recovery(base_vha) == QLA_SUCCESS)
5696 return QLA_SUCCESS;
5697 else
5698 return QLA_FUNCTION_FAILED;
5699 }
5700
5701 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &n_drv_lockid);
5702 if (rval)
5703 goto exit;
5704
5705 if (o_drv_lockid == n_drv_lockid) {
5706 qla83xx_wait_logic();
5707 goto retry_lockid;
5708 } else
5709 return QLA_SUCCESS;
5710
5711exit:
5712 return rval;
5713}
5714
5715void
5716qla83xx_idc_lock(scsi_qla_host_t *base_vha, uint16_t requester_id)
5717{
5718 uint16_t options = (requester_id << 15) | BIT_6;
5719 uint32_t data;
6c315553 5720 uint32_t lock_owner;
7d613ac6
SV		 5721 struct qla_hw_data *ha = base_vha->hw;
5722
5723 /* IDC-lock implementation using driver-lock/lock-id remote registers */
5724retry_lock:
5725 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCK, &data)
5726 == QLA_SUCCESS) {
5727 if (data) {
5728 /* Setting lock-id to our function-number */
5729 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
5730 ha->portnum);
5731 } else {
6c315553
SK		 5732 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID,
5733 &lock_owner);
7d613ac6 5734 ql_dbg(ql_dbg_p3p, base_vha, 0xb063,
6c315553
SK		 5735 "Failed to acquire IDC lock, acquired by %d, "
5736 "retrying...\n", lock_owner);
7d613ac6
SV		 5737
5738 /* Retry/Perform IDC-Lock recovery */
5739 if (qla83xx_idc_lock_recovery(base_vha)
5740 == QLA_SUCCESS) {
5741 qla83xx_wait_logic();
5742 goto retry_lock;
5743 } else
5744 ql_log(ql_log_warn, base_vha, 0xb075,
5745 "IDC Lock recovery FAILED.\n");
5746 }
5747
5748 }
5749
5750 return;
5751
5752 /* XXX: IDC-lock implementation using access-control mbx */
5753retry_lock2:
5754 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
5755 ql_dbg(ql_dbg_p3p, base_vha, 0xb072,
5756 "Failed to acquire IDC lock. retrying...\n");
5757 /* Retry/Perform IDC-Lock recovery */
5758 if (qla83xx_idc_lock_recovery(base_vha) == QLA_SUCCESS) {
5759 qla83xx_wait_logic();
5760 goto retry_lock2;
5761 } else
5762 ql_log(ql_log_warn, base_vha, 0xb076,
5763 "IDC Lock recovery FAILED.\n");
5764 }
5765
5766 return;
5767}
5768
5769void
5770qla83xx_idc_unlock(scsi_qla_host_t *base_vha, uint16_t requester_id)
5771{
5897cb2f
BVA		 5772#if 0
5773 uint16_t options = (requester_id << 15) | BIT_7;
5774#endif
5775 uint16_t retry;
7d613ac6
SV		 5776 uint32_t data;
5777 struct qla_hw_data *ha = base_vha->hw;
5778
5779 /* IDC-unlock implementation using driver-unlock/lock-id
5780 * remote registers
5781 */
5782 retry = 0;
5783retry_unlock:
5784 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &data)
5785 == QLA_SUCCESS) {
5786 if (data == ha->portnum) {
5787 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, &data);
5788 /* Clearing lock-id by setting 0xff */
5789 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 0xff);
5790 } else if (retry < 10) {
5791 /* SV: XXX: IDC unlock retrying needed here? */
5792
5793 /* Retry for IDC-unlock */
5794 qla83xx_wait_logic();
5795 retry++;
5796 ql_dbg(ql_dbg_p3p, base_vha, 0xb064,
ee6a8773 5797 "Failed to release IDC lock, retrying=%d\n", retry);
7d613ac6
SV		 5798 goto retry_unlock;
5799 }
5800 } else if (retry < 10) {
5801 /* Retry for IDC-unlock */
5802 qla83xx_wait_logic();
5803 retry++;
5804 ql_dbg(ql_dbg_p3p, base_vha, 0xb065,
ee6a8773 5805 "Failed to read drv-lockid, retrying=%d\n", retry);
7d613ac6
SV		 5806 goto retry_unlock;
5807 }
5808
5809 return;
5810
5897cb2f 5811#if 0
7d613ac6
SV		 5812 /* XXX: IDC-unlock implementation using access-control mbx */
5813 retry = 0;
5814retry_unlock2:
5815 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
5816 if (retry < 10) {
5817 /* Retry for IDC-unlock */
5818 qla83xx_wait_logic();
5819 retry++;
5820 ql_dbg(ql_dbg_p3p, base_vha, 0xb066,
ee6a8773 5821 "Failed to release IDC lock, retrying=%d\n", retry);
7d613ac6
SV		 5822 goto retry_unlock2;
5823 }
5824 }
5825
5826 return;
5897cb2f 5827#endif
7d613ac6
SV		 5828}
5829
5830int
5831__qla83xx_set_drv_presence(scsi_qla_host_t *vha)
5832{
5833 int rval = QLA_SUCCESS;
5834 struct qla_hw_data *ha = vha->hw;
5835 uint32_t drv_presence;
5836
5837 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
5838 if (rval == QLA_SUCCESS) {
5839 drv_presence |= (1 << ha->portnum);
5840 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
5841 drv_presence);
5842 }
5843
5844 return rval;
5845}
5846
5847int
5848qla83xx_set_drv_presence(scsi_qla_host_t *vha)
5849{
5850 int rval = QLA_SUCCESS;
5851
5852 qla83xx_idc_lock(vha, 0);
5853 rval = __qla83xx_set_drv_presence(vha);
5854 qla83xx_idc_unlock(vha, 0);
5855
5856 return rval;
5857}
5858
5859int
5860__qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
5861{
5862 int rval = QLA_SUCCESS;
5863 struct qla_hw_data *ha = vha->hw;
5864 uint32_t drv_presence;
5865
5866 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
5867 if (rval == QLA_SUCCESS) {
5868 drv_presence &= ~(1 << ha->portnum);
5869 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
5870 drv_presence);
5871 }
5872
5873 return rval;
5874}
5875
5876int
5877qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
5878{
5879 int rval = QLA_SUCCESS;
5880
5881 qla83xx_idc_lock(vha, 0);
5882 rval = __qla83xx_clear_drv_presence(vha);
5883 qla83xx_idc_unlock(vha, 0);
5884
5885 return rval;
5886}
5887
fa492630 5888static void
7d613ac6
SV		 5889qla83xx_need_reset_handler(scsi_qla_host_t *vha)
5890{
5891 struct qla_hw_data *ha = vha->hw;
5892 uint32_t drv_ack, drv_presence;
5893 unsigned long ack_timeout;
5894
5895 /* Wait for IDC ACK from all functions (DRV-ACK == DRV-PRESENCE) */
5896 ack_timeout = jiffies + (ha->fcoe_reset_timeout * HZ);
5897 while (1) {
5898 qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
5899 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
807fb6d8 5900 if ((drv_ack & drv_presence) == drv_presence)
7d613ac6
SV		 5901 break;
5902
5903 if (time_after_eq(jiffies, ack_timeout)) {
5904 ql_log(ql_log_warn, vha, 0xb067,
5905 "RESET ACK TIMEOUT! drv_presence=0x%x "
5906 "drv_ack=0x%x\n", drv_presence, drv_ack);
5907 /*
5908 * The function(s) which did not ack in time are forced
5909 * to withdraw any further participation in the IDC
5910 * reset.
5911 */
5912 if (drv_ack != drv_presence)
5913 qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
5914 drv_ack);
5915 break;
5916 }
5917
5918 qla83xx_idc_unlock(vha, 0);
5919 msleep(1000);
5920 qla83xx_idc_lock(vha, 0);
5921 }
5922
5923 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_COLD);
5924 ql_log(ql_log_info, vha, 0xb068, "HW State: COLD/RE-INIT.\n");
5925}
5926
fa492630 5927static int
7d613ac6
SV		 5928qla83xx_device_bootstrap(scsi_qla_host_t *vha)
5929{
5930 int rval = QLA_SUCCESS;
5931 uint32_t idc_control;
5932
5933 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_INITIALIZING);
5934 ql_log(ql_log_info, vha, 0xb069, "HW State: INITIALIZING.\n");
5935
5936 /* Clearing IDC-Control Graceful-Reset Bit before resetting f/w */
5937 __qla83xx_get_idc_control(vha, &idc_control);
5938 idc_control &= ~QLA83XX_IDC_GRACEFUL_RESET;
5939 __qla83xx_set_idc_control(vha, 0);
5940
5941 qla83xx_idc_unlock(vha, 0);
5942 rval = qla83xx_restart_nic_firmware(vha);
5943 qla83xx_idc_lock(vha, 0);
5944
5945 if (rval != QLA_SUCCESS) {
5946 ql_log(ql_log_fatal, vha, 0xb06a,
5947 "Failed to restart NIC f/w.\n");
5948 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_FAILED);
5949 ql_log(ql_log_info, vha, 0xb06b, "HW State: FAILED.\n");
5950 } else {
5951 ql_dbg(ql_dbg_p3p, vha, 0xb06c,
5952 "Success in restarting nic f/w.\n");
5953 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_READY);
5954 ql_log(ql_log_info, vha, 0xb06d, "HW State: READY.\n");
5955 }
5956
5957 return rval;
5958}
5959
5960/* Assumes idc_lock always held on entry */
5961int
5962qla83xx_idc_state_handler(scsi_qla_host_t *base_vha)
5963{
5964 struct qla_hw_data *ha = base_vha->hw;
5965 int rval = QLA_SUCCESS;
5966 unsigned long dev_init_timeout;
5967 uint32_t dev_state;
5968
5969 /* Wait for MAX-INIT-TIMEOUT for the device to go ready */
5970 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ);
5971
5972 while (1) {
5973
5974 if (time_after_eq(jiffies, dev_init_timeout)) {
5975 ql_log(ql_log_warn, base_vha, 0xb06e,
5976 "Initialization TIMEOUT!\n");
5977 /* Init timeout. Disable further NIC Core
5978 * communication.
5979 */
5980 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
5981 QLA8XXX_DEV_FAILED);
5982 ql_log(ql_log_info, base_vha, 0xb06f,
5983 "HW State: FAILED.\n");
5984 }
5985
5986 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
5987 switch (dev_state) {
5988 case QLA8XXX_DEV_READY:
5989 if (ha->flags.nic_core_reset_owner)
5990 qla83xx_idc_audit(base_vha,
5991 IDC_AUDIT_COMPLETION);
5992 ha->flags.nic_core_reset_owner = 0;
5993 ql_dbg(ql_dbg_p3p, base_vha, 0xb070,
5994 "Reset_owner reset by 0x%x.\n",
5995 ha->portnum);
5996 goto exit;
5997 case QLA8XXX_DEV_COLD:
5998 if (ha->flags.nic_core_reset_owner)
5999 rval = qla83xx_device_bootstrap(base_vha);
6000 else {
6001 /* Wait for AEN to change device-state */
6002 qla83xx_idc_unlock(base_vha, 0);
6003 msleep(1000);
6004 qla83xx_idc_lock(base_vha, 0);
6005 }
6006 break;
6007 case QLA8XXX_DEV_INITIALIZING:
6008 /* Wait for AEN to change device-state */
6009 qla83xx_idc_unlock(base_vha, 0);
6010 msleep(1000);
6011 qla83xx_idc_lock(base_vha, 0);
6012 break;
6013 case QLA8XXX_DEV_NEED_RESET:
6014 if (!ql2xdontresethba && ha->flags.nic_core_reset_owner)
6015 qla83xx_need_reset_handler(base_vha);
6016 else {
6017 /* Wait for AEN to change device-state */
6018 qla83xx_idc_unlock(base_vha, 0);
6019 msleep(1000);
6020 qla83xx_idc_lock(base_vha, 0);
6021 }
6022 /* reset timeout value after need reset handler */
6023 dev_init_timeout = jiffies +
6024 (ha->fcoe_dev_init_timeout * HZ);
6025 break;
6026 case QLA8XXX_DEV_NEED_QUIESCENT:
6027 /* XXX: DEBUG for now */
6028 qla83xx_idc_unlock(base_vha, 0);
6029 msleep(1000);
6030 qla83xx_idc_lock(base_vha, 0);
6031 break;
6032 case QLA8XXX_DEV_QUIESCENT:
6033 /* XXX: DEBUG for now */
6034 if (ha->flags.quiesce_owner)
6035 goto exit;
6036
6037 qla83xx_idc_unlock(base_vha, 0);
6038 msleep(1000);
6039 qla83xx_idc_lock(base_vha, 0);
6040 dev_init_timeout = jiffies +
6041 (ha->fcoe_dev_init_timeout * HZ);
6042 break;
6043 case QLA8XXX_DEV_FAILED:
6044 if (ha->flags.nic_core_reset_owner)
6045 qla83xx_idc_audit(base_vha,
6046 IDC_AUDIT_COMPLETION);
6047 ha->flags.nic_core_reset_owner = 0;
6048 __qla83xx_clear_drv_presence(base_vha);
6049 qla83xx_idc_unlock(base_vha, 0);
6050 qla8xxx_dev_failed_handler(base_vha);
6051 rval = QLA_FUNCTION_FAILED;
6052 qla83xx_idc_lock(base_vha, 0);
6053 goto exit;
6054 case QLA8XXX_BAD_VALUE:
6055 qla83xx_idc_unlock(base_vha, 0);
6056 msleep(1000);
6057 qla83xx_idc_lock(base_vha, 0);
6058 break;
6059 default:
6060 ql_log(ql_log_warn, base_vha, 0xb071,
d939be3a 6061 "Unknown Device State: %x.\n", dev_state);
7d613ac6
SV		 6062 qla83xx_idc_unlock(base_vha, 0);
6063 qla8xxx_dev_failed_handler(base_vha);
6064 rval = QLA_FUNCTION_FAILED;
6065 qla83xx_idc_lock(base_vha, 0);
6066 goto exit;
6067 }
6068 }
6069
6070exit:
6071 return rval;
6072}
6073
f3ddac19
CD		 6074void
6075qla2x00_disable_board_on_pci_error(struct work_struct *work)
6076{
6077 struct qla_hw_data *ha = container_of(work, struct qla_hw_data,
6078 board_disable);
6079 struct pci_dev *pdev = ha->pdev;
6080 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
6081
726b8548
QT		 6082 /*
6083 * if UNLOAD flag is already set, then continue unload,
783e0dc4
SC		 6084 * where it was set first.
6085 */
6086 if (test_bit(UNLOADING, &base_vha->dpc_flags))
6087 return;
6088
f3ddac19
CD		 6089 ql_log(ql_log_warn, base_vha, 0x015b,
6090 "Disabling adapter.\n");
6091
efdb5760
SC		 6092 if (!atomic_read(&pdev->enable_cnt)) {
6093 ql_log(ql_log_info, base_vha, 0xfffc,
6094 "PCI device disabled, no action req for PCI error=%lx\n",
6095 base_vha->pci_flags);
6096 return;
6097 }
6098
726b8548
QT		 6099 qla2x00_wait_for_sess_deletion(base_vha);
6100
f3ddac19
CD		 6101 set_bit(UNLOADING, &base_vha->dpc_flags);
6102
6103 qla2x00_delete_all_vps(ha, base_vha);
6104
6105 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
6106
6107 qla2x00_dfs_remove(base_vha);
6108
6109 qla84xx_put_chip(base_vha);
6110
6111 if (base_vha->timer_active)
6112 qla2x00_stop_timer(base_vha);
6113
6114 base_vha->flags.online = 0;
6115
6116 qla2x00_destroy_deferred_work(ha);
6117
6118 /*
6119 * Do not try to stop beacon blink as it will issue a mailbox
6120 * command.
6121 */
6122 qla2x00_free_sysfs_attr(base_vha, false);
6123
6124 fc_remove_host(base_vha->host);
6125
6126 scsi_remove_host(base_vha->host);
6127
6128 base_vha->flags.init_done = 0;
6129 qla25xx_delete_queues(base_vha);
f3ddac19 6130 qla2x00_free_fcports(base_vha);
093df737 6131 qla2x00_free_irqs(base_vha);
f3ddac19
CD		 6132 qla2x00_mem_free(ha);
6133 qla82xx_md_free(base_vha);
6134 qla2x00_free_queues(ha);
6135
f3ddac19
CD		 6136 qla2x00_unmap_iobases(ha);
6137
6138 pci_release_selected_regions(ha->pdev, ha->bars);
f3ddac19
CD		 6139 pci_disable_pcie_error_reporting(pdev);
6140 pci_disable_device(pdev);
f3ddac19 6141
beb9e315
JL		 6142 /*
6143 * Let qla2x00_remove_one cleanup qla_hw_data on device removal.
6144 */
f3ddac19
CD		 6145}
6146
1da177e4
LT		 6147/**************************************************************************
6148* qla2x00_do_dpc
6149* This kernel thread is a task that is schedule by the interrupt handler
6150* to perform the background processing for interrupts.
6151*
6152* Notes:
6153* This task always run in the context of a kernel thread. It
6154* is kick-off by the driver's detect code and starts up
6155* up one per adapter. It immediately goes to sleep and waits for
6156* some fibre event. When either the interrupt handler or
6157* the timer routine detects a event it will one of the task
6158* bits then wake us up.
6159**************************************************************************/
6160static int
6161qla2x00_do_dpc(void *data)
6162{
e315cd28
AC		 6163 scsi_qla_host_t *base_vha;
6164 struct qla_hw_data *ha;
d7459527
MH		 6165 uint32_t online;
6166 struct qla_qpair *qpair;
1da177e4 6167
e315cd28
AC		 6168 ha = (struct qla_hw_data *)data;
6169 base_vha = pci_get_drvdata(ha->pdev);
1da177e4 6170
8698a745 6171 set_user_nice(current, MIN_NICE);
1da177e4 6172
563585ec 6173 set_current_state(TASK_INTERRUPTIBLE);
39a11240 6174 while (!kthread_should_stop()) {
7c3df132
SK		 6175 ql_dbg(ql_dbg_dpc, base_vha, 0x4000,
6176 "DPC handler sleeping.\n");
1da177e4 6177
39a11240 6178 schedule();
1da177e4 6179
c142caf0
AV		 6180 if (!base_vha->flags.init_done || ha->flags.mbox_busy)
6181 goto end_loop;
1da177e4 6182
85880801 6183 if (ha->flags.eeh_busy) {
7c3df132
SK		 6184 ql_dbg(ql_dbg_dpc, base_vha, 0x4003,
6185 "eeh_busy=%d.\n", ha->flags.eeh_busy);
c142caf0 6186 goto end_loop;
85880801
AV		 6187 }
6188
1da177e4
LT		 6189 ha->dpc_active = 1;
6190
5f28d2d7
SK		 6191 ql_dbg(ql_dbg_dpc + ql_dbg_verbose, base_vha, 0x4001,
6192 "DPC handler waking up, dpc_flags=0x%lx.\n",
6193 base_vha->dpc_flags);
1da177e4 6194
a29b3dd7
JC		 6195 if (test_bit(UNLOADING, &base_vha->dpc_flags))
6196 break;
6197
7ec0effd
AD		 6198 if (IS_P3P_TYPE(ha)) {
6199 if (IS_QLA8044(ha)) {
6200 if (test_and_clear_bit(ISP_UNRECOVERABLE,
6201 &base_vha->dpc_flags)) {
6202 qla8044_idc_lock(ha);
6203 qla8044_wr_direct(base_vha,
6204 QLA8044_CRB_DEV_STATE_INDEX,
6205 QLA8XXX_DEV_FAILED);
6206 qla8044_idc_unlock(ha);
6207 ql_log(ql_log_info, base_vha, 0x4004,
6208 "HW State: FAILED.\n");
6209 qla8044_device_state_handler(base_vha);
6210 continue;
6211 }
6212
6213 } else {
6214 if (test_and_clear_bit(ISP_UNRECOVERABLE,
6215 &base_vha->dpc_flags)) {
6216 qla82xx_idc_lock(ha);
6217 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
6218 QLA8XXX_DEV_FAILED);
6219 qla82xx_idc_unlock(ha);
6220 ql_log(ql_log_info, base_vha, 0x0151,
6221 "HW State: FAILED.\n");
6222 qla82xx_device_state_handler(base_vha);
6223 continue;
6224 }
a9083016
GM		 6225 }
6226
6227 if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED,
6228 &base_vha->dpc_flags)) {
6229
7c3df132
SK		 6230 ql_dbg(ql_dbg_dpc, base_vha, 0x4005,
6231 "FCoE context reset scheduled.\n");
a9083016
GM		 6232 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
6233 &base_vha->dpc_flags))) {
6234 if (qla82xx_fcoe_ctx_reset(base_vha)) {
6235 /* FCoE-ctx reset failed.
6236 * Escalate to chip-reset
6237 */
6238 set_bit(ISP_ABORT_NEEDED,
6239 &base_vha->dpc_flags);
6240 }
6241 clear_bit(ABORT_ISP_ACTIVE,
6242 &base_vha->dpc_flags);
6243 }
6244
7c3df132
SK		 6245 ql_dbg(ql_dbg_dpc, base_vha, 0x4006,
6246 "FCoE context reset end.\n");
a9083016 6247 }
8ae6d9c7
GM		 6248 } else if (IS_QLAFX00(ha)) {
6249 if (test_and_clear_bit(ISP_UNRECOVERABLE,
6250 &base_vha->dpc_flags)) {
6251 ql_dbg(ql_dbg_dpc, base_vha, 0x4020,
6252 "Firmware Reset Recovery\n");
6253 if (qlafx00_reset_initialize(base_vha)) {
6254 /* Failed. Abort isp later. */
6255 if (!test_bit(UNLOADING,
f92f82d6 6256 &base_vha->dpc_flags)) {
8ae6d9c7
GM		 6257 set_bit(ISP_UNRECOVERABLE,
6258 &base_vha->dpc_flags);
6259 ql_dbg(ql_dbg_dpc, base_vha,
6260 0x4021,
6261 "Reset Recovery Failed\n");
f92f82d6 6262 }
8ae6d9c7
GM		 6263 }
6264 }
6265
6266 if (test_and_clear_bit(FX00_TARGET_SCAN,
6267 &base_vha->dpc_flags)) {
6268 ql_dbg(ql_dbg_dpc, base_vha, 0x4022,
6269 "ISPFx00 Target Scan scheduled\n");
6270 if (qlafx00_rescan_isp(base_vha)) {
6271 if (!test_bit(UNLOADING,
6272 &base_vha->dpc_flags))
6273 set_bit(ISP_UNRECOVERABLE,
6274 &base_vha->dpc_flags);
6275 ql_dbg(ql_dbg_dpc, base_vha, 0x401e,
6276 "ISPFx00 Target Scan Failed\n");
6277 }
6278 ql_dbg(ql_dbg_dpc, base_vha, 0x401f,
6279 "ISPFx00 Target Scan End\n");
6280 }
e8f5e95d
AB		 6281 if (test_and_clear_bit(FX00_HOST_INFO_RESEND,
6282 &base_vha->dpc_flags)) {
6283 ql_dbg(ql_dbg_dpc, base_vha, 0x4023,
6284 "ISPFx00 Host Info resend scheduled\n");
6285 qlafx00_fx_disc(base_vha,
6286 &base_vha->hw->mr.fcport,
6287 FXDISC_REG_HOST_INFO);
6288 }
a9083016
GM		 6289 }
6290
e4e3a2ce
QT		 6291 if (test_and_clear_bit(DETECT_SFP_CHANGE,
6292 &base_vha->dpc_flags) &&
6293 !test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) {
6294 qla24xx_detect_sfp(base_vha);
6295
6296 if (ha->flags.detected_lr_sfp !=
6297 ha->flags.using_lr_setting)
6298 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
6299 }
6300
b08abbd9
QT		 6301 if (test_and_clear_bit
6302 (ISP_ABORT_NEEDED, &base_vha->dpc_flags) &&
6303 !test_bit(UNLOADING, &base_vha->dpc_flags)) {
93eca613
QT		 6304 bool do_reset = true;
6305
0645cb83 6306 switch (base_vha->qlini_mode) {
93eca613
QT		 6307 case QLA2XXX_INI_MODE_ENABLED:
6308 break;
6309 case QLA2XXX_INI_MODE_DISABLED:
0645cb83
QT		 6310 if (!qla_tgt_mode_enabled(base_vha) &&
6311 !ha->flags.fw_started)
93eca613
QT		 6312 do_reset = false;
6313 break;
6314 case QLA2XXX_INI_MODE_DUAL:
0645cb83
QT		 6315 if (!qla_dual_mode_enabled(base_vha) &&
6316 !ha->flags.fw_started)
93eca613
QT		 6317 do_reset = false;
6318 break;
6319 default:
6320 break;
6321 }
1da177e4 6322
93eca613 6323 if (do_reset && !(test_and_set_bit(ABORT_ISP_ACTIVE,
e315cd28 6324 &base_vha->dpc_flags))) {
93eca613
QT		 6325 ql_dbg(ql_dbg_dpc, base_vha, 0x4007,
6326 "ISP abort scheduled.\n");
a9083016 6327 if (ha->isp_ops->abort_isp(base_vha)) {
1da177e4
LT		 6328 /* failed. retry later */
6329 set_bit(ISP_ABORT_NEEDED,
e315cd28 6330 &base_vha->dpc_flags);
99363ef8 6331 }
e315cd28
AC		 6332 clear_bit(ABORT_ISP_ACTIVE,
6333 &base_vha->dpc_flags);
93eca613
QT		 6334 ql_dbg(ql_dbg_dpc, base_vha, 0x4008,
6335 "ISP abort end.\n");
99363ef8 6336 }
1da177e4
LT		 6337 }
6338
a394aac8
DJ		 6339 if (test_and_clear_bit(FCPORT_UPDATE_NEEDED,
6340 &base_vha->dpc_flags)) {
e315cd28 6341 qla2x00_update_fcports(base_vha);
c9c5ced9 6342 }
d97994dc 6343
8ae6d9c7
GM		 6344 if (IS_QLAFX00(ha))
6345 goto loop_resync_check;
6346
579d12b5 6347 if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) {
7c3df132
SK		 6348 ql_dbg(ql_dbg_dpc, base_vha, 0x4009,
6349 "Quiescence mode scheduled.\n");
7ec0effd
AD		 6350 if (IS_P3P_TYPE(ha)) {
6351 if (IS_QLA82XX(ha))
6352 qla82xx_device_state_handler(base_vha);
6353 if (IS_QLA8044(ha))
6354 qla8044_device_state_handler(base_vha);
8fcd6b8b
CD		 6355 clear_bit(ISP_QUIESCE_NEEDED,
6356 &base_vha->dpc_flags);
6357 if (!ha->flags.quiesce_owner) {
6358 qla2x00_perform_loop_resync(base_vha);
7ec0effd
AD		 6359 if (IS_QLA82XX(ha)) {
6360 qla82xx_idc_lock(ha);
6361 qla82xx_clear_qsnt_ready(
6362 base_vha);
6363 qla82xx_idc_unlock(ha);
6364 } else if (IS_QLA8044(ha)) {
6365 qla8044_idc_lock(ha);
6366 qla8044_clear_qsnt_ready(
6367 base_vha);
6368 qla8044_idc_unlock(ha);
6369 }
8fcd6b8b
CD		 6370 }
6371 } else {
6372 clear_bit(ISP_QUIESCE_NEEDED,
6373 &base_vha->dpc_flags);
6374 qla2x00_quiesce_io(base_vha);
579d12b5 6375 }
7c3df132
SK		 6376 ql_dbg(ql_dbg_dpc, base_vha, 0x400a,
6377 "Quiescence mode end.\n");
579d12b5
SK		 6378 }
6379
e315cd28 6380 if (test_and_clear_bit(RESET_MARKER_NEEDED,
8ae6d9c7 6381 &base_vha->dpc_flags) &&
e315cd28 6382 (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) {
1da177e4 6383
7c3df132
SK		 6384 ql_dbg(ql_dbg_dpc, base_vha, 0x400b,
6385 "Reset marker scheduled.\n");
e315cd28
AC		 6386 qla2x00_rst_aen(base_vha);
6387 clear_bit(RESET_ACTIVE, &base_vha->dpc_flags);
7c3df132
SK		 6388 ql_dbg(ql_dbg_dpc, base_vha, 0x400c,
6389 "Reset marker end.\n");
1da177e4
LT		 6390 }
6391
6392 /* Retry each device up to login retry count */
4005a995 6393 if (test_bit(RELOGIN_NEEDED, &base_vha->dpc_flags) &&
e315cd28
AC		 6394 !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) &&
6395 atomic_read(&base_vha->loop_state) != LOOP_DOWN) {
1da177e4 6396
4005a995
QT		 6397 if (!base_vha->relogin_jif ||
6398 time_after_eq(jiffies, base_vha->relogin_jif)) {
6399 base_vha->relogin_jif = jiffies + HZ;
6400 clear_bit(RELOGIN_NEEDED, &base_vha->dpc_flags);
6401
9b3e0f4d 6402 ql_dbg(ql_dbg_disc, base_vha, 0x400d,
4005a995 6403 "Relogin scheduled.\n");
9b3e0f4d 6404 qla24xx_post_relogin_work(base_vha);
4005a995 6405 }
1da177e4 6406 }
8ae6d9c7 6407loop_resync_check:
e315cd28 6408 if (test_and_clear_bit(LOOP_RESYNC_NEEDED,
8ae6d9c7 6409 &base_vha->dpc_flags)) {
1da177e4 6410
7c3df132
SK		 6411 ql_dbg(ql_dbg_dpc, base_vha, 0x400f,
6412 "Loop resync scheduled.\n");
1da177e4
LT		 6413
6414 if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE,
e315cd28 6415 &base_vha->dpc_flags))) {
1da177e4 6416
52c82823 6417 qla2x00_loop_resync(base_vha);
1da177e4 6418
e315cd28
AC		 6419 clear_bit(LOOP_RESYNC_ACTIVE,
6420 &base_vha->dpc_flags);
1da177e4
LT		 6421 }
6422
7c3df132
SK		 6423 ql_dbg(ql_dbg_dpc, base_vha, 0x4010,
6424 "Loop resync end.\n");
1da177e4
LT		 6425 }
6426
8ae6d9c7
GM		 6427 if (IS_QLAFX00(ha))
6428 goto intr_on_check;
6429
e315cd28
AC		 6430 if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) &&
6431 atomic_read(&base_vha->loop_state) == LOOP_READY) {
6432 clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags);
6433 qla2xxx_flash_npiv_conf(base_vha);
272976ca
AV		 6434 }
6435
8ae6d9c7 6436intr_on_check:
1da177e4 6437 if (!ha->interrupts_on)
fd34f556 6438 ha->isp_ops->enable_intrs(ha);
1da177e4 6439
e315cd28 6440 if (test_and_clear_bit(BEACON_BLINK_NEEDED,
90b604f2
HM		 6441 &base_vha->dpc_flags)) {
6442 if (ha->beacon_blink_led == 1)
6443 ha->isp_ops->beacon_blink(base_vha);
6444 }
f6df144c 6445
d7459527
MH		 6446 /* qpair online check */
6447 if (test_and_clear_bit(QPAIR_ONLINE_CHECK_NEEDED,
6448 &base_vha->dpc_flags)) {
6449 if (ha->flags.eeh_busy ||
6450 ha->flags.pci_channel_io_perm_failure)
6451 online = 0;
6452 else
6453 online = 1;
6454
6455 mutex_lock(&ha->mq_lock);
6456 list_for_each_entry(qpair, &base_vha->qp_list,
6457 qp_list_elem)
6458 qpair->online = online;
6459 mutex_unlock(&ha->mq_lock);
6460 }
6461
8b4673ba
QT		 6462 if (test_and_clear_bit(SET_NVME_ZIO_THRESHOLD_NEEDED,
6463 &base_vha->dpc_flags)) {
deeae7a6
DG		 6464 ql_log(ql_log_info, base_vha, 0xffffff,
6465 "nvme: SET ZIO Activity exchange threshold to %d.\n",
6466 ha->nvme_last_rptd_aen);
8b4673ba
QT		 6467 if (qla27xx_set_zio_threshold(base_vha,
6468 ha->nvme_last_rptd_aen)) {
deeae7a6 6469 ql_log(ql_log_info, base_vha, 0xffffff,
8b4673ba
QT		 6470 "nvme: Unable to SET ZIO Activity exchange threshold to %d.\n",
6471 ha->nvme_last_rptd_aen);
deeae7a6
DG		 6472 }
6473 }
6474
8b4673ba
QT		 6475 if (test_and_clear_bit(SET_ZIO_THRESHOLD_NEEDED,
6476 &base_vha->dpc_flags)) {
6477 ql_log(ql_log_info, base_vha, 0xffffff,
6478 "SET ZIO Activity exchange threshold to %d.\n",
6479 ha->last_zio_threshold);
6480 qla27xx_set_zio_threshold(base_vha,
6481 ha->last_zio_threshold);
6482 }
6483
8ae6d9c7
GM		 6484 if (!IS_QLAFX00(ha))
6485 qla2x00_do_dpc_all_vps(base_vha);
2c3dfe3f 6486
48acad09
QT		 6487 if (test_and_clear_bit(N2N_LINK_RESET,
6488 &base_vha->dpc_flags)) {
6489 qla2x00_lip_reset(base_vha);
6490 }
6491
1da177e4 6492 ha->dpc_active = 0;
c142caf0 6493end_loop:
563585ec 6494 set_current_state(TASK_INTERRUPTIBLE);
1da177e4 6495 } /* End of while(1) */
563585ec 6496 __set_current_state(TASK_RUNNING);
1da177e4 6497
7c3df132
SK		 6498 ql_dbg(ql_dbg_dpc, base_vha, 0x4011,
6499 "DPC handler exiting.\n");
1da177e4
LT		 6500
6501 /*
6502 * Make sure that nobody tries to wake us up again.
6503 */
1da177e4
LT		 6504 ha->dpc_active = 0;
6505
ac280b67
AV		 6506 /* Cleanup any residual CTX SRBs. */
6507 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
6508
39a11240
CH		 6509 return 0;
6510}
6511
6512void
e315cd28 6513qla2xxx_wake_dpc(struct scsi_qla_host *vha)
39a11240 6514{
e315cd28 6515 struct qla_hw_data *ha = vha->hw;
c795c1e4
AV		 6516 struct task_struct *t = ha->dpc_thread;
6517
e315cd28 6518 if (!test_bit(UNLOADING, &vha->dpc_flags) && t)
c795c1e4 6519 wake_up_process(t);
1da177e4
LT		 6520}
6521
1da177e4
LT		 6522/*
6523* qla2x00_rst_aen
6524* Processes asynchronous reset.
6525*
6526* Input:
6527* ha = adapter block pointer.
6528*/
6529static void
e315cd28 6530qla2x00_rst_aen(scsi_qla_host_t *vha)
1da177e4 6531{
e315cd28
AC		 6532 if (vha->flags.online && !vha->flags.reset_active &&
6533 !atomic_read(&vha->loop_down_timer) &&
6534 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) {
1da177e4 6535 do {
e315cd28 6536 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
1da177e4
LT		 6537
6538 /*
6539 * Issue marker command only when we are going to start
6540 * the I/O.
6541 */
e315cd28
AC		 6542 vha->marker_needed = 1;
6543 } while (!atomic_read(&vha->loop_down_timer) &&
6544 (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)));
1da177e4
LT		 6545 }
6546}
6547
1da177e4
LT		 6548/**************************************************************************
6549* qla2x00_timer
6550*
6551* Description:
6552* One second timer
6553*
6554* Context: Interrupt
6555***************************************************************************/
2c3dfe3f 6556void
8e5f4ba0 6557qla2x00_timer(struct timer_list *t)
1da177e4 6558{
8e5f4ba0 6559 scsi_qla_host_t *vha = from_timer(vha, t, timer);
1da177e4 6560 unsigned long cpu_flags = 0;
1da177e4
LT		 6561 int start_dpc = 0;
6562 int index;
6563 srb_t *sp;
85880801 6564 uint16_t w;
e315cd28 6565 struct qla_hw_data *ha = vha->hw;
73208dfd 6566 struct req_que *req;
85880801 6567
a5b36321 6568 if (ha->flags.eeh_busy) {
7c3df132
SK		 6569 ql_dbg(ql_dbg_timer, vha, 0x6000,
6570 "EEH = %d, restarting timer.\n",
6571 ha->flags.eeh_busy);
a5b36321
LC		 6572 qla2x00_restart_timer(vha, WATCH_INTERVAL);
6573 return;
6574 }
6575
f3ddac19
CD		 6576 /*
6577 * Hardware read to raise pending EEH errors during mailbox waits. If
6578 * the read returns -1 then disable the board.
6579 */
6580 if (!pci_channel_offline(ha->pdev)) {
85880801 6581 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w);
c821e0d5 6582 qla2x00_check_reg16_for_disconnect(vha, w);
f3ddac19 6583 }
1da177e4 6584
cefcaba6 6585 /* Make sure qla82xx_watchdog is run only for physical port */
7ec0effd 6586 if (!vha->vp_idx && IS_P3P_TYPE(ha)) {
579d12b5
SK		 6587 if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags))
6588 start_dpc++;
7ec0effd
AD		 6589 if (IS_QLA82XX(ha))
6590 qla82xx_watchdog(vha);
6591 else if (IS_QLA8044(ha))
6592 qla8044_watchdog(vha);
579d12b5
SK		 6593 }
6594
8ae6d9c7
GM		 6595 if (!vha->vp_idx && IS_QLAFX00(ha))
6596 qlafx00_timer_routine(vha);
6597
1da177e4 6598 /* Loop down handler. */
e315cd28 6599 if (atomic_read(&vha->loop_down_timer) > 0 &&
8f7daead
GM		 6600 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) &&
6601 !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags))
e315cd28 6602 && vha->flags.online) {
1da177e4 6603
e315cd28
AC		 6604 if (atomic_read(&vha->loop_down_timer) ==
6605 vha->loop_down_abort_time) {
1da177e4 6606
7c3df132
SK		 6607 ql_log(ql_log_info, vha, 0x6008,
6608 "Loop down - aborting the queues before time expires.\n");
1da177e4 6609
e315cd28
AC		 6610 if (!IS_QLA2100(ha) && vha->link_down_timeout)
6611 atomic_set(&vha->loop_state, LOOP_DEAD);
1da177e4 6612
f08b7251
AV		 6613 /*
6614 * Schedule an ISP abort to return any FCP2-device
6615 * commands.
6616 */
2c3dfe3f 6617 /* NPIV - scan physical port only */
e315cd28 6618 if (!vha->vp_idx) {
2c3dfe3f
SJ		 6619 spin_lock_irqsave(&ha->hardware_lock,
6620 cpu_flags);
73208dfd 6621 req = ha->req_q_map[0];
2c3dfe3f 6622 for (index = 1;
8d93f550 6623 index < req->num_outstanding_cmds;
2c3dfe3f
SJ		 6624 index++) {
6625 fc_port_t *sfcp;
6626
e315cd28 6627 sp = req->outstanding_cmds[index];
2c3dfe3f
SJ		 6628 if (!sp)
6629 continue;
c5419e26
QT		 6630 if (sp->cmd_type != TYPE_SRB)
6631 continue;
9ba56b95 6632 if (sp->type != SRB_SCSI_CMD)
cf53b069 6633 continue;
2c3dfe3f 6634 sfcp = sp->fcport;
f08b7251 6635 if (!(sfcp->flags & FCF_FCP2_DEVICE))
2c3dfe3f 6636 continue;
bdf79621 6637
8f7daead
GM		 6638 if (IS_QLA82XX(ha))
6639 set_bit(FCOE_CTX_RESET_NEEDED,
6640 &vha->dpc_flags);
6641 else
6642 set_bit(ISP_ABORT_NEEDED,
e315cd28 6643 &vha->dpc_flags);
2c3dfe3f
SJ		 6644 break;
6645 }
6646 spin_unlock_irqrestore(&ha->hardware_lock,
e315cd28 6647 cpu_flags);
1da177e4 6648 }
1da177e4
LT		 6649 start_dpc++;
6650 }
6651
6652 /* if the loop has been down for 4 minutes, reinit adapter */
e315cd28 6653 if (atomic_dec_and_test(&vha->loop_down_timer) != 0) {
0d6e61bc 6654 if (!(vha->device_flags & DFLG_NO_CABLE)) {
7c3df132 6655 ql_log(ql_log_warn, vha, 0x6009,
1da177e4
LT		 6656 "Loop down - aborting ISP.\n");
6657
8f7daead
GM		 6658 if (IS_QLA82XX(ha))
6659 set_bit(FCOE_CTX_RESET_NEEDED,
6660 &vha->dpc_flags);
6661 else
6662 set_bit(ISP_ABORT_NEEDED,
6663 &vha->dpc_flags);
1da177e4
LT		 6664 }
6665 }
7c3df132
SK		 6666 ql_dbg(ql_dbg_timer, vha, 0x600a,
6667 "Loop down - seconds remaining %d.\n",
6668 atomic_read(&vha->loop_down_timer));
1da177e4 6669 }
cefcaba6
SK		 6670 /* Check if beacon LED needs to be blinked for physical host only */
6671 if (!vha->vp_idx && (ha->beacon_blink_led == 1)) {
999916dc 6672 /* There is no beacon_blink function for ISP82xx */
7ec0effd 6673 if (!IS_P3P_TYPE(ha)) {
999916dc
SK		 6674 set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags);
6675 start_dpc++;
6676 }
f6df144c 6677 }
6678
550bf57d 6679 /* Process any deferred work. */
9b3e0f4d
QT		 6680 if (!list_empty(&vha->work_list)) {
6681 unsigned long flags;
6682 bool q = false;
6683
6684 spin_lock_irqsave(&vha->work_lock, flags);
6685 if (!test_and_set_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags))
6686 q = true;
6687 spin_unlock_irqrestore(&vha->work_lock, flags);
6688 if (q)
6689 queue_work(vha->hw->wq, &vha->iocb_work);
6690 }
550bf57d 6691
7401bc18
DG		 6692 /*
6693 * FC-NVME
6694 * see if the active AEN count has changed from what was last reported.
6695 */
b2d1453a
GM		 6696 if (!vha->vp_idx &&
6697 (atomic_read(&ha->nvme_active_aen_cnt) != ha->nvme_last_rptd_aen) &&
6698 ha->zio_mode == QLA_ZIO_MODE_6 &&
6699 !ha->flags.host_shutting_down) {
7401bc18 6700 ql_log(ql_log_info, vha, 0x3002,
8b4673ba
QT		 6701 "nvme: Sched: Set ZIO exchange threshold to %d.\n",
6702 ha->nvme_last_rptd_aen);
deeae7a6 6703 ha->nvme_last_rptd_aen = atomic_read(&ha->nvme_active_aen_cnt);
8b4673ba
QT		 6704 set_bit(SET_NVME_ZIO_THRESHOLD_NEEDED, &vha->dpc_flags);
6705 start_dpc++;
6706 }
6707
6708 if (!vha->vp_idx &&
6709 (atomic_read(&ha->zio_threshold) != ha->last_zio_threshold) &&
6710 (ha->zio_mode == QLA_ZIO_MODE_6) &&
ecc89f25 6711 (IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))) {
8b4673ba
QT		 6712 ql_log(ql_log_info, vha, 0x3002,
6713 "Sched: Set ZIO exchange threshold to %d.\n",
6714 ha->last_zio_threshold);
6715 ha->last_zio_threshold = atomic_read(&ha->zio_threshold);
deeae7a6
DG		 6716 set_bit(SET_ZIO_THRESHOLD_NEEDED, &vha->dpc_flags);
6717 start_dpc++;
7401bc18
DG		 6718 }
6719
1da177e4 6720 /* Schedule the DPC routine if needed */
e315cd28
AC		 6721 if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) ||
6722 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) ||
6723 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags) ||
1da177e4 6724 start_dpc ||
e315cd28
AC		 6725 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) ||
6726 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) ||
a9083016
GM		 6727 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) ||
6728 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) ||
e315cd28 6729 test_bit(VP_DPC_NEEDED, &vha->dpc_flags) ||
50280c01 6730 test_bit(RELOGIN_NEEDED, &vha->dpc_flags))) {
7c3df132
SK		 6731 ql_dbg(ql_dbg_timer, vha, 0x600b,
6732 "isp_abort_needed=%d loop_resync_needed=%d "
6733 "fcport_update_needed=%d start_dpc=%d "
6734 "reset_marker_needed=%d",
6735 test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags),
6736 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags),
6737 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags),
6738 start_dpc,
6739 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags));
6740 ql_dbg(ql_dbg_timer, vha, 0x600c,
6741 "beacon_blink_needed=%d isp_unrecoverable=%d "
6742 "fcoe_ctx_reset_needed=%d vp_dpc_needed=%d "
50280c01 6743 "relogin_needed=%d.\n",
7c3df132
SK		 6744 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags),
6745 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags),
6746 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags),
6747 test_bit(VP_DPC_NEEDED, &vha->dpc_flags),
50280c01 6748 test_bit(RELOGIN_NEEDED, &vha->dpc_flags));
e315cd28 6749 qla2xxx_wake_dpc(vha);
7c3df132 6750 }
1da177e4 6751
e315cd28 6752 qla2x00_restart_timer(vha, WATCH_INTERVAL);
1da177e4
LT		 6753}
6754
5433383e
AV		 6755/* Firmware interface routines. */
6756
5433383e
AV		 6757#define FW_ISP21XX 0
6758#define FW_ISP22XX 1
6759#define FW_ISP2300 2
6760#define FW_ISP2322 3
48c02fde 6761#define FW_ISP24XX 4
c3a2f0df 6762#define FW_ISP25XX 5
3a03eb79 6763#define FW_ISP81XX 6
a9083016 6764#define FW_ISP82XX 7
6246b8a1
GM		 6765#define FW_ISP2031 8
6766#define FW_ISP8031 9
2c5bbbb2 6767#define FW_ISP27XX 10
ecc89f25 6768#define FW_ISP28XX 11
5433383e 6769
bb8ee499
AV		 6770#define FW_FILE_ISP21XX "ql2100_fw.bin"
6771#define FW_FILE_ISP22XX "ql2200_fw.bin"
6772#define FW_FILE_ISP2300 "ql2300_fw.bin"
6773#define FW_FILE_ISP2322 "ql2322_fw.bin"
6774#define FW_FILE_ISP24XX "ql2400_fw.bin"
c3a2f0df 6775#define FW_FILE_ISP25XX "ql2500_fw.bin"
3a03eb79 6776#define FW_FILE_ISP81XX "ql8100_fw.bin"
a9083016 6777#define FW_FILE_ISP82XX "ql8200_fw.bin"
6246b8a1
GM		 6778#define FW_FILE_ISP2031 "ql2600_fw.bin"
6779#define FW_FILE_ISP8031 "ql8300_fw.bin"
2c5bbbb2 6780#define FW_FILE_ISP27XX "ql2700_fw.bin"
ecc89f25 6781#define FW_FILE_ISP28XX "ql2800_fw.bin"
f73cb695 6782
bb8ee499 6783
e1e82b6f 6784static DEFINE_MUTEX(qla_fw_lock);
5433383e 6785
ecc89f25 6786static struct fw_blob qla_fw_blobs[] = {
bb8ee499
AV		 6787 { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, },
6788 { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, },
6789 { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, },
6790 { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, },
6791 { .name = FW_FILE_ISP24XX, },
c3a2f0df 6792 { .name = FW_FILE_ISP25XX, },
3a03eb79 6793 { .name = FW_FILE_ISP81XX, },
a9083016 6794 { .name = FW_FILE_ISP82XX, },
6246b8a1
GM		 6795 { .name = FW_FILE_ISP2031, },
6796 { .name = FW_FILE_ISP8031, },
2c5bbbb2 6797 { .name = FW_FILE_ISP27XX, },
ecc89f25
JC		 6798 { .name = FW_FILE_ISP28XX, },
6799 { .name = NULL, },
5433383e
AV		 6800};
6801
6802struct fw_blob *
e315cd28 6803qla2x00_request_firmware(scsi_qla_host_t *vha)
5433383e 6804{
e315cd28 6805 struct qla_hw_data *ha = vha->hw;
5433383e
AV		 6806 struct fw_blob *blob;
6807
5433383e
AV		 6808 if (IS_QLA2100(ha)) {
6809 blob = &qla_fw_blobs[FW_ISP21XX];
6810 } else if (IS_QLA2200(ha)) {
6811 blob = &qla_fw_blobs[FW_ISP22XX];
48c02fde 6812 } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
5433383e 6813 blob = &qla_fw_blobs[FW_ISP2300];
48c02fde 6814 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
5433383e 6815 blob = &qla_fw_blobs[FW_ISP2322];
4d4df193 6816 } else if (IS_QLA24XX_TYPE(ha)) {
5433383e 6817 blob = &qla_fw_blobs[FW_ISP24XX];
c3a2f0df
AV		 6818 } else if (IS_QLA25XX(ha)) {
6819 blob = &qla_fw_blobs[FW_ISP25XX];
3a03eb79
AV		 6820 } else if (IS_QLA81XX(ha)) {
6821 blob = &qla_fw_blobs[FW_ISP81XX];
a9083016
GM		 6822 } else if (IS_QLA82XX(ha)) {
6823 blob = &qla_fw_blobs[FW_ISP82XX];
6246b8a1
GM		 6824 } else if (IS_QLA2031(ha)) {
6825 blob = &qla_fw_blobs[FW_ISP2031];
6826 } else if (IS_QLA8031(ha)) {
6827 blob = &qla_fw_blobs[FW_ISP8031];
2c5bbbb2
JC		 6828 } else if (IS_QLA27XX(ha)) {
6829 blob = &qla_fw_blobs[FW_ISP27XX];
ecc89f25
JC		 6830 } else if (IS_QLA28XX(ha)) {
6831 blob = &qla_fw_blobs[FW_ISP28XX];
8a655229
DC		 6832 } else {
6833 return NULL;
5433383e
AV		 6834 }
6835
ecc89f25
JC		 6836 if (!blob->name)
6837 return NULL;
6838
e1e82b6f 6839 mutex_lock(&qla_fw_lock);
5433383e
AV		 6840 if (blob->fw)
6841 goto out;
6842
6843 if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) {
7c3df132
SK		 6844 ql_log(ql_log_warn, vha, 0x0063,
6845 "Failed to load firmware image (%s).\n", blob->name);
5433383e
AV		 6846 blob->fw = NULL;
6847 blob = NULL;
5433383e
AV		 6848 }
6849
6850out:
e1e82b6f 6851 mutex_unlock(&qla_fw_lock);
5433383e
AV		 6852 return blob;
6853}
6854
6855static void
6856qla2x00_release_firmware(void)
6857{
ecc89f25 6858 struct fw_blob *blob;
5433383e 6859
e1e82b6f 6860 mutex_lock(&qla_fw_lock);
ecc89f25
JC		 6861 for (blob = qla_fw_blobs; blob->name; blob++)
6862 release_firmware(blob->fw);
e1e82b6f 6863 mutex_unlock(&qla_fw_lock);
5433383e
AV		 6864}
6865
5386a4e6
QT		 6866static void qla_pci_error_cleanup(scsi_qla_host_t *vha)
6867{
6868 struct qla_hw_data *ha = vha->hw;
6869 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
6870 struct qla_qpair *qpair = NULL;
6871 struct scsi_qla_host *vp;
6872 fc_port_t *fcport;
6873 int i;
6874 unsigned long flags;
6875
6876 ha->chip_reset++;
6877
6878 ha->base_qpair->chip_reset = ha->chip_reset;
6879 for (i = 0; i < ha->max_qpairs; i++) {
6880 if (ha->queue_pair_map[i])
6881 ha->queue_pair_map[i]->chip_reset =
6882 ha->base_qpair->chip_reset;
6883 }
6884
6885 /* purge MBox commands */
6886 if (atomic_read(&ha->num_pend_mbx_stage3)) {
6887 clear_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags);
6888 complete(&ha->mbx_intr_comp);
6889 }
6890
6891 i = 0;
6892
6893 while (atomic_read(&ha->num_pend_mbx_stage3) ||
6894 atomic_read(&ha->num_pend_mbx_stage2) ||
6895 atomic_read(&ha->num_pend_mbx_stage1)) {
6896 msleep(20);
6897 i++;
6898 if (i > 50)
6899 break;
6900 }
6901
6902 ha->flags.purge_mbox = 0;
6903
6904 mutex_lock(&ha->mq_lock);
6905 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem)
6906 qpair->online = 0;
6907 mutex_unlock(&ha->mq_lock);
6908
6909 qla2x00_mark_all_devices_lost(vha, 0);
6910
6911 spin_lock_irqsave(&ha->vport_slock, flags);
6912 list_for_each_entry(vp, &ha->vp_list, list) {
6913 atomic_inc(&vp->vref_count);
6914 spin_unlock_irqrestore(&ha->vport_slock, flags);
6915 qla2x00_mark_all_devices_lost(vp, 0);
6916 spin_lock_irqsave(&ha->vport_slock, flags);
6917 atomic_dec(&vp->vref_count);
6918 }
6919 spin_unlock_irqrestore(&ha->vport_slock, flags);
6920
6921 /* Clear all async request states across all VPs. */
6922 list_for_each_entry(fcport, &vha->vp_fcports, list)
6923 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
6924
6925 spin_lock_irqsave(&ha->vport_slock, flags);
6926 list_for_each_entry(vp, &ha->vp_list, list) {
6927 atomic_inc(&vp->vref_count);
6928 spin_unlock_irqrestore(&ha->vport_slock, flags);
6929 list_for_each_entry(fcport, &vp->vp_fcports, list)
6930 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
6931 spin_lock_irqsave(&ha->vport_slock, flags);
6932 atomic_dec(&vp->vref_count);
6933 }
6934 spin_unlock_irqrestore(&ha->vport_slock, flags);
6935}
6936
6937
14e660e6
SJ		 6938static pci_ers_result_t
6939qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
6940{
85880801
AV		 6941 scsi_qla_host_t *vha = pci_get_drvdata(pdev);
6942 struct qla_hw_data *ha = vha->hw;
6943
7c3df132
SK		 6944 ql_dbg(ql_dbg_aer, vha, 0x9000,
6945 "PCI error detected, state %x.\n", state);
b9b12f73 6946
efdb5760
SC		 6947 if (!atomic_read(&pdev->enable_cnt)) {
6948 ql_log(ql_log_info, vha, 0xffff,
6949 "PCI device is disabled,state %x\n", state);
6950 return PCI_ERS_RESULT_NEED_RESET;
6951 }
6952
14e660e6
SJ		 6953 switch (state) {
6954 case pci_channel_io_normal:
85880801 6955 ha->flags.eeh_busy = 0;
c38d1baf 6956 if (ql2xmqsupport || ql2xnvmeenable) {
d7459527
MH		 6957 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags);
6958 qla2xxx_wake_dpc(vha);
6959 }
14e660e6
SJ		 6960 return PCI_ERS_RESULT_CAN_RECOVER;
6961 case pci_channel_io_frozen:
85880801 6962 ha->flags.eeh_busy = 1;
5386a4e6 6963 qla_pci_error_cleanup(vha);
14e660e6
SJ		 6964 return PCI_ERS_RESULT_NEED_RESET;
6965 case pci_channel_io_perm_failure:
85880801
AV		 6966 ha->flags.pci_channel_io_perm_failure = 1;
6967 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
c38d1baf 6968 if (ql2xmqsupport || ql2xnvmeenable) {
d7459527
MH		 6969 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags);
6970 qla2xxx_wake_dpc(vha);
6971 }
14e660e6
SJ		 6972 return PCI_ERS_RESULT_DISCONNECT;
6973 }
6974 return PCI_ERS_RESULT_NEED_RESET;
6975}
6976
6977static pci_ers_result_t
6978qla2xxx_pci_mmio_enabled(struct pci_dev *pdev)
6979{
6980 int risc_paused = 0;
6981 uint32_t stat;
6982 unsigned long flags;
e315cd28
AC		 6983 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
6984 struct qla_hw_data *ha = base_vha->hw;
14e660e6
SJ		 6985 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
6986 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
6987
bcc5b6d3
SK		 6988 if (IS_QLA82XX(ha))
6989 return PCI_ERS_RESULT_RECOVERED;
6990
14e660e6
SJ		 6991 spin_lock_irqsave(&ha->hardware_lock, flags);
6992 if (IS_QLA2100(ha) || IS_QLA2200(ha)){
6993 stat = RD_REG_DWORD(&reg->hccr);
6994 if (stat & HCCR_RISC_PAUSE)
6995 risc_paused = 1;
6996 } else if (IS_QLA23XX(ha)) {
6997 stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
6998 if (stat & HSR_RISC_PAUSED)
6999 risc_paused = 1;
7000 } else if (IS_FWI2_CAPABLE(ha)) {
7001 stat = RD_REG_DWORD(&reg24->host_status);
7002 if (stat & HSRX_RISC_PAUSED)
7003 risc_paused = 1;
7004 }
7005 spin_unlock_irqrestore(&ha->hardware_lock, flags);
7006
7007 if (risc_paused) {
7c3df132
SK		 7008 ql_log(ql_log_info, base_vha, 0x9003,
7009 "RISC paused -- mmio_enabled, Dumping firmware.\n");
e315cd28 7010 ha->isp_ops->fw_dump(base_vha, 0);
14e660e6
SJ		 7011
7012 return PCI_ERS_RESULT_NEED_RESET;
7013 } else
7014 return PCI_ERS_RESULT_RECOVERED;
7015}
7016
7017static pci_ers_result_t
7018qla2xxx_pci_slot_reset(struct pci_dev *pdev)
7019{
7020 pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT;
e315cd28
AC		 7021 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
7022 struct qla_hw_data *ha = base_vha->hw;
5386a4e6
QT		 7023 int rc;
7024 struct qla_qpair *qpair = NULL;
09483916 7025
7c3df132
SK		 7026 ql_dbg(ql_dbg_aer, base_vha, 0x9004,
7027 "Slot Reset.\n");
85880801 7028
90a86fc0
JC		 7029 /* Workaround: qla2xxx driver which access hardware earlier
7030 * needs error state to be pci_channel_io_online.
7031 * Otherwise mailbox command timesout.
7032 */
7033 pdev->error_state = pci_channel_io_normal;
7034
7035 pci_restore_state(pdev);
7036
8c1496bd
RL		 7037 /* pci_restore_state() clears the saved_state flag of the device
7038 * save restored state which resets saved_state flag
7039 */
7040 pci_save_state(pdev);
7041
09483916
BH		 7042 if (ha->mem_only)
7043 rc = pci_enable_device_mem(pdev);
7044 else
7045 rc = pci_enable_device(pdev);
14e660e6 7046
09483916 7047 if (rc) {
7c3df132 7048 ql_log(ql_log_warn, base_vha, 0x9005,
14e660e6 7049 "Can't re-enable PCI device after reset.\n");
a5b36321 7050 goto exit_slot_reset;
14e660e6 7051 }
14e660e6 7052
90a86fc0 7053
e315cd28 7054 if (ha->isp_ops->pci_config(base_vha))
a5b36321
LC		 7055 goto exit_slot_reset;
7056
5386a4e6
QT		 7057 mutex_lock(&ha->mq_lock);
7058 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem)
7059 qpair->online = 1;
7060 mutex_unlock(&ha->mq_lock);
85880801 7061
5386a4e6 7062 base_vha->flags.online = 1;
e315cd28 7063 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
a9083016 7064 if (ha->isp_ops->abort_isp(base_vha) == QLA_SUCCESS)
14e660e6 7065 ret = PCI_ERS_RESULT_RECOVERED;
e315cd28 7066 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
14e660e6 7067
90a86fc0 7068
a5b36321 7069exit_slot_reset:
7c3df132
SK		 7070 ql_dbg(ql_dbg_aer, base_vha, 0x900e,
7071 "slot_reset return %x.\n", ret);
85880801 7072
14e660e6
SJ		 7073 return ret;
7074}
7075
7076static void
7077qla2xxx_pci_resume(struct pci_dev *pdev)
7078{
e315cd28
AC		 7079 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
7080 struct qla_hw_data *ha = base_vha->hw;
14e660e6
SJ		 7081 int ret;
7082
7c3df132
SK		 7083 ql_dbg(ql_dbg_aer, base_vha, 0x900f,
7084 "pci_resume.\n");
85880801 7085
5386a4e6
QT		 7086 ha->flags.eeh_busy = 0;
7087
e315cd28 7088 ret = qla2x00_wait_for_hba_online(base_vha);
14e660e6 7089 if (ret != QLA_SUCCESS) {
7c3df132
SK		 7090 ql_log(ql_log_fatal, base_vha, 0x9002,
7091 "The device failed to resume I/O from slot/link_reset.\n");
14e660e6 7092 }
14e660e6
SJ		 7093}
7094
590f806d
QT		 7095static void
7096qla_pci_reset_prepare(struct pci_dev *pdev)
7097{
7098 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
7099 struct qla_hw_data *ha = base_vha->hw;
7100 struct qla_qpair *qpair;
7101
7102 ql_log(ql_log_warn, base_vha, 0xffff,
7103 "%s.\n", __func__);
7104
7105 /*
7106 * PCI FLR/function reset is about to reset the
7107 * slot. Stop the chip to stop all DMA access.
7108 * It is assumed that pci_reset_done will be called
7109 * after FLR to resume Chip operation.
7110 */
7111 ha->flags.eeh_busy = 1;
7112 mutex_lock(&ha->mq_lock);
7113 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem)
7114 qpair->online = 0;
7115 mutex_unlock(&ha->mq_lock);
7116
7117 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
7118 qla2x00_abort_isp_cleanup(base_vha);
7119 qla2x00_abort_all_cmds(base_vha, DID_RESET << 16);
7120}
7121
7122static void
7123qla_pci_reset_done(struct pci_dev *pdev)
7124{
7125 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
7126 struct qla_hw_data *ha = base_vha->hw;
7127 struct qla_qpair *qpair;
7128
7129 ql_log(ql_log_warn, base_vha, 0xffff,
7130 "%s.\n", __func__);
7131
7132 /*
7133 * FLR just completed by PCI layer. Resume adapter
7134 */
7135 ha->flags.eeh_busy = 0;
7136 mutex_lock(&ha->mq_lock);
7137 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem)
7138 qpair->online = 1;
7139 mutex_unlock(&ha->mq_lock);
7140
7141 base_vha->flags.online = 1;
7142 ha->isp_ops->abort_isp(base_vha);
7143 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
7144}
7145
5601236b
MH		 7146static int qla2xxx_map_queues(struct Scsi_Host *shost)
7147{
d68b850e 7148 int rc;
5601236b 7149 scsi_qla_host_t *vha = (scsi_qla_host_t *)shost->hostdata;
485b0eca 7150 struct blk_mq_queue_map *qmap = &shost->tag_set.map[HCTX_TYPE_DEFAULT];
5601236b 7151
f3e02695 7152 if (USER_CTRL_IRQ(vha->hw) || !vha->hw->mqiobase)
ed76e329 7153 rc = blk_mq_map_queues(qmap);
d68b850e 7154 else
f0783d43 7155 rc = blk_mq_pci_map_queues(qmap, vha->hw->pdev, vha->irq_offset);
d68b850e 7156 return rc;
5601236b
MH		 7157}
7158
6515ad71
BVA		 7159struct scsi_host_template qla2xxx_driver_template = {
7160 .module = THIS_MODULE,
7161 .name = QLA2XXX_DRIVER_NAME,
7162 .queuecommand = qla2xxx_queuecommand,
7163
7164 .eh_timed_out = fc_eh_timed_out,
7165 .eh_abort_handler = qla2xxx_eh_abort,
7166 .eh_device_reset_handler = qla2xxx_eh_device_reset,
7167 .eh_target_reset_handler = qla2xxx_eh_target_reset,
7168 .eh_bus_reset_handler = qla2xxx_eh_bus_reset,
7169 .eh_host_reset_handler = qla2xxx_eh_host_reset,
7170
7171 .slave_configure = qla2xxx_slave_configure,
7172
7173 .slave_alloc = qla2xxx_slave_alloc,
7174 .slave_destroy = qla2xxx_slave_destroy,
7175 .scan_finished = qla2xxx_scan_finished,
7176 .scan_start = qla2xxx_scan_start,
7177 .change_queue_depth = scsi_change_queue_depth,
7178 .map_queues = qla2xxx_map_queues,
7179 .this_id = -1,
7180 .cmd_per_lun = 3,
7181 .sg_tablesize = SG_ALL,
7182
7183 .max_sectors = 0xFFFF,
7184 .shost_attrs = qla2x00_host_attrs,
7185
7186 .supported_mode = MODE_INITIATOR,
7187 .track_queue_depth = 1,
7188};
7189
a55b2d21 7190static const struct pci_error_handlers qla2xxx_err_handler = {
14e660e6
SJ		 7191 .error_detected = qla2xxx_pci_error_detected,
7192 .mmio_enabled = qla2xxx_pci_mmio_enabled,
7193 .slot_reset = qla2xxx_pci_slot_reset,
7194 .resume = qla2xxx_pci_resume,
590f806d
QT		 7195 .reset_prepare = qla_pci_reset_prepare,
7196 .reset_done = qla_pci_reset_done,
14e660e6
SJ		 7197};
7198
5433383e 7199static struct pci_device_id qla2xxx_pci_tbl[] = {
47f5e069
AV		 7200 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) },
7201 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) },
7202 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) },
7203 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) },
7204 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) },
7205 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) },
7206 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) },
7207 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) },
7208 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) },
4d4df193 7209 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) },
47f5e069
AV		 7210 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) },
7211 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) },
c3a2f0df 7212 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) },
6246b8a1 7213 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2031) },
3a03eb79 7214 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) },
a9083016 7215 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) },
650f528f 7216 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8031) },
8ae6d9c7 7217 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISPF001) },
7ec0effd 7218 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8044) },
f73cb695 7219 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2071) },
2c5bbbb2 7220 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2271) },
2b48992f 7221 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2261) },
ecc89f25
JC		 7222 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2061) },
7223 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2081) },
7224 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2281) },
7225 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2089) },
7226 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2289) },
5433383e
AV		 7227 { 0 },
7228};
7229MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl);
7230
fca29703 7231static struct pci_driver qla2xxx_pci_driver = {
cb63067a 7232 .name = QLA2XXX_DRIVER_NAME,
0a21ef1e
JB		 7233 .driver = {
7234 .owner = THIS_MODULE,
7235 },
fca29703 7236 .id_table = qla2xxx_pci_tbl,
7ee61397 7237 .probe = qla2x00_probe_one,
4c993f76 7238 .remove = qla2x00_remove_one,
e30d1756 7239 .shutdown = qla2x00_shutdown,
14e660e6 7240 .err_handler = &qla2xxx_err_handler,
fca29703
AV		 7241};
7242
75ef9de1 7243static const struct file_operations apidev_fops = {
6a03b4cd 7244 .owner = THIS_MODULE,
6038f373 7245 .llseek = noop_llseek,
6a03b4cd
HZ		 7246};
7247
1da177e4
LT		 7248/**
7249 * qla2x00_module_init - Module initialization.
7250 **/
7251static int __init
7252qla2x00_module_init(void)
7253{
fca29703
AV		 7254 int ret = 0;
7255
bc04459c
BVA		 7256 BUILD_BUG_ON(sizeof(cmd_entry_t) != 64);
7257 BUILD_BUG_ON(sizeof(cont_a64_entry_t) != 64);
7258 BUILD_BUG_ON(sizeof(cont_entry_t) != 64);
7259 BUILD_BUG_ON(sizeof(init_cb_t) != 96);
7260 BUILD_BUG_ON(sizeof(ms_iocb_entry_t) != 64);
7261 BUILD_BUG_ON(sizeof(request_t) != 64);
7262 BUILD_BUG_ON(sizeof(struct access_chip_84xx) != 64);
7263 BUILD_BUG_ON(sizeof(struct cmd_bidir) != 64);
7264 BUILD_BUG_ON(sizeof(struct cmd_nvme) != 64);
7265 BUILD_BUG_ON(sizeof(struct cmd_type_6) != 64);
7266 BUILD_BUG_ON(sizeof(struct cmd_type_7) != 64);
7267 BUILD_BUG_ON(sizeof(struct cmd_type_7_fx00) != 64);
7268 BUILD_BUG_ON(sizeof(struct cmd_type_crc_2) != 64);
7269 BUILD_BUG_ON(sizeof(struct ct_entry_24xx) != 64);
7270 BUILD_BUG_ON(sizeof(struct ctio_crc2_to_fw) != 64);
7271 BUILD_BUG_ON(sizeof(struct els_entry_24xx) != 64);
7272 BUILD_BUG_ON(sizeof(struct fxdisc_entry_fx00) != 64);
7273 BUILD_BUG_ON(sizeof(struct init_cb_24xx) != 128);
7274 BUILD_BUG_ON(sizeof(struct init_cb_81xx) != 128);
7275 BUILD_BUG_ON(sizeof(struct pt_ls4_request) != 64);
7276 BUILD_BUG_ON(sizeof(struct sns_cmd_pkt) != 2064);
7277 BUILD_BUG_ON(sizeof(struct verify_chip_entry_84xx) != 64);
7278 BUILD_BUG_ON(sizeof(struct vf_evfp_entry_24xx) != 56);
7279
1da177e4 7280 /* Allocate cache for SRBs. */
354d6b21 7281 srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0,
20c2df83 7282 SLAB_HWCACHE_ALIGN, NULL);
1da177e4 7283 if (srb_cachep == NULL) {
7c3df132
SK		 7284 ql_log(ql_log_fatal, NULL, 0x0001,
7285 "Unable to allocate SRB cache...Failing load!.\n");
1da177e4
LT		 7286 return -ENOMEM;
7287 }
7288
2d70c103
NB		 7289 /* Initialize target kmem_cache and mem_pools */
7290 ret = qlt_init();
7291 if (ret < 0) {
c794d24e 7292 goto destroy_cache;
2d70c103
NB		 7293 } else if (ret > 0) {
7294 /*
7295 * If initiator mode is explictly disabled by qlt_init(),
7296 * prevent scsi_transport_fc.c:fc_scsi_scan_rport() from
7297 * performing scsi_scan_target() during LOOP UP event.
7298 */
7299 qla2xxx_transport_functions.disable_target_scan = 1;
7300 qla2xxx_transport_vport_functions.disable_target_scan = 1;
7301 }
7302
1da177e4
LT		 7303 /* Derive version string. */
7304 strcpy(qla2x00_version_str, QLA2XXX_VERSION);
11010fec 7305 if (ql2xextended_error_logging)
0181944f 7306 strcat(qla2x00_version_str, "-debug");
fed0f68a
JC		 7307 if (ql2xextended_error_logging == 1)
7308 ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK;
0181944f 7309
0645cb83
QT		 7310 if (ql2x_ini_mode == QLA2XXX_INI_MODE_DUAL)
7311 qla_insert_tgt_attrs();
7312
1c97a12a
AV		 7313 qla2xxx_transport_template =
7314 fc_attach_transport(&qla2xxx_transport_functions);
2c3dfe3f 7315 if (!qla2xxx_transport_template) {
7c3df132
SK		 7316 ql_log(ql_log_fatal, NULL, 0x0002,
7317 "fc_attach_transport failed...Failing load!.\n");
c794d24e
BVA		 7318 ret = -ENODEV;
7319 goto qlt_exit;
2c3dfe3f 7320 }
6a03b4cd
HZ		 7321
7322 apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops);
7323 if (apidev_major < 0) {
7c3df132
SK		 7324 ql_log(ql_log_fatal, NULL, 0x0003,
7325 "Unable to register char device %s.\n", QLA2XXX_APIDEV);
6a03b4cd
HZ		 7326 }
7327
2c3dfe3f
SJ		 7328 qla2xxx_transport_vport_template =
7329 fc_attach_transport(&qla2xxx_transport_vport_functions);
7330 if (!qla2xxx_transport_vport_template) {
7c3df132
SK		 7331 ql_log(ql_log_fatal, NULL, 0x0004,
7332 "fc_attach_transport vport failed...Failing load!.\n");
c794d24e
BVA		 7333 ret = -ENODEV;
7334 goto unreg_chrdev;
2c3dfe3f 7335 }
7c3df132
SK		 7336 ql_log(ql_log_info, NULL, 0x0005,
7337 "QLogic Fibre Channel HBA Driver: %s.\n",
fd9a29f0 7338 qla2x00_version_str);
7ee61397 7339 ret = pci_register_driver(&qla2xxx_pci_driver);
fca29703 7340 if (ret) {
7c3df132
SK		 7341 ql_log(ql_log_fatal, NULL, 0x0006,
7342 "pci_register_driver failed...ret=%d Failing load!.\n",
7343 ret);
c794d24e 7344 goto release_vport_transport;
fca29703
AV		 7345 }
7346 return ret;
c794d24e
BVA		 7347
7348release_vport_transport:
7349 fc_release_transport(qla2xxx_transport_vport_template);
7350
7351unreg_chrdev:
7352 if (apidev_major >= 0)
7353 unregister_chrdev(apidev_major, QLA2XXX_APIDEV);
7354 fc_release_transport(qla2xxx_transport_template);
7355
7356qlt_exit:
7357 qlt_exit();
7358
7359destroy_cache:
7360 kmem_cache_destroy(srb_cachep);
7361 return ret;
1da177e4
LT		 7362}
7363
7364/**
7365 * qla2x00_module_exit - Module cleanup.
7366 **/
7367static void __exit
7368qla2x00_module_exit(void)
7369{
7ee61397 7370 pci_unregister_driver(&qla2xxx_pci_driver);
5433383e 7371 qla2x00_release_firmware();
75c1d48a 7372 kmem_cache_destroy(ctx_cachep);
2c3dfe3f 7373 fc_release_transport(qla2xxx_transport_vport_template);
59c209a6
BVA		 7374 if (apidev_major >= 0)
7375 unregister_chrdev(apidev_major, QLA2XXX_APIDEV);
7376 fc_release_transport(qla2xxx_transport_template);
7377 qlt_exit();
7378 kmem_cache_destroy(srb_cachep);
1da177e4
LT		 7379}
7380
7381module_init(qla2x00_module_init);
7382module_exit(qla2x00_module_exit);
7383
7384MODULE_AUTHOR("QLogic Corporation");
7385MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver");
7386MODULE_LICENSE("GPL");
7387MODULE_VERSION(QLA2XXX_VERSION);
bb8ee499
AV		 7388MODULE_FIRMWARE(FW_FILE_ISP21XX);
7389MODULE_FIRMWARE(FW_FILE_ISP22XX);
7390MODULE_FIRMWARE(FW_FILE_ISP2300);
7391MODULE_FIRMWARE(FW_FILE_ISP2322);
7392MODULE_FIRMWARE(FW_FILE_ISP24XX);
61623fc3 7393MODULE_FIRMWARE(FW_FILE_ISP25XX);
Linux 6.x block layer and io_uring tree(s)