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[SCSI] qla2xxx: Don't consider the drivers knocked out of IDC participation for futur...
[linux-2.6-block.git] / drivers / scsi / qla2xxx / qla_os.c
CommitLineData
1da177e4 1/*
fa90c54f 2 * QLogic Fibre Channel HBA Driver
1e63395c 3 * Copyright (c) 2003-2013 QLogic Corporation
1da177e4 4 *
fa90c54f 5 * See LICENSE.qla2xxx for copyright and licensing details.
1da177e4
LT		 6 */
7#include "qla_def.h"
8
9#include <linux/moduleparam.h>
10#include <linux/vmalloc.h>
1da177e4 11#include <linux/delay.h>
39a11240 12#include <linux/kthread.h>
e1e82b6f 13#include <linux/mutex.h>
3420d36c 14#include <linux/kobject.h>
5a0e3ad6 15#include <linux/slab.h>
1da177e4
LT		 16#include <scsi/scsi_tcq.h>
17#include <scsi/scsicam.h>
18#include <scsi/scsi_transport.h>
19#include <scsi/scsi_transport_fc.h>
20
2d70c103
NB		 21#include "qla_target.h"
22
1da177e4
LT		 23/*
24 * Driver version
25 */
26char qla2x00_version_str[40];
27
6a03b4cd
HZ		 28static int apidev_major;
29
1da177e4
LT		 30/*
31 * SRB allocation cache
32 */
e18b890b 33static struct kmem_cache *srb_cachep;
1da177e4 34
a9083016
GM		 35/*
36 * CT6 CTX allocation cache
37 */
38static struct kmem_cache *ctx_cachep;
3ce8866c
SK		 39/*
40 * error level for logging
41 */
42int ql_errlev = ql_log_all;
a9083016 43
fa492630 44static int ql2xenableclass2;
2d70c103
NB		 45module_param(ql2xenableclass2, int, S_IRUGO|S_IRUSR);
46MODULE_PARM_DESC(ql2xenableclass2,
47 "Specify if Class 2 operations are supported from the very "
48 "beginning. Default is 0 - class 2 not supported.");
49
8ae6d9c7 50
1da177e4 51int ql2xlogintimeout = 20;
f2019cb1 52module_param(ql2xlogintimeout, int, S_IRUGO);
1da177e4
LT		 53MODULE_PARM_DESC(ql2xlogintimeout,
54 "Login timeout value in seconds.");
55
a7b61842 56int qlport_down_retry;
f2019cb1 57module_param(qlport_down_retry, int, S_IRUGO);
1da177e4 58MODULE_PARM_DESC(qlport_down_retry,
900d9f98 59 "Maximum number of command retries to a port that returns "
1da177e4
LT		 60 "a PORT-DOWN status.");
61
1da177e4
LT		 62int ql2xplogiabsentdevice;
63module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR);
64MODULE_PARM_DESC(ql2xplogiabsentdevice,
65 "Option to enable PLOGI to devices that are not present after "
900d9f98 66 "a Fabric scan. This is needed for several broken switches. "
1da177e4
LT		 67 "Default is 0 - no PLOGI. 1 - perfom PLOGI.");
68
1da177e4 69int ql2xloginretrycount = 0;
f2019cb1 70module_param(ql2xloginretrycount, int, S_IRUGO);
1da177e4
LT		 71MODULE_PARM_DESC(ql2xloginretrycount,
72 "Specify an alternate value for the NVRAM login retry count.");
73
a7a167bf 74int ql2xallocfwdump = 1;
f2019cb1 75module_param(ql2xallocfwdump, int, S_IRUGO);
a7a167bf
AV		 76MODULE_PARM_DESC(ql2xallocfwdump,
77 "Option to enable allocation of memory for a firmware dump "
78 "during HBA initialization. Memory allocation requirements "
79 "vary by ISP type. Default is 1 - allocate memory.");
80
11010fec 81int ql2xextended_error_logging;
27d94035 82module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
11010fec 83MODULE_PARM_DESC(ql2xextended_error_logging,
3ce8866c
SK		 84 "Option to enable extended error logging,\n"
85 "\t\tDefault is 0 - no logging. 0x40000000 - Module Init & Probe.\n"
86 "\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n"
87 "\t\t0x08000000 - IO tracing. 0x04000000 - DPC Thread.\n"
88 "\t\t0x02000000 - Async events. 0x01000000 - Timer routines.\n"
89 "\t\t0x00800000 - User space. 0x00400000 - Task Management.\n"
90 "\t\t0x00200000 - AER/EEH. 0x00100000 - Multi Q.\n"
91 "\t\t0x00080000 - P3P Specific. 0x00040000 - Virtual Port.\n"
92 "\t\t0x00020000 - Buffer Dump. 0x00010000 - Misc.\n"
29f9f90c
CD		 93 "\t\t0x00008000 - Verbose. 0x00004000 - Target.\n"
94 "\t\t0x00002000 - Target Mgmt. 0x00001000 - Target TMF.\n"
3ce8866c 95 "\t\t0x7fffffff - For enabling all logs, can be too many logs.\n"
cfb0919c
CD		 96 "\t\t0x1e400000 - Preferred value for capturing essential "
97 "debug information (equivalent to old "
98 "ql2xextended_error_logging=1).\n"
3ce8866c 99 "\t\tDo LOGICAL OR of the value to enable more than one level");
0181944f 100
a9083016 101int ql2xshiftctondsd = 6;
f2019cb1 102module_param(ql2xshiftctondsd, int, S_IRUGO);
a9083016
GM		 103MODULE_PARM_DESC(ql2xshiftctondsd,
104 "Set to control shifting of command type processing "
105 "based on total number of SG elements.");
106
7e47e5ca 107int ql2xfdmienable=1;
f2019cb1 108module_param(ql2xfdmienable, int, S_IRUGO);
cca5335c 109MODULE_PARM_DESC(ql2xfdmienable,
7794a5af
FW		 110 "Enables FDMI registrations. "
111 "0 - no FDMI. Default is 1 - perform FDMI.");
cca5335c 112
3c290d0b 113int ql2xmaxqdepth = MAX_Q_DEPTH;
df7baa50
AV		 114module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR);
115MODULE_PARM_DESC(ql2xmaxqdepth,
e92e4a8f
CD		 116 "Maximum queue depth to set for each LUN. "
117 "Default is 32.");
df7baa50 118
9e522cd8
AE		 119int ql2xenabledif = 2;
120module_param(ql2xenabledif, int, S_IRUGO);
bad75002
AE		 121MODULE_PARM_DESC(ql2xenabledif,
122 " Enable T10-CRC-DIF "
8cb2049c
AE		 123 " Default is 0 - No DIF Support. 1 - Enable it"
124 ", 2 - Enable DIF for all types, except Type 0.");
bad75002 125
8cb2049c 126int ql2xenablehba_err_chk = 2;
bad75002
AE		 127module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR);
128MODULE_PARM_DESC(ql2xenablehba_err_chk,
8cb2049c
AE		 129 " Enable T10-CRC-DIF Error isolation by HBA:\n"
130 " Default is 1.\n"
131 " 0 -- Error isolation disabled\n"
132 " 1 -- Error isolation enabled only for DIX Type 0\n"
133 " 2 -- Error isolation enabled for all Types\n");
bad75002 134
e5896bd5 135int ql2xiidmaenable=1;
f2019cb1 136module_param(ql2xiidmaenable, int, S_IRUGO);
e5896bd5
AV		 137MODULE_PARM_DESC(ql2xiidmaenable,
138 "Enables iIDMA settings "
139 "Default is 1 - perform iIDMA. 0 - no iIDMA.");
140
73208dfd 141int ql2xmaxqueues = 1;
f2019cb1 142module_param(ql2xmaxqueues, int, S_IRUGO);
73208dfd
AC		 143MODULE_PARM_DESC(ql2xmaxqueues,
144 "Enables MQ settings "
ae68230c
JP		 145 "Default is 1 for single queue. Set it to number "
146 "of queues in MQ mode.");
68ca949c
AC		 147
148int ql2xmultique_tag;
f2019cb1 149module_param(ql2xmultique_tag, int, S_IRUGO);
68ca949c
AC		 150MODULE_PARM_DESC(ql2xmultique_tag,
151 "Enables CPU affinity settings for the driver "
152 "Default is 0 for no affinity of request and response IO. "
153 "Set it to 1 to turn on the cpu affinity.");
e337d907
AV		 154
155int ql2xfwloadbin;
86e45bf6 156module_param(ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
e337d907 157MODULE_PARM_DESC(ql2xfwloadbin,
7c3df132
SK		 158 "Option to specify location from which to load ISP firmware:.\n"
159 " 2 -- load firmware via the request_firmware() (hotplug).\n"
e337d907
AV		 160 " interface.\n"
161 " 1 -- load firmware from flash.\n"
162 " 0 -- use default semantics.\n");
163
ae97c91e 164int ql2xetsenable;
f2019cb1 165module_param(ql2xetsenable, int, S_IRUGO);
ae97c91e
AV		 166MODULE_PARM_DESC(ql2xetsenable,
167 "Enables firmware ETS burst."
168 "Default is 0 - skip ETS enablement.");
169
6907869d 170int ql2xdbwr = 1;
86e45bf6 171module_param(ql2xdbwr, int, S_IRUGO|S_IWUSR);
a9083016 172MODULE_PARM_DESC(ql2xdbwr,
08de2844
GM		 173 "Option to specify scheme for request queue posting.\n"
174 " 0 -- Regular doorbell.\n"
175 " 1 -- CAMRAM doorbell (faster).\n");
a9083016 176
f4c496c1 177int ql2xtargetreset = 1;
f2019cb1 178module_param(ql2xtargetreset, int, S_IRUGO);
f4c496c1
GM		 179MODULE_PARM_DESC(ql2xtargetreset,
180 "Enable target reset."
181 "Default is 1 - use hw defaults.");
182
4da26e16 183int ql2xgffidenable;
f2019cb1 184module_param(ql2xgffidenable, int, S_IRUGO);
4da26e16
CD		 185MODULE_PARM_DESC(ql2xgffidenable,
186 "Enables GFF_ID checks of port type. "
187 "Default is 0 - Do not use GFF_ID information.");
a9083016 188
3822263e 189int ql2xasynctmfenable;
f2019cb1 190module_param(ql2xasynctmfenable, int, S_IRUGO);
3822263e
MI		 191MODULE_PARM_DESC(ql2xasynctmfenable,
192 "Enables issue of TM IOCBs asynchronously via IOCB mechanism"
193 "Default is 0 - Issue TM IOCBs via mailbox mechanism.");
ed0de87c
GM		 194
195int ql2xdontresethba;
86e45bf6 196module_param(ql2xdontresethba, int, S_IRUGO|S_IWUSR);
ed0de87c 197MODULE_PARM_DESC(ql2xdontresethba,
08de2844
GM		 198 "Option to specify reset behaviour.\n"
199 " 0 (Default) -- Reset on failure.\n"
200 " 1 -- Do not reset on failure.\n");
ed0de87c 201
82515920
AV		 202uint ql2xmaxlun = MAX_LUNS;
203module_param(ql2xmaxlun, uint, S_IRUGO);
204MODULE_PARM_DESC(ql2xmaxlun,
205 "Defines the maximum LU number to register with the SCSI "
206 "midlayer. Default is 65535.");
207
08de2844
GM		 208int ql2xmdcapmask = 0x1F;
209module_param(ql2xmdcapmask, int, S_IRUGO);
210MODULE_PARM_DESC(ql2xmdcapmask,
211 "Set the Minidump driver capture mask level. "
6e96fa7b 212 "Default is 0x1F - Can be set to 0x3, 0x7, 0xF, 0x1F, 0x7F.");
08de2844 213
3aadff35 214int ql2xmdenable = 1;
08de2844
GM		 215module_param(ql2xmdenable, int, S_IRUGO);
216MODULE_PARM_DESC(ql2xmdenable,
217 "Enable/disable MiniDump. "
3aadff35
GM		 218 "0 - MiniDump disabled. "
219 "1 (Default) - MiniDump enabled.");
08de2844 220
1da177e4 221/*
fa2a1ce5 222 * SCSI host template entry points
1da177e4
LT		 223 */
224static int qla2xxx_slave_configure(struct scsi_device * device);
f4f051eb 225static int qla2xxx_slave_alloc(struct scsi_device *);
1e99e33a
AV		 226static int qla2xxx_scan_finished(struct Scsi_Host *, unsigned long time);
227static void qla2xxx_scan_start(struct Scsi_Host *);
f4f051eb 228static void qla2xxx_slave_destroy(struct scsi_device *);
f281233d 229static int qla2xxx_queuecommand(struct Scsi_Host *h, struct scsi_cmnd *cmd);
1da177e4
LT		 230static int qla2xxx_eh_abort(struct scsi_cmnd *);
231static int qla2xxx_eh_device_reset(struct scsi_cmnd *);
523ec773 232static int qla2xxx_eh_target_reset(struct scsi_cmnd *);
1da177e4
LT		 233static int qla2xxx_eh_bus_reset(struct scsi_cmnd *);
234static int qla2xxx_eh_host_reset(struct scsi_cmnd *);
1da177e4 235
e881a172 236static int qla2x00_change_queue_depth(struct scsi_device *, int, int);
ce7e4af7 237static int qla2x00_change_queue_type(struct scsi_device *, int);
3491255e 238static void qla2x00_free_device(scsi_qla_host_t *);
ce7e4af7 239
a5326f86 240struct scsi_host_template qla2xxx_driver_template = {
1da177e4 241 .module = THIS_MODULE,
cb63067a 242 .name = QLA2XXX_DRIVER_NAME,
a5326f86 243 .queuecommand = qla2xxx_queuecommand,
fca29703
AV		 244
245 .eh_abort_handler = qla2xxx_eh_abort,
246 .eh_device_reset_handler = qla2xxx_eh_device_reset,
523ec773 247 .eh_target_reset_handler = qla2xxx_eh_target_reset,
fca29703
AV		 248 .eh_bus_reset_handler = qla2xxx_eh_bus_reset,
249 .eh_host_reset_handler = qla2xxx_eh_host_reset,
250
251 .slave_configure = qla2xxx_slave_configure,
252
253 .slave_alloc = qla2xxx_slave_alloc,
254 .slave_destroy = qla2xxx_slave_destroy,
ed677086
AV		 255 .scan_finished = qla2xxx_scan_finished,
256 .scan_start = qla2xxx_scan_start,
ce7e4af7
AV		 257 .change_queue_depth = qla2x00_change_queue_depth,
258 .change_queue_type = qla2x00_change_queue_type,
fca29703
AV		 259 .this_id = -1,
260 .cmd_per_lun = 3,
261 .use_clustering = ENABLE_CLUSTERING,
262 .sg_tablesize = SG_ALL,
263
264 .max_sectors = 0xFFFF,
afb046e2 265 .shost_attrs = qla2x00_host_attrs,
2d70c103
NB		 266
267 .supported_mode = MODE_INITIATOR,
fca29703
AV		 268};
269
1da177e4 270static struct scsi_transport_template *qla2xxx_transport_template = NULL;
2c3dfe3f 271struct scsi_transport_template *qla2xxx_transport_vport_template = NULL;
1da177e4 272
1da177e4
LT		 273/* TODO Convert to inlines
274 *
275 * Timer routines
276 */
1da177e4 277
2c3dfe3f 278__inline__ void
e315cd28 279qla2x00_start_timer(scsi_qla_host_t *vha, void *func, unsigned long interval)
1da177e4 280{
e315cd28
AC		 281 init_timer(&vha->timer);
282 vha->timer.expires = jiffies + interval * HZ;
283 vha->timer.data = (unsigned long)vha;
284 vha->timer.function = (void (*)(unsigned long))func;
285 add_timer(&vha->timer);
286 vha->timer_active = 1;
1da177e4
LT		 287}
288
289static inline void
e315cd28 290qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval)
1da177e4 291{
a9083016 292 /* Currently used for 82XX only. */
7c3df132
SK		 293 if (vha->device_flags & DFLG_DEV_FAILED) {
294 ql_dbg(ql_dbg_timer, vha, 0x600d,
295 "Device in a failed state, returning.\n");
a9083016 296 return;
7c3df132 297 }
a9083016 298
e315cd28 299 mod_timer(&vha->timer, jiffies + interval * HZ);
1da177e4
LT		 300}
301
a824ebb3 302static __inline__ void
e315cd28 303qla2x00_stop_timer(scsi_qla_host_t *vha)
1da177e4 304{
e315cd28
AC		 305 del_timer_sync(&vha->timer);
306 vha->timer_active = 0;
1da177e4
LT		 307}
308
1da177e4
LT		 309static int qla2x00_do_dpc(void *data);
310
311static void qla2x00_rst_aen(scsi_qla_host_t *);
312
73208dfd
AC		 313static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t,
314 struct req_que **, struct rsp_que **);
e30d1756 315static void qla2x00_free_fw_dump(struct qla_hw_data *);
e315cd28 316static void qla2x00_mem_free(struct qla_hw_data *);
1da177e4 317
1da177e4 318/* -------------------------------------------------------------------------- */
9a347ff4
CD		 319static int qla2x00_alloc_queues(struct qla_hw_data *ha, struct req_que *req,
320 struct rsp_que *rsp)
73208dfd 321{
7c3df132 322 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2afa19a9 323 ha->req_q_map = kzalloc(sizeof(struct req_que *) * ha->max_req_queues,
73208dfd
AC		 324 GFP_KERNEL);
325 if (!ha->req_q_map) {
7c3df132
SK		 326 ql_log(ql_log_fatal, vha, 0x003b,
327 "Unable to allocate memory for request queue ptrs.\n");
73208dfd
AC		 328 goto fail_req_map;
329 }
330
2afa19a9 331 ha->rsp_q_map = kzalloc(sizeof(struct rsp_que *) * ha->max_rsp_queues,
73208dfd
AC		 332 GFP_KERNEL);
333 if (!ha->rsp_q_map) {
7c3df132
SK		 334 ql_log(ql_log_fatal, vha, 0x003c,
335 "Unable to allocate memory for response queue ptrs.\n");
73208dfd
AC		 336 goto fail_rsp_map;
337 }
9a347ff4
CD		 338 /*
339 * Make sure we record at least the request and response queue zero in
340 * case we need to free them if part of the probe fails.
341 */
342 ha->rsp_q_map[0] = rsp;
343 ha->req_q_map[0] = req;
73208dfd
AC		 344 set_bit(0, ha->rsp_qid_map);
345 set_bit(0, ha->req_qid_map);
346 return 1;
347
348fail_rsp_map:
349 kfree(ha->req_q_map);
350 ha->req_q_map = NULL;
351fail_req_map:
352 return -ENOMEM;
353}
354
2afa19a9 355static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req)
73208dfd 356{
8ae6d9c7
GM		 357 if (IS_QLAFX00(ha)) {
358 if (req && req->ring_fx00)
359 dma_free_coherent(&ha->pdev->dev,
360 (req->length_fx00 + 1) * sizeof(request_t),
361 req->ring_fx00, req->dma_fx00);
362 } else if (req && req->ring)
73208dfd
AC		 363 dma_free_coherent(&ha->pdev->dev,
364 (req->length + 1) * sizeof(request_t),
365 req->ring, req->dma);
366
8d93f550
CD		 367 if (req)
368 kfree(req->outstanding_cmds);
369
73208dfd
AC		 370 kfree(req);
371 req = NULL;
372}
373
2afa19a9
AC		 374static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp)
375{
8ae6d9c7
GM		 376 if (IS_QLAFX00(ha)) {
377 if (rsp && rsp->ring)
378 dma_free_coherent(&ha->pdev->dev,
379 (rsp->length_fx00 + 1) * sizeof(request_t),
380 rsp->ring_fx00, rsp->dma_fx00);
381 } else if (rsp && rsp->ring) {
2afa19a9
AC		 382 dma_free_coherent(&ha->pdev->dev,
383 (rsp->length + 1) * sizeof(response_t),
384 rsp->ring, rsp->dma);
8ae6d9c7 385 }
2afa19a9
AC		 386 kfree(rsp);
387 rsp = NULL;
388}
389
73208dfd
AC		 390static void qla2x00_free_queues(struct qla_hw_data *ha)
391{
392 struct req_que *req;
393 struct rsp_que *rsp;
394 int cnt;
395
2afa19a9 396 for (cnt = 0; cnt < ha->max_req_queues; cnt++) {
73208dfd 397 req = ha->req_q_map[cnt];
2afa19a9 398 qla2x00_free_req_que(ha, req);
73208dfd 399 }
73208dfd
AC		 400 kfree(ha->req_q_map);
401 ha->req_q_map = NULL;
2afa19a9
AC		 402
403 for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) {
404 rsp = ha->rsp_q_map[cnt];
405 qla2x00_free_rsp_que(ha, rsp);
406 }
407 kfree(ha->rsp_q_map);
408 ha->rsp_q_map = NULL;
73208dfd
AC		 409}
410
68ca949c
AC		 411static int qla25xx_setup_mode(struct scsi_qla_host *vha)
412{
413 uint16_t options = 0;
414 int ques, req, ret;
415 struct qla_hw_data *ha = vha->hw;
416
7163ea81 417 if (!(ha->fw_attributes & BIT_6)) {
7c3df132
SK		 418 ql_log(ql_log_warn, vha, 0x00d8,
419 "Firmware is not multi-queue capable.\n");
7163ea81
AC		 420 goto fail;
421 }
68ca949c 422 if (ql2xmultique_tag) {
68ca949c
AC		 423 /* create a request queue for IO */
424 options |= BIT_7;
425 req = qla25xx_create_req_que(ha, options, 0, 0, -1,
426 QLA_DEFAULT_QUE_QOS);
427 if (!req) {
7c3df132
SK		 428 ql_log(ql_log_warn, vha, 0x00e0,
429 "Failed to create request queue.\n");
68ca949c
AC		 430 goto fail;
431 }
278274d5 432 ha->wq = alloc_workqueue("qla2xxx_wq", WQ_MEM_RECLAIM, 1);
68ca949c
AC		 433 vha->req = ha->req_q_map[req];
434 options |= BIT_1;
435 for (ques = 1; ques < ha->max_rsp_queues; ques++) {
436 ret = qla25xx_create_rsp_que(ha, options, 0, 0, req);
437 if (!ret) {
7c3df132
SK		 438 ql_log(ql_log_warn, vha, 0x00e8,
439 "Failed to create response queue.\n");
68ca949c
AC		 440 goto fail2;
441 }
442 }
7163ea81 443 ha->flags.cpu_affinity_enabled = 1;
7c3df132
SK		 444 ql_dbg(ql_dbg_multiq, vha, 0xc007,
445 "CPU affinity mode enalbed, "
446 "no. of response queues:%d no. of request queues:%d.\n",
447 ha->max_rsp_queues, ha->max_req_queues);
448 ql_dbg(ql_dbg_init, vha, 0x00e9,
449 "CPU affinity mode enalbed, "
450 "no. of response queues:%d no. of request queues:%d.\n",
451 ha->max_rsp_queues, ha->max_req_queues);
68ca949c
AC		 452 }
453 return 0;
454fail2:
455 qla25xx_delete_queues(vha);
7163ea81
AC		 456 destroy_workqueue(ha->wq);
457 ha->wq = NULL;
0cd33fcf 458 vha->req = ha->req_q_map[0];
68ca949c
AC		 459fail:
460 ha->mqenable = 0;
7163ea81
AC		 461 kfree(ha->req_q_map);
462 kfree(ha->rsp_q_map);
463 ha->max_req_queues = ha->max_rsp_queues = 1;
68ca949c
AC		 464 return 1;
465}
466
1da177e4 467static char *
e315cd28 468qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str)
1da177e4 469{
e315cd28 470 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 471 static char *pci_bus_modes[] = {
472 "33", "66", "100", "133",
473 };
474 uint16_t pci_bus;
475
476 strcpy(str, "PCI");
477 pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9;
478 if (pci_bus) {
479 strcat(str, "-X (");
480 strcat(str, pci_bus_modes[pci_bus]);
481 } else {
482 pci_bus = (ha->pci_attr & BIT_8) >> 8;
483 strcat(str, " (");
484 strcat(str, pci_bus_modes[pci_bus]);
485 }
486 strcat(str, " MHz)");
487
488 return (str);
489}
490
fca29703 491static char *
e315cd28 492qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str)
fca29703
AV		 493{
494 static char *pci_bus_modes[] = { "33", "66", "100", "133", };
e315cd28 495 struct qla_hw_data *ha = vha->hw;
fca29703 496 uint32_t pci_bus;
fca29703 497
62a276f8 498 if (pci_is_pcie(ha->pdev)) {
fca29703 499 char lwstr[6];
62a276f8 500 uint32_t lstat, lspeed, lwidth;
fca29703 501
62a276f8
BH		 502 pcie_capability_read_dword(ha->pdev, PCI_EXP_LNKCAP, &lstat);
503 lspeed = lstat & PCI_EXP_LNKCAP_SLS;
504 lwidth = (lstat & PCI_EXP_LNKCAP_MLW) >> 4;
fca29703
AV		 505
506 strcpy(str, "PCIe (");
49300af7
SK		 507 switch (lspeed) {
508 case 1:
c87a0d8c 509 strcat(str, "2.5GT/s ");
49300af7
SK		 510 break;
511 case 2:
c87a0d8c 512 strcat(str, "5.0GT/s ");
49300af7
SK		 513 break;
514 case 3:
515 strcat(str, "8.0GT/s ");
516 break;
517 default:
fca29703 518 strcat(str, "<unknown> ");
49300af7
SK		 519 break;
520 }
fca29703
AV		 521 snprintf(lwstr, sizeof(lwstr), "x%d)", lwidth);
522 strcat(str, lwstr);
523
524 return str;
525 }
526
527 strcpy(str, "PCI");
528 pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8;
529 if (pci_bus == 0 || pci_bus == 8) {
530 strcat(str, " (");
531 strcat(str, pci_bus_modes[pci_bus >> 3]);
532 } else {
533 strcat(str, "-X ");
534 if (pci_bus & BIT_2)
535 strcat(str, "Mode 2");
536 else
537 strcat(str, "Mode 1");
538 strcat(str, " (");
539 strcat(str, pci_bus_modes[pci_bus & ~BIT_2]);
540 }
541 strcat(str, " MHz)");
542
543 return str;
544}
545
e5f82ab8 546static char *
e315cd28 547qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str)
1da177e4
LT		 548{
549 char un_str[10];
e315cd28 550 struct qla_hw_data *ha = vha->hw;
fa2a1ce5 551
1da177e4
LT		 552 sprintf(str, "%d.%02d.%02d ", ha->fw_major_version,
553 ha->fw_minor_version,
554 ha->fw_subminor_version);
555
556 if (ha->fw_attributes & BIT_9) {
557 strcat(str, "FLX");
558 return (str);
559 }
560
561 switch (ha->fw_attributes & 0xFF) {
562 case 0x7:
563 strcat(str, "EF");
564 break;
565 case 0x17:
566 strcat(str, "TP");
567 break;
568 case 0x37:
569 strcat(str, "IP");
570 break;
571 case 0x77:
572 strcat(str, "VI");
573 break;
574 default:
575 sprintf(un_str, "(%x)", ha->fw_attributes);
576 strcat(str, un_str);
577 break;
578 }
579 if (ha->fw_attributes & 0x100)
580 strcat(str, "X");
581
582 return (str);
583}
584
e5f82ab8 585static char *
e315cd28 586qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str)
fca29703 587{
e315cd28 588 struct qla_hw_data *ha = vha->hw;
f0883ac6 589
3a03eb79
AV		 590 sprintf(str, "%d.%02d.%02d (%x)", ha->fw_major_version,
591 ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes);
fca29703 592 return str;
fca29703
AV		 593}
594
9ba56b95
GM		 595void
596qla2x00_sp_free_dma(void *vha, void *ptr)
fca29703 597{
9ba56b95
GM		 598 srb_t *sp = (srb_t *)ptr;
599 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
600 struct qla_hw_data *ha = sp->fcport->vha->hw;
601 void *ctx = GET_CMD_CTX_SP(sp);
fca29703 602
9ba56b95
GM		 603 if (sp->flags & SRB_DMA_VALID) {
604 scsi_dma_unmap(cmd);
605 sp->flags &= ~SRB_DMA_VALID;
7c3df132 606 }
fca29703 607
9ba56b95
GM		 608 if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
609 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
610 scsi_prot_sg_count(cmd), cmd->sc_data_direction);
611 sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
612 }
613
614 if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
615 /* List assured to be having elements */
616 qla2x00_clean_dsd_pool(ha, sp);
617 sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
618 }
619
620 if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
621 dma_pool_free(ha->dl_dma_pool, ctx,
622 ((struct crc_context *)ctx)->crc_ctx_dma);
623 sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
624 }
625
626 if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
627 struct ct6_dsd *ctx1 = (struct ct6_dsd *)ctx;
fca29703 628
9ba56b95
GM		 629 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd,
630 ctx1->fcp_cmnd_dma);
631 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list);
632 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt;
633 ha->gbl_dsd_avail += ctx1->dsd_use_cnt;
634 mempool_free(ctx1, ha->ctx_mempool);
635 ctx1 = NULL;
636 }
637
638 CMD_SP(cmd) = NULL;
b00ee7d7 639 qla2x00_rel_sp(sp->fcport->vha, sp);
9ba56b95
GM		 640}
641
14b06808 642static void
9ba56b95
GM		 643qla2x00_sp_compl(void *data, void *ptr, int res)
644{
645 struct qla_hw_data *ha = (struct qla_hw_data *)data;
646 srb_t *sp = (srb_t *)ptr;
647 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
648
649 cmd->result = res;
650
651 if (atomic_read(&sp->ref_count) == 0) {
652 ql_dbg(ql_dbg_io, sp->fcport->vha, 0x3015,
653 "SP reference-count to ZERO -- sp=%p cmd=%p.\n",
654 sp, GET_CMD_SP(sp));
655 if (ql2xextended_error_logging & ql_dbg_io)
656 BUG();
657 return;
658 }
659 if (!atomic_dec_and_test(&sp->ref_count))
660 return;
661
662 qla2x00_sp_free_dma(ha, sp);
663 cmd->scsi_done(cmd);
fca29703
AV		 664}
665
8ae6d9c7
GM		 666/* If we are SP1 here, we need to still take and release the host_lock as SP1
667 * does not have the changes necessary to avoid taking host->host_lock.
668 */
1da177e4 669static int
f5e3e40b 670qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
fca29703 671{
134ae078 672 scsi_qla_host_t *vha = shost_priv(host);
fca29703 673 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
19a7b4ae 674 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
e315cd28
AC		 675 struct qla_hw_data *ha = vha->hw;
676 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
fca29703
AV		 677 srb_t *sp;
678 int rval;
679
85880801 680 if (ha->flags.eeh_busy) {
7c3df132 681 if (ha->flags.pci_channel_io_perm_failure) {
5f28d2d7 682 ql_dbg(ql_dbg_aer, vha, 0x9010,
7c3df132
SK		 683 "PCI Channel IO permanent failure, exiting "
684 "cmd=%p.\n", cmd);
b9b12f73 685 cmd->result = DID_NO_CONNECT << 16;
7c3df132 686 } else {
5f28d2d7 687 ql_dbg(ql_dbg_aer, vha, 0x9011,
7c3df132 688 "EEH_Busy, Requeuing the cmd=%p.\n", cmd);
85880801 689 cmd->result = DID_REQUEUE << 16;
7c3df132 690 }
14e660e6
SJ		 691 goto qc24_fail_command;
692 }
693
19a7b4ae
JSEC		 694 rval = fc_remote_port_chkready(rport);
695 if (rval) {
696 cmd->result = rval;
5f28d2d7 697 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3003,
7c3df132
SK		 698 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
699 cmd, rval);
fca29703
AV		 700 goto qc24_fail_command;
701 }
702
bad75002
AE		 703 if (!vha->flags.difdix_supported &&
704 scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) {
7c3df132
SK		 705 ql_dbg(ql_dbg_io, vha, 0x3004,
706 "DIF Cap not reg, fail DIF capable cmd's:%p.\n",
707 cmd);
bad75002
AE		 708 cmd->result = DID_NO_CONNECT << 16;
709 goto qc24_fail_command;
710 }
aa651be8
CD		 711
712 if (!fcport) {
713 cmd->result = DID_NO_CONNECT << 16;
714 goto qc24_fail_command;
715 }
716
fca29703
AV		 717 if (atomic_read(&fcport->state) != FCS_ONLINE) {
718 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
38170fa8 719 atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
7c3df132
SK		 720 ql_dbg(ql_dbg_io, vha, 0x3005,
721 "Returning DNC, fcport_state=%d loop_state=%d.\n",
722 atomic_read(&fcport->state),
723 atomic_read(&base_vha->loop_state));
fca29703
AV		 724 cmd->result = DID_NO_CONNECT << 16;
725 goto qc24_fail_command;
726 }
7b594131 727 goto qc24_target_busy;
fca29703
AV		 728 }
729
b00ee7d7 730 sp = qla2x00_get_sp(vha, fcport, GFP_ATOMIC);
3c290d0b
CD		 731 if (!sp) {
732 set_bit(HOST_RAMP_DOWN_QUEUE_DEPTH, &vha->dpc_flags);
f5e3e40b 733 goto qc24_host_busy;
3c290d0b 734 }
fca29703 735
9ba56b95
GM		 736 sp->u.scmd.cmd = cmd;
737 sp->type = SRB_SCSI_CMD;
738 atomic_set(&sp->ref_count, 1);
739 CMD_SP(cmd) = (void *)sp;
740 sp->free = qla2x00_sp_free_dma;
741 sp->done = qla2x00_sp_compl;
742
e315cd28 743 rval = ha->isp_ops->start_scsi(sp);
7c3df132 744 if (rval != QLA_SUCCESS) {
53016ed3 745 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3013,
7c3df132 746 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
3c290d0b 747 set_bit(HOST_RAMP_DOWN_QUEUE_DEPTH, &vha->dpc_flags);
fca29703 748 goto qc24_host_busy_free_sp;
7c3df132 749 }
fca29703 750
fca29703
AV		 751 return 0;
752
753qc24_host_busy_free_sp:
9ba56b95 754 qla2x00_sp_free_dma(ha, sp);
fca29703 755
f5e3e40b 756qc24_host_busy:
fca29703
AV		 757 return SCSI_MLQUEUE_HOST_BUSY;
758
7b594131
MC		 759qc24_target_busy:
760 return SCSI_MLQUEUE_TARGET_BUSY;
761
fca29703 762qc24_fail_command:
f5e3e40b 763 cmd->scsi_done(cmd);
fca29703
AV		 764
765 return 0;
766}
767
1da177e4
LT		 768/*
769 * qla2x00_eh_wait_on_command
770 * Waits for the command to be returned by the Firmware for some
771 * max time.
772 *
773 * Input:
1da177e4 774 * cmd = Scsi Command to wait on.
1da177e4
LT		 775 *
776 * Return:
777 * Not Found : 0
778 * Found : 1
779 */
780static int
e315cd28 781qla2x00_eh_wait_on_command(struct scsi_cmnd *cmd)
1da177e4 782{
fe74c71f
AV		 783#define ABORT_POLLING_PERIOD 1000
784#define ABORT_WAIT_ITER ((10 * 1000) / (ABORT_POLLING_PERIOD))
f4f051eb 785 unsigned long wait_iter = ABORT_WAIT_ITER;
85880801
AV		 786 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
787 struct qla_hw_data *ha = vha->hw;
f4f051eb 788 int ret = QLA_SUCCESS;
1da177e4 789
85880801 790 if (unlikely(pci_channel_offline(ha->pdev)) || ha->flags.eeh_busy) {
7c3df132
SK		 791 ql_dbg(ql_dbg_taskm, vha, 0x8005,
792 "Return:eh_wait.\n");
85880801
AV		 793 return ret;
794 }
795
d970432c 796 while (CMD_SP(cmd) && wait_iter--) {
fe74c71f 797 msleep(ABORT_POLLING_PERIOD);
f4f051eb 798 }
799 if (CMD_SP(cmd))
800 ret = QLA_FUNCTION_FAILED;
1da177e4 801
f4f051eb 802 return ret;
1da177e4
LT		 803}
804
805/*
806 * qla2x00_wait_for_hba_online
fa2a1ce5 807 * Wait till the HBA is online after going through
1da177e4
LT		 808 * <= MAX_RETRIES_OF_ISP_ABORT or
809 * finally HBA is disabled ie marked offline
810 *
811 * Input:
812 * ha - pointer to host adapter structure
fa2a1ce5
AV		 813 *
814 * Note:
1da177e4
LT		 815 * Does context switching-Release SPIN_LOCK
816 * (if any) before calling this routine.
817 *
818 * Return:
819 * Success (Adapter is online) : 0
820 * Failed (Adapter is offline/disabled) : 1
821 */
854165f4 822int
e315cd28 823qla2x00_wait_for_hba_online(scsi_qla_host_t *vha)
1da177e4 824{
fca29703
AV		 825 int return_status;
826 unsigned long wait_online;
e315cd28
AC		 827 struct qla_hw_data *ha = vha->hw;
828 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4 829
fa2a1ce5 830 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ);
e315cd28
AC		 831 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
832 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
833 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
834 ha->dpc_active) && time_before(jiffies, wait_online)) {
1da177e4
LT		 835
836 msleep(1000);
837 }
e315cd28 838 if (base_vha->flags.online)
fa2a1ce5 839 return_status = QLA_SUCCESS;
1da177e4
LT		 840 else
841 return_status = QLA_FUNCTION_FAILED;
842
1da177e4
LT		 843 return (return_status);
844}
845
86fbee86
LC		 846/*
847 * qla2x00_wait_for_reset_ready
848 * Wait till the HBA is online after going through
849 * <= MAX_RETRIES_OF_ISP_ABORT or
850 * finally HBA is disabled ie marked offline or flash
851 * operations are in progress.
852 *
853 * Input:
854 * ha - pointer to host adapter structure
855 *
856 * Note:
857 * Does context switching-Release SPIN_LOCK
858 * (if any) before calling this routine.
859 *
860 * Return:
861 * Success (Adapter is online/no flash ops) : 0
862 * Failed (Adapter is offline/disabled/flash ops in progress) : 1
863 */
3dbe756a 864static int
86fbee86
LC		 865qla2x00_wait_for_reset_ready(scsi_qla_host_t *vha)
866{
867 int return_status;
868 unsigned long wait_online;
869 struct qla_hw_data *ha = vha->hw;
870 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
871
872 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ);
873 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
874 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
875 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
876 ha->optrom_state != QLA_SWAITING ||
877 ha->dpc_active) && time_before(jiffies, wait_online))
878 msleep(1000);
879
880 if (base_vha->flags.online && ha->optrom_state == QLA_SWAITING)
881 return_status = QLA_SUCCESS;
882 else
883 return_status = QLA_FUNCTION_FAILED;
884
7c3df132
SK		 885 ql_dbg(ql_dbg_taskm, vha, 0x8019,
886 "%s return status=%d.\n", __func__, return_status);
86fbee86
LC		 887
888 return return_status;
889}
890
2533cf67
LC		 891int
892qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha)
893{
894 int return_status;
895 unsigned long wait_reset;
896 struct qla_hw_data *ha = vha->hw;
897 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
898
899 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ);
900 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
901 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
902 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
903 ha->dpc_active) && time_before(jiffies, wait_reset)) {
904
905 msleep(1000);
906
907 if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) &&
908 ha->flags.chip_reset_done)
909 break;
910 }
911 if (ha->flags.chip_reset_done)
912 return_status = QLA_SUCCESS;
913 else
914 return_status = QLA_FUNCTION_FAILED;
915
916 return return_status;
917}
918
083a469d
GM		 919static void
920sp_get(struct srb *sp)
921{
922 atomic_inc(&sp->ref_count);
923}
924
1da177e4
LT		 925/**************************************************************************
926* qla2xxx_eh_abort
927*
928* Description:
929* The abort function will abort the specified command.
930*
931* Input:
932* cmd = Linux SCSI command packet to be aborted.
933*
934* Returns:
935* Either SUCCESS or FAILED.
936*
937* Note:
2ea00202 938* Only return FAILED if command not returned by firmware.
1da177e4 939**************************************************************************/
e5f82ab8 940static int
1da177e4
LT		 941qla2xxx_eh_abort(struct scsi_cmnd *cmd)
942{
e315cd28 943 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
f4f051eb 944 srb_t *sp;
4e98d3b8 945 int ret;
f4f051eb 946 unsigned int id, lun;
18e144d3 947 unsigned long flags;
2ea00202 948 int wait = 0;
e315cd28 949 struct qla_hw_data *ha = vha->hw;
1da177e4 950
f4f051eb 951 if (!CMD_SP(cmd))
2ea00202 952 return SUCCESS;
1da177e4 953
4e98d3b8
AV		 954 ret = fc_block_scsi_eh(cmd);
955 if (ret != 0)
956 return ret;
957 ret = SUCCESS;
958
f4f051eb 959 id = cmd->device->id;
960 lun = cmd->device->lun;
1da177e4 961
e315cd28 962 spin_lock_irqsave(&ha->hardware_lock, flags);
170babc3
MC		 963 sp = (srb_t *) CMD_SP(cmd);
964 if (!sp) {
965 spin_unlock_irqrestore(&ha->hardware_lock, flags);
966 return SUCCESS;
967 }
1da177e4 968
7c3df132 969 ql_dbg(ql_dbg_taskm, vha, 0x8002,
cfb0919c
CD		 970 "Aborting from RISC nexus=%ld:%d:%d sp=%p cmd=%p\n",
971 vha->host_no, id, lun, sp, cmd);
17d98630 972
170babc3
MC		 973 /* Get a reference to the sp and drop the lock.*/
974 sp_get(sp);
083a469d 975
e315cd28 976 spin_unlock_irqrestore(&ha->hardware_lock, flags);
170babc3 977 if (ha->isp_ops->abort_command(sp)) {
a55aac79 978 ret = FAILED;
7c3df132 979 ql_dbg(ql_dbg_taskm, vha, 0x8003,
cfb0919c 980 "Abort command mbx failed cmd=%p.\n", cmd);
170babc3 981 } else {
7c3df132 982 ql_dbg(ql_dbg_taskm, vha, 0x8004,
cfb0919c 983 "Abort command mbx success cmd=%p.\n", cmd);
170babc3
MC		 984 wait = 1;
985 }
75942064
SK		 986
987 spin_lock_irqsave(&ha->hardware_lock, flags);
9ba56b95 988 sp->done(ha, sp, 0);
75942064 989 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1da177e4 990
bc91ade9
CD		 991 /* Did the command return during mailbox execution? */
992 if (ret == FAILED && !CMD_SP(cmd))
993 ret = SUCCESS;
994
f4f051eb 995 /* Wait for the command to be returned. */
2ea00202 996 if (wait) {
e315cd28 997 if (qla2x00_eh_wait_on_command(cmd) != QLA_SUCCESS) {
7c3df132 998 ql_log(ql_log_warn, vha, 0x8006,
cfb0919c 999 "Abort handler timed out cmd=%p.\n", cmd);
2ea00202 1000 ret = FAILED;
f4f051eb 1001 }
1da177e4 1002 }
1da177e4 1003
7c3df132 1004 ql_log(ql_log_info, vha, 0x801c,
cfb0919c
CD		 1005 "Abort command issued nexus=%ld:%d:%d -- %d %x.\n",
1006 vha->host_no, id, lun, wait, ret);
1da177e4 1007
f4f051eb 1008 return ret;
1009}
1da177e4 1010
4d78c973 1011int
e315cd28 1012qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t,
4d78c973 1013 unsigned int l, enum nexus_wait_type type)
f4f051eb 1014{
17d98630 1015 int cnt, match, status;
18e144d3 1016 unsigned long flags;
e315cd28 1017 struct qla_hw_data *ha = vha->hw;
73208dfd 1018 struct req_que *req;
4d78c973 1019 srb_t *sp;
9ba56b95 1020 struct scsi_cmnd *cmd;
1da177e4 1021
523ec773 1022 status = QLA_SUCCESS;
17d98630 1023
e315cd28 1024 spin_lock_irqsave(&ha->hardware_lock, flags);
67c2e93a 1025 req = vha->req;
17d98630 1026 for (cnt = 1; status == QLA_SUCCESS &&
8d93f550 1027 cnt < req->num_outstanding_cmds; cnt++) {
17d98630
AC		 1028 sp = req->outstanding_cmds[cnt];
1029 if (!sp)
523ec773 1030 continue;
9ba56b95 1031 if (sp->type != SRB_SCSI_CMD)
cf53b069 1032 continue;
17d98630
AC		 1033 if (vha->vp_idx != sp->fcport->vha->vp_idx)
1034 continue;
1035 match = 0;
9ba56b95 1036 cmd = GET_CMD_SP(sp);
17d98630
AC		 1037 switch (type) {
1038 case WAIT_HOST:
1039 match = 1;
1040 break;
1041 case WAIT_TARGET:
9ba56b95 1042 match = cmd->device->id == t;
17d98630
AC		 1043 break;
1044 case WAIT_LUN:
9ba56b95
GM		 1045 match = (cmd->device->id == t &&
1046 cmd->device->lun == l);
17d98630 1047 break;
73208dfd 1048 }
17d98630
AC		 1049 if (!match)
1050 continue;
1051
1052 spin_unlock_irqrestore(&ha->hardware_lock, flags);
9ba56b95 1053 status = qla2x00_eh_wait_on_command(cmd);
17d98630 1054 spin_lock_irqsave(&ha->hardware_lock, flags);
1da177e4 1055 }
e315cd28 1056 spin_unlock_irqrestore(&ha->hardware_lock, flags);
523ec773
AV		 1057
1058 return status;
1da177e4
LT		 1059}
1060
523ec773
AV		 1061static char *reset_errors[] = {
1062 "HBA not online",
1063 "HBA not ready",
1064 "Task management failed",
1065 "Waiting for command completions",
1066};
1da177e4 1067
e5f82ab8 1068static int
523ec773 1069__qla2xxx_eh_generic_reset(char *name, enum nexus_wait_type type,
2afa19a9 1070 struct scsi_cmnd *cmd, int (*do_reset)(struct fc_port *, unsigned int, int))
1da177e4 1071{
e315cd28 1072 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
bdf79621 1073 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
523ec773 1074 int err;
1da177e4 1075
7c3df132 1076 if (!fcport) {
523ec773 1077 return FAILED;
7c3df132 1078 }
1da177e4 1079
4e98d3b8
AV		 1080 err = fc_block_scsi_eh(cmd);
1081 if (err != 0)
1082 return err;
1083
7c3df132 1084 ql_log(ql_log_info, vha, 0x8009,
cfb0919c 1085 "%s RESET ISSUED nexus=%ld:%d:%d cmd=%p.\n", name, vha->host_no,
7c3df132 1086 cmd->device->id, cmd->device->lun, cmd);
1da177e4 1087
523ec773 1088 err = 0;
7c3df132
SK		 1089 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1090 ql_log(ql_log_warn, vha, 0x800a,
1091 "Wait for hba online failed for cmd=%p.\n", cmd);
523ec773 1092 goto eh_reset_failed;
7c3df132 1093 }
523ec773 1094 err = 2;
2afa19a9 1095 if (do_reset(fcport, cmd->device->lun, cmd->request->cpu + 1)
7c3df132
SK		 1096 != QLA_SUCCESS) {
1097 ql_log(ql_log_warn, vha, 0x800c,
1098 "do_reset failed for cmd=%p.\n", cmd);
523ec773 1099 goto eh_reset_failed;
7c3df132 1100 }
523ec773 1101 err = 3;
e315cd28 1102 if (qla2x00_eh_wait_for_pending_commands(vha, cmd->device->id,
7c3df132
SK		 1103 cmd->device->lun, type) != QLA_SUCCESS) {
1104 ql_log(ql_log_warn, vha, 0x800d,
d6a03581 1105 "wait for pending cmds failed for cmd=%p.\n", cmd);
523ec773 1106 goto eh_reset_failed;
7c3df132 1107 }
523ec773 1108
7c3df132 1109 ql_log(ql_log_info, vha, 0x800e,
cfb0919c
CD		 1110 "%s RESET SUCCEEDED nexus:%ld:%d:%d cmd=%p.\n", name,
1111 vha->host_no, cmd->device->id, cmd->device->lun, cmd);
523ec773
AV		 1112
1113 return SUCCESS;
1114
4d78c973 1115eh_reset_failed:
7c3df132 1116 ql_log(ql_log_info, vha, 0x800f,
cfb0919c
CD		 1117 "%s RESET FAILED: %s nexus=%ld:%d:%d cmd=%p.\n", name,
1118 reset_errors[err], vha->host_no, cmd->device->id, cmd->device->lun,
1119 cmd);
523ec773
AV		 1120 return FAILED;
1121}
1da177e4 1122
523ec773
AV		 1123static int
1124qla2xxx_eh_device_reset(struct scsi_cmnd *cmd)
1125{
e315cd28
AC		 1126 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1127 struct qla_hw_data *ha = vha->hw;
1da177e4 1128
523ec773
AV		 1129 return __qla2xxx_eh_generic_reset("DEVICE", WAIT_LUN, cmd,
1130 ha->isp_ops->lun_reset);
1da177e4
LT		 1131}
1132
1da177e4 1133static int
523ec773 1134qla2xxx_eh_target_reset(struct scsi_cmnd *cmd)
1da177e4 1135{
e315cd28
AC		 1136 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1137 struct qla_hw_data *ha = vha->hw;
1da177e4 1138
523ec773
AV		 1139 return __qla2xxx_eh_generic_reset("TARGET", WAIT_TARGET, cmd,
1140 ha->isp_ops->target_reset);
1da177e4
LT		 1141}
1142
1da177e4
LT		 1143/**************************************************************************
1144* qla2xxx_eh_bus_reset
1145*
1146* Description:
1147* The bus reset function will reset the bus and abort any executing
1148* commands.
1149*
1150* Input:
1151* cmd = Linux SCSI command packet of the command that cause the
1152* bus reset.
1153*
1154* Returns:
1155* SUCCESS/FAILURE (defined as macro in scsi.h).
1156*
1157**************************************************************************/
e5f82ab8 1158static int
1da177e4
LT		 1159qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd)
1160{
e315cd28 1161 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
bdf79621 1162 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
2c3dfe3f 1163 int ret = FAILED;
f4f051eb 1164 unsigned int id, lun;
f4f051eb 1165
f4f051eb 1166 id = cmd->device->id;
1167 lun = cmd->device->lun;
1da177e4 1168
7c3df132 1169 if (!fcport) {
f4f051eb 1170 return ret;
7c3df132 1171 }
1da177e4 1172
4e98d3b8
AV		 1173 ret = fc_block_scsi_eh(cmd);
1174 if (ret != 0)
1175 return ret;
1176 ret = FAILED;
1177
7c3df132 1178 ql_log(ql_log_info, vha, 0x8012,
46270afe 1179 "BUS RESET ISSUED nexus=%ld:%d:%d.\n", vha->host_no, id, lun);
1da177e4 1180
e315cd28 1181 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
7c3df132
SK		 1182 ql_log(ql_log_fatal, vha, 0x8013,
1183 "Wait for hba online failed board disabled.\n");
f4f051eb 1184 goto eh_bus_reset_done;
1da177e4
LT		 1185 }
1186
ad537689
SK		 1187 if (qla2x00_loop_reset(vha) == QLA_SUCCESS)
1188 ret = SUCCESS;
1189
f4f051eb 1190 if (ret == FAILED)
1191 goto eh_bus_reset_done;
1da177e4 1192
9a41a62b 1193 /* Flush outstanding commands. */
4d78c973 1194 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) !=
7c3df132
SK		 1195 QLA_SUCCESS) {
1196 ql_log(ql_log_warn, vha, 0x8014,
1197 "Wait for pending commands failed.\n");
9a41a62b 1198 ret = FAILED;
7c3df132 1199 }
1da177e4 1200
f4f051eb 1201eh_bus_reset_done:
7c3df132 1202 ql_log(ql_log_warn, vha, 0x802b,
cfb0919c 1203 "BUS RESET %s nexus=%ld:%d:%d.\n",
d6a03581 1204 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1da177e4 1205
f4f051eb 1206 return ret;
1da177e4
LT		 1207}
1208
1209/**************************************************************************
1210* qla2xxx_eh_host_reset
1211*
1212* Description:
1213* The reset function will reset the Adapter.
1214*
1215* Input:
1216* cmd = Linux SCSI command packet of the command that cause the
1217* adapter reset.
1218*
1219* Returns:
1220* Either SUCCESS or FAILED.
1221*
1222* Note:
1223**************************************************************************/
e5f82ab8 1224static int
1da177e4
LT		 1225qla2xxx_eh_host_reset(struct scsi_cmnd *cmd)
1226{
e315cd28 1227 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
e315cd28 1228 struct qla_hw_data *ha = vha->hw;
2c3dfe3f 1229 int ret = FAILED;
f4f051eb 1230 unsigned int id, lun;
e315cd28 1231 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4 1232
f4f051eb 1233 id = cmd->device->id;
1234 lun = cmd->device->lun;
f4f051eb 1235
7c3df132 1236 ql_log(ql_log_info, vha, 0x8018,
cfb0919c 1237 "ADAPTER RESET ISSUED nexus=%ld:%d:%d.\n", vha->host_no, id, lun);
1da177e4 1238
86fbee86 1239 if (qla2x00_wait_for_reset_ready(vha) != QLA_SUCCESS)
f4f051eb 1240 goto eh_host_reset_lock;
1da177e4 1241
e315cd28
AC		 1242 if (vha != base_vha) {
1243 if (qla2x00_vp_abort_isp(vha))
f4f051eb 1244 goto eh_host_reset_lock;
e315cd28 1245 } else {
7ec0effd 1246 if (IS_P3P_TYPE(vha->hw)) {
a9083016
GM		 1247 if (!qla82xx_fcoe_ctx_reset(vha)) {
1248 /* Ctx reset success */
1249 ret = SUCCESS;
1250 goto eh_host_reset_lock;
1251 }
1252 /* fall thru if ctx reset failed */
1253 }
68ca949c
AC		 1254 if (ha->wq)
1255 flush_workqueue(ha->wq);
1256
e315cd28 1257 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
a9083016 1258 if (ha->isp_ops->abort_isp(base_vha)) {
e315cd28
AC		 1259 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1260 /* failed. schedule dpc to try */
1261 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
1262
7c3df132
SK		 1263 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1264 ql_log(ql_log_warn, vha, 0x802a,
1265 "wait for hba online failed.\n");
e315cd28 1266 goto eh_host_reset_lock;
7c3df132 1267 }
e315cd28
AC		 1268 }
1269 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
fa2a1ce5 1270 }
1da177e4 1271
e315cd28 1272 /* Waiting for command to be returned to OS.*/
4d78c973 1273 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) ==
e315cd28 1274 QLA_SUCCESS)
f4f051eb 1275 ret = SUCCESS;
1da177e4 1276
f4f051eb 1277eh_host_reset_lock:
cfb0919c
CD		 1278 ql_log(ql_log_info, vha, 0x8017,
1279 "ADAPTER RESET %s nexus=%ld:%d:%d.\n",
1280 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1da177e4 1281
f4f051eb 1282 return ret;
1283}
1da177e4
LT		 1284
1285/*
1286* qla2x00_loop_reset
1287* Issue loop reset.
1288*
1289* Input:
1290* ha = adapter block pointer.
1291*
1292* Returns:
1293* 0 = success
1294*/
a4722cf2 1295int
e315cd28 1296qla2x00_loop_reset(scsi_qla_host_t *vha)
1da177e4 1297{
0c8c39af 1298 int ret;
bdf79621 1299 struct fc_port *fcport;
e315cd28 1300 struct qla_hw_data *ha = vha->hw;
1da177e4 1301
5854771e
AB		 1302 if (IS_QLAFX00(ha)) {
1303 return qlafx00_loop_reset(vha);
1304 }
1305
f4c496c1 1306 if (ql2xtargetreset == 1 && ha->flags.enable_target_reset) {
55e5ed27
AV		 1307 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1308 if (fcport->port_type != FCT_TARGET)
1309 continue;
1310
1311 ret = ha->isp_ops->target_reset(fcport, 0, 0);
1312 if (ret != QLA_SUCCESS) {
7c3df132 1313 ql_dbg(ql_dbg_taskm, vha, 0x802c,
5854771e 1314 "Bus Reset failed: Reset=%d "
7c3df132 1315 "d_id=%x.\n", ret, fcport->d_id.b24);
55e5ed27
AV		 1316 }
1317 }
1318 }
1319
8ae6d9c7 1320
6246b8a1 1321 if (ha->flags.enable_lip_full_login && !IS_CNA_CAPABLE(ha)) {
0b7e7c53
AV		 1322 atomic_set(&vha->loop_state, LOOP_DOWN);
1323 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
1324 qla2x00_mark_all_devices_lost(vha, 0);
e315cd28 1325 ret = qla2x00_full_login_lip(vha);
0c8c39af 1326 if (ret != QLA_SUCCESS) {
7c3df132
SK		 1327 ql_dbg(ql_dbg_taskm, vha, 0x802d,
1328 "full_login_lip=%d.\n", ret);
749af3d5 1329 }
0c8c39af
AV		 1330 }
1331
0d6e61bc 1332 if (ha->flags.enable_lip_reset) {
e315cd28 1333 ret = qla2x00_lip_reset(vha);
ad537689 1334 if (ret != QLA_SUCCESS)
7c3df132
SK		 1335 ql_dbg(ql_dbg_taskm, vha, 0x802e,
1336 "lip_reset failed (%d).\n", ret);
1da177e4
LT		 1337 }
1338
1da177e4 1339 /* Issue marker command only when we are going to start the I/O */
e315cd28 1340 vha->marker_needed = 1;
1da177e4 1341
0c8c39af 1342 return QLA_SUCCESS;
1da177e4
LT		 1343}
1344
df4bf0bb 1345void
e315cd28 1346qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res)
df4bf0bb 1347{
73208dfd 1348 int que, cnt;
df4bf0bb
AV		 1349 unsigned long flags;
1350 srb_t *sp;
e315cd28 1351 struct qla_hw_data *ha = vha->hw;
73208dfd 1352 struct req_que *req;
df4bf0bb
AV		 1353
1354 spin_lock_irqsave(&ha->hardware_lock, flags);
2afa19a9 1355 for (que = 0; que < ha->max_req_queues; que++) {
29bdccbe 1356 req = ha->req_q_map[que];
73208dfd
AC		 1357 if (!req)
1358 continue;
8d93f550
CD		 1359 if (!req->outstanding_cmds)
1360 continue;
1361 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) {
73208dfd 1362 sp = req->outstanding_cmds[cnt];
e612d465 1363 if (sp) {
73208dfd 1364 req->outstanding_cmds[cnt] = NULL;
9ba56b95 1365 sp->done(vha, sp, res);
73208dfd 1366 }
df4bf0bb
AV		 1367 }
1368 }
1369 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1370}
1371
f4f051eb 1372static int
1373qla2xxx_slave_alloc(struct scsi_device *sdev)
1da177e4 1374{
bdf79621 1375 struct fc_rport *rport = starget_to_rport(scsi_target(sdev));
1da177e4 1376
19a7b4ae 1377 if (!rport || fc_remote_port_chkready(rport))
f4f051eb 1378 return -ENXIO;
bdf79621 1379
19a7b4ae 1380 sdev->hostdata = *(fc_port_t **)rport->dd_data;
1da177e4 1381
f4f051eb 1382 return 0;
1383}
1da177e4 1384
f4f051eb 1385static int
1386qla2xxx_slave_configure(struct scsi_device *sdev)
1387{
e315cd28 1388 scsi_qla_host_t *vha = shost_priv(sdev->host);
2afa19a9 1389 struct req_que *req = vha->req;
8482e118 1390
9e522cd8
AE		 1391 if (IS_T10_PI_CAPABLE(vha->hw))
1392 blk_queue_update_dma_alignment(sdev->request_queue, 0x7);
1393
f4f051eb 1394 if (sdev->tagged_supported)
73208dfd 1395 scsi_activate_tcq(sdev, req->max_q_depth);
f4f051eb 1396 else
73208dfd 1397 scsi_deactivate_tcq(sdev, req->max_q_depth);
f4f051eb 1398 return 0;
1399}
1da177e4 1400
f4f051eb 1401static void
1402qla2xxx_slave_destroy(struct scsi_device *sdev)
1403{
1404 sdev->hostdata = NULL;
1da177e4
LT		 1405}
1406
c45dd305
GM		 1407static void qla2x00_handle_queue_full(struct scsi_device *sdev, int qdepth)
1408{
1409 fc_port_t *fcport = (struct fc_port *) sdev->hostdata;
1410
1411 if (!scsi_track_queue_full(sdev, qdepth))
1412 return;
1413
7c3df132 1414 ql_dbg(ql_dbg_io, fcport->vha, 0x3029,
cfb0919c
CD		 1415 "Queue depth adjusted-down to %d for nexus=%ld:%d:%d.\n",
1416 sdev->queue_depth, fcport->vha->host_no, sdev->id, sdev->lun);
c45dd305
GM		 1417}
1418
1419static void qla2x00_adjust_sdev_qdepth_up(struct scsi_device *sdev, int qdepth)
1420{
1421 fc_port_t *fcport = sdev->hostdata;
1422 struct scsi_qla_host *vha = fcport->vha;
c45dd305
GM		 1423 struct req_que *req = NULL;
1424
1425 req = vha->req;
1426 if (!req)
1427 return;
1428
1429 if (req->max_q_depth <= sdev->queue_depth || req->max_q_depth < qdepth)
1430 return;
1431
1432 if (sdev->ordered_tags)
1433 scsi_adjust_queue_depth(sdev, MSG_ORDERED_TAG, qdepth);
1434 else
1435 scsi_adjust_queue_depth(sdev, MSG_SIMPLE_TAG, qdepth);
1436
7c3df132 1437 ql_dbg(ql_dbg_io, vha, 0x302a,
cfb0919c
CD		 1438 "Queue depth adjusted-up to %d for nexus=%ld:%d:%d.\n",
1439 sdev->queue_depth, fcport->vha->host_no, sdev->id, sdev->lun);
c45dd305
GM		 1440}
1441
ce7e4af7 1442static int
e881a172 1443qla2x00_change_queue_depth(struct scsi_device *sdev, int qdepth, int reason)
ce7e4af7 1444{
c45dd305
GM		 1445 switch (reason) {
1446 case SCSI_QDEPTH_DEFAULT:
1447 scsi_adjust_queue_depth(sdev, scsi_get_tag_type(sdev), qdepth);
1448 break;
1449 case SCSI_QDEPTH_QFULL:
1450 qla2x00_handle_queue_full(sdev, qdepth);
1451 break;
1452 case SCSI_QDEPTH_RAMP_UP:
1453 qla2x00_adjust_sdev_qdepth_up(sdev, qdepth);
1454 break;
1455 default:
08002af2 1456 return -EOPNOTSUPP;
c45dd305 1457 }
e881a172 1458
ce7e4af7
AV		 1459 return sdev->queue_depth;
1460}
1461
1462static int
1463qla2x00_change_queue_type(struct scsi_device *sdev, int tag_type)
1464{
1465 if (sdev->tagged_supported) {
1466 scsi_set_tag_type(sdev, tag_type);
1467 if (tag_type)
1468 scsi_activate_tcq(sdev, sdev->queue_depth);
1469 else
1470 scsi_deactivate_tcq(sdev, sdev->queue_depth);
1471 } else
1472 tag_type = 0;
1473
1474 return tag_type;
1475}
1476
3c290d0b
CD		 1477static void
1478qla2x00_host_ramp_down_queuedepth(scsi_qla_host_t *vha)
1479{
1480 scsi_qla_host_t *vp;
1481 struct Scsi_Host *shost;
1482 struct scsi_device *sdev;
1483 struct qla_hw_data *ha = vha->hw;
1484 unsigned long flags;
1485
1486 ha->host_last_rampdown_time = jiffies;
1487
1488 if (ha->cfg_lun_q_depth <= vha->host->cmd_per_lun)
1489 return;
1490
1491 if ((ha->cfg_lun_q_depth / 2) < vha->host->cmd_per_lun)
1492 ha->cfg_lun_q_depth = vha->host->cmd_per_lun;
1493 else
1494 ha->cfg_lun_q_depth = ha->cfg_lun_q_depth / 2;
1495
1496 /*
1497 * Geometrically ramp down the queue depth for all devices on this
1498 * adapter
1499 */
1500 spin_lock_irqsave(&ha->vport_slock, flags);
1501 list_for_each_entry(vp, &ha->vp_list, list) {
1502 shost = vp->host;
1503 shost_for_each_device(sdev, shost) {
1504 if (sdev->queue_depth > shost->cmd_per_lun) {
1505 if (sdev->queue_depth < ha->cfg_lun_q_depth)
1506 continue;
353d9449 1507 ql_dbg(ql_dbg_io, vp, 0x3031,
3c290d0b
CD		 1508 "%ld:%d:%d: Ramping down queue depth to %d",
1509 vp->host_no, sdev->id, sdev->lun,
1510 ha->cfg_lun_q_depth);
1511 qla2x00_change_queue_depth(sdev,
1512 ha->cfg_lun_q_depth, SCSI_QDEPTH_DEFAULT);
1513 }
1514 }
1515 }
1516 spin_unlock_irqrestore(&ha->vport_slock, flags);
1517
1518 return;
1519}
1520
1521static void
1522qla2x00_host_ramp_up_queuedepth(scsi_qla_host_t *vha)
1523{
1524 scsi_qla_host_t *vp;
1525 struct Scsi_Host *shost;
1526 struct scsi_device *sdev;
1527 struct qla_hw_data *ha = vha->hw;
1528 unsigned long flags;
1529
1530 ha->host_last_rampup_time = jiffies;
1531 ha->cfg_lun_q_depth++;
1532
1533 /*
1534 * Linearly ramp up the queue depth for all devices on this
1535 * adapter
1536 */
1537 spin_lock_irqsave(&ha->vport_slock, flags);
1538 list_for_each_entry(vp, &ha->vp_list, list) {
1539 shost = vp->host;
1540 shost_for_each_device(sdev, shost) {
1541 if (sdev->queue_depth > ha->cfg_lun_q_depth)
1542 continue;
1543 qla2x00_change_queue_depth(sdev, ha->cfg_lun_q_depth,
1544 SCSI_QDEPTH_RAMP_UP);
1545 }
1546 }
1547 spin_unlock_irqrestore(&ha->vport_slock, flags);
1548
1549 return;
1550}
1551
1da177e4
LT		 1552/**
1553 * qla2x00_config_dma_addressing() - Configure OS DMA addressing method.
1554 * @ha: HA context
1555 *
1556 * At exit, the @ha's flags.enable_64bit_addressing set to indicated
1557 * supported addressing method.
1558 */
1559static void
53303c42 1560qla2x00_config_dma_addressing(struct qla_hw_data *ha)
1da177e4 1561{
7524f9b9 1562 /* Assume a 32bit DMA mask. */
1da177e4 1563 ha->flags.enable_64bit_addressing = 0;
1da177e4 1564
6a35528a 1565 if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) {
7524f9b9
AV		 1566 /* Any upper-dword bits set? */
1567 if (MSD(dma_get_required_mask(&ha->pdev->dev)) &&
6a35528a 1568 !pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(64))) {
7524f9b9 1569 /* Ok, a 64bit DMA mask is applicable. */
1da177e4 1570 ha->flags.enable_64bit_addressing = 1;
fd34f556
AV		 1571 ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64;
1572 ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64;
7524f9b9 1573 return;
1da177e4 1574 }
1da177e4 1575 }
7524f9b9 1576
284901a9
YH		 1577 dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32));
1578 pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(32));
1da177e4
LT		 1579}
1580
fd34f556 1581static void
e315cd28 1582qla2x00_enable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1583{
1584 unsigned long flags = 0;
1585 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1586
1587 spin_lock_irqsave(&ha->hardware_lock, flags);
1588 ha->interrupts_on = 1;
1589 /* enable risc and host interrupts */
1590 WRT_REG_WORD(&reg->ictrl, ICR_EN_INT | ICR_EN_RISC);
1591 RD_REG_WORD(&reg->ictrl);
1592 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1593
1594}
1595
1596static void
e315cd28 1597qla2x00_disable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1598{
1599 unsigned long flags = 0;
1600 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1601
1602 spin_lock_irqsave(&ha->hardware_lock, flags);
1603 ha->interrupts_on = 0;
1604 /* disable risc and host interrupts */
1605 WRT_REG_WORD(&reg->ictrl, 0);
1606 RD_REG_WORD(&reg->ictrl);
1607 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1608}
1609
1610static void
e315cd28 1611qla24xx_enable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1612{
1613 unsigned long flags = 0;
1614 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1615
1616 spin_lock_irqsave(&ha->hardware_lock, flags);
1617 ha->interrupts_on = 1;
1618 WRT_REG_DWORD(&reg->ictrl, ICRX_EN_RISC_INT);
1619 RD_REG_DWORD(&reg->ictrl);
1620 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1621}
1622
1623static void
e315cd28 1624qla24xx_disable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1625{
1626 unsigned long flags = 0;
1627 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1628
124f85e6
AV		 1629 if (IS_NOPOLLING_TYPE(ha))
1630 return;
fd34f556
AV		 1631 spin_lock_irqsave(&ha->hardware_lock, flags);
1632 ha->interrupts_on = 0;
1633 WRT_REG_DWORD(&reg->ictrl, 0);
1634 RD_REG_DWORD(&reg->ictrl);
1635 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1636}
1637
706f457d
GM		 1638static int
1639qla2x00_iospace_config(struct qla_hw_data *ha)
1640{
1641 resource_size_t pio;
1642 uint16_t msix;
1643 int cpus;
1644
706f457d
GM		 1645 if (pci_request_selected_regions(ha->pdev, ha->bars,
1646 QLA2XXX_DRIVER_NAME)) {
1647 ql_log_pci(ql_log_fatal, ha->pdev, 0x0011,
1648 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
1649 pci_name(ha->pdev));
1650 goto iospace_error_exit;
1651 }
1652 if (!(ha->bars & 1))
1653 goto skip_pio;
1654
1655 /* We only need PIO for Flash operations on ISP2312 v2 chips. */
1656 pio = pci_resource_start(ha->pdev, 0);
1657 if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) {
1658 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
1659 ql_log_pci(ql_log_warn, ha->pdev, 0x0012,
1660 "Invalid pci I/O region size (%s).\n",
1661 pci_name(ha->pdev));
1662 pio = 0;
1663 }
1664 } else {
1665 ql_log_pci(ql_log_warn, ha->pdev, 0x0013,
1666 "Region #0 no a PIO resource (%s).\n",
1667 pci_name(ha->pdev));
1668 pio = 0;
1669 }
1670 ha->pio_address = pio;
1671 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014,
1672 "PIO address=%llu.\n",
1673 (unsigned long long)ha->pio_address);
1674
1675skip_pio:
1676 /* Use MMIO operations for all accesses. */
1677 if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) {
1678 ql_log_pci(ql_log_fatal, ha->pdev, 0x0015,
1679 "Region #1 not an MMIO resource (%s), aborting.\n",
1680 pci_name(ha->pdev));
1681 goto iospace_error_exit;
1682 }
1683 if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) {
1684 ql_log_pci(ql_log_fatal, ha->pdev, 0x0016,
1685 "Invalid PCI mem region size (%s), aborting.\n",
1686 pci_name(ha->pdev));
1687 goto iospace_error_exit;
1688 }
1689
1690 ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN);
1691 if (!ha->iobase) {
1692 ql_log_pci(ql_log_fatal, ha->pdev, 0x0017,
1693 "Cannot remap MMIO (%s), aborting.\n",
1694 pci_name(ha->pdev));
1695 goto iospace_error_exit;
1696 }
1697
1698 /* Determine queue resources */
1699 ha->max_req_queues = ha->max_rsp_queues = 1;
1700 if ((ql2xmaxqueues <= 1 && !ql2xmultique_tag) ||
1701 (ql2xmaxqueues > 1 && ql2xmultique_tag) ||
1702 (!IS_QLA25XX(ha) && !IS_QLA81XX(ha)))
1703 goto mqiobase_exit;
1704
1705 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3),
1706 pci_resource_len(ha->pdev, 3));
1707 if (ha->mqiobase) {
1708 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018,
1709 "MQIO Base=%p.\n", ha->mqiobase);
1710 /* Read MSIX vector size of the board */
1711 pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix);
1712 ha->msix_count = msix;
1713 /* Max queues are bounded by available msix vectors */
1714 /* queue 0 uses two msix vectors */
1715 if (ql2xmultique_tag) {
1716 cpus = num_online_cpus();
1717 ha->max_rsp_queues = (ha->msix_count - 1 > cpus) ?
1718 (cpus + 1) : (ha->msix_count - 1);
1719 ha->max_req_queues = 2;
1720 } else if (ql2xmaxqueues > 1) {
1721 ha->max_req_queues = ql2xmaxqueues > QLA_MQ_SIZE ?
1722 QLA_MQ_SIZE : ql2xmaxqueues;
1723 ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc008,
1724 "QoS mode set, max no of request queues:%d.\n",
1725 ha->max_req_queues);
1726 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0019,
1727 "QoS mode set, max no of request queues:%d.\n",
1728 ha->max_req_queues);
1729 }
1730 ql_log_pci(ql_log_info, ha->pdev, 0x001a,
1731 "MSI-X vector count: %d.\n", msix);
1732 } else
1733 ql_log_pci(ql_log_info, ha->pdev, 0x001b,
1734 "BAR 3 not enabled.\n");
1735
1736mqiobase_exit:
1737 ha->msix_count = ha->max_rsp_queues + 1;
1738 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c,
1739 "MSIX Count:%d.\n", ha->msix_count);
1740 return (0);
1741
1742iospace_error_exit:
1743 return (-ENOMEM);
1744}
1745
1746
6246b8a1
GM		 1747static int
1748qla83xx_iospace_config(struct qla_hw_data *ha)
1749{
1750 uint16_t msix;
1751 int cpus;
1752
1753 if (pci_request_selected_regions(ha->pdev, ha->bars,
1754 QLA2XXX_DRIVER_NAME)) {
1755 ql_log_pci(ql_log_fatal, ha->pdev, 0x0117,
1756 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
1757 pci_name(ha->pdev));
1758
1759 goto iospace_error_exit;
1760 }
1761
1762 /* Use MMIO operations for all accesses. */
1763 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) {
1764 ql_log_pci(ql_log_warn, ha->pdev, 0x0118,
1765 "Invalid pci I/O region size (%s).\n",
1766 pci_name(ha->pdev));
1767 goto iospace_error_exit;
1768 }
1769 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
1770 ql_log_pci(ql_log_warn, ha->pdev, 0x0119,
1771 "Invalid PCI mem region size (%s), aborting\n",
1772 pci_name(ha->pdev));
1773 goto iospace_error_exit;
1774 }
1775
1776 ha->iobase = ioremap(pci_resource_start(ha->pdev, 0), MIN_IOBASE_LEN);
1777 if (!ha->iobase) {
1778 ql_log_pci(ql_log_fatal, ha->pdev, 0x011a,
1779 "Cannot remap MMIO (%s), aborting.\n",
1780 pci_name(ha->pdev));
1781 goto iospace_error_exit;
1782 }
1783
1784 /* 64bit PCI BAR - BAR2 will correspoond to region 4 */
1785 /* 83XX 26XX always use MQ type access for queues
1786 * - mbar 2, a.k.a region 4 */
1787 ha->max_req_queues = ha->max_rsp_queues = 1;
1788 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 4),
1789 pci_resource_len(ha->pdev, 4));
1790
1791 if (!ha->mqiobase) {
1792 ql_log_pci(ql_log_fatal, ha->pdev, 0x011d,
1793 "BAR2/region4 not enabled\n");
1794 goto mqiobase_exit;
1795 }
1796
1797 ha->msixbase = ioremap(pci_resource_start(ha->pdev, 2),
1798 pci_resource_len(ha->pdev, 2));
1799 if (ha->msixbase) {
1800 /* Read MSIX vector size of the board */
1801 pci_read_config_word(ha->pdev,
1802 QLA_83XX_PCI_MSIX_CONTROL, &msix);
1803 ha->msix_count = msix;
1804 /* Max queues are bounded by available msix vectors */
1805 /* queue 0 uses two msix vectors */
1806 if (ql2xmultique_tag) {
1807 cpus = num_online_cpus();
1808 ha->max_rsp_queues = (ha->msix_count - 1 > cpus) ?
1809 (cpus + 1) : (ha->msix_count - 1);
1810 ha->max_req_queues = 2;
1811 } else if (ql2xmaxqueues > 1) {
1812 ha->max_req_queues = ql2xmaxqueues > QLA_MQ_SIZE ?
1813 QLA_MQ_SIZE : ql2xmaxqueues;
1814 ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc00c,
1815 "QoS mode set, max no of request queues:%d.\n",
1816 ha->max_req_queues);
1817 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b,
1818 "QoS mode set, max no of request queues:%d.\n",
1819 ha->max_req_queues);
1820 }
1821 ql_log_pci(ql_log_info, ha->pdev, 0x011c,
1822 "MSI-X vector count: %d.\n", msix);
1823 } else
1824 ql_log_pci(ql_log_info, ha->pdev, 0x011e,
1825 "BAR 1 not enabled.\n");
1826
1827mqiobase_exit:
1828 ha->msix_count = ha->max_rsp_queues + 1;
aa230bc5
AE		 1829
1830 qlt_83xx_iospace_config(ha);
1831
6246b8a1
GM		 1832 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011f,
1833 "MSIX Count:%d.\n", ha->msix_count);
1834 return 0;
1835
1836iospace_error_exit:
1837 return -ENOMEM;
1838}
1839
fd34f556
AV		 1840static struct isp_operations qla2100_isp_ops = {
1841 .pci_config = qla2100_pci_config,
1842 .reset_chip = qla2x00_reset_chip,
1843 .chip_diag = qla2x00_chip_diag,
1844 .config_rings = qla2x00_config_rings,
1845 .reset_adapter = qla2x00_reset_adapter,
1846 .nvram_config = qla2x00_nvram_config,
1847 .update_fw_options = qla2x00_update_fw_options,
1848 .load_risc = qla2x00_load_risc,
1849 .pci_info_str = qla2x00_pci_info_str,
1850 .fw_version_str = qla2x00_fw_version_str,
1851 .intr_handler = qla2100_intr_handler,
1852 .enable_intrs = qla2x00_enable_intrs,
1853 .disable_intrs = qla2x00_disable_intrs,
1854 .abort_command = qla2x00_abort_command,
523ec773
AV		 1855 .target_reset = qla2x00_abort_target,
1856 .lun_reset = qla2x00_lun_reset,
fd34f556
AV		 1857 .fabric_login = qla2x00_login_fabric,
1858 .fabric_logout = qla2x00_fabric_logout,
1859 .calc_req_entries = qla2x00_calc_iocbs_32,
1860 .build_iocbs = qla2x00_build_scsi_iocbs_32,
1861 .prep_ms_iocb = qla2x00_prep_ms_iocb,
1862 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
1863 .read_nvram = qla2x00_read_nvram_data,
1864 .write_nvram = qla2x00_write_nvram_data,
1865 .fw_dump = qla2100_fw_dump,
1866 .beacon_on = NULL,
1867 .beacon_off = NULL,
1868 .beacon_blink = NULL,
1869 .read_optrom = qla2x00_read_optrom_data,
1870 .write_optrom = qla2x00_write_optrom_data,
1871 .get_flash_version = qla2x00_get_flash_version,
e315cd28 1872 .start_scsi = qla2x00_start_scsi,
a9083016 1873 .abort_isp = qla2x00_abort_isp,
706f457d 1874 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 1875 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 1876};
1877
1878static struct isp_operations qla2300_isp_ops = {
1879 .pci_config = qla2300_pci_config,
1880 .reset_chip = qla2x00_reset_chip,
1881 .chip_diag = qla2x00_chip_diag,
1882 .config_rings = qla2x00_config_rings,
1883 .reset_adapter = qla2x00_reset_adapter,
1884 .nvram_config = qla2x00_nvram_config,
1885 .update_fw_options = qla2x00_update_fw_options,
1886 .load_risc = qla2x00_load_risc,
1887 .pci_info_str = qla2x00_pci_info_str,
1888 .fw_version_str = qla2x00_fw_version_str,
1889 .intr_handler = qla2300_intr_handler,
1890 .enable_intrs = qla2x00_enable_intrs,
1891 .disable_intrs = qla2x00_disable_intrs,
1892 .abort_command = qla2x00_abort_command,
523ec773
AV		 1893 .target_reset = qla2x00_abort_target,
1894 .lun_reset = qla2x00_lun_reset,
fd34f556
AV		 1895 .fabric_login = qla2x00_login_fabric,
1896 .fabric_logout = qla2x00_fabric_logout,
1897 .calc_req_entries = qla2x00_calc_iocbs_32,
1898 .build_iocbs = qla2x00_build_scsi_iocbs_32,
1899 .prep_ms_iocb = qla2x00_prep_ms_iocb,
1900 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
1901 .read_nvram = qla2x00_read_nvram_data,
1902 .write_nvram = qla2x00_write_nvram_data,
1903 .fw_dump = qla2300_fw_dump,
1904 .beacon_on = qla2x00_beacon_on,
1905 .beacon_off = qla2x00_beacon_off,
1906 .beacon_blink = qla2x00_beacon_blink,
1907 .read_optrom = qla2x00_read_optrom_data,
1908 .write_optrom = qla2x00_write_optrom_data,
1909 .get_flash_version = qla2x00_get_flash_version,
e315cd28 1910 .start_scsi = qla2x00_start_scsi,
a9083016 1911 .abort_isp = qla2x00_abort_isp,
7ec0effd 1912 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 1913 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 1914};
1915
1916static struct isp_operations qla24xx_isp_ops = {
1917 .pci_config = qla24xx_pci_config,
1918 .reset_chip = qla24xx_reset_chip,
1919 .chip_diag = qla24xx_chip_diag,
1920 .config_rings = qla24xx_config_rings,
1921 .reset_adapter = qla24xx_reset_adapter,
1922 .nvram_config = qla24xx_nvram_config,
1923 .update_fw_options = qla24xx_update_fw_options,
1924 .load_risc = qla24xx_load_risc,
1925 .pci_info_str = qla24xx_pci_info_str,
1926 .fw_version_str = qla24xx_fw_version_str,
1927 .intr_handler = qla24xx_intr_handler,
1928 .enable_intrs = qla24xx_enable_intrs,
1929 .disable_intrs = qla24xx_disable_intrs,
1930 .abort_command = qla24xx_abort_command,
523ec773
AV		 1931 .target_reset = qla24xx_abort_target,
1932 .lun_reset = qla24xx_lun_reset,
fd34f556
AV		 1933 .fabric_login = qla24xx_login_fabric,
1934 .fabric_logout = qla24xx_fabric_logout,
1935 .calc_req_entries = NULL,
1936 .build_iocbs = NULL,
1937 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1938 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1939 .read_nvram = qla24xx_read_nvram_data,
1940 .write_nvram = qla24xx_write_nvram_data,
1941 .fw_dump = qla24xx_fw_dump,
1942 .beacon_on = qla24xx_beacon_on,
1943 .beacon_off = qla24xx_beacon_off,
1944 .beacon_blink = qla24xx_beacon_blink,
1945 .read_optrom = qla24xx_read_optrom_data,
1946 .write_optrom = qla24xx_write_optrom_data,
1947 .get_flash_version = qla24xx_get_flash_version,
e315cd28 1948 .start_scsi = qla24xx_start_scsi,
a9083016 1949 .abort_isp = qla2x00_abort_isp,
7ec0effd 1950 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 1951 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 1952};
1953
c3a2f0df
AV		 1954static struct isp_operations qla25xx_isp_ops = {
1955 .pci_config = qla25xx_pci_config,
1956 .reset_chip = qla24xx_reset_chip,
1957 .chip_diag = qla24xx_chip_diag,
1958 .config_rings = qla24xx_config_rings,
1959 .reset_adapter = qla24xx_reset_adapter,
1960 .nvram_config = qla24xx_nvram_config,
1961 .update_fw_options = qla24xx_update_fw_options,
1962 .load_risc = qla24xx_load_risc,
1963 .pci_info_str = qla24xx_pci_info_str,
1964 .fw_version_str = qla24xx_fw_version_str,
1965 .intr_handler = qla24xx_intr_handler,
1966 .enable_intrs = qla24xx_enable_intrs,
1967 .disable_intrs = qla24xx_disable_intrs,
1968 .abort_command = qla24xx_abort_command,
523ec773
AV		 1969 .target_reset = qla24xx_abort_target,
1970 .lun_reset = qla24xx_lun_reset,
c3a2f0df
AV		 1971 .fabric_login = qla24xx_login_fabric,
1972 .fabric_logout = qla24xx_fabric_logout,
1973 .calc_req_entries = NULL,
1974 .build_iocbs = NULL,
1975 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1976 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1977 .read_nvram = qla25xx_read_nvram_data,
1978 .write_nvram = qla25xx_write_nvram_data,
1979 .fw_dump = qla25xx_fw_dump,
1980 .beacon_on = qla24xx_beacon_on,
1981 .beacon_off = qla24xx_beacon_off,
1982 .beacon_blink = qla24xx_beacon_blink,
338c9161 1983 .read_optrom = qla25xx_read_optrom_data,
c3a2f0df
AV		 1984 .write_optrom = qla24xx_write_optrom_data,
1985 .get_flash_version = qla24xx_get_flash_version,
bad75002 1986 .start_scsi = qla24xx_dif_start_scsi,
a9083016 1987 .abort_isp = qla2x00_abort_isp,
7ec0effd 1988 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 1989 .initialize_adapter = qla2x00_initialize_adapter,
c3a2f0df
AV		 1990};
1991
3a03eb79
AV		 1992static struct isp_operations qla81xx_isp_ops = {
1993 .pci_config = qla25xx_pci_config,
1994 .reset_chip = qla24xx_reset_chip,
1995 .chip_diag = qla24xx_chip_diag,
1996 .config_rings = qla24xx_config_rings,
1997 .reset_adapter = qla24xx_reset_adapter,
1998 .nvram_config = qla81xx_nvram_config,
1999 .update_fw_options = qla81xx_update_fw_options,
eaac30be 2000 .load_risc = qla81xx_load_risc,
3a03eb79
AV		 2001 .pci_info_str = qla24xx_pci_info_str,
2002 .fw_version_str = qla24xx_fw_version_str,
2003 .intr_handler = qla24xx_intr_handler,
2004 .enable_intrs = qla24xx_enable_intrs,
2005 .disable_intrs = qla24xx_disable_intrs,
2006 .abort_command = qla24xx_abort_command,
2007 .target_reset = qla24xx_abort_target,
2008 .lun_reset = qla24xx_lun_reset,
2009 .fabric_login = qla24xx_login_fabric,
2010 .fabric_logout = qla24xx_fabric_logout,
2011 .calc_req_entries = NULL,
2012 .build_iocbs = NULL,
2013 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2014 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
3d79038f
AV		 2015 .read_nvram = NULL,
2016 .write_nvram = NULL,
3a03eb79
AV		 2017 .fw_dump = qla81xx_fw_dump,
2018 .beacon_on = qla24xx_beacon_on,
2019 .beacon_off = qla24xx_beacon_off,
6246b8a1 2020 .beacon_blink = qla83xx_beacon_blink,
3a03eb79
AV		 2021 .read_optrom = qla25xx_read_optrom_data,
2022 .write_optrom = qla24xx_write_optrom_data,
2023 .get_flash_version = qla24xx_get_flash_version,
ba77ef53 2024 .start_scsi = qla24xx_dif_start_scsi,
a9083016 2025 .abort_isp = qla2x00_abort_isp,
7ec0effd 2026 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2027 .initialize_adapter = qla2x00_initialize_adapter,
a9083016
GM		 2028};
2029
2030static struct isp_operations qla82xx_isp_ops = {
2031 .pci_config = qla82xx_pci_config,
2032 .reset_chip = qla82xx_reset_chip,
2033 .chip_diag = qla24xx_chip_diag,
2034 .config_rings = qla82xx_config_rings,
2035 .reset_adapter = qla24xx_reset_adapter,
2036 .nvram_config = qla81xx_nvram_config,
2037 .update_fw_options = qla24xx_update_fw_options,
2038 .load_risc = qla82xx_load_risc,
9d55ca66 2039 .pci_info_str = qla24xx_pci_info_str,
a9083016
GM		 2040 .fw_version_str = qla24xx_fw_version_str,
2041 .intr_handler = qla82xx_intr_handler,
2042 .enable_intrs = qla82xx_enable_intrs,
2043 .disable_intrs = qla82xx_disable_intrs,
2044 .abort_command = qla24xx_abort_command,
2045 .target_reset = qla24xx_abort_target,
2046 .lun_reset = qla24xx_lun_reset,
2047 .fabric_login = qla24xx_login_fabric,
2048 .fabric_logout = qla24xx_fabric_logout,
2049 .calc_req_entries = NULL,
2050 .build_iocbs = NULL,
2051 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2052 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2053 .read_nvram = qla24xx_read_nvram_data,
2054 .write_nvram = qla24xx_write_nvram_data,
2055 .fw_dump = qla24xx_fw_dump,
999916dc
SK		 2056 .beacon_on = qla82xx_beacon_on,
2057 .beacon_off = qla82xx_beacon_off,
2058 .beacon_blink = NULL,
a9083016
GM		 2059 .read_optrom = qla82xx_read_optrom_data,
2060 .write_optrom = qla82xx_write_optrom_data,
7ec0effd 2061 .get_flash_version = qla82xx_get_flash_version,
a9083016
GM		 2062 .start_scsi = qla82xx_start_scsi,
2063 .abort_isp = qla82xx_abort_isp,
706f457d 2064 .iospace_config = qla82xx_iospace_config,
8ae6d9c7 2065 .initialize_adapter = qla2x00_initialize_adapter,
3a03eb79
AV		 2066};
2067
7ec0effd
AD		 2068static struct isp_operations qla8044_isp_ops = {
2069 .pci_config = qla82xx_pci_config,
2070 .reset_chip = qla82xx_reset_chip,
2071 .chip_diag = qla24xx_chip_diag,
2072 .config_rings = qla82xx_config_rings,
2073 .reset_adapter = qla24xx_reset_adapter,
2074 .nvram_config = qla81xx_nvram_config,
2075 .update_fw_options = qla24xx_update_fw_options,
2076 .load_risc = qla82xx_load_risc,
2077 .pci_info_str = qla24xx_pci_info_str,
2078 .fw_version_str = qla24xx_fw_version_str,
2079 .intr_handler = qla8044_intr_handler,
2080 .enable_intrs = qla82xx_enable_intrs,
2081 .disable_intrs = qla82xx_disable_intrs,
2082 .abort_command = qla24xx_abort_command,
2083 .target_reset = qla24xx_abort_target,
2084 .lun_reset = qla24xx_lun_reset,
2085 .fabric_login = qla24xx_login_fabric,
2086 .fabric_logout = qla24xx_fabric_logout,
2087 .calc_req_entries = NULL,
2088 .build_iocbs = NULL,
2089 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2090 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2091 .read_nvram = NULL,
2092 .write_nvram = NULL,
2093 .fw_dump = qla24xx_fw_dump,
2094 .beacon_on = qla82xx_beacon_on,
2095 .beacon_off = qla82xx_beacon_off,
2096 .beacon_blink = NULL,
2097 .read_optrom = qla82xx_read_optrom_data,
2098 .write_optrom = qla8044_write_optrom_data,
2099 .get_flash_version = qla82xx_get_flash_version,
2100 .start_scsi = qla82xx_start_scsi,
2101 .abort_isp = qla8044_abort_isp,
2102 .iospace_config = qla82xx_iospace_config,
2103 .initialize_adapter = qla2x00_initialize_adapter,
2104};
2105
6246b8a1
GM		 2106static struct isp_operations qla83xx_isp_ops = {
2107 .pci_config = qla25xx_pci_config,
2108 .reset_chip = qla24xx_reset_chip,
2109 .chip_diag = qla24xx_chip_diag,
2110 .config_rings = qla24xx_config_rings,
2111 .reset_adapter = qla24xx_reset_adapter,
2112 .nvram_config = qla81xx_nvram_config,
2113 .update_fw_options = qla81xx_update_fw_options,
2114 .load_risc = qla81xx_load_risc,
2115 .pci_info_str = qla24xx_pci_info_str,
2116 .fw_version_str = qla24xx_fw_version_str,
2117 .intr_handler = qla24xx_intr_handler,
2118 .enable_intrs = qla24xx_enable_intrs,
2119 .disable_intrs = qla24xx_disable_intrs,
2120 .abort_command = qla24xx_abort_command,
2121 .target_reset = qla24xx_abort_target,
2122 .lun_reset = qla24xx_lun_reset,
2123 .fabric_login = qla24xx_login_fabric,
2124 .fabric_logout = qla24xx_fabric_logout,
2125 .calc_req_entries = NULL,
2126 .build_iocbs = NULL,
2127 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2128 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2129 .read_nvram = NULL,
2130 .write_nvram = NULL,
2131 .fw_dump = qla83xx_fw_dump,
2132 .beacon_on = qla24xx_beacon_on,
2133 .beacon_off = qla24xx_beacon_off,
2134 .beacon_blink = qla83xx_beacon_blink,
2135 .read_optrom = qla25xx_read_optrom_data,
2136 .write_optrom = qla24xx_write_optrom_data,
2137 .get_flash_version = qla24xx_get_flash_version,
2138 .start_scsi = qla24xx_dif_start_scsi,
2139 .abort_isp = qla2x00_abort_isp,
2140 .iospace_config = qla83xx_iospace_config,
8ae6d9c7
GM		 2141 .initialize_adapter = qla2x00_initialize_adapter,
2142};
2143
2144static struct isp_operations qlafx00_isp_ops = {
2145 .pci_config = qlafx00_pci_config,
2146 .reset_chip = qlafx00_soft_reset,
2147 .chip_diag = qlafx00_chip_diag,
2148 .config_rings = qlafx00_config_rings,
2149 .reset_adapter = qlafx00_soft_reset,
2150 .nvram_config = NULL,
2151 .update_fw_options = NULL,
2152 .load_risc = NULL,
2153 .pci_info_str = qlafx00_pci_info_str,
2154 .fw_version_str = qlafx00_fw_version_str,
2155 .intr_handler = qlafx00_intr_handler,
2156 .enable_intrs = qlafx00_enable_intrs,
2157 .disable_intrs = qlafx00_disable_intrs,
2158 .abort_command = qlafx00_abort_command,
2159 .target_reset = qlafx00_abort_target,
2160 .lun_reset = qlafx00_lun_reset,
2161 .fabric_login = NULL,
2162 .fabric_logout = NULL,
2163 .calc_req_entries = NULL,
2164 .build_iocbs = NULL,
2165 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2166 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2167 .read_nvram = qla24xx_read_nvram_data,
2168 .write_nvram = qla24xx_write_nvram_data,
2169 .fw_dump = NULL,
2170 .beacon_on = qla24xx_beacon_on,
2171 .beacon_off = qla24xx_beacon_off,
2172 .beacon_blink = NULL,
2173 .read_optrom = qla24xx_read_optrom_data,
2174 .write_optrom = qla24xx_write_optrom_data,
2175 .get_flash_version = qla24xx_get_flash_version,
2176 .start_scsi = qlafx00_start_scsi,
2177 .abort_isp = qlafx00_abort_isp,
2178 .iospace_config = qlafx00_iospace_config,
2179 .initialize_adapter = qlafx00_initialize_adapter,
6246b8a1
GM		 2180};
2181
ea5b6382 2182static inline void
e315cd28 2183qla2x00_set_isp_flags(struct qla_hw_data *ha)
ea5b6382 2184{
2185 ha->device_type = DT_EXTENDED_IDS;
2186 switch (ha->pdev->device) {
2187 case PCI_DEVICE_ID_QLOGIC_ISP2100:
2188 ha->device_type |= DT_ISP2100;
2189 ha->device_type &= ~DT_EXTENDED_IDS;
441d1072 2190 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
ea5b6382 2191 break;
2192 case PCI_DEVICE_ID_QLOGIC_ISP2200:
2193 ha->device_type |= DT_ISP2200;
2194 ha->device_type &= ~DT_EXTENDED_IDS;
441d1072 2195 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
ea5b6382 2196 break;
2197 case PCI_DEVICE_ID_QLOGIC_ISP2300:
2198 ha->device_type |= DT_ISP2300;
4a59f71d 2199 ha->device_type |= DT_ZIO_SUPPORTED;
441d1072 2200 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 2201 break;
2202 case PCI_DEVICE_ID_QLOGIC_ISP2312:
2203 ha->device_type |= DT_ISP2312;
4a59f71d 2204 ha->device_type |= DT_ZIO_SUPPORTED;
441d1072 2205 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 2206 break;
2207 case PCI_DEVICE_ID_QLOGIC_ISP2322:
2208 ha->device_type |= DT_ISP2322;
4a59f71d 2209 ha->device_type |= DT_ZIO_SUPPORTED;
ea5b6382 2210 if (ha->pdev->subsystem_vendor == 0x1028 &&
2211 ha->pdev->subsystem_device == 0x0170)
2212 ha->device_type |= DT_OEM_001;
441d1072 2213 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 2214 break;
2215 case PCI_DEVICE_ID_QLOGIC_ISP6312:
2216 ha->device_type |= DT_ISP6312;
441d1072 2217 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 2218 break;
2219 case PCI_DEVICE_ID_QLOGIC_ISP6322:
2220 ha->device_type |= DT_ISP6322;
441d1072 2221 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 2222 break;
2223 case PCI_DEVICE_ID_QLOGIC_ISP2422:
2224 ha->device_type |= DT_ISP2422;
4a59f71d 2225 ha->device_type |= DT_ZIO_SUPPORTED;
e428924c 2226 ha->device_type |= DT_FWI2;
c76f2c01 2227 ha->device_type |= DT_IIDMA;
441d1072 2228 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2229 break;
2230 case PCI_DEVICE_ID_QLOGIC_ISP2432:
2231 ha->device_type |= DT_ISP2432;
4a59f71d 2232 ha->device_type |= DT_ZIO_SUPPORTED;
e428924c 2233 ha->device_type |= DT_FWI2;
c76f2c01 2234 ha->device_type |= DT_IIDMA;
441d1072 2235 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2236 break;
4d4df193
HK		 2237 case PCI_DEVICE_ID_QLOGIC_ISP8432:
2238 ha->device_type |= DT_ISP8432;
2239 ha->device_type |= DT_ZIO_SUPPORTED;
2240 ha->device_type |= DT_FWI2;
2241 ha->device_type |= DT_IIDMA;
2242 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2243 break;
044cc6c8 2244 case PCI_DEVICE_ID_QLOGIC_ISP5422:
2245 ha->device_type |= DT_ISP5422;
e428924c 2246 ha->device_type |= DT_FWI2;
441d1072 2247 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2248 break;
044cc6c8 2249 case PCI_DEVICE_ID_QLOGIC_ISP5432:
2250 ha->device_type |= DT_ISP5432;
e428924c 2251 ha->device_type |= DT_FWI2;
441d1072 2252 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2253 break;
c3a2f0df
AV		 2254 case PCI_DEVICE_ID_QLOGIC_ISP2532:
2255 ha->device_type |= DT_ISP2532;
2256 ha->device_type |= DT_ZIO_SUPPORTED;
2257 ha->device_type |= DT_FWI2;
2258 ha->device_type |= DT_IIDMA;
441d1072 2259 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2260 break;
3a03eb79
AV		 2261 case PCI_DEVICE_ID_QLOGIC_ISP8001:
2262 ha->device_type |= DT_ISP8001;
2263 ha->device_type |= DT_ZIO_SUPPORTED;
2264 ha->device_type |= DT_FWI2;
2265 ha->device_type |= DT_IIDMA;
2266 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2267 break;
a9083016
GM		 2268 case PCI_DEVICE_ID_QLOGIC_ISP8021:
2269 ha->device_type |= DT_ISP8021;
2270 ha->device_type |= DT_ZIO_SUPPORTED;
2271 ha->device_type |= DT_FWI2;
2272 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2273 /* Initialize 82XX ISP flags */
2274 qla82xx_init_flags(ha);
2275 break;
7ec0effd
AD		 2276 case PCI_DEVICE_ID_QLOGIC_ISP8044:
2277 ha->device_type |= DT_ISP8044;
2278 ha->device_type |= DT_ZIO_SUPPORTED;
2279 ha->device_type |= DT_FWI2;
2280 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2281 /* Initialize 82XX ISP flags */
2282 qla82xx_init_flags(ha);
2283 break;
6246b8a1
GM		 2284 case PCI_DEVICE_ID_QLOGIC_ISP2031:
2285 ha->device_type |= DT_ISP2031;
2286 ha->device_type |= DT_ZIO_SUPPORTED;
2287 ha->device_type |= DT_FWI2;
2288 ha->device_type |= DT_IIDMA;
2289 ha->device_type |= DT_T10_PI;
2290 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2291 break;
2292 case PCI_DEVICE_ID_QLOGIC_ISP8031:
2293 ha->device_type |= DT_ISP8031;
2294 ha->device_type |= DT_ZIO_SUPPORTED;
2295 ha->device_type |= DT_FWI2;
2296 ha->device_type |= DT_IIDMA;
2297 ha->device_type |= DT_T10_PI;
2298 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2299 break;
8ae6d9c7
GM		 2300 case PCI_DEVICE_ID_QLOGIC_ISPF001:
2301 ha->device_type |= DT_ISPFX00;
2302 break;
ea5b6382 2303 }
e5b68a61 2304
a9083016
GM		 2305 if (IS_QLA82XX(ha))
2306 ha->port_no = !(ha->portnum & 1);
2307 else
2308 /* Get adapter physical port no from interrupt pin register. */
2309 pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no);
2310
e5b68a61
AC		 2311 if (ha->port_no & 1)
2312 ha->flags.port0 = 1;
2313 else
2314 ha->flags.port0 = 0;
7c3df132 2315 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b,
d8424f68 2316 "device_type=0x%x port=%d fw_srisc_address=0x%x.\n",
7c3df132 2317 ha->device_type, ha->flags.port0, ha->fw_srisc_address);
ea5b6382 2318}
2319
1e99e33a
AV		 2320static void
2321qla2xxx_scan_start(struct Scsi_Host *shost)
2322{
e315cd28 2323 scsi_qla_host_t *vha = shost_priv(shost);
1e99e33a 2324
cbc8eb67
AV		 2325 if (vha->hw->flags.running_gold_fw)
2326 return;
2327
e315cd28
AC		 2328 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
2329 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
2330 set_bit(RSCN_UPDATE, &vha->dpc_flags);
2331 set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags);
1e99e33a
AV		 2332}
2333
2334static int
2335qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time)
2336{
e315cd28 2337 scsi_qla_host_t *vha = shost_priv(shost);
1e99e33a 2338
e315cd28 2339 if (!vha->host)
1e99e33a 2340 return 1;
e315cd28 2341 if (time > vha->hw->loop_reset_delay * HZ)
1e99e33a
AV		 2342 return 1;
2343
e315cd28 2344 return atomic_read(&vha->loop_state) == LOOP_READY;
1e99e33a
AV		 2345}
2346
1da177e4
LT		 2347/*
2348 * PCI driver interface
2349 */
6f039790 2350static int
7ee61397 2351qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
1da177e4 2352{
a1541d5a 2353 int ret = -ENODEV;
1da177e4 2354 struct Scsi_Host *host;
e315cd28
AC		 2355 scsi_qla_host_t *base_vha = NULL;
2356 struct qla_hw_data *ha;
29856e28 2357 char pci_info[30];
7d613ac6 2358 char fw_str[30], wq_name[30];
5433383e 2359 struct scsi_host_template *sht;
642ef983 2360 int bars, mem_only = 0;
e315cd28 2361 uint16_t req_length = 0, rsp_length = 0;
73208dfd
AC		 2362 struct req_que *req = NULL;
2363 struct rsp_que *rsp = NULL;
285d0321 2364 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO);
a5326f86 2365 sht = &qla2xxx_driver_template;
5433383e 2366 if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 ||
8bc69e7d 2367 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 ||
4d4df193 2368 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 ||
8bc69e7d 2369 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 ||
c3a2f0df 2370 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 ||
3a03eb79 2371 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 ||
a9083016 2372 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 ||
6246b8a1
GM		 2373 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021 ||
2374 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2031 ||
8ae6d9c7 2375 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8031 ||
7ec0effd
AD		 2376 pdev->device == PCI_DEVICE_ID_QLOGIC_ISPF001 ||
2377 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8044) {
285d0321 2378 bars = pci_select_bars(pdev, IORESOURCE_MEM);
09483916 2379 mem_only = 1;
7c3df132
SK		 2380 ql_dbg_pci(ql_dbg_init, pdev, 0x0007,
2381 "Mem only adapter.\n");
285d0321 2382 }
7c3df132
SK		 2383 ql_dbg_pci(ql_dbg_init, pdev, 0x0008,
2384 "Bars=%d.\n", bars);
285d0321 2385
09483916
BH		 2386 if (mem_only) {
2387 if (pci_enable_device_mem(pdev))
2388 goto probe_out;
2389 } else {
2390 if (pci_enable_device(pdev))
2391 goto probe_out;
2392 }
285d0321 2393
0927678f
JB		 2394 /* This may fail but that's ok */
2395 pci_enable_pcie_error_reporting(pdev);
285d0321 2396
e315cd28
AC		 2397 ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL);
2398 if (!ha) {
7c3df132
SK		 2399 ql_log_pci(ql_log_fatal, pdev, 0x0009,
2400 "Unable to allocate memory for ha.\n");
e315cd28 2401 goto probe_out;
1da177e4 2402 }
7c3df132
SK		 2403 ql_dbg_pci(ql_dbg_init, pdev, 0x000a,
2404 "Memory allocated for ha=%p.\n", ha);
e315cd28 2405 ha->pdev = pdev;
2d70c103 2406 ha->tgt.enable_class_2 = ql2xenableclass2;
1da177e4
LT		 2407
2408 /* Clear our data area */
285d0321 2409 ha->bars = bars;
09483916 2410 ha->mem_only = mem_only;
df4bf0bb 2411 spin_lock_init(&ha->hardware_lock);
339aa70e 2412 spin_lock_init(&ha->vport_slock);
a9b6f722 2413 mutex_init(&ha->selflogin_lock);
1da177e4 2414
ea5b6382 2415 /* Set ISP-type information. */
2416 qla2x00_set_isp_flags(ha);
ca79cf66
DG		 2417
2418 /* Set EEH reset type to fundamental if required by hba */
95676112
JC		 2419 if (IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha) ||
2420 IS_QLA83XX(ha))
ca79cf66 2421 pdev->needs_freset = 1;
ca79cf66 2422
cba1e47f
CD		 2423 ha->prev_topology = 0;
2424 ha->init_cb_size = sizeof(init_cb_t);
2425 ha->link_data_rate = PORT_SPEED_UNKNOWN;
2426 ha->optrom_size = OPTROM_SIZE_2300;
3c290d0b 2427 ha->cfg_lun_q_depth = ql2xmaxqdepth;
cba1e47f 2428
abbd8870 2429 /* Assign ISP specific operations. */
1da177e4 2430 if (IS_QLA2100(ha)) {
642ef983 2431 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
1da177e4 2432 ha->mbx_count = MAILBOX_REGISTER_COUNT_2100;
e315cd28
AC		 2433 req_length = REQUEST_ENTRY_CNT_2100;
2434 rsp_length = RESPONSE_ENTRY_CNT_2100;
2435 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
abbd8870 2436 ha->gid_list_info_size = 4;
3a03eb79
AV		 2437 ha->flash_conf_off = ~0;
2438 ha->flash_data_off = ~0;
2439 ha->nvram_conf_off = ~0;
2440 ha->nvram_data_off = ~0;
fd34f556 2441 ha->isp_ops = &qla2100_isp_ops;
1da177e4 2442 } else if (IS_QLA2200(ha)) {
642ef983 2443 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
67ddda35 2444 ha->mbx_count = MAILBOX_REGISTER_COUNT_2200;
e315cd28
AC		 2445 req_length = REQUEST_ENTRY_CNT_2200;
2446 rsp_length = RESPONSE_ENTRY_CNT_2100;
2447 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
abbd8870 2448 ha->gid_list_info_size = 4;
3a03eb79
AV		 2449 ha->flash_conf_off = ~0;
2450 ha->flash_data_off = ~0;
2451 ha->nvram_conf_off = ~0;
2452 ha->nvram_data_off = ~0;
fd34f556 2453 ha->isp_ops = &qla2100_isp_ops;
fca29703 2454 } else if (IS_QLA23XX(ha)) {
642ef983 2455 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
1da177e4 2456 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2457 req_length = REQUEST_ENTRY_CNT_2200;
2458 rsp_length = RESPONSE_ENTRY_CNT_2300;
2459 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
abbd8870 2460 ha->gid_list_info_size = 6;
854165f4 2461 if (IS_QLA2322(ha) || IS_QLA6322(ha))
2462 ha->optrom_size = OPTROM_SIZE_2322;
3a03eb79
AV		 2463 ha->flash_conf_off = ~0;
2464 ha->flash_data_off = ~0;
2465 ha->nvram_conf_off = ~0;
2466 ha->nvram_data_off = ~0;
fd34f556 2467 ha->isp_ops = &qla2300_isp_ops;
4d4df193 2468 } else if (IS_QLA24XX_TYPE(ha)) {
642ef983 2469 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
fca29703 2470 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2471 req_length = REQUEST_ENTRY_CNT_24XX;
2472 rsp_length = RESPONSE_ENTRY_CNT_2300;
2d70c103 2473 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
e315cd28 2474 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2c3dfe3f 2475 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
fca29703 2476 ha->gid_list_info_size = 8;
854165f4 2477 ha->optrom_size = OPTROM_SIZE_24XX;
73208dfd 2478 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX;
fd34f556 2479 ha->isp_ops = &qla24xx_isp_ops;
3a03eb79
AV		 2480 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2481 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2482 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2483 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
c3a2f0df 2484 } else if (IS_QLA25XX(ha)) {
642ef983 2485 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
c3a2f0df 2486 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2487 req_length = REQUEST_ENTRY_CNT_24XX;
2488 rsp_length = RESPONSE_ENTRY_CNT_2300;
2d70c103 2489 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
e315cd28 2490 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
c3a2f0df 2491 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
c3a2f0df
AV		 2492 ha->gid_list_info_size = 8;
2493 ha->optrom_size = OPTROM_SIZE_25XX;
73208dfd 2494 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
c3a2f0df 2495 ha->isp_ops = &qla25xx_isp_ops;
3a03eb79
AV		 2496 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2497 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2498 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2499 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
2500 } else if (IS_QLA81XX(ha)) {
642ef983 2501 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3a03eb79
AV		 2502 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2503 req_length = REQUEST_ENTRY_CNT_24XX;
2504 rsp_length = RESPONSE_ENTRY_CNT_2300;
aa230bc5 2505 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
3a03eb79
AV		 2506 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2507 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2508 ha->gid_list_info_size = 8;
2509 ha->optrom_size = OPTROM_SIZE_81XX;
40859ae5 2510 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3a03eb79
AV		 2511 ha->isp_ops = &qla81xx_isp_ops;
2512 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2513 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2514 ha->nvram_conf_off = ~0;
2515 ha->nvram_data_off = ~0;
a9083016 2516 } else if (IS_QLA82XX(ha)) {
642ef983 2517 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
a9083016
GM		 2518 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2519 req_length = REQUEST_ENTRY_CNT_82XX;
2520 rsp_length = RESPONSE_ENTRY_CNT_82XX;
2521 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2522 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2523 ha->gid_list_info_size = 8;
2524 ha->optrom_size = OPTROM_SIZE_82XX;
087c621e 2525 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
a9083016
GM		 2526 ha->isp_ops = &qla82xx_isp_ops;
2527 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2528 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2529 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2530 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
7ec0effd
AD		 2531 } else if (IS_QLA8044(ha)) {
2532 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2533 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2534 req_length = REQUEST_ENTRY_CNT_82XX;
2535 rsp_length = RESPONSE_ENTRY_CNT_82XX;
2536 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2537 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2538 ha->gid_list_info_size = 8;
2539 ha->optrom_size = OPTROM_SIZE_83XX;
2540 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2541 ha->isp_ops = &qla8044_isp_ops;
2542 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2543 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2544 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2545 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
6246b8a1 2546 } else if (IS_QLA83XX(ha)) {
7d613ac6 2547 ha->portnum = PCI_FUNC(ha->pdev->devfn);
642ef983 2548 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
6246b8a1
GM		 2549 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2550 req_length = REQUEST_ENTRY_CNT_24XX;
2551 rsp_length = RESPONSE_ENTRY_CNT_2300;
b8aa4bdf 2552 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
6246b8a1
GM		 2553 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2554 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2555 ha->gid_list_info_size = 8;
2556 ha->optrom_size = OPTROM_SIZE_83XX;
2557 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2558 ha->isp_ops = &qla83xx_isp_ops;
2559 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2560 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2561 ha->nvram_conf_off = ~0;
2562 ha->nvram_data_off = ~0;
8ae6d9c7
GM		 2563 } else if (IS_QLAFX00(ha)) {
2564 ha->max_fibre_devices = MAX_FIBRE_DEVICES_FX00;
2565 ha->mbx_count = MAILBOX_REGISTER_COUNT_FX00;
2566 ha->aen_mbx_count = AEN_MAILBOX_REGISTER_COUNT_FX00;
2567 req_length = REQUEST_ENTRY_CNT_FX00;
2568 rsp_length = RESPONSE_ENTRY_CNT_FX00;
2569 ha->init_cb_size = sizeof(struct init_cb_fx);
2570 ha->isp_ops = &qlafx00_isp_ops;
2571 ha->port_down_retry_count = 30; /* default value */
2572 ha->mr.fw_hbt_cnt = QLAFX00_HEARTBEAT_INTERVAL;
2573 ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL;
71e56003 2574 ha->mr.fw_critemp_timer_tick = QLAFX00_CRITEMP_INTERVAL;
8ae6d9c7 2575 ha->mr.fw_hbt_en = 1;
1da177e4 2576 }
6246b8a1 2577
7c3df132
SK		 2578 ql_dbg_pci(ql_dbg_init, pdev, 0x001e,
2579 "mbx_count=%d, req_length=%d, "
2580 "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, "
642ef983
CD		 2581 "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, "
2582 "max_fibre_devices=%d.\n",
7c3df132
SK		 2583 ha->mbx_count, req_length, rsp_length, ha->max_loop_id,
2584 ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size,
642ef983 2585 ha->nvram_npiv_size, ha->max_fibre_devices);
7c3df132
SK		 2586 ql_dbg_pci(ql_dbg_init, pdev, 0x001f,
2587 "isp_ops=%p, flash_conf_off=%d, "
2588 "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n",
2589 ha->isp_ops, ha->flash_conf_off, ha->flash_data_off,
2590 ha->nvram_conf_off, ha->nvram_data_off);
706f457d
GM		 2591
2592 /* Configure PCI I/O space */
2593 ret = ha->isp_ops->iospace_config(ha);
2594 if (ret)
0a63ad12 2595 goto iospace_config_failed;
706f457d
GM		 2596
2597 ql_log_pci(ql_log_info, pdev, 0x001d,
2598 "Found an ISP%04X irq %d iobase 0x%p.\n",
2599 pdev->device, pdev->irq, ha->iobase);
6c2f527c 2600 mutex_init(&ha->vport_lock);
0b05a1f0
MB		 2601 init_completion(&ha->mbx_cmd_comp);
2602 complete(&ha->mbx_cmd_comp);
2603 init_completion(&ha->mbx_intr_comp);
23f2ebd1 2604 init_completion(&ha->dcbx_comp);
f356bef1 2605 init_completion(&ha->lb_portup_comp);
1da177e4 2606
2c3dfe3f 2607 set_bit(0, (unsigned long *) ha->vp_idx_map);
1da177e4 2608
53303c42 2609 qla2x00_config_dma_addressing(ha);
7c3df132
SK		 2610 ql_dbg_pci(ql_dbg_init, pdev, 0x0020,
2611 "64 Bit addressing is %s.\n",
2612 ha->flags.enable_64bit_addressing ? "enable" :
2613 "disable");
73208dfd 2614 ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp);
e315cd28 2615 if (!ret) {
7c3df132
SK		 2616 ql_log_pci(ql_log_fatal, pdev, 0x0031,
2617 "Failed to allocate memory for adapter, aborting.\n");
1da177e4 2618
e315cd28
AC		 2619 goto probe_hw_failed;
2620 }
2621
73208dfd 2622 req->max_q_depth = MAX_Q_DEPTH;
e315cd28 2623 if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU)
73208dfd
AC		 2624 req->max_q_depth = ql2xmaxqdepth;
2625
e315cd28
AC		 2626
2627 base_vha = qla2x00_create_host(sht, ha);
2628 if (!base_vha) {
a1541d5a 2629 ret = -ENOMEM;
6e9f21f3 2630 qla2x00_mem_free(ha);
2afa19a9
AC		 2631 qla2x00_free_req_que(ha, req);
2632 qla2x00_free_rsp_que(ha, rsp);
e315cd28 2633 goto probe_hw_failed;
1da177e4
LT		 2634 }
2635
e315cd28
AC		 2636 pci_set_drvdata(pdev, base_vha);
2637
e315cd28 2638 host = base_vha->host;
2afa19a9 2639 base_vha->req = req;
8ae6d9c7
GM		 2640 if (IS_QLAFX00(ha))
2641 host->can_queue = 1024;
2642 else
2643 host->can_queue = req->length + 128;
73208dfd 2644 if (IS_QLA2XXX_MIDTYPE(ha))
e315cd28 2645 base_vha->mgmt_svr_loop_id = 10 + base_vha->vp_idx;
73208dfd 2646 else
e315cd28
AC		 2647 base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER +
2648 base_vha->vp_idx;
58548cb5 2649
8ae6d9c7
GM		 2650 /* Setup fcport template structure. */
2651 ha->mr.fcport.vha = base_vha;
2652 ha->mr.fcport.port_type = FCT_UNKNOWN;
2653 ha->mr.fcport.loop_id = FC_NO_LOOP_ID;
2654 qla2x00_set_fcport_state(&ha->mr.fcport, FCS_UNCONFIGURED);
2655 ha->mr.fcport.supported_classes = FC_COS_UNSPECIFIED;
2656 ha->mr.fcport.scan_state = 1;
2657
58548cb5
GM		 2658 /* Set the SG table size based on ISP type */
2659 if (!IS_FWI2_CAPABLE(ha)) {
2660 if (IS_QLA2100(ha))
2661 host->sg_tablesize = 32;
2662 } else {
2663 if (!IS_QLA82XX(ha))
2664 host->sg_tablesize = QLA_SG_ALL;
2665 }
7c3df132
SK		 2666 ql_dbg(ql_dbg_init, base_vha, 0x0032,
2667 "can_queue=%d, req=%p, "
2668 "mgmt_svr_loop_id=%d, sg_tablesize=%d.\n",
2669 host->can_queue, base_vha->req,
2670 base_vha->mgmt_svr_loop_id, host->sg_tablesize);
642ef983 2671 host->max_id = ha->max_fibre_devices;
e315cd28
AC		 2672 host->cmd_per_lun = 3;
2673 host->unique_id = host->host_no;
e02587d7 2674 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif)
0c470874
AE		 2675 host->max_cmd_len = 32;
2676 else
2677 host->max_cmd_len = MAX_CMDSZ;
e315cd28 2678 host->max_channel = MAX_BUSES - 1;
82515920 2679 host->max_lun = ql2xmaxlun;
e315cd28 2680 host->transportt = qla2xxx_transport_template;
9a069e19 2681 sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC);
e315cd28 2682
7c3df132
SK		 2683 ql_dbg(ql_dbg_init, base_vha, 0x0033,
2684 "max_id=%d this_id=%d "
2685 "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d "
d8424f68 2686 "max_lun=%d transportt=%p, vendor_id=%llu.\n", host->max_id,
7c3df132
SK		 2687 host->this_id, host->cmd_per_lun, host->unique_id,
2688 host->max_cmd_len, host->max_channel, host->max_lun,
2689 host->transportt, sht->vendor_id);
2690
9a347ff4
CD		 2691que_init:
2692 /* Alloc arrays of request and response ring ptrs */
2693 if (!qla2x00_alloc_queues(ha, req, rsp)) {
2694 ql_log(ql_log_fatal, base_vha, 0x003d,
2695 "Failed to allocate memory for queue pointers..."
2696 "aborting.\n");
2697 goto probe_init_failed;
2698 }
2699
2d70c103 2700 qlt_probe_one_stage1(base_vha, ha);
9a347ff4 2701
73208dfd
AC		 2702 /* Set up the irqs */
2703 ret = qla2x00_request_irqs(ha, rsp);
2704 if (ret)
6e9f21f3 2705 goto probe_init_failed;
90a86fc0
JC		 2706
2707 pci_save_state(pdev);
2708
9a347ff4 2709 /* Assign back pointers */
2afa19a9
AC		 2710 rsp->req = req;
2711 req->rsp = rsp;
9a347ff4 2712
8ae6d9c7
GM		 2713 if (IS_QLAFX00(ha)) {
2714 ha->rsp_q_map[0] = rsp;
2715 ha->req_q_map[0] = req;
2716 set_bit(0, ha->req_qid_map);
2717 set_bit(0, ha->rsp_qid_map);
2718 }
2719
08029990
AV		 2720 /* FWI2-capable only. */
2721 req->req_q_in = &ha->iobase->isp24.req_q_in;
2722 req->req_q_out = &ha->iobase->isp24.req_q_out;
2723 rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in;
2724 rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out;
6246b8a1 2725 if (ha->mqenable || IS_QLA83XX(ha)) {
08029990
AV		 2726 req->req_q_in = &ha->mqiobase->isp25mq.req_q_in;
2727 req->req_q_out = &ha->mqiobase->isp25mq.req_q_out;
2728 rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in;
2729 rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out;
17d98630
AC		 2730 }
2731
8ae6d9c7
GM		 2732 if (IS_QLAFX00(ha)) {
2733 req->req_q_in = &ha->iobase->ispfx00.req_q_in;
2734 req->req_q_out = &ha->iobase->ispfx00.req_q_out;
2735 rsp->rsp_q_in = &ha->iobase->ispfx00.rsp_q_in;
2736 rsp->rsp_q_out = &ha->iobase->ispfx00.rsp_q_out;
2737 }
2738
7ec0effd 2739 if (IS_P3P_TYPE(ha)) {
a9083016
GM		 2740 req->req_q_out = &ha->iobase->isp82.req_q_out[0];
2741 rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0];
2742 rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0];
2743 }
2744
7c3df132
SK		 2745 ql_dbg(ql_dbg_multiq, base_vha, 0xc009,
2746 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
2747 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
2748 ql_dbg(ql_dbg_multiq, base_vha, 0xc00a,
2749 "req->req_q_in=%p req->req_q_out=%p "
2750 "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
2751 req->req_q_in, req->req_q_out,
2752 rsp->rsp_q_in, rsp->rsp_q_out);
2753 ql_dbg(ql_dbg_init, base_vha, 0x003e,
2754 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
2755 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
2756 ql_dbg(ql_dbg_init, base_vha, 0x003f,
2757 "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
2758 req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out);
1da177e4 2759
8ae6d9c7 2760 if (ha->isp_ops->initialize_adapter(base_vha)) {
7c3df132
SK		 2761 ql_log(ql_log_fatal, base_vha, 0x00d6,
2762 "Failed to initialize adapter - Adapter flags %x.\n",
2763 base_vha->device_flags);
1da177e4 2764
a9083016
GM		 2765 if (IS_QLA82XX(ha)) {
2766 qla82xx_idc_lock(ha);
2767 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 2768 QLA8XXX_DEV_FAILED);
a9083016 2769 qla82xx_idc_unlock(ha);
7c3df132
SK		 2770 ql_log(ql_log_fatal, base_vha, 0x00d7,
2771 "HW State: FAILED.\n");
7ec0effd
AD		 2772 } else if (IS_QLA8044(ha)) {
2773 qla8044_idc_lock(ha);
2774 qla8044_wr_direct(base_vha,
2775 QLA8044_CRB_DEV_STATE_INDEX,
2776 QLA8XXX_DEV_FAILED);
2777 qla8044_idc_unlock(ha);
2778 ql_log(ql_log_fatal, base_vha, 0x0150,
2779 "HW State: FAILED.\n");
a9083016
GM		 2780 }
2781
a1541d5a 2782 ret = -ENODEV;
1da177e4
LT		 2783 goto probe_failed;
2784 }
2785
7163ea81
AC		 2786 if (ha->mqenable) {
2787 if (qla25xx_setup_mode(base_vha)) {
7c3df132
SK		 2788 ql_log(ql_log_warn, base_vha, 0x00ec,
2789 "Failed to create queues, falling back to single queue mode.\n");
7163ea81
AC		 2790 goto que_init;
2791 }
2792 }
68ca949c 2793
cbc8eb67
AV		 2794 if (ha->flags.running_gold_fw)
2795 goto skip_dpc;
2796
1da177e4
LT		 2797 /*
2798 * Startup the kernel thread for this host adapter
2799 */
39a11240 2800 ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha,
7c3df132 2801 "%s_dpc", base_vha->host_str);
39a11240 2802 if (IS_ERR(ha->dpc_thread)) {
7c3df132
SK		 2803 ql_log(ql_log_fatal, base_vha, 0x00ed,
2804 "Failed to start DPC thread.\n");
39a11240 2805 ret = PTR_ERR(ha->dpc_thread);
1da177e4
LT		 2806 goto probe_failed;
2807 }
7c3df132
SK		 2808 ql_dbg(ql_dbg_init, base_vha, 0x00ee,
2809 "DPC thread started successfully.\n");
1da177e4 2810
2d70c103
NB		 2811 /*
2812 * If we're not coming up in initiator mode, we might sit for
2813 * a while without waking up the dpc thread, which leads to a
2814 * stuck process warning. So just kick the dpc once here and
2815 * let the kthread start (and go back to sleep in qla2x00_do_dpc).
2816 */
2817 qla2xxx_wake_dpc(base_vha);
2818
81178772
SK		 2819 if (IS_QLA8031(ha) || IS_MCTP_CAPABLE(ha)) {
2820 sprintf(wq_name, "qla2xxx_%lu_dpc_lp_wq", base_vha->host_no);
2821 ha->dpc_lp_wq = create_singlethread_workqueue(wq_name);
2822 INIT_WORK(&ha->idc_aen, qla83xx_service_idc_aen);
2823
2824 sprintf(wq_name, "qla2xxx_%lu_dpc_hp_wq", base_vha->host_no);
2825 ha->dpc_hp_wq = create_singlethread_workqueue(wq_name);
2826 INIT_WORK(&ha->nic_core_reset, qla83xx_nic_core_reset_work);
2827 INIT_WORK(&ha->idc_state_handler,
2828 qla83xx_idc_state_handler_work);
2829 INIT_WORK(&ha->nic_core_unrecoverable,
2830 qla83xx_nic_core_unrecoverable_work);
2831 }
2832
cbc8eb67 2833skip_dpc:
e315cd28
AC		 2834 list_add_tail(&base_vha->list, &ha->vp_list);
2835 base_vha->host->irq = ha->pdev->irq;
1da177e4
LT		 2836
2837 /* Initialized the timer */
e315cd28 2838 qla2x00_start_timer(base_vha, qla2x00_timer, WATCH_INTERVAL);
7c3df132
SK		 2839 ql_dbg(ql_dbg_init, base_vha, 0x00ef,
2840 "Started qla2x00_timer with "
2841 "interval=%d.\n", WATCH_INTERVAL);
2842 ql_dbg(ql_dbg_init, base_vha, 0x00f0,
2843 "Detected hba at address=%p.\n",
2844 ha);
d19044c3 2845
e02587d7 2846 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) {
bad75002 2847 if (ha->fw_attributes & BIT_4) {
9e522cd8 2848 int prot = 0, guard;
bad75002 2849 base_vha->flags.difdix_supported = 1;
7c3df132
SK		 2850 ql_dbg(ql_dbg_init, base_vha, 0x00f1,
2851 "Registering for DIF/DIX type 1 and 3 protection.\n");
8cb2049c
AE		 2852 if (ql2xenabledif == 1)
2853 prot = SHOST_DIX_TYPE0_PROTECTION;
bad75002 2854 scsi_host_set_prot(host,
8cb2049c 2855 prot | SHOST_DIF_TYPE1_PROTECTION
0c470874 2856 | SHOST_DIF_TYPE2_PROTECTION
bad75002
AE		 2857 | SHOST_DIF_TYPE3_PROTECTION
2858 | SHOST_DIX_TYPE1_PROTECTION
0c470874 2859 | SHOST_DIX_TYPE2_PROTECTION
bad75002 2860 | SHOST_DIX_TYPE3_PROTECTION);
9e522cd8
AE		 2861
2862 guard = SHOST_DIX_GUARD_CRC;
2863
2864 if (IS_PI_IPGUARD_CAPABLE(ha) &&
2865 (ql2xenabledif > 1 || IS_PI_DIFB_DIX0_CAPABLE(ha)))
2866 guard |= SHOST_DIX_GUARD_IP;
2867
2868 scsi_host_set_guard(host, guard);
bad75002
AE		 2869 } else
2870 base_vha->flags.difdix_supported = 0;
2871 }
2872
a9083016
GM		 2873 ha->isp_ops->enable_intrs(ha);
2874
1fe19ee4
AB		 2875 if (IS_QLAFX00(ha)) {
2876 ret = qlafx00_fx_disc(base_vha,
2877 &base_vha->hw->mr.fcport, FXDISC_GET_CONFIG_INFO);
2878 host->sg_tablesize = (ha->mr.extended_io_enabled) ?
2879 QLA_SG_ALL : 128;
2880 }
2881
a1541d5a
AV		 2882 ret = scsi_add_host(host, &pdev->dev);
2883 if (ret)
2884 goto probe_failed;
2885
1486400f
MR		 2886 base_vha->flags.init_done = 1;
2887 base_vha->flags.online = 1;
2888
7c3df132
SK		 2889 ql_dbg(ql_dbg_init, base_vha, 0x00f2,
2890 "Init done and hba is online.\n");
2891
2d70c103
NB		 2892 if (qla_ini_mode_enabled(base_vha))
2893 scsi_scan_host(host);
2894 else
2895 ql_dbg(ql_dbg_init, base_vha, 0x0122,
2896 "skipping scsi_scan_host() for non-initiator port\n");
1e99e33a 2897
e315cd28 2898 qla2x00_alloc_sysfs_attr(base_vha);
a1541d5a 2899
8ae6d9c7 2900 if (IS_QLAFX00(ha)) {
8ae6d9c7
GM		 2901 ret = qlafx00_fx_disc(base_vha,
2902 &base_vha->hw->mr.fcport, FXDISC_GET_PORT_INFO);
2903
2904 /* Register system information */
2905 ret = qlafx00_fx_disc(base_vha,
2906 &base_vha->hw->mr.fcport, FXDISC_REG_HOST_INFO);
2907 }
2908
e315cd28 2909 qla2x00_init_host_attr(base_vha);
a1541d5a 2910
e315cd28 2911 qla2x00_dfs_setup(base_vha);
df613b96 2912
a324031c
AB		 2913 if (IS_QLAFX00(ha))
2914 ql_log(ql_log_info, base_vha, 0x015a,
2915 "QLogic %s.\n", ha->mr.product_name);
2916 else
2917 ql_log(ql_log_info, base_vha, 0x00fb,
2918 "QLogic %s - %s.\n", ha->model_number, ha->model_desc);
7c3df132
SK		 2919 ql_log(ql_log_info, base_vha, 0x00fc,
2920 "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n",
2921 pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info),
2922 pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-',
2923 base_vha->host_no,
e315cd28 2924 ha->isp_ops->fw_version_str(base_vha, fw_str));
1da177e4 2925
2d70c103
NB		 2926 qlt_add_target(ha, base_vha);
2927
1da177e4
LT		 2928 return 0;
2929
6e9f21f3 2930probe_init_failed:
2afa19a9 2931 qla2x00_free_req_que(ha, req);
9a347ff4
CD		 2932 ha->req_q_map[0] = NULL;
2933 clear_bit(0, ha->req_qid_map);
2afa19a9 2934 qla2x00_free_rsp_que(ha, rsp);
9a347ff4
CD		 2935 ha->rsp_q_map[0] = NULL;
2936 clear_bit(0, ha->rsp_qid_map);
2afa19a9 2937 ha->max_req_queues = ha->max_rsp_queues = 0;
6e9f21f3 2938
1da177e4 2939probe_failed:
b9978769
AV		 2940 if (base_vha->timer_active)
2941 qla2x00_stop_timer(base_vha);
2942 base_vha->flags.online = 0;
2943 if (ha->dpc_thread) {
2944 struct task_struct *t = ha->dpc_thread;
2945
2946 ha->dpc_thread = NULL;
2947 kthread_stop(t);
2948 }
2949
e315cd28 2950 qla2x00_free_device(base_vha);
1da177e4 2951
e315cd28 2952 scsi_host_put(base_vha->host);
1da177e4 2953
e315cd28 2954probe_hw_failed:
a9083016
GM		 2955 if (IS_QLA82XX(ha)) {
2956 qla82xx_idc_lock(ha);
2957 qla82xx_clear_drv_active(ha);
2958 qla82xx_idc_unlock(ha);
0a63ad12 2959 }
7ec0effd
AD		 2960 if (IS_QLA8044(ha)) {
2961 qla8044_idc_lock(ha);
2962 qla8044_clear_drv_active(base_vha);
2963 qla8044_idc_unlock(ha);
2964 }
0a63ad12 2965iospace_config_failed:
7ec0effd 2966 if (IS_P3P_TYPE(ha)) {
0a63ad12
SK		 2967 if (!ha->nx_pcibase)
2968 iounmap((device_reg_t __iomem *)ha->nx_pcibase);
a9083016
GM		 2969 if (!ql2xdbwr)
2970 iounmap((device_reg_t __iomem *)ha->nxdb_wr_ptr);
2971 } else {
2972 if (ha->iobase)
2973 iounmap(ha->iobase);
8ae6d9c7
GM		 2974 if (ha->cregbase)
2975 iounmap(ha->cregbase);
a9083016 2976 }
e315cd28
AC		 2977 pci_release_selected_regions(ha->pdev, ha->bars);
2978 kfree(ha);
2979 ha = NULL;
1da177e4 2980
a1541d5a 2981probe_out:
e315cd28 2982 pci_disable_device(pdev);
a1541d5a 2983 return ret;
1da177e4 2984}
1da177e4 2985
2d70c103
NB		 2986static void
2987qla2x00_stop_dpc_thread(scsi_qla_host_t *vha)
2988{
2989 struct qla_hw_data *ha = vha->hw;
2990 struct task_struct *t = ha->dpc_thread;
2991
2992 if (ha->dpc_thread == NULL)
2993 return;
2994 /*
2995 * qla2xxx_wake_dpc checks for ->dpc_thread
2996 * so we need to zero it out.
2997 */
2998 ha->dpc_thread = NULL;
2999 kthread_stop(t);
3000}
3001
e30d1756
MI		 3002static void
3003qla2x00_shutdown(struct pci_dev *pdev)
3004{
3005 scsi_qla_host_t *vha;
3006 struct qla_hw_data *ha;
3007
552f3f9a
MI		 3008 if (!atomic_read(&pdev->enable_cnt))
3009 return;
3010
e30d1756
MI		 3011 vha = pci_get_drvdata(pdev);
3012 ha = vha->hw;
3013
42479343
AB		 3014 /* Notify ISPFX00 firmware */
3015 if (IS_QLAFX00(ha))
3016 qlafx00_driver_shutdown(vha, 20);
3017
e30d1756
MI		 3018 /* Turn-off FCE trace */
3019 if (ha->flags.fce_enabled) {
3020 qla2x00_disable_fce_trace(vha, NULL, NULL);
3021 ha->flags.fce_enabled = 0;
3022 }
3023
3024 /* Turn-off EFT trace */
3025 if (ha->eft)
3026 qla2x00_disable_eft_trace(vha);
3027
3028 /* Stop currently executing firmware. */
3029 qla2x00_try_to_stop_firmware(vha);
3030
3031 /* Turn adapter off line */
3032 vha->flags.online = 0;
3033
3034 /* turn-off interrupts on the card */
3035 if (ha->interrupts_on) {
3036 vha->flags.init_done = 0;
3037 ha->isp_ops->disable_intrs(ha);
3038 }
3039
3040 qla2x00_free_irqs(vha);
3041
3042 qla2x00_free_fw_dump(ha);
3043}
3044
4c993f76 3045static void
7ee61397 3046qla2x00_remove_one(struct pci_dev *pdev)
1da177e4 3047{
feafb7b1 3048 scsi_qla_host_t *base_vha, *vha;
e315cd28 3049 struct qla_hw_data *ha;
feafb7b1 3050 unsigned long flags;
e315cd28 3051
9a347ff4
CD		 3052 /*
3053 * If the PCI device is disabled that means that probe failed and any
3054 * resources should be have cleaned up on probe exit.
3055 */
3056 if (!atomic_read(&pdev->enable_cnt))
3057 return;
3058
e315cd28
AC		 3059 base_vha = pci_get_drvdata(pdev);
3060 ha = base_vha->hw;
3061
2d70c103
NB		 3062 ha->flags.host_shutting_down = 1;
3063
220d36b4 3064 set_bit(UNLOADING, &base_vha->dpc_flags);
42479343
AB		 3065 if (IS_QLAFX00(ha))
3066 qlafx00_driver_shutdown(base_vha, 20);
3067
43ebf16d
AE		 3068 mutex_lock(&ha->vport_lock);
3069 while (ha->cur_vport_count) {
43ebf16d 3070 spin_lock_irqsave(&ha->vport_slock, flags);
feafb7b1 3071
43ebf16d
AE		 3072 BUG_ON(base_vha->list.next == &ha->vp_list);
3073 /* This assumes first entry in ha->vp_list is always base vha */
3074 vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list);
6e97c9d5 3075 scsi_host_get(vha->host);
feafb7b1 3076
43ebf16d
AE		 3077 spin_unlock_irqrestore(&ha->vport_slock, flags);
3078 mutex_unlock(&ha->vport_lock);
3079
3080 fc_vport_terminate(vha->fc_vport);
3081 scsi_host_put(vha->host);
feafb7b1 3082
43ebf16d 3083 mutex_lock(&ha->vport_lock);
e315cd28 3084 }
43ebf16d 3085 mutex_unlock(&ha->vport_lock);
1da177e4 3086
7d613ac6
SV		 3087 if (IS_QLA8031(ha)) {
3088 ql_dbg(ql_dbg_p3p, base_vha, 0xb07e,
3089 "Clearing fcoe driver presence.\n");
3090 if (qla83xx_clear_drv_presence(base_vha) != QLA_SUCCESS)
3091 ql_dbg(ql_dbg_p3p, base_vha, 0xb079,
3092 "Error while clearing DRV-Presence.\n");
3093 }
3094
b9978769
AV		 3095 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
3096
e315cd28 3097 qla2x00_dfs_remove(base_vha);
c795c1e4 3098
e315cd28 3099 qla84xx_put_chip(base_vha);
c795c1e4 3100
b9978769
AV		 3101 /* Disable timer */
3102 if (base_vha->timer_active)
3103 qla2x00_stop_timer(base_vha);
3104
3105 base_vha->flags.online = 0;
3106
68ca949c
AC		 3107 /* Flush the work queue and remove it */
3108 if (ha->wq) {
3109 flush_workqueue(ha->wq);
3110 destroy_workqueue(ha->wq);
3111 ha->wq = NULL;
3112 }
3113
7d613ac6
SV		 3114 /* Cancel all work and destroy DPC workqueues */
3115 if (ha->dpc_lp_wq) {
3116 cancel_work_sync(&ha->idc_aen);
3117 destroy_workqueue(ha->dpc_lp_wq);
3118 ha->dpc_lp_wq = NULL;
3119 }
3120
3121 if (ha->dpc_hp_wq) {
3122 cancel_work_sync(&ha->nic_core_reset);
3123 cancel_work_sync(&ha->idc_state_handler);
3124 cancel_work_sync(&ha->nic_core_unrecoverable);
3125 destroy_workqueue(ha->dpc_hp_wq);
3126 ha->dpc_hp_wq = NULL;
3127 }
3128
b9978769
AV		 3129 /* Kill the kernel thread for this host */
3130 if (ha->dpc_thread) {
3131 struct task_struct *t = ha->dpc_thread;
3132
3133 /*
3134 * qla2xxx_wake_dpc checks for ->dpc_thread
3135 * so we need to zero it out.
3136 */
3137 ha->dpc_thread = NULL;
3138 kthread_stop(t);
3139 }
2d70c103 3140 qlt_remove_target(ha, base_vha);
b9978769 3141
e315cd28 3142 qla2x00_free_sysfs_attr(base_vha);
df613b96 3143
e315cd28 3144 fc_remove_host(base_vha->host);
4d4df193 3145
e315cd28 3146 scsi_remove_host(base_vha->host);
1da177e4 3147
e315cd28 3148 qla2x00_free_device(base_vha);
bdf79621 3149
e315cd28 3150 scsi_host_put(base_vha->host);
1da177e4 3151
7ec0effd
AD		 3152 if (IS_QLA8044(ha)) {
3153 qla8044_idc_lock(ha);
3154 qla8044_clear_drv_active(base_vha);
3155 qla8044_idc_unlock(ha);
3156 }
a9083016 3157 if (IS_QLA82XX(ha)) {
b963752f
GM		 3158 qla82xx_idc_lock(ha);
3159 qla82xx_clear_drv_active(ha);
3160 qla82xx_idc_unlock(ha);
3161
a9083016
GM		 3162 iounmap((device_reg_t __iomem *)ha->nx_pcibase);
3163 if (!ql2xdbwr)
3164 iounmap((device_reg_t __iomem *)ha->nxdb_wr_ptr);
3165 } else {
3166 if (ha->iobase)
3167 iounmap(ha->iobase);
1da177e4 3168
8ae6d9c7
GM		 3169 if (ha->cregbase)
3170 iounmap(ha->cregbase);
3171
a9083016
GM		 3172 if (ha->mqiobase)
3173 iounmap(ha->mqiobase);
6246b8a1
GM		 3174
3175 if (IS_QLA83XX(ha) && ha->msixbase)
3176 iounmap(ha->msixbase);
a9083016 3177 }
73208dfd 3178
e315cd28
AC		 3179 pci_release_selected_regions(ha->pdev, ha->bars);
3180 kfree(ha);
3181 ha = NULL;
1da177e4 3182
90a86fc0
JC		 3183 pci_disable_pcie_error_reporting(pdev);
3184
665db93b 3185 pci_disable_device(pdev);
1da177e4 3186}
1da177e4
LT		 3187
3188static void
e315cd28 3189qla2x00_free_device(scsi_qla_host_t *vha)
1da177e4 3190{
e315cd28 3191 struct qla_hw_data *ha = vha->hw;
1da177e4 3192
85880801
AV		 3193 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
3194
3195 /* Disable timer */
3196 if (vha->timer_active)
3197 qla2x00_stop_timer(vha);
3198
2d70c103 3199 qla2x00_stop_dpc_thread(vha);
85880801 3200
2afa19a9 3201 qla25xx_delete_queues(vha);
df613b96 3202 if (ha->flags.fce_enabled)
e315cd28 3203 qla2x00_disable_fce_trace(vha, NULL, NULL);
df613b96 3204
a7a167bf 3205 if (ha->eft)
e315cd28 3206 qla2x00_disable_eft_trace(vha);
a7a167bf 3207
f6ef3b18 3208 /* Stop currently executing firmware. */
e315cd28 3209 qla2x00_try_to_stop_firmware(vha);
1da177e4 3210
85880801
AV		 3211 vha->flags.online = 0;
3212
f6ef3b18 3213 /* turn-off interrupts on the card */
a9083016
GM		 3214 if (ha->interrupts_on) {
3215 vha->flags.init_done = 0;
fd34f556 3216 ha->isp_ops->disable_intrs(ha);
a9083016 3217 }
f6ef3b18 3218
e315cd28 3219 qla2x00_free_irqs(vha);
1da177e4 3220
8867048b
CD		 3221 qla2x00_free_fcports(vha);
3222
e315cd28 3223 qla2x00_mem_free(ha);
73208dfd 3224
08de2844
GM		 3225 qla82xx_md_free(vha);
3226
73208dfd 3227 qla2x00_free_queues(ha);
1da177e4
LT		 3228}
3229
8867048b
CD		 3230void qla2x00_free_fcports(struct scsi_qla_host *vha)
3231{
3232 fc_port_t *fcport, *tfcport;
3233
3234 list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list) {
3235 list_del(&fcport->list);
5f16b331 3236 qla2x00_clear_loop_id(fcport);
8867048b
CD		 3237 kfree(fcport);
3238 fcport = NULL;
3239 }
3240}
3241
d97994dc 3242static inline void
e315cd28 3243qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport,
d97994dc 3244 int defer)
3245{
d97994dc 3246 struct fc_rport *rport;
67becc00 3247 scsi_qla_host_t *base_vha;
044d78e1 3248 unsigned long flags;
d97994dc 3249
3250 if (!fcport->rport)
3251 return;
3252
3253 rport = fcport->rport;
3254 if (defer) {
67becc00 3255 base_vha = pci_get_drvdata(vha->hw->pdev);
044d78e1 3256 spin_lock_irqsave(vha->host->host_lock, flags);
d97994dc 3257 fcport->drport = rport;
044d78e1 3258 spin_unlock_irqrestore(vha->host->host_lock, flags);
67becc00
AV		 3259 set_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags);
3260 qla2xxx_wake_dpc(base_vha);
2d70c103 3261 } else {
d97994dc 3262 fc_remote_port_delete(rport);
2d70c103
NB		 3263 qlt_fc_port_deleted(vha, fcport);
3264 }
d97994dc 3265}
3266
1da177e4
LT		 3267/*
3268 * qla2x00_mark_device_lost Updates fcport state when device goes offline.
3269 *
3270 * Input: ha = adapter block pointer. fcport = port structure pointer.
3271 *
3272 * Return: None.
3273 *
3274 * Context:
3275 */
e315cd28 3276void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport,
d97994dc 3277 int do_login, int defer)
1da177e4 3278{
8ae6d9c7
GM		 3279 if (IS_QLAFX00(vha->hw)) {
3280 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
3281 qla2x00_schedule_rport_del(vha, fcport, defer);
3282 return;
3283 }
3284
2c3dfe3f 3285 if (atomic_read(&fcport->state) == FCS_ONLINE &&
c6d39e23 3286 vha->vp_idx == fcport->vha->vp_idx) {
ec426e10 3287 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
e315cd28
AC		 3288 qla2x00_schedule_rport_del(vha, fcport, defer);
3289 }
fa2a1ce5 3290 /*
1da177e4
LT		 3291 * We may need to retry the login, so don't change the state of the
3292 * port but do the retries.
3293 */
3294 if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD)
ec426e10 3295 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
1da177e4
LT		 3296
3297 if (!do_login)
3298 return;
3299
3300 if (fcport->login_retry == 0) {
e315cd28
AC		 3301 fcport->login_retry = vha->hw->login_retry_count;
3302 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
1da177e4 3303
7c3df132 3304 ql_dbg(ql_dbg_disc, vha, 0x2067,
7b833558
OK		 3305 "Port login retry %8phN, id = 0x%04x retry cnt=%d.\n",
3306 fcport->port_name, fcport->loop_id, fcport->login_retry);
1da177e4
LT		 3307 }
3308}
3309
3310/*
3311 * qla2x00_mark_all_devices_lost
3312 * Updates fcport state when device goes offline.
3313 *
3314 * Input:
3315 * ha = adapter block pointer.
3316 * fcport = port structure pointer.
3317 *
3318 * Return:
3319 * None.
3320 *
3321 * Context:
3322 */
3323void
e315cd28 3324qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha, int defer)
1da177e4
LT		 3325{
3326 fc_port_t *fcport;
3327
e315cd28 3328 list_for_each_entry(fcport, &vha->vp_fcports, list) {
c6d39e23 3329 if (vha->vp_idx != 0 && vha->vp_idx != fcport->vha->vp_idx)
1da177e4 3330 continue;
0d6e61bc 3331
1da177e4
LT		 3332 /*
3333 * No point in marking the device as lost, if the device is
3334 * already DEAD.
3335 */
3336 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD)
3337 continue;
e315cd28 3338 if (atomic_read(&fcport->state) == FCS_ONLINE) {
ec426e10 3339 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
0d6e61bc
AV		 3340 if (defer)
3341 qla2x00_schedule_rport_del(vha, fcport, defer);
c6d39e23 3342 else if (vha->vp_idx == fcport->vha->vp_idx)
0d6e61bc
AV		 3343 qla2x00_schedule_rport_del(vha, fcport, defer);
3344 }
1da177e4
LT		 3345 }
3346}
3347
3348/*
3349* qla2x00_mem_alloc
3350* Allocates adapter memory.
3351*
3352* Returns:
3353* 0 = success.
e8711085 3354* !0 = failure.
1da177e4 3355*/
e8711085 3356static int
73208dfd
AC		 3357qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len,
3358 struct req_que **req, struct rsp_que **rsp)
1da177e4
LT		 3359{
3360 char name[16];
1da177e4 3361
e8711085 3362 ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size,
e315cd28 3363 &ha->init_cb_dma, GFP_KERNEL);
e8711085 3364 if (!ha->init_cb)
e315cd28 3365 goto fail;
e8711085 3366
2d70c103
NB		 3367 if (qlt_mem_alloc(ha) < 0)
3368 goto fail_free_init_cb;
3369
642ef983
CD		 3370 ha->gid_list = dma_alloc_coherent(&ha->pdev->dev,
3371 qla2x00_gid_list_size(ha), &ha->gid_list_dma, GFP_KERNEL);
e315cd28 3372 if (!ha->gid_list)
2d70c103 3373 goto fail_free_tgt_mem;
1da177e4 3374
e8711085
AV		 3375 ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep);
3376 if (!ha->srb_mempool)
e315cd28 3377 goto fail_free_gid_list;
e8711085 3378
7ec0effd 3379 if (IS_P3P_TYPE(ha)) {
a9083016
GM		 3380 /* Allocate cache for CT6 Ctx. */
3381 if (!ctx_cachep) {
3382 ctx_cachep = kmem_cache_create("qla2xxx_ctx",
3383 sizeof(struct ct6_dsd), 0,
3384 SLAB_HWCACHE_ALIGN, NULL);
3385 if (!ctx_cachep)
3386 goto fail_free_gid_list;
3387 }
3388 ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ,
3389 ctx_cachep);
3390 if (!ha->ctx_mempool)
3391 goto fail_free_srb_mempool;
7c3df132
SK		 3392 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021,
3393 "ctx_cachep=%p ctx_mempool=%p.\n",
3394 ctx_cachep, ha->ctx_mempool);
a9083016
GM		 3395 }
3396
e8711085
AV		 3397 /* Get memory for cached NVRAM */
3398 ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL);
3399 if (!ha->nvram)
a9083016 3400 goto fail_free_ctx_mempool;
e8711085 3401
e315cd28
AC		 3402 snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME,
3403 ha->pdev->device);
3404 ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3405 DMA_POOL_SIZE, 8, 0);
3406 if (!ha->s_dma_pool)
3407 goto fail_free_nvram;
3408
7c3df132
SK		 3409 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022,
3410 "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n",
3411 ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool);
3412
7ec0effd 3413 if (IS_P3P_TYPE(ha) || ql2xenabledif) {
a9083016
GM		 3414 ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3415 DSD_LIST_DMA_POOL_SIZE, 8, 0);
3416 if (!ha->dl_dma_pool) {
7c3df132
SK		 3417 ql_log_pci(ql_log_fatal, ha->pdev, 0x0023,
3418 "Failed to allocate memory for dl_dma_pool.\n");
a9083016
GM		 3419 goto fail_s_dma_pool;
3420 }
3421
3422 ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3423 FCP_CMND_DMA_POOL_SIZE, 8, 0);
3424 if (!ha->fcp_cmnd_dma_pool) {
7c3df132
SK		 3425 ql_log_pci(ql_log_fatal, ha->pdev, 0x0024,
3426 "Failed to allocate memory for fcp_cmnd_dma_pool.\n");
a9083016
GM		 3427 goto fail_dl_dma_pool;
3428 }
7c3df132
SK		 3429 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025,
3430 "dl_dma_pool=%p fcp_cmnd_dma_pool=%p.\n",
3431 ha->dl_dma_pool, ha->fcp_cmnd_dma_pool);
a9083016
GM		 3432 }
3433
e8711085
AV		 3434 /* Allocate memory for SNS commands */
3435 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
e315cd28 3436 /* Get consistent memory allocated for SNS commands */
e8711085 3437 ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev,
e315cd28 3438 sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL);
e8711085 3439 if (!ha->sns_cmd)
e315cd28 3440 goto fail_dma_pool;
7c3df132 3441 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026,
d8424f68 3442 "sns_cmd: %p.\n", ha->sns_cmd);
e8711085 3443 } else {
e315cd28 3444 /* Get consistent memory allocated for MS IOCB */
e8711085 3445 ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
e315cd28 3446 &ha->ms_iocb_dma);
e8711085 3447 if (!ha->ms_iocb)
e315cd28
AC		 3448 goto fail_dma_pool;
3449 /* Get consistent memory allocated for CT SNS commands */
e8711085 3450 ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev,
e315cd28 3451 sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL);
e8711085
AV		 3452 if (!ha->ct_sns)
3453 goto fail_free_ms_iocb;
7c3df132
SK		 3454 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027,
3455 "ms_iocb=%p ct_sns=%p.\n",
3456 ha->ms_iocb, ha->ct_sns);
1da177e4
LT		 3457 }
3458
e315cd28 3459 /* Allocate memory for request ring */
73208dfd
AC		 3460 *req = kzalloc(sizeof(struct req_que), GFP_KERNEL);
3461 if (!*req) {
7c3df132
SK		 3462 ql_log_pci(ql_log_fatal, ha->pdev, 0x0028,
3463 "Failed to allocate memory for req.\n");
e315cd28
AC		 3464 goto fail_req;
3465 }
73208dfd
AC		 3466 (*req)->length = req_len;
3467 (*req)->ring = dma_alloc_coherent(&ha->pdev->dev,
3468 ((*req)->length + 1) * sizeof(request_t),
3469 &(*req)->dma, GFP_KERNEL);
3470 if (!(*req)->ring) {
7c3df132
SK		 3471 ql_log_pci(ql_log_fatal, ha->pdev, 0x0029,
3472 "Failed to allocate memory for req_ring.\n");
e315cd28
AC		 3473 goto fail_req_ring;
3474 }
3475 /* Allocate memory for response ring */
73208dfd
AC		 3476 *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL);
3477 if (!*rsp) {
7c3df132
SK		 3478 ql_log_pci(ql_log_fatal, ha->pdev, 0x002a,
3479 "Failed to allocate memory for rsp.\n");
e315cd28
AC		 3480 goto fail_rsp;
3481 }
73208dfd
AC		 3482 (*rsp)->hw = ha;
3483 (*rsp)->length = rsp_len;
3484 (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev,
3485 ((*rsp)->length + 1) * sizeof(response_t),
3486 &(*rsp)->dma, GFP_KERNEL);
3487 if (!(*rsp)->ring) {
7c3df132
SK		 3488 ql_log_pci(ql_log_fatal, ha->pdev, 0x002b,
3489 "Failed to allocate memory for rsp_ring.\n");
e315cd28
AC		 3490 goto fail_rsp_ring;
3491 }
73208dfd
AC		 3492 (*req)->rsp = *rsp;
3493 (*rsp)->req = *req;
7c3df132
SK		 3494 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c,
3495 "req=%p req->length=%d req->ring=%p rsp=%p "
3496 "rsp->length=%d rsp->ring=%p.\n",
3497 *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length,
3498 (*rsp)->ring);
73208dfd
AC		 3499 /* Allocate memory for NVRAM data for vports */
3500 if (ha->nvram_npiv_size) {
3501 ha->npiv_info = kzalloc(sizeof(struct qla_npiv_entry) *
7c3df132 3502 ha->nvram_npiv_size, GFP_KERNEL);
73208dfd 3503 if (!ha->npiv_info) {
7c3df132
SK		 3504 ql_log_pci(ql_log_fatal, ha->pdev, 0x002d,
3505 "Failed to allocate memory for npiv_info.\n");
73208dfd
AC		 3506 goto fail_npiv_info;
3507 }
3508 } else
3509 ha->npiv_info = NULL;
e8711085 3510
b64b0e8f 3511 /* Get consistent memory allocated for EX-INIT-CB. */
6246b8a1 3512 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha)) {
b64b0e8f
AV		 3513 ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
3514 &ha->ex_init_cb_dma);
3515 if (!ha->ex_init_cb)
3516 goto fail_ex_init_cb;
7c3df132
SK		 3517 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e,
3518 "ex_init_cb=%p.\n", ha->ex_init_cb);
b64b0e8f
AV		 3519 }
3520
a9083016
GM		 3521 INIT_LIST_HEAD(&ha->gbl_dsd_list);
3522
5ff1d584
AV		 3523 /* Get consistent memory allocated for Async Port-Database. */
3524 if (!IS_FWI2_CAPABLE(ha)) {
3525 ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
3526 &ha->async_pd_dma);
3527 if (!ha->async_pd)
3528 goto fail_async_pd;
7c3df132
SK		 3529 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f,
3530 "async_pd=%p.\n", ha->async_pd);
5ff1d584
AV		 3531 }
3532
e315cd28 3533 INIT_LIST_HEAD(&ha->vp_list);
5f16b331
CD		 3534
3535 /* Allocate memory for our loop_id bitmap */
3536 ha->loop_id_map = kzalloc(BITS_TO_LONGS(LOOPID_MAP_SIZE) * sizeof(long),
3537 GFP_KERNEL);
3538 if (!ha->loop_id_map)
3539 goto fail_async_pd;
3540 else {
3541 qla2x00_set_reserved_loop_ids(ha);
3542 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0123,
3543 "loop_id_map=%p. \n", ha->loop_id_map);
3544 }
3545
e315cd28
AC		 3546 return 1;
3547
5ff1d584
AV		 3548fail_async_pd:
3549 dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma);
b64b0e8f
AV		 3550fail_ex_init_cb:
3551 kfree(ha->npiv_info);
73208dfd
AC		 3552fail_npiv_info:
3553 dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) *
3554 sizeof(response_t), (*rsp)->ring, (*rsp)->dma);
3555 (*rsp)->ring = NULL;
3556 (*rsp)->dma = 0;
e315cd28 3557fail_rsp_ring:
73208dfd 3558 kfree(*rsp);
e315cd28 3559fail_rsp:
73208dfd
AC		 3560 dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) *
3561 sizeof(request_t), (*req)->ring, (*req)->dma);
3562 (*req)->ring = NULL;
3563 (*req)->dma = 0;
e315cd28 3564fail_req_ring:
73208dfd 3565 kfree(*req);
e315cd28
AC		 3566fail_req:
3567 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
3568 ha->ct_sns, ha->ct_sns_dma);
3569 ha->ct_sns = NULL;
3570 ha->ct_sns_dma = 0;
e8711085
AV		 3571fail_free_ms_iocb:
3572 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
3573 ha->ms_iocb = NULL;
3574 ha->ms_iocb_dma = 0;
e315cd28 3575fail_dma_pool:
bad75002 3576 if (IS_QLA82XX(ha) || ql2xenabledif) {
a9083016
GM		 3577 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
3578 ha->fcp_cmnd_dma_pool = NULL;
3579 }
3580fail_dl_dma_pool:
bad75002 3581 if (IS_QLA82XX(ha) || ql2xenabledif) {
a9083016
GM		 3582 dma_pool_destroy(ha->dl_dma_pool);
3583 ha->dl_dma_pool = NULL;
3584 }
3585fail_s_dma_pool:
e315cd28
AC		 3586 dma_pool_destroy(ha->s_dma_pool);
3587 ha->s_dma_pool = NULL;
e8711085
AV		 3588fail_free_nvram:
3589 kfree(ha->nvram);
3590 ha->nvram = NULL;
a9083016
GM		 3591fail_free_ctx_mempool:
3592 mempool_destroy(ha->ctx_mempool);
3593 ha->ctx_mempool = NULL;
e8711085
AV		 3594fail_free_srb_mempool:
3595 mempool_destroy(ha->srb_mempool);
3596 ha->srb_mempool = NULL;
e8711085 3597fail_free_gid_list:
642ef983
CD		 3598 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
3599 ha->gid_list,
e315cd28 3600 ha->gid_list_dma);
e8711085
AV		 3601 ha->gid_list = NULL;
3602 ha->gid_list_dma = 0;
2d70c103
NB		 3603fail_free_tgt_mem:
3604 qlt_mem_free(ha);
e315cd28
AC		 3605fail_free_init_cb:
3606 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb,
3607 ha->init_cb_dma);
3608 ha->init_cb = NULL;
3609 ha->init_cb_dma = 0;
e8711085 3610fail:
7c3df132
SK		 3611 ql_log(ql_log_fatal, NULL, 0x0030,
3612 "Memory allocation failure.\n");
e8711085 3613 return -ENOMEM;
1da177e4
LT		 3614}
3615
3616/*
e30d1756
MI		 3617* qla2x00_free_fw_dump
3618* Frees fw dump stuff.
1da177e4
LT		 3619*
3620* Input:
7ec0effd 3621* ha = adapter block pointer
1da177e4 3622*/
a824ebb3 3623static void
e30d1756 3624qla2x00_free_fw_dump(struct qla_hw_data *ha)
1da177e4 3625{
df613b96
AV		 3626 if (ha->fce)
3627 dma_free_coherent(&ha->pdev->dev, FCE_SIZE, ha->fce,
e30d1756 3628 ha->fce_dma);
df613b96 3629
a7a167bf
AV		 3630 if (ha->fw_dump) {
3631 if (ha->eft)
3632 dma_free_coherent(&ha->pdev->dev,
e30d1756 3633 ntohl(ha->fw_dump->eft_size), ha->eft, ha->eft_dma);
a7a167bf
AV		 3634 vfree(ha->fw_dump);
3635 }
e30d1756
MI		 3636 ha->fce = NULL;
3637 ha->fce_dma = 0;
3638 ha->eft = NULL;
3639 ha->eft_dma = 0;
3640 ha->fw_dump = NULL;
3641 ha->fw_dumped = 0;
3642 ha->fw_dump_reading = 0;
3643}
3644
3645/*
3646* qla2x00_mem_free
3647* Frees all adapter allocated memory.
3648*
3649* Input:
3650* ha = adapter block pointer.
3651*/
3652static void
3653qla2x00_mem_free(struct qla_hw_data *ha)
3654{
3655 qla2x00_free_fw_dump(ha);
3656
81178772
SK		 3657 if (ha->mctp_dump)
3658 dma_free_coherent(&ha->pdev->dev, MCTP_DUMP_SIZE, ha->mctp_dump,
3659 ha->mctp_dump_dma);
3660
e30d1756
MI		 3661 if (ha->srb_mempool)
3662 mempool_destroy(ha->srb_mempool);
a7a167bf 3663
11bbc1d8
AV		 3664 if (ha->dcbx_tlv)
3665 dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE,
3666 ha->dcbx_tlv, ha->dcbx_tlv_dma);
3667
ce0423f4
AV		 3668 if (ha->xgmac_data)
3669 dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE,
3670 ha->xgmac_data, ha->xgmac_data_dma);
3671
1da177e4
LT		 3672 if (ha->sns_cmd)
3673 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
e315cd28 3674 ha->sns_cmd, ha->sns_cmd_dma);
1da177e4
LT		 3675
3676 if (ha->ct_sns)
3677 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
e315cd28 3678 ha->ct_sns, ha->ct_sns_dma);
1da177e4 3679
88729e53
AV		 3680 if (ha->sfp_data)
3681 dma_pool_free(ha->s_dma_pool, ha->sfp_data, ha->sfp_data_dma);
3682
1da177e4
LT		 3683 if (ha->ms_iocb)
3684 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
3685
b64b0e8f 3686 if (ha->ex_init_cb)
a9083016
GM		 3687 dma_pool_free(ha->s_dma_pool,
3688 ha->ex_init_cb, ha->ex_init_cb_dma);
b64b0e8f 3689
5ff1d584
AV		 3690 if (ha->async_pd)
3691 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
3692
1da177e4
LT		 3693 if (ha->s_dma_pool)
3694 dma_pool_destroy(ha->s_dma_pool);
3695
1da177e4 3696 if (ha->gid_list)
642ef983
CD		 3697 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
3698 ha->gid_list, ha->gid_list_dma);
1da177e4 3699
a9083016
GM		 3700 if (IS_QLA82XX(ha)) {
3701 if (!list_empty(&ha->gbl_dsd_list)) {
3702 struct dsd_dma *dsd_ptr, *tdsd_ptr;
3703
3704 /* clean up allocated prev pool */
3705 list_for_each_entry_safe(dsd_ptr,
3706 tdsd_ptr, &ha->gbl_dsd_list, list) {
3707 dma_pool_free(ha->dl_dma_pool,
3708 dsd_ptr->dsd_addr, dsd_ptr->dsd_list_dma);
3709 list_del(&dsd_ptr->list);
3710 kfree(dsd_ptr);
3711 }
3712 }
3713 }
3714
3715 if (ha->dl_dma_pool)
3716 dma_pool_destroy(ha->dl_dma_pool);
3717
3718 if (ha->fcp_cmnd_dma_pool)
3719 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
3720
3721 if (ha->ctx_mempool)
3722 mempool_destroy(ha->ctx_mempool);
3723
2d70c103
NB		 3724 qlt_mem_free(ha);
3725
e315cd28
AC		 3726 if (ha->init_cb)
3727 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size,
a9083016 3728 ha->init_cb, ha->init_cb_dma);
e315cd28
AC		 3729 vfree(ha->optrom_buffer);
3730 kfree(ha->nvram);
73208dfd 3731 kfree(ha->npiv_info);
7a67735b 3732 kfree(ha->swl);
5f16b331 3733 kfree(ha->loop_id_map);
1da177e4 3734
e8711085 3735 ha->srb_mempool = NULL;
a9083016 3736 ha->ctx_mempool = NULL;
1da177e4
LT		 3737 ha->sns_cmd = NULL;
3738 ha->sns_cmd_dma = 0;
3739 ha->ct_sns = NULL;
3740 ha->ct_sns_dma = 0;
3741 ha->ms_iocb = NULL;
3742 ha->ms_iocb_dma = 0;
1da177e4
LT		 3743 ha->init_cb = NULL;
3744 ha->init_cb_dma = 0;
b64b0e8f
AV		 3745 ha->ex_init_cb = NULL;
3746 ha->ex_init_cb_dma = 0;
5ff1d584
AV		 3747 ha->async_pd = NULL;
3748 ha->async_pd_dma = 0;
1da177e4
LT		 3749
3750 ha->s_dma_pool = NULL;
a9083016
GM		 3751 ha->dl_dma_pool = NULL;
3752 ha->fcp_cmnd_dma_pool = NULL;
1da177e4 3753
1da177e4
LT		 3754 ha->gid_list = NULL;
3755 ha->gid_list_dma = 0;
2d70c103
NB		 3756
3757 ha->tgt.atio_ring = NULL;
3758 ha->tgt.atio_dma = 0;
3759 ha->tgt.tgt_vp_map = NULL;
e315cd28 3760}
1da177e4 3761
e315cd28
AC		 3762struct scsi_qla_host *qla2x00_create_host(struct scsi_host_template *sht,
3763 struct qla_hw_data *ha)
3764{
3765 struct Scsi_Host *host;
3766 struct scsi_qla_host *vha = NULL;
854165f4 3767
e315cd28
AC		 3768 host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t));
3769 if (host == NULL) {
7c3df132
SK		 3770 ql_log_pci(ql_log_fatal, ha->pdev, 0x0107,
3771 "Failed to allocate host from the scsi layer, aborting.\n");
e315cd28
AC		 3772 goto fail;
3773 }
3774
3775 /* Clear our data area */
3776 vha = shost_priv(host);
3777 memset(vha, 0, sizeof(scsi_qla_host_t));
3778
3779 vha->host = host;
3780 vha->host_no = host->host_no;
3781 vha->hw = ha;
3782
3783 INIT_LIST_HEAD(&vha->vp_fcports);
3784 INIT_LIST_HEAD(&vha->work_list);
3785 INIT_LIST_HEAD(&vha->list);
3786
f999f4c1
AV		 3787 spin_lock_init(&vha->work_lock);
3788
e315cd28 3789 sprintf(vha->host_str, "%s_%ld", QLA2XXX_DRIVER_NAME, vha->host_no);
7c3df132
SK		 3790 ql_dbg(ql_dbg_init, vha, 0x0041,
3791 "Allocated the host=%p hw=%p vha=%p dev_name=%s",
3792 vha->host, vha->hw, vha,
3793 dev_name(&(ha->pdev->dev)));
3794
e315cd28
AC		 3795 return vha;
3796
3797fail:
3798 return vha;
1da177e4
LT		 3799}
3800
01ef66bb 3801static struct qla_work_evt *
f999f4c1 3802qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type)
0971de7f
AV		 3803{
3804 struct qla_work_evt *e;
feafb7b1
AE		 3805 uint8_t bail;
3806
3807 QLA_VHA_MARK_BUSY(vha, bail);
3808 if (bail)
3809 return NULL;
0971de7f 3810
f999f4c1 3811 e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC);
feafb7b1
AE		 3812 if (!e) {
3813 QLA_VHA_MARK_NOT_BUSY(vha);
0971de7f 3814 return NULL;
feafb7b1 3815 }
0971de7f
AV		 3816
3817 INIT_LIST_HEAD(&e->list);
3818 e->type = type;
3819 e->flags = QLA_EVT_FLAG_FREE;
3820 return e;
3821}
3822
01ef66bb 3823static int
f999f4c1 3824qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e)
0971de7f 3825{
f999f4c1 3826 unsigned long flags;
0971de7f 3827
f999f4c1 3828 spin_lock_irqsave(&vha->work_lock, flags);
e315cd28 3829 list_add_tail(&e->list, &vha->work_list);
f999f4c1 3830 spin_unlock_irqrestore(&vha->work_lock, flags);
e315cd28 3831 qla2xxx_wake_dpc(vha);
f999f4c1 3832
0971de7f
AV		 3833 return QLA_SUCCESS;
3834}
3835
3836int
e315cd28 3837qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code,
0971de7f
AV		 3838 u32 data)
3839{
3840 struct qla_work_evt *e;
3841
f999f4c1 3842 e = qla2x00_alloc_work(vha, QLA_EVT_AEN);
0971de7f
AV		 3843 if (!e)
3844 return QLA_FUNCTION_FAILED;
3845
3846 e->u.aen.code = code;
3847 e->u.aen.data = data;
f999f4c1 3848 return qla2x00_post_work(vha, e);
0971de7f
AV		 3849}
3850
8a659571
AV		 3851int
3852qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb)
3853{
3854 struct qla_work_evt *e;
3855
f999f4c1 3856 e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK);
8a659571
AV		 3857 if (!e)
3858 return QLA_FUNCTION_FAILED;
3859
3860 memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t));
f999f4c1 3861 return qla2x00_post_work(vha, e);
8a659571
AV		 3862}
3863
ac280b67
AV		 3864#define qla2x00_post_async_work(name, type) \
3865int qla2x00_post_async_##name##_work( \
3866 struct scsi_qla_host *vha, \
3867 fc_port_t *fcport, uint16_t *data) \
3868{ \
3869 struct qla_work_evt *e; \
3870 \
3871 e = qla2x00_alloc_work(vha, type); \
3872 if (!e) \
3873 return QLA_FUNCTION_FAILED; \
3874 \
3875 e->u.logio.fcport = fcport; \
3876 if (data) { \
3877 e->u.logio.data[0] = data[0]; \
3878 e->u.logio.data[1] = data[1]; \
3879 } \
3880 return qla2x00_post_work(vha, e); \
3881}
3882
3883qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN);
3884qla2x00_post_async_work(login_done, QLA_EVT_ASYNC_LOGIN_DONE);
3885qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT);
3886qla2x00_post_async_work(logout_done, QLA_EVT_ASYNC_LOGOUT_DONE);
5ff1d584
AV		 3887qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC);
3888qla2x00_post_async_work(adisc_done, QLA_EVT_ASYNC_ADISC_DONE);
ac280b67 3889
3420d36c
AV		 3890int
3891qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code)
3892{
3893 struct qla_work_evt *e;
3894
3895 e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT);
3896 if (!e)
3897 return QLA_FUNCTION_FAILED;
3898
3899 e->u.uevent.code = code;
3900 return qla2x00_post_work(vha, e);
3901}
3902
3903static void
3904qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code)
3905{
3906 char event_string[40];
3907 char *envp[] = { event_string, NULL };
3908
3909 switch (code) {
3910 case QLA_UEVENT_CODE_FW_DUMP:
3911 snprintf(event_string, sizeof(event_string), "FW_DUMP=%ld",
3912 vha->host_no);
3913 break;
3914 default:
3915 /* do nothing */
3916 break;
3917 }
3918 kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp);
3919}
3920
8ae6d9c7
GM		 3921int
3922qlafx00_post_aenfx_work(struct scsi_qla_host *vha, uint32_t evtcode,
3923 uint32_t *data, int cnt)
3924{
3925 struct qla_work_evt *e;
3926
3927 e = qla2x00_alloc_work(vha, QLA_EVT_AENFX);
3928 if (!e)
3929 return QLA_FUNCTION_FAILED;
3930
3931 e->u.aenfx.evtcode = evtcode;
3932 e->u.aenfx.count = cnt;
3933 memcpy(e->u.aenfx.mbx, data, sizeof(*data) * cnt);
3934 return qla2x00_post_work(vha, e);
3935}
3936
ac280b67 3937void
e315cd28 3938qla2x00_do_work(struct scsi_qla_host *vha)
0971de7f 3939{
f999f4c1
AV		 3940 struct qla_work_evt *e, *tmp;
3941 unsigned long flags;
3942 LIST_HEAD(work);
0971de7f 3943
f999f4c1
AV		 3944 spin_lock_irqsave(&vha->work_lock, flags);
3945 list_splice_init(&vha->work_list, &work);
3946 spin_unlock_irqrestore(&vha->work_lock, flags);
3947
3948 list_for_each_entry_safe(e, tmp, &work, list) {
0971de7f 3949 list_del_init(&e->list);
0971de7f
AV		 3950
3951 switch (e->type) {
3952 case QLA_EVT_AEN:
e315cd28 3953 fc_host_post_event(vha->host, fc_get_event_number(),
0971de7f
AV		 3954 e->u.aen.code, e->u.aen.data);
3955 break;
8a659571
AV		 3956 case QLA_EVT_IDC_ACK:
3957 qla81xx_idc_ack(vha, e->u.idc_ack.mb);
3958 break;
ac280b67
AV		 3959 case QLA_EVT_ASYNC_LOGIN:
3960 qla2x00_async_login(vha, e->u.logio.fcport,
3961 e->u.logio.data);
3962 break;
3963 case QLA_EVT_ASYNC_LOGIN_DONE:
3964 qla2x00_async_login_done(vha, e->u.logio.fcport,
3965 e->u.logio.data);
3966 break;
3967 case QLA_EVT_ASYNC_LOGOUT:
3968 qla2x00_async_logout(vha, e->u.logio.fcport);
3969 break;
3970 case QLA_EVT_ASYNC_LOGOUT_DONE:
3971 qla2x00_async_logout_done(vha, e->u.logio.fcport,
3972 e->u.logio.data);
3973 break;
5ff1d584
AV		 3974 case QLA_EVT_ASYNC_ADISC:
3975 qla2x00_async_adisc(vha, e->u.logio.fcport,
3976 e->u.logio.data);
3977 break;
3978 case QLA_EVT_ASYNC_ADISC_DONE:
3979 qla2x00_async_adisc_done(vha, e->u.logio.fcport,
3980 e->u.logio.data);
3981 break;
3420d36c
AV		 3982 case QLA_EVT_UEVENT:
3983 qla2x00_uevent_emit(vha, e->u.uevent.code);
3984 break;
8ae6d9c7
GM		 3985 case QLA_EVT_AENFX:
3986 qlafx00_process_aen(vha, e);
3987 break;
0971de7f
AV		 3988 }
3989 if (e->flags & QLA_EVT_FLAG_FREE)
3990 kfree(e);
feafb7b1
AE		 3991
3992 /* For each work completed decrement vha ref count */
3993 QLA_VHA_MARK_NOT_BUSY(vha);
e315cd28 3994 }
e315cd28 3995}
f999f4c1 3996
e315cd28
AC		 3997/* Relogins all the fcports of a vport
3998 * Context: dpc thread
3999 */
4000void qla2x00_relogin(struct scsi_qla_host *vha)
4001{
4002 fc_port_t *fcport;
c6b2fca8 4003 int status;
e315cd28
AC		 4004 uint16_t next_loopid = 0;
4005 struct qla_hw_data *ha = vha->hw;
ac280b67 4006 uint16_t data[2];
e315cd28
AC		 4007
4008 list_for_each_entry(fcport, &vha->vp_fcports, list) {
4009 /*
4010 * If the port is not ONLINE then try to login
4011 * to it if we haven't run out of retries.
4012 */
5ff1d584
AV		 4013 if (atomic_read(&fcport->state) != FCS_ONLINE &&
4014 fcport->login_retry && !(fcport->flags & FCF_ASYNC_SENT)) {
ac280b67 4015 fcport->login_retry--;
e315cd28 4016 if (fcport->flags & FCF_FABRIC_DEVICE) {
f08b7251 4017 if (fcport->flags & FCF_FCP2_DEVICE)
e315cd28
AC		 4018 ha->isp_ops->fabric_logout(vha,
4019 fcport->loop_id,
4020 fcport->d_id.b.domain,
4021 fcport->d_id.b.area,
4022 fcport->d_id.b.al_pa);
4023
03bcfb57
JC		 4024 if (fcport->loop_id == FC_NO_LOOP_ID) {
4025 fcport->loop_id = next_loopid =
4026 ha->min_external_loopid;
4027 status = qla2x00_find_new_loop_id(
4028 vha, fcport);
4029 if (status != QLA_SUCCESS) {
4030 /* Ran out of IDs to use */
4031 break;
4032 }
4033 }
4034
ac280b67 4035 if (IS_ALOGIO_CAPABLE(ha)) {
5ff1d584 4036 fcport->flags |= FCF_ASYNC_SENT;
ac280b67
AV		 4037 data[0] = 0;
4038 data[1] = QLA_LOGIO_LOGIN_RETRIED;
4039 status = qla2x00_post_async_login_work(
4040 vha, fcport, data);
4041 if (status == QLA_SUCCESS)
4042 continue;
4043 /* Attempt a retry. */
4044 status = 1;
aaf4d3e2 4045 } else {
ac280b67
AV		 4046 status = qla2x00_fabric_login(vha,
4047 fcport, &next_loopid);
aaf4d3e2
SK		 4048 if (status == QLA_SUCCESS) {
4049 int status2;
4050 uint8_t opts;
4051
4052 opts = 0;
4053 if (fcport->flags &
4054 FCF_FCP2_DEVICE)
4055 opts |= BIT_1;
03003960
SK		 4056 status2 =
4057 qla2x00_get_port_database(
4058 vha, fcport, opts);
aaf4d3e2
SK		 4059 if (status2 != QLA_SUCCESS)
4060 status = 1;
4061 }
4062 }
e315cd28
AC		 4063 } else
4064 status = qla2x00_local_device_login(vha,
4065 fcport);
4066
e315cd28
AC		 4067 if (status == QLA_SUCCESS) {
4068 fcport->old_loop_id = fcport->loop_id;
4069
7c3df132
SK		 4070 ql_dbg(ql_dbg_disc, vha, 0x2003,
4071 "Port login OK: logged in ID 0x%x.\n",
4072 fcport->loop_id);
e315cd28
AC		 4073
4074 qla2x00_update_fcport(vha, fcport);
4075
4076 } else if (status == 1) {
4077 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
4078 /* retry the login again */
7c3df132
SK		 4079 ql_dbg(ql_dbg_disc, vha, 0x2007,
4080 "Retrying %d login again loop_id 0x%x.\n",
4081 fcport->login_retry, fcport->loop_id);
e315cd28
AC		 4082 } else {
4083 fcport->login_retry = 0;
4084 }
4085
4086 if (fcport->login_retry == 0 && status != QLA_SUCCESS)
5f16b331 4087 qla2x00_clear_loop_id(fcport);
e315cd28
AC		 4088 }
4089 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
4090 break;
0971de7f 4091 }
0971de7f
AV		 4092}
4093
7d613ac6
SV		 4094/* Schedule work on any of the dpc-workqueues */
4095void
4096qla83xx_schedule_work(scsi_qla_host_t *base_vha, int work_code)
4097{
4098 struct qla_hw_data *ha = base_vha->hw;
4099
4100 switch (work_code) {
4101 case MBA_IDC_AEN: /* 0x8200 */
4102 if (ha->dpc_lp_wq)
4103 queue_work(ha->dpc_lp_wq, &ha->idc_aen);
4104 break;
4105
4106 case QLA83XX_NIC_CORE_RESET: /* 0x1 */
4107 if (!ha->flags.nic_core_reset_hdlr_active) {
4108 if (ha->dpc_hp_wq)
4109 queue_work(ha->dpc_hp_wq, &ha->nic_core_reset);
4110 } else
4111 ql_dbg(ql_dbg_p3p, base_vha, 0xb05e,
4112 "NIC Core reset is already active. Skip "
4113 "scheduling it again.\n");
4114 break;
4115 case QLA83XX_IDC_STATE_HANDLER: /* 0x2 */
4116 if (ha->dpc_hp_wq)
4117 queue_work(ha->dpc_hp_wq, &ha->idc_state_handler);
4118 break;
4119 case QLA83XX_NIC_CORE_UNRECOVERABLE: /* 0x3 */
4120 if (ha->dpc_hp_wq)
4121 queue_work(ha->dpc_hp_wq, &ha->nic_core_unrecoverable);
4122 break;
4123 default:
4124 ql_log(ql_log_warn, base_vha, 0xb05f,
4125 "Unknow work-code=0x%x.\n", work_code);
4126 }
4127
4128 return;
4129}
4130
4131/* Work: Perform NIC Core Unrecoverable state handling */
4132void
4133qla83xx_nic_core_unrecoverable_work(struct work_struct *work)
4134{
4135 struct qla_hw_data *ha =
2ad1b67c 4136 container_of(work, struct qla_hw_data, nic_core_unrecoverable);
7d613ac6
SV		 4137 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4138 uint32_t dev_state = 0;
4139
4140 qla83xx_idc_lock(base_vha, 0);
4141 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4142 qla83xx_reset_ownership(base_vha);
4143 if (ha->flags.nic_core_reset_owner) {
4144 ha->flags.nic_core_reset_owner = 0;
4145 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
4146 QLA8XXX_DEV_FAILED);
4147 ql_log(ql_log_info, base_vha, 0xb060, "HW State: FAILED.\n");
4148 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
4149 }
4150 qla83xx_idc_unlock(base_vha, 0);
4151}
4152
4153/* Work: Execute IDC state handler */
4154void
4155qla83xx_idc_state_handler_work(struct work_struct *work)
4156{
4157 struct qla_hw_data *ha =
2ad1b67c 4158 container_of(work, struct qla_hw_data, idc_state_handler);
7d613ac6
SV		 4159 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4160 uint32_t dev_state = 0;
4161
4162 qla83xx_idc_lock(base_vha, 0);
4163 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4164 if (dev_state == QLA8XXX_DEV_FAILED ||
4165 dev_state == QLA8XXX_DEV_NEED_QUIESCENT)
4166 qla83xx_idc_state_handler(base_vha);
4167 qla83xx_idc_unlock(base_vha, 0);
4168}
4169
fa492630 4170static int
7d613ac6
SV		 4171qla83xx_check_nic_core_fw_alive(scsi_qla_host_t *base_vha)
4172{
4173 int rval = QLA_SUCCESS;
4174 unsigned long heart_beat_wait = jiffies + (1 * HZ);
4175 uint32_t heart_beat_counter1, heart_beat_counter2;
4176
4177 do {
4178 if (time_after(jiffies, heart_beat_wait)) {
4179 ql_dbg(ql_dbg_p3p, base_vha, 0xb07c,
4180 "Nic Core f/w is not alive.\n");
4181 rval = QLA_FUNCTION_FAILED;
4182 break;
4183 }
4184
4185 qla83xx_idc_lock(base_vha, 0);
4186 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
4187 &heart_beat_counter1);
4188 qla83xx_idc_unlock(base_vha, 0);
4189 msleep(100);
4190 qla83xx_idc_lock(base_vha, 0);
4191 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
4192 &heart_beat_counter2);
4193 qla83xx_idc_unlock(base_vha, 0);
4194 } while (heart_beat_counter1 == heart_beat_counter2);
4195
4196 return rval;
4197}
4198
4199/* Work: Perform NIC Core Reset handling */
4200void
4201qla83xx_nic_core_reset_work(struct work_struct *work)
4202{
4203 struct qla_hw_data *ha =
4204 container_of(work, struct qla_hw_data, nic_core_reset);
4205 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4206 uint32_t dev_state = 0;
4207
81178772
SK		 4208 if (IS_QLA2031(ha)) {
4209 if (qla2xxx_mctp_dump(base_vha) != QLA_SUCCESS)
4210 ql_log(ql_log_warn, base_vha, 0xb081,
4211 "Failed to dump mctp\n");
4212 return;
4213 }
4214
7d613ac6
SV		 4215 if (!ha->flags.nic_core_reset_hdlr_active) {
4216 if (qla83xx_check_nic_core_fw_alive(base_vha) == QLA_SUCCESS) {
4217 qla83xx_idc_lock(base_vha, 0);
4218 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE,
4219 &dev_state);
4220 qla83xx_idc_unlock(base_vha, 0);
4221 if (dev_state != QLA8XXX_DEV_NEED_RESET) {
4222 ql_dbg(ql_dbg_p3p, base_vha, 0xb07a,
4223 "Nic Core f/w is alive.\n");
4224 return;
4225 }
4226 }
4227
4228 ha->flags.nic_core_reset_hdlr_active = 1;
4229 if (qla83xx_nic_core_reset(base_vha)) {
4230 /* NIC Core reset failed. */
4231 ql_dbg(ql_dbg_p3p, base_vha, 0xb061,
4232 "NIC Core reset failed.\n");
4233 }
4234 ha->flags.nic_core_reset_hdlr_active = 0;
4235 }
4236}
4237
4238/* Work: Handle 8200 IDC aens */
4239void
4240qla83xx_service_idc_aen(struct work_struct *work)
4241{
4242 struct qla_hw_data *ha =
4243 container_of(work, struct qla_hw_data, idc_aen);
4244 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4245 uint32_t dev_state, idc_control;
4246
4247 qla83xx_idc_lock(base_vha, 0);
4248 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4249 qla83xx_rd_reg(base_vha, QLA83XX_IDC_CONTROL, &idc_control);
4250 qla83xx_idc_unlock(base_vha, 0);
4251 if (dev_state == QLA8XXX_DEV_NEED_RESET) {
4252 if (idc_control & QLA83XX_IDC_GRACEFUL_RESET) {
4253 ql_dbg(ql_dbg_p3p, base_vha, 0xb062,
4254 "Application requested NIC Core Reset.\n");
4255 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
4256 } else if (qla83xx_check_nic_core_fw_alive(base_vha) ==
4257 QLA_SUCCESS) {
4258 ql_dbg(ql_dbg_p3p, base_vha, 0xb07b,
4259 "Other protocol driver requested NIC Core Reset.\n");
4260 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
4261 }
4262 } else if (dev_state == QLA8XXX_DEV_FAILED ||
4263 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) {
4264 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
4265 }
4266}
4267
4268static void
4269qla83xx_wait_logic(void)
4270{
4271 int i;
4272
4273 /* Yield CPU */
4274 if (!in_interrupt()) {
4275 /*
4276 * Wait about 200ms before retrying again.
4277 * This controls the number of retries for single
4278 * lock operation.
4279 */
4280 msleep(100);
4281 schedule();
4282 } else {
4283 for (i = 0; i < 20; i++)
4284 cpu_relax(); /* This a nop instr on i386 */
4285 }
4286}
4287
fa492630 4288static int
7d613ac6
SV		 4289qla83xx_force_lock_recovery(scsi_qla_host_t *base_vha)
4290{
4291 int rval;
4292 uint32_t data;
4293 uint32_t idc_lck_rcvry_stage_mask = 0x3;
4294 uint32_t idc_lck_rcvry_owner_mask = 0x3c;
4295 struct qla_hw_data *ha = base_vha->hw;
6c315553
SK		 4296 ql_dbg(ql_dbg_p3p, base_vha, 0xb086,
4297 "Trying force recovery of the IDC lock.\n");
7d613ac6
SV		 4298
4299 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, &data);
4300 if (rval)
4301 return rval;
4302
4303 if ((data & idc_lck_rcvry_stage_mask) > 0) {
4304 return QLA_SUCCESS;
4305 } else {
4306 data = (IDC_LOCK_RECOVERY_STAGE1) | (ha->portnum << 2);
4307 rval = qla83xx_wr_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
4308 data);
4309 if (rval)
4310 return rval;
4311
4312 msleep(200);
4313
4314 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
4315 &data);
4316 if (rval)
4317 return rval;
4318
4319 if (((data & idc_lck_rcvry_owner_mask) >> 2) == ha->portnum) {
4320 data &= (IDC_LOCK_RECOVERY_STAGE2 |
4321 ~(idc_lck_rcvry_stage_mask));
4322 rval = qla83xx_wr_reg(base_vha,
4323 QLA83XX_IDC_LOCK_RECOVERY, data);
4324 if (rval)
4325 return rval;
4326
4327 /* Forcefully perform IDC UnLock */
4328 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK,
4329 &data);
4330 if (rval)
4331 return rval;
4332 /* Clear lock-id by setting 0xff */
4333 rval = qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
4334 0xff);
4335 if (rval)
4336 return rval;
4337 /* Clear lock-recovery by setting 0x0 */
4338 rval = qla83xx_wr_reg(base_vha,
4339 QLA83XX_IDC_LOCK_RECOVERY, 0x0);
4340 if (rval)
4341 return rval;
4342 } else
4343 return QLA_SUCCESS;
4344 }
4345
4346 return rval;
4347}
4348
fa492630 4349static int
7d613ac6
SV		 4350qla83xx_idc_lock_recovery(scsi_qla_host_t *base_vha)
4351{
4352 int rval = QLA_SUCCESS;
4353 uint32_t o_drv_lockid, n_drv_lockid;
4354 unsigned long lock_recovery_timeout;
4355
4356 lock_recovery_timeout = jiffies + QLA83XX_MAX_LOCK_RECOVERY_WAIT;
4357retry_lockid:
4358 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &o_drv_lockid);
4359 if (rval)
4360 goto exit;
4361
4362 /* MAX wait time before forcing IDC Lock recovery = 2 secs */
4363 if (time_after_eq(jiffies, lock_recovery_timeout)) {
4364 if (qla83xx_force_lock_recovery(base_vha) == QLA_SUCCESS)
4365 return QLA_SUCCESS;
4366 else
4367 return QLA_FUNCTION_FAILED;
4368 }
4369
4370 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &n_drv_lockid);
4371 if (rval)
4372 goto exit;
4373
4374 if (o_drv_lockid == n_drv_lockid) {
4375 qla83xx_wait_logic();
4376 goto retry_lockid;
4377 } else
4378 return QLA_SUCCESS;
4379
4380exit:
4381 return rval;
4382}
4383
4384void
4385qla83xx_idc_lock(scsi_qla_host_t *base_vha, uint16_t requester_id)
4386{
4387 uint16_t options = (requester_id << 15) | BIT_6;
4388 uint32_t data;
6c315553 4389 uint32_t lock_owner;
7d613ac6
SV		 4390 struct qla_hw_data *ha = base_vha->hw;
4391
4392 /* IDC-lock implementation using driver-lock/lock-id remote registers */
4393retry_lock:
4394 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCK, &data)
4395 == QLA_SUCCESS) {
4396 if (data) {
4397 /* Setting lock-id to our function-number */
4398 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
4399 ha->portnum);
4400 } else {
6c315553
SK		 4401 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID,
4402 &lock_owner);
7d613ac6 4403 ql_dbg(ql_dbg_p3p, base_vha, 0xb063,
6c315553
SK		 4404 "Failed to acquire IDC lock, acquired by %d, "
4405 "retrying...\n", lock_owner);
7d613ac6
SV		 4406
4407 /* Retry/Perform IDC-Lock recovery */
4408 if (qla83xx_idc_lock_recovery(base_vha)
4409 == QLA_SUCCESS) {
4410 qla83xx_wait_logic();
4411 goto retry_lock;
4412 } else
4413 ql_log(ql_log_warn, base_vha, 0xb075,
4414 "IDC Lock recovery FAILED.\n");
4415 }
4416
4417 }
4418
4419 return;
4420
4421 /* XXX: IDC-lock implementation using access-control mbx */
4422retry_lock2:
4423 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
4424 ql_dbg(ql_dbg_p3p, base_vha, 0xb072,
4425 "Failed to acquire IDC lock. retrying...\n");
4426 /* Retry/Perform IDC-Lock recovery */
4427 if (qla83xx_idc_lock_recovery(base_vha) == QLA_SUCCESS) {
4428 qla83xx_wait_logic();
4429 goto retry_lock2;
4430 } else
4431 ql_log(ql_log_warn, base_vha, 0xb076,
4432 "IDC Lock recovery FAILED.\n");
4433 }
4434
4435 return;
4436}
4437
4438void
4439qla83xx_idc_unlock(scsi_qla_host_t *base_vha, uint16_t requester_id)
4440{
4441 uint16_t options = (requester_id << 15) | BIT_7, retry;
4442 uint32_t data;
4443 struct qla_hw_data *ha = base_vha->hw;
4444
4445 /* IDC-unlock implementation using driver-unlock/lock-id
4446 * remote registers
4447 */
4448 retry = 0;
4449retry_unlock:
4450 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &data)
4451 == QLA_SUCCESS) {
4452 if (data == ha->portnum) {
4453 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, &data);
4454 /* Clearing lock-id by setting 0xff */
4455 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 0xff);
4456 } else if (retry < 10) {
4457 /* SV: XXX: IDC unlock retrying needed here? */
4458
4459 /* Retry for IDC-unlock */
4460 qla83xx_wait_logic();
4461 retry++;
4462 ql_dbg(ql_dbg_p3p, base_vha, 0xb064,
4463 "Failed to release IDC lock, retyring=%d\n", retry);
4464 goto retry_unlock;
4465 }
4466 } else if (retry < 10) {
4467 /* Retry for IDC-unlock */
4468 qla83xx_wait_logic();
4469 retry++;
4470 ql_dbg(ql_dbg_p3p, base_vha, 0xb065,
4471 "Failed to read drv-lockid, retyring=%d\n", retry);
4472 goto retry_unlock;
4473 }
4474
4475 return;
4476
4477 /* XXX: IDC-unlock implementation using access-control mbx */
4478 retry = 0;
4479retry_unlock2:
4480 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
4481 if (retry < 10) {
4482 /* Retry for IDC-unlock */
4483 qla83xx_wait_logic();
4484 retry++;
4485 ql_dbg(ql_dbg_p3p, base_vha, 0xb066,
4486 "Failed to release IDC lock, retyring=%d\n", retry);
4487 goto retry_unlock2;
4488 }
4489 }
4490
4491 return;
4492}
4493
4494int
4495__qla83xx_set_drv_presence(scsi_qla_host_t *vha)
4496{
4497 int rval = QLA_SUCCESS;
4498 struct qla_hw_data *ha = vha->hw;
4499 uint32_t drv_presence;
4500
4501 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
4502 if (rval == QLA_SUCCESS) {
4503 drv_presence |= (1 << ha->portnum);
4504 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
4505 drv_presence);
4506 }
4507
4508 return rval;
4509}
4510
4511int
4512qla83xx_set_drv_presence(scsi_qla_host_t *vha)
4513{
4514 int rval = QLA_SUCCESS;
4515
4516 qla83xx_idc_lock(vha, 0);
4517 rval = __qla83xx_set_drv_presence(vha);
4518 qla83xx_idc_unlock(vha, 0);
4519
4520 return rval;
4521}
4522
4523int
4524__qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
4525{
4526 int rval = QLA_SUCCESS;
4527 struct qla_hw_data *ha = vha->hw;
4528 uint32_t drv_presence;
4529
4530 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
4531 if (rval == QLA_SUCCESS) {
4532 drv_presence &= ~(1 << ha->portnum);
4533 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
4534 drv_presence);
4535 }
4536
4537 return rval;
4538}
4539
4540int
4541qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
4542{
4543 int rval = QLA_SUCCESS;
4544
4545 qla83xx_idc_lock(vha, 0);
4546 rval = __qla83xx_clear_drv_presence(vha);
4547 qla83xx_idc_unlock(vha, 0);
4548
4549 return rval;
4550}
4551
fa492630 4552static void
7d613ac6
SV		 4553qla83xx_need_reset_handler(scsi_qla_host_t *vha)
4554{
4555 struct qla_hw_data *ha = vha->hw;
4556 uint32_t drv_ack, drv_presence;
4557 unsigned long ack_timeout;
4558
4559 /* Wait for IDC ACK from all functions (DRV-ACK == DRV-PRESENCE) */
4560 ack_timeout = jiffies + (ha->fcoe_reset_timeout * HZ);
4561 while (1) {
4562 qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
4563 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
807fb6d8 4564 if ((drv_ack & drv_presence) == drv_presence)
7d613ac6
SV		 4565 break;
4566
4567 if (time_after_eq(jiffies, ack_timeout)) {
4568 ql_log(ql_log_warn, vha, 0xb067,
4569 "RESET ACK TIMEOUT! drv_presence=0x%x "
4570 "drv_ack=0x%x\n", drv_presence, drv_ack);
4571 /*
4572 * The function(s) which did not ack in time are forced
4573 * to withdraw any further participation in the IDC
4574 * reset.
4575 */
4576 if (drv_ack != drv_presence)
4577 qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
4578 drv_ack);
4579 break;
4580 }
4581
4582 qla83xx_idc_unlock(vha, 0);
4583 msleep(1000);
4584 qla83xx_idc_lock(vha, 0);
4585 }
4586
4587 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_COLD);
4588 ql_log(ql_log_info, vha, 0xb068, "HW State: COLD/RE-INIT.\n");
4589}
4590
fa492630 4591static int
7d613ac6
SV		 4592qla83xx_device_bootstrap(scsi_qla_host_t *vha)
4593{
4594 int rval = QLA_SUCCESS;
4595 uint32_t idc_control;
4596
4597 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_INITIALIZING);
4598 ql_log(ql_log_info, vha, 0xb069, "HW State: INITIALIZING.\n");
4599
4600 /* Clearing IDC-Control Graceful-Reset Bit before resetting f/w */
4601 __qla83xx_get_idc_control(vha, &idc_control);
4602 idc_control &= ~QLA83XX_IDC_GRACEFUL_RESET;
4603 __qla83xx_set_idc_control(vha, 0);
4604
4605 qla83xx_idc_unlock(vha, 0);
4606 rval = qla83xx_restart_nic_firmware(vha);
4607 qla83xx_idc_lock(vha, 0);
4608
4609 if (rval != QLA_SUCCESS) {
4610 ql_log(ql_log_fatal, vha, 0xb06a,
4611 "Failed to restart NIC f/w.\n");
4612 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_FAILED);
4613 ql_log(ql_log_info, vha, 0xb06b, "HW State: FAILED.\n");
4614 } else {
4615 ql_dbg(ql_dbg_p3p, vha, 0xb06c,
4616 "Success in restarting nic f/w.\n");
4617 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_READY);
4618 ql_log(ql_log_info, vha, 0xb06d, "HW State: READY.\n");
4619 }
4620
4621 return rval;
4622}
4623
4624/* Assumes idc_lock always held on entry */
4625int
4626qla83xx_idc_state_handler(scsi_qla_host_t *base_vha)
4627{
4628 struct qla_hw_data *ha = base_vha->hw;
4629 int rval = QLA_SUCCESS;
4630 unsigned long dev_init_timeout;
4631 uint32_t dev_state;
4632
4633 /* Wait for MAX-INIT-TIMEOUT for the device to go ready */
4634 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ);
4635
4636 while (1) {
4637
4638 if (time_after_eq(jiffies, dev_init_timeout)) {
4639 ql_log(ql_log_warn, base_vha, 0xb06e,
4640 "Initialization TIMEOUT!\n");
4641 /* Init timeout. Disable further NIC Core
4642 * communication.
4643 */
4644 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
4645 QLA8XXX_DEV_FAILED);
4646 ql_log(ql_log_info, base_vha, 0xb06f,
4647 "HW State: FAILED.\n");
4648 }
4649
4650 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4651 switch (dev_state) {
4652 case QLA8XXX_DEV_READY:
4653 if (ha->flags.nic_core_reset_owner)
4654 qla83xx_idc_audit(base_vha,
4655 IDC_AUDIT_COMPLETION);
4656 ha->flags.nic_core_reset_owner = 0;
4657 ql_dbg(ql_dbg_p3p, base_vha, 0xb070,
4658 "Reset_owner reset by 0x%x.\n",
4659 ha->portnum);
4660 goto exit;
4661 case QLA8XXX_DEV_COLD:
4662 if (ha->flags.nic_core_reset_owner)
4663 rval = qla83xx_device_bootstrap(base_vha);
4664 else {
4665 /* Wait for AEN to change device-state */
4666 qla83xx_idc_unlock(base_vha, 0);
4667 msleep(1000);
4668 qla83xx_idc_lock(base_vha, 0);
4669 }
4670 break;
4671 case QLA8XXX_DEV_INITIALIZING:
4672 /* Wait for AEN to change device-state */
4673 qla83xx_idc_unlock(base_vha, 0);
4674 msleep(1000);
4675 qla83xx_idc_lock(base_vha, 0);
4676 break;
4677 case QLA8XXX_DEV_NEED_RESET:
4678 if (!ql2xdontresethba && ha->flags.nic_core_reset_owner)
4679 qla83xx_need_reset_handler(base_vha);
4680 else {
4681 /* Wait for AEN to change device-state */
4682 qla83xx_idc_unlock(base_vha, 0);
4683 msleep(1000);
4684 qla83xx_idc_lock(base_vha, 0);
4685 }
4686 /* reset timeout value after need reset handler */
4687 dev_init_timeout = jiffies +
4688 (ha->fcoe_dev_init_timeout * HZ);
4689 break;
4690 case QLA8XXX_DEV_NEED_QUIESCENT:
4691 /* XXX: DEBUG for now */
4692 qla83xx_idc_unlock(base_vha, 0);
4693 msleep(1000);
4694 qla83xx_idc_lock(base_vha, 0);
4695 break;
4696 case QLA8XXX_DEV_QUIESCENT:
4697 /* XXX: DEBUG for now */
4698 if (ha->flags.quiesce_owner)
4699 goto exit;
4700
4701 qla83xx_idc_unlock(base_vha, 0);
4702 msleep(1000);
4703 qla83xx_idc_lock(base_vha, 0);
4704 dev_init_timeout = jiffies +
4705 (ha->fcoe_dev_init_timeout * HZ);
4706 break;
4707 case QLA8XXX_DEV_FAILED:
4708 if (ha->flags.nic_core_reset_owner)
4709 qla83xx_idc_audit(base_vha,
4710 IDC_AUDIT_COMPLETION);
4711 ha->flags.nic_core_reset_owner = 0;
4712 __qla83xx_clear_drv_presence(base_vha);
4713 qla83xx_idc_unlock(base_vha, 0);
4714 qla8xxx_dev_failed_handler(base_vha);
4715 rval = QLA_FUNCTION_FAILED;
4716 qla83xx_idc_lock(base_vha, 0);
4717 goto exit;
4718 case QLA8XXX_BAD_VALUE:
4719 qla83xx_idc_unlock(base_vha, 0);
4720 msleep(1000);
4721 qla83xx_idc_lock(base_vha, 0);
4722 break;
4723 default:
4724 ql_log(ql_log_warn, base_vha, 0xb071,
4725 "Unknow Device State: %x.\n", dev_state);
4726 qla83xx_idc_unlock(base_vha, 0);
4727 qla8xxx_dev_failed_handler(base_vha);
4728 rval = QLA_FUNCTION_FAILED;
4729 qla83xx_idc_lock(base_vha, 0);
4730 goto exit;
4731 }
4732 }
4733
4734exit:
4735 return rval;
4736}
4737
1da177e4
LT		 4738/**************************************************************************
4739* qla2x00_do_dpc
4740* This kernel thread is a task that is schedule by the interrupt handler
4741* to perform the background processing for interrupts.
4742*
4743* Notes:
4744* This task always run in the context of a kernel thread. It
4745* is kick-off by the driver's detect code and starts up
4746* up one per adapter. It immediately goes to sleep and waits for
4747* some fibre event. When either the interrupt handler or
4748* the timer routine detects a event it will one of the task
4749* bits then wake us up.
4750**************************************************************************/
4751static int
4752qla2x00_do_dpc(void *data)
4753{
2c3dfe3f 4754 int rval;
e315cd28
AC		 4755 scsi_qla_host_t *base_vha;
4756 struct qla_hw_data *ha;
1da177e4 4757
e315cd28
AC		 4758 ha = (struct qla_hw_data *)data;
4759 base_vha = pci_get_drvdata(ha->pdev);
1da177e4 4760
1da177e4
LT		 4761 set_user_nice(current, -20);
4762
563585ec 4763 set_current_state(TASK_INTERRUPTIBLE);
39a11240 4764 while (!kthread_should_stop()) {
7c3df132
SK		 4765 ql_dbg(ql_dbg_dpc, base_vha, 0x4000,
4766 "DPC handler sleeping.\n");
1da177e4 4767
39a11240
CH		 4768 schedule();
4769 __set_current_state(TASK_RUNNING);
1da177e4 4770
c142caf0
AV		 4771 if (!base_vha->flags.init_done || ha->flags.mbox_busy)
4772 goto end_loop;
1da177e4 4773
85880801 4774 if (ha->flags.eeh_busy) {
7c3df132
SK		 4775 ql_dbg(ql_dbg_dpc, base_vha, 0x4003,
4776 "eeh_busy=%d.\n", ha->flags.eeh_busy);
c142caf0 4777 goto end_loop;
85880801
AV		 4778 }
4779
1da177e4
LT		 4780 ha->dpc_active = 1;
4781
5f28d2d7
SK		 4782 ql_dbg(ql_dbg_dpc + ql_dbg_verbose, base_vha, 0x4001,
4783 "DPC handler waking up, dpc_flags=0x%lx.\n",
4784 base_vha->dpc_flags);
1da177e4 4785
e315cd28 4786 qla2x00_do_work(base_vha);
0971de7f 4787
7ec0effd
AD		 4788 if (IS_P3P_TYPE(ha)) {
4789 if (IS_QLA8044(ha)) {
4790 if (test_and_clear_bit(ISP_UNRECOVERABLE,
4791 &base_vha->dpc_flags)) {
4792 qla8044_idc_lock(ha);
4793 qla8044_wr_direct(base_vha,
4794 QLA8044_CRB_DEV_STATE_INDEX,
4795 QLA8XXX_DEV_FAILED);
4796 qla8044_idc_unlock(ha);
4797 ql_log(ql_log_info, base_vha, 0x4004,
4798 "HW State: FAILED.\n");
4799 qla8044_device_state_handler(base_vha);
4800 continue;
4801 }
4802
4803 } else {
4804 if (test_and_clear_bit(ISP_UNRECOVERABLE,
4805 &base_vha->dpc_flags)) {
4806 qla82xx_idc_lock(ha);
4807 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
4808 QLA8XXX_DEV_FAILED);
4809 qla82xx_idc_unlock(ha);
4810 ql_log(ql_log_info, base_vha, 0x0151,
4811 "HW State: FAILED.\n");
4812 qla82xx_device_state_handler(base_vha);
4813 continue;
4814 }
a9083016
GM		 4815 }
4816
4817 if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED,
4818 &base_vha->dpc_flags)) {
4819
7c3df132
SK		 4820 ql_dbg(ql_dbg_dpc, base_vha, 0x4005,
4821 "FCoE context reset scheduled.\n");
a9083016
GM		 4822 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
4823 &base_vha->dpc_flags))) {
4824 if (qla82xx_fcoe_ctx_reset(base_vha)) {
4825 /* FCoE-ctx reset failed.
4826 * Escalate to chip-reset
4827 */
4828 set_bit(ISP_ABORT_NEEDED,
4829 &base_vha->dpc_flags);
4830 }
4831 clear_bit(ABORT_ISP_ACTIVE,
4832 &base_vha->dpc_flags);
4833 }
4834
7c3df132
SK		 4835 ql_dbg(ql_dbg_dpc, base_vha, 0x4006,
4836 "FCoE context reset end.\n");
a9083016 4837 }
8ae6d9c7
GM		 4838 } else if (IS_QLAFX00(ha)) {
4839 if (test_and_clear_bit(ISP_UNRECOVERABLE,
4840 &base_vha->dpc_flags)) {
4841 ql_dbg(ql_dbg_dpc, base_vha, 0x4020,
4842 "Firmware Reset Recovery\n");
4843 if (qlafx00_reset_initialize(base_vha)) {
4844 /* Failed. Abort isp later. */
4845 if (!test_bit(UNLOADING,
4846 &base_vha->dpc_flags))
4847 set_bit(ISP_UNRECOVERABLE,
4848 &base_vha->dpc_flags);
4849 ql_dbg(ql_dbg_dpc, base_vha,
4850 0x4021,
4851 "Reset Recovery Failed\n");
4852 }
4853 }
4854
4855 if (test_and_clear_bit(FX00_TARGET_SCAN,
4856 &base_vha->dpc_flags)) {
4857 ql_dbg(ql_dbg_dpc, base_vha, 0x4022,
4858 "ISPFx00 Target Scan scheduled\n");
4859 if (qlafx00_rescan_isp(base_vha)) {
4860 if (!test_bit(UNLOADING,
4861 &base_vha->dpc_flags))
4862 set_bit(ISP_UNRECOVERABLE,
4863 &base_vha->dpc_flags);
4864 ql_dbg(ql_dbg_dpc, base_vha, 0x401e,
4865 "ISPFx00 Target Scan Failed\n");
4866 }
4867 ql_dbg(ql_dbg_dpc, base_vha, 0x401f,
4868 "ISPFx00 Target Scan End\n");
4869 }
a9083016
GM		 4870 }
4871
e315cd28
AC		 4872 if (test_and_clear_bit(ISP_ABORT_NEEDED,
4873 &base_vha->dpc_flags)) {
1da177e4 4874
7c3df132
SK		 4875 ql_dbg(ql_dbg_dpc, base_vha, 0x4007,
4876 "ISP abort scheduled.\n");
1da177e4 4877 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
e315cd28 4878 &base_vha->dpc_flags))) {
1da177e4 4879
a9083016 4880 if (ha->isp_ops->abort_isp(base_vha)) {
1da177e4
LT		 4881 /* failed. retry later */
4882 set_bit(ISP_ABORT_NEEDED,
e315cd28 4883 &base_vha->dpc_flags);
99363ef8 4884 }
e315cd28
AC		 4885 clear_bit(ABORT_ISP_ACTIVE,
4886 &base_vha->dpc_flags);
99363ef8
SJ		 4887 }
4888
7c3df132
SK		 4889 ql_dbg(ql_dbg_dpc, base_vha, 0x4008,
4890 "ISP abort end.\n");
1da177e4
LT		 4891 }
4892
a394aac8
DJ		 4893 if (test_and_clear_bit(FCPORT_UPDATE_NEEDED,
4894 &base_vha->dpc_flags)) {
e315cd28 4895 qla2x00_update_fcports(base_vha);
c9c5ced9 4896 }
d97994dc 4897
2d70c103
NB		 4898 if (test_bit(SCR_PENDING, &base_vha->dpc_flags)) {
4899 int ret;
4900 ret = qla2x00_send_change_request(base_vha, 0x3, 0);
4901 if (ret != QLA_SUCCESS)
4902 ql_log(ql_log_warn, base_vha, 0x121,
4903 "Failed to enable receiving of RSCN "
4904 "requests: 0x%x.\n", ret);
4905 clear_bit(SCR_PENDING, &base_vha->dpc_flags);
4906 }
4907
8ae6d9c7
GM		 4908 if (IS_QLAFX00(ha))
4909 goto loop_resync_check;
4910
579d12b5 4911 if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) {
7c3df132
SK		 4912 ql_dbg(ql_dbg_dpc, base_vha, 0x4009,
4913 "Quiescence mode scheduled.\n");
7ec0effd
AD		 4914 if (IS_P3P_TYPE(ha)) {
4915 if (IS_QLA82XX(ha))
4916 qla82xx_device_state_handler(base_vha);
4917 if (IS_QLA8044(ha))
4918 qla8044_device_state_handler(base_vha);
8fcd6b8b
CD		 4919 clear_bit(ISP_QUIESCE_NEEDED,
4920 &base_vha->dpc_flags);
4921 if (!ha->flags.quiesce_owner) {
4922 qla2x00_perform_loop_resync(base_vha);
7ec0effd
AD		 4923 if (IS_QLA82XX(ha)) {
4924 qla82xx_idc_lock(ha);
4925 qla82xx_clear_qsnt_ready(
4926 base_vha);
4927 qla82xx_idc_unlock(ha);
4928 } else if (IS_QLA8044(ha)) {
4929 qla8044_idc_lock(ha);
4930 qla8044_clear_qsnt_ready(
4931 base_vha);
4932 qla8044_idc_unlock(ha);
4933 }
8fcd6b8b
CD		 4934 }
4935 } else {
4936 clear_bit(ISP_QUIESCE_NEEDED,
4937 &base_vha->dpc_flags);
4938 qla2x00_quiesce_io(base_vha);
579d12b5 4939 }
7c3df132
SK		 4940 ql_dbg(ql_dbg_dpc, base_vha, 0x400a,
4941 "Quiescence mode end.\n");
579d12b5
SK		 4942 }
4943
e315cd28 4944 if (test_and_clear_bit(RESET_MARKER_NEEDED,
8ae6d9c7 4945 &base_vha->dpc_flags) &&
e315cd28 4946 (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) {
1da177e4 4947
7c3df132
SK		 4948 ql_dbg(ql_dbg_dpc, base_vha, 0x400b,
4949 "Reset marker scheduled.\n");
e315cd28
AC		 4950 qla2x00_rst_aen(base_vha);
4951 clear_bit(RESET_ACTIVE, &base_vha->dpc_flags);
7c3df132
SK		 4952 ql_dbg(ql_dbg_dpc, base_vha, 0x400c,
4953 "Reset marker end.\n");
1da177e4
LT		 4954 }
4955
4956 /* Retry each device up to login retry count */
e315cd28
AC		 4957 if ((test_and_clear_bit(RELOGIN_NEEDED,
4958 &base_vha->dpc_flags)) &&
4959 !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) &&
4960 atomic_read(&base_vha->loop_state) != LOOP_DOWN) {
1da177e4 4961
7c3df132
SK		 4962 ql_dbg(ql_dbg_dpc, base_vha, 0x400d,
4963 "Relogin scheduled.\n");
e315cd28 4964 qla2x00_relogin(base_vha);
7c3df132
SK		 4965 ql_dbg(ql_dbg_dpc, base_vha, 0x400e,
4966 "Relogin end.\n");
1da177e4 4967 }
8ae6d9c7 4968loop_resync_check:
e315cd28 4969 if (test_and_clear_bit(LOOP_RESYNC_NEEDED,
8ae6d9c7 4970 &base_vha->dpc_flags)) {
1da177e4 4971
7c3df132
SK		 4972 ql_dbg(ql_dbg_dpc, base_vha, 0x400f,
4973 "Loop resync scheduled.\n");
1da177e4
LT		 4974
4975 if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE,
e315cd28 4976 &base_vha->dpc_flags))) {
1da177e4 4977
e315cd28 4978 rval = qla2x00_loop_resync(base_vha);
1da177e4 4979
e315cd28
AC		 4980 clear_bit(LOOP_RESYNC_ACTIVE,
4981 &base_vha->dpc_flags);
1da177e4
LT		 4982 }
4983
7c3df132
SK		 4984 ql_dbg(ql_dbg_dpc, base_vha, 0x4010,
4985 "Loop resync end.\n");
1da177e4
LT		 4986 }
4987
8ae6d9c7
GM		 4988 if (IS_QLAFX00(ha))
4989 goto intr_on_check;
4990
e315cd28
AC		 4991 if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) &&
4992 atomic_read(&base_vha->loop_state) == LOOP_READY) {
4993 clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags);
4994 qla2xxx_flash_npiv_conf(base_vha);
272976ca
AV		 4995 }
4996
3c290d0b
CD		 4997 if (test_and_clear_bit(HOST_RAMP_DOWN_QUEUE_DEPTH,
4998 &base_vha->dpc_flags)) {
4999 /* Prevents simultaneous ramp up and down */
5000 clear_bit(HOST_RAMP_UP_QUEUE_DEPTH,
5001 &base_vha->dpc_flags);
5002 qla2x00_host_ramp_down_queuedepth(base_vha);
5003 }
5004
5005 if (test_and_clear_bit(HOST_RAMP_UP_QUEUE_DEPTH,
5006 &base_vha->dpc_flags))
5007 qla2x00_host_ramp_up_queuedepth(base_vha);
8ae6d9c7 5008intr_on_check:
1da177e4 5009 if (!ha->interrupts_on)
fd34f556 5010 ha->isp_ops->enable_intrs(ha);
1da177e4 5011
e315cd28
AC		 5012 if (test_and_clear_bit(BEACON_BLINK_NEEDED,
5013 &base_vha->dpc_flags))
5014 ha->isp_ops->beacon_blink(base_vha);
f6df144c 5015
8ae6d9c7
GM		 5016 if (!IS_QLAFX00(ha))
5017 qla2x00_do_dpc_all_vps(base_vha);
2c3dfe3f 5018
1da177e4 5019 ha->dpc_active = 0;
c142caf0 5020end_loop:
563585ec 5021 set_current_state(TASK_INTERRUPTIBLE);
1da177e4 5022 } /* End of while(1) */
563585ec 5023 __set_current_state(TASK_RUNNING);
1da177e4 5024
7c3df132
SK		 5025 ql_dbg(ql_dbg_dpc, base_vha, 0x4011,
5026 "DPC handler exiting.\n");
1da177e4
LT		 5027
5028 /*
5029 * Make sure that nobody tries to wake us up again.
5030 */
1da177e4
LT		 5031 ha->dpc_active = 0;
5032
ac280b67
AV		 5033 /* Cleanup any residual CTX SRBs. */
5034 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
5035
39a11240
CH		 5036 return 0;
5037}
5038
5039void
e315cd28 5040qla2xxx_wake_dpc(struct scsi_qla_host *vha)
39a11240 5041{
e315cd28 5042 struct qla_hw_data *ha = vha->hw;
c795c1e4
AV		 5043 struct task_struct *t = ha->dpc_thread;
5044
e315cd28 5045 if (!test_bit(UNLOADING, &vha->dpc_flags) && t)
c795c1e4 5046 wake_up_process(t);
1da177e4
LT		 5047}
5048
1da177e4
LT		 5049/*
5050* qla2x00_rst_aen
5051* Processes asynchronous reset.
5052*
5053* Input:
5054* ha = adapter block pointer.
5055*/
5056static void
e315cd28 5057qla2x00_rst_aen(scsi_qla_host_t *vha)
1da177e4 5058{
e315cd28
AC		 5059 if (vha->flags.online && !vha->flags.reset_active &&
5060 !atomic_read(&vha->loop_down_timer) &&
5061 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) {
1da177e4 5062 do {
e315cd28 5063 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
1da177e4
LT		 5064
5065 /*
5066 * Issue marker command only when we are going to start
5067 * the I/O.
5068 */
e315cd28
AC		 5069 vha->marker_needed = 1;
5070 } while (!atomic_read(&vha->loop_down_timer) &&
5071 (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)));
1da177e4
LT		 5072 }
5073}
5074
1da177e4
LT		 5075/**************************************************************************
5076* qla2x00_timer
5077*
5078* Description:
5079* One second timer
5080*
5081* Context: Interrupt
5082***************************************************************************/
2c3dfe3f 5083void
e315cd28 5084qla2x00_timer(scsi_qla_host_t *vha)
1da177e4 5085{
1da177e4 5086 unsigned long cpu_flags = 0;
1da177e4
LT		 5087 int start_dpc = 0;
5088 int index;
5089 srb_t *sp;
85880801 5090 uint16_t w;
e315cd28 5091 struct qla_hw_data *ha = vha->hw;
73208dfd 5092 struct req_que *req;
85880801 5093
a5b36321 5094 if (ha->flags.eeh_busy) {
7c3df132
SK		 5095 ql_dbg(ql_dbg_timer, vha, 0x6000,
5096 "EEH = %d, restarting timer.\n",
5097 ha->flags.eeh_busy);
a5b36321
LC		 5098 qla2x00_restart_timer(vha, WATCH_INTERVAL);
5099 return;
5100 }
5101
85880801
AV		 5102 /* Hardware read to raise pending EEH errors during mailbox waits. */
5103 if (!pci_channel_offline(ha->pdev))
5104 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w);
1da177e4 5105
cefcaba6 5106 /* Make sure qla82xx_watchdog is run only for physical port */
7ec0effd 5107 if (!vha->vp_idx && IS_P3P_TYPE(ha)) {
579d12b5
SK		 5108 if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags))
5109 start_dpc++;
7ec0effd
AD		 5110 if (IS_QLA82XX(ha))
5111 qla82xx_watchdog(vha);
5112 else if (IS_QLA8044(ha))
5113 qla8044_watchdog(vha);
579d12b5
SK		 5114 }
5115
8ae6d9c7
GM		 5116 if (!vha->vp_idx && IS_QLAFX00(ha))
5117 qlafx00_timer_routine(vha);
5118
1da177e4 5119 /* Loop down handler. */
e315cd28 5120 if (atomic_read(&vha->loop_down_timer) > 0 &&
8f7daead
GM		 5121 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) &&
5122 !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags))
e315cd28 5123 && vha->flags.online) {
1da177e4 5124
e315cd28
AC		 5125 if (atomic_read(&vha->loop_down_timer) ==
5126 vha->loop_down_abort_time) {
1da177e4 5127
7c3df132
SK		 5128 ql_log(ql_log_info, vha, 0x6008,
5129 "Loop down - aborting the queues before time expires.\n");
1da177e4 5130
e315cd28
AC		 5131 if (!IS_QLA2100(ha) && vha->link_down_timeout)
5132 atomic_set(&vha->loop_state, LOOP_DEAD);
1da177e4 5133
f08b7251
AV		 5134 /*
5135 * Schedule an ISP abort to return any FCP2-device
5136 * commands.
5137 */
2c3dfe3f 5138 /* NPIV - scan physical port only */
e315cd28 5139 if (!vha->vp_idx) {
2c3dfe3f
SJ		 5140 spin_lock_irqsave(&ha->hardware_lock,
5141 cpu_flags);
73208dfd 5142 req = ha->req_q_map[0];
2c3dfe3f 5143 for (index = 1;
8d93f550 5144 index < req->num_outstanding_cmds;
2c3dfe3f
SJ		 5145 index++) {
5146 fc_port_t *sfcp;
5147
e315cd28 5148 sp = req->outstanding_cmds[index];
2c3dfe3f
SJ		 5149 if (!sp)
5150 continue;
9ba56b95 5151 if (sp->type != SRB_SCSI_CMD)
cf53b069 5152 continue;
2c3dfe3f 5153 sfcp = sp->fcport;
f08b7251 5154 if (!(sfcp->flags & FCF_FCP2_DEVICE))
2c3dfe3f 5155 continue;
bdf79621 5156
8f7daead
GM		 5157 if (IS_QLA82XX(ha))
5158 set_bit(FCOE_CTX_RESET_NEEDED,
5159 &vha->dpc_flags);
5160 else
5161 set_bit(ISP_ABORT_NEEDED,
e315cd28 5162 &vha->dpc_flags);
2c3dfe3f
SJ		 5163 break;
5164 }
5165 spin_unlock_irqrestore(&ha->hardware_lock,
e315cd28 5166 cpu_flags);
1da177e4 5167 }
1da177e4
LT		 5168 start_dpc++;
5169 }
5170
5171 /* if the loop has been down for 4 minutes, reinit adapter */
e315cd28 5172 if (atomic_dec_and_test(&vha->loop_down_timer) != 0) {
0d6e61bc 5173 if (!(vha->device_flags & DFLG_NO_CABLE)) {
7c3df132 5174 ql_log(ql_log_warn, vha, 0x6009,
1da177e4
LT		 5175 "Loop down - aborting ISP.\n");
5176
8f7daead
GM		 5177 if (IS_QLA82XX(ha))
5178 set_bit(FCOE_CTX_RESET_NEEDED,
5179 &vha->dpc_flags);
5180 else
5181 set_bit(ISP_ABORT_NEEDED,
5182 &vha->dpc_flags);
1da177e4
LT		 5183 }
5184 }
7c3df132
SK		 5185 ql_dbg(ql_dbg_timer, vha, 0x600a,
5186 "Loop down - seconds remaining %d.\n",
5187 atomic_read(&vha->loop_down_timer));
1da177e4
LT		 5188 }
5189
cefcaba6
SK		 5190 /* Check if beacon LED needs to be blinked for physical host only */
5191 if (!vha->vp_idx && (ha->beacon_blink_led == 1)) {
999916dc 5192 /* There is no beacon_blink function for ISP82xx */
7ec0effd 5193 if (!IS_P3P_TYPE(ha)) {
999916dc
SK		 5194 set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags);
5195 start_dpc++;
5196 }
f6df144c 5197 }
5198
550bf57d 5199 /* Process any deferred work. */
e315cd28 5200 if (!list_empty(&vha->work_list))
550bf57d
AV		 5201 start_dpc++;
5202
1da177e4 5203 /* Schedule the DPC routine if needed */
e315cd28
AC		 5204 if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) ||
5205 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) ||
5206 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags) ||
1da177e4 5207 start_dpc ||
e315cd28
AC		 5208 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) ||
5209 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) ||
a9083016
GM		 5210 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) ||
5211 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) ||
e315cd28 5212 test_bit(VP_DPC_NEEDED, &vha->dpc_flags) ||
3c290d0b
CD		 5213 test_bit(RELOGIN_NEEDED, &vha->dpc_flags) ||
5214 test_bit(HOST_RAMP_DOWN_QUEUE_DEPTH, &vha->dpc_flags) ||
5215 test_bit(HOST_RAMP_UP_QUEUE_DEPTH, &vha->dpc_flags))) {
7c3df132
SK		 5216 ql_dbg(ql_dbg_timer, vha, 0x600b,
5217 "isp_abort_needed=%d loop_resync_needed=%d "
5218 "fcport_update_needed=%d start_dpc=%d "
5219 "reset_marker_needed=%d",
5220 test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags),
5221 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags),
5222 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags),
5223 start_dpc,
5224 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags));
5225 ql_dbg(ql_dbg_timer, vha, 0x600c,
5226 "beacon_blink_needed=%d isp_unrecoverable=%d "
5227 "fcoe_ctx_reset_needed=%d vp_dpc_needed=%d "
3c290d0b
CD		 5228 "relogin_needed=%d, host_ramp_down_needed=%d "
5229 "host_ramp_up_needed=%d.\n",
7c3df132
SK		 5230 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags),
5231 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags),
5232 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags),
5233 test_bit(VP_DPC_NEEDED, &vha->dpc_flags),
3c290d0b
CD		 5234 test_bit(RELOGIN_NEEDED, &vha->dpc_flags),
5235 test_bit(HOST_RAMP_UP_QUEUE_DEPTH, &vha->dpc_flags),
5236 test_bit(HOST_RAMP_DOWN_QUEUE_DEPTH, &vha->dpc_flags));
e315cd28 5237 qla2xxx_wake_dpc(vha);
7c3df132 5238 }
1da177e4 5239
e315cd28 5240 qla2x00_restart_timer(vha, WATCH_INTERVAL);
1da177e4
LT		 5241}
5242
5433383e
AV		 5243/* Firmware interface routines. */
5244
6246b8a1 5245#define FW_BLOBS 10
5433383e
AV		 5246#define FW_ISP21XX 0
5247#define FW_ISP22XX 1
5248#define FW_ISP2300 2
5249#define FW_ISP2322 3
48c02fde 5250#define FW_ISP24XX 4
c3a2f0df 5251#define FW_ISP25XX 5
3a03eb79 5252#define FW_ISP81XX 6
a9083016 5253#define FW_ISP82XX 7
6246b8a1
GM		 5254#define FW_ISP2031 8
5255#define FW_ISP8031 9
5433383e 5256
bb8ee499
AV		 5257#define FW_FILE_ISP21XX "ql2100_fw.bin"
5258#define FW_FILE_ISP22XX "ql2200_fw.bin"
5259#define FW_FILE_ISP2300 "ql2300_fw.bin"
5260#define FW_FILE_ISP2322 "ql2322_fw.bin"
5261#define FW_FILE_ISP24XX "ql2400_fw.bin"
c3a2f0df 5262#define FW_FILE_ISP25XX "ql2500_fw.bin"
3a03eb79 5263#define FW_FILE_ISP81XX "ql8100_fw.bin"
a9083016 5264#define FW_FILE_ISP82XX "ql8200_fw.bin"
6246b8a1
GM		 5265#define FW_FILE_ISP2031 "ql2600_fw.bin"
5266#define FW_FILE_ISP8031 "ql8300_fw.bin"
bb8ee499 5267
e1e82b6f 5268static DEFINE_MUTEX(qla_fw_lock);
5433383e
AV		 5269
5270static struct fw_blob qla_fw_blobs[FW_BLOBS] = {
bb8ee499
AV		 5271 { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, },
5272 { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, },
5273 { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, },
5274 { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, },
5275 { .name = FW_FILE_ISP24XX, },
c3a2f0df 5276 { .name = FW_FILE_ISP25XX, },
3a03eb79 5277 { .name = FW_FILE_ISP81XX, },
a9083016 5278 { .name = FW_FILE_ISP82XX, },
6246b8a1
GM		 5279 { .name = FW_FILE_ISP2031, },
5280 { .name = FW_FILE_ISP8031, },
5433383e
AV		 5281};
5282
5283struct fw_blob *
e315cd28 5284qla2x00_request_firmware(scsi_qla_host_t *vha)
5433383e 5285{
e315cd28 5286 struct qla_hw_data *ha = vha->hw;
5433383e
AV		 5287 struct fw_blob *blob;
5288
5433383e
AV		 5289 if (IS_QLA2100(ha)) {
5290 blob = &qla_fw_blobs[FW_ISP21XX];
5291 } else if (IS_QLA2200(ha)) {
5292 blob = &qla_fw_blobs[FW_ISP22XX];
48c02fde 5293 } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
5433383e 5294 blob = &qla_fw_blobs[FW_ISP2300];
48c02fde 5295 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
5433383e 5296 blob = &qla_fw_blobs[FW_ISP2322];
4d4df193 5297 } else if (IS_QLA24XX_TYPE(ha)) {
5433383e 5298 blob = &qla_fw_blobs[FW_ISP24XX];
c3a2f0df
AV		 5299 } else if (IS_QLA25XX(ha)) {
5300 blob = &qla_fw_blobs[FW_ISP25XX];
3a03eb79
AV		 5301 } else if (IS_QLA81XX(ha)) {
5302 blob = &qla_fw_blobs[FW_ISP81XX];
a9083016
GM		 5303 } else if (IS_QLA82XX(ha)) {
5304 blob = &qla_fw_blobs[FW_ISP82XX];
6246b8a1
GM		 5305 } else if (IS_QLA2031(ha)) {
5306 blob = &qla_fw_blobs[FW_ISP2031];
5307 } else if (IS_QLA8031(ha)) {
5308 blob = &qla_fw_blobs[FW_ISP8031];
8a655229
DC		 5309 } else {
5310 return NULL;
5433383e
AV		 5311 }
5312
e1e82b6f 5313 mutex_lock(&qla_fw_lock);
5433383e
AV		 5314 if (blob->fw)
5315 goto out;
5316
5317 if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) {
7c3df132
SK		 5318 ql_log(ql_log_warn, vha, 0x0063,
5319 "Failed to load firmware image (%s).\n", blob->name);
5433383e
AV		 5320 blob->fw = NULL;
5321 blob = NULL;
5322 goto out;
5323 }
5324
5325out:
e1e82b6f 5326 mutex_unlock(&qla_fw_lock);
5433383e
AV		 5327 return blob;
5328}
5329
5330static void
5331qla2x00_release_firmware(void)
5332{
5333 int idx;
5334
e1e82b6f 5335 mutex_lock(&qla_fw_lock);
5433383e 5336 for (idx = 0; idx < FW_BLOBS; idx++)
cf92549f 5337 release_firmware(qla_fw_blobs[idx].fw);
e1e82b6f 5338 mutex_unlock(&qla_fw_lock);
5433383e
AV		 5339}
5340
14e660e6
SJ		 5341static pci_ers_result_t
5342qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
5343{
85880801
AV		 5344 scsi_qla_host_t *vha = pci_get_drvdata(pdev);
5345 struct qla_hw_data *ha = vha->hw;
5346
7c3df132
SK		 5347 ql_dbg(ql_dbg_aer, vha, 0x9000,
5348 "PCI error detected, state %x.\n", state);
b9b12f73 5349
14e660e6
SJ		 5350 switch (state) {
5351 case pci_channel_io_normal:
85880801 5352 ha->flags.eeh_busy = 0;
14e660e6
SJ		 5353 return PCI_ERS_RESULT_CAN_RECOVER;
5354 case pci_channel_io_frozen:
85880801 5355 ha->flags.eeh_busy = 1;
a5b36321
LC		 5356 /* For ISP82XX complete any pending mailbox cmd */
5357 if (IS_QLA82XX(ha)) {
7190575f 5358 ha->flags.isp82xx_fw_hung = 1;
c8f6544e
CD		 5359 ql_dbg(ql_dbg_aer, vha, 0x9001, "Pci channel io frozen\n");
5360 qla82xx_clear_pending_mbx(vha);
a5b36321 5361 }
90a86fc0 5362 qla2x00_free_irqs(vha);
14e660e6 5363 pci_disable_device(pdev);
bddd2d65
LC		 5364 /* Return back all IOs */
5365 qla2x00_abort_all_cmds(vha, DID_RESET << 16);
14e660e6
SJ		 5366 return PCI_ERS_RESULT_NEED_RESET;
5367 case pci_channel_io_perm_failure:
85880801
AV		 5368 ha->flags.pci_channel_io_perm_failure = 1;
5369 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
14e660e6
SJ		 5370 return PCI_ERS_RESULT_DISCONNECT;
5371 }
5372 return PCI_ERS_RESULT_NEED_RESET;
5373}
5374
5375static pci_ers_result_t
5376qla2xxx_pci_mmio_enabled(struct pci_dev *pdev)
5377{
5378 int risc_paused = 0;
5379 uint32_t stat;
5380 unsigned long flags;
e315cd28
AC		 5381 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
5382 struct qla_hw_data *ha = base_vha->hw;
14e660e6
SJ		 5383 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
5384 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
5385
bcc5b6d3
SK		 5386 if (IS_QLA82XX(ha))
5387 return PCI_ERS_RESULT_RECOVERED;
5388
14e660e6
SJ		 5389 spin_lock_irqsave(&ha->hardware_lock, flags);
5390 if (IS_QLA2100(ha) || IS_QLA2200(ha)){
5391 stat = RD_REG_DWORD(&reg->hccr);
5392 if (stat & HCCR_RISC_PAUSE)
5393 risc_paused = 1;
5394 } else if (IS_QLA23XX(ha)) {
5395 stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
5396 if (stat & HSR_RISC_PAUSED)
5397 risc_paused = 1;
5398 } else if (IS_FWI2_CAPABLE(ha)) {
5399 stat = RD_REG_DWORD(&reg24->host_status);
5400 if (stat & HSRX_RISC_PAUSED)
5401 risc_paused = 1;
5402 }
5403 spin_unlock_irqrestore(&ha->hardware_lock, flags);
5404
5405 if (risc_paused) {
7c3df132
SK		 5406 ql_log(ql_log_info, base_vha, 0x9003,
5407 "RISC paused -- mmio_enabled, Dumping firmware.\n");
e315cd28 5408 ha->isp_ops->fw_dump(base_vha, 0);
14e660e6
SJ		 5409
5410 return PCI_ERS_RESULT_NEED_RESET;
5411 } else
5412 return PCI_ERS_RESULT_RECOVERED;
5413}
5414
fa492630
SK		 5415static uint32_t
5416qla82xx_error_recovery(scsi_qla_host_t *base_vha)
a5b36321
LC		 5417{
5418 uint32_t rval = QLA_FUNCTION_FAILED;
5419 uint32_t drv_active = 0;
5420 struct qla_hw_data *ha = base_vha->hw;
5421 int fn;
5422 struct pci_dev *other_pdev = NULL;
5423
7c3df132
SK		 5424 ql_dbg(ql_dbg_aer, base_vha, 0x9006,
5425 "Entered %s.\n", __func__);
a5b36321
LC		 5426
5427 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
5428
5429 if (base_vha->flags.online) {
5430 /* Abort all outstanding commands,
5431 * so as to be requeued later */
5432 qla2x00_abort_isp_cleanup(base_vha);
5433 }
5434
5435
5436 fn = PCI_FUNC(ha->pdev->devfn);
5437 while (fn > 0) {
5438 fn--;
7c3df132
SK		 5439 ql_dbg(ql_dbg_aer, base_vha, 0x9007,
5440 "Finding pci device at function = 0x%x.\n", fn);
a5b36321
LC		 5441 other_pdev =
5442 pci_get_domain_bus_and_slot(pci_domain_nr(ha->pdev->bus),
5443 ha->pdev->bus->number, PCI_DEVFN(PCI_SLOT(ha->pdev->devfn),
5444 fn));
5445
5446 if (!other_pdev)
5447 continue;
5448 if (atomic_read(&other_pdev->enable_cnt)) {
7c3df132
SK		 5449 ql_dbg(ql_dbg_aer, base_vha, 0x9008,
5450 "Found PCI func available and enable at 0x%x.\n",
5451 fn);
a5b36321
LC		 5452 pci_dev_put(other_pdev);
5453 break;
5454 }
5455 pci_dev_put(other_pdev);
5456 }
5457
5458 if (!fn) {
5459 /* Reset owner */
7c3df132
SK		 5460 ql_dbg(ql_dbg_aer, base_vha, 0x9009,
5461 "This devfn is reset owner = 0x%x.\n",
5462 ha->pdev->devfn);
a5b36321
LC		 5463 qla82xx_idc_lock(ha);
5464
5465 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 5466 QLA8XXX_DEV_INITIALIZING);
a5b36321
LC		 5467
5468 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION,
5469 QLA82XX_IDC_VERSION);
5470
5471 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
7c3df132
SK		 5472 ql_dbg(ql_dbg_aer, base_vha, 0x900a,
5473 "drv_active = 0x%x.\n", drv_active);
a5b36321
LC		 5474
5475 qla82xx_idc_unlock(ha);
5476 /* Reset if device is not already reset
5477 * drv_active would be 0 if a reset has already been done
5478 */
5479 if (drv_active)
5480 rval = qla82xx_start_firmware(base_vha);
5481 else
5482 rval = QLA_SUCCESS;
5483 qla82xx_idc_lock(ha);
5484
5485 if (rval != QLA_SUCCESS) {
7c3df132
SK		 5486 ql_log(ql_log_info, base_vha, 0x900b,
5487 "HW State: FAILED.\n");
a5b36321
LC		 5488 qla82xx_clear_drv_active(ha);
5489 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 5490 QLA8XXX_DEV_FAILED);
a5b36321 5491 } else {
7c3df132
SK		 5492 ql_log(ql_log_info, base_vha, 0x900c,
5493 "HW State: READY.\n");
a5b36321 5494 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 5495 QLA8XXX_DEV_READY);
a5b36321 5496 qla82xx_idc_unlock(ha);
7190575f 5497 ha->flags.isp82xx_fw_hung = 0;
a5b36321
LC		 5498 rval = qla82xx_restart_isp(base_vha);
5499 qla82xx_idc_lock(ha);
5500 /* Clear driver state register */
5501 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, 0);
5502 qla82xx_set_drv_active(base_vha);
5503 }
5504 qla82xx_idc_unlock(ha);
5505 } else {
7c3df132
SK		 5506 ql_dbg(ql_dbg_aer, base_vha, 0x900d,
5507 "This devfn is not reset owner = 0x%x.\n",
5508 ha->pdev->devfn);
a5b36321 5509 if ((qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE) ==
7d613ac6 5510 QLA8XXX_DEV_READY)) {
7190575f 5511 ha->flags.isp82xx_fw_hung = 0;
a5b36321
LC		 5512 rval = qla82xx_restart_isp(base_vha);
5513 qla82xx_idc_lock(ha);
5514 qla82xx_set_drv_active(base_vha);
5515 qla82xx_idc_unlock(ha);
5516 }
5517 }
5518 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
5519
5520 return rval;
5521}
5522
14e660e6
SJ		 5523static pci_ers_result_t
5524qla2xxx_pci_slot_reset(struct pci_dev *pdev)
5525{
5526 pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT;
e315cd28
AC		 5527 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
5528 struct qla_hw_data *ha = base_vha->hw;
90a86fc0
JC		 5529 struct rsp_que *rsp;
5530 int rc, retries = 10;
09483916 5531
7c3df132
SK		 5532 ql_dbg(ql_dbg_aer, base_vha, 0x9004,
5533 "Slot Reset.\n");
85880801 5534
90a86fc0
JC		 5535 /* Workaround: qla2xxx driver which access hardware earlier
5536 * needs error state to be pci_channel_io_online.
5537 * Otherwise mailbox command timesout.
5538 */
5539 pdev->error_state = pci_channel_io_normal;
5540
5541 pci_restore_state(pdev);
5542
8c1496bd
RL		 5543 /* pci_restore_state() clears the saved_state flag of the device
5544 * save restored state which resets saved_state flag
5545 */
5546 pci_save_state(pdev);
5547
09483916
BH		 5548 if (ha->mem_only)
5549 rc = pci_enable_device_mem(pdev);
5550 else
5551 rc = pci_enable_device(pdev);
14e660e6 5552
09483916 5553 if (rc) {
7c3df132 5554 ql_log(ql_log_warn, base_vha, 0x9005,
14e660e6 5555 "Can't re-enable PCI device after reset.\n");
a5b36321 5556 goto exit_slot_reset;
14e660e6 5557 }
14e660e6 5558
90a86fc0
JC		 5559 rsp = ha->rsp_q_map[0];
5560 if (qla2x00_request_irqs(ha, rsp))
a5b36321 5561 goto exit_slot_reset;
90a86fc0 5562
e315cd28 5563 if (ha->isp_ops->pci_config(base_vha))
a5b36321
LC		 5564 goto exit_slot_reset;
5565
5566 if (IS_QLA82XX(ha)) {
5567 if (qla82xx_error_recovery(base_vha) == QLA_SUCCESS) {
5568 ret = PCI_ERS_RESULT_RECOVERED;
5569 goto exit_slot_reset;
5570 } else
5571 goto exit_slot_reset;
5572 }
14e660e6 5573
90a86fc0
JC		 5574 while (ha->flags.mbox_busy && retries--)
5575 msleep(1000);
85880801 5576
e315cd28 5577 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
a9083016 5578 if (ha->isp_ops->abort_isp(base_vha) == QLA_SUCCESS)
14e660e6 5579 ret = PCI_ERS_RESULT_RECOVERED;
e315cd28 5580 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
14e660e6 5581
90a86fc0 5582
a5b36321 5583exit_slot_reset:
7c3df132
SK		 5584 ql_dbg(ql_dbg_aer, base_vha, 0x900e,
5585 "slot_reset return %x.\n", ret);
85880801 5586
14e660e6
SJ		 5587 return ret;
5588}
5589
5590static void
5591qla2xxx_pci_resume(struct pci_dev *pdev)
5592{
e315cd28
AC		 5593 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
5594 struct qla_hw_data *ha = base_vha->hw;
14e660e6
SJ		 5595 int ret;
5596
7c3df132
SK		 5597 ql_dbg(ql_dbg_aer, base_vha, 0x900f,
5598 "pci_resume.\n");
85880801 5599
e315cd28 5600 ret = qla2x00_wait_for_hba_online(base_vha);
14e660e6 5601 if (ret != QLA_SUCCESS) {
7c3df132
SK		 5602 ql_log(ql_log_fatal, base_vha, 0x9002,
5603 "The device failed to resume I/O from slot/link_reset.\n");
14e660e6 5604 }
85880801 5605
3e46f031
LC		 5606 pci_cleanup_aer_uncorrect_error_status(pdev);
5607
85880801 5608 ha->flags.eeh_busy = 0;
14e660e6
SJ		 5609}
5610
a55b2d21 5611static const struct pci_error_handlers qla2xxx_err_handler = {
14e660e6
SJ		 5612 .error_detected = qla2xxx_pci_error_detected,
5613 .mmio_enabled = qla2xxx_pci_mmio_enabled,
5614 .slot_reset = qla2xxx_pci_slot_reset,
5615 .resume = qla2xxx_pci_resume,
5616};
5617
5433383e 5618static struct pci_device_id qla2xxx_pci_tbl[] = {
47f5e069
AV		 5619 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) },
5620 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) },
5621 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) },
5622 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) },
5623 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) },
5624 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) },
5625 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) },
5626 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) },
5627 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) },
4d4df193 5628 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) },
47f5e069
AV		 5629 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) },
5630 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) },
c3a2f0df 5631 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) },
6246b8a1 5632 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2031) },
3a03eb79 5633 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) },
a9083016 5634 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) },
650f528f 5635 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8031) },
8ae6d9c7 5636 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISPF001) },
7ec0effd 5637 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8044) },
5433383e
AV		 5638 { 0 },
5639};
5640MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl);
5641
fca29703 5642static struct pci_driver qla2xxx_pci_driver = {
cb63067a 5643 .name = QLA2XXX_DRIVER_NAME,
0a21ef1e
JB		 5644 .driver = {
5645 .owner = THIS_MODULE,
5646 },
fca29703 5647 .id_table = qla2xxx_pci_tbl,
7ee61397 5648 .probe = qla2x00_probe_one,
4c993f76 5649 .remove = qla2x00_remove_one,
e30d1756 5650 .shutdown = qla2x00_shutdown,
14e660e6 5651 .err_handler = &qla2xxx_err_handler,
fca29703
AV		 5652};
5653
75ef9de1 5654static const struct file_operations apidev_fops = {
6a03b4cd 5655 .owner = THIS_MODULE,
6038f373 5656 .llseek = noop_llseek,
6a03b4cd
HZ		 5657};
5658
1da177e4
LT		 5659/**
5660 * qla2x00_module_init - Module initialization.
5661 **/
5662static int __init
5663qla2x00_module_init(void)
5664{
fca29703
AV		 5665 int ret = 0;
5666
1da177e4 5667 /* Allocate cache for SRBs. */
354d6b21 5668 srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0,
20c2df83 5669 SLAB_HWCACHE_ALIGN, NULL);
1da177e4 5670 if (srb_cachep == NULL) {
7c3df132
SK		 5671 ql_log(ql_log_fatal, NULL, 0x0001,
5672 "Unable to allocate SRB cache...Failing load!.\n");
1da177e4
LT		 5673 return -ENOMEM;
5674 }
5675
2d70c103
NB		 5676 /* Initialize target kmem_cache and mem_pools */
5677 ret = qlt_init();
5678 if (ret < 0) {
5679 kmem_cache_destroy(srb_cachep);
5680 return ret;
5681 } else if (ret > 0) {
5682 /*
5683 * If initiator mode is explictly disabled by qlt_init(),
5684 * prevent scsi_transport_fc.c:fc_scsi_scan_rport() from
5685 * performing scsi_scan_target() during LOOP UP event.
5686 */
5687 qla2xxx_transport_functions.disable_target_scan = 1;
5688 qla2xxx_transport_vport_functions.disable_target_scan = 1;
5689 }
5690
1da177e4
LT		 5691 /* Derive version string. */
5692 strcpy(qla2x00_version_str, QLA2XXX_VERSION);
11010fec 5693 if (ql2xextended_error_logging)
0181944f
AV		 5694 strcat(qla2x00_version_str, "-debug");
5695
1c97a12a
AV		 5696 qla2xxx_transport_template =
5697 fc_attach_transport(&qla2xxx_transport_functions);
2c3dfe3f
SJ		 5698 if (!qla2xxx_transport_template) {
5699 kmem_cache_destroy(srb_cachep);
7c3df132
SK		 5700 ql_log(ql_log_fatal, NULL, 0x0002,
5701 "fc_attach_transport failed...Failing load!.\n");
2d70c103 5702 qlt_exit();
1da177e4 5703 return -ENODEV;
2c3dfe3f 5704 }
6a03b4cd
HZ		 5705
5706 apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops);
5707 if (apidev_major < 0) {
7c3df132
SK		 5708 ql_log(ql_log_fatal, NULL, 0x0003,
5709 "Unable to register char device %s.\n", QLA2XXX_APIDEV);
6a03b4cd
HZ		 5710 }
5711
2c3dfe3f
SJ		 5712 qla2xxx_transport_vport_template =
5713 fc_attach_transport(&qla2xxx_transport_vport_functions);
5714 if (!qla2xxx_transport_vport_template) {
5715 kmem_cache_destroy(srb_cachep);
2d70c103 5716 qlt_exit();
2c3dfe3f 5717 fc_release_transport(qla2xxx_transport_template);
7c3df132
SK		 5718 ql_log(ql_log_fatal, NULL, 0x0004,
5719 "fc_attach_transport vport failed...Failing load!.\n");
1da177e4 5720 return -ENODEV;
2c3dfe3f 5721 }
7c3df132
SK		 5722 ql_log(ql_log_info, NULL, 0x0005,
5723 "QLogic Fibre Channel HBA Driver: %s.\n",
fd9a29f0 5724 qla2x00_version_str);
7ee61397 5725 ret = pci_register_driver(&qla2xxx_pci_driver);
fca29703
AV		 5726 if (ret) {
5727 kmem_cache_destroy(srb_cachep);
2d70c103 5728 qlt_exit();
fca29703 5729 fc_release_transport(qla2xxx_transport_template);
2c3dfe3f 5730 fc_release_transport(qla2xxx_transport_vport_template);
7c3df132
SK		 5731 ql_log(ql_log_fatal, NULL, 0x0006,
5732 "pci_register_driver failed...ret=%d Failing load!.\n",
5733 ret);
fca29703
AV		 5734 }
5735 return ret;
1da177e4
LT		 5736}
5737
5738/**
5739 * qla2x00_module_exit - Module cleanup.
5740 **/
5741static void __exit
5742qla2x00_module_exit(void)
5743{
6a03b4cd 5744 unregister_chrdev(apidev_major, QLA2XXX_APIDEV);
7ee61397 5745 pci_unregister_driver(&qla2xxx_pci_driver);
5433383e 5746 qla2x00_release_firmware();
354d6b21 5747 kmem_cache_destroy(srb_cachep);
2d70c103 5748 qlt_exit();
a9083016
GM		 5749 if (ctx_cachep)
5750 kmem_cache_destroy(ctx_cachep);
1da177e4 5751 fc_release_transport(qla2xxx_transport_template);
2c3dfe3f 5752 fc_release_transport(qla2xxx_transport_vport_template);
1da177e4
LT		 5753}
5754
5755module_init(qla2x00_module_init);
5756module_exit(qla2x00_module_exit);
5757
5758MODULE_AUTHOR("QLogic Corporation");
5759MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver");
5760MODULE_LICENSE("GPL");
5761MODULE_VERSION(QLA2XXX_VERSION);
bb8ee499
AV		 5762MODULE_FIRMWARE(FW_FILE_ISP21XX);
5763MODULE_FIRMWARE(FW_FILE_ISP22XX);
5764MODULE_FIRMWARE(FW_FILE_ISP2300);
5765MODULE_FIRMWARE(FW_FILE_ISP2322);
5766MODULE_FIRMWARE(FW_FILE_ISP24XX);
61623fc3 5767MODULE_FIRMWARE(FW_FILE_ISP25XX);
Linux 6.x block layer and io_uring tree(s)