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[SCSI] qla2xxx: Update the driver version to 8.07.00.02-k.
[linux-2.6-block.git] / drivers / scsi / qla2xxx / qla_os.c
CommitLineData
1da177e4 1/*
fa90c54f 2 * QLogic Fibre Channel HBA Driver
1e63395c 3 * Copyright (c) 2003-2013 QLogic Corporation
1da177e4 4 *
fa90c54f 5 * See LICENSE.qla2xxx for copyright and licensing details.
1da177e4
LT		 6 */
7#include "qla_def.h"
8
9#include <linux/moduleparam.h>
10#include <linux/vmalloc.h>
1da177e4 11#include <linux/delay.h>
39a11240 12#include <linux/kthread.h>
e1e82b6f 13#include <linux/mutex.h>
3420d36c 14#include <linux/kobject.h>
5a0e3ad6 15#include <linux/slab.h>
1da177e4
LT		 16#include <scsi/scsi_tcq.h>
17#include <scsi/scsicam.h>
18#include <scsi/scsi_transport.h>
19#include <scsi/scsi_transport_fc.h>
20
2d70c103
NB		 21#include "qla_target.h"
22
1da177e4
LT		 23/*
24 * Driver version
25 */
26char qla2x00_version_str[40];
27
6a03b4cd
HZ		 28static int apidev_major;
29
1da177e4
LT		 30/*
31 * SRB allocation cache
32 */
e18b890b 33static struct kmem_cache *srb_cachep;
1da177e4 34
a9083016
GM		 35/*
36 * CT6 CTX allocation cache
37 */
38static struct kmem_cache *ctx_cachep;
3ce8866c
SK		 39/*
40 * error level for logging
41 */
42int ql_errlev = ql_log_all;
a9083016 43
fa492630 44static int ql2xenableclass2;
2d70c103
NB		 45module_param(ql2xenableclass2, int, S_IRUGO|S_IRUSR);
46MODULE_PARM_DESC(ql2xenableclass2,
47 "Specify if Class 2 operations are supported from the very "
48 "beginning. Default is 0 - class 2 not supported.");
49
8ae6d9c7 50
1da177e4 51int ql2xlogintimeout = 20;
f2019cb1 52module_param(ql2xlogintimeout, int, S_IRUGO);
1da177e4
LT		 53MODULE_PARM_DESC(ql2xlogintimeout,
54 "Login timeout value in seconds.");
55
a7b61842 56int qlport_down_retry;
f2019cb1 57module_param(qlport_down_retry, int, S_IRUGO);
1da177e4 58MODULE_PARM_DESC(qlport_down_retry,
900d9f98 59 "Maximum number of command retries to a port that returns "
1da177e4
LT		 60 "a PORT-DOWN status.");
61
1da177e4
LT		 62int ql2xplogiabsentdevice;
63module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR);
64MODULE_PARM_DESC(ql2xplogiabsentdevice,
65 "Option to enable PLOGI to devices that are not present after "
900d9f98 66 "a Fabric scan. This is needed for several broken switches. "
1da177e4
LT		 67 "Default is 0 - no PLOGI. 1 - perfom PLOGI.");
68
1da177e4 69int ql2xloginretrycount = 0;
f2019cb1 70module_param(ql2xloginretrycount, int, S_IRUGO);
1da177e4
LT		 71MODULE_PARM_DESC(ql2xloginretrycount,
72 "Specify an alternate value for the NVRAM login retry count.");
73
a7a167bf 74int ql2xallocfwdump = 1;
f2019cb1 75module_param(ql2xallocfwdump, int, S_IRUGO);
a7a167bf
AV		 76MODULE_PARM_DESC(ql2xallocfwdump,
77 "Option to enable allocation of memory for a firmware dump "
78 "during HBA initialization. Memory allocation requirements "
79 "vary by ISP type. Default is 1 - allocate memory.");
80
11010fec 81int ql2xextended_error_logging;
27d94035 82module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
11010fec 83MODULE_PARM_DESC(ql2xextended_error_logging,
3ce8866c
SK		 84 "Option to enable extended error logging,\n"
85 "\t\tDefault is 0 - no logging. 0x40000000 - Module Init & Probe.\n"
86 "\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n"
87 "\t\t0x08000000 - IO tracing. 0x04000000 - DPC Thread.\n"
88 "\t\t0x02000000 - Async events. 0x01000000 - Timer routines.\n"
89 "\t\t0x00800000 - User space. 0x00400000 - Task Management.\n"
90 "\t\t0x00200000 - AER/EEH. 0x00100000 - Multi Q.\n"
91 "\t\t0x00080000 - P3P Specific. 0x00040000 - Virtual Port.\n"
92 "\t\t0x00020000 - Buffer Dump. 0x00010000 - Misc.\n"
29f9f90c
CD		 93 "\t\t0x00008000 - Verbose. 0x00004000 - Target.\n"
94 "\t\t0x00002000 - Target Mgmt. 0x00001000 - Target TMF.\n"
3ce8866c 95 "\t\t0x7fffffff - For enabling all logs, can be too many logs.\n"
cfb0919c
CD		 96 "\t\t0x1e400000 - Preferred value for capturing essential "
97 "debug information (equivalent to old "
98 "ql2xextended_error_logging=1).\n"
3ce8866c 99 "\t\tDo LOGICAL OR of the value to enable more than one level");
0181944f 100
a9083016 101int ql2xshiftctondsd = 6;
f2019cb1 102module_param(ql2xshiftctondsd, int, S_IRUGO);
a9083016
GM		 103MODULE_PARM_DESC(ql2xshiftctondsd,
104 "Set to control shifting of command type processing "
105 "based on total number of SG elements.");
106
7e47e5ca 107int ql2xfdmienable=1;
f2019cb1 108module_param(ql2xfdmienable, int, S_IRUGO);
cca5335c 109MODULE_PARM_DESC(ql2xfdmienable,
7794a5af
FW		 110 "Enables FDMI registrations. "
111 "0 - no FDMI. Default is 1 - perform FDMI.");
cca5335c 112
50280c01
CD		 113#define MAX_Q_DEPTH 32
114static int ql2xmaxqdepth = MAX_Q_DEPTH;
df7baa50
AV		 115module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR);
116MODULE_PARM_DESC(ql2xmaxqdepth,
e92e4a8f
CD		 117 "Maximum queue depth to set for each LUN. "
118 "Default is 32.");
df7baa50 119
9e522cd8
AE		 120int ql2xenabledif = 2;
121module_param(ql2xenabledif, int, S_IRUGO);
bad75002
AE		 122MODULE_PARM_DESC(ql2xenabledif,
123 " Enable T10-CRC-DIF "
8cb2049c
AE		 124 " Default is 0 - No DIF Support. 1 - Enable it"
125 ", 2 - Enable DIF for all types, except Type 0.");
bad75002 126
8cb2049c 127int ql2xenablehba_err_chk = 2;
bad75002
AE		 128module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR);
129MODULE_PARM_DESC(ql2xenablehba_err_chk,
8cb2049c
AE		 130 " Enable T10-CRC-DIF Error isolation by HBA:\n"
131 " Default is 1.\n"
132 " 0 -- Error isolation disabled\n"
133 " 1 -- Error isolation enabled only for DIX Type 0\n"
134 " 2 -- Error isolation enabled for all Types\n");
bad75002 135
e5896bd5 136int ql2xiidmaenable=1;
f2019cb1 137module_param(ql2xiidmaenable, int, S_IRUGO);
e5896bd5
AV		 138MODULE_PARM_DESC(ql2xiidmaenable,
139 "Enables iIDMA settings "
140 "Default is 1 - perform iIDMA. 0 - no iIDMA.");
141
73208dfd 142int ql2xmaxqueues = 1;
f2019cb1 143module_param(ql2xmaxqueues, int, S_IRUGO);
73208dfd
AC		 144MODULE_PARM_DESC(ql2xmaxqueues,
145 "Enables MQ settings "
ae68230c
JP		 146 "Default is 1 for single queue. Set it to number "
147 "of queues in MQ mode.");
68ca949c
AC		 148
149int ql2xmultique_tag;
f2019cb1 150module_param(ql2xmultique_tag, int, S_IRUGO);
68ca949c
AC		 151MODULE_PARM_DESC(ql2xmultique_tag,
152 "Enables CPU affinity settings for the driver "
153 "Default is 0 for no affinity of request and response IO. "
154 "Set it to 1 to turn on the cpu affinity.");
e337d907
AV		 155
156int ql2xfwloadbin;
86e45bf6 157module_param(ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
e337d907 158MODULE_PARM_DESC(ql2xfwloadbin,
7c3df132
SK		 159 "Option to specify location from which to load ISP firmware:.\n"
160 " 2 -- load firmware via the request_firmware() (hotplug).\n"
e337d907
AV		 161 " interface.\n"
162 " 1 -- load firmware from flash.\n"
163 " 0 -- use default semantics.\n");
164
ae97c91e 165int ql2xetsenable;
f2019cb1 166module_param(ql2xetsenable, int, S_IRUGO);
ae97c91e
AV		 167MODULE_PARM_DESC(ql2xetsenable,
168 "Enables firmware ETS burst."
169 "Default is 0 - skip ETS enablement.");
170
6907869d 171int ql2xdbwr = 1;
86e45bf6 172module_param(ql2xdbwr, int, S_IRUGO|S_IWUSR);
a9083016 173MODULE_PARM_DESC(ql2xdbwr,
08de2844
GM		 174 "Option to specify scheme for request queue posting.\n"
175 " 0 -- Regular doorbell.\n"
176 " 1 -- CAMRAM doorbell (faster).\n");
a9083016 177
f4c496c1 178int ql2xtargetreset = 1;
f2019cb1 179module_param(ql2xtargetreset, int, S_IRUGO);
f4c496c1
GM		 180MODULE_PARM_DESC(ql2xtargetreset,
181 "Enable target reset."
182 "Default is 1 - use hw defaults.");
183
4da26e16 184int ql2xgffidenable;
f2019cb1 185module_param(ql2xgffidenable, int, S_IRUGO);
4da26e16
CD		 186MODULE_PARM_DESC(ql2xgffidenable,
187 "Enables GFF_ID checks of port type. "
188 "Default is 0 - Do not use GFF_ID information.");
a9083016 189
3822263e 190int ql2xasynctmfenable;
f2019cb1 191module_param(ql2xasynctmfenable, int, S_IRUGO);
3822263e
MI		 192MODULE_PARM_DESC(ql2xasynctmfenable,
193 "Enables issue of TM IOCBs asynchronously via IOCB mechanism"
194 "Default is 0 - Issue TM IOCBs via mailbox mechanism.");
ed0de87c
GM		 195
196int ql2xdontresethba;
86e45bf6 197module_param(ql2xdontresethba, int, S_IRUGO|S_IWUSR);
ed0de87c 198MODULE_PARM_DESC(ql2xdontresethba,
08de2844
GM		 199 "Option to specify reset behaviour.\n"
200 " 0 (Default) -- Reset on failure.\n"
201 " 1 -- Do not reset on failure.\n");
ed0de87c 202
82515920
AV		 203uint ql2xmaxlun = MAX_LUNS;
204module_param(ql2xmaxlun, uint, S_IRUGO);
205MODULE_PARM_DESC(ql2xmaxlun,
206 "Defines the maximum LU number to register with the SCSI "
207 "midlayer. Default is 65535.");
208
08de2844
GM		 209int ql2xmdcapmask = 0x1F;
210module_param(ql2xmdcapmask, int, S_IRUGO);
211MODULE_PARM_DESC(ql2xmdcapmask,
212 "Set the Minidump driver capture mask level. "
6e96fa7b 213 "Default is 0x1F - Can be set to 0x3, 0x7, 0xF, 0x1F, 0x7F.");
08de2844 214
3aadff35 215int ql2xmdenable = 1;
08de2844
GM		 216module_param(ql2xmdenable, int, S_IRUGO);
217MODULE_PARM_DESC(ql2xmdenable,
218 "Enable/disable MiniDump. "
3aadff35
GM		 219 "0 - MiniDump disabled. "
220 "1 (Default) - MiniDump enabled.");
08de2844 221
1da177e4 222/*
fa2a1ce5 223 * SCSI host template entry points
1da177e4
LT		 224 */
225static int qla2xxx_slave_configure(struct scsi_device * device);
f4f051eb 226static int qla2xxx_slave_alloc(struct scsi_device *);
1e99e33a
AV		 227static int qla2xxx_scan_finished(struct Scsi_Host *, unsigned long time);
228static void qla2xxx_scan_start(struct Scsi_Host *);
f4f051eb 229static void qla2xxx_slave_destroy(struct scsi_device *);
f281233d 230static int qla2xxx_queuecommand(struct Scsi_Host *h, struct scsi_cmnd *cmd);
1da177e4
LT		 231static int qla2xxx_eh_abort(struct scsi_cmnd *);
232static int qla2xxx_eh_device_reset(struct scsi_cmnd *);
523ec773 233static int qla2xxx_eh_target_reset(struct scsi_cmnd *);
1da177e4
LT		 234static int qla2xxx_eh_bus_reset(struct scsi_cmnd *);
235static int qla2xxx_eh_host_reset(struct scsi_cmnd *);
1da177e4 236
e881a172 237static int qla2x00_change_queue_depth(struct scsi_device *, int, int);
ce7e4af7 238static int qla2x00_change_queue_type(struct scsi_device *, int);
3491255e 239static void qla2x00_free_device(scsi_qla_host_t *);
ce7e4af7 240
a5326f86 241struct scsi_host_template qla2xxx_driver_template = {
1da177e4 242 .module = THIS_MODULE,
cb63067a 243 .name = QLA2XXX_DRIVER_NAME,
a5326f86 244 .queuecommand = qla2xxx_queuecommand,
fca29703
AV		 245
246 .eh_abort_handler = qla2xxx_eh_abort,
247 .eh_device_reset_handler = qla2xxx_eh_device_reset,
523ec773 248 .eh_target_reset_handler = qla2xxx_eh_target_reset,
fca29703
AV		 249 .eh_bus_reset_handler = qla2xxx_eh_bus_reset,
250 .eh_host_reset_handler = qla2xxx_eh_host_reset,
251
252 .slave_configure = qla2xxx_slave_configure,
253
254 .slave_alloc = qla2xxx_slave_alloc,
255 .slave_destroy = qla2xxx_slave_destroy,
ed677086
AV		 256 .scan_finished = qla2xxx_scan_finished,
257 .scan_start = qla2xxx_scan_start,
ce7e4af7
AV		 258 .change_queue_depth = qla2x00_change_queue_depth,
259 .change_queue_type = qla2x00_change_queue_type,
fca29703
AV		 260 .this_id = -1,
261 .cmd_per_lun = 3,
262 .use_clustering = ENABLE_CLUSTERING,
263 .sg_tablesize = SG_ALL,
264
265 .max_sectors = 0xFFFF,
afb046e2 266 .shost_attrs = qla2x00_host_attrs,
2d70c103
NB		 267
268 .supported_mode = MODE_INITIATOR,
fca29703
AV		 269};
270
1da177e4 271static struct scsi_transport_template *qla2xxx_transport_template = NULL;
2c3dfe3f 272struct scsi_transport_template *qla2xxx_transport_vport_template = NULL;
1da177e4 273
1da177e4
LT		 274/* TODO Convert to inlines
275 *
276 * Timer routines
277 */
1da177e4 278
2c3dfe3f 279__inline__ void
e315cd28 280qla2x00_start_timer(scsi_qla_host_t *vha, void *func, unsigned long interval)
1da177e4 281{
e315cd28
AC		 282 init_timer(&vha->timer);
283 vha->timer.expires = jiffies + interval * HZ;
284 vha->timer.data = (unsigned long)vha;
285 vha->timer.function = (void (*)(unsigned long))func;
286 add_timer(&vha->timer);
287 vha->timer_active = 1;
1da177e4
LT		 288}
289
290static inline void
e315cd28 291qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval)
1da177e4 292{
a9083016 293 /* Currently used for 82XX only. */
7c3df132
SK		 294 if (vha->device_flags & DFLG_DEV_FAILED) {
295 ql_dbg(ql_dbg_timer, vha, 0x600d,
296 "Device in a failed state, returning.\n");
a9083016 297 return;
7c3df132 298 }
a9083016 299
e315cd28 300 mod_timer(&vha->timer, jiffies + interval * HZ);
1da177e4
LT		 301}
302
a824ebb3 303static __inline__ void
e315cd28 304qla2x00_stop_timer(scsi_qla_host_t *vha)
1da177e4 305{
e315cd28
AC		 306 del_timer_sync(&vha->timer);
307 vha->timer_active = 0;
1da177e4
LT		 308}
309
1da177e4
LT		 310static int qla2x00_do_dpc(void *data);
311
312static void qla2x00_rst_aen(scsi_qla_host_t *);
313
73208dfd
AC		 314static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t,
315 struct req_que **, struct rsp_que **);
e30d1756 316static void qla2x00_free_fw_dump(struct qla_hw_data *);
e315cd28 317static void qla2x00_mem_free(struct qla_hw_data *);
1da177e4 318
1da177e4 319/* -------------------------------------------------------------------------- */
9a347ff4
CD		 320static int qla2x00_alloc_queues(struct qla_hw_data *ha, struct req_que *req,
321 struct rsp_que *rsp)
73208dfd 322{
7c3df132 323 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2afa19a9 324 ha->req_q_map = kzalloc(sizeof(struct req_que *) * ha->max_req_queues,
73208dfd
AC		 325 GFP_KERNEL);
326 if (!ha->req_q_map) {
7c3df132
SK		 327 ql_log(ql_log_fatal, vha, 0x003b,
328 "Unable to allocate memory for request queue ptrs.\n");
73208dfd
AC		 329 goto fail_req_map;
330 }
331
2afa19a9 332 ha->rsp_q_map = kzalloc(sizeof(struct rsp_que *) * ha->max_rsp_queues,
73208dfd
AC		 333 GFP_KERNEL);
334 if (!ha->rsp_q_map) {
7c3df132
SK		 335 ql_log(ql_log_fatal, vha, 0x003c,
336 "Unable to allocate memory for response queue ptrs.\n");
73208dfd
AC		 337 goto fail_rsp_map;
338 }
9a347ff4
CD		 339 /*
340 * Make sure we record at least the request and response queue zero in
341 * case we need to free them if part of the probe fails.
342 */
343 ha->rsp_q_map[0] = rsp;
344 ha->req_q_map[0] = req;
73208dfd
AC		 345 set_bit(0, ha->rsp_qid_map);
346 set_bit(0, ha->req_qid_map);
347 return 1;
348
349fail_rsp_map:
350 kfree(ha->req_q_map);
351 ha->req_q_map = NULL;
352fail_req_map:
353 return -ENOMEM;
354}
355
2afa19a9 356static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req)
73208dfd 357{
8ae6d9c7
GM		 358 if (IS_QLAFX00(ha)) {
359 if (req && req->ring_fx00)
360 dma_free_coherent(&ha->pdev->dev,
361 (req->length_fx00 + 1) * sizeof(request_t),
362 req->ring_fx00, req->dma_fx00);
363 } else if (req && req->ring)
73208dfd
AC		 364 dma_free_coherent(&ha->pdev->dev,
365 (req->length + 1) * sizeof(request_t),
366 req->ring, req->dma);
367
8d93f550
CD		 368 if (req)
369 kfree(req->outstanding_cmds);
370
73208dfd
AC		 371 kfree(req);
372 req = NULL;
373}
374
2afa19a9
AC		 375static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp)
376{
8ae6d9c7
GM		 377 if (IS_QLAFX00(ha)) {
378 if (rsp && rsp->ring)
379 dma_free_coherent(&ha->pdev->dev,
380 (rsp->length_fx00 + 1) * sizeof(request_t),
381 rsp->ring_fx00, rsp->dma_fx00);
382 } else if (rsp && rsp->ring) {
2afa19a9
AC		 383 dma_free_coherent(&ha->pdev->dev,
384 (rsp->length + 1) * sizeof(response_t),
385 rsp->ring, rsp->dma);
8ae6d9c7 386 }
2afa19a9
AC		 387 kfree(rsp);
388 rsp = NULL;
389}
390
73208dfd
AC		 391static void qla2x00_free_queues(struct qla_hw_data *ha)
392{
393 struct req_que *req;
394 struct rsp_que *rsp;
395 int cnt;
396
2afa19a9 397 for (cnt = 0; cnt < ha->max_req_queues; cnt++) {
73208dfd 398 req = ha->req_q_map[cnt];
2afa19a9 399 qla2x00_free_req_que(ha, req);
73208dfd 400 }
73208dfd
AC		 401 kfree(ha->req_q_map);
402 ha->req_q_map = NULL;
2afa19a9
AC		 403
404 for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) {
405 rsp = ha->rsp_q_map[cnt];
406 qla2x00_free_rsp_que(ha, rsp);
407 }
408 kfree(ha->rsp_q_map);
409 ha->rsp_q_map = NULL;
73208dfd
AC		 410}
411
68ca949c
AC		 412static int qla25xx_setup_mode(struct scsi_qla_host *vha)
413{
414 uint16_t options = 0;
415 int ques, req, ret;
416 struct qla_hw_data *ha = vha->hw;
417
7163ea81 418 if (!(ha->fw_attributes & BIT_6)) {
7c3df132
SK		 419 ql_log(ql_log_warn, vha, 0x00d8,
420 "Firmware is not multi-queue capable.\n");
7163ea81
AC		 421 goto fail;
422 }
68ca949c 423 if (ql2xmultique_tag) {
68ca949c
AC		 424 /* create a request queue for IO */
425 options |= BIT_7;
426 req = qla25xx_create_req_que(ha, options, 0, 0, -1,
427 QLA_DEFAULT_QUE_QOS);
428 if (!req) {
7c3df132
SK		 429 ql_log(ql_log_warn, vha, 0x00e0,
430 "Failed to create request queue.\n");
68ca949c
AC		 431 goto fail;
432 }
278274d5 433 ha->wq = alloc_workqueue("qla2xxx_wq", WQ_MEM_RECLAIM, 1);
68ca949c
AC		 434 vha->req = ha->req_q_map[req];
435 options |= BIT_1;
436 for (ques = 1; ques < ha->max_rsp_queues; ques++) {
437 ret = qla25xx_create_rsp_que(ha, options, 0, 0, req);
438 if (!ret) {
7c3df132
SK		 439 ql_log(ql_log_warn, vha, 0x00e8,
440 "Failed to create response queue.\n");
68ca949c
AC		 441 goto fail2;
442 }
443 }
7163ea81 444 ha->flags.cpu_affinity_enabled = 1;
7c3df132
SK		 445 ql_dbg(ql_dbg_multiq, vha, 0xc007,
446 "CPU affinity mode enalbed, "
447 "no. of response queues:%d no. of request queues:%d.\n",
448 ha->max_rsp_queues, ha->max_req_queues);
449 ql_dbg(ql_dbg_init, vha, 0x00e9,
450 "CPU affinity mode enalbed, "
451 "no. of response queues:%d no. of request queues:%d.\n",
452 ha->max_rsp_queues, ha->max_req_queues);
68ca949c
AC		 453 }
454 return 0;
455fail2:
456 qla25xx_delete_queues(vha);
7163ea81
AC		 457 destroy_workqueue(ha->wq);
458 ha->wq = NULL;
0cd33fcf 459 vha->req = ha->req_q_map[0];
68ca949c
AC		 460fail:
461 ha->mqenable = 0;
7163ea81
AC		 462 kfree(ha->req_q_map);
463 kfree(ha->rsp_q_map);
464 ha->max_req_queues = ha->max_rsp_queues = 1;
68ca949c
AC		 465 return 1;
466}
467
1da177e4 468static char *
e315cd28 469qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str)
1da177e4 470{
e315cd28 471 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 472 static char *pci_bus_modes[] = {
473 "33", "66", "100", "133",
474 };
475 uint16_t pci_bus;
476
477 strcpy(str, "PCI");
478 pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9;
479 if (pci_bus) {
480 strcat(str, "-X (");
481 strcat(str, pci_bus_modes[pci_bus]);
482 } else {
483 pci_bus = (ha->pci_attr & BIT_8) >> 8;
484 strcat(str, " (");
485 strcat(str, pci_bus_modes[pci_bus]);
486 }
487 strcat(str, " MHz)");
488
489 return (str);
490}
491
fca29703 492static char *
e315cd28 493qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str)
fca29703
AV		 494{
495 static char *pci_bus_modes[] = { "33", "66", "100", "133", };
e315cd28 496 struct qla_hw_data *ha = vha->hw;
fca29703 497 uint32_t pci_bus;
fca29703 498
62a276f8 499 if (pci_is_pcie(ha->pdev)) {
fca29703 500 char lwstr[6];
62a276f8 501 uint32_t lstat, lspeed, lwidth;
fca29703 502
62a276f8
BH		 503 pcie_capability_read_dword(ha->pdev, PCI_EXP_LNKCAP, &lstat);
504 lspeed = lstat & PCI_EXP_LNKCAP_SLS;
505 lwidth = (lstat & PCI_EXP_LNKCAP_MLW) >> 4;
fca29703
AV		 506
507 strcpy(str, "PCIe (");
49300af7
SK		 508 switch (lspeed) {
509 case 1:
c87a0d8c 510 strcat(str, "2.5GT/s ");
49300af7
SK		 511 break;
512 case 2:
c87a0d8c 513 strcat(str, "5.0GT/s ");
49300af7
SK		 514 break;
515 case 3:
516 strcat(str, "8.0GT/s ");
517 break;
518 default:
fca29703 519 strcat(str, "<unknown> ");
49300af7
SK		 520 break;
521 }
fca29703
AV		 522 snprintf(lwstr, sizeof(lwstr), "x%d)", lwidth);
523 strcat(str, lwstr);
524
525 return str;
526 }
527
528 strcpy(str, "PCI");
529 pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8;
530 if (pci_bus == 0 || pci_bus == 8) {
531 strcat(str, " (");
532 strcat(str, pci_bus_modes[pci_bus >> 3]);
533 } else {
534 strcat(str, "-X ");
535 if (pci_bus & BIT_2)
536 strcat(str, "Mode 2");
537 else
538 strcat(str, "Mode 1");
539 strcat(str, " (");
540 strcat(str, pci_bus_modes[pci_bus & ~BIT_2]);
541 }
542 strcat(str, " MHz)");
543
544 return str;
545}
546
e5f82ab8 547static char *
e315cd28 548qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str)
1da177e4
LT		 549{
550 char un_str[10];
e315cd28 551 struct qla_hw_data *ha = vha->hw;
fa2a1ce5 552
1da177e4
LT		 553 sprintf(str, "%d.%02d.%02d ", ha->fw_major_version,
554 ha->fw_minor_version,
555 ha->fw_subminor_version);
556
557 if (ha->fw_attributes & BIT_9) {
558 strcat(str, "FLX");
559 return (str);
560 }
561
562 switch (ha->fw_attributes & 0xFF) {
563 case 0x7:
564 strcat(str, "EF");
565 break;
566 case 0x17:
567 strcat(str, "TP");
568 break;
569 case 0x37:
570 strcat(str, "IP");
571 break;
572 case 0x77:
573 strcat(str, "VI");
574 break;
575 default:
576 sprintf(un_str, "(%x)", ha->fw_attributes);
577 strcat(str, un_str);
578 break;
579 }
580 if (ha->fw_attributes & 0x100)
581 strcat(str, "X");
582
583 return (str);
584}
585
e5f82ab8 586static char *
e315cd28 587qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str)
fca29703 588{
e315cd28 589 struct qla_hw_data *ha = vha->hw;
f0883ac6 590
3a03eb79
AV		 591 sprintf(str, "%d.%02d.%02d (%x)", ha->fw_major_version,
592 ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes);
fca29703 593 return str;
fca29703
AV		 594}
595
9ba56b95
GM		 596void
597qla2x00_sp_free_dma(void *vha, void *ptr)
fca29703 598{
9ba56b95
GM		 599 srb_t *sp = (srb_t *)ptr;
600 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
601 struct qla_hw_data *ha = sp->fcport->vha->hw;
602 void *ctx = GET_CMD_CTX_SP(sp);
fca29703 603
9ba56b95
GM		 604 if (sp->flags & SRB_DMA_VALID) {
605 scsi_dma_unmap(cmd);
606 sp->flags &= ~SRB_DMA_VALID;
7c3df132 607 }
fca29703 608
9ba56b95
GM		 609 if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
610 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
611 scsi_prot_sg_count(cmd), cmd->sc_data_direction);
612 sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
613 }
614
615 if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
616 /* List assured to be having elements */
617 qla2x00_clean_dsd_pool(ha, sp);
618 sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
619 }
620
621 if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
622 dma_pool_free(ha->dl_dma_pool, ctx,
623 ((struct crc_context *)ctx)->crc_ctx_dma);
624 sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
625 }
626
627 if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
628 struct ct6_dsd *ctx1 = (struct ct6_dsd *)ctx;
fca29703 629
9ba56b95
GM		 630 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd,
631 ctx1->fcp_cmnd_dma);
632 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list);
633 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt;
634 ha->gbl_dsd_avail += ctx1->dsd_use_cnt;
635 mempool_free(ctx1, ha->ctx_mempool);
636 ctx1 = NULL;
637 }
638
639 CMD_SP(cmd) = NULL;
b00ee7d7 640 qla2x00_rel_sp(sp->fcport->vha, sp);
9ba56b95
GM		 641}
642
14b06808 643static void
9ba56b95
GM		 644qla2x00_sp_compl(void *data, void *ptr, int res)
645{
646 struct qla_hw_data *ha = (struct qla_hw_data *)data;
647 srb_t *sp = (srb_t *)ptr;
648 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
649
650 cmd->result = res;
651
652 if (atomic_read(&sp->ref_count) == 0) {
653 ql_dbg(ql_dbg_io, sp->fcport->vha, 0x3015,
654 "SP reference-count to ZERO -- sp=%p cmd=%p.\n",
655 sp, GET_CMD_SP(sp));
656 if (ql2xextended_error_logging & ql_dbg_io)
657 BUG();
658 return;
659 }
660 if (!atomic_dec_and_test(&sp->ref_count))
661 return;
662
663 qla2x00_sp_free_dma(ha, sp);
664 cmd->scsi_done(cmd);
fca29703
AV		 665}
666
8ae6d9c7
GM		 667/* If we are SP1 here, we need to still take and release the host_lock as SP1
668 * does not have the changes necessary to avoid taking host->host_lock.
669 */
1da177e4 670static int
f5e3e40b 671qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
fca29703 672{
134ae078 673 scsi_qla_host_t *vha = shost_priv(host);
fca29703 674 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
19a7b4ae 675 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
e315cd28
AC		 676 struct qla_hw_data *ha = vha->hw;
677 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
fca29703
AV		 678 srb_t *sp;
679 int rval;
680
85880801 681 if (ha->flags.eeh_busy) {
7c3df132 682 if (ha->flags.pci_channel_io_perm_failure) {
5f28d2d7 683 ql_dbg(ql_dbg_aer, vha, 0x9010,
7c3df132
SK		 684 "PCI Channel IO permanent failure, exiting "
685 "cmd=%p.\n", cmd);
b9b12f73 686 cmd->result = DID_NO_CONNECT << 16;
7c3df132 687 } else {
5f28d2d7 688 ql_dbg(ql_dbg_aer, vha, 0x9011,
7c3df132 689 "EEH_Busy, Requeuing the cmd=%p.\n", cmd);
85880801 690 cmd->result = DID_REQUEUE << 16;
7c3df132 691 }
14e660e6
SJ		 692 goto qc24_fail_command;
693 }
694
19a7b4ae
JSEC		 695 rval = fc_remote_port_chkready(rport);
696 if (rval) {
697 cmd->result = rval;
5f28d2d7 698 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3003,
7c3df132
SK		 699 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
700 cmd, rval);
fca29703
AV		 701 goto qc24_fail_command;
702 }
703
bad75002
AE		 704 if (!vha->flags.difdix_supported &&
705 scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) {
7c3df132
SK		 706 ql_dbg(ql_dbg_io, vha, 0x3004,
707 "DIF Cap not reg, fail DIF capable cmd's:%p.\n",
708 cmd);
bad75002
AE		 709 cmd->result = DID_NO_CONNECT << 16;
710 goto qc24_fail_command;
711 }
aa651be8
CD		 712
713 if (!fcport) {
714 cmd->result = DID_NO_CONNECT << 16;
715 goto qc24_fail_command;
716 }
717
fca29703
AV		 718 if (atomic_read(&fcport->state) != FCS_ONLINE) {
719 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
38170fa8 720 atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
7c3df132
SK		 721 ql_dbg(ql_dbg_io, vha, 0x3005,
722 "Returning DNC, fcport_state=%d loop_state=%d.\n",
723 atomic_read(&fcport->state),
724 atomic_read(&base_vha->loop_state));
fca29703
AV		 725 cmd->result = DID_NO_CONNECT << 16;
726 goto qc24_fail_command;
727 }
7b594131 728 goto qc24_target_busy;
fca29703
AV		 729 }
730
b00ee7d7 731 sp = qla2x00_get_sp(vha, fcport, GFP_ATOMIC);
50280c01 732 if (!sp)
f5e3e40b 733 goto qc24_host_busy;
fca29703 734
9ba56b95
GM		 735 sp->u.scmd.cmd = cmd;
736 sp->type = SRB_SCSI_CMD;
737 atomic_set(&sp->ref_count, 1);
738 CMD_SP(cmd) = (void *)sp;
739 sp->free = qla2x00_sp_free_dma;
740 sp->done = qla2x00_sp_compl;
741
e315cd28 742 rval = ha->isp_ops->start_scsi(sp);
7c3df132 743 if (rval != QLA_SUCCESS) {
53016ed3 744 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3013,
7c3df132 745 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
fca29703 746 goto qc24_host_busy_free_sp;
7c3df132 747 }
fca29703 748
fca29703
AV		 749 return 0;
750
751qc24_host_busy_free_sp:
9ba56b95 752 qla2x00_sp_free_dma(ha, sp);
fca29703 753
f5e3e40b 754qc24_host_busy:
fca29703
AV		 755 return SCSI_MLQUEUE_HOST_BUSY;
756
7b594131
MC		 757qc24_target_busy:
758 return SCSI_MLQUEUE_TARGET_BUSY;
759
fca29703 760qc24_fail_command:
f5e3e40b 761 cmd->scsi_done(cmd);
fca29703
AV		 762
763 return 0;
764}
765
1da177e4
LT		 766/*
767 * qla2x00_eh_wait_on_command
768 * Waits for the command to be returned by the Firmware for some
769 * max time.
770 *
771 * Input:
1da177e4 772 * cmd = Scsi Command to wait on.
1da177e4
LT		 773 *
774 * Return:
775 * Not Found : 0
776 * Found : 1
777 */
778static int
e315cd28 779qla2x00_eh_wait_on_command(struct scsi_cmnd *cmd)
1da177e4 780{
fe74c71f
AV		 781#define ABORT_POLLING_PERIOD 1000
782#define ABORT_WAIT_ITER ((10 * 1000) / (ABORT_POLLING_PERIOD))
f4f051eb 783 unsigned long wait_iter = ABORT_WAIT_ITER;
85880801
AV		 784 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
785 struct qla_hw_data *ha = vha->hw;
f4f051eb 786 int ret = QLA_SUCCESS;
1da177e4 787
85880801 788 if (unlikely(pci_channel_offline(ha->pdev)) || ha->flags.eeh_busy) {
7c3df132
SK		 789 ql_dbg(ql_dbg_taskm, vha, 0x8005,
790 "Return:eh_wait.\n");
85880801
AV		 791 return ret;
792 }
793
d970432c 794 while (CMD_SP(cmd) && wait_iter--) {
fe74c71f 795 msleep(ABORT_POLLING_PERIOD);
f4f051eb 796 }
797 if (CMD_SP(cmd))
798 ret = QLA_FUNCTION_FAILED;
1da177e4 799
f4f051eb 800 return ret;
1da177e4
LT		 801}
802
803/*
804 * qla2x00_wait_for_hba_online
fa2a1ce5 805 * Wait till the HBA is online after going through
1da177e4
LT		 806 * <= MAX_RETRIES_OF_ISP_ABORT or
807 * finally HBA is disabled ie marked offline
808 *
809 * Input:
810 * ha - pointer to host adapter structure
fa2a1ce5
AV		 811 *
812 * Note:
1da177e4
LT		 813 * Does context switching-Release SPIN_LOCK
814 * (if any) before calling this routine.
815 *
816 * Return:
817 * Success (Adapter is online) : 0
818 * Failed (Adapter is offline/disabled) : 1
819 */
854165f4 820int
e315cd28 821qla2x00_wait_for_hba_online(scsi_qla_host_t *vha)
1da177e4 822{
fca29703
AV		 823 int return_status;
824 unsigned long wait_online;
e315cd28
AC		 825 struct qla_hw_data *ha = vha->hw;
826 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4 827
fa2a1ce5 828 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ);
e315cd28
AC		 829 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
830 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
831 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
832 ha->dpc_active) && time_before(jiffies, wait_online)) {
1da177e4
LT		 833
834 msleep(1000);
835 }
e315cd28 836 if (base_vha->flags.online)
fa2a1ce5 837 return_status = QLA_SUCCESS;
1da177e4
LT		 838 else
839 return_status = QLA_FUNCTION_FAILED;
840
1da177e4
LT		 841 return (return_status);
842}
843
86fbee86
LC		 844/*
845 * qla2x00_wait_for_reset_ready
846 * Wait till the HBA is online after going through
847 * <= MAX_RETRIES_OF_ISP_ABORT or
848 * finally HBA is disabled ie marked offline or flash
849 * operations are in progress.
850 *
851 * Input:
852 * ha - pointer to host adapter structure
853 *
854 * Note:
855 * Does context switching-Release SPIN_LOCK
856 * (if any) before calling this routine.
857 *
858 * Return:
859 * Success (Adapter is online/no flash ops) : 0
860 * Failed (Adapter is offline/disabled/flash ops in progress) : 1
861 */
3dbe756a 862static int
86fbee86
LC		 863qla2x00_wait_for_reset_ready(scsi_qla_host_t *vha)
864{
865 int return_status;
866 unsigned long wait_online;
867 struct qla_hw_data *ha = vha->hw;
868 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
869
870 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ);
871 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
872 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
873 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
874 ha->optrom_state != QLA_SWAITING ||
875 ha->dpc_active) && time_before(jiffies, wait_online))
876 msleep(1000);
877
878 if (base_vha->flags.online && ha->optrom_state == QLA_SWAITING)
879 return_status = QLA_SUCCESS;
880 else
881 return_status = QLA_FUNCTION_FAILED;
882
7c3df132
SK		 883 ql_dbg(ql_dbg_taskm, vha, 0x8019,
884 "%s return status=%d.\n", __func__, return_status);
86fbee86
LC		 885
886 return return_status;
887}
888
2533cf67
LC		 889int
890qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha)
891{
892 int return_status;
893 unsigned long wait_reset;
894 struct qla_hw_data *ha = vha->hw;
895 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
896
897 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ);
898 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
899 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
900 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
901 ha->dpc_active) && time_before(jiffies, wait_reset)) {
902
903 msleep(1000);
904
905 if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) &&
906 ha->flags.chip_reset_done)
907 break;
908 }
909 if (ha->flags.chip_reset_done)
910 return_status = QLA_SUCCESS;
911 else
912 return_status = QLA_FUNCTION_FAILED;
913
914 return return_status;
915}
916
083a469d
GM		 917static void
918sp_get(struct srb *sp)
919{
920 atomic_inc(&sp->ref_count);
921}
922
1da177e4
LT		 923/**************************************************************************
924* qla2xxx_eh_abort
925*
926* Description:
927* The abort function will abort the specified command.
928*
929* Input:
930* cmd = Linux SCSI command packet to be aborted.
931*
932* Returns:
933* Either SUCCESS or FAILED.
934*
935* Note:
2ea00202 936* Only return FAILED if command not returned by firmware.
1da177e4 937**************************************************************************/
e5f82ab8 938static int
1da177e4
LT		 939qla2xxx_eh_abort(struct scsi_cmnd *cmd)
940{
e315cd28 941 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
f4f051eb 942 srb_t *sp;
4e98d3b8 943 int ret;
f4f051eb 944 unsigned int id, lun;
18e144d3 945 unsigned long flags;
2ea00202 946 int wait = 0;
e315cd28 947 struct qla_hw_data *ha = vha->hw;
1da177e4 948
f4f051eb 949 if (!CMD_SP(cmd))
2ea00202 950 return SUCCESS;
1da177e4 951
4e98d3b8
AV		 952 ret = fc_block_scsi_eh(cmd);
953 if (ret != 0)
954 return ret;
955 ret = SUCCESS;
956
f4f051eb 957 id = cmd->device->id;
958 lun = cmd->device->lun;
1da177e4 959
e315cd28 960 spin_lock_irqsave(&ha->hardware_lock, flags);
170babc3
MC		 961 sp = (srb_t *) CMD_SP(cmd);
962 if (!sp) {
963 spin_unlock_irqrestore(&ha->hardware_lock, flags);
964 return SUCCESS;
965 }
1da177e4 966
7c3df132 967 ql_dbg(ql_dbg_taskm, vha, 0x8002,
cfb0919c
CD		 968 "Aborting from RISC nexus=%ld:%d:%d sp=%p cmd=%p\n",
969 vha->host_no, id, lun, sp, cmd);
17d98630 970
170babc3
MC		 971 /* Get a reference to the sp and drop the lock.*/
972 sp_get(sp);
083a469d 973
e315cd28 974 spin_unlock_irqrestore(&ha->hardware_lock, flags);
170babc3 975 if (ha->isp_ops->abort_command(sp)) {
a55aac79 976 ret = FAILED;
7c3df132 977 ql_dbg(ql_dbg_taskm, vha, 0x8003,
cfb0919c 978 "Abort command mbx failed cmd=%p.\n", cmd);
170babc3 979 } else {
7c3df132 980 ql_dbg(ql_dbg_taskm, vha, 0x8004,
cfb0919c 981 "Abort command mbx success cmd=%p.\n", cmd);
170babc3
MC		 982 wait = 1;
983 }
75942064
SK		 984
985 spin_lock_irqsave(&ha->hardware_lock, flags);
9ba56b95 986 sp->done(ha, sp, 0);
75942064 987 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1da177e4 988
bc91ade9
CD		 989 /* Did the command return during mailbox execution? */
990 if (ret == FAILED && !CMD_SP(cmd))
991 ret = SUCCESS;
992
f4f051eb 993 /* Wait for the command to be returned. */
2ea00202 994 if (wait) {
e315cd28 995 if (qla2x00_eh_wait_on_command(cmd) != QLA_SUCCESS) {
7c3df132 996 ql_log(ql_log_warn, vha, 0x8006,
cfb0919c 997 "Abort handler timed out cmd=%p.\n", cmd);
2ea00202 998 ret = FAILED;
f4f051eb 999 }
1da177e4 1000 }
1da177e4 1001
7c3df132 1002 ql_log(ql_log_info, vha, 0x801c,
cfb0919c
CD		 1003 "Abort command issued nexus=%ld:%d:%d -- %d %x.\n",
1004 vha->host_no, id, lun, wait, ret);
1da177e4 1005
f4f051eb 1006 return ret;
1007}
1da177e4 1008
4d78c973 1009int
e315cd28 1010qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t,
4d78c973 1011 unsigned int l, enum nexus_wait_type type)
f4f051eb 1012{
17d98630 1013 int cnt, match, status;
18e144d3 1014 unsigned long flags;
e315cd28 1015 struct qla_hw_data *ha = vha->hw;
73208dfd 1016 struct req_que *req;
4d78c973 1017 srb_t *sp;
9ba56b95 1018 struct scsi_cmnd *cmd;
1da177e4 1019
523ec773 1020 status = QLA_SUCCESS;
17d98630 1021
e315cd28 1022 spin_lock_irqsave(&ha->hardware_lock, flags);
67c2e93a 1023 req = vha->req;
17d98630 1024 for (cnt = 1; status == QLA_SUCCESS &&
8d93f550 1025 cnt < req->num_outstanding_cmds; cnt++) {
17d98630
AC		 1026 sp = req->outstanding_cmds[cnt];
1027 if (!sp)
523ec773 1028 continue;
9ba56b95 1029 if (sp->type != SRB_SCSI_CMD)
cf53b069 1030 continue;
17d98630
AC		 1031 if (vha->vp_idx != sp->fcport->vha->vp_idx)
1032 continue;
1033 match = 0;
9ba56b95 1034 cmd = GET_CMD_SP(sp);
17d98630
AC		 1035 switch (type) {
1036 case WAIT_HOST:
1037 match = 1;
1038 break;
1039 case WAIT_TARGET:
9ba56b95 1040 match = cmd->device->id == t;
17d98630
AC		 1041 break;
1042 case WAIT_LUN:
9ba56b95
GM		 1043 match = (cmd->device->id == t &&
1044 cmd->device->lun == l);
17d98630 1045 break;
73208dfd 1046 }
17d98630
AC		 1047 if (!match)
1048 continue;
1049
1050 spin_unlock_irqrestore(&ha->hardware_lock, flags);
9ba56b95 1051 status = qla2x00_eh_wait_on_command(cmd);
17d98630 1052 spin_lock_irqsave(&ha->hardware_lock, flags);
1da177e4 1053 }
e315cd28 1054 spin_unlock_irqrestore(&ha->hardware_lock, flags);
523ec773
AV		 1055
1056 return status;
1da177e4
LT		 1057}
1058
523ec773
AV		 1059static char *reset_errors[] = {
1060 "HBA not online",
1061 "HBA not ready",
1062 "Task management failed",
1063 "Waiting for command completions",
1064};
1da177e4 1065
e5f82ab8 1066static int
523ec773 1067__qla2xxx_eh_generic_reset(char *name, enum nexus_wait_type type,
2afa19a9 1068 struct scsi_cmnd *cmd, int (*do_reset)(struct fc_port *, unsigned int, int))
1da177e4 1069{
e315cd28 1070 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
bdf79621 1071 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
523ec773 1072 int err;
1da177e4 1073
7c3df132 1074 if (!fcport) {
523ec773 1075 return FAILED;
7c3df132 1076 }
1da177e4 1077
4e98d3b8
AV		 1078 err = fc_block_scsi_eh(cmd);
1079 if (err != 0)
1080 return err;
1081
7c3df132 1082 ql_log(ql_log_info, vha, 0x8009,
cfb0919c 1083 "%s RESET ISSUED nexus=%ld:%d:%d cmd=%p.\n", name, vha->host_no,
7c3df132 1084 cmd->device->id, cmd->device->lun, cmd);
1da177e4 1085
523ec773 1086 err = 0;
7c3df132
SK		 1087 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1088 ql_log(ql_log_warn, vha, 0x800a,
1089 "Wait for hba online failed for cmd=%p.\n", cmd);
523ec773 1090 goto eh_reset_failed;
7c3df132 1091 }
523ec773 1092 err = 2;
2afa19a9 1093 if (do_reset(fcport, cmd->device->lun, cmd->request->cpu + 1)
7c3df132
SK		 1094 != QLA_SUCCESS) {
1095 ql_log(ql_log_warn, vha, 0x800c,
1096 "do_reset failed for cmd=%p.\n", cmd);
523ec773 1097 goto eh_reset_failed;
7c3df132 1098 }
523ec773 1099 err = 3;
e315cd28 1100 if (qla2x00_eh_wait_for_pending_commands(vha, cmd->device->id,
7c3df132
SK		 1101 cmd->device->lun, type) != QLA_SUCCESS) {
1102 ql_log(ql_log_warn, vha, 0x800d,
d6a03581 1103 "wait for pending cmds failed for cmd=%p.\n", cmd);
523ec773 1104 goto eh_reset_failed;
7c3df132 1105 }
523ec773 1106
7c3df132 1107 ql_log(ql_log_info, vha, 0x800e,
cfb0919c
CD		 1108 "%s RESET SUCCEEDED nexus:%ld:%d:%d cmd=%p.\n", name,
1109 vha->host_no, cmd->device->id, cmd->device->lun, cmd);
523ec773
AV		 1110
1111 return SUCCESS;
1112
4d78c973 1113eh_reset_failed:
7c3df132 1114 ql_log(ql_log_info, vha, 0x800f,
cfb0919c
CD		 1115 "%s RESET FAILED: %s nexus=%ld:%d:%d cmd=%p.\n", name,
1116 reset_errors[err], vha->host_no, cmd->device->id, cmd->device->lun,
1117 cmd);
523ec773
AV		 1118 return FAILED;
1119}
1da177e4 1120
523ec773
AV		 1121static int
1122qla2xxx_eh_device_reset(struct scsi_cmnd *cmd)
1123{
e315cd28
AC		 1124 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1125 struct qla_hw_data *ha = vha->hw;
1da177e4 1126
523ec773
AV		 1127 return __qla2xxx_eh_generic_reset("DEVICE", WAIT_LUN, cmd,
1128 ha->isp_ops->lun_reset);
1da177e4
LT		 1129}
1130
1da177e4 1131static int
523ec773 1132qla2xxx_eh_target_reset(struct scsi_cmnd *cmd)
1da177e4 1133{
e315cd28
AC		 1134 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1135 struct qla_hw_data *ha = vha->hw;
1da177e4 1136
523ec773
AV		 1137 return __qla2xxx_eh_generic_reset("TARGET", WAIT_TARGET, cmd,
1138 ha->isp_ops->target_reset);
1da177e4
LT		 1139}
1140
1da177e4
LT		 1141/**************************************************************************
1142* qla2xxx_eh_bus_reset
1143*
1144* Description:
1145* The bus reset function will reset the bus and abort any executing
1146* commands.
1147*
1148* Input:
1149* cmd = Linux SCSI command packet of the command that cause the
1150* bus reset.
1151*
1152* Returns:
1153* SUCCESS/FAILURE (defined as macro in scsi.h).
1154*
1155**************************************************************************/
e5f82ab8 1156static int
1da177e4
LT		 1157qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd)
1158{
e315cd28 1159 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
bdf79621 1160 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
2c3dfe3f 1161 int ret = FAILED;
f4f051eb 1162 unsigned int id, lun;
f4f051eb 1163
f4f051eb 1164 id = cmd->device->id;
1165 lun = cmd->device->lun;
1da177e4 1166
7c3df132 1167 if (!fcport) {
f4f051eb 1168 return ret;
7c3df132 1169 }
1da177e4 1170
4e98d3b8
AV		 1171 ret = fc_block_scsi_eh(cmd);
1172 if (ret != 0)
1173 return ret;
1174 ret = FAILED;
1175
7c3df132 1176 ql_log(ql_log_info, vha, 0x8012,
46270afe 1177 "BUS RESET ISSUED nexus=%ld:%d:%d.\n", vha->host_no, id, lun);
1da177e4 1178
e315cd28 1179 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
7c3df132
SK		 1180 ql_log(ql_log_fatal, vha, 0x8013,
1181 "Wait for hba online failed board disabled.\n");
f4f051eb 1182 goto eh_bus_reset_done;
1da177e4
LT		 1183 }
1184
ad537689
SK		 1185 if (qla2x00_loop_reset(vha) == QLA_SUCCESS)
1186 ret = SUCCESS;
1187
f4f051eb 1188 if (ret == FAILED)
1189 goto eh_bus_reset_done;
1da177e4 1190
9a41a62b 1191 /* Flush outstanding commands. */
4d78c973 1192 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) !=
7c3df132
SK		 1193 QLA_SUCCESS) {
1194 ql_log(ql_log_warn, vha, 0x8014,
1195 "Wait for pending commands failed.\n");
9a41a62b 1196 ret = FAILED;
7c3df132 1197 }
1da177e4 1198
f4f051eb 1199eh_bus_reset_done:
7c3df132 1200 ql_log(ql_log_warn, vha, 0x802b,
cfb0919c 1201 "BUS RESET %s nexus=%ld:%d:%d.\n",
d6a03581 1202 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1da177e4 1203
f4f051eb 1204 return ret;
1da177e4
LT		 1205}
1206
1207/**************************************************************************
1208* qla2xxx_eh_host_reset
1209*
1210* Description:
1211* The reset function will reset the Adapter.
1212*
1213* Input:
1214* cmd = Linux SCSI command packet of the command that cause the
1215* adapter reset.
1216*
1217* Returns:
1218* Either SUCCESS or FAILED.
1219*
1220* Note:
1221**************************************************************************/
e5f82ab8 1222static int
1da177e4
LT		 1223qla2xxx_eh_host_reset(struct scsi_cmnd *cmd)
1224{
e315cd28 1225 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
e315cd28 1226 struct qla_hw_data *ha = vha->hw;
2c3dfe3f 1227 int ret = FAILED;
f4f051eb 1228 unsigned int id, lun;
e315cd28 1229 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4 1230
f4f051eb 1231 id = cmd->device->id;
1232 lun = cmd->device->lun;
f4f051eb 1233
7c3df132 1234 ql_log(ql_log_info, vha, 0x8018,
cfb0919c 1235 "ADAPTER RESET ISSUED nexus=%ld:%d:%d.\n", vha->host_no, id, lun);
1da177e4 1236
86fbee86 1237 if (qla2x00_wait_for_reset_ready(vha) != QLA_SUCCESS)
f4f051eb 1238 goto eh_host_reset_lock;
1da177e4 1239
e315cd28
AC		 1240 if (vha != base_vha) {
1241 if (qla2x00_vp_abort_isp(vha))
f4f051eb 1242 goto eh_host_reset_lock;
e315cd28 1243 } else {
7ec0effd 1244 if (IS_P3P_TYPE(vha->hw)) {
a9083016
GM		 1245 if (!qla82xx_fcoe_ctx_reset(vha)) {
1246 /* Ctx reset success */
1247 ret = SUCCESS;
1248 goto eh_host_reset_lock;
1249 }
1250 /* fall thru if ctx reset failed */
1251 }
68ca949c
AC		 1252 if (ha->wq)
1253 flush_workqueue(ha->wq);
1254
e315cd28 1255 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
a9083016 1256 if (ha->isp_ops->abort_isp(base_vha)) {
e315cd28
AC		 1257 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1258 /* failed. schedule dpc to try */
1259 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
1260
7c3df132
SK		 1261 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1262 ql_log(ql_log_warn, vha, 0x802a,
1263 "wait for hba online failed.\n");
e315cd28 1264 goto eh_host_reset_lock;
7c3df132 1265 }
e315cd28
AC		 1266 }
1267 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
fa2a1ce5 1268 }
1da177e4 1269
e315cd28 1270 /* Waiting for command to be returned to OS.*/
4d78c973 1271 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) ==
e315cd28 1272 QLA_SUCCESS)
f4f051eb 1273 ret = SUCCESS;
1da177e4 1274
f4f051eb 1275eh_host_reset_lock:
cfb0919c
CD		 1276 ql_log(ql_log_info, vha, 0x8017,
1277 "ADAPTER RESET %s nexus=%ld:%d:%d.\n",
1278 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1da177e4 1279
f4f051eb 1280 return ret;
1281}
1da177e4
LT		 1282
1283/*
1284* qla2x00_loop_reset
1285* Issue loop reset.
1286*
1287* Input:
1288* ha = adapter block pointer.
1289*
1290* Returns:
1291* 0 = success
1292*/
a4722cf2 1293int
e315cd28 1294qla2x00_loop_reset(scsi_qla_host_t *vha)
1da177e4 1295{
0c8c39af 1296 int ret;
bdf79621 1297 struct fc_port *fcport;
e315cd28 1298 struct qla_hw_data *ha = vha->hw;
1da177e4 1299
5854771e
AB		 1300 if (IS_QLAFX00(ha)) {
1301 return qlafx00_loop_reset(vha);
1302 }
1303
f4c496c1 1304 if (ql2xtargetreset == 1 && ha->flags.enable_target_reset) {
55e5ed27
AV		 1305 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1306 if (fcport->port_type != FCT_TARGET)
1307 continue;
1308
1309 ret = ha->isp_ops->target_reset(fcport, 0, 0);
1310 if (ret != QLA_SUCCESS) {
7c3df132 1311 ql_dbg(ql_dbg_taskm, vha, 0x802c,
5854771e 1312 "Bus Reset failed: Reset=%d "
7c3df132 1313 "d_id=%x.\n", ret, fcport->d_id.b24);
55e5ed27
AV		 1314 }
1315 }
1316 }
1317
8ae6d9c7 1318
6246b8a1 1319 if (ha->flags.enable_lip_full_login && !IS_CNA_CAPABLE(ha)) {
0b7e7c53
AV		 1320 atomic_set(&vha->loop_state, LOOP_DOWN);
1321 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
1322 qla2x00_mark_all_devices_lost(vha, 0);
e315cd28 1323 ret = qla2x00_full_login_lip(vha);
0c8c39af 1324 if (ret != QLA_SUCCESS) {
7c3df132
SK		 1325 ql_dbg(ql_dbg_taskm, vha, 0x802d,
1326 "full_login_lip=%d.\n", ret);
749af3d5 1327 }
0c8c39af
AV		 1328 }
1329
0d6e61bc 1330 if (ha->flags.enable_lip_reset) {
e315cd28 1331 ret = qla2x00_lip_reset(vha);
ad537689 1332 if (ret != QLA_SUCCESS)
7c3df132
SK		 1333 ql_dbg(ql_dbg_taskm, vha, 0x802e,
1334 "lip_reset failed (%d).\n", ret);
1da177e4
LT		 1335 }
1336
1da177e4 1337 /* Issue marker command only when we are going to start the I/O */
e315cd28 1338 vha->marker_needed = 1;
1da177e4 1339
0c8c39af 1340 return QLA_SUCCESS;
1da177e4
LT		 1341}
1342
df4bf0bb 1343void
e315cd28 1344qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res)
df4bf0bb 1345{
73208dfd 1346 int que, cnt;
df4bf0bb
AV		 1347 unsigned long flags;
1348 srb_t *sp;
e315cd28 1349 struct qla_hw_data *ha = vha->hw;
73208dfd 1350 struct req_que *req;
df4bf0bb
AV		 1351
1352 spin_lock_irqsave(&ha->hardware_lock, flags);
2afa19a9 1353 for (que = 0; que < ha->max_req_queues; que++) {
29bdccbe 1354 req = ha->req_q_map[que];
73208dfd
AC		 1355 if (!req)
1356 continue;
8d93f550
CD		 1357 if (!req->outstanding_cmds)
1358 continue;
1359 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) {
73208dfd 1360 sp = req->outstanding_cmds[cnt];
e612d465 1361 if (sp) {
73208dfd 1362 req->outstanding_cmds[cnt] = NULL;
9ba56b95 1363 sp->done(vha, sp, res);
73208dfd 1364 }
df4bf0bb
AV		 1365 }
1366 }
1367 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1368}
1369
f4f051eb 1370static int
1371qla2xxx_slave_alloc(struct scsi_device *sdev)
1da177e4 1372{
bdf79621 1373 struct fc_rport *rport = starget_to_rport(scsi_target(sdev));
1da177e4 1374
19a7b4ae 1375 if (!rport || fc_remote_port_chkready(rport))
f4f051eb 1376 return -ENXIO;
bdf79621 1377
19a7b4ae 1378 sdev->hostdata = *(fc_port_t **)rport->dd_data;
1da177e4 1379
f4f051eb 1380 return 0;
1381}
1da177e4 1382
f4f051eb 1383static int
1384qla2xxx_slave_configure(struct scsi_device *sdev)
1385{
e315cd28 1386 scsi_qla_host_t *vha = shost_priv(sdev->host);
2afa19a9 1387 struct req_que *req = vha->req;
8482e118 1388
9e522cd8
AE		 1389 if (IS_T10_PI_CAPABLE(vha->hw))
1390 blk_queue_update_dma_alignment(sdev->request_queue, 0x7);
1391
f4f051eb 1392 if (sdev->tagged_supported)
73208dfd 1393 scsi_activate_tcq(sdev, req->max_q_depth);
f4f051eb 1394 else
73208dfd 1395 scsi_deactivate_tcq(sdev, req->max_q_depth);
f4f051eb 1396 return 0;
1397}
1da177e4 1398
f4f051eb 1399static void
1400qla2xxx_slave_destroy(struct scsi_device *sdev)
1401{
1402 sdev->hostdata = NULL;
1da177e4
LT		 1403}
1404
c45dd305
GM		 1405static void qla2x00_handle_queue_full(struct scsi_device *sdev, int qdepth)
1406{
1407 fc_port_t *fcport = (struct fc_port *) sdev->hostdata;
1408
1409 if (!scsi_track_queue_full(sdev, qdepth))
1410 return;
1411
7c3df132 1412 ql_dbg(ql_dbg_io, fcport->vha, 0x3029,
cfb0919c
CD		 1413 "Queue depth adjusted-down to %d for nexus=%ld:%d:%d.\n",
1414 sdev->queue_depth, fcport->vha->host_no, sdev->id, sdev->lun);
c45dd305
GM		 1415}
1416
1417static void qla2x00_adjust_sdev_qdepth_up(struct scsi_device *sdev, int qdepth)
1418{
1419 fc_port_t *fcport = sdev->hostdata;
1420 struct scsi_qla_host *vha = fcport->vha;
c45dd305
GM		 1421 struct req_que *req = NULL;
1422
1423 req = vha->req;
1424 if (!req)
1425 return;
1426
1427 if (req->max_q_depth <= sdev->queue_depth || req->max_q_depth < qdepth)
1428 return;
1429
1430 if (sdev->ordered_tags)
1431 scsi_adjust_queue_depth(sdev, MSG_ORDERED_TAG, qdepth);
1432 else
1433 scsi_adjust_queue_depth(sdev, MSG_SIMPLE_TAG, qdepth);
1434
7c3df132 1435 ql_dbg(ql_dbg_io, vha, 0x302a,
cfb0919c
CD		 1436 "Queue depth adjusted-up to %d for nexus=%ld:%d:%d.\n",
1437 sdev->queue_depth, fcport->vha->host_no, sdev->id, sdev->lun);
c45dd305
GM		 1438}
1439
ce7e4af7 1440static int
e881a172 1441qla2x00_change_queue_depth(struct scsi_device *sdev, int qdepth, int reason)
ce7e4af7 1442{
c45dd305
GM		 1443 switch (reason) {
1444 case SCSI_QDEPTH_DEFAULT:
1445 scsi_adjust_queue_depth(sdev, scsi_get_tag_type(sdev), qdepth);
1446 break;
1447 case SCSI_QDEPTH_QFULL:
1448 qla2x00_handle_queue_full(sdev, qdepth);
1449 break;
1450 case SCSI_QDEPTH_RAMP_UP:
1451 qla2x00_adjust_sdev_qdepth_up(sdev, qdepth);
1452 break;
1453 default:
08002af2 1454 return -EOPNOTSUPP;
c45dd305 1455 }
e881a172 1456
ce7e4af7
AV		 1457 return sdev->queue_depth;
1458}
1459
1460static int
1461qla2x00_change_queue_type(struct scsi_device *sdev, int tag_type)
1462{
1463 if (sdev->tagged_supported) {
1464 scsi_set_tag_type(sdev, tag_type);
1465 if (tag_type)
1466 scsi_activate_tcq(sdev, sdev->queue_depth);
1467 else
1468 scsi_deactivate_tcq(sdev, sdev->queue_depth);
1469 } else
1470 tag_type = 0;
1471
1472 return tag_type;
1473}
1474
1da177e4
LT		 1475/**
1476 * qla2x00_config_dma_addressing() - Configure OS DMA addressing method.
1477 * @ha: HA context
1478 *
1479 * At exit, the @ha's flags.enable_64bit_addressing set to indicated
1480 * supported addressing method.
1481 */
1482static void
53303c42 1483qla2x00_config_dma_addressing(struct qla_hw_data *ha)
1da177e4 1484{
7524f9b9 1485 /* Assume a 32bit DMA mask. */
1da177e4 1486 ha->flags.enable_64bit_addressing = 0;
1da177e4 1487
6a35528a 1488 if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) {
7524f9b9
AV		 1489 /* Any upper-dword bits set? */
1490 if (MSD(dma_get_required_mask(&ha->pdev->dev)) &&
6a35528a 1491 !pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(64))) {
7524f9b9 1492 /* Ok, a 64bit DMA mask is applicable. */
1da177e4 1493 ha->flags.enable_64bit_addressing = 1;
fd34f556
AV		 1494 ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64;
1495 ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64;
7524f9b9 1496 return;
1da177e4 1497 }
1da177e4 1498 }
7524f9b9 1499
284901a9
YH		 1500 dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32));
1501 pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(32));
1da177e4
LT		 1502}
1503
fd34f556 1504static void
e315cd28 1505qla2x00_enable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1506{
1507 unsigned long flags = 0;
1508 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1509
1510 spin_lock_irqsave(&ha->hardware_lock, flags);
1511 ha->interrupts_on = 1;
1512 /* enable risc and host interrupts */
1513 WRT_REG_WORD(&reg->ictrl, ICR_EN_INT | ICR_EN_RISC);
1514 RD_REG_WORD(&reg->ictrl);
1515 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1516
1517}
1518
1519static void
e315cd28 1520qla2x00_disable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1521{
1522 unsigned long flags = 0;
1523 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1524
1525 spin_lock_irqsave(&ha->hardware_lock, flags);
1526 ha->interrupts_on = 0;
1527 /* disable risc and host interrupts */
1528 WRT_REG_WORD(&reg->ictrl, 0);
1529 RD_REG_WORD(&reg->ictrl);
1530 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1531}
1532
1533static void
e315cd28 1534qla24xx_enable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1535{
1536 unsigned long flags = 0;
1537 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1538
1539 spin_lock_irqsave(&ha->hardware_lock, flags);
1540 ha->interrupts_on = 1;
1541 WRT_REG_DWORD(&reg->ictrl, ICRX_EN_RISC_INT);
1542 RD_REG_DWORD(&reg->ictrl);
1543 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1544}
1545
1546static void
e315cd28 1547qla24xx_disable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1548{
1549 unsigned long flags = 0;
1550 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1551
124f85e6
AV		 1552 if (IS_NOPOLLING_TYPE(ha))
1553 return;
fd34f556
AV		 1554 spin_lock_irqsave(&ha->hardware_lock, flags);
1555 ha->interrupts_on = 0;
1556 WRT_REG_DWORD(&reg->ictrl, 0);
1557 RD_REG_DWORD(&reg->ictrl);
1558 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1559}
1560
706f457d
GM		 1561static int
1562qla2x00_iospace_config(struct qla_hw_data *ha)
1563{
1564 resource_size_t pio;
1565 uint16_t msix;
1566 int cpus;
1567
706f457d
GM		 1568 if (pci_request_selected_regions(ha->pdev, ha->bars,
1569 QLA2XXX_DRIVER_NAME)) {
1570 ql_log_pci(ql_log_fatal, ha->pdev, 0x0011,
1571 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
1572 pci_name(ha->pdev));
1573 goto iospace_error_exit;
1574 }
1575 if (!(ha->bars & 1))
1576 goto skip_pio;
1577
1578 /* We only need PIO for Flash operations on ISP2312 v2 chips. */
1579 pio = pci_resource_start(ha->pdev, 0);
1580 if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) {
1581 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
1582 ql_log_pci(ql_log_warn, ha->pdev, 0x0012,
1583 "Invalid pci I/O region size (%s).\n",
1584 pci_name(ha->pdev));
1585 pio = 0;
1586 }
1587 } else {
1588 ql_log_pci(ql_log_warn, ha->pdev, 0x0013,
1589 "Region #0 no a PIO resource (%s).\n",
1590 pci_name(ha->pdev));
1591 pio = 0;
1592 }
1593 ha->pio_address = pio;
1594 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014,
1595 "PIO address=%llu.\n",
1596 (unsigned long long)ha->pio_address);
1597
1598skip_pio:
1599 /* Use MMIO operations for all accesses. */
1600 if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) {
1601 ql_log_pci(ql_log_fatal, ha->pdev, 0x0015,
1602 "Region #1 not an MMIO resource (%s), aborting.\n",
1603 pci_name(ha->pdev));
1604 goto iospace_error_exit;
1605 }
1606 if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) {
1607 ql_log_pci(ql_log_fatal, ha->pdev, 0x0016,
1608 "Invalid PCI mem region size (%s), aborting.\n",
1609 pci_name(ha->pdev));
1610 goto iospace_error_exit;
1611 }
1612
1613 ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN);
1614 if (!ha->iobase) {
1615 ql_log_pci(ql_log_fatal, ha->pdev, 0x0017,
1616 "Cannot remap MMIO (%s), aborting.\n",
1617 pci_name(ha->pdev));
1618 goto iospace_error_exit;
1619 }
1620
1621 /* Determine queue resources */
1622 ha->max_req_queues = ha->max_rsp_queues = 1;
1623 if ((ql2xmaxqueues <= 1 && !ql2xmultique_tag) ||
1624 (ql2xmaxqueues > 1 && ql2xmultique_tag) ||
1625 (!IS_QLA25XX(ha) && !IS_QLA81XX(ha)))
1626 goto mqiobase_exit;
1627
1628 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3),
1629 pci_resource_len(ha->pdev, 3));
1630 if (ha->mqiobase) {
1631 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018,
1632 "MQIO Base=%p.\n", ha->mqiobase);
1633 /* Read MSIX vector size of the board */
1634 pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix);
1635 ha->msix_count = msix;
1636 /* Max queues are bounded by available msix vectors */
1637 /* queue 0 uses two msix vectors */
1638 if (ql2xmultique_tag) {
1639 cpus = num_online_cpus();
1640 ha->max_rsp_queues = (ha->msix_count - 1 > cpus) ?
1641 (cpus + 1) : (ha->msix_count - 1);
1642 ha->max_req_queues = 2;
1643 } else if (ql2xmaxqueues > 1) {
1644 ha->max_req_queues = ql2xmaxqueues > QLA_MQ_SIZE ?
1645 QLA_MQ_SIZE : ql2xmaxqueues;
1646 ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc008,
1647 "QoS mode set, max no of request queues:%d.\n",
1648 ha->max_req_queues);
1649 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0019,
1650 "QoS mode set, max no of request queues:%d.\n",
1651 ha->max_req_queues);
1652 }
1653 ql_log_pci(ql_log_info, ha->pdev, 0x001a,
1654 "MSI-X vector count: %d.\n", msix);
1655 } else
1656 ql_log_pci(ql_log_info, ha->pdev, 0x001b,
1657 "BAR 3 not enabled.\n");
1658
1659mqiobase_exit:
1660 ha->msix_count = ha->max_rsp_queues + 1;
1661 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c,
1662 "MSIX Count:%d.\n", ha->msix_count);
1663 return (0);
1664
1665iospace_error_exit:
1666 return (-ENOMEM);
1667}
1668
1669
6246b8a1
GM		 1670static int
1671qla83xx_iospace_config(struct qla_hw_data *ha)
1672{
1673 uint16_t msix;
1674 int cpus;
1675
1676 if (pci_request_selected_regions(ha->pdev, ha->bars,
1677 QLA2XXX_DRIVER_NAME)) {
1678 ql_log_pci(ql_log_fatal, ha->pdev, 0x0117,
1679 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
1680 pci_name(ha->pdev));
1681
1682 goto iospace_error_exit;
1683 }
1684
1685 /* Use MMIO operations for all accesses. */
1686 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) {
1687 ql_log_pci(ql_log_warn, ha->pdev, 0x0118,
1688 "Invalid pci I/O region size (%s).\n",
1689 pci_name(ha->pdev));
1690 goto iospace_error_exit;
1691 }
1692 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
1693 ql_log_pci(ql_log_warn, ha->pdev, 0x0119,
1694 "Invalid PCI mem region size (%s), aborting\n",
1695 pci_name(ha->pdev));
1696 goto iospace_error_exit;
1697 }
1698
1699 ha->iobase = ioremap(pci_resource_start(ha->pdev, 0), MIN_IOBASE_LEN);
1700 if (!ha->iobase) {
1701 ql_log_pci(ql_log_fatal, ha->pdev, 0x011a,
1702 "Cannot remap MMIO (%s), aborting.\n",
1703 pci_name(ha->pdev));
1704 goto iospace_error_exit;
1705 }
1706
1707 /* 64bit PCI BAR - BAR2 will correspoond to region 4 */
1708 /* 83XX 26XX always use MQ type access for queues
1709 * - mbar 2, a.k.a region 4 */
1710 ha->max_req_queues = ha->max_rsp_queues = 1;
1711 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 4),
1712 pci_resource_len(ha->pdev, 4));
1713
1714 if (!ha->mqiobase) {
1715 ql_log_pci(ql_log_fatal, ha->pdev, 0x011d,
1716 "BAR2/region4 not enabled\n");
1717 goto mqiobase_exit;
1718 }
1719
1720 ha->msixbase = ioremap(pci_resource_start(ha->pdev, 2),
1721 pci_resource_len(ha->pdev, 2));
1722 if (ha->msixbase) {
1723 /* Read MSIX vector size of the board */
1724 pci_read_config_word(ha->pdev,
1725 QLA_83XX_PCI_MSIX_CONTROL, &msix);
1726 ha->msix_count = msix;
1727 /* Max queues are bounded by available msix vectors */
1728 /* queue 0 uses two msix vectors */
1729 if (ql2xmultique_tag) {
1730 cpus = num_online_cpus();
1731 ha->max_rsp_queues = (ha->msix_count - 1 > cpus) ?
1732 (cpus + 1) : (ha->msix_count - 1);
1733 ha->max_req_queues = 2;
1734 } else if (ql2xmaxqueues > 1) {
1735 ha->max_req_queues = ql2xmaxqueues > QLA_MQ_SIZE ?
1736 QLA_MQ_SIZE : ql2xmaxqueues;
1737 ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc00c,
1738 "QoS mode set, max no of request queues:%d.\n",
1739 ha->max_req_queues);
1740 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b,
1741 "QoS mode set, max no of request queues:%d.\n",
1742 ha->max_req_queues);
1743 }
1744 ql_log_pci(ql_log_info, ha->pdev, 0x011c,
1745 "MSI-X vector count: %d.\n", msix);
1746 } else
1747 ql_log_pci(ql_log_info, ha->pdev, 0x011e,
1748 "BAR 1 not enabled.\n");
1749
1750mqiobase_exit:
1751 ha->msix_count = ha->max_rsp_queues + 1;
aa230bc5
AE		 1752
1753 qlt_83xx_iospace_config(ha);
1754
6246b8a1
GM		 1755 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011f,
1756 "MSIX Count:%d.\n", ha->msix_count);
1757 return 0;
1758
1759iospace_error_exit:
1760 return -ENOMEM;
1761}
1762
fd34f556
AV		 1763static struct isp_operations qla2100_isp_ops = {
1764 .pci_config = qla2100_pci_config,
1765 .reset_chip = qla2x00_reset_chip,
1766 .chip_diag = qla2x00_chip_diag,
1767 .config_rings = qla2x00_config_rings,
1768 .reset_adapter = qla2x00_reset_adapter,
1769 .nvram_config = qla2x00_nvram_config,
1770 .update_fw_options = qla2x00_update_fw_options,
1771 .load_risc = qla2x00_load_risc,
1772 .pci_info_str = qla2x00_pci_info_str,
1773 .fw_version_str = qla2x00_fw_version_str,
1774 .intr_handler = qla2100_intr_handler,
1775 .enable_intrs = qla2x00_enable_intrs,
1776 .disable_intrs = qla2x00_disable_intrs,
1777 .abort_command = qla2x00_abort_command,
523ec773
AV		 1778 .target_reset = qla2x00_abort_target,
1779 .lun_reset = qla2x00_lun_reset,
fd34f556
AV		 1780 .fabric_login = qla2x00_login_fabric,
1781 .fabric_logout = qla2x00_fabric_logout,
1782 .calc_req_entries = qla2x00_calc_iocbs_32,
1783 .build_iocbs = qla2x00_build_scsi_iocbs_32,
1784 .prep_ms_iocb = qla2x00_prep_ms_iocb,
1785 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
1786 .read_nvram = qla2x00_read_nvram_data,
1787 .write_nvram = qla2x00_write_nvram_data,
1788 .fw_dump = qla2100_fw_dump,
1789 .beacon_on = NULL,
1790 .beacon_off = NULL,
1791 .beacon_blink = NULL,
1792 .read_optrom = qla2x00_read_optrom_data,
1793 .write_optrom = qla2x00_write_optrom_data,
1794 .get_flash_version = qla2x00_get_flash_version,
e315cd28 1795 .start_scsi = qla2x00_start_scsi,
a9083016 1796 .abort_isp = qla2x00_abort_isp,
706f457d 1797 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 1798 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 1799};
1800
1801static struct isp_operations qla2300_isp_ops = {
1802 .pci_config = qla2300_pci_config,
1803 .reset_chip = qla2x00_reset_chip,
1804 .chip_diag = qla2x00_chip_diag,
1805 .config_rings = qla2x00_config_rings,
1806 .reset_adapter = qla2x00_reset_adapter,
1807 .nvram_config = qla2x00_nvram_config,
1808 .update_fw_options = qla2x00_update_fw_options,
1809 .load_risc = qla2x00_load_risc,
1810 .pci_info_str = qla2x00_pci_info_str,
1811 .fw_version_str = qla2x00_fw_version_str,
1812 .intr_handler = qla2300_intr_handler,
1813 .enable_intrs = qla2x00_enable_intrs,
1814 .disable_intrs = qla2x00_disable_intrs,
1815 .abort_command = qla2x00_abort_command,
523ec773
AV		 1816 .target_reset = qla2x00_abort_target,
1817 .lun_reset = qla2x00_lun_reset,
fd34f556
AV		 1818 .fabric_login = qla2x00_login_fabric,
1819 .fabric_logout = qla2x00_fabric_logout,
1820 .calc_req_entries = qla2x00_calc_iocbs_32,
1821 .build_iocbs = qla2x00_build_scsi_iocbs_32,
1822 .prep_ms_iocb = qla2x00_prep_ms_iocb,
1823 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
1824 .read_nvram = qla2x00_read_nvram_data,
1825 .write_nvram = qla2x00_write_nvram_data,
1826 .fw_dump = qla2300_fw_dump,
1827 .beacon_on = qla2x00_beacon_on,
1828 .beacon_off = qla2x00_beacon_off,
1829 .beacon_blink = qla2x00_beacon_blink,
1830 .read_optrom = qla2x00_read_optrom_data,
1831 .write_optrom = qla2x00_write_optrom_data,
1832 .get_flash_version = qla2x00_get_flash_version,
e315cd28 1833 .start_scsi = qla2x00_start_scsi,
a9083016 1834 .abort_isp = qla2x00_abort_isp,
7ec0effd 1835 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 1836 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 1837};
1838
1839static struct isp_operations qla24xx_isp_ops = {
1840 .pci_config = qla24xx_pci_config,
1841 .reset_chip = qla24xx_reset_chip,
1842 .chip_diag = qla24xx_chip_diag,
1843 .config_rings = qla24xx_config_rings,
1844 .reset_adapter = qla24xx_reset_adapter,
1845 .nvram_config = qla24xx_nvram_config,
1846 .update_fw_options = qla24xx_update_fw_options,
1847 .load_risc = qla24xx_load_risc,
1848 .pci_info_str = qla24xx_pci_info_str,
1849 .fw_version_str = qla24xx_fw_version_str,
1850 .intr_handler = qla24xx_intr_handler,
1851 .enable_intrs = qla24xx_enable_intrs,
1852 .disable_intrs = qla24xx_disable_intrs,
1853 .abort_command = qla24xx_abort_command,
523ec773
AV		 1854 .target_reset = qla24xx_abort_target,
1855 .lun_reset = qla24xx_lun_reset,
fd34f556
AV		 1856 .fabric_login = qla24xx_login_fabric,
1857 .fabric_logout = qla24xx_fabric_logout,
1858 .calc_req_entries = NULL,
1859 .build_iocbs = NULL,
1860 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1861 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1862 .read_nvram = qla24xx_read_nvram_data,
1863 .write_nvram = qla24xx_write_nvram_data,
1864 .fw_dump = qla24xx_fw_dump,
1865 .beacon_on = qla24xx_beacon_on,
1866 .beacon_off = qla24xx_beacon_off,
1867 .beacon_blink = qla24xx_beacon_blink,
1868 .read_optrom = qla24xx_read_optrom_data,
1869 .write_optrom = qla24xx_write_optrom_data,
1870 .get_flash_version = qla24xx_get_flash_version,
e315cd28 1871 .start_scsi = qla24xx_start_scsi,
a9083016 1872 .abort_isp = qla2x00_abort_isp,
7ec0effd 1873 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 1874 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 1875};
1876
c3a2f0df
AV		 1877static struct isp_operations qla25xx_isp_ops = {
1878 .pci_config = qla25xx_pci_config,
1879 .reset_chip = qla24xx_reset_chip,
1880 .chip_diag = qla24xx_chip_diag,
1881 .config_rings = qla24xx_config_rings,
1882 .reset_adapter = qla24xx_reset_adapter,
1883 .nvram_config = qla24xx_nvram_config,
1884 .update_fw_options = qla24xx_update_fw_options,
1885 .load_risc = qla24xx_load_risc,
1886 .pci_info_str = qla24xx_pci_info_str,
1887 .fw_version_str = qla24xx_fw_version_str,
1888 .intr_handler = qla24xx_intr_handler,
1889 .enable_intrs = qla24xx_enable_intrs,
1890 .disable_intrs = qla24xx_disable_intrs,
1891 .abort_command = qla24xx_abort_command,
523ec773
AV		 1892 .target_reset = qla24xx_abort_target,
1893 .lun_reset = qla24xx_lun_reset,
c3a2f0df
AV		 1894 .fabric_login = qla24xx_login_fabric,
1895 .fabric_logout = qla24xx_fabric_logout,
1896 .calc_req_entries = NULL,
1897 .build_iocbs = NULL,
1898 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1899 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1900 .read_nvram = qla25xx_read_nvram_data,
1901 .write_nvram = qla25xx_write_nvram_data,
1902 .fw_dump = qla25xx_fw_dump,
1903 .beacon_on = qla24xx_beacon_on,
1904 .beacon_off = qla24xx_beacon_off,
1905 .beacon_blink = qla24xx_beacon_blink,
338c9161 1906 .read_optrom = qla25xx_read_optrom_data,
c3a2f0df
AV		 1907 .write_optrom = qla24xx_write_optrom_data,
1908 .get_flash_version = qla24xx_get_flash_version,
bad75002 1909 .start_scsi = qla24xx_dif_start_scsi,
a9083016 1910 .abort_isp = qla2x00_abort_isp,
7ec0effd 1911 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 1912 .initialize_adapter = qla2x00_initialize_adapter,
c3a2f0df
AV		 1913};
1914
3a03eb79
AV		 1915static struct isp_operations qla81xx_isp_ops = {
1916 .pci_config = qla25xx_pci_config,
1917 .reset_chip = qla24xx_reset_chip,
1918 .chip_diag = qla24xx_chip_diag,
1919 .config_rings = qla24xx_config_rings,
1920 .reset_adapter = qla24xx_reset_adapter,
1921 .nvram_config = qla81xx_nvram_config,
1922 .update_fw_options = qla81xx_update_fw_options,
eaac30be 1923 .load_risc = qla81xx_load_risc,
3a03eb79
AV		 1924 .pci_info_str = qla24xx_pci_info_str,
1925 .fw_version_str = qla24xx_fw_version_str,
1926 .intr_handler = qla24xx_intr_handler,
1927 .enable_intrs = qla24xx_enable_intrs,
1928 .disable_intrs = qla24xx_disable_intrs,
1929 .abort_command = qla24xx_abort_command,
1930 .target_reset = qla24xx_abort_target,
1931 .lun_reset = qla24xx_lun_reset,
1932 .fabric_login = qla24xx_login_fabric,
1933 .fabric_logout = qla24xx_fabric_logout,
1934 .calc_req_entries = NULL,
1935 .build_iocbs = NULL,
1936 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1937 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
3d79038f
AV		 1938 .read_nvram = NULL,
1939 .write_nvram = NULL,
3a03eb79
AV		 1940 .fw_dump = qla81xx_fw_dump,
1941 .beacon_on = qla24xx_beacon_on,
1942 .beacon_off = qla24xx_beacon_off,
6246b8a1 1943 .beacon_blink = qla83xx_beacon_blink,
3a03eb79
AV		 1944 .read_optrom = qla25xx_read_optrom_data,
1945 .write_optrom = qla24xx_write_optrom_data,
1946 .get_flash_version = qla24xx_get_flash_version,
ba77ef53 1947 .start_scsi = qla24xx_dif_start_scsi,
a9083016 1948 .abort_isp = qla2x00_abort_isp,
7ec0effd 1949 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 1950 .initialize_adapter = qla2x00_initialize_adapter,
a9083016
GM		 1951};
1952
1953static struct isp_operations qla82xx_isp_ops = {
1954 .pci_config = qla82xx_pci_config,
1955 .reset_chip = qla82xx_reset_chip,
1956 .chip_diag = qla24xx_chip_diag,
1957 .config_rings = qla82xx_config_rings,
1958 .reset_adapter = qla24xx_reset_adapter,
1959 .nvram_config = qla81xx_nvram_config,
1960 .update_fw_options = qla24xx_update_fw_options,
1961 .load_risc = qla82xx_load_risc,
9d55ca66 1962 .pci_info_str = qla24xx_pci_info_str,
a9083016
GM		 1963 .fw_version_str = qla24xx_fw_version_str,
1964 .intr_handler = qla82xx_intr_handler,
1965 .enable_intrs = qla82xx_enable_intrs,
1966 .disable_intrs = qla82xx_disable_intrs,
1967 .abort_command = qla24xx_abort_command,
1968 .target_reset = qla24xx_abort_target,
1969 .lun_reset = qla24xx_lun_reset,
1970 .fabric_login = qla24xx_login_fabric,
1971 .fabric_logout = qla24xx_fabric_logout,
1972 .calc_req_entries = NULL,
1973 .build_iocbs = NULL,
1974 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1975 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1976 .read_nvram = qla24xx_read_nvram_data,
1977 .write_nvram = qla24xx_write_nvram_data,
a1b23c5a 1978 .fw_dump = qla82xx_fw_dump,
999916dc
SK		 1979 .beacon_on = qla82xx_beacon_on,
1980 .beacon_off = qla82xx_beacon_off,
1981 .beacon_blink = NULL,
a9083016
GM		 1982 .read_optrom = qla82xx_read_optrom_data,
1983 .write_optrom = qla82xx_write_optrom_data,
7ec0effd 1984 .get_flash_version = qla82xx_get_flash_version,
a9083016
GM		 1985 .start_scsi = qla82xx_start_scsi,
1986 .abort_isp = qla82xx_abort_isp,
706f457d 1987 .iospace_config = qla82xx_iospace_config,
8ae6d9c7 1988 .initialize_adapter = qla2x00_initialize_adapter,
3a03eb79
AV		 1989};
1990
7ec0effd
AD		 1991static struct isp_operations qla8044_isp_ops = {
1992 .pci_config = qla82xx_pci_config,
1993 .reset_chip = qla82xx_reset_chip,
1994 .chip_diag = qla24xx_chip_diag,
1995 .config_rings = qla82xx_config_rings,
1996 .reset_adapter = qla24xx_reset_adapter,
1997 .nvram_config = qla81xx_nvram_config,
1998 .update_fw_options = qla24xx_update_fw_options,
1999 .load_risc = qla82xx_load_risc,
2000 .pci_info_str = qla24xx_pci_info_str,
2001 .fw_version_str = qla24xx_fw_version_str,
2002 .intr_handler = qla8044_intr_handler,
2003 .enable_intrs = qla82xx_enable_intrs,
2004 .disable_intrs = qla82xx_disable_intrs,
2005 .abort_command = qla24xx_abort_command,
2006 .target_reset = qla24xx_abort_target,
2007 .lun_reset = qla24xx_lun_reset,
2008 .fabric_login = qla24xx_login_fabric,
2009 .fabric_logout = qla24xx_fabric_logout,
2010 .calc_req_entries = NULL,
2011 .build_iocbs = NULL,
2012 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2013 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2014 .read_nvram = NULL,
2015 .write_nvram = NULL,
a1b23c5a 2016 .fw_dump = qla8044_fw_dump,
7ec0effd
AD		 2017 .beacon_on = qla82xx_beacon_on,
2018 .beacon_off = qla82xx_beacon_off,
2019 .beacon_blink = NULL,
888e639d 2020 .read_optrom = qla8044_read_optrom_data,
7ec0effd
AD		 2021 .write_optrom = qla8044_write_optrom_data,
2022 .get_flash_version = qla82xx_get_flash_version,
2023 .start_scsi = qla82xx_start_scsi,
2024 .abort_isp = qla8044_abort_isp,
2025 .iospace_config = qla82xx_iospace_config,
2026 .initialize_adapter = qla2x00_initialize_adapter,
2027};
2028
6246b8a1
GM		 2029static struct isp_operations qla83xx_isp_ops = {
2030 .pci_config = qla25xx_pci_config,
2031 .reset_chip = qla24xx_reset_chip,
2032 .chip_diag = qla24xx_chip_diag,
2033 .config_rings = qla24xx_config_rings,
2034 .reset_adapter = qla24xx_reset_adapter,
2035 .nvram_config = qla81xx_nvram_config,
2036 .update_fw_options = qla81xx_update_fw_options,
2037 .load_risc = qla81xx_load_risc,
2038 .pci_info_str = qla24xx_pci_info_str,
2039 .fw_version_str = qla24xx_fw_version_str,
2040 .intr_handler = qla24xx_intr_handler,
2041 .enable_intrs = qla24xx_enable_intrs,
2042 .disable_intrs = qla24xx_disable_intrs,
2043 .abort_command = qla24xx_abort_command,
2044 .target_reset = qla24xx_abort_target,
2045 .lun_reset = qla24xx_lun_reset,
2046 .fabric_login = qla24xx_login_fabric,
2047 .fabric_logout = qla24xx_fabric_logout,
2048 .calc_req_entries = NULL,
2049 .build_iocbs = NULL,
2050 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2051 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2052 .read_nvram = NULL,
2053 .write_nvram = NULL,
2054 .fw_dump = qla83xx_fw_dump,
2055 .beacon_on = qla24xx_beacon_on,
2056 .beacon_off = qla24xx_beacon_off,
2057 .beacon_blink = qla83xx_beacon_blink,
2058 .read_optrom = qla25xx_read_optrom_data,
2059 .write_optrom = qla24xx_write_optrom_data,
2060 .get_flash_version = qla24xx_get_flash_version,
2061 .start_scsi = qla24xx_dif_start_scsi,
2062 .abort_isp = qla2x00_abort_isp,
2063 .iospace_config = qla83xx_iospace_config,
8ae6d9c7
GM		 2064 .initialize_adapter = qla2x00_initialize_adapter,
2065};
2066
2067static struct isp_operations qlafx00_isp_ops = {
2068 .pci_config = qlafx00_pci_config,
2069 .reset_chip = qlafx00_soft_reset,
2070 .chip_diag = qlafx00_chip_diag,
2071 .config_rings = qlafx00_config_rings,
2072 .reset_adapter = qlafx00_soft_reset,
2073 .nvram_config = NULL,
2074 .update_fw_options = NULL,
2075 .load_risc = NULL,
2076 .pci_info_str = qlafx00_pci_info_str,
2077 .fw_version_str = qlafx00_fw_version_str,
2078 .intr_handler = qlafx00_intr_handler,
2079 .enable_intrs = qlafx00_enable_intrs,
2080 .disable_intrs = qlafx00_disable_intrs,
2081 .abort_command = qlafx00_abort_command,
2082 .target_reset = qlafx00_abort_target,
2083 .lun_reset = qlafx00_lun_reset,
2084 .fabric_login = NULL,
2085 .fabric_logout = NULL,
2086 .calc_req_entries = NULL,
2087 .build_iocbs = NULL,
2088 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2089 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2090 .read_nvram = qla24xx_read_nvram_data,
2091 .write_nvram = qla24xx_write_nvram_data,
2092 .fw_dump = NULL,
2093 .beacon_on = qla24xx_beacon_on,
2094 .beacon_off = qla24xx_beacon_off,
2095 .beacon_blink = NULL,
2096 .read_optrom = qla24xx_read_optrom_data,
2097 .write_optrom = qla24xx_write_optrom_data,
2098 .get_flash_version = qla24xx_get_flash_version,
2099 .start_scsi = qlafx00_start_scsi,
2100 .abort_isp = qlafx00_abort_isp,
2101 .iospace_config = qlafx00_iospace_config,
2102 .initialize_adapter = qlafx00_initialize_adapter,
6246b8a1
GM		 2103};
2104
f73cb695
CD		 2105static struct isp_operations qla27xx_isp_ops = {
2106 .pci_config = qla25xx_pci_config,
2107 .reset_chip = qla24xx_reset_chip,
2108 .chip_diag = qla24xx_chip_diag,
2109 .config_rings = qla24xx_config_rings,
2110 .reset_adapter = qla24xx_reset_adapter,
2111 .nvram_config = qla81xx_nvram_config,
2112 .update_fw_options = qla81xx_update_fw_options,
2113 .load_risc = qla81xx_load_risc,
2114 .pci_info_str = qla24xx_pci_info_str,
2115 .fw_version_str = qla24xx_fw_version_str,
2116 .intr_handler = qla24xx_intr_handler,
2117 .enable_intrs = qla24xx_enable_intrs,
2118 .disable_intrs = qla24xx_disable_intrs,
2119 .abort_command = qla24xx_abort_command,
2120 .target_reset = qla24xx_abort_target,
2121 .lun_reset = qla24xx_lun_reset,
2122 .fabric_login = qla24xx_login_fabric,
2123 .fabric_logout = qla24xx_fabric_logout,
2124 .calc_req_entries = NULL,
2125 .build_iocbs = NULL,
2126 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2127 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2128 .read_nvram = NULL,
2129 .write_nvram = NULL,
2130 .fw_dump = qla27xx_fwdump,
2131 .beacon_on = qla24xx_beacon_on,
2132 .beacon_off = qla24xx_beacon_off,
2133 .beacon_blink = qla83xx_beacon_blink,
2134 .read_optrom = qla25xx_read_optrom_data,
2135 .write_optrom = qla24xx_write_optrom_data,
2136 .get_flash_version = qla24xx_get_flash_version,
2137 .start_scsi = qla24xx_dif_start_scsi,
2138 .abort_isp = qla2x00_abort_isp,
2139 .iospace_config = qla83xx_iospace_config,
2140 .initialize_adapter = qla2x00_initialize_adapter,
2141};
2142
ea5b6382 2143static inline void
e315cd28 2144qla2x00_set_isp_flags(struct qla_hw_data *ha)
ea5b6382 2145{
2146 ha->device_type = DT_EXTENDED_IDS;
2147 switch (ha->pdev->device) {
2148 case PCI_DEVICE_ID_QLOGIC_ISP2100:
2149 ha->device_type |= DT_ISP2100;
2150 ha->device_type &= ~DT_EXTENDED_IDS;
441d1072 2151 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
ea5b6382 2152 break;
2153 case PCI_DEVICE_ID_QLOGIC_ISP2200:
2154 ha->device_type |= DT_ISP2200;
2155 ha->device_type &= ~DT_EXTENDED_IDS;
441d1072 2156 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
ea5b6382 2157 break;
2158 case PCI_DEVICE_ID_QLOGIC_ISP2300:
2159 ha->device_type |= DT_ISP2300;
4a59f71d 2160 ha->device_type |= DT_ZIO_SUPPORTED;
441d1072 2161 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 2162 break;
2163 case PCI_DEVICE_ID_QLOGIC_ISP2312:
2164 ha->device_type |= DT_ISP2312;
4a59f71d 2165 ha->device_type |= DT_ZIO_SUPPORTED;
441d1072 2166 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 2167 break;
2168 case PCI_DEVICE_ID_QLOGIC_ISP2322:
2169 ha->device_type |= DT_ISP2322;
4a59f71d 2170 ha->device_type |= DT_ZIO_SUPPORTED;
ea5b6382 2171 if (ha->pdev->subsystem_vendor == 0x1028 &&
2172 ha->pdev->subsystem_device == 0x0170)
2173 ha->device_type |= DT_OEM_001;
441d1072 2174 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 2175 break;
2176 case PCI_DEVICE_ID_QLOGIC_ISP6312:
2177 ha->device_type |= DT_ISP6312;
441d1072 2178 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 2179 break;
2180 case PCI_DEVICE_ID_QLOGIC_ISP6322:
2181 ha->device_type |= DT_ISP6322;
441d1072 2182 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 2183 break;
2184 case PCI_DEVICE_ID_QLOGIC_ISP2422:
2185 ha->device_type |= DT_ISP2422;
4a59f71d 2186 ha->device_type |= DT_ZIO_SUPPORTED;
e428924c 2187 ha->device_type |= DT_FWI2;
c76f2c01 2188 ha->device_type |= DT_IIDMA;
441d1072 2189 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2190 break;
2191 case PCI_DEVICE_ID_QLOGIC_ISP2432:
2192 ha->device_type |= DT_ISP2432;
4a59f71d 2193 ha->device_type |= DT_ZIO_SUPPORTED;
e428924c 2194 ha->device_type |= DT_FWI2;
c76f2c01 2195 ha->device_type |= DT_IIDMA;
441d1072 2196 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2197 break;
4d4df193
HK		 2198 case PCI_DEVICE_ID_QLOGIC_ISP8432:
2199 ha->device_type |= DT_ISP8432;
2200 ha->device_type |= DT_ZIO_SUPPORTED;
2201 ha->device_type |= DT_FWI2;
2202 ha->device_type |= DT_IIDMA;
2203 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2204 break;
044cc6c8 2205 case PCI_DEVICE_ID_QLOGIC_ISP5422:
2206 ha->device_type |= DT_ISP5422;
e428924c 2207 ha->device_type |= DT_FWI2;
441d1072 2208 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2209 break;
044cc6c8 2210 case PCI_DEVICE_ID_QLOGIC_ISP5432:
2211 ha->device_type |= DT_ISP5432;
e428924c 2212 ha->device_type |= DT_FWI2;
441d1072 2213 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2214 break;
c3a2f0df
AV		 2215 case PCI_DEVICE_ID_QLOGIC_ISP2532:
2216 ha->device_type |= DT_ISP2532;
2217 ha->device_type |= DT_ZIO_SUPPORTED;
2218 ha->device_type |= DT_FWI2;
2219 ha->device_type |= DT_IIDMA;
441d1072 2220 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2221 break;
3a03eb79
AV		 2222 case PCI_DEVICE_ID_QLOGIC_ISP8001:
2223 ha->device_type |= DT_ISP8001;
2224 ha->device_type |= DT_ZIO_SUPPORTED;
2225 ha->device_type |= DT_FWI2;
2226 ha->device_type |= DT_IIDMA;
2227 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2228 break;
a9083016
GM		 2229 case PCI_DEVICE_ID_QLOGIC_ISP8021:
2230 ha->device_type |= DT_ISP8021;
2231 ha->device_type |= DT_ZIO_SUPPORTED;
2232 ha->device_type |= DT_FWI2;
2233 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2234 /* Initialize 82XX ISP flags */
2235 qla82xx_init_flags(ha);
2236 break;
7ec0effd
AD		 2237 case PCI_DEVICE_ID_QLOGIC_ISP8044:
2238 ha->device_type |= DT_ISP8044;
2239 ha->device_type |= DT_ZIO_SUPPORTED;
2240 ha->device_type |= DT_FWI2;
2241 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2242 /* Initialize 82XX ISP flags */
2243 qla82xx_init_flags(ha);
2244 break;
6246b8a1
GM		 2245 case PCI_DEVICE_ID_QLOGIC_ISP2031:
2246 ha->device_type |= DT_ISP2031;
2247 ha->device_type |= DT_ZIO_SUPPORTED;
2248 ha->device_type |= DT_FWI2;
2249 ha->device_type |= DT_IIDMA;
2250 ha->device_type |= DT_T10_PI;
2251 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2252 break;
2253 case PCI_DEVICE_ID_QLOGIC_ISP8031:
2254 ha->device_type |= DT_ISP8031;
2255 ha->device_type |= DT_ZIO_SUPPORTED;
2256 ha->device_type |= DT_FWI2;
2257 ha->device_type |= DT_IIDMA;
2258 ha->device_type |= DT_T10_PI;
2259 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2260 break;
8ae6d9c7
GM		 2261 case PCI_DEVICE_ID_QLOGIC_ISPF001:
2262 ha->device_type |= DT_ISPFX00;
2263 break;
f73cb695
CD		 2264 case PCI_DEVICE_ID_QLOGIC_ISP2071:
2265 ha->device_type |= DT_ISP2071;
2266 ha->device_type |= DT_ZIO_SUPPORTED;
2267 ha->device_type |= DT_FWI2;
2268 ha->device_type |= DT_IIDMA;
2269 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2270 break;
ea5b6382 2271 }
e5b68a61 2272
a9083016
GM		 2273 if (IS_QLA82XX(ha))
2274 ha->port_no = !(ha->portnum & 1);
f73cb695 2275 else {
a9083016
GM		 2276 /* Get adapter physical port no from interrupt pin register. */
2277 pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no);
f73cb695
CD		 2278 if (IS_QLA27XX(ha))
2279 ha->port_no--;
2280 else
2281 ha->port_no = !(ha->port_no & 1);
2282 }
a9083016 2283
7c3df132 2284 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b,
d8424f68 2285 "device_type=0x%x port=%d fw_srisc_address=0x%x.\n",
f73cb695 2286 ha->device_type, ha->port_no, ha->fw_srisc_address);
ea5b6382 2287}
2288
1e99e33a
AV		 2289static void
2290qla2xxx_scan_start(struct Scsi_Host *shost)
2291{
e315cd28 2292 scsi_qla_host_t *vha = shost_priv(shost);
1e99e33a 2293
cbc8eb67
AV		 2294 if (vha->hw->flags.running_gold_fw)
2295 return;
2296
e315cd28
AC		 2297 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
2298 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
2299 set_bit(RSCN_UPDATE, &vha->dpc_flags);
2300 set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags);
1e99e33a
AV		 2301}
2302
2303static int
2304qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time)
2305{
e315cd28 2306 scsi_qla_host_t *vha = shost_priv(shost);
1e99e33a 2307
e315cd28 2308 if (!vha->host)
1e99e33a 2309 return 1;
e315cd28 2310 if (time > vha->hw->loop_reset_delay * HZ)
1e99e33a
AV		 2311 return 1;
2312
e315cd28 2313 return atomic_read(&vha->loop_state) == LOOP_READY;
1e99e33a
AV		 2314}
2315
1da177e4
LT		 2316/*
2317 * PCI driver interface
2318 */
6f039790 2319static int
7ee61397 2320qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
1da177e4 2321{
a1541d5a 2322 int ret = -ENODEV;
1da177e4 2323 struct Scsi_Host *host;
e315cd28
AC		 2324 scsi_qla_host_t *base_vha = NULL;
2325 struct qla_hw_data *ha;
29856e28 2326 char pci_info[30];
7d613ac6 2327 char fw_str[30], wq_name[30];
5433383e 2328 struct scsi_host_template *sht;
642ef983 2329 int bars, mem_only = 0;
e315cd28 2330 uint16_t req_length = 0, rsp_length = 0;
73208dfd
AC		 2331 struct req_que *req = NULL;
2332 struct rsp_que *rsp = NULL;
285d0321 2333 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO);
a5326f86 2334 sht = &qla2xxx_driver_template;
5433383e 2335 if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 ||
8bc69e7d 2336 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 ||
4d4df193 2337 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 ||
8bc69e7d 2338 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 ||
c3a2f0df 2339 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 ||
3a03eb79 2340 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 ||
a9083016 2341 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 ||
6246b8a1
GM		 2342 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021 ||
2343 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2031 ||
8ae6d9c7 2344 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8031 ||
7ec0effd 2345 pdev->device == PCI_DEVICE_ID_QLOGIC_ISPF001 ||
f73cb695
CD		 2346 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8044 ||
2347 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2071) {
285d0321 2348 bars = pci_select_bars(pdev, IORESOURCE_MEM);
09483916 2349 mem_only = 1;
7c3df132
SK		 2350 ql_dbg_pci(ql_dbg_init, pdev, 0x0007,
2351 "Mem only adapter.\n");
285d0321 2352 }
7c3df132
SK		 2353 ql_dbg_pci(ql_dbg_init, pdev, 0x0008,
2354 "Bars=%d.\n", bars);
285d0321 2355
09483916
BH		 2356 if (mem_only) {
2357 if (pci_enable_device_mem(pdev))
2358 goto probe_out;
2359 } else {
2360 if (pci_enable_device(pdev))
2361 goto probe_out;
2362 }
285d0321 2363
0927678f
JB		 2364 /* This may fail but that's ok */
2365 pci_enable_pcie_error_reporting(pdev);
285d0321 2366
e315cd28
AC		 2367 ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL);
2368 if (!ha) {
7c3df132
SK		 2369 ql_log_pci(ql_log_fatal, pdev, 0x0009,
2370 "Unable to allocate memory for ha.\n");
e315cd28 2371 goto probe_out;
1da177e4 2372 }
7c3df132
SK		 2373 ql_dbg_pci(ql_dbg_init, pdev, 0x000a,
2374 "Memory allocated for ha=%p.\n", ha);
e315cd28 2375 ha->pdev = pdev;
2d70c103 2376 ha->tgt.enable_class_2 = ql2xenableclass2;
1da177e4
LT		 2377
2378 /* Clear our data area */
285d0321 2379 ha->bars = bars;
09483916 2380 ha->mem_only = mem_only;
df4bf0bb 2381 spin_lock_init(&ha->hardware_lock);
339aa70e 2382 spin_lock_init(&ha->vport_slock);
a9b6f722 2383 mutex_init(&ha->selflogin_lock);
7a8ab9c8 2384 mutex_init(&ha->optrom_mutex);
1da177e4 2385
ea5b6382 2386 /* Set ISP-type information. */
2387 qla2x00_set_isp_flags(ha);
ca79cf66
DG		 2388
2389 /* Set EEH reset type to fundamental if required by hba */
95676112 2390 if (IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha) ||
f73cb695 2391 IS_QLA83XX(ha) || IS_QLA27XX(ha))
ca79cf66 2392 pdev->needs_freset = 1;
ca79cf66 2393
cba1e47f
CD		 2394 ha->prev_topology = 0;
2395 ha->init_cb_size = sizeof(init_cb_t);
2396 ha->link_data_rate = PORT_SPEED_UNKNOWN;
2397 ha->optrom_size = OPTROM_SIZE_2300;
2398
abbd8870 2399 /* Assign ISP specific operations. */
1da177e4 2400 if (IS_QLA2100(ha)) {
642ef983 2401 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
1da177e4 2402 ha->mbx_count = MAILBOX_REGISTER_COUNT_2100;
e315cd28
AC		 2403 req_length = REQUEST_ENTRY_CNT_2100;
2404 rsp_length = RESPONSE_ENTRY_CNT_2100;
2405 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
abbd8870 2406 ha->gid_list_info_size = 4;
3a03eb79
AV		 2407 ha->flash_conf_off = ~0;
2408 ha->flash_data_off = ~0;
2409 ha->nvram_conf_off = ~0;
2410 ha->nvram_data_off = ~0;
fd34f556 2411 ha->isp_ops = &qla2100_isp_ops;
1da177e4 2412 } else if (IS_QLA2200(ha)) {
642ef983 2413 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
67ddda35 2414 ha->mbx_count = MAILBOX_REGISTER_COUNT_2200;
e315cd28
AC		 2415 req_length = REQUEST_ENTRY_CNT_2200;
2416 rsp_length = RESPONSE_ENTRY_CNT_2100;
2417 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
abbd8870 2418 ha->gid_list_info_size = 4;
3a03eb79
AV		 2419 ha->flash_conf_off = ~0;
2420 ha->flash_data_off = ~0;
2421 ha->nvram_conf_off = ~0;
2422 ha->nvram_data_off = ~0;
fd34f556 2423 ha->isp_ops = &qla2100_isp_ops;
fca29703 2424 } else if (IS_QLA23XX(ha)) {
642ef983 2425 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
1da177e4 2426 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2427 req_length = REQUEST_ENTRY_CNT_2200;
2428 rsp_length = RESPONSE_ENTRY_CNT_2300;
2429 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
abbd8870 2430 ha->gid_list_info_size = 6;
854165f4 2431 if (IS_QLA2322(ha) || IS_QLA6322(ha))
2432 ha->optrom_size = OPTROM_SIZE_2322;
3a03eb79
AV		 2433 ha->flash_conf_off = ~0;
2434 ha->flash_data_off = ~0;
2435 ha->nvram_conf_off = ~0;
2436 ha->nvram_data_off = ~0;
fd34f556 2437 ha->isp_ops = &qla2300_isp_ops;
4d4df193 2438 } else if (IS_QLA24XX_TYPE(ha)) {
642ef983 2439 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
fca29703 2440 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2441 req_length = REQUEST_ENTRY_CNT_24XX;
2442 rsp_length = RESPONSE_ENTRY_CNT_2300;
2d70c103 2443 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
e315cd28 2444 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2c3dfe3f 2445 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
fca29703 2446 ha->gid_list_info_size = 8;
854165f4 2447 ha->optrom_size = OPTROM_SIZE_24XX;
73208dfd 2448 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX;
fd34f556 2449 ha->isp_ops = &qla24xx_isp_ops;
3a03eb79
AV		 2450 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2451 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2452 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2453 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
c3a2f0df 2454 } else if (IS_QLA25XX(ha)) {
642ef983 2455 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
c3a2f0df 2456 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2457 req_length = REQUEST_ENTRY_CNT_24XX;
2458 rsp_length = RESPONSE_ENTRY_CNT_2300;
2d70c103 2459 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
e315cd28 2460 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
c3a2f0df 2461 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
c3a2f0df
AV		 2462 ha->gid_list_info_size = 8;
2463 ha->optrom_size = OPTROM_SIZE_25XX;
73208dfd 2464 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
c3a2f0df 2465 ha->isp_ops = &qla25xx_isp_ops;
3a03eb79
AV		 2466 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2467 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2468 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2469 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
2470 } else if (IS_QLA81XX(ha)) {
642ef983 2471 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3a03eb79
AV		 2472 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2473 req_length = REQUEST_ENTRY_CNT_24XX;
2474 rsp_length = RESPONSE_ENTRY_CNT_2300;
aa230bc5 2475 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
3a03eb79
AV		 2476 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2477 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2478 ha->gid_list_info_size = 8;
2479 ha->optrom_size = OPTROM_SIZE_81XX;
40859ae5 2480 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3a03eb79
AV		 2481 ha->isp_ops = &qla81xx_isp_ops;
2482 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2483 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2484 ha->nvram_conf_off = ~0;
2485 ha->nvram_data_off = ~0;
a9083016 2486 } else if (IS_QLA82XX(ha)) {
642ef983 2487 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
a9083016
GM		 2488 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2489 req_length = REQUEST_ENTRY_CNT_82XX;
2490 rsp_length = RESPONSE_ENTRY_CNT_82XX;
2491 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2492 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2493 ha->gid_list_info_size = 8;
2494 ha->optrom_size = OPTROM_SIZE_82XX;
087c621e 2495 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
a9083016
GM		 2496 ha->isp_ops = &qla82xx_isp_ops;
2497 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2498 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2499 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2500 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
7ec0effd
AD		 2501 } else if (IS_QLA8044(ha)) {
2502 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2503 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2504 req_length = REQUEST_ENTRY_CNT_82XX;
2505 rsp_length = RESPONSE_ENTRY_CNT_82XX;
2506 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2507 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2508 ha->gid_list_info_size = 8;
2509 ha->optrom_size = OPTROM_SIZE_83XX;
2510 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2511 ha->isp_ops = &qla8044_isp_ops;
2512 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2513 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2514 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2515 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
6246b8a1 2516 } else if (IS_QLA83XX(ha)) {
7d613ac6 2517 ha->portnum = PCI_FUNC(ha->pdev->devfn);
642ef983 2518 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
6246b8a1
GM		 2519 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2520 req_length = REQUEST_ENTRY_CNT_24XX;
2521 rsp_length = RESPONSE_ENTRY_CNT_2300;
b8aa4bdf 2522 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
6246b8a1
GM		 2523 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2524 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2525 ha->gid_list_info_size = 8;
2526 ha->optrom_size = OPTROM_SIZE_83XX;
2527 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2528 ha->isp_ops = &qla83xx_isp_ops;
2529 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2530 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2531 ha->nvram_conf_off = ~0;
2532 ha->nvram_data_off = ~0;
8ae6d9c7
GM		 2533 } else if (IS_QLAFX00(ha)) {
2534 ha->max_fibre_devices = MAX_FIBRE_DEVICES_FX00;
2535 ha->mbx_count = MAILBOX_REGISTER_COUNT_FX00;
2536 ha->aen_mbx_count = AEN_MAILBOX_REGISTER_COUNT_FX00;
2537 req_length = REQUEST_ENTRY_CNT_FX00;
2538 rsp_length = RESPONSE_ENTRY_CNT_FX00;
8ae6d9c7
GM		 2539 ha->isp_ops = &qlafx00_isp_ops;
2540 ha->port_down_retry_count = 30; /* default value */
2541 ha->mr.fw_hbt_cnt = QLAFX00_HEARTBEAT_INTERVAL;
2542 ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL;
71e56003 2543 ha->mr.fw_critemp_timer_tick = QLAFX00_CRITEMP_INTERVAL;
8ae6d9c7 2544 ha->mr.fw_hbt_en = 1;
e8f5e95d
AB		 2545 ha->mr.host_info_resend = false;
2546 ha->mr.hinfo_resend_timer_tick = QLAFX00_HINFO_RESEND_INTERVAL;
f73cb695
CD		 2547 } else if (IS_QLA27XX(ha)) {
2548 ha->portnum = PCI_FUNC(ha->pdev->devfn);
2549 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2550 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2551 req_length = REQUEST_ENTRY_CNT_24XX;
2552 rsp_length = RESPONSE_ENTRY_CNT_2300;
2553 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2554 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2555 ha->gid_list_info_size = 8;
2556 ha->optrom_size = OPTROM_SIZE_83XX;
2557 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2558 ha->isp_ops = &qla27xx_isp_ops;
2559 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2560 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2561 ha->nvram_conf_off = ~0;
2562 ha->nvram_data_off = ~0;
1da177e4 2563 }
6246b8a1 2564
7c3df132
SK		 2565 ql_dbg_pci(ql_dbg_init, pdev, 0x001e,
2566 "mbx_count=%d, req_length=%d, "
2567 "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, "
642ef983
CD		 2568 "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, "
2569 "max_fibre_devices=%d.\n",
7c3df132
SK		 2570 ha->mbx_count, req_length, rsp_length, ha->max_loop_id,
2571 ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size,
642ef983 2572 ha->nvram_npiv_size, ha->max_fibre_devices);
7c3df132
SK		 2573 ql_dbg_pci(ql_dbg_init, pdev, 0x001f,
2574 "isp_ops=%p, flash_conf_off=%d, "
2575 "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n",
2576 ha->isp_ops, ha->flash_conf_off, ha->flash_data_off,
2577 ha->nvram_conf_off, ha->nvram_data_off);
706f457d
GM		 2578
2579 /* Configure PCI I/O space */
2580 ret = ha->isp_ops->iospace_config(ha);
2581 if (ret)
0a63ad12 2582 goto iospace_config_failed;
706f457d
GM		 2583
2584 ql_log_pci(ql_log_info, pdev, 0x001d,
2585 "Found an ISP%04X irq %d iobase 0x%p.\n",
2586 pdev->device, pdev->irq, ha->iobase);
6c2f527c 2587 mutex_init(&ha->vport_lock);
0b05a1f0
MB		 2588 init_completion(&ha->mbx_cmd_comp);
2589 complete(&ha->mbx_cmd_comp);
2590 init_completion(&ha->mbx_intr_comp);
23f2ebd1 2591 init_completion(&ha->dcbx_comp);
f356bef1 2592 init_completion(&ha->lb_portup_comp);
1da177e4 2593
2c3dfe3f 2594 set_bit(0, (unsigned long *) ha->vp_idx_map);
1da177e4 2595
53303c42 2596 qla2x00_config_dma_addressing(ha);
7c3df132
SK		 2597 ql_dbg_pci(ql_dbg_init, pdev, 0x0020,
2598 "64 Bit addressing is %s.\n",
2599 ha->flags.enable_64bit_addressing ? "enable" :
2600 "disable");
73208dfd 2601 ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp);
e315cd28 2602 if (!ret) {
7c3df132
SK		 2603 ql_log_pci(ql_log_fatal, pdev, 0x0031,
2604 "Failed to allocate memory for adapter, aborting.\n");
1da177e4 2605
e315cd28
AC		 2606 goto probe_hw_failed;
2607 }
2608
73208dfd 2609 req->max_q_depth = MAX_Q_DEPTH;
e315cd28 2610 if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU)
73208dfd
AC		 2611 req->max_q_depth = ql2xmaxqdepth;
2612
e315cd28
AC		 2613
2614 base_vha = qla2x00_create_host(sht, ha);
2615 if (!base_vha) {
a1541d5a 2616 ret = -ENOMEM;
6e9f21f3 2617 qla2x00_mem_free(ha);
2afa19a9
AC		 2618 qla2x00_free_req_que(ha, req);
2619 qla2x00_free_rsp_que(ha, rsp);
e315cd28 2620 goto probe_hw_failed;
1da177e4
LT		 2621 }
2622
e315cd28
AC		 2623 pci_set_drvdata(pdev, base_vha);
2624
e315cd28 2625 host = base_vha->host;
2afa19a9 2626 base_vha->req = req;
73208dfd 2627 if (IS_QLA2XXX_MIDTYPE(ha))
e315cd28 2628 base_vha->mgmt_svr_loop_id = 10 + base_vha->vp_idx;
73208dfd 2629 else
e315cd28
AC		 2630 base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER +
2631 base_vha->vp_idx;
58548cb5 2632
8ae6d9c7
GM		 2633 /* Setup fcport template structure. */
2634 ha->mr.fcport.vha = base_vha;
2635 ha->mr.fcport.port_type = FCT_UNKNOWN;
2636 ha->mr.fcport.loop_id = FC_NO_LOOP_ID;
2637 qla2x00_set_fcport_state(&ha->mr.fcport, FCS_UNCONFIGURED);
2638 ha->mr.fcport.supported_classes = FC_COS_UNSPECIFIED;
2639 ha->mr.fcport.scan_state = 1;
2640
58548cb5
GM		 2641 /* Set the SG table size based on ISP type */
2642 if (!IS_FWI2_CAPABLE(ha)) {
2643 if (IS_QLA2100(ha))
2644 host->sg_tablesize = 32;
2645 } else {
2646 if (!IS_QLA82XX(ha))
2647 host->sg_tablesize = QLA_SG_ALL;
2648 }
642ef983 2649 host->max_id = ha->max_fibre_devices;
e315cd28
AC		 2650 host->cmd_per_lun = 3;
2651 host->unique_id = host->host_no;
e02587d7 2652 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif)
0c470874
AE		 2653 host->max_cmd_len = 32;
2654 else
2655 host->max_cmd_len = MAX_CMDSZ;
e315cd28 2656 host->max_channel = MAX_BUSES - 1;
82515920 2657 host->max_lun = ql2xmaxlun;
e315cd28 2658 host->transportt = qla2xxx_transport_template;
9a069e19 2659 sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC);
e315cd28 2660
7c3df132
SK		 2661 ql_dbg(ql_dbg_init, base_vha, 0x0033,
2662 "max_id=%d this_id=%d "
2663 "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d "
d8424f68 2664 "max_lun=%d transportt=%p, vendor_id=%llu.\n", host->max_id,
7c3df132
SK		 2665 host->this_id, host->cmd_per_lun, host->unique_id,
2666 host->max_cmd_len, host->max_channel, host->max_lun,
2667 host->transportt, sht->vendor_id);
2668
9a347ff4
CD		 2669que_init:
2670 /* Alloc arrays of request and response ring ptrs */
2671 if (!qla2x00_alloc_queues(ha, req, rsp)) {
2672 ql_log(ql_log_fatal, base_vha, 0x003d,
2673 "Failed to allocate memory for queue pointers..."
2674 "aborting.\n");
2675 goto probe_init_failed;
2676 }
2677
2d70c103 2678 qlt_probe_one_stage1(base_vha, ha);
9a347ff4 2679
73208dfd
AC		 2680 /* Set up the irqs */
2681 ret = qla2x00_request_irqs(ha, rsp);
2682 if (ret)
6e9f21f3 2683 goto probe_init_failed;
90a86fc0
JC		 2684
2685 pci_save_state(pdev);
2686
9a347ff4 2687 /* Assign back pointers */
2afa19a9
AC		 2688 rsp->req = req;
2689 req->rsp = rsp;
9a347ff4 2690
8ae6d9c7
GM		 2691 if (IS_QLAFX00(ha)) {
2692 ha->rsp_q_map[0] = rsp;
2693 ha->req_q_map[0] = req;
2694 set_bit(0, ha->req_qid_map);
2695 set_bit(0, ha->rsp_qid_map);
2696 }
2697
08029990
AV		 2698 /* FWI2-capable only. */
2699 req->req_q_in = &ha->iobase->isp24.req_q_in;
2700 req->req_q_out = &ha->iobase->isp24.req_q_out;
2701 rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in;
2702 rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out;
f73cb695 2703 if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
08029990
AV		 2704 req->req_q_in = &ha->mqiobase->isp25mq.req_q_in;
2705 req->req_q_out = &ha->mqiobase->isp25mq.req_q_out;
2706 rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in;
2707 rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out;
17d98630
AC		 2708 }
2709
8ae6d9c7
GM		 2710 if (IS_QLAFX00(ha)) {
2711 req->req_q_in = &ha->iobase->ispfx00.req_q_in;
2712 req->req_q_out = &ha->iobase->ispfx00.req_q_out;
2713 rsp->rsp_q_in = &ha->iobase->ispfx00.rsp_q_in;
2714 rsp->rsp_q_out = &ha->iobase->ispfx00.rsp_q_out;
2715 }
2716
7ec0effd 2717 if (IS_P3P_TYPE(ha)) {
a9083016
GM		 2718 req->req_q_out = &ha->iobase->isp82.req_q_out[0];
2719 rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0];
2720 rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0];
2721 }
2722
7c3df132
SK		 2723 ql_dbg(ql_dbg_multiq, base_vha, 0xc009,
2724 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
2725 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
2726 ql_dbg(ql_dbg_multiq, base_vha, 0xc00a,
2727 "req->req_q_in=%p req->req_q_out=%p "
2728 "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
2729 req->req_q_in, req->req_q_out,
2730 rsp->rsp_q_in, rsp->rsp_q_out);
2731 ql_dbg(ql_dbg_init, base_vha, 0x003e,
2732 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
2733 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
2734 ql_dbg(ql_dbg_init, base_vha, 0x003f,
2735 "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
2736 req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out);
1da177e4 2737
8ae6d9c7 2738 if (ha->isp_ops->initialize_adapter(base_vha)) {
7c3df132
SK		 2739 ql_log(ql_log_fatal, base_vha, 0x00d6,
2740 "Failed to initialize adapter - Adapter flags %x.\n",
2741 base_vha->device_flags);
1da177e4 2742
a9083016
GM		 2743 if (IS_QLA82XX(ha)) {
2744 qla82xx_idc_lock(ha);
2745 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 2746 QLA8XXX_DEV_FAILED);
a9083016 2747 qla82xx_idc_unlock(ha);
7c3df132
SK		 2748 ql_log(ql_log_fatal, base_vha, 0x00d7,
2749 "HW State: FAILED.\n");
7ec0effd
AD		 2750 } else if (IS_QLA8044(ha)) {
2751 qla8044_idc_lock(ha);
2752 qla8044_wr_direct(base_vha,
2753 QLA8044_CRB_DEV_STATE_INDEX,
2754 QLA8XXX_DEV_FAILED);
2755 qla8044_idc_unlock(ha);
2756 ql_log(ql_log_fatal, base_vha, 0x0150,
2757 "HW State: FAILED.\n");
a9083016
GM		 2758 }
2759
a1541d5a 2760 ret = -ENODEV;
1da177e4
LT		 2761 goto probe_failed;
2762 }
2763
3b1bef64
CD		 2764 if (IS_QLAFX00(ha))
2765 host->can_queue = QLAFX00_MAX_CANQUEUE;
2766 else
2767 host->can_queue = req->num_outstanding_cmds - 10;
2768
2769 ql_dbg(ql_dbg_init, base_vha, 0x0032,
2770 "can_queue=%d, req=%p, mgmt_svr_loop_id=%d, sg_tablesize=%d.\n",
2771 host->can_queue, base_vha->req,
2772 base_vha->mgmt_svr_loop_id, host->sg_tablesize);
2773
7163ea81
AC		 2774 if (ha->mqenable) {
2775 if (qla25xx_setup_mode(base_vha)) {
7c3df132
SK		 2776 ql_log(ql_log_warn, base_vha, 0x00ec,
2777 "Failed to create queues, falling back to single queue mode.\n");
7163ea81
AC		 2778 goto que_init;
2779 }
2780 }
68ca949c 2781
cbc8eb67
AV		 2782 if (ha->flags.running_gold_fw)
2783 goto skip_dpc;
2784
1da177e4
LT		 2785 /*
2786 * Startup the kernel thread for this host adapter
2787 */
39a11240 2788 ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha,
7c3df132 2789 "%s_dpc", base_vha->host_str);
39a11240 2790 if (IS_ERR(ha->dpc_thread)) {
7c3df132
SK		 2791 ql_log(ql_log_fatal, base_vha, 0x00ed,
2792 "Failed to start DPC thread.\n");
39a11240 2793 ret = PTR_ERR(ha->dpc_thread);
1da177e4
LT		 2794 goto probe_failed;
2795 }
7c3df132
SK		 2796 ql_dbg(ql_dbg_init, base_vha, 0x00ee,
2797 "DPC thread started successfully.\n");
1da177e4 2798
2d70c103
NB		 2799 /*
2800 * If we're not coming up in initiator mode, we might sit for
2801 * a while without waking up the dpc thread, which leads to a
2802 * stuck process warning. So just kick the dpc once here and
2803 * let the kthread start (and go back to sleep in qla2x00_do_dpc).
2804 */
2805 qla2xxx_wake_dpc(base_vha);
2806
f3ddac19
CD		 2807 INIT_WORK(&ha->board_disable, qla2x00_disable_board_on_pci_error);
2808
81178772
SK		 2809 if (IS_QLA8031(ha) || IS_MCTP_CAPABLE(ha)) {
2810 sprintf(wq_name, "qla2xxx_%lu_dpc_lp_wq", base_vha->host_no);
2811 ha->dpc_lp_wq = create_singlethread_workqueue(wq_name);
2812 INIT_WORK(&ha->idc_aen, qla83xx_service_idc_aen);
2813
2814 sprintf(wq_name, "qla2xxx_%lu_dpc_hp_wq", base_vha->host_no);
2815 ha->dpc_hp_wq = create_singlethread_workqueue(wq_name);
2816 INIT_WORK(&ha->nic_core_reset, qla83xx_nic_core_reset_work);
2817 INIT_WORK(&ha->idc_state_handler,
2818 qla83xx_idc_state_handler_work);
2819 INIT_WORK(&ha->nic_core_unrecoverable,
2820 qla83xx_nic_core_unrecoverable_work);
2821 }
2822
cbc8eb67 2823skip_dpc:
e315cd28
AC		 2824 list_add_tail(&base_vha->list, &ha->vp_list);
2825 base_vha->host->irq = ha->pdev->irq;
1da177e4
LT		 2826
2827 /* Initialized the timer */
e315cd28 2828 qla2x00_start_timer(base_vha, qla2x00_timer, WATCH_INTERVAL);
7c3df132
SK		 2829 ql_dbg(ql_dbg_init, base_vha, 0x00ef,
2830 "Started qla2x00_timer with "
2831 "interval=%d.\n", WATCH_INTERVAL);
2832 ql_dbg(ql_dbg_init, base_vha, 0x00f0,
2833 "Detected hba at address=%p.\n",
2834 ha);
d19044c3 2835
e02587d7 2836 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) {
bad75002 2837 if (ha->fw_attributes & BIT_4) {
9e522cd8 2838 int prot = 0, guard;
bad75002 2839 base_vha->flags.difdix_supported = 1;
7c3df132
SK		 2840 ql_dbg(ql_dbg_init, base_vha, 0x00f1,
2841 "Registering for DIF/DIX type 1 and 3 protection.\n");
8cb2049c
AE		 2842 if (ql2xenabledif == 1)
2843 prot = SHOST_DIX_TYPE0_PROTECTION;
bad75002 2844 scsi_host_set_prot(host,
8cb2049c 2845 prot | SHOST_DIF_TYPE1_PROTECTION
0c470874 2846 | SHOST_DIF_TYPE2_PROTECTION
bad75002
AE		 2847 | SHOST_DIF_TYPE3_PROTECTION
2848 | SHOST_DIX_TYPE1_PROTECTION
0c470874 2849 | SHOST_DIX_TYPE2_PROTECTION
bad75002 2850 | SHOST_DIX_TYPE3_PROTECTION);
9e522cd8
AE		 2851
2852 guard = SHOST_DIX_GUARD_CRC;
2853
2854 if (IS_PI_IPGUARD_CAPABLE(ha) &&
2855 (ql2xenabledif > 1 || IS_PI_DIFB_DIX0_CAPABLE(ha)))
2856 guard |= SHOST_DIX_GUARD_IP;
2857
2858 scsi_host_set_guard(host, guard);
bad75002
AE		 2859 } else
2860 base_vha->flags.difdix_supported = 0;
2861 }
2862
a9083016
GM		 2863 ha->isp_ops->enable_intrs(ha);
2864
1fe19ee4
AB		 2865 if (IS_QLAFX00(ha)) {
2866 ret = qlafx00_fx_disc(base_vha,
2867 &base_vha->hw->mr.fcport, FXDISC_GET_CONFIG_INFO);
2868 host->sg_tablesize = (ha->mr.extended_io_enabled) ?
2869 QLA_SG_ALL : 128;
2870 }
2871
a1541d5a
AV		 2872 ret = scsi_add_host(host, &pdev->dev);
2873 if (ret)
2874 goto probe_failed;
2875
1486400f
MR		 2876 base_vha->flags.init_done = 1;
2877 base_vha->flags.online = 1;
2878
7c3df132
SK		 2879 ql_dbg(ql_dbg_init, base_vha, 0x00f2,
2880 "Init done and hba is online.\n");
2881
2d70c103
NB		 2882 if (qla_ini_mode_enabled(base_vha))
2883 scsi_scan_host(host);
2884 else
2885 ql_dbg(ql_dbg_init, base_vha, 0x0122,
2886 "skipping scsi_scan_host() for non-initiator port\n");
1e99e33a 2887
e315cd28 2888 qla2x00_alloc_sysfs_attr(base_vha);
a1541d5a 2889
8ae6d9c7 2890 if (IS_QLAFX00(ha)) {
8ae6d9c7
GM		 2891 ret = qlafx00_fx_disc(base_vha,
2892 &base_vha->hw->mr.fcport, FXDISC_GET_PORT_INFO);
2893
2894 /* Register system information */
2895 ret = qlafx00_fx_disc(base_vha,
2896 &base_vha->hw->mr.fcport, FXDISC_REG_HOST_INFO);
2897 }
2898
e315cd28 2899 qla2x00_init_host_attr(base_vha);
a1541d5a 2900
e315cd28 2901 qla2x00_dfs_setup(base_vha);
df613b96 2902
03eb912a
AB		 2903 ql_log(ql_log_info, base_vha, 0x00fb,
2904 "QLogic %s - %s.\n", ha->model_number, ha->model_desc);
7c3df132
SK		 2905 ql_log(ql_log_info, base_vha, 0x00fc,
2906 "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n",
2907 pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info),
2908 pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-',
2909 base_vha->host_no,
e315cd28 2910 ha->isp_ops->fw_version_str(base_vha, fw_str));
1da177e4 2911
2d70c103
NB		 2912 qlt_add_target(ha, base_vha);
2913
1da177e4
LT		 2914 return 0;
2915
6e9f21f3 2916probe_init_failed:
2afa19a9 2917 qla2x00_free_req_que(ha, req);
9a347ff4
CD		 2918 ha->req_q_map[0] = NULL;
2919 clear_bit(0, ha->req_qid_map);
2afa19a9 2920 qla2x00_free_rsp_que(ha, rsp);
9a347ff4
CD		 2921 ha->rsp_q_map[0] = NULL;
2922 clear_bit(0, ha->rsp_qid_map);
2afa19a9 2923 ha->max_req_queues = ha->max_rsp_queues = 0;
6e9f21f3 2924
1da177e4 2925probe_failed:
b9978769
AV		 2926 if (base_vha->timer_active)
2927 qla2x00_stop_timer(base_vha);
2928 base_vha->flags.online = 0;
2929 if (ha->dpc_thread) {
2930 struct task_struct *t = ha->dpc_thread;
2931
2932 ha->dpc_thread = NULL;
2933 kthread_stop(t);
2934 }
2935
e315cd28 2936 qla2x00_free_device(base_vha);
1da177e4 2937
e315cd28 2938 scsi_host_put(base_vha->host);
1da177e4 2939
e315cd28 2940probe_hw_failed:
a9083016
GM		 2941 if (IS_QLA82XX(ha)) {
2942 qla82xx_idc_lock(ha);
2943 qla82xx_clear_drv_active(ha);
2944 qla82xx_idc_unlock(ha);
0a63ad12 2945 }
7ec0effd
AD		 2946 if (IS_QLA8044(ha)) {
2947 qla8044_idc_lock(ha);
c41afc9a 2948 qla8044_clear_drv_active(ha);
7ec0effd
AD		 2949 qla8044_idc_unlock(ha);
2950 }
0a63ad12 2951iospace_config_failed:
7ec0effd 2952 if (IS_P3P_TYPE(ha)) {
0a63ad12 2953 if (!ha->nx_pcibase)
f73cb695 2954 iounmap((device_reg_t *)ha->nx_pcibase);
a9083016 2955 if (!ql2xdbwr)
f73cb695 2956 iounmap((device_reg_t *)ha->nxdb_wr_ptr);
a9083016
GM		 2957 } else {
2958 if (ha->iobase)
2959 iounmap(ha->iobase);
8ae6d9c7
GM		 2960 if (ha->cregbase)
2961 iounmap(ha->cregbase);
a9083016 2962 }
e315cd28
AC		 2963 pci_release_selected_regions(ha->pdev, ha->bars);
2964 kfree(ha);
2965 ha = NULL;
1da177e4 2966
a1541d5a 2967probe_out:
e315cd28 2968 pci_disable_device(pdev);
a1541d5a 2969 return ret;
1da177e4 2970}
1da177e4 2971
e30d1756
MI		 2972static void
2973qla2x00_shutdown(struct pci_dev *pdev)
2974{
2975 scsi_qla_host_t *vha;
2976 struct qla_hw_data *ha;
2977
552f3f9a
MI		 2978 if (!atomic_read(&pdev->enable_cnt))
2979 return;
2980
e30d1756
MI		 2981 vha = pci_get_drvdata(pdev);
2982 ha = vha->hw;
2983
42479343
AB		 2984 /* Notify ISPFX00 firmware */
2985 if (IS_QLAFX00(ha))
2986 qlafx00_driver_shutdown(vha, 20);
2987
e30d1756
MI		 2988 /* Turn-off FCE trace */
2989 if (ha->flags.fce_enabled) {
2990 qla2x00_disable_fce_trace(vha, NULL, NULL);
2991 ha->flags.fce_enabled = 0;
2992 }
2993
2994 /* Turn-off EFT trace */
2995 if (ha->eft)
2996 qla2x00_disable_eft_trace(vha);
2997
2998 /* Stop currently executing firmware. */
2999 qla2x00_try_to_stop_firmware(vha);
3000
3001 /* Turn adapter off line */
3002 vha->flags.online = 0;
3003
3004 /* turn-off interrupts on the card */
3005 if (ha->interrupts_on) {
3006 vha->flags.init_done = 0;
3007 ha->isp_ops->disable_intrs(ha);
3008 }
3009
3010 qla2x00_free_irqs(vha);
3011
3012 qla2x00_free_fw_dump(ha);
3013}
3014
fe1b806f 3015/* Deletes all the virtual ports for a given ha */
4c993f76 3016static void
fe1b806f 3017qla2x00_delete_all_vps(struct qla_hw_data *ha, scsi_qla_host_t *base_vha)
1da177e4 3018{
fe1b806f
CD		 3019 struct Scsi_Host *scsi_host;
3020 scsi_qla_host_t *vha;
feafb7b1 3021 unsigned long flags;
e315cd28 3022
43ebf16d
AE		 3023 mutex_lock(&ha->vport_lock);
3024 while (ha->cur_vport_count) {
43ebf16d 3025 spin_lock_irqsave(&ha->vport_slock, flags);
feafb7b1 3026
43ebf16d
AE		 3027 BUG_ON(base_vha->list.next == &ha->vp_list);
3028 /* This assumes first entry in ha->vp_list is always base vha */
3029 vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list);
fe1b806f 3030 scsi_host = scsi_host_get(vha->host);
feafb7b1 3031
43ebf16d
AE		 3032 spin_unlock_irqrestore(&ha->vport_slock, flags);
3033 mutex_unlock(&ha->vport_lock);
3034
3035 fc_vport_terminate(vha->fc_vport);
3036 scsi_host_put(vha->host);
feafb7b1 3037
43ebf16d 3038 mutex_lock(&ha->vport_lock);
e315cd28 3039 }
43ebf16d 3040 mutex_unlock(&ha->vport_lock);
fe1b806f 3041}
1da177e4 3042
fe1b806f
CD		 3043/* Stops all deferred work threads */
3044static void
3045qla2x00_destroy_deferred_work(struct qla_hw_data *ha)
3046{
68ca949c
AC		 3047 /* Flush the work queue and remove it */
3048 if (ha->wq) {
3049 flush_workqueue(ha->wq);
3050 destroy_workqueue(ha->wq);
3051 ha->wq = NULL;
3052 }
3053
7d613ac6
SV		 3054 /* Cancel all work and destroy DPC workqueues */
3055 if (ha->dpc_lp_wq) {
3056 cancel_work_sync(&ha->idc_aen);
3057 destroy_workqueue(ha->dpc_lp_wq);
3058 ha->dpc_lp_wq = NULL;
3059 }
3060
3061 if (ha->dpc_hp_wq) {
3062 cancel_work_sync(&ha->nic_core_reset);
3063 cancel_work_sync(&ha->idc_state_handler);
3064 cancel_work_sync(&ha->nic_core_unrecoverable);
3065 destroy_workqueue(ha->dpc_hp_wq);
3066 ha->dpc_hp_wq = NULL;
3067 }
3068
b9978769
AV		 3069 /* Kill the kernel thread for this host */
3070 if (ha->dpc_thread) {
3071 struct task_struct *t = ha->dpc_thread;
3072
3073 /*
3074 * qla2xxx_wake_dpc checks for ->dpc_thread
3075 * so we need to zero it out.
3076 */
3077 ha->dpc_thread = NULL;
3078 kthread_stop(t);
3079 }
fe1b806f 3080}
1da177e4 3081
fe1b806f
CD		 3082static void
3083qla2x00_unmap_iobases(struct qla_hw_data *ha)
3084{
a9083016 3085 if (IS_QLA82XX(ha)) {
b963752f 3086
f73cb695 3087 iounmap((device_reg_t *)ha->nx_pcibase);
a9083016 3088 if (!ql2xdbwr)
f73cb695 3089 iounmap((device_reg_t *)ha->nxdb_wr_ptr);
a9083016
GM		 3090 } else {
3091 if (ha->iobase)
3092 iounmap(ha->iobase);
1da177e4 3093
8ae6d9c7
GM		 3094 if (ha->cregbase)
3095 iounmap(ha->cregbase);
3096
a9083016
GM		 3097 if (ha->mqiobase)
3098 iounmap(ha->mqiobase);
6246b8a1 3099
f73cb695 3100 if ((IS_QLA83XX(ha) || IS_QLA27XX(ha)) && ha->msixbase)
6246b8a1 3101 iounmap(ha->msixbase);
a9083016 3102 }
fe1b806f
CD		 3103}
3104
3105static void
3106qla2x00_clear_drv_active(scsi_qla_host_t *vha)
3107{
3108 struct qla_hw_data *ha = vha->hw;
3109
3110 if (IS_QLA8044(ha)) {
3111 qla8044_idc_lock(ha);
c41afc9a 3112 qla8044_clear_drv_active(ha);
fe1b806f
CD		 3113 qla8044_idc_unlock(ha);
3114 } else if (IS_QLA82XX(ha)) {
3115 qla82xx_idc_lock(ha);
3116 qla82xx_clear_drv_active(ha);
3117 qla82xx_idc_unlock(ha);
3118 }
3119}
3120
3121static void
3122qla2x00_remove_one(struct pci_dev *pdev)
3123{
3124 scsi_qla_host_t *base_vha;
3125 struct qla_hw_data *ha;
3126
3127 /*
3128 * If the PCI device is disabled that means that probe failed and any
3129 * resources should be have cleaned up on probe exit.
3130 */
3131 if (!atomic_read(&pdev->enable_cnt))
3132 return;
3133
3134 base_vha = pci_get_drvdata(pdev);
3135 ha = base_vha->hw;
3136
3137 set_bit(UNLOADING, &base_vha->dpc_flags);
3138
3139 if (IS_QLAFX00(ha))
3140 qlafx00_driver_shutdown(base_vha, 20);
3141
3142 qla2x00_delete_all_vps(ha, base_vha);
3143
3144 if (IS_QLA8031(ha)) {
3145 ql_dbg(ql_dbg_p3p, base_vha, 0xb07e,
3146 "Clearing fcoe driver presence.\n");
3147 if (qla83xx_clear_drv_presence(base_vha) != QLA_SUCCESS)
3148 ql_dbg(ql_dbg_p3p, base_vha, 0xb079,
3149 "Error while clearing DRV-Presence.\n");
3150 }
3151
3152 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
3153
3154 qla2x00_dfs_remove(base_vha);
3155
3156 qla84xx_put_chip(base_vha);
3157
3158 /* Disable timer */
3159 if (base_vha->timer_active)
3160 qla2x00_stop_timer(base_vha);
3161
3162 base_vha->flags.online = 0;
3163
3164 qla2x00_destroy_deferred_work(ha);
3165
3166 qlt_remove_target(ha, base_vha);
3167
3168 qla2x00_free_sysfs_attr(base_vha, true);
3169
3170 fc_remove_host(base_vha->host);
3171
3172 scsi_remove_host(base_vha->host);
3173
3174 qla2x00_free_device(base_vha);
3175
3176 scsi_host_put(base_vha->host);
3177
3178 qla2x00_clear_drv_active(base_vha);
3179
3180 qla2x00_unmap_iobases(ha);
73208dfd 3181
e315cd28
AC		 3182 pci_release_selected_regions(ha->pdev, ha->bars);
3183 kfree(ha);
3184 ha = NULL;
1da177e4 3185
90a86fc0
JC		 3186 pci_disable_pcie_error_reporting(pdev);
3187
665db93b 3188 pci_disable_device(pdev);
1da177e4 3189}
1da177e4
LT		 3190
3191static void
e315cd28 3192qla2x00_free_device(scsi_qla_host_t *vha)
1da177e4 3193{
e315cd28 3194 struct qla_hw_data *ha = vha->hw;
1da177e4 3195
85880801
AV		 3196 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
3197
3198 /* Disable timer */
3199 if (vha->timer_active)
3200 qla2x00_stop_timer(vha);
3201
2afa19a9 3202 qla25xx_delete_queues(vha);
fe1b806f 3203
df613b96 3204 if (ha->flags.fce_enabled)
e315cd28 3205 qla2x00_disable_fce_trace(vha, NULL, NULL);
df613b96 3206
a7a167bf 3207 if (ha->eft)
e315cd28 3208 qla2x00_disable_eft_trace(vha);
a7a167bf 3209
f6ef3b18 3210 /* Stop currently executing firmware. */
e315cd28 3211 qla2x00_try_to_stop_firmware(vha);
1da177e4 3212
85880801
AV		 3213 vha->flags.online = 0;
3214
f6ef3b18 3215 /* turn-off interrupts on the card */
a9083016
GM		 3216 if (ha->interrupts_on) {
3217 vha->flags.init_done = 0;
fd34f556 3218 ha->isp_ops->disable_intrs(ha);
a9083016 3219 }
f6ef3b18 3220
e315cd28 3221 qla2x00_free_irqs(vha);
1da177e4 3222
8867048b
CD		 3223 qla2x00_free_fcports(vha);
3224
e315cd28 3225 qla2x00_mem_free(ha);
73208dfd 3226
08de2844
GM		 3227 qla82xx_md_free(vha);
3228
73208dfd 3229 qla2x00_free_queues(ha);
1da177e4
LT		 3230}
3231
8867048b
CD		 3232void qla2x00_free_fcports(struct scsi_qla_host *vha)
3233{
3234 fc_port_t *fcport, *tfcport;
3235
3236 list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list) {
3237 list_del(&fcport->list);
5f16b331 3238 qla2x00_clear_loop_id(fcport);
8867048b
CD		 3239 kfree(fcport);
3240 fcport = NULL;
3241 }
3242}
3243
d97994dc 3244static inline void
e315cd28 3245qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport,
d97994dc 3246 int defer)
3247{
d97994dc 3248 struct fc_rport *rport;
67becc00 3249 scsi_qla_host_t *base_vha;
044d78e1 3250 unsigned long flags;
d97994dc 3251
3252 if (!fcport->rport)
3253 return;
3254
3255 rport = fcport->rport;
3256 if (defer) {
67becc00 3257 base_vha = pci_get_drvdata(vha->hw->pdev);
044d78e1 3258 spin_lock_irqsave(vha->host->host_lock, flags);
d97994dc 3259 fcport->drport = rport;
044d78e1 3260 spin_unlock_irqrestore(vha->host->host_lock, flags);
67becc00
AV		 3261 set_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags);
3262 qla2xxx_wake_dpc(base_vha);
2d70c103 3263 } else {
d97994dc 3264 fc_remote_port_delete(rport);
2d70c103
NB		 3265 qlt_fc_port_deleted(vha, fcport);
3266 }
d97994dc 3267}
3268
1da177e4
LT		 3269/*
3270 * qla2x00_mark_device_lost Updates fcport state when device goes offline.
3271 *
3272 * Input: ha = adapter block pointer. fcport = port structure pointer.
3273 *
3274 * Return: None.
3275 *
3276 * Context:
3277 */
e315cd28 3278void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport,
d97994dc 3279 int do_login, int defer)
1da177e4 3280{
8ae6d9c7
GM		 3281 if (IS_QLAFX00(vha->hw)) {
3282 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
3283 qla2x00_schedule_rport_del(vha, fcport, defer);
3284 return;
3285 }
3286
2c3dfe3f 3287 if (atomic_read(&fcport->state) == FCS_ONLINE &&
c6d39e23 3288 vha->vp_idx == fcport->vha->vp_idx) {
ec426e10 3289 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
e315cd28
AC		 3290 qla2x00_schedule_rport_del(vha, fcport, defer);
3291 }
fa2a1ce5 3292 /*
1da177e4
LT		 3293 * We may need to retry the login, so don't change the state of the
3294 * port but do the retries.
3295 */
3296 if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD)
ec426e10 3297 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
1da177e4
LT		 3298
3299 if (!do_login)
3300 return;
3301
3302 if (fcport->login_retry == 0) {
e315cd28
AC		 3303 fcport->login_retry = vha->hw->login_retry_count;
3304 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
1da177e4 3305
7c3df132 3306 ql_dbg(ql_dbg_disc, vha, 0x2067,
7b833558
OK		 3307 "Port login retry %8phN, id = 0x%04x retry cnt=%d.\n",
3308 fcport->port_name, fcport->loop_id, fcport->login_retry);
1da177e4
LT		 3309 }
3310}
3311
3312/*
3313 * qla2x00_mark_all_devices_lost
3314 * Updates fcport state when device goes offline.
3315 *
3316 * Input:
3317 * ha = adapter block pointer.
3318 * fcport = port structure pointer.
3319 *
3320 * Return:
3321 * None.
3322 *
3323 * Context:
3324 */
3325void
e315cd28 3326qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha, int defer)
1da177e4
LT		 3327{
3328 fc_port_t *fcport;
3329
e315cd28 3330 list_for_each_entry(fcport, &vha->vp_fcports, list) {
c6d39e23 3331 if (vha->vp_idx != 0 && vha->vp_idx != fcport->vha->vp_idx)
1da177e4 3332 continue;
0d6e61bc 3333
1da177e4
LT		 3334 /*
3335 * No point in marking the device as lost, if the device is
3336 * already DEAD.
3337 */
3338 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD)
3339 continue;
e315cd28 3340 if (atomic_read(&fcport->state) == FCS_ONLINE) {
ec426e10 3341 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
0d6e61bc
AV		 3342 if (defer)
3343 qla2x00_schedule_rport_del(vha, fcport, defer);
c6d39e23 3344 else if (vha->vp_idx == fcport->vha->vp_idx)
0d6e61bc
AV		 3345 qla2x00_schedule_rport_del(vha, fcport, defer);
3346 }
1da177e4
LT		 3347 }
3348}
3349
3350/*
3351* qla2x00_mem_alloc
3352* Allocates adapter memory.
3353*
3354* Returns:
3355* 0 = success.
e8711085 3356* !0 = failure.
1da177e4 3357*/
e8711085 3358static int
73208dfd
AC		 3359qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len,
3360 struct req_que **req, struct rsp_que **rsp)
1da177e4
LT		 3361{
3362 char name[16];
1da177e4 3363
e8711085 3364 ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size,
e315cd28 3365 &ha->init_cb_dma, GFP_KERNEL);
e8711085 3366 if (!ha->init_cb)
e315cd28 3367 goto fail;
e8711085 3368
2d70c103
NB		 3369 if (qlt_mem_alloc(ha) < 0)
3370 goto fail_free_init_cb;
3371
642ef983
CD		 3372 ha->gid_list = dma_alloc_coherent(&ha->pdev->dev,
3373 qla2x00_gid_list_size(ha), &ha->gid_list_dma, GFP_KERNEL);
e315cd28 3374 if (!ha->gid_list)
2d70c103 3375 goto fail_free_tgt_mem;
1da177e4 3376
e8711085
AV		 3377 ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep);
3378 if (!ha->srb_mempool)
e315cd28 3379 goto fail_free_gid_list;
e8711085 3380
7ec0effd 3381 if (IS_P3P_TYPE(ha)) {
a9083016
GM		 3382 /* Allocate cache for CT6 Ctx. */
3383 if (!ctx_cachep) {
3384 ctx_cachep = kmem_cache_create("qla2xxx_ctx",
3385 sizeof(struct ct6_dsd), 0,
3386 SLAB_HWCACHE_ALIGN, NULL);
3387 if (!ctx_cachep)
3388 goto fail_free_gid_list;
3389 }
3390 ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ,
3391 ctx_cachep);
3392 if (!ha->ctx_mempool)
3393 goto fail_free_srb_mempool;
7c3df132
SK		 3394 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021,
3395 "ctx_cachep=%p ctx_mempool=%p.\n",
3396 ctx_cachep, ha->ctx_mempool);
a9083016
GM		 3397 }
3398
e8711085
AV		 3399 /* Get memory for cached NVRAM */
3400 ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL);
3401 if (!ha->nvram)
a9083016 3402 goto fail_free_ctx_mempool;
e8711085 3403
e315cd28
AC		 3404 snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME,
3405 ha->pdev->device);
3406 ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3407 DMA_POOL_SIZE, 8, 0);
3408 if (!ha->s_dma_pool)
3409 goto fail_free_nvram;
3410
7c3df132
SK		 3411 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022,
3412 "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n",
3413 ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool);
3414
7ec0effd 3415 if (IS_P3P_TYPE(ha) || ql2xenabledif) {
a9083016
GM		 3416 ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3417 DSD_LIST_DMA_POOL_SIZE, 8, 0);
3418 if (!ha->dl_dma_pool) {
7c3df132
SK		 3419 ql_log_pci(ql_log_fatal, ha->pdev, 0x0023,
3420 "Failed to allocate memory for dl_dma_pool.\n");
a9083016
GM		 3421 goto fail_s_dma_pool;
3422 }
3423
3424 ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3425 FCP_CMND_DMA_POOL_SIZE, 8, 0);
3426 if (!ha->fcp_cmnd_dma_pool) {
7c3df132
SK		 3427 ql_log_pci(ql_log_fatal, ha->pdev, 0x0024,
3428 "Failed to allocate memory for fcp_cmnd_dma_pool.\n");
a9083016
GM		 3429 goto fail_dl_dma_pool;
3430 }
7c3df132
SK		 3431 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025,
3432 "dl_dma_pool=%p fcp_cmnd_dma_pool=%p.\n",
3433 ha->dl_dma_pool, ha->fcp_cmnd_dma_pool);
a9083016
GM		 3434 }
3435
e8711085
AV		 3436 /* Allocate memory for SNS commands */
3437 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
e315cd28 3438 /* Get consistent memory allocated for SNS commands */
e8711085 3439 ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev,
e315cd28 3440 sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL);
e8711085 3441 if (!ha->sns_cmd)
e315cd28 3442 goto fail_dma_pool;
7c3df132 3443 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026,
d8424f68 3444 "sns_cmd: %p.\n", ha->sns_cmd);
e8711085 3445 } else {
e315cd28 3446 /* Get consistent memory allocated for MS IOCB */
e8711085 3447 ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
e315cd28 3448 &ha->ms_iocb_dma);
e8711085 3449 if (!ha->ms_iocb)
e315cd28
AC		 3450 goto fail_dma_pool;
3451 /* Get consistent memory allocated for CT SNS commands */
e8711085 3452 ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev,
e315cd28 3453 sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL);
e8711085
AV		 3454 if (!ha->ct_sns)
3455 goto fail_free_ms_iocb;
7c3df132
SK		 3456 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027,
3457 "ms_iocb=%p ct_sns=%p.\n",
3458 ha->ms_iocb, ha->ct_sns);
1da177e4
LT		 3459 }
3460
e315cd28 3461 /* Allocate memory for request ring */
73208dfd
AC		 3462 *req = kzalloc(sizeof(struct req_que), GFP_KERNEL);
3463 if (!*req) {
7c3df132
SK		 3464 ql_log_pci(ql_log_fatal, ha->pdev, 0x0028,
3465 "Failed to allocate memory for req.\n");
e315cd28
AC		 3466 goto fail_req;
3467 }
73208dfd
AC		 3468 (*req)->length = req_len;
3469 (*req)->ring = dma_alloc_coherent(&ha->pdev->dev,
3470 ((*req)->length + 1) * sizeof(request_t),
3471 &(*req)->dma, GFP_KERNEL);
3472 if (!(*req)->ring) {
7c3df132
SK		 3473 ql_log_pci(ql_log_fatal, ha->pdev, 0x0029,
3474 "Failed to allocate memory for req_ring.\n");
e315cd28
AC		 3475 goto fail_req_ring;
3476 }
3477 /* Allocate memory for response ring */
73208dfd
AC		 3478 *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL);
3479 if (!*rsp) {
7c3df132
SK		 3480 ql_log_pci(ql_log_fatal, ha->pdev, 0x002a,
3481 "Failed to allocate memory for rsp.\n");
e315cd28
AC		 3482 goto fail_rsp;
3483 }
73208dfd
AC		 3484 (*rsp)->hw = ha;
3485 (*rsp)->length = rsp_len;
3486 (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev,
3487 ((*rsp)->length + 1) * sizeof(response_t),
3488 &(*rsp)->dma, GFP_KERNEL);
3489 if (!(*rsp)->ring) {
7c3df132
SK		 3490 ql_log_pci(ql_log_fatal, ha->pdev, 0x002b,
3491 "Failed to allocate memory for rsp_ring.\n");
e315cd28
AC		 3492 goto fail_rsp_ring;
3493 }
73208dfd
AC		 3494 (*req)->rsp = *rsp;
3495 (*rsp)->req = *req;
7c3df132
SK		 3496 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c,
3497 "req=%p req->length=%d req->ring=%p rsp=%p "
3498 "rsp->length=%d rsp->ring=%p.\n",
3499 *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length,
3500 (*rsp)->ring);
73208dfd
AC		 3501 /* Allocate memory for NVRAM data for vports */
3502 if (ha->nvram_npiv_size) {
3503 ha->npiv_info = kzalloc(sizeof(struct qla_npiv_entry) *
7c3df132 3504 ha->nvram_npiv_size, GFP_KERNEL);
73208dfd 3505 if (!ha->npiv_info) {
7c3df132
SK		 3506 ql_log_pci(ql_log_fatal, ha->pdev, 0x002d,
3507 "Failed to allocate memory for npiv_info.\n");
73208dfd
AC		 3508 goto fail_npiv_info;
3509 }
3510 } else
3511 ha->npiv_info = NULL;
e8711085 3512
b64b0e8f 3513 /* Get consistent memory allocated for EX-INIT-CB. */
f73cb695 3514 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha)) {
b64b0e8f
AV		 3515 ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
3516 &ha->ex_init_cb_dma);
3517 if (!ha->ex_init_cb)
3518 goto fail_ex_init_cb;
7c3df132
SK		 3519 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e,
3520 "ex_init_cb=%p.\n", ha->ex_init_cb);
b64b0e8f
AV		 3521 }
3522
a9083016
GM		 3523 INIT_LIST_HEAD(&ha->gbl_dsd_list);
3524
5ff1d584
AV		 3525 /* Get consistent memory allocated for Async Port-Database. */
3526 if (!IS_FWI2_CAPABLE(ha)) {
3527 ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
3528 &ha->async_pd_dma);
3529 if (!ha->async_pd)
3530 goto fail_async_pd;
7c3df132
SK		 3531 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f,
3532 "async_pd=%p.\n", ha->async_pd);
5ff1d584
AV		 3533 }
3534
e315cd28 3535 INIT_LIST_HEAD(&ha->vp_list);
5f16b331
CD		 3536
3537 /* Allocate memory for our loop_id bitmap */
3538 ha->loop_id_map = kzalloc(BITS_TO_LONGS(LOOPID_MAP_SIZE) * sizeof(long),
3539 GFP_KERNEL);
3540 if (!ha->loop_id_map)
3541 goto fail_async_pd;
3542 else {
3543 qla2x00_set_reserved_loop_ids(ha);
3544 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0123,
3545 "loop_id_map=%p. \n", ha->loop_id_map);
3546 }
3547
e315cd28
AC		 3548 return 1;
3549
5ff1d584
AV		 3550fail_async_pd:
3551 dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma);
b64b0e8f
AV		 3552fail_ex_init_cb:
3553 kfree(ha->npiv_info);
73208dfd
AC		 3554fail_npiv_info:
3555 dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) *
3556 sizeof(response_t), (*rsp)->ring, (*rsp)->dma);
3557 (*rsp)->ring = NULL;
3558 (*rsp)->dma = 0;
e315cd28 3559fail_rsp_ring:
73208dfd 3560 kfree(*rsp);
e315cd28 3561fail_rsp:
73208dfd
AC		 3562 dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) *
3563 sizeof(request_t), (*req)->ring, (*req)->dma);
3564 (*req)->ring = NULL;
3565 (*req)->dma = 0;
e315cd28 3566fail_req_ring:
73208dfd 3567 kfree(*req);
e315cd28
AC		 3568fail_req:
3569 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
3570 ha->ct_sns, ha->ct_sns_dma);
3571 ha->ct_sns = NULL;
3572 ha->ct_sns_dma = 0;
e8711085
AV		 3573fail_free_ms_iocb:
3574 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
3575 ha->ms_iocb = NULL;
3576 ha->ms_iocb_dma = 0;
e315cd28 3577fail_dma_pool:
bad75002 3578 if (IS_QLA82XX(ha) || ql2xenabledif) {
a9083016
GM		 3579 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
3580 ha->fcp_cmnd_dma_pool = NULL;
3581 }
3582fail_dl_dma_pool:
bad75002 3583 if (IS_QLA82XX(ha) || ql2xenabledif) {
a9083016
GM		 3584 dma_pool_destroy(ha->dl_dma_pool);
3585 ha->dl_dma_pool = NULL;
3586 }
3587fail_s_dma_pool:
e315cd28
AC		 3588 dma_pool_destroy(ha->s_dma_pool);
3589 ha->s_dma_pool = NULL;
e8711085
AV		 3590fail_free_nvram:
3591 kfree(ha->nvram);
3592 ha->nvram = NULL;
a9083016
GM		 3593fail_free_ctx_mempool:
3594 mempool_destroy(ha->ctx_mempool);
3595 ha->ctx_mempool = NULL;
e8711085
AV		 3596fail_free_srb_mempool:
3597 mempool_destroy(ha->srb_mempool);
3598 ha->srb_mempool = NULL;
e8711085 3599fail_free_gid_list:
642ef983
CD		 3600 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
3601 ha->gid_list,
e315cd28 3602 ha->gid_list_dma);
e8711085
AV		 3603 ha->gid_list = NULL;
3604 ha->gid_list_dma = 0;
2d70c103
NB		 3605fail_free_tgt_mem:
3606 qlt_mem_free(ha);
e315cd28
AC		 3607fail_free_init_cb:
3608 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb,
3609 ha->init_cb_dma);
3610 ha->init_cb = NULL;
3611 ha->init_cb_dma = 0;
e8711085 3612fail:
7c3df132
SK		 3613 ql_log(ql_log_fatal, NULL, 0x0030,
3614 "Memory allocation failure.\n");
e8711085 3615 return -ENOMEM;
1da177e4
LT		 3616}
3617
3618/*
e30d1756
MI		 3619* qla2x00_free_fw_dump
3620* Frees fw dump stuff.
1da177e4
LT		 3621*
3622* Input:
7ec0effd 3623* ha = adapter block pointer
1da177e4 3624*/
a824ebb3 3625static void
e30d1756 3626qla2x00_free_fw_dump(struct qla_hw_data *ha)
1da177e4 3627{
df613b96 3628 if (ha->fce)
f73cb695
CD		 3629 dma_free_coherent(&ha->pdev->dev,
3630 FCE_SIZE, ha->fce, ha->fce_dma);
df613b96 3631
f73cb695
CD		 3632 if (ha->eft)
3633 dma_free_coherent(&ha->pdev->dev,
3634 EFT_SIZE, ha->eft, ha->eft_dma);
3635
3636 if (ha->fw_dump)
a7a167bf 3637 vfree(ha->fw_dump);
f73cb695
CD		 3638 if (ha->fw_dump_template)
3639 vfree(ha->fw_dump_template);
3640
e30d1756
MI		 3641 ha->fce = NULL;
3642 ha->fce_dma = 0;
3643 ha->eft = NULL;
3644 ha->eft_dma = 0;
e30d1756
MI		 3645 ha->fw_dumped = 0;
3646 ha->fw_dump_reading = 0;
f73cb695
CD		 3647 ha->fw_dump = NULL;
3648 ha->fw_dump_len = 0;
3649 ha->fw_dump_template = NULL;
3650 ha->fw_dump_template_len = 0;
e30d1756
MI		 3651}
3652
3653/*
3654* qla2x00_mem_free
3655* Frees all adapter allocated memory.
3656*
3657* Input:
3658* ha = adapter block pointer.
3659*/
3660static void
3661qla2x00_mem_free(struct qla_hw_data *ha)
3662{
3663 qla2x00_free_fw_dump(ha);
3664
81178772
SK		 3665 if (ha->mctp_dump)
3666 dma_free_coherent(&ha->pdev->dev, MCTP_DUMP_SIZE, ha->mctp_dump,
3667 ha->mctp_dump_dma);
3668
e30d1756
MI		 3669 if (ha->srb_mempool)
3670 mempool_destroy(ha->srb_mempool);
a7a167bf 3671
11bbc1d8
AV		 3672 if (ha->dcbx_tlv)
3673 dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE,
3674 ha->dcbx_tlv, ha->dcbx_tlv_dma);
3675
ce0423f4
AV		 3676 if (ha->xgmac_data)
3677 dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE,
3678 ha->xgmac_data, ha->xgmac_data_dma);
3679
1da177e4
LT		 3680 if (ha->sns_cmd)
3681 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
e315cd28 3682 ha->sns_cmd, ha->sns_cmd_dma);
1da177e4
LT		 3683
3684 if (ha->ct_sns)
3685 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
e315cd28 3686 ha->ct_sns, ha->ct_sns_dma);
1da177e4 3687
88729e53
AV		 3688 if (ha->sfp_data)
3689 dma_pool_free(ha->s_dma_pool, ha->sfp_data, ha->sfp_data_dma);
3690
1da177e4
LT		 3691 if (ha->ms_iocb)
3692 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
3693
b64b0e8f 3694 if (ha->ex_init_cb)
a9083016
GM		 3695 dma_pool_free(ha->s_dma_pool,
3696 ha->ex_init_cb, ha->ex_init_cb_dma);
b64b0e8f 3697
5ff1d584
AV		 3698 if (ha->async_pd)
3699 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
3700
1da177e4
LT		 3701 if (ha->s_dma_pool)
3702 dma_pool_destroy(ha->s_dma_pool);
3703
1da177e4 3704 if (ha->gid_list)
642ef983
CD		 3705 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
3706 ha->gid_list, ha->gid_list_dma);
1da177e4 3707
a9083016
GM		 3708 if (IS_QLA82XX(ha)) {
3709 if (!list_empty(&ha->gbl_dsd_list)) {
3710 struct dsd_dma *dsd_ptr, *tdsd_ptr;
3711
3712 /* clean up allocated prev pool */
3713 list_for_each_entry_safe(dsd_ptr,
3714 tdsd_ptr, &ha->gbl_dsd_list, list) {
3715 dma_pool_free(ha->dl_dma_pool,
3716 dsd_ptr->dsd_addr, dsd_ptr->dsd_list_dma);
3717 list_del(&dsd_ptr->list);
3718 kfree(dsd_ptr);
3719 }
3720 }
3721 }
3722
3723 if (ha->dl_dma_pool)
3724 dma_pool_destroy(ha->dl_dma_pool);
3725
3726 if (ha->fcp_cmnd_dma_pool)
3727 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
3728
3729 if (ha->ctx_mempool)
3730 mempool_destroy(ha->ctx_mempool);
3731
2d70c103
NB		 3732 qlt_mem_free(ha);
3733
e315cd28
AC		 3734 if (ha->init_cb)
3735 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size,
a9083016 3736 ha->init_cb, ha->init_cb_dma);
e315cd28
AC		 3737 vfree(ha->optrom_buffer);
3738 kfree(ha->nvram);
73208dfd 3739 kfree(ha->npiv_info);
7a67735b 3740 kfree(ha->swl);
5f16b331 3741 kfree(ha->loop_id_map);
1da177e4 3742
e8711085 3743 ha->srb_mempool = NULL;
a9083016 3744 ha->ctx_mempool = NULL;
1da177e4
LT		 3745 ha->sns_cmd = NULL;
3746 ha->sns_cmd_dma = 0;
3747 ha->ct_sns = NULL;
3748 ha->ct_sns_dma = 0;
3749 ha->ms_iocb = NULL;
3750 ha->ms_iocb_dma = 0;
1da177e4
LT		 3751 ha->init_cb = NULL;
3752 ha->init_cb_dma = 0;
b64b0e8f
AV		 3753 ha->ex_init_cb = NULL;
3754 ha->ex_init_cb_dma = 0;
5ff1d584
AV		 3755 ha->async_pd = NULL;
3756 ha->async_pd_dma = 0;
1da177e4
LT		 3757
3758 ha->s_dma_pool = NULL;
a9083016
GM		 3759 ha->dl_dma_pool = NULL;
3760 ha->fcp_cmnd_dma_pool = NULL;
1da177e4 3761
1da177e4
LT		 3762 ha->gid_list = NULL;
3763 ha->gid_list_dma = 0;
2d70c103
NB		 3764
3765 ha->tgt.atio_ring = NULL;
3766 ha->tgt.atio_dma = 0;
3767 ha->tgt.tgt_vp_map = NULL;
e315cd28 3768}
1da177e4 3769
e315cd28
AC		 3770struct scsi_qla_host *qla2x00_create_host(struct scsi_host_template *sht,
3771 struct qla_hw_data *ha)
3772{
3773 struct Scsi_Host *host;
3774 struct scsi_qla_host *vha = NULL;
854165f4 3775
e315cd28
AC		 3776 host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t));
3777 if (host == NULL) {
7c3df132
SK		 3778 ql_log_pci(ql_log_fatal, ha->pdev, 0x0107,
3779 "Failed to allocate host from the scsi layer, aborting.\n");
e315cd28
AC		 3780 goto fail;
3781 }
3782
3783 /* Clear our data area */
3784 vha = shost_priv(host);
3785 memset(vha, 0, sizeof(scsi_qla_host_t));
3786
3787 vha->host = host;
3788 vha->host_no = host->host_no;
3789 vha->hw = ha;
3790
3791 INIT_LIST_HEAD(&vha->vp_fcports);
3792 INIT_LIST_HEAD(&vha->work_list);
3793 INIT_LIST_HEAD(&vha->list);
3794
f999f4c1
AV		 3795 spin_lock_init(&vha->work_lock);
3796
e315cd28 3797 sprintf(vha->host_str, "%s_%ld", QLA2XXX_DRIVER_NAME, vha->host_no);
7c3df132
SK		 3798 ql_dbg(ql_dbg_init, vha, 0x0041,
3799 "Allocated the host=%p hw=%p vha=%p dev_name=%s",
3800 vha->host, vha->hw, vha,
3801 dev_name(&(ha->pdev->dev)));
3802
e315cd28
AC		 3803 return vha;
3804
3805fail:
3806 return vha;
1da177e4
LT		 3807}
3808
01ef66bb 3809static struct qla_work_evt *
f999f4c1 3810qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type)
0971de7f
AV		 3811{
3812 struct qla_work_evt *e;
feafb7b1
AE		 3813 uint8_t bail;
3814
3815 QLA_VHA_MARK_BUSY(vha, bail);
3816 if (bail)
3817 return NULL;
0971de7f 3818
f999f4c1 3819 e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC);
feafb7b1
AE		 3820 if (!e) {
3821 QLA_VHA_MARK_NOT_BUSY(vha);
0971de7f 3822 return NULL;
feafb7b1 3823 }
0971de7f
AV		 3824
3825 INIT_LIST_HEAD(&e->list);
3826 e->type = type;
3827 e->flags = QLA_EVT_FLAG_FREE;
3828 return e;
3829}
3830
01ef66bb 3831static int
f999f4c1 3832qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e)
0971de7f 3833{
f999f4c1 3834 unsigned long flags;
0971de7f 3835
f999f4c1 3836 spin_lock_irqsave(&vha->work_lock, flags);
e315cd28 3837 list_add_tail(&e->list, &vha->work_list);
f999f4c1 3838 spin_unlock_irqrestore(&vha->work_lock, flags);
e315cd28 3839 qla2xxx_wake_dpc(vha);
f999f4c1 3840
0971de7f
AV		 3841 return QLA_SUCCESS;
3842}
3843
3844int
e315cd28 3845qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code,
0971de7f
AV		 3846 u32 data)
3847{
3848 struct qla_work_evt *e;
3849
f999f4c1 3850 e = qla2x00_alloc_work(vha, QLA_EVT_AEN);
0971de7f
AV		 3851 if (!e)
3852 return QLA_FUNCTION_FAILED;
3853
3854 e->u.aen.code = code;
3855 e->u.aen.data = data;
f999f4c1 3856 return qla2x00_post_work(vha, e);
0971de7f
AV		 3857}
3858
8a659571
AV		 3859int
3860qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb)
3861{
3862 struct qla_work_evt *e;
3863
f999f4c1 3864 e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK);
8a659571
AV		 3865 if (!e)
3866 return QLA_FUNCTION_FAILED;
3867
3868 memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t));
f999f4c1 3869 return qla2x00_post_work(vha, e);
8a659571
AV		 3870}
3871
ac280b67
AV		 3872#define qla2x00_post_async_work(name, type) \
3873int qla2x00_post_async_##name##_work( \
3874 struct scsi_qla_host *vha, \
3875 fc_port_t *fcport, uint16_t *data) \
3876{ \
3877 struct qla_work_evt *e; \
3878 \
3879 e = qla2x00_alloc_work(vha, type); \
3880 if (!e) \
3881 return QLA_FUNCTION_FAILED; \
3882 \
3883 e->u.logio.fcport = fcport; \
3884 if (data) { \
3885 e->u.logio.data[0] = data[0]; \
3886 e->u.logio.data[1] = data[1]; \
3887 } \
3888 return qla2x00_post_work(vha, e); \
3889}
3890
3891qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN);
3892qla2x00_post_async_work(login_done, QLA_EVT_ASYNC_LOGIN_DONE);
3893qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT);
3894qla2x00_post_async_work(logout_done, QLA_EVT_ASYNC_LOGOUT_DONE);
5ff1d584
AV		 3895qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC);
3896qla2x00_post_async_work(adisc_done, QLA_EVT_ASYNC_ADISC_DONE);
ac280b67 3897
3420d36c
AV		 3898int
3899qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code)
3900{
3901 struct qla_work_evt *e;
3902
3903 e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT);
3904 if (!e)
3905 return QLA_FUNCTION_FAILED;
3906
3907 e->u.uevent.code = code;
3908 return qla2x00_post_work(vha, e);
3909}
3910
3911static void
3912qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code)
3913{
3914 char event_string[40];
3915 char *envp[] = { event_string, NULL };
3916
3917 switch (code) {
3918 case QLA_UEVENT_CODE_FW_DUMP:
3919 snprintf(event_string, sizeof(event_string), "FW_DUMP=%ld",
3920 vha->host_no);
3921 break;
3922 default:
3923 /* do nothing */
3924 break;
3925 }
3926 kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp);
3927}
3928
8ae6d9c7
GM		 3929int
3930qlafx00_post_aenfx_work(struct scsi_qla_host *vha, uint32_t evtcode,
3931 uint32_t *data, int cnt)
3932{
3933 struct qla_work_evt *e;
3934
3935 e = qla2x00_alloc_work(vha, QLA_EVT_AENFX);
3936 if (!e)
3937 return QLA_FUNCTION_FAILED;
3938
3939 e->u.aenfx.evtcode = evtcode;
3940 e->u.aenfx.count = cnt;
3941 memcpy(e->u.aenfx.mbx, data, sizeof(*data) * cnt);
3942 return qla2x00_post_work(vha, e);
3943}
3944
ac280b67 3945void
e315cd28 3946qla2x00_do_work(struct scsi_qla_host *vha)
0971de7f 3947{
f999f4c1
AV		 3948 struct qla_work_evt *e, *tmp;
3949 unsigned long flags;
3950 LIST_HEAD(work);
0971de7f 3951
f999f4c1
AV		 3952 spin_lock_irqsave(&vha->work_lock, flags);
3953 list_splice_init(&vha->work_list, &work);
3954 spin_unlock_irqrestore(&vha->work_lock, flags);
3955
3956 list_for_each_entry_safe(e, tmp, &work, list) {
0971de7f 3957 list_del_init(&e->list);
0971de7f
AV		 3958
3959 switch (e->type) {
3960 case QLA_EVT_AEN:
e315cd28 3961 fc_host_post_event(vha->host, fc_get_event_number(),
0971de7f
AV		 3962 e->u.aen.code, e->u.aen.data);
3963 break;
8a659571
AV		 3964 case QLA_EVT_IDC_ACK:
3965 qla81xx_idc_ack(vha, e->u.idc_ack.mb);
3966 break;
ac280b67
AV		 3967 case QLA_EVT_ASYNC_LOGIN:
3968 qla2x00_async_login(vha, e->u.logio.fcport,
3969 e->u.logio.data);
3970 break;
3971 case QLA_EVT_ASYNC_LOGIN_DONE:
3972 qla2x00_async_login_done(vha, e->u.logio.fcport,
3973 e->u.logio.data);
3974 break;
3975 case QLA_EVT_ASYNC_LOGOUT:
3976 qla2x00_async_logout(vha, e->u.logio.fcport);
3977 break;
3978 case QLA_EVT_ASYNC_LOGOUT_DONE:
3979 qla2x00_async_logout_done(vha, e->u.logio.fcport,
3980 e->u.logio.data);
3981 break;
5ff1d584
AV		 3982 case QLA_EVT_ASYNC_ADISC:
3983 qla2x00_async_adisc(vha, e->u.logio.fcport,
3984 e->u.logio.data);
3985 break;
3986 case QLA_EVT_ASYNC_ADISC_DONE:
3987 qla2x00_async_adisc_done(vha, e->u.logio.fcport,
3988 e->u.logio.data);
3989 break;
3420d36c
AV		 3990 case QLA_EVT_UEVENT:
3991 qla2x00_uevent_emit(vha, e->u.uevent.code);
3992 break;
8ae6d9c7
GM		 3993 case QLA_EVT_AENFX:
3994 qlafx00_process_aen(vha, e);
3995 break;
0971de7f
AV		 3996 }
3997 if (e->flags & QLA_EVT_FLAG_FREE)
3998 kfree(e);
feafb7b1
AE		 3999
4000 /* For each work completed decrement vha ref count */
4001 QLA_VHA_MARK_NOT_BUSY(vha);
e315cd28 4002 }
e315cd28 4003}
f999f4c1 4004
e315cd28
AC		 4005/* Relogins all the fcports of a vport
4006 * Context: dpc thread
4007 */
4008void qla2x00_relogin(struct scsi_qla_host *vha)
4009{
4010 fc_port_t *fcport;
c6b2fca8 4011 int status;
e315cd28
AC		 4012 uint16_t next_loopid = 0;
4013 struct qla_hw_data *ha = vha->hw;
ac280b67 4014 uint16_t data[2];
e315cd28
AC		 4015
4016 list_for_each_entry(fcport, &vha->vp_fcports, list) {
4017 /*
4018 * If the port is not ONLINE then try to login
4019 * to it if we haven't run out of retries.
4020 */
5ff1d584
AV		 4021 if (atomic_read(&fcport->state) != FCS_ONLINE &&
4022 fcport->login_retry && !(fcport->flags & FCF_ASYNC_SENT)) {
ac280b67 4023 fcport->login_retry--;
e315cd28 4024 if (fcport->flags & FCF_FABRIC_DEVICE) {
f08b7251 4025 if (fcport->flags & FCF_FCP2_DEVICE)
e315cd28
AC		 4026 ha->isp_ops->fabric_logout(vha,
4027 fcport->loop_id,
4028 fcport->d_id.b.domain,
4029 fcport->d_id.b.area,
4030 fcport->d_id.b.al_pa);
4031
03bcfb57
JC		 4032 if (fcport->loop_id == FC_NO_LOOP_ID) {
4033 fcport->loop_id = next_loopid =
4034 ha->min_external_loopid;
4035 status = qla2x00_find_new_loop_id(
4036 vha, fcport);
4037 if (status != QLA_SUCCESS) {
4038 /* Ran out of IDs to use */
4039 break;
4040 }
4041 }
4042
ac280b67 4043 if (IS_ALOGIO_CAPABLE(ha)) {
5ff1d584 4044 fcport->flags |= FCF_ASYNC_SENT;
ac280b67
AV		 4045 data[0] = 0;
4046 data[1] = QLA_LOGIO_LOGIN_RETRIED;
4047 status = qla2x00_post_async_login_work(
4048 vha, fcport, data);
4049 if (status == QLA_SUCCESS)
4050 continue;
4051 /* Attempt a retry. */
4052 status = 1;
aaf4d3e2 4053 } else {
ac280b67
AV		 4054 status = qla2x00_fabric_login(vha,
4055 fcport, &next_loopid);
aaf4d3e2
SK		 4056 if (status == QLA_SUCCESS) {
4057 int status2;
4058 uint8_t opts;
4059
4060 opts = 0;
4061 if (fcport->flags &
4062 FCF_FCP2_DEVICE)
4063 opts |= BIT_1;
03003960
SK		 4064 status2 =
4065 qla2x00_get_port_database(
4066 vha, fcport, opts);
aaf4d3e2
SK		 4067 if (status2 != QLA_SUCCESS)
4068 status = 1;
4069 }
4070 }
e315cd28
AC		 4071 } else
4072 status = qla2x00_local_device_login(vha,
4073 fcport);
4074
e315cd28
AC		 4075 if (status == QLA_SUCCESS) {
4076 fcport->old_loop_id = fcport->loop_id;
4077
7c3df132
SK		 4078 ql_dbg(ql_dbg_disc, vha, 0x2003,
4079 "Port login OK: logged in ID 0x%x.\n",
4080 fcport->loop_id);
e315cd28
AC		 4081
4082 qla2x00_update_fcport(vha, fcport);
4083
4084 } else if (status == 1) {
4085 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
4086 /* retry the login again */
7c3df132
SK		 4087 ql_dbg(ql_dbg_disc, vha, 0x2007,
4088 "Retrying %d login again loop_id 0x%x.\n",
4089 fcport->login_retry, fcport->loop_id);
e315cd28
AC		 4090 } else {
4091 fcport->login_retry = 0;
4092 }
4093
4094 if (fcport->login_retry == 0 && status != QLA_SUCCESS)
5f16b331 4095 qla2x00_clear_loop_id(fcport);
e315cd28
AC		 4096 }
4097 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
4098 break;
0971de7f 4099 }
0971de7f
AV		 4100}
4101
7d613ac6
SV		 4102/* Schedule work on any of the dpc-workqueues */
4103void
4104qla83xx_schedule_work(scsi_qla_host_t *base_vha, int work_code)
4105{
4106 struct qla_hw_data *ha = base_vha->hw;
4107
4108 switch (work_code) {
4109 case MBA_IDC_AEN: /* 0x8200 */
4110 if (ha->dpc_lp_wq)
4111 queue_work(ha->dpc_lp_wq, &ha->idc_aen);
4112 break;
4113
4114 case QLA83XX_NIC_CORE_RESET: /* 0x1 */
4115 if (!ha->flags.nic_core_reset_hdlr_active) {
4116 if (ha->dpc_hp_wq)
4117 queue_work(ha->dpc_hp_wq, &ha->nic_core_reset);
4118 } else
4119 ql_dbg(ql_dbg_p3p, base_vha, 0xb05e,
4120 "NIC Core reset is already active. Skip "
4121 "scheduling it again.\n");
4122 break;
4123 case QLA83XX_IDC_STATE_HANDLER: /* 0x2 */
4124 if (ha->dpc_hp_wq)
4125 queue_work(ha->dpc_hp_wq, &ha->idc_state_handler);
4126 break;
4127 case QLA83XX_NIC_CORE_UNRECOVERABLE: /* 0x3 */
4128 if (ha->dpc_hp_wq)
4129 queue_work(ha->dpc_hp_wq, &ha->nic_core_unrecoverable);
4130 break;
4131 default:
4132 ql_log(ql_log_warn, base_vha, 0xb05f,
4133 "Unknow work-code=0x%x.\n", work_code);
4134 }
4135
4136 return;
4137}
4138
4139/* Work: Perform NIC Core Unrecoverable state handling */
4140void
4141qla83xx_nic_core_unrecoverable_work(struct work_struct *work)
4142{
4143 struct qla_hw_data *ha =
2ad1b67c 4144 container_of(work, struct qla_hw_data, nic_core_unrecoverable);
7d613ac6
SV		 4145 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4146 uint32_t dev_state = 0;
4147
4148 qla83xx_idc_lock(base_vha, 0);
4149 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4150 qla83xx_reset_ownership(base_vha);
4151 if (ha->flags.nic_core_reset_owner) {
4152 ha->flags.nic_core_reset_owner = 0;
4153 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
4154 QLA8XXX_DEV_FAILED);
4155 ql_log(ql_log_info, base_vha, 0xb060, "HW State: FAILED.\n");
4156 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
4157 }
4158 qla83xx_idc_unlock(base_vha, 0);
4159}
4160
4161/* Work: Execute IDC state handler */
4162void
4163qla83xx_idc_state_handler_work(struct work_struct *work)
4164{
4165 struct qla_hw_data *ha =
2ad1b67c 4166 container_of(work, struct qla_hw_data, idc_state_handler);
7d613ac6
SV		 4167 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4168 uint32_t dev_state = 0;
4169
4170 qla83xx_idc_lock(base_vha, 0);
4171 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4172 if (dev_state == QLA8XXX_DEV_FAILED ||
4173 dev_state == QLA8XXX_DEV_NEED_QUIESCENT)
4174 qla83xx_idc_state_handler(base_vha);
4175 qla83xx_idc_unlock(base_vha, 0);
4176}
4177
fa492630 4178static int
7d613ac6
SV		 4179qla83xx_check_nic_core_fw_alive(scsi_qla_host_t *base_vha)
4180{
4181 int rval = QLA_SUCCESS;
4182 unsigned long heart_beat_wait = jiffies + (1 * HZ);
4183 uint32_t heart_beat_counter1, heart_beat_counter2;
4184
4185 do {
4186 if (time_after(jiffies, heart_beat_wait)) {
4187 ql_dbg(ql_dbg_p3p, base_vha, 0xb07c,
4188 "Nic Core f/w is not alive.\n");
4189 rval = QLA_FUNCTION_FAILED;
4190 break;
4191 }
4192
4193 qla83xx_idc_lock(base_vha, 0);
4194 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
4195 &heart_beat_counter1);
4196 qla83xx_idc_unlock(base_vha, 0);
4197 msleep(100);
4198 qla83xx_idc_lock(base_vha, 0);
4199 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
4200 &heart_beat_counter2);
4201 qla83xx_idc_unlock(base_vha, 0);
4202 } while (heart_beat_counter1 == heart_beat_counter2);
4203
4204 return rval;
4205}
4206
4207/* Work: Perform NIC Core Reset handling */
4208void
4209qla83xx_nic_core_reset_work(struct work_struct *work)
4210{
4211 struct qla_hw_data *ha =
4212 container_of(work, struct qla_hw_data, nic_core_reset);
4213 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4214 uint32_t dev_state = 0;
4215
81178772
SK		 4216 if (IS_QLA2031(ha)) {
4217 if (qla2xxx_mctp_dump(base_vha) != QLA_SUCCESS)
4218 ql_log(ql_log_warn, base_vha, 0xb081,
4219 "Failed to dump mctp\n");
4220 return;
4221 }
4222
7d613ac6
SV		 4223 if (!ha->flags.nic_core_reset_hdlr_active) {
4224 if (qla83xx_check_nic_core_fw_alive(base_vha) == QLA_SUCCESS) {
4225 qla83xx_idc_lock(base_vha, 0);
4226 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE,
4227 &dev_state);
4228 qla83xx_idc_unlock(base_vha, 0);
4229 if (dev_state != QLA8XXX_DEV_NEED_RESET) {
4230 ql_dbg(ql_dbg_p3p, base_vha, 0xb07a,
4231 "Nic Core f/w is alive.\n");
4232 return;
4233 }
4234 }
4235
4236 ha->flags.nic_core_reset_hdlr_active = 1;
4237 if (qla83xx_nic_core_reset(base_vha)) {
4238 /* NIC Core reset failed. */
4239 ql_dbg(ql_dbg_p3p, base_vha, 0xb061,
4240 "NIC Core reset failed.\n");
4241 }
4242 ha->flags.nic_core_reset_hdlr_active = 0;
4243 }
4244}
4245
4246/* Work: Handle 8200 IDC aens */
4247void
4248qla83xx_service_idc_aen(struct work_struct *work)
4249{
4250 struct qla_hw_data *ha =
4251 container_of(work, struct qla_hw_data, idc_aen);
4252 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4253 uint32_t dev_state, idc_control;
4254
4255 qla83xx_idc_lock(base_vha, 0);
4256 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4257 qla83xx_rd_reg(base_vha, QLA83XX_IDC_CONTROL, &idc_control);
4258 qla83xx_idc_unlock(base_vha, 0);
4259 if (dev_state == QLA8XXX_DEV_NEED_RESET) {
4260 if (idc_control & QLA83XX_IDC_GRACEFUL_RESET) {
4261 ql_dbg(ql_dbg_p3p, base_vha, 0xb062,
4262 "Application requested NIC Core Reset.\n");
4263 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
4264 } else if (qla83xx_check_nic_core_fw_alive(base_vha) ==
4265 QLA_SUCCESS) {
4266 ql_dbg(ql_dbg_p3p, base_vha, 0xb07b,
4267 "Other protocol driver requested NIC Core Reset.\n");
4268 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
4269 }
4270 } else if (dev_state == QLA8XXX_DEV_FAILED ||
4271 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) {
4272 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
4273 }
4274}
4275
4276static void
4277qla83xx_wait_logic(void)
4278{
4279 int i;
4280
4281 /* Yield CPU */
4282 if (!in_interrupt()) {
4283 /*
4284 * Wait about 200ms before retrying again.
4285 * This controls the number of retries for single
4286 * lock operation.
4287 */
4288 msleep(100);
4289 schedule();
4290 } else {
4291 for (i = 0; i < 20; i++)
4292 cpu_relax(); /* This a nop instr on i386 */
4293 }
4294}
4295
fa492630 4296static int
7d613ac6
SV		 4297qla83xx_force_lock_recovery(scsi_qla_host_t *base_vha)
4298{
4299 int rval;
4300 uint32_t data;
4301 uint32_t idc_lck_rcvry_stage_mask = 0x3;
4302 uint32_t idc_lck_rcvry_owner_mask = 0x3c;
4303 struct qla_hw_data *ha = base_vha->hw;
6c315553
SK		 4304 ql_dbg(ql_dbg_p3p, base_vha, 0xb086,
4305 "Trying force recovery of the IDC lock.\n");
7d613ac6
SV		 4306
4307 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, &data);
4308 if (rval)
4309 return rval;
4310
4311 if ((data & idc_lck_rcvry_stage_mask) > 0) {
4312 return QLA_SUCCESS;
4313 } else {
4314 data = (IDC_LOCK_RECOVERY_STAGE1) | (ha->portnum << 2);
4315 rval = qla83xx_wr_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
4316 data);
4317 if (rval)
4318 return rval;
4319
4320 msleep(200);
4321
4322 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
4323 &data);
4324 if (rval)
4325 return rval;
4326
4327 if (((data & idc_lck_rcvry_owner_mask) >> 2) == ha->portnum) {
4328 data &= (IDC_LOCK_RECOVERY_STAGE2 |
4329 ~(idc_lck_rcvry_stage_mask));
4330 rval = qla83xx_wr_reg(base_vha,
4331 QLA83XX_IDC_LOCK_RECOVERY, data);
4332 if (rval)
4333 return rval;
4334
4335 /* Forcefully perform IDC UnLock */
4336 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK,
4337 &data);
4338 if (rval)
4339 return rval;
4340 /* Clear lock-id by setting 0xff */
4341 rval = qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
4342 0xff);
4343 if (rval)
4344 return rval;
4345 /* Clear lock-recovery by setting 0x0 */
4346 rval = qla83xx_wr_reg(base_vha,
4347 QLA83XX_IDC_LOCK_RECOVERY, 0x0);
4348 if (rval)
4349 return rval;
4350 } else
4351 return QLA_SUCCESS;
4352 }
4353
4354 return rval;
4355}
4356
fa492630 4357static int
7d613ac6
SV		 4358qla83xx_idc_lock_recovery(scsi_qla_host_t *base_vha)
4359{
4360 int rval = QLA_SUCCESS;
4361 uint32_t o_drv_lockid, n_drv_lockid;
4362 unsigned long lock_recovery_timeout;
4363
4364 lock_recovery_timeout = jiffies + QLA83XX_MAX_LOCK_RECOVERY_WAIT;
4365retry_lockid:
4366 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &o_drv_lockid);
4367 if (rval)
4368 goto exit;
4369
4370 /* MAX wait time before forcing IDC Lock recovery = 2 secs */
4371 if (time_after_eq(jiffies, lock_recovery_timeout)) {
4372 if (qla83xx_force_lock_recovery(base_vha) == QLA_SUCCESS)
4373 return QLA_SUCCESS;
4374 else
4375 return QLA_FUNCTION_FAILED;
4376 }
4377
4378 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &n_drv_lockid);
4379 if (rval)
4380 goto exit;
4381
4382 if (o_drv_lockid == n_drv_lockid) {
4383 qla83xx_wait_logic();
4384 goto retry_lockid;
4385 } else
4386 return QLA_SUCCESS;
4387
4388exit:
4389 return rval;
4390}
4391
4392void
4393qla83xx_idc_lock(scsi_qla_host_t *base_vha, uint16_t requester_id)
4394{
4395 uint16_t options = (requester_id << 15) | BIT_6;
4396 uint32_t data;
6c315553 4397 uint32_t lock_owner;
7d613ac6
SV		 4398 struct qla_hw_data *ha = base_vha->hw;
4399
4400 /* IDC-lock implementation using driver-lock/lock-id remote registers */
4401retry_lock:
4402 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCK, &data)
4403 == QLA_SUCCESS) {
4404 if (data) {
4405 /* Setting lock-id to our function-number */
4406 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
4407 ha->portnum);
4408 } else {
6c315553
SK		 4409 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID,
4410 &lock_owner);
7d613ac6 4411 ql_dbg(ql_dbg_p3p, base_vha, 0xb063,
6c315553
SK		 4412 "Failed to acquire IDC lock, acquired by %d, "
4413 "retrying...\n", lock_owner);
7d613ac6
SV		 4414
4415 /* Retry/Perform IDC-Lock recovery */
4416 if (qla83xx_idc_lock_recovery(base_vha)
4417 == QLA_SUCCESS) {
4418 qla83xx_wait_logic();
4419 goto retry_lock;
4420 } else
4421 ql_log(ql_log_warn, base_vha, 0xb075,
4422 "IDC Lock recovery FAILED.\n");
4423 }
4424
4425 }
4426
4427 return;
4428
4429 /* XXX: IDC-lock implementation using access-control mbx */
4430retry_lock2:
4431 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
4432 ql_dbg(ql_dbg_p3p, base_vha, 0xb072,
4433 "Failed to acquire IDC lock. retrying...\n");
4434 /* Retry/Perform IDC-Lock recovery */
4435 if (qla83xx_idc_lock_recovery(base_vha) == QLA_SUCCESS) {
4436 qla83xx_wait_logic();
4437 goto retry_lock2;
4438 } else
4439 ql_log(ql_log_warn, base_vha, 0xb076,
4440 "IDC Lock recovery FAILED.\n");
4441 }
4442
4443 return;
4444}
4445
4446void
4447qla83xx_idc_unlock(scsi_qla_host_t *base_vha, uint16_t requester_id)
4448{
4449 uint16_t options = (requester_id << 15) | BIT_7, retry;
4450 uint32_t data;
4451 struct qla_hw_data *ha = base_vha->hw;
4452
4453 /* IDC-unlock implementation using driver-unlock/lock-id
4454 * remote registers
4455 */
4456 retry = 0;
4457retry_unlock:
4458 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &data)
4459 == QLA_SUCCESS) {
4460 if (data == ha->portnum) {
4461 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, &data);
4462 /* Clearing lock-id by setting 0xff */
4463 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 0xff);
4464 } else if (retry < 10) {
4465 /* SV: XXX: IDC unlock retrying needed here? */
4466
4467 /* Retry for IDC-unlock */
4468 qla83xx_wait_logic();
4469 retry++;
4470 ql_dbg(ql_dbg_p3p, base_vha, 0xb064,
4471 "Failed to release IDC lock, retyring=%d\n", retry);
4472 goto retry_unlock;
4473 }
4474 } else if (retry < 10) {
4475 /* Retry for IDC-unlock */
4476 qla83xx_wait_logic();
4477 retry++;
4478 ql_dbg(ql_dbg_p3p, base_vha, 0xb065,
4479 "Failed to read drv-lockid, retyring=%d\n", retry);
4480 goto retry_unlock;
4481 }
4482
4483 return;
4484
4485 /* XXX: IDC-unlock implementation using access-control mbx */
4486 retry = 0;
4487retry_unlock2:
4488 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
4489 if (retry < 10) {
4490 /* Retry for IDC-unlock */
4491 qla83xx_wait_logic();
4492 retry++;
4493 ql_dbg(ql_dbg_p3p, base_vha, 0xb066,
4494 "Failed to release IDC lock, retyring=%d\n", retry);
4495 goto retry_unlock2;
4496 }
4497 }
4498
4499 return;
4500}
4501
4502int
4503__qla83xx_set_drv_presence(scsi_qla_host_t *vha)
4504{
4505 int rval = QLA_SUCCESS;
4506 struct qla_hw_data *ha = vha->hw;
4507 uint32_t drv_presence;
4508
4509 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
4510 if (rval == QLA_SUCCESS) {
4511 drv_presence |= (1 << ha->portnum);
4512 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
4513 drv_presence);
4514 }
4515
4516 return rval;
4517}
4518
4519int
4520qla83xx_set_drv_presence(scsi_qla_host_t *vha)
4521{
4522 int rval = QLA_SUCCESS;
4523
4524 qla83xx_idc_lock(vha, 0);
4525 rval = __qla83xx_set_drv_presence(vha);
4526 qla83xx_idc_unlock(vha, 0);
4527
4528 return rval;
4529}
4530
4531int
4532__qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
4533{
4534 int rval = QLA_SUCCESS;
4535 struct qla_hw_data *ha = vha->hw;
4536 uint32_t drv_presence;
4537
4538 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
4539 if (rval == QLA_SUCCESS) {
4540 drv_presence &= ~(1 << ha->portnum);
4541 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
4542 drv_presence);
4543 }
4544
4545 return rval;
4546}
4547
4548int
4549qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
4550{
4551 int rval = QLA_SUCCESS;
4552
4553 qla83xx_idc_lock(vha, 0);
4554 rval = __qla83xx_clear_drv_presence(vha);
4555 qla83xx_idc_unlock(vha, 0);
4556
4557 return rval;
4558}
4559
fa492630 4560static void
7d613ac6
SV		 4561qla83xx_need_reset_handler(scsi_qla_host_t *vha)
4562{
4563 struct qla_hw_data *ha = vha->hw;
4564 uint32_t drv_ack, drv_presence;
4565 unsigned long ack_timeout;
4566
4567 /* Wait for IDC ACK from all functions (DRV-ACK == DRV-PRESENCE) */
4568 ack_timeout = jiffies + (ha->fcoe_reset_timeout * HZ);
4569 while (1) {
4570 qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
4571 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
807fb6d8 4572 if ((drv_ack & drv_presence) == drv_presence)
7d613ac6
SV		 4573 break;
4574
4575 if (time_after_eq(jiffies, ack_timeout)) {
4576 ql_log(ql_log_warn, vha, 0xb067,
4577 "RESET ACK TIMEOUT! drv_presence=0x%x "
4578 "drv_ack=0x%x\n", drv_presence, drv_ack);
4579 /*
4580 * The function(s) which did not ack in time are forced
4581 * to withdraw any further participation in the IDC
4582 * reset.
4583 */
4584 if (drv_ack != drv_presence)
4585 qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
4586 drv_ack);
4587 break;
4588 }
4589
4590 qla83xx_idc_unlock(vha, 0);
4591 msleep(1000);
4592 qla83xx_idc_lock(vha, 0);
4593 }
4594
4595 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_COLD);
4596 ql_log(ql_log_info, vha, 0xb068, "HW State: COLD/RE-INIT.\n");
4597}
4598
fa492630 4599static int
7d613ac6
SV		 4600qla83xx_device_bootstrap(scsi_qla_host_t *vha)
4601{
4602 int rval = QLA_SUCCESS;
4603 uint32_t idc_control;
4604
4605 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_INITIALIZING);
4606 ql_log(ql_log_info, vha, 0xb069, "HW State: INITIALIZING.\n");
4607
4608 /* Clearing IDC-Control Graceful-Reset Bit before resetting f/w */
4609 __qla83xx_get_idc_control(vha, &idc_control);
4610 idc_control &= ~QLA83XX_IDC_GRACEFUL_RESET;
4611 __qla83xx_set_idc_control(vha, 0);
4612
4613 qla83xx_idc_unlock(vha, 0);
4614 rval = qla83xx_restart_nic_firmware(vha);
4615 qla83xx_idc_lock(vha, 0);
4616
4617 if (rval != QLA_SUCCESS) {
4618 ql_log(ql_log_fatal, vha, 0xb06a,
4619 "Failed to restart NIC f/w.\n");
4620 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_FAILED);
4621 ql_log(ql_log_info, vha, 0xb06b, "HW State: FAILED.\n");
4622 } else {
4623 ql_dbg(ql_dbg_p3p, vha, 0xb06c,
4624 "Success in restarting nic f/w.\n");
4625 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_READY);
4626 ql_log(ql_log_info, vha, 0xb06d, "HW State: READY.\n");
4627 }
4628
4629 return rval;
4630}
4631
4632/* Assumes idc_lock always held on entry */
4633int
4634qla83xx_idc_state_handler(scsi_qla_host_t *base_vha)
4635{
4636 struct qla_hw_data *ha = base_vha->hw;
4637 int rval = QLA_SUCCESS;
4638 unsigned long dev_init_timeout;
4639 uint32_t dev_state;
4640
4641 /* Wait for MAX-INIT-TIMEOUT for the device to go ready */
4642 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ);
4643
4644 while (1) {
4645
4646 if (time_after_eq(jiffies, dev_init_timeout)) {
4647 ql_log(ql_log_warn, base_vha, 0xb06e,
4648 "Initialization TIMEOUT!\n");
4649 /* Init timeout. Disable further NIC Core
4650 * communication.
4651 */
4652 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
4653 QLA8XXX_DEV_FAILED);
4654 ql_log(ql_log_info, base_vha, 0xb06f,
4655 "HW State: FAILED.\n");
4656 }
4657
4658 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4659 switch (dev_state) {
4660 case QLA8XXX_DEV_READY:
4661 if (ha->flags.nic_core_reset_owner)
4662 qla83xx_idc_audit(base_vha,
4663 IDC_AUDIT_COMPLETION);
4664 ha->flags.nic_core_reset_owner = 0;
4665 ql_dbg(ql_dbg_p3p, base_vha, 0xb070,
4666 "Reset_owner reset by 0x%x.\n",
4667 ha->portnum);
4668 goto exit;
4669 case QLA8XXX_DEV_COLD:
4670 if (ha->flags.nic_core_reset_owner)
4671 rval = qla83xx_device_bootstrap(base_vha);
4672 else {
4673 /* Wait for AEN to change device-state */
4674 qla83xx_idc_unlock(base_vha, 0);
4675 msleep(1000);
4676 qla83xx_idc_lock(base_vha, 0);
4677 }
4678 break;
4679 case QLA8XXX_DEV_INITIALIZING:
4680 /* Wait for AEN to change device-state */
4681 qla83xx_idc_unlock(base_vha, 0);
4682 msleep(1000);
4683 qla83xx_idc_lock(base_vha, 0);
4684 break;
4685 case QLA8XXX_DEV_NEED_RESET:
4686 if (!ql2xdontresethba && ha->flags.nic_core_reset_owner)
4687 qla83xx_need_reset_handler(base_vha);
4688 else {
4689 /* Wait for AEN to change device-state */
4690 qla83xx_idc_unlock(base_vha, 0);
4691 msleep(1000);
4692 qla83xx_idc_lock(base_vha, 0);
4693 }
4694 /* reset timeout value after need reset handler */
4695 dev_init_timeout = jiffies +
4696 (ha->fcoe_dev_init_timeout * HZ);
4697 break;
4698 case QLA8XXX_DEV_NEED_QUIESCENT:
4699 /* XXX: DEBUG for now */
4700 qla83xx_idc_unlock(base_vha, 0);
4701 msleep(1000);
4702 qla83xx_idc_lock(base_vha, 0);
4703 break;
4704 case QLA8XXX_DEV_QUIESCENT:
4705 /* XXX: DEBUG for now */
4706 if (ha->flags.quiesce_owner)
4707 goto exit;
4708
4709 qla83xx_idc_unlock(base_vha, 0);
4710 msleep(1000);
4711 qla83xx_idc_lock(base_vha, 0);
4712 dev_init_timeout = jiffies +
4713 (ha->fcoe_dev_init_timeout * HZ);
4714 break;
4715 case QLA8XXX_DEV_FAILED:
4716 if (ha->flags.nic_core_reset_owner)
4717 qla83xx_idc_audit(base_vha,
4718 IDC_AUDIT_COMPLETION);
4719 ha->flags.nic_core_reset_owner = 0;
4720 __qla83xx_clear_drv_presence(base_vha);
4721 qla83xx_idc_unlock(base_vha, 0);
4722 qla8xxx_dev_failed_handler(base_vha);
4723 rval = QLA_FUNCTION_FAILED;
4724 qla83xx_idc_lock(base_vha, 0);
4725 goto exit;
4726 case QLA8XXX_BAD_VALUE:
4727 qla83xx_idc_unlock(base_vha, 0);
4728 msleep(1000);
4729 qla83xx_idc_lock(base_vha, 0);
4730 break;
4731 default:
4732 ql_log(ql_log_warn, base_vha, 0xb071,
4733 "Unknow Device State: %x.\n", dev_state);
4734 qla83xx_idc_unlock(base_vha, 0);
4735 qla8xxx_dev_failed_handler(base_vha);
4736 rval = QLA_FUNCTION_FAILED;
4737 qla83xx_idc_lock(base_vha, 0);
4738 goto exit;
4739 }
4740 }
4741
4742exit:
4743 return rval;
4744}
4745
f3ddac19
CD		 4746void
4747qla2x00_disable_board_on_pci_error(struct work_struct *work)
4748{
4749 struct qla_hw_data *ha = container_of(work, struct qla_hw_data,
4750 board_disable);
4751 struct pci_dev *pdev = ha->pdev;
4752 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4753
4754 ql_log(ql_log_warn, base_vha, 0x015b,
4755 "Disabling adapter.\n");
4756
4757 set_bit(UNLOADING, &base_vha->dpc_flags);
4758
4759 qla2x00_delete_all_vps(ha, base_vha);
4760
4761 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
4762
4763 qla2x00_dfs_remove(base_vha);
4764
4765 qla84xx_put_chip(base_vha);
4766
4767 if (base_vha->timer_active)
4768 qla2x00_stop_timer(base_vha);
4769
4770 base_vha->flags.online = 0;
4771
4772 qla2x00_destroy_deferred_work(ha);
4773
4774 /*
4775 * Do not try to stop beacon blink as it will issue a mailbox
4776 * command.
4777 */
4778 qla2x00_free_sysfs_attr(base_vha, false);
4779
4780 fc_remove_host(base_vha->host);
4781
4782 scsi_remove_host(base_vha->host);
4783
4784 base_vha->flags.init_done = 0;
4785 qla25xx_delete_queues(base_vha);
4786 qla2x00_free_irqs(base_vha);
4787 qla2x00_free_fcports(base_vha);
4788 qla2x00_mem_free(ha);
4789 qla82xx_md_free(base_vha);
4790 qla2x00_free_queues(ha);
4791
4792 scsi_host_put(base_vha->host);
4793
4794 qla2x00_unmap_iobases(ha);
4795
4796 pci_release_selected_regions(ha->pdev, ha->bars);
4797 kfree(ha);
4798 ha = NULL;
4799
4800 pci_disable_pcie_error_reporting(pdev);
4801 pci_disable_device(pdev);
4802 pci_set_drvdata(pdev, NULL);
4803
4804}
4805
1da177e4
LT		 4806/**************************************************************************
4807* qla2x00_do_dpc
4808* This kernel thread is a task that is schedule by the interrupt handler
4809* to perform the background processing for interrupts.
4810*
4811* Notes:
4812* This task always run in the context of a kernel thread. It
4813* is kick-off by the driver's detect code and starts up
4814* up one per adapter. It immediately goes to sleep and waits for
4815* some fibre event. When either the interrupt handler or
4816* the timer routine detects a event it will one of the task
4817* bits then wake us up.
4818**************************************************************************/
4819static int
4820qla2x00_do_dpc(void *data)
4821{
2c3dfe3f 4822 int rval;
e315cd28
AC		 4823 scsi_qla_host_t *base_vha;
4824 struct qla_hw_data *ha;
1da177e4 4825
e315cd28
AC		 4826 ha = (struct qla_hw_data *)data;
4827 base_vha = pci_get_drvdata(ha->pdev);
1da177e4 4828
1da177e4
LT		 4829 set_user_nice(current, -20);
4830
563585ec 4831 set_current_state(TASK_INTERRUPTIBLE);
39a11240 4832 while (!kthread_should_stop()) {
7c3df132
SK		 4833 ql_dbg(ql_dbg_dpc, base_vha, 0x4000,
4834 "DPC handler sleeping.\n");
1da177e4 4835
39a11240
CH		 4836 schedule();
4837 __set_current_state(TASK_RUNNING);
1da177e4 4838
c142caf0
AV		 4839 if (!base_vha->flags.init_done || ha->flags.mbox_busy)
4840 goto end_loop;
1da177e4 4841
85880801 4842 if (ha->flags.eeh_busy) {
7c3df132
SK		 4843 ql_dbg(ql_dbg_dpc, base_vha, 0x4003,
4844 "eeh_busy=%d.\n", ha->flags.eeh_busy);
c142caf0 4845 goto end_loop;
85880801
AV		 4846 }
4847
1da177e4
LT		 4848 ha->dpc_active = 1;
4849
5f28d2d7
SK		 4850 ql_dbg(ql_dbg_dpc + ql_dbg_verbose, base_vha, 0x4001,
4851 "DPC handler waking up, dpc_flags=0x%lx.\n",
4852 base_vha->dpc_flags);
1da177e4 4853
e315cd28 4854 qla2x00_do_work(base_vha);
0971de7f 4855
7ec0effd
AD		 4856 if (IS_P3P_TYPE(ha)) {
4857 if (IS_QLA8044(ha)) {
4858 if (test_and_clear_bit(ISP_UNRECOVERABLE,
4859 &base_vha->dpc_flags)) {
4860 qla8044_idc_lock(ha);
4861 qla8044_wr_direct(base_vha,
4862 QLA8044_CRB_DEV_STATE_INDEX,
4863 QLA8XXX_DEV_FAILED);
4864 qla8044_idc_unlock(ha);
4865 ql_log(ql_log_info, base_vha, 0x4004,
4866 "HW State: FAILED.\n");
4867 qla8044_device_state_handler(base_vha);
4868 continue;
4869 }
4870
4871 } else {
4872 if (test_and_clear_bit(ISP_UNRECOVERABLE,
4873 &base_vha->dpc_flags)) {
4874 qla82xx_idc_lock(ha);
4875 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
4876 QLA8XXX_DEV_FAILED);
4877 qla82xx_idc_unlock(ha);
4878 ql_log(ql_log_info, base_vha, 0x0151,
4879 "HW State: FAILED.\n");
4880 qla82xx_device_state_handler(base_vha);
4881 continue;
4882 }
a9083016
GM		 4883 }
4884
4885 if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED,
4886 &base_vha->dpc_flags)) {
4887
7c3df132
SK		 4888 ql_dbg(ql_dbg_dpc, base_vha, 0x4005,
4889 "FCoE context reset scheduled.\n");
a9083016
GM		 4890 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
4891 &base_vha->dpc_flags))) {
4892 if (qla82xx_fcoe_ctx_reset(base_vha)) {
4893 /* FCoE-ctx reset failed.
4894 * Escalate to chip-reset
4895 */
4896 set_bit(ISP_ABORT_NEEDED,
4897 &base_vha->dpc_flags);
4898 }
4899 clear_bit(ABORT_ISP_ACTIVE,
4900 &base_vha->dpc_flags);
4901 }
4902
7c3df132
SK		 4903 ql_dbg(ql_dbg_dpc, base_vha, 0x4006,
4904 "FCoE context reset end.\n");
a9083016 4905 }
8ae6d9c7
GM		 4906 } else if (IS_QLAFX00(ha)) {
4907 if (test_and_clear_bit(ISP_UNRECOVERABLE,
4908 &base_vha->dpc_flags)) {
4909 ql_dbg(ql_dbg_dpc, base_vha, 0x4020,
4910 "Firmware Reset Recovery\n");
4911 if (qlafx00_reset_initialize(base_vha)) {
4912 /* Failed. Abort isp later. */
4913 if (!test_bit(UNLOADING,
4914 &base_vha->dpc_flags))
4915 set_bit(ISP_UNRECOVERABLE,
4916 &base_vha->dpc_flags);
4917 ql_dbg(ql_dbg_dpc, base_vha,
4918 0x4021,
4919 "Reset Recovery Failed\n");
4920 }
4921 }
4922
4923 if (test_and_clear_bit(FX00_TARGET_SCAN,
4924 &base_vha->dpc_flags)) {
4925 ql_dbg(ql_dbg_dpc, base_vha, 0x4022,
4926 "ISPFx00 Target Scan scheduled\n");
4927 if (qlafx00_rescan_isp(base_vha)) {
4928 if (!test_bit(UNLOADING,
4929 &base_vha->dpc_flags))
4930 set_bit(ISP_UNRECOVERABLE,
4931 &base_vha->dpc_flags);
4932 ql_dbg(ql_dbg_dpc, base_vha, 0x401e,
4933 "ISPFx00 Target Scan Failed\n");
4934 }
4935 ql_dbg(ql_dbg_dpc, base_vha, 0x401f,
4936 "ISPFx00 Target Scan End\n");
4937 }
e8f5e95d
AB		 4938 if (test_and_clear_bit(FX00_HOST_INFO_RESEND,
4939 &base_vha->dpc_flags)) {
4940 ql_dbg(ql_dbg_dpc, base_vha, 0x4023,
4941 "ISPFx00 Host Info resend scheduled\n");
4942 qlafx00_fx_disc(base_vha,
4943 &base_vha->hw->mr.fcport,
4944 FXDISC_REG_HOST_INFO);
4945 }
a9083016
GM		 4946 }
4947
e315cd28
AC		 4948 if (test_and_clear_bit(ISP_ABORT_NEEDED,
4949 &base_vha->dpc_flags)) {
1da177e4 4950
7c3df132
SK		 4951 ql_dbg(ql_dbg_dpc, base_vha, 0x4007,
4952 "ISP abort scheduled.\n");
1da177e4 4953 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
e315cd28 4954 &base_vha->dpc_flags))) {
1da177e4 4955
a9083016 4956 if (ha->isp_ops->abort_isp(base_vha)) {
1da177e4
LT		 4957 /* failed. retry later */
4958 set_bit(ISP_ABORT_NEEDED,
e315cd28 4959 &base_vha->dpc_flags);
99363ef8 4960 }
e315cd28
AC		 4961 clear_bit(ABORT_ISP_ACTIVE,
4962 &base_vha->dpc_flags);
99363ef8
SJ		 4963 }
4964
7c3df132
SK		 4965 ql_dbg(ql_dbg_dpc, base_vha, 0x4008,
4966 "ISP abort end.\n");
1da177e4
LT		 4967 }
4968
a394aac8
DJ		 4969 if (test_and_clear_bit(FCPORT_UPDATE_NEEDED,
4970 &base_vha->dpc_flags)) {
e315cd28 4971 qla2x00_update_fcports(base_vha);
c9c5ced9 4972 }
d97994dc 4973
2d70c103
NB		 4974 if (test_bit(SCR_PENDING, &base_vha->dpc_flags)) {
4975 int ret;
4976 ret = qla2x00_send_change_request(base_vha, 0x3, 0);
4977 if (ret != QLA_SUCCESS)
4978 ql_log(ql_log_warn, base_vha, 0x121,
4979 "Failed to enable receiving of RSCN "
4980 "requests: 0x%x.\n", ret);
4981 clear_bit(SCR_PENDING, &base_vha->dpc_flags);
4982 }
4983
8ae6d9c7
GM		 4984 if (IS_QLAFX00(ha))
4985 goto loop_resync_check;
4986
579d12b5 4987 if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) {
7c3df132
SK		 4988 ql_dbg(ql_dbg_dpc, base_vha, 0x4009,
4989 "Quiescence mode scheduled.\n");
7ec0effd
AD		 4990 if (IS_P3P_TYPE(ha)) {
4991 if (IS_QLA82XX(ha))
4992 qla82xx_device_state_handler(base_vha);
4993 if (IS_QLA8044(ha))
4994 qla8044_device_state_handler(base_vha);
8fcd6b8b
CD		 4995 clear_bit(ISP_QUIESCE_NEEDED,
4996 &base_vha->dpc_flags);
4997 if (!ha->flags.quiesce_owner) {
4998 qla2x00_perform_loop_resync(base_vha);
7ec0effd
AD		 4999 if (IS_QLA82XX(ha)) {
5000 qla82xx_idc_lock(ha);
5001 qla82xx_clear_qsnt_ready(
5002 base_vha);
5003 qla82xx_idc_unlock(ha);
5004 } else if (IS_QLA8044(ha)) {
5005 qla8044_idc_lock(ha);
5006 qla8044_clear_qsnt_ready(
5007 base_vha);
5008 qla8044_idc_unlock(ha);
5009 }
8fcd6b8b
CD		 5010 }
5011 } else {
5012 clear_bit(ISP_QUIESCE_NEEDED,
5013 &base_vha->dpc_flags);
5014 qla2x00_quiesce_io(base_vha);
579d12b5 5015 }
7c3df132
SK		 5016 ql_dbg(ql_dbg_dpc, base_vha, 0x400a,
5017 "Quiescence mode end.\n");
579d12b5
SK		 5018 }
5019
e315cd28 5020 if (test_and_clear_bit(RESET_MARKER_NEEDED,
8ae6d9c7 5021 &base_vha->dpc_flags) &&
e315cd28 5022 (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) {
1da177e4 5023
7c3df132
SK		 5024 ql_dbg(ql_dbg_dpc, base_vha, 0x400b,
5025 "Reset marker scheduled.\n");
e315cd28
AC		 5026 qla2x00_rst_aen(base_vha);
5027 clear_bit(RESET_ACTIVE, &base_vha->dpc_flags);
7c3df132
SK		 5028 ql_dbg(ql_dbg_dpc, base_vha, 0x400c,
5029 "Reset marker end.\n");
1da177e4
LT		 5030 }
5031
5032 /* Retry each device up to login retry count */
e315cd28
AC		 5033 if ((test_and_clear_bit(RELOGIN_NEEDED,
5034 &base_vha->dpc_flags)) &&
5035 !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) &&
5036 atomic_read(&base_vha->loop_state) != LOOP_DOWN) {
1da177e4 5037
7c3df132
SK		 5038 ql_dbg(ql_dbg_dpc, base_vha, 0x400d,
5039 "Relogin scheduled.\n");
e315cd28 5040 qla2x00_relogin(base_vha);
7c3df132
SK		 5041 ql_dbg(ql_dbg_dpc, base_vha, 0x400e,
5042 "Relogin end.\n");
1da177e4 5043 }
8ae6d9c7 5044loop_resync_check:
e315cd28 5045 if (test_and_clear_bit(LOOP_RESYNC_NEEDED,
8ae6d9c7 5046 &base_vha->dpc_flags)) {
1da177e4 5047
7c3df132
SK		 5048 ql_dbg(ql_dbg_dpc, base_vha, 0x400f,
5049 "Loop resync scheduled.\n");
1da177e4
LT		 5050
5051 if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE,
e315cd28 5052 &base_vha->dpc_flags))) {
1da177e4 5053
e315cd28 5054 rval = qla2x00_loop_resync(base_vha);
1da177e4 5055
e315cd28
AC		 5056 clear_bit(LOOP_RESYNC_ACTIVE,
5057 &base_vha->dpc_flags);
1da177e4
LT		 5058 }
5059
7c3df132
SK		 5060 ql_dbg(ql_dbg_dpc, base_vha, 0x4010,
5061 "Loop resync end.\n");
1da177e4
LT		 5062 }
5063
8ae6d9c7
GM		 5064 if (IS_QLAFX00(ha))
5065 goto intr_on_check;
5066
e315cd28
AC		 5067 if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) &&
5068 atomic_read(&base_vha->loop_state) == LOOP_READY) {
5069 clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags);
5070 qla2xxx_flash_npiv_conf(base_vha);
272976ca
AV		 5071 }
5072
8ae6d9c7 5073intr_on_check:
1da177e4 5074 if (!ha->interrupts_on)
fd34f556 5075 ha->isp_ops->enable_intrs(ha);
1da177e4 5076
e315cd28
AC		 5077 if (test_and_clear_bit(BEACON_BLINK_NEEDED,
5078 &base_vha->dpc_flags))
5079 ha->isp_ops->beacon_blink(base_vha);
f6df144c 5080
8ae6d9c7
GM		 5081 if (!IS_QLAFX00(ha))
5082 qla2x00_do_dpc_all_vps(base_vha);
2c3dfe3f 5083
1da177e4 5084 ha->dpc_active = 0;
c142caf0 5085end_loop:
563585ec 5086 set_current_state(TASK_INTERRUPTIBLE);
1da177e4 5087 } /* End of while(1) */
563585ec 5088 __set_current_state(TASK_RUNNING);
1da177e4 5089
7c3df132
SK		 5090 ql_dbg(ql_dbg_dpc, base_vha, 0x4011,
5091 "DPC handler exiting.\n");
1da177e4
LT		 5092
5093 /*
5094 * Make sure that nobody tries to wake us up again.
5095 */
1da177e4
LT		 5096 ha->dpc_active = 0;
5097
ac280b67
AV		 5098 /* Cleanup any residual CTX SRBs. */
5099 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
5100
39a11240
CH		 5101 return 0;
5102}
5103
5104void
e315cd28 5105qla2xxx_wake_dpc(struct scsi_qla_host *vha)
39a11240 5106{
e315cd28 5107 struct qla_hw_data *ha = vha->hw;
c795c1e4
AV		 5108 struct task_struct *t = ha->dpc_thread;
5109
e315cd28 5110 if (!test_bit(UNLOADING, &vha->dpc_flags) && t)
c795c1e4 5111 wake_up_process(t);
1da177e4
LT		 5112}
5113
1da177e4
LT		 5114/*
5115* qla2x00_rst_aen
5116* Processes asynchronous reset.
5117*
5118* Input:
5119* ha = adapter block pointer.
5120*/
5121static void
e315cd28 5122qla2x00_rst_aen(scsi_qla_host_t *vha)
1da177e4 5123{
e315cd28
AC		 5124 if (vha->flags.online && !vha->flags.reset_active &&
5125 !atomic_read(&vha->loop_down_timer) &&
5126 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) {
1da177e4 5127 do {
e315cd28 5128 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
1da177e4
LT		 5129
5130 /*
5131 * Issue marker command only when we are going to start
5132 * the I/O.
5133 */
e315cd28
AC		 5134 vha->marker_needed = 1;
5135 } while (!atomic_read(&vha->loop_down_timer) &&
5136 (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)));
1da177e4
LT		 5137 }
5138}
5139
1da177e4
LT		 5140/**************************************************************************
5141* qla2x00_timer
5142*
5143* Description:
5144* One second timer
5145*
5146* Context: Interrupt
5147***************************************************************************/
2c3dfe3f 5148void
e315cd28 5149qla2x00_timer(scsi_qla_host_t *vha)
1da177e4 5150{
1da177e4 5151 unsigned long cpu_flags = 0;
1da177e4
LT		 5152 int start_dpc = 0;
5153 int index;
5154 srb_t *sp;
85880801 5155 uint16_t w;
e315cd28 5156 struct qla_hw_data *ha = vha->hw;
73208dfd 5157 struct req_que *req;
85880801 5158
a5b36321 5159 if (ha->flags.eeh_busy) {
7c3df132
SK		 5160 ql_dbg(ql_dbg_timer, vha, 0x6000,
5161 "EEH = %d, restarting timer.\n",
5162 ha->flags.eeh_busy);
a5b36321
LC		 5163 qla2x00_restart_timer(vha, WATCH_INTERVAL);
5164 return;
5165 }
5166
f3ddac19
CD		 5167 /*
5168 * Hardware read to raise pending EEH errors during mailbox waits. If
5169 * the read returns -1 then disable the board.
5170 */
5171 if (!pci_channel_offline(ha->pdev)) {
85880801 5172 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w);
f3ddac19
CD		 5173 if (w == 0xffff)
5174 /*
5175 * Schedule this on the default system workqueue so that
5176 * all the adapter workqueues and the DPC thread can be
5177 * shutdown cleanly.
5178 */
5179 schedule_work(&ha->board_disable);
5180 }
1da177e4 5181
cefcaba6 5182 /* Make sure qla82xx_watchdog is run only for physical port */
7ec0effd 5183 if (!vha->vp_idx && IS_P3P_TYPE(ha)) {
579d12b5
SK		 5184 if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags))
5185 start_dpc++;
7ec0effd
AD		 5186 if (IS_QLA82XX(ha))
5187 qla82xx_watchdog(vha);
5188 else if (IS_QLA8044(ha))
5189 qla8044_watchdog(vha);
579d12b5
SK		 5190 }
5191
8ae6d9c7
GM		 5192 if (!vha->vp_idx && IS_QLAFX00(ha))
5193 qlafx00_timer_routine(vha);
5194
1da177e4 5195 /* Loop down handler. */
e315cd28 5196 if (atomic_read(&vha->loop_down_timer) > 0 &&
8f7daead
GM		 5197 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) &&
5198 !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags))
e315cd28 5199 && vha->flags.online) {
1da177e4 5200
e315cd28
AC		 5201 if (atomic_read(&vha->loop_down_timer) ==
5202 vha->loop_down_abort_time) {
1da177e4 5203
7c3df132
SK		 5204 ql_log(ql_log_info, vha, 0x6008,
5205 "Loop down - aborting the queues before time expires.\n");
1da177e4 5206
e315cd28
AC		 5207 if (!IS_QLA2100(ha) && vha->link_down_timeout)
5208 atomic_set(&vha->loop_state, LOOP_DEAD);
1da177e4 5209
f08b7251
AV		 5210 /*
5211 * Schedule an ISP abort to return any FCP2-device
5212 * commands.
5213 */
2c3dfe3f 5214 /* NPIV - scan physical port only */
e315cd28 5215 if (!vha->vp_idx) {
2c3dfe3f
SJ		 5216 spin_lock_irqsave(&ha->hardware_lock,
5217 cpu_flags);
73208dfd 5218 req = ha->req_q_map[0];
2c3dfe3f 5219 for (index = 1;
8d93f550 5220 index < req->num_outstanding_cmds;
2c3dfe3f
SJ		 5221 index++) {
5222 fc_port_t *sfcp;
5223
e315cd28 5224 sp = req->outstanding_cmds[index];
2c3dfe3f
SJ		 5225 if (!sp)
5226 continue;
9ba56b95 5227 if (sp->type != SRB_SCSI_CMD)
cf53b069 5228 continue;
2c3dfe3f 5229 sfcp = sp->fcport;
f08b7251 5230 if (!(sfcp->flags & FCF_FCP2_DEVICE))
2c3dfe3f 5231 continue;
bdf79621 5232
8f7daead
GM		 5233 if (IS_QLA82XX(ha))
5234 set_bit(FCOE_CTX_RESET_NEEDED,
5235 &vha->dpc_flags);
5236 else
5237 set_bit(ISP_ABORT_NEEDED,
e315cd28 5238 &vha->dpc_flags);
2c3dfe3f
SJ		 5239 break;
5240 }
5241 spin_unlock_irqrestore(&ha->hardware_lock,
e315cd28 5242 cpu_flags);
1da177e4 5243 }
1da177e4
LT		 5244 start_dpc++;
5245 }
5246
5247 /* if the loop has been down for 4 minutes, reinit adapter */
e315cd28 5248 if (atomic_dec_and_test(&vha->loop_down_timer) != 0) {
0d6e61bc 5249 if (!(vha->device_flags & DFLG_NO_CABLE)) {
7c3df132 5250 ql_log(ql_log_warn, vha, 0x6009,
1da177e4
LT		 5251 "Loop down - aborting ISP.\n");
5252
8f7daead
GM		 5253 if (IS_QLA82XX(ha))
5254 set_bit(FCOE_CTX_RESET_NEEDED,
5255 &vha->dpc_flags);
5256 else
5257 set_bit(ISP_ABORT_NEEDED,
5258 &vha->dpc_flags);
1da177e4
LT		 5259 }
5260 }
7c3df132
SK		 5261 ql_dbg(ql_dbg_timer, vha, 0x600a,
5262 "Loop down - seconds remaining %d.\n",
5263 atomic_read(&vha->loop_down_timer));
1da177e4 5264 }
cefcaba6
SK		 5265 /* Check if beacon LED needs to be blinked for physical host only */
5266 if (!vha->vp_idx && (ha->beacon_blink_led == 1)) {
999916dc 5267 /* There is no beacon_blink function for ISP82xx */
7ec0effd 5268 if (!IS_P3P_TYPE(ha)) {
999916dc
SK		 5269 set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags);
5270 start_dpc++;
5271 }
f6df144c 5272 }
5273
550bf57d 5274 /* Process any deferred work. */
e315cd28 5275 if (!list_empty(&vha->work_list))
550bf57d
AV		 5276 start_dpc++;
5277
1da177e4 5278 /* Schedule the DPC routine if needed */
e315cd28
AC		 5279 if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) ||
5280 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) ||
5281 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags) ||
1da177e4 5282 start_dpc ||
e315cd28
AC		 5283 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) ||
5284 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) ||
a9083016
GM		 5285 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) ||
5286 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) ||
e315cd28 5287 test_bit(VP_DPC_NEEDED, &vha->dpc_flags) ||
50280c01 5288 test_bit(RELOGIN_NEEDED, &vha->dpc_flags))) {
7c3df132
SK		 5289 ql_dbg(ql_dbg_timer, vha, 0x600b,
5290 "isp_abort_needed=%d loop_resync_needed=%d "
5291 "fcport_update_needed=%d start_dpc=%d "
5292 "reset_marker_needed=%d",
5293 test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags),
5294 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags),
5295 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags),
5296 start_dpc,
5297 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags));
5298 ql_dbg(ql_dbg_timer, vha, 0x600c,
5299 "beacon_blink_needed=%d isp_unrecoverable=%d "
5300 "fcoe_ctx_reset_needed=%d vp_dpc_needed=%d "
50280c01 5301 "relogin_needed=%d.\n",
7c3df132
SK		 5302 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags),
5303 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags),
5304 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags),
5305 test_bit(VP_DPC_NEEDED, &vha->dpc_flags),
50280c01 5306 test_bit(RELOGIN_NEEDED, &vha->dpc_flags));
e315cd28 5307 qla2xxx_wake_dpc(vha);
7c3df132 5308 }
1da177e4 5309
e315cd28 5310 qla2x00_restart_timer(vha, WATCH_INTERVAL);
1da177e4
LT		 5311}
5312
5433383e
AV		 5313/* Firmware interface routines. */
5314
f73cb695 5315#define FW_BLOBS 11
5433383e
AV		 5316#define FW_ISP21XX 0
5317#define FW_ISP22XX 1
5318#define FW_ISP2300 2
5319#define FW_ISP2322 3
48c02fde 5320#define FW_ISP24XX 4
c3a2f0df 5321#define FW_ISP25XX 5
3a03eb79 5322#define FW_ISP81XX 6
a9083016 5323#define FW_ISP82XX 7
6246b8a1
GM		 5324#define FW_ISP2031 8
5325#define FW_ISP8031 9
f73cb695 5326#define FW_ISP2071 10
5433383e 5327
bb8ee499
AV		 5328#define FW_FILE_ISP21XX "ql2100_fw.bin"
5329#define FW_FILE_ISP22XX "ql2200_fw.bin"
5330#define FW_FILE_ISP2300 "ql2300_fw.bin"
5331#define FW_FILE_ISP2322 "ql2322_fw.bin"
5332#define FW_FILE_ISP24XX "ql2400_fw.bin"
c3a2f0df 5333#define FW_FILE_ISP25XX "ql2500_fw.bin"
3a03eb79 5334#define FW_FILE_ISP81XX "ql8100_fw.bin"
a9083016 5335#define FW_FILE_ISP82XX "ql8200_fw.bin"
6246b8a1
GM		 5336#define FW_FILE_ISP2031 "ql2600_fw.bin"
5337#define FW_FILE_ISP8031 "ql8300_fw.bin"
f73cb695
CD		 5338#define FW_FILE_ISP2071 "ql2700_fw.bin"
5339
bb8ee499 5340
e1e82b6f 5341static DEFINE_MUTEX(qla_fw_lock);
5433383e
AV		 5342
5343static struct fw_blob qla_fw_blobs[FW_BLOBS] = {
bb8ee499
AV		 5344 { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, },
5345 { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, },
5346 { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, },
5347 { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, },
5348 { .name = FW_FILE_ISP24XX, },
c3a2f0df 5349 { .name = FW_FILE_ISP25XX, },
3a03eb79 5350 { .name = FW_FILE_ISP81XX, },
a9083016 5351 { .name = FW_FILE_ISP82XX, },
6246b8a1
GM		 5352 { .name = FW_FILE_ISP2031, },
5353 { .name = FW_FILE_ISP8031, },
f73cb695 5354 { .name = FW_FILE_ISP2071, },
5433383e
AV		 5355};
5356
5357struct fw_blob *
e315cd28 5358qla2x00_request_firmware(scsi_qla_host_t *vha)
5433383e 5359{
e315cd28 5360 struct qla_hw_data *ha = vha->hw;
5433383e
AV		 5361 struct fw_blob *blob;
5362
5433383e
AV		 5363 if (IS_QLA2100(ha)) {
5364 blob = &qla_fw_blobs[FW_ISP21XX];
5365 } else if (IS_QLA2200(ha)) {
5366 blob = &qla_fw_blobs[FW_ISP22XX];
48c02fde 5367 } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
5433383e 5368 blob = &qla_fw_blobs[FW_ISP2300];
48c02fde 5369 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
5433383e 5370 blob = &qla_fw_blobs[FW_ISP2322];
4d4df193 5371 } else if (IS_QLA24XX_TYPE(ha)) {
5433383e 5372 blob = &qla_fw_blobs[FW_ISP24XX];
c3a2f0df
AV		 5373 } else if (IS_QLA25XX(ha)) {
5374 blob = &qla_fw_blobs[FW_ISP25XX];
3a03eb79
AV		 5375 } else if (IS_QLA81XX(ha)) {
5376 blob = &qla_fw_blobs[FW_ISP81XX];
a9083016
GM		 5377 } else if (IS_QLA82XX(ha)) {
5378 blob = &qla_fw_blobs[FW_ISP82XX];
6246b8a1
GM		 5379 } else if (IS_QLA2031(ha)) {
5380 blob = &qla_fw_blobs[FW_ISP2031];
5381 } else if (IS_QLA8031(ha)) {
5382 blob = &qla_fw_blobs[FW_ISP8031];
f73cb695
CD		 5383 } else if (IS_QLA2071(ha)) {
5384 blob = &qla_fw_blobs[FW_ISP2071];
8a655229
DC		 5385 } else {
5386 return NULL;
5433383e
AV		 5387 }
5388
e1e82b6f 5389 mutex_lock(&qla_fw_lock);
5433383e
AV		 5390 if (blob->fw)
5391 goto out;
5392
5393 if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) {
7c3df132
SK		 5394 ql_log(ql_log_warn, vha, 0x0063,
5395 "Failed to load firmware image (%s).\n", blob->name);
5433383e
AV		 5396 blob->fw = NULL;
5397 blob = NULL;
5398 goto out;
5399 }
5400
5401out:
e1e82b6f 5402 mutex_unlock(&qla_fw_lock);
5433383e
AV		 5403 return blob;
5404}
5405
5406static void
5407qla2x00_release_firmware(void)
5408{
5409 int idx;
5410
e1e82b6f 5411 mutex_lock(&qla_fw_lock);
5433383e 5412 for (idx = 0; idx < FW_BLOBS; idx++)
cf92549f 5413 release_firmware(qla_fw_blobs[idx].fw);
e1e82b6f 5414 mutex_unlock(&qla_fw_lock);
5433383e
AV		 5415}
5416
14e660e6
SJ		 5417static pci_ers_result_t
5418qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
5419{
85880801
AV		 5420 scsi_qla_host_t *vha = pci_get_drvdata(pdev);
5421 struct qla_hw_data *ha = vha->hw;
5422
7c3df132
SK		 5423 ql_dbg(ql_dbg_aer, vha, 0x9000,
5424 "PCI error detected, state %x.\n", state);
b9b12f73 5425
14e660e6
SJ		 5426 switch (state) {
5427 case pci_channel_io_normal:
85880801 5428 ha->flags.eeh_busy = 0;
14e660e6
SJ		 5429 return PCI_ERS_RESULT_CAN_RECOVER;
5430 case pci_channel_io_frozen:
85880801 5431 ha->flags.eeh_busy = 1;
a5b36321
LC		 5432 /* For ISP82XX complete any pending mailbox cmd */
5433 if (IS_QLA82XX(ha)) {
7190575f 5434 ha->flags.isp82xx_fw_hung = 1;
c8f6544e
CD		 5435 ql_dbg(ql_dbg_aer, vha, 0x9001, "Pci channel io frozen\n");
5436 qla82xx_clear_pending_mbx(vha);
a5b36321 5437 }
90a86fc0 5438 qla2x00_free_irqs(vha);
14e660e6 5439 pci_disable_device(pdev);
bddd2d65
LC		 5440 /* Return back all IOs */
5441 qla2x00_abort_all_cmds(vha, DID_RESET << 16);
14e660e6
SJ		 5442 return PCI_ERS_RESULT_NEED_RESET;
5443 case pci_channel_io_perm_failure:
85880801
AV		 5444 ha->flags.pci_channel_io_perm_failure = 1;
5445 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
14e660e6
SJ		 5446 return PCI_ERS_RESULT_DISCONNECT;
5447 }
5448 return PCI_ERS_RESULT_NEED_RESET;
5449}
5450
5451static pci_ers_result_t
5452qla2xxx_pci_mmio_enabled(struct pci_dev *pdev)
5453{
5454 int risc_paused = 0;
5455 uint32_t stat;
5456 unsigned long flags;
e315cd28
AC		 5457 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
5458 struct qla_hw_data *ha = base_vha->hw;
14e660e6
SJ		 5459 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
5460 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
5461
bcc5b6d3
SK		 5462 if (IS_QLA82XX(ha))
5463 return PCI_ERS_RESULT_RECOVERED;
5464
14e660e6
SJ		 5465 spin_lock_irqsave(&ha->hardware_lock, flags);
5466 if (IS_QLA2100(ha) || IS_QLA2200(ha)){
5467 stat = RD_REG_DWORD(&reg->hccr);
5468 if (stat & HCCR_RISC_PAUSE)
5469 risc_paused = 1;
5470 } else if (IS_QLA23XX(ha)) {
5471 stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
5472 if (stat & HSR_RISC_PAUSED)
5473 risc_paused = 1;
5474 } else if (IS_FWI2_CAPABLE(ha)) {
5475 stat = RD_REG_DWORD(&reg24->host_status);
5476 if (stat & HSRX_RISC_PAUSED)
5477 risc_paused = 1;
5478 }
5479 spin_unlock_irqrestore(&ha->hardware_lock, flags);
5480
5481 if (risc_paused) {
7c3df132
SK		 5482 ql_log(ql_log_info, base_vha, 0x9003,
5483 "RISC paused -- mmio_enabled, Dumping firmware.\n");
e315cd28 5484 ha->isp_ops->fw_dump(base_vha, 0);
14e660e6
SJ		 5485
5486 return PCI_ERS_RESULT_NEED_RESET;
5487 } else
5488 return PCI_ERS_RESULT_RECOVERED;
5489}
5490
fa492630
SK		 5491static uint32_t
5492qla82xx_error_recovery(scsi_qla_host_t *base_vha)
a5b36321
LC		 5493{
5494 uint32_t rval = QLA_FUNCTION_FAILED;
5495 uint32_t drv_active = 0;
5496 struct qla_hw_data *ha = base_vha->hw;
5497 int fn;
5498 struct pci_dev *other_pdev = NULL;
5499
7c3df132
SK		 5500 ql_dbg(ql_dbg_aer, base_vha, 0x9006,
5501 "Entered %s.\n", __func__);
a5b36321
LC		 5502
5503 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
5504
5505 if (base_vha->flags.online) {
5506 /* Abort all outstanding commands,
5507 * so as to be requeued later */
5508 qla2x00_abort_isp_cleanup(base_vha);
5509 }
5510
5511
5512 fn = PCI_FUNC(ha->pdev->devfn);
5513 while (fn > 0) {
5514 fn--;
7c3df132
SK		 5515 ql_dbg(ql_dbg_aer, base_vha, 0x9007,
5516 "Finding pci device at function = 0x%x.\n", fn);
a5b36321
LC		 5517 other_pdev =
5518 pci_get_domain_bus_and_slot(pci_domain_nr(ha->pdev->bus),
5519 ha->pdev->bus->number, PCI_DEVFN(PCI_SLOT(ha->pdev->devfn),
5520 fn));
5521
5522 if (!other_pdev)
5523 continue;
5524 if (atomic_read(&other_pdev->enable_cnt)) {
7c3df132
SK		 5525 ql_dbg(ql_dbg_aer, base_vha, 0x9008,
5526 "Found PCI func available and enable at 0x%x.\n",
5527 fn);
a5b36321
LC		 5528 pci_dev_put(other_pdev);
5529 break;
5530 }
5531 pci_dev_put(other_pdev);
5532 }
5533
5534 if (!fn) {
5535 /* Reset owner */
7c3df132
SK		 5536 ql_dbg(ql_dbg_aer, base_vha, 0x9009,
5537 "This devfn is reset owner = 0x%x.\n",
5538 ha->pdev->devfn);
a5b36321
LC		 5539 qla82xx_idc_lock(ha);
5540
5541 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 5542 QLA8XXX_DEV_INITIALIZING);
a5b36321
LC		 5543
5544 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION,
5545 QLA82XX_IDC_VERSION);
5546
5547 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
7c3df132
SK		 5548 ql_dbg(ql_dbg_aer, base_vha, 0x900a,
5549 "drv_active = 0x%x.\n", drv_active);
a5b36321
LC		 5550
5551 qla82xx_idc_unlock(ha);
5552 /* Reset if device is not already reset
5553 * drv_active would be 0 if a reset has already been done
5554 */
5555 if (drv_active)
5556 rval = qla82xx_start_firmware(base_vha);
5557 else
5558 rval = QLA_SUCCESS;
5559 qla82xx_idc_lock(ha);
5560
5561 if (rval != QLA_SUCCESS) {
7c3df132
SK		 5562 ql_log(ql_log_info, base_vha, 0x900b,
5563 "HW State: FAILED.\n");
a5b36321
LC		 5564 qla82xx_clear_drv_active(ha);
5565 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 5566 QLA8XXX_DEV_FAILED);
a5b36321 5567 } else {
7c3df132
SK		 5568 ql_log(ql_log_info, base_vha, 0x900c,
5569 "HW State: READY.\n");
a5b36321 5570 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 5571 QLA8XXX_DEV_READY);
a5b36321 5572 qla82xx_idc_unlock(ha);
7190575f 5573 ha->flags.isp82xx_fw_hung = 0;
a5b36321
LC		 5574 rval = qla82xx_restart_isp(base_vha);
5575 qla82xx_idc_lock(ha);
5576 /* Clear driver state register */
5577 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, 0);
5578 qla82xx_set_drv_active(base_vha);
5579 }
5580 qla82xx_idc_unlock(ha);
5581 } else {
7c3df132
SK		 5582 ql_dbg(ql_dbg_aer, base_vha, 0x900d,
5583 "This devfn is not reset owner = 0x%x.\n",
5584 ha->pdev->devfn);
a5b36321 5585 if ((qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE) ==
7d613ac6 5586 QLA8XXX_DEV_READY)) {
7190575f 5587 ha->flags.isp82xx_fw_hung = 0;
a5b36321
LC		 5588 rval = qla82xx_restart_isp(base_vha);
5589 qla82xx_idc_lock(ha);
5590 qla82xx_set_drv_active(base_vha);
5591 qla82xx_idc_unlock(ha);
5592 }
5593 }
5594 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
5595
5596 return rval;
5597}
5598
14e660e6
SJ		 5599static pci_ers_result_t
5600qla2xxx_pci_slot_reset(struct pci_dev *pdev)
5601{
5602 pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT;
e315cd28
AC		 5603 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
5604 struct qla_hw_data *ha = base_vha->hw;
90a86fc0
JC		 5605 struct rsp_que *rsp;
5606 int rc, retries = 10;
09483916 5607
7c3df132
SK		 5608 ql_dbg(ql_dbg_aer, base_vha, 0x9004,
5609 "Slot Reset.\n");
85880801 5610
90a86fc0
JC		 5611 /* Workaround: qla2xxx driver which access hardware earlier
5612 * needs error state to be pci_channel_io_online.
5613 * Otherwise mailbox command timesout.
5614 */
5615 pdev->error_state = pci_channel_io_normal;
5616
5617 pci_restore_state(pdev);
5618
8c1496bd
RL		 5619 /* pci_restore_state() clears the saved_state flag of the device
5620 * save restored state which resets saved_state flag
5621 */
5622 pci_save_state(pdev);
5623
09483916
BH		 5624 if (ha->mem_only)
5625 rc = pci_enable_device_mem(pdev);
5626 else
5627 rc = pci_enable_device(pdev);
14e660e6 5628
09483916 5629 if (rc) {
7c3df132 5630 ql_log(ql_log_warn, base_vha, 0x9005,
14e660e6 5631 "Can't re-enable PCI device after reset.\n");
a5b36321 5632 goto exit_slot_reset;
14e660e6 5633 }
14e660e6 5634
90a86fc0
JC		 5635 rsp = ha->rsp_q_map[0];
5636 if (qla2x00_request_irqs(ha, rsp))
a5b36321 5637 goto exit_slot_reset;
90a86fc0 5638
e315cd28 5639 if (ha->isp_ops->pci_config(base_vha))
a5b36321
LC		 5640 goto exit_slot_reset;
5641
5642 if (IS_QLA82XX(ha)) {
5643 if (qla82xx_error_recovery(base_vha) == QLA_SUCCESS) {
5644 ret = PCI_ERS_RESULT_RECOVERED;
5645 goto exit_slot_reset;
5646 } else
5647 goto exit_slot_reset;
5648 }
14e660e6 5649
90a86fc0
JC		 5650 while (ha->flags.mbox_busy && retries--)
5651 msleep(1000);
85880801 5652
e315cd28 5653 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
a9083016 5654 if (ha->isp_ops->abort_isp(base_vha) == QLA_SUCCESS)
14e660e6 5655 ret = PCI_ERS_RESULT_RECOVERED;
e315cd28 5656 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
14e660e6 5657
90a86fc0 5658
a5b36321 5659exit_slot_reset:
7c3df132
SK		 5660 ql_dbg(ql_dbg_aer, base_vha, 0x900e,
5661 "slot_reset return %x.\n", ret);
85880801 5662
14e660e6
SJ		 5663 return ret;
5664}
5665
5666static void
5667qla2xxx_pci_resume(struct pci_dev *pdev)
5668{
e315cd28
AC		 5669 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
5670 struct qla_hw_data *ha = base_vha->hw;
14e660e6
SJ		 5671 int ret;
5672
7c3df132
SK		 5673 ql_dbg(ql_dbg_aer, base_vha, 0x900f,
5674 "pci_resume.\n");
85880801 5675
e315cd28 5676 ret = qla2x00_wait_for_hba_online(base_vha);
14e660e6 5677 if (ret != QLA_SUCCESS) {
7c3df132
SK		 5678 ql_log(ql_log_fatal, base_vha, 0x9002,
5679 "The device failed to resume I/O from slot/link_reset.\n");
14e660e6 5680 }
85880801 5681
3e46f031
LC		 5682 pci_cleanup_aer_uncorrect_error_status(pdev);
5683
85880801 5684 ha->flags.eeh_busy = 0;
14e660e6
SJ		 5685}
5686
a55b2d21 5687static const struct pci_error_handlers qla2xxx_err_handler = {
14e660e6
SJ		 5688 .error_detected = qla2xxx_pci_error_detected,
5689 .mmio_enabled = qla2xxx_pci_mmio_enabled,
5690 .slot_reset = qla2xxx_pci_slot_reset,
5691 .resume = qla2xxx_pci_resume,
5692};
5693
5433383e 5694static struct pci_device_id qla2xxx_pci_tbl[] = {
47f5e069
AV		 5695 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) },
5696 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) },
5697 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) },
5698 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) },
5699 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) },
5700 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) },
5701 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) },
5702 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) },
5703 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) },
4d4df193 5704 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) },
47f5e069
AV		 5705 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) },
5706 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) },
c3a2f0df 5707 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) },
6246b8a1 5708 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2031) },
3a03eb79 5709 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) },
a9083016 5710 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) },
650f528f 5711 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8031) },
8ae6d9c7 5712 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISPF001) },
7ec0effd 5713 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8044) },
f73cb695 5714 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2071) },
5433383e
AV		 5715 { 0 },
5716};
5717MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl);
5718
fca29703 5719static struct pci_driver qla2xxx_pci_driver = {
cb63067a 5720 .name = QLA2XXX_DRIVER_NAME,
0a21ef1e
JB		 5721 .driver = {
5722 .owner = THIS_MODULE,
5723 },
fca29703 5724 .id_table = qla2xxx_pci_tbl,
7ee61397 5725 .probe = qla2x00_probe_one,
4c993f76 5726 .remove = qla2x00_remove_one,
e30d1756 5727 .shutdown = qla2x00_shutdown,
14e660e6 5728 .err_handler = &qla2xxx_err_handler,
fca29703
AV		 5729};
5730
75ef9de1 5731static const struct file_operations apidev_fops = {
6a03b4cd 5732 .owner = THIS_MODULE,
6038f373 5733 .llseek = noop_llseek,
6a03b4cd
HZ		 5734};
5735
1da177e4
LT		 5736/**
5737 * qla2x00_module_init - Module initialization.
5738 **/
5739static int __init
5740qla2x00_module_init(void)
5741{
fca29703
AV		 5742 int ret = 0;
5743
1da177e4 5744 /* Allocate cache for SRBs. */
354d6b21 5745 srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0,
20c2df83 5746 SLAB_HWCACHE_ALIGN, NULL);
1da177e4 5747 if (srb_cachep == NULL) {
7c3df132
SK		 5748 ql_log(ql_log_fatal, NULL, 0x0001,
5749 "Unable to allocate SRB cache...Failing load!.\n");
1da177e4
LT		 5750 return -ENOMEM;
5751 }
5752
2d70c103
NB		 5753 /* Initialize target kmem_cache and mem_pools */
5754 ret = qlt_init();
5755 if (ret < 0) {
5756 kmem_cache_destroy(srb_cachep);
5757 return ret;
5758 } else if (ret > 0) {
5759 /*
5760 * If initiator mode is explictly disabled by qlt_init(),
5761 * prevent scsi_transport_fc.c:fc_scsi_scan_rport() from
5762 * performing scsi_scan_target() during LOOP UP event.
5763 */
5764 qla2xxx_transport_functions.disable_target_scan = 1;
5765 qla2xxx_transport_vport_functions.disable_target_scan = 1;
5766 }
5767
1da177e4
LT		 5768 /* Derive version string. */
5769 strcpy(qla2x00_version_str, QLA2XXX_VERSION);
11010fec 5770 if (ql2xextended_error_logging)
0181944f
AV		 5771 strcat(qla2x00_version_str, "-debug");
5772
1c97a12a
AV		 5773 qla2xxx_transport_template =
5774 fc_attach_transport(&qla2xxx_transport_functions);
2c3dfe3f
SJ		 5775 if (!qla2xxx_transport_template) {
5776 kmem_cache_destroy(srb_cachep);
7c3df132
SK		 5777 ql_log(ql_log_fatal, NULL, 0x0002,
5778 "fc_attach_transport failed...Failing load!.\n");
2d70c103 5779 qlt_exit();
1da177e4 5780 return -ENODEV;
2c3dfe3f 5781 }
6a03b4cd
HZ		 5782
5783 apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops);
5784 if (apidev_major < 0) {
7c3df132
SK		 5785 ql_log(ql_log_fatal, NULL, 0x0003,
5786 "Unable to register char device %s.\n", QLA2XXX_APIDEV);
6a03b4cd
HZ		 5787 }
5788
2c3dfe3f
SJ		 5789 qla2xxx_transport_vport_template =
5790 fc_attach_transport(&qla2xxx_transport_vport_functions);
5791 if (!qla2xxx_transport_vport_template) {
5792 kmem_cache_destroy(srb_cachep);
2d70c103 5793 qlt_exit();
2c3dfe3f 5794 fc_release_transport(qla2xxx_transport_template);
7c3df132
SK		 5795 ql_log(ql_log_fatal, NULL, 0x0004,
5796 "fc_attach_transport vport failed...Failing load!.\n");
1da177e4 5797 return -ENODEV;
2c3dfe3f 5798 }
7c3df132
SK		 5799 ql_log(ql_log_info, NULL, 0x0005,
5800 "QLogic Fibre Channel HBA Driver: %s.\n",
fd9a29f0 5801 qla2x00_version_str);
7ee61397 5802 ret = pci_register_driver(&qla2xxx_pci_driver);
fca29703
AV		 5803 if (ret) {
5804 kmem_cache_destroy(srb_cachep);
2d70c103 5805 qlt_exit();
fca29703 5806 fc_release_transport(qla2xxx_transport_template);
2c3dfe3f 5807 fc_release_transport(qla2xxx_transport_vport_template);
7c3df132
SK		 5808 ql_log(ql_log_fatal, NULL, 0x0006,
5809 "pci_register_driver failed...ret=%d Failing load!.\n",
5810 ret);
fca29703
AV		 5811 }
5812 return ret;
1da177e4
LT		 5813}
5814
5815/**
5816 * qla2x00_module_exit - Module cleanup.
5817 **/
5818static void __exit
5819qla2x00_module_exit(void)
5820{
6a03b4cd 5821 unregister_chrdev(apidev_major, QLA2XXX_APIDEV);
7ee61397 5822 pci_unregister_driver(&qla2xxx_pci_driver);
5433383e 5823 qla2x00_release_firmware();
354d6b21 5824 kmem_cache_destroy(srb_cachep);
2d70c103 5825 qlt_exit();
a9083016
GM		 5826 if (ctx_cachep)
5827 kmem_cache_destroy(ctx_cachep);
1da177e4 5828 fc_release_transport(qla2xxx_transport_template);
2c3dfe3f 5829 fc_release_transport(qla2xxx_transport_vport_template);
1da177e4
LT		 5830}
5831
5832module_init(qla2x00_module_init);
5833module_exit(qla2x00_module_exit);
5834
5835MODULE_AUTHOR("QLogic Corporation");
5836MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver");
5837MODULE_LICENSE("GPL");
5838MODULE_VERSION(QLA2XXX_VERSION);
bb8ee499
AV		 5839MODULE_FIRMWARE(FW_FILE_ISP21XX);
5840MODULE_FIRMWARE(FW_FILE_ISP22XX);
5841MODULE_FIRMWARE(FW_FILE_ISP2300);
5842MODULE_FIRMWARE(FW_FILE_ISP2322);
5843MODULE_FIRMWARE(FW_FILE_ISP24XX);
61623fc3 5844MODULE_FIRMWARE(FW_FILE_ISP25XX);
Linux 6.x block layer and io_uring tree(s)