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scsi: qla2xxx: Use tabs to indent code
[linux-2.6-block.git] / drivers / scsi / qla2xxx / qla_os.c
CommitLineData
1da177e4 1/*
fa90c54f 2 * QLogic Fibre Channel HBA Driver
bd21eaf9 3 * Copyright (c) 2003-2014 QLogic Corporation
1da177e4 4 *
fa90c54f 5 * See LICENSE.qla2xxx for copyright and licensing details.
1da177e4
LT		 6 */
7#include "qla_def.h"
8
9#include <linux/moduleparam.h>
10#include <linux/vmalloc.h>
1da177e4 11#include <linux/delay.h>
39a11240 12#include <linux/kthread.h>
e1e82b6f 13#include <linux/mutex.h>
3420d36c 14#include <linux/kobject.h>
5a0e3ad6 15#include <linux/slab.h>
5601236b 16#include <linux/blk-mq-pci.h>
585def9b
QT		 17#include <linux/refcount.h>
18
1da177e4
LT		 19#include <scsi/scsi_tcq.h>
20#include <scsi/scsicam.h>
21#include <scsi/scsi_transport.h>
22#include <scsi/scsi_transport_fc.h>
23
2d70c103
NB		 24#include "qla_target.h"
25
1da177e4
LT		 26/*
27 * Driver version
28 */
29char qla2x00_version_str[40];
30
6a03b4cd
HZ		 31static int apidev_major;
32
1da177e4
LT		 33/*
34 * SRB allocation cache
35 */
d7459527 36struct kmem_cache *srb_cachep;
1da177e4 37
a9083016
GM		 38/*
39 * CT6 CTX allocation cache
40 */
41static struct kmem_cache *ctx_cachep;
3ce8866c
SK		 42/*
43 * error level for logging
44 */
3f006ac3 45uint ql_errlev = 0x8001;
a9083016 46
fa492630 47static int ql2xenableclass2;
2d70c103
NB		 48module_param(ql2xenableclass2, int, S_IRUGO|S_IRUSR);
49MODULE_PARM_DESC(ql2xenableclass2,
50 "Specify if Class 2 operations are supported from the very "
51 "beginning. Default is 0 - class 2 not supported.");
52
8ae6d9c7 53
1da177e4 54int ql2xlogintimeout = 20;
f2019cb1 55module_param(ql2xlogintimeout, int, S_IRUGO);
1da177e4
LT		 56MODULE_PARM_DESC(ql2xlogintimeout,
57 "Login timeout value in seconds.");
58
a7b61842 59int qlport_down_retry;
f2019cb1 60module_param(qlport_down_retry, int, S_IRUGO);
1da177e4 61MODULE_PARM_DESC(qlport_down_retry,
900d9f98 62 "Maximum number of command retries to a port that returns "
1da177e4
LT		 63 "a PORT-DOWN status.");
64
1da177e4
LT		 65int ql2xplogiabsentdevice;
66module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR);
67MODULE_PARM_DESC(ql2xplogiabsentdevice,
68 "Option to enable PLOGI to devices that are not present after "
900d9f98 69 "a Fabric scan. This is needed for several broken switches. "
0d52e642 70 "Default is 0 - no PLOGI. 1 - perform PLOGI.");
1da177e4 71
1da177e4 72int ql2xloginretrycount = 0;
f2019cb1 73module_param(ql2xloginretrycount, int, S_IRUGO);
1da177e4
LT		 74MODULE_PARM_DESC(ql2xloginretrycount,
75 "Specify an alternate value for the NVRAM login retry count.");
76
a7a167bf 77int ql2xallocfwdump = 1;
f2019cb1 78module_param(ql2xallocfwdump, int, S_IRUGO);
a7a167bf
AV		 79MODULE_PARM_DESC(ql2xallocfwdump,
80 "Option to enable allocation of memory for a firmware dump "
81 "during HBA initialization. Memory allocation requirements "
82 "vary by ISP type. Default is 1 - allocate memory.");
83
11010fec 84int ql2xextended_error_logging;
27d94035 85module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
a2b3e01d 86module_param_named(logging, ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
11010fec 87MODULE_PARM_DESC(ql2xextended_error_logging,
3ce8866c
SK		 88 "Option to enable extended error logging,\n"
89 "\t\tDefault is 0 - no logging. 0x40000000 - Module Init & Probe.\n"
90 "\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n"
91 "\t\t0x08000000 - IO tracing. 0x04000000 - DPC Thread.\n"
92 "\t\t0x02000000 - Async events. 0x01000000 - Timer routines.\n"
93 "\t\t0x00800000 - User space. 0x00400000 - Task Management.\n"
94 "\t\t0x00200000 - AER/EEH. 0x00100000 - Multi Q.\n"
95 "\t\t0x00080000 - P3P Specific. 0x00040000 - Virtual Port.\n"
96 "\t\t0x00020000 - Buffer Dump. 0x00010000 - Misc.\n"
29f9f90c
CD		 97 "\t\t0x00008000 - Verbose. 0x00004000 - Target.\n"
98 "\t\t0x00002000 - Target Mgmt. 0x00001000 - Target TMF.\n"
3ce8866c 99 "\t\t0x7fffffff - For enabling all logs, can be too many logs.\n"
cfb0919c
CD		 100 "\t\t0x1e400000 - Preferred value for capturing essential "
101 "debug information (equivalent to old "
102 "ql2xextended_error_logging=1).\n"
3ce8866c 103 "\t\tDo LOGICAL OR of the value to enable more than one level");
0181944f 104
a9083016 105int ql2xshiftctondsd = 6;
f2019cb1 106module_param(ql2xshiftctondsd, int, S_IRUGO);
a9083016
GM		 107MODULE_PARM_DESC(ql2xshiftctondsd,
108 "Set to control shifting of command type processing "
109 "based on total number of SG elements.");
110
7e47e5ca 111int ql2xfdmienable=1;
de187df8 112module_param(ql2xfdmienable, int, S_IRUGO|S_IWUSR);
a2b3e01d 113module_param_named(fdmi, ql2xfdmienable, int, S_IRUGO|S_IWUSR);
cca5335c 114MODULE_PARM_DESC(ql2xfdmienable,
7794a5af
FW		 115 "Enables FDMI registrations. "
116 "0 - no FDMI. Default is 1 - perform FDMI.");
cca5335c 117
d213a4b7 118#define MAX_Q_DEPTH 64
50280c01 119static int ql2xmaxqdepth = MAX_Q_DEPTH;
df7baa50
AV		 120module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR);
121MODULE_PARM_DESC(ql2xmaxqdepth,
e92e4a8f 122 "Maximum queue depth to set for each LUN. "
d213a4b7 123 "Default is 64.");
df7baa50 124
e84067d7
DG		 125#if (IS_ENABLED(CONFIG_NVME_FC))
126int ql2xenabledif;
127#else
9e522cd8 128int ql2xenabledif = 2;
e84067d7 129#endif
9e522cd8 130module_param(ql2xenabledif, int, S_IRUGO);
bad75002 131MODULE_PARM_DESC(ql2xenabledif,
b97f5d0b
SM		 132 " Enable T10-CRC-DIF:\n"
133 " Default is 2.\n"
134 " 0 -- No DIF Support\n"
135 " 1 -- Enable DIF for all types\n"
136 " 2 -- Enable DIF for all types, except Type 0.\n");
bad75002 137
e84067d7
DG		 138#if (IS_ENABLED(CONFIG_NVME_FC))
139int ql2xnvmeenable = 1;
140#else
141int ql2xnvmeenable;
142#endif
143module_param(ql2xnvmeenable, int, 0644);
144MODULE_PARM_DESC(ql2xnvmeenable,
145 "Enables NVME support. "
146 "0 - no NVMe. Default is Y");
147
8cb2049c 148int ql2xenablehba_err_chk = 2;
bad75002
AE		 149module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR);
150MODULE_PARM_DESC(ql2xenablehba_err_chk,
8cb2049c 151 " Enable T10-CRC-DIF Error isolation by HBA:\n"
b97f5d0b 152 " Default is 2.\n"
8cb2049c
AE		 153 " 0 -- Error isolation disabled\n"
154 " 1 -- Error isolation enabled only for DIX Type 0\n"
155 " 2 -- Error isolation enabled for all Types\n");
bad75002 156
e5896bd5 157int ql2xiidmaenable=1;
f2019cb1 158module_param(ql2xiidmaenable, int, S_IRUGO);
e5896bd5
AV		 159MODULE_PARM_DESC(ql2xiidmaenable,
160 "Enables iIDMA settings "
161 "Default is 1 - perform iIDMA. 0 - no iIDMA.");
162
d7459527
MH		 163int ql2xmqsupport = 1;
164module_param(ql2xmqsupport, int, S_IRUGO);
165MODULE_PARM_DESC(ql2xmqsupport,
166 "Enable on demand multiple queue pairs support "
167 "Default is 1 for supported. "
168 "Set it to 0 to turn off mq qpair support.");
e337d907
AV		 169
170int ql2xfwloadbin;
86e45bf6 171module_param(ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
a2b3e01d 172module_param_named(fwload, ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
e337d907 173MODULE_PARM_DESC(ql2xfwloadbin,
7c3df132
SK		 174 "Option to specify location from which to load ISP firmware:.\n"
175 " 2 -- load firmware via the request_firmware() (hotplug).\n"
e337d907
AV		 176 " interface.\n"
177 " 1 -- load firmware from flash.\n"
178 " 0 -- use default semantics.\n");
179
ae97c91e 180int ql2xetsenable;
f2019cb1 181module_param(ql2xetsenable, int, S_IRUGO);
ae97c91e
AV		 182MODULE_PARM_DESC(ql2xetsenable,
183 "Enables firmware ETS burst."
184 "Default is 0 - skip ETS enablement.");
185
6907869d 186int ql2xdbwr = 1;
86e45bf6 187module_param(ql2xdbwr, int, S_IRUGO|S_IWUSR);
a9083016 188MODULE_PARM_DESC(ql2xdbwr,
08de2844
GM		 189 "Option to specify scheme for request queue posting.\n"
190 " 0 -- Regular doorbell.\n"
191 " 1 -- CAMRAM doorbell (faster).\n");
a9083016 192
f4c496c1 193int ql2xtargetreset = 1;
f2019cb1 194module_param(ql2xtargetreset, int, S_IRUGO);
f4c496c1
GM		 195MODULE_PARM_DESC(ql2xtargetreset,
196 "Enable target reset."
197 "Default is 1 - use hw defaults.");
198
4da26e16 199int ql2xgffidenable;
f2019cb1 200module_param(ql2xgffidenable, int, S_IRUGO);
4da26e16
CD		 201MODULE_PARM_DESC(ql2xgffidenable,
202 "Enables GFF_ID checks of port type. "
203 "Default is 0 - Do not use GFF_ID information.");
a9083016 204
043dc1d7 205int ql2xasynctmfenable = 1;
f2019cb1 206module_param(ql2xasynctmfenable, int, S_IRUGO);
3822263e
MI		 207MODULE_PARM_DESC(ql2xasynctmfenable,
208 "Enables issue of TM IOCBs asynchronously via IOCB mechanism"
84e13c45 209 "Default is 1 - Issue TM IOCBs via mailbox mechanism.");
ed0de87c
GM		 210
211int ql2xdontresethba;
86e45bf6 212module_param(ql2xdontresethba, int, S_IRUGO|S_IWUSR);
ed0de87c 213MODULE_PARM_DESC(ql2xdontresethba,
08de2844
GM		 214 "Option to specify reset behaviour.\n"
215 " 0 (Default) -- Reset on failure.\n"
216 " 1 -- Do not reset on failure.\n");
ed0de87c 217
1abf635d
HR		 218uint64_t ql2xmaxlun = MAX_LUNS;
219module_param(ql2xmaxlun, ullong, S_IRUGO);
82515920
AV		 220MODULE_PARM_DESC(ql2xmaxlun,
221 "Defines the maximum LU number to register with the SCSI "
222 "midlayer. Default is 65535.");
223
08de2844
GM		 224int ql2xmdcapmask = 0x1F;
225module_param(ql2xmdcapmask, int, S_IRUGO);
226MODULE_PARM_DESC(ql2xmdcapmask,
227 "Set the Minidump driver capture mask level. "
6e96fa7b 228 "Default is 0x1F - Can be set to 0x3, 0x7, 0xF, 0x1F, 0x7F.");
08de2844 229
3aadff35 230int ql2xmdenable = 1;
08de2844
GM		 231module_param(ql2xmdenable, int, S_IRUGO);
232MODULE_PARM_DESC(ql2xmdenable,
233 "Enable/disable MiniDump. "
3aadff35
GM		 234 "0 - MiniDump disabled. "
235 "1 (Default) - MiniDump enabled.");
08de2844 236
b0d6cabd
HM		 237int ql2xexlogins = 0;
238module_param(ql2xexlogins, uint, S_IRUGO|S_IWUSR);
239MODULE_PARM_DESC(ql2xexlogins,
240 "Number of extended Logins. "
241 "0 (Default)- Disabled.");
242
99e1b683
QT		 243int ql2xexchoffld = 1024;
244module_param(ql2xexchoffld, uint, 0644);
2f56a7f1 245MODULE_PARM_DESC(ql2xexchoffld,
99e1b683
QT		 246 "Number of target exchanges.");
247
248int ql2xiniexchg = 1024;
249module_param(ql2xiniexchg, uint, 0644);
250MODULE_PARM_DESC(ql2xiniexchg,
251 "Number of initiator exchanges.");
2f56a7f1 252
f198cafa
HM		 253int ql2xfwholdabts = 0;
254module_param(ql2xfwholdabts, int, S_IRUGO);
255MODULE_PARM_DESC(ql2xfwholdabts,
256 "Allow FW to hold status IOCB until ABTS rsp received. "
257 "0 (Default) Do not set fw option. "
258 "1 - Set fw option to hold ABTS.");
259
41dc529a
QT		 260int ql2xmvasynctoatio = 1;
261module_param(ql2xmvasynctoatio, int, S_IRUGO|S_IWUSR);
262MODULE_PARM_DESC(ql2xmvasynctoatio,
263 "Move PUREX, ABTS RX and RIDA IOCBs to ATIOQ"
264 "0 (Default). Do not move IOCBs"
265 "1 - Move IOCBs.");
266
e4e3a2ce
QT		 267int ql2xautodetectsfp = 1;
268module_param(ql2xautodetectsfp, int, 0444);
269MODULE_PARM_DESC(ql2xautodetectsfp,
270 "Detect SFP range and set appropriate distance.\n"
271 "1 (Default): Enable\n");
272
e7240af5
HM		 273int ql2xenablemsix = 1;
274module_param(ql2xenablemsix, int, 0444);
275MODULE_PARM_DESC(ql2xenablemsix,
276 "Set to enable MSI or MSI-X interrupt mechanism.\n"
277 " Default is 1, enable MSI-X interrupt mechanism.\n"
278 " 0 -- enable traditional pin-based mechanism.\n"
279 " 1 -- enable MSI-X interrupt mechanism.\n"
280 " 2 -- enable MSI interrupt mechanism.\n");
281
9ecf0b0d
QT		 282int qla2xuseresexchforels;
283module_param(qla2xuseresexchforels, int, 0444);
284MODULE_PARM_DESC(qla2xuseresexchforels,
285 "Reserve 1/2 of emergency exchanges for ELS.\n"
286 " 0 (default): disabled");
287
b3ede8ea 288static int ql2xprotmask;
7855d2ba
MP		 289module_param(ql2xprotmask, int, 0644);
290MODULE_PARM_DESC(ql2xprotmask,
291 "Override DIF/DIX protection capabilities mask\n"
292 "Default is 0 which sets protection mask based on "
293 "capabilities reported by HBA firmware.\n");
294
b3ede8ea 295static int ql2xprotguard;
7855d2ba
MP		 296module_param(ql2xprotguard, int, 0644);
297MODULE_PARM_DESC(ql2xprotguard, "Override choice of DIX checksum\n"
298 " 0 -- Let HBA firmware decide\n"
299 " 1 -- Force T10 CRC\n"
300 " 2 -- Force IP checksum\n");
301
50b81275
GM		 302int ql2xdifbundlinginternalbuffers;
303module_param(ql2xdifbundlinginternalbuffers, int, 0644);
304MODULE_PARM_DESC(ql2xdifbundlinginternalbuffers,
305 "Force using internal buffers for DIF information\n"
306 "0 (Default). Based on check.\n"
307 "1 Force using internal buffers\n");
308
1a2fbf18 309static void qla2x00_clear_drv_active(struct qla_hw_data *);
3491255e 310static void qla2x00_free_device(scsi_qla_host_t *);
5601236b 311static int qla2xxx_map_queues(struct Scsi_Host *shost);
e84067d7 312static void qla2x00_destroy_deferred_work(struct qla_hw_data *);
ce7e4af7 313
45235022 314
1da177e4 315static struct scsi_transport_template *qla2xxx_transport_template = NULL;
2c3dfe3f 316struct scsi_transport_template *qla2xxx_transport_vport_template = NULL;
1da177e4 317
1da177e4
LT		 318/* TODO Convert to inlines
319 *
320 * Timer routines
321 */
1da177e4 322
2c3dfe3f 323__inline__ void
8e5f4ba0 324qla2x00_start_timer(scsi_qla_host_t *vha, unsigned long interval)
1da177e4 325{
8e5f4ba0 326 timer_setup(&vha->timer, qla2x00_timer, 0);
e315cd28 327 vha->timer.expires = jiffies + interval * HZ;
e315cd28
AC		 328 add_timer(&vha->timer);
329 vha->timer_active = 1;
1da177e4
LT		 330}
331
332static inline void
e315cd28 333qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval)
1da177e4 334{
a9083016 335 /* Currently used for 82XX only. */
7c3df132
SK		 336 if (vha->device_flags & DFLG_DEV_FAILED) {
337 ql_dbg(ql_dbg_timer, vha, 0x600d,
338 "Device in a failed state, returning.\n");
a9083016 339 return;
7c3df132 340 }
a9083016 341
e315cd28 342 mod_timer(&vha->timer, jiffies + interval * HZ);
1da177e4
LT		 343}
344
a824ebb3 345static __inline__ void
e315cd28 346qla2x00_stop_timer(scsi_qla_host_t *vha)
1da177e4 347{
e315cd28
AC		 348 del_timer_sync(&vha->timer);
349 vha->timer_active = 0;
1da177e4
LT		 350}
351
1da177e4
LT		 352static int qla2x00_do_dpc(void *data);
353
354static void qla2x00_rst_aen(scsi_qla_host_t *);
355
73208dfd
AC		 356static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t,
357 struct req_que **, struct rsp_que **);
e30d1756 358static void qla2x00_free_fw_dump(struct qla_hw_data *);
e315cd28 359static void qla2x00_mem_free(struct qla_hw_data *);
d7459527
MH		 360int qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd,
361 struct qla_qpair *qpair);
1da177e4 362
1da177e4 363/* -------------------------------------------------------------------------- */
8abfa9e2
QT		 364static void qla_init_base_qpair(struct scsi_qla_host *vha, struct req_que *req,
365 struct rsp_que *rsp)
366{
367 struct qla_hw_data *ha = vha->hw;
368 rsp->qpair = ha->base_qpair;
369 rsp->req = req;
0691094f 370 ha->base_qpair->hw = ha;
8abfa9e2
QT		 371 ha->base_qpair->req = req;
372 ha->base_qpair->rsp = rsp;
373 ha->base_qpair->vha = vha;
374 ha->base_qpair->qp_lock_ptr = &ha->hardware_lock;
375 ha->base_qpair->use_shadow_reg = IS_SHADOW_REG_CAPABLE(ha) ? 1 : 0;
376 ha->base_qpair->msix = &ha->msix_entries[QLA_MSIX_RSP_Q];
6a629468 377 ha->base_qpair->srb_mempool = ha->srb_mempool;
8abfa9e2
QT		 378 INIT_LIST_HEAD(&ha->base_qpair->hints_list);
379 ha->base_qpair->enable_class_2 = ql2xenableclass2;
380 /* init qpair to this cpu. Will adjust at run time. */
86531887 381 qla_cpu_update(rsp->qpair, raw_smp_processor_id());
8abfa9e2
QT		 382 ha->base_qpair->pdev = ha->pdev;
383
ecc89f25 384 if (IS_QLA27XX(ha) || IS_QLA83XX(ha) || IS_QLA28XX(ha))
8abfa9e2
QT		 385 ha->base_qpair->reqq_start_iocbs = qla_83xx_start_iocbs;
386}
387
9a347ff4
CD		 388static int qla2x00_alloc_queues(struct qla_hw_data *ha, struct req_que *req,
389 struct rsp_que *rsp)
73208dfd 390{
7c3df132 391 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
6396bb22 392 ha->req_q_map = kcalloc(ha->max_req_queues, sizeof(struct req_que *),
73208dfd
AC		 393 GFP_KERNEL);
394 if (!ha->req_q_map) {
7c3df132
SK		 395 ql_log(ql_log_fatal, vha, 0x003b,
396 "Unable to allocate memory for request queue ptrs.\n");
73208dfd
AC		 397 goto fail_req_map;
398 }
399
6396bb22 400 ha->rsp_q_map = kcalloc(ha->max_rsp_queues, sizeof(struct rsp_que *),
73208dfd
AC		 401 GFP_KERNEL);
402 if (!ha->rsp_q_map) {
7c3df132
SK		 403 ql_log(ql_log_fatal, vha, 0x003c,
404 "Unable to allocate memory for response queue ptrs.\n");
73208dfd
AC		 405 goto fail_rsp_map;
406 }
d7459527 407
e326d22a
QT		 408 ha->base_qpair = kzalloc(sizeof(struct qla_qpair), GFP_KERNEL);
409 if (ha->base_qpair == NULL) {
410 ql_log(ql_log_warn, vha, 0x00e0,
411 "Failed to allocate base queue pair memory.\n");
412 goto fail_base_qpair;
413 }
414
8abfa9e2 415 qla_init_base_qpair(vha, req, rsp);
e326d22a 416
c38d1baf 417 if ((ql2xmqsupport || ql2xnvmeenable) && ha->max_qpairs) {
d7459527
MH		 418 ha->queue_pair_map = kcalloc(ha->max_qpairs, sizeof(struct qla_qpair *),
419 GFP_KERNEL);
420 if (!ha->queue_pair_map) {
421 ql_log(ql_log_fatal, vha, 0x0180,
422 "Unable to allocate memory for queue pair ptrs.\n");
423 goto fail_qpair_map;
424 }
d7459527
MH		 425 }
426
9a347ff4
CD		 427 /*
428 * Make sure we record at least the request and response queue zero in
429 * case we need to free them if part of the probe fails.
430 */
431 ha->rsp_q_map[0] = rsp;
432 ha->req_q_map[0] = req;
73208dfd
AC		 433 set_bit(0, ha->rsp_qid_map);
434 set_bit(0, ha->req_qid_map);
6a2cf8d3 435 return 0;
73208dfd 436
d7459527 437fail_qpair_map:
82de802a
QT		 438 kfree(ha->base_qpair);
439 ha->base_qpair = NULL;
440fail_base_qpair:
d7459527
MH		 441 kfree(ha->rsp_q_map);
442 ha->rsp_q_map = NULL;
73208dfd
AC		 443fail_rsp_map:
444 kfree(ha->req_q_map);
445 ha->req_q_map = NULL;
446fail_req_map:
447 return -ENOMEM;
448}
449
2afa19a9 450static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req)
73208dfd 451{
8ae6d9c7
GM		 452 if (IS_QLAFX00(ha)) {
453 if (req && req->ring_fx00)
454 dma_free_coherent(&ha->pdev->dev,
455 (req->length_fx00 + 1) * sizeof(request_t),
456 req->ring_fx00, req->dma_fx00);
457 } else if (req && req->ring)
73208dfd
AC		 458 dma_free_coherent(&ha->pdev->dev,
459 (req->length + 1) * sizeof(request_t),
460 req->ring, req->dma);
461
6d634067 462 if (req)
8d93f550 463 kfree(req->outstanding_cmds);
6d634067
BK		 464
465 kfree(req);
73208dfd
AC		 466}
467
2afa19a9
AC		 468static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp)
469{
8ae6d9c7 470 if (IS_QLAFX00(ha)) {
3f6c9be2 471 if (rsp && rsp->ring_fx00)
8ae6d9c7
GM		 472 dma_free_coherent(&ha->pdev->dev,
473 (rsp->length_fx00 + 1) * sizeof(request_t),
474 rsp->ring_fx00, rsp->dma_fx00);
475 } else if (rsp && rsp->ring) {
2afa19a9
AC		 476 dma_free_coherent(&ha->pdev->dev,
477 (rsp->length + 1) * sizeof(response_t),
478 rsp->ring, rsp->dma);
8ae6d9c7 479 }
6d634067 480 kfree(rsp);
2afa19a9
AC		 481}
482
73208dfd
AC		 483static void qla2x00_free_queues(struct qla_hw_data *ha)
484{
485 struct req_que *req;
486 struct rsp_que *rsp;
487 int cnt;
093df737 488 unsigned long flags;
73208dfd 489
82de802a
QT		 490 if (ha->queue_pair_map) {
491 kfree(ha->queue_pair_map);
492 ha->queue_pair_map = NULL;
493 }
494 if (ha->base_qpair) {
495 kfree(ha->base_qpair);
496 ha->base_qpair = NULL;
497 }
498
093df737 499 spin_lock_irqsave(&ha->hardware_lock, flags);
2afa19a9 500 for (cnt = 0; cnt < ha->max_req_queues; cnt++) {
cb43285f
QT		 501 if (!test_bit(cnt, ha->req_qid_map))
502 continue;
503
73208dfd 504 req = ha->req_q_map[cnt];
093df737
QT		 505 clear_bit(cnt, ha->req_qid_map);
506 ha->req_q_map[cnt] = NULL;
507
508 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2afa19a9 509 qla2x00_free_req_que(ha, req);
093df737 510 spin_lock_irqsave(&ha->hardware_lock, flags);
73208dfd 511 }
093df737
QT		 512 spin_unlock_irqrestore(&ha->hardware_lock, flags);
513
73208dfd
AC		 514 kfree(ha->req_q_map);
515 ha->req_q_map = NULL;
2afa19a9 516
093df737
QT		 517
518 spin_lock_irqsave(&ha->hardware_lock, flags);
2afa19a9 519 for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) {
cb43285f
QT		 520 if (!test_bit(cnt, ha->rsp_qid_map))
521 continue;
522
2afa19a9 523 rsp = ha->rsp_q_map[cnt];
c3c42394 524 clear_bit(cnt, ha->rsp_qid_map);
093df737
QT		 525 ha->rsp_q_map[cnt] = NULL;
526 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2afa19a9 527 qla2x00_free_rsp_que(ha, rsp);
093df737 528 spin_lock_irqsave(&ha->hardware_lock, flags);
2afa19a9 529 }
093df737
QT		 530 spin_unlock_irqrestore(&ha->hardware_lock, flags);
531
2afa19a9
AC		 532 kfree(ha->rsp_q_map);
533 ha->rsp_q_map = NULL;
73208dfd
AC		 534}
535
1da177e4 536static char *
e315cd28 537qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str)
1da177e4 538{
e315cd28 539 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 540 static char *pci_bus_modes[] = {
541 "33", "66", "100", "133",
542 };
543 uint16_t pci_bus;
544
545 strcpy(str, "PCI");
546 pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9;
547 if (pci_bus) {
548 strcat(str, "-X (");
549 strcat(str, pci_bus_modes[pci_bus]);
550 } else {
551 pci_bus = (ha->pci_attr & BIT_8) >> 8;
552 strcat(str, " (");
553 strcat(str, pci_bus_modes[pci_bus]);
554 }
555 strcat(str, " MHz)");
556
557 return (str);
558}
559
fca29703 560static char *
e315cd28 561qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str)
fca29703
AV		 562{
563 static char *pci_bus_modes[] = { "33", "66", "100", "133", };
e315cd28 564 struct qla_hw_data *ha = vha->hw;
fca29703 565 uint32_t pci_bus;
fca29703 566
62a276f8 567 if (pci_is_pcie(ha->pdev)) {
fca29703 568 char lwstr[6];
62a276f8 569 uint32_t lstat, lspeed, lwidth;
fca29703 570
62a276f8
BH		 571 pcie_capability_read_dword(ha->pdev, PCI_EXP_LNKCAP, &lstat);
572 lspeed = lstat & PCI_EXP_LNKCAP_SLS;
573 lwidth = (lstat & PCI_EXP_LNKCAP_MLW) >> 4;
fca29703
AV		 574
575 strcpy(str, "PCIe (");
49300af7
SK		 576 switch (lspeed) {
577 case 1:
c87a0d8c 578 strcat(str, "2.5GT/s ");
49300af7
SK		 579 break;
580 case 2:
c87a0d8c 581 strcat(str, "5.0GT/s ");
49300af7
SK		 582 break;
583 case 3:
584 strcat(str, "8.0GT/s ");
585 break;
586 default:
fca29703 587 strcat(str, "<unknown> ");
49300af7
SK		 588 break;
589 }
fca29703
AV		 590 snprintf(lwstr, sizeof(lwstr), "x%d)", lwidth);
591 strcat(str, lwstr);
592
593 return str;
594 }
595
596 strcpy(str, "PCI");
597 pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8;
598 if (pci_bus == 0 || pci_bus == 8) {
599 strcat(str, " (");
600 strcat(str, pci_bus_modes[pci_bus >> 3]);
601 } else {
602 strcat(str, "-X ");
603 if (pci_bus & BIT_2)
604 strcat(str, "Mode 2");
605 else
606 strcat(str, "Mode 1");
607 strcat(str, " (");
608 strcat(str, pci_bus_modes[pci_bus & ~BIT_2]);
609 }
610 strcat(str, " MHz)");
611
612 return str;
613}
614
e5f82ab8 615static char *
df57caba 616qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
1da177e4
LT		 617{
618 char un_str[10];
e315cd28 619 struct qla_hw_data *ha = vha->hw;
fa2a1ce5 620
df57caba
HM		 621 snprintf(str, size, "%d.%02d.%02d ", ha->fw_major_version,
622 ha->fw_minor_version, ha->fw_subminor_version);
1da177e4
LT		 623
624 if (ha->fw_attributes & BIT_9) {
625 strcat(str, "FLX");
626 return (str);
627 }
628
629 switch (ha->fw_attributes & 0xFF) {
630 case 0x7:
631 strcat(str, "EF");
632 break;
633 case 0x17:
634 strcat(str, "TP");
635 break;
636 case 0x37:
637 strcat(str, "IP");
638 break;
639 case 0x77:
640 strcat(str, "VI");
641 break;
642 default:
643 sprintf(un_str, "(%x)", ha->fw_attributes);
644 strcat(str, un_str);
645 break;
646 }
647 if (ha->fw_attributes & 0x100)
648 strcat(str, "X");
649
650 return (str);
651}
652
e5f82ab8 653static char *
df57caba 654qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
fca29703 655{
e315cd28 656 struct qla_hw_data *ha = vha->hw;
f0883ac6 657
df57caba 658 snprintf(str, size, "%d.%02d.%02d (%x)", ha->fw_major_version,
3a03eb79 659 ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes);
fca29703 660 return str;
fca29703
AV		 661}
662
9ba56b95 663void
25ff6af1 664qla2x00_sp_free_dma(void *ptr)
fca29703 665{
25ff6af1
JC		 666 srb_t *sp = ptr;
667 struct qla_hw_data *ha = sp->vha->hw;
9ba56b95 668 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
9ba56b95 669 void *ctx = GET_CMD_CTX_SP(sp);
fca29703 670
9ba56b95
GM		 671 if (sp->flags & SRB_DMA_VALID) {
672 scsi_dma_unmap(cmd);
673 sp->flags &= ~SRB_DMA_VALID;
7c3df132 674 }
fca29703 675
9ba56b95
GM		 676 if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
677 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
678 scsi_prot_sg_count(cmd), cmd->sc_data_direction);
679 sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
680 }
681
d5ff0eed 682 if (!ctx)
711a08d7 683 return;
d5ff0eed 684
9ba56b95
GM		 685 if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
686 /* List assured to be having elements */
d5ff0eed 687 qla2x00_clean_dsd_pool(ha, ctx);
9ba56b95
GM		 688 sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
689 }
690
691 if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
d5ff0eed
JC		 692 struct crc_context *ctx0 = ctx;
693
694 dma_pool_free(ha->dl_dma_pool, ctx0, ctx0->crc_ctx_dma);
9ba56b95
GM		 695 sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
696 }
697
698 if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
d5ff0eed 699 struct ct6_dsd *ctx1 = ctx;
fca29703 700
9ba56b95 701 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd,
d5ff0eed 702 ctx1->fcp_cmnd_dma);
9ba56b95
GM		 703 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list);
704 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt;
705 ha->gbl_dsd_avail += ctx1->dsd_use_cnt;
706 mempool_free(ctx1, ha->ctx_mempool);
9ba56b95 707 }
9ba56b95
GM		 708}
709
d7459527 710void
25ff6af1 711qla2x00_sp_compl(void *ptr, int res)
9ba56b95 712{
25ff6af1 713 srb_t *sp = ptr;
9ba56b95 714 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
711a08d7 715 wait_queue_head_t *cwaitq = sp->cwaitq;
9ba56b95 716
9ba56b95 717 if (atomic_read(&sp->ref_count) == 0) {
25ff6af1 718 ql_dbg(ql_dbg_io, sp->vha, 0x3015,
9ba56b95
GM		 719 "SP reference-count to ZERO -- sp=%p cmd=%p.\n",
720 sp, GET_CMD_SP(sp));
721 if (ql2xextended_error_logging & ql_dbg_io)
8fbdac8c 722 WARN_ON(atomic_read(&sp->ref_count) == 0);
9ba56b95
GM		 723 return;
724 }
725 if (!atomic_dec_and_test(&sp->ref_count))
726 return;
727
f3caa990 728 sp->free(sp);
740e2935 729 cmd->result = res;
711a08d7 730 CMD_SP(cmd) = NULL;
9ba56b95 731 cmd->scsi_done(cmd);
711a08d7
GM		 732 if (cwaitq)
733 wake_up(cwaitq);
734 qla2x00_rel_sp(sp);
fca29703
AV		 735}
736
d7459527 737void
25ff6af1 738qla2xxx_qpair_sp_free_dma(void *ptr)
d7459527
MH		 739{
740 srb_t *sp = (srb_t *)ptr;
741 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
742 struct qla_hw_data *ha = sp->fcport->vha->hw;
743 void *ctx = GET_CMD_CTX_SP(sp);
744
745 if (sp->flags & SRB_DMA_VALID) {
746 scsi_dma_unmap(cmd);
747 sp->flags &= ~SRB_DMA_VALID;
748 }
749
750 if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
751 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
752 scsi_prot_sg_count(cmd), cmd->sc_data_direction);
753 sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
754 }
755
d5ff0eed 756 if (!ctx)
711a08d7 757 return;
d5ff0eed 758
d7459527
MH		 759 if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
760 /* List assured to be having elements */
d5ff0eed 761 qla2x00_clean_dsd_pool(ha, ctx);
d7459527
MH		 762 sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
763 }
764
765 if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
d5ff0eed
JC		 766 struct crc_context *ctx0 = ctx;
767
768 dma_pool_free(ha->dl_dma_pool, ctx, ctx0->crc_ctx_dma);
d7459527
MH		 769 sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
770 }
771
772 if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
d5ff0eed 773 struct ct6_dsd *ctx1 = ctx;
d7459527
MH		 774 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd,
775 ctx1->fcp_cmnd_dma);
776 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list);
777 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt;
778 ha->gbl_dsd_avail += ctx1->dsd_use_cnt;
779 mempool_free(ctx1, ha->ctx_mempool);
50b81275
GM		 780 sp->flags &= ~SRB_FCP_CMND_DMA_VALID;
781 }
782 if (sp->flags & SRB_DIF_BUNDL_DMA_VALID) {
783 struct crc_context *difctx = sp->u.scmd.ctx;
784 struct dsd_dma *dif_dsd, *nxt_dsd;
785
786 list_for_each_entry_safe(dif_dsd, nxt_dsd,
787 &difctx->ldif_dma_hndl_list, list) {
788 list_del(&dif_dsd->list);
789 dma_pool_free(ha->dif_bundl_pool, dif_dsd->dsd_addr,
790 dif_dsd->dsd_list_dma);
791 kfree(dif_dsd);
792 difctx->no_dif_bundl--;
793 }
794
795 list_for_each_entry_safe(dif_dsd, nxt_dsd,
796 &difctx->ldif_dsd_list, list) {
797 list_del(&dif_dsd->list);
798 dma_pool_free(ha->dl_dma_pool, dif_dsd->dsd_addr,
799 dif_dsd->dsd_list_dma);
800 kfree(dif_dsd);
801 difctx->no_ldif_dsd--;
802 }
803
804 if (difctx->no_ldif_dsd) {
805 ql_dbg(ql_dbg_tgt+ql_dbg_verbose, sp->vha, 0xe022,
806 "%s: difctx->no_ldif_dsd=%x\n",
807 __func__, difctx->no_ldif_dsd);
808 }
809
810 if (difctx->no_dif_bundl) {
811 ql_dbg(ql_dbg_tgt+ql_dbg_verbose, sp->vha, 0xe022,
812 "%s: difctx->no_dif_bundl=%x\n",
813 __func__, difctx->no_dif_bundl);
814 }
815 sp->flags &= ~SRB_DIF_BUNDL_DMA_VALID;
d7459527 816 }
d7459527
MH		 817}
818
819void
25ff6af1 820qla2xxx_qpair_sp_compl(void *ptr, int res)
d7459527 821{
25ff6af1 822 srb_t *sp = ptr;
d7459527 823 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
711a08d7 824 wait_queue_head_t *cwaitq = sp->cwaitq;
d7459527
MH		 825
826 if (atomic_read(&sp->ref_count) == 0) {
827 ql_dbg(ql_dbg_io, sp->fcport->vha, 0x3079,
828 "SP reference-count to ZERO -- sp=%p cmd=%p.\n",
829 sp, GET_CMD_SP(sp));
830 if (ql2xextended_error_logging & ql_dbg_io)
831 WARN_ON(atomic_read(&sp->ref_count) == 0);
832 return;
833 }
834 if (!atomic_dec_and_test(&sp->ref_count))
835 return;
836
f3caa990 837 sp->free(sp);
711a08d7
GM		 838 cmd->result = res;
839 CMD_SP(cmd) = NULL;
d7459527 840 cmd->scsi_done(cmd);
711a08d7
GM		 841 if (cwaitq)
842 wake_up(cwaitq);
843 qla2xxx_rel_qpair_sp(sp->qpair, sp);
d7459527
MH		 844}
845
1da177e4 846static int
f5e3e40b 847qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
fca29703 848{
134ae078 849 scsi_qla_host_t *vha = shost_priv(host);
fca29703 850 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
19a7b4ae 851 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
e315cd28
AC		 852 struct qla_hw_data *ha = vha->hw;
853 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
fca29703
AV		 854 srb_t *sp;
855 int rval;
5601236b
MH		 856 struct qla_qpair *qpair = NULL;
857 uint32_t tag;
858 uint16_t hwq;
fca29703 859
04dfaa53
MFO		 860 if (unlikely(test_bit(UNLOADING, &base_vha->dpc_flags))) {
861 cmd->result = DID_NO_CONNECT << 16;
862 goto qc24_fail_command;
863 }
864
5601236b 865 if (ha->mqenable) {
f664a3cc
JA		 866 tag = blk_mq_unique_tag(cmd->request);
867 hwq = blk_mq_unique_tag_to_hwq(tag);
868 qpair = ha->queue_pair_map[hwq];
5601236b
MH		 869
870 if (qpair)
871 return qla2xxx_mqueuecommand(host, cmd, qpair);
d7459527
MH		 872 }
873
85880801 874 if (ha->flags.eeh_busy) {
7c3df132 875 if (ha->flags.pci_channel_io_perm_failure) {
5f28d2d7 876 ql_dbg(ql_dbg_aer, vha, 0x9010,
7c3df132
SK		 877 "PCI Channel IO permanent failure, exiting "
878 "cmd=%p.\n", cmd);
b9b12f73 879 cmd->result = DID_NO_CONNECT << 16;
7c3df132 880 } else {
5f28d2d7 881 ql_dbg(ql_dbg_aer, vha, 0x9011,
7c3df132 882 "EEH_Busy, Requeuing the cmd=%p.\n", cmd);
85880801 883 cmd->result = DID_REQUEUE << 16;
7c3df132 884 }
14e660e6
SJ		 885 goto qc24_fail_command;
886 }
887
19a7b4ae
JSEC		 888 rval = fc_remote_port_chkready(rport);
889 if (rval) {
890 cmd->result = rval;
5f28d2d7 891 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3003,
7c3df132
SK		 892 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
893 cmd, rval);
fca29703
AV		 894 goto qc24_fail_command;
895 }
896
bad75002
AE		 897 if (!vha->flags.difdix_supported &&
898 scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) {
7c3df132
SK		 899 ql_dbg(ql_dbg_io, vha, 0x3004,
900 "DIF Cap not reg, fail DIF capable cmd's:%p.\n",
901 cmd);
bad75002
AE		 902 cmd->result = DID_NO_CONNECT << 16;
903 goto qc24_fail_command;
904 }
aa651be8
CD		 905
906 if (!fcport) {
907 cmd->result = DID_NO_CONNECT << 16;
908 goto qc24_fail_command;
909 }
910
fca29703
AV		 911 if (atomic_read(&fcport->state) != FCS_ONLINE) {
912 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
38170fa8 913 atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
7c3df132
SK		 914 ql_dbg(ql_dbg_io, vha, 0x3005,
915 "Returning DNC, fcport_state=%d loop_state=%d.\n",
916 atomic_read(&fcport->state),
917 atomic_read(&base_vha->loop_state));
fca29703
AV		 918 cmd->result = DID_NO_CONNECT << 16;
919 goto qc24_fail_command;
920 }
7b594131 921 goto qc24_target_busy;
fca29703
AV		 922 }
923
e05fe292
CD		 924 /*
925 * Return target busy if we've received a non-zero retry_delay_timer
926 * in a FCP_RSP.
927 */
975f7d46
BP		 928 if (fcport->retry_delay_timestamp == 0) {
929 /* retry delay not set */
930 } else if (time_after(jiffies, fcport->retry_delay_timestamp))
e05fe292
CD		 931 fcport->retry_delay_timestamp = 0;
932 else
933 goto qc24_target_busy;
934
b00ee7d7 935 sp = qla2x00_get_sp(vha, fcport, GFP_ATOMIC);
50280c01 936 if (!sp)
f5e3e40b 937 goto qc24_host_busy;
fca29703 938
9ba56b95
GM		 939 sp->u.scmd.cmd = cmd;
940 sp->type = SRB_SCSI_CMD;
941 atomic_set(&sp->ref_count, 1);
942 CMD_SP(cmd) = (void *)sp;
943 sp->free = qla2x00_sp_free_dma;
944 sp->done = qla2x00_sp_compl;
945
e315cd28 946 rval = ha->isp_ops->start_scsi(sp);
7c3df132 947 if (rval != QLA_SUCCESS) {
53016ed3 948 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3013,
7c3df132 949 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
fca29703 950 goto qc24_host_busy_free_sp;
7c3df132 951 }
fca29703 952
fca29703
AV		 953 return 0;
954
955qc24_host_busy_free_sp:
f3caa990 956 sp->free(sp);
fca29703 957
f5e3e40b 958qc24_host_busy:
fca29703
AV		 959 return SCSI_MLQUEUE_HOST_BUSY;
960
7b594131
MC		 961qc24_target_busy:
962 return SCSI_MLQUEUE_TARGET_BUSY;
963
fca29703 964qc24_fail_command:
f5e3e40b 965 cmd->scsi_done(cmd);
fca29703
AV		 966
967 return 0;
968}
969
d7459527
MH		 970/* For MQ supported I/O */
971int
972qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd,
973 struct qla_qpair *qpair)
974{
975 scsi_qla_host_t *vha = shost_priv(host);
976 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
977 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
978 struct qla_hw_data *ha = vha->hw;
979 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
980 srb_t *sp;
981 int rval;
982
983 rval = fc_remote_port_chkready(rport);
984 if (rval) {
985 cmd->result = rval;
986 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3076,
987 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
988 cmd, rval);
989 goto qc24_fail_command;
990 }
991
992 if (!fcport) {
993 cmd->result = DID_NO_CONNECT << 16;
994 goto qc24_fail_command;
995 }
996
997 if (atomic_read(&fcport->state) != FCS_ONLINE) {
998 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
999 atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
1000 ql_dbg(ql_dbg_io, vha, 0x3077,
1001 "Returning DNC, fcport_state=%d loop_state=%d.\n",
1002 atomic_read(&fcport->state),
1003 atomic_read(&base_vha->loop_state));
1004 cmd->result = DID_NO_CONNECT << 16;
1005 goto qc24_fail_command;
1006 }
1007 goto qc24_target_busy;
1008 }
1009
1010 /*
1011 * Return target busy if we've received a non-zero retry_delay_timer
1012 * in a FCP_RSP.
1013 */
1014 if (fcport->retry_delay_timestamp == 0) {
1015 /* retry delay not set */
1016 } else if (time_after(jiffies, fcport->retry_delay_timestamp))
1017 fcport->retry_delay_timestamp = 0;
1018 else
1019 goto qc24_target_busy;
1020
6a629468 1021 sp = qla2xxx_get_qpair_sp(vha, qpair, fcport, GFP_ATOMIC);
d7459527
MH		 1022 if (!sp)
1023 goto qc24_host_busy;
1024
1025 sp->u.scmd.cmd = cmd;
1026 sp->type = SRB_SCSI_CMD;
1027 atomic_set(&sp->ref_count, 1);
1028 CMD_SP(cmd) = (void *)sp;
1029 sp->free = qla2xxx_qpair_sp_free_dma;
1030 sp->done = qla2xxx_qpair_sp_compl;
1031 sp->qpair = qpair;
1032
1033 rval = ha->isp_ops->start_scsi_mq(sp);
1034 if (rval != QLA_SUCCESS) {
1035 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3078,
1036 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
1037 if (rval == QLA_INTERFACE_ERROR)
1038 goto qc24_fail_command;
1039 goto qc24_host_busy_free_sp;
1040 }
1041
1042 return 0;
1043
1044qc24_host_busy_free_sp:
f3caa990 1045 sp->free(sp);
d7459527
MH		 1046
1047qc24_host_busy:
1048 return SCSI_MLQUEUE_HOST_BUSY;
1049
1050qc24_target_busy:
1051 return SCSI_MLQUEUE_TARGET_BUSY;
1052
1053qc24_fail_command:
1054 cmd->scsi_done(cmd);
1055
1056 return 0;
1057}
1058
1da177e4
LT		 1059/*
1060 * qla2x00_eh_wait_on_command
1061 * Waits for the command to be returned by the Firmware for some
1062 * max time.
1063 *
1064 * Input:
1da177e4 1065 * cmd = Scsi Command to wait on.
1da177e4
LT		 1066 *
1067 * Return:
1068 * Not Found : 0
1069 * Found : 1
1070 */
1071static int
e315cd28 1072qla2x00_eh_wait_on_command(struct scsi_cmnd *cmd)
1da177e4 1073{
fe74c71f 1074#define ABORT_POLLING_PERIOD 1000
478c3b03 1075#define ABORT_WAIT_ITER ((2 * 1000) / (ABORT_POLLING_PERIOD))
f4f051eb 1076 unsigned long wait_iter = ABORT_WAIT_ITER;
85880801
AV		 1077 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1078 struct qla_hw_data *ha = vha->hw;
f4f051eb 1079 int ret = QLA_SUCCESS;
1da177e4 1080
85880801 1081 if (unlikely(pci_channel_offline(ha->pdev)) || ha->flags.eeh_busy) {
7c3df132
SK		 1082 ql_dbg(ql_dbg_taskm, vha, 0x8005,
1083 "Return:eh_wait.\n");
85880801
AV		 1084 return ret;
1085 }
1086
d970432c 1087 while (CMD_SP(cmd) && wait_iter--) {
fe74c71f 1088 msleep(ABORT_POLLING_PERIOD);
f4f051eb 1089 }
1090 if (CMD_SP(cmd))
1091 ret = QLA_FUNCTION_FAILED;
1da177e4 1092
f4f051eb 1093 return ret;
1da177e4
LT		 1094}
1095
1096/*
1097 * qla2x00_wait_for_hba_online
fa2a1ce5 1098 * Wait till the HBA is online after going through
1da177e4
LT		 1099 * <= MAX_RETRIES_OF_ISP_ABORT or
1100 * finally HBA is disabled ie marked offline
1101 *
1102 * Input:
1103 * ha - pointer to host adapter structure
fa2a1ce5
AV		 1104 *
1105 * Note:
1da177e4
LT		 1106 * Does context switching-Release SPIN_LOCK
1107 * (if any) before calling this routine.
1108 *
1109 * Return:
1110 * Success (Adapter is online) : 0
1111 * Failed (Adapter is offline/disabled) : 1
1112 */
854165f4 1113int
e315cd28 1114qla2x00_wait_for_hba_online(scsi_qla_host_t *vha)
1da177e4 1115{
fca29703
AV		 1116 int return_status;
1117 unsigned long wait_online;
e315cd28
AC		 1118 struct qla_hw_data *ha = vha->hw;
1119 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4 1120
fa2a1ce5 1121 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ);
e315cd28
AC		 1122 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
1123 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
1124 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
1125 ha->dpc_active) && time_before(jiffies, wait_online)) {
1da177e4
LT		 1126
1127 msleep(1000);
1128 }
e315cd28 1129 if (base_vha->flags.online)
fa2a1ce5 1130 return_status = QLA_SUCCESS;
1da177e4
LT		 1131 else
1132 return_status = QLA_FUNCTION_FAILED;
1133
1da177e4
LT		 1134 return (return_status);
1135}
1136
726b8548
QT		 1137static inline int test_fcport_count(scsi_qla_host_t *vha)
1138{
1139 struct qla_hw_data *ha = vha->hw;
1140 unsigned long flags;
1141 int res;
1142
1143 spin_lock_irqsave(&ha->tgt.sess_lock, flags);
83548fe2
QT		 1144 ql_dbg(ql_dbg_init, vha, 0x00ec,
1145 "tgt %p, fcport_count=%d\n",
1146 vha, vha->fcport_count);
726b8548
QT		 1147 res = (vha->fcport_count == 0);
1148 spin_unlock_irqrestore(&ha->tgt.sess_lock, flags);
1149
1150 return res;
1151}
1152
1153/*
1154 * qla2x00_wait_for_sess_deletion can only be called from remove_one.
1155 * it has dependency on UNLOADING flag to stop device discovery
1156 */
efa93f48 1157void
726b8548
QT		 1158qla2x00_wait_for_sess_deletion(scsi_qla_host_t *vha)
1159{
1160 qla2x00_mark_all_devices_lost(vha, 0);
1161
b85e0957 1162 wait_event_timeout(vha->fcport_waitQ, test_fcport_count(vha), 10*HZ);
726b8548
QT		 1163}
1164
86fbee86 1165/*
638a1a01
SC		 1166 * qla2x00_wait_for_hba_ready
1167 * Wait till the HBA is ready before doing driver unload
86fbee86
LC		 1168 *
1169 * Input:
1170 * ha - pointer to host adapter structure
1171 *
1172 * Note:
1173 * Does context switching-Release SPIN_LOCK
1174 * (if any) before calling this routine.
1175 *
86fbee86 1176 */
638a1a01
SC		 1177static void
1178qla2x00_wait_for_hba_ready(scsi_qla_host_t *vha)
86fbee86 1179{
86fbee86 1180 struct qla_hw_data *ha = vha->hw;
783e0dc4 1181 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
86fbee86 1182
1d483901
DC		 1183 while ((qla2x00_reset_active(vha) || ha->dpc_active ||
1184 ha->flags.mbox_busy) ||
1185 test_bit(FX00_RESET_RECOVERY, &vha->dpc_flags) ||
1186 test_bit(FX00_TARGET_SCAN, &vha->dpc_flags)) {
1187 if (test_bit(UNLOADING, &base_vha->dpc_flags))
1188 break;
86fbee86 1189 msleep(1000);
783e0dc4 1190 }
86fbee86
LC		 1191}
1192
2533cf67
LC		 1193int
1194qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha)
1195{
1196 int return_status;
1197 unsigned long wait_reset;
1198 struct qla_hw_data *ha = vha->hw;
1199 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1200
1201 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ);
1202 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
1203 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
1204 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
1205 ha->dpc_active) && time_before(jiffies, wait_reset)) {
1206
1207 msleep(1000);
1208
1209 if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) &&
1210 ha->flags.chip_reset_done)
1211 break;
1212 }
1213 if (ha->flags.chip_reset_done)
1214 return_status = QLA_SUCCESS;
1215 else
1216 return_status = QLA_FUNCTION_FAILED;
1217
1218 return return_status;
1219}
1220
585def9b 1221static int
083a469d
GM		 1222sp_get(struct srb *sp)
1223{
585def9b
QT		 1224 if (!refcount_inc_not_zero((refcount_t*)&sp->ref_count))
1225 /* kref get fail */
1226 return ENXIO;
1227 else
1228 return 0;
083a469d
GM		 1229}
1230
a465537a
SC		 1231#define ISP_REG_DISCONNECT 0xffffffffU
1232/**************************************************************************
1233* qla2x00_isp_reg_stat
1234*
1235* Description:
1236* Read the host status register of ISP before aborting the command.
1237*
1238* Input:
1239* ha = pointer to host adapter structure.
1240*
1241*
1242* Returns:
1243* Either true or false.
1244*
1245* Note: Return true if there is register disconnect.
1246**************************************************************************/
1247static inline
1248uint32_t qla2x00_isp_reg_stat(struct qla_hw_data *ha)
1249{
1250 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
bf6061b1 1251 struct device_reg_82xx __iomem *reg82 = &ha->iobase->isp82;
a465537a 1252
bf6061b1
SC		 1253 if (IS_P3P_TYPE(ha))
1254 return ((RD_REG_DWORD(&reg82->host_int)) == ISP_REG_DISCONNECT);
1255 else
1256 return ((RD_REG_DWORD(&reg->host_status)) ==
1257 ISP_REG_DISCONNECT);
a465537a
SC		 1258}
1259
1da177e4
LT		 1260/**************************************************************************
1261* qla2xxx_eh_abort
1262*
1263* Description:
1264* The abort function will abort the specified command.
1265*
1266* Input:
1267* cmd = Linux SCSI command packet to be aborted.
1268*
1269* Returns:
1270* Either SUCCESS or FAILED.
1271*
1272* Note:
2ea00202 1273* Only return FAILED if command not returned by firmware.
1da177e4 1274**************************************************************************/
e5f82ab8 1275static int
1da177e4
LT		 1276qla2xxx_eh_abort(struct scsi_cmnd *cmd)
1277{
e315cd28 1278 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
f4f051eb 1279 srb_t *sp;
4e98d3b8 1280 int ret;
9cb78c16
HR		 1281 unsigned int id;
1282 uint64_t lun;
18e144d3 1283 unsigned long flags;
f934c9d0 1284 int rval, wait = 0;
e315cd28 1285 struct qla_hw_data *ha = vha->hw;
585def9b 1286 struct qla_qpair *qpair;
1da177e4 1287
a465537a
SC		 1288 if (qla2x00_isp_reg_stat(ha)) {
1289 ql_log(ql_log_info, vha, 0x8042,
1290 "PCI/Register disconnect, exiting.\n");
1291 return FAILED;
1292 }
1da177e4 1293
4e98d3b8
AV		 1294 ret = fc_block_scsi_eh(cmd);
1295 if (ret != 0)
1296 return ret;
1297 ret = SUCCESS;
1298
170babc3 1299 sp = (srb_t *) CMD_SP(cmd);
585def9b
QT		 1300 if (!sp)
1301 return SUCCESS;
1302
1303 qpair = sp->qpair;
1304 if (!qpair)
1305 return SUCCESS;
1306
1307 spin_lock_irqsave(qpair->qp_lock_ptr, flags);
1308 if (!CMD_SP(cmd)) {
1309 /* there's a chance an interrupt could clear
1310 the ptr as part of done & free */
1311 spin_unlock_irqrestore(qpair->qp_lock_ptr, flags);
170babc3
MC		 1312 return SUCCESS;
1313 }
1da177e4 1314
585def9b
QT		 1315 if (sp_get(sp)){
1316 /* ref_count is already 0 */
1317 spin_unlock_irqrestore(qpair->qp_lock_ptr, flags);
170babc3
MC		 1318 return SUCCESS;
1319 }
585def9b
QT		 1320 spin_unlock_irqrestore(qpair->qp_lock_ptr, flags);
1321
1322 id = cmd->device->id;
1323 lun = cmd->device->lun;
1da177e4 1324
7c3df132 1325 ql_dbg(ql_dbg_taskm, vha, 0x8002,
c7bc4cae
CD		 1326 "Aborting from RISC nexus=%ld:%d:%llu sp=%p cmd=%p handle=%x\n",
1327 vha->host_no, id, lun, sp, cmd, sp->handle);
17d98630 1328
170babc3 1329 /* Get a reference to the sp and drop the lock.*/
f934c9d0
CD		 1330 rval = ha->isp_ops->abort_command(sp);
1331 if (rval) {
96219424 1332 if (rval == QLA_FUNCTION_PARAMETER_ERROR)
f934c9d0 1333 ret = SUCCESS;
96219424 1334 else
f934c9d0
CD		 1335 ret = FAILED;
1336
7c3df132 1337 ql_dbg(ql_dbg_taskm, vha, 0x8003,
f934c9d0 1338 "Abort command mbx failed cmd=%p, rval=%x.\n", cmd, rval);
170babc3 1339 } else {
7c3df132 1340 ql_dbg(ql_dbg_taskm, vha, 0x8004,
cfb0919c 1341 "Abort command mbx success cmd=%p.\n", cmd);
170babc3
MC		 1342 wait = 1;
1343 }
75942064 1344
585def9b 1345 spin_lock_irqsave(qpair->qp_lock_ptr, flags);
585def9b
QT		 1346
1347 /*
711a08d7
GM		 1348 * Releasing of the SRB and associated command resources
1349 * is managed through ref_count.
1350 * Whether we need to wait for the abort completion or complete
1351 * the abort handler should be based on the ref_count.
585def9b 1352 */
711a08d7
GM		 1353 if (atomic_read(&sp->ref_count) > 1) {
1354 /*
1355 * The command is not yet completed. We need to wait for either
1356 * command completion or abort completion.
1357 */
1358 DECLARE_WAIT_QUEUE_HEAD_ONSTACK(eh_waitq);
1359 uint32_t ratov = ha->r_a_tov/10;
1360
1361 /* Go ahead and release the extra ref_count obtained earlier */
1362 sp->done(sp, DID_RESET << 16);
1363 sp->cwaitq = &eh_waitq;
1364
1365 if (!wait_event_lock_irq_timeout(eh_waitq,
1366 CMD_SP(cmd) == NULL, *qpair->qp_lock_ptr,
1367 msecs_to_jiffies(4 * ratov * 1000))) {
1368 /*
1369 * The abort got dropped, LOGO will be sent and the
1370 * original command will be completed with CS_TIMEOUT
1371 * completion
1372 */
1373 ql_dbg(ql_dbg_taskm, vha, 0xffff,
1374 "%s: Abort wait timer (4 * R_A_TOV[%d]) expired\n",
1375 __func__, ha->r_a_tov);
1376 sp->cwaitq = NULL;
2ea00202 1377 ret = FAILED;
711a08d7 1378 goto end;
f4f051eb 1379 }
711a08d7
GM		 1380 } else {
1381 /* Command completed while processing the abort */
1382 sp->done(sp, DID_RESET << 16);
1da177e4 1383 }
711a08d7
GM		 1384end:
1385 spin_unlock_irqrestore(qpair->qp_lock_ptr, flags);
7c3df132 1386 ql_log(ql_log_info, vha, 0x801c,
9cb78c16 1387 "Abort command issued nexus=%ld:%d:%llu -- %d %x.\n",
cfb0919c 1388 vha->host_no, id, lun, wait, ret);
1da177e4 1389
f4f051eb 1390 return ret;
1391}
1da177e4 1392
4d78c973 1393int
e315cd28 1394qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t,
9cb78c16 1395 uint64_t l, enum nexus_wait_type type)
f4f051eb 1396{
17d98630 1397 int cnt, match, status;
18e144d3 1398 unsigned long flags;
e315cd28 1399 struct qla_hw_data *ha = vha->hw;
73208dfd 1400 struct req_que *req;
4d78c973 1401 srb_t *sp;
9ba56b95 1402 struct scsi_cmnd *cmd;
1da177e4 1403
523ec773 1404 status = QLA_SUCCESS;
17d98630 1405
e315cd28 1406 spin_lock_irqsave(&ha->hardware_lock, flags);
67c2e93a 1407 req = vha->req;
17d98630 1408 for (cnt = 1; status == QLA_SUCCESS &&
8d93f550 1409 cnt < req->num_outstanding_cmds; cnt++) {
17d98630
AC		 1410 sp = req->outstanding_cmds[cnt];
1411 if (!sp)
523ec773 1412 continue;
9ba56b95 1413 if (sp->type != SRB_SCSI_CMD)
cf53b069 1414 continue;
25ff6af1 1415 if (vha->vp_idx != sp->vha->vp_idx)
17d98630
AC		 1416 continue;
1417 match = 0;
9ba56b95 1418 cmd = GET_CMD_SP(sp);
17d98630
AC		 1419 switch (type) {
1420 case WAIT_HOST:
1421 match = 1;
1422 break;
1423 case WAIT_TARGET:
9ba56b95 1424 match = cmd->device->id == t;
17d98630
AC		 1425 break;
1426 case WAIT_LUN:
9ba56b95
GM		 1427 match = (cmd->device->id == t &&
1428 cmd->device->lun == l);
17d98630 1429 break;
73208dfd 1430 }
17d98630
AC		 1431 if (!match)
1432 continue;
1433
1434 spin_unlock_irqrestore(&ha->hardware_lock, flags);
9ba56b95 1435 status = qla2x00_eh_wait_on_command(cmd);
17d98630 1436 spin_lock_irqsave(&ha->hardware_lock, flags);
1da177e4 1437 }
e315cd28 1438 spin_unlock_irqrestore(&ha->hardware_lock, flags);
523ec773
AV		 1439
1440 return status;
1da177e4
LT		 1441}
1442
523ec773
AV		 1443static char *reset_errors[] = {
1444 "HBA not online",
1445 "HBA not ready",
1446 "Task management failed",
1447 "Waiting for command completions",
1448};
1da177e4 1449
e5f82ab8 1450static int
523ec773 1451__qla2xxx_eh_generic_reset(char *name, enum nexus_wait_type type,
9cb78c16 1452 struct scsi_cmnd *cmd, int (*do_reset)(struct fc_port *, uint64_t, int))
1da177e4 1453{
e315cd28 1454 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
bdf79621 1455 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
523ec773 1456 int err;
1da177e4 1457
7c3df132 1458 if (!fcport) {
523ec773 1459 return FAILED;
7c3df132 1460 }
1da177e4 1461
4e98d3b8
AV		 1462 err = fc_block_scsi_eh(cmd);
1463 if (err != 0)
1464 return err;
1465
7c3df132 1466 ql_log(ql_log_info, vha, 0x8009,
9cb78c16 1467 "%s RESET ISSUED nexus=%ld:%d:%llu cmd=%p.\n", name, vha->host_no,
7c3df132 1468 cmd->device->id, cmd->device->lun, cmd);
1da177e4 1469
523ec773 1470 err = 0;
7c3df132
SK		 1471 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1472 ql_log(ql_log_warn, vha, 0x800a,
1473 "Wait for hba online failed for cmd=%p.\n", cmd);
523ec773 1474 goto eh_reset_failed;
7c3df132 1475 }
523ec773 1476 err = 2;
ac444b4f 1477 if (do_reset(fcport, cmd->device->lun, 1)
7c3df132
SK		 1478 != QLA_SUCCESS) {
1479 ql_log(ql_log_warn, vha, 0x800c,
1480 "do_reset failed for cmd=%p.\n", cmd);
523ec773 1481 goto eh_reset_failed;
7c3df132 1482 }
523ec773 1483 err = 3;
e315cd28 1484 if (qla2x00_eh_wait_for_pending_commands(vha, cmd->device->id,
7c3df132
SK		 1485 cmd->device->lun, type) != QLA_SUCCESS) {
1486 ql_log(ql_log_warn, vha, 0x800d,
d6a03581 1487 "wait for pending cmds failed for cmd=%p.\n", cmd);
523ec773 1488 goto eh_reset_failed;
7c3df132 1489 }
523ec773 1490
7c3df132 1491 ql_log(ql_log_info, vha, 0x800e,
9cb78c16 1492 "%s RESET SUCCEEDED nexus:%ld:%d:%llu cmd=%p.\n", name,
cfb0919c 1493 vha->host_no, cmd->device->id, cmd->device->lun, cmd);
523ec773
AV		 1494
1495 return SUCCESS;
1496
4d78c973 1497eh_reset_failed:
7c3df132 1498 ql_log(ql_log_info, vha, 0x800f,
9cb78c16 1499 "%s RESET FAILED: %s nexus=%ld:%d:%llu cmd=%p.\n", name,
cfb0919c
CD		 1500 reset_errors[err], vha->host_no, cmd->device->id, cmd->device->lun,
1501 cmd);
523ec773
AV		 1502 return FAILED;
1503}
1da177e4 1504
523ec773
AV		 1505static int
1506qla2xxx_eh_device_reset(struct scsi_cmnd *cmd)
1507{
e315cd28
AC		 1508 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1509 struct qla_hw_data *ha = vha->hw;
1da177e4 1510
a465537a
SC		 1511 if (qla2x00_isp_reg_stat(ha)) {
1512 ql_log(ql_log_info, vha, 0x803e,
1513 "PCI/Register disconnect, exiting.\n");
1514 return FAILED;
1515 }
1516
523ec773
AV		 1517 return __qla2xxx_eh_generic_reset("DEVICE", WAIT_LUN, cmd,
1518 ha->isp_ops->lun_reset);
1da177e4
LT		 1519}
1520
1da177e4 1521static int
523ec773 1522qla2xxx_eh_target_reset(struct scsi_cmnd *cmd)
1da177e4 1523{
e315cd28
AC		 1524 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1525 struct qla_hw_data *ha = vha->hw;
1da177e4 1526
a465537a
SC		 1527 if (qla2x00_isp_reg_stat(ha)) {
1528 ql_log(ql_log_info, vha, 0x803f,
1529 "PCI/Register disconnect, exiting.\n");
1530 return FAILED;
1531 }
1532
523ec773
AV		 1533 return __qla2xxx_eh_generic_reset("TARGET", WAIT_TARGET, cmd,
1534 ha->isp_ops->target_reset);
1da177e4
LT		 1535}
1536
1da177e4
LT		 1537/**************************************************************************
1538* qla2xxx_eh_bus_reset
1539*
1540* Description:
1541* The bus reset function will reset the bus and abort any executing
1542* commands.
1543*
1544* Input:
1545* cmd = Linux SCSI command packet of the command that cause the
1546* bus reset.
1547*
1548* Returns:
1549* SUCCESS/FAILURE (defined as macro in scsi.h).
1550*
1551**************************************************************************/
e5f82ab8 1552static int
1da177e4
LT		 1553qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd)
1554{
e315cd28 1555 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
bdf79621 1556 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
2c3dfe3f 1557 int ret = FAILED;
9cb78c16
HR		 1558 unsigned int id;
1559 uint64_t lun;
a465537a
SC		 1560 struct qla_hw_data *ha = vha->hw;
1561
1562 if (qla2x00_isp_reg_stat(ha)) {
1563 ql_log(ql_log_info, vha, 0x8040,
1564 "PCI/Register disconnect, exiting.\n");
1565 return FAILED;
1566 }
f4f051eb 1567
f4f051eb 1568 id = cmd->device->id;
1569 lun = cmd->device->lun;
1da177e4 1570
7c3df132 1571 if (!fcport) {
f4f051eb 1572 return ret;
7c3df132 1573 }
1da177e4 1574
4e98d3b8
AV		 1575 ret = fc_block_scsi_eh(cmd);
1576 if (ret != 0)
1577 return ret;
1578 ret = FAILED;
1579
7c3df132 1580 ql_log(ql_log_info, vha, 0x8012,
9cb78c16 1581 "BUS RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun);
1da177e4 1582
e315cd28 1583 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
7c3df132
SK		 1584 ql_log(ql_log_fatal, vha, 0x8013,
1585 "Wait for hba online failed board disabled.\n");
f4f051eb 1586 goto eh_bus_reset_done;
1da177e4
LT		 1587 }
1588
ad537689
SK		 1589 if (qla2x00_loop_reset(vha) == QLA_SUCCESS)
1590 ret = SUCCESS;
1591
f4f051eb 1592 if (ret == FAILED)
1593 goto eh_bus_reset_done;
1da177e4 1594
9a41a62b 1595 /* Flush outstanding commands. */
4d78c973 1596 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) !=
7c3df132
SK		 1597 QLA_SUCCESS) {
1598 ql_log(ql_log_warn, vha, 0x8014,
1599 "Wait for pending commands failed.\n");
9a41a62b 1600 ret = FAILED;
7c3df132 1601 }
1da177e4 1602
f4f051eb 1603eh_bus_reset_done:
7c3df132 1604 ql_log(ql_log_warn, vha, 0x802b,
9cb78c16 1605 "BUS RESET %s nexus=%ld:%d:%llu.\n",
d6a03581 1606 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1da177e4 1607
f4f051eb 1608 return ret;
1da177e4
LT		 1609}
1610
1611/**************************************************************************
1612* qla2xxx_eh_host_reset
1613*
1614* Description:
1615* The reset function will reset the Adapter.
1616*
1617* Input:
1618* cmd = Linux SCSI command packet of the command that cause the
1619* adapter reset.
1620*
1621* Returns:
1622* Either SUCCESS or FAILED.
1623*
1624* Note:
1625**************************************************************************/
e5f82ab8 1626static int
1da177e4
LT		 1627qla2xxx_eh_host_reset(struct scsi_cmnd *cmd)
1628{
e315cd28 1629 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
e315cd28 1630 struct qla_hw_data *ha = vha->hw;
2c3dfe3f 1631 int ret = FAILED;
9cb78c16
HR		 1632 unsigned int id;
1633 uint64_t lun;
e315cd28 1634 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4 1635
a465537a
SC		 1636 if (qla2x00_isp_reg_stat(ha)) {
1637 ql_log(ql_log_info, vha, 0x8041,
1638 "PCI/Register disconnect, exiting.\n");
1639 schedule_work(&ha->board_disable);
1640 return SUCCESS;
1641 }
1642
f4f051eb 1643 id = cmd->device->id;
1644 lun = cmd->device->lun;
f4f051eb 1645
7c3df132 1646 ql_log(ql_log_info, vha, 0x8018,
9cb78c16 1647 "ADAPTER RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun);
1da177e4 1648
63ee7072
CD		 1649 /*
1650 * No point in issuing another reset if one is active. Also do not
1651 * attempt a reset if we are updating flash.
1652 */
1653 if (qla2x00_reset_active(vha) || ha->optrom_state != QLA_SWAITING)
f4f051eb 1654 goto eh_host_reset_lock;
1da177e4 1655
e315cd28
AC		 1656 if (vha != base_vha) {
1657 if (qla2x00_vp_abort_isp(vha))
f4f051eb 1658 goto eh_host_reset_lock;
e315cd28 1659 } else {
7ec0effd 1660 if (IS_P3P_TYPE(vha->hw)) {
a9083016
GM		 1661 if (!qla82xx_fcoe_ctx_reset(vha)) {
1662 /* Ctx reset success */
1663 ret = SUCCESS;
1664 goto eh_host_reset_lock;
1665 }
1666 /* fall thru if ctx reset failed */
1667 }
68ca949c
AC		 1668 if (ha->wq)
1669 flush_workqueue(ha->wq);
1670
e315cd28 1671 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
a9083016 1672 if (ha->isp_ops->abort_isp(base_vha)) {
e315cd28
AC		 1673 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1674 /* failed. schedule dpc to try */
1675 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
1676
7c3df132
SK		 1677 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1678 ql_log(ql_log_warn, vha, 0x802a,
1679 "wait for hba online failed.\n");
e315cd28 1680 goto eh_host_reset_lock;
7c3df132 1681 }
e315cd28
AC		 1682 }
1683 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
fa2a1ce5 1684 }
1da177e4 1685
e315cd28 1686 /* Waiting for command to be returned to OS.*/
4d78c973 1687 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) ==
e315cd28 1688 QLA_SUCCESS)
f4f051eb 1689 ret = SUCCESS;
1da177e4 1690
f4f051eb 1691eh_host_reset_lock:
cfb0919c 1692 ql_log(ql_log_info, vha, 0x8017,
9cb78c16 1693 "ADAPTER RESET %s nexus=%ld:%d:%llu.\n",
cfb0919c 1694 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1da177e4 1695
f4f051eb 1696 return ret;
1697}
1da177e4
LT		 1698
1699/*
1700* qla2x00_loop_reset
1701* Issue loop reset.
1702*
1703* Input:
1704* ha = adapter block pointer.
1705*
1706* Returns:
1707* 0 = success
1708*/
a4722cf2 1709int
e315cd28 1710qla2x00_loop_reset(scsi_qla_host_t *vha)
1da177e4 1711{
0c8c39af 1712 int ret;
bdf79621 1713 struct fc_port *fcport;
e315cd28 1714 struct qla_hw_data *ha = vha->hw;
1da177e4 1715
5854771e
AB		 1716 if (IS_QLAFX00(ha)) {
1717 return qlafx00_loop_reset(vha);
1718 }
1719
f4c496c1 1720 if (ql2xtargetreset == 1 && ha->flags.enable_target_reset) {
55e5ed27
AV		 1721 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1722 if (fcport->port_type != FCT_TARGET)
1723 continue;
1724
1725 ret = ha->isp_ops->target_reset(fcport, 0, 0);
1726 if (ret != QLA_SUCCESS) {
7c3df132 1727 ql_dbg(ql_dbg_taskm, vha, 0x802c,
5854771e 1728 "Bus Reset failed: Reset=%d "
7c3df132 1729 "d_id=%x.\n", ret, fcport->d_id.b24);
55e5ed27
AV		 1730 }
1731 }
1732 }
1733
8ae6d9c7 1734
6246b8a1 1735 if (ha->flags.enable_lip_full_login && !IS_CNA_CAPABLE(ha)) {
0b7e7c53
AV		 1736 atomic_set(&vha->loop_state, LOOP_DOWN);
1737 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
1738 qla2x00_mark_all_devices_lost(vha, 0);
e315cd28 1739 ret = qla2x00_full_login_lip(vha);
0c8c39af 1740 if (ret != QLA_SUCCESS) {
7c3df132
SK		 1741 ql_dbg(ql_dbg_taskm, vha, 0x802d,
1742 "full_login_lip=%d.\n", ret);
749af3d5 1743 }
0c8c39af
AV		 1744 }
1745
0d6e61bc 1746 if (ha->flags.enable_lip_reset) {
e315cd28 1747 ret = qla2x00_lip_reset(vha);
ad537689 1748 if (ret != QLA_SUCCESS)
7c3df132
SK		 1749 ql_dbg(ql_dbg_taskm, vha, 0x802e,
1750 "lip_reset failed (%d).\n", ret);
1da177e4
LT		 1751 }
1752
1da177e4 1753 /* Issue marker command only when we are going to start the I/O */
e315cd28 1754 vha->marker_needed = 1;
1da177e4 1755
0c8c39af 1756 return QLA_SUCCESS;
1da177e4
LT		 1757}
1758
c4e521b6
BVA		 1759static void qla2x00_abort_srb(struct qla_qpair *qp, srb_t *sp, const int res,
1760 unsigned long *flags)
1761 __releases(qp->qp_lock_ptr)
1762 __acquires(qp->qp_lock_ptr)
1763{
1764 scsi_qla_host_t *vha = qp->vha;
1765 struct qla_hw_data *ha = vha->hw;
1766
1767 if (sp->type == SRB_NVME_CMD || sp->type == SRB_NVME_LS) {
1768 if (!sp_get(sp)) {
1769 /* got sp */
1770 spin_unlock_irqrestore(qp->qp_lock_ptr, *flags);
1771 qla_nvme_abort(ha, sp, res);
1772 spin_lock_irqsave(qp->qp_lock_ptr, *flags);
1773 }
1774 } else if (GET_CMD_SP(sp) && !ha->flags.eeh_busy &&
1775 !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) &&
1776 !qla2x00_isp_reg_stat(ha) && sp->type == SRB_SCSI_CMD) {
1777 /*
1778 * Don't abort commands in adapter during EEH recovery as it's
1779 * not accessible/responding.
1780 *
1781 * Get a reference to the sp and drop the lock. The reference
1782 * ensures this sp->done() call and not the call in
1783 * qla2xxx_eh_abort() ends the SCSI cmd (with result 'res').
1784 */
1785 if (!sp_get(sp)) {
938edb8a
LT		 1786 int status;
1787
c4e521b6 1788 spin_unlock_irqrestore(qp->qp_lock_ptr, *flags);
938edb8a 1789 status = qla2xxx_eh_abort(GET_CMD_SP(sp));
c4e521b6 1790 spin_lock_irqsave(qp->qp_lock_ptr, *flags);
938edb8a
LT		 1791 /*
1792 * Get rid of extra reference caused
1793 * by early exit from qla2xxx_eh_abort
1794 */
1795 if (status == FAST_IO_FAIL)
1796 atomic_dec(&sp->ref_count);
c4e521b6
BVA		 1797 }
1798 }
1799 sp->done(sp, res);
1800}
1801
bbead493
QT		 1802static void
1803__qla2x00_abort_all_cmds(struct qla_qpair *qp, int res)
df4bf0bb 1804{
eb023220 1805 int cnt;
df4bf0bb
AV		 1806 unsigned long flags;
1807 srb_t *sp;
bbead493 1808 scsi_qla_host_t *vha = qp->vha;
e315cd28 1809 struct qla_hw_data *ha = vha->hw;
73208dfd 1810 struct req_que *req;
c5419e26
QT		 1811 struct qla_tgt *tgt = vha->vha_tgt.qla_tgt;
1812 struct qla_tgt_cmd *cmd;
c0cb4496 1813
6a2cf8d3
BK		 1814 if (!ha->req_q_map)
1815 return;
bbead493
QT		 1816 spin_lock_irqsave(qp->qp_lock_ptr, flags);
1817 req = qp->req;
1818 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) {
1819 sp = req->outstanding_cmds[cnt];
1820 if (sp) {
1821 req->outstanding_cmds[cnt] = NULL;
6b0431d6
QT		 1822 switch (sp->cmd_type) {
1823 case TYPE_SRB:
c4e521b6 1824 qla2x00_abort_srb(qp, sp, res, &flags);
585def9b
QT		 1825 break;
1826 case TYPE_TGT_CMD:
bbead493
QT		 1827 if (!vha->hw->tgt.tgt_ops || !tgt ||
1828 qla_ini_mode_enabled(vha)) {
585def9b
QT		 1829 ql_dbg(ql_dbg_tgt_mgt, vha, 0xf003,
1830 "HOST-ABORT-HNDLR: dpc_flags=%lx. Target mode disabled\n",
1831 vha->dpc_flags);
bbead493 1832 continue;
c733ab35 1833 }
bbead493
QT		 1834 cmd = (struct qla_tgt_cmd *)sp;
1835 qlt_abort_cmd_on_host_reset(cmd->vha, cmd);
585def9b
QT		 1836 break;
1837 case TYPE_TGT_TMCMD:
1838 /*
1839 * Currently, only ABTS response gets on the
1840 * outstanding_cmds[]
1841 */
1842 ha->tgt.tgt_ops->free_mcmd(
1843 (struct qla_tgt_mgmt_cmd *)sp);
1844 break;
1845 default:
1846 break;
73208dfd 1847 }
df4bf0bb
AV		 1848 }
1849 }
bbead493
QT		 1850 spin_unlock_irqrestore(qp->qp_lock_ptr, flags);
1851}
1852
1853void
1854qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res)
1855{
1856 int que;
1857 struct qla_hw_data *ha = vha->hw;
1858
1859 __qla2x00_abort_all_cmds(ha->base_qpair, res);
1860
1861 for (que = 0; que < ha->max_qpairs; que++) {
1862 if (!ha->queue_pair_map[que])
1863 continue;
1864
1865 __qla2x00_abort_all_cmds(ha->queue_pair_map[que], res);
1866 }
df4bf0bb
AV		 1867}
1868
f4f051eb 1869static int
1870qla2xxx_slave_alloc(struct scsi_device *sdev)
1da177e4 1871{
bdf79621 1872 struct fc_rport *rport = starget_to_rport(scsi_target(sdev));
1da177e4 1873
19a7b4ae 1874 if (!rport || fc_remote_port_chkready(rport))
f4f051eb 1875 return -ENXIO;
bdf79621 1876
19a7b4ae 1877 sdev->hostdata = *(fc_port_t **)rport->dd_data;
1da177e4 1878
f4f051eb 1879 return 0;
1880}
1da177e4 1881
f4f051eb 1882static int
1883qla2xxx_slave_configure(struct scsi_device *sdev)
1884{
e315cd28 1885 scsi_qla_host_t *vha = shost_priv(sdev->host);
2afa19a9 1886 struct req_que *req = vha->req;
8482e118 1887
9e522cd8
AE		 1888 if (IS_T10_PI_CAPABLE(vha->hw))
1889 blk_queue_update_dma_alignment(sdev->request_queue, 0x7);
1890
db5ed4df 1891 scsi_change_queue_depth(sdev, req->max_q_depth);
f4f051eb 1892 return 0;
1893}
1da177e4 1894
f4f051eb 1895static void
1896qla2xxx_slave_destroy(struct scsi_device *sdev)
1897{
1898 sdev->hostdata = NULL;
1da177e4
LT		 1899}
1900
1901/**
1902 * qla2x00_config_dma_addressing() - Configure OS DMA addressing method.
1903 * @ha: HA context
1904 *
1905 * At exit, the @ha's flags.enable_64bit_addressing set to indicated
1906 * supported addressing method.
1907 */
1908static void
53303c42 1909qla2x00_config_dma_addressing(struct qla_hw_data *ha)
1da177e4 1910{
7524f9b9 1911 /* Assume a 32bit DMA mask. */
1da177e4 1912 ha->flags.enable_64bit_addressing = 0;
1da177e4 1913
6a35528a 1914 if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) {
7524f9b9
AV		 1915 /* Any upper-dword bits set? */
1916 if (MSD(dma_get_required_mask(&ha->pdev->dev)) &&
6a35528a 1917 !pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(64))) {
7524f9b9 1918 /* Ok, a 64bit DMA mask is applicable. */
1da177e4 1919 ha->flags.enable_64bit_addressing = 1;
fd34f556
AV		 1920 ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64;
1921 ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64;
7524f9b9 1922 return;
1da177e4 1923 }
1da177e4 1924 }
7524f9b9 1925
284901a9
YH		 1926 dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32));
1927 pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(32));
1da177e4
LT		 1928}
1929
fd34f556 1930static void
e315cd28 1931qla2x00_enable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1932{
1933 unsigned long flags = 0;
1934 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1935
1936 spin_lock_irqsave(&ha->hardware_lock, flags);
1937 ha->interrupts_on = 1;
1938 /* enable risc and host interrupts */
1939 WRT_REG_WORD(&reg->ictrl, ICR_EN_INT | ICR_EN_RISC);
1940 RD_REG_WORD(&reg->ictrl);
1941 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1942
1943}
1944
1945static void
e315cd28 1946qla2x00_disable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1947{
1948 unsigned long flags = 0;
1949 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1950
1951 spin_lock_irqsave(&ha->hardware_lock, flags);
1952 ha->interrupts_on = 0;
1953 /* disable risc and host interrupts */
1954 WRT_REG_WORD(&reg->ictrl, 0);
1955 RD_REG_WORD(&reg->ictrl);
1956 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1957}
1958
1959static void
e315cd28 1960qla24xx_enable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1961{
1962 unsigned long flags = 0;
1963 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1964
1965 spin_lock_irqsave(&ha->hardware_lock, flags);
1966 ha->interrupts_on = 1;
1967 WRT_REG_DWORD(&reg->ictrl, ICRX_EN_RISC_INT);
1968 RD_REG_DWORD(&reg->ictrl);
1969 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1970}
1971
1972static void
e315cd28 1973qla24xx_disable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1974{
1975 unsigned long flags = 0;
1976 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1977
124f85e6
AV		 1978 if (IS_NOPOLLING_TYPE(ha))
1979 return;
fd34f556
AV		 1980 spin_lock_irqsave(&ha->hardware_lock, flags);
1981 ha->interrupts_on = 0;
1982 WRT_REG_DWORD(&reg->ictrl, 0);
1983 RD_REG_DWORD(&reg->ictrl);
1984 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1985}
1986
706f457d
GM		 1987static int
1988qla2x00_iospace_config(struct qla_hw_data *ha)
1989{
1990 resource_size_t pio;
1991 uint16_t msix;
706f457d 1992
706f457d
GM		 1993 if (pci_request_selected_regions(ha->pdev, ha->bars,
1994 QLA2XXX_DRIVER_NAME)) {
1995 ql_log_pci(ql_log_fatal, ha->pdev, 0x0011,
1996 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
1997 pci_name(ha->pdev));
1998 goto iospace_error_exit;
1999 }
2000 if (!(ha->bars & 1))
2001 goto skip_pio;
2002
2003 /* We only need PIO for Flash operations on ISP2312 v2 chips. */
2004 pio = pci_resource_start(ha->pdev, 0);
2005 if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) {
2006 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
2007 ql_log_pci(ql_log_warn, ha->pdev, 0x0012,
2008 "Invalid pci I/O region size (%s).\n",
2009 pci_name(ha->pdev));
2010 pio = 0;
2011 }
2012 } else {
2013 ql_log_pci(ql_log_warn, ha->pdev, 0x0013,
2014 "Region #0 no a PIO resource (%s).\n",
2015 pci_name(ha->pdev));
2016 pio = 0;
2017 }
2018 ha->pio_address = pio;
2019 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014,
2020 "PIO address=%llu.\n",
2021 (unsigned long long)ha->pio_address);
2022
2023skip_pio:
2024 /* Use MMIO operations for all accesses. */
2025 if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) {
2026 ql_log_pci(ql_log_fatal, ha->pdev, 0x0015,
2027 "Region #1 not an MMIO resource (%s), aborting.\n",
2028 pci_name(ha->pdev));
2029 goto iospace_error_exit;
2030 }
2031 if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) {
2032 ql_log_pci(ql_log_fatal, ha->pdev, 0x0016,
2033 "Invalid PCI mem region size (%s), aborting.\n",
2034 pci_name(ha->pdev));
2035 goto iospace_error_exit;
2036 }
2037
2038 ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN);
2039 if (!ha->iobase) {
2040 ql_log_pci(ql_log_fatal, ha->pdev, 0x0017,
2041 "Cannot remap MMIO (%s), aborting.\n",
2042 pci_name(ha->pdev));
2043 goto iospace_error_exit;
2044 }
2045
2046 /* Determine queue resources */
2047 ha->max_req_queues = ha->max_rsp_queues = 1;
f54f2cb5 2048 ha->msix_count = QLA_BASE_VECTORS;
c38d1baf
HM		 2049 if (!ql2xmqsupport || !ql2xnvmeenable ||
2050 (!IS_QLA25XX(ha) && !IS_QLA81XX(ha)))
706f457d
GM		 2051 goto mqiobase_exit;
2052
2053 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3),
2054 pci_resource_len(ha->pdev, 3));
2055 if (ha->mqiobase) {
2056 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018,
2057 "MQIO Base=%p.\n", ha->mqiobase);
2058 /* Read MSIX vector size of the board */
2059 pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix);
d7459527 2060 ha->msix_count = msix + 1;
706f457d 2061 /* Max queues are bounded by available msix vectors */
d7459527
MH		 2062 /* MB interrupt uses 1 vector */
2063 ha->max_req_queues = ha->msix_count - 1;
2064 ha->max_rsp_queues = ha->max_req_queues;
2065 /* Queue pairs is the max value minus the base queue pair */
2066 ha->max_qpairs = ha->max_rsp_queues - 1;
2067 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0188,
2068 "Max no of queues pairs: %d.\n", ha->max_qpairs);
2069
706f457d 2070 ql_log_pci(ql_log_info, ha->pdev, 0x001a,
d7459527 2071 "MSI-X vector count: %d.\n", ha->msix_count);
706f457d
GM		 2072 } else
2073 ql_log_pci(ql_log_info, ha->pdev, 0x001b,
2074 "BAR 3 not enabled.\n");
2075
2076mqiobase_exit:
706f457d 2077 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c,
f54f2cb5 2078 "MSIX Count: %d.\n", ha->msix_count);
706f457d
GM		 2079 return (0);
2080
2081iospace_error_exit:
2082 return (-ENOMEM);
2083}
2084
2085
6246b8a1
GM		 2086static int
2087qla83xx_iospace_config(struct qla_hw_data *ha)
2088{
2089 uint16_t msix;
6246b8a1
GM		 2090
2091 if (pci_request_selected_regions(ha->pdev, ha->bars,
2092 QLA2XXX_DRIVER_NAME)) {
2093 ql_log_pci(ql_log_fatal, ha->pdev, 0x0117,
2094 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
2095 pci_name(ha->pdev));
2096
2097 goto iospace_error_exit;
2098 }
2099
2100 /* Use MMIO operations for all accesses. */
2101 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) {
2102 ql_log_pci(ql_log_warn, ha->pdev, 0x0118,
2103 "Invalid pci I/O region size (%s).\n",
2104 pci_name(ha->pdev));
2105 goto iospace_error_exit;
2106 }
2107 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
2108 ql_log_pci(ql_log_warn, ha->pdev, 0x0119,
2109 "Invalid PCI mem region size (%s), aborting\n",
2110 pci_name(ha->pdev));
2111 goto iospace_error_exit;
2112 }
2113
2114 ha->iobase = ioremap(pci_resource_start(ha->pdev, 0), MIN_IOBASE_LEN);
2115 if (!ha->iobase) {
2116 ql_log_pci(ql_log_fatal, ha->pdev, 0x011a,
2117 "Cannot remap MMIO (%s), aborting.\n",
2118 pci_name(ha->pdev));
2119 goto iospace_error_exit;
2120 }
2121
2122 /* 64bit PCI BAR - BAR2 will correspoond to region 4 */
2123 /* 83XX 26XX always use MQ type access for queues
2124 * - mbar 2, a.k.a region 4 */
2125 ha->max_req_queues = ha->max_rsp_queues = 1;
f54f2cb5 2126 ha->msix_count = QLA_BASE_VECTORS;
6246b8a1
GM		 2127 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 4),
2128 pci_resource_len(ha->pdev, 4));
2129
2130 if (!ha->mqiobase) {
2131 ql_log_pci(ql_log_fatal, ha->pdev, 0x011d,
2132 "BAR2/region4 not enabled\n");
2133 goto mqiobase_exit;
2134 }
2135
2136 ha->msixbase = ioremap(pci_resource_start(ha->pdev, 2),
2137 pci_resource_len(ha->pdev, 2));
2138 if (ha->msixbase) {
2139 /* Read MSIX vector size of the board */
2140 pci_read_config_word(ha->pdev,
2141 QLA_83XX_PCI_MSIX_CONTROL, &msix);
e326d22a 2142 ha->msix_count = (msix & PCI_MSIX_FLAGS_QSIZE) + 1;
093df737
QT		 2143 /*
2144 * By default, driver uses at least two msix vectors
2145 * (default & rspq)
2146 */
c38d1baf 2147 if (ql2xmqsupport || ql2xnvmeenable) {
d7459527
MH		 2148 /* MB interrupt uses 1 vector */
2149 ha->max_req_queues = ha->msix_count - 1;
093df737
QT		 2150
2151 /* ATIOQ needs 1 vector. That's 1 less QPair */
2152 if (QLA_TGT_MODE_ENABLED())
2153 ha->max_req_queues--;
2154
d0d2c68b
MH		 2155 ha->max_rsp_queues = ha->max_req_queues;
2156
d7459527
MH		 2157 /* Queue pairs is the max value minus
2158 * the base queue pair */
2159 ha->max_qpairs = ha->max_req_queues - 1;
83548fe2 2160 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x00e3,
d7459527 2161 "Max no of queues pairs: %d.\n", ha->max_qpairs);
6246b8a1
GM		 2162 }
2163 ql_log_pci(ql_log_info, ha->pdev, 0x011c,
d7459527 2164 "MSI-X vector count: %d.\n", ha->msix_count);
6246b8a1
GM		 2165 } else
2166 ql_log_pci(ql_log_info, ha->pdev, 0x011e,
2167 "BAR 1 not enabled.\n");
2168
2169mqiobase_exit:
6246b8a1 2170 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011f,
f54f2cb5 2171 "MSIX Count: %d.\n", ha->msix_count);
6246b8a1
GM		 2172 return 0;
2173
2174iospace_error_exit:
2175 return -ENOMEM;
2176}
2177
fd34f556
AV		 2178static struct isp_operations qla2100_isp_ops = {
2179 .pci_config = qla2100_pci_config,
2180 .reset_chip = qla2x00_reset_chip,
2181 .chip_diag = qla2x00_chip_diag,
2182 .config_rings = qla2x00_config_rings,
2183 .reset_adapter = qla2x00_reset_adapter,
2184 .nvram_config = qla2x00_nvram_config,
2185 .update_fw_options = qla2x00_update_fw_options,
2186 .load_risc = qla2x00_load_risc,
2187 .pci_info_str = qla2x00_pci_info_str,
2188 .fw_version_str = qla2x00_fw_version_str,
2189 .intr_handler = qla2100_intr_handler,
2190 .enable_intrs = qla2x00_enable_intrs,
2191 .disable_intrs = qla2x00_disable_intrs,
2192 .abort_command = qla2x00_abort_command,
523ec773
AV		 2193 .target_reset = qla2x00_abort_target,
2194 .lun_reset = qla2x00_lun_reset,
fd34f556
AV		 2195 .fabric_login = qla2x00_login_fabric,
2196 .fabric_logout = qla2x00_fabric_logout,
2197 .calc_req_entries = qla2x00_calc_iocbs_32,
2198 .build_iocbs = qla2x00_build_scsi_iocbs_32,
2199 .prep_ms_iocb = qla2x00_prep_ms_iocb,
2200 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
2201 .read_nvram = qla2x00_read_nvram_data,
2202 .write_nvram = qla2x00_write_nvram_data,
2203 .fw_dump = qla2100_fw_dump,
2204 .beacon_on = NULL,
2205 .beacon_off = NULL,
2206 .beacon_blink = NULL,
2207 .read_optrom = qla2x00_read_optrom_data,
2208 .write_optrom = qla2x00_write_optrom_data,
2209 .get_flash_version = qla2x00_get_flash_version,
e315cd28 2210 .start_scsi = qla2x00_start_scsi,
d7459527 2211 .start_scsi_mq = NULL,
a9083016 2212 .abort_isp = qla2x00_abort_isp,
706f457d 2213 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2214 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 2215};
2216
2217static struct isp_operations qla2300_isp_ops = {
2218 .pci_config = qla2300_pci_config,
2219 .reset_chip = qla2x00_reset_chip,
2220 .chip_diag = qla2x00_chip_diag,
2221 .config_rings = qla2x00_config_rings,
2222 .reset_adapter = qla2x00_reset_adapter,
2223 .nvram_config = qla2x00_nvram_config,
2224 .update_fw_options = qla2x00_update_fw_options,
2225 .load_risc = qla2x00_load_risc,
2226 .pci_info_str = qla2x00_pci_info_str,
2227 .fw_version_str = qla2x00_fw_version_str,
2228 .intr_handler = qla2300_intr_handler,
2229 .enable_intrs = qla2x00_enable_intrs,
2230 .disable_intrs = qla2x00_disable_intrs,
2231 .abort_command = qla2x00_abort_command,
523ec773
AV		 2232 .target_reset = qla2x00_abort_target,
2233 .lun_reset = qla2x00_lun_reset,
fd34f556
AV		 2234 .fabric_login = qla2x00_login_fabric,
2235 .fabric_logout = qla2x00_fabric_logout,
2236 .calc_req_entries = qla2x00_calc_iocbs_32,
2237 .build_iocbs = qla2x00_build_scsi_iocbs_32,
2238 .prep_ms_iocb = qla2x00_prep_ms_iocb,
2239 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
2240 .read_nvram = qla2x00_read_nvram_data,
2241 .write_nvram = qla2x00_write_nvram_data,
2242 .fw_dump = qla2300_fw_dump,
2243 .beacon_on = qla2x00_beacon_on,
2244 .beacon_off = qla2x00_beacon_off,
2245 .beacon_blink = qla2x00_beacon_blink,
2246 .read_optrom = qla2x00_read_optrom_data,
2247 .write_optrom = qla2x00_write_optrom_data,
2248 .get_flash_version = qla2x00_get_flash_version,
e315cd28 2249 .start_scsi = qla2x00_start_scsi,
d7459527 2250 .start_scsi_mq = NULL,
a9083016 2251 .abort_isp = qla2x00_abort_isp,
7ec0effd 2252 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2253 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 2254};
2255
2256static struct isp_operations qla24xx_isp_ops = {
2257 .pci_config = qla24xx_pci_config,
2258 .reset_chip = qla24xx_reset_chip,
2259 .chip_diag = qla24xx_chip_diag,
2260 .config_rings = qla24xx_config_rings,
2261 .reset_adapter = qla24xx_reset_adapter,
2262 .nvram_config = qla24xx_nvram_config,
2263 .update_fw_options = qla24xx_update_fw_options,
2264 .load_risc = qla24xx_load_risc,
2265 .pci_info_str = qla24xx_pci_info_str,
2266 .fw_version_str = qla24xx_fw_version_str,
2267 .intr_handler = qla24xx_intr_handler,
2268 .enable_intrs = qla24xx_enable_intrs,
2269 .disable_intrs = qla24xx_disable_intrs,
2270 .abort_command = qla24xx_abort_command,
523ec773
AV		 2271 .target_reset = qla24xx_abort_target,
2272 .lun_reset = qla24xx_lun_reset,
fd34f556
AV		 2273 .fabric_login = qla24xx_login_fabric,
2274 .fabric_logout = qla24xx_fabric_logout,
2275 .calc_req_entries = NULL,
2276 .build_iocbs = NULL,
2277 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2278 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2279 .read_nvram = qla24xx_read_nvram_data,
2280 .write_nvram = qla24xx_write_nvram_data,
2281 .fw_dump = qla24xx_fw_dump,
2282 .beacon_on = qla24xx_beacon_on,
2283 .beacon_off = qla24xx_beacon_off,
2284 .beacon_blink = qla24xx_beacon_blink,
2285 .read_optrom = qla24xx_read_optrom_data,
2286 .write_optrom = qla24xx_write_optrom_data,
2287 .get_flash_version = qla24xx_get_flash_version,
e315cd28 2288 .start_scsi = qla24xx_start_scsi,
d7459527 2289 .start_scsi_mq = NULL,
a9083016 2290 .abort_isp = qla2x00_abort_isp,
7ec0effd 2291 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2292 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 2293};
2294
c3a2f0df
AV		 2295static struct isp_operations qla25xx_isp_ops = {
2296 .pci_config = qla25xx_pci_config,
2297 .reset_chip = qla24xx_reset_chip,
2298 .chip_diag = qla24xx_chip_diag,
2299 .config_rings = qla24xx_config_rings,
2300 .reset_adapter = qla24xx_reset_adapter,
2301 .nvram_config = qla24xx_nvram_config,
2302 .update_fw_options = qla24xx_update_fw_options,
2303 .load_risc = qla24xx_load_risc,
2304 .pci_info_str = qla24xx_pci_info_str,
2305 .fw_version_str = qla24xx_fw_version_str,
2306 .intr_handler = qla24xx_intr_handler,
2307 .enable_intrs = qla24xx_enable_intrs,
2308 .disable_intrs = qla24xx_disable_intrs,
2309 .abort_command = qla24xx_abort_command,
523ec773
AV		 2310 .target_reset = qla24xx_abort_target,
2311 .lun_reset = qla24xx_lun_reset,
c3a2f0df
AV		 2312 .fabric_login = qla24xx_login_fabric,
2313 .fabric_logout = qla24xx_fabric_logout,
2314 .calc_req_entries = NULL,
2315 .build_iocbs = NULL,
2316 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2317 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2318 .read_nvram = qla25xx_read_nvram_data,
2319 .write_nvram = qla25xx_write_nvram_data,
2320 .fw_dump = qla25xx_fw_dump,
2321 .beacon_on = qla24xx_beacon_on,
2322 .beacon_off = qla24xx_beacon_off,
2323 .beacon_blink = qla24xx_beacon_blink,
338c9161 2324 .read_optrom = qla25xx_read_optrom_data,
c3a2f0df
AV		 2325 .write_optrom = qla24xx_write_optrom_data,
2326 .get_flash_version = qla24xx_get_flash_version,
bad75002 2327 .start_scsi = qla24xx_dif_start_scsi,
d7459527 2328 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
a9083016 2329 .abort_isp = qla2x00_abort_isp,
7ec0effd 2330 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2331 .initialize_adapter = qla2x00_initialize_adapter,
c3a2f0df
AV		 2332};
2333
3a03eb79
AV		 2334static struct isp_operations qla81xx_isp_ops = {
2335 .pci_config = qla25xx_pci_config,
2336 .reset_chip = qla24xx_reset_chip,
2337 .chip_diag = qla24xx_chip_diag,
2338 .config_rings = qla24xx_config_rings,
2339 .reset_adapter = qla24xx_reset_adapter,
2340 .nvram_config = qla81xx_nvram_config,
2341 .update_fw_options = qla81xx_update_fw_options,
eaac30be 2342 .load_risc = qla81xx_load_risc,
3a03eb79
AV		 2343 .pci_info_str = qla24xx_pci_info_str,
2344 .fw_version_str = qla24xx_fw_version_str,
2345 .intr_handler = qla24xx_intr_handler,
2346 .enable_intrs = qla24xx_enable_intrs,
2347 .disable_intrs = qla24xx_disable_intrs,
2348 .abort_command = qla24xx_abort_command,
2349 .target_reset = qla24xx_abort_target,
2350 .lun_reset = qla24xx_lun_reset,
2351 .fabric_login = qla24xx_login_fabric,
2352 .fabric_logout = qla24xx_fabric_logout,
2353 .calc_req_entries = NULL,
2354 .build_iocbs = NULL,
2355 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2356 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
3d79038f
AV		 2357 .read_nvram = NULL,
2358 .write_nvram = NULL,
3a03eb79
AV		 2359 .fw_dump = qla81xx_fw_dump,
2360 .beacon_on = qla24xx_beacon_on,
2361 .beacon_off = qla24xx_beacon_off,
6246b8a1 2362 .beacon_blink = qla83xx_beacon_blink,
3a03eb79
AV		 2363 .read_optrom = qla25xx_read_optrom_data,
2364 .write_optrom = qla24xx_write_optrom_data,
2365 .get_flash_version = qla24xx_get_flash_version,
ba77ef53 2366 .start_scsi = qla24xx_dif_start_scsi,
d7459527 2367 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
a9083016 2368 .abort_isp = qla2x00_abort_isp,
7ec0effd 2369 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2370 .initialize_adapter = qla2x00_initialize_adapter,
a9083016
GM		 2371};
2372
2373static struct isp_operations qla82xx_isp_ops = {
2374 .pci_config = qla82xx_pci_config,
2375 .reset_chip = qla82xx_reset_chip,
2376 .chip_diag = qla24xx_chip_diag,
2377 .config_rings = qla82xx_config_rings,
2378 .reset_adapter = qla24xx_reset_adapter,
2379 .nvram_config = qla81xx_nvram_config,
2380 .update_fw_options = qla24xx_update_fw_options,
2381 .load_risc = qla82xx_load_risc,
9d55ca66 2382 .pci_info_str = qla24xx_pci_info_str,
a9083016
GM		 2383 .fw_version_str = qla24xx_fw_version_str,
2384 .intr_handler = qla82xx_intr_handler,
2385 .enable_intrs = qla82xx_enable_intrs,
2386 .disable_intrs = qla82xx_disable_intrs,
2387 .abort_command = qla24xx_abort_command,
2388 .target_reset = qla24xx_abort_target,
2389 .lun_reset = qla24xx_lun_reset,
2390 .fabric_login = qla24xx_login_fabric,
2391 .fabric_logout = qla24xx_fabric_logout,
2392 .calc_req_entries = NULL,
2393 .build_iocbs = NULL,
2394 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2395 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2396 .read_nvram = qla24xx_read_nvram_data,
2397 .write_nvram = qla24xx_write_nvram_data,
a1b23c5a 2398 .fw_dump = qla82xx_fw_dump,
999916dc
SK		 2399 .beacon_on = qla82xx_beacon_on,
2400 .beacon_off = qla82xx_beacon_off,
2401 .beacon_blink = NULL,
a9083016
GM		 2402 .read_optrom = qla82xx_read_optrom_data,
2403 .write_optrom = qla82xx_write_optrom_data,
7ec0effd 2404 .get_flash_version = qla82xx_get_flash_version,
a9083016 2405 .start_scsi = qla82xx_start_scsi,
d7459527 2406 .start_scsi_mq = NULL,
a9083016 2407 .abort_isp = qla82xx_abort_isp,
706f457d 2408 .iospace_config = qla82xx_iospace_config,
8ae6d9c7 2409 .initialize_adapter = qla2x00_initialize_adapter,
3a03eb79
AV		 2410};
2411
7ec0effd
AD		 2412static struct isp_operations qla8044_isp_ops = {
2413 .pci_config = qla82xx_pci_config,
2414 .reset_chip = qla82xx_reset_chip,
2415 .chip_diag = qla24xx_chip_diag,
2416 .config_rings = qla82xx_config_rings,
2417 .reset_adapter = qla24xx_reset_adapter,
2418 .nvram_config = qla81xx_nvram_config,
2419 .update_fw_options = qla24xx_update_fw_options,
2420 .load_risc = qla82xx_load_risc,
2421 .pci_info_str = qla24xx_pci_info_str,
2422 .fw_version_str = qla24xx_fw_version_str,
2423 .intr_handler = qla8044_intr_handler,
2424 .enable_intrs = qla82xx_enable_intrs,
2425 .disable_intrs = qla82xx_disable_intrs,
2426 .abort_command = qla24xx_abort_command,
2427 .target_reset = qla24xx_abort_target,
2428 .lun_reset = qla24xx_lun_reset,
2429 .fabric_login = qla24xx_login_fabric,
2430 .fabric_logout = qla24xx_fabric_logout,
2431 .calc_req_entries = NULL,
2432 .build_iocbs = NULL,
2433 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2434 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2435 .read_nvram = NULL,
2436 .write_nvram = NULL,
a1b23c5a 2437 .fw_dump = qla8044_fw_dump,
7ec0effd
AD		 2438 .beacon_on = qla82xx_beacon_on,
2439 .beacon_off = qla82xx_beacon_off,
2440 .beacon_blink = NULL,
888e639d 2441 .read_optrom = qla8044_read_optrom_data,
7ec0effd
AD		 2442 .write_optrom = qla8044_write_optrom_data,
2443 .get_flash_version = qla82xx_get_flash_version,
2444 .start_scsi = qla82xx_start_scsi,
d7459527 2445 .start_scsi_mq = NULL,
7ec0effd
AD		 2446 .abort_isp = qla8044_abort_isp,
2447 .iospace_config = qla82xx_iospace_config,
2448 .initialize_adapter = qla2x00_initialize_adapter,
2449};
2450
6246b8a1
GM		 2451static struct isp_operations qla83xx_isp_ops = {
2452 .pci_config = qla25xx_pci_config,
2453 .reset_chip = qla24xx_reset_chip,
2454 .chip_diag = qla24xx_chip_diag,
2455 .config_rings = qla24xx_config_rings,
2456 .reset_adapter = qla24xx_reset_adapter,
2457 .nvram_config = qla81xx_nvram_config,
2458 .update_fw_options = qla81xx_update_fw_options,
2459 .load_risc = qla81xx_load_risc,
2460 .pci_info_str = qla24xx_pci_info_str,
2461 .fw_version_str = qla24xx_fw_version_str,
2462 .intr_handler = qla24xx_intr_handler,
2463 .enable_intrs = qla24xx_enable_intrs,
2464 .disable_intrs = qla24xx_disable_intrs,
2465 .abort_command = qla24xx_abort_command,
2466 .target_reset = qla24xx_abort_target,
2467 .lun_reset = qla24xx_lun_reset,
2468 .fabric_login = qla24xx_login_fabric,
2469 .fabric_logout = qla24xx_fabric_logout,
2470 .calc_req_entries = NULL,
2471 .build_iocbs = NULL,
2472 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2473 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2474 .read_nvram = NULL,
2475 .write_nvram = NULL,
2476 .fw_dump = qla83xx_fw_dump,
2477 .beacon_on = qla24xx_beacon_on,
2478 .beacon_off = qla24xx_beacon_off,
2479 .beacon_blink = qla83xx_beacon_blink,
2480 .read_optrom = qla25xx_read_optrom_data,
2481 .write_optrom = qla24xx_write_optrom_data,
2482 .get_flash_version = qla24xx_get_flash_version,
2483 .start_scsi = qla24xx_dif_start_scsi,
d7459527 2484 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
6246b8a1
GM		 2485 .abort_isp = qla2x00_abort_isp,
2486 .iospace_config = qla83xx_iospace_config,
8ae6d9c7
GM		 2487 .initialize_adapter = qla2x00_initialize_adapter,
2488};
2489
2490static struct isp_operations qlafx00_isp_ops = {
2491 .pci_config = qlafx00_pci_config,
2492 .reset_chip = qlafx00_soft_reset,
2493 .chip_diag = qlafx00_chip_diag,
2494 .config_rings = qlafx00_config_rings,
2495 .reset_adapter = qlafx00_soft_reset,
2496 .nvram_config = NULL,
2497 .update_fw_options = NULL,
2498 .load_risc = NULL,
2499 .pci_info_str = qlafx00_pci_info_str,
2500 .fw_version_str = qlafx00_fw_version_str,
2501 .intr_handler = qlafx00_intr_handler,
2502 .enable_intrs = qlafx00_enable_intrs,
2503 .disable_intrs = qlafx00_disable_intrs,
4440e46d 2504 .abort_command = qla24xx_async_abort_command,
8ae6d9c7
GM		 2505 .target_reset = qlafx00_abort_target,
2506 .lun_reset = qlafx00_lun_reset,
2507 .fabric_login = NULL,
2508 .fabric_logout = NULL,
2509 .calc_req_entries = NULL,
2510 .build_iocbs = NULL,
2511 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2512 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2513 .read_nvram = qla24xx_read_nvram_data,
2514 .write_nvram = qla24xx_write_nvram_data,
2515 .fw_dump = NULL,
2516 .beacon_on = qla24xx_beacon_on,
2517 .beacon_off = qla24xx_beacon_off,
2518 .beacon_blink = NULL,
2519 .read_optrom = qla24xx_read_optrom_data,
2520 .write_optrom = qla24xx_write_optrom_data,
2521 .get_flash_version = qla24xx_get_flash_version,
2522 .start_scsi = qlafx00_start_scsi,
d7459527 2523 .start_scsi_mq = NULL,
8ae6d9c7
GM		 2524 .abort_isp = qlafx00_abort_isp,
2525 .iospace_config = qlafx00_iospace_config,
2526 .initialize_adapter = qlafx00_initialize_adapter,
6246b8a1
GM		 2527};
2528
f73cb695
CD		 2529static struct isp_operations qla27xx_isp_ops = {
2530 .pci_config = qla25xx_pci_config,
2531 .reset_chip = qla24xx_reset_chip,
2532 .chip_diag = qla24xx_chip_diag,
2533 .config_rings = qla24xx_config_rings,
2534 .reset_adapter = qla24xx_reset_adapter,
2535 .nvram_config = qla81xx_nvram_config,
2536 .update_fw_options = qla81xx_update_fw_options,
2537 .load_risc = qla81xx_load_risc,
2538 .pci_info_str = qla24xx_pci_info_str,
2539 .fw_version_str = qla24xx_fw_version_str,
2540 .intr_handler = qla24xx_intr_handler,
2541 .enable_intrs = qla24xx_enable_intrs,
2542 .disable_intrs = qla24xx_disable_intrs,
2543 .abort_command = qla24xx_abort_command,
2544 .target_reset = qla24xx_abort_target,
2545 .lun_reset = qla24xx_lun_reset,
2546 .fabric_login = qla24xx_login_fabric,
2547 .fabric_logout = qla24xx_fabric_logout,
2548 .calc_req_entries = NULL,
2549 .build_iocbs = NULL,
2550 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2551 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2552 .read_nvram = NULL,
2553 .write_nvram = NULL,
2554 .fw_dump = qla27xx_fwdump,
2555 .beacon_on = qla24xx_beacon_on,
2556 .beacon_off = qla24xx_beacon_off,
2557 .beacon_blink = qla83xx_beacon_blink,
2558 .read_optrom = qla25xx_read_optrom_data,
2559 .write_optrom = qla24xx_write_optrom_data,
2560 .get_flash_version = qla24xx_get_flash_version,
2561 .start_scsi = qla24xx_dif_start_scsi,
d7459527 2562 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
f73cb695
CD		 2563 .abort_isp = qla2x00_abort_isp,
2564 .iospace_config = qla83xx_iospace_config,
2565 .initialize_adapter = qla2x00_initialize_adapter,
2566};
2567
ea5b6382 2568static inline void
e315cd28 2569qla2x00_set_isp_flags(struct qla_hw_data *ha)
ea5b6382 2570{
2571 ha->device_type = DT_EXTENDED_IDS;
2572 switch (ha->pdev->device) {
2573 case PCI_DEVICE_ID_QLOGIC_ISP2100:
9e052e2d 2574 ha->isp_type |= DT_ISP2100;
ea5b6382 2575 ha->device_type &= ~DT_EXTENDED_IDS;
441d1072 2576 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
ea5b6382 2577 break;
2578 case PCI_DEVICE_ID_QLOGIC_ISP2200:
9e052e2d 2579 ha->isp_type |= DT_ISP2200;
ea5b6382 2580 ha->device_type &= ~DT_EXTENDED_IDS;
441d1072 2581 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
ea5b6382 2582 break;
2583 case PCI_DEVICE_ID_QLOGIC_ISP2300:
9e052e2d 2584 ha->isp_type |= DT_ISP2300;
4a59f71d 2585 ha->device_type |= DT_ZIO_SUPPORTED;
441d1072 2586 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 2587 break;
2588 case PCI_DEVICE_ID_QLOGIC_ISP2312:
9e052e2d 2589 ha->isp_type |= DT_ISP2312;
4a59f71d 2590 ha->device_type |= DT_ZIO_SUPPORTED;
441d1072 2591 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 2592 break;
2593 case PCI_DEVICE_ID_QLOGIC_ISP2322:
9e052e2d 2594 ha->isp_type |= DT_ISP2322;
4a59f71d 2595 ha->device_type |= DT_ZIO_SUPPORTED;
ea5b6382 2596 if (ha->pdev->subsystem_vendor == 0x1028 &&
2597 ha->pdev->subsystem_device == 0x0170)
2598 ha->device_type |= DT_OEM_001;
441d1072 2599 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 2600 break;
2601 case PCI_DEVICE_ID_QLOGIC_ISP6312:
9e052e2d 2602 ha->isp_type |= DT_ISP6312;
441d1072 2603 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 2604 break;
2605 case PCI_DEVICE_ID_QLOGIC_ISP6322:
9e052e2d 2606 ha->isp_type |= DT_ISP6322;
441d1072 2607 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 2608 break;
2609 case PCI_DEVICE_ID_QLOGIC_ISP2422:
9e052e2d 2610 ha->isp_type |= DT_ISP2422;
4a59f71d 2611 ha->device_type |= DT_ZIO_SUPPORTED;
e428924c 2612 ha->device_type |= DT_FWI2;
c76f2c01 2613 ha->device_type |= DT_IIDMA;
441d1072 2614 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2615 break;
2616 case PCI_DEVICE_ID_QLOGIC_ISP2432:
9e052e2d 2617 ha->isp_type |= DT_ISP2432;
4a59f71d 2618 ha->device_type |= DT_ZIO_SUPPORTED;
e428924c 2619 ha->device_type |= DT_FWI2;
c76f2c01 2620 ha->device_type |= DT_IIDMA;
441d1072 2621 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2622 break;
4d4df193 2623 case PCI_DEVICE_ID_QLOGIC_ISP8432:
9e052e2d 2624 ha->isp_type |= DT_ISP8432;
4d4df193
HK		 2625 ha->device_type |= DT_ZIO_SUPPORTED;
2626 ha->device_type |= DT_FWI2;
2627 ha->device_type |= DT_IIDMA;
2628 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2629 break;
044cc6c8 2630 case PCI_DEVICE_ID_QLOGIC_ISP5422:
9e052e2d 2631 ha->isp_type |= DT_ISP5422;
e428924c 2632 ha->device_type |= DT_FWI2;
441d1072 2633 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2634 break;
044cc6c8 2635 case PCI_DEVICE_ID_QLOGIC_ISP5432:
9e052e2d 2636 ha->isp_type |= DT_ISP5432;
e428924c 2637 ha->device_type |= DT_FWI2;
441d1072 2638 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2639 break;
c3a2f0df 2640 case PCI_DEVICE_ID_QLOGIC_ISP2532:
9e052e2d 2641 ha->isp_type |= DT_ISP2532;
c3a2f0df
AV		 2642 ha->device_type |= DT_ZIO_SUPPORTED;
2643 ha->device_type |= DT_FWI2;
2644 ha->device_type |= DT_IIDMA;
441d1072 2645 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2646 break;
3a03eb79 2647 case PCI_DEVICE_ID_QLOGIC_ISP8001:
9e052e2d 2648 ha->isp_type |= DT_ISP8001;
3a03eb79
AV		 2649 ha->device_type |= DT_ZIO_SUPPORTED;
2650 ha->device_type |= DT_FWI2;
2651 ha->device_type |= DT_IIDMA;
2652 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2653 break;
a9083016 2654 case PCI_DEVICE_ID_QLOGIC_ISP8021:
9e052e2d 2655 ha->isp_type |= DT_ISP8021;
a9083016
GM		 2656 ha->device_type |= DT_ZIO_SUPPORTED;
2657 ha->device_type |= DT_FWI2;
2658 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2659 /* Initialize 82XX ISP flags */
2660 qla82xx_init_flags(ha);
2661 break;
7ec0effd 2662 case PCI_DEVICE_ID_QLOGIC_ISP8044:
9e052e2d 2663 ha->isp_type |= DT_ISP8044;
7ec0effd
AD		 2664 ha->device_type |= DT_ZIO_SUPPORTED;
2665 ha->device_type |= DT_FWI2;
2666 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2667 /* Initialize 82XX ISP flags */
2668 qla82xx_init_flags(ha);
2669 break;
6246b8a1 2670 case PCI_DEVICE_ID_QLOGIC_ISP2031:
9e052e2d 2671 ha->isp_type |= DT_ISP2031;
6246b8a1
GM		 2672 ha->device_type |= DT_ZIO_SUPPORTED;
2673 ha->device_type |= DT_FWI2;
2674 ha->device_type |= DT_IIDMA;
2675 ha->device_type |= DT_T10_PI;
2676 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2677 break;
2678 case PCI_DEVICE_ID_QLOGIC_ISP8031:
9e052e2d 2679 ha->isp_type |= DT_ISP8031;
6246b8a1
GM		 2680 ha->device_type |= DT_ZIO_SUPPORTED;
2681 ha->device_type |= DT_FWI2;
2682 ha->device_type |= DT_IIDMA;
2683 ha->device_type |= DT_T10_PI;
2684 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2685 break;
8ae6d9c7 2686 case PCI_DEVICE_ID_QLOGIC_ISPF001:
9e052e2d 2687 ha->isp_type |= DT_ISPFX00;
8ae6d9c7 2688 break;
f73cb695 2689 case PCI_DEVICE_ID_QLOGIC_ISP2071:
9e052e2d 2690 ha->isp_type |= DT_ISP2071;
f73cb695
CD		 2691 ha->device_type |= DT_ZIO_SUPPORTED;
2692 ha->device_type |= DT_FWI2;
2693 ha->device_type |= DT_IIDMA;
8ce3f570 2694 ha->device_type |= DT_T10_PI;
f73cb695
CD		 2695 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2696 break;
2c5bbbb2 2697 case PCI_DEVICE_ID_QLOGIC_ISP2271:
9e052e2d 2698 ha->isp_type |= DT_ISP2271;
2c5bbbb2
JC		 2699 ha->device_type |= DT_ZIO_SUPPORTED;
2700 ha->device_type |= DT_FWI2;
2701 ha->device_type |= DT_IIDMA;
8ce3f570 2702 ha->device_type |= DT_T10_PI;
2c5bbbb2
JC		 2703 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2704 break;
2b48992f 2705 case PCI_DEVICE_ID_QLOGIC_ISP2261:
9e052e2d 2706 ha->isp_type |= DT_ISP2261;
2b48992f
SC		 2707 ha->device_type |= DT_ZIO_SUPPORTED;
2708 ha->device_type |= DT_FWI2;
2709 ha->device_type |= DT_IIDMA;
8ce3f570 2710 ha->device_type |= DT_T10_PI;
2b48992f
SC		 2711 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2712 break;
ecc89f25
JC		 2713 case PCI_DEVICE_ID_QLOGIC_ISP2081:
2714 case PCI_DEVICE_ID_QLOGIC_ISP2089:
2715 ha->isp_type |= DT_ISP2081;
2716 ha->device_type |= DT_ZIO_SUPPORTED;
2717 ha->device_type |= DT_FWI2;
2718 ha->device_type |= DT_IIDMA;
2719 ha->device_type |= DT_T10_PI;
2720 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2721 break;
2722 case PCI_DEVICE_ID_QLOGIC_ISP2281:
2723 case PCI_DEVICE_ID_QLOGIC_ISP2289:
2724 ha->isp_type |= DT_ISP2281;
2725 ha->device_type |= DT_ZIO_SUPPORTED;
2726 ha->device_type |= DT_FWI2;
2727 ha->device_type |= DT_IIDMA;
2728 ha->device_type |= DT_T10_PI;
2729 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2730 break;
ea5b6382 2731 }
e5b68a61 2732
a9083016 2733 if (IS_QLA82XX(ha))
43a9c38b 2734 ha->port_no = ha->portnum & 1;
f73cb695 2735 else {
a9083016
GM		 2736 /* Get adapter physical port no from interrupt pin register. */
2737 pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no);
ecc89f25
JC		 2738 if (IS_QLA25XX(ha) || IS_QLA2031(ha) ||
2739 IS_QLA27XX(ha) || IS_QLA28XX(ha))
f73cb695
CD		 2740 ha->port_no--;
2741 else
2742 ha->port_no = !(ha->port_no & 1);
2743 }
a9083016 2744
7c3df132 2745 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b,
d8424f68 2746 "device_type=0x%x port=%d fw_srisc_address=0x%x.\n",
f73cb695 2747 ha->device_type, ha->port_no, ha->fw_srisc_address);
ea5b6382 2748}
2749
1e99e33a
AV		 2750static void
2751qla2xxx_scan_start(struct Scsi_Host *shost)
2752{
e315cd28 2753 scsi_qla_host_t *vha = shost_priv(shost);
1e99e33a 2754
cbc8eb67
AV		 2755 if (vha->hw->flags.running_gold_fw)
2756 return;
2757
e315cd28
AC		 2758 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
2759 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
2760 set_bit(RSCN_UPDATE, &vha->dpc_flags);
2761 set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags);
1e99e33a
AV		 2762}
2763
2764static int
2765qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time)
2766{
e315cd28 2767 scsi_qla_host_t *vha = shost_priv(shost);
1e99e33a 2768
a5dd506e
BK		 2769 if (test_bit(UNLOADING, &vha->dpc_flags))
2770 return 1;
e315cd28 2771 if (!vha->host)
1e99e33a 2772 return 1;
e315cd28 2773 if (time > vha->hw->loop_reset_delay * HZ)
1e99e33a
AV		 2774 return 1;
2775
e315cd28 2776 return atomic_read(&vha->loop_state) == LOOP_READY;
1e99e33a
AV		 2777}
2778
ec7193e2
QT		 2779static void qla2x00_iocb_work_fn(struct work_struct *work)
2780{
2781 struct scsi_qla_host *vha = container_of(work,
2782 struct scsi_qla_host, iocb_work);
9b3e0f4d
QT		 2783 struct qla_hw_data *ha = vha->hw;
2784 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
0aca7784 2785 int i = 2;
9b3e0f4d
QT		 2786 unsigned long flags;
2787
2788 if (test_bit(UNLOADING, &base_vha->dpc_flags))
2789 return;
ec7193e2 2790
9b3e0f4d 2791 while (!list_empty(&vha->work_list) && i > 0) {
ec7193e2 2792 qla2x00_do_work(vha);
9b3e0f4d 2793 i--;
ec7193e2 2794 }
9b3e0f4d
QT		 2795
2796 spin_lock_irqsave(&vha->work_lock, flags);
2797 clear_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags);
2798 spin_unlock_irqrestore(&vha->work_lock, flags);
ec7193e2
QT		 2799}
2800
1da177e4
LT		 2801/*
2802 * PCI driver interface
2803 */
6f039790 2804static int
7ee61397 2805qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
1da177e4 2806{
a1541d5a 2807 int ret = -ENODEV;
1da177e4 2808 struct Scsi_Host *host;
e315cd28
AC		 2809 scsi_qla_host_t *base_vha = NULL;
2810 struct qla_hw_data *ha;
29856e28 2811 char pci_info[30];
7d613ac6 2812 char fw_str[30], wq_name[30];
5433383e 2813 struct scsi_host_template *sht;
642ef983 2814 int bars, mem_only = 0;
e315cd28 2815 uint16_t req_length = 0, rsp_length = 0;
73208dfd
AC		 2816 struct req_que *req = NULL;
2817 struct rsp_que *rsp = NULL;
5601236b 2818 int i;
d7459527 2819
285d0321 2820 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO);
a5326f86 2821 sht = &qla2xxx_driver_template;
5433383e 2822 if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 ||
8bc69e7d 2823 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 ||
4d4df193 2824 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 ||
8bc69e7d 2825 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 ||
c3a2f0df 2826 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 ||
3a03eb79 2827 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 ||
a9083016 2828 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 ||
6246b8a1
GM		 2829 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021 ||
2830 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2031 ||
8ae6d9c7 2831 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8031 ||
7ec0effd 2832 pdev->device == PCI_DEVICE_ID_QLOGIC_ISPF001 ||
f73cb695 2833 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8044 ||
2c5bbbb2 2834 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2071 ||
2b48992f 2835 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2271 ||
ecc89f25
JC		 2836 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2261 ||
2837 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2081 ||
2838 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2281 ||
2839 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2089 ||
2840 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2289) {
285d0321 2841 bars = pci_select_bars(pdev, IORESOURCE_MEM);
09483916 2842 mem_only = 1;
7c3df132
SK		 2843 ql_dbg_pci(ql_dbg_init, pdev, 0x0007,
2844 "Mem only adapter.\n");
285d0321 2845 }
7c3df132
SK		 2846 ql_dbg_pci(ql_dbg_init, pdev, 0x0008,
2847 "Bars=%d.\n", bars);
285d0321 2848
09483916
BH		 2849 if (mem_only) {
2850 if (pci_enable_device_mem(pdev))
ddff7ed4 2851 return ret;
09483916
BH		 2852 } else {
2853 if (pci_enable_device(pdev))
ddff7ed4 2854 return ret;
09483916 2855 }
285d0321 2856
0927678f
JB		 2857 /* This may fail but that's ok */
2858 pci_enable_pcie_error_reporting(pdev);
285d0321 2859
5da05a26
GM		 2860 /* Turn off T10-DIF when FC-NVMe is enabled */
2861 if (ql2xnvmeenable)
2862 ql2xenabledif = 0;
2863
e315cd28
AC		 2864 ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL);
2865 if (!ha) {
7c3df132
SK		 2866 ql_log_pci(ql_log_fatal, pdev, 0x0009,
2867 "Unable to allocate memory for ha.\n");
ddff7ed4 2868 goto disable_device;
1da177e4 2869 }
7c3df132
SK		 2870 ql_dbg_pci(ql_dbg_init, pdev, 0x000a,
2871 "Memory allocated for ha=%p.\n", ha);
e315cd28 2872 ha->pdev = pdev;
33e79977
QT		 2873 INIT_LIST_HEAD(&ha->tgt.q_full_list);
2874 spin_lock_init(&ha->tgt.q_full_lock);
7560151b 2875 spin_lock_init(&ha->tgt.sess_lock);
2f424b9b
QT		 2876 spin_lock_init(&ha->tgt.atio_lock);
2877
deeae7a6 2878 atomic_set(&ha->nvme_active_aen_cnt, 0);
1da177e4
LT		 2879
2880 /* Clear our data area */
285d0321 2881 ha->bars = bars;
09483916 2882 ha->mem_only = mem_only;
df4bf0bb 2883 spin_lock_init(&ha->hardware_lock);
339aa70e 2884 spin_lock_init(&ha->vport_slock);
a9b6f722 2885 mutex_init(&ha->selflogin_lock);
7a8ab9c8 2886 mutex_init(&ha->optrom_mutex);
1da177e4 2887
ea5b6382 2888 /* Set ISP-type information. */
2889 qla2x00_set_isp_flags(ha);
ca79cf66
DG		 2890
2891 /* Set EEH reset type to fundamental if required by hba */
95676112 2892 if (IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha) ||
ecc89f25 2893 IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))
ca79cf66 2894 pdev->needs_freset = 1;
ca79cf66 2895
cba1e47f
CD		 2896 ha->prev_topology = 0;
2897 ha->init_cb_size = sizeof(init_cb_t);
2898 ha->link_data_rate = PORT_SPEED_UNKNOWN;
2899 ha->optrom_size = OPTROM_SIZE_2300;
d1e3635a 2900 ha->max_exchg = FW_MAX_EXCHANGES_CNT;
b2000805
QT		 2901 atomic_set(&ha->num_pend_mbx_stage1, 0);
2902 atomic_set(&ha->num_pend_mbx_stage2, 0);
2903 atomic_set(&ha->num_pend_mbx_stage3, 0);
8b4673ba
QT		 2904 atomic_set(&ha->zio_threshold, DEFAULT_ZIO_THRESHOLD);
2905 ha->last_zio_threshold = DEFAULT_ZIO_THRESHOLD;
cba1e47f 2906
abbd8870 2907 /* Assign ISP specific operations. */
1da177e4 2908 if (IS_QLA2100(ha)) {
642ef983 2909 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
1da177e4 2910 ha->mbx_count = MAILBOX_REGISTER_COUNT_2100;
e315cd28
AC		 2911 req_length = REQUEST_ENTRY_CNT_2100;
2912 rsp_length = RESPONSE_ENTRY_CNT_2100;
2913 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
abbd8870 2914 ha->gid_list_info_size = 4;
3a03eb79
AV		 2915 ha->flash_conf_off = ~0;
2916 ha->flash_data_off = ~0;
2917 ha->nvram_conf_off = ~0;
2918 ha->nvram_data_off = ~0;
fd34f556 2919 ha->isp_ops = &qla2100_isp_ops;
1da177e4 2920 } else if (IS_QLA2200(ha)) {
642ef983 2921 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
67ddda35 2922 ha->mbx_count = MAILBOX_REGISTER_COUNT_2200;
e315cd28
AC		 2923 req_length = REQUEST_ENTRY_CNT_2200;
2924 rsp_length = RESPONSE_ENTRY_CNT_2100;
2925 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
abbd8870 2926 ha->gid_list_info_size = 4;
3a03eb79
AV		 2927 ha->flash_conf_off = ~0;
2928 ha->flash_data_off = ~0;
2929 ha->nvram_conf_off = ~0;
2930 ha->nvram_data_off = ~0;
fd34f556 2931 ha->isp_ops = &qla2100_isp_ops;
fca29703 2932 } else if (IS_QLA23XX(ha)) {
642ef983 2933 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
1da177e4 2934 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2935 req_length = REQUEST_ENTRY_CNT_2200;
2936 rsp_length = RESPONSE_ENTRY_CNT_2300;
2937 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
abbd8870 2938 ha->gid_list_info_size = 6;
854165f4 2939 if (IS_QLA2322(ha) || IS_QLA6322(ha))
2940 ha->optrom_size = OPTROM_SIZE_2322;
3a03eb79
AV		 2941 ha->flash_conf_off = ~0;
2942 ha->flash_data_off = ~0;
2943 ha->nvram_conf_off = ~0;
2944 ha->nvram_data_off = ~0;
fd34f556 2945 ha->isp_ops = &qla2300_isp_ops;
4d4df193 2946 } else if (IS_QLA24XX_TYPE(ha)) {
642ef983 2947 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
fca29703 2948 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2949 req_length = REQUEST_ENTRY_CNT_24XX;
2950 rsp_length = RESPONSE_ENTRY_CNT_2300;
2d70c103 2951 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
e315cd28 2952 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2c3dfe3f 2953 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
fca29703 2954 ha->gid_list_info_size = 8;
854165f4 2955 ha->optrom_size = OPTROM_SIZE_24XX;
73208dfd 2956 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX;
fd34f556 2957 ha->isp_ops = &qla24xx_isp_ops;
3a03eb79
AV		 2958 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2959 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2960 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2961 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
c3a2f0df 2962 } else if (IS_QLA25XX(ha)) {
642ef983 2963 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
c3a2f0df 2964 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2965 req_length = REQUEST_ENTRY_CNT_24XX;
2966 rsp_length = RESPONSE_ENTRY_CNT_2300;
2d70c103 2967 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
e315cd28 2968 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
c3a2f0df 2969 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
c3a2f0df
AV		 2970 ha->gid_list_info_size = 8;
2971 ha->optrom_size = OPTROM_SIZE_25XX;
73208dfd 2972 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
c3a2f0df 2973 ha->isp_ops = &qla25xx_isp_ops;
3a03eb79
AV		 2974 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2975 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2976 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2977 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
2978 } else if (IS_QLA81XX(ha)) {
642ef983 2979 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3a03eb79
AV		 2980 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2981 req_length = REQUEST_ENTRY_CNT_24XX;
2982 rsp_length = RESPONSE_ENTRY_CNT_2300;
aa230bc5 2983 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
3a03eb79
AV		 2984 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2985 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2986 ha->gid_list_info_size = 8;
2987 ha->optrom_size = OPTROM_SIZE_81XX;
40859ae5 2988 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3a03eb79
AV		 2989 ha->isp_ops = &qla81xx_isp_ops;
2990 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2991 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2992 ha->nvram_conf_off = ~0;
2993 ha->nvram_data_off = ~0;
a9083016 2994 } else if (IS_QLA82XX(ha)) {
642ef983 2995 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
a9083016
GM		 2996 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2997 req_length = REQUEST_ENTRY_CNT_82XX;
2998 rsp_length = RESPONSE_ENTRY_CNT_82XX;
2999 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
3000 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
3001 ha->gid_list_info_size = 8;
3002 ha->optrom_size = OPTROM_SIZE_82XX;
087c621e 3003 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
a9083016
GM		 3004 ha->isp_ops = &qla82xx_isp_ops;
3005 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
3006 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
3007 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
3008 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
7ec0effd
AD		 3009 } else if (IS_QLA8044(ha)) {
3010 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3011 ha->mbx_count = MAILBOX_REGISTER_COUNT;
3012 req_length = REQUEST_ENTRY_CNT_82XX;
3013 rsp_length = RESPONSE_ENTRY_CNT_82XX;
3014 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
3015 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
3016 ha->gid_list_info_size = 8;
3017 ha->optrom_size = OPTROM_SIZE_83XX;
3018 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3019 ha->isp_ops = &qla8044_isp_ops;
3020 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
3021 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
3022 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
3023 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
6246b8a1 3024 } else if (IS_QLA83XX(ha)) {
7d613ac6 3025 ha->portnum = PCI_FUNC(ha->pdev->devfn);
642ef983 3026 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
6246b8a1 3027 ha->mbx_count = MAILBOX_REGISTER_COUNT;
f2ea653f 3028 req_length = REQUEST_ENTRY_CNT_83XX;
e7b42e33 3029 rsp_length = RESPONSE_ENTRY_CNT_83XX;
b8aa4bdf 3030 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
6246b8a1
GM		 3031 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
3032 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
3033 ha->gid_list_info_size = 8;
3034 ha->optrom_size = OPTROM_SIZE_83XX;
3035 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3036 ha->isp_ops = &qla83xx_isp_ops;
3037 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
3038 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
3039 ha->nvram_conf_off = ~0;
3040 ha->nvram_data_off = ~0;
8ae6d9c7
GM		 3041 } else if (IS_QLAFX00(ha)) {
3042 ha->max_fibre_devices = MAX_FIBRE_DEVICES_FX00;
3043 ha->mbx_count = MAILBOX_REGISTER_COUNT_FX00;
3044 ha->aen_mbx_count = AEN_MAILBOX_REGISTER_COUNT_FX00;
3045 req_length = REQUEST_ENTRY_CNT_FX00;
3046 rsp_length = RESPONSE_ENTRY_CNT_FX00;
8ae6d9c7
GM		 3047 ha->isp_ops = &qlafx00_isp_ops;
3048 ha->port_down_retry_count = 30; /* default value */
3049 ha->mr.fw_hbt_cnt = QLAFX00_HEARTBEAT_INTERVAL;
3050 ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL;
71e56003 3051 ha->mr.fw_critemp_timer_tick = QLAFX00_CRITEMP_INTERVAL;
8ae6d9c7 3052 ha->mr.fw_hbt_en = 1;
e8f5e95d
AB		 3053 ha->mr.host_info_resend = false;
3054 ha->mr.hinfo_resend_timer_tick = QLAFX00_HINFO_RESEND_INTERVAL;
f73cb695
CD		 3055 } else if (IS_QLA27XX(ha)) {
3056 ha->portnum = PCI_FUNC(ha->pdev->devfn);
3057 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3058 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e7b42e33
QT		 3059 req_length = REQUEST_ENTRY_CNT_83XX;
3060 rsp_length = RESPONSE_ENTRY_CNT_83XX;
b20f02e1 3061 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
f73cb695
CD		 3062 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
3063 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
3064 ha->gid_list_info_size = 8;
3065 ha->optrom_size = OPTROM_SIZE_83XX;
3066 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3067 ha->isp_ops = &qla27xx_isp_ops;
3068 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
3069 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
3070 ha->nvram_conf_off = ~0;
3071 ha->nvram_data_off = ~0;
ecc89f25
JC		 3072 } else if (IS_QLA28XX(ha)) {
3073 ha->portnum = PCI_FUNC(ha->pdev->devfn);
3074 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3075 ha->mbx_count = MAILBOX_REGISTER_COUNT;
3076 req_length = REQUEST_ENTRY_CNT_24XX;
3077 rsp_length = RESPONSE_ENTRY_CNT_2300;
3078 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
3079 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
3080 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
3081 ha->gid_list_info_size = 8;
3082 ha->optrom_size = OPTROM_SIZE_28XX;
3083 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3084 ha->isp_ops = &qla27xx_isp_ops;
3085 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_28XX;
3086 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_28XX;
3087 ha->nvram_conf_off = ~0;
3088 ha->nvram_data_off = ~0;
1da177e4 3089 }
6246b8a1 3090
7c3df132
SK		 3091 ql_dbg_pci(ql_dbg_init, pdev, 0x001e,
3092 "mbx_count=%d, req_length=%d, "
3093 "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, "
642ef983
CD		 3094 "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, "
3095 "max_fibre_devices=%d.\n",
7c3df132
SK		 3096 ha->mbx_count, req_length, rsp_length, ha->max_loop_id,
3097 ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size,
642ef983 3098 ha->nvram_npiv_size, ha->max_fibre_devices);
7c3df132
SK		 3099 ql_dbg_pci(ql_dbg_init, pdev, 0x001f,
3100 "isp_ops=%p, flash_conf_off=%d, "
3101 "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n",
3102 ha->isp_ops, ha->flash_conf_off, ha->flash_data_off,
3103 ha->nvram_conf_off, ha->nvram_data_off);
706f457d
GM		 3104
3105 /* Configure PCI I/O space */
3106 ret = ha->isp_ops->iospace_config(ha);
3107 if (ret)
0a63ad12 3108 goto iospace_config_failed;
706f457d
GM		 3109
3110 ql_log_pci(ql_log_info, pdev, 0x001d,
3111 "Found an ISP%04X irq %d iobase 0x%p.\n",
3112 pdev->device, pdev->irq, ha->iobase);
6c2f527c 3113 mutex_init(&ha->vport_lock);
d7459527 3114 mutex_init(&ha->mq_lock);
0b05a1f0
MB		 3115 init_completion(&ha->mbx_cmd_comp);
3116 complete(&ha->mbx_cmd_comp);
3117 init_completion(&ha->mbx_intr_comp);
23f2ebd1 3118 init_completion(&ha->dcbx_comp);
f356bef1 3119 init_completion(&ha->lb_portup_comp);
1da177e4 3120
2c3dfe3f 3121 set_bit(0, (unsigned long *) ha->vp_idx_map);
1da177e4 3122
53303c42 3123 qla2x00_config_dma_addressing(ha);
7c3df132
SK		 3124 ql_dbg_pci(ql_dbg_init, pdev, 0x0020,
3125 "64 Bit addressing is %s.\n",
3126 ha->flags.enable_64bit_addressing ? "enable" :
3127 "disable");
73208dfd 3128 ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp);
b2a72ec3 3129 if (ret) {
7c3df132
SK		 3130 ql_log_pci(ql_log_fatal, pdev, 0x0031,
3131 "Failed to allocate memory for adapter, aborting.\n");
1da177e4 3132
e315cd28
AC		 3133 goto probe_hw_failed;
3134 }
3135
73208dfd 3136 req->max_q_depth = MAX_Q_DEPTH;
e315cd28 3137 if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU)
73208dfd
AC		 3138 req->max_q_depth = ql2xmaxqdepth;
3139
e315cd28
AC		 3140
3141 base_vha = qla2x00_create_host(sht, ha);
3142 if (!base_vha) {
a1541d5a 3143 ret = -ENOMEM;
e315cd28 3144 goto probe_hw_failed;
1da177e4
LT		 3145 }
3146
e315cd28 3147 pci_set_drvdata(pdev, base_vha);
6b383979 3148 set_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags);
e315cd28 3149
e315cd28 3150 host = base_vha->host;
2afa19a9 3151 base_vha->req = req;
73208dfd 3152 if (IS_QLA2XXX_MIDTYPE(ha))
f6602f3b
QT		 3153 base_vha->mgmt_svr_loop_id =
3154 qla2x00_reserve_mgmt_server_loop_id(base_vha);
73208dfd 3155 else
e315cd28
AC		 3156 base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER +
3157 base_vha->vp_idx;
58548cb5 3158
8ae6d9c7
GM		 3159 /* Setup fcport template structure. */
3160 ha->mr.fcport.vha = base_vha;
3161 ha->mr.fcport.port_type = FCT_UNKNOWN;
3162 ha->mr.fcport.loop_id = FC_NO_LOOP_ID;
3163 qla2x00_set_fcport_state(&ha->mr.fcport, FCS_UNCONFIGURED);
3164 ha->mr.fcport.supported_classes = FC_COS_UNSPECIFIED;
3165 ha->mr.fcport.scan_state = 1;
3166
58548cb5
GM		 3167 /* Set the SG table size based on ISP type */
3168 if (!IS_FWI2_CAPABLE(ha)) {
3169 if (IS_QLA2100(ha))
3170 host->sg_tablesize = 32;
3171 } else {
3172 if (!IS_QLA82XX(ha))
3173 host->sg_tablesize = QLA_SG_ALL;
3174 }
642ef983 3175 host->max_id = ha->max_fibre_devices;
e315cd28
AC		 3176 host->cmd_per_lun = 3;
3177 host->unique_id = host->host_no;
e02587d7 3178 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif)
0c470874
AE		 3179 host->max_cmd_len = 32;
3180 else
3181 host->max_cmd_len = MAX_CMDSZ;
e315cd28 3182 host->max_channel = MAX_BUSES - 1;
755f516b
HR		 3183 /* Older HBAs support only 16-bit LUNs */
3184 if (!IS_QLAFX00(ha) && !IS_FWI2_CAPABLE(ha) &&
3185 ql2xmaxlun > 0xffff)
3186 host->max_lun = 0xffff;
3187 else
3188 host->max_lun = ql2xmaxlun;
e315cd28 3189 host->transportt = qla2xxx_transport_template;
9a069e19 3190 sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC);
e315cd28 3191
7c3df132
SK		 3192 ql_dbg(ql_dbg_init, base_vha, 0x0033,
3193 "max_id=%d this_id=%d "
3194 "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d "
1abf635d 3195 "max_lun=%llu transportt=%p, vendor_id=%llu.\n", host->max_id,
7c3df132
SK		 3196 host->this_id, host->cmd_per_lun, host->unique_id,
3197 host->max_cmd_len, host->max_channel, host->max_lun,
3198 host->transportt, sht->vendor_id);
3199
1010f21e
HM		 3200 INIT_WORK(&base_vha->iocb_work, qla2x00_iocb_work_fn);
3201
d7459527
MH		 3202 /* Set up the irqs */
3203 ret = qla2x00_request_irqs(ha, rsp);
3204 if (ret)
6a2cf8d3 3205 goto probe_failed;
d7459527 3206
9a347ff4 3207 /* Alloc arrays of request and response ring ptrs */
6d634067
BK		 3208 ret = qla2x00_alloc_queues(ha, req, rsp);
3209 if (ret) {
9a347ff4
CD		 3210 ql_log(ql_log_fatal, base_vha, 0x003d,
3211 "Failed to allocate memory for queue pointers..."
3212 "aborting.\n");
6a2cf8d3 3213 goto probe_failed;
9a347ff4
CD		 3214 }
3215
f664a3cc 3216 if (ha->mqenable) {
5601236b
MH		 3217 /* number of hardware queues supported by blk/scsi-mq*/
3218 host->nr_hw_queues = ha->max_qpairs;
3219
3220 ql_dbg(ql_dbg_init, base_vha, 0x0192,
3221 "blk/scsi-mq enabled, HW queues = %d.\n", host->nr_hw_queues);
c38d1baf
HM		 3222 } else {
3223 if (ql2xnvmeenable) {
3224 host->nr_hw_queues = ha->max_qpairs;
3225 ql_dbg(ql_dbg_init, base_vha, 0x0194,
3226 "FC-NVMe support is enabled, HW queues=%d\n",
3227 host->nr_hw_queues);
3228 } else {
3229 ql_dbg(ql_dbg_init, base_vha, 0x0193,
3230 "blk/scsi-mq disabled.\n");
3231 }
3232 }
5601236b 3233
2d70c103 3234 qlt_probe_one_stage1(base_vha, ha);
9a347ff4 3235
90a86fc0
JC		 3236 pci_save_state(pdev);
3237
9a347ff4 3238 /* Assign back pointers */
2afa19a9
AC		 3239 rsp->req = req;
3240 req->rsp = rsp;
9a347ff4 3241
8ae6d9c7
GM		 3242 if (IS_QLAFX00(ha)) {
3243 ha->rsp_q_map[0] = rsp;
3244 ha->req_q_map[0] = req;
3245 set_bit(0, ha->req_qid_map);
3246 set_bit(0, ha->rsp_qid_map);
3247 }
3248
08029990
AV		 3249 /* FWI2-capable only. */
3250 req->req_q_in = &ha->iobase->isp24.req_q_in;
3251 req->req_q_out = &ha->iobase->isp24.req_q_out;
3252 rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in;
3253 rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out;
ecc89f25
JC		 3254 if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha) ||
3255 IS_QLA28XX(ha)) {
08029990
AV		 3256 req->req_q_in = &ha->mqiobase->isp25mq.req_q_in;
3257 req->req_q_out = &ha->mqiobase->isp25mq.req_q_out;
3258 rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in;
3259 rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out;
17d98630
AC		 3260 }
3261
8ae6d9c7
GM		 3262 if (IS_QLAFX00(ha)) {
3263 req->req_q_in = &ha->iobase->ispfx00.req_q_in;
3264 req->req_q_out = &ha->iobase->ispfx00.req_q_out;
3265 rsp->rsp_q_in = &ha->iobase->ispfx00.rsp_q_in;
3266 rsp->rsp_q_out = &ha->iobase->ispfx00.rsp_q_out;
3267 }
3268
7ec0effd 3269 if (IS_P3P_TYPE(ha)) {
a9083016
GM		 3270 req->req_q_out = &ha->iobase->isp82.req_q_out[0];
3271 rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0];
3272 rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0];
3273 }
3274
7c3df132
SK		 3275 ql_dbg(ql_dbg_multiq, base_vha, 0xc009,
3276 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
3277 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
3278 ql_dbg(ql_dbg_multiq, base_vha, 0xc00a,
3279 "req->req_q_in=%p req->req_q_out=%p "
3280 "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
3281 req->req_q_in, req->req_q_out,
3282 rsp->rsp_q_in, rsp->rsp_q_out);
3283 ql_dbg(ql_dbg_init, base_vha, 0x003e,
3284 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
3285 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
3286 ql_dbg(ql_dbg_init, base_vha, 0x003f,
3287 "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
3288 req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out);
1da177e4 3289
d48cc67c 3290 ha->wq = alloc_workqueue("qla2xxx_wq", 0, 0);
3291
8ae6d9c7 3292 if (ha->isp_ops->initialize_adapter(base_vha)) {
7c3df132
SK		 3293 ql_log(ql_log_fatal, base_vha, 0x00d6,
3294 "Failed to initialize adapter - Adapter flags %x.\n",
3295 base_vha->device_flags);
1da177e4 3296
a9083016
GM		 3297 if (IS_QLA82XX(ha)) {
3298 qla82xx_idc_lock(ha);
3299 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 3300 QLA8XXX_DEV_FAILED);
a9083016 3301 qla82xx_idc_unlock(ha);
7c3df132
SK		 3302 ql_log(ql_log_fatal, base_vha, 0x00d7,
3303 "HW State: FAILED.\n");
7ec0effd
AD		 3304 } else if (IS_QLA8044(ha)) {
3305 qla8044_idc_lock(ha);
3306 qla8044_wr_direct(base_vha,
3307 QLA8044_CRB_DEV_STATE_INDEX,
3308 QLA8XXX_DEV_FAILED);
3309 qla8044_idc_unlock(ha);
3310 ql_log(ql_log_fatal, base_vha, 0x0150,
3311 "HW State: FAILED.\n");
a9083016
GM		 3312 }
3313
a1541d5a 3314 ret = -ENODEV;
1da177e4
LT		 3315 goto probe_failed;
3316 }
3317
3b1bef64
CD		 3318 if (IS_QLAFX00(ha))
3319 host->can_queue = QLAFX00_MAX_CANQUEUE;
3320 else
3321 host->can_queue = req->num_outstanding_cmds - 10;
3322
3323 ql_dbg(ql_dbg_init, base_vha, 0x0032,
3324 "can_queue=%d, req=%p, mgmt_svr_loop_id=%d, sg_tablesize=%d.\n",
3325 host->can_queue, base_vha->req,
3326 base_vha->mgmt_svr_loop_id, host->sg_tablesize);
3327
e326d22a 3328 if (ha->mqenable) {
e326d22a 3329 bool startit = false;
e326d22a 3330
f664a3cc 3331 if (QLA_TGT_MODE_ENABLED())
e326d22a 3332 startit = false;
e326d22a 3333
f664a3cc 3334 if (ql2x_ini_mode == QLA2XXX_INI_MODE_ENABLED)
e326d22a 3335 startit = true;
e326d22a 3336
f664a3cc
JA		 3337 /* Create start of day qpairs for Block MQ */
3338 for (i = 0; i < ha->max_qpairs; i++)
3339 qla2xxx_create_qpair(base_vha, 5, 0, startit);
5601236b 3340 }
68ca949c 3341
cbc8eb67
AV		 3342 if (ha->flags.running_gold_fw)
3343 goto skip_dpc;
3344
1da177e4
LT		 3345 /*
3346 * Startup the kernel thread for this host adapter
3347 */
39a11240 3348 ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha,
7c3df132 3349 "%s_dpc", base_vha->host_str);
39a11240 3350 if (IS_ERR(ha->dpc_thread)) {
7c3df132
SK		 3351 ql_log(ql_log_fatal, base_vha, 0x00ed,
3352 "Failed to start DPC thread.\n");
39a11240 3353 ret = PTR_ERR(ha->dpc_thread);
e2532b4a 3354 ha->dpc_thread = NULL;
1da177e4
LT		 3355 goto probe_failed;
3356 }
7c3df132
SK		 3357 ql_dbg(ql_dbg_init, base_vha, 0x00ee,
3358 "DPC thread started successfully.\n");
1da177e4 3359
2d70c103
NB		 3360 /*
3361 * If we're not coming up in initiator mode, we might sit for
3362 * a while without waking up the dpc thread, which leads to a
3363 * stuck process warning. So just kick the dpc once here and
3364 * let the kthread start (and go back to sleep in qla2x00_do_dpc).
3365 */
3366 qla2xxx_wake_dpc(base_vha);
3367
f3ddac19
CD		 3368 INIT_WORK(&ha->board_disable, qla2x00_disable_board_on_pci_error);
3369
81178772
SK		 3370 if (IS_QLA8031(ha) || IS_MCTP_CAPABLE(ha)) {
3371 sprintf(wq_name, "qla2xxx_%lu_dpc_lp_wq", base_vha->host_no);
3372 ha->dpc_lp_wq = create_singlethread_workqueue(wq_name);
3373 INIT_WORK(&ha->idc_aen, qla83xx_service_idc_aen);
3374
3375 sprintf(wq_name, "qla2xxx_%lu_dpc_hp_wq", base_vha->host_no);
3376 ha->dpc_hp_wq = create_singlethread_workqueue(wq_name);
3377 INIT_WORK(&ha->nic_core_reset, qla83xx_nic_core_reset_work);
3378 INIT_WORK(&ha->idc_state_handler,
3379 qla83xx_idc_state_handler_work);
3380 INIT_WORK(&ha->nic_core_unrecoverable,
3381 qla83xx_nic_core_unrecoverable_work);
3382 }
3383
cbc8eb67 3384skip_dpc:
e315cd28
AC		 3385 list_add_tail(&base_vha->list, &ha->vp_list);
3386 base_vha->host->irq = ha->pdev->irq;
1da177e4
LT		 3387
3388 /* Initialized the timer */
8e5f4ba0 3389 qla2x00_start_timer(base_vha, WATCH_INTERVAL);
7c3df132
SK		 3390 ql_dbg(ql_dbg_init, base_vha, 0x00ef,
3391 "Started qla2x00_timer with "
3392 "interval=%d.\n", WATCH_INTERVAL);
3393 ql_dbg(ql_dbg_init, base_vha, 0x00f0,
3394 "Detected hba at address=%p.\n",
3395 ha);
d19044c3 3396
e02587d7 3397 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) {
bad75002 3398 if (ha->fw_attributes & BIT_4) {
9e522cd8 3399 int prot = 0, guard;
bad75002 3400 base_vha->flags.difdix_supported = 1;
7c3df132
SK		 3401 ql_dbg(ql_dbg_init, base_vha, 0x00f1,
3402 "Registering for DIF/DIX type 1 and 3 protection.\n");
8cb2049c
AE		 3403 if (ql2xenabledif == 1)
3404 prot = SHOST_DIX_TYPE0_PROTECTION;
7855d2ba
MP		 3405 if (ql2xprotmask)
3406 scsi_host_set_prot(host, ql2xprotmask);
3407 else
3408 scsi_host_set_prot(host,
3409 prot | SHOST_DIF_TYPE1_PROTECTION
3410 | SHOST_DIF_TYPE2_PROTECTION
3411 | SHOST_DIF_TYPE3_PROTECTION
3412 | SHOST_DIX_TYPE1_PROTECTION
3413 | SHOST_DIX_TYPE2_PROTECTION
3414 | SHOST_DIX_TYPE3_PROTECTION);
9e522cd8
AE		 3415
3416 guard = SHOST_DIX_GUARD_CRC;
3417
3418 if (IS_PI_IPGUARD_CAPABLE(ha) &&
3419 (ql2xenabledif > 1 || IS_PI_DIFB_DIX0_CAPABLE(ha)))
3420 guard |= SHOST_DIX_GUARD_IP;
3421
7855d2ba
MP		 3422 if (ql2xprotguard)
3423 scsi_host_set_guard(host, ql2xprotguard);
3424 else
3425 scsi_host_set_guard(host, guard);
bad75002
AE		 3426 } else
3427 base_vha->flags.difdix_supported = 0;
3428 }
3429
a9083016
GM		 3430 ha->isp_ops->enable_intrs(ha);
3431
1fe19ee4
AB		 3432 if (IS_QLAFX00(ha)) {
3433 ret = qlafx00_fx_disc(base_vha,
3434 &base_vha->hw->mr.fcport, FXDISC_GET_CONFIG_INFO);
3435 host->sg_tablesize = (ha->mr.extended_io_enabled) ?
3436 QLA_SG_ALL : 128;
3437 }
3438
a1541d5a
AV		 3439 ret = scsi_add_host(host, &pdev->dev);
3440 if (ret)
3441 goto probe_failed;
3442
1486400f
MR		 3443 base_vha->flags.init_done = 1;
3444 base_vha->flags.online = 1;
edaa5c74 3445 ha->prev_minidump_failed = 0;
1486400f 3446
7c3df132
SK		 3447 ql_dbg(ql_dbg_init, base_vha, 0x00f2,
3448 "Init done and hba is online.\n");
3449
726b8548
QT		 3450 if (qla_ini_mode_enabled(base_vha) ||
3451 qla_dual_mode_enabled(base_vha))
2d70c103
NB		 3452 scsi_scan_host(host);
3453 else
3454 ql_dbg(ql_dbg_init, base_vha, 0x0122,
3455 "skipping scsi_scan_host() for non-initiator port\n");
1e99e33a 3456
e315cd28 3457 qla2x00_alloc_sysfs_attr(base_vha);
a1541d5a 3458
8ae6d9c7 3459 if (IS_QLAFX00(ha)) {
8ae6d9c7
GM		 3460 ret = qlafx00_fx_disc(base_vha,
3461 &base_vha->hw->mr.fcport, FXDISC_GET_PORT_INFO);
3462
3463 /* Register system information */
3464 ret = qlafx00_fx_disc(base_vha,
3465 &base_vha->hw->mr.fcport, FXDISC_REG_HOST_INFO);
3466 }
3467
e315cd28 3468 qla2x00_init_host_attr(base_vha);
a1541d5a 3469
e315cd28 3470 qla2x00_dfs_setup(base_vha);
df613b96 3471
03eb912a
AB		 3472 ql_log(ql_log_info, base_vha, 0x00fb,
3473 "QLogic %s - %s.\n", ha->model_number, ha->model_desc);
7c3df132
SK		 3474 ql_log(ql_log_info, base_vha, 0x00fc,
3475 "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n",
3476 pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info),
3477 pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-',
3478 base_vha->host_no,
df57caba 3479 ha->isp_ops->fw_version_str(base_vha, fw_str, sizeof(fw_str)));
1da177e4 3480
2d70c103
NB		 3481 qlt_add_target(ha, base_vha);
3482
6b383979 3483 clear_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags);
a29b3dd7
JC		 3484
3485 if (test_bit(UNLOADING, &base_vha->dpc_flags))
3486 return -ENODEV;
3487
e4e3a2ce
QT		 3488 if (ha->flags.detected_lr_sfp) {
3489 ql_log(ql_log_info, base_vha, 0xffff,
3490 "Reset chip to pick up LR SFP setting\n");
3491 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
3492 qla2xxx_wake_dpc(base_vha);
3493 }
3494
1da177e4
LT		 3495 return 0;
3496
3497probe_failed:
b9978769
AV		 3498 if (base_vha->timer_active)
3499 qla2x00_stop_timer(base_vha);
3500 base_vha->flags.online = 0;
3501 if (ha->dpc_thread) {
3502 struct task_struct *t = ha->dpc_thread;
3503
3504 ha->dpc_thread = NULL;
3505 kthread_stop(t);
3506 }
3507
e315cd28 3508 qla2x00_free_device(base_vha);
e315cd28 3509 scsi_host_put(base_vha->host);
6d634067
BK		 3510 /*
3511 * Need to NULL out local req/rsp after
3512 * qla2x00_free_device => qla2x00_free_queues frees
3513 * what these are pointing to. Or else we'll
3514 * fall over below in qla2x00_free_req/rsp_que.
3515 */
3516 req = NULL;
3517 rsp = NULL;
1da177e4 3518
e315cd28 3519probe_hw_failed:
d64d6c56 3520 qla2x00_mem_free(ha);
3521 qla2x00_free_req_que(ha, req);
3522 qla2x00_free_rsp_que(ha, rsp);
1a2fbf18
JL		 3523 qla2x00_clear_drv_active(ha);
3524
0a63ad12 3525iospace_config_failed:
7ec0effd 3526 if (IS_P3P_TYPE(ha)) {
0a63ad12 3527 if (!ha->nx_pcibase)
f73cb695 3528 iounmap((device_reg_t *)ha->nx_pcibase);
a9083016 3529 if (!ql2xdbwr)
f73cb695 3530 iounmap((device_reg_t *)ha->nxdb_wr_ptr);
a9083016
GM		 3531 } else {
3532 if (ha->iobase)
3533 iounmap(ha->iobase);
8ae6d9c7
GM		 3534 if (ha->cregbase)
3535 iounmap(ha->cregbase);
a9083016 3536 }
e315cd28
AC		 3537 pci_release_selected_regions(ha->pdev, ha->bars);
3538 kfree(ha);
1da177e4 3539
ddff7ed4 3540disable_device:
e315cd28 3541 pci_disable_device(pdev);
a1541d5a 3542 return ret;
1da177e4 3543}
1da177e4 3544
e30d1756
MI		 3545static void
3546qla2x00_shutdown(struct pci_dev *pdev)
3547{
3548 scsi_qla_host_t *vha;
3549 struct qla_hw_data *ha;
3550
3551 vha = pci_get_drvdata(pdev);
3552 ha = vha->hw;
3553
efdb5760
SC		 3554 ql_log(ql_log_info, vha, 0xfffa,
3555 "Adapter shutdown\n");
3556
3557 /*
3558 * Prevent future board_disable and wait
3559 * until any pending board_disable has completed.
3560 */
3561 set_bit(PFLG_DRIVER_REMOVING, &vha->pci_flags);
3562 cancel_work_sync(&ha->board_disable);
3563
3564 if (!atomic_read(&pdev->enable_cnt))
3565 return;
3566
42479343
AB		 3567 /* Notify ISPFX00 firmware */
3568 if (IS_QLAFX00(ha))
3569 qlafx00_driver_shutdown(vha, 20);
3570
e30d1756
MI		 3571 /* Turn-off FCE trace */
3572 if (ha->flags.fce_enabled) {
3573 qla2x00_disable_fce_trace(vha, NULL, NULL);
3574 ha->flags.fce_enabled = 0;
3575 }
3576
3577 /* Turn-off EFT trace */
3578 if (ha->eft)
3579 qla2x00_disable_eft_trace(vha);
3580
ecc89f25
JC		 3581 if (IS_QLA25XX(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) ||
3582 IS_QLA28XX(ha)) {
3407fc37
QT		 3583 if (ha->flags.fw_started)
3584 qla2x00_abort_isp_cleanup(vha);
3585 } else {
3586 /* Stop currently executing firmware. */
3587 qla2x00_try_to_stop_firmware(vha);
3588 }
e30d1756
MI		 3589
3590 /* Turn adapter off line */
3591 vha->flags.online = 0;
3592
3593 /* turn-off interrupts on the card */
3594 if (ha->interrupts_on) {
3595 vha->flags.init_done = 0;
3596 ha->isp_ops->disable_intrs(ha);
3597 }
3598
3599 qla2x00_free_irqs(vha);
3600
3601 qla2x00_free_fw_dump(ha);
61d41f61 3602
61d41f61 3603 pci_disable_device(pdev);
efdb5760
SC		 3604 ql_log(ql_log_info, vha, 0xfffe,
3605 "Adapter shutdown successfully.\n");
e30d1756
MI		 3606}
3607
fe1b806f 3608/* Deletes all the virtual ports for a given ha */
4c993f76 3609static void
fe1b806f 3610qla2x00_delete_all_vps(struct qla_hw_data *ha, scsi_qla_host_t *base_vha)
1da177e4 3611{
fe1b806f 3612 scsi_qla_host_t *vha;
feafb7b1 3613 unsigned long flags;
e315cd28 3614
43ebf16d
AE		 3615 mutex_lock(&ha->vport_lock);
3616 while (ha->cur_vport_count) {
43ebf16d 3617 spin_lock_irqsave(&ha->vport_slock, flags);
feafb7b1 3618
43ebf16d
AE		 3619 BUG_ON(base_vha->list.next == &ha->vp_list);
3620 /* This assumes first entry in ha->vp_list is always base vha */
3621 vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list);
52c82823 3622 scsi_host_get(vha->host);
feafb7b1 3623
43ebf16d
AE		 3624 spin_unlock_irqrestore(&ha->vport_slock, flags);
3625 mutex_unlock(&ha->vport_lock);
3626
5e6803b4
HM		 3627 qla_nvme_delete(vha);
3628
43ebf16d
AE		 3629 fc_vport_terminate(vha->fc_vport);
3630 scsi_host_put(vha->host);
feafb7b1 3631
43ebf16d 3632 mutex_lock(&ha->vport_lock);
e315cd28 3633 }
43ebf16d 3634 mutex_unlock(&ha->vport_lock);
fe1b806f 3635}
1da177e4 3636
fe1b806f
CD		 3637/* Stops all deferred work threads */
3638static void
3639qla2x00_destroy_deferred_work(struct qla_hw_data *ha)
3640{
7d613ac6
SV		 3641 /* Cancel all work and destroy DPC workqueues */
3642 if (ha->dpc_lp_wq) {
3643 cancel_work_sync(&ha->idc_aen);
3644 destroy_workqueue(ha->dpc_lp_wq);
3645 ha->dpc_lp_wq = NULL;
3646 }
3647
3648 if (ha->dpc_hp_wq) {
3649 cancel_work_sync(&ha->nic_core_reset);
3650 cancel_work_sync(&ha->idc_state_handler);
3651 cancel_work_sync(&ha->nic_core_unrecoverable);
3652 destroy_workqueue(ha->dpc_hp_wq);
3653 ha->dpc_hp_wq = NULL;
3654 }
3655
b9978769
AV		 3656 /* Kill the kernel thread for this host */
3657 if (ha->dpc_thread) {
3658 struct task_struct *t = ha->dpc_thread;
3659
3660 /*
3661 * qla2xxx_wake_dpc checks for ->dpc_thread
3662 * so we need to zero it out.
3663 */
3664 ha->dpc_thread = NULL;
3665 kthread_stop(t);
3666 }
fe1b806f 3667}
1da177e4 3668
fe1b806f
CD		 3669static void
3670qla2x00_unmap_iobases(struct qla_hw_data *ha)
3671{
a9083016 3672 if (IS_QLA82XX(ha)) {
b963752f 3673
f73cb695 3674 iounmap((device_reg_t *)ha->nx_pcibase);
a9083016 3675 if (!ql2xdbwr)
f73cb695 3676 iounmap((device_reg_t *)ha->nxdb_wr_ptr);
a9083016
GM		 3677 } else {
3678 if (ha->iobase)
3679 iounmap(ha->iobase);
1da177e4 3680
8ae6d9c7
GM		 3681 if (ha->cregbase)
3682 iounmap(ha->cregbase);
3683
a9083016
GM		 3684 if (ha->mqiobase)
3685 iounmap(ha->mqiobase);
6246b8a1 3686
ecc89f25
JC		 3687 if ((IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) &&
3688 ha->msixbase)
6246b8a1 3689 iounmap(ha->msixbase);
a9083016 3690 }
fe1b806f
CD		 3691}
3692
3693static void
db7157d4 3694qla2x00_clear_drv_active(struct qla_hw_data *ha)
fe1b806f 3695{
fe1b806f
CD		 3696 if (IS_QLA8044(ha)) {
3697 qla8044_idc_lock(ha);
c41afc9a 3698 qla8044_clear_drv_active(ha);
fe1b806f
CD		 3699 qla8044_idc_unlock(ha);
3700 } else if (IS_QLA82XX(ha)) {
3701 qla82xx_idc_lock(ha);
3702 qla82xx_clear_drv_active(ha);
3703 qla82xx_idc_unlock(ha);
3704 }
3705}
3706
3707static void
3708qla2x00_remove_one(struct pci_dev *pdev)
3709{
3710 scsi_qla_host_t *base_vha;
3711 struct qla_hw_data *ha;
3712
beb9e315
JL		 3713 base_vha = pci_get_drvdata(pdev);
3714 ha = base_vha->hw;
45235022
QT		 3715 ql_log(ql_log_info, base_vha, 0xb079,
3716 "Removing driver\n");
beb9e315
JL		 3717
3718 /* Indicate device removal to prevent future board_disable and wait
3719 * until any pending board_disable has completed. */
3720 set_bit(PFLG_DRIVER_REMOVING, &base_vha->pci_flags);
3721 cancel_work_sync(&ha->board_disable);
3722
fe1b806f 3723 /*
beb9e315
JL		 3724 * If the PCI device is disabled then there was a PCI-disconnect and
3725 * qla2x00_disable_board_on_pci_error has taken care of most of the
3726 * resources.
fe1b806f 3727 */
beb9e315 3728 if (!atomic_read(&pdev->enable_cnt)) {
726b8548
QT		 3729 dma_free_coherent(&ha->pdev->dev, base_vha->gnl.size,
3730 base_vha->gnl.l, base_vha->gnl.ldma);
3731
beb9e315
JL		 3732 scsi_host_put(base_vha->host);
3733 kfree(ha);
3734 pci_set_drvdata(pdev, NULL);
fe1b806f 3735 return;
beb9e315 3736 }
638a1a01
SC		 3737 qla2x00_wait_for_hba_ready(base_vha);
3738
ecc89f25
JC		 3739 if (IS_QLA25XX(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) ||
3740 IS_QLA28XX(ha)) {
45235022
QT		 3741 if (ha->flags.fw_started)
3742 qla2x00_abort_isp_cleanup(base_vha);
3743 } else if (!IS_QLAFX00(ha)) {
3744 if (IS_QLA8031(ha)) {
3745 ql_dbg(ql_dbg_p3p, base_vha, 0xb07e,
3746 "Clearing fcoe driver presence.\n");
3747 if (qla83xx_clear_drv_presence(base_vha) != QLA_SUCCESS)
3748 ql_dbg(ql_dbg_p3p, base_vha, 0xb079,
3749 "Error while clearing DRV-Presence.\n");
3750 }
3751
3752 qla2x00_try_to_stop_firmware(base_vha);
3753 }
3754
2ce87cc5
QT		 3755 qla2x00_wait_for_sess_deletion(base_vha);
3756
726b8548
QT		 3757 /*
3758 * if UNLOAD flag is already set, then continue unload,
783e0dc4
SC		 3759 * where it was set first.
3760 */
3761 if (test_bit(UNLOADING, &base_vha->dpc_flags))
3762 return;
3763
fe1b806f 3764 set_bit(UNLOADING, &base_vha->dpc_flags);
e84067d7
DG		 3765
3766 qla_nvme_delete(base_vha);
3767
726b8548
QT		 3768 dma_free_coherent(&ha->pdev->dev,
3769 base_vha->gnl.size, base_vha->gnl.l, base_vha->gnl.ldma);
fe1b806f 3770
a4239945
QT		 3771 vfree(base_vha->scan.l);
3772
fe1b806f
CD		 3773 if (IS_QLAFX00(ha))
3774 qlafx00_driver_shutdown(base_vha, 20);
3775
3776 qla2x00_delete_all_vps(ha, base_vha);
3777
fe1b806f
CD		 3778 qla2x00_dfs_remove(base_vha);
3779
3780 qla84xx_put_chip(base_vha);
3781
3782 /* Disable timer */
3783 if (base_vha->timer_active)
3784 qla2x00_stop_timer(base_vha);
3785
3786 base_vha->flags.online = 0;
3787
b0d6cabd
HM		 3788 /* free DMA memory */
3789 if (ha->exlogin_buf)
3790 qla2x00_free_exlogin_buffer(ha);
3791
2f56a7f1
HM		 3792 /* free DMA memory */
3793 if (ha->exchoffld_buf)
3794 qla2x00_free_exchoffld_buffer(ha);
3795
fe1b806f
CD		 3796 qla2x00_destroy_deferred_work(ha);
3797
3798 qlt_remove_target(ha, base_vha);
3799
3800 qla2x00_free_sysfs_attr(base_vha, true);
3801
3802 fc_remove_host(base_vha->host);
482c9dc7 3803 qlt_remove_target_resources(ha);
fe1b806f
CD		 3804
3805 scsi_remove_host(base_vha->host);
3806
3807 qla2x00_free_device(base_vha);
3808
db7157d4 3809 qla2x00_clear_drv_active(ha);
fe1b806f 3810
d2749ffa
AE		 3811 scsi_host_put(base_vha->host);
3812
fe1b806f 3813 qla2x00_unmap_iobases(ha);
73208dfd 3814
e315cd28
AC		 3815 pci_release_selected_regions(ha->pdev, ha->bars);
3816 kfree(ha);
1da177e4 3817
90a86fc0
JC		 3818 pci_disable_pcie_error_reporting(pdev);
3819
665db93b 3820 pci_disable_device(pdev);
1da177e4 3821}
1da177e4
LT		 3822
3823static void
e315cd28 3824qla2x00_free_device(scsi_qla_host_t *vha)
1da177e4 3825{
e315cd28 3826 struct qla_hw_data *ha = vha->hw;
1da177e4 3827
85880801
AV		 3828 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
3829
3830 /* Disable timer */
3831 if (vha->timer_active)
3832 qla2x00_stop_timer(vha);
3833
2afa19a9 3834 qla25xx_delete_queues(vha);
85880801
AV		 3835 vha->flags.online = 0;
3836
f6ef3b18 3837 /* turn-off interrupts on the card */
a9083016
GM		 3838 if (ha->interrupts_on) {
3839 vha->flags.init_done = 0;
fd34f556 3840 ha->isp_ops->disable_intrs(ha);
a9083016 3841 }
f6ef3b18 3842
093df737
QT		 3843 qla2x00_free_fcports(vha);
3844
e315cd28 3845 qla2x00_free_irqs(vha);
1da177e4 3846
093df737
QT		 3847 /* Flush the work queue and remove it */
3848 if (ha->wq) {
3849 flush_workqueue(ha->wq);
3850 destroy_workqueue(ha->wq);
3851 ha->wq = NULL;
3852 }
3853
8867048b 3854
e315cd28 3855 qla2x00_mem_free(ha);
73208dfd 3856
08de2844
GM		 3857 qla82xx_md_free(vha);
3858
73208dfd 3859 qla2x00_free_queues(ha);
1da177e4
LT		 3860}
3861
8867048b
CD		 3862void qla2x00_free_fcports(struct scsi_qla_host *vha)
3863{
3864 fc_port_t *fcport, *tfcport;
3865
ffbc6476
QT		 3866 list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list)
3867 qla2x00_free_fcport(fcport);
8867048b
CD		 3868}
3869
d97994dc 3870static inline void
e315cd28 3871qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport,
d97994dc 3872 int defer)
3873{
d97994dc 3874 struct fc_rport *rport;
67becc00 3875 scsi_qla_host_t *base_vha;
044d78e1 3876 unsigned long flags;
d97994dc 3877
3878 if (!fcport->rport)
3879 return;
3880
3881 rport = fcport->rport;
3882 if (defer) {
67becc00 3883 base_vha = pci_get_drvdata(vha->hw->pdev);
044d78e1 3884 spin_lock_irqsave(vha->host->host_lock, flags);
d97994dc 3885 fcport->drport = rport;
044d78e1 3886 spin_unlock_irqrestore(vha->host->host_lock, flags);
df673274 3887 qlt_do_generation_tick(vha, &base_vha->total_fcport_update_gen);
67becc00
AV		 3888 set_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags);
3889 qla2xxx_wake_dpc(base_vha);
2d70c103 3890 } else {
df673274 3891 int now;
726b8548 3892 if (rport) {
83548fe2
QT		 3893 ql_dbg(ql_dbg_disc, fcport->vha, 0x2109,
3894 "%s %8phN. rport %p roles %x\n",
3895 __func__, fcport->port_name, rport,
3896 rport->roles);
d20ed91b 3897 fc_remote_port_delete(rport);
726b8548 3898 }
df673274 3899 qlt_do_generation_tick(vha, &now);
2d70c103 3900 }
d97994dc 3901}
3902
1da177e4
LT		 3903/*
3904 * qla2x00_mark_device_lost Updates fcport state when device goes offline.
3905 *
3906 * Input: ha = adapter block pointer. fcport = port structure pointer.
3907 *
3908 * Return: None.
3909 *
3910 * Context:
3911 */
e315cd28 3912void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport,
d97994dc 3913 int do_login, int defer)
1da177e4 3914{
8ae6d9c7
GM		 3915 if (IS_QLAFX00(vha->hw)) {
3916 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
3917 qla2x00_schedule_rport_del(vha, fcport, defer);
3918 return;
3919 }
3920
2c3dfe3f 3921 if (atomic_read(&fcport->state) == FCS_ONLINE &&
c6d39e23 3922 vha->vp_idx == fcport->vha->vp_idx) {
ec426e10 3923 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
e315cd28
AC		 3924 qla2x00_schedule_rport_del(vha, fcport, defer);
3925 }
fa2a1ce5 3926 /*
1da177e4
LT		 3927 * We may need to retry the login, so don't change the state of the
3928 * port but do the retries.
3929 */
3930 if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD)
ec426e10 3931 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
1da177e4
LT		 3932
3933 if (!do_login)
3934 return;
3935
a1d0285e 3936 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
1da177e4
LT		 3937}
3938
3939/*
3940 * qla2x00_mark_all_devices_lost
3941 * Updates fcport state when device goes offline.
3942 *
3943 * Input:
3944 * ha = adapter block pointer.
3945 * fcport = port structure pointer.
3946 *
3947 * Return:
3948 * None.
3949 *
3950 * Context:
3951 */
3952void
e315cd28 3953qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha, int defer)
1da177e4
LT		 3954{
3955 fc_port_t *fcport;
3956
83548fe2
QT		 3957 ql_dbg(ql_dbg_disc, vha, 0x20f1,
3958 "Mark all dev lost\n");
726b8548 3959
e315cd28 3960 list_for_each_entry(fcport, &vha->vp_fcports, list) {
726b8548 3961 fcport->scan_state = 0;
d8630bb9 3962 qlt_schedule_sess_for_deletion(fcport);
726b8548 3963
c6d39e23 3964 if (vha->vp_idx != 0 && vha->vp_idx != fcport->vha->vp_idx)
1da177e4 3965 continue;
0d6e61bc 3966
1da177e4
LT		 3967 /*
3968 * No point in marking the device as lost, if the device is
3969 * already DEAD.
3970 */
3971 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD)
3972 continue;
e315cd28 3973 if (atomic_read(&fcport->state) == FCS_ONLINE) {
ec426e10 3974 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
0d6e61bc
AV		 3975 if (defer)
3976 qla2x00_schedule_rport_del(vha, fcport, defer);
c6d39e23 3977 else if (vha->vp_idx == fcport->vha->vp_idx)
0d6e61bc
AV		 3978 qla2x00_schedule_rport_del(vha, fcport, defer);
3979 }
1da177e4
LT		 3980 }
3981}
3982
3983/*
3984* qla2x00_mem_alloc
3985* Allocates adapter memory.
3986*
3987* Returns:
3988* 0 = success.
e8711085 3989* !0 = failure.
1da177e4 3990*/
e8711085 3991static int
73208dfd
AC		 3992qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len,
3993 struct req_que **req, struct rsp_que **rsp)
1da177e4
LT		 3994{
3995 char name[16];
1da177e4 3996
e8711085 3997 ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size,
e315cd28 3998 &ha->init_cb_dma, GFP_KERNEL);
e8711085 3999 if (!ha->init_cb)
e315cd28 4000 goto fail;
e8711085 4001
2d70c103
NB		 4002 if (qlt_mem_alloc(ha) < 0)
4003 goto fail_free_init_cb;
4004
642ef983
CD		 4005 ha->gid_list = dma_alloc_coherent(&ha->pdev->dev,
4006 qla2x00_gid_list_size(ha), &ha->gid_list_dma, GFP_KERNEL);
e315cd28 4007 if (!ha->gid_list)
2d70c103 4008 goto fail_free_tgt_mem;
1da177e4 4009
e8711085
AV		 4010 ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep);
4011 if (!ha->srb_mempool)
e315cd28 4012 goto fail_free_gid_list;
e8711085 4013
7ec0effd 4014 if (IS_P3P_TYPE(ha)) {
a9083016
GM		 4015 /* Allocate cache for CT6 Ctx. */
4016 if (!ctx_cachep) {
4017 ctx_cachep = kmem_cache_create("qla2xxx_ctx",
4018 sizeof(struct ct6_dsd), 0,
4019 SLAB_HWCACHE_ALIGN, NULL);
4020 if (!ctx_cachep)
fc1ffd6c 4021 goto fail_free_srb_mempool;
a9083016
GM		 4022 }
4023 ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ,
4024 ctx_cachep);
4025 if (!ha->ctx_mempool)
4026 goto fail_free_srb_mempool;
7c3df132
SK		 4027 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021,
4028 "ctx_cachep=%p ctx_mempool=%p.\n",
4029 ctx_cachep, ha->ctx_mempool);
a9083016
GM		 4030 }
4031
e8711085
AV		 4032 /* Get memory for cached NVRAM */
4033 ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL);
4034 if (!ha->nvram)
a9083016 4035 goto fail_free_ctx_mempool;
e8711085 4036
e315cd28
AC		 4037 snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME,
4038 ha->pdev->device);
4039 ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev,
4040 DMA_POOL_SIZE, 8, 0);
4041 if (!ha->s_dma_pool)
4042 goto fail_free_nvram;
4043
7c3df132
SK		 4044 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022,
4045 "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n",
4046 ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool);
4047
7ec0effd 4048 if (IS_P3P_TYPE(ha) || ql2xenabledif) {
a9083016
GM		 4049 ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev,
4050 DSD_LIST_DMA_POOL_SIZE, 8, 0);
4051 if (!ha->dl_dma_pool) {
7c3df132
SK		 4052 ql_log_pci(ql_log_fatal, ha->pdev, 0x0023,
4053 "Failed to allocate memory for dl_dma_pool.\n");
a9083016
GM		 4054 goto fail_s_dma_pool;
4055 }
4056
4057 ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev,
4058 FCP_CMND_DMA_POOL_SIZE, 8, 0);
4059 if (!ha->fcp_cmnd_dma_pool) {
7c3df132
SK		 4060 ql_log_pci(ql_log_fatal, ha->pdev, 0x0024,
4061 "Failed to allocate memory for fcp_cmnd_dma_pool.\n");
a9083016
GM		 4062 goto fail_dl_dma_pool;
4063 }
50b81275
GM		 4064
4065 if (ql2xenabledif) {
4066 u64 bufsize = DIF_BUNDLING_DMA_POOL_SIZE;
4067 struct dsd_dma *dsd, *nxt;
4068 uint i;
4069 /* Creata a DMA pool of buffers for DIF bundling */
4070 ha->dif_bundl_pool = dma_pool_create(name,
4071 &ha->pdev->dev, DIF_BUNDLING_DMA_POOL_SIZE, 8, 0);
4072 if (!ha->dif_bundl_pool) {
4073 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0024,
4074 "%s: failed create dif_bundl_pool\n",
4075 __func__);
4076 goto fail_dif_bundl_dma_pool;
4077 }
4078
4079 INIT_LIST_HEAD(&ha->pool.good.head);
4080 INIT_LIST_HEAD(&ha->pool.unusable.head);
4081 ha->pool.good.count = 0;
4082 ha->pool.unusable.count = 0;
4083 for (i = 0; i < 128; i++) {
4084 dsd = kzalloc(sizeof(*dsd), GFP_ATOMIC);
4085 if (!dsd) {
4086 ql_dbg_pci(ql_dbg_init, ha->pdev,
4087 0xe0ee, "%s: failed alloc dsd\n",
4088 __func__);
4089 return 1;
4090 }
4091 ha->dif_bundle_kallocs++;
4092
4093 dsd->dsd_addr = dma_pool_alloc(
4094 ha->dif_bundl_pool, GFP_ATOMIC,
4095 &dsd->dsd_list_dma);
4096 if (!dsd->dsd_addr) {
4097 ql_dbg_pci(ql_dbg_init, ha->pdev,
4098 0xe0ee,
4099 "%s: failed alloc ->dsd_addr\n",
4100 __func__);
4101 kfree(dsd);
4102 ha->dif_bundle_kallocs--;
4103 continue;
4104 }
4105 ha->dif_bundle_dma_allocs++;
4106
4107 /*
4108 * if DMA buffer crosses 4G boundary,
4109 * put it on bad list
4110 */
4111 if (MSD(dsd->dsd_list_dma) ^
4112 MSD(dsd->dsd_list_dma + bufsize)) {
4113 list_add_tail(&dsd->list,
4114 &ha->pool.unusable.head);
4115 ha->pool.unusable.count++;
4116 } else {
4117 list_add_tail(&dsd->list,
4118 &ha->pool.good.head);
4119 ha->pool.good.count++;
4120 }
4121 }
4122
4123 /* return the good ones back to the pool */
4124 list_for_each_entry_safe(dsd, nxt,
4125 &ha->pool.good.head, list) {
4126 list_del(&dsd->list);
4127 dma_pool_free(ha->dif_bundl_pool,
4128 dsd->dsd_addr, dsd->dsd_list_dma);
4129 ha->dif_bundle_dma_allocs--;
4130 kfree(dsd);
4131 ha->dif_bundle_kallocs--;
4132 }
4133
4134 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0024,
4135 "%s: dif dma pool (good=%u unusable=%u)\n",
4136 __func__, ha->pool.good.count,
4137 ha->pool.unusable.count);
4138 }
4139
7c3df132 4140 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025,
50b81275
GM		 4141 "dl_dma_pool=%p fcp_cmnd_dma_pool=%p dif_bundl_pool=%p.\n",
4142 ha->dl_dma_pool, ha->fcp_cmnd_dma_pool,
4143 ha->dif_bundl_pool);
a9083016
GM		 4144 }
4145
e8711085
AV		 4146 /* Allocate memory for SNS commands */
4147 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
e315cd28 4148 /* Get consistent memory allocated for SNS commands */
e8711085 4149 ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev,
e315cd28 4150 sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL);
e8711085 4151 if (!ha->sns_cmd)
e315cd28 4152 goto fail_dma_pool;
7c3df132 4153 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026,
d8424f68 4154 "sns_cmd: %p.\n", ha->sns_cmd);
e8711085 4155 } else {
e315cd28 4156 /* Get consistent memory allocated for MS IOCB */
e8711085 4157 ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
e315cd28 4158 &ha->ms_iocb_dma);
e8711085 4159 if (!ha->ms_iocb)
e315cd28
AC		 4160 goto fail_dma_pool;
4161 /* Get consistent memory allocated for CT SNS commands */
e8711085 4162 ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev,
e315cd28 4163 sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL);
e8711085
AV		 4164 if (!ha->ct_sns)
4165 goto fail_free_ms_iocb;
7c3df132
SK		 4166 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027,
4167 "ms_iocb=%p ct_sns=%p.\n",
4168 ha->ms_iocb, ha->ct_sns);
1da177e4
LT		 4169 }
4170
e315cd28 4171 /* Allocate memory for request ring */
73208dfd
AC		 4172 *req = kzalloc(sizeof(struct req_que), GFP_KERNEL);
4173 if (!*req) {
7c3df132
SK		 4174 ql_log_pci(ql_log_fatal, ha->pdev, 0x0028,
4175 "Failed to allocate memory for req.\n");
e315cd28
AC		 4176 goto fail_req;
4177 }
73208dfd
AC		 4178 (*req)->length = req_len;
4179 (*req)->ring = dma_alloc_coherent(&ha->pdev->dev,
4180 ((*req)->length + 1) * sizeof(request_t),
4181 &(*req)->dma, GFP_KERNEL);
4182 if (!(*req)->ring) {
7c3df132
SK		 4183 ql_log_pci(ql_log_fatal, ha->pdev, 0x0029,
4184 "Failed to allocate memory for req_ring.\n");
e315cd28
AC		 4185 goto fail_req_ring;
4186 }
4187 /* Allocate memory for response ring */
73208dfd
AC		 4188 *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL);
4189 if (!*rsp) {
7c3df132
SK		 4190 ql_log_pci(ql_log_fatal, ha->pdev, 0x002a,
4191 "Failed to allocate memory for rsp.\n");
e315cd28
AC		 4192 goto fail_rsp;
4193 }
73208dfd
AC		 4194 (*rsp)->hw = ha;
4195 (*rsp)->length = rsp_len;
4196 (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev,
4197 ((*rsp)->length + 1) * sizeof(response_t),
4198 &(*rsp)->dma, GFP_KERNEL);
4199 if (!(*rsp)->ring) {
7c3df132
SK		 4200 ql_log_pci(ql_log_fatal, ha->pdev, 0x002b,
4201 "Failed to allocate memory for rsp_ring.\n");
e315cd28
AC		 4202 goto fail_rsp_ring;
4203 }
73208dfd
AC		 4204 (*req)->rsp = *rsp;
4205 (*rsp)->req = *req;
7c3df132
SK		 4206 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c,
4207 "req=%p req->length=%d req->ring=%p rsp=%p "
4208 "rsp->length=%d rsp->ring=%p.\n",
4209 *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length,
4210 (*rsp)->ring);
73208dfd
AC		 4211 /* Allocate memory for NVRAM data for vports */
4212 if (ha->nvram_npiv_size) {
6396bb22
KC		 4213 ha->npiv_info = kcalloc(ha->nvram_npiv_size,
4214 sizeof(struct qla_npiv_entry),
4215 GFP_KERNEL);
73208dfd 4216 if (!ha->npiv_info) {
7c3df132
SK		 4217 ql_log_pci(ql_log_fatal, ha->pdev, 0x002d,
4218 "Failed to allocate memory for npiv_info.\n");
73208dfd
AC		 4219 goto fail_npiv_info;
4220 }
4221 } else
4222 ha->npiv_info = NULL;
e8711085 4223
b64b0e8f 4224 /* Get consistent memory allocated for EX-INIT-CB. */
ecc89f25
JC		 4225 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) ||
4226 IS_QLA28XX(ha)) {
b64b0e8f
AV		 4227 ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
4228 &ha->ex_init_cb_dma);
4229 if (!ha->ex_init_cb)
4230 goto fail_ex_init_cb;
7c3df132
SK		 4231 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e,
4232 "ex_init_cb=%p.\n", ha->ex_init_cb);
b64b0e8f
AV		 4233 }
4234
a9083016
GM		 4235 INIT_LIST_HEAD(&ha->gbl_dsd_list);
4236
5ff1d584
AV		 4237 /* Get consistent memory allocated for Async Port-Database. */
4238 if (!IS_FWI2_CAPABLE(ha)) {
4239 ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
4240 &ha->async_pd_dma);
4241 if (!ha->async_pd)
4242 goto fail_async_pd;
7c3df132
SK		 4243 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f,
4244 "async_pd=%p.\n", ha->async_pd);
5ff1d584
AV		 4245 }
4246
e315cd28 4247 INIT_LIST_HEAD(&ha->vp_list);
5f16b331
CD		 4248
4249 /* Allocate memory for our loop_id bitmap */
6396bb22
KC		 4250 ha->loop_id_map = kcalloc(BITS_TO_LONGS(LOOPID_MAP_SIZE),
4251 sizeof(long),
4252 GFP_KERNEL);
5f16b331 4253 if (!ha->loop_id_map)
fc1ffd6c 4254 goto fail_loop_id_map;
5f16b331
CD		 4255 else {
4256 qla2x00_set_reserved_loop_ids(ha);
4257 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0123,
b2a72ec3 4258 "loop_id_map=%p.\n", ha->loop_id_map);
5f16b331
CD		 4259 }
4260
e4e3a2ce
QT		 4261 ha->sfp_data = dma_alloc_coherent(&ha->pdev->dev,
4262 SFP_DEV_SIZE, &ha->sfp_data_dma, GFP_KERNEL);
4263 if (!ha->sfp_data) {
4264 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b,
4265 "Unable to allocate memory for SFP read-data.\n");
4266 goto fail_sfp_data;
4267 }
4268
3f006ac3
MH		 4269 ha->flt = dma_alloc_coherent(&ha->pdev->dev,
4270 sizeof(struct qla_flt_header) + FLT_REGIONS_SIZE, &ha->flt_dma,
4271 GFP_KERNEL);
4272 if (!ha->flt) {
4273 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b,
4274 "Unable to allocate memory for FLT.\n");
4275 goto fail_flt_buffer;
4276 }
4277
b2a72ec3 4278 return 0;
e315cd28 4279
3f006ac3
MH		 4280fail_flt_buffer:
4281 dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE,
4282 ha->sfp_data, ha->sfp_data_dma);
e4e3a2ce
QT		 4283fail_sfp_data:
4284 kfree(ha->loop_id_map);
fc1ffd6c
QT		 4285fail_loop_id_map:
4286 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
5ff1d584
AV		 4287fail_async_pd:
4288 dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma);
b64b0e8f
AV		 4289fail_ex_init_cb:
4290 kfree(ha->npiv_info);
73208dfd
AC		 4291fail_npiv_info:
4292 dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) *
4293 sizeof(response_t), (*rsp)->ring, (*rsp)->dma);
4294 (*rsp)->ring = NULL;
4295 (*rsp)->dma = 0;
e315cd28 4296fail_rsp_ring:
73208dfd 4297 kfree(*rsp);
6d634067 4298 *rsp = NULL;
e315cd28 4299fail_rsp:
73208dfd
AC		 4300 dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) *
4301 sizeof(request_t), (*req)->ring, (*req)->dma);
4302 (*req)->ring = NULL;
4303 (*req)->dma = 0;
e315cd28 4304fail_req_ring:
73208dfd 4305 kfree(*req);
6d634067 4306 *req = NULL;
e315cd28
AC		 4307fail_req:
4308 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
4309 ha->ct_sns, ha->ct_sns_dma);
4310 ha->ct_sns = NULL;
4311 ha->ct_sns_dma = 0;
e8711085
AV		 4312fail_free_ms_iocb:
4313 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
4314 ha->ms_iocb = NULL;
4315 ha->ms_iocb_dma = 0;
fc1ffd6c
QT		 4316
4317 if (ha->sns_cmd)
4318 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
4319 ha->sns_cmd, ha->sns_cmd_dma);
e315cd28 4320fail_dma_pool:
50b81275
GM		 4321 if (ql2xenabledif) {
4322 struct dsd_dma *dsd, *nxt;
4323
4324 list_for_each_entry_safe(dsd, nxt, &ha->pool.unusable.head,
4325 list) {
4326 list_del(&dsd->list);
4327 dma_pool_free(ha->dif_bundl_pool, dsd->dsd_addr,
4328 dsd->dsd_list_dma);
4329 ha->dif_bundle_dma_allocs--;
4330 kfree(dsd);
4331 ha->dif_bundle_kallocs--;
4332 ha->pool.unusable.count--;
4333 }
4334 dma_pool_destroy(ha->dif_bundl_pool);
4335 ha->dif_bundl_pool = NULL;
4336 }
4337
4338fail_dif_bundl_dma_pool:
bad75002 4339 if (IS_QLA82XX(ha) || ql2xenabledif) {
a9083016
GM		 4340 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
4341 ha->fcp_cmnd_dma_pool = NULL;
4342 }
4343fail_dl_dma_pool:
bad75002 4344 if (IS_QLA82XX(ha) || ql2xenabledif) {
a9083016
GM		 4345 dma_pool_destroy(ha->dl_dma_pool);
4346 ha->dl_dma_pool = NULL;
4347 }
4348fail_s_dma_pool:
e315cd28
AC		 4349 dma_pool_destroy(ha->s_dma_pool);
4350 ha->s_dma_pool = NULL;
e8711085
AV		 4351fail_free_nvram:
4352 kfree(ha->nvram);
4353 ha->nvram = NULL;
a9083016 4354fail_free_ctx_mempool:
75c1d48a 4355 mempool_destroy(ha->ctx_mempool);
a9083016 4356 ha->ctx_mempool = NULL;
e8711085 4357fail_free_srb_mempool:
75c1d48a 4358 mempool_destroy(ha->srb_mempool);
e8711085 4359 ha->srb_mempool = NULL;
e8711085 4360fail_free_gid_list:
642ef983
CD		 4361 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
4362 ha->gid_list,
e315cd28 4363 ha->gid_list_dma);
e8711085
AV		 4364 ha->gid_list = NULL;
4365 ha->gid_list_dma = 0;
2d70c103
NB		 4366fail_free_tgt_mem:
4367 qlt_mem_free(ha);
e315cd28
AC		 4368fail_free_init_cb:
4369 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb,
4370 ha->init_cb_dma);
4371 ha->init_cb = NULL;
4372 ha->init_cb_dma = 0;
e8711085 4373fail:
7c3df132
SK		 4374 ql_log(ql_log_fatal, NULL, 0x0030,
4375 "Memory allocation failure.\n");
e8711085 4376 return -ENOMEM;
1da177e4
LT		 4377}
4378
b0d6cabd
HM		 4379int
4380qla2x00_set_exlogins_buffer(scsi_qla_host_t *vha)
4381{
4382 int rval;
4383 uint16_t size, max_cnt, temp;
4384 struct qla_hw_data *ha = vha->hw;
4385
4386 /* Return if we don't need to alloacate any extended logins */
4387 if (!ql2xexlogins)
4388 return QLA_SUCCESS;
4389
99e1b683
QT		 4390 if (!IS_EXLOGIN_OFFLD_CAPABLE(ha))
4391 return QLA_SUCCESS;
4392
b0d6cabd
HM		 4393 ql_log(ql_log_info, vha, 0xd021, "EXLOGIN count: %d.\n", ql2xexlogins);
4394 max_cnt = 0;
4395 rval = qla_get_exlogin_status(vha, &size, &max_cnt);
4396 if (rval != QLA_SUCCESS) {
4397 ql_log_pci(ql_log_fatal, ha->pdev, 0xd029,
4398 "Failed to get exlogin status.\n");
4399 return rval;
4400 }
4401
4402 temp = (ql2xexlogins > max_cnt) ? max_cnt : ql2xexlogins;
99e1b683
QT		 4403 temp *= size;
4404
4405 if (temp != ha->exlogin_size) {
4406 qla2x00_free_exlogin_buffer(ha);
4407 ha->exlogin_size = temp;
4408
4409 ql_log(ql_log_info, vha, 0xd024,
4410 "EXLOGIN: max_logins=%d, portdb=0x%x, total=%d.\n",
4411 max_cnt, size, temp);
4412
4413 ql_log(ql_log_info, vha, 0xd025,
4414 "EXLOGIN: requested size=0x%x\n", ha->exlogin_size);
4415
4416 /* Get consistent memory for extended logins */
4417 ha->exlogin_buf = dma_alloc_coherent(&ha->pdev->dev,
4418 ha->exlogin_size, &ha->exlogin_buf_dma, GFP_KERNEL);
4419 if (!ha->exlogin_buf) {
4420 ql_log_pci(ql_log_fatal, ha->pdev, 0xd02a,
b0d6cabd 4421 "Failed to allocate memory for exlogin_buf_dma.\n");
99e1b683
QT		 4422 return -ENOMEM;
4423 }
b0d6cabd
HM		 4424 }
4425
4426 /* Now configure the dma buffer */
4427 rval = qla_set_exlogin_mem_cfg(vha, ha->exlogin_buf_dma);
4428 if (rval) {
83548fe2 4429 ql_log(ql_log_fatal, vha, 0xd033,
b0d6cabd
HM		 4430 "Setup extended login buffer ****FAILED****.\n");
4431 qla2x00_free_exlogin_buffer(ha);
4432 }
4433
4434 return rval;
4435}
4436
4437/*
4438* qla2x00_free_exlogin_buffer
4439*
4440* Input:
4441* ha = adapter block pointer
4442*/
4443void
4444qla2x00_free_exlogin_buffer(struct qla_hw_data *ha)
4445{
4446 if (ha->exlogin_buf) {
4447 dma_free_coherent(&ha->pdev->dev, ha->exlogin_size,
4448 ha->exlogin_buf, ha->exlogin_buf_dma);
4449 ha->exlogin_buf = NULL;
4450 ha->exlogin_size = 0;
4451 }
4452}
4453
99e1b683
QT		 4454static void
4455qla2x00_number_of_exch(scsi_qla_host_t *vha, u32 *ret_cnt, u16 max_cnt)
4456{
4457 u32 temp;
0645cb83 4458 struct init_cb_81xx *icb = (struct init_cb_81xx *)&vha->hw->init_cb;
99e1b683
QT		 4459 *ret_cnt = FW_DEF_EXCHANGES_CNT;
4460
d1e3635a
QT		 4461 if (max_cnt > vha->hw->max_exchg)
4462 max_cnt = vha->hw->max_exchg;
4463
99e1b683 4464 if (qla_ini_mode_enabled(vha)) {
0645cb83
QT		 4465 if (vha->ql2xiniexchg > max_cnt)
4466 vha->ql2xiniexchg = max_cnt;
4467
4468 if (vha->ql2xiniexchg > FW_DEF_EXCHANGES_CNT)
4469 *ret_cnt = vha->ql2xiniexchg;
99e1b683 4470
99e1b683 4471 } else if (qla_tgt_mode_enabled(vha)) {
0645cb83
QT		 4472 if (vha->ql2xexchoffld > max_cnt) {
4473 vha->ql2xexchoffld = max_cnt;
4474 icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld);
4475 }
99e1b683 4476
0645cb83
QT		 4477 if (vha->ql2xexchoffld > FW_DEF_EXCHANGES_CNT)
4478 *ret_cnt = vha->ql2xexchoffld;
99e1b683 4479 } else if (qla_dual_mode_enabled(vha)) {
0645cb83 4480 temp = vha->ql2xiniexchg + vha->ql2xexchoffld;
99e1b683 4481 if (temp > max_cnt) {
0645cb83
QT		 4482 vha->ql2xiniexchg -= (temp - max_cnt)/2;
4483 vha->ql2xexchoffld -= (((temp - max_cnt)/2) + 1);
99e1b683 4484 temp = max_cnt;
0645cb83 4485 icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld);
99e1b683
QT		 4486 }
4487
4488 if (temp > FW_DEF_EXCHANGES_CNT)
4489 *ret_cnt = temp;
4490 }
4491}
4492
2f56a7f1
HM		 4493int
4494qla2x00_set_exchoffld_buffer(scsi_qla_host_t *vha)
4495{
4496 int rval;
d1e3635a
QT		 4497 u16 size, max_cnt;
4498 u32 actual_cnt, totsz;
2f56a7f1
HM		 4499 struct qla_hw_data *ha = vha->hw;
4500
99e1b683
QT		 4501 if (!ha->flags.exchoffld_enabled)
4502 return QLA_SUCCESS;
4503
4504 if (!IS_EXCHG_OFFLD_CAPABLE(ha))
2f56a7f1
HM		 4505 return QLA_SUCCESS;
4506
2f56a7f1
HM		 4507 max_cnt = 0;
4508 rval = qla_get_exchoffld_status(vha, &size, &max_cnt);
4509 if (rval != QLA_SUCCESS) {
4510 ql_log_pci(ql_log_fatal, ha->pdev, 0xd012,
4511 "Failed to get exlogin status.\n");
4512 return rval;
4513 }
4514
d1e3635a
QT		 4515 qla2x00_number_of_exch(vha, &actual_cnt, max_cnt);
4516 ql_log(ql_log_info, vha, 0xd014,
4517 "Actual exchange offload count: %d.\n", actual_cnt);
4518
4519 totsz = actual_cnt * size;
2f56a7f1 4520
d1e3635a 4521 if (totsz != ha->exchoffld_size) {
99e1b683 4522 qla2x00_free_exchoffld_buffer(ha);
0645cb83
QT		 4523 if (actual_cnt <= FW_DEF_EXCHANGES_CNT) {
4524 ha->exchoffld_size = 0;
4525 ha->flags.exchoffld_enabled = 0;
4526 return QLA_SUCCESS;
4527 }
4528
d1e3635a 4529 ha->exchoffld_size = totsz;
99e1b683
QT		 4530
4531 ql_log(ql_log_info, vha, 0xd016,
d1e3635a
QT		 4532 "Exchange offload: max_count=%d, actual count=%d entry sz=0x%x, total sz=0x%x\n",
4533 max_cnt, actual_cnt, size, totsz);
99e1b683
QT		 4534
4535 ql_log(ql_log_info, vha, 0xd017,
4536 "Exchange Buffers requested size = 0x%x\n",
4537 ha->exchoffld_size);
4538
4539 /* Get consistent memory for extended logins */
4540 ha->exchoffld_buf = dma_alloc_coherent(&ha->pdev->dev,
4541 ha->exchoffld_size, &ha->exchoffld_buf_dma, GFP_KERNEL);
4542 if (!ha->exchoffld_buf) {
4543 ql_log_pci(ql_log_fatal, ha->pdev, 0xd013,
d1e3635a
QT		 4544 "Failed to allocate memory for Exchange Offload.\n");
4545
4546 if (ha->max_exchg >
4547 (FW_DEF_EXCHANGES_CNT + REDUCE_EXCHANGES_CNT)) {
4548 ha->max_exchg -= REDUCE_EXCHANGES_CNT;
4549 } else if (ha->max_exchg >
4550 (FW_DEF_EXCHANGES_CNT + 512)) {
4551 ha->max_exchg -= 512;
4552 } else {
4553 ha->flags.exchoffld_enabled = 0;
4554 ql_log_pci(ql_log_fatal, ha->pdev, 0xd013,
4555 "Disabling Exchange offload due to lack of memory\n");
4556 }
4557 ha->exchoffld_size = 0;
4558
99e1b683
QT		 4559 return -ENOMEM;
4560 }
0645cb83
QT		 4561 } else if (!ha->exchoffld_buf || (actual_cnt <= FW_DEF_EXCHANGES_CNT)) {
4562 /* pathological case */
4563 qla2x00_free_exchoffld_buffer(ha);
4564 ha->exchoffld_size = 0;
4565 ha->flags.exchoffld_enabled = 0;
4566 ql_log(ql_log_info, vha, 0xd016,
4567 "Exchange offload not enable: offld size=%d, actual count=%d entry sz=0x%x, total sz=0x%x.\n",
4568 ha->exchoffld_size, actual_cnt, size, totsz);
4569 return 0;
2f56a7f1
HM		 4570 }
4571
4572 /* Now configure the dma buffer */
99e1b683 4573 rval = qla_set_exchoffld_mem_cfg(vha);
2f56a7f1
HM		 4574 if (rval) {
4575 ql_log(ql_log_fatal, vha, 0xd02e,
4576 "Setup exchange offload buffer ****FAILED****.\n");
4577 qla2x00_free_exchoffld_buffer(ha);
99e1b683
QT		 4578 } else {
4579 /* re-adjust number of target exchange */
4580 struct init_cb_81xx *icb = (struct init_cb_81xx *)ha->init_cb;
4581
4582 if (qla_ini_mode_enabled(vha))
4583 icb->exchange_count = 0;
4584 else
0645cb83 4585 icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld);
2f56a7f1
HM		 4586 }
4587
4588 return rval;
4589}
4590
4591/*
4592* qla2x00_free_exchoffld_buffer
4593*
4594* Input:
4595* ha = adapter block pointer
4596*/
4597void
4598qla2x00_free_exchoffld_buffer(struct qla_hw_data *ha)
4599{
4600 if (ha->exchoffld_buf) {
4601 dma_free_coherent(&ha->pdev->dev, ha->exchoffld_size,
4602 ha->exchoffld_buf, ha->exchoffld_buf_dma);
4603 ha->exchoffld_buf = NULL;
4604 ha->exchoffld_size = 0;
4605 }
4606}
4607
1da177e4 4608/*
e30d1756
MI		 4609* qla2x00_free_fw_dump
4610* Frees fw dump stuff.
1da177e4
LT		 4611*
4612* Input:
7ec0effd 4613* ha = adapter block pointer
1da177e4 4614*/
a824ebb3 4615static void
e30d1756 4616qla2x00_free_fw_dump(struct qla_hw_data *ha)
1da177e4 4617{
a28d9e4e
JC		 4618 struct fwdt *fwdt = ha->fwdt;
4619 uint j;
4620
df613b96 4621 if (ha->fce)
f73cb695
CD		 4622 dma_free_coherent(&ha->pdev->dev,
4623 FCE_SIZE, ha->fce, ha->fce_dma);
df613b96 4624
f73cb695
CD		 4625 if (ha->eft)
4626 dma_free_coherent(&ha->pdev->dev,
4627 EFT_SIZE, ha->eft, ha->eft_dma);
4628
4629 if (ha->fw_dump)
a7a167bf 4630 vfree(ha->fw_dump);
f73cb695 4631
e30d1756
MI		 4632 ha->fce = NULL;
4633 ha->fce_dma = 0;
4634 ha->eft = NULL;
4635 ha->eft_dma = 0;
e30d1756 4636 ha->fw_dumped = 0;
61f098dd 4637 ha->fw_dump_cap_flags = 0;
e30d1756 4638 ha->fw_dump_reading = 0;
f73cb695
CD		 4639 ha->fw_dump = NULL;
4640 ha->fw_dump_len = 0;
a28d9e4e
JC		 4641
4642 for (j = 0; j < 2; j++, fwdt++) {
4643 if (fwdt->template)
4644 vfree(fwdt->template);
4645 fwdt->template = NULL;
4646 fwdt->length = 0;
4647 }
e30d1756
MI		 4648}
4649
4650/*
4651* qla2x00_mem_free
4652* Frees all adapter allocated memory.
4653*
4654* Input:
4655* ha = adapter block pointer.
4656*/
4657static void
4658qla2x00_mem_free(struct qla_hw_data *ha)
4659{
4660 qla2x00_free_fw_dump(ha);
4661
81178772
SK		 4662 if (ha->mctp_dump)
4663 dma_free_coherent(&ha->pdev->dev, MCTP_DUMP_SIZE, ha->mctp_dump,
4664 ha->mctp_dump_dma);
4665
75c1d48a 4666 mempool_destroy(ha->srb_mempool);
a7a167bf 4667
11bbc1d8
AV		 4668 if (ha->dcbx_tlv)
4669 dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE,
4670 ha->dcbx_tlv, ha->dcbx_tlv_dma);
4671
ce0423f4
AV		 4672 if (ha->xgmac_data)
4673 dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE,
4674 ha->xgmac_data, ha->xgmac_data_dma);
4675
1da177e4
LT		 4676 if (ha->sns_cmd)
4677 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
e315cd28 4678 ha->sns_cmd, ha->sns_cmd_dma);
1da177e4
LT		 4679
4680 if (ha->ct_sns)
4681 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
e315cd28 4682 ha->ct_sns, ha->ct_sns_dma);
1da177e4 4683
88729e53 4684 if (ha->sfp_data)
e4e3a2ce
QT		 4685 dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE, ha->sfp_data,
4686 ha->sfp_data_dma);
88729e53 4687
3f006ac3
MH		 4688 if (ha->flt)
4689 dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE,
4690 ha->flt, ha->flt_dma);
4691
1da177e4
LT		 4692 if (ha->ms_iocb)
4693 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
4694
b64b0e8f 4695 if (ha->ex_init_cb)
a9083016
GM		 4696 dma_pool_free(ha->s_dma_pool,
4697 ha->ex_init_cb, ha->ex_init_cb_dma);
b64b0e8f 4698
5ff1d584
AV		 4699 if (ha->async_pd)
4700 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
4701
75c1d48a 4702 dma_pool_destroy(ha->s_dma_pool);
1da177e4 4703
1da177e4 4704 if (ha->gid_list)
642ef983
CD		 4705 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
4706 ha->gid_list, ha->gid_list_dma);
1da177e4 4707
a9083016
GM		 4708 if (IS_QLA82XX(ha)) {
4709 if (!list_empty(&ha->gbl_dsd_list)) {
4710 struct dsd_dma *dsd_ptr, *tdsd_ptr;
4711
4712 /* clean up allocated prev pool */
4713 list_for_each_entry_safe(dsd_ptr,
4714 tdsd_ptr, &ha->gbl_dsd_list, list) {
4715 dma_pool_free(ha->dl_dma_pool,
4716 dsd_ptr->dsd_addr, dsd_ptr->dsd_list_dma);
4717 list_del(&dsd_ptr->list);
4718 kfree(dsd_ptr);
4719 }
4720 }
4721 }
4722
75c1d48a 4723 dma_pool_destroy(ha->dl_dma_pool);
a9083016 4724
75c1d48a 4725 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
a9083016 4726
75c1d48a 4727 mempool_destroy(ha->ctx_mempool);
a9083016 4728
50b81275
GM		 4729 if (ql2xenabledif) {
4730 struct dsd_dma *dsd, *nxt;
4731
4732 list_for_each_entry_safe(dsd, nxt, &ha->pool.unusable.head,
4733 list) {
4734 list_del(&dsd->list);
4735 dma_pool_free(ha->dif_bundl_pool, dsd->dsd_addr,
4736 dsd->dsd_list_dma);
4737 ha->dif_bundle_dma_allocs--;
4738 kfree(dsd);
4739 ha->dif_bundle_kallocs--;
4740 ha->pool.unusable.count--;
4741 }
4742 list_for_each_entry_safe(dsd, nxt, &ha->pool.good.head, list) {
4743 list_del(&dsd->list);
4744 dma_pool_free(ha->dif_bundl_pool, dsd->dsd_addr,
4745 dsd->dsd_list_dma);
4746 ha->dif_bundle_dma_allocs--;
4747 kfree(dsd);
4748 ha->dif_bundle_kallocs--;
4749 }
4750 }
4751
4752 if (ha->dif_bundl_pool)
4753 dma_pool_destroy(ha->dif_bundl_pool);
4754
2d70c103
NB		 4755 qlt_mem_free(ha);
4756
e315cd28
AC		 4757 if (ha->init_cb)
4758 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size,
a9083016 4759 ha->init_cb, ha->init_cb_dma);
6a2cf8d3 4760
6d634067
BK		 4761 vfree(ha->optrom_buffer);
4762 kfree(ha->nvram);
4763 kfree(ha->npiv_info);
4764 kfree(ha->swl);
4765 kfree(ha->loop_id_map);
1da177e4 4766
e8711085 4767 ha->srb_mempool = NULL;
a9083016 4768 ha->ctx_mempool = NULL;
1da177e4
LT		 4769 ha->sns_cmd = NULL;
4770 ha->sns_cmd_dma = 0;
4771 ha->ct_sns = NULL;
4772 ha->ct_sns_dma = 0;
4773 ha->ms_iocb = NULL;
4774 ha->ms_iocb_dma = 0;
1da177e4
LT		 4775 ha->init_cb = NULL;
4776 ha->init_cb_dma = 0;
b64b0e8f
AV		 4777 ha->ex_init_cb = NULL;
4778 ha->ex_init_cb_dma = 0;
5ff1d584
AV		 4779 ha->async_pd = NULL;
4780 ha->async_pd_dma = 0;
6a2cf8d3
BK		 4781 ha->loop_id_map = NULL;
4782 ha->npiv_info = NULL;
4783 ha->optrom_buffer = NULL;
4784 ha->swl = NULL;
4785 ha->nvram = NULL;
4786 ha->mctp_dump = NULL;
4787 ha->dcbx_tlv = NULL;
4788 ha->xgmac_data = NULL;
4789 ha->sfp_data = NULL;
1da177e4
LT		 4790
4791 ha->s_dma_pool = NULL;
a9083016
GM		 4792 ha->dl_dma_pool = NULL;
4793 ha->fcp_cmnd_dma_pool = NULL;
1da177e4 4794
1da177e4
LT		 4795 ha->gid_list = NULL;
4796 ha->gid_list_dma = 0;
2d70c103
NB		 4797
4798 ha->tgt.atio_ring = NULL;
4799 ha->tgt.atio_dma = 0;
4800 ha->tgt.tgt_vp_map = NULL;
e315cd28 4801}
1da177e4 4802
e315cd28
AC		 4803struct scsi_qla_host *qla2x00_create_host(struct scsi_host_template *sht,
4804 struct qla_hw_data *ha)
4805{
4806 struct Scsi_Host *host;
4807 struct scsi_qla_host *vha = NULL;
854165f4 4808
e315cd28 4809 host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t));
41dc529a 4810 if (!host) {
7c3df132
SK		 4811 ql_log_pci(ql_log_fatal, ha->pdev, 0x0107,
4812 "Failed to allocate host from the scsi layer, aborting.\n");
41dc529a 4813 return NULL;
e315cd28
AC		 4814 }
4815
4816 /* Clear our data area */
4817 vha = shost_priv(host);
4818 memset(vha, 0, sizeof(scsi_qla_host_t));
4819
4820 vha->host = host;
4821 vha->host_no = host->host_no;
4822 vha->hw = ha;
4823
0645cb83
QT		 4824 vha->qlini_mode = ql2x_ini_mode;
4825 vha->ql2xexchoffld = ql2xexchoffld;
4826 vha->ql2xiniexchg = ql2xiniexchg;
4827
e315cd28
AC		 4828 INIT_LIST_HEAD(&vha->vp_fcports);
4829 INIT_LIST_HEAD(&vha->work_list);
4830 INIT_LIST_HEAD(&vha->list);
8b2f5ff3
SN		 4831 INIT_LIST_HEAD(&vha->qla_cmd_list);
4832 INIT_LIST_HEAD(&vha->qla_sess_op_cmd_list);
71cdc079 4833 INIT_LIST_HEAD(&vha->logo_list);
b7bd104e 4834 INIT_LIST_HEAD(&vha->plogi_ack_list);
d7459527 4835 INIT_LIST_HEAD(&vha->qp_list);
41dc529a 4836 INIT_LIST_HEAD(&vha->gnl.fcports);
a5d42f4c 4837 INIT_LIST_HEAD(&vha->nvme_rport_list);
2d73ac61 4838 INIT_LIST_HEAD(&vha->gpnid_list);
9b3e0f4d 4839 INIT_WORK(&vha->iocb_work, qla2x00_iocb_work_fn);
e315cd28 4840
f999f4c1 4841 spin_lock_init(&vha->work_lock);
8b2f5ff3 4842 spin_lock_init(&vha->cmd_list_lock);
726b8548 4843 init_waitqueue_head(&vha->fcport_waitQ);
c4a9b538 4844 init_waitqueue_head(&vha->vref_waitq);
f999f4c1 4845
2fdbc65e
BVA		 4846 vha->gnl.size = sizeof(struct get_name_list_extended) *
4847 (ha->max_loop_id + 1);
41dc529a
QT		 4848 vha->gnl.l = dma_alloc_coherent(&ha->pdev->dev,
4849 vha->gnl.size, &vha->gnl.ldma, GFP_KERNEL);
4850 if (!vha->gnl.l) {
83548fe2 4851 ql_log(ql_log_fatal, vha, 0xd04a,
41dc529a
QT		 4852 "Alloc failed for name list.\n");
4853 scsi_remove_host(vha->host);
4854 return NULL;
4855 }
f999f4c1 4856
a4239945
QT		 4857 /* todo: what about ext login? */
4858 vha->scan.size = ha->max_fibre_devices * sizeof(struct fab_scan_rp);
4859 vha->scan.l = vmalloc(vha->scan.size);
4860 if (!vha->scan.l) {
4861 ql_log(ql_log_fatal, vha, 0xd04a,
4862 "Alloc failed for scan database.\n");
4863 dma_free_coherent(&ha->pdev->dev, vha->gnl.size,
4864 vha->gnl.l, vha->gnl.ldma);
4865 scsi_remove_host(vha->host);
4866 return NULL;
4867 }
f352eeb7 4868 INIT_DELAYED_WORK(&vha->scan.scan_work, qla_scan_work_fn);
a4239945 4869
e315cd28 4870 sprintf(vha->host_str, "%s_%ld", QLA2XXX_DRIVER_NAME, vha->host_no);
7c3df132
SK		 4871 ql_dbg(ql_dbg_init, vha, 0x0041,
4872 "Allocated the host=%p hw=%p vha=%p dev_name=%s",
4873 vha->host, vha->hw, vha,
4874 dev_name(&(ha->pdev->dev)));
4875
e315cd28 4876 return vha;
1da177e4
LT		 4877}
4878
726b8548 4879struct qla_work_evt *
f999f4c1 4880qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type)
0971de7f
AV		 4881{
4882 struct qla_work_evt *e;
feafb7b1
AE		 4883 uint8_t bail;
4884
4885 QLA_VHA_MARK_BUSY(vha, bail);
4886 if (bail)
4887 return NULL;
0971de7f 4888
f999f4c1 4889 e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC);
feafb7b1
AE		 4890 if (!e) {
4891 QLA_VHA_MARK_NOT_BUSY(vha);
0971de7f 4892 return NULL;
feafb7b1 4893 }
0971de7f
AV		 4894
4895 INIT_LIST_HEAD(&e->list);
4896 e->type = type;
4897 e->flags = QLA_EVT_FLAG_FREE;
4898 return e;
4899}
4900
726b8548 4901int
f999f4c1 4902qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e)
0971de7f 4903{
f999f4c1 4904 unsigned long flags;
9b3e0f4d 4905 bool q = false;
0971de7f 4906
f999f4c1 4907 spin_lock_irqsave(&vha->work_lock, flags);
e315cd28 4908 list_add_tail(&e->list, &vha->work_list);
9b3e0f4d
QT		 4909
4910 if (!test_and_set_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags))
4911 q = true;
4912
f999f4c1 4913 spin_unlock_irqrestore(&vha->work_lock, flags);
ec7193e2 4914
9b3e0f4d
QT		 4915 if (q)
4916 queue_work(vha->hw->wq, &vha->iocb_work);
f999f4c1 4917
0971de7f
AV		 4918 return QLA_SUCCESS;
4919}
4920
4921int
e315cd28 4922qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code,
0971de7f
AV		 4923 u32 data)
4924{
4925 struct qla_work_evt *e;
4926
f999f4c1 4927 e = qla2x00_alloc_work(vha, QLA_EVT_AEN);
0971de7f
AV		 4928 if (!e)
4929 return QLA_FUNCTION_FAILED;
4930
4931 e->u.aen.code = code;
4932 e->u.aen.data = data;
f999f4c1 4933 return qla2x00_post_work(vha, e);
0971de7f
AV		 4934}
4935
8a659571
AV		 4936int
4937qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb)
4938{
4939 struct qla_work_evt *e;
4940
f999f4c1 4941 e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK);
8a659571
AV		 4942 if (!e)
4943 return QLA_FUNCTION_FAILED;
4944
4945 memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t));
f999f4c1 4946 return qla2x00_post_work(vha, e);
8a659571
AV		 4947}
4948
ac280b67
AV		 4949#define qla2x00_post_async_work(name, type) \
4950int qla2x00_post_async_##name##_work( \
4951 struct scsi_qla_host *vha, \
4952 fc_port_t *fcport, uint16_t *data) \
4953{ \
4954 struct qla_work_evt *e; \
4955 \
4956 e = qla2x00_alloc_work(vha, type); \
4957 if (!e) \
4958 return QLA_FUNCTION_FAILED; \
4959 \
4960 e->u.logio.fcport = fcport; \
4961 if (data) { \
4962 e->u.logio.data[0] = data[0]; \
4963 e->u.logio.data[1] = data[1]; \
4964 } \
6d674927 4965 fcport->flags |= FCF_ASYNC_ACTIVE; \
ac280b67
AV		 4966 return qla2x00_post_work(vha, e); \
4967}
4968
4969qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN);
ac280b67
AV		 4970qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT);
4971qla2x00_post_async_work(logout_done, QLA_EVT_ASYNC_LOGOUT_DONE);
5ff1d584 4972qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC);
11aea16a
QT		 4973qla2x00_post_async_work(prlo, QLA_EVT_ASYNC_PRLO);
4974qla2x00_post_async_work(prlo_done, QLA_EVT_ASYNC_PRLO_DONE);
ac280b67 4975
3420d36c
AV		 4976int
4977qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code)
4978{
4979 struct qla_work_evt *e;
4980
4981 e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT);
4982 if (!e)
4983 return QLA_FUNCTION_FAILED;
4984
4985 e->u.uevent.code = code;
4986 return qla2x00_post_work(vha, e);
4987}
4988
4989static void
4990qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code)
4991{
4992 char event_string[40];
4993 char *envp[] = { event_string, NULL };
4994
4995 switch (code) {
4996 case QLA_UEVENT_CODE_FW_DUMP:
4997 snprintf(event_string, sizeof(event_string), "FW_DUMP=%ld",
4998 vha->host_no);
4999 break;
5000 default:
5001 /* do nothing */
5002 break;
5003 }
5004 kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp);
5005}
5006
8ae6d9c7
GM		 5007int
5008qlafx00_post_aenfx_work(struct scsi_qla_host *vha, uint32_t evtcode,
5009 uint32_t *data, int cnt)
5010{
5011 struct qla_work_evt *e;
5012
5013 e = qla2x00_alloc_work(vha, QLA_EVT_AENFX);
5014 if (!e)
5015 return QLA_FUNCTION_FAILED;
5016
5017 e->u.aenfx.evtcode = evtcode;
5018 e->u.aenfx.count = cnt;
5019 memcpy(e->u.aenfx.mbx, data, sizeof(*data) * cnt);
5020 return qla2x00_post_work(vha, e);
5021}
5022
cd4ed6b4 5023void qla24xx_sched_upd_fcport(fc_port_t *fcport)
726b8548 5024{
cd4ed6b4 5025 unsigned long flags;
726b8548 5026
cd4ed6b4
QT		 5027 if (IS_SW_RESV_ADDR(fcport->d_id))
5028 return;
726b8548 5029
cd4ed6b4
QT		 5030 spin_lock_irqsave(&fcport->vha->work_lock, flags);
5031 if (fcport->disc_state == DSC_UPD_FCPORT) {
5032 spin_unlock_irqrestore(&fcport->vha->work_lock, flags);
5033 return;
5034 }
5035 fcport->jiffies_at_registration = jiffies;
5036 fcport->sec_since_registration = 0;
5037 fcport->next_disc_state = DSC_DELETED;
5038 fcport->disc_state = DSC_UPD_FCPORT;
5039 spin_unlock_irqrestore(&fcport->vha->work_lock, flags);
5040
5041 queue_work(system_unbound_wq, &fcport->reg_work);
726b8548
QT		 5042}
5043
5044static
5045void qla24xx_create_new_sess(struct scsi_qla_host *vha, struct qla_work_evt *e)
5046{
5047 unsigned long flags;
b5d15312 5048 fc_port_t *fcport = NULL, *tfcp;
726b8548
QT		 5049 struct qlt_plogi_ack_t *pla =
5050 (struct qlt_plogi_ack_t *)e->u.new_sess.pla;
b5d15312 5051 uint8_t free_fcport = 0;
726b8548 5052
9cd883f0
QT		 5053 ql_dbg(ql_dbg_disc, vha, 0xffff,
5054 "%s %d %8phC enter\n",
5055 __func__, __LINE__, e->u.new_sess.port_name);
5056
726b8548
QT		 5057 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
5058 fcport = qla2x00_find_fcport_by_wwpn(vha, e->u.new_sess.port_name, 1);
5059 if (fcport) {
5060 fcport->d_id = e->u.new_sess.id;
5061 if (pla) {
5062 fcport->fw_login_state = DSC_LS_PLOGI_PEND;
9b3e0f4d
QT		 5063 memcpy(fcport->node_name,
5064 pla->iocb.u.isp24.u.plogi.node_name,
5065 WWN_SIZE);
726b8548
QT		 5066 qlt_plogi_ack_link(vha, pla, fcport, QLT_PLOGI_LINK_SAME_WWN);
5067 /* we took an extra ref_count to prevent PLOGI ACK when
5068 * fcport/sess has not been created.
5069 */
5070 pla->ref_count--;
5071 }
5072 } else {
b5d15312 5073 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
726b8548
QT		 5074 fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
5075 if (fcport) {
5076 fcport->d_id = e->u.new_sess.id;
726b8548
QT		 5077 fcport->flags |= FCF_FABRIC_DEVICE;
5078 fcport->fw_login_state = DSC_LS_PLOGI_PEND;
c64a87f9 5079 if (e->u.new_sess.fc4_type == FS_FC4TYPE_FCP)
a4239945 5080 fcport->fc4_type = FC4_TYPE_FCP_SCSI;
726b8548 5081
c64a87f9 5082 if (e->u.new_sess.fc4_type == FS_FC4TYPE_NVME) {
2b5b9647
DT		 5083 fcport->fc4_type = FC4_TYPE_OTHER;
5084 fcport->fc4f_nvme = FC4_TYPE_NVME;
5085 }
33b28357 5086
726b8548
QT		 5087 memcpy(fcport->port_name, e->u.new_sess.port_name,
5088 WWN_SIZE);
b5d15312
QT		 5089 } else {
5090 ql_dbg(ql_dbg_disc, vha, 0xffff,
5091 "%s %8phC mem alloc fail.\n",
5092 __func__, e->u.new_sess.port_name);
5093
5094 if (pla)
5095 kmem_cache_free(qla_tgt_plogi_cachep, pla);
5096 return;
5097 }
5098
5099 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
a4239945 5100 /* search again to make sure no one else got ahead */
b5d15312
QT		 5101 tfcp = qla2x00_find_fcport_by_wwpn(vha,
5102 e->u.new_sess.port_name, 1);
5103 if (tfcp) {
5104 /* should rarily happen */
5105 ql_dbg(ql_dbg_disc, vha, 0xffff,
5106 "%s %8phC found existing fcport b4 add. DS %d LS %d\n",
5107 __func__, tfcp->port_name, tfcp->disc_state,
5108 tfcp->fw_login_state);
5109
5110 free_fcport = 1;
5111 } else {
726b8548
QT		 5112 list_add_tail(&fcport->list, &vha->vp_fcports);
5113
19759033
QT		 5114 }
5115 if (pla) {
5116 qlt_plogi_ack_link(vha, pla, fcport,
5117 QLT_PLOGI_LINK_SAME_WWN);
5118 pla->ref_count--;
726b8548
QT		 5119 }
5120 }
5121 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
5122
5123 if (fcport) {
a4239945
QT		 5124 fcport->id_changed = 1;
5125 fcport->scan_state = QLA_FCPORT_FOUND;
5126 memcpy(fcport->node_name, e->u.new_sess.node_name, WWN_SIZE);
5127
5ef696aa 5128 if (pla) {
9cd883f0
QT		 5129 if (pla->iocb.u.isp24.status_subcode == ELS_PRLI) {
5130 u16 wd3_lo;
5131
5132 fcport->fw_login_state = DSC_LS_PRLI_PEND;
5133 fcport->local = 0;
5134 fcport->loop_id =
5135 le16_to_cpu(
5136 pla->iocb.u.isp24.nport_handle);
5137 fcport->fw_login_state = DSC_LS_PRLI_PEND;
5138 wd3_lo =
5139 le16_to_cpu(
5140 pla->iocb.u.isp24.u.prli.wd3_lo);
5141
5142 if (wd3_lo & BIT_7)
5143 fcport->conf_compl_supported = 1;
5144
5145 if ((wd3_lo & BIT_4) == 0)
5146 fcport->port_type = FCT_INITIATOR;
5147 else
5148 fcport->port_type = FCT_TARGET;
5149 }
726b8548 5150 qlt_plogi_ack_unref(vha, pla);
5ef696aa 5151 } else {
1c6cacf4
HR		 5152 fc_port_t *dfcp = NULL;
5153
5ef696aa
QT		 5154 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
5155 tfcp = qla2x00_find_fcport_by_nportid(vha,
5156 &e->u.new_sess.id, 1);
5157 if (tfcp && (tfcp != fcport)) {
5158 /*
5159 * We have a conflict fcport with same NportID.
5160 */
5161 ql_dbg(ql_dbg_disc, vha, 0xffff,
5162 "%s %8phC found conflict b4 add. DS %d LS %d\n",
5163 __func__, tfcp->port_name, tfcp->disc_state,
5164 tfcp->fw_login_state);
5165
5166 switch (tfcp->disc_state) {
5167 case DSC_DELETED:
5168 break;
5169 case DSC_DELETE_PEND:
5170 fcport->login_pause = 1;
5171 tfcp->conflict = fcport;
5172 break;
5173 default:
5174 fcport->login_pause = 1;
5175 tfcp->conflict = fcport;
1c6cacf4 5176 dfcp = tfcp;
5ef696aa
QT		 5177 break;
5178 }
5179 }
5180 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
1c6cacf4
HR		 5181 if (dfcp)
5182 qlt_schedule_sess_for_deletion(tfcp);
a4239945 5183
a4239945 5184
8777e431
QT		 5185 if (N2N_TOPO(vha->hw))
5186 fcport->flags &= ~FCF_FABRIC_DEVICE;
5187
5188 if (N2N_TOPO(vha->hw)) {
5189 if (vha->flags.nvme_enabled) {
5190 fcport->fc4f_nvme = 1;
5191 fcport->n2n_flag = 1;
5192 }
5193 fcport->fw_login_state = 0;
5194 /*
5195 * wait link init done before sending login
5196 */
5197 } else {
5198 qla24xx_fcport_handle_login(vha, fcport);
5199 }
5ef696aa 5200 }
726b8548 5201 }
b5d15312
QT		 5202
5203 if (free_fcport) {
5204 qla2x00_free_fcport(fcport);
5205 if (pla)
5206 kmem_cache_free(qla_tgt_plogi_cachep, pla);
5207 }
726b8548
QT		 5208}
5209
e374f9f5
QT		 5210static void qla_sp_retry(struct scsi_qla_host *vha, struct qla_work_evt *e)
5211{
5212 struct srb *sp = e->u.iosb.sp;
5213 int rval;
5214
5215 rval = qla2x00_start_sp(sp);
5216 if (rval != QLA_SUCCESS) {
5217 ql_dbg(ql_dbg_disc, vha, 0x2043,
5218 "%s: %s: Re-issue IOCB failed (%d).\n",
5219 __func__, sp->name, rval);
5220 qla24xx_sp_unmap(vha, sp);
5221 }
5222}
5223
ac280b67 5224void
e315cd28 5225qla2x00_do_work(struct scsi_qla_host *vha)
0971de7f 5226{
f999f4c1
AV		 5227 struct qla_work_evt *e, *tmp;
5228 unsigned long flags;
5229 LIST_HEAD(work);
80676d05 5230 int rc;
0971de7f 5231
f999f4c1
AV		 5232 spin_lock_irqsave(&vha->work_lock, flags);
5233 list_splice_init(&vha->work_list, &work);
5234 spin_unlock_irqrestore(&vha->work_lock, flags);
5235
5236 list_for_each_entry_safe(e, tmp, &work, list) {
80676d05 5237 rc = QLA_SUCCESS;
0971de7f
AV		 5238 switch (e->type) {
5239 case QLA_EVT_AEN:
e315cd28 5240 fc_host_post_event(vha->host, fc_get_event_number(),
0971de7f
AV		 5241 e->u.aen.code, e->u.aen.data);
5242 break;
8a659571
AV		 5243 case QLA_EVT_IDC_ACK:
5244 qla81xx_idc_ack(vha, e->u.idc_ack.mb);
5245 break;
ac280b67
AV		 5246 case QLA_EVT_ASYNC_LOGIN:
5247 qla2x00_async_login(vha, e->u.logio.fcport,
5248 e->u.logio.data);
5249 break;
ac280b67 5250 case QLA_EVT_ASYNC_LOGOUT:
80676d05 5251 rc = qla2x00_async_logout(vha, e->u.logio.fcport);
ac280b67
AV		 5252 break;
5253 case QLA_EVT_ASYNC_LOGOUT_DONE:
5254 qla2x00_async_logout_done(vha, e->u.logio.fcport,
5255 e->u.logio.data);
5256 break;
5ff1d584
AV		 5257 case QLA_EVT_ASYNC_ADISC:
5258 qla2x00_async_adisc(vha, e->u.logio.fcport,
5259 e->u.logio.data);
5260 break;
3420d36c
AV		 5261 case QLA_EVT_UEVENT:
5262 qla2x00_uevent_emit(vha, e->u.uevent.code);
5263 break;
8ae6d9c7
GM		 5264 case QLA_EVT_AENFX:
5265 qlafx00_process_aen(vha, e);
5266 break;
726b8548
QT		 5267 case QLA_EVT_GPNID:
5268 qla24xx_async_gpnid(vha, &e->u.gpnid.id);
5269 break;
e374f9f5
QT		 5270 case QLA_EVT_UNMAP:
5271 qla24xx_sp_unmap(vha, e->u.iosb.sp);
726b8548 5272 break;
9b3e0f4d
QT		 5273 case QLA_EVT_RELOGIN:
5274 qla2x00_relogin(vha);
5275 break;
726b8548
QT		 5276 case QLA_EVT_NEW_SESS:
5277 qla24xx_create_new_sess(vha, e);
5278 break;
5279 case QLA_EVT_GPDB:
5280 qla24xx_async_gpdb(vha, e->u.fcport.fcport,
5281 e->u.fcport.opt);
5282 break;
a5d42f4c
DG		 5283 case QLA_EVT_PRLI:
5284 qla24xx_async_prli(vha, e->u.fcport.fcport);
5285 break;
726b8548
QT		 5286 case QLA_EVT_GPSC:
5287 qla24xx_async_gpsc(vha, e->u.fcport.fcport);
5288 break;
726b8548
QT		 5289 case QLA_EVT_GNL:
5290 qla24xx_async_gnl(vha, e->u.fcport.fcport);
5291 break;
5292 case QLA_EVT_NACK:
5293 qla24xx_do_nack_work(vha, e);
5294 break;
11aea16a 5295 case QLA_EVT_ASYNC_PRLO:
80676d05 5296 rc = qla2x00_async_prlo(vha, e->u.logio.fcport);
11aea16a
QT		 5297 break;
5298 case QLA_EVT_ASYNC_PRLO_DONE:
5299 qla2x00_async_prlo_done(vha, e->u.logio.fcport,
5300 e->u.logio.data);
5301 break;
a4239945 5302 case QLA_EVT_GPNFT:
33b28357
QT		 5303 qla24xx_async_gpnft(vha, e->u.gpnft.fc4_type,
5304 e->u.gpnft.sp);
a4239945
QT		 5305 break;
5306 case QLA_EVT_GPNFT_DONE:
5307 qla24xx_async_gpnft_done(vha, e->u.iosb.sp);
5308 break;
5309 case QLA_EVT_GNNFT_DONE:
5310 qla24xx_async_gnnft_done(vha, e->u.iosb.sp);
5311 break;
5312 case QLA_EVT_GNNID:
5313 qla24xx_async_gnnid(vha, e->u.fcport.fcport);
5314 break;
5315 case QLA_EVT_GFPNID:
5316 qla24xx_async_gfpnid(vha, e->u.fcport.fcport);
5317 break;
e374f9f5
QT		 5318 case QLA_EVT_SP_RETRY:
5319 qla_sp_retry(vha, e);
cc28e0ac
QT		 5320 break;
5321 case QLA_EVT_IIDMA:
5322 qla_do_iidma_work(vha, e->u.fcport.fcport);
5323 break;
8777e431
QT		 5324 case QLA_EVT_ELS_PLOGI:
5325 qla24xx_els_dcmd2_iocb(vha, ELS_DCMD_PLOGI,
5326 e->u.fcport.fcport, false);
5327 break;
0971de7f 5328 }
80676d05
QT		 5329
5330 if (rc == EAGAIN) {
5331 /* put 'work' at head of 'vha->work_list' */
5332 spin_lock_irqsave(&vha->work_lock, flags);
5333 list_splice(&work, &vha->work_list);
5334 spin_unlock_irqrestore(&vha->work_lock, flags);
5335 break;
5336 }
5337 list_del_init(&e->list);
0971de7f
AV		 5338 if (e->flags & QLA_EVT_FLAG_FREE)
5339 kfree(e);
feafb7b1
AE		 5340
5341 /* For each work completed decrement vha ref count */
5342 QLA_VHA_MARK_NOT_BUSY(vha);
e315cd28 5343 }
e315cd28 5344}
f999f4c1 5345
9b3e0f4d
QT		 5346int qla24xx_post_relogin_work(struct scsi_qla_host *vha)
5347{
5348 struct qla_work_evt *e;
5349
5350 e = qla2x00_alloc_work(vha, QLA_EVT_RELOGIN);
5351
5352 if (!e) {
5353 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
5354 return QLA_FUNCTION_FAILED;
5355 }
5356
5357 return qla2x00_post_work(vha, e);
5358}
5359
e315cd28
AC		 5360/* Relogins all the fcports of a vport
5361 * Context: dpc thread
5362 */
5363void qla2x00_relogin(struct scsi_qla_host *vha)
5364{
5365 fc_port_t *fcport;
23dd98a6 5366 int status, relogin_needed = 0;
726b8548 5367 struct event_arg ea;
e315cd28
AC		 5368
5369 list_for_each_entry(fcport, &vha->vp_fcports, list) {
9cd883f0
QT		 5370 /*
5371 * If the port is not ONLINE then try to login
5372 * to it if we haven't run out of retries.
5373 */
5ff1d584 5374 if (atomic_read(&fcport->state) != FCS_ONLINE &&
23dd98a6
QT		 5375 fcport->login_retry) {
5376 if (fcport->scan_state != QLA_FCPORT_FOUND ||
5377 fcport->disc_state == DSC_LOGIN_COMPLETE)
5378 continue;
e315cd28 5379
23dd98a6
QT		 5380 if (fcport->flags & (FCF_ASYNC_SENT|FCF_ASYNC_ACTIVE) ||
5381 fcport->disc_state == DSC_DELETE_PEND) {
5382 relogin_needed = 1;
5383 } else {
5384 if (vha->hw->current_topology != ISP_CFG_NL) {
5385 memset(&ea, 0, sizeof(ea));
5386 ea.event = FCME_RELOGIN;
5387 ea.fcport = fcport;
5388 qla2x00_fcport_event_handler(vha, &ea);
5389 } else if (vha->hw->current_topology ==
5390 ISP_CFG_NL) {
5391 fcport->login_retry--;
5392 status =
5393 qla2x00_local_device_login(vha,
5394 fcport);
5395 if (status == QLA_SUCCESS) {
5396 fcport->old_loop_id =
5397 fcport->loop_id;
5398 ql_dbg(ql_dbg_disc, vha, 0x2003,
5399 "Port login OK: logged in ID 0x%x.\n",
5400 fcport->loop_id);
5401 qla2x00_update_fcport
5402 (vha, fcport);
5403 } else if (status == 1) {
5404 set_bit(RELOGIN_NEEDED,
5405 &vha->dpc_flags);
5406 /* retry the login again */
5407 ql_dbg(ql_dbg_disc, vha, 0x2007,
5408 "Retrying %d login again loop_id 0x%x.\n",
5409 fcport->login_retry,
5410 fcport->loop_id);
5411 } else {
5412 fcport->login_retry = 0;
5413 }
e315cd28 5414
23dd98a6
QT		 5415 if (fcport->login_retry == 0 &&
5416 status != QLA_SUCCESS)
5417 qla2x00_clear_loop_id(fcport);
5418 }
e315cd28 5419 }
e315cd28
AC		 5420 }
5421 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
5422 break;
0971de7f 5423 }
9b3e0f4d 5424
23dd98a6
QT		 5425 if (relogin_needed)
5426 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
5427
9b3e0f4d
QT		 5428 ql_dbg(ql_dbg_disc, vha, 0x400e,
5429 "Relogin end.\n");
0971de7f
AV		 5430}
5431
7d613ac6
SV		 5432/* Schedule work on any of the dpc-workqueues */
5433void
5434qla83xx_schedule_work(scsi_qla_host_t *base_vha, int work_code)
5435{
5436 struct qla_hw_data *ha = base_vha->hw;
5437
5438 switch (work_code) {
5439 case MBA_IDC_AEN: /* 0x8200 */
5440 if (ha->dpc_lp_wq)
5441 queue_work(ha->dpc_lp_wq, &ha->idc_aen);
5442 break;
5443
5444 case QLA83XX_NIC_CORE_RESET: /* 0x1 */
5445 if (!ha->flags.nic_core_reset_hdlr_active) {
5446 if (ha->dpc_hp_wq)
5447 queue_work(ha->dpc_hp_wq, &ha->nic_core_reset);
5448 } else
5449 ql_dbg(ql_dbg_p3p, base_vha, 0xb05e,
5450 "NIC Core reset is already active. Skip "
5451 "scheduling it again.\n");
5452 break;
5453 case QLA83XX_IDC_STATE_HANDLER: /* 0x2 */
5454 if (ha->dpc_hp_wq)
5455 queue_work(ha->dpc_hp_wq, &ha->idc_state_handler);
5456 break;
5457 case QLA83XX_NIC_CORE_UNRECOVERABLE: /* 0x3 */
5458 if (ha->dpc_hp_wq)
5459 queue_work(ha->dpc_hp_wq, &ha->nic_core_unrecoverable);
5460 break;
5461 default:
5462 ql_log(ql_log_warn, base_vha, 0xb05f,
d939be3a 5463 "Unknown work-code=0x%x.\n", work_code);
7d613ac6
SV		 5464 }
5465
5466 return;
5467}
5468
5469/* Work: Perform NIC Core Unrecoverable state handling */
5470void
5471qla83xx_nic_core_unrecoverable_work(struct work_struct *work)
5472{
5473 struct qla_hw_data *ha =
2ad1b67c 5474 container_of(work, struct qla_hw_data, nic_core_unrecoverable);
7d613ac6
SV		 5475 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5476 uint32_t dev_state = 0;
5477
5478 qla83xx_idc_lock(base_vha, 0);
5479 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
5480 qla83xx_reset_ownership(base_vha);
5481 if (ha->flags.nic_core_reset_owner) {
5482 ha->flags.nic_core_reset_owner = 0;
5483 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
5484 QLA8XXX_DEV_FAILED);
5485 ql_log(ql_log_info, base_vha, 0xb060, "HW State: FAILED.\n");
5486 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
5487 }
5488 qla83xx_idc_unlock(base_vha, 0);
5489}
5490
5491/* Work: Execute IDC state handler */
5492void
5493qla83xx_idc_state_handler_work(struct work_struct *work)
5494{
5495 struct qla_hw_data *ha =
2ad1b67c 5496 container_of(work, struct qla_hw_data, idc_state_handler);
7d613ac6
SV		 5497 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5498 uint32_t dev_state = 0;
5499
5500 qla83xx_idc_lock(base_vha, 0);
5501 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
5502 if (dev_state == QLA8XXX_DEV_FAILED ||
5503 dev_state == QLA8XXX_DEV_NEED_QUIESCENT)
5504 qla83xx_idc_state_handler(base_vha);
5505 qla83xx_idc_unlock(base_vha, 0);
5506}
5507
fa492630 5508static int
7d613ac6
SV		 5509qla83xx_check_nic_core_fw_alive(scsi_qla_host_t *base_vha)
5510{
5511 int rval = QLA_SUCCESS;
5512 unsigned long heart_beat_wait = jiffies + (1 * HZ);
5513 uint32_t heart_beat_counter1, heart_beat_counter2;
5514
5515 do {
5516 if (time_after(jiffies, heart_beat_wait)) {
5517 ql_dbg(ql_dbg_p3p, base_vha, 0xb07c,
5518 "Nic Core f/w is not alive.\n");
5519 rval = QLA_FUNCTION_FAILED;
5520 break;
5521 }
5522
5523 qla83xx_idc_lock(base_vha, 0);
5524 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
5525 &heart_beat_counter1);
5526 qla83xx_idc_unlock(base_vha, 0);
5527 msleep(100);
5528 qla83xx_idc_lock(base_vha, 0);
5529 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
5530 &heart_beat_counter2);
5531 qla83xx_idc_unlock(base_vha, 0);
5532 } while (heart_beat_counter1 == heart_beat_counter2);
5533
5534 return rval;
5535}
5536
5537/* Work: Perform NIC Core Reset handling */
5538void
5539qla83xx_nic_core_reset_work(struct work_struct *work)
5540{
5541 struct qla_hw_data *ha =
5542 container_of(work, struct qla_hw_data, nic_core_reset);
5543 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5544 uint32_t dev_state = 0;
5545
81178772
SK		 5546 if (IS_QLA2031(ha)) {
5547 if (qla2xxx_mctp_dump(base_vha) != QLA_SUCCESS)
5548 ql_log(ql_log_warn, base_vha, 0xb081,
5549 "Failed to dump mctp\n");
5550 return;
5551 }
5552
7d613ac6
SV		 5553 if (!ha->flags.nic_core_reset_hdlr_active) {
5554 if (qla83xx_check_nic_core_fw_alive(base_vha) == QLA_SUCCESS) {
5555 qla83xx_idc_lock(base_vha, 0);
5556 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE,
5557 &dev_state);
5558 qla83xx_idc_unlock(base_vha, 0);
5559 if (dev_state != QLA8XXX_DEV_NEED_RESET) {
5560 ql_dbg(ql_dbg_p3p, base_vha, 0xb07a,
5561 "Nic Core f/w is alive.\n");
5562 return;
5563 }
5564 }
5565
5566 ha->flags.nic_core_reset_hdlr_active = 1;
5567 if (qla83xx_nic_core_reset(base_vha)) {
5568 /* NIC Core reset failed. */
5569 ql_dbg(ql_dbg_p3p, base_vha, 0xb061,
5570 "NIC Core reset failed.\n");
5571 }
5572 ha->flags.nic_core_reset_hdlr_active = 0;
5573 }
5574}
5575
5576/* Work: Handle 8200 IDC aens */
5577void
5578qla83xx_service_idc_aen(struct work_struct *work)
5579{
5580 struct qla_hw_data *ha =
5581 container_of(work, struct qla_hw_data, idc_aen);
5582 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5583 uint32_t dev_state, idc_control;
5584
5585 qla83xx_idc_lock(base_vha, 0);
5586 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
5587 qla83xx_rd_reg(base_vha, QLA83XX_IDC_CONTROL, &idc_control);
5588 qla83xx_idc_unlock(base_vha, 0);
5589 if (dev_state == QLA8XXX_DEV_NEED_RESET) {
5590 if (idc_control & QLA83XX_IDC_GRACEFUL_RESET) {
5591 ql_dbg(ql_dbg_p3p, base_vha, 0xb062,
5592 "Application requested NIC Core Reset.\n");
5593 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
5594 } else if (qla83xx_check_nic_core_fw_alive(base_vha) ==
5595 QLA_SUCCESS) {
5596 ql_dbg(ql_dbg_p3p, base_vha, 0xb07b,
5597 "Other protocol driver requested NIC Core Reset.\n");
5598 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
5599 }
5600 } else if (dev_state == QLA8XXX_DEV_FAILED ||
5601 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) {
5602 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
5603 }
5604}
5605
5606static void
5607qla83xx_wait_logic(void)
5608{
5609 int i;
5610
5611 /* Yield CPU */
5612 if (!in_interrupt()) {
5613 /*
5614 * Wait about 200ms before retrying again.
5615 * This controls the number of retries for single
5616 * lock operation.
5617 */
5618 msleep(100);
5619 schedule();
5620 } else {
5621 for (i = 0; i < 20; i++)
5622 cpu_relax(); /* This a nop instr on i386 */
5623 }
5624}
5625
fa492630 5626static int
7d613ac6
SV		 5627qla83xx_force_lock_recovery(scsi_qla_host_t *base_vha)
5628{
5629 int rval;
5630 uint32_t data;
5631 uint32_t idc_lck_rcvry_stage_mask = 0x3;
5632 uint32_t idc_lck_rcvry_owner_mask = 0x3c;
5633 struct qla_hw_data *ha = base_vha->hw;
6c315553
SK		 5634 ql_dbg(ql_dbg_p3p, base_vha, 0xb086,
5635 "Trying force recovery of the IDC lock.\n");
7d613ac6
SV		 5636
5637 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, &data);
5638 if (rval)
5639 return rval;
5640
5641 if ((data & idc_lck_rcvry_stage_mask) > 0) {
5642 return QLA_SUCCESS;
5643 } else {
5644 data = (IDC_LOCK_RECOVERY_STAGE1) | (ha->portnum << 2);
5645 rval = qla83xx_wr_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
5646 data);
5647 if (rval)
5648 return rval;
5649
5650 msleep(200);
5651
5652 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
5653 &data);
5654 if (rval)
5655 return rval;
5656
5657 if (((data & idc_lck_rcvry_owner_mask) >> 2) == ha->portnum) {
5658 data &= (IDC_LOCK_RECOVERY_STAGE2 |
5659 ~(idc_lck_rcvry_stage_mask));
5660 rval = qla83xx_wr_reg(base_vha,
5661 QLA83XX_IDC_LOCK_RECOVERY, data);
5662 if (rval)
5663 return rval;
5664
5665 /* Forcefully perform IDC UnLock */
5666 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK,
5667 &data);
5668 if (rval)
5669 return rval;
5670 /* Clear lock-id by setting 0xff */
5671 rval = qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
5672 0xff);
5673 if (rval)
5674 return rval;
5675 /* Clear lock-recovery by setting 0x0 */
5676 rval = qla83xx_wr_reg(base_vha,
5677 QLA83XX_IDC_LOCK_RECOVERY, 0x0);
5678 if (rval)
5679 return rval;
5680 } else
5681 return QLA_SUCCESS;
5682 }
5683
5684 return rval;
5685}
5686
fa492630 5687static int
7d613ac6
SV		 5688qla83xx_idc_lock_recovery(scsi_qla_host_t *base_vha)
5689{
5690 int rval = QLA_SUCCESS;
5691 uint32_t o_drv_lockid, n_drv_lockid;
5692 unsigned long lock_recovery_timeout;
5693
5694 lock_recovery_timeout = jiffies + QLA83XX_MAX_LOCK_RECOVERY_WAIT;
5695retry_lockid:
5696 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &o_drv_lockid);
5697 if (rval)
5698 goto exit;
5699
5700 /* MAX wait time before forcing IDC Lock recovery = 2 secs */
5701 if (time_after_eq(jiffies, lock_recovery_timeout)) {
5702 if (qla83xx_force_lock_recovery(base_vha) == QLA_SUCCESS)
5703 return QLA_SUCCESS;
5704 else
5705 return QLA_FUNCTION_FAILED;
5706 }
5707
5708 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &n_drv_lockid);
5709 if (rval)
5710 goto exit;
5711
5712 if (o_drv_lockid == n_drv_lockid) {
5713 qla83xx_wait_logic();
5714 goto retry_lockid;
5715 } else
5716 return QLA_SUCCESS;
5717
5718exit:
5719 return rval;
5720}
5721
5722void
5723qla83xx_idc_lock(scsi_qla_host_t *base_vha, uint16_t requester_id)
5724{
5725 uint16_t options = (requester_id << 15) | BIT_6;
5726 uint32_t data;
6c315553 5727 uint32_t lock_owner;
7d613ac6
SV		 5728 struct qla_hw_data *ha = base_vha->hw;
5729
5730 /* IDC-lock implementation using driver-lock/lock-id remote registers */
5731retry_lock:
5732 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCK, &data)
5733 == QLA_SUCCESS) {
5734 if (data) {
5735 /* Setting lock-id to our function-number */
5736 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
5737 ha->portnum);
5738 } else {
6c315553
SK		 5739 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID,
5740 &lock_owner);
7d613ac6 5741 ql_dbg(ql_dbg_p3p, base_vha, 0xb063,
6c315553
SK		 5742 "Failed to acquire IDC lock, acquired by %d, "
5743 "retrying...\n", lock_owner);
7d613ac6
SV		 5744
5745 /* Retry/Perform IDC-Lock recovery */
5746 if (qla83xx_idc_lock_recovery(base_vha)
5747 == QLA_SUCCESS) {
5748 qla83xx_wait_logic();
5749 goto retry_lock;
5750 } else
5751 ql_log(ql_log_warn, base_vha, 0xb075,
5752 "IDC Lock recovery FAILED.\n");
5753 }
5754
5755 }
5756
5757 return;
5758
5759 /* XXX: IDC-lock implementation using access-control mbx */
5760retry_lock2:
5761 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
5762 ql_dbg(ql_dbg_p3p, base_vha, 0xb072,
5763 "Failed to acquire IDC lock. retrying...\n");
5764 /* Retry/Perform IDC-Lock recovery */
5765 if (qla83xx_idc_lock_recovery(base_vha) == QLA_SUCCESS) {
5766 qla83xx_wait_logic();
5767 goto retry_lock2;
5768 } else
5769 ql_log(ql_log_warn, base_vha, 0xb076,
5770 "IDC Lock recovery FAILED.\n");
5771 }
5772
5773 return;
5774}
5775
5776void
5777qla83xx_idc_unlock(scsi_qla_host_t *base_vha, uint16_t requester_id)
5778{
5897cb2f
BVA		 5779#if 0
5780 uint16_t options = (requester_id << 15) | BIT_7;
5781#endif
5782 uint16_t retry;
7d613ac6
SV		 5783 uint32_t data;
5784 struct qla_hw_data *ha = base_vha->hw;
5785
5786 /* IDC-unlock implementation using driver-unlock/lock-id
5787 * remote registers
5788 */
5789 retry = 0;
5790retry_unlock:
5791 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &data)
5792 == QLA_SUCCESS) {
5793 if (data == ha->portnum) {
5794 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, &data);
5795 /* Clearing lock-id by setting 0xff */
5796 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 0xff);
5797 } else if (retry < 10) {
5798 /* SV: XXX: IDC unlock retrying needed here? */
5799
5800 /* Retry for IDC-unlock */
5801 qla83xx_wait_logic();
5802 retry++;
5803 ql_dbg(ql_dbg_p3p, base_vha, 0xb064,
ee6a8773 5804 "Failed to release IDC lock, retrying=%d\n", retry);
7d613ac6
SV		 5805 goto retry_unlock;
5806 }
5807 } else if (retry < 10) {
5808 /* Retry for IDC-unlock */
5809 qla83xx_wait_logic();
5810 retry++;
5811 ql_dbg(ql_dbg_p3p, base_vha, 0xb065,
ee6a8773 5812 "Failed to read drv-lockid, retrying=%d\n", retry);
7d613ac6
SV		 5813 goto retry_unlock;
5814 }
5815
5816 return;
5817
5897cb2f 5818#if 0
7d613ac6
SV		 5819 /* XXX: IDC-unlock implementation using access-control mbx */
5820 retry = 0;
5821retry_unlock2:
5822 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
5823 if (retry < 10) {
5824 /* Retry for IDC-unlock */
5825 qla83xx_wait_logic();
5826 retry++;
5827 ql_dbg(ql_dbg_p3p, base_vha, 0xb066,
ee6a8773 5828 "Failed to release IDC lock, retrying=%d\n", retry);
7d613ac6
SV		 5829 goto retry_unlock2;
5830 }
5831 }
5832
5833 return;
5897cb2f 5834#endif
7d613ac6
SV		 5835}
5836
5837int
5838__qla83xx_set_drv_presence(scsi_qla_host_t *vha)
5839{
5840 int rval = QLA_SUCCESS;
5841 struct qla_hw_data *ha = vha->hw;
5842 uint32_t drv_presence;
5843
5844 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
5845 if (rval == QLA_SUCCESS) {
5846 drv_presence |= (1 << ha->portnum);
5847 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
5848 drv_presence);
5849 }
5850
5851 return rval;
5852}
5853
5854int
5855qla83xx_set_drv_presence(scsi_qla_host_t *vha)
5856{
5857 int rval = QLA_SUCCESS;
5858
5859 qla83xx_idc_lock(vha, 0);
5860 rval = __qla83xx_set_drv_presence(vha);
5861 qla83xx_idc_unlock(vha, 0);
5862
5863 return rval;
5864}
5865
5866int
5867__qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
5868{
5869 int rval = QLA_SUCCESS;
5870 struct qla_hw_data *ha = vha->hw;
5871 uint32_t drv_presence;
5872
5873 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
5874 if (rval == QLA_SUCCESS) {
5875 drv_presence &= ~(1 << ha->portnum);
5876 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
5877 drv_presence);
5878 }
5879
5880 return rval;
5881}
5882
5883int
5884qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
5885{
5886 int rval = QLA_SUCCESS;
5887
5888 qla83xx_idc_lock(vha, 0);
5889 rval = __qla83xx_clear_drv_presence(vha);
5890 qla83xx_idc_unlock(vha, 0);
5891
5892 return rval;
5893}
5894
fa492630 5895static void
7d613ac6
SV		 5896qla83xx_need_reset_handler(scsi_qla_host_t *vha)
5897{
5898 struct qla_hw_data *ha = vha->hw;
5899 uint32_t drv_ack, drv_presence;
5900 unsigned long ack_timeout;
5901
5902 /* Wait for IDC ACK from all functions (DRV-ACK == DRV-PRESENCE) */
5903 ack_timeout = jiffies + (ha->fcoe_reset_timeout * HZ);
5904 while (1) {
5905 qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
5906 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
807fb6d8 5907 if ((drv_ack & drv_presence) == drv_presence)
7d613ac6
SV		 5908 break;
5909
5910 if (time_after_eq(jiffies, ack_timeout)) {
5911 ql_log(ql_log_warn, vha, 0xb067,
5912 "RESET ACK TIMEOUT! drv_presence=0x%x "
5913 "drv_ack=0x%x\n", drv_presence, drv_ack);
5914 /*
5915 * The function(s) which did not ack in time are forced
5916 * to withdraw any further participation in the IDC
5917 * reset.
5918 */
5919 if (drv_ack != drv_presence)
5920 qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
5921 drv_ack);
5922 break;
5923 }
5924
5925 qla83xx_idc_unlock(vha, 0);
5926 msleep(1000);
5927 qla83xx_idc_lock(vha, 0);
5928 }
5929
5930 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_COLD);
5931 ql_log(ql_log_info, vha, 0xb068, "HW State: COLD/RE-INIT.\n");
5932}
5933
fa492630 5934static int
7d613ac6
SV		 5935qla83xx_device_bootstrap(scsi_qla_host_t *vha)
5936{
5937 int rval = QLA_SUCCESS;
5938 uint32_t idc_control;
5939
5940 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_INITIALIZING);
5941 ql_log(ql_log_info, vha, 0xb069, "HW State: INITIALIZING.\n");
5942
5943 /* Clearing IDC-Control Graceful-Reset Bit before resetting f/w */
5944 __qla83xx_get_idc_control(vha, &idc_control);
5945 idc_control &= ~QLA83XX_IDC_GRACEFUL_RESET;
5946 __qla83xx_set_idc_control(vha, 0);
5947
5948 qla83xx_idc_unlock(vha, 0);
5949 rval = qla83xx_restart_nic_firmware(vha);
5950 qla83xx_idc_lock(vha, 0);
5951
5952 if (rval != QLA_SUCCESS) {
5953 ql_log(ql_log_fatal, vha, 0xb06a,
5954 "Failed to restart NIC f/w.\n");
5955 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_FAILED);
5956 ql_log(ql_log_info, vha, 0xb06b, "HW State: FAILED.\n");
5957 } else {
5958 ql_dbg(ql_dbg_p3p, vha, 0xb06c,
5959 "Success in restarting nic f/w.\n");
5960 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_READY);
5961 ql_log(ql_log_info, vha, 0xb06d, "HW State: READY.\n");
5962 }
5963
5964 return rval;
5965}
5966
5967/* Assumes idc_lock always held on entry */
5968int
5969qla83xx_idc_state_handler(scsi_qla_host_t *base_vha)
5970{
5971 struct qla_hw_data *ha = base_vha->hw;
5972 int rval = QLA_SUCCESS;
5973 unsigned long dev_init_timeout;
5974 uint32_t dev_state;
5975
5976 /* Wait for MAX-INIT-TIMEOUT for the device to go ready */
5977 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ);
5978
5979 while (1) {
5980
5981 if (time_after_eq(jiffies, dev_init_timeout)) {
5982 ql_log(ql_log_warn, base_vha, 0xb06e,
5983 "Initialization TIMEOUT!\n");
5984 /* Init timeout. Disable further NIC Core
5985 * communication.
5986 */
5987 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
5988 QLA8XXX_DEV_FAILED);
5989 ql_log(ql_log_info, base_vha, 0xb06f,
5990 "HW State: FAILED.\n");
5991 }
5992
5993 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
5994 switch (dev_state) {
5995 case QLA8XXX_DEV_READY:
5996 if (ha->flags.nic_core_reset_owner)
5997 qla83xx_idc_audit(base_vha,
5998 IDC_AUDIT_COMPLETION);
5999 ha->flags.nic_core_reset_owner = 0;
6000 ql_dbg(ql_dbg_p3p, base_vha, 0xb070,
6001 "Reset_owner reset by 0x%x.\n",
6002 ha->portnum);
6003 goto exit;
6004 case QLA8XXX_DEV_COLD:
6005 if (ha->flags.nic_core_reset_owner)
6006 rval = qla83xx_device_bootstrap(base_vha);
6007 else {
6008 /* Wait for AEN to change device-state */
6009 qla83xx_idc_unlock(base_vha, 0);
6010 msleep(1000);
6011 qla83xx_idc_lock(base_vha, 0);
6012 }
6013 break;
6014 case QLA8XXX_DEV_INITIALIZING:
6015 /* Wait for AEN to change device-state */
6016 qla83xx_idc_unlock(base_vha, 0);
6017 msleep(1000);
6018 qla83xx_idc_lock(base_vha, 0);
6019 break;
6020 case QLA8XXX_DEV_NEED_RESET:
6021 if (!ql2xdontresethba && ha->flags.nic_core_reset_owner)
6022 qla83xx_need_reset_handler(base_vha);
6023 else {
6024 /* Wait for AEN to change device-state */
6025 qla83xx_idc_unlock(base_vha, 0);
6026 msleep(1000);
6027 qla83xx_idc_lock(base_vha, 0);
6028 }
6029 /* reset timeout value after need reset handler */
6030 dev_init_timeout = jiffies +
6031 (ha->fcoe_dev_init_timeout * HZ);
6032 break;
6033 case QLA8XXX_DEV_NEED_QUIESCENT:
6034 /* XXX: DEBUG for now */
6035 qla83xx_idc_unlock(base_vha, 0);
6036 msleep(1000);
6037 qla83xx_idc_lock(base_vha, 0);
6038 break;
6039 case QLA8XXX_DEV_QUIESCENT:
6040 /* XXX: DEBUG for now */
6041 if (ha->flags.quiesce_owner)
6042 goto exit;
6043
6044 qla83xx_idc_unlock(base_vha, 0);
6045 msleep(1000);
6046 qla83xx_idc_lock(base_vha, 0);
6047 dev_init_timeout = jiffies +
6048 (ha->fcoe_dev_init_timeout * HZ);
6049 break;
6050 case QLA8XXX_DEV_FAILED:
6051 if (ha->flags.nic_core_reset_owner)
6052 qla83xx_idc_audit(base_vha,
6053 IDC_AUDIT_COMPLETION);
6054 ha->flags.nic_core_reset_owner = 0;
6055 __qla83xx_clear_drv_presence(base_vha);
6056 qla83xx_idc_unlock(base_vha, 0);
6057 qla8xxx_dev_failed_handler(base_vha);
6058 rval = QLA_FUNCTION_FAILED;
6059 qla83xx_idc_lock(base_vha, 0);
6060 goto exit;
6061 case QLA8XXX_BAD_VALUE:
6062 qla83xx_idc_unlock(base_vha, 0);
6063 msleep(1000);
6064 qla83xx_idc_lock(base_vha, 0);
6065 break;
6066 default:
6067 ql_log(ql_log_warn, base_vha, 0xb071,
d939be3a 6068 "Unknown Device State: %x.\n", dev_state);
7d613ac6
SV		 6069 qla83xx_idc_unlock(base_vha, 0);
6070 qla8xxx_dev_failed_handler(base_vha);
6071 rval = QLA_FUNCTION_FAILED;
6072 qla83xx_idc_lock(base_vha, 0);
6073 goto exit;
6074 }
6075 }
6076
6077exit:
6078 return rval;
6079}
6080
f3ddac19
CD		 6081void
6082qla2x00_disable_board_on_pci_error(struct work_struct *work)
6083{
6084 struct qla_hw_data *ha = container_of(work, struct qla_hw_data,
6085 board_disable);
6086 struct pci_dev *pdev = ha->pdev;
6087 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
6088
726b8548
QT		 6089 /*
6090 * if UNLOAD flag is already set, then continue unload,
783e0dc4
SC		 6091 * where it was set first.
6092 */
6093 if (test_bit(UNLOADING, &base_vha->dpc_flags))
6094 return;
6095
f3ddac19
CD		 6096 ql_log(ql_log_warn, base_vha, 0x015b,
6097 "Disabling adapter.\n");
6098
efdb5760
SC		 6099 if (!atomic_read(&pdev->enable_cnt)) {
6100 ql_log(ql_log_info, base_vha, 0xfffc,
6101 "PCI device disabled, no action req for PCI error=%lx\n",
6102 base_vha->pci_flags);
6103 return;
6104 }
6105
726b8548
QT		 6106 qla2x00_wait_for_sess_deletion(base_vha);
6107
f3ddac19
CD		 6108 set_bit(UNLOADING, &base_vha->dpc_flags);
6109
6110 qla2x00_delete_all_vps(ha, base_vha);
6111
6112 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
6113
6114 qla2x00_dfs_remove(base_vha);
6115
6116 qla84xx_put_chip(base_vha);
6117
6118 if (base_vha->timer_active)
6119 qla2x00_stop_timer(base_vha);
6120
6121 base_vha->flags.online = 0;
6122
6123 qla2x00_destroy_deferred_work(ha);
6124
6125 /*
6126 * Do not try to stop beacon blink as it will issue a mailbox
6127 * command.
6128 */
6129 qla2x00_free_sysfs_attr(base_vha, false);
6130
6131 fc_remove_host(base_vha->host);
6132
6133 scsi_remove_host(base_vha->host);
6134
6135 base_vha->flags.init_done = 0;
6136 qla25xx_delete_queues(base_vha);
f3ddac19 6137 qla2x00_free_fcports(base_vha);
093df737 6138 qla2x00_free_irqs(base_vha);
f3ddac19
CD		 6139 qla2x00_mem_free(ha);
6140 qla82xx_md_free(base_vha);
6141 qla2x00_free_queues(ha);
6142
f3ddac19
CD		 6143 qla2x00_unmap_iobases(ha);
6144
6145 pci_release_selected_regions(ha->pdev, ha->bars);
f3ddac19
CD		 6146 pci_disable_pcie_error_reporting(pdev);
6147 pci_disable_device(pdev);
f3ddac19 6148
beb9e315
JL		 6149 /*
6150 * Let qla2x00_remove_one cleanup qla_hw_data on device removal.
6151 */
f3ddac19
CD		 6152}
6153
1da177e4
LT		 6154/**************************************************************************
6155* qla2x00_do_dpc
6156* This kernel thread is a task that is schedule by the interrupt handler
6157* to perform the background processing for interrupts.
6158*
6159* Notes:
6160* This task always run in the context of a kernel thread. It
6161* is kick-off by the driver's detect code and starts up
6162* up one per adapter. It immediately goes to sleep and waits for
6163* some fibre event. When either the interrupt handler or
6164* the timer routine detects a event it will one of the task
6165* bits then wake us up.
6166**************************************************************************/
6167static int
6168qla2x00_do_dpc(void *data)
6169{
e315cd28
AC		 6170 scsi_qla_host_t *base_vha;
6171 struct qla_hw_data *ha;
d7459527
MH		 6172 uint32_t online;
6173 struct qla_qpair *qpair;
1da177e4 6174
e315cd28
AC		 6175 ha = (struct qla_hw_data *)data;
6176 base_vha = pci_get_drvdata(ha->pdev);
1da177e4 6177
8698a745 6178 set_user_nice(current, MIN_NICE);
1da177e4 6179
563585ec 6180 set_current_state(TASK_INTERRUPTIBLE);
39a11240 6181 while (!kthread_should_stop()) {
7c3df132
SK		 6182 ql_dbg(ql_dbg_dpc, base_vha, 0x4000,
6183 "DPC handler sleeping.\n");
1da177e4 6184
39a11240 6185 schedule();
1da177e4 6186
c142caf0
AV		 6187 if (!base_vha->flags.init_done || ha->flags.mbox_busy)
6188 goto end_loop;
1da177e4 6189
85880801 6190 if (ha->flags.eeh_busy) {
7c3df132
SK		 6191 ql_dbg(ql_dbg_dpc, base_vha, 0x4003,
6192 "eeh_busy=%d.\n", ha->flags.eeh_busy);
c142caf0 6193 goto end_loop;
85880801
AV		 6194 }
6195
1da177e4
LT		 6196 ha->dpc_active = 1;
6197
5f28d2d7
SK		 6198 ql_dbg(ql_dbg_dpc + ql_dbg_verbose, base_vha, 0x4001,
6199 "DPC handler waking up, dpc_flags=0x%lx.\n",
6200 base_vha->dpc_flags);
1da177e4 6201
a29b3dd7
JC		 6202 if (test_bit(UNLOADING, &base_vha->dpc_flags))
6203 break;
6204
7ec0effd
AD		 6205 if (IS_P3P_TYPE(ha)) {
6206 if (IS_QLA8044(ha)) {
6207 if (test_and_clear_bit(ISP_UNRECOVERABLE,
6208 &base_vha->dpc_flags)) {
6209 qla8044_idc_lock(ha);
6210 qla8044_wr_direct(base_vha,
6211 QLA8044_CRB_DEV_STATE_INDEX,
6212 QLA8XXX_DEV_FAILED);
6213 qla8044_idc_unlock(ha);
6214 ql_log(ql_log_info, base_vha, 0x4004,
6215 "HW State: FAILED.\n");
6216 qla8044_device_state_handler(base_vha);
6217 continue;
6218 }
6219
6220 } else {
6221 if (test_and_clear_bit(ISP_UNRECOVERABLE,
6222 &base_vha->dpc_flags)) {
6223 qla82xx_idc_lock(ha);
6224 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
6225 QLA8XXX_DEV_FAILED);
6226 qla82xx_idc_unlock(ha);
6227 ql_log(ql_log_info, base_vha, 0x0151,
6228 "HW State: FAILED.\n");
6229 qla82xx_device_state_handler(base_vha);
6230 continue;
6231 }
a9083016
GM		 6232 }
6233
6234 if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED,
6235 &base_vha->dpc_flags)) {
6236
7c3df132
SK		 6237 ql_dbg(ql_dbg_dpc, base_vha, 0x4005,
6238 "FCoE context reset scheduled.\n");
a9083016
GM		 6239 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
6240 &base_vha->dpc_flags))) {
6241 if (qla82xx_fcoe_ctx_reset(base_vha)) {
6242 /* FCoE-ctx reset failed.
6243 * Escalate to chip-reset
6244 */
6245 set_bit(ISP_ABORT_NEEDED,
6246 &base_vha->dpc_flags);
6247 }
6248 clear_bit(ABORT_ISP_ACTIVE,
6249 &base_vha->dpc_flags);
6250 }
6251
7c3df132
SK		 6252 ql_dbg(ql_dbg_dpc, base_vha, 0x4006,
6253 "FCoE context reset end.\n");
a9083016 6254 }
8ae6d9c7
GM		 6255 } else if (IS_QLAFX00(ha)) {
6256 if (test_and_clear_bit(ISP_UNRECOVERABLE,
6257 &base_vha->dpc_flags)) {
6258 ql_dbg(ql_dbg_dpc, base_vha, 0x4020,
6259 "Firmware Reset Recovery\n");
6260 if (qlafx00_reset_initialize(base_vha)) {
6261 /* Failed. Abort isp later. */
6262 if (!test_bit(UNLOADING,
f92f82d6 6263 &base_vha->dpc_flags)) {
8ae6d9c7
GM		 6264 set_bit(ISP_UNRECOVERABLE,
6265 &base_vha->dpc_flags);
6266 ql_dbg(ql_dbg_dpc, base_vha,
6267 0x4021,
6268 "Reset Recovery Failed\n");
f92f82d6 6269 }
8ae6d9c7
GM		 6270 }
6271 }
6272
6273 if (test_and_clear_bit(FX00_TARGET_SCAN,
6274 &base_vha->dpc_flags)) {
6275 ql_dbg(ql_dbg_dpc, base_vha, 0x4022,
6276 "ISPFx00 Target Scan scheduled\n");
6277 if (qlafx00_rescan_isp(base_vha)) {
6278 if (!test_bit(UNLOADING,
6279 &base_vha->dpc_flags))
6280 set_bit(ISP_UNRECOVERABLE,
6281 &base_vha->dpc_flags);
6282 ql_dbg(ql_dbg_dpc, base_vha, 0x401e,
6283 "ISPFx00 Target Scan Failed\n");
6284 }
6285 ql_dbg(ql_dbg_dpc, base_vha, 0x401f,
6286 "ISPFx00 Target Scan End\n");
6287 }
e8f5e95d
AB		 6288 if (test_and_clear_bit(FX00_HOST_INFO_RESEND,
6289 &base_vha->dpc_flags)) {
6290 ql_dbg(ql_dbg_dpc, base_vha, 0x4023,
6291 "ISPFx00 Host Info resend scheduled\n");
6292 qlafx00_fx_disc(base_vha,
6293 &base_vha->hw->mr.fcport,
6294 FXDISC_REG_HOST_INFO);
6295 }
a9083016
GM		 6296 }
6297
e4e3a2ce
QT		 6298 if (test_and_clear_bit(DETECT_SFP_CHANGE,
6299 &base_vha->dpc_flags) &&
6300 !test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) {
6301 qla24xx_detect_sfp(base_vha);
6302
6303 if (ha->flags.detected_lr_sfp !=
6304 ha->flags.using_lr_setting)
6305 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
6306 }
6307
b08abbd9
QT		 6308 if (test_and_clear_bit
6309 (ISP_ABORT_NEEDED, &base_vha->dpc_flags) &&
6310 !test_bit(UNLOADING, &base_vha->dpc_flags)) {
93eca613
QT		 6311 bool do_reset = true;
6312
0645cb83 6313 switch (base_vha->qlini_mode) {
93eca613
QT		 6314 case QLA2XXX_INI_MODE_ENABLED:
6315 break;
6316 case QLA2XXX_INI_MODE_DISABLED:
0645cb83
QT		 6317 if (!qla_tgt_mode_enabled(base_vha) &&
6318 !ha->flags.fw_started)
93eca613
QT		 6319 do_reset = false;
6320 break;
6321 case QLA2XXX_INI_MODE_DUAL:
0645cb83
QT		 6322 if (!qla_dual_mode_enabled(base_vha) &&
6323 !ha->flags.fw_started)
93eca613
QT		 6324 do_reset = false;
6325 break;
6326 default:
6327 break;
6328 }
1da177e4 6329
93eca613 6330 if (do_reset && !(test_and_set_bit(ABORT_ISP_ACTIVE,
e315cd28 6331 &base_vha->dpc_flags))) {
93eca613
QT		 6332 ql_dbg(ql_dbg_dpc, base_vha, 0x4007,
6333 "ISP abort scheduled.\n");
a9083016 6334 if (ha->isp_ops->abort_isp(base_vha)) {
1da177e4
LT		 6335 /* failed. retry later */
6336 set_bit(ISP_ABORT_NEEDED,
e315cd28 6337 &base_vha->dpc_flags);
99363ef8 6338 }
e315cd28
AC		 6339 clear_bit(ABORT_ISP_ACTIVE,
6340 &base_vha->dpc_flags);
93eca613
QT		 6341 ql_dbg(ql_dbg_dpc, base_vha, 0x4008,
6342 "ISP abort end.\n");
99363ef8 6343 }
1da177e4
LT		 6344 }
6345
a394aac8
DJ		 6346 if (test_and_clear_bit(FCPORT_UPDATE_NEEDED,
6347 &base_vha->dpc_flags)) {
e315cd28 6348 qla2x00_update_fcports(base_vha);
c9c5ced9 6349 }
d97994dc 6350
8ae6d9c7
GM		 6351 if (IS_QLAFX00(ha))
6352 goto loop_resync_check;
6353
579d12b5 6354 if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) {
7c3df132
SK		 6355 ql_dbg(ql_dbg_dpc, base_vha, 0x4009,
6356 "Quiescence mode scheduled.\n");
7ec0effd
AD		 6357 if (IS_P3P_TYPE(ha)) {
6358 if (IS_QLA82XX(ha))
6359 qla82xx_device_state_handler(base_vha);
6360 if (IS_QLA8044(ha))
6361 qla8044_device_state_handler(base_vha);
8fcd6b8b
CD		 6362 clear_bit(ISP_QUIESCE_NEEDED,
6363 &base_vha->dpc_flags);
6364 if (!ha->flags.quiesce_owner) {
6365 qla2x00_perform_loop_resync(base_vha);
7ec0effd
AD		 6366 if (IS_QLA82XX(ha)) {
6367 qla82xx_idc_lock(ha);
6368 qla82xx_clear_qsnt_ready(
6369 base_vha);
6370 qla82xx_idc_unlock(ha);
6371 } else if (IS_QLA8044(ha)) {
6372 qla8044_idc_lock(ha);
6373 qla8044_clear_qsnt_ready(
6374 base_vha);
6375 qla8044_idc_unlock(ha);
6376 }
8fcd6b8b
CD		 6377 }
6378 } else {
6379 clear_bit(ISP_QUIESCE_NEEDED,
6380 &base_vha->dpc_flags);
6381 qla2x00_quiesce_io(base_vha);
579d12b5 6382 }
7c3df132
SK		 6383 ql_dbg(ql_dbg_dpc, base_vha, 0x400a,
6384 "Quiescence mode end.\n");
579d12b5
SK		 6385 }
6386
e315cd28 6387 if (test_and_clear_bit(RESET_MARKER_NEEDED,
8ae6d9c7 6388 &base_vha->dpc_flags) &&
e315cd28 6389 (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) {
1da177e4 6390
7c3df132
SK		 6391 ql_dbg(ql_dbg_dpc, base_vha, 0x400b,
6392 "Reset marker scheduled.\n");
e315cd28
AC		 6393 qla2x00_rst_aen(base_vha);
6394 clear_bit(RESET_ACTIVE, &base_vha->dpc_flags);
7c3df132
SK		 6395 ql_dbg(ql_dbg_dpc, base_vha, 0x400c,
6396 "Reset marker end.\n");
1da177e4
LT		 6397 }
6398
6399 /* Retry each device up to login retry count */
4005a995 6400 if (test_bit(RELOGIN_NEEDED, &base_vha->dpc_flags) &&
e315cd28
AC		 6401 !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) &&
6402 atomic_read(&base_vha->loop_state) != LOOP_DOWN) {
1da177e4 6403
4005a995
QT		 6404 if (!base_vha->relogin_jif ||
6405 time_after_eq(jiffies, base_vha->relogin_jif)) {
6406 base_vha->relogin_jif = jiffies + HZ;
6407 clear_bit(RELOGIN_NEEDED, &base_vha->dpc_flags);
6408
9b3e0f4d 6409 ql_dbg(ql_dbg_disc, base_vha, 0x400d,
4005a995 6410 "Relogin scheduled.\n");
9b3e0f4d 6411 qla24xx_post_relogin_work(base_vha);
4005a995 6412 }
1da177e4 6413 }
8ae6d9c7 6414loop_resync_check:
e315cd28 6415 if (test_and_clear_bit(LOOP_RESYNC_NEEDED,
8ae6d9c7 6416 &base_vha->dpc_flags)) {
1da177e4 6417
7c3df132
SK		 6418 ql_dbg(ql_dbg_dpc, base_vha, 0x400f,
6419 "Loop resync scheduled.\n");
1da177e4
LT		 6420
6421 if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE,
e315cd28 6422 &base_vha->dpc_flags))) {
1da177e4 6423
52c82823 6424 qla2x00_loop_resync(base_vha);
1da177e4 6425
e315cd28
AC		 6426 clear_bit(LOOP_RESYNC_ACTIVE,
6427 &base_vha->dpc_flags);
1da177e4
LT		 6428 }
6429
7c3df132
SK		 6430 ql_dbg(ql_dbg_dpc, base_vha, 0x4010,
6431 "Loop resync end.\n");
1da177e4
LT		 6432 }
6433
8ae6d9c7
GM		 6434 if (IS_QLAFX00(ha))
6435 goto intr_on_check;
6436
e315cd28
AC		 6437 if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) &&
6438 atomic_read(&base_vha->loop_state) == LOOP_READY) {
6439 clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags);
6440 qla2xxx_flash_npiv_conf(base_vha);
272976ca
AV		 6441 }
6442
8ae6d9c7 6443intr_on_check:
1da177e4 6444 if (!ha->interrupts_on)
fd34f556 6445 ha->isp_ops->enable_intrs(ha);
1da177e4 6446
e315cd28 6447 if (test_and_clear_bit(BEACON_BLINK_NEEDED,
90b604f2
HM		 6448 &base_vha->dpc_flags)) {
6449 if (ha->beacon_blink_led == 1)
6450 ha->isp_ops->beacon_blink(base_vha);
6451 }
f6df144c 6452
d7459527
MH		 6453 /* qpair online check */
6454 if (test_and_clear_bit(QPAIR_ONLINE_CHECK_NEEDED,
6455 &base_vha->dpc_flags)) {
6456 if (ha->flags.eeh_busy ||
6457 ha->flags.pci_channel_io_perm_failure)
6458 online = 0;
6459 else
6460 online = 1;
6461
6462 mutex_lock(&ha->mq_lock);
6463 list_for_each_entry(qpair, &base_vha->qp_list,
6464 qp_list_elem)
6465 qpair->online = online;
6466 mutex_unlock(&ha->mq_lock);
6467 }
6468
8b4673ba
QT		 6469 if (test_and_clear_bit(SET_NVME_ZIO_THRESHOLD_NEEDED,
6470 &base_vha->dpc_flags)) {
deeae7a6
DG		 6471 ql_log(ql_log_info, base_vha, 0xffffff,
6472 "nvme: SET ZIO Activity exchange threshold to %d.\n",
6473 ha->nvme_last_rptd_aen);
8b4673ba
QT		 6474 if (qla27xx_set_zio_threshold(base_vha,
6475 ha->nvme_last_rptd_aen)) {
deeae7a6 6476 ql_log(ql_log_info, base_vha, 0xffffff,
8b4673ba
QT		 6477 "nvme: Unable to SET ZIO Activity exchange threshold to %d.\n",
6478 ha->nvme_last_rptd_aen);
deeae7a6
DG		 6479 }
6480 }
6481
8b4673ba
QT		 6482 if (test_and_clear_bit(SET_ZIO_THRESHOLD_NEEDED,
6483 &base_vha->dpc_flags)) {
6484 ql_log(ql_log_info, base_vha, 0xffffff,
6485 "SET ZIO Activity exchange threshold to %d.\n",
6486 ha->last_zio_threshold);
6487 qla27xx_set_zio_threshold(base_vha,
6488 ha->last_zio_threshold);
6489 }
6490
8ae6d9c7
GM		 6491 if (!IS_QLAFX00(ha))
6492 qla2x00_do_dpc_all_vps(base_vha);
2c3dfe3f 6493
48acad09
QT		 6494 if (test_and_clear_bit(N2N_LINK_RESET,
6495 &base_vha->dpc_flags)) {
6496 qla2x00_lip_reset(base_vha);
6497 }
6498
1da177e4 6499 ha->dpc_active = 0;
c142caf0 6500end_loop:
563585ec 6501 set_current_state(TASK_INTERRUPTIBLE);
1da177e4 6502 } /* End of while(1) */
563585ec 6503 __set_current_state(TASK_RUNNING);
1da177e4 6504
7c3df132
SK		 6505 ql_dbg(ql_dbg_dpc, base_vha, 0x4011,
6506 "DPC handler exiting.\n");
1da177e4
LT		 6507
6508 /*
6509 * Make sure that nobody tries to wake us up again.
6510 */
1da177e4
LT		 6511 ha->dpc_active = 0;
6512
ac280b67
AV		 6513 /* Cleanup any residual CTX SRBs. */
6514 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
6515
39a11240
CH		 6516 return 0;
6517}
6518
6519void
e315cd28 6520qla2xxx_wake_dpc(struct scsi_qla_host *vha)
39a11240 6521{
e315cd28 6522 struct qla_hw_data *ha = vha->hw;
c795c1e4
AV		 6523 struct task_struct *t = ha->dpc_thread;
6524
e315cd28 6525 if (!test_bit(UNLOADING, &vha->dpc_flags) && t)
c795c1e4 6526 wake_up_process(t);
1da177e4
LT		 6527}
6528
1da177e4
LT		 6529/*
6530* qla2x00_rst_aen
6531* Processes asynchronous reset.
6532*
6533* Input:
6534* ha = adapter block pointer.
6535*/
6536static void
e315cd28 6537qla2x00_rst_aen(scsi_qla_host_t *vha)
1da177e4 6538{
e315cd28
AC		 6539 if (vha->flags.online && !vha->flags.reset_active &&
6540 !atomic_read(&vha->loop_down_timer) &&
6541 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) {
1da177e4 6542 do {
e315cd28 6543 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
1da177e4
LT		 6544
6545 /*
6546 * Issue marker command only when we are going to start
6547 * the I/O.
6548 */
e315cd28
AC		 6549 vha->marker_needed = 1;
6550 } while (!atomic_read(&vha->loop_down_timer) &&
6551 (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)));
1da177e4
LT		 6552 }
6553}
6554
1da177e4
LT		 6555/**************************************************************************
6556* qla2x00_timer
6557*
6558* Description:
6559* One second timer
6560*
6561* Context: Interrupt
6562***************************************************************************/
2c3dfe3f 6563void
8e5f4ba0 6564qla2x00_timer(struct timer_list *t)
1da177e4 6565{
8e5f4ba0 6566 scsi_qla_host_t *vha = from_timer(vha, t, timer);
1da177e4 6567 unsigned long cpu_flags = 0;
1da177e4
LT		 6568 int start_dpc = 0;
6569 int index;
6570 srb_t *sp;
85880801 6571 uint16_t w;
e315cd28 6572 struct qla_hw_data *ha = vha->hw;
73208dfd 6573 struct req_que *req;
85880801 6574
a5b36321 6575 if (ha->flags.eeh_busy) {
7c3df132
SK		 6576 ql_dbg(ql_dbg_timer, vha, 0x6000,
6577 "EEH = %d, restarting timer.\n",
6578 ha->flags.eeh_busy);
a5b36321
LC		 6579 qla2x00_restart_timer(vha, WATCH_INTERVAL);
6580 return;
6581 }
6582
f3ddac19
CD		 6583 /*
6584 * Hardware read to raise pending EEH errors during mailbox waits. If
6585 * the read returns -1 then disable the board.
6586 */
6587 if (!pci_channel_offline(ha->pdev)) {
85880801 6588 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w);
c821e0d5 6589 qla2x00_check_reg16_for_disconnect(vha, w);
f3ddac19 6590 }
1da177e4 6591
cefcaba6 6592 /* Make sure qla82xx_watchdog is run only for physical port */
7ec0effd 6593 if (!vha->vp_idx && IS_P3P_TYPE(ha)) {
579d12b5
SK		 6594 if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags))
6595 start_dpc++;
7ec0effd
AD		 6596 if (IS_QLA82XX(ha))
6597 qla82xx_watchdog(vha);
6598 else if (IS_QLA8044(ha))
6599 qla8044_watchdog(vha);
579d12b5
SK		 6600 }
6601
8ae6d9c7
GM		 6602 if (!vha->vp_idx && IS_QLAFX00(ha))
6603 qlafx00_timer_routine(vha);
6604
1da177e4 6605 /* Loop down handler. */
e315cd28 6606 if (atomic_read(&vha->loop_down_timer) > 0 &&
8f7daead
GM		 6607 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) &&
6608 !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags))
e315cd28 6609 && vha->flags.online) {
1da177e4 6610
e315cd28
AC		 6611 if (atomic_read(&vha->loop_down_timer) ==
6612 vha->loop_down_abort_time) {
1da177e4 6613
7c3df132
SK		 6614 ql_log(ql_log_info, vha, 0x6008,
6615 "Loop down - aborting the queues before time expires.\n");
1da177e4 6616
e315cd28
AC		 6617 if (!IS_QLA2100(ha) && vha->link_down_timeout)
6618 atomic_set(&vha->loop_state, LOOP_DEAD);
1da177e4 6619
f08b7251
AV		 6620 /*
6621 * Schedule an ISP abort to return any FCP2-device
6622 * commands.
6623 */
2c3dfe3f 6624 /* NPIV - scan physical port only */
e315cd28 6625 if (!vha->vp_idx) {
2c3dfe3f
SJ		 6626 spin_lock_irqsave(&ha->hardware_lock,
6627 cpu_flags);
73208dfd 6628 req = ha->req_q_map[0];
2c3dfe3f 6629 for (index = 1;
8d93f550 6630 index < req->num_outstanding_cmds;
2c3dfe3f
SJ		 6631 index++) {
6632 fc_port_t *sfcp;
6633
e315cd28 6634 sp = req->outstanding_cmds[index];
2c3dfe3f
SJ		 6635 if (!sp)
6636 continue;
c5419e26
QT		 6637 if (sp->cmd_type != TYPE_SRB)
6638 continue;
9ba56b95 6639 if (sp->type != SRB_SCSI_CMD)
cf53b069 6640 continue;
2c3dfe3f 6641 sfcp = sp->fcport;
f08b7251 6642 if (!(sfcp->flags & FCF_FCP2_DEVICE))
2c3dfe3f 6643 continue;
bdf79621 6644
8f7daead
GM		 6645 if (IS_QLA82XX(ha))
6646 set_bit(FCOE_CTX_RESET_NEEDED,
6647 &vha->dpc_flags);
6648 else
6649 set_bit(ISP_ABORT_NEEDED,
e315cd28 6650 &vha->dpc_flags);
2c3dfe3f
SJ		 6651 break;
6652 }
6653 spin_unlock_irqrestore(&ha->hardware_lock,
e315cd28 6654 cpu_flags);
1da177e4 6655 }
1da177e4
LT		 6656 start_dpc++;
6657 }
6658
6659 /* if the loop has been down for 4 minutes, reinit adapter */
e315cd28 6660 if (atomic_dec_and_test(&vha->loop_down_timer) != 0) {
0d6e61bc 6661 if (!(vha->device_flags & DFLG_NO_CABLE)) {
7c3df132 6662 ql_log(ql_log_warn, vha, 0x6009,
1da177e4
LT		 6663 "Loop down - aborting ISP.\n");
6664
8f7daead
GM		 6665 if (IS_QLA82XX(ha))
6666 set_bit(FCOE_CTX_RESET_NEEDED,
6667 &vha->dpc_flags);
6668 else
6669 set_bit(ISP_ABORT_NEEDED,
6670 &vha->dpc_flags);
1da177e4
LT		 6671 }
6672 }
7c3df132
SK		 6673 ql_dbg(ql_dbg_timer, vha, 0x600a,
6674 "Loop down - seconds remaining %d.\n",
6675 atomic_read(&vha->loop_down_timer));
1da177e4 6676 }
cefcaba6
SK		 6677 /* Check if beacon LED needs to be blinked for physical host only */
6678 if (!vha->vp_idx && (ha->beacon_blink_led == 1)) {
999916dc 6679 /* There is no beacon_blink function for ISP82xx */
7ec0effd 6680 if (!IS_P3P_TYPE(ha)) {
999916dc
SK		 6681 set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags);
6682 start_dpc++;
6683 }
f6df144c 6684 }
6685
550bf57d 6686 /* Process any deferred work. */
9b3e0f4d
QT		 6687 if (!list_empty(&vha->work_list)) {
6688 unsigned long flags;
6689 bool q = false;
6690
6691 spin_lock_irqsave(&vha->work_lock, flags);
6692 if (!test_and_set_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags))
6693 q = true;
6694 spin_unlock_irqrestore(&vha->work_lock, flags);
6695 if (q)
6696 queue_work(vha->hw->wq, &vha->iocb_work);
6697 }
550bf57d 6698
7401bc18
DG		 6699 /*
6700 * FC-NVME
6701 * see if the active AEN count has changed from what was last reported.
6702 */
b2d1453a
GM		 6703 if (!vha->vp_idx &&
6704 (atomic_read(&ha->nvme_active_aen_cnt) != ha->nvme_last_rptd_aen) &&
6705 ha->zio_mode == QLA_ZIO_MODE_6 &&
6706 !ha->flags.host_shutting_down) {
7401bc18 6707 ql_log(ql_log_info, vha, 0x3002,
8b4673ba
QT		 6708 "nvme: Sched: Set ZIO exchange threshold to %d.\n",
6709 ha->nvme_last_rptd_aen);
deeae7a6 6710 ha->nvme_last_rptd_aen = atomic_read(&ha->nvme_active_aen_cnt);
8b4673ba
QT		 6711 set_bit(SET_NVME_ZIO_THRESHOLD_NEEDED, &vha->dpc_flags);
6712 start_dpc++;
6713 }
6714
6715 if (!vha->vp_idx &&
6716 (atomic_read(&ha->zio_threshold) != ha->last_zio_threshold) &&
6717 (ha->zio_mode == QLA_ZIO_MODE_6) &&
ecc89f25 6718 (IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))) {
8b4673ba
QT		 6719 ql_log(ql_log_info, vha, 0x3002,
6720 "Sched: Set ZIO exchange threshold to %d.\n",
6721 ha->last_zio_threshold);
6722 ha->last_zio_threshold = atomic_read(&ha->zio_threshold);
deeae7a6
DG		 6723 set_bit(SET_ZIO_THRESHOLD_NEEDED, &vha->dpc_flags);
6724 start_dpc++;
7401bc18
DG		 6725 }
6726
1da177e4 6727 /* Schedule the DPC routine if needed */
e315cd28
AC		 6728 if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) ||
6729 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) ||
6730 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags) ||
1da177e4 6731 start_dpc ||
e315cd28
AC		 6732 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) ||
6733 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) ||
a9083016
GM		 6734 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) ||
6735 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) ||
e315cd28 6736 test_bit(VP_DPC_NEEDED, &vha->dpc_flags) ||
50280c01 6737 test_bit(RELOGIN_NEEDED, &vha->dpc_flags))) {
7c3df132
SK		 6738 ql_dbg(ql_dbg_timer, vha, 0x600b,
6739 "isp_abort_needed=%d loop_resync_needed=%d "
6740 "fcport_update_needed=%d start_dpc=%d "
6741 "reset_marker_needed=%d",
6742 test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags),
6743 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags),
6744 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags),
6745 start_dpc,
6746 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags));
6747 ql_dbg(ql_dbg_timer, vha, 0x600c,
6748 "beacon_blink_needed=%d isp_unrecoverable=%d "
6749 "fcoe_ctx_reset_needed=%d vp_dpc_needed=%d "
50280c01 6750 "relogin_needed=%d.\n",
7c3df132
SK		 6751 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags),
6752 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags),
6753 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags),
6754 test_bit(VP_DPC_NEEDED, &vha->dpc_flags),
50280c01 6755 test_bit(RELOGIN_NEEDED, &vha->dpc_flags));
e315cd28 6756 qla2xxx_wake_dpc(vha);
7c3df132 6757 }
1da177e4 6758
e315cd28 6759 qla2x00_restart_timer(vha, WATCH_INTERVAL);
1da177e4
LT		 6760}
6761
5433383e
AV		 6762/* Firmware interface routines. */
6763
5433383e
AV		 6764#define FW_ISP21XX 0
6765#define FW_ISP22XX 1
6766#define FW_ISP2300 2
6767#define FW_ISP2322 3
48c02fde 6768#define FW_ISP24XX 4
c3a2f0df 6769#define FW_ISP25XX 5
3a03eb79 6770#define FW_ISP81XX 6
a9083016 6771#define FW_ISP82XX 7
6246b8a1
GM		 6772#define FW_ISP2031 8
6773#define FW_ISP8031 9
2c5bbbb2 6774#define FW_ISP27XX 10
ecc89f25 6775#define FW_ISP28XX 11
5433383e 6776
bb8ee499
AV		 6777#define FW_FILE_ISP21XX "ql2100_fw.bin"
6778#define FW_FILE_ISP22XX "ql2200_fw.bin"
6779#define FW_FILE_ISP2300 "ql2300_fw.bin"
6780#define FW_FILE_ISP2322 "ql2322_fw.bin"
6781#define FW_FILE_ISP24XX "ql2400_fw.bin"
c3a2f0df 6782#define FW_FILE_ISP25XX "ql2500_fw.bin"
3a03eb79 6783#define FW_FILE_ISP81XX "ql8100_fw.bin"
a9083016 6784#define FW_FILE_ISP82XX "ql8200_fw.bin"
6246b8a1
GM		 6785#define FW_FILE_ISP2031 "ql2600_fw.bin"
6786#define FW_FILE_ISP8031 "ql8300_fw.bin"
2c5bbbb2 6787#define FW_FILE_ISP27XX "ql2700_fw.bin"
ecc89f25 6788#define FW_FILE_ISP28XX "ql2800_fw.bin"
f73cb695 6789
bb8ee499 6790
e1e82b6f 6791static DEFINE_MUTEX(qla_fw_lock);
5433383e 6792
ecc89f25 6793static struct fw_blob qla_fw_blobs[] = {
bb8ee499
AV		 6794 { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, },
6795 { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, },
6796 { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, },
6797 { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, },
6798 { .name = FW_FILE_ISP24XX, },
c3a2f0df 6799 { .name = FW_FILE_ISP25XX, },
3a03eb79 6800 { .name = FW_FILE_ISP81XX, },
a9083016 6801 { .name = FW_FILE_ISP82XX, },
6246b8a1
GM		 6802 { .name = FW_FILE_ISP2031, },
6803 { .name = FW_FILE_ISP8031, },
2c5bbbb2 6804 { .name = FW_FILE_ISP27XX, },
ecc89f25
JC		 6805 { .name = FW_FILE_ISP28XX, },
6806 { .name = NULL, },
5433383e
AV		 6807};
6808
6809struct fw_blob *
e315cd28 6810qla2x00_request_firmware(scsi_qla_host_t *vha)
5433383e 6811{
e315cd28 6812 struct qla_hw_data *ha = vha->hw;
5433383e
AV		 6813 struct fw_blob *blob;
6814
5433383e
AV		 6815 if (IS_QLA2100(ha)) {
6816 blob = &qla_fw_blobs[FW_ISP21XX];
6817 } else if (IS_QLA2200(ha)) {
6818 blob = &qla_fw_blobs[FW_ISP22XX];
48c02fde 6819 } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
5433383e 6820 blob = &qla_fw_blobs[FW_ISP2300];
48c02fde 6821 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
5433383e 6822 blob = &qla_fw_blobs[FW_ISP2322];
4d4df193 6823 } else if (IS_QLA24XX_TYPE(ha)) {
5433383e 6824 blob = &qla_fw_blobs[FW_ISP24XX];
c3a2f0df
AV		 6825 } else if (IS_QLA25XX(ha)) {
6826 blob = &qla_fw_blobs[FW_ISP25XX];
3a03eb79
AV		 6827 } else if (IS_QLA81XX(ha)) {
6828 blob = &qla_fw_blobs[FW_ISP81XX];
a9083016
GM		 6829 } else if (IS_QLA82XX(ha)) {
6830 blob = &qla_fw_blobs[FW_ISP82XX];
6246b8a1
GM		 6831 } else if (IS_QLA2031(ha)) {
6832 blob = &qla_fw_blobs[FW_ISP2031];
6833 } else if (IS_QLA8031(ha)) {
6834 blob = &qla_fw_blobs[FW_ISP8031];
2c5bbbb2
JC		 6835 } else if (IS_QLA27XX(ha)) {
6836 blob = &qla_fw_blobs[FW_ISP27XX];
ecc89f25
JC		 6837 } else if (IS_QLA28XX(ha)) {
6838 blob = &qla_fw_blobs[FW_ISP28XX];
8a655229
DC		 6839 } else {
6840 return NULL;
5433383e
AV		 6841 }
6842
ecc89f25
JC		 6843 if (!blob->name)
6844 return NULL;
6845
e1e82b6f 6846 mutex_lock(&qla_fw_lock);
5433383e
AV		 6847 if (blob->fw)
6848 goto out;
6849
6850 if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) {
7c3df132
SK		 6851 ql_log(ql_log_warn, vha, 0x0063,
6852 "Failed to load firmware image (%s).\n", blob->name);
5433383e
AV		 6853 blob->fw = NULL;
6854 blob = NULL;
5433383e
AV		 6855 }
6856
6857out:
e1e82b6f 6858 mutex_unlock(&qla_fw_lock);
5433383e
AV		 6859 return blob;
6860}
6861
6862static void
6863qla2x00_release_firmware(void)
6864{
ecc89f25 6865 struct fw_blob *blob;
5433383e 6866
e1e82b6f 6867 mutex_lock(&qla_fw_lock);
ecc89f25
JC		 6868 for (blob = qla_fw_blobs; blob->name; blob++)
6869 release_firmware(blob->fw);
e1e82b6f 6870 mutex_unlock(&qla_fw_lock);
5433383e
AV		 6871}
6872
14e660e6
SJ		 6873static pci_ers_result_t
6874qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
6875{
85880801
AV		 6876 scsi_qla_host_t *vha = pci_get_drvdata(pdev);
6877 struct qla_hw_data *ha = vha->hw;
6878
7c3df132
SK		 6879 ql_dbg(ql_dbg_aer, vha, 0x9000,
6880 "PCI error detected, state %x.\n", state);
b9b12f73 6881
efdb5760
SC		 6882 if (!atomic_read(&pdev->enable_cnt)) {
6883 ql_log(ql_log_info, vha, 0xffff,
6884 "PCI device is disabled,state %x\n", state);
6885 return PCI_ERS_RESULT_NEED_RESET;
6886 }
6887
14e660e6
SJ		 6888 switch (state) {
6889 case pci_channel_io_normal:
85880801 6890 ha->flags.eeh_busy = 0;
c38d1baf 6891 if (ql2xmqsupport || ql2xnvmeenable) {
d7459527
MH		 6892 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags);
6893 qla2xxx_wake_dpc(vha);
6894 }
14e660e6
SJ		 6895 return PCI_ERS_RESULT_CAN_RECOVER;
6896 case pci_channel_io_frozen:
85880801 6897 ha->flags.eeh_busy = 1;
a5b36321
LC		 6898 /* For ISP82XX complete any pending mailbox cmd */
6899 if (IS_QLA82XX(ha)) {
7190575f 6900 ha->flags.isp82xx_fw_hung = 1;
c8f6544e
CD		 6901 ql_dbg(ql_dbg_aer, vha, 0x9001, "Pci channel io frozen\n");
6902 qla82xx_clear_pending_mbx(vha);
a5b36321 6903 }
90a86fc0 6904 qla2x00_free_irqs(vha);
14e660e6 6905 pci_disable_device(pdev);
bddd2d65
LC		 6906 /* Return back all IOs */
6907 qla2x00_abort_all_cmds(vha, DID_RESET << 16);
c38d1baf 6908 if (ql2xmqsupport || ql2xnvmeenable) {
d7459527
MH		 6909 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags);
6910 qla2xxx_wake_dpc(vha);
6911 }
14e660e6
SJ		 6912 return PCI_ERS_RESULT_NEED_RESET;
6913 case pci_channel_io_perm_failure:
85880801
AV		 6914 ha->flags.pci_channel_io_perm_failure = 1;
6915 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
c38d1baf 6916 if (ql2xmqsupport || ql2xnvmeenable) {
d7459527
MH		 6917 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags);
6918 qla2xxx_wake_dpc(vha);
6919 }
14e660e6
SJ		 6920 return PCI_ERS_RESULT_DISCONNECT;
6921 }
6922 return PCI_ERS_RESULT_NEED_RESET;
6923}
6924
6925static pci_ers_result_t
6926qla2xxx_pci_mmio_enabled(struct pci_dev *pdev)
6927{
6928 int risc_paused = 0;
6929 uint32_t stat;
6930 unsigned long flags;
e315cd28
AC		 6931 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
6932 struct qla_hw_data *ha = base_vha->hw;
14e660e6
SJ		 6933 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
6934 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
6935
bcc5b6d3
SK		 6936 if (IS_QLA82XX(ha))
6937 return PCI_ERS_RESULT_RECOVERED;
6938
14e660e6
SJ		 6939 spin_lock_irqsave(&ha->hardware_lock, flags);
6940 if (IS_QLA2100(ha) || IS_QLA2200(ha)){
6941 stat = RD_REG_DWORD(&reg->hccr);
6942 if (stat & HCCR_RISC_PAUSE)
6943 risc_paused = 1;
6944 } else if (IS_QLA23XX(ha)) {
6945 stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
6946 if (stat & HSR_RISC_PAUSED)
6947 risc_paused = 1;
6948 } else if (IS_FWI2_CAPABLE(ha)) {
6949 stat = RD_REG_DWORD(&reg24->host_status);
6950 if (stat & HSRX_RISC_PAUSED)
6951 risc_paused = 1;
6952 }
6953 spin_unlock_irqrestore(&ha->hardware_lock, flags);
6954
6955 if (risc_paused) {
7c3df132
SK		 6956 ql_log(ql_log_info, base_vha, 0x9003,
6957 "RISC paused -- mmio_enabled, Dumping firmware.\n");
e315cd28 6958 ha->isp_ops->fw_dump(base_vha, 0);
14e660e6
SJ		 6959
6960 return PCI_ERS_RESULT_NEED_RESET;
6961 } else
6962 return PCI_ERS_RESULT_RECOVERED;
6963}
6964
fa492630
SK		 6965static uint32_t
6966qla82xx_error_recovery(scsi_qla_host_t *base_vha)
a5b36321
LC		 6967{
6968 uint32_t rval = QLA_FUNCTION_FAILED;
6969 uint32_t drv_active = 0;
6970 struct qla_hw_data *ha = base_vha->hw;
6971 int fn;
6972 struct pci_dev *other_pdev = NULL;
6973
7c3df132
SK		 6974 ql_dbg(ql_dbg_aer, base_vha, 0x9006,
6975 "Entered %s.\n", __func__);
a5b36321
LC		 6976
6977 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
6978
6979 if (base_vha->flags.online) {
6980 /* Abort all outstanding commands,
6981 * so as to be requeued later */
6982 qla2x00_abort_isp_cleanup(base_vha);
6983 }
6984
6985
6986 fn = PCI_FUNC(ha->pdev->devfn);
6987 while (fn > 0) {
6988 fn--;
7c3df132
SK		 6989 ql_dbg(ql_dbg_aer, base_vha, 0x9007,
6990 "Finding pci device at function = 0x%x.\n", fn);
a5b36321
LC		 6991 other_pdev =
6992 pci_get_domain_bus_and_slot(pci_domain_nr(ha->pdev->bus),
6993 ha->pdev->bus->number, PCI_DEVFN(PCI_SLOT(ha->pdev->devfn),
6994 fn));
6995
6996 if (!other_pdev)
6997 continue;
6998 if (atomic_read(&other_pdev->enable_cnt)) {
7c3df132
SK		 6999 ql_dbg(ql_dbg_aer, base_vha, 0x9008,
7000 "Found PCI func available and enable at 0x%x.\n",
7001 fn);
a5b36321
LC		 7002 pci_dev_put(other_pdev);
7003 break;
7004 }
7005 pci_dev_put(other_pdev);
7006 }
7007
7008 if (!fn) {
7009 /* Reset owner */
7c3df132
SK		 7010 ql_dbg(ql_dbg_aer, base_vha, 0x9009,
7011 "This devfn is reset owner = 0x%x.\n",
7012 ha->pdev->devfn);
a5b36321
LC		 7013 qla82xx_idc_lock(ha);
7014
7015 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 7016 QLA8XXX_DEV_INITIALIZING);
a5b36321
LC		 7017
7018 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION,
7019 QLA82XX_IDC_VERSION);
7020
7021 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
7c3df132
SK		 7022 ql_dbg(ql_dbg_aer, base_vha, 0x900a,
7023 "drv_active = 0x%x.\n", drv_active);
a5b36321
LC		 7024
7025 qla82xx_idc_unlock(ha);
7026 /* Reset if device is not already reset
7027 * drv_active would be 0 if a reset has already been done
7028 */
7029 if (drv_active)
7030 rval = qla82xx_start_firmware(base_vha);
7031 else
7032 rval = QLA_SUCCESS;
7033 qla82xx_idc_lock(ha);
7034
7035 if (rval != QLA_SUCCESS) {
7c3df132
SK		 7036 ql_log(ql_log_info, base_vha, 0x900b,
7037 "HW State: FAILED.\n");
a5b36321
LC		 7038 qla82xx_clear_drv_active(ha);
7039 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 7040 QLA8XXX_DEV_FAILED);
a5b36321 7041 } else {
7c3df132
SK		 7042 ql_log(ql_log_info, base_vha, 0x900c,
7043 "HW State: READY.\n");
a5b36321 7044 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 7045 QLA8XXX_DEV_READY);
a5b36321 7046 qla82xx_idc_unlock(ha);
7190575f 7047 ha->flags.isp82xx_fw_hung = 0;
a5b36321
LC		 7048 rval = qla82xx_restart_isp(base_vha);
7049 qla82xx_idc_lock(ha);
7050 /* Clear driver state register */
7051 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, 0);
7052 qla82xx_set_drv_active(base_vha);
7053 }
7054 qla82xx_idc_unlock(ha);
7055 } else {
7c3df132
SK		 7056 ql_dbg(ql_dbg_aer, base_vha, 0x900d,
7057 "This devfn is not reset owner = 0x%x.\n",
7058 ha->pdev->devfn);
a5b36321 7059 if ((qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE) ==
7d613ac6 7060 QLA8XXX_DEV_READY)) {
7190575f 7061 ha->flags.isp82xx_fw_hung = 0;
a5b36321
LC		 7062 rval = qla82xx_restart_isp(base_vha);
7063 qla82xx_idc_lock(ha);
7064 qla82xx_set_drv_active(base_vha);
7065 qla82xx_idc_unlock(ha);
7066 }
7067 }
7068 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
7069
7070 return rval;
7071}
7072
14e660e6
SJ		 7073static pci_ers_result_t
7074qla2xxx_pci_slot_reset(struct pci_dev *pdev)
7075{
7076 pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT;
e315cd28
AC		 7077 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
7078 struct qla_hw_data *ha = base_vha->hw;
90a86fc0
JC		 7079 struct rsp_que *rsp;
7080 int rc, retries = 10;
09483916 7081
7c3df132
SK		 7082 ql_dbg(ql_dbg_aer, base_vha, 0x9004,
7083 "Slot Reset.\n");
85880801 7084
90a86fc0
JC		 7085 /* Workaround: qla2xxx driver which access hardware earlier
7086 * needs error state to be pci_channel_io_online.
7087 * Otherwise mailbox command timesout.
7088 */
7089 pdev->error_state = pci_channel_io_normal;
7090
7091 pci_restore_state(pdev);
7092
8c1496bd
RL		 7093 /* pci_restore_state() clears the saved_state flag of the device
7094 * save restored state which resets saved_state flag
7095 */
7096 pci_save_state(pdev);
7097
09483916
BH		 7098 if (ha->mem_only)
7099 rc = pci_enable_device_mem(pdev);
7100 else
7101 rc = pci_enable_device(pdev);
14e660e6 7102
09483916 7103 if (rc) {
7c3df132 7104 ql_log(ql_log_warn, base_vha, 0x9005,
14e660e6 7105 "Can't re-enable PCI device after reset.\n");
a5b36321 7106 goto exit_slot_reset;
14e660e6 7107 }
14e660e6 7108
90a86fc0
JC		 7109 rsp = ha->rsp_q_map[0];
7110 if (qla2x00_request_irqs(ha, rsp))
a5b36321 7111 goto exit_slot_reset;
90a86fc0 7112
e315cd28 7113 if (ha->isp_ops->pci_config(base_vha))
a5b36321
LC		 7114 goto exit_slot_reset;
7115
7116 if (IS_QLA82XX(ha)) {
7117 if (qla82xx_error_recovery(base_vha) == QLA_SUCCESS) {
7118 ret = PCI_ERS_RESULT_RECOVERED;
7119 goto exit_slot_reset;
7120 } else
7121 goto exit_slot_reset;
7122 }
14e660e6 7123
90a86fc0
JC		 7124 while (ha->flags.mbox_busy && retries--)
7125 msleep(1000);
85880801 7126
e315cd28 7127 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
a9083016 7128 if (ha->isp_ops->abort_isp(base_vha) == QLA_SUCCESS)
14e660e6 7129 ret = PCI_ERS_RESULT_RECOVERED;
e315cd28 7130 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
14e660e6 7131
90a86fc0 7132
a5b36321 7133exit_slot_reset:
7c3df132
SK		 7134 ql_dbg(ql_dbg_aer, base_vha, 0x900e,
7135 "slot_reset return %x.\n", ret);
85880801 7136
14e660e6
SJ		 7137 return ret;
7138}
7139
7140static void
7141qla2xxx_pci_resume(struct pci_dev *pdev)
7142{
e315cd28
AC		 7143 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
7144 struct qla_hw_data *ha = base_vha->hw;
14e660e6
SJ		 7145 int ret;
7146
7c3df132
SK		 7147 ql_dbg(ql_dbg_aer, base_vha, 0x900f,
7148 "pci_resume.\n");
85880801 7149
e315cd28 7150 ret = qla2x00_wait_for_hba_online(base_vha);
14e660e6 7151 if (ret != QLA_SUCCESS) {
7c3df132
SK		 7152 ql_log(ql_log_fatal, base_vha, 0x9002,
7153 "The device failed to resume I/O from slot/link_reset.\n");
14e660e6 7154 }
85880801
AV		 7155
7156 ha->flags.eeh_busy = 0;
14e660e6
SJ		 7157}
7158
590f806d
QT		 7159static void
7160qla_pci_reset_prepare(struct pci_dev *pdev)
7161{
7162 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
7163 struct qla_hw_data *ha = base_vha->hw;
7164 struct qla_qpair *qpair;
7165
7166 ql_log(ql_log_warn, base_vha, 0xffff,
7167 "%s.\n", __func__);
7168
7169 /*
7170 * PCI FLR/function reset is about to reset the
7171 * slot. Stop the chip to stop all DMA access.
7172 * It is assumed that pci_reset_done will be called
7173 * after FLR to resume Chip operation.
7174 */
7175 ha->flags.eeh_busy = 1;
7176 mutex_lock(&ha->mq_lock);
7177 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem)
7178 qpair->online = 0;
7179 mutex_unlock(&ha->mq_lock);
7180
7181 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
7182 qla2x00_abort_isp_cleanup(base_vha);
7183 qla2x00_abort_all_cmds(base_vha, DID_RESET << 16);
7184}
7185
7186static void
7187qla_pci_reset_done(struct pci_dev *pdev)
7188{
7189 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
7190 struct qla_hw_data *ha = base_vha->hw;
7191 struct qla_qpair *qpair;
7192
7193 ql_log(ql_log_warn, base_vha, 0xffff,
7194 "%s.\n", __func__);
7195
7196 /*
7197 * FLR just completed by PCI layer. Resume adapter
7198 */
7199 ha->flags.eeh_busy = 0;
7200 mutex_lock(&ha->mq_lock);
7201 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem)
7202 qpair->online = 1;
7203 mutex_unlock(&ha->mq_lock);
7204
7205 base_vha->flags.online = 1;
7206 ha->isp_ops->abort_isp(base_vha);
7207 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
7208}
7209
5601236b
MH		 7210static int qla2xxx_map_queues(struct Scsi_Host *shost)
7211{
d68b850e 7212 int rc;
5601236b 7213 scsi_qla_host_t *vha = (scsi_qla_host_t *)shost->hostdata;
485b0eca 7214 struct blk_mq_queue_map *qmap = &shost->tag_set.map[HCTX_TYPE_DEFAULT];
5601236b 7215
f3e02695 7216 if (USER_CTRL_IRQ(vha->hw) || !vha->hw->mqiobase)
ed76e329 7217 rc = blk_mq_map_queues(qmap);
d68b850e 7218 else
f0783d43 7219 rc = blk_mq_pci_map_queues(qmap, vha->hw->pdev, vha->irq_offset);
d68b850e 7220 return rc;
5601236b
MH		 7221}
7222
6515ad71
BVA		 7223struct scsi_host_template qla2xxx_driver_template = {
7224 .module = THIS_MODULE,
7225 .name = QLA2XXX_DRIVER_NAME,
7226 .queuecommand = qla2xxx_queuecommand,
7227
7228 .eh_timed_out = fc_eh_timed_out,
7229 .eh_abort_handler = qla2xxx_eh_abort,
7230 .eh_device_reset_handler = qla2xxx_eh_device_reset,
7231 .eh_target_reset_handler = qla2xxx_eh_target_reset,
7232 .eh_bus_reset_handler = qla2xxx_eh_bus_reset,
7233 .eh_host_reset_handler = qla2xxx_eh_host_reset,
7234
7235 .slave_configure = qla2xxx_slave_configure,
7236
7237 .slave_alloc = qla2xxx_slave_alloc,
7238 .slave_destroy = qla2xxx_slave_destroy,
7239 .scan_finished = qla2xxx_scan_finished,
7240 .scan_start = qla2xxx_scan_start,
7241 .change_queue_depth = scsi_change_queue_depth,
7242 .map_queues = qla2xxx_map_queues,
7243 .this_id = -1,
7244 .cmd_per_lun = 3,
7245 .sg_tablesize = SG_ALL,
7246
7247 .max_sectors = 0xFFFF,
7248 .shost_attrs = qla2x00_host_attrs,
7249
7250 .supported_mode = MODE_INITIATOR,
7251 .track_queue_depth = 1,
7252};
7253
a55b2d21 7254static const struct pci_error_handlers qla2xxx_err_handler = {
14e660e6
SJ		 7255 .error_detected = qla2xxx_pci_error_detected,
7256 .mmio_enabled = qla2xxx_pci_mmio_enabled,
7257 .slot_reset = qla2xxx_pci_slot_reset,
7258 .resume = qla2xxx_pci_resume,
590f806d
QT		 7259 .reset_prepare = qla_pci_reset_prepare,
7260 .reset_done = qla_pci_reset_done,
14e660e6
SJ		 7261};
7262
5433383e 7263static struct pci_device_id qla2xxx_pci_tbl[] = {
47f5e069
AV		 7264 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) },
7265 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) },
7266 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) },
7267 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) },
7268 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) },
7269 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) },
7270 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) },
7271 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) },
7272 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) },
4d4df193 7273 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) },
47f5e069
AV		 7274 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) },
7275 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) },
c3a2f0df 7276 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) },
6246b8a1 7277 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2031) },
3a03eb79 7278 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) },
a9083016 7279 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) },
650f528f 7280 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8031) },
8ae6d9c7 7281 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISPF001) },
7ec0effd 7282 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8044) },
f73cb695 7283 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2071) },
2c5bbbb2 7284 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2271) },
2b48992f 7285 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2261) },
ecc89f25
JC		 7286 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2061) },
7287 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2081) },
7288 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2281) },
7289 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2089) },
7290 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2289) },
5433383e
AV		 7291 { 0 },
7292};
7293MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl);
7294
fca29703 7295static struct pci_driver qla2xxx_pci_driver = {
cb63067a 7296 .name = QLA2XXX_DRIVER_NAME,
0a21ef1e
JB		 7297 .driver = {
7298 .owner = THIS_MODULE,
7299 },
fca29703 7300 .id_table = qla2xxx_pci_tbl,
7ee61397 7301 .probe = qla2x00_probe_one,
4c993f76 7302 .remove = qla2x00_remove_one,
e30d1756 7303 .shutdown = qla2x00_shutdown,
14e660e6 7304 .err_handler = &qla2xxx_err_handler,
fca29703
AV		 7305};
7306
75ef9de1 7307static const struct file_operations apidev_fops = {
6a03b4cd 7308 .owner = THIS_MODULE,
6038f373 7309 .llseek = noop_llseek,
6a03b4cd
HZ		 7310};
7311
1da177e4
LT		 7312/**
7313 * qla2x00_module_init - Module initialization.
7314 **/
7315static int __init
7316qla2x00_module_init(void)
7317{
fca29703
AV		 7318 int ret = 0;
7319
1da177e4 7320 /* Allocate cache for SRBs. */
354d6b21 7321 srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0,
20c2df83 7322 SLAB_HWCACHE_ALIGN, NULL);
1da177e4 7323 if (srb_cachep == NULL) {
7c3df132
SK		 7324 ql_log(ql_log_fatal, NULL, 0x0001,
7325 "Unable to allocate SRB cache...Failing load!.\n");
1da177e4
LT		 7326 return -ENOMEM;
7327 }
7328
2d70c103
NB		 7329 /* Initialize target kmem_cache and mem_pools */
7330 ret = qlt_init();
7331 if (ret < 0) {
c794d24e 7332 goto destroy_cache;
2d70c103
NB		 7333 } else if (ret > 0) {
7334 /*
7335 * If initiator mode is explictly disabled by qlt_init(),
7336 * prevent scsi_transport_fc.c:fc_scsi_scan_rport() from
7337 * performing scsi_scan_target() during LOOP UP event.
7338 */
7339 qla2xxx_transport_functions.disable_target_scan = 1;
7340 qla2xxx_transport_vport_functions.disable_target_scan = 1;
7341 }
7342
1da177e4
LT		 7343 /* Derive version string. */
7344 strcpy(qla2x00_version_str, QLA2XXX_VERSION);
11010fec 7345 if (ql2xextended_error_logging)
0181944f 7346 strcat(qla2x00_version_str, "-debug");
fed0f68a
JC		 7347 if (ql2xextended_error_logging == 1)
7348 ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK;
0181944f 7349
0645cb83
QT		 7350 if (ql2x_ini_mode == QLA2XXX_INI_MODE_DUAL)
7351 qla_insert_tgt_attrs();
7352
1c97a12a
AV		 7353 qla2xxx_transport_template =
7354 fc_attach_transport(&qla2xxx_transport_functions);
2c3dfe3f 7355 if (!qla2xxx_transport_template) {
7c3df132
SK		 7356 ql_log(ql_log_fatal, NULL, 0x0002,
7357 "fc_attach_transport failed...Failing load!.\n");
c794d24e
BVA		 7358 ret = -ENODEV;
7359 goto qlt_exit;
2c3dfe3f 7360 }
6a03b4cd
HZ		 7361
7362 apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops);
7363 if (apidev_major < 0) {
7c3df132
SK		 7364 ql_log(ql_log_fatal, NULL, 0x0003,
7365 "Unable to register char device %s.\n", QLA2XXX_APIDEV);
6a03b4cd
HZ		 7366 }
7367
2c3dfe3f
SJ		 7368 qla2xxx_transport_vport_template =
7369 fc_attach_transport(&qla2xxx_transport_vport_functions);
7370 if (!qla2xxx_transport_vport_template) {
7c3df132
SK		 7371 ql_log(ql_log_fatal, NULL, 0x0004,
7372 "fc_attach_transport vport failed...Failing load!.\n");
c794d24e
BVA		 7373 ret = -ENODEV;
7374 goto unreg_chrdev;
2c3dfe3f 7375 }
7c3df132
SK		 7376 ql_log(ql_log_info, NULL, 0x0005,
7377 "QLogic Fibre Channel HBA Driver: %s.\n",
fd9a29f0 7378 qla2x00_version_str);
7ee61397 7379 ret = pci_register_driver(&qla2xxx_pci_driver);
fca29703 7380 if (ret) {
7c3df132
SK		 7381 ql_log(ql_log_fatal, NULL, 0x0006,
7382 "pci_register_driver failed...ret=%d Failing load!.\n",
7383 ret);
c794d24e 7384 goto release_vport_transport;
fca29703
AV		 7385 }
7386 return ret;
c794d24e
BVA		 7387
7388release_vport_transport:
7389 fc_release_transport(qla2xxx_transport_vport_template);
7390
7391unreg_chrdev:
7392 if (apidev_major >= 0)
7393 unregister_chrdev(apidev_major, QLA2XXX_APIDEV);
7394 fc_release_transport(qla2xxx_transport_template);
7395
7396qlt_exit:
7397 qlt_exit();
7398
7399destroy_cache:
7400 kmem_cache_destroy(srb_cachep);
7401 return ret;
1da177e4
LT		 7402}
7403
7404/**
7405 * qla2x00_module_exit - Module cleanup.
7406 **/
7407static void __exit
7408qla2x00_module_exit(void)
7409{
7ee61397 7410 pci_unregister_driver(&qla2xxx_pci_driver);
5433383e 7411 qla2x00_release_firmware();
75c1d48a 7412 kmem_cache_destroy(ctx_cachep);
2c3dfe3f 7413 fc_release_transport(qla2xxx_transport_vport_template);
59c209a6
BVA		 7414 if (apidev_major >= 0)
7415 unregister_chrdev(apidev_major, QLA2XXX_APIDEV);
7416 fc_release_transport(qla2xxx_transport_template);
7417 qlt_exit();
7418 kmem_cache_destroy(srb_cachep);
1da177e4
LT		 7419}
7420
7421module_init(qla2x00_module_init);
7422module_exit(qla2x00_module_exit);
7423
7424MODULE_AUTHOR("QLogic Corporation");
7425MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver");
7426MODULE_LICENSE("GPL");
7427MODULE_VERSION(QLA2XXX_VERSION);
bb8ee499
AV		 7428MODULE_FIRMWARE(FW_FILE_ISP21XX);
7429MODULE_FIRMWARE(FW_FILE_ISP22XX);
7430MODULE_FIRMWARE(FW_FILE_ISP2300);
7431MODULE_FIRMWARE(FW_FILE_ISP2322);
7432MODULE_FIRMWARE(FW_FILE_ISP24XX);
61623fc3 7433MODULE_FIRMWARE(FW_FILE_ISP25XX);
Linux 6.x block layer and io_uring tree(s)