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scsi: qla2xxx: Retry switch command on time out
[linux-2.6-block.git] / drivers / scsi / qla2xxx / qla_os.c
CommitLineData
1da177e4 1/*
fa90c54f 2 * QLogic Fibre Channel HBA Driver
bd21eaf9 3 * Copyright (c) 2003-2014 QLogic Corporation
1da177e4 4 *
fa90c54f 5 * See LICENSE.qla2xxx for copyright and licensing details.
1da177e4
LT		 6 */
7#include "qla_def.h"
8
9#include <linux/moduleparam.h>
10#include <linux/vmalloc.h>
1da177e4 11#include <linux/delay.h>
39a11240 12#include <linux/kthread.h>
e1e82b6f 13#include <linux/mutex.h>
3420d36c 14#include <linux/kobject.h>
5a0e3ad6 15#include <linux/slab.h>
5601236b 16#include <linux/blk-mq-pci.h>
1da177e4
LT		 17#include <scsi/scsi_tcq.h>
18#include <scsi/scsicam.h>
19#include <scsi/scsi_transport.h>
20#include <scsi/scsi_transport_fc.h>
21
2d70c103
NB		 22#include "qla_target.h"
23
1da177e4
LT		 24/*
25 * Driver version
26 */
27char qla2x00_version_str[40];
28
6a03b4cd
HZ		 29static int apidev_major;
30
1da177e4
LT		 31/*
32 * SRB allocation cache
33 */
d7459527 34struct kmem_cache *srb_cachep;
1da177e4 35
a9083016
GM		 36/*
37 * CT6 CTX allocation cache
38 */
39static struct kmem_cache *ctx_cachep;
3ce8866c
SK		 40/*
41 * error level for logging
42 */
43int ql_errlev = ql_log_all;
a9083016 44
fa492630 45static int ql2xenableclass2;
2d70c103
NB		 46module_param(ql2xenableclass2, int, S_IRUGO|S_IRUSR);
47MODULE_PARM_DESC(ql2xenableclass2,
48 "Specify if Class 2 operations are supported from the very "
49 "beginning. Default is 0 - class 2 not supported.");
50
8ae6d9c7 51
1da177e4 52int ql2xlogintimeout = 20;
f2019cb1 53module_param(ql2xlogintimeout, int, S_IRUGO);
1da177e4
LT		 54MODULE_PARM_DESC(ql2xlogintimeout,
55 "Login timeout value in seconds.");
56
a7b61842 57int qlport_down_retry;
f2019cb1 58module_param(qlport_down_retry, int, S_IRUGO);
1da177e4 59MODULE_PARM_DESC(qlport_down_retry,
900d9f98 60 "Maximum number of command retries to a port that returns "
1da177e4
LT		 61 "a PORT-DOWN status.");
62
1da177e4
LT		 63int ql2xplogiabsentdevice;
64module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR);
65MODULE_PARM_DESC(ql2xplogiabsentdevice,
66 "Option to enable PLOGI to devices that are not present after "
900d9f98 67 "a Fabric scan. This is needed for several broken switches. "
1da177e4
LT		 68 "Default is 0 - no PLOGI. 1 - perfom PLOGI.");
69
1da177e4 70int ql2xloginretrycount = 0;
f2019cb1 71module_param(ql2xloginretrycount, int, S_IRUGO);
1da177e4
LT		 72MODULE_PARM_DESC(ql2xloginretrycount,
73 "Specify an alternate value for the NVRAM login retry count.");
74
a7a167bf 75int ql2xallocfwdump = 1;
f2019cb1 76module_param(ql2xallocfwdump, int, S_IRUGO);
a7a167bf
AV		 77MODULE_PARM_DESC(ql2xallocfwdump,
78 "Option to enable allocation of memory for a firmware dump "
79 "during HBA initialization. Memory allocation requirements "
80 "vary by ISP type. Default is 1 - allocate memory.");
81
11010fec 82int ql2xextended_error_logging;
27d94035 83module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
a2b3e01d 84module_param_named(logging, ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
11010fec 85MODULE_PARM_DESC(ql2xextended_error_logging,
3ce8866c
SK		 86 "Option to enable extended error logging,\n"
87 "\t\tDefault is 0 - no logging. 0x40000000 - Module Init & Probe.\n"
88 "\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n"
89 "\t\t0x08000000 - IO tracing. 0x04000000 - DPC Thread.\n"
90 "\t\t0x02000000 - Async events. 0x01000000 - Timer routines.\n"
91 "\t\t0x00800000 - User space. 0x00400000 - Task Management.\n"
92 "\t\t0x00200000 - AER/EEH. 0x00100000 - Multi Q.\n"
93 "\t\t0x00080000 - P3P Specific. 0x00040000 - Virtual Port.\n"
94 "\t\t0x00020000 - Buffer Dump. 0x00010000 - Misc.\n"
29f9f90c
CD		 95 "\t\t0x00008000 - Verbose. 0x00004000 - Target.\n"
96 "\t\t0x00002000 - Target Mgmt. 0x00001000 - Target TMF.\n"
3ce8866c 97 "\t\t0x7fffffff - For enabling all logs, can be too many logs.\n"
cfb0919c
CD		 98 "\t\t0x1e400000 - Preferred value for capturing essential "
99 "debug information (equivalent to old "
100 "ql2xextended_error_logging=1).\n"
3ce8866c 101 "\t\tDo LOGICAL OR of the value to enable more than one level");
0181944f 102
a9083016 103int ql2xshiftctondsd = 6;
f2019cb1 104module_param(ql2xshiftctondsd, int, S_IRUGO);
a9083016
GM		 105MODULE_PARM_DESC(ql2xshiftctondsd,
106 "Set to control shifting of command type processing "
107 "based on total number of SG elements.");
108
7e47e5ca 109int ql2xfdmienable=1;
de187df8 110module_param(ql2xfdmienable, int, S_IRUGO|S_IWUSR);
a2b3e01d 111module_param_named(fdmi, ql2xfdmienable, int, S_IRUGO|S_IWUSR);
cca5335c 112MODULE_PARM_DESC(ql2xfdmienable,
7794a5af
FW		 113 "Enables FDMI registrations. "
114 "0 - no FDMI. Default is 1 - perform FDMI.");
cca5335c 115
d213a4b7 116#define MAX_Q_DEPTH 64
50280c01 117static int ql2xmaxqdepth = MAX_Q_DEPTH;
df7baa50
AV		 118module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR);
119MODULE_PARM_DESC(ql2xmaxqdepth,
e92e4a8f 120 "Maximum queue depth to set for each LUN. "
d213a4b7 121 "Default is 64.");
df7baa50 122
e84067d7
DG		 123#if (IS_ENABLED(CONFIG_NVME_FC))
124int ql2xenabledif;
125#else
9e522cd8 126int ql2xenabledif = 2;
e84067d7 127#endif
9e522cd8 128module_param(ql2xenabledif, int, S_IRUGO);
bad75002 129MODULE_PARM_DESC(ql2xenabledif,
b97f5d0b
SM		 130 " Enable T10-CRC-DIF:\n"
131 " Default is 2.\n"
132 " 0 -- No DIF Support\n"
133 " 1 -- Enable DIF for all types\n"
134 " 2 -- Enable DIF for all types, except Type 0.\n");
bad75002 135
e84067d7
DG		 136#if (IS_ENABLED(CONFIG_NVME_FC))
137int ql2xnvmeenable = 1;
138#else
139int ql2xnvmeenable;
140#endif
141module_param(ql2xnvmeenable, int, 0644);
142MODULE_PARM_DESC(ql2xnvmeenable,
143 "Enables NVME support. "
144 "0 - no NVMe. Default is Y");
145
8cb2049c 146int ql2xenablehba_err_chk = 2;
bad75002
AE		 147module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR);
148MODULE_PARM_DESC(ql2xenablehba_err_chk,
8cb2049c 149 " Enable T10-CRC-DIF Error isolation by HBA:\n"
b97f5d0b 150 " Default is 2.\n"
8cb2049c
AE		 151 " 0 -- Error isolation disabled\n"
152 " 1 -- Error isolation enabled only for DIX Type 0\n"
153 " 2 -- Error isolation enabled for all Types\n");
bad75002 154
e5896bd5 155int ql2xiidmaenable=1;
f2019cb1 156module_param(ql2xiidmaenable, int, S_IRUGO);
e5896bd5
AV		 157MODULE_PARM_DESC(ql2xiidmaenable,
158 "Enables iIDMA settings "
159 "Default is 1 - perform iIDMA. 0 - no iIDMA.");
160
d7459527
MH		 161int ql2xmqsupport = 1;
162module_param(ql2xmqsupport, int, S_IRUGO);
163MODULE_PARM_DESC(ql2xmqsupport,
164 "Enable on demand multiple queue pairs support "
165 "Default is 1 for supported. "
166 "Set it to 0 to turn off mq qpair support.");
e337d907
AV		 167
168int ql2xfwloadbin;
86e45bf6 169module_param(ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
a2b3e01d 170module_param_named(fwload, ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
e337d907 171MODULE_PARM_DESC(ql2xfwloadbin,
7c3df132
SK		 172 "Option to specify location from which to load ISP firmware:.\n"
173 " 2 -- load firmware via the request_firmware() (hotplug).\n"
e337d907
AV		 174 " interface.\n"
175 " 1 -- load firmware from flash.\n"
176 " 0 -- use default semantics.\n");
177
ae97c91e 178int ql2xetsenable;
f2019cb1 179module_param(ql2xetsenable, int, S_IRUGO);
ae97c91e
AV		 180MODULE_PARM_DESC(ql2xetsenable,
181 "Enables firmware ETS burst."
182 "Default is 0 - skip ETS enablement.");
183
6907869d 184int ql2xdbwr = 1;
86e45bf6 185module_param(ql2xdbwr, int, S_IRUGO|S_IWUSR);
a9083016 186MODULE_PARM_DESC(ql2xdbwr,
08de2844
GM		 187 "Option to specify scheme for request queue posting.\n"
188 " 0 -- Regular doorbell.\n"
189 " 1 -- CAMRAM doorbell (faster).\n");
a9083016 190
f4c496c1 191int ql2xtargetreset = 1;
f2019cb1 192module_param(ql2xtargetreset, int, S_IRUGO);
f4c496c1
GM		 193MODULE_PARM_DESC(ql2xtargetreset,
194 "Enable target reset."
195 "Default is 1 - use hw defaults.");
196
4da26e16 197int ql2xgffidenable;
f2019cb1 198module_param(ql2xgffidenable, int, S_IRUGO);
4da26e16
CD		 199MODULE_PARM_DESC(ql2xgffidenable,
200 "Enables GFF_ID checks of port type. "
201 "Default is 0 - Do not use GFF_ID information.");
a9083016 202
043dc1d7 203int ql2xasynctmfenable = 1;
f2019cb1 204module_param(ql2xasynctmfenable, int, S_IRUGO);
3822263e
MI		 205MODULE_PARM_DESC(ql2xasynctmfenable,
206 "Enables issue of TM IOCBs asynchronously via IOCB mechanism"
207 "Default is 0 - Issue TM IOCBs via mailbox mechanism.");
ed0de87c
GM		 208
209int ql2xdontresethba;
86e45bf6 210module_param(ql2xdontresethba, int, S_IRUGO|S_IWUSR);
ed0de87c 211MODULE_PARM_DESC(ql2xdontresethba,
08de2844
GM		 212 "Option to specify reset behaviour.\n"
213 " 0 (Default) -- Reset on failure.\n"
214 " 1 -- Do not reset on failure.\n");
ed0de87c 215
1abf635d
HR		 216uint64_t ql2xmaxlun = MAX_LUNS;
217module_param(ql2xmaxlun, ullong, S_IRUGO);
82515920
AV		 218MODULE_PARM_DESC(ql2xmaxlun,
219 "Defines the maximum LU number to register with the SCSI "
220 "midlayer. Default is 65535.");
221
08de2844
GM		 222int ql2xmdcapmask = 0x1F;
223module_param(ql2xmdcapmask, int, S_IRUGO);
224MODULE_PARM_DESC(ql2xmdcapmask,
225 "Set the Minidump driver capture mask level. "
6e96fa7b 226 "Default is 0x1F - Can be set to 0x3, 0x7, 0xF, 0x1F, 0x7F.");
08de2844 227
3aadff35 228int ql2xmdenable = 1;
08de2844
GM		 229module_param(ql2xmdenable, int, S_IRUGO);
230MODULE_PARM_DESC(ql2xmdenable,
231 "Enable/disable MiniDump. "
3aadff35
GM		 232 "0 - MiniDump disabled. "
233 "1 (Default) - MiniDump enabled.");
08de2844 234
b0d6cabd
HM		 235int ql2xexlogins = 0;
236module_param(ql2xexlogins, uint, S_IRUGO|S_IWUSR);
237MODULE_PARM_DESC(ql2xexlogins,
238 "Number of extended Logins. "
239 "0 (Default)- Disabled.");
240
99e1b683
QT		 241int ql2xexchoffld = 1024;
242module_param(ql2xexchoffld, uint, 0644);
2f56a7f1 243MODULE_PARM_DESC(ql2xexchoffld,
99e1b683
QT		 244 "Number of target exchanges.");
245
246int ql2xiniexchg = 1024;
247module_param(ql2xiniexchg, uint, 0644);
248MODULE_PARM_DESC(ql2xiniexchg,
249 "Number of initiator exchanges.");
2f56a7f1 250
f198cafa
HM		 251int ql2xfwholdabts = 0;
252module_param(ql2xfwholdabts, int, S_IRUGO);
253MODULE_PARM_DESC(ql2xfwholdabts,
254 "Allow FW to hold status IOCB until ABTS rsp received. "
255 "0 (Default) Do not set fw option. "
256 "1 - Set fw option to hold ABTS.");
257
41dc529a
QT		 258int ql2xmvasynctoatio = 1;
259module_param(ql2xmvasynctoatio, int, S_IRUGO|S_IWUSR);
260MODULE_PARM_DESC(ql2xmvasynctoatio,
261 "Move PUREX, ABTS RX and RIDA IOCBs to ATIOQ"
262 "0 (Default). Do not move IOCBs"
263 "1 - Move IOCBs.");
264
e4e3a2ce
QT		 265int ql2xautodetectsfp = 1;
266module_param(ql2xautodetectsfp, int, 0444);
267MODULE_PARM_DESC(ql2xautodetectsfp,
268 "Detect SFP range and set appropriate distance.\n"
269 "1 (Default): Enable\n");
270
e7240af5
HM		 271int ql2xenablemsix = 1;
272module_param(ql2xenablemsix, int, 0444);
273MODULE_PARM_DESC(ql2xenablemsix,
274 "Set to enable MSI or MSI-X interrupt mechanism.\n"
275 " Default is 1, enable MSI-X interrupt mechanism.\n"
276 " 0 -- enable traditional pin-based mechanism.\n"
277 " 1 -- enable MSI-X interrupt mechanism.\n"
278 " 2 -- enable MSI interrupt mechanism.\n");
279
1da177e4 280/*
fa2a1ce5 281 * SCSI host template entry points
1da177e4
LT		 282 */
283static int qla2xxx_slave_configure(struct scsi_device * device);
f4f051eb 284static int qla2xxx_slave_alloc(struct scsi_device *);
1e99e33a
AV		 285static int qla2xxx_scan_finished(struct Scsi_Host *, unsigned long time);
286static void qla2xxx_scan_start(struct Scsi_Host *);
f4f051eb 287static void qla2xxx_slave_destroy(struct scsi_device *);
f281233d 288static int qla2xxx_queuecommand(struct Scsi_Host *h, struct scsi_cmnd *cmd);
1da177e4
LT		 289static int qla2xxx_eh_abort(struct scsi_cmnd *);
290static int qla2xxx_eh_device_reset(struct scsi_cmnd *);
523ec773 291static int qla2xxx_eh_target_reset(struct scsi_cmnd *);
1da177e4
LT		 292static int qla2xxx_eh_bus_reset(struct scsi_cmnd *);
293static int qla2xxx_eh_host_reset(struct scsi_cmnd *);
1da177e4 294
1a2fbf18 295static void qla2x00_clear_drv_active(struct qla_hw_data *);
3491255e 296static void qla2x00_free_device(scsi_qla_host_t *);
2d5a4c34 297static void qla83xx_disable_laser(scsi_qla_host_t *vha);
5601236b 298static int qla2xxx_map_queues(struct Scsi_Host *shost);
e84067d7 299static void qla2x00_destroy_deferred_work(struct qla_hw_data *);
ce7e4af7 300
a5326f86 301struct scsi_host_template qla2xxx_driver_template = {
1da177e4 302 .module = THIS_MODULE,
cb63067a 303 .name = QLA2XXX_DRIVER_NAME,
a5326f86 304 .queuecommand = qla2xxx_queuecommand,
fca29703 305
b6a05c82 306 .eh_timed_out = fc_eh_timed_out,
fca29703
AV		 307 .eh_abort_handler = qla2xxx_eh_abort,
308 .eh_device_reset_handler = qla2xxx_eh_device_reset,
523ec773 309 .eh_target_reset_handler = qla2xxx_eh_target_reset,
fca29703
AV		 310 .eh_bus_reset_handler = qla2xxx_eh_bus_reset,
311 .eh_host_reset_handler = qla2xxx_eh_host_reset,
312
313 .slave_configure = qla2xxx_slave_configure,
314
315 .slave_alloc = qla2xxx_slave_alloc,
316 .slave_destroy = qla2xxx_slave_destroy,
ed677086
AV		 317 .scan_finished = qla2xxx_scan_finished,
318 .scan_start = qla2xxx_scan_start,
db5ed4df 319 .change_queue_depth = scsi_change_queue_depth,
5601236b 320 .map_queues = qla2xxx_map_queues,
fca29703
AV		 321 .this_id = -1,
322 .cmd_per_lun = 3,
323 .use_clustering = ENABLE_CLUSTERING,
324 .sg_tablesize = SG_ALL,
325
326 .max_sectors = 0xFFFF,
afb046e2 327 .shost_attrs = qla2x00_host_attrs,
2d70c103
NB		 328
329 .supported_mode = MODE_INITIATOR,
c40ecc12 330 .track_queue_depth = 1,
fca29703
AV		 331};
332
1da177e4 333static struct scsi_transport_template *qla2xxx_transport_template = NULL;
2c3dfe3f 334struct scsi_transport_template *qla2xxx_transport_vport_template = NULL;
1da177e4 335
1da177e4
LT		 336/* TODO Convert to inlines
337 *
338 * Timer routines
339 */
1da177e4 340
2c3dfe3f 341__inline__ void
8e5f4ba0 342qla2x00_start_timer(scsi_qla_host_t *vha, unsigned long interval)
1da177e4 343{
8e5f4ba0 344 timer_setup(&vha->timer, qla2x00_timer, 0);
e315cd28 345 vha->timer.expires = jiffies + interval * HZ;
e315cd28
AC		 346 add_timer(&vha->timer);
347 vha->timer_active = 1;
1da177e4
LT		 348}
349
350static inline void
e315cd28 351qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval)
1da177e4 352{
a9083016 353 /* Currently used for 82XX only. */
7c3df132
SK		 354 if (vha->device_flags & DFLG_DEV_FAILED) {
355 ql_dbg(ql_dbg_timer, vha, 0x600d,
356 "Device in a failed state, returning.\n");
a9083016 357 return;
7c3df132 358 }
a9083016 359
e315cd28 360 mod_timer(&vha->timer, jiffies + interval * HZ);
1da177e4
LT		 361}
362
a824ebb3 363static __inline__ void
e315cd28 364qla2x00_stop_timer(scsi_qla_host_t *vha)
1da177e4 365{
e315cd28
AC		 366 del_timer_sync(&vha->timer);
367 vha->timer_active = 0;
1da177e4
LT		 368}
369
1da177e4
LT		 370static int qla2x00_do_dpc(void *data);
371
372static void qla2x00_rst_aen(scsi_qla_host_t *);
373
73208dfd
AC		 374static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t,
375 struct req_que **, struct rsp_que **);
e30d1756 376static void qla2x00_free_fw_dump(struct qla_hw_data *);
e315cd28 377static void qla2x00_mem_free(struct qla_hw_data *);
d7459527
MH		 378int qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd,
379 struct qla_qpair *qpair);
1da177e4 380
1da177e4 381/* -------------------------------------------------------------------------- */
8abfa9e2
QT		 382static void qla_init_base_qpair(struct scsi_qla_host *vha, struct req_que *req,
383 struct rsp_que *rsp)
384{
385 struct qla_hw_data *ha = vha->hw;
386 rsp->qpair = ha->base_qpair;
387 rsp->req = req;
388 ha->base_qpair->req = req;
389 ha->base_qpair->rsp = rsp;
390 ha->base_qpair->vha = vha;
391 ha->base_qpair->qp_lock_ptr = &ha->hardware_lock;
392 ha->base_qpair->use_shadow_reg = IS_SHADOW_REG_CAPABLE(ha) ? 1 : 0;
393 ha->base_qpair->msix = &ha->msix_entries[QLA_MSIX_RSP_Q];
394 INIT_LIST_HEAD(&ha->base_qpair->hints_list);
cf19c45d 395 INIT_LIST_HEAD(&ha->base_qpair->nvme_done_list);
8abfa9e2
QT		 396 ha->base_qpair->enable_class_2 = ql2xenableclass2;
397 /* init qpair to this cpu. Will adjust at run time. */
86531887 398 qla_cpu_update(rsp->qpair, raw_smp_processor_id());
8abfa9e2
QT		 399 ha->base_qpair->pdev = ha->pdev;
400
401 if (IS_QLA27XX(ha) || IS_QLA83XX(ha))
402 ha->base_qpair->reqq_start_iocbs = qla_83xx_start_iocbs;
403}
404
9a347ff4
CD		 405static int qla2x00_alloc_queues(struct qla_hw_data *ha, struct req_que *req,
406 struct rsp_que *rsp)
73208dfd 407{
7c3df132 408 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2afa19a9 409 ha->req_q_map = kzalloc(sizeof(struct req_que *) * ha->max_req_queues,
73208dfd
AC		 410 GFP_KERNEL);
411 if (!ha->req_q_map) {
7c3df132
SK		 412 ql_log(ql_log_fatal, vha, 0x003b,
413 "Unable to allocate memory for request queue ptrs.\n");
73208dfd
AC		 414 goto fail_req_map;
415 }
416
2afa19a9 417 ha->rsp_q_map = kzalloc(sizeof(struct rsp_que *) * ha->max_rsp_queues,
73208dfd
AC		 418 GFP_KERNEL);
419 if (!ha->rsp_q_map) {
7c3df132
SK		 420 ql_log(ql_log_fatal, vha, 0x003c,
421 "Unable to allocate memory for response queue ptrs.\n");
73208dfd
AC		 422 goto fail_rsp_map;
423 }
d7459527 424
e326d22a
QT		 425 ha->base_qpair = kzalloc(sizeof(struct qla_qpair), GFP_KERNEL);
426 if (ha->base_qpair == NULL) {
427 ql_log(ql_log_warn, vha, 0x00e0,
428 "Failed to allocate base queue pair memory.\n");
429 goto fail_base_qpair;
430 }
431
8abfa9e2 432 qla_init_base_qpair(vha, req, rsp);
e326d22a 433
c38d1baf 434 if ((ql2xmqsupport || ql2xnvmeenable) && ha->max_qpairs) {
d7459527
MH		 435 ha->queue_pair_map = kcalloc(ha->max_qpairs, sizeof(struct qla_qpair *),
436 GFP_KERNEL);
437 if (!ha->queue_pair_map) {
438 ql_log(ql_log_fatal, vha, 0x0180,
439 "Unable to allocate memory for queue pair ptrs.\n");
440 goto fail_qpair_map;
441 }
d7459527
MH		 442 }
443
9a347ff4
CD		 444 /*
445 * Make sure we record at least the request and response queue zero in
446 * case we need to free them if part of the probe fails.
447 */
448 ha->rsp_q_map[0] = rsp;
449 ha->req_q_map[0] = req;
73208dfd
AC		 450 set_bit(0, ha->rsp_qid_map);
451 set_bit(0, ha->req_qid_map);
452 return 1;
453
d7459527 454fail_qpair_map:
82de802a
QT		 455 kfree(ha->base_qpair);
456 ha->base_qpair = NULL;
457fail_base_qpair:
d7459527
MH		 458 kfree(ha->rsp_q_map);
459 ha->rsp_q_map = NULL;
73208dfd
AC		 460fail_rsp_map:
461 kfree(ha->req_q_map);
462 ha->req_q_map = NULL;
463fail_req_map:
464 return -ENOMEM;
465}
466
2afa19a9 467static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req)
73208dfd 468{
8ae6d9c7
GM		 469 if (IS_QLAFX00(ha)) {
470 if (req && req->ring_fx00)
471 dma_free_coherent(&ha->pdev->dev,
472 (req->length_fx00 + 1) * sizeof(request_t),
473 req->ring_fx00, req->dma_fx00);
474 } else if (req && req->ring)
73208dfd
AC		 475 dma_free_coherent(&ha->pdev->dev,
476 (req->length + 1) * sizeof(request_t),
477 req->ring, req->dma);
478
8d93f550
CD		 479 if (req)
480 kfree(req->outstanding_cmds);
481
73208dfd 482 kfree(req);
73208dfd
AC		 483}
484
2afa19a9
AC		 485static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp)
486{
8ae6d9c7
GM		 487 if (IS_QLAFX00(ha)) {
488 if (rsp && rsp->ring)
489 dma_free_coherent(&ha->pdev->dev,
490 (rsp->length_fx00 + 1) * sizeof(request_t),
491 rsp->ring_fx00, rsp->dma_fx00);
492 } else if (rsp && rsp->ring) {
2afa19a9
AC		 493 dma_free_coherent(&ha->pdev->dev,
494 (rsp->length + 1) * sizeof(response_t),
495 rsp->ring, rsp->dma);
8ae6d9c7 496 }
2afa19a9 497 kfree(rsp);
2afa19a9
AC		 498}
499
73208dfd
AC		 500static void qla2x00_free_queues(struct qla_hw_data *ha)
501{
502 struct req_que *req;
503 struct rsp_que *rsp;
504 int cnt;
093df737 505 unsigned long flags;
73208dfd 506
82de802a
QT		 507 if (ha->queue_pair_map) {
508 kfree(ha->queue_pair_map);
509 ha->queue_pair_map = NULL;
510 }
511 if (ha->base_qpair) {
512 kfree(ha->base_qpair);
513 ha->base_qpair = NULL;
514 }
515
093df737 516 spin_lock_irqsave(&ha->hardware_lock, flags);
2afa19a9 517 for (cnt = 0; cnt < ha->max_req_queues; cnt++) {
cb43285f
QT		 518 if (!test_bit(cnt, ha->req_qid_map))
519 continue;
520
73208dfd 521 req = ha->req_q_map[cnt];
093df737
QT		 522 clear_bit(cnt, ha->req_qid_map);
523 ha->req_q_map[cnt] = NULL;
524
525 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2afa19a9 526 qla2x00_free_req_que(ha, req);
093df737 527 spin_lock_irqsave(&ha->hardware_lock, flags);
73208dfd 528 }
093df737
QT		 529 spin_unlock_irqrestore(&ha->hardware_lock, flags);
530
73208dfd
AC		 531 kfree(ha->req_q_map);
532 ha->req_q_map = NULL;
2afa19a9 533
093df737
QT		 534
535 spin_lock_irqsave(&ha->hardware_lock, flags);
2afa19a9 536 for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) {
cb43285f
QT		 537 if (!test_bit(cnt, ha->rsp_qid_map))
538 continue;
539
2afa19a9 540 rsp = ha->rsp_q_map[cnt];
c3c42394 541 clear_bit(cnt, ha->rsp_qid_map);
093df737
QT		 542 ha->rsp_q_map[cnt] = NULL;
543 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2afa19a9 544 qla2x00_free_rsp_que(ha, rsp);
093df737 545 spin_lock_irqsave(&ha->hardware_lock, flags);
2afa19a9 546 }
093df737
QT		 547 spin_unlock_irqrestore(&ha->hardware_lock, flags);
548
2afa19a9
AC		 549 kfree(ha->rsp_q_map);
550 ha->rsp_q_map = NULL;
73208dfd
AC		 551}
552
1da177e4 553static char *
e315cd28 554qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str)
1da177e4 555{
e315cd28 556 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 557 static char *pci_bus_modes[] = {
558 "33", "66", "100", "133",
559 };
560 uint16_t pci_bus;
561
562 strcpy(str, "PCI");
563 pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9;
564 if (pci_bus) {
565 strcat(str, "-X (");
566 strcat(str, pci_bus_modes[pci_bus]);
567 } else {
568 pci_bus = (ha->pci_attr & BIT_8) >> 8;
569 strcat(str, " (");
570 strcat(str, pci_bus_modes[pci_bus]);
571 }
572 strcat(str, " MHz)");
573
574 return (str);
575}
576
fca29703 577static char *
e315cd28 578qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str)
fca29703
AV		 579{
580 static char *pci_bus_modes[] = { "33", "66", "100", "133", };
e315cd28 581 struct qla_hw_data *ha = vha->hw;
fca29703 582 uint32_t pci_bus;
fca29703 583
62a276f8 584 if (pci_is_pcie(ha->pdev)) {
fca29703 585 char lwstr[6];
62a276f8 586 uint32_t lstat, lspeed, lwidth;
fca29703 587
62a276f8
BH		 588 pcie_capability_read_dword(ha->pdev, PCI_EXP_LNKCAP, &lstat);
589 lspeed = lstat & PCI_EXP_LNKCAP_SLS;
590 lwidth = (lstat & PCI_EXP_LNKCAP_MLW) >> 4;
fca29703
AV		 591
592 strcpy(str, "PCIe (");
49300af7
SK		 593 switch (lspeed) {
594 case 1:
c87a0d8c 595 strcat(str, "2.5GT/s ");
49300af7
SK		 596 break;
597 case 2:
c87a0d8c 598 strcat(str, "5.0GT/s ");
49300af7
SK		 599 break;
600 case 3:
601 strcat(str, "8.0GT/s ");
602 break;
603 default:
fca29703 604 strcat(str, "<unknown> ");
49300af7
SK		 605 break;
606 }
fca29703
AV		 607 snprintf(lwstr, sizeof(lwstr), "x%d)", lwidth);
608 strcat(str, lwstr);
609
610 return str;
611 }
612
613 strcpy(str, "PCI");
614 pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8;
615 if (pci_bus == 0 || pci_bus == 8) {
616 strcat(str, " (");
617 strcat(str, pci_bus_modes[pci_bus >> 3]);
618 } else {
619 strcat(str, "-X ");
620 if (pci_bus & BIT_2)
621 strcat(str, "Mode 2");
622 else
623 strcat(str, "Mode 1");
624 strcat(str, " (");
625 strcat(str, pci_bus_modes[pci_bus & ~BIT_2]);
626 }
627 strcat(str, " MHz)");
628
629 return str;
630}
631
e5f82ab8 632static char *
df57caba 633qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
1da177e4
LT		 634{
635 char un_str[10];
e315cd28 636 struct qla_hw_data *ha = vha->hw;
fa2a1ce5 637
df57caba
HM		 638 snprintf(str, size, "%d.%02d.%02d ", ha->fw_major_version,
639 ha->fw_minor_version, ha->fw_subminor_version);
1da177e4
LT		 640
641 if (ha->fw_attributes & BIT_9) {
642 strcat(str, "FLX");
643 return (str);
644 }
645
646 switch (ha->fw_attributes & 0xFF) {
647 case 0x7:
648 strcat(str, "EF");
649 break;
650 case 0x17:
651 strcat(str, "TP");
652 break;
653 case 0x37:
654 strcat(str, "IP");
655 break;
656 case 0x77:
657 strcat(str, "VI");
658 break;
659 default:
660 sprintf(un_str, "(%x)", ha->fw_attributes);
661 strcat(str, un_str);
662 break;
663 }
664 if (ha->fw_attributes & 0x100)
665 strcat(str, "X");
666
667 return (str);
668}
669
e5f82ab8 670static char *
df57caba 671qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
fca29703 672{
e315cd28 673 struct qla_hw_data *ha = vha->hw;
f0883ac6 674
df57caba 675 snprintf(str, size, "%d.%02d.%02d (%x)", ha->fw_major_version,
3a03eb79 676 ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes);
fca29703 677 return str;
fca29703
AV		 678}
679
9ba56b95 680void
25ff6af1 681qla2x00_sp_free_dma(void *ptr)
fca29703 682{
25ff6af1
JC		 683 srb_t *sp = ptr;
684 struct qla_hw_data *ha = sp->vha->hw;
9ba56b95 685 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
9ba56b95 686 void *ctx = GET_CMD_CTX_SP(sp);
fca29703 687
9ba56b95
GM		 688 if (sp->flags & SRB_DMA_VALID) {
689 scsi_dma_unmap(cmd);
690 sp->flags &= ~SRB_DMA_VALID;
7c3df132 691 }
fca29703 692
9ba56b95
GM		 693 if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
694 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
695 scsi_prot_sg_count(cmd), cmd->sc_data_direction);
696 sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
697 }
698
d5ff0eed
JC		 699 if (!ctx)
700 goto end;
701
9ba56b95
GM		 702 if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
703 /* List assured to be having elements */
d5ff0eed 704 qla2x00_clean_dsd_pool(ha, ctx);
9ba56b95
GM		 705 sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
706 }
707
708 if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
d5ff0eed
JC		 709 struct crc_context *ctx0 = ctx;
710
711 dma_pool_free(ha->dl_dma_pool, ctx0, ctx0->crc_ctx_dma);
9ba56b95
GM		 712 sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
713 }
714
715 if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
d5ff0eed 716 struct ct6_dsd *ctx1 = ctx;
fca29703 717
9ba56b95 718 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd,
d5ff0eed 719 ctx1->fcp_cmnd_dma);
9ba56b95
GM		 720 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list);
721 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt;
722 ha->gbl_dsd_avail += ctx1->dsd_use_cnt;
723 mempool_free(ctx1, ha->ctx_mempool);
9ba56b95
GM		 724 }
725
d5ff0eed 726end:
6fcd98fd 727 if (sp->type != SRB_NVME_CMD && sp->type != SRB_NVME_LS) {
7401bc18
DG		 728 CMD_SP(cmd) = NULL;
729 qla2x00_rel_sp(sp);
730 }
9ba56b95
GM		 731}
732
d7459527 733void
25ff6af1 734qla2x00_sp_compl(void *ptr, int res)
9ba56b95 735{
25ff6af1 736 srb_t *sp = ptr;
9ba56b95
GM		 737 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
738
739 cmd->result = res;
740
741 if (atomic_read(&sp->ref_count) == 0) {
25ff6af1 742 ql_dbg(ql_dbg_io, sp->vha, 0x3015,
9ba56b95
GM		 743 "SP reference-count to ZERO -- sp=%p cmd=%p.\n",
744 sp, GET_CMD_SP(sp));
745 if (ql2xextended_error_logging & ql_dbg_io)
8fbdac8c 746 WARN_ON(atomic_read(&sp->ref_count) == 0);
9ba56b95
GM		 747 return;
748 }
749 if (!atomic_dec_and_test(&sp->ref_count))
750 return;
751
f3caa990 752 sp->free(sp);
9ba56b95 753 cmd->scsi_done(cmd);
fca29703
AV		 754}
755
d7459527 756void
25ff6af1 757qla2xxx_qpair_sp_free_dma(void *ptr)
d7459527
MH		 758{
759 srb_t *sp = (srb_t *)ptr;
760 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
761 struct qla_hw_data *ha = sp->fcport->vha->hw;
762 void *ctx = GET_CMD_CTX_SP(sp);
763
764 if (sp->flags & SRB_DMA_VALID) {
765 scsi_dma_unmap(cmd);
766 sp->flags &= ~SRB_DMA_VALID;
767 }
768
769 if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
770 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
771 scsi_prot_sg_count(cmd), cmd->sc_data_direction);
772 sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
773 }
774
d5ff0eed
JC		 775 if (!ctx)
776 goto end;
777
d7459527
MH		 778 if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
779 /* List assured to be having elements */
d5ff0eed 780 qla2x00_clean_dsd_pool(ha, ctx);
d7459527
MH		 781 sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
782 }
783
784 if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
d5ff0eed
JC		 785 struct crc_context *ctx0 = ctx;
786
787 dma_pool_free(ha->dl_dma_pool, ctx, ctx0->crc_ctx_dma);
d7459527
MH		 788 sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
789 }
790
791 if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
d5ff0eed 792 struct ct6_dsd *ctx1 = ctx;
d7459527
MH		 793 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd,
794 ctx1->fcp_cmnd_dma);
795 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list);
796 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt;
797 ha->gbl_dsd_avail += ctx1->dsd_use_cnt;
798 mempool_free(ctx1, ha->ctx_mempool);
799 }
d5ff0eed 800end:
d7459527
MH		 801 CMD_SP(cmd) = NULL;
802 qla2xxx_rel_qpair_sp(sp->qpair, sp);
803}
804
805void
25ff6af1 806qla2xxx_qpair_sp_compl(void *ptr, int res)
d7459527 807{
25ff6af1 808 srb_t *sp = ptr;
d7459527
MH		 809 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
810
811 cmd->result = res;
812
813 if (atomic_read(&sp->ref_count) == 0) {
814 ql_dbg(ql_dbg_io, sp->fcport->vha, 0x3079,
815 "SP reference-count to ZERO -- sp=%p cmd=%p.\n",
816 sp, GET_CMD_SP(sp));
817 if (ql2xextended_error_logging & ql_dbg_io)
818 WARN_ON(atomic_read(&sp->ref_count) == 0);
819 return;
820 }
821 if (!atomic_dec_and_test(&sp->ref_count))
822 return;
823
f3caa990 824 sp->free(sp);
d7459527
MH		 825 cmd->scsi_done(cmd);
826}
827
8ae6d9c7
GM		 828/* If we are SP1 here, we need to still take and release the host_lock as SP1
829 * does not have the changes necessary to avoid taking host->host_lock.
830 */
1da177e4 831static int
f5e3e40b 832qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
fca29703 833{
134ae078 834 scsi_qla_host_t *vha = shost_priv(host);
fca29703 835 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
19a7b4ae 836 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
e315cd28
AC		 837 struct qla_hw_data *ha = vha->hw;
838 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
fca29703
AV		 839 srb_t *sp;
840 int rval;
5601236b
MH		 841 struct qla_qpair *qpair = NULL;
842 uint32_t tag;
843 uint16_t hwq;
fca29703 844
04dfaa53
MFO		 845 if (unlikely(test_bit(UNLOADING, &base_vha->dpc_flags))) {
846 cmd->result = DID_NO_CONNECT << 16;
847 goto qc24_fail_command;
848 }
849
5601236b
MH		 850 if (ha->mqenable) {
851 if (shost_use_blk_mq(vha->host)) {
852 tag = blk_mq_unique_tag(cmd->request);
853 hwq = blk_mq_unique_tag_to_hwq(tag);
854 qpair = ha->queue_pair_map[hwq];
855 } else if (vha->vp_idx && vha->qpair) {
856 qpair = vha->qpair;
857 }
858
859 if (qpair)
860 return qla2xxx_mqueuecommand(host, cmd, qpair);
d7459527
MH		 861 }
862
85880801 863 if (ha->flags.eeh_busy) {
7c3df132 864 if (ha->flags.pci_channel_io_perm_failure) {
5f28d2d7 865 ql_dbg(ql_dbg_aer, vha, 0x9010,
7c3df132
SK		 866 "PCI Channel IO permanent failure, exiting "
867 "cmd=%p.\n", cmd);
b9b12f73 868 cmd->result = DID_NO_CONNECT << 16;
7c3df132 869 } else {
5f28d2d7 870 ql_dbg(ql_dbg_aer, vha, 0x9011,
7c3df132 871 "EEH_Busy, Requeuing the cmd=%p.\n", cmd);
85880801 872 cmd->result = DID_REQUEUE << 16;
7c3df132 873 }
14e660e6
SJ		 874 goto qc24_fail_command;
875 }
876
19a7b4ae
JSEC		 877 rval = fc_remote_port_chkready(rport);
878 if (rval) {
879 cmd->result = rval;
5f28d2d7 880 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3003,
7c3df132
SK		 881 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
882 cmd, rval);
fca29703
AV		 883 goto qc24_fail_command;
884 }
885
bad75002
AE		 886 if (!vha->flags.difdix_supported &&
887 scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) {
7c3df132
SK		 888 ql_dbg(ql_dbg_io, vha, 0x3004,
889 "DIF Cap not reg, fail DIF capable cmd's:%p.\n",
890 cmd);
bad75002
AE		 891 cmd->result = DID_NO_CONNECT << 16;
892 goto qc24_fail_command;
893 }
aa651be8
CD		 894
895 if (!fcport) {
896 cmd->result = DID_NO_CONNECT << 16;
897 goto qc24_fail_command;
898 }
899
fca29703
AV		 900 if (atomic_read(&fcport->state) != FCS_ONLINE) {
901 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
38170fa8 902 atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
7c3df132
SK		 903 ql_dbg(ql_dbg_io, vha, 0x3005,
904 "Returning DNC, fcport_state=%d loop_state=%d.\n",
905 atomic_read(&fcport->state),
906 atomic_read(&base_vha->loop_state));
fca29703
AV		 907 cmd->result = DID_NO_CONNECT << 16;
908 goto qc24_fail_command;
909 }
7b594131 910 goto qc24_target_busy;
fca29703
AV		 911 }
912
e05fe292
CD		 913 /*
914 * Return target busy if we've received a non-zero retry_delay_timer
915 * in a FCP_RSP.
916 */
975f7d46
BP		 917 if (fcport->retry_delay_timestamp == 0) {
918 /* retry delay not set */
919 } else if (time_after(jiffies, fcport->retry_delay_timestamp))
e05fe292
CD		 920 fcport->retry_delay_timestamp = 0;
921 else
922 goto qc24_target_busy;
923
b00ee7d7 924 sp = qla2x00_get_sp(vha, fcport, GFP_ATOMIC);
50280c01 925 if (!sp)
f5e3e40b 926 goto qc24_host_busy;
fca29703 927
9ba56b95
GM		 928 sp->u.scmd.cmd = cmd;
929 sp->type = SRB_SCSI_CMD;
930 atomic_set(&sp->ref_count, 1);
931 CMD_SP(cmd) = (void *)sp;
932 sp->free = qla2x00_sp_free_dma;
933 sp->done = qla2x00_sp_compl;
934
e315cd28 935 rval = ha->isp_ops->start_scsi(sp);
7c3df132 936 if (rval != QLA_SUCCESS) {
53016ed3 937 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3013,
7c3df132 938 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
fca29703 939 goto qc24_host_busy_free_sp;
7c3df132 940 }
fca29703 941
fca29703
AV		 942 return 0;
943
944qc24_host_busy_free_sp:
f3caa990 945 sp->free(sp);
fca29703 946
f5e3e40b 947qc24_host_busy:
fca29703
AV		 948 return SCSI_MLQUEUE_HOST_BUSY;
949
7b594131
MC		 950qc24_target_busy:
951 return SCSI_MLQUEUE_TARGET_BUSY;
952
fca29703 953qc24_fail_command:
f5e3e40b 954 cmd->scsi_done(cmd);
fca29703
AV		 955
956 return 0;
957}
958
d7459527
MH		 959/* For MQ supported I/O */
960int
961qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd,
962 struct qla_qpair *qpair)
963{
964 scsi_qla_host_t *vha = shost_priv(host);
965 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
966 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
967 struct qla_hw_data *ha = vha->hw;
968 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
969 srb_t *sp;
970 int rval;
971
972 rval = fc_remote_port_chkready(rport);
973 if (rval) {
974 cmd->result = rval;
975 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3076,
976 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
977 cmd, rval);
978 goto qc24_fail_command;
979 }
980
981 if (!fcport) {
982 cmd->result = DID_NO_CONNECT << 16;
983 goto qc24_fail_command;
984 }
985
986 if (atomic_read(&fcport->state) != FCS_ONLINE) {
987 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
988 atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
989 ql_dbg(ql_dbg_io, vha, 0x3077,
990 "Returning DNC, fcport_state=%d loop_state=%d.\n",
991 atomic_read(&fcport->state),
992 atomic_read(&base_vha->loop_state));
993 cmd->result = DID_NO_CONNECT << 16;
994 goto qc24_fail_command;
995 }
996 goto qc24_target_busy;
997 }
998
999 /*
1000 * Return target busy if we've received a non-zero retry_delay_timer
1001 * in a FCP_RSP.
1002 */
1003 if (fcport->retry_delay_timestamp == 0) {
1004 /* retry delay not set */
1005 } else if (time_after(jiffies, fcport->retry_delay_timestamp))
1006 fcport->retry_delay_timestamp = 0;
1007 else
1008 goto qc24_target_busy;
1009
1010 sp = qla2xxx_get_qpair_sp(qpair, fcport, GFP_ATOMIC);
1011 if (!sp)
1012 goto qc24_host_busy;
1013
1014 sp->u.scmd.cmd = cmd;
1015 sp->type = SRB_SCSI_CMD;
1016 atomic_set(&sp->ref_count, 1);
1017 CMD_SP(cmd) = (void *)sp;
1018 sp->free = qla2xxx_qpair_sp_free_dma;
1019 sp->done = qla2xxx_qpair_sp_compl;
1020 sp->qpair = qpair;
1021
1022 rval = ha->isp_ops->start_scsi_mq(sp);
1023 if (rval != QLA_SUCCESS) {
1024 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3078,
1025 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
1026 if (rval == QLA_INTERFACE_ERROR)
1027 goto qc24_fail_command;
1028 goto qc24_host_busy_free_sp;
1029 }
1030
1031 return 0;
1032
1033qc24_host_busy_free_sp:
f3caa990 1034 sp->free(sp);
d7459527
MH		 1035
1036qc24_host_busy:
1037 return SCSI_MLQUEUE_HOST_BUSY;
1038
1039qc24_target_busy:
1040 return SCSI_MLQUEUE_TARGET_BUSY;
1041
1042qc24_fail_command:
1043 cmd->scsi_done(cmd);
1044
1045 return 0;
1046}
1047
1da177e4
LT		 1048/*
1049 * qla2x00_eh_wait_on_command
1050 * Waits for the command to be returned by the Firmware for some
1051 * max time.
1052 *
1053 * Input:
1da177e4 1054 * cmd = Scsi Command to wait on.
1da177e4
LT		 1055 *
1056 * Return:
1057 * Not Found : 0
1058 * Found : 1
1059 */
1060static int
e315cd28 1061qla2x00_eh_wait_on_command(struct scsi_cmnd *cmd)
1da177e4 1062{
fe74c71f 1063#define ABORT_POLLING_PERIOD 1000
478c3b03 1064#define ABORT_WAIT_ITER ((2 * 1000) / (ABORT_POLLING_PERIOD))
f4f051eb 1065 unsigned long wait_iter = ABORT_WAIT_ITER;
85880801
AV		 1066 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1067 struct qla_hw_data *ha = vha->hw;
f4f051eb 1068 int ret = QLA_SUCCESS;
1da177e4 1069
85880801 1070 if (unlikely(pci_channel_offline(ha->pdev)) || ha->flags.eeh_busy) {
7c3df132
SK		 1071 ql_dbg(ql_dbg_taskm, vha, 0x8005,
1072 "Return:eh_wait.\n");
85880801
AV		 1073 return ret;
1074 }
1075
d970432c 1076 while (CMD_SP(cmd) && wait_iter--) {
fe74c71f 1077 msleep(ABORT_POLLING_PERIOD);
f4f051eb 1078 }
1079 if (CMD_SP(cmd))
1080 ret = QLA_FUNCTION_FAILED;
1da177e4 1081
f4f051eb 1082 return ret;
1da177e4
LT		 1083}
1084
1085/*
1086 * qla2x00_wait_for_hba_online
fa2a1ce5 1087 * Wait till the HBA is online after going through
1da177e4
LT		 1088 * <= MAX_RETRIES_OF_ISP_ABORT or
1089 * finally HBA is disabled ie marked offline
1090 *
1091 * Input:
1092 * ha - pointer to host adapter structure
fa2a1ce5
AV		 1093 *
1094 * Note:
1da177e4
LT		 1095 * Does context switching-Release SPIN_LOCK
1096 * (if any) before calling this routine.
1097 *
1098 * Return:
1099 * Success (Adapter is online) : 0
1100 * Failed (Adapter is offline/disabled) : 1
1101 */
854165f4 1102int
e315cd28 1103qla2x00_wait_for_hba_online(scsi_qla_host_t *vha)
1da177e4 1104{
fca29703
AV		 1105 int return_status;
1106 unsigned long wait_online;
e315cd28
AC		 1107 struct qla_hw_data *ha = vha->hw;
1108 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4 1109
fa2a1ce5 1110 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ);
e315cd28
AC		 1111 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
1112 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
1113 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
1114 ha->dpc_active) && time_before(jiffies, wait_online)) {
1da177e4
LT		 1115
1116 msleep(1000);
1117 }
e315cd28 1118 if (base_vha->flags.online)
fa2a1ce5 1119 return_status = QLA_SUCCESS;
1da177e4
LT		 1120 else
1121 return_status = QLA_FUNCTION_FAILED;
1122
1da177e4
LT		 1123 return (return_status);
1124}
1125
726b8548
QT		 1126static inline int test_fcport_count(scsi_qla_host_t *vha)
1127{
1128 struct qla_hw_data *ha = vha->hw;
1129 unsigned long flags;
1130 int res;
1131
1132 spin_lock_irqsave(&ha->tgt.sess_lock, flags);
83548fe2
QT		 1133 ql_dbg(ql_dbg_init, vha, 0x00ec,
1134 "tgt %p, fcport_count=%d\n",
1135 vha, vha->fcport_count);
726b8548
QT		 1136 res = (vha->fcport_count == 0);
1137 spin_unlock_irqrestore(&ha->tgt.sess_lock, flags);
1138
1139 return res;
1140}
1141
1142/*
1143 * qla2x00_wait_for_sess_deletion can only be called from remove_one.
1144 * it has dependency on UNLOADING flag to stop device discovery
1145 */
1146static void
1147qla2x00_wait_for_sess_deletion(scsi_qla_host_t *vha)
1148{
1149 qla2x00_mark_all_devices_lost(vha, 0);
1150
b85e0957 1151 wait_event_timeout(vha->fcport_waitQ, test_fcport_count(vha), 10*HZ);
726b8548
QT		 1152}
1153
86fbee86 1154/*
638a1a01
SC		 1155 * qla2x00_wait_for_hba_ready
1156 * Wait till the HBA is ready before doing driver unload
86fbee86
LC		 1157 *
1158 * Input:
1159 * ha - pointer to host adapter structure
1160 *
1161 * Note:
1162 * Does context switching-Release SPIN_LOCK
1163 * (if any) before calling this routine.
1164 *
86fbee86 1165 */
638a1a01
SC		 1166static void
1167qla2x00_wait_for_hba_ready(scsi_qla_host_t *vha)
86fbee86 1168{
86fbee86 1169 struct qla_hw_data *ha = vha->hw;
783e0dc4 1170 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
86fbee86 1171
1d483901
DC		 1172 while ((qla2x00_reset_active(vha) || ha->dpc_active ||
1173 ha->flags.mbox_busy) ||
1174 test_bit(FX00_RESET_RECOVERY, &vha->dpc_flags) ||
1175 test_bit(FX00_TARGET_SCAN, &vha->dpc_flags)) {
1176 if (test_bit(UNLOADING, &base_vha->dpc_flags))
1177 break;
86fbee86 1178 msleep(1000);
783e0dc4 1179 }
86fbee86
LC		 1180}
1181
2533cf67
LC		 1182int
1183qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha)
1184{
1185 int return_status;
1186 unsigned long wait_reset;
1187 struct qla_hw_data *ha = vha->hw;
1188 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1189
1190 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ);
1191 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
1192 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
1193 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
1194 ha->dpc_active) && time_before(jiffies, wait_reset)) {
1195
1196 msleep(1000);
1197
1198 if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) &&
1199 ha->flags.chip_reset_done)
1200 break;
1201 }
1202 if (ha->flags.chip_reset_done)
1203 return_status = QLA_SUCCESS;
1204 else
1205 return_status = QLA_FUNCTION_FAILED;
1206
1207 return return_status;
1208}
1209
083a469d
GM		 1210static void
1211sp_get(struct srb *sp)
1212{
1213 atomic_inc(&sp->ref_count);
1214}
1215
a465537a
SC		 1216#define ISP_REG_DISCONNECT 0xffffffffU
1217/**************************************************************************
1218* qla2x00_isp_reg_stat
1219*
1220* Description:
1221* Read the host status register of ISP before aborting the command.
1222*
1223* Input:
1224* ha = pointer to host adapter structure.
1225*
1226*
1227* Returns:
1228* Either true or false.
1229*
1230* Note: Return true if there is register disconnect.
1231**************************************************************************/
1232static inline
1233uint32_t qla2x00_isp_reg_stat(struct qla_hw_data *ha)
1234{
1235 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
bf6061b1 1236 struct device_reg_82xx __iomem *reg82 = &ha->iobase->isp82;
a465537a 1237
bf6061b1
SC		 1238 if (IS_P3P_TYPE(ha))
1239 return ((RD_REG_DWORD(&reg82->host_int)) == ISP_REG_DISCONNECT);
1240 else
1241 return ((RD_REG_DWORD(&reg->host_status)) ==
1242 ISP_REG_DISCONNECT);
a465537a
SC		 1243}
1244
1da177e4
LT		 1245/**************************************************************************
1246* qla2xxx_eh_abort
1247*
1248* Description:
1249* The abort function will abort the specified command.
1250*
1251* Input:
1252* cmd = Linux SCSI command packet to be aborted.
1253*
1254* Returns:
1255* Either SUCCESS or FAILED.
1256*
1257* Note:
2ea00202 1258* Only return FAILED if command not returned by firmware.
1da177e4 1259**************************************************************************/
e5f82ab8 1260static int
1da177e4
LT		 1261qla2xxx_eh_abort(struct scsi_cmnd *cmd)
1262{
e315cd28 1263 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
f4f051eb 1264 srb_t *sp;
4e98d3b8 1265 int ret;
9cb78c16
HR		 1266 unsigned int id;
1267 uint64_t lun;
18e144d3 1268 unsigned long flags;
f934c9d0 1269 int rval, wait = 0;
e315cd28 1270 struct qla_hw_data *ha = vha->hw;
1da177e4 1271
a465537a
SC		 1272 if (qla2x00_isp_reg_stat(ha)) {
1273 ql_log(ql_log_info, vha, 0x8042,
1274 "PCI/Register disconnect, exiting.\n");
1275 return FAILED;
1276 }
f4f051eb 1277 if (!CMD_SP(cmd))
2ea00202 1278 return SUCCESS;
1da177e4 1279
4e98d3b8
AV		 1280 ret = fc_block_scsi_eh(cmd);
1281 if (ret != 0)
1282 return ret;
1283 ret = SUCCESS;
1284
f4f051eb 1285 id = cmd->device->id;
1286 lun = cmd->device->lun;
1da177e4 1287
e315cd28 1288 spin_lock_irqsave(&ha->hardware_lock, flags);
170babc3
MC		 1289 sp = (srb_t *) CMD_SP(cmd);
1290 if (!sp) {
1291 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1292 return SUCCESS;
1293 }
1da177e4 1294
7c3df132 1295 ql_dbg(ql_dbg_taskm, vha, 0x8002,
c7bc4cae
CD		 1296 "Aborting from RISC nexus=%ld:%d:%llu sp=%p cmd=%p handle=%x\n",
1297 vha->host_no, id, lun, sp, cmd, sp->handle);
17d98630 1298
170babc3
MC		 1299 /* Get a reference to the sp and drop the lock.*/
1300 sp_get(sp);
083a469d 1301
e315cd28 1302 spin_unlock_irqrestore(&ha->hardware_lock, flags);
f934c9d0
CD		 1303 rval = ha->isp_ops->abort_command(sp);
1304 if (rval) {
96219424 1305 if (rval == QLA_FUNCTION_PARAMETER_ERROR)
f934c9d0 1306 ret = SUCCESS;
96219424 1307 else
f934c9d0
CD		 1308 ret = FAILED;
1309
7c3df132 1310 ql_dbg(ql_dbg_taskm, vha, 0x8003,
f934c9d0 1311 "Abort command mbx failed cmd=%p, rval=%x.\n", cmd, rval);
170babc3 1312 } else {
7c3df132 1313 ql_dbg(ql_dbg_taskm, vha, 0x8004,
cfb0919c 1314 "Abort command mbx success cmd=%p.\n", cmd);
170babc3
MC		 1315 wait = 1;
1316 }
75942064
SK		 1317
1318 spin_lock_irqsave(&ha->hardware_lock, flags);
25ff6af1 1319 sp->done(sp, 0);
75942064 1320 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1da177e4 1321
bc91ade9
CD		 1322 /* Did the command return during mailbox execution? */
1323 if (ret == FAILED && !CMD_SP(cmd))
1324 ret = SUCCESS;
1325
f4f051eb 1326 /* Wait for the command to be returned. */
2ea00202 1327 if (wait) {
e315cd28 1328 if (qla2x00_eh_wait_on_command(cmd) != QLA_SUCCESS) {
7c3df132 1329 ql_log(ql_log_warn, vha, 0x8006,
cfb0919c 1330 "Abort handler timed out cmd=%p.\n", cmd);
2ea00202 1331 ret = FAILED;
f4f051eb 1332 }
1da177e4 1333 }
1da177e4 1334
7c3df132 1335 ql_log(ql_log_info, vha, 0x801c,
9cb78c16 1336 "Abort command issued nexus=%ld:%d:%llu -- %d %x.\n",
cfb0919c 1337 vha->host_no, id, lun, wait, ret);
1da177e4 1338
f4f051eb 1339 return ret;
1340}
1da177e4 1341
4d78c973 1342int
e315cd28 1343qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t,
9cb78c16 1344 uint64_t l, enum nexus_wait_type type)
f4f051eb 1345{
17d98630 1346 int cnt, match, status;
18e144d3 1347 unsigned long flags;
e315cd28 1348 struct qla_hw_data *ha = vha->hw;
73208dfd 1349 struct req_que *req;
4d78c973 1350 srb_t *sp;
9ba56b95 1351 struct scsi_cmnd *cmd;
1da177e4 1352
523ec773 1353 status = QLA_SUCCESS;
17d98630 1354
e315cd28 1355 spin_lock_irqsave(&ha->hardware_lock, flags);
67c2e93a 1356 req = vha->req;
17d98630 1357 for (cnt = 1; status == QLA_SUCCESS &&
8d93f550 1358 cnt < req->num_outstanding_cmds; cnt++) {
17d98630
AC		 1359 sp = req->outstanding_cmds[cnt];
1360 if (!sp)
523ec773 1361 continue;
9ba56b95 1362 if (sp->type != SRB_SCSI_CMD)
cf53b069 1363 continue;
25ff6af1 1364 if (vha->vp_idx != sp->vha->vp_idx)
17d98630
AC		 1365 continue;
1366 match = 0;
9ba56b95 1367 cmd = GET_CMD_SP(sp);
17d98630
AC		 1368 switch (type) {
1369 case WAIT_HOST:
1370 match = 1;
1371 break;
1372 case WAIT_TARGET:
9ba56b95 1373 match = cmd->device->id == t;
17d98630
AC		 1374 break;
1375 case WAIT_LUN:
9ba56b95
GM		 1376 match = (cmd->device->id == t &&
1377 cmd->device->lun == l);
17d98630 1378 break;
73208dfd 1379 }
17d98630
AC		 1380 if (!match)
1381 continue;
1382
1383 spin_unlock_irqrestore(&ha->hardware_lock, flags);
9ba56b95 1384 status = qla2x00_eh_wait_on_command(cmd);
17d98630 1385 spin_lock_irqsave(&ha->hardware_lock, flags);
1da177e4 1386 }
e315cd28 1387 spin_unlock_irqrestore(&ha->hardware_lock, flags);
523ec773
AV		 1388
1389 return status;
1da177e4
LT		 1390}
1391
523ec773
AV		 1392static char *reset_errors[] = {
1393 "HBA not online",
1394 "HBA not ready",
1395 "Task management failed",
1396 "Waiting for command completions",
1397};
1da177e4 1398
e5f82ab8 1399static int
523ec773 1400__qla2xxx_eh_generic_reset(char *name, enum nexus_wait_type type,
9cb78c16 1401 struct scsi_cmnd *cmd, int (*do_reset)(struct fc_port *, uint64_t, int))
1da177e4 1402{
e315cd28 1403 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
bdf79621 1404 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
523ec773 1405 int err;
1da177e4 1406
7c3df132 1407 if (!fcport) {
523ec773 1408 return FAILED;
7c3df132 1409 }
1da177e4 1410
4e98d3b8
AV		 1411 err = fc_block_scsi_eh(cmd);
1412 if (err != 0)
1413 return err;
1414
7c3df132 1415 ql_log(ql_log_info, vha, 0x8009,
9cb78c16 1416 "%s RESET ISSUED nexus=%ld:%d:%llu cmd=%p.\n", name, vha->host_no,
7c3df132 1417 cmd->device->id, cmd->device->lun, cmd);
1da177e4 1418
523ec773 1419 err = 0;
7c3df132
SK		 1420 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1421 ql_log(ql_log_warn, vha, 0x800a,
1422 "Wait for hba online failed for cmd=%p.\n", cmd);
523ec773 1423 goto eh_reset_failed;
7c3df132 1424 }
523ec773 1425 err = 2;
2afa19a9 1426 if (do_reset(fcport, cmd->device->lun, cmd->request->cpu + 1)
7c3df132
SK		 1427 != QLA_SUCCESS) {
1428 ql_log(ql_log_warn, vha, 0x800c,
1429 "do_reset failed for cmd=%p.\n", cmd);
523ec773 1430 goto eh_reset_failed;
7c3df132 1431 }
523ec773 1432 err = 3;
e315cd28 1433 if (qla2x00_eh_wait_for_pending_commands(vha, cmd->device->id,
7c3df132
SK		 1434 cmd->device->lun, type) != QLA_SUCCESS) {
1435 ql_log(ql_log_warn, vha, 0x800d,
d6a03581 1436 "wait for pending cmds failed for cmd=%p.\n", cmd);
523ec773 1437 goto eh_reset_failed;
7c3df132 1438 }
523ec773 1439
7c3df132 1440 ql_log(ql_log_info, vha, 0x800e,
9cb78c16 1441 "%s RESET SUCCEEDED nexus:%ld:%d:%llu cmd=%p.\n", name,
cfb0919c 1442 vha->host_no, cmd->device->id, cmd->device->lun, cmd);
523ec773
AV		 1443
1444 return SUCCESS;
1445
4d78c973 1446eh_reset_failed:
7c3df132 1447 ql_log(ql_log_info, vha, 0x800f,
9cb78c16 1448 "%s RESET FAILED: %s nexus=%ld:%d:%llu cmd=%p.\n", name,
cfb0919c
CD		 1449 reset_errors[err], vha->host_no, cmd->device->id, cmd->device->lun,
1450 cmd);
523ec773
AV		 1451 return FAILED;
1452}
1da177e4 1453
523ec773
AV		 1454static int
1455qla2xxx_eh_device_reset(struct scsi_cmnd *cmd)
1456{
e315cd28
AC		 1457 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1458 struct qla_hw_data *ha = vha->hw;
1da177e4 1459
a465537a
SC		 1460 if (qla2x00_isp_reg_stat(ha)) {
1461 ql_log(ql_log_info, vha, 0x803e,
1462 "PCI/Register disconnect, exiting.\n");
1463 return FAILED;
1464 }
1465
523ec773
AV		 1466 return __qla2xxx_eh_generic_reset("DEVICE", WAIT_LUN, cmd,
1467 ha->isp_ops->lun_reset);
1da177e4
LT		 1468}
1469
1da177e4 1470static int
523ec773 1471qla2xxx_eh_target_reset(struct scsi_cmnd *cmd)
1da177e4 1472{
e315cd28
AC		 1473 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1474 struct qla_hw_data *ha = vha->hw;
1da177e4 1475
a465537a
SC		 1476 if (qla2x00_isp_reg_stat(ha)) {
1477 ql_log(ql_log_info, vha, 0x803f,
1478 "PCI/Register disconnect, exiting.\n");
1479 return FAILED;
1480 }
1481
523ec773
AV		 1482 return __qla2xxx_eh_generic_reset("TARGET", WAIT_TARGET, cmd,
1483 ha->isp_ops->target_reset);
1da177e4
LT		 1484}
1485
1da177e4
LT		 1486/**************************************************************************
1487* qla2xxx_eh_bus_reset
1488*
1489* Description:
1490* The bus reset function will reset the bus and abort any executing
1491* commands.
1492*
1493* Input:
1494* cmd = Linux SCSI command packet of the command that cause the
1495* bus reset.
1496*
1497* Returns:
1498* SUCCESS/FAILURE (defined as macro in scsi.h).
1499*
1500**************************************************************************/
e5f82ab8 1501static int
1da177e4
LT		 1502qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd)
1503{
e315cd28 1504 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
bdf79621 1505 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
2c3dfe3f 1506 int ret = FAILED;
9cb78c16
HR		 1507 unsigned int id;
1508 uint64_t lun;
a465537a
SC		 1509 struct qla_hw_data *ha = vha->hw;
1510
1511 if (qla2x00_isp_reg_stat(ha)) {
1512 ql_log(ql_log_info, vha, 0x8040,
1513 "PCI/Register disconnect, exiting.\n");
1514 return FAILED;
1515 }
f4f051eb 1516
f4f051eb 1517 id = cmd->device->id;
1518 lun = cmd->device->lun;
1da177e4 1519
7c3df132 1520 if (!fcport) {
f4f051eb 1521 return ret;
7c3df132 1522 }
1da177e4 1523
4e98d3b8
AV		 1524 ret = fc_block_scsi_eh(cmd);
1525 if (ret != 0)
1526 return ret;
1527 ret = FAILED;
1528
7c3df132 1529 ql_log(ql_log_info, vha, 0x8012,
9cb78c16 1530 "BUS RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun);
1da177e4 1531
e315cd28 1532 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
7c3df132
SK		 1533 ql_log(ql_log_fatal, vha, 0x8013,
1534 "Wait for hba online failed board disabled.\n");
f4f051eb 1535 goto eh_bus_reset_done;
1da177e4
LT		 1536 }
1537
ad537689
SK		 1538 if (qla2x00_loop_reset(vha) == QLA_SUCCESS)
1539 ret = SUCCESS;
1540
f4f051eb 1541 if (ret == FAILED)
1542 goto eh_bus_reset_done;
1da177e4 1543
9a41a62b 1544 /* Flush outstanding commands. */
4d78c973 1545 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) !=
7c3df132
SK		 1546 QLA_SUCCESS) {
1547 ql_log(ql_log_warn, vha, 0x8014,
1548 "Wait for pending commands failed.\n");
9a41a62b 1549 ret = FAILED;
7c3df132 1550 }
1da177e4 1551
f4f051eb 1552eh_bus_reset_done:
7c3df132 1553 ql_log(ql_log_warn, vha, 0x802b,
9cb78c16 1554 "BUS RESET %s nexus=%ld:%d:%llu.\n",
d6a03581 1555 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1da177e4 1556
f4f051eb 1557 return ret;
1da177e4
LT		 1558}
1559
1560/**************************************************************************
1561* qla2xxx_eh_host_reset
1562*
1563* Description:
1564* The reset function will reset the Adapter.
1565*
1566* Input:
1567* cmd = Linux SCSI command packet of the command that cause the
1568* adapter reset.
1569*
1570* Returns:
1571* Either SUCCESS or FAILED.
1572*
1573* Note:
1574**************************************************************************/
e5f82ab8 1575static int
1da177e4
LT		 1576qla2xxx_eh_host_reset(struct scsi_cmnd *cmd)
1577{
e315cd28 1578 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
e315cd28 1579 struct qla_hw_data *ha = vha->hw;
2c3dfe3f 1580 int ret = FAILED;
9cb78c16
HR		 1581 unsigned int id;
1582 uint64_t lun;
e315cd28 1583 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4 1584
a465537a
SC		 1585 if (qla2x00_isp_reg_stat(ha)) {
1586 ql_log(ql_log_info, vha, 0x8041,
1587 "PCI/Register disconnect, exiting.\n");
1588 schedule_work(&ha->board_disable);
1589 return SUCCESS;
1590 }
1591
f4f051eb 1592 id = cmd->device->id;
1593 lun = cmd->device->lun;
f4f051eb 1594
7c3df132 1595 ql_log(ql_log_info, vha, 0x8018,
9cb78c16 1596 "ADAPTER RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun);
1da177e4 1597
63ee7072
CD		 1598 /*
1599 * No point in issuing another reset if one is active. Also do not
1600 * attempt a reset if we are updating flash.
1601 */
1602 if (qla2x00_reset_active(vha) || ha->optrom_state != QLA_SWAITING)
f4f051eb 1603 goto eh_host_reset_lock;
1da177e4 1604
e315cd28
AC		 1605 if (vha != base_vha) {
1606 if (qla2x00_vp_abort_isp(vha))
f4f051eb 1607 goto eh_host_reset_lock;
e315cd28 1608 } else {
7ec0effd 1609 if (IS_P3P_TYPE(vha->hw)) {
a9083016
GM		 1610 if (!qla82xx_fcoe_ctx_reset(vha)) {
1611 /* Ctx reset success */
1612 ret = SUCCESS;
1613 goto eh_host_reset_lock;
1614 }
1615 /* fall thru if ctx reset failed */
1616 }
68ca949c
AC		 1617 if (ha->wq)
1618 flush_workqueue(ha->wq);
1619
e315cd28 1620 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
a9083016 1621 if (ha->isp_ops->abort_isp(base_vha)) {
e315cd28
AC		 1622 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1623 /* failed. schedule dpc to try */
1624 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
1625
7c3df132
SK		 1626 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1627 ql_log(ql_log_warn, vha, 0x802a,
1628 "wait for hba online failed.\n");
e315cd28 1629 goto eh_host_reset_lock;
7c3df132 1630 }
e315cd28
AC		 1631 }
1632 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
fa2a1ce5 1633 }
1da177e4 1634
e315cd28 1635 /* Waiting for command to be returned to OS.*/
4d78c973 1636 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) ==
e315cd28 1637 QLA_SUCCESS)
f4f051eb 1638 ret = SUCCESS;
1da177e4 1639
f4f051eb 1640eh_host_reset_lock:
cfb0919c 1641 ql_log(ql_log_info, vha, 0x8017,
9cb78c16 1642 "ADAPTER RESET %s nexus=%ld:%d:%llu.\n",
cfb0919c 1643 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1da177e4 1644
f4f051eb 1645 return ret;
1646}
1da177e4
LT		 1647
1648/*
1649* qla2x00_loop_reset
1650* Issue loop reset.
1651*
1652* Input:
1653* ha = adapter block pointer.
1654*
1655* Returns:
1656* 0 = success
1657*/
a4722cf2 1658int
e315cd28 1659qla2x00_loop_reset(scsi_qla_host_t *vha)
1da177e4 1660{
0c8c39af 1661 int ret;
bdf79621 1662 struct fc_port *fcport;
e315cd28 1663 struct qla_hw_data *ha = vha->hw;
1da177e4 1664
5854771e
AB		 1665 if (IS_QLAFX00(ha)) {
1666 return qlafx00_loop_reset(vha);
1667 }
1668
f4c496c1 1669 if (ql2xtargetreset == 1 && ha->flags.enable_target_reset) {
55e5ed27
AV		 1670 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1671 if (fcport->port_type != FCT_TARGET)
1672 continue;
1673
1674 ret = ha->isp_ops->target_reset(fcport, 0, 0);
1675 if (ret != QLA_SUCCESS) {
7c3df132 1676 ql_dbg(ql_dbg_taskm, vha, 0x802c,
5854771e 1677 "Bus Reset failed: Reset=%d "
7c3df132 1678 "d_id=%x.\n", ret, fcport->d_id.b24);
55e5ed27
AV		 1679 }
1680 }
1681 }
1682
8ae6d9c7 1683
6246b8a1 1684 if (ha->flags.enable_lip_full_login && !IS_CNA_CAPABLE(ha)) {
0b7e7c53
AV		 1685 atomic_set(&vha->loop_state, LOOP_DOWN);
1686 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
1687 qla2x00_mark_all_devices_lost(vha, 0);
e315cd28 1688 ret = qla2x00_full_login_lip(vha);
0c8c39af 1689 if (ret != QLA_SUCCESS) {
7c3df132
SK		 1690 ql_dbg(ql_dbg_taskm, vha, 0x802d,
1691 "full_login_lip=%d.\n", ret);
749af3d5 1692 }
0c8c39af
AV		 1693 }
1694
0d6e61bc 1695 if (ha->flags.enable_lip_reset) {
e315cd28 1696 ret = qla2x00_lip_reset(vha);
ad537689 1697 if (ret != QLA_SUCCESS)
7c3df132
SK		 1698 ql_dbg(ql_dbg_taskm, vha, 0x802e,
1699 "lip_reset failed (%d).\n", ret);
1da177e4
LT		 1700 }
1701
1da177e4 1702 /* Issue marker command only when we are going to start the I/O */
e315cd28 1703 vha->marker_needed = 1;
1da177e4 1704
0c8c39af 1705 return QLA_SUCCESS;
1da177e4
LT		 1706}
1707
df4bf0bb 1708void
e315cd28 1709qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res)
df4bf0bb 1710{
4cd3b6eb 1711 int que, cnt, status;
df4bf0bb
AV		 1712 unsigned long flags;
1713 srb_t *sp;
e315cd28 1714 struct qla_hw_data *ha = vha->hw;
73208dfd 1715 struct req_que *req;
c5419e26
QT		 1716 struct qla_tgt *tgt = vha->vha_tgt.qla_tgt;
1717 struct qla_tgt_cmd *cmd;
1718 uint8_t trace = 0;
c0cb4496 1719
df4bf0bb 1720 spin_lock_irqsave(&ha->hardware_lock, flags);
2afa19a9 1721 for (que = 0; que < ha->max_req_queues; que++) {
29bdccbe 1722 req = ha->req_q_map[que];
73208dfd
AC		 1723 if (!req)
1724 continue;
8d93f550
CD		 1725 if (!req->outstanding_cmds)
1726 continue;
1727 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) {
73208dfd 1728 sp = req->outstanding_cmds[cnt];
e612d465 1729 if (sp) {
c5419e26
QT		 1730 req->outstanding_cmds[cnt] = NULL;
1731 if (sp->cmd_type == TYPE_SRB) {
6fcd98fd 1732 if (sp->type == SRB_NVME_CMD ||
1733 sp->type == SRB_NVME_LS) {
e84067d7
DG		 1734 sp_get(sp);
1735 spin_unlock_irqrestore(
1736 &ha->hardware_lock, flags);
1737 qla_nvme_abort(ha, sp);
1738 spin_lock_irqsave(
1739 &ha->hardware_lock, flags);
1740 } else if (GET_CMD_SP(sp) &&
c5419e26 1741 !ha->flags.eeh_busy &&
d61cca60
SC		 1742 (!test_bit(ABORT_ISP_ACTIVE,
1743 &vha->dpc_flags)) &&
c5419e26
QT		 1744 (sp->type == SRB_SCSI_CMD)) {
1745 /*
e84067d7
DG		 1746 * Don't abort commands in
1747 * adapter during EEH
1748 * recovery as it's not
1749 * accessible/responding.
1750 *
c5419e26
QT		 1751 * Get a reference to the sp
1752 * and drop the lock. The
1753 * reference ensures this
1754 * sp->done() call and not the
1755 * call in qla2xxx_eh_abort()
1756 * ends the SCSI command (with
1757 * result 'res').
1758 */
1759 sp_get(sp);
1760 spin_unlock_irqrestore(
1761 &ha->hardware_lock, flags);
1762 status = qla2xxx_eh_abort(
1763 GET_CMD_SP(sp));
1764 spin_lock_irqsave(
1765 &ha->hardware_lock, flags);
1766 /*
1767 * Get rid of extra reference
1768 * if immediate exit from
1769 * ql2xxx_eh_abort
1770 */
1771 if (status == FAILED &&
1772 (qla2x00_isp_reg_stat(ha)))
1773 atomic_dec(
1774 &sp->ref_count);
1775 }
1776 sp->done(sp, res);
1777 } else {
1778 if (!vha->hw->tgt.tgt_ops || !tgt ||
1779 qla_ini_mode_enabled(vha)) {
1780 if (!trace)
1781 ql_dbg(ql_dbg_tgt_mgt,
1782 vha, 0xf003,
1783 "HOST-ABORT-HNDLR: dpc_flags=%lx. Target mode disabled\n",
1784 vha->dpc_flags);
1785 continue;
1786 }
1787 cmd = (struct qla_tgt_cmd *)sp;
1788 qlt_abort_cmd_on_host_reset(cmd->vha,
1789 cmd);
c733ab35 1790 }
73208dfd 1791 }
df4bf0bb
AV		 1792 }
1793 }
1794 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1795}
1796
f4f051eb 1797static int
1798qla2xxx_slave_alloc(struct scsi_device *sdev)
1da177e4 1799{
bdf79621 1800 struct fc_rport *rport = starget_to_rport(scsi_target(sdev));
1da177e4 1801
19a7b4ae 1802 if (!rport || fc_remote_port_chkready(rport))
f4f051eb 1803 return -ENXIO;
bdf79621 1804
19a7b4ae 1805 sdev->hostdata = *(fc_port_t **)rport->dd_data;
1da177e4 1806
f4f051eb 1807 return 0;
1808}
1da177e4 1809
f4f051eb 1810static int
1811qla2xxx_slave_configure(struct scsi_device *sdev)
1812{
e315cd28 1813 scsi_qla_host_t *vha = shost_priv(sdev->host);
2afa19a9 1814 struct req_que *req = vha->req;
8482e118 1815
9e522cd8
AE		 1816 if (IS_T10_PI_CAPABLE(vha->hw))
1817 blk_queue_update_dma_alignment(sdev->request_queue, 0x7);
1818
db5ed4df 1819 scsi_change_queue_depth(sdev, req->max_q_depth);
f4f051eb 1820 return 0;
1821}
1da177e4 1822
f4f051eb 1823static void
1824qla2xxx_slave_destroy(struct scsi_device *sdev)
1825{
1826 sdev->hostdata = NULL;
1da177e4
LT		 1827}
1828
1829/**
1830 * qla2x00_config_dma_addressing() - Configure OS DMA addressing method.
1831 * @ha: HA context
1832 *
1833 * At exit, the @ha's flags.enable_64bit_addressing set to indicated
1834 * supported addressing method.
1835 */
1836static void
53303c42 1837qla2x00_config_dma_addressing(struct qla_hw_data *ha)
1da177e4 1838{
7524f9b9 1839 /* Assume a 32bit DMA mask. */
1da177e4 1840 ha->flags.enable_64bit_addressing = 0;
1da177e4 1841
6a35528a 1842 if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) {
7524f9b9
AV		 1843 /* Any upper-dword bits set? */
1844 if (MSD(dma_get_required_mask(&ha->pdev->dev)) &&
6a35528a 1845 !pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(64))) {
7524f9b9 1846 /* Ok, a 64bit DMA mask is applicable. */
1da177e4 1847 ha->flags.enable_64bit_addressing = 1;
fd34f556
AV		 1848 ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64;
1849 ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64;
7524f9b9 1850 return;
1da177e4 1851 }
1da177e4 1852 }
7524f9b9 1853
284901a9
YH		 1854 dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32));
1855 pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(32));
1da177e4
LT		 1856}
1857
fd34f556 1858static void
e315cd28 1859qla2x00_enable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1860{
1861 unsigned long flags = 0;
1862 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1863
1864 spin_lock_irqsave(&ha->hardware_lock, flags);
1865 ha->interrupts_on = 1;
1866 /* enable risc and host interrupts */
1867 WRT_REG_WORD(&reg->ictrl, ICR_EN_INT | ICR_EN_RISC);
1868 RD_REG_WORD(&reg->ictrl);
1869 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1870
1871}
1872
1873static void
e315cd28 1874qla2x00_disable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1875{
1876 unsigned long flags = 0;
1877 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1878
1879 spin_lock_irqsave(&ha->hardware_lock, flags);
1880 ha->interrupts_on = 0;
1881 /* disable risc and host interrupts */
1882 WRT_REG_WORD(&reg->ictrl, 0);
1883 RD_REG_WORD(&reg->ictrl);
1884 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1885}
1886
1887static void
e315cd28 1888qla24xx_enable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1889{
1890 unsigned long flags = 0;
1891 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1892
1893 spin_lock_irqsave(&ha->hardware_lock, flags);
1894 ha->interrupts_on = 1;
1895 WRT_REG_DWORD(&reg->ictrl, ICRX_EN_RISC_INT);
1896 RD_REG_DWORD(&reg->ictrl);
1897 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1898}
1899
1900static void
e315cd28 1901qla24xx_disable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1902{
1903 unsigned long flags = 0;
1904 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1905
124f85e6
AV		 1906 if (IS_NOPOLLING_TYPE(ha))
1907 return;
fd34f556
AV		 1908 spin_lock_irqsave(&ha->hardware_lock, flags);
1909 ha->interrupts_on = 0;
1910 WRT_REG_DWORD(&reg->ictrl, 0);
1911 RD_REG_DWORD(&reg->ictrl);
1912 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1913}
1914
706f457d
GM		 1915static int
1916qla2x00_iospace_config(struct qla_hw_data *ha)
1917{
1918 resource_size_t pio;
1919 uint16_t msix;
706f457d 1920
706f457d
GM		 1921 if (pci_request_selected_regions(ha->pdev, ha->bars,
1922 QLA2XXX_DRIVER_NAME)) {
1923 ql_log_pci(ql_log_fatal, ha->pdev, 0x0011,
1924 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
1925 pci_name(ha->pdev));
1926 goto iospace_error_exit;
1927 }
1928 if (!(ha->bars & 1))
1929 goto skip_pio;
1930
1931 /* We only need PIO for Flash operations on ISP2312 v2 chips. */
1932 pio = pci_resource_start(ha->pdev, 0);
1933 if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) {
1934 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
1935 ql_log_pci(ql_log_warn, ha->pdev, 0x0012,
1936 "Invalid pci I/O region size (%s).\n",
1937 pci_name(ha->pdev));
1938 pio = 0;
1939 }
1940 } else {
1941 ql_log_pci(ql_log_warn, ha->pdev, 0x0013,
1942 "Region #0 no a PIO resource (%s).\n",
1943 pci_name(ha->pdev));
1944 pio = 0;
1945 }
1946 ha->pio_address = pio;
1947 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014,
1948 "PIO address=%llu.\n",
1949 (unsigned long long)ha->pio_address);
1950
1951skip_pio:
1952 /* Use MMIO operations for all accesses. */
1953 if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) {
1954 ql_log_pci(ql_log_fatal, ha->pdev, 0x0015,
1955 "Region #1 not an MMIO resource (%s), aborting.\n",
1956 pci_name(ha->pdev));
1957 goto iospace_error_exit;
1958 }
1959 if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) {
1960 ql_log_pci(ql_log_fatal, ha->pdev, 0x0016,
1961 "Invalid PCI mem region size (%s), aborting.\n",
1962 pci_name(ha->pdev));
1963 goto iospace_error_exit;
1964 }
1965
1966 ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN);
1967 if (!ha->iobase) {
1968 ql_log_pci(ql_log_fatal, ha->pdev, 0x0017,
1969 "Cannot remap MMIO (%s), aborting.\n",
1970 pci_name(ha->pdev));
1971 goto iospace_error_exit;
1972 }
1973
1974 /* Determine queue resources */
1975 ha->max_req_queues = ha->max_rsp_queues = 1;
f54f2cb5 1976 ha->msix_count = QLA_BASE_VECTORS;
c38d1baf
HM		 1977 if (!ql2xmqsupport || !ql2xnvmeenable ||
1978 (!IS_QLA25XX(ha) && !IS_QLA81XX(ha)))
706f457d
GM		 1979 goto mqiobase_exit;
1980
1981 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3),
1982 pci_resource_len(ha->pdev, 3));
1983 if (ha->mqiobase) {
1984 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018,
1985 "MQIO Base=%p.\n", ha->mqiobase);
1986 /* Read MSIX vector size of the board */
1987 pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix);
d7459527 1988 ha->msix_count = msix + 1;
706f457d 1989 /* Max queues are bounded by available msix vectors */
d7459527
MH		 1990 /* MB interrupt uses 1 vector */
1991 ha->max_req_queues = ha->msix_count - 1;
1992 ha->max_rsp_queues = ha->max_req_queues;
1993 /* Queue pairs is the max value minus the base queue pair */
1994 ha->max_qpairs = ha->max_rsp_queues - 1;
1995 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0188,
1996 "Max no of queues pairs: %d.\n", ha->max_qpairs);
1997
706f457d 1998 ql_log_pci(ql_log_info, ha->pdev, 0x001a,
d7459527 1999 "MSI-X vector count: %d.\n", ha->msix_count);
706f457d
GM		 2000 } else
2001 ql_log_pci(ql_log_info, ha->pdev, 0x001b,
2002 "BAR 3 not enabled.\n");
2003
2004mqiobase_exit:
706f457d 2005 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c,
f54f2cb5 2006 "MSIX Count: %d.\n", ha->msix_count);
706f457d
GM		 2007 return (0);
2008
2009iospace_error_exit:
2010 return (-ENOMEM);
2011}
2012
2013
6246b8a1
GM		 2014static int
2015qla83xx_iospace_config(struct qla_hw_data *ha)
2016{
2017 uint16_t msix;
6246b8a1
GM		 2018
2019 if (pci_request_selected_regions(ha->pdev, ha->bars,
2020 QLA2XXX_DRIVER_NAME)) {
2021 ql_log_pci(ql_log_fatal, ha->pdev, 0x0117,
2022 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
2023 pci_name(ha->pdev));
2024
2025 goto iospace_error_exit;
2026 }
2027
2028 /* Use MMIO operations for all accesses. */
2029 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) {
2030 ql_log_pci(ql_log_warn, ha->pdev, 0x0118,
2031 "Invalid pci I/O region size (%s).\n",
2032 pci_name(ha->pdev));
2033 goto iospace_error_exit;
2034 }
2035 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
2036 ql_log_pci(ql_log_warn, ha->pdev, 0x0119,
2037 "Invalid PCI mem region size (%s), aborting\n",
2038 pci_name(ha->pdev));
2039 goto iospace_error_exit;
2040 }
2041
2042 ha->iobase = ioremap(pci_resource_start(ha->pdev, 0), MIN_IOBASE_LEN);
2043 if (!ha->iobase) {
2044 ql_log_pci(ql_log_fatal, ha->pdev, 0x011a,
2045 "Cannot remap MMIO (%s), aborting.\n",
2046 pci_name(ha->pdev));
2047 goto iospace_error_exit;
2048 }
2049
2050 /* 64bit PCI BAR - BAR2 will correspoond to region 4 */
2051 /* 83XX 26XX always use MQ type access for queues
2052 * - mbar 2, a.k.a region 4 */
2053 ha->max_req_queues = ha->max_rsp_queues = 1;
f54f2cb5 2054 ha->msix_count = QLA_BASE_VECTORS;
6246b8a1
GM		 2055 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 4),
2056 pci_resource_len(ha->pdev, 4));
2057
2058 if (!ha->mqiobase) {
2059 ql_log_pci(ql_log_fatal, ha->pdev, 0x011d,
2060 "BAR2/region4 not enabled\n");
2061 goto mqiobase_exit;
2062 }
2063
2064 ha->msixbase = ioremap(pci_resource_start(ha->pdev, 2),
2065 pci_resource_len(ha->pdev, 2));
2066 if (ha->msixbase) {
2067 /* Read MSIX vector size of the board */
2068 pci_read_config_word(ha->pdev,
2069 QLA_83XX_PCI_MSIX_CONTROL, &msix);
e326d22a 2070 ha->msix_count = (msix & PCI_MSIX_FLAGS_QSIZE) + 1;
093df737
QT		 2071 /*
2072 * By default, driver uses at least two msix vectors
2073 * (default & rspq)
2074 */
c38d1baf 2075 if (ql2xmqsupport || ql2xnvmeenable) {
d7459527
MH		 2076 /* MB interrupt uses 1 vector */
2077 ha->max_req_queues = ha->msix_count - 1;
093df737
QT		 2078
2079 /* ATIOQ needs 1 vector. That's 1 less QPair */
2080 if (QLA_TGT_MODE_ENABLED())
2081 ha->max_req_queues--;
2082
d0d2c68b
MH		 2083 ha->max_rsp_queues = ha->max_req_queues;
2084
d7459527
MH		 2085 /* Queue pairs is the max value minus
2086 * the base queue pair */
2087 ha->max_qpairs = ha->max_req_queues - 1;
83548fe2 2088 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x00e3,
d7459527 2089 "Max no of queues pairs: %d.\n", ha->max_qpairs);
6246b8a1
GM		 2090 }
2091 ql_log_pci(ql_log_info, ha->pdev, 0x011c,
d7459527 2092 "MSI-X vector count: %d.\n", ha->msix_count);
6246b8a1
GM		 2093 } else
2094 ql_log_pci(ql_log_info, ha->pdev, 0x011e,
2095 "BAR 1 not enabled.\n");
2096
2097mqiobase_exit:
6246b8a1 2098 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011f,
f54f2cb5 2099 "MSIX Count: %d.\n", ha->msix_count);
6246b8a1
GM		 2100 return 0;
2101
2102iospace_error_exit:
2103 return -ENOMEM;
2104}
2105
fd34f556
AV		 2106static struct isp_operations qla2100_isp_ops = {
2107 .pci_config = qla2100_pci_config,
2108 .reset_chip = qla2x00_reset_chip,
2109 .chip_diag = qla2x00_chip_diag,
2110 .config_rings = qla2x00_config_rings,
2111 .reset_adapter = qla2x00_reset_adapter,
2112 .nvram_config = qla2x00_nvram_config,
2113 .update_fw_options = qla2x00_update_fw_options,
2114 .load_risc = qla2x00_load_risc,
2115 .pci_info_str = qla2x00_pci_info_str,
2116 .fw_version_str = qla2x00_fw_version_str,
2117 .intr_handler = qla2100_intr_handler,
2118 .enable_intrs = qla2x00_enable_intrs,
2119 .disable_intrs = qla2x00_disable_intrs,
2120 .abort_command = qla2x00_abort_command,
523ec773
AV		 2121 .target_reset = qla2x00_abort_target,
2122 .lun_reset = qla2x00_lun_reset,
fd34f556
AV		 2123 .fabric_login = qla2x00_login_fabric,
2124 .fabric_logout = qla2x00_fabric_logout,
2125 .calc_req_entries = qla2x00_calc_iocbs_32,
2126 .build_iocbs = qla2x00_build_scsi_iocbs_32,
2127 .prep_ms_iocb = qla2x00_prep_ms_iocb,
2128 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
2129 .read_nvram = qla2x00_read_nvram_data,
2130 .write_nvram = qla2x00_write_nvram_data,
2131 .fw_dump = qla2100_fw_dump,
2132 .beacon_on = NULL,
2133 .beacon_off = NULL,
2134 .beacon_blink = NULL,
2135 .read_optrom = qla2x00_read_optrom_data,
2136 .write_optrom = qla2x00_write_optrom_data,
2137 .get_flash_version = qla2x00_get_flash_version,
e315cd28 2138 .start_scsi = qla2x00_start_scsi,
d7459527 2139 .start_scsi_mq = NULL,
a9083016 2140 .abort_isp = qla2x00_abort_isp,
706f457d 2141 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2142 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 2143};
2144
2145static struct isp_operations qla2300_isp_ops = {
2146 .pci_config = qla2300_pci_config,
2147 .reset_chip = qla2x00_reset_chip,
2148 .chip_diag = qla2x00_chip_diag,
2149 .config_rings = qla2x00_config_rings,
2150 .reset_adapter = qla2x00_reset_adapter,
2151 .nvram_config = qla2x00_nvram_config,
2152 .update_fw_options = qla2x00_update_fw_options,
2153 .load_risc = qla2x00_load_risc,
2154 .pci_info_str = qla2x00_pci_info_str,
2155 .fw_version_str = qla2x00_fw_version_str,
2156 .intr_handler = qla2300_intr_handler,
2157 .enable_intrs = qla2x00_enable_intrs,
2158 .disable_intrs = qla2x00_disable_intrs,
2159 .abort_command = qla2x00_abort_command,
523ec773
AV		 2160 .target_reset = qla2x00_abort_target,
2161 .lun_reset = qla2x00_lun_reset,
fd34f556
AV		 2162 .fabric_login = qla2x00_login_fabric,
2163 .fabric_logout = qla2x00_fabric_logout,
2164 .calc_req_entries = qla2x00_calc_iocbs_32,
2165 .build_iocbs = qla2x00_build_scsi_iocbs_32,
2166 .prep_ms_iocb = qla2x00_prep_ms_iocb,
2167 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
2168 .read_nvram = qla2x00_read_nvram_data,
2169 .write_nvram = qla2x00_write_nvram_data,
2170 .fw_dump = qla2300_fw_dump,
2171 .beacon_on = qla2x00_beacon_on,
2172 .beacon_off = qla2x00_beacon_off,
2173 .beacon_blink = qla2x00_beacon_blink,
2174 .read_optrom = qla2x00_read_optrom_data,
2175 .write_optrom = qla2x00_write_optrom_data,
2176 .get_flash_version = qla2x00_get_flash_version,
e315cd28 2177 .start_scsi = qla2x00_start_scsi,
d7459527 2178 .start_scsi_mq = NULL,
a9083016 2179 .abort_isp = qla2x00_abort_isp,
7ec0effd 2180 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2181 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 2182};
2183
2184static struct isp_operations qla24xx_isp_ops = {
2185 .pci_config = qla24xx_pci_config,
2186 .reset_chip = qla24xx_reset_chip,
2187 .chip_diag = qla24xx_chip_diag,
2188 .config_rings = qla24xx_config_rings,
2189 .reset_adapter = qla24xx_reset_adapter,
2190 .nvram_config = qla24xx_nvram_config,
2191 .update_fw_options = qla24xx_update_fw_options,
2192 .load_risc = qla24xx_load_risc,
2193 .pci_info_str = qla24xx_pci_info_str,
2194 .fw_version_str = qla24xx_fw_version_str,
2195 .intr_handler = qla24xx_intr_handler,
2196 .enable_intrs = qla24xx_enable_intrs,
2197 .disable_intrs = qla24xx_disable_intrs,
2198 .abort_command = qla24xx_abort_command,
523ec773
AV		 2199 .target_reset = qla24xx_abort_target,
2200 .lun_reset = qla24xx_lun_reset,
fd34f556
AV		 2201 .fabric_login = qla24xx_login_fabric,
2202 .fabric_logout = qla24xx_fabric_logout,
2203 .calc_req_entries = NULL,
2204 .build_iocbs = NULL,
2205 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2206 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2207 .read_nvram = qla24xx_read_nvram_data,
2208 .write_nvram = qla24xx_write_nvram_data,
2209 .fw_dump = qla24xx_fw_dump,
2210 .beacon_on = qla24xx_beacon_on,
2211 .beacon_off = qla24xx_beacon_off,
2212 .beacon_blink = qla24xx_beacon_blink,
2213 .read_optrom = qla24xx_read_optrom_data,
2214 .write_optrom = qla24xx_write_optrom_data,
2215 .get_flash_version = qla24xx_get_flash_version,
e315cd28 2216 .start_scsi = qla24xx_start_scsi,
d7459527 2217 .start_scsi_mq = NULL,
a9083016 2218 .abort_isp = qla2x00_abort_isp,
7ec0effd 2219 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2220 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 2221};
2222
c3a2f0df
AV		 2223static struct isp_operations qla25xx_isp_ops = {
2224 .pci_config = qla25xx_pci_config,
2225 .reset_chip = qla24xx_reset_chip,
2226 .chip_diag = qla24xx_chip_diag,
2227 .config_rings = qla24xx_config_rings,
2228 .reset_adapter = qla24xx_reset_adapter,
2229 .nvram_config = qla24xx_nvram_config,
2230 .update_fw_options = qla24xx_update_fw_options,
2231 .load_risc = qla24xx_load_risc,
2232 .pci_info_str = qla24xx_pci_info_str,
2233 .fw_version_str = qla24xx_fw_version_str,
2234 .intr_handler = qla24xx_intr_handler,
2235 .enable_intrs = qla24xx_enable_intrs,
2236 .disable_intrs = qla24xx_disable_intrs,
2237 .abort_command = qla24xx_abort_command,
523ec773
AV		 2238 .target_reset = qla24xx_abort_target,
2239 .lun_reset = qla24xx_lun_reset,
c3a2f0df
AV		 2240 .fabric_login = qla24xx_login_fabric,
2241 .fabric_logout = qla24xx_fabric_logout,
2242 .calc_req_entries = NULL,
2243 .build_iocbs = NULL,
2244 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2245 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2246 .read_nvram = qla25xx_read_nvram_data,
2247 .write_nvram = qla25xx_write_nvram_data,
2248 .fw_dump = qla25xx_fw_dump,
2249 .beacon_on = qla24xx_beacon_on,
2250 .beacon_off = qla24xx_beacon_off,
2251 .beacon_blink = qla24xx_beacon_blink,
338c9161 2252 .read_optrom = qla25xx_read_optrom_data,
c3a2f0df
AV		 2253 .write_optrom = qla24xx_write_optrom_data,
2254 .get_flash_version = qla24xx_get_flash_version,
bad75002 2255 .start_scsi = qla24xx_dif_start_scsi,
d7459527 2256 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
a9083016 2257 .abort_isp = qla2x00_abort_isp,
7ec0effd 2258 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2259 .initialize_adapter = qla2x00_initialize_adapter,
c3a2f0df
AV		 2260};
2261
3a03eb79
AV		 2262static struct isp_operations qla81xx_isp_ops = {
2263 .pci_config = qla25xx_pci_config,
2264 .reset_chip = qla24xx_reset_chip,
2265 .chip_diag = qla24xx_chip_diag,
2266 .config_rings = qla24xx_config_rings,
2267 .reset_adapter = qla24xx_reset_adapter,
2268 .nvram_config = qla81xx_nvram_config,
2269 .update_fw_options = qla81xx_update_fw_options,
eaac30be 2270 .load_risc = qla81xx_load_risc,
3a03eb79
AV		 2271 .pci_info_str = qla24xx_pci_info_str,
2272 .fw_version_str = qla24xx_fw_version_str,
2273 .intr_handler = qla24xx_intr_handler,
2274 .enable_intrs = qla24xx_enable_intrs,
2275 .disable_intrs = qla24xx_disable_intrs,
2276 .abort_command = qla24xx_abort_command,
2277 .target_reset = qla24xx_abort_target,
2278 .lun_reset = qla24xx_lun_reset,
2279 .fabric_login = qla24xx_login_fabric,
2280 .fabric_logout = qla24xx_fabric_logout,
2281 .calc_req_entries = NULL,
2282 .build_iocbs = NULL,
2283 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2284 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
3d79038f
AV		 2285 .read_nvram = NULL,
2286 .write_nvram = NULL,
3a03eb79
AV		 2287 .fw_dump = qla81xx_fw_dump,
2288 .beacon_on = qla24xx_beacon_on,
2289 .beacon_off = qla24xx_beacon_off,
6246b8a1 2290 .beacon_blink = qla83xx_beacon_blink,
3a03eb79
AV		 2291 .read_optrom = qla25xx_read_optrom_data,
2292 .write_optrom = qla24xx_write_optrom_data,
2293 .get_flash_version = qla24xx_get_flash_version,
ba77ef53 2294 .start_scsi = qla24xx_dif_start_scsi,
d7459527 2295 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
a9083016 2296 .abort_isp = qla2x00_abort_isp,
7ec0effd 2297 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2298 .initialize_adapter = qla2x00_initialize_adapter,
a9083016
GM		 2299};
2300
2301static struct isp_operations qla82xx_isp_ops = {
2302 .pci_config = qla82xx_pci_config,
2303 .reset_chip = qla82xx_reset_chip,
2304 .chip_diag = qla24xx_chip_diag,
2305 .config_rings = qla82xx_config_rings,
2306 .reset_adapter = qla24xx_reset_adapter,
2307 .nvram_config = qla81xx_nvram_config,
2308 .update_fw_options = qla24xx_update_fw_options,
2309 .load_risc = qla82xx_load_risc,
9d55ca66 2310 .pci_info_str = qla24xx_pci_info_str,
a9083016
GM		 2311 .fw_version_str = qla24xx_fw_version_str,
2312 .intr_handler = qla82xx_intr_handler,
2313 .enable_intrs = qla82xx_enable_intrs,
2314 .disable_intrs = qla82xx_disable_intrs,
2315 .abort_command = qla24xx_abort_command,
2316 .target_reset = qla24xx_abort_target,
2317 .lun_reset = qla24xx_lun_reset,
2318 .fabric_login = qla24xx_login_fabric,
2319 .fabric_logout = qla24xx_fabric_logout,
2320 .calc_req_entries = NULL,
2321 .build_iocbs = NULL,
2322 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2323 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2324 .read_nvram = qla24xx_read_nvram_data,
2325 .write_nvram = qla24xx_write_nvram_data,
a1b23c5a 2326 .fw_dump = qla82xx_fw_dump,
999916dc
SK		 2327 .beacon_on = qla82xx_beacon_on,
2328 .beacon_off = qla82xx_beacon_off,
2329 .beacon_blink = NULL,
a9083016
GM		 2330 .read_optrom = qla82xx_read_optrom_data,
2331 .write_optrom = qla82xx_write_optrom_data,
7ec0effd 2332 .get_flash_version = qla82xx_get_flash_version,
a9083016 2333 .start_scsi = qla82xx_start_scsi,
d7459527 2334 .start_scsi_mq = NULL,
a9083016 2335 .abort_isp = qla82xx_abort_isp,
706f457d 2336 .iospace_config = qla82xx_iospace_config,
8ae6d9c7 2337 .initialize_adapter = qla2x00_initialize_adapter,
3a03eb79
AV		 2338};
2339
7ec0effd
AD		 2340static struct isp_operations qla8044_isp_ops = {
2341 .pci_config = qla82xx_pci_config,
2342 .reset_chip = qla82xx_reset_chip,
2343 .chip_diag = qla24xx_chip_diag,
2344 .config_rings = qla82xx_config_rings,
2345 .reset_adapter = qla24xx_reset_adapter,
2346 .nvram_config = qla81xx_nvram_config,
2347 .update_fw_options = qla24xx_update_fw_options,
2348 .load_risc = qla82xx_load_risc,
2349 .pci_info_str = qla24xx_pci_info_str,
2350 .fw_version_str = qla24xx_fw_version_str,
2351 .intr_handler = qla8044_intr_handler,
2352 .enable_intrs = qla82xx_enable_intrs,
2353 .disable_intrs = qla82xx_disable_intrs,
2354 .abort_command = qla24xx_abort_command,
2355 .target_reset = qla24xx_abort_target,
2356 .lun_reset = qla24xx_lun_reset,
2357 .fabric_login = qla24xx_login_fabric,
2358 .fabric_logout = qla24xx_fabric_logout,
2359 .calc_req_entries = NULL,
2360 .build_iocbs = NULL,
2361 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2362 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2363 .read_nvram = NULL,
2364 .write_nvram = NULL,
a1b23c5a 2365 .fw_dump = qla8044_fw_dump,
7ec0effd
AD		 2366 .beacon_on = qla82xx_beacon_on,
2367 .beacon_off = qla82xx_beacon_off,
2368 .beacon_blink = NULL,
888e639d 2369 .read_optrom = qla8044_read_optrom_data,
7ec0effd
AD		 2370 .write_optrom = qla8044_write_optrom_data,
2371 .get_flash_version = qla82xx_get_flash_version,
2372 .start_scsi = qla82xx_start_scsi,
d7459527 2373 .start_scsi_mq = NULL,
7ec0effd
AD		 2374 .abort_isp = qla8044_abort_isp,
2375 .iospace_config = qla82xx_iospace_config,
2376 .initialize_adapter = qla2x00_initialize_adapter,
2377};
2378
6246b8a1
GM		 2379static struct isp_operations qla83xx_isp_ops = {
2380 .pci_config = qla25xx_pci_config,
2381 .reset_chip = qla24xx_reset_chip,
2382 .chip_diag = qla24xx_chip_diag,
2383 .config_rings = qla24xx_config_rings,
2384 .reset_adapter = qla24xx_reset_adapter,
2385 .nvram_config = qla81xx_nvram_config,
2386 .update_fw_options = qla81xx_update_fw_options,
2387 .load_risc = qla81xx_load_risc,
2388 .pci_info_str = qla24xx_pci_info_str,
2389 .fw_version_str = qla24xx_fw_version_str,
2390 .intr_handler = qla24xx_intr_handler,
2391 .enable_intrs = qla24xx_enable_intrs,
2392 .disable_intrs = qla24xx_disable_intrs,
2393 .abort_command = qla24xx_abort_command,
2394 .target_reset = qla24xx_abort_target,
2395 .lun_reset = qla24xx_lun_reset,
2396 .fabric_login = qla24xx_login_fabric,
2397 .fabric_logout = qla24xx_fabric_logout,
2398 .calc_req_entries = NULL,
2399 .build_iocbs = NULL,
2400 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2401 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2402 .read_nvram = NULL,
2403 .write_nvram = NULL,
2404 .fw_dump = qla83xx_fw_dump,
2405 .beacon_on = qla24xx_beacon_on,
2406 .beacon_off = qla24xx_beacon_off,
2407 .beacon_blink = qla83xx_beacon_blink,
2408 .read_optrom = qla25xx_read_optrom_data,
2409 .write_optrom = qla24xx_write_optrom_data,
2410 .get_flash_version = qla24xx_get_flash_version,
2411 .start_scsi = qla24xx_dif_start_scsi,
d7459527 2412 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
6246b8a1
GM		 2413 .abort_isp = qla2x00_abort_isp,
2414 .iospace_config = qla83xx_iospace_config,
8ae6d9c7
GM		 2415 .initialize_adapter = qla2x00_initialize_adapter,
2416};
2417
2418static struct isp_operations qlafx00_isp_ops = {
2419 .pci_config = qlafx00_pci_config,
2420 .reset_chip = qlafx00_soft_reset,
2421 .chip_diag = qlafx00_chip_diag,
2422 .config_rings = qlafx00_config_rings,
2423 .reset_adapter = qlafx00_soft_reset,
2424 .nvram_config = NULL,
2425 .update_fw_options = NULL,
2426 .load_risc = NULL,
2427 .pci_info_str = qlafx00_pci_info_str,
2428 .fw_version_str = qlafx00_fw_version_str,
2429 .intr_handler = qlafx00_intr_handler,
2430 .enable_intrs = qlafx00_enable_intrs,
2431 .disable_intrs = qlafx00_disable_intrs,
4440e46d 2432 .abort_command = qla24xx_async_abort_command,
8ae6d9c7
GM		 2433 .target_reset = qlafx00_abort_target,
2434 .lun_reset = qlafx00_lun_reset,
2435 .fabric_login = NULL,
2436 .fabric_logout = NULL,
2437 .calc_req_entries = NULL,
2438 .build_iocbs = NULL,
2439 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2440 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2441 .read_nvram = qla24xx_read_nvram_data,
2442 .write_nvram = qla24xx_write_nvram_data,
2443 .fw_dump = NULL,
2444 .beacon_on = qla24xx_beacon_on,
2445 .beacon_off = qla24xx_beacon_off,
2446 .beacon_blink = NULL,
2447 .read_optrom = qla24xx_read_optrom_data,
2448 .write_optrom = qla24xx_write_optrom_data,
2449 .get_flash_version = qla24xx_get_flash_version,
2450 .start_scsi = qlafx00_start_scsi,
d7459527 2451 .start_scsi_mq = NULL,
8ae6d9c7
GM		 2452 .abort_isp = qlafx00_abort_isp,
2453 .iospace_config = qlafx00_iospace_config,
2454 .initialize_adapter = qlafx00_initialize_adapter,
6246b8a1
GM		 2455};
2456
f73cb695
CD		 2457static struct isp_operations qla27xx_isp_ops = {
2458 .pci_config = qla25xx_pci_config,
2459 .reset_chip = qla24xx_reset_chip,
2460 .chip_diag = qla24xx_chip_diag,
2461 .config_rings = qla24xx_config_rings,
2462 .reset_adapter = qla24xx_reset_adapter,
2463 .nvram_config = qla81xx_nvram_config,
2464 .update_fw_options = qla81xx_update_fw_options,
2465 .load_risc = qla81xx_load_risc,
2466 .pci_info_str = qla24xx_pci_info_str,
2467 .fw_version_str = qla24xx_fw_version_str,
2468 .intr_handler = qla24xx_intr_handler,
2469 .enable_intrs = qla24xx_enable_intrs,
2470 .disable_intrs = qla24xx_disable_intrs,
2471 .abort_command = qla24xx_abort_command,
2472 .target_reset = qla24xx_abort_target,
2473 .lun_reset = qla24xx_lun_reset,
2474 .fabric_login = qla24xx_login_fabric,
2475 .fabric_logout = qla24xx_fabric_logout,
2476 .calc_req_entries = NULL,
2477 .build_iocbs = NULL,
2478 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2479 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2480 .read_nvram = NULL,
2481 .write_nvram = NULL,
2482 .fw_dump = qla27xx_fwdump,
2483 .beacon_on = qla24xx_beacon_on,
2484 .beacon_off = qla24xx_beacon_off,
2485 .beacon_blink = qla83xx_beacon_blink,
2486 .read_optrom = qla25xx_read_optrom_data,
2487 .write_optrom = qla24xx_write_optrom_data,
2488 .get_flash_version = qla24xx_get_flash_version,
2489 .start_scsi = qla24xx_dif_start_scsi,
d7459527 2490 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
f73cb695
CD		 2491 .abort_isp = qla2x00_abort_isp,
2492 .iospace_config = qla83xx_iospace_config,
2493 .initialize_adapter = qla2x00_initialize_adapter,
2494};
2495
ea5b6382 2496static inline void
e315cd28 2497qla2x00_set_isp_flags(struct qla_hw_data *ha)
ea5b6382 2498{
2499 ha->device_type = DT_EXTENDED_IDS;
2500 switch (ha->pdev->device) {
2501 case PCI_DEVICE_ID_QLOGIC_ISP2100:
9e052e2d 2502 ha->isp_type |= DT_ISP2100;
ea5b6382 2503 ha->device_type &= ~DT_EXTENDED_IDS;
441d1072 2504 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
ea5b6382 2505 break;
2506 case PCI_DEVICE_ID_QLOGIC_ISP2200:
9e052e2d 2507 ha->isp_type |= DT_ISP2200;
ea5b6382 2508 ha->device_type &= ~DT_EXTENDED_IDS;
441d1072 2509 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
ea5b6382 2510 break;
2511 case PCI_DEVICE_ID_QLOGIC_ISP2300:
9e052e2d 2512 ha->isp_type |= DT_ISP2300;
4a59f71d 2513 ha->device_type |= DT_ZIO_SUPPORTED;
441d1072 2514 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 2515 break;
2516 case PCI_DEVICE_ID_QLOGIC_ISP2312:
9e052e2d 2517 ha->isp_type |= DT_ISP2312;
4a59f71d 2518 ha->device_type |= DT_ZIO_SUPPORTED;
441d1072 2519 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 2520 break;
2521 case PCI_DEVICE_ID_QLOGIC_ISP2322:
9e052e2d 2522 ha->isp_type |= DT_ISP2322;
4a59f71d 2523 ha->device_type |= DT_ZIO_SUPPORTED;
ea5b6382 2524 if (ha->pdev->subsystem_vendor == 0x1028 &&
2525 ha->pdev->subsystem_device == 0x0170)
2526 ha->device_type |= DT_OEM_001;
441d1072 2527 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 2528 break;
2529 case PCI_DEVICE_ID_QLOGIC_ISP6312:
9e052e2d 2530 ha->isp_type |= DT_ISP6312;
441d1072 2531 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 2532 break;
2533 case PCI_DEVICE_ID_QLOGIC_ISP6322:
9e052e2d 2534 ha->isp_type |= DT_ISP6322;
441d1072 2535 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 2536 break;
2537 case PCI_DEVICE_ID_QLOGIC_ISP2422:
9e052e2d 2538 ha->isp_type |= DT_ISP2422;
4a59f71d 2539 ha->device_type |= DT_ZIO_SUPPORTED;
e428924c 2540 ha->device_type |= DT_FWI2;
c76f2c01 2541 ha->device_type |= DT_IIDMA;
441d1072 2542 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2543 break;
2544 case PCI_DEVICE_ID_QLOGIC_ISP2432:
9e052e2d 2545 ha->isp_type |= DT_ISP2432;
4a59f71d 2546 ha->device_type |= DT_ZIO_SUPPORTED;
e428924c 2547 ha->device_type |= DT_FWI2;
c76f2c01 2548 ha->device_type |= DT_IIDMA;
441d1072 2549 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2550 break;
4d4df193 2551 case PCI_DEVICE_ID_QLOGIC_ISP8432:
9e052e2d 2552 ha->isp_type |= DT_ISP8432;
4d4df193
HK		 2553 ha->device_type |= DT_ZIO_SUPPORTED;
2554 ha->device_type |= DT_FWI2;
2555 ha->device_type |= DT_IIDMA;
2556 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2557 break;
044cc6c8 2558 case PCI_DEVICE_ID_QLOGIC_ISP5422:
9e052e2d 2559 ha->isp_type |= DT_ISP5422;
e428924c 2560 ha->device_type |= DT_FWI2;
441d1072 2561 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2562 break;
044cc6c8 2563 case PCI_DEVICE_ID_QLOGIC_ISP5432:
9e052e2d 2564 ha->isp_type |= DT_ISP5432;
e428924c 2565 ha->device_type |= DT_FWI2;
441d1072 2566 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2567 break;
c3a2f0df 2568 case PCI_DEVICE_ID_QLOGIC_ISP2532:
9e052e2d 2569 ha->isp_type |= DT_ISP2532;
c3a2f0df
AV		 2570 ha->device_type |= DT_ZIO_SUPPORTED;
2571 ha->device_type |= DT_FWI2;
2572 ha->device_type |= DT_IIDMA;
441d1072 2573 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2574 break;
3a03eb79 2575 case PCI_DEVICE_ID_QLOGIC_ISP8001:
9e052e2d 2576 ha->isp_type |= DT_ISP8001;
3a03eb79
AV		 2577 ha->device_type |= DT_ZIO_SUPPORTED;
2578 ha->device_type |= DT_FWI2;
2579 ha->device_type |= DT_IIDMA;
2580 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2581 break;
a9083016 2582 case PCI_DEVICE_ID_QLOGIC_ISP8021:
9e052e2d 2583 ha->isp_type |= DT_ISP8021;
a9083016
GM		 2584 ha->device_type |= DT_ZIO_SUPPORTED;
2585 ha->device_type |= DT_FWI2;
2586 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2587 /* Initialize 82XX ISP flags */
2588 qla82xx_init_flags(ha);
2589 break;
7ec0effd 2590 case PCI_DEVICE_ID_QLOGIC_ISP8044:
9e052e2d 2591 ha->isp_type |= DT_ISP8044;
7ec0effd
AD		 2592 ha->device_type |= DT_ZIO_SUPPORTED;
2593 ha->device_type |= DT_FWI2;
2594 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2595 /* Initialize 82XX ISP flags */
2596 qla82xx_init_flags(ha);
2597 break;
6246b8a1 2598 case PCI_DEVICE_ID_QLOGIC_ISP2031:
9e052e2d 2599 ha->isp_type |= DT_ISP2031;
6246b8a1
GM		 2600 ha->device_type |= DT_ZIO_SUPPORTED;
2601 ha->device_type |= DT_FWI2;
2602 ha->device_type |= DT_IIDMA;
2603 ha->device_type |= DT_T10_PI;
2604 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2605 break;
2606 case PCI_DEVICE_ID_QLOGIC_ISP8031:
9e052e2d 2607 ha->isp_type |= DT_ISP8031;
6246b8a1
GM		 2608 ha->device_type |= DT_ZIO_SUPPORTED;
2609 ha->device_type |= DT_FWI2;
2610 ha->device_type |= DT_IIDMA;
2611 ha->device_type |= DT_T10_PI;
2612 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2613 break;
8ae6d9c7 2614 case PCI_DEVICE_ID_QLOGIC_ISPF001:
9e052e2d 2615 ha->isp_type |= DT_ISPFX00;
8ae6d9c7 2616 break;
f73cb695 2617 case PCI_DEVICE_ID_QLOGIC_ISP2071:
9e052e2d 2618 ha->isp_type |= DT_ISP2071;
f73cb695
CD		 2619 ha->device_type |= DT_ZIO_SUPPORTED;
2620 ha->device_type |= DT_FWI2;
2621 ha->device_type |= DT_IIDMA;
8ce3f570 2622 ha->device_type |= DT_T10_PI;
f73cb695
CD		 2623 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2624 break;
2c5bbbb2 2625 case PCI_DEVICE_ID_QLOGIC_ISP2271:
9e052e2d 2626 ha->isp_type |= DT_ISP2271;
2c5bbbb2
JC		 2627 ha->device_type |= DT_ZIO_SUPPORTED;
2628 ha->device_type |= DT_FWI2;
2629 ha->device_type |= DT_IIDMA;
8ce3f570 2630 ha->device_type |= DT_T10_PI;
2c5bbbb2
JC		 2631 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2632 break;
2b48992f 2633 case PCI_DEVICE_ID_QLOGIC_ISP2261:
9e052e2d 2634 ha->isp_type |= DT_ISP2261;
2b48992f
SC		 2635 ha->device_type |= DT_ZIO_SUPPORTED;
2636 ha->device_type |= DT_FWI2;
2637 ha->device_type |= DT_IIDMA;
8ce3f570 2638 ha->device_type |= DT_T10_PI;
2b48992f
SC		 2639 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2640 break;
ea5b6382 2641 }
e5b68a61 2642
a9083016 2643 if (IS_QLA82XX(ha))
43a9c38b 2644 ha->port_no = ha->portnum & 1;
f73cb695 2645 else {
a9083016
GM		 2646 /* Get adapter physical port no from interrupt pin register. */
2647 pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no);
f73cb695
CD		 2648 if (IS_QLA27XX(ha))
2649 ha->port_no--;
2650 else
2651 ha->port_no = !(ha->port_no & 1);
2652 }
a9083016 2653
7c3df132 2654 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b,
d8424f68 2655 "device_type=0x%x port=%d fw_srisc_address=0x%x.\n",
f73cb695 2656 ha->device_type, ha->port_no, ha->fw_srisc_address);
ea5b6382 2657}
2658
1e99e33a
AV		 2659static void
2660qla2xxx_scan_start(struct Scsi_Host *shost)
2661{
e315cd28 2662 scsi_qla_host_t *vha = shost_priv(shost);
1e99e33a 2663
cbc8eb67
AV		 2664 if (vha->hw->flags.running_gold_fw)
2665 return;
2666
e315cd28
AC		 2667 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
2668 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
2669 set_bit(RSCN_UPDATE, &vha->dpc_flags);
2670 set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags);
1e99e33a
AV		 2671}
2672
2673static int
2674qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time)
2675{
e315cd28 2676 scsi_qla_host_t *vha = shost_priv(shost);
1e99e33a 2677
a5dd506e
BK		 2678 if (test_bit(UNLOADING, &vha->dpc_flags))
2679 return 1;
e315cd28 2680 if (!vha->host)
1e99e33a 2681 return 1;
e315cd28 2682 if (time > vha->hw->loop_reset_delay * HZ)
1e99e33a
AV		 2683 return 1;
2684
e315cd28 2685 return atomic_read(&vha->loop_state) == LOOP_READY;
1e99e33a
AV		 2686}
2687
ec7193e2
QT		 2688static void qla2x00_iocb_work_fn(struct work_struct *work)
2689{
2690 struct scsi_qla_host *vha = container_of(work,
2691 struct scsi_qla_host, iocb_work);
2692 int cnt = 0;
2693
2694 while (!list_empty(&vha->work_list)) {
2695 qla2x00_do_work(vha);
2696 cnt++;
2697 if (cnt > 10)
2698 break;
2699 }
2700}
2701
1da177e4
LT		 2702/*
2703 * PCI driver interface
2704 */
6f039790 2705static int
7ee61397 2706qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
1da177e4 2707{
a1541d5a 2708 int ret = -ENODEV;
1da177e4 2709 struct Scsi_Host *host;
e315cd28
AC		 2710 scsi_qla_host_t *base_vha = NULL;
2711 struct qla_hw_data *ha;
29856e28 2712 char pci_info[30];
7d613ac6 2713 char fw_str[30], wq_name[30];
5433383e 2714 struct scsi_host_template *sht;
642ef983 2715 int bars, mem_only = 0;
e315cd28 2716 uint16_t req_length = 0, rsp_length = 0;
73208dfd
AC		 2717 struct req_que *req = NULL;
2718 struct rsp_que *rsp = NULL;
5601236b 2719 int i;
d7459527 2720
285d0321 2721 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO);
a5326f86 2722 sht = &qla2xxx_driver_template;
5433383e 2723 if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 ||
8bc69e7d 2724 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 ||
4d4df193 2725 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 ||
8bc69e7d 2726 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 ||
c3a2f0df 2727 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 ||
3a03eb79 2728 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 ||
a9083016 2729 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 ||
6246b8a1
GM		 2730 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021 ||
2731 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2031 ||
8ae6d9c7 2732 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8031 ||
7ec0effd 2733 pdev->device == PCI_DEVICE_ID_QLOGIC_ISPF001 ||
f73cb695 2734 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8044 ||
2c5bbbb2 2735 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2071 ||
2b48992f
SC		 2736 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2271 ||
2737 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2261) {
285d0321 2738 bars = pci_select_bars(pdev, IORESOURCE_MEM);
09483916 2739 mem_only = 1;
7c3df132
SK		 2740 ql_dbg_pci(ql_dbg_init, pdev, 0x0007,
2741 "Mem only adapter.\n");
285d0321 2742 }
7c3df132
SK		 2743 ql_dbg_pci(ql_dbg_init, pdev, 0x0008,
2744 "Bars=%d.\n", bars);
285d0321 2745
09483916
BH		 2746 if (mem_only) {
2747 if (pci_enable_device_mem(pdev))
ddff7ed4 2748 return ret;
09483916
BH		 2749 } else {
2750 if (pci_enable_device(pdev))
ddff7ed4 2751 return ret;
09483916 2752 }
285d0321 2753
0927678f
JB		 2754 /* This may fail but that's ok */
2755 pci_enable_pcie_error_reporting(pdev);
285d0321 2756
e315cd28
AC		 2757 ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL);
2758 if (!ha) {
7c3df132
SK		 2759 ql_log_pci(ql_log_fatal, pdev, 0x0009,
2760 "Unable to allocate memory for ha.\n");
ddff7ed4 2761 goto disable_device;
1da177e4 2762 }
7c3df132
SK		 2763 ql_dbg_pci(ql_dbg_init, pdev, 0x000a,
2764 "Memory allocated for ha=%p.\n", ha);
e315cd28 2765 ha->pdev = pdev;
33e79977
QT		 2766 INIT_LIST_HEAD(&ha->tgt.q_full_list);
2767 spin_lock_init(&ha->tgt.q_full_lock);
7560151b 2768 spin_lock_init(&ha->tgt.sess_lock);
2f424b9b
QT		 2769 spin_lock_init(&ha->tgt.atio_lock);
2770
deeae7a6 2771 atomic_set(&ha->nvme_active_aen_cnt, 0);
1da177e4
LT		 2772
2773 /* Clear our data area */
285d0321 2774 ha->bars = bars;
09483916 2775 ha->mem_only = mem_only;
df4bf0bb 2776 spin_lock_init(&ha->hardware_lock);
339aa70e 2777 spin_lock_init(&ha->vport_slock);
a9b6f722 2778 mutex_init(&ha->selflogin_lock);
7a8ab9c8 2779 mutex_init(&ha->optrom_mutex);
1da177e4 2780
ea5b6382 2781 /* Set ISP-type information. */
2782 qla2x00_set_isp_flags(ha);
ca79cf66
DG		 2783
2784 /* Set EEH reset type to fundamental if required by hba */
95676112 2785 if (IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha) ||
f73cb695 2786 IS_QLA83XX(ha) || IS_QLA27XX(ha))
ca79cf66 2787 pdev->needs_freset = 1;
ca79cf66 2788
cba1e47f
CD		 2789 ha->prev_topology = 0;
2790 ha->init_cb_size = sizeof(init_cb_t);
2791 ha->link_data_rate = PORT_SPEED_UNKNOWN;
2792 ha->optrom_size = OPTROM_SIZE_2300;
2793
abbd8870 2794 /* Assign ISP specific operations. */
1da177e4 2795 if (IS_QLA2100(ha)) {
642ef983 2796 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
1da177e4 2797 ha->mbx_count = MAILBOX_REGISTER_COUNT_2100;
e315cd28
AC		 2798 req_length = REQUEST_ENTRY_CNT_2100;
2799 rsp_length = RESPONSE_ENTRY_CNT_2100;
2800 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
abbd8870 2801 ha->gid_list_info_size = 4;
3a03eb79
AV		 2802 ha->flash_conf_off = ~0;
2803 ha->flash_data_off = ~0;
2804 ha->nvram_conf_off = ~0;
2805 ha->nvram_data_off = ~0;
fd34f556 2806 ha->isp_ops = &qla2100_isp_ops;
1da177e4 2807 } else if (IS_QLA2200(ha)) {
642ef983 2808 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
67ddda35 2809 ha->mbx_count = MAILBOX_REGISTER_COUNT_2200;
e315cd28
AC		 2810 req_length = REQUEST_ENTRY_CNT_2200;
2811 rsp_length = RESPONSE_ENTRY_CNT_2100;
2812 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
abbd8870 2813 ha->gid_list_info_size = 4;
3a03eb79
AV		 2814 ha->flash_conf_off = ~0;
2815 ha->flash_data_off = ~0;
2816 ha->nvram_conf_off = ~0;
2817 ha->nvram_data_off = ~0;
fd34f556 2818 ha->isp_ops = &qla2100_isp_ops;
fca29703 2819 } else if (IS_QLA23XX(ha)) {
642ef983 2820 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
1da177e4 2821 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2822 req_length = REQUEST_ENTRY_CNT_2200;
2823 rsp_length = RESPONSE_ENTRY_CNT_2300;
2824 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
abbd8870 2825 ha->gid_list_info_size = 6;
854165f4 2826 if (IS_QLA2322(ha) || IS_QLA6322(ha))
2827 ha->optrom_size = OPTROM_SIZE_2322;
3a03eb79
AV		 2828 ha->flash_conf_off = ~0;
2829 ha->flash_data_off = ~0;
2830 ha->nvram_conf_off = ~0;
2831 ha->nvram_data_off = ~0;
fd34f556 2832 ha->isp_ops = &qla2300_isp_ops;
4d4df193 2833 } else if (IS_QLA24XX_TYPE(ha)) {
642ef983 2834 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
fca29703 2835 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2836 req_length = REQUEST_ENTRY_CNT_24XX;
2837 rsp_length = RESPONSE_ENTRY_CNT_2300;
2d70c103 2838 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
e315cd28 2839 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2c3dfe3f 2840 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
fca29703 2841 ha->gid_list_info_size = 8;
854165f4 2842 ha->optrom_size = OPTROM_SIZE_24XX;
73208dfd 2843 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX;
fd34f556 2844 ha->isp_ops = &qla24xx_isp_ops;
3a03eb79
AV		 2845 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2846 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2847 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2848 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
c3a2f0df 2849 } else if (IS_QLA25XX(ha)) {
642ef983 2850 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
c3a2f0df 2851 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2852 req_length = REQUEST_ENTRY_CNT_24XX;
2853 rsp_length = RESPONSE_ENTRY_CNT_2300;
2d70c103 2854 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
e315cd28 2855 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
c3a2f0df 2856 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
c3a2f0df
AV		 2857 ha->gid_list_info_size = 8;
2858 ha->optrom_size = OPTROM_SIZE_25XX;
73208dfd 2859 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
c3a2f0df 2860 ha->isp_ops = &qla25xx_isp_ops;
3a03eb79
AV		 2861 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2862 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2863 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2864 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
2865 } else if (IS_QLA81XX(ha)) {
642ef983 2866 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3a03eb79
AV		 2867 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2868 req_length = REQUEST_ENTRY_CNT_24XX;
2869 rsp_length = RESPONSE_ENTRY_CNT_2300;
aa230bc5 2870 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
3a03eb79
AV		 2871 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2872 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2873 ha->gid_list_info_size = 8;
2874 ha->optrom_size = OPTROM_SIZE_81XX;
40859ae5 2875 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3a03eb79
AV		 2876 ha->isp_ops = &qla81xx_isp_ops;
2877 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2878 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2879 ha->nvram_conf_off = ~0;
2880 ha->nvram_data_off = ~0;
a9083016 2881 } else if (IS_QLA82XX(ha)) {
642ef983 2882 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
a9083016
GM		 2883 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2884 req_length = REQUEST_ENTRY_CNT_82XX;
2885 rsp_length = RESPONSE_ENTRY_CNT_82XX;
2886 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2887 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2888 ha->gid_list_info_size = 8;
2889 ha->optrom_size = OPTROM_SIZE_82XX;
087c621e 2890 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
a9083016
GM		 2891 ha->isp_ops = &qla82xx_isp_ops;
2892 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2893 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2894 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2895 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
7ec0effd
AD		 2896 } else if (IS_QLA8044(ha)) {
2897 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2898 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2899 req_length = REQUEST_ENTRY_CNT_82XX;
2900 rsp_length = RESPONSE_ENTRY_CNT_82XX;
2901 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2902 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2903 ha->gid_list_info_size = 8;
2904 ha->optrom_size = OPTROM_SIZE_83XX;
2905 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2906 ha->isp_ops = &qla8044_isp_ops;
2907 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2908 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2909 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2910 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
6246b8a1 2911 } else if (IS_QLA83XX(ha)) {
7d613ac6 2912 ha->portnum = PCI_FUNC(ha->pdev->devfn);
642ef983 2913 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
6246b8a1 2914 ha->mbx_count = MAILBOX_REGISTER_COUNT;
f2ea653f 2915 req_length = REQUEST_ENTRY_CNT_83XX;
e7b42e33 2916 rsp_length = RESPONSE_ENTRY_CNT_83XX;
b8aa4bdf 2917 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
6246b8a1
GM		 2918 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2919 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2920 ha->gid_list_info_size = 8;
2921 ha->optrom_size = OPTROM_SIZE_83XX;
2922 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2923 ha->isp_ops = &qla83xx_isp_ops;
2924 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2925 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2926 ha->nvram_conf_off = ~0;
2927 ha->nvram_data_off = ~0;
8ae6d9c7
GM		 2928 } else if (IS_QLAFX00(ha)) {
2929 ha->max_fibre_devices = MAX_FIBRE_DEVICES_FX00;
2930 ha->mbx_count = MAILBOX_REGISTER_COUNT_FX00;
2931 ha->aen_mbx_count = AEN_MAILBOX_REGISTER_COUNT_FX00;
2932 req_length = REQUEST_ENTRY_CNT_FX00;
2933 rsp_length = RESPONSE_ENTRY_CNT_FX00;
8ae6d9c7
GM		 2934 ha->isp_ops = &qlafx00_isp_ops;
2935 ha->port_down_retry_count = 30; /* default value */
2936 ha->mr.fw_hbt_cnt = QLAFX00_HEARTBEAT_INTERVAL;
2937 ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL;
71e56003 2938 ha->mr.fw_critemp_timer_tick = QLAFX00_CRITEMP_INTERVAL;
8ae6d9c7 2939 ha->mr.fw_hbt_en = 1;
e8f5e95d
AB		 2940 ha->mr.host_info_resend = false;
2941 ha->mr.hinfo_resend_timer_tick = QLAFX00_HINFO_RESEND_INTERVAL;
f73cb695
CD		 2942 } else if (IS_QLA27XX(ha)) {
2943 ha->portnum = PCI_FUNC(ha->pdev->devfn);
2944 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2945 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e7b42e33
QT		 2946 req_length = REQUEST_ENTRY_CNT_83XX;
2947 rsp_length = RESPONSE_ENTRY_CNT_83XX;
b20f02e1 2948 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
f73cb695
CD		 2949 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2950 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2951 ha->gid_list_info_size = 8;
2952 ha->optrom_size = OPTROM_SIZE_83XX;
2953 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2954 ha->isp_ops = &qla27xx_isp_ops;
2955 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2956 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2957 ha->nvram_conf_off = ~0;
2958 ha->nvram_data_off = ~0;
1da177e4 2959 }
6246b8a1 2960
7c3df132
SK		 2961 ql_dbg_pci(ql_dbg_init, pdev, 0x001e,
2962 "mbx_count=%d, req_length=%d, "
2963 "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, "
642ef983
CD		 2964 "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, "
2965 "max_fibre_devices=%d.\n",
7c3df132
SK		 2966 ha->mbx_count, req_length, rsp_length, ha->max_loop_id,
2967 ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size,
642ef983 2968 ha->nvram_npiv_size, ha->max_fibre_devices);
7c3df132
SK		 2969 ql_dbg_pci(ql_dbg_init, pdev, 0x001f,
2970 "isp_ops=%p, flash_conf_off=%d, "
2971 "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n",
2972 ha->isp_ops, ha->flash_conf_off, ha->flash_data_off,
2973 ha->nvram_conf_off, ha->nvram_data_off);
706f457d
GM		 2974
2975 /* Configure PCI I/O space */
2976 ret = ha->isp_ops->iospace_config(ha);
2977 if (ret)
0a63ad12 2978 goto iospace_config_failed;
706f457d
GM		 2979
2980 ql_log_pci(ql_log_info, pdev, 0x001d,
2981 "Found an ISP%04X irq %d iobase 0x%p.\n",
2982 pdev->device, pdev->irq, ha->iobase);
6c2f527c 2983 mutex_init(&ha->vport_lock);
d7459527 2984 mutex_init(&ha->mq_lock);
0b05a1f0
MB		 2985 init_completion(&ha->mbx_cmd_comp);
2986 complete(&ha->mbx_cmd_comp);
2987 init_completion(&ha->mbx_intr_comp);
23f2ebd1 2988 init_completion(&ha->dcbx_comp);
f356bef1 2989 init_completion(&ha->lb_portup_comp);
1da177e4 2990
2c3dfe3f 2991 set_bit(0, (unsigned long *) ha->vp_idx_map);
1da177e4 2992
53303c42 2993 qla2x00_config_dma_addressing(ha);
7c3df132
SK		 2994 ql_dbg_pci(ql_dbg_init, pdev, 0x0020,
2995 "64 Bit addressing is %s.\n",
2996 ha->flags.enable_64bit_addressing ? "enable" :
2997 "disable");
73208dfd 2998 ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp);
b2a72ec3 2999 if (ret) {
7c3df132
SK		 3000 ql_log_pci(ql_log_fatal, pdev, 0x0031,
3001 "Failed to allocate memory for adapter, aborting.\n");
1da177e4 3002
e315cd28
AC		 3003 goto probe_hw_failed;
3004 }
3005
73208dfd 3006 req->max_q_depth = MAX_Q_DEPTH;
e315cd28 3007 if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU)
73208dfd
AC		 3008 req->max_q_depth = ql2xmaxqdepth;
3009
e315cd28
AC		 3010
3011 base_vha = qla2x00_create_host(sht, ha);
3012 if (!base_vha) {
a1541d5a 3013 ret = -ENOMEM;
6e9f21f3 3014 qla2x00_mem_free(ha);
2afa19a9
AC		 3015 qla2x00_free_req_que(ha, req);
3016 qla2x00_free_rsp_que(ha, rsp);
e315cd28 3017 goto probe_hw_failed;
1da177e4
LT		 3018 }
3019
e315cd28 3020 pci_set_drvdata(pdev, base_vha);
6b383979 3021 set_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags);
e315cd28 3022
e315cd28 3023 host = base_vha->host;
2afa19a9 3024 base_vha->req = req;
73208dfd 3025 if (IS_QLA2XXX_MIDTYPE(ha))
e315cd28 3026 base_vha->mgmt_svr_loop_id = 10 + base_vha->vp_idx;
73208dfd 3027 else
e315cd28
AC		 3028 base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER +
3029 base_vha->vp_idx;
58548cb5 3030
8ae6d9c7
GM		 3031 /* Setup fcport template structure. */
3032 ha->mr.fcport.vha = base_vha;
3033 ha->mr.fcport.port_type = FCT_UNKNOWN;
3034 ha->mr.fcport.loop_id = FC_NO_LOOP_ID;
3035 qla2x00_set_fcport_state(&ha->mr.fcport, FCS_UNCONFIGURED);
3036 ha->mr.fcport.supported_classes = FC_COS_UNSPECIFIED;
3037 ha->mr.fcport.scan_state = 1;
3038
58548cb5
GM		 3039 /* Set the SG table size based on ISP type */
3040 if (!IS_FWI2_CAPABLE(ha)) {
3041 if (IS_QLA2100(ha))
3042 host->sg_tablesize = 32;
3043 } else {
3044 if (!IS_QLA82XX(ha))
3045 host->sg_tablesize = QLA_SG_ALL;
3046 }
642ef983 3047 host->max_id = ha->max_fibre_devices;
e315cd28
AC		 3048 host->cmd_per_lun = 3;
3049 host->unique_id = host->host_no;
e02587d7 3050 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif)
0c470874
AE		 3051 host->max_cmd_len = 32;
3052 else
3053 host->max_cmd_len = MAX_CMDSZ;
e315cd28 3054 host->max_channel = MAX_BUSES - 1;
755f516b
HR		 3055 /* Older HBAs support only 16-bit LUNs */
3056 if (!IS_QLAFX00(ha) && !IS_FWI2_CAPABLE(ha) &&
3057 ql2xmaxlun > 0xffff)
3058 host->max_lun = 0xffff;
3059 else
3060 host->max_lun = ql2xmaxlun;
e315cd28 3061 host->transportt = qla2xxx_transport_template;
9a069e19 3062 sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC);
e315cd28 3063
7c3df132
SK		 3064 ql_dbg(ql_dbg_init, base_vha, 0x0033,
3065 "max_id=%d this_id=%d "
3066 "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d "
1abf635d 3067 "max_lun=%llu transportt=%p, vendor_id=%llu.\n", host->max_id,
7c3df132
SK		 3068 host->this_id, host->cmd_per_lun, host->unique_id,
3069 host->max_cmd_len, host->max_channel, host->max_lun,
3070 host->transportt, sht->vendor_id);
3071
1010f21e
HM		 3072 INIT_WORK(&base_vha->iocb_work, qla2x00_iocb_work_fn);
3073
d7459527
MH		 3074 /* Set up the irqs */
3075 ret = qla2x00_request_irqs(ha, rsp);
3076 if (ret)
3077 goto probe_init_failed;
3078
9a347ff4
CD		 3079 /* Alloc arrays of request and response ring ptrs */
3080 if (!qla2x00_alloc_queues(ha, req, rsp)) {
3081 ql_log(ql_log_fatal, base_vha, 0x003d,
3082 "Failed to allocate memory for queue pointers..."
3083 "aborting.\n");
3084 goto probe_init_failed;
3085 }
3086
5601236b
MH		 3087 if (ha->mqenable && shost_use_blk_mq(host)) {
3088 /* number of hardware queues supported by blk/scsi-mq*/
3089 host->nr_hw_queues = ha->max_qpairs;
3090
3091 ql_dbg(ql_dbg_init, base_vha, 0x0192,
3092 "blk/scsi-mq enabled, HW queues = %d.\n", host->nr_hw_queues);
c38d1baf
HM		 3093 } else {
3094 if (ql2xnvmeenable) {
3095 host->nr_hw_queues = ha->max_qpairs;
3096 ql_dbg(ql_dbg_init, base_vha, 0x0194,
3097 "FC-NVMe support is enabled, HW queues=%d\n",
3098 host->nr_hw_queues);
3099 } else {
3100 ql_dbg(ql_dbg_init, base_vha, 0x0193,
3101 "blk/scsi-mq disabled.\n");
3102 }
3103 }
5601236b 3104
2d70c103 3105 qlt_probe_one_stage1(base_vha, ha);
9a347ff4 3106
90a86fc0
JC		 3107 pci_save_state(pdev);
3108
9a347ff4 3109 /* Assign back pointers */
2afa19a9
AC		 3110 rsp->req = req;
3111 req->rsp = rsp;
9a347ff4 3112
8ae6d9c7
GM		 3113 if (IS_QLAFX00(ha)) {
3114 ha->rsp_q_map[0] = rsp;
3115 ha->req_q_map[0] = req;
3116 set_bit(0, ha->req_qid_map);
3117 set_bit(0, ha->rsp_qid_map);
3118 }
3119
08029990
AV		 3120 /* FWI2-capable only. */
3121 req->req_q_in = &ha->iobase->isp24.req_q_in;
3122 req->req_q_out = &ha->iobase->isp24.req_q_out;
3123 rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in;
3124 rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out;
f73cb695 3125 if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
08029990
AV		 3126 req->req_q_in = &ha->mqiobase->isp25mq.req_q_in;
3127 req->req_q_out = &ha->mqiobase->isp25mq.req_q_out;
3128 rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in;
3129 rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out;
17d98630
AC		 3130 }
3131
8ae6d9c7
GM		 3132 if (IS_QLAFX00(ha)) {
3133 req->req_q_in = &ha->iobase->ispfx00.req_q_in;
3134 req->req_q_out = &ha->iobase->ispfx00.req_q_out;
3135 rsp->rsp_q_in = &ha->iobase->ispfx00.rsp_q_in;
3136 rsp->rsp_q_out = &ha->iobase->ispfx00.rsp_q_out;
3137 }
3138
7ec0effd 3139 if (IS_P3P_TYPE(ha)) {
a9083016
GM		 3140 req->req_q_out = &ha->iobase->isp82.req_q_out[0];
3141 rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0];
3142 rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0];
3143 }
3144
7c3df132
SK		 3145 ql_dbg(ql_dbg_multiq, base_vha, 0xc009,
3146 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
3147 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
3148 ql_dbg(ql_dbg_multiq, base_vha, 0xc00a,
3149 "req->req_q_in=%p req->req_q_out=%p "
3150 "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
3151 req->req_q_in, req->req_q_out,
3152 rsp->rsp_q_in, rsp->rsp_q_out);
3153 ql_dbg(ql_dbg_init, base_vha, 0x003e,
3154 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
3155 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
3156 ql_dbg(ql_dbg_init, base_vha, 0x003f,
3157 "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
3158 req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out);
1da177e4 3159
8ae6d9c7 3160 if (ha->isp_ops->initialize_adapter(base_vha)) {
7c3df132
SK		 3161 ql_log(ql_log_fatal, base_vha, 0x00d6,
3162 "Failed to initialize adapter - Adapter flags %x.\n",
3163 base_vha->device_flags);
1da177e4 3164
a9083016
GM		 3165 if (IS_QLA82XX(ha)) {
3166 qla82xx_idc_lock(ha);
3167 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 3168 QLA8XXX_DEV_FAILED);
a9083016 3169 qla82xx_idc_unlock(ha);
7c3df132
SK		 3170 ql_log(ql_log_fatal, base_vha, 0x00d7,
3171 "HW State: FAILED.\n");
7ec0effd
AD		 3172 } else if (IS_QLA8044(ha)) {
3173 qla8044_idc_lock(ha);
3174 qla8044_wr_direct(base_vha,
3175 QLA8044_CRB_DEV_STATE_INDEX,
3176 QLA8XXX_DEV_FAILED);
3177 qla8044_idc_unlock(ha);
3178 ql_log(ql_log_fatal, base_vha, 0x0150,
3179 "HW State: FAILED.\n");
a9083016
GM		 3180 }
3181
a1541d5a 3182 ret = -ENODEV;
1da177e4
LT		 3183 goto probe_failed;
3184 }
3185
3b1bef64
CD		 3186 if (IS_QLAFX00(ha))
3187 host->can_queue = QLAFX00_MAX_CANQUEUE;
3188 else
3189 host->can_queue = req->num_outstanding_cmds - 10;
3190
3191 ql_dbg(ql_dbg_init, base_vha, 0x0032,
3192 "can_queue=%d, req=%p, mgmt_svr_loop_id=%d, sg_tablesize=%d.\n",
3193 host->can_queue, base_vha->req,
3194 base_vha->mgmt_svr_loop_id, host->sg_tablesize);
3195
a01c77d2
QT		 3196 ha->wq = alloc_workqueue("qla2xxx_wq", WQ_MEM_RECLAIM, 0);
3197
e326d22a
QT		 3198 if (ha->mqenable) {
3199 bool mq = false;
3200 bool startit = false;
e326d22a
QT		 3201
3202 if (QLA_TGT_MODE_ENABLED()) {
3203 mq = true;
3204 startit = false;
3205 }
3206
3207 if ((ql2x_ini_mode == QLA2XXX_INI_MODE_ENABLED) &&
3208 shost_use_blk_mq(host)) {
3209 mq = true;
3210 startit = true;
3211 }
3212
3213 if (mq) {
3214 /* Create start of day qpairs for Block MQ */
5601236b 3215 for (i = 0; i < ha->max_qpairs; i++)
e326d22a 3216 qla2xxx_create_qpair(base_vha, 5, 0, startit);
5601236b
MH		 3217 }
3218 }
68ca949c 3219
cbc8eb67
AV		 3220 if (ha->flags.running_gold_fw)
3221 goto skip_dpc;
3222
1da177e4
LT		 3223 /*
3224 * Startup the kernel thread for this host adapter
3225 */
39a11240 3226 ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha,
7c3df132 3227 "%s_dpc", base_vha->host_str);
39a11240 3228 if (IS_ERR(ha->dpc_thread)) {
7c3df132
SK		 3229 ql_log(ql_log_fatal, base_vha, 0x00ed,
3230 "Failed to start DPC thread.\n");
39a11240 3231 ret = PTR_ERR(ha->dpc_thread);
e2532b4a 3232 ha->dpc_thread = NULL;
1da177e4
LT		 3233 goto probe_failed;
3234 }
7c3df132
SK		 3235 ql_dbg(ql_dbg_init, base_vha, 0x00ee,
3236 "DPC thread started successfully.\n");
1da177e4 3237
2d70c103
NB		 3238 /*
3239 * If we're not coming up in initiator mode, we might sit for
3240 * a while without waking up the dpc thread, which leads to a
3241 * stuck process warning. So just kick the dpc once here and
3242 * let the kthread start (and go back to sleep in qla2x00_do_dpc).
3243 */
3244 qla2xxx_wake_dpc(base_vha);
3245
f3ddac19
CD		 3246 INIT_WORK(&ha->board_disable, qla2x00_disable_board_on_pci_error);
3247
81178772
SK		 3248 if (IS_QLA8031(ha) || IS_MCTP_CAPABLE(ha)) {
3249 sprintf(wq_name, "qla2xxx_%lu_dpc_lp_wq", base_vha->host_no);
3250 ha->dpc_lp_wq = create_singlethread_workqueue(wq_name);
3251 INIT_WORK(&ha->idc_aen, qla83xx_service_idc_aen);
3252
3253 sprintf(wq_name, "qla2xxx_%lu_dpc_hp_wq", base_vha->host_no);
3254 ha->dpc_hp_wq = create_singlethread_workqueue(wq_name);
3255 INIT_WORK(&ha->nic_core_reset, qla83xx_nic_core_reset_work);
3256 INIT_WORK(&ha->idc_state_handler,
3257 qla83xx_idc_state_handler_work);
3258 INIT_WORK(&ha->nic_core_unrecoverable,
3259 qla83xx_nic_core_unrecoverable_work);
3260 }
3261
cbc8eb67 3262skip_dpc:
e315cd28
AC		 3263 list_add_tail(&base_vha->list, &ha->vp_list);
3264 base_vha->host->irq = ha->pdev->irq;
1da177e4
LT		 3265
3266 /* Initialized the timer */
8e5f4ba0 3267 qla2x00_start_timer(base_vha, WATCH_INTERVAL);
7c3df132
SK		 3268 ql_dbg(ql_dbg_init, base_vha, 0x00ef,
3269 "Started qla2x00_timer with "
3270 "interval=%d.\n", WATCH_INTERVAL);
3271 ql_dbg(ql_dbg_init, base_vha, 0x00f0,
3272 "Detected hba at address=%p.\n",
3273 ha);
d19044c3 3274
e02587d7 3275 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) {
bad75002 3276 if (ha->fw_attributes & BIT_4) {
9e522cd8 3277 int prot = 0, guard;
bad75002 3278 base_vha->flags.difdix_supported = 1;
7c3df132
SK		 3279 ql_dbg(ql_dbg_init, base_vha, 0x00f1,
3280 "Registering for DIF/DIX type 1 and 3 protection.\n");
8cb2049c
AE		 3281 if (ql2xenabledif == 1)
3282 prot = SHOST_DIX_TYPE0_PROTECTION;
bad75002 3283 scsi_host_set_prot(host,
8cb2049c 3284 prot | SHOST_DIF_TYPE1_PROTECTION
0c470874 3285 | SHOST_DIF_TYPE2_PROTECTION
bad75002
AE		 3286 | SHOST_DIF_TYPE3_PROTECTION
3287 | SHOST_DIX_TYPE1_PROTECTION
0c470874 3288 | SHOST_DIX_TYPE2_PROTECTION
bad75002 3289 | SHOST_DIX_TYPE3_PROTECTION);
9e522cd8
AE		 3290
3291 guard = SHOST_DIX_GUARD_CRC;
3292
3293 if (IS_PI_IPGUARD_CAPABLE(ha) &&
3294 (ql2xenabledif > 1 || IS_PI_DIFB_DIX0_CAPABLE(ha)))
3295 guard |= SHOST_DIX_GUARD_IP;
3296
3297 scsi_host_set_guard(host, guard);
bad75002
AE		 3298 } else
3299 base_vha->flags.difdix_supported = 0;
3300 }
3301
a9083016
GM		 3302 ha->isp_ops->enable_intrs(ha);
3303
1fe19ee4
AB		 3304 if (IS_QLAFX00(ha)) {
3305 ret = qlafx00_fx_disc(base_vha,
3306 &base_vha->hw->mr.fcport, FXDISC_GET_CONFIG_INFO);
3307 host->sg_tablesize = (ha->mr.extended_io_enabled) ?
3308 QLA_SG_ALL : 128;
3309 }
3310
a1541d5a
AV		 3311 ret = scsi_add_host(host, &pdev->dev);
3312 if (ret)
3313 goto probe_failed;
3314
1486400f
MR		 3315 base_vha->flags.init_done = 1;
3316 base_vha->flags.online = 1;
edaa5c74 3317 ha->prev_minidump_failed = 0;
1486400f 3318
7c3df132
SK		 3319 ql_dbg(ql_dbg_init, base_vha, 0x00f2,
3320 "Init done and hba is online.\n");
3321
726b8548
QT		 3322 if (qla_ini_mode_enabled(base_vha) ||
3323 qla_dual_mode_enabled(base_vha))
2d70c103
NB		 3324 scsi_scan_host(host);
3325 else
3326 ql_dbg(ql_dbg_init, base_vha, 0x0122,
3327 "skipping scsi_scan_host() for non-initiator port\n");
1e99e33a 3328
e315cd28 3329 qla2x00_alloc_sysfs_attr(base_vha);
a1541d5a 3330
8ae6d9c7 3331 if (IS_QLAFX00(ha)) {
8ae6d9c7
GM		 3332 ret = qlafx00_fx_disc(base_vha,
3333 &base_vha->hw->mr.fcport, FXDISC_GET_PORT_INFO);
3334
3335 /* Register system information */
3336 ret = qlafx00_fx_disc(base_vha,
3337 &base_vha->hw->mr.fcport, FXDISC_REG_HOST_INFO);
3338 }
3339
e315cd28 3340 qla2x00_init_host_attr(base_vha);
a1541d5a 3341
e315cd28 3342 qla2x00_dfs_setup(base_vha);
df613b96 3343
03eb912a
AB		 3344 ql_log(ql_log_info, base_vha, 0x00fb,
3345 "QLogic %s - %s.\n", ha->model_number, ha->model_desc);
7c3df132
SK		 3346 ql_log(ql_log_info, base_vha, 0x00fc,
3347 "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n",
3348 pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info),
3349 pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-',
3350 base_vha->host_no,
df57caba 3351 ha->isp_ops->fw_version_str(base_vha, fw_str, sizeof(fw_str)));
1da177e4 3352
2d70c103
NB		 3353 qlt_add_target(ha, base_vha);
3354
6b383979 3355 clear_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags);
a29b3dd7
JC		 3356
3357 if (test_bit(UNLOADING, &base_vha->dpc_flags))
3358 return -ENODEV;
3359
e4e3a2ce
QT		 3360 if (ha->flags.detected_lr_sfp) {
3361 ql_log(ql_log_info, base_vha, 0xffff,
3362 "Reset chip to pick up LR SFP setting\n");
3363 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
3364 qla2xxx_wake_dpc(base_vha);
3365 }
3366
1da177e4
LT		 3367 return 0;
3368
6e9f21f3 3369probe_init_failed:
2afa19a9 3370 qla2x00_free_req_que(ha, req);
9a347ff4
CD		 3371 ha->req_q_map[0] = NULL;
3372 clear_bit(0, ha->req_qid_map);
2afa19a9 3373 qla2x00_free_rsp_que(ha, rsp);
9a347ff4
CD		 3374 ha->rsp_q_map[0] = NULL;
3375 clear_bit(0, ha->rsp_qid_map);
2afa19a9 3376 ha->max_req_queues = ha->max_rsp_queues = 0;
6e9f21f3 3377
1da177e4 3378probe_failed:
b9978769
AV		 3379 if (base_vha->timer_active)
3380 qla2x00_stop_timer(base_vha);
3381 base_vha->flags.online = 0;
3382 if (ha->dpc_thread) {
3383 struct task_struct *t = ha->dpc_thread;
3384
3385 ha->dpc_thread = NULL;
3386 kthread_stop(t);
3387 }
3388
e315cd28 3389 qla2x00_free_device(base_vha);
1da177e4 3390
e315cd28 3391 scsi_host_put(base_vha->host);
1da177e4 3392
e315cd28 3393probe_hw_failed:
1a2fbf18
JL		 3394 qla2x00_clear_drv_active(ha);
3395
0a63ad12 3396iospace_config_failed:
7ec0effd 3397 if (IS_P3P_TYPE(ha)) {
0a63ad12 3398 if (!ha->nx_pcibase)
f73cb695 3399 iounmap((device_reg_t *)ha->nx_pcibase);
a9083016 3400 if (!ql2xdbwr)
f73cb695 3401 iounmap((device_reg_t *)ha->nxdb_wr_ptr);
a9083016
GM		 3402 } else {
3403 if (ha->iobase)
3404 iounmap(ha->iobase);
8ae6d9c7
GM		 3405 if (ha->cregbase)
3406 iounmap(ha->cregbase);
a9083016 3407 }
e315cd28
AC		 3408 pci_release_selected_regions(ha->pdev, ha->bars);
3409 kfree(ha);
1da177e4 3410
ddff7ed4 3411disable_device:
e315cd28 3412 pci_disable_device(pdev);
a1541d5a 3413 return ret;
1da177e4 3414}
1da177e4 3415
e30d1756
MI		 3416static void
3417qla2x00_shutdown(struct pci_dev *pdev)
3418{
3419 scsi_qla_host_t *vha;
3420 struct qla_hw_data *ha;
3421
3422 vha = pci_get_drvdata(pdev);
3423 ha = vha->hw;
3424
efdb5760
SC		 3425 ql_log(ql_log_info, vha, 0xfffa,
3426 "Adapter shutdown\n");
3427
3428 /*
3429 * Prevent future board_disable and wait
3430 * until any pending board_disable has completed.
3431 */
3432 set_bit(PFLG_DRIVER_REMOVING, &vha->pci_flags);
3433 cancel_work_sync(&ha->board_disable);
3434
3435 if (!atomic_read(&pdev->enable_cnt))
3436 return;
3437
42479343
AB		 3438 /* Notify ISPFX00 firmware */
3439 if (IS_QLAFX00(ha))
3440 qlafx00_driver_shutdown(vha, 20);
3441
e30d1756
MI		 3442 /* Turn-off FCE trace */
3443 if (ha->flags.fce_enabled) {
3444 qla2x00_disable_fce_trace(vha, NULL, NULL);
3445 ha->flags.fce_enabled = 0;
3446 }
3447
3448 /* Turn-off EFT trace */
3449 if (ha->eft)
3450 qla2x00_disable_eft_trace(vha);
3451
3452 /* Stop currently executing firmware. */
3453 qla2x00_try_to_stop_firmware(vha);
3454
3455 /* Turn adapter off line */
3456 vha->flags.online = 0;
3457
3458 /* turn-off interrupts on the card */
3459 if (ha->interrupts_on) {
3460 vha->flags.init_done = 0;
3461 ha->isp_ops->disable_intrs(ha);
3462 }
3463
3464 qla2x00_free_irqs(vha);
3465
3466 qla2x00_free_fw_dump(ha);
61d41f61 3467
61d41f61 3468 pci_disable_device(pdev);
efdb5760
SC		 3469 ql_log(ql_log_info, vha, 0xfffe,
3470 "Adapter shutdown successfully.\n");
e30d1756
MI		 3471}
3472
fe1b806f 3473/* Deletes all the virtual ports for a given ha */
4c993f76 3474static void
fe1b806f 3475qla2x00_delete_all_vps(struct qla_hw_data *ha, scsi_qla_host_t *base_vha)
1da177e4 3476{
fe1b806f 3477 scsi_qla_host_t *vha;
feafb7b1 3478 unsigned long flags;
e315cd28 3479
43ebf16d
AE		 3480 mutex_lock(&ha->vport_lock);
3481 while (ha->cur_vport_count) {
43ebf16d 3482 spin_lock_irqsave(&ha->vport_slock, flags);
feafb7b1 3483
43ebf16d
AE		 3484 BUG_ON(base_vha->list.next == &ha->vp_list);
3485 /* This assumes first entry in ha->vp_list is always base vha */
3486 vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list);
52c82823 3487 scsi_host_get(vha->host);
feafb7b1 3488
43ebf16d
AE		 3489 spin_unlock_irqrestore(&ha->vport_slock, flags);
3490 mutex_unlock(&ha->vport_lock);
3491
3492 fc_vport_terminate(vha->fc_vport);
3493 scsi_host_put(vha->host);
feafb7b1 3494
43ebf16d 3495 mutex_lock(&ha->vport_lock);
e315cd28 3496 }
43ebf16d 3497 mutex_unlock(&ha->vport_lock);
fe1b806f 3498}
1da177e4 3499
fe1b806f
CD		 3500/* Stops all deferred work threads */
3501static void
3502qla2x00_destroy_deferred_work(struct qla_hw_data *ha)
3503{
7d613ac6
SV		 3504 /* Cancel all work and destroy DPC workqueues */
3505 if (ha->dpc_lp_wq) {
3506 cancel_work_sync(&ha->idc_aen);
3507 destroy_workqueue(ha->dpc_lp_wq);
3508 ha->dpc_lp_wq = NULL;
3509 }
3510
3511 if (ha->dpc_hp_wq) {
3512 cancel_work_sync(&ha->nic_core_reset);
3513 cancel_work_sync(&ha->idc_state_handler);
3514 cancel_work_sync(&ha->nic_core_unrecoverable);
3515 destroy_workqueue(ha->dpc_hp_wq);
3516 ha->dpc_hp_wq = NULL;
3517 }
3518
b9978769
AV		 3519 /* Kill the kernel thread for this host */
3520 if (ha->dpc_thread) {
3521 struct task_struct *t = ha->dpc_thread;
3522
3523 /*
3524 * qla2xxx_wake_dpc checks for ->dpc_thread
3525 * so we need to zero it out.
3526 */
3527 ha->dpc_thread = NULL;
3528 kthread_stop(t);
3529 }
fe1b806f 3530}
1da177e4 3531
fe1b806f
CD		 3532static void
3533qla2x00_unmap_iobases(struct qla_hw_data *ha)
3534{
a9083016 3535 if (IS_QLA82XX(ha)) {
b963752f 3536
f73cb695 3537 iounmap((device_reg_t *)ha->nx_pcibase);
a9083016 3538 if (!ql2xdbwr)
f73cb695 3539 iounmap((device_reg_t *)ha->nxdb_wr_ptr);
a9083016
GM		 3540 } else {
3541 if (ha->iobase)
3542 iounmap(ha->iobase);
1da177e4 3543
8ae6d9c7
GM		 3544 if (ha->cregbase)
3545 iounmap(ha->cregbase);
3546
a9083016
GM		 3547 if (ha->mqiobase)
3548 iounmap(ha->mqiobase);
6246b8a1 3549
f73cb695 3550 if ((IS_QLA83XX(ha) || IS_QLA27XX(ha)) && ha->msixbase)
6246b8a1 3551 iounmap(ha->msixbase);
a9083016 3552 }
fe1b806f
CD		 3553}
3554
3555static void
db7157d4 3556qla2x00_clear_drv_active(struct qla_hw_data *ha)
fe1b806f 3557{
fe1b806f
CD		 3558 if (IS_QLA8044(ha)) {
3559 qla8044_idc_lock(ha);
c41afc9a 3560 qla8044_clear_drv_active(ha);
fe1b806f
CD		 3561 qla8044_idc_unlock(ha);
3562 } else if (IS_QLA82XX(ha)) {
3563 qla82xx_idc_lock(ha);
3564 qla82xx_clear_drv_active(ha);
3565 qla82xx_idc_unlock(ha);
3566 }
3567}
3568
3569static void
3570qla2x00_remove_one(struct pci_dev *pdev)
3571{
3572 scsi_qla_host_t *base_vha;
3573 struct qla_hw_data *ha;
3574
beb9e315
JL		 3575 base_vha = pci_get_drvdata(pdev);
3576 ha = base_vha->hw;
3577
3578 /* Indicate device removal to prevent future board_disable and wait
3579 * until any pending board_disable has completed. */
3580 set_bit(PFLG_DRIVER_REMOVING, &base_vha->pci_flags);
3581 cancel_work_sync(&ha->board_disable);
3582
fe1b806f 3583 /*
beb9e315
JL		 3584 * If the PCI device is disabled then there was a PCI-disconnect and
3585 * qla2x00_disable_board_on_pci_error has taken care of most of the
3586 * resources.
fe1b806f 3587 */
beb9e315 3588 if (!atomic_read(&pdev->enable_cnt)) {
726b8548
QT		 3589 dma_free_coherent(&ha->pdev->dev, base_vha->gnl.size,
3590 base_vha->gnl.l, base_vha->gnl.ldma);
3591
beb9e315
JL		 3592 scsi_host_put(base_vha->host);
3593 kfree(ha);
3594 pci_set_drvdata(pdev, NULL);
fe1b806f 3595 return;
beb9e315 3596 }
638a1a01
SC		 3597 qla2x00_wait_for_hba_ready(base_vha);
3598
726b8548
QT		 3599 /*
3600 * if UNLOAD flag is already set, then continue unload,
783e0dc4
SC		 3601 * where it was set first.
3602 */
3603 if (test_bit(UNLOADING, &base_vha->dpc_flags))
3604 return;
3605
fe1b806f 3606 set_bit(UNLOADING, &base_vha->dpc_flags);
e84067d7
DG		 3607
3608 qla_nvme_delete(base_vha);
3609
726b8548
QT		 3610 dma_free_coherent(&ha->pdev->dev,
3611 base_vha->gnl.size, base_vha->gnl.l, base_vha->gnl.ldma);
fe1b806f
CD		 3612
3613 if (IS_QLAFX00(ha))
3614 qlafx00_driver_shutdown(base_vha, 20);
3615
3616 qla2x00_delete_all_vps(ha, base_vha);
3617
3618 if (IS_QLA8031(ha)) {
3619 ql_dbg(ql_dbg_p3p, base_vha, 0xb07e,
3620 "Clearing fcoe driver presence.\n");
3621 if (qla83xx_clear_drv_presence(base_vha) != QLA_SUCCESS)
3622 ql_dbg(ql_dbg_p3p, base_vha, 0xb079,
3623 "Error while clearing DRV-Presence.\n");
3624 }
3625
3626 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
3627
3628 qla2x00_dfs_remove(base_vha);
3629
3630 qla84xx_put_chip(base_vha);
3631
2d5a4c34
HM		 3632 /* Laser should be disabled only for ISP2031 */
3633 if (IS_QLA2031(ha))
3634 qla83xx_disable_laser(base_vha);
3635
fe1b806f
CD		 3636 /* Disable timer */
3637 if (base_vha->timer_active)
3638 qla2x00_stop_timer(base_vha);
3639
3640 base_vha->flags.online = 0;
3641
b0d6cabd
HM		 3642 /* free DMA memory */
3643 if (ha->exlogin_buf)
3644 qla2x00_free_exlogin_buffer(ha);
3645
2f56a7f1
HM		 3646 /* free DMA memory */
3647 if (ha->exchoffld_buf)
3648 qla2x00_free_exchoffld_buffer(ha);
3649
fe1b806f
CD		 3650 qla2x00_destroy_deferred_work(ha);
3651
3652 qlt_remove_target(ha, base_vha);
3653
3654 qla2x00_free_sysfs_attr(base_vha, true);
3655
3656 fc_remove_host(base_vha->host);
482c9dc7 3657 qlt_remove_target_resources(ha);
fe1b806f
CD		 3658
3659 scsi_remove_host(base_vha->host);
3660
3661 qla2x00_free_device(base_vha);
3662
db7157d4 3663 qla2x00_clear_drv_active(ha);
fe1b806f 3664
d2749ffa
AE		 3665 scsi_host_put(base_vha->host);
3666
fe1b806f 3667 qla2x00_unmap_iobases(ha);
73208dfd 3668
e315cd28
AC		 3669 pci_release_selected_regions(ha->pdev, ha->bars);
3670 kfree(ha);
1da177e4 3671
90a86fc0
JC		 3672 pci_disable_pcie_error_reporting(pdev);
3673
665db93b 3674 pci_disable_device(pdev);
1da177e4 3675}
1da177e4
LT		 3676
3677static void
e315cd28 3678qla2x00_free_device(scsi_qla_host_t *vha)
1da177e4 3679{
e315cd28 3680 struct qla_hw_data *ha = vha->hw;
1da177e4 3681
85880801
AV		 3682 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
3683
3684 /* Disable timer */
3685 if (vha->timer_active)
3686 qla2x00_stop_timer(vha);
3687
2afa19a9 3688 qla25xx_delete_queues(vha);
fe1b806f 3689
df613b96 3690 if (ha->flags.fce_enabled)
e315cd28 3691 qla2x00_disable_fce_trace(vha, NULL, NULL);
df613b96 3692
a7a167bf 3693 if (ha->eft)
e315cd28 3694 qla2x00_disable_eft_trace(vha);
a7a167bf 3695
f6ef3b18 3696 /* Stop currently executing firmware. */
e315cd28 3697 qla2x00_try_to_stop_firmware(vha);
1da177e4 3698
85880801
AV		 3699 vha->flags.online = 0;
3700
f6ef3b18 3701 /* turn-off interrupts on the card */
a9083016
GM		 3702 if (ha->interrupts_on) {
3703 vha->flags.init_done = 0;
fd34f556 3704 ha->isp_ops->disable_intrs(ha);
a9083016 3705 }
f6ef3b18 3706
093df737
QT		 3707 qla2x00_free_fcports(vha);
3708
e315cd28 3709 qla2x00_free_irqs(vha);
1da177e4 3710
093df737
QT		 3711 /* Flush the work queue and remove it */
3712 if (ha->wq) {
3713 flush_workqueue(ha->wq);
3714 destroy_workqueue(ha->wq);
3715 ha->wq = NULL;
3716 }
3717
8867048b 3718
e315cd28 3719 qla2x00_mem_free(ha);
73208dfd 3720
08de2844
GM		 3721 qla82xx_md_free(vha);
3722
73208dfd 3723 qla2x00_free_queues(ha);
1da177e4
LT		 3724}
3725
8867048b
CD		 3726void qla2x00_free_fcports(struct scsi_qla_host *vha)
3727{
3728 fc_port_t *fcport, *tfcport;
3729
3730 list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list) {
3731 list_del(&fcport->list);
5f16b331 3732 qla2x00_clear_loop_id(fcport);
8867048b 3733 kfree(fcport);
8867048b
CD		 3734 }
3735}
3736
d97994dc 3737static inline void
e315cd28 3738qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport,
d97994dc 3739 int defer)
3740{
d97994dc 3741 struct fc_rport *rport;
67becc00 3742 scsi_qla_host_t *base_vha;
044d78e1 3743 unsigned long flags;
d97994dc 3744
3745 if (!fcport->rport)
3746 return;
3747
3748 rport = fcport->rport;
3749 if (defer) {
67becc00 3750 base_vha = pci_get_drvdata(vha->hw->pdev);
044d78e1 3751 spin_lock_irqsave(vha->host->host_lock, flags);
d97994dc 3752 fcport->drport = rport;
044d78e1 3753 spin_unlock_irqrestore(vha->host->host_lock, flags);
df673274 3754 qlt_do_generation_tick(vha, &base_vha->total_fcport_update_gen);
67becc00
AV		 3755 set_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags);
3756 qla2xxx_wake_dpc(base_vha);
2d70c103 3757 } else {
df673274 3758 int now;
726b8548 3759 if (rport) {
83548fe2
QT		 3760 ql_dbg(ql_dbg_disc, fcport->vha, 0x2109,
3761 "%s %8phN. rport %p roles %x\n",
3762 __func__, fcport->port_name, rport,
3763 rport->roles);
d20ed91b 3764 fc_remote_port_delete(rport);
726b8548 3765 }
df673274 3766 qlt_do_generation_tick(vha, &now);
2d70c103 3767 }
d97994dc 3768}
3769
1da177e4
LT		 3770/*
3771 * qla2x00_mark_device_lost Updates fcport state when device goes offline.
3772 *
3773 * Input: ha = adapter block pointer. fcport = port structure pointer.
3774 *
3775 * Return: None.
3776 *
3777 * Context:
3778 */
e315cd28 3779void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport,
d97994dc 3780 int do_login, int defer)
1da177e4 3781{
8ae6d9c7
GM		 3782 if (IS_QLAFX00(vha->hw)) {
3783 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
3784 qla2x00_schedule_rport_del(vha, fcport, defer);
3785 return;
3786 }
3787
2c3dfe3f 3788 if (atomic_read(&fcport->state) == FCS_ONLINE &&
c6d39e23 3789 vha->vp_idx == fcport->vha->vp_idx) {
ec426e10 3790 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
e315cd28
AC		 3791 qla2x00_schedule_rport_del(vha, fcport, defer);
3792 }
fa2a1ce5 3793 /*
1da177e4
LT		 3794 * We may need to retry the login, so don't change the state of the
3795 * port but do the retries.
3796 */
3797 if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD)
ec426e10 3798 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
1da177e4
LT		 3799
3800 if (!do_login)
3801 return;
3802
a1d0285e
AE		 3803 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
3804
1da177e4 3805 if (fcport->login_retry == 0) {
e315cd28 3806 fcport->login_retry = vha->hw->login_retry_count;
1da177e4 3807
83548fe2 3808 ql_dbg(ql_dbg_disc, vha, 0x20a3,
726b8548 3809 "Port login retry %8phN, lid 0x%04x retry cnt=%d.\n",
7b833558 3810 fcport->port_name, fcport->loop_id, fcport->login_retry);
1da177e4
LT		 3811 }
3812}
3813
3814/*
3815 * qla2x00_mark_all_devices_lost
3816 * Updates fcport state when device goes offline.
3817 *
3818 * Input:
3819 * ha = adapter block pointer.
3820 * fcport = port structure pointer.
3821 *
3822 * Return:
3823 * None.
3824 *
3825 * Context:
3826 */
3827void
e315cd28 3828qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha, int defer)
1da177e4
LT		 3829{
3830 fc_port_t *fcport;
3831
83548fe2
QT		 3832 ql_dbg(ql_dbg_disc, vha, 0x20f1,
3833 "Mark all dev lost\n");
726b8548 3834
e315cd28 3835 list_for_each_entry(fcport, &vha->vp_fcports, list) {
726b8548
QT		 3836 fcport->scan_state = 0;
3837 qlt_schedule_sess_for_deletion_lock(fcport);
3838
c6d39e23 3839 if (vha->vp_idx != 0 && vha->vp_idx != fcport->vha->vp_idx)
1da177e4 3840 continue;
0d6e61bc 3841
1da177e4
LT		 3842 /*
3843 * No point in marking the device as lost, if the device is
3844 * already DEAD.
3845 */
3846 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD)
3847 continue;
e315cd28 3848 if (atomic_read(&fcport->state) == FCS_ONLINE) {
ec426e10 3849 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
0d6e61bc
AV		 3850 if (defer)
3851 qla2x00_schedule_rport_del(vha, fcport, defer);
c6d39e23 3852 else if (vha->vp_idx == fcport->vha->vp_idx)
0d6e61bc
AV		 3853 qla2x00_schedule_rport_del(vha, fcport, defer);
3854 }
1da177e4
LT		 3855 }
3856}
3857
3858/*
3859* qla2x00_mem_alloc
3860* Allocates adapter memory.
3861*
3862* Returns:
3863* 0 = success.
e8711085 3864* !0 = failure.
1da177e4 3865*/
e8711085 3866static int
73208dfd
AC		 3867qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len,
3868 struct req_que **req, struct rsp_que **rsp)
1da177e4
LT		 3869{
3870 char name[16];
1da177e4 3871
e8711085 3872 ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size,
e315cd28 3873 &ha->init_cb_dma, GFP_KERNEL);
e8711085 3874 if (!ha->init_cb)
e315cd28 3875 goto fail;
e8711085 3876
2d70c103
NB		 3877 if (qlt_mem_alloc(ha) < 0)
3878 goto fail_free_init_cb;
3879
642ef983
CD		 3880 ha->gid_list = dma_alloc_coherent(&ha->pdev->dev,
3881 qla2x00_gid_list_size(ha), &ha->gid_list_dma, GFP_KERNEL);
e315cd28 3882 if (!ha->gid_list)
2d70c103 3883 goto fail_free_tgt_mem;
1da177e4 3884
e8711085
AV		 3885 ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep);
3886 if (!ha->srb_mempool)
e315cd28 3887 goto fail_free_gid_list;
e8711085 3888
7ec0effd 3889 if (IS_P3P_TYPE(ha)) {
a9083016
GM		 3890 /* Allocate cache for CT6 Ctx. */
3891 if (!ctx_cachep) {
3892 ctx_cachep = kmem_cache_create("qla2xxx_ctx",
3893 sizeof(struct ct6_dsd), 0,
3894 SLAB_HWCACHE_ALIGN, NULL);
3895 if (!ctx_cachep)
fc1ffd6c 3896 goto fail_free_srb_mempool;
a9083016
GM		 3897 }
3898 ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ,
3899 ctx_cachep);
3900 if (!ha->ctx_mempool)
3901 goto fail_free_srb_mempool;
7c3df132
SK		 3902 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021,
3903 "ctx_cachep=%p ctx_mempool=%p.\n",
3904 ctx_cachep, ha->ctx_mempool);
a9083016
GM		 3905 }
3906
e8711085
AV		 3907 /* Get memory for cached NVRAM */
3908 ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL);
3909 if (!ha->nvram)
a9083016 3910 goto fail_free_ctx_mempool;
e8711085 3911
e315cd28
AC		 3912 snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME,
3913 ha->pdev->device);
3914 ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3915 DMA_POOL_SIZE, 8, 0);
3916 if (!ha->s_dma_pool)
3917 goto fail_free_nvram;
3918
7c3df132
SK		 3919 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022,
3920 "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n",
3921 ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool);
3922
7ec0effd 3923 if (IS_P3P_TYPE(ha) || ql2xenabledif) {
a9083016
GM		 3924 ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3925 DSD_LIST_DMA_POOL_SIZE, 8, 0);
3926 if (!ha->dl_dma_pool) {
7c3df132
SK		 3927 ql_log_pci(ql_log_fatal, ha->pdev, 0x0023,
3928 "Failed to allocate memory for dl_dma_pool.\n");
a9083016
GM		 3929 goto fail_s_dma_pool;
3930 }
3931
3932 ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3933 FCP_CMND_DMA_POOL_SIZE, 8, 0);
3934 if (!ha->fcp_cmnd_dma_pool) {
7c3df132
SK		 3935 ql_log_pci(ql_log_fatal, ha->pdev, 0x0024,
3936 "Failed to allocate memory for fcp_cmnd_dma_pool.\n");
a9083016
GM		 3937 goto fail_dl_dma_pool;
3938 }
7c3df132
SK		 3939 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025,
3940 "dl_dma_pool=%p fcp_cmnd_dma_pool=%p.\n",
3941 ha->dl_dma_pool, ha->fcp_cmnd_dma_pool);
a9083016
GM		 3942 }
3943
e8711085
AV		 3944 /* Allocate memory for SNS commands */
3945 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
e315cd28 3946 /* Get consistent memory allocated for SNS commands */
e8711085 3947 ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev,
e315cd28 3948 sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL);
e8711085 3949 if (!ha->sns_cmd)
e315cd28 3950 goto fail_dma_pool;
7c3df132 3951 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026,
d8424f68 3952 "sns_cmd: %p.\n", ha->sns_cmd);
e8711085 3953 } else {
e315cd28 3954 /* Get consistent memory allocated for MS IOCB */
e8711085 3955 ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
e315cd28 3956 &ha->ms_iocb_dma);
e8711085 3957 if (!ha->ms_iocb)
e315cd28
AC		 3958 goto fail_dma_pool;
3959 /* Get consistent memory allocated for CT SNS commands */
e8711085 3960 ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev,
e315cd28 3961 sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL);
e8711085
AV		 3962 if (!ha->ct_sns)
3963 goto fail_free_ms_iocb;
7c3df132
SK		 3964 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027,
3965 "ms_iocb=%p ct_sns=%p.\n",
3966 ha->ms_iocb, ha->ct_sns);
1da177e4
LT		 3967 }
3968
e315cd28 3969 /* Allocate memory for request ring */
73208dfd
AC		 3970 *req = kzalloc(sizeof(struct req_que), GFP_KERNEL);
3971 if (!*req) {
7c3df132
SK		 3972 ql_log_pci(ql_log_fatal, ha->pdev, 0x0028,
3973 "Failed to allocate memory for req.\n");
e315cd28
AC		 3974 goto fail_req;
3975 }
73208dfd
AC		 3976 (*req)->length = req_len;
3977 (*req)->ring = dma_alloc_coherent(&ha->pdev->dev,
3978 ((*req)->length + 1) * sizeof(request_t),
3979 &(*req)->dma, GFP_KERNEL);
3980 if (!(*req)->ring) {
7c3df132
SK		 3981 ql_log_pci(ql_log_fatal, ha->pdev, 0x0029,
3982 "Failed to allocate memory for req_ring.\n");
e315cd28
AC		 3983 goto fail_req_ring;
3984 }
3985 /* Allocate memory for response ring */
73208dfd
AC		 3986 *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL);
3987 if (!*rsp) {
7c3df132
SK		 3988 ql_log_pci(ql_log_fatal, ha->pdev, 0x002a,
3989 "Failed to allocate memory for rsp.\n");
e315cd28
AC		 3990 goto fail_rsp;
3991 }
73208dfd
AC		 3992 (*rsp)->hw = ha;
3993 (*rsp)->length = rsp_len;
3994 (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev,
3995 ((*rsp)->length + 1) * sizeof(response_t),
3996 &(*rsp)->dma, GFP_KERNEL);
3997 if (!(*rsp)->ring) {
7c3df132
SK		 3998 ql_log_pci(ql_log_fatal, ha->pdev, 0x002b,
3999 "Failed to allocate memory for rsp_ring.\n");
e315cd28
AC		 4000 goto fail_rsp_ring;
4001 }
73208dfd
AC		 4002 (*req)->rsp = *rsp;
4003 (*rsp)->req = *req;
7c3df132
SK		 4004 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c,
4005 "req=%p req->length=%d req->ring=%p rsp=%p "
4006 "rsp->length=%d rsp->ring=%p.\n",
4007 *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length,
4008 (*rsp)->ring);
73208dfd
AC		 4009 /* Allocate memory for NVRAM data for vports */
4010 if (ha->nvram_npiv_size) {
4011 ha->npiv_info = kzalloc(sizeof(struct qla_npiv_entry) *
7c3df132 4012 ha->nvram_npiv_size, GFP_KERNEL);
73208dfd 4013 if (!ha->npiv_info) {
7c3df132
SK		 4014 ql_log_pci(ql_log_fatal, ha->pdev, 0x002d,
4015 "Failed to allocate memory for npiv_info.\n");
73208dfd
AC		 4016 goto fail_npiv_info;
4017 }
4018 } else
4019 ha->npiv_info = NULL;
e8711085 4020
b64b0e8f 4021 /* Get consistent memory allocated for EX-INIT-CB. */
f73cb695 4022 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha)) {
b64b0e8f
AV		 4023 ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
4024 &ha->ex_init_cb_dma);
4025 if (!ha->ex_init_cb)
4026 goto fail_ex_init_cb;
7c3df132
SK		 4027 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e,
4028 "ex_init_cb=%p.\n", ha->ex_init_cb);
b64b0e8f
AV		 4029 }
4030
a9083016
GM		 4031 INIT_LIST_HEAD(&ha->gbl_dsd_list);
4032
5ff1d584
AV		 4033 /* Get consistent memory allocated for Async Port-Database. */
4034 if (!IS_FWI2_CAPABLE(ha)) {
4035 ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
4036 &ha->async_pd_dma);
4037 if (!ha->async_pd)
4038 goto fail_async_pd;
7c3df132
SK		 4039 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f,
4040 "async_pd=%p.\n", ha->async_pd);
5ff1d584
AV		 4041 }
4042
e315cd28 4043 INIT_LIST_HEAD(&ha->vp_list);
5f16b331
CD		 4044
4045 /* Allocate memory for our loop_id bitmap */
4046 ha->loop_id_map = kzalloc(BITS_TO_LONGS(LOOPID_MAP_SIZE) * sizeof(long),
4047 GFP_KERNEL);
4048 if (!ha->loop_id_map)
fc1ffd6c 4049 goto fail_loop_id_map;
5f16b331
CD		 4050 else {
4051 qla2x00_set_reserved_loop_ids(ha);
4052 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0123,
b2a72ec3 4053 "loop_id_map=%p.\n", ha->loop_id_map);
5f16b331
CD		 4054 }
4055
e4e3a2ce
QT		 4056 ha->sfp_data = dma_alloc_coherent(&ha->pdev->dev,
4057 SFP_DEV_SIZE, &ha->sfp_data_dma, GFP_KERNEL);
4058 if (!ha->sfp_data) {
4059 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b,
4060 "Unable to allocate memory for SFP read-data.\n");
4061 goto fail_sfp_data;
4062 }
4063
b2a72ec3 4064 return 0;
e315cd28 4065
e4e3a2ce
QT		 4066fail_sfp_data:
4067 kfree(ha->loop_id_map);
fc1ffd6c
QT		 4068fail_loop_id_map:
4069 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
5ff1d584
AV		 4070fail_async_pd:
4071 dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma);
b64b0e8f
AV		 4072fail_ex_init_cb:
4073 kfree(ha->npiv_info);
73208dfd
AC		 4074fail_npiv_info:
4075 dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) *
4076 sizeof(response_t), (*rsp)->ring, (*rsp)->dma);
4077 (*rsp)->ring = NULL;
4078 (*rsp)->dma = 0;
e315cd28 4079fail_rsp_ring:
73208dfd 4080 kfree(*rsp);
e315cd28 4081fail_rsp:
73208dfd
AC		 4082 dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) *
4083 sizeof(request_t), (*req)->ring, (*req)->dma);
4084 (*req)->ring = NULL;
4085 (*req)->dma = 0;
e315cd28 4086fail_req_ring:
73208dfd 4087 kfree(*req);
e315cd28
AC		 4088fail_req:
4089 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
4090 ha->ct_sns, ha->ct_sns_dma);
4091 ha->ct_sns = NULL;
4092 ha->ct_sns_dma = 0;
e8711085
AV		 4093fail_free_ms_iocb:
4094 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
4095 ha->ms_iocb = NULL;
4096 ha->ms_iocb_dma = 0;
fc1ffd6c
QT		 4097
4098 if (ha->sns_cmd)
4099 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
4100 ha->sns_cmd, ha->sns_cmd_dma);
e315cd28 4101fail_dma_pool:
bad75002 4102 if (IS_QLA82XX(ha) || ql2xenabledif) {
a9083016
GM		 4103 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
4104 ha->fcp_cmnd_dma_pool = NULL;
4105 }
4106fail_dl_dma_pool:
bad75002 4107 if (IS_QLA82XX(ha) || ql2xenabledif) {
a9083016
GM		 4108 dma_pool_destroy(ha->dl_dma_pool);
4109 ha->dl_dma_pool = NULL;
4110 }
4111fail_s_dma_pool:
e315cd28
AC		 4112 dma_pool_destroy(ha->s_dma_pool);
4113 ha->s_dma_pool = NULL;
e8711085
AV		 4114fail_free_nvram:
4115 kfree(ha->nvram);
4116 ha->nvram = NULL;
a9083016 4117fail_free_ctx_mempool:
fc1ffd6c
QT		 4118 if (ha->ctx_mempool)
4119 mempool_destroy(ha->ctx_mempool);
a9083016 4120 ha->ctx_mempool = NULL;
e8711085 4121fail_free_srb_mempool:
fc1ffd6c
QT		 4122 if (ha->srb_mempool)
4123 mempool_destroy(ha->srb_mempool);
e8711085 4124 ha->srb_mempool = NULL;
e8711085 4125fail_free_gid_list:
642ef983
CD		 4126 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
4127 ha->gid_list,
e315cd28 4128 ha->gid_list_dma);
e8711085
AV		 4129 ha->gid_list = NULL;
4130 ha->gid_list_dma = 0;
2d70c103
NB		 4131fail_free_tgt_mem:
4132 qlt_mem_free(ha);
e315cd28
AC		 4133fail_free_init_cb:
4134 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb,
4135 ha->init_cb_dma);
4136 ha->init_cb = NULL;
4137 ha->init_cb_dma = 0;
e8711085 4138fail:
7c3df132
SK		 4139 ql_log(ql_log_fatal, NULL, 0x0030,
4140 "Memory allocation failure.\n");
e8711085 4141 return -ENOMEM;
1da177e4
LT		 4142}
4143
b0d6cabd
HM		 4144int
4145qla2x00_set_exlogins_buffer(scsi_qla_host_t *vha)
4146{
4147 int rval;
4148 uint16_t size, max_cnt, temp;
4149 struct qla_hw_data *ha = vha->hw;
4150
4151 /* Return if we don't need to alloacate any extended logins */
4152 if (!ql2xexlogins)
4153 return QLA_SUCCESS;
4154
99e1b683
QT		 4155 if (!IS_EXLOGIN_OFFLD_CAPABLE(ha))
4156 return QLA_SUCCESS;
4157
b0d6cabd
HM		 4158 ql_log(ql_log_info, vha, 0xd021, "EXLOGIN count: %d.\n", ql2xexlogins);
4159 max_cnt = 0;
4160 rval = qla_get_exlogin_status(vha, &size, &max_cnt);
4161 if (rval != QLA_SUCCESS) {
4162 ql_log_pci(ql_log_fatal, ha->pdev, 0xd029,
4163 "Failed to get exlogin status.\n");
4164 return rval;
4165 }
4166
4167 temp = (ql2xexlogins > max_cnt) ? max_cnt : ql2xexlogins;
99e1b683
QT		 4168 temp *= size;
4169
4170 if (temp != ha->exlogin_size) {
4171 qla2x00_free_exlogin_buffer(ha);
4172 ha->exlogin_size = temp;
4173
4174 ql_log(ql_log_info, vha, 0xd024,
4175 "EXLOGIN: max_logins=%d, portdb=0x%x, total=%d.\n",
4176 max_cnt, size, temp);
4177
4178 ql_log(ql_log_info, vha, 0xd025,
4179 "EXLOGIN: requested size=0x%x\n", ha->exlogin_size);
4180
4181 /* Get consistent memory for extended logins */
4182 ha->exlogin_buf = dma_alloc_coherent(&ha->pdev->dev,
4183 ha->exlogin_size, &ha->exlogin_buf_dma, GFP_KERNEL);
4184 if (!ha->exlogin_buf) {
4185 ql_log_pci(ql_log_fatal, ha->pdev, 0xd02a,
b0d6cabd 4186 "Failed to allocate memory for exlogin_buf_dma.\n");
99e1b683
QT		 4187 return -ENOMEM;
4188 }
b0d6cabd
HM		 4189 }
4190
4191 /* Now configure the dma buffer */
4192 rval = qla_set_exlogin_mem_cfg(vha, ha->exlogin_buf_dma);
4193 if (rval) {
83548fe2 4194 ql_log(ql_log_fatal, vha, 0xd033,
b0d6cabd
HM		 4195 "Setup extended login buffer ****FAILED****.\n");
4196 qla2x00_free_exlogin_buffer(ha);
4197 }
4198
4199 return rval;
4200}
4201
4202/*
4203* qla2x00_free_exlogin_buffer
4204*
4205* Input:
4206* ha = adapter block pointer
4207*/
4208void
4209qla2x00_free_exlogin_buffer(struct qla_hw_data *ha)
4210{
4211 if (ha->exlogin_buf) {
4212 dma_free_coherent(&ha->pdev->dev, ha->exlogin_size,
4213 ha->exlogin_buf, ha->exlogin_buf_dma);
4214 ha->exlogin_buf = NULL;
4215 ha->exlogin_size = 0;
4216 }
4217}
4218
99e1b683
QT		 4219static void
4220qla2x00_number_of_exch(scsi_qla_host_t *vha, u32 *ret_cnt, u16 max_cnt)
4221{
4222 u32 temp;
4223 *ret_cnt = FW_DEF_EXCHANGES_CNT;
4224
4225 if (qla_ini_mode_enabled(vha)) {
4226 if (ql2xiniexchg > max_cnt)
4227 ql2xiniexchg = max_cnt;
4228
4229 if (ql2xiniexchg > FW_DEF_EXCHANGES_CNT)
4230 *ret_cnt = ql2xiniexchg;
4231 } else if (qla_tgt_mode_enabled(vha)) {
4232 if (ql2xexchoffld > max_cnt)
4233 ql2xexchoffld = max_cnt;
4234
4235 if (ql2xexchoffld > FW_DEF_EXCHANGES_CNT)
4236 *ret_cnt = ql2xexchoffld;
4237 } else if (qla_dual_mode_enabled(vha)) {
4238 temp = ql2xiniexchg + ql2xexchoffld;
4239 if (temp > max_cnt) {
4240 ql2xiniexchg -= (temp - max_cnt)/2;
4241 ql2xexchoffld -= (((temp - max_cnt)/2) + 1);
4242 temp = max_cnt;
4243 }
4244
4245 if (temp > FW_DEF_EXCHANGES_CNT)
4246 *ret_cnt = temp;
4247 }
4248}
4249
2f56a7f1
HM		 4250int
4251qla2x00_set_exchoffld_buffer(scsi_qla_host_t *vha)
4252{
4253 int rval;
99e1b683
QT		 4254 u16 size, max_cnt;
4255 u32 temp;
2f56a7f1
HM		 4256 struct qla_hw_data *ha = vha->hw;
4257
99e1b683
QT		 4258 if (!ha->flags.exchoffld_enabled)
4259 return QLA_SUCCESS;
4260
4261 if (!IS_EXCHG_OFFLD_CAPABLE(ha))
2f56a7f1
HM		 4262 return QLA_SUCCESS;
4263
2f56a7f1
HM		 4264 max_cnt = 0;
4265 rval = qla_get_exchoffld_status(vha, &size, &max_cnt);
4266 if (rval != QLA_SUCCESS) {
4267 ql_log_pci(ql_log_fatal, ha->pdev, 0xd012,
4268 "Failed to get exlogin status.\n");
4269 return rval;
4270 }
4271
99e1b683
QT		 4272 qla2x00_number_of_exch(vha, &temp, max_cnt);
4273 temp *= size;
2f56a7f1 4274
99e1b683
QT		 4275 if (temp != ha->exchoffld_size) {
4276 qla2x00_free_exchoffld_buffer(ha);
4277 ha->exchoffld_size = temp;
4278
4279 ql_log(ql_log_info, vha, 0xd016,
4280 "Exchange offload: max_count=%d, buffers=0x%x, total=%d.\n",
4281 max_cnt, size, temp);
4282
4283 ql_log(ql_log_info, vha, 0xd017,
4284 "Exchange Buffers requested size = 0x%x\n",
4285 ha->exchoffld_size);
4286
4287 /* Get consistent memory for extended logins */
4288 ha->exchoffld_buf = dma_alloc_coherent(&ha->pdev->dev,
4289 ha->exchoffld_size, &ha->exchoffld_buf_dma, GFP_KERNEL);
4290 if (!ha->exchoffld_buf) {
4291 ql_log_pci(ql_log_fatal, ha->pdev, 0xd013,
4292 "Failed to allocate memory for exchoffld_buf_dma.\n");
4293 return -ENOMEM;
4294 }
2f56a7f1
HM		 4295 }
4296
4297 /* Now configure the dma buffer */
99e1b683 4298 rval = qla_set_exchoffld_mem_cfg(vha);
2f56a7f1
HM		 4299 if (rval) {
4300 ql_log(ql_log_fatal, vha, 0xd02e,
4301 "Setup exchange offload buffer ****FAILED****.\n");
4302 qla2x00_free_exchoffld_buffer(ha);
99e1b683
QT		 4303 } else {
4304 /* re-adjust number of target exchange */
4305 struct init_cb_81xx *icb = (struct init_cb_81xx *)ha->init_cb;
4306
4307 if (qla_ini_mode_enabled(vha))
4308 icb->exchange_count = 0;
4309 else
4310 icb->exchange_count = cpu_to_le16(ql2xexchoffld);
2f56a7f1
HM		 4311 }
4312
4313 return rval;
4314}
4315
4316/*
4317* qla2x00_free_exchoffld_buffer
4318*
4319* Input:
4320* ha = adapter block pointer
4321*/
4322void
4323qla2x00_free_exchoffld_buffer(struct qla_hw_data *ha)
4324{
4325 if (ha->exchoffld_buf) {
4326 dma_free_coherent(&ha->pdev->dev, ha->exchoffld_size,
4327 ha->exchoffld_buf, ha->exchoffld_buf_dma);
4328 ha->exchoffld_buf = NULL;
4329 ha->exchoffld_size = 0;
4330 }
4331}
4332
1da177e4 4333/*
e30d1756
MI		 4334* qla2x00_free_fw_dump
4335* Frees fw dump stuff.
1da177e4
LT		 4336*
4337* Input:
7ec0effd 4338* ha = adapter block pointer
1da177e4 4339*/
a824ebb3 4340static void
e30d1756 4341qla2x00_free_fw_dump(struct qla_hw_data *ha)
1da177e4 4342{
df613b96 4343 if (ha->fce)
f73cb695
CD		 4344 dma_free_coherent(&ha->pdev->dev,
4345 FCE_SIZE, ha->fce, ha->fce_dma);
df613b96 4346
f73cb695
CD		 4347 if (ha->eft)
4348 dma_free_coherent(&ha->pdev->dev,
4349 EFT_SIZE, ha->eft, ha->eft_dma);
4350
4351 if (ha->fw_dump)
a7a167bf 4352 vfree(ha->fw_dump);
f73cb695
CD		 4353 if (ha->fw_dump_template)
4354 vfree(ha->fw_dump_template);
4355
e30d1756
MI		 4356 ha->fce = NULL;
4357 ha->fce_dma = 0;
4358 ha->eft = NULL;
4359 ha->eft_dma = 0;
e30d1756 4360 ha->fw_dumped = 0;
61f098dd 4361 ha->fw_dump_cap_flags = 0;
e30d1756 4362 ha->fw_dump_reading = 0;
f73cb695
CD		 4363 ha->fw_dump = NULL;
4364 ha->fw_dump_len = 0;
4365 ha->fw_dump_template = NULL;
4366 ha->fw_dump_template_len = 0;
e30d1756
MI		 4367}
4368
4369/*
4370* qla2x00_mem_free
4371* Frees all adapter allocated memory.
4372*
4373* Input:
4374* ha = adapter block pointer.
4375*/
4376static void
4377qla2x00_mem_free(struct qla_hw_data *ha)
4378{
4379 qla2x00_free_fw_dump(ha);
4380
81178772
SK		 4381 if (ha->mctp_dump)
4382 dma_free_coherent(&ha->pdev->dev, MCTP_DUMP_SIZE, ha->mctp_dump,
4383 ha->mctp_dump_dma);
4384
e30d1756
MI		 4385 if (ha->srb_mempool)
4386 mempool_destroy(ha->srb_mempool);
a7a167bf 4387
11bbc1d8
AV		 4388 if (ha->dcbx_tlv)
4389 dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE,
4390 ha->dcbx_tlv, ha->dcbx_tlv_dma);
4391
ce0423f4
AV		 4392 if (ha->xgmac_data)
4393 dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE,
4394 ha->xgmac_data, ha->xgmac_data_dma);
4395
1da177e4
LT		 4396 if (ha->sns_cmd)
4397 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
e315cd28 4398 ha->sns_cmd, ha->sns_cmd_dma);
1da177e4
LT		 4399
4400 if (ha->ct_sns)
4401 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
e315cd28 4402 ha->ct_sns, ha->ct_sns_dma);
1da177e4 4403
88729e53 4404 if (ha->sfp_data)
e4e3a2ce
QT		 4405 dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE, ha->sfp_data,
4406 ha->sfp_data_dma);
88729e53 4407
1da177e4
LT		 4408 if (ha->ms_iocb)
4409 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
4410
b64b0e8f 4411 if (ha->ex_init_cb)
a9083016
GM		 4412 dma_pool_free(ha->s_dma_pool,
4413 ha->ex_init_cb, ha->ex_init_cb_dma);
b64b0e8f 4414
5ff1d584
AV		 4415 if (ha->async_pd)
4416 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
4417
1da177e4
LT		 4418 if (ha->s_dma_pool)
4419 dma_pool_destroy(ha->s_dma_pool);
4420
1da177e4 4421 if (ha->gid_list)
642ef983
CD		 4422 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
4423 ha->gid_list, ha->gid_list_dma);
1da177e4 4424
a9083016
GM		 4425 if (IS_QLA82XX(ha)) {
4426 if (!list_empty(&ha->gbl_dsd_list)) {
4427 struct dsd_dma *dsd_ptr, *tdsd_ptr;
4428
4429 /* clean up allocated prev pool */
4430 list_for_each_entry_safe(dsd_ptr,
4431 tdsd_ptr, &ha->gbl_dsd_list, list) {
4432 dma_pool_free(ha->dl_dma_pool,
4433 dsd_ptr->dsd_addr, dsd_ptr->dsd_list_dma);
4434 list_del(&dsd_ptr->list);
4435 kfree(dsd_ptr);
4436 }
4437 }
4438 }
4439
4440 if (ha->dl_dma_pool)
4441 dma_pool_destroy(ha->dl_dma_pool);
4442
4443 if (ha->fcp_cmnd_dma_pool)
4444 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
4445
4446 if (ha->ctx_mempool)
4447 mempool_destroy(ha->ctx_mempool);
4448
2d70c103
NB		 4449 qlt_mem_free(ha);
4450
e315cd28
AC		 4451 if (ha->init_cb)
4452 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size,
a9083016 4453 ha->init_cb, ha->init_cb_dma);
e315cd28
AC		 4454 vfree(ha->optrom_buffer);
4455 kfree(ha->nvram);
73208dfd 4456 kfree(ha->npiv_info);
7a67735b 4457 kfree(ha->swl);
5f16b331 4458 kfree(ha->loop_id_map);
1da177e4 4459
e8711085 4460 ha->srb_mempool = NULL;
a9083016 4461 ha->ctx_mempool = NULL;
1da177e4
LT		 4462 ha->sns_cmd = NULL;
4463 ha->sns_cmd_dma = 0;
4464 ha->ct_sns = NULL;
4465 ha->ct_sns_dma = 0;
4466 ha->ms_iocb = NULL;
4467 ha->ms_iocb_dma = 0;
1da177e4
LT		 4468 ha->init_cb = NULL;
4469 ha->init_cb_dma = 0;
b64b0e8f
AV		 4470 ha->ex_init_cb = NULL;
4471 ha->ex_init_cb_dma = 0;
5ff1d584
AV		 4472 ha->async_pd = NULL;
4473 ha->async_pd_dma = 0;
1da177e4
LT		 4474
4475 ha->s_dma_pool = NULL;
a9083016
GM		 4476 ha->dl_dma_pool = NULL;
4477 ha->fcp_cmnd_dma_pool = NULL;
1da177e4 4478
1da177e4
LT		 4479 ha->gid_list = NULL;
4480 ha->gid_list_dma = 0;
2d70c103
NB		 4481
4482 ha->tgt.atio_ring = NULL;
4483 ha->tgt.atio_dma = 0;
4484 ha->tgt.tgt_vp_map = NULL;
e315cd28 4485}
1da177e4 4486
e315cd28
AC		 4487struct scsi_qla_host *qla2x00_create_host(struct scsi_host_template *sht,
4488 struct qla_hw_data *ha)
4489{
4490 struct Scsi_Host *host;
4491 struct scsi_qla_host *vha = NULL;
854165f4 4492
e315cd28 4493 host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t));
41dc529a 4494 if (!host) {
7c3df132
SK		 4495 ql_log_pci(ql_log_fatal, ha->pdev, 0x0107,
4496 "Failed to allocate host from the scsi layer, aborting.\n");
41dc529a 4497 return NULL;
e315cd28
AC		 4498 }
4499
4500 /* Clear our data area */
4501 vha = shost_priv(host);
4502 memset(vha, 0, sizeof(scsi_qla_host_t));
4503
4504 vha->host = host;
4505 vha->host_no = host->host_no;
4506 vha->hw = ha;
4507
4508 INIT_LIST_HEAD(&vha->vp_fcports);
4509 INIT_LIST_HEAD(&vha->work_list);
4510 INIT_LIST_HEAD(&vha->list);
8b2f5ff3
SN		 4511 INIT_LIST_HEAD(&vha->qla_cmd_list);
4512 INIT_LIST_HEAD(&vha->qla_sess_op_cmd_list);
71cdc079 4513 INIT_LIST_HEAD(&vha->logo_list);
b7bd104e 4514 INIT_LIST_HEAD(&vha->plogi_ack_list);
d7459527 4515 INIT_LIST_HEAD(&vha->qp_list);
41dc529a 4516 INIT_LIST_HEAD(&vha->gnl.fcports);
a5d42f4c 4517 INIT_LIST_HEAD(&vha->nvme_rport_list);
e315cd28 4518
f999f4c1 4519 spin_lock_init(&vha->work_lock);
8b2f5ff3 4520 spin_lock_init(&vha->cmd_list_lock);
726b8548 4521 init_waitqueue_head(&vha->fcport_waitQ);
c4a9b538 4522 init_waitqueue_head(&vha->vref_waitq);
f999f4c1 4523
2fdbc65e
BVA		 4524 vha->gnl.size = sizeof(struct get_name_list_extended) *
4525 (ha->max_loop_id + 1);
41dc529a
QT		 4526 vha->gnl.l = dma_alloc_coherent(&ha->pdev->dev,
4527 vha->gnl.size, &vha->gnl.ldma, GFP_KERNEL);
4528 if (!vha->gnl.l) {
83548fe2 4529 ql_log(ql_log_fatal, vha, 0xd04a,
41dc529a
QT		 4530 "Alloc failed for name list.\n");
4531 scsi_remove_host(vha->host);
4532 return NULL;
4533 }
f999f4c1 4534
e315cd28 4535 sprintf(vha->host_str, "%s_%ld", QLA2XXX_DRIVER_NAME, vha->host_no);
7c3df132
SK		 4536 ql_dbg(ql_dbg_init, vha, 0x0041,
4537 "Allocated the host=%p hw=%p vha=%p dev_name=%s",
4538 vha->host, vha->hw, vha,
4539 dev_name(&(ha->pdev->dev)));
4540
e315cd28 4541 return vha;
1da177e4
LT		 4542}
4543
726b8548 4544struct qla_work_evt *
f999f4c1 4545qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type)
0971de7f
AV		 4546{
4547 struct qla_work_evt *e;
feafb7b1
AE		 4548 uint8_t bail;
4549
4550 QLA_VHA_MARK_BUSY(vha, bail);
4551 if (bail)
4552 return NULL;
0971de7f 4553
f999f4c1 4554 e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC);
feafb7b1
AE		 4555 if (!e) {
4556 QLA_VHA_MARK_NOT_BUSY(vha);
0971de7f 4557 return NULL;
feafb7b1 4558 }
0971de7f
AV		 4559
4560 INIT_LIST_HEAD(&e->list);
4561 e->type = type;
4562 e->flags = QLA_EVT_FLAG_FREE;
4563 return e;
4564}
4565
726b8548 4566int
f999f4c1 4567qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e)
0971de7f 4568{
f999f4c1 4569 unsigned long flags;
0971de7f 4570
f999f4c1 4571 spin_lock_irqsave(&vha->work_lock, flags);
e315cd28 4572 list_add_tail(&e->list, &vha->work_list);
f999f4c1 4573 spin_unlock_irqrestore(&vha->work_lock, flags);
ec7193e2
QT		 4574
4575 if (QLA_EARLY_LINKUP(vha->hw))
4576 schedule_work(&vha->iocb_work);
4577 else
4578 qla2xxx_wake_dpc(vha);
f999f4c1 4579
0971de7f
AV		 4580 return QLA_SUCCESS;
4581}
4582
4583int
e315cd28 4584qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code,
0971de7f
AV		 4585 u32 data)
4586{
4587 struct qla_work_evt *e;
4588
f999f4c1 4589 e = qla2x00_alloc_work(vha, QLA_EVT_AEN);
0971de7f
AV		 4590 if (!e)
4591 return QLA_FUNCTION_FAILED;
4592
4593 e->u.aen.code = code;
4594 e->u.aen.data = data;
f999f4c1 4595 return qla2x00_post_work(vha, e);
0971de7f
AV		 4596}
4597
8a659571
AV		 4598int
4599qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb)
4600{
4601 struct qla_work_evt *e;
4602
f999f4c1 4603 e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK);
8a659571
AV		 4604 if (!e)
4605 return QLA_FUNCTION_FAILED;
4606
4607 memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t));
f999f4c1 4608 return qla2x00_post_work(vha, e);
8a659571
AV		 4609}
4610
ac280b67
AV		 4611#define qla2x00_post_async_work(name, type) \
4612int qla2x00_post_async_##name##_work( \
4613 struct scsi_qla_host *vha, \
4614 fc_port_t *fcport, uint16_t *data) \
4615{ \
4616 struct qla_work_evt *e; \
4617 \
4618 e = qla2x00_alloc_work(vha, type); \
4619 if (!e) \
4620 return QLA_FUNCTION_FAILED; \
4621 \
4622 e->u.logio.fcport = fcport; \
4623 if (data) { \
4624 e->u.logio.data[0] = data[0]; \
4625 e->u.logio.data[1] = data[1]; \
4626 } \
4627 return qla2x00_post_work(vha, e); \
4628}
4629
4630qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN);
ac280b67
AV		 4631qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT);
4632qla2x00_post_async_work(logout_done, QLA_EVT_ASYNC_LOGOUT_DONE);
5ff1d584
AV		 4633qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC);
4634qla2x00_post_async_work(adisc_done, QLA_EVT_ASYNC_ADISC_DONE);
ac280b67 4635
3420d36c
AV		 4636int
4637qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code)
4638{
4639 struct qla_work_evt *e;
4640
4641 e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT);
4642 if (!e)
4643 return QLA_FUNCTION_FAILED;
4644
4645 e->u.uevent.code = code;
4646 return qla2x00_post_work(vha, e);
4647}
4648
4649static void
4650qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code)
4651{
4652 char event_string[40];
4653 char *envp[] = { event_string, NULL };
4654
4655 switch (code) {
4656 case QLA_UEVENT_CODE_FW_DUMP:
4657 snprintf(event_string, sizeof(event_string), "FW_DUMP=%ld",
4658 vha->host_no);
4659 break;
4660 default:
4661 /* do nothing */
4662 break;
4663 }
4664 kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp);
4665}
4666
8ae6d9c7
GM		 4667int
4668qlafx00_post_aenfx_work(struct scsi_qla_host *vha, uint32_t evtcode,
4669 uint32_t *data, int cnt)
4670{
4671 struct qla_work_evt *e;
4672
4673 e = qla2x00_alloc_work(vha, QLA_EVT_AENFX);
4674 if (!e)
4675 return QLA_FUNCTION_FAILED;
4676
4677 e->u.aenfx.evtcode = evtcode;
4678 e->u.aenfx.count = cnt;
4679 memcpy(e->u.aenfx.mbx, data, sizeof(*data) * cnt);
4680 return qla2x00_post_work(vha, e);
4681}
4682
726b8548
QT		 4683int qla24xx_post_upd_fcport_work(struct scsi_qla_host *vha, fc_port_t *fcport)
4684{
4685 struct qla_work_evt *e;
4686
4687 e = qla2x00_alloc_work(vha, QLA_EVT_UPD_FCPORT);
4688 if (!e)
4689 return QLA_FUNCTION_FAILED;
4690
4691 e->u.fcport.fcport = fcport;
4692 return qla2x00_post_work(vha, e);
4693}
4694
4695static
4696void qla24xx_create_new_sess(struct scsi_qla_host *vha, struct qla_work_evt *e)
4697{
4698 unsigned long flags;
b5d15312 4699 fc_port_t *fcport = NULL, *tfcp;
726b8548
QT		 4700 struct qlt_plogi_ack_t *pla =
4701 (struct qlt_plogi_ack_t *)e->u.new_sess.pla;
b5d15312 4702 uint8_t free_fcport = 0;
726b8548
QT		 4703
4704 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
4705 fcport = qla2x00_find_fcport_by_wwpn(vha, e->u.new_sess.port_name, 1);
4706 if (fcport) {
4707 fcport->d_id = e->u.new_sess.id;
4708 if (pla) {
4709 fcport->fw_login_state = DSC_LS_PLOGI_PEND;
4710 qlt_plogi_ack_link(vha, pla, fcport, QLT_PLOGI_LINK_SAME_WWN);
4711 /* we took an extra ref_count to prevent PLOGI ACK when
4712 * fcport/sess has not been created.
4713 */
4714 pla->ref_count--;
4715 }
4716 } else {
b5d15312 4717 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
726b8548
QT		 4718 fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
4719 if (fcport) {
4720 fcport->d_id = e->u.new_sess.id;
4721 fcport->scan_state = QLA_FCPORT_FOUND;
4722 fcport->flags |= FCF_FABRIC_DEVICE;
4723 fcport->fw_login_state = DSC_LS_PLOGI_PEND;
4724
4725 memcpy(fcport->port_name, e->u.new_sess.port_name,
4726 WWN_SIZE);
b5d15312
QT		 4727 } else {
4728 ql_dbg(ql_dbg_disc, vha, 0xffff,
4729 "%s %8phC mem alloc fail.\n",
4730 __func__, e->u.new_sess.port_name);
4731
4732 if (pla)
4733 kmem_cache_free(qla_tgt_plogi_cachep, pla);
4734 return;
4735 }
4736
4737 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
4738 /* search again to make sure one else got ahead */
4739 tfcp = qla2x00_find_fcport_by_wwpn(vha,
4740 e->u.new_sess.port_name, 1);
4741 if (tfcp) {
4742 /* should rarily happen */
4743 ql_dbg(ql_dbg_disc, vha, 0xffff,
4744 "%s %8phC found existing fcport b4 add. DS %d LS %d\n",
4745 __func__, tfcp->port_name, tfcp->disc_state,
4746 tfcp->fw_login_state);
4747
4748 free_fcport = 1;
4749 } else {
726b8548
QT		 4750 list_add_tail(&fcport->list, &vha->vp_fcports);
4751
4752 if (pla) {
4753 qlt_plogi_ack_link(vha, pla, fcport,
4754 QLT_PLOGI_LINK_SAME_WWN);
4755 pla->ref_count--;
4756 }
4757 }
4758 }
4759 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
4760
4761 if (fcport) {
4762 if (pla)
4763 qlt_plogi_ack_unref(vha, pla);
4764 else
2d57b5ef 4765 qla24xx_async_gffid(vha, fcport);
726b8548 4766 }
b5d15312
QT		 4767
4768 if (free_fcport) {
4769 qla2x00_free_fcport(fcport);
4770 if (pla)
4771 kmem_cache_free(qla_tgt_plogi_cachep, pla);
4772 }
726b8548
QT		 4773}
4774
ac280b67 4775void
e315cd28 4776qla2x00_do_work(struct scsi_qla_host *vha)
0971de7f 4777{
f999f4c1
AV		 4778 struct qla_work_evt *e, *tmp;
4779 unsigned long flags;
4780 LIST_HEAD(work);
0971de7f 4781
f999f4c1
AV		 4782 spin_lock_irqsave(&vha->work_lock, flags);
4783 list_splice_init(&vha->work_list, &work);
4784 spin_unlock_irqrestore(&vha->work_lock, flags);
4785
4786 list_for_each_entry_safe(e, tmp, &work, list) {
0971de7f 4787 list_del_init(&e->list);
0971de7f
AV		 4788
4789 switch (e->type) {
4790 case QLA_EVT_AEN:
e315cd28 4791 fc_host_post_event(vha->host, fc_get_event_number(),
0971de7f
AV		 4792 e->u.aen.code, e->u.aen.data);
4793 break;
8a659571
AV		 4794 case QLA_EVT_IDC_ACK:
4795 qla81xx_idc_ack(vha, e->u.idc_ack.mb);
4796 break;
ac280b67
AV		 4797 case QLA_EVT_ASYNC_LOGIN:
4798 qla2x00_async_login(vha, e->u.logio.fcport,
4799 e->u.logio.data);
4800 break;
ac280b67
AV		 4801 case QLA_EVT_ASYNC_LOGOUT:
4802 qla2x00_async_logout(vha, e->u.logio.fcport);
4803 break;
4804 case QLA_EVT_ASYNC_LOGOUT_DONE:
4805 qla2x00_async_logout_done(vha, e->u.logio.fcport,
4806 e->u.logio.data);
4807 break;
5ff1d584
AV		 4808 case QLA_EVT_ASYNC_ADISC:
4809 qla2x00_async_adisc(vha, e->u.logio.fcport,
4810 e->u.logio.data);
4811 break;
4812 case QLA_EVT_ASYNC_ADISC_DONE:
4813 qla2x00_async_adisc_done(vha, e->u.logio.fcport,
4814 e->u.logio.data);
4815 break;
3420d36c
AV		 4816 case QLA_EVT_UEVENT:
4817 qla2x00_uevent_emit(vha, e->u.uevent.code);
4818 break;
8ae6d9c7
GM		 4819 case QLA_EVT_AENFX:
4820 qlafx00_process_aen(vha, e);
4821 break;
726b8548
QT		 4822 case QLA_EVT_GIDPN:
4823 qla24xx_async_gidpn(vha, e->u.fcport.fcport);
4824 break;
4825 case QLA_EVT_GPNID:
4826 qla24xx_async_gpnid(vha, &e->u.gpnid.id);
4827 break;
4828 case QLA_EVT_GPNID_DONE:
4829 qla24xx_async_gpnid_done(vha, e->u.iosb.sp);
4830 break;
4831 case QLA_EVT_NEW_SESS:
4832 qla24xx_create_new_sess(vha, e);
4833 break;
4834 case QLA_EVT_GPDB:
4835 qla24xx_async_gpdb(vha, e->u.fcport.fcport,
4836 e->u.fcport.opt);
4837 break;
a5d42f4c
DG		 4838 case QLA_EVT_PRLI:
4839 qla24xx_async_prli(vha, e->u.fcport.fcport);
4840 break;
726b8548
QT		 4841 case QLA_EVT_GPSC:
4842 qla24xx_async_gpsc(vha, e->u.fcport.fcport);
4843 break;
4844 case QLA_EVT_UPD_FCPORT:
4845 qla2x00_update_fcport(vha, e->u.fcport.fcport);
4846 break;
4847 case QLA_EVT_GNL:
4848 qla24xx_async_gnl(vha, e->u.fcport.fcport);
4849 break;
4850 case QLA_EVT_NACK:
4851 qla24xx_do_nack_work(vha, e);
4852 break;
0971de7f
AV		 4853 }
4854 if (e->flags & QLA_EVT_FLAG_FREE)
4855 kfree(e);
feafb7b1
AE		 4856
4857 /* For each work completed decrement vha ref count */
4858 QLA_VHA_MARK_NOT_BUSY(vha);
e315cd28 4859 }
e315cd28 4860}
f999f4c1 4861
e315cd28
AC		 4862/* Relogins all the fcports of a vport
4863 * Context: dpc thread
4864 */
4865void qla2x00_relogin(struct scsi_qla_host *vha)
4866{
4867 fc_port_t *fcport;
c6b2fca8 4868 int status;
726b8548 4869 struct event_arg ea;
e315cd28
AC		 4870
4871 list_for_each_entry(fcport, &vha->vp_fcports, list) {
4872 /*
4873 * If the port is not ONLINE then try to login
4874 * to it if we haven't run out of retries.
4875 */
5ff1d584
AV		 4876 if (atomic_read(&fcport->state) != FCS_ONLINE &&
4877 fcport->login_retry && !(fcport->flags & FCF_ASYNC_SENT)) {
ac280b67 4878 fcport->login_retry--;
e315cd28 4879 if (fcport->flags & FCF_FABRIC_DEVICE) {
83548fe2 4880 ql_dbg(ql_dbg_disc, fcport->vha, 0x2108,
726b8548
QT		 4881 "%s %8phC DS %d LS %d\n", __func__,
4882 fcport->port_name, fcport->disc_state,
4883 fcport->fw_login_state);
4884 memset(&ea, 0, sizeof(ea));
4885 ea.event = FCME_RELOGIN;
4886 ea.fcport = fcport;
4887 qla2x00_fcport_event_handler(vha, &ea);
4888 } else {
e315cd28
AC		 4889 status = qla2x00_local_device_login(vha,
4890 fcport);
726b8548
QT		 4891 if (status == QLA_SUCCESS) {
4892 fcport->old_loop_id = fcport->loop_id;
4893 ql_dbg(ql_dbg_disc, vha, 0x2003,
4894 "Port login OK: logged in ID 0x%x.\n",
4895 fcport->loop_id);
4896 qla2x00_update_fcport(vha, fcport);
4897 } else if (status == 1) {
4898 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
4899 /* retry the login again */
4900 ql_dbg(ql_dbg_disc, vha, 0x2007,
4901 "Retrying %d login again loop_id 0x%x.\n",
4902 fcport->login_retry,
4903 fcport->loop_id);
4904 } else {
4905 fcport->login_retry = 0;
4906 }
e315cd28 4907
726b8548
QT		 4908 if (fcport->login_retry == 0 &&
4909 status != QLA_SUCCESS)
4910 qla2x00_clear_loop_id(fcport);
e315cd28 4911 }
e315cd28
AC		 4912 }
4913 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
4914 break;
0971de7f 4915 }
0971de7f
AV		 4916}
4917
7d613ac6
SV		 4918/* Schedule work on any of the dpc-workqueues */
4919void
4920qla83xx_schedule_work(scsi_qla_host_t *base_vha, int work_code)
4921{
4922 struct qla_hw_data *ha = base_vha->hw;
4923
4924 switch (work_code) {
4925 case MBA_IDC_AEN: /* 0x8200 */
4926 if (ha->dpc_lp_wq)
4927 queue_work(ha->dpc_lp_wq, &ha->idc_aen);
4928 break;
4929
4930 case QLA83XX_NIC_CORE_RESET: /* 0x1 */
4931 if (!ha->flags.nic_core_reset_hdlr_active) {
4932 if (ha->dpc_hp_wq)
4933 queue_work(ha->dpc_hp_wq, &ha->nic_core_reset);
4934 } else
4935 ql_dbg(ql_dbg_p3p, base_vha, 0xb05e,
4936 "NIC Core reset is already active. Skip "
4937 "scheduling it again.\n");
4938 break;
4939 case QLA83XX_IDC_STATE_HANDLER: /* 0x2 */
4940 if (ha->dpc_hp_wq)
4941 queue_work(ha->dpc_hp_wq, &ha->idc_state_handler);
4942 break;
4943 case QLA83XX_NIC_CORE_UNRECOVERABLE: /* 0x3 */
4944 if (ha->dpc_hp_wq)
4945 queue_work(ha->dpc_hp_wq, &ha->nic_core_unrecoverable);
4946 break;
4947 default:
4948 ql_log(ql_log_warn, base_vha, 0xb05f,
d939be3a 4949 "Unknown work-code=0x%x.\n", work_code);
7d613ac6
SV		 4950 }
4951
4952 return;
4953}
4954
4955/* Work: Perform NIC Core Unrecoverable state handling */
4956void
4957qla83xx_nic_core_unrecoverable_work(struct work_struct *work)
4958{
4959 struct qla_hw_data *ha =
2ad1b67c 4960 container_of(work, struct qla_hw_data, nic_core_unrecoverable);
7d613ac6
SV		 4961 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4962 uint32_t dev_state = 0;
4963
4964 qla83xx_idc_lock(base_vha, 0);
4965 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4966 qla83xx_reset_ownership(base_vha);
4967 if (ha->flags.nic_core_reset_owner) {
4968 ha->flags.nic_core_reset_owner = 0;
4969 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
4970 QLA8XXX_DEV_FAILED);
4971 ql_log(ql_log_info, base_vha, 0xb060, "HW State: FAILED.\n");
4972 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
4973 }
4974 qla83xx_idc_unlock(base_vha, 0);
4975}
4976
4977/* Work: Execute IDC state handler */
4978void
4979qla83xx_idc_state_handler_work(struct work_struct *work)
4980{
4981 struct qla_hw_data *ha =
2ad1b67c 4982 container_of(work, struct qla_hw_data, idc_state_handler);
7d613ac6
SV		 4983 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4984 uint32_t dev_state = 0;
4985
4986 qla83xx_idc_lock(base_vha, 0);
4987 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4988 if (dev_state == QLA8XXX_DEV_FAILED ||
4989 dev_state == QLA8XXX_DEV_NEED_QUIESCENT)
4990 qla83xx_idc_state_handler(base_vha);
4991 qla83xx_idc_unlock(base_vha, 0);
4992}
4993
fa492630 4994static int
7d613ac6
SV		 4995qla83xx_check_nic_core_fw_alive(scsi_qla_host_t *base_vha)
4996{
4997 int rval = QLA_SUCCESS;
4998 unsigned long heart_beat_wait = jiffies + (1 * HZ);
4999 uint32_t heart_beat_counter1, heart_beat_counter2;
5000
5001 do {
5002 if (time_after(jiffies, heart_beat_wait)) {
5003 ql_dbg(ql_dbg_p3p, base_vha, 0xb07c,
5004 "Nic Core f/w is not alive.\n");
5005 rval = QLA_FUNCTION_FAILED;
5006 break;
5007 }
5008
5009 qla83xx_idc_lock(base_vha, 0);
5010 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
5011 &heart_beat_counter1);
5012 qla83xx_idc_unlock(base_vha, 0);
5013 msleep(100);
5014 qla83xx_idc_lock(base_vha, 0);
5015 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
5016 &heart_beat_counter2);
5017 qla83xx_idc_unlock(base_vha, 0);
5018 } while (heart_beat_counter1 == heart_beat_counter2);
5019
5020 return rval;
5021}
5022
5023/* Work: Perform NIC Core Reset handling */
5024void
5025qla83xx_nic_core_reset_work(struct work_struct *work)
5026{
5027 struct qla_hw_data *ha =
5028 container_of(work, struct qla_hw_data, nic_core_reset);
5029 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5030 uint32_t dev_state = 0;
5031
81178772
SK		 5032 if (IS_QLA2031(ha)) {
5033 if (qla2xxx_mctp_dump(base_vha) != QLA_SUCCESS)
5034 ql_log(ql_log_warn, base_vha, 0xb081,
5035 "Failed to dump mctp\n");
5036 return;
5037 }
5038
7d613ac6
SV		 5039 if (!ha->flags.nic_core_reset_hdlr_active) {
5040 if (qla83xx_check_nic_core_fw_alive(base_vha) == QLA_SUCCESS) {
5041 qla83xx_idc_lock(base_vha, 0);
5042 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE,
5043 &dev_state);
5044 qla83xx_idc_unlock(base_vha, 0);
5045 if (dev_state != QLA8XXX_DEV_NEED_RESET) {
5046 ql_dbg(ql_dbg_p3p, base_vha, 0xb07a,
5047 "Nic Core f/w is alive.\n");
5048 return;
5049 }
5050 }
5051
5052 ha->flags.nic_core_reset_hdlr_active = 1;
5053 if (qla83xx_nic_core_reset(base_vha)) {
5054 /* NIC Core reset failed. */
5055 ql_dbg(ql_dbg_p3p, base_vha, 0xb061,
5056 "NIC Core reset failed.\n");
5057 }
5058 ha->flags.nic_core_reset_hdlr_active = 0;
5059 }
5060}
5061
5062/* Work: Handle 8200 IDC aens */
5063void
5064qla83xx_service_idc_aen(struct work_struct *work)
5065{
5066 struct qla_hw_data *ha =
5067 container_of(work, struct qla_hw_data, idc_aen);
5068 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5069 uint32_t dev_state, idc_control;
5070
5071 qla83xx_idc_lock(base_vha, 0);
5072 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
5073 qla83xx_rd_reg(base_vha, QLA83XX_IDC_CONTROL, &idc_control);
5074 qla83xx_idc_unlock(base_vha, 0);
5075 if (dev_state == QLA8XXX_DEV_NEED_RESET) {
5076 if (idc_control & QLA83XX_IDC_GRACEFUL_RESET) {
5077 ql_dbg(ql_dbg_p3p, base_vha, 0xb062,
5078 "Application requested NIC Core Reset.\n");
5079 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
5080 } else if (qla83xx_check_nic_core_fw_alive(base_vha) ==
5081 QLA_SUCCESS) {
5082 ql_dbg(ql_dbg_p3p, base_vha, 0xb07b,
5083 "Other protocol driver requested NIC Core Reset.\n");
5084 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
5085 }
5086 } else if (dev_state == QLA8XXX_DEV_FAILED ||
5087 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) {
5088 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
5089 }
5090}
5091
5092static void
5093qla83xx_wait_logic(void)
5094{
5095 int i;
5096
5097 /* Yield CPU */
5098 if (!in_interrupt()) {
5099 /*
5100 * Wait about 200ms before retrying again.
5101 * This controls the number of retries for single
5102 * lock operation.
5103 */
5104 msleep(100);
5105 schedule();
5106 } else {
5107 for (i = 0; i < 20; i++)
5108 cpu_relax(); /* This a nop instr on i386 */
5109 }
5110}
5111
fa492630 5112static int
7d613ac6
SV		 5113qla83xx_force_lock_recovery(scsi_qla_host_t *base_vha)
5114{
5115 int rval;
5116 uint32_t data;
5117 uint32_t idc_lck_rcvry_stage_mask = 0x3;
5118 uint32_t idc_lck_rcvry_owner_mask = 0x3c;
5119 struct qla_hw_data *ha = base_vha->hw;
6c315553
SK		 5120 ql_dbg(ql_dbg_p3p, base_vha, 0xb086,
5121 "Trying force recovery of the IDC lock.\n");
7d613ac6
SV		 5122
5123 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, &data);
5124 if (rval)
5125 return rval;
5126
5127 if ((data & idc_lck_rcvry_stage_mask) > 0) {
5128 return QLA_SUCCESS;
5129 } else {
5130 data = (IDC_LOCK_RECOVERY_STAGE1) | (ha->portnum << 2);
5131 rval = qla83xx_wr_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
5132 data);
5133 if (rval)
5134 return rval;
5135
5136 msleep(200);
5137
5138 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
5139 &data);
5140 if (rval)
5141 return rval;
5142
5143 if (((data & idc_lck_rcvry_owner_mask) >> 2) == ha->portnum) {
5144 data &= (IDC_LOCK_RECOVERY_STAGE2 |
5145 ~(idc_lck_rcvry_stage_mask));
5146 rval = qla83xx_wr_reg(base_vha,
5147 QLA83XX_IDC_LOCK_RECOVERY, data);
5148 if (rval)
5149 return rval;
5150
5151 /* Forcefully perform IDC UnLock */
5152 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK,
5153 &data);
5154 if (rval)
5155 return rval;
5156 /* Clear lock-id by setting 0xff */
5157 rval = qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
5158 0xff);
5159 if (rval)
5160 return rval;
5161 /* Clear lock-recovery by setting 0x0 */
5162 rval = qla83xx_wr_reg(base_vha,
5163 QLA83XX_IDC_LOCK_RECOVERY, 0x0);
5164 if (rval)
5165 return rval;
5166 } else
5167 return QLA_SUCCESS;
5168 }
5169
5170 return rval;
5171}
5172
fa492630 5173static int
7d613ac6
SV		 5174qla83xx_idc_lock_recovery(scsi_qla_host_t *base_vha)
5175{
5176 int rval = QLA_SUCCESS;
5177 uint32_t o_drv_lockid, n_drv_lockid;
5178 unsigned long lock_recovery_timeout;
5179
5180 lock_recovery_timeout = jiffies + QLA83XX_MAX_LOCK_RECOVERY_WAIT;
5181retry_lockid:
5182 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &o_drv_lockid);
5183 if (rval)
5184 goto exit;
5185
5186 /* MAX wait time before forcing IDC Lock recovery = 2 secs */
5187 if (time_after_eq(jiffies, lock_recovery_timeout)) {
5188 if (qla83xx_force_lock_recovery(base_vha) == QLA_SUCCESS)
5189 return QLA_SUCCESS;
5190 else
5191 return QLA_FUNCTION_FAILED;
5192 }
5193
5194 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &n_drv_lockid);
5195 if (rval)
5196 goto exit;
5197
5198 if (o_drv_lockid == n_drv_lockid) {
5199 qla83xx_wait_logic();
5200 goto retry_lockid;
5201 } else
5202 return QLA_SUCCESS;
5203
5204exit:
5205 return rval;
5206}
5207
5208void
5209qla83xx_idc_lock(scsi_qla_host_t *base_vha, uint16_t requester_id)
5210{
5211 uint16_t options = (requester_id << 15) | BIT_6;
5212 uint32_t data;
6c315553 5213 uint32_t lock_owner;
7d613ac6
SV		 5214 struct qla_hw_data *ha = base_vha->hw;
5215
5216 /* IDC-lock implementation using driver-lock/lock-id remote registers */
5217retry_lock:
5218 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCK, &data)
5219 == QLA_SUCCESS) {
5220 if (data) {
5221 /* Setting lock-id to our function-number */
5222 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
5223 ha->portnum);
5224 } else {
6c315553
SK		 5225 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID,
5226 &lock_owner);
7d613ac6 5227 ql_dbg(ql_dbg_p3p, base_vha, 0xb063,
6c315553
SK		 5228 "Failed to acquire IDC lock, acquired by %d, "
5229 "retrying...\n", lock_owner);
7d613ac6
SV		 5230
5231 /* Retry/Perform IDC-Lock recovery */
5232 if (qla83xx_idc_lock_recovery(base_vha)
5233 == QLA_SUCCESS) {
5234 qla83xx_wait_logic();
5235 goto retry_lock;
5236 } else
5237 ql_log(ql_log_warn, base_vha, 0xb075,
5238 "IDC Lock recovery FAILED.\n");
5239 }
5240
5241 }
5242
5243 return;
5244
5245 /* XXX: IDC-lock implementation using access-control mbx */
5246retry_lock2:
5247 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
5248 ql_dbg(ql_dbg_p3p, base_vha, 0xb072,
5249 "Failed to acquire IDC lock. retrying...\n");
5250 /* Retry/Perform IDC-Lock recovery */
5251 if (qla83xx_idc_lock_recovery(base_vha) == QLA_SUCCESS) {
5252 qla83xx_wait_logic();
5253 goto retry_lock2;
5254 } else
5255 ql_log(ql_log_warn, base_vha, 0xb076,
5256 "IDC Lock recovery FAILED.\n");
5257 }
5258
5259 return;
5260}
5261
5262void
5263qla83xx_idc_unlock(scsi_qla_host_t *base_vha, uint16_t requester_id)
5264{
5897cb2f
BVA		 5265#if 0
5266 uint16_t options = (requester_id << 15) | BIT_7;
5267#endif
5268 uint16_t retry;
7d613ac6
SV		 5269 uint32_t data;
5270 struct qla_hw_data *ha = base_vha->hw;
5271
5272 /* IDC-unlock implementation using driver-unlock/lock-id
5273 * remote registers
5274 */
5275 retry = 0;
5276retry_unlock:
5277 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &data)
5278 == QLA_SUCCESS) {
5279 if (data == ha->portnum) {
5280 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, &data);
5281 /* Clearing lock-id by setting 0xff */
5282 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 0xff);
5283 } else if (retry < 10) {
5284 /* SV: XXX: IDC unlock retrying needed here? */
5285
5286 /* Retry for IDC-unlock */
5287 qla83xx_wait_logic();
5288 retry++;
5289 ql_dbg(ql_dbg_p3p, base_vha, 0xb064,
ee6a8773 5290 "Failed to release IDC lock, retrying=%d\n", retry);
7d613ac6
SV		 5291 goto retry_unlock;
5292 }
5293 } else if (retry < 10) {
5294 /* Retry for IDC-unlock */
5295 qla83xx_wait_logic();
5296 retry++;
5297 ql_dbg(ql_dbg_p3p, base_vha, 0xb065,
ee6a8773 5298 "Failed to read drv-lockid, retrying=%d\n", retry);
7d613ac6
SV		 5299 goto retry_unlock;
5300 }
5301
5302 return;
5303
5897cb2f 5304#if 0
7d613ac6
SV		 5305 /* XXX: IDC-unlock implementation using access-control mbx */
5306 retry = 0;
5307retry_unlock2:
5308 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
5309 if (retry < 10) {
5310 /* Retry for IDC-unlock */
5311 qla83xx_wait_logic();
5312 retry++;
5313 ql_dbg(ql_dbg_p3p, base_vha, 0xb066,
ee6a8773 5314 "Failed to release IDC lock, retrying=%d\n", retry);
7d613ac6
SV		 5315 goto retry_unlock2;
5316 }
5317 }
5318
5319 return;
5897cb2f 5320#endif
7d613ac6
SV		 5321}
5322
5323int
5324__qla83xx_set_drv_presence(scsi_qla_host_t *vha)
5325{
5326 int rval = QLA_SUCCESS;
5327 struct qla_hw_data *ha = vha->hw;
5328 uint32_t drv_presence;
5329
5330 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
5331 if (rval == QLA_SUCCESS) {
5332 drv_presence |= (1 << ha->portnum);
5333 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
5334 drv_presence);
5335 }
5336
5337 return rval;
5338}
5339
5340int
5341qla83xx_set_drv_presence(scsi_qla_host_t *vha)
5342{
5343 int rval = QLA_SUCCESS;
5344
5345 qla83xx_idc_lock(vha, 0);
5346 rval = __qla83xx_set_drv_presence(vha);
5347 qla83xx_idc_unlock(vha, 0);
5348
5349 return rval;
5350}
5351
5352int
5353__qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
5354{
5355 int rval = QLA_SUCCESS;
5356 struct qla_hw_data *ha = vha->hw;
5357 uint32_t drv_presence;
5358
5359 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
5360 if (rval == QLA_SUCCESS) {
5361 drv_presence &= ~(1 << ha->portnum);
5362 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
5363 drv_presence);
5364 }
5365
5366 return rval;
5367}
5368
5369int
5370qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
5371{
5372 int rval = QLA_SUCCESS;
5373
5374 qla83xx_idc_lock(vha, 0);
5375 rval = __qla83xx_clear_drv_presence(vha);
5376 qla83xx_idc_unlock(vha, 0);
5377
5378 return rval;
5379}
5380
fa492630 5381static void
7d613ac6
SV		 5382qla83xx_need_reset_handler(scsi_qla_host_t *vha)
5383{
5384 struct qla_hw_data *ha = vha->hw;
5385 uint32_t drv_ack, drv_presence;
5386 unsigned long ack_timeout;
5387
5388 /* Wait for IDC ACK from all functions (DRV-ACK == DRV-PRESENCE) */
5389 ack_timeout = jiffies + (ha->fcoe_reset_timeout * HZ);
5390 while (1) {
5391 qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
5392 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
807fb6d8 5393 if ((drv_ack & drv_presence) == drv_presence)
7d613ac6
SV		 5394 break;
5395
5396 if (time_after_eq(jiffies, ack_timeout)) {
5397 ql_log(ql_log_warn, vha, 0xb067,
5398 "RESET ACK TIMEOUT! drv_presence=0x%x "
5399 "drv_ack=0x%x\n", drv_presence, drv_ack);
5400 /*
5401 * The function(s) which did not ack in time are forced
5402 * to withdraw any further participation in the IDC
5403 * reset.
5404 */
5405 if (drv_ack != drv_presence)
5406 qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
5407 drv_ack);
5408 break;
5409 }
5410
5411 qla83xx_idc_unlock(vha, 0);
5412 msleep(1000);
5413 qla83xx_idc_lock(vha, 0);
5414 }
5415
5416 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_COLD);
5417 ql_log(ql_log_info, vha, 0xb068, "HW State: COLD/RE-INIT.\n");
5418}
5419
fa492630 5420static int
7d613ac6
SV		 5421qla83xx_device_bootstrap(scsi_qla_host_t *vha)
5422{
5423 int rval = QLA_SUCCESS;
5424 uint32_t idc_control;
5425
5426 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_INITIALIZING);
5427 ql_log(ql_log_info, vha, 0xb069, "HW State: INITIALIZING.\n");
5428
5429 /* Clearing IDC-Control Graceful-Reset Bit before resetting f/w */
5430 __qla83xx_get_idc_control(vha, &idc_control);
5431 idc_control &= ~QLA83XX_IDC_GRACEFUL_RESET;
5432 __qla83xx_set_idc_control(vha, 0);
5433
5434 qla83xx_idc_unlock(vha, 0);
5435 rval = qla83xx_restart_nic_firmware(vha);
5436 qla83xx_idc_lock(vha, 0);
5437
5438 if (rval != QLA_SUCCESS) {
5439 ql_log(ql_log_fatal, vha, 0xb06a,
5440 "Failed to restart NIC f/w.\n");
5441 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_FAILED);
5442 ql_log(ql_log_info, vha, 0xb06b, "HW State: FAILED.\n");
5443 } else {
5444 ql_dbg(ql_dbg_p3p, vha, 0xb06c,
5445 "Success in restarting nic f/w.\n");
5446 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_READY);
5447 ql_log(ql_log_info, vha, 0xb06d, "HW State: READY.\n");
5448 }
5449
5450 return rval;
5451}
5452
5453/* Assumes idc_lock always held on entry */
5454int
5455qla83xx_idc_state_handler(scsi_qla_host_t *base_vha)
5456{
5457 struct qla_hw_data *ha = base_vha->hw;
5458 int rval = QLA_SUCCESS;
5459 unsigned long dev_init_timeout;
5460 uint32_t dev_state;
5461
5462 /* Wait for MAX-INIT-TIMEOUT for the device to go ready */
5463 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ);
5464
5465 while (1) {
5466
5467 if (time_after_eq(jiffies, dev_init_timeout)) {
5468 ql_log(ql_log_warn, base_vha, 0xb06e,
5469 "Initialization TIMEOUT!\n");
5470 /* Init timeout. Disable further NIC Core
5471 * communication.
5472 */
5473 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
5474 QLA8XXX_DEV_FAILED);
5475 ql_log(ql_log_info, base_vha, 0xb06f,
5476 "HW State: FAILED.\n");
5477 }
5478
5479 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
5480 switch (dev_state) {
5481 case QLA8XXX_DEV_READY:
5482 if (ha->flags.nic_core_reset_owner)
5483 qla83xx_idc_audit(base_vha,
5484 IDC_AUDIT_COMPLETION);
5485 ha->flags.nic_core_reset_owner = 0;
5486 ql_dbg(ql_dbg_p3p, base_vha, 0xb070,
5487 "Reset_owner reset by 0x%x.\n",
5488 ha->portnum);
5489 goto exit;
5490 case QLA8XXX_DEV_COLD:
5491 if (ha->flags.nic_core_reset_owner)
5492 rval = qla83xx_device_bootstrap(base_vha);
5493 else {
5494 /* Wait for AEN to change device-state */
5495 qla83xx_idc_unlock(base_vha, 0);
5496 msleep(1000);
5497 qla83xx_idc_lock(base_vha, 0);
5498 }
5499 break;
5500 case QLA8XXX_DEV_INITIALIZING:
5501 /* Wait for AEN to change device-state */
5502 qla83xx_idc_unlock(base_vha, 0);
5503 msleep(1000);
5504 qla83xx_idc_lock(base_vha, 0);
5505 break;
5506 case QLA8XXX_DEV_NEED_RESET:
5507 if (!ql2xdontresethba && ha->flags.nic_core_reset_owner)
5508 qla83xx_need_reset_handler(base_vha);
5509 else {
5510 /* Wait for AEN to change device-state */
5511 qla83xx_idc_unlock(base_vha, 0);
5512 msleep(1000);
5513 qla83xx_idc_lock(base_vha, 0);
5514 }
5515 /* reset timeout value after need reset handler */
5516 dev_init_timeout = jiffies +
5517 (ha->fcoe_dev_init_timeout * HZ);
5518 break;
5519 case QLA8XXX_DEV_NEED_QUIESCENT:
5520 /* XXX: DEBUG for now */
5521 qla83xx_idc_unlock(base_vha, 0);
5522 msleep(1000);
5523 qla83xx_idc_lock(base_vha, 0);
5524 break;
5525 case QLA8XXX_DEV_QUIESCENT:
5526 /* XXX: DEBUG for now */
5527 if (ha->flags.quiesce_owner)
5528 goto exit;
5529
5530 qla83xx_idc_unlock(base_vha, 0);
5531 msleep(1000);
5532 qla83xx_idc_lock(base_vha, 0);
5533 dev_init_timeout = jiffies +
5534 (ha->fcoe_dev_init_timeout * HZ);
5535 break;
5536 case QLA8XXX_DEV_FAILED:
5537 if (ha->flags.nic_core_reset_owner)
5538 qla83xx_idc_audit(base_vha,
5539 IDC_AUDIT_COMPLETION);
5540 ha->flags.nic_core_reset_owner = 0;
5541 __qla83xx_clear_drv_presence(base_vha);
5542 qla83xx_idc_unlock(base_vha, 0);
5543 qla8xxx_dev_failed_handler(base_vha);
5544 rval = QLA_FUNCTION_FAILED;
5545 qla83xx_idc_lock(base_vha, 0);
5546 goto exit;
5547 case QLA8XXX_BAD_VALUE:
5548 qla83xx_idc_unlock(base_vha, 0);
5549 msleep(1000);
5550 qla83xx_idc_lock(base_vha, 0);
5551 break;
5552 default:
5553 ql_log(ql_log_warn, base_vha, 0xb071,
d939be3a 5554 "Unknown Device State: %x.\n", dev_state);
7d613ac6
SV		 5555 qla83xx_idc_unlock(base_vha, 0);
5556 qla8xxx_dev_failed_handler(base_vha);
5557 rval = QLA_FUNCTION_FAILED;
5558 qla83xx_idc_lock(base_vha, 0);
5559 goto exit;
5560 }
5561 }
5562
5563exit:
5564 return rval;
5565}
5566
f3ddac19
CD		 5567void
5568qla2x00_disable_board_on_pci_error(struct work_struct *work)
5569{
5570 struct qla_hw_data *ha = container_of(work, struct qla_hw_data,
5571 board_disable);
5572 struct pci_dev *pdev = ha->pdev;
5573 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5574
726b8548
QT		 5575 /*
5576 * if UNLOAD flag is already set, then continue unload,
783e0dc4
SC		 5577 * where it was set first.
5578 */
5579 if (test_bit(UNLOADING, &base_vha->dpc_flags))
5580 return;
5581
f3ddac19
CD		 5582 ql_log(ql_log_warn, base_vha, 0x015b,
5583 "Disabling adapter.\n");
5584
efdb5760
SC		 5585 if (!atomic_read(&pdev->enable_cnt)) {
5586 ql_log(ql_log_info, base_vha, 0xfffc,
5587 "PCI device disabled, no action req for PCI error=%lx\n",
5588 base_vha->pci_flags);
5589 return;
5590 }
5591
726b8548
QT		 5592 qla2x00_wait_for_sess_deletion(base_vha);
5593
f3ddac19
CD		 5594 set_bit(UNLOADING, &base_vha->dpc_flags);
5595
5596 qla2x00_delete_all_vps(ha, base_vha);
5597
5598 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
5599
5600 qla2x00_dfs_remove(base_vha);
5601
5602 qla84xx_put_chip(base_vha);
5603
5604 if (base_vha->timer_active)
5605 qla2x00_stop_timer(base_vha);
5606
5607 base_vha->flags.online = 0;
5608
5609 qla2x00_destroy_deferred_work(ha);
5610
5611 /*
5612 * Do not try to stop beacon blink as it will issue a mailbox
5613 * command.
5614 */
5615 qla2x00_free_sysfs_attr(base_vha, false);
5616
5617 fc_remove_host(base_vha->host);
5618
5619 scsi_remove_host(base_vha->host);
5620
5621 base_vha->flags.init_done = 0;
5622 qla25xx_delete_queues(base_vha);
f3ddac19 5623 qla2x00_free_fcports(base_vha);
093df737 5624 qla2x00_free_irqs(base_vha);
f3ddac19
CD		 5625 qla2x00_mem_free(ha);
5626 qla82xx_md_free(base_vha);
5627 qla2x00_free_queues(ha);
5628
f3ddac19
CD		 5629 qla2x00_unmap_iobases(ha);
5630
5631 pci_release_selected_regions(ha->pdev, ha->bars);
f3ddac19
CD		 5632 pci_disable_pcie_error_reporting(pdev);
5633 pci_disable_device(pdev);
f3ddac19 5634
beb9e315
JL		 5635 /*
5636 * Let qla2x00_remove_one cleanup qla_hw_data on device removal.
5637 */
f3ddac19
CD		 5638}
5639
1da177e4
LT		 5640/**************************************************************************
5641* qla2x00_do_dpc
5642* This kernel thread is a task that is schedule by the interrupt handler
5643* to perform the background processing for interrupts.
5644*
5645* Notes:
5646* This task always run in the context of a kernel thread. It
5647* is kick-off by the driver's detect code and starts up
5648* up one per adapter. It immediately goes to sleep and waits for
5649* some fibre event. When either the interrupt handler or
5650* the timer routine detects a event it will one of the task
5651* bits then wake us up.
5652**************************************************************************/
5653static int
5654qla2x00_do_dpc(void *data)
5655{
e315cd28
AC		 5656 scsi_qla_host_t *base_vha;
5657 struct qla_hw_data *ha;
d7459527
MH		 5658 uint32_t online;
5659 struct qla_qpair *qpair;
1da177e4 5660
e315cd28
AC		 5661 ha = (struct qla_hw_data *)data;
5662 base_vha = pci_get_drvdata(ha->pdev);
1da177e4 5663
8698a745 5664 set_user_nice(current, MIN_NICE);
1da177e4 5665
563585ec 5666 set_current_state(TASK_INTERRUPTIBLE);
39a11240 5667 while (!kthread_should_stop()) {
7c3df132
SK		 5668 ql_dbg(ql_dbg_dpc, base_vha, 0x4000,
5669 "DPC handler sleeping.\n");
1da177e4 5670
39a11240 5671 schedule();
1da177e4 5672
c142caf0
AV		 5673 if (!base_vha->flags.init_done || ha->flags.mbox_busy)
5674 goto end_loop;
1da177e4 5675
85880801 5676 if (ha->flags.eeh_busy) {
7c3df132
SK		 5677 ql_dbg(ql_dbg_dpc, base_vha, 0x4003,
5678 "eeh_busy=%d.\n", ha->flags.eeh_busy);
c142caf0 5679 goto end_loop;
85880801
AV		 5680 }
5681
1da177e4
LT		 5682 ha->dpc_active = 1;
5683
5f28d2d7
SK		 5684 ql_dbg(ql_dbg_dpc + ql_dbg_verbose, base_vha, 0x4001,
5685 "DPC handler waking up, dpc_flags=0x%lx.\n",
5686 base_vha->dpc_flags);
1da177e4 5687
a29b3dd7
JC		 5688 if (test_bit(UNLOADING, &base_vha->dpc_flags))
5689 break;
5690
e315cd28 5691 qla2x00_do_work(base_vha);
0971de7f 5692
7ec0effd
AD		 5693 if (IS_P3P_TYPE(ha)) {
5694 if (IS_QLA8044(ha)) {
5695 if (test_and_clear_bit(ISP_UNRECOVERABLE,
5696 &base_vha->dpc_flags)) {
5697 qla8044_idc_lock(ha);
5698 qla8044_wr_direct(base_vha,
5699 QLA8044_CRB_DEV_STATE_INDEX,
5700 QLA8XXX_DEV_FAILED);
5701 qla8044_idc_unlock(ha);
5702 ql_log(ql_log_info, base_vha, 0x4004,
5703 "HW State: FAILED.\n");
5704 qla8044_device_state_handler(base_vha);
5705 continue;
5706 }
5707
5708 } else {
5709 if (test_and_clear_bit(ISP_UNRECOVERABLE,
5710 &base_vha->dpc_flags)) {
5711 qla82xx_idc_lock(ha);
5712 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
5713 QLA8XXX_DEV_FAILED);
5714 qla82xx_idc_unlock(ha);
5715 ql_log(ql_log_info, base_vha, 0x0151,
5716 "HW State: FAILED.\n");
5717 qla82xx_device_state_handler(base_vha);
5718 continue;
5719 }
a9083016
GM		 5720 }
5721
5722 if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED,
5723 &base_vha->dpc_flags)) {
5724
7c3df132
SK		 5725 ql_dbg(ql_dbg_dpc, base_vha, 0x4005,
5726 "FCoE context reset scheduled.\n");
a9083016
GM		 5727 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
5728 &base_vha->dpc_flags))) {
5729 if (qla82xx_fcoe_ctx_reset(base_vha)) {
5730 /* FCoE-ctx reset failed.
5731 * Escalate to chip-reset
5732 */
5733 set_bit(ISP_ABORT_NEEDED,
5734 &base_vha->dpc_flags);
5735 }
5736 clear_bit(ABORT_ISP_ACTIVE,
5737 &base_vha->dpc_flags);
5738 }
5739
7c3df132
SK		 5740 ql_dbg(ql_dbg_dpc, base_vha, 0x4006,
5741 "FCoE context reset end.\n");
a9083016 5742 }
8ae6d9c7
GM		 5743 } else if (IS_QLAFX00(ha)) {
5744 if (test_and_clear_bit(ISP_UNRECOVERABLE,
5745 &base_vha->dpc_flags)) {
5746 ql_dbg(ql_dbg_dpc, base_vha, 0x4020,
5747 "Firmware Reset Recovery\n");
5748 if (qlafx00_reset_initialize(base_vha)) {
5749 /* Failed. Abort isp later. */
5750 if (!test_bit(UNLOADING,
f92f82d6 5751 &base_vha->dpc_flags)) {
8ae6d9c7
GM		 5752 set_bit(ISP_UNRECOVERABLE,
5753 &base_vha->dpc_flags);
5754 ql_dbg(ql_dbg_dpc, base_vha,
5755 0x4021,
5756 "Reset Recovery Failed\n");
f92f82d6 5757 }
8ae6d9c7
GM		 5758 }
5759 }
5760
5761 if (test_and_clear_bit(FX00_TARGET_SCAN,
5762 &base_vha->dpc_flags)) {
5763 ql_dbg(ql_dbg_dpc, base_vha, 0x4022,
5764 "ISPFx00 Target Scan scheduled\n");
5765 if (qlafx00_rescan_isp(base_vha)) {
5766 if (!test_bit(UNLOADING,
5767 &base_vha->dpc_flags))
5768 set_bit(ISP_UNRECOVERABLE,
5769 &base_vha->dpc_flags);
5770 ql_dbg(ql_dbg_dpc, base_vha, 0x401e,
5771 "ISPFx00 Target Scan Failed\n");
5772 }
5773 ql_dbg(ql_dbg_dpc, base_vha, 0x401f,
5774 "ISPFx00 Target Scan End\n");
5775 }
e8f5e95d
AB		 5776 if (test_and_clear_bit(FX00_HOST_INFO_RESEND,
5777 &base_vha->dpc_flags)) {
5778 ql_dbg(ql_dbg_dpc, base_vha, 0x4023,
5779 "ISPFx00 Host Info resend scheduled\n");
5780 qlafx00_fx_disc(base_vha,
5781 &base_vha->hw->mr.fcport,
5782 FXDISC_REG_HOST_INFO);
5783 }
a9083016
GM		 5784 }
5785
e4e3a2ce
QT		 5786 if (test_and_clear_bit(DETECT_SFP_CHANGE,
5787 &base_vha->dpc_flags) &&
5788 !test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) {
5789 qla24xx_detect_sfp(base_vha);
5790
5791 if (ha->flags.detected_lr_sfp !=
5792 ha->flags.using_lr_setting)
5793 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
5794 }
5795
e315cd28
AC		 5796 if (test_and_clear_bit(ISP_ABORT_NEEDED,
5797 &base_vha->dpc_flags)) {
1da177e4 5798
7c3df132
SK		 5799 ql_dbg(ql_dbg_dpc, base_vha, 0x4007,
5800 "ISP abort scheduled.\n");
1da177e4 5801 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
e315cd28 5802 &base_vha->dpc_flags))) {
1da177e4 5803
a9083016 5804 if (ha->isp_ops->abort_isp(base_vha)) {
1da177e4
LT		 5805 /* failed. retry later */
5806 set_bit(ISP_ABORT_NEEDED,
e315cd28 5807 &base_vha->dpc_flags);
99363ef8 5808 }
e315cd28
AC		 5809 clear_bit(ABORT_ISP_ACTIVE,
5810 &base_vha->dpc_flags);
99363ef8
SJ		 5811 }
5812
7c3df132
SK		 5813 ql_dbg(ql_dbg_dpc, base_vha, 0x4008,
5814 "ISP abort end.\n");
1da177e4
LT		 5815 }
5816
a394aac8
DJ		 5817 if (test_and_clear_bit(FCPORT_UPDATE_NEEDED,
5818 &base_vha->dpc_flags)) {
e315cd28 5819 qla2x00_update_fcports(base_vha);
c9c5ced9 5820 }
d97994dc 5821
8ae6d9c7
GM		 5822 if (IS_QLAFX00(ha))
5823 goto loop_resync_check;
5824
579d12b5 5825 if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) {
7c3df132
SK		 5826 ql_dbg(ql_dbg_dpc, base_vha, 0x4009,
5827 "Quiescence mode scheduled.\n");
7ec0effd
AD		 5828 if (IS_P3P_TYPE(ha)) {
5829 if (IS_QLA82XX(ha))
5830 qla82xx_device_state_handler(base_vha);
5831 if (IS_QLA8044(ha))
5832 qla8044_device_state_handler(base_vha);
8fcd6b8b
CD		 5833 clear_bit(ISP_QUIESCE_NEEDED,
5834 &base_vha->dpc_flags);
5835 if (!ha->flags.quiesce_owner) {
5836 qla2x00_perform_loop_resync(base_vha);
7ec0effd
AD		 5837 if (IS_QLA82XX(ha)) {
5838 qla82xx_idc_lock(ha);
5839 qla82xx_clear_qsnt_ready(
5840 base_vha);
5841 qla82xx_idc_unlock(ha);
5842 } else if (IS_QLA8044(ha)) {
5843 qla8044_idc_lock(ha);
5844 qla8044_clear_qsnt_ready(
5845 base_vha);
5846 qla8044_idc_unlock(ha);
5847 }
8fcd6b8b
CD		 5848 }
5849 } else {
5850 clear_bit(ISP_QUIESCE_NEEDED,
5851 &base_vha->dpc_flags);
5852 qla2x00_quiesce_io(base_vha);
579d12b5 5853 }
7c3df132
SK		 5854 ql_dbg(ql_dbg_dpc, base_vha, 0x400a,
5855 "Quiescence mode end.\n");
579d12b5
SK		 5856 }
5857
e315cd28 5858 if (test_and_clear_bit(RESET_MARKER_NEEDED,
8ae6d9c7 5859 &base_vha->dpc_flags) &&
e315cd28 5860 (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) {
1da177e4 5861
7c3df132
SK		 5862 ql_dbg(ql_dbg_dpc, base_vha, 0x400b,
5863 "Reset marker scheduled.\n");
e315cd28
AC		 5864 qla2x00_rst_aen(base_vha);
5865 clear_bit(RESET_ACTIVE, &base_vha->dpc_flags);
7c3df132
SK		 5866 ql_dbg(ql_dbg_dpc, base_vha, 0x400c,
5867 "Reset marker end.\n");
1da177e4
LT		 5868 }
5869
5870 /* Retry each device up to login retry count */
e315cd28
AC		 5871 if ((test_and_clear_bit(RELOGIN_NEEDED,
5872 &base_vha->dpc_flags)) &&
5873 !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) &&
5874 atomic_read(&base_vha->loop_state) != LOOP_DOWN) {
1da177e4 5875
7c3df132
SK		 5876 ql_dbg(ql_dbg_dpc, base_vha, 0x400d,
5877 "Relogin scheduled.\n");
e315cd28 5878 qla2x00_relogin(base_vha);
7c3df132
SK		 5879 ql_dbg(ql_dbg_dpc, base_vha, 0x400e,
5880 "Relogin end.\n");
1da177e4 5881 }
8ae6d9c7 5882loop_resync_check:
e315cd28 5883 if (test_and_clear_bit(LOOP_RESYNC_NEEDED,
8ae6d9c7 5884 &base_vha->dpc_flags)) {
1da177e4 5885
7c3df132
SK		 5886 ql_dbg(ql_dbg_dpc, base_vha, 0x400f,
5887 "Loop resync scheduled.\n");
1da177e4
LT		 5888
5889 if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE,
e315cd28 5890 &base_vha->dpc_flags))) {
1da177e4 5891
52c82823 5892 qla2x00_loop_resync(base_vha);
1da177e4 5893
e315cd28
AC		 5894 clear_bit(LOOP_RESYNC_ACTIVE,
5895 &base_vha->dpc_flags);
1da177e4
LT		 5896 }
5897
7c3df132
SK		 5898 ql_dbg(ql_dbg_dpc, base_vha, 0x4010,
5899 "Loop resync end.\n");
1da177e4
LT		 5900 }
5901
8ae6d9c7
GM		 5902 if (IS_QLAFX00(ha))
5903 goto intr_on_check;
5904
e315cd28
AC		 5905 if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) &&
5906 atomic_read(&base_vha->loop_state) == LOOP_READY) {
5907 clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags);
5908 qla2xxx_flash_npiv_conf(base_vha);
272976ca
AV		 5909 }
5910
8ae6d9c7 5911intr_on_check:
1da177e4 5912 if (!ha->interrupts_on)
fd34f556 5913 ha->isp_ops->enable_intrs(ha);
1da177e4 5914
e315cd28 5915 if (test_and_clear_bit(BEACON_BLINK_NEEDED,
90b604f2
HM		 5916 &base_vha->dpc_flags)) {
5917 if (ha->beacon_blink_led == 1)
5918 ha->isp_ops->beacon_blink(base_vha);
5919 }
f6df144c 5920
d7459527
MH		 5921 /* qpair online check */
5922 if (test_and_clear_bit(QPAIR_ONLINE_CHECK_NEEDED,
5923 &base_vha->dpc_flags)) {
5924 if (ha->flags.eeh_busy ||
5925 ha->flags.pci_channel_io_perm_failure)
5926 online = 0;
5927 else
5928 online = 1;
5929
5930 mutex_lock(&ha->mq_lock);
5931 list_for_each_entry(qpair, &base_vha->qp_list,
5932 qp_list_elem)
5933 qpair->online = online;
5934 mutex_unlock(&ha->mq_lock);
5935 }
5936
deeae7a6
DG		 5937 if (test_and_clear_bit(SET_ZIO_THRESHOLD_NEEDED, &base_vha->dpc_flags)) {
5938 ql_log(ql_log_info, base_vha, 0xffffff,
5939 "nvme: SET ZIO Activity exchange threshold to %d.\n",
5940 ha->nvme_last_rptd_aen);
5941 if (qla27xx_set_zio_threshold(base_vha, ha->nvme_last_rptd_aen)) {
5942 ql_log(ql_log_info, base_vha, 0xffffff,
5943 "nvme: Unable to SET ZIO Activity exchange threshold to %d.\n",
5944 ha->nvme_last_rptd_aen);
5945 }
5946 }
5947
8ae6d9c7
GM		 5948 if (!IS_QLAFX00(ha))
5949 qla2x00_do_dpc_all_vps(base_vha);
2c3dfe3f 5950
1da177e4 5951 ha->dpc_active = 0;
c142caf0 5952end_loop:
563585ec 5953 set_current_state(TASK_INTERRUPTIBLE);
1da177e4 5954 } /* End of while(1) */
563585ec 5955 __set_current_state(TASK_RUNNING);
1da177e4 5956
7c3df132
SK		 5957 ql_dbg(ql_dbg_dpc, base_vha, 0x4011,
5958 "DPC handler exiting.\n");
1da177e4
LT		 5959
5960 /*
5961 * Make sure that nobody tries to wake us up again.
5962 */
1da177e4
LT		 5963 ha->dpc_active = 0;
5964
ac280b67
AV		 5965 /* Cleanup any residual CTX SRBs. */
5966 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
5967
39a11240
CH		 5968 return 0;
5969}
5970
5971void
e315cd28 5972qla2xxx_wake_dpc(struct scsi_qla_host *vha)
39a11240 5973{
e315cd28 5974 struct qla_hw_data *ha = vha->hw;
c795c1e4
AV		 5975 struct task_struct *t = ha->dpc_thread;
5976
e315cd28 5977 if (!test_bit(UNLOADING, &vha->dpc_flags) && t)
c795c1e4 5978 wake_up_process(t);
1da177e4
LT		 5979}
5980
1da177e4
LT		 5981/*
5982* qla2x00_rst_aen
5983* Processes asynchronous reset.
5984*
5985* Input:
5986* ha = adapter block pointer.
5987*/
5988static void
e315cd28 5989qla2x00_rst_aen(scsi_qla_host_t *vha)
1da177e4 5990{
e315cd28
AC		 5991 if (vha->flags.online && !vha->flags.reset_active &&
5992 !atomic_read(&vha->loop_down_timer) &&
5993 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) {
1da177e4 5994 do {
e315cd28 5995 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
1da177e4
LT		 5996
5997 /*
5998 * Issue marker command only when we are going to start
5999 * the I/O.
6000 */
e315cd28
AC		 6001 vha->marker_needed = 1;
6002 } while (!atomic_read(&vha->loop_down_timer) &&
6003 (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)));
1da177e4
LT		 6004 }
6005}
6006
1da177e4
LT		 6007/**************************************************************************
6008* qla2x00_timer
6009*
6010* Description:
6011* One second timer
6012*
6013* Context: Interrupt
6014***************************************************************************/
2c3dfe3f 6015void
8e5f4ba0 6016qla2x00_timer(struct timer_list *t)
1da177e4 6017{
8e5f4ba0 6018 scsi_qla_host_t *vha = from_timer(vha, t, timer);
1da177e4 6019 unsigned long cpu_flags = 0;
1da177e4
LT		 6020 int start_dpc = 0;
6021 int index;
6022 srb_t *sp;
85880801 6023 uint16_t w;
e315cd28 6024 struct qla_hw_data *ha = vha->hw;
73208dfd 6025 struct req_que *req;
85880801 6026
a5b36321 6027 if (ha->flags.eeh_busy) {
7c3df132
SK		 6028 ql_dbg(ql_dbg_timer, vha, 0x6000,
6029 "EEH = %d, restarting timer.\n",
6030 ha->flags.eeh_busy);
a5b36321
LC		 6031 qla2x00_restart_timer(vha, WATCH_INTERVAL);
6032 return;
6033 }
6034
f3ddac19
CD		 6035 /*
6036 * Hardware read to raise pending EEH errors during mailbox waits. If
6037 * the read returns -1 then disable the board.
6038 */
6039 if (!pci_channel_offline(ha->pdev)) {
85880801 6040 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w);
c821e0d5 6041 qla2x00_check_reg16_for_disconnect(vha, w);
f3ddac19 6042 }
1da177e4 6043
cefcaba6 6044 /* Make sure qla82xx_watchdog is run only for physical port */
7ec0effd 6045 if (!vha->vp_idx && IS_P3P_TYPE(ha)) {
579d12b5
SK		 6046 if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags))
6047 start_dpc++;
7ec0effd
AD		 6048 if (IS_QLA82XX(ha))
6049 qla82xx_watchdog(vha);
6050 else if (IS_QLA8044(ha))
6051 qla8044_watchdog(vha);
579d12b5
SK		 6052 }
6053
8ae6d9c7
GM		 6054 if (!vha->vp_idx && IS_QLAFX00(ha))
6055 qlafx00_timer_routine(vha);
6056
1da177e4 6057 /* Loop down handler. */
e315cd28 6058 if (atomic_read(&vha->loop_down_timer) > 0 &&
8f7daead
GM		 6059 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) &&
6060 !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags))
e315cd28 6061 && vha->flags.online) {
1da177e4 6062
e315cd28
AC		 6063 if (atomic_read(&vha->loop_down_timer) ==
6064 vha->loop_down_abort_time) {
1da177e4 6065
7c3df132
SK		 6066 ql_log(ql_log_info, vha, 0x6008,
6067 "Loop down - aborting the queues before time expires.\n");
1da177e4 6068
e315cd28
AC		 6069 if (!IS_QLA2100(ha) && vha->link_down_timeout)
6070 atomic_set(&vha->loop_state, LOOP_DEAD);
1da177e4 6071
f08b7251
AV		 6072 /*
6073 * Schedule an ISP abort to return any FCP2-device
6074 * commands.
6075 */
2c3dfe3f 6076 /* NPIV - scan physical port only */
e315cd28 6077 if (!vha->vp_idx) {
2c3dfe3f
SJ		 6078 spin_lock_irqsave(&ha->hardware_lock,
6079 cpu_flags);
73208dfd 6080 req = ha->req_q_map[0];
2c3dfe3f 6081 for (index = 1;
8d93f550 6082 index < req->num_outstanding_cmds;
2c3dfe3f
SJ		 6083 index++) {
6084 fc_port_t *sfcp;
6085
e315cd28 6086 sp = req->outstanding_cmds[index];
2c3dfe3f
SJ		 6087 if (!sp)
6088 continue;
c5419e26
QT		 6089 if (sp->cmd_type != TYPE_SRB)
6090 continue;
9ba56b95 6091 if (sp->type != SRB_SCSI_CMD)
cf53b069 6092 continue;
2c3dfe3f 6093 sfcp = sp->fcport;
f08b7251 6094 if (!(sfcp->flags & FCF_FCP2_DEVICE))
2c3dfe3f 6095 continue;
bdf79621 6096
8f7daead
GM		 6097 if (IS_QLA82XX(ha))
6098 set_bit(FCOE_CTX_RESET_NEEDED,
6099 &vha->dpc_flags);
6100 else
6101 set_bit(ISP_ABORT_NEEDED,
e315cd28 6102 &vha->dpc_flags);
2c3dfe3f
SJ		 6103 break;
6104 }
6105 spin_unlock_irqrestore(&ha->hardware_lock,
e315cd28 6106 cpu_flags);
1da177e4 6107 }
1da177e4
LT		 6108 start_dpc++;
6109 }
6110
6111 /* if the loop has been down for 4 minutes, reinit adapter */
e315cd28 6112 if (atomic_dec_and_test(&vha->loop_down_timer) != 0) {
0d6e61bc 6113 if (!(vha->device_flags & DFLG_NO_CABLE)) {
7c3df132 6114 ql_log(ql_log_warn, vha, 0x6009,
1da177e4
LT		 6115 "Loop down - aborting ISP.\n");
6116
8f7daead
GM		 6117 if (IS_QLA82XX(ha))
6118 set_bit(FCOE_CTX_RESET_NEEDED,
6119 &vha->dpc_flags);
6120 else
6121 set_bit(ISP_ABORT_NEEDED,
6122 &vha->dpc_flags);
1da177e4
LT		 6123 }
6124 }
7c3df132
SK		 6125 ql_dbg(ql_dbg_timer, vha, 0x600a,
6126 "Loop down - seconds remaining %d.\n",
6127 atomic_read(&vha->loop_down_timer));
1da177e4 6128 }
cefcaba6
SK		 6129 /* Check if beacon LED needs to be blinked for physical host only */
6130 if (!vha->vp_idx && (ha->beacon_blink_led == 1)) {
999916dc 6131 /* There is no beacon_blink function for ISP82xx */
7ec0effd 6132 if (!IS_P3P_TYPE(ha)) {
999916dc
SK		 6133 set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags);
6134 start_dpc++;
6135 }
f6df144c 6136 }
6137
550bf57d 6138 /* Process any deferred work. */
e315cd28 6139 if (!list_empty(&vha->work_list))
550bf57d
AV		 6140 start_dpc++;
6141
7401bc18
DG		 6142 /*
6143 * FC-NVME
6144 * see if the active AEN count has changed from what was last reported.
6145 */
deeae7a6
DG		 6146 if (!vha->vp_idx &&
6147 atomic_read(&ha->nvme_active_aen_cnt) != ha->nvme_last_rptd_aen &&
6148 ha->zio_mode == QLA_ZIO_MODE_6) {
7401bc18 6149 ql_log(ql_log_info, vha, 0x3002,
deeae7a6
DG		 6150 "nvme: Sched: Set ZIO exchange threshold to %d.\n",
6151 ha->nvme_last_rptd_aen);
6152 ha->nvme_last_rptd_aen = atomic_read(&ha->nvme_active_aen_cnt);
6153 set_bit(SET_ZIO_THRESHOLD_NEEDED, &vha->dpc_flags);
6154 start_dpc++;
7401bc18
DG		 6155 }
6156
1da177e4 6157 /* Schedule the DPC routine if needed */
e315cd28
AC		 6158 if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) ||
6159 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) ||
6160 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags) ||
1da177e4 6161 start_dpc ||
e315cd28
AC		 6162 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) ||
6163 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) ||
a9083016
GM		 6164 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) ||
6165 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) ||
e315cd28 6166 test_bit(VP_DPC_NEEDED, &vha->dpc_flags) ||
50280c01 6167 test_bit(RELOGIN_NEEDED, &vha->dpc_flags))) {
7c3df132
SK		 6168 ql_dbg(ql_dbg_timer, vha, 0x600b,
6169 "isp_abort_needed=%d loop_resync_needed=%d "
6170 "fcport_update_needed=%d start_dpc=%d "
6171 "reset_marker_needed=%d",
6172 test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags),
6173 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags),
6174 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags),
6175 start_dpc,
6176 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags));
6177 ql_dbg(ql_dbg_timer, vha, 0x600c,
6178 "beacon_blink_needed=%d isp_unrecoverable=%d "
6179 "fcoe_ctx_reset_needed=%d vp_dpc_needed=%d "
50280c01 6180 "relogin_needed=%d.\n",
7c3df132
SK		 6181 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags),
6182 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags),
6183 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags),
6184 test_bit(VP_DPC_NEEDED, &vha->dpc_flags),
50280c01 6185 test_bit(RELOGIN_NEEDED, &vha->dpc_flags));
e315cd28 6186 qla2xxx_wake_dpc(vha);
7c3df132 6187 }
1da177e4 6188
e315cd28 6189 qla2x00_restart_timer(vha, WATCH_INTERVAL);
1da177e4
LT		 6190}
6191
5433383e
AV		 6192/* Firmware interface routines. */
6193
f73cb695 6194#define FW_BLOBS 11
5433383e
AV		 6195#define FW_ISP21XX 0
6196#define FW_ISP22XX 1
6197#define FW_ISP2300 2
6198#define FW_ISP2322 3
48c02fde 6199#define FW_ISP24XX 4
c3a2f0df 6200#define FW_ISP25XX 5
3a03eb79 6201#define FW_ISP81XX 6
a9083016 6202#define FW_ISP82XX 7
6246b8a1
GM		 6203#define FW_ISP2031 8
6204#define FW_ISP8031 9
2c5bbbb2 6205#define FW_ISP27XX 10
5433383e 6206
bb8ee499
AV		 6207#define FW_FILE_ISP21XX "ql2100_fw.bin"
6208#define FW_FILE_ISP22XX "ql2200_fw.bin"
6209#define FW_FILE_ISP2300 "ql2300_fw.bin"
6210#define FW_FILE_ISP2322 "ql2322_fw.bin"
6211#define FW_FILE_ISP24XX "ql2400_fw.bin"
c3a2f0df 6212#define FW_FILE_ISP25XX "ql2500_fw.bin"
3a03eb79 6213#define FW_FILE_ISP81XX "ql8100_fw.bin"
a9083016 6214#define FW_FILE_ISP82XX "ql8200_fw.bin"
6246b8a1
GM		 6215#define FW_FILE_ISP2031 "ql2600_fw.bin"
6216#define FW_FILE_ISP8031 "ql8300_fw.bin"
2c5bbbb2 6217#define FW_FILE_ISP27XX "ql2700_fw.bin"
f73cb695 6218
bb8ee499 6219
e1e82b6f 6220static DEFINE_MUTEX(qla_fw_lock);
5433383e
AV		 6221
6222static struct fw_blob qla_fw_blobs[FW_BLOBS] = {
bb8ee499
AV		 6223 { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, },
6224 { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, },
6225 { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, },
6226 { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, },
6227 { .name = FW_FILE_ISP24XX, },
c3a2f0df 6228 { .name = FW_FILE_ISP25XX, },
3a03eb79 6229 { .name = FW_FILE_ISP81XX, },
a9083016 6230 { .name = FW_FILE_ISP82XX, },
6246b8a1
GM		 6231 { .name = FW_FILE_ISP2031, },
6232 { .name = FW_FILE_ISP8031, },
2c5bbbb2 6233 { .name = FW_FILE_ISP27XX, },
5433383e
AV		 6234};
6235
6236struct fw_blob *
e315cd28 6237qla2x00_request_firmware(scsi_qla_host_t *vha)
5433383e 6238{
e315cd28 6239 struct qla_hw_data *ha = vha->hw;
5433383e
AV		 6240 struct fw_blob *blob;
6241
5433383e
AV		 6242 if (IS_QLA2100(ha)) {
6243 blob = &qla_fw_blobs[FW_ISP21XX];
6244 } else if (IS_QLA2200(ha)) {
6245 blob = &qla_fw_blobs[FW_ISP22XX];
48c02fde 6246 } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
5433383e 6247 blob = &qla_fw_blobs[FW_ISP2300];
48c02fde 6248 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
5433383e 6249 blob = &qla_fw_blobs[FW_ISP2322];
4d4df193 6250 } else if (IS_QLA24XX_TYPE(ha)) {
5433383e 6251 blob = &qla_fw_blobs[FW_ISP24XX];
c3a2f0df
AV		 6252 } else if (IS_QLA25XX(ha)) {
6253 blob = &qla_fw_blobs[FW_ISP25XX];
3a03eb79
AV		 6254 } else if (IS_QLA81XX(ha)) {
6255 blob = &qla_fw_blobs[FW_ISP81XX];
a9083016
GM		 6256 } else if (IS_QLA82XX(ha)) {
6257 blob = &qla_fw_blobs[FW_ISP82XX];
6246b8a1
GM		 6258 } else if (IS_QLA2031(ha)) {
6259 blob = &qla_fw_blobs[FW_ISP2031];
6260 } else if (IS_QLA8031(ha)) {
6261 blob = &qla_fw_blobs[FW_ISP8031];
2c5bbbb2
JC		 6262 } else if (IS_QLA27XX(ha)) {
6263 blob = &qla_fw_blobs[FW_ISP27XX];
8a655229
DC		 6264 } else {
6265 return NULL;
5433383e
AV		 6266 }
6267
e1e82b6f 6268 mutex_lock(&qla_fw_lock);
5433383e
AV		 6269 if (blob->fw)
6270 goto out;
6271
6272 if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) {
7c3df132
SK		 6273 ql_log(ql_log_warn, vha, 0x0063,
6274 "Failed to load firmware image (%s).\n", blob->name);
5433383e
AV		 6275 blob->fw = NULL;
6276 blob = NULL;
6277 goto out;
6278 }
6279
6280out:
e1e82b6f 6281 mutex_unlock(&qla_fw_lock);
5433383e
AV		 6282 return blob;
6283}
6284
6285static void
6286qla2x00_release_firmware(void)
6287{
6288 int idx;
6289
e1e82b6f 6290 mutex_lock(&qla_fw_lock);
5433383e 6291 for (idx = 0; idx < FW_BLOBS; idx++)
cf92549f 6292 release_firmware(qla_fw_blobs[idx].fw);
e1e82b6f 6293 mutex_unlock(&qla_fw_lock);
5433383e
AV		 6294}
6295
14e660e6
SJ		 6296static pci_ers_result_t
6297qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
6298{
85880801
AV		 6299 scsi_qla_host_t *vha = pci_get_drvdata(pdev);
6300 struct qla_hw_data *ha = vha->hw;
6301
7c3df132
SK		 6302 ql_dbg(ql_dbg_aer, vha, 0x9000,
6303 "PCI error detected, state %x.\n", state);
b9b12f73 6304
efdb5760
SC		 6305 if (!atomic_read(&pdev->enable_cnt)) {
6306 ql_log(ql_log_info, vha, 0xffff,
6307 "PCI device is disabled,state %x\n", state);
6308 return PCI_ERS_RESULT_NEED_RESET;
6309 }
6310
14e660e6
SJ		 6311 switch (state) {
6312 case pci_channel_io_normal:
85880801 6313 ha->flags.eeh_busy = 0;
c38d1baf 6314 if (ql2xmqsupport || ql2xnvmeenable) {
d7459527
MH		 6315 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags);
6316 qla2xxx_wake_dpc(vha);
6317 }
14e660e6
SJ		 6318 return PCI_ERS_RESULT_CAN_RECOVER;
6319 case pci_channel_io_frozen:
85880801 6320 ha->flags.eeh_busy = 1;
a5b36321
LC		 6321 /* For ISP82XX complete any pending mailbox cmd */
6322 if (IS_QLA82XX(ha)) {
7190575f 6323 ha->flags.isp82xx_fw_hung = 1;
c8f6544e
CD		 6324 ql_dbg(ql_dbg_aer, vha, 0x9001, "Pci channel io frozen\n");
6325 qla82xx_clear_pending_mbx(vha);
a5b36321 6326 }
90a86fc0 6327 qla2x00_free_irqs(vha);
14e660e6 6328 pci_disable_device(pdev);
bddd2d65
LC		 6329 /* Return back all IOs */
6330 qla2x00_abort_all_cmds(vha, DID_RESET << 16);
c38d1baf 6331 if (ql2xmqsupport || ql2xnvmeenable) {
d7459527
MH		 6332 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags);
6333 qla2xxx_wake_dpc(vha);
6334 }
14e660e6
SJ		 6335 return PCI_ERS_RESULT_NEED_RESET;
6336 case pci_channel_io_perm_failure:
85880801
AV		 6337 ha->flags.pci_channel_io_perm_failure = 1;
6338 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
c38d1baf 6339 if (ql2xmqsupport || ql2xnvmeenable) {
d7459527
MH		 6340 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags);
6341 qla2xxx_wake_dpc(vha);
6342 }
14e660e6
SJ		 6343 return PCI_ERS_RESULT_DISCONNECT;
6344 }
6345 return PCI_ERS_RESULT_NEED_RESET;
6346}
6347
6348static pci_ers_result_t
6349qla2xxx_pci_mmio_enabled(struct pci_dev *pdev)
6350{
6351 int risc_paused = 0;
6352 uint32_t stat;
6353 unsigned long flags;
e315cd28
AC		 6354 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
6355 struct qla_hw_data *ha = base_vha->hw;
14e660e6
SJ		 6356 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
6357 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
6358
bcc5b6d3
SK		 6359 if (IS_QLA82XX(ha))
6360 return PCI_ERS_RESULT_RECOVERED;
6361
14e660e6
SJ		 6362 spin_lock_irqsave(&ha->hardware_lock, flags);
6363 if (IS_QLA2100(ha) || IS_QLA2200(ha)){
6364 stat = RD_REG_DWORD(&reg->hccr);
6365 if (stat & HCCR_RISC_PAUSE)
6366 risc_paused = 1;
6367 } else if (IS_QLA23XX(ha)) {
6368 stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
6369 if (stat & HSR_RISC_PAUSED)
6370 risc_paused = 1;
6371 } else if (IS_FWI2_CAPABLE(ha)) {
6372 stat = RD_REG_DWORD(&reg24->host_status);
6373 if (stat & HSRX_RISC_PAUSED)
6374 risc_paused = 1;
6375 }
6376 spin_unlock_irqrestore(&ha->hardware_lock, flags);
6377
6378 if (risc_paused) {
7c3df132
SK		 6379 ql_log(ql_log_info, base_vha, 0x9003,
6380 "RISC paused -- mmio_enabled, Dumping firmware.\n");
e315cd28 6381 ha->isp_ops->fw_dump(base_vha, 0);
14e660e6
SJ		 6382
6383 return PCI_ERS_RESULT_NEED_RESET;
6384 } else
6385 return PCI_ERS_RESULT_RECOVERED;
6386}
6387
fa492630
SK		 6388static uint32_t
6389qla82xx_error_recovery(scsi_qla_host_t *base_vha)
a5b36321
LC		 6390{
6391 uint32_t rval = QLA_FUNCTION_FAILED;
6392 uint32_t drv_active = 0;
6393 struct qla_hw_data *ha = base_vha->hw;
6394 int fn;
6395 struct pci_dev *other_pdev = NULL;
6396
7c3df132
SK		 6397 ql_dbg(ql_dbg_aer, base_vha, 0x9006,
6398 "Entered %s.\n", __func__);
a5b36321
LC		 6399
6400 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
6401
6402 if (base_vha->flags.online) {
6403 /* Abort all outstanding commands,
6404 * so as to be requeued later */
6405 qla2x00_abort_isp_cleanup(base_vha);
6406 }
6407
6408
6409 fn = PCI_FUNC(ha->pdev->devfn);
6410 while (fn > 0) {
6411 fn--;
7c3df132
SK		 6412 ql_dbg(ql_dbg_aer, base_vha, 0x9007,
6413 "Finding pci device at function = 0x%x.\n", fn);
a5b36321
LC		 6414 other_pdev =
6415 pci_get_domain_bus_and_slot(pci_domain_nr(ha->pdev->bus),
6416 ha->pdev->bus->number, PCI_DEVFN(PCI_SLOT(ha->pdev->devfn),
6417 fn));
6418
6419 if (!other_pdev)
6420 continue;
6421 if (atomic_read(&other_pdev->enable_cnt)) {
7c3df132
SK		 6422 ql_dbg(ql_dbg_aer, base_vha, 0x9008,
6423 "Found PCI func available and enable at 0x%x.\n",
6424 fn);
a5b36321
LC		 6425 pci_dev_put(other_pdev);
6426 break;
6427 }
6428 pci_dev_put(other_pdev);
6429 }
6430
6431 if (!fn) {
6432 /* Reset owner */
7c3df132
SK		 6433 ql_dbg(ql_dbg_aer, base_vha, 0x9009,
6434 "This devfn is reset owner = 0x%x.\n",
6435 ha->pdev->devfn);
a5b36321
LC		 6436 qla82xx_idc_lock(ha);
6437
6438 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 6439 QLA8XXX_DEV_INITIALIZING);
a5b36321
LC		 6440
6441 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION,
6442 QLA82XX_IDC_VERSION);
6443
6444 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
7c3df132
SK		 6445 ql_dbg(ql_dbg_aer, base_vha, 0x900a,
6446 "drv_active = 0x%x.\n", drv_active);
a5b36321
LC		 6447
6448 qla82xx_idc_unlock(ha);
6449 /* Reset if device is not already reset
6450 * drv_active would be 0 if a reset has already been done
6451 */
6452 if (drv_active)
6453 rval = qla82xx_start_firmware(base_vha);
6454 else
6455 rval = QLA_SUCCESS;
6456 qla82xx_idc_lock(ha);
6457
6458 if (rval != QLA_SUCCESS) {
7c3df132
SK		 6459 ql_log(ql_log_info, base_vha, 0x900b,
6460 "HW State: FAILED.\n");
a5b36321
LC		 6461 qla82xx_clear_drv_active(ha);
6462 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 6463 QLA8XXX_DEV_FAILED);
a5b36321 6464 } else {
7c3df132
SK		 6465 ql_log(ql_log_info, base_vha, 0x900c,
6466 "HW State: READY.\n");
a5b36321 6467 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 6468 QLA8XXX_DEV_READY);
a5b36321 6469 qla82xx_idc_unlock(ha);
7190575f 6470 ha->flags.isp82xx_fw_hung = 0;
a5b36321
LC		 6471 rval = qla82xx_restart_isp(base_vha);
6472 qla82xx_idc_lock(ha);
6473 /* Clear driver state register */
6474 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, 0);
6475 qla82xx_set_drv_active(base_vha);
6476 }
6477 qla82xx_idc_unlock(ha);
6478 } else {
7c3df132
SK		 6479 ql_dbg(ql_dbg_aer, base_vha, 0x900d,
6480 "This devfn is not reset owner = 0x%x.\n",
6481 ha->pdev->devfn);
a5b36321 6482 if ((qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE) ==
7d613ac6 6483 QLA8XXX_DEV_READY)) {
7190575f 6484 ha->flags.isp82xx_fw_hung = 0;
a5b36321
LC		 6485 rval = qla82xx_restart_isp(base_vha);
6486 qla82xx_idc_lock(ha);
6487 qla82xx_set_drv_active(base_vha);
6488 qla82xx_idc_unlock(ha);
6489 }
6490 }
6491 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
6492
6493 return rval;
6494}
6495
14e660e6
SJ		 6496static pci_ers_result_t
6497qla2xxx_pci_slot_reset(struct pci_dev *pdev)
6498{
6499 pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT;
e315cd28
AC		 6500 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
6501 struct qla_hw_data *ha = base_vha->hw;
90a86fc0
JC		 6502 struct rsp_que *rsp;
6503 int rc, retries = 10;
09483916 6504
7c3df132
SK		 6505 ql_dbg(ql_dbg_aer, base_vha, 0x9004,
6506 "Slot Reset.\n");
85880801 6507
90a86fc0
JC		 6508 /* Workaround: qla2xxx driver which access hardware earlier
6509 * needs error state to be pci_channel_io_online.
6510 * Otherwise mailbox command timesout.
6511 */
6512 pdev->error_state = pci_channel_io_normal;
6513
6514 pci_restore_state(pdev);
6515
8c1496bd
RL		 6516 /* pci_restore_state() clears the saved_state flag of the device
6517 * save restored state which resets saved_state flag
6518 */
6519 pci_save_state(pdev);
6520
09483916
BH		 6521 if (ha->mem_only)
6522 rc = pci_enable_device_mem(pdev);
6523 else
6524 rc = pci_enable_device(pdev);
14e660e6 6525
09483916 6526 if (rc) {
7c3df132 6527 ql_log(ql_log_warn, base_vha, 0x9005,
14e660e6 6528 "Can't re-enable PCI device after reset.\n");
a5b36321 6529 goto exit_slot_reset;
14e660e6 6530 }
14e660e6 6531
90a86fc0
JC		 6532 rsp = ha->rsp_q_map[0];
6533 if (qla2x00_request_irqs(ha, rsp))
a5b36321 6534 goto exit_slot_reset;
90a86fc0 6535
e315cd28 6536 if (ha->isp_ops->pci_config(base_vha))
a5b36321
LC		 6537 goto exit_slot_reset;
6538
6539 if (IS_QLA82XX(ha)) {
6540 if (qla82xx_error_recovery(base_vha) == QLA_SUCCESS) {
6541 ret = PCI_ERS_RESULT_RECOVERED;
6542 goto exit_slot_reset;
6543 } else
6544 goto exit_slot_reset;
6545 }
14e660e6 6546
90a86fc0
JC		 6547 while (ha->flags.mbox_busy && retries--)
6548 msleep(1000);
85880801 6549
e315cd28 6550 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
a9083016 6551 if (ha->isp_ops->abort_isp(base_vha) == QLA_SUCCESS)
14e660e6 6552 ret = PCI_ERS_RESULT_RECOVERED;
e315cd28 6553 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
14e660e6 6554
90a86fc0 6555
a5b36321 6556exit_slot_reset:
7c3df132
SK		 6557 ql_dbg(ql_dbg_aer, base_vha, 0x900e,
6558 "slot_reset return %x.\n", ret);
85880801 6559
14e660e6
SJ		 6560 return ret;
6561}
6562
6563static void
6564qla2xxx_pci_resume(struct pci_dev *pdev)
6565{
e315cd28
AC		 6566 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
6567 struct qla_hw_data *ha = base_vha->hw;
14e660e6
SJ		 6568 int ret;
6569
7c3df132
SK		 6570 ql_dbg(ql_dbg_aer, base_vha, 0x900f,
6571 "pci_resume.\n");
85880801 6572
e315cd28 6573 ret = qla2x00_wait_for_hba_online(base_vha);
14e660e6 6574 if (ret != QLA_SUCCESS) {
7c3df132
SK		 6575 ql_log(ql_log_fatal, base_vha, 0x9002,
6576 "The device failed to resume I/O from slot/link_reset.\n");
14e660e6 6577 }
85880801 6578
3e46f031
LC		 6579 pci_cleanup_aer_uncorrect_error_status(pdev);
6580
85880801 6581 ha->flags.eeh_busy = 0;
14e660e6
SJ		 6582}
6583
2d5a4c34
HM		 6584static void
6585qla83xx_disable_laser(scsi_qla_host_t *vha)
6586{
6587 uint32_t reg, data, fn;
6588 struct qla_hw_data *ha = vha->hw;
6589 struct device_reg_24xx __iomem *isp_reg = &ha->iobase->isp24;
6590
6591 /* pci func #/port # */
6592 ql_dbg(ql_dbg_init, vha, 0x004b,
6593 "Disabling Laser for hba: %p\n", vha);
6594
6595 fn = (RD_REG_DWORD(&isp_reg->ctrl_status) &
6596 (BIT_15|BIT_14|BIT_13|BIT_12));
6597
6598 fn = (fn >> 12);
6599
6600 if (fn & 1)
6601 reg = PORT_1_2031;
6602 else
6603 reg = PORT_0_2031;
6604
6605 data = LASER_OFF_2031;
6606
6607 qla83xx_wr_reg(vha, reg, data);
6608}
6609
5601236b
MH		 6610static int qla2xxx_map_queues(struct Scsi_Host *shost)
6611{
d68b850e 6612 int rc;
5601236b
MH		 6613 scsi_qla_host_t *vha = (scsi_qla_host_t *)shost->hostdata;
6614
d68b850e
QT		 6615 if (USER_CTRL_IRQ(vha->hw))
6616 rc = blk_mq_map_queues(&shost->tag_set);
6617 else
6618 rc = blk_mq_pci_map_queues(&shost->tag_set, vha->hw->pdev);
6619 return rc;
5601236b
MH		 6620}
6621
a55b2d21 6622static const struct pci_error_handlers qla2xxx_err_handler = {
14e660e6
SJ		 6623 .error_detected = qla2xxx_pci_error_detected,
6624 .mmio_enabled = qla2xxx_pci_mmio_enabled,
6625 .slot_reset = qla2xxx_pci_slot_reset,
6626 .resume = qla2xxx_pci_resume,
6627};
6628
5433383e 6629static struct pci_device_id qla2xxx_pci_tbl[] = {
47f5e069
AV		 6630 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) },
6631 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) },
6632 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) },
6633 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) },
6634 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) },
6635 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) },
6636 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) },
6637 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) },
6638 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) },
4d4df193 6639 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) },
47f5e069
AV		 6640 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) },
6641 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) },
c3a2f0df 6642 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) },
6246b8a1 6643 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2031) },
3a03eb79 6644 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) },
a9083016 6645 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) },
650f528f 6646 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8031) },
8ae6d9c7 6647 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISPF001) },
7ec0effd 6648 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8044) },
f73cb695 6649 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2071) },
2c5bbbb2 6650 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2271) },
2b48992f 6651 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2261) },
5433383e
AV		 6652 { 0 },
6653};
6654MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl);
6655
fca29703 6656static struct pci_driver qla2xxx_pci_driver = {
cb63067a 6657 .name = QLA2XXX_DRIVER_NAME,
0a21ef1e
JB		 6658 .driver = {
6659 .owner = THIS_MODULE,
6660 },
fca29703 6661 .id_table = qla2xxx_pci_tbl,
7ee61397 6662 .probe = qla2x00_probe_one,
4c993f76 6663 .remove = qla2x00_remove_one,
e30d1756 6664 .shutdown = qla2x00_shutdown,
14e660e6 6665 .err_handler = &qla2xxx_err_handler,
fca29703
AV		 6666};
6667
75ef9de1 6668static const struct file_operations apidev_fops = {
6a03b4cd 6669 .owner = THIS_MODULE,
6038f373 6670 .llseek = noop_llseek,
6a03b4cd
HZ		 6671};
6672
1da177e4
LT		 6673/**
6674 * qla2x00_module_init - Module initialization.
6675 **/
6676static int __init
6677qla2x00_module_init(void)
6678{
fca29703
AV		 6679 int ret = 0;
6680
1da177e4 6681 /* Allocate cache for SRBs. */
354d6b21 6682 srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0,
20c2df83 6683 SLAB_HWCACHE_ALIGN, NULL);
1da177e4 6684 if (srb_cachep == NULL) {
7c3df132
SK		 6685 ql_log(ql_log_fatal, NULL, 0x0001,
6686 "Unable to allocate SRB cache...Failing load!.\n");
1da177e4
LT		 6687 return -ENOMEM;
6688 }
6689
2d70c103
NB		 6690 /* Initialize target kmem_cache and mem_pools */
6691 ret = qlt_init();
6692 if (ret < 0) {
6693 kmem_cache_destroy(srb_cachep);
6694 return ret;
6695 } else if (ret > 0) {
6696 /*
6697 * If initiator mode is explictly disabled by qlt_init(),
6698 * prevent scsi_transport_fc.c:fc_scsi_scan_rport() from
6699 * performing scsi_scan_target() during LOOP UP event.
6700 */
6701 qla2xxx_transport_functions.disable_target_scan = 1;
6702 qla2xxx_transport_vport_functions.disable_target_scan = 1;
6703 }
6704
1da177e4
LT		 6705 /* Derive version string. */
6706 strcpy(qla2x00_version_str, QLA2XXX_VERSION);
11010fec 6707 if (ql2xextended_error_logging)
0181944f 6708 strcat(qla2x00_version_str, "-debug");
fed0f68a
JC		 6709 if (ql2xextended_error_logging == 1)
6710 ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK;
0181944f 6711
1c97a12a
AV		 6712 qla2xxx_transport_template =
6713 fc_attach_transport(&qla2xxx_transport_functions);
2c3dfe3f
SJ		 6714 if (!qla2xxx_transport_template) {
6715 kmem_cache_destroy(srb_cachep);
7c3df132
SK		 6716 ql_log(ql_log_fatal, NULL, 0x0002,
6717 "fc_attach_transport failed...Failing load!.\n");
2d70c103 6718 qlt_exit();
1da177e4 6719 return -ENODEV;
2c3dfe3f 6720 }
6a03b4cd
HZ		 6721
6722 apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops);
6723 if (apidev_major < 0) {
7c3df132
SK		 6724 ql_log(ql_log_fatal, NULL, 0x0003,
6725 "Unable to register char device %s.\n", QLA2XXX_APIDEV);
6a03b4cd
HZ		 6726 }
6727
2c3dfe3f
SJ		 6728 qla2xxx_transport_vport_template =
6729 fc_attach_transport(&qla2xxx_transport_vport_functions);
6730 if (!qla2xxx_transport_vport_template) {
6731 kmem_cache_destroy(srb_cachep);
2d70c103 6732 qlt_exit();
2c3dfe3f 6733 fc_release_transport(qla2xxx_transport_template);
7c3df132
SK		 6734 ql_log(ql_log_fatal, NULL, 0x0004,
6735 "fc_attach_transport vport failed...Failing load!.\n");
1da177e4 6736 return -ENODEV;
2c3dfe3f 6737 }
7c3df132
SK		 6738 ql_log(ql_log_info, NULL, 0x0005,
6739 "QLogic Fibre Channel HBA Driver: %s.\n",
fd9a29f0 6740 qla2x00_version_str);
7ee61397 6741 ret = pci_register_driver(&qla2xxx_pci_driver);
fca29703
AV		 6742 if (ret) {
6743 kmem_cache_destroy(srb_cachep);
2d70c103 6744 qlt_exit();
fca29703 6745 fc_release_transport(qla2xxx_transport_template);
2c3dfe3f 6746 fc_release_transport(qla2xxx_transport_vport_template);
7c3df132
SK		 6747 ql_log(ql_log_fatal, NULL, 0x0006,
6748 "pci_register_driver failed...ret=%d Failing load!.\n",
6749 ret);
fca29703
AV		 6750 }
6751 return ret;
1da177e4
LT		 6752}
6753
6754/**
6755 * qla2x00_module_exit - Module cleanup.
6756 **/
6757static void __exit
6758qla2x00_module_exit(void)
6759{
6a03b4cd 6760 unregister_chrdev(apidev_major, QLA2XXX_APIDEV);
7ee61397 6761 pci_unregister_driver(&qla2xxx_pci_driver);
5433383e 6762 qla2x00_release_firmware();
354d6b21 6763 kmem_cache_destroy(srb_cachep);
2d70c103 6764 qlt_exit();
a9083016
GM		 6765 if (ctx_cachep)
6766 kmem_cache_destroy(ctx_cachep);
1da177e4 6767 fc_release_transport(qla2xxx_transport_template);
2c3dfe3f 6768 fc_release_transport(qla2xxx_transport_vport_template);
1da177e4
LT		 6769}
6770
6771module_init(qla2x00_module_init);
6772module_exit(qla2x00_module_exit);
6773
6774MODULE_AUTHOR("QLogic Corporation");
6775MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver");
6776MODULE_LICENSE("GPL");
6777MODULE_VERSION(QLA2XXX_VERSION);
bb8ee499
AV		 6778MODULE_FIRMWARE(FW_FILE_ISP21XX);
6779MODULE_FIRMWARE(FW_FILE_ISP22XX);
6780MODULE_FIRMWARE(FW_FILE_ISP2300);
6781MODULE_FIRMWARE(FW_FILE_ISP2322);
6782MODULE_FIRMWARE(FW_FILE_ISP24XX);
61623fc3 6783MODULE_FIRMWARE(FW_FILE_ISP25XX);
Linux 6.x block layer and io_uring tree(s)