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scsi: qla2xxx: Add appropriate debug info for invalid RX_ID
[linux-2.6-block.git] / drivers / scsi / qla2xxx / qla_os.c
CommitLineData
1da177e4 1/*
fa90c54f 2 * QLogic Fibre Channel HBA Driver
bd21eaf9 3 * Copyright (c) 2003-2014 QLogic Corporation
1da177e4 4 *
fa90c54f 5 * See LICENSE.qla2xxx for copyright and licensing details.
1da177e4
LT		 6 */
7#include "qla_def.h"
8
9#include <linux/moduleparam.h>
10#include <linux/vmalloc.h>
1da177e4 11#include <linux/delay.h>
39a11240 12#include <linux/kthread.h>
e1e82b6f 13#include <linux/mutex.h>
3420d36c 14#include <linux/kobject.h>
5a0e3ad6 15#include <linux/slab.h>
5601236b 16#include <linux/blk-mq-pci.h>
1da177e4
LT		 17#include <scsi/scsi_tcq.h>
18#include <scsi/scsicam.h>
19#include <scsi/scsi_transport.h>
20#include <scsi/scsi_transport_fc.h>
21
2d70c103
NB		 22#include "qla_target.h"
23
1da177e4
LT		 24/*
25 * Driver version
26 */
27char qla2x00_version_str[40];
28
6a03b4cd
HZ		 29static int apidev_major;
30
1da177e4
LT		 31/*
32 * SRB allocation cache
33 */
d7459527 34struct kmem_cache *srb_cachep;
1da177e4 35
a9083016
GM		 36/*
37 * CT6 CTX allocation cache
38 */
39static struct kmem_cache *ctx_cachep;
3ce8866c
SK		 40/*
41 * error level for logging
42 */
43int ql_errlev = ql_log_all;
a9083016 44
fa492630 45static int ql2xenableclass2;
2d70c103
NB		 46module_param(ql2xenableclass2, int, S_IRUGO|S_IRUSR);
47MODULE_PARM_DESC(ql2xenableclass2,
48 "Specify if Class 2 operations are supported from the very "
49 "beginning. Default is 0 - class 2 not supported.");
50
8ae6d9c7 51
1da177e4 52int ql2xlogintimeout = 20;
f2019cb1 53module_param(ql2xlogintimeout, int, S_IRUGO);
1da177e4
LT		 54MODULE_PARM_DESC(ql2xlogintimeout,
55 "Login timeout value in seconds.");
56
a7b61842 57int qlport_down_retry;
f2019cb1 58module_param(qlport_down_retry, int, S_IRUGO);
1da177e4 59MODULE_PARM_DESC(qlport_down_retry,
900d9f98 60 "Maximum number of command retries to a port that returns "
1da177e4
LT		 61 "a PORT-DOWN status.");
62
1da177e4
LT		 63int ql2xplogiabsentdevice;
64module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR);
65MODULE_PARM_DESC(ql2xplogiabsentdevice,
66 "Option to enable PLOGI to devices that are not present after "
900d9f98 67 "a Fabric scan. This is needed for several broken switches. "
1da177e4
LT		 68 "Default is 0 - no PLOGI. 1 - perfom PLOGI.");
69
1da177e4 70int ql2xloginretrycount = 0;
f2019cb1 71module_param(ql2xloginretrycount, int, S_IRUGO);
1da177e4
LT		 72MODULE_PARM_DESC(ql2xloginretrycount,
73 "Specify an alternate value for the NVRAM login retry count.");
74
a7a167bf 75int ql2xallocfwdump = 1;
f2019cb1 76module_param(ql2xallocfwdump, int, S_IRUGO);
a7a167bf
AV		 77MODULE_PARM_DESC(ql2xallocfwdump,
78 "Option to enable allocation of memory for a firmware dump "
79 "during HBA initialization. Memory allocation requirements "
80 "vary by ISP type. Default is 1 - allocate memory.");
81
11010fec 82int ql2xextended_error_logging;
27d94035 83module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
a2b3e01d 84module_param_named(logging, ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
11010fec 85MODULE_PARM_DESC(ql2xextended_error_logging,
3ce8866c
SK		 86 "Option to enable extended error logging,\n"
87 "\t\tDefault is 0 - no logging. 0x40000000 - Module Init & Probe.\n"
88 "\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n"
89 "\t\t0x08000000 - IO tracing. 0x04000000 - DPC Thread.\n"
90 "\t\t0x02000000 - Async events. 0x01000000 - Timer routines.\n"
91 "\t\t0x00800000 - User space. 0x00400000 - Task Management.\n"
92 "\t\t0x00200000 - AER/EEH. 0x00100000 - Multi Q.\n"
93 "\t\t0x00080000 - P3P Specific. 0x00040000 - Virtual Port.\n"
94 "\t\t0x00020000 - Buffer Dump. 0x00010000 - Misc.\n"
29f9f90c
CD		 95 "\t\t0x00008000 - Verbose. 0x00004000 - Target.\n"
96 "\t\t0x00002000 - Target Mgmt. 0x00001000 - Target TMF.\n"
3ce8866c 97 "\t\t0x7fffffff - For enabling all logs, can be too many logs.\n"
cfb0919c
CD		 98 "\t\t0x1e400000 - Preferred value for capturing essential "
99 "debug information (equivalent to old "
100 "ql2xextended_error_logging=1).\n"
3ce8866c 101 "\t\tDo LOGICAL OR of the value to enable more than one level");
0181944f 102
a9083016 103int ql2xshiftctondsd = 6;
f2019cb1 104module_param(ql2xshiftctondsd, int, S_IRUGO);
a9083016
GM		 105MODULE_PARM_DESC(ql2xshiftctondsd,
106 "Set to control shifting of command type processing "
107 "based on total number of SG elements.");
108
7e47e5ca 109int ql2xfdmienable=1;
de187df8 110module_param(ql2xfdmienable, int, S_IRUGO|S_IWUSR);
a2b3e01d 111module_param_named(fdmi, ql2xfdmienable, int, S_IRUGO|S_IWUSR);
cca5335c 112MODULE_PARM_DESC(ql2xfdmienable,
7794a5af
FW		 113 "Enables FDMI registrations. "
114 "0 - no FDMI. Default is 1 - perform FDMI.");
cca5335c 115
d213a4b7 116#define MAX_Q_DEPTH 64
50280c01 117static int ql2xmaxqdepth = MAX_Q_DEPTH;
df7baa50
AV		 118module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR);
119MODULE_PARM_DESC(ql2xmaxqdepth,
e92e4a8f 120 "Maximum queue depth to set for each LUN. "
d213a4b7 121 "Default is 64.");
df7baa50 122
e84067d7
DG		 123#if (IS_ENABLED(CONFIG_NVME_FC))
124int ql2xenabledif;
125#else
9e522cd8 126int ql2xenabledif = 2;
e84067d7 127#endif
9e522cd8 128module_param(ql2xenabledif, int, S_IRUGO);
bad75002 129MODULE_PARM_DESC(ql2xenabledif,
b97f5d0b
SM		 130 " Enable T10-CRC-DIF:\n"
131 " Default is 2.\n"
132 " 0 -- No DIF Support\n"
133 " 1 -- Enable DIF for all types\n"
134 " 2 -- Enable DIF for all types, except Type 0.\n");
bad75002 135
e84067d7
DG		 136#if (IS_ENABLED(CONFIG_NVME_FC))
137int ql2xnvmeenable = 1;
138#else
139int ql2xnvmeenable;
140#endif
141module_param(ql2xnvmeenable, int, 0644);
142MODULE_PARM_DESC(ql2xnvmeenable,
143 "Enables NVME support. "
144 "0 - no NVMe. Default is Y");
145
8cb2049c 146int ql2xenablehba_err_chk = 2;
bad75002
AE		 147module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR);
148MODULE_PARM_DESC(ql2xenablehba_err_chk,
8cb2049c 149 " Enable T10-CRC-DIF Error isolation by HBA:\n"
b97f5d0b 150 " Default is 2.\n"
8cb2049c
AE		 151 " 0 -- Error isolation disabled\n"
152 " 1 -- Error isolation enabled only for DIX Type 0\n"
153 " 2 -- Error isolation enabled for all Types\n");
bad75002 154
e5896bd5 155int ql2xiidmaenable=1;
f2019cb1 156module_param(ql2xiidmaenable, int, S_IRUGO);
e5896bd5
AV		 157MODULE_PARM_DESC(ql2xiidmaenable,
158 "Enables iIDMA settings "
159 "Default is 1 - perform iIDMA. 0 - no iIDMA.");
160
d7459527
MH		 161int ql2xmqsupport = 1;
162module_param(ql2xmqsupport, int, S_IRUGO);
163MODULE_PARM_DESC(ql2xmqsupport,
164 "Enable on demand multiple queue pairs support "
165 "Default is 1 for supported. "
166 "Set it to 0 to turn off mq qpair support.");
e337d907
AV		 167
168int ql2xfwloadbin;
86e45bf6 169module_param(ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
a2b3e01d 170module_param_named(fwload, ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
e337d907 171MODULE_PARM_DESC(ql2xfwloadbin,
7c3df132
SK		 172 "Option to specify location from which to load ISP firmware:.\n"
173 " 2 -- load firmware via the request_firmware() (hotplug).\n"
e337d907
AV		 174 " interface.\n"
175 " 1 -- load firmware from flash.\n"
176 " 0 -- use default semantics.\n");
177
ae97c91e 178int ql2xetsenable;
f2019cb1 179module_param(ql2xetsenable, int, S_IRUGO);
ae97c91e
AV		 180MODULE_PARM_DESC(ql2xetsenable,
181 "Enables firmware ETS burst."
182 "Default is 0 - skip ETS enablement.");
183
6907869d 184int ql2xdbwr = 1;
86e45bf6 185module_param(ql2xdbwr, int, S_IRUGO|S_IWUSR);
a9083016 186MODULE_PARM_DESC(ql2xdbwr,
08de2844
GM		 187 "Option to specify scheme for request queue posting.\n"
188 " 0 -- Regular doorbell.\n"
189 " 1 -- CAMRAM doorbell (faster).\n");
a9083016 190
f4c496c1 191int ql2xtargetreset = 1;
f2019cb1 192module_param(ql2xtargetreset, int, S_IRUGO);
f4c496c1
GM		 193MODULE_PARM_DESC(ql2xtargetreset,
194 "Enable target reset."
195 "Default is 1 - use hw defaults.");
196
4da26e16 197int ql2xgffidenable;
f2019cb1 198module_param(ql2xgffidenable, int, S_IRUGO);
4da26e16
CD		 199MODULE_PARM_DESC(ql2xgffidenable,
200 "Enables GFF_ID checks of port type. "
201 "Default is 0 - Do not use GFF_ID information.");
a9083016 202
043dc1d7 203int ql2xasynctmfenable = 1;
f2019cb1 204module_param(ql2xasynctmfenable, int, S_IRUGO);
3822263e
MI		 205MODULE_PARM_DESC(ql2xasynctmfenable,
206 "Enables issue of TM IOCBs asynchronously via IOCB mechanism"
207 "Default is 0 - Issue TM IOCBs via mailbox mechanism.");
ed0de87c
GM		 208
209int ql2xdontresethba;
86e45bf6 210module_param(ql2xdontresethba, int, S_IRUGO|S_IWUSR);
ed0de87c 211MODULE_PARM_DESC(ql2xdontresethba,
08de2844
GM		 212 "Option to specify reset behaviour.\n"
213 " 0 (Default) -- Reset on failure.\n"
214 " 1 -- Do not reset on failure.\n");
ed0de87c 215
1abf635d
HR		 216uint64_t ql2xmaxlun = MAX_LUNS;
217module_param(ql2xmaxlun, ullong, S_IRUGO);
82515920
AV		 218MODULE_PARM_DESC(ql2xmaxlun,
219 "Defines the maximum LU number to register with the SCSI "
220 "midlayer. Default is 65535.");
221
08de2844
GM		 222int ql2xmdcapmask = 0x1F;
223module_param(ql2xmdcapmask, int, S_IRUGO);
224MODULE_PARM_DESC(ql2xmdcapmask,
225 "Set the Minidump driver capture mask level. "
6e96fa7b 226 "Default is 0x1F - Can be set to 0x3, 0x7, 0xF, 0x1F, 0x7F.");
08de2844 227
3aadff35 228int ql2xmdenable = 1;
08de2844
GM		 229module_param(ql2xmdenable, int, S_IRUGO);
230MODULE_PARM_DESC(ql2xmdenable,
231 "Enable/disable MiniDump. "
3aadff35
GM		 232 "0 - MiniDump disabled. "
233 "1 (Default) - MiniDump enabled.");
08de2844 234
b0d6cabd
HM		 235int ql2xexlogins = 0;
236module_param(ql2xexlogins, uint, S_IRUGO|S_IWUSR);
237MODULE_PARM_DESC(ql2xexlogins,
238 "Number of extended Logins. "
239 "0 (Default)- Disabled.");
240
99e1b683
QT		 241int ql2xexchoffld = 1024;
242module_param(ql2xexchoffld, uint, 0644);
2f56a7f1 243MODULE_PARM_DESC(ql2xexchoffld,
99e1b683
QT		 244 "Number of target exchanges.");
245
246int ql2xiniexchg = 1024;
247module_param(ql2xiniexchg, uint, 0644);
248MODULE_PARM_DESC(ql2xiniexchg,
249 "Number of initiator exchanges.");
2f56a7f1 250
f198cafa
HM		 251int ql2xfwholdabts = 0;
252module_param(ql2xfwholdabts, int, S_IRUGO);
253MODULE_PARM_DESC(ql2xfwholdabts,
254 "Allow FW to hold status IOCB until ABTS rsp received. "
255 "0 (Default) Do not set fw option. "
256 "1 - Set fw option to hold ABTS.");
257
41dc529a
QT		 258int ql2xmvasynctoatio = 1;
259module_param(ql2xmvasynctoatio, int, S_IRUGO|S_IWUSR);
260MODULE_PARM_DESC(ql2xmvasynctoatio,
261 "Move PUREX, ABTS RX and RIDA IOCBs to ATIOQ"
262 "0 (Default). Do not move IOCBs"
263 "1 - Move IOCBs.");
264
e4e3a2ce
QT		 265int ql2xautodetectsfp = 1;
266module_param(ql2xautodetectsfp, int, 0444);
267MODULE_PARM_DESC(ql2xautodetectsfp,
268 "Detect SFP range and set appropriate distance.\n"
269 "1 (Default): Enable\n");
270
e7240af5
HM		 271int ql2xenablemsix = 1;
272module_param(ql2xenablemsix, int, 0444);
273MODULE_PARM_DESC(ql2xenablemsix,
274 "Set to enable MSI or MSI-X interrupt mechanism.\n"
275 " Default is 1, enable MSI-X interrupt mechanism.\n"
276 " 0 -- enable traditional pin-based mechanism.\n"
277 " 1 -- enable MSI-X interrupt mechanism.\n"
278 " 2 -- enable MSI interrupt mechanism.\n");
279
9ecf0b0d
QT		 280int qla2xuseresexchforels;
281module_param(qla2xuseresexchforels, int, 0444);
282MODULE_PARM_DESC(qla2xuseresexchforels,
283 "Reserve 1/2 of emergency exchanges for ELS.\n"
284 " 0 (default): disabled");
285
1da177e4 286/*
fa2a1ce5 287 * SCSI host template entry points
1da177e4
LT		 288 */
289static int qla2xxx_slave_configure(struct scsi_device * device);
f4f051eb 290static int qla2xxx_slave_alloc(struct scsi_device *);
1e99e33a
AV		 291static int qla2xxx_scan_finished(struct Scsi_Host *, unsigned long time);
292static void qla2xxx_scan_start(struct Scsi_Host *);
f4f051eb 293static void qla2xxx_slave_destroy(struct scsi_device *);
f281233d 294static int qla2xxx_queuecommand(struct Scsi_Host *h, struct scsi_cmnd *cmd);
1da177e4
LT		 295static int qla2xxx_eh_abort(struct scsi_cmnd *);
296static int qla2xxx_eh_device_reset(struct scsi_cmnd *);
523ec773 297static int qla2xxx_eh_target_reset(struct scsi_cmnd *);
1da177e4
LT		 298static int qla2xxx_eh_bus_reset(struct scsi_cmnd *);
299static int qla2xxx_eh_host_reset(struct scsi_cmnd *);
1da177e4 300
1a2fbf18 301static void qla2x00_clear_drv_active(struct qla_hw_data *);
3491255e 302static void qla2x00_free_device(scsi_qla_host_t *);
5601236b 303static int qla2xxx_map_queues(struct Scsi_Host *shost);
e84067d7 304static void qla2x00_destroy_deferred_work(struct qla_hw_data *);
ce7e4af7 305
45235022 306
a5326f86 307struct scsi_host_template qla2xxx_driver_template = {
1da177e4 308 .module = THIS_MODULE,
cb63067a 309 .name = QLA2XXX_DRIVER_NAME,
a5326f86 310 .queuecommand = qla2xxx_queuecommand,
fca29703 311
b6a05c82 312 .eh_timed_out = fc_eh_timed_out,
fca29703
AV		 313 .eh_abort_handler = qla2xxx_eh_abort,
314 .eh_device_reset_handler = qla2xxx_eh_device_reset,
523ec773 315 .eh_target_reset_handler = qla2xxx_eh_target_reset,
fca29703
AV		 316 .eh_bus_reset_handler = qla2xxx_eh_bus_reset,
317 .eh_host_reset_handler = qla2xxx_eh_host_reset,
318
319 .slave_configure = qla2xxx_slave_configure,
320
321 .slave_alloc = qla2xxx_slave_alloc,
322 .slave_destroy = qla2xxx_slave_destroy,
ed677086
AV		 323 .scan_finished = qla2xxx_scan_finished,
324 .scan_start = qla2xxx_scan_start,
db5ed4df 325 .change_queue_depth = scsi_change_queue_depth,
5601236b 326 .map_queues = qla2xxx_map_queues,
fca29703
AV		 327 .this_id = -1,
328 .cmd_per_lun = 3,
329 .use_clustering = ENABLE_CLUSTERING,
330 .sg_tablesize = SG_ALL,
331
332 .max_sectors = 0xFFFF,
afb046e2 333 .shost_attrs = qla2x00_host_attrs,
2d70c103
NB		 334
335 .supported_mode = MODE_INITIATOR,
c40ecc12 336 .track_queue_depth = 1,
fca29703
AV		 337};
338
1da177e4 339static struct scsi_transport_template *qla2xxx_transport_template = NULL;
2c3dfe3f 340struct scsi_transport_template *qla2xxx_transport_vport_template = NULL;
1da177e4 341
1da177e4
LT		 342/* TODO Convert to inlines
343 *
344 * Timer routines
345 */
1da177e4 346
2c3dfe3f 347__inline__ void
8e5f4ba0 348qla2x00_start_timer(scsi_qla_host_t *vha, unsigned long interval)
1da177e4 349{
8e5f4ba0 350 timer_setup(&vha->timer, qla2x00_timer, 0);
e315cd28 351 vha->timer.expires = jiffies + interval * HZ;
e315cd28
AC		 352 add_timer(&vha->timer);
353 vha->timer_active = 1;
1da177e4
LT		 354}
355
356static inline void
e315cd28 357qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval)
1da177e4 358{
a9083016 359 /* Currently used for 82XX only. */
7c3df132
SK		 360 if (vha->device_flags & DFLG_DEV_FAILED) {
361 ql_dbg(ql_dbg_timer, vha, 0x600d,
362 "Device in a failed state, returning.\n");
a9083016 363 return;
7c3df132 364 }
a9083016 365
e315cd28 366 mod_timer(&vha->timer, jiffies + interval * HZ);
1da177e4
LT		 367}
368
a824ebb3 369static __inline__ void
e315cd28 370qla2x00_stop_timer(scsi_qla_host_t *vha)
1da177e4 371{
e315cd28
AC		 372 del_timer_sync(&vha->timer);
373 vha->timer_active = 0;
1da177e4
LT		 374}
375
1da177e4
LT		 376static int qla2x00_do_dpc(void *data);
377
378static void qla2x00_rst_aen(scsi_qla_host_t *);
379
73208dfd
AC		 380static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t,
381 struct req_que **, struct rsp_que **);
e30d1756 382static void qla2x00_free_fw_dump(struct qla_hw_data *);
e315cd28 383static void qla2x00_mem_free(struct qla_hw_data *);
d7459527
MH		 384int qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd,
385 struct qla_qpair *qpair);
1da177e4 386
1da177e4 387/* -------------------------------------------------------------------------- */
8abfa9e2
QT		 388static void qla_init_base_qpair(struct scsi_qla_host *vha, struct req_que *req,
389 struct rsp_que *rsp)
390{
391 struct qla_hw_data *ha = vha->hw;
392 rsp->qpair = ha->base_qpair;
393 rsp->req = req;
394 ha->base_qpair->req = req;
395 ha->base_qpair->rsp = rsp;
396 ha->base_qpair->vha = vha;
397 ha->base_qpair->qp_lock_ptr = &ha->hardware_lock;
398 ha->base_qpair->use_shadow_reg = IS_SHADOW_REG_CAPABLE(ha) ? 1 : 0;
399 ha->base_qpair->msix = &ha->msix_entries[QLA_MSIX_RSP_Q];
400 INIT_LIST_HEAD(&ha->base_qpair->hints_list);
401 ha->base_qpair->enable_class_2 = ql2xenableclass2;
402 /* init qpair to this cpu. Will adjust at run time. */
86531887 403 qla_cpu_update(rsp->qpair, raw_smp_processor_id());
8abfa9e2
QT		 404 ha->base_qpair->pdev = ha->pdev;
405
406 if (IS_QLA27XX(ha) || IS_QLA83XX(ha))
407 ha->base_qpair->reqq_start_iocbs = qla_83xx_start_iocbs;
408}
409
9a347ff4
CD		 410static int qla2x00_alloc_queues(struct qla_hw_data *ha, struct req_que *req,
411 struct rsp_que *rsp)
73208dfd 412{
7c3df132 413 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
6396bb22 414 ha->req_q_map = kcalloc(ha->max_req_queues, sizeof(struct req_que *),
73208dfd
AC		 415 GFP_KERNEL);
416 if (!ha->req_q_map) {
7c3df132
SK		 417 ql_log(ql_log_fatal, vha, 0x003b,
418 "Unable to allocate memory for request queue ptrs.\n");
73208dfd
AC		 419 goto fail_req_map;
420 }
421
6396bb22 422 ha->rsp_q_map = kcalloc(ha->max_rsp_queues, sizeof(struct rsp_que *),
73208dfd
AC		 423 GFP_KERNEL);
424 if (!ha->rsp_q_map) {
7c3df132
SK		 425 ql_log(ql_log_fatal, vha, 0x003c,
426 "Unable to allocate memory for response queue ptrs.\n");
73208dfd
AC		 427 goto fail_rsp_map;
428 }
d7459527 429
e326d22a
QT		 430 ha->base_qpair = kzalloc(sizeof(struct qla_qpair), GFP_KERNEL);
431 if (ha->base_qpair == NULL) {
432 ql_log(ql_log_warn, vha, 0x00e0,
433 "Failed to allocate base queue pair memory.\n");
434 goto fail_base_qpair;
435 }
436
8abfa9e2 437 qla_init_base_qpair(vha, req, rsp);
e326d22a 438
c38d1baf 439 if ((ql2xmqsupport || ql2xnvmeenable) && ha->max_qpairs) {
d7459527
MH		 440 ha->queue_pair_map = kcalloc(ha->max_qpairs, sizeof(struct qla_qpair *),
441 GFP_KERNEL);
442 if (!ha->queue_pair_map) {
443 ql_log(ql_log_fatal, vha, 0x0180,
444 "Unable to allocate memory for queue pair ptrs.\n");
445 goto fail_qpair_map;
446 }
d7459527
MH		 447 }
448
9a347ff4
CD		 449 /*
450 * Make sure we record at least the request and response queue zero in
451 * case we need to free them if part of the probe fails.
452 */
453 ha->rsp_q_map[0] = rsp;
454 ha->req_q_map[0] = req;
73208dfd
AC		 455 set_bit(0, ha->rsp_qid_map);
456 set_bit(0, ha->req_qid_map);
6a2cf8d3 457 return 0;
73208dfd 458
d7459527 459fail_qpair_map:
82de802a
QT		 460 kfree(ha->base_qpair);
461 ha->base_qpair = NULL;
462fail_base_qpair:
d7459527
MH		 463 kfree(ha->rsp_q_map);
464 ha->rsp_q_map = NULL;
73208dfd
AC		 465fail_rsp_map:
466 kfree(ha->req_q_map);
467 ha->req_q_map = NULL;
468fail_req_map:
469 return -ENOMEM;
470}
471
2afa19a9 472static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req)
73208dfd 473{
8ae6d9c7
GM		 474 if (IS_QLAFX00(ha)) {
475 if (req && req->ring_fx00)
476 dma_free_coherent(&ha->pdev->dev,
477 (req->length_fx00 + 1) * sizeof(request_t),
478 req->ring_fx00, req->dma_fx00);
479 } else if (req && req->ring)
73208dfd
AC		 480 dma_free_coherent(&ha->pdev->dev,
481 (req->length + 1) * sizeof(request_t),
482 req->ring, req->dma);
483
6d634067 484 if (req)
8d93f550 485 kfree(req->outstanding_cmds);
6d634067
BK		 486
487 kfree(req);
73208dfd
AC		 488}
489
2afa19a9
AC		 490static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp)
491{
8ae6d9c7 492 if (IS_QLAFX00(ha)) {
3f6c9be2 493 if (rsp && rsp->ring_fx00)
8ae6d9c7
GM		 494 dma_free_coherent(&ha->pdev->dev,
495 (rsp->length_fx00 + 1) * sizeof(request_t),
496 rsp->ring_fx00, rsp->dma_fx00);
497 } else if (rsp && rsp->ring) {
2afa19a9
AC		 498 dma_free_coherent(&ha->pdev->dev,
499 (rsp->length + 1) * sizeof(response_t),
500 rsp->ring, rsp->dma);
8ae6d9c7 501 }
6d634067 502 kfree(rsp);
2afa19a9
AC		 503}
504
73208dfd
AC		 505static void qla2x00_free_queues(struct qla_hw_data *ha)
506{
507 struct req_que *req;
508 struct rsp_que *rsp;
509 int cnt;
093df737 510 unsigned long flags;
73208dfd 511
82de802a
QT		 512 if (ha->queue_pair_map) {
513 kfree(ha->queue_pair_map);
514 ha->queue_pair_map = NULL;
515 }
516 if (ha->base_qpair) {
517 kfree(ha->base_qpair);
518 ha->base_qpair = NULL;
519 }
520
093df737 521 spin_lock_irqsave(&ha->hardware_lock, flags);
2afa19a9 522 for (cnt = 0; cnt < ha->max_req_queues; cnt++) {
cb43285f
QT		 523 if (!test_bit(cnt, ha->req_qid_map))
524 continue;
525
73208dfd 526 req = ha->req_q_map[cnt];
093df737
QT		 527 clear_bit(cnt, ha->req_qid_map);
528 ha->req_q_map[cnt] = NULL;
529
530 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2afa19a9 531 qla2x00_free_req_que(ha, req);
093df737 532 spin_lock_irqsave(&ha->hardware_lock, flags);
73208dfd 533 }
093df737
QT		 534 spin_unlock_irqrestore(&ha->hardware_lock, flags);
535
73208dfd
AC		 536 kfree(ha->req_q_map);
537 ha->req_q_map = NULL;
2afa19a9 538
093df737
QT		 539
540 spin_lock_irqsave(&ha->hardware_lock, flags);
2afa19a9 541 for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) {
cb43285f
QT		 542 if (!test_bit(cnt, ha->rsp_qid_map))
543 continue;
544
2afa19a9 545 rsp = ha->rsp_q_map[cnt];
c3c42394 546 clear_bit(cnt, ha->rsp_qid_map);
093df737
QT		 547 ha->rsp_q_map[cnt] = NULL;
548 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2afa19a9 549 qla2x00_free_rsp_que(ha, rsp);
093df737 550 spin_lock_irqsave(&ha->hardware_lock, flags);
2afa19a9 551 }
093df737
QT		 552 spin_unlock_irqrestore(&ha->hardware_lock, flags);
553
2afa19a9
AC		 554 kfree(ha->rsp_q_map);
555 ha->rsp_q_map = NULL;
73208dfd
AC		 556}
557
1da177e4 558static char *
e315cd28 559qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str)
1da177e4 560{
e315cd28 561 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 562 static char *pci_bus_modes[] = {
563 "33", "66", "100", "133",
564 };
565 uint16_t pci_bus;
566
567 strcpy(str, "PCI");
568 pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9;
569 if (pci_bus) {
570 strcat(str, "-X (");
571 strcat(str, pci_bus_modes[pci_bus]);
572 } else {
573 pci_bus = (ha->pci_attr & BIT_8) >> 8;
574 strcat(str, " (");
575 strcat(str, pci_bus_modes[pci_bus]);
576 }
577 strcat(str, " MHz)");
578
579 return (str);
580}
581
fca29703 582static char *
e315cd28 583qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str)
fca29703
AV		 584{
585 static char *pci_bus_modes[] = { "33", "66", "100", "133", };
e315cd28 586 struct qla_hw_data *ha = vha->hw;
fca29703 587 uint32_t pci_bus;
fca29703 588
62a276f8 589 if (pci_is_pcie(ha->pdev)) {
fca29703 590 char lwstr[6];
62a276f8 591 uint32_t lstat, lspeed, lwidth;
fca29703 592
62a276f8
BH		 593 pcie_capability_read_dword(ha->pdev, PCI_EXP_LNKCAP, &lstat);
594 lspeed = lstat & PCI_EXP_LNKCAP_SLS;
595 lwidth = (lstat & PCI_EXP_LNKCAP_MLW) >> 4;
fca29703
AV		 596
597 strcpy(str, "PCIe (");
49300af7
SK		 598 switch (lspeed) {
599 case 1:
c87a0d8c 600 strcat(str, "2.5GT/s ");
49300af7
SK		 601 break;
602 case 2:
c87a0d8c 603 strcat(str, "5.0GT/s ");
49300af7
SK		 604 break;
605 case 3:
606 strcat(str, "8.0GT/s ");
607 break;
608 default:
fca29703 609 strcat(str, "<unknown> ");
49300af7
SK		 610 break;
611 }
fca29703
AV		 612 snprintf(lwstr, sizeof(lwstr), "x%d)", lwidth);
613 strcat(str, lwstr);
614
615 return str;
616 }
617
618 strcpy(str, "PCI");
619 pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8;
620 if (pci_bus == 0 || pci_bus == 8) {
621 strcat(str, " (");
622 strcat(str, pci_bus_modes[pci_bus >> 3]);
623 } else {
624 strcat(str, "-X ");
625 if (pci_bus & BIT_2)
626 strcat(str, "Mode 2");
627 else
628 strcat(str, "Mode 1");
629 strcat(str, " (");
630 strcat(str, pci_bus_modes[pci_bus & ~BIT_2]);
631 }
632 strcat(str, " MHz)");
633
634 return str;
635}
636
e5f82ab8 637static char *
df57caba 638qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
1da177e4
LT		 639{
640 char un_str[10];
e315cd28 641 struct qla_hw_data *ha = vha->hw;
fa2a1ce5 642
df57caba
HM		 643 snprintf(str, size, "%d.%02d.%02d ", ha->fw_major_version,
644 ha->fw_minor_version, ha->fw_subminor_version);
1da177e4
LT		 645
646 if (ha->fw_attributes & BIT_9) {
647 strcat(str, "FLX");
648 return (str);
649 }
650
651 switch (ha->fw_attributes & 0xFF) {
652 case 0x7:
653 strcat(str, "EF");
654 break;
655 case 0x17:
656 strcat(str, "TP");
657 break;
658 case 0x37:
659 strcat(str, "IP");
660 break;
661 case 0x77:
662 strcat(str, "VI");
663 break;
664 default:
665 sprintf(un_str, "(%x)", ha->fw_attributes);
666 strcat(str, un_str);
667 break;
668 }
669 if (ha->fw_attributes & 0x100)
670 strcat(str, "X");
671
672 return (str);
673}
674
e5f82ab8 675static char *
df57caba 676qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
fca29703 677{
e315cd28 678 struct qla_hw_data *ha = vha->hw;
f0883ac6 679
df57caba 680 snprintf(str, size, "%d.%02d.%02d (%x)", ha->fw_major_version,
3a03eb79 681 ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes);
fca29703 682 return str;
fca29703
AV		 683}
684
9ba56b95 685void
25ff6af1 686qla2x00_sp_free_dma(void *ptr)
fca29703 687{
25ff6af1
JC		 688 srb_t *sp = ptr;
689 struct qla_hw_data *ha = sp->vha->hw;
9ba56b95 690 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
9ba56b95 691 void *ctx = GET_CMD_CTX_SP(sp);
fca29703 692
9ba56b95
GM		 693 if (sp->flags & SRB_DMA_VALID) {
694 scsi_dma_unmap(cmd);
695 sp->flags &= ~SRB_DMA_VALID;
7c3df132 696 }
fca29703 697
9ba56b95
GM		 698 if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
699 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
700 scsi_prot_sg_count(cmd), cmd->sc_data_direction);
701 sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
702 }
703
d5ff0eed
JC		 704 if (!ctx)
705 goto end;
706
9ba56b95
GM		 707 if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
708 /* List assured to be having elements */
d5ff0eed 709 qla2x00_clean_dsd_pool(ha, ctx);
9ba56b95
GM		 710 sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
711 }
712
713 if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
d5ff0eed
JC		 714 struct crc_context *ctx0 = ctx;
715
716 dma_pool_free(ha->dl_dma_pool, ctx0, ctx0->crc_ctx_dma);
9ba56b95
GM		 717 sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
718 }
719
720 if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
d5ff0eed 721 struct ct6_dsd *ctx1 = ctx;
fca29703 722
9ba56b95 723 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd,
d5ff0eed 724 ctx1->fcp_cmnd_dma);
9ba56b95
GM		 725 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list);
726 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt;
727 ha->gbl_dsd_avail += ctx1->dsd_use_cnt;
728 mempool_free(ctx1, ha->ctx_mempool);
9ba56b95
GM		 729 }
730
d5ff0eed 731end:
6fcd98fd 732 if (sp->type != SRB_NVME_CMD && sp->type != SRB_NVME_LS) {
7401bc18
DG		 733 CMD_SP(cmd) = NULL;
734 qla2x00_rel_sp(sp);
735 }
9ba56b95
GM		 736}
737
d7459527 738void
25ff6af1 739qla2x00_sp_compl(void *ptr, int res)
9ba56b95 740{
25ff6af1 741 srb_t *sp = ptr;
9ba56b95
GM		 742 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
743
744 cmd->result = res;
745
746 if (atomic_read(&sp->ref_count) == 0) {
25ff6af1 747 ql_dbg(ql_dbg_io, sp->vha, 0x3015,
9ba56b95
GM		 748 "SP reference-count to ZERO -- sp=%p cmd=%p.\n",
749 sp, GET_CMD_SP(sp));
750 if (ql2xextended_error_logging & ql_dbg_io)
8fbdac8c 751 WARN_ON(atomic_read(&sp->ref_count) == 0);
9ba56b95
GM		 752 return;
753 }
754 if (!atomic_dec_and_test(&sp->ref_count))
755 return;
756
f3caa990 757 sp->free(sp);
9ba56b95 758 cmd->scsi_done(cmd);
fca29703
AV		 759}
760
d7459527 761void
25ff6af1 762qla2xxx_qpair_sp_free_dma(void *ptr)
d7459527
MH		 763{
764 srb_t *sp = (srb_t *)ptr;
765 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
766 struct qla_hw_data *ha = sp->fcport->vha->hw;
767 void *ctx = GET_CMD_CTX_SP(sp);
768
769 if (sp->flags & SRB_DMA_VALID) {
770 scsi_dma_unmap(cmd);
771 sp->flags &= ~SRB_DMA_VALID;
772 }
773
774 if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
775 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
776 scsi_prot_sg_count(cmd), cmd->sc_data_direction);
777 sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
778 }
779
d5ff0eed
JC		 780 if (!ctx)
781 goto end;
782
d7459527
MH		 783 if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
784 /* List assured to be having elements */
d5ff0eed 785 qla2x00_clean_dsd_pool(ha, ctx);
d7459527
MH		 786 sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
787 }
788
789 if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
d5ff0eed
JC		 790 struct crc_context *ctx0 = ctx;
791
792 dma_pool_free(ha->dl_dma_pool, ctx, ctx0->crc_ctx_dma);
d7459527
MH		 793 sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
794 }
795
796 if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
d5ff0eed 797 struct ct6_dsd *ctx1 = ctx;
d7459527
MH		 798 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd,
799 ctx1->fcp_cmnd_dma);
800 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list);
801 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt;
802 ha->gbl_dsd_avail += ctx1->dsd_use_cnt;
803 mempool_free(ctx1, ha->ctx_mempool);
804 }
d5ff0eed 805end:
d7459527
MH		 806 CMD_SP(cmd) = NULL;
807 qla2xxx_rel_qpair_sp(sp->qpair, sp);
808}
809
810void
25ff6af1 811qla2xxx_qpair_sp_compl(void *ptr, int res)
d7459527 812{
25ff6af1 813 srb_t *sp = ptr;
d7459527
MH		 814 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
815
816 cmd->result = res;
817
818 if (atomic_read(&sp->ref_count) == 0) {
819 ql_dbg(ql_dbg_io, sp->fcport->vha, 0x3079,
820 "SP reference-count to ZERO -- sp=%p cmd=%p.\n",
821 sp, GET_CMD_SP(sp));
822 if (ql2xextended_error_logging & ql_dbg_io)
823 WARN_ON(atomic_read(&sp->ref_count) == 0);
824 return;
825 }
826 if (!atomic_dec_and_test(&sp->ref_count))
827 return;
828
f3caa990 829 sp->free(sp);
d7459527
MH		 830 cmd->scsi_done(cmd);
831}
832
8ae6d9c7
GM		 833/* If we are SP1 here, we need to still take and release the host_lock as SP1
834 * does not have the changes necessary to avoid taking host->host_lock.
835 */
1da177e4 836static int
f5e3e40b 837qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
fca29703 838{
134ae078 839 scsi_qla_host_t *vha = shost_priv(host);
fca29703 840 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
19a7b4ae 841 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
e315cd28
AC		 842 struct qla_hw_data *ha = vha->hw;
843 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
fca29703
AV		 844 srb_t *sp;
845 int rval;
5601236b
MH		 846 struct qla_qpair *qpair = NULL;
847 uint32_t tag;
848 uint16_t hwq;
fca29703 849
04dfaa53
MFO		 850 if (unlikely(test_bit(UNLOADING, &base_vha->dpc_flags))) {
851 cmd->result = DID_NO_CONNECT << 16;
852 goto qc24_fail_command;
853 }
854
5601236b
MH		 855 if (ha->mqenable) {
856 if (shost_use_blk_mq(vha->host)) {
857 tag = blk_mq_unique_tag(cmd->request);
858 hwq = blk_mq_unique_tag_to_hwq(tag);
859 qpair = ha->queue_pair_map[hwq];
860 } else if (vha->vp_idx && vha->qpair) {
861 qpair = vha->qpair;
862 }
863
864 if (qpair)
865 return qla2xxx_mqueuecommand(host, cmd, qpair);
d7459527
MH		 866 }
867
85880801 868 if (ha->flags.eeh_busy) {
7c3df132 869 if (ha->flags.pci_channel_io_perm_failure) {
5f28d2d7 870 ql_dbg(ql_dbg_aer, vha, 0x9010,
7c3df132
SK		 871 "PCI Channel IO permanent failure, exiting "
872 "cmd=%p.\n", cmd);
b9b12f73 873 cmd->result = DID_NO_CONNECT << 16;
7c3df132 874 } else {
5f28d2d7 875 ql_dbg(ql_dbg_aer, vha, 0x9011,
7c3df132 876 "EEH_Busy, Requeuing the cmd=%p.\n", cmd);
85880801 877 cmd->result = DID_REQUEUE << 16;
7c3df132 878 }
14e660e6
SJ		 879 goto qc24_fail_command;
880 }
881
19a7b4ae
JSEC		 882 rval = fc_remote_port_chkready(rport);
883 if (rval) {
884 cmd->result = rval;
5f28d2d7 885 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3003,
7c3df132
SK		 886 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
887 cmd, rval);
fca29703
AV		 888 goto qc24_fail_command;
889 }
890
bad75002
AE		 891 if (!vha->flags.difdix_supported &&
892 scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) {
7c3df132
SK		 893 ql_dbg(ql_dbg_io, vha, 0x3004,
894 "DIF Cap not reg, fail DIF capable cmd's:%p.\n",
895 cmd);
bad75002
AE		 896 cmd->result = DID_NO_CONNECT << 16;
897 goto qc24_fail_command;
898 }
aa651be8
CD		 899
900 if (!fcport) {
901 cmd->result = DID_NO_CONNECT << 16;
902 goto qc24_fail_command;
903 }
904
fca29703
AV		 905 if (atomic_read(&fcport->state) != FCS_ONLINE) {
906 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
38170fa8 907 atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
7c3df132
SK		 908 ql_dbg(ql_dbg_io, vha, 0x3005,
909 "Returning DNC, fcport_state=%d loop_state=%d.\n",
910 atomic_read(&fcport->state),
911 atomic_read(&base_vha->loop_state));
fca29703
AV		 912 cmd->result = DID_NO_CONNECT << 16;
913 goto qc24_fail_command;
914 }
7b594131 915 goto qc24_target_busy;
fca29703
AV		 916 }
917
e05fe292
CD		 918 /*
919 * Return target busy if we've received a non-zero retry_delay_timer
920 * in a FCP_RSP.
921 */
975f7d46
BP		 922 if (fcport->retry_delay_timestamp == 0) {
923 /* retry delay not set */
924 } else if (time_after(jiffies, fcport->retry_delay_timestamp))
e05fe292
CD		 925 fcport->retry_delay_timestamp = 0;
926 else
927 goto qc24_target_busy;
928
b00ee7d7 929 sp = qla2x00_get_sp(vha, fcport, GFP_ATOMIC);
50280c01 930 if (!sp)
f5e3e40b 931 goto qc24_host_busy;
fca29703 932
9ba56b95
GM		 933 sp->u.scmd.cmd = cmd;
934 sp->type = SRB_SCSI_CMD;
935 atomic_set(&sp->ref_count, 1);
936 CMD_SP(cmd) = (void *)sp;
937 sp->free = qla2x00_sp_free_dma;
938 sp->done = qla2x00_sp_compl;
939
e315cd28 940 rval = ha->isp_ops->start_scsi(sp);
7c3df132 941 if (rval != QLA_SUCCESS) {
53016ed3 942 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3013,
7c3df132 943 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
fca29703 944 goto qc24_host_busy_free_sp;
7c3df132 945 }
fca29703 946
fca29703
AV		 947 return 0;
948
949qc24_host_busy_free_sp:
f3caa990 950 sp->free(sp);
fca29703 951
f5e3e40b 952qc24_host_busy:
fca29703
AV		 953 return SCSI_MLQUEUE_HOST_BUSY;
954
7b594131
MC		 955qc24_target_busy:
956 return SCSI_MLQUEUE_TARGET_BUSY;
957
fca29703 958qc24_fail_command:
f5e3e40b 959 cmd->scsi_done(cmd);
fca29703
AV		 960
961 return 0;
962}
963
d7459527
MH		 964/* For MQ supported I/O */
965int
966qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd,
967 struct qla_qpair *qpair)
968{
969 scsi_qla_host_t *vha = shost_priv(host);
970 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
971 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
972 struct qla_hw_data *ha = vha->hw;
973 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
974 srb_t *sp;
975 int rval;
976
977 rval = fc_remote_port_chkready(rport);
978 if (rval) {
979 cmd->result = rval;
980 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3076,
981 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
982 cmd, rval);
983 goto qc24_fail_command;
984 }
985
986 if (!fcport) {
987 cmd->result = DID_NO_CONNECT << 16;
988 goto qc24_fail_command;
989 }
990
991 if (atomic_read(&fcport->state) != FCS_ONLINE) {
992 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
993 atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
994 ql_dbg(ql_dbg_io, vha, 0x3077,
995 "Returning DNC, fcport_state=%d loop_state=%d.\n",
996 atomic_read(&fcport->state),
997 atomic_read(&base_vha->loop_state));
998 cmd->result = DID_NO_CONNECT << 16;
999 goto qc24_fail_command;
1000 }
1001 goto qc24_target_busy;
1002 }
1003
1004 /*
1005 * Return target busy if we've received a non-zero retry_delay_timer
1006 * in a FCP_RSP.
1007 */
1008 if (fcport->retry_delay_timestamp == 0) {
1009 /* retry delay not set */
1010 } else if (time_after(jiffies, fcport->retry_delay_timestamp))
1011 fcport->retry_delay_timestamp = 0;
1012 else
1013 goto qc24_target_busy;
1014
1015 sp = qla2xxx_get_qpair_sp(qpair, fcport, GFP_ATOMIC);
1016 if (!sp)
1017 goto qc24_host_busy;
1018
1019 sp->u.scmd.cmd = cmd;
1020 sp->type = SRB_SCSI_CMD;
1021 atomic_set(&sp->ref_count, 1);
1022 CMD_SP(cmd) = (void *)sp;
1023 sp->free = qla2xxx_qpair_sp_free_dma;
1024 sp->done = qla2xxx_qpair_sp_compl;
1025 sp->qpair = qpair;
1026
1027 rval = ha->isp_ops->start_scsi_mq(sp);
1028 if (rval != QLA_SUCCESS) {
1029 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3078,
1030 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
1031 if (rval == QLA_INTERFACE_ERROR)
1032 goto qc24_fail_command;
1033 goto qc24_host_busy_free_sp;
1034 }
1035
1036 return 0;
1037
1038qc24_host_busy_free_sp:
f3caa990 1039 sp->free(sp);
d7459527
MH		 1040
1041qc24_host_busy:
1042 return SCSI_MLQUEUE_HOST_BUSY;
1043
1044qc24_target_busy:
1045 return SCSI_MLQUEUE_TARGET_BUSY;
1046
1047qc24_fail_command:
1048 cmd->scsi_done(cmd);
1049
1050 return 0;
1051}
1052
1da177e4
LT		 1053/*
1054 * qla2x00_eh_wait_on_command
1055 * Waits for the command to be returned by the Firmware for some
1056 * max time.
1057 *
1058 * Input:
1da177e4 1059 * cmd = Scsi Command to wait on.
1da177e4
LT		 1060 *
1061 * Return:
1062 * Not Found : 0
1063 * Found : 1
1064 */
1065static int
e315cd28 1066qla2x00_eh_wait_on_command(struct scsi_cmnd *cmd)
1da177e4 1067{
fe74c71f 1068#define ABORT_POLLING_PERIOD 1000
478c3b03 1069#define ABORT_WAIT_ITER ((2 * 1000) / (ABORT_POLLING_PERIOD))
f4f051eb 1070 unsigned long wait_iter = ABORT_WAIT_ITER;
85880801
AV		 1071 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1072 struct qla_hw_data *ha = vha->hw;
f4f051eb 1073 int ret = QLA_SUCCESS;
1da177e4 1074
85880801 1075 if (unlikely(pci_channel_offline(ha->pdev)) || ha->flags.eeh_busy) {
7c3df132
SK		 1076 ql_dbg(ql_dbg_taskm, vha, 0x8005,
1077 "Return:eh_wait.\n");
85880801
AV		 1078 return ret;
1079 }
1080
d970432c 1081 while (CMD_SP(cmd) && wait_iter--) {
fe74c71f 1082 msleep(ABORT_POLLING_PERIOD);
f4f051eb 1083 }
1084 if (CMD_SP(cmd))
1085 ret = QLA_FUNCTION_FAILED;
1da177e4 1086
f4f051eb 1087 return ret;
1da177e4
LT		 1088}
1089
1090/*
1091 * qla2x00_wait_for_hba_online
fa2a1ce5 1092 * Wait till the HBA is online after going through
1da177e4
LT		 1093 * <= MAX_RETRIES_OF_ISP_ABORT or
1094 * finally HBA is disabled ie marked offline
1095 *
1096 * Input:
1097 * ha - pointer to host adapter structure
fa2a1ce5
AV		 1098 *
1099 * Note:
1da177e4
LT		 1100 * Does context switching-Release SPIN_LOCK
1101 * (if any) before calling this routine.
1102 *
1103 * Return:
1104 * Success (Adapter is online) : 0
1105 * Failed (Adapter is offline/disabled) : 1
1106 */
854165f4 1107int
e315cd28 1108qla2x00_wait_for_hba_online(scsi_qla_host_t *vha)
1da177e4 1109{
fca29703
AV		 1110 int return_status;
1111 unsigned long wait_online;
e315cd28
AC		 1112 struct qla_hw_data *ha = vha->hw;
1113 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4 1114
fa2a1ce5 1115 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ);
e315cd28
AC		 1116 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
1117 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
1118 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
1119 ha->dpc_active) && time_before(jiffies, wait_online)) {
1da177e4
LT		 1120
1121 msleep(1000);
1122 }
e315cd28 1123 if (base_vha->flags.online)
fa2a1ce5 1124 return_status = QLA_SUCCESS;
1da177e4
LT		 1125 else
1126 return_status = QLA_FUNCTION_FAILED;
1127
1da177e4
LT		 1128 return (return_status);
1129}
1130
726b8548
QT		 1131static inline int test_fcport_count(scsi_qla_host_t *vha)
1132{
1133 struct qla_hw_data *ha = vha->hw;
1134 unsigned long flags;
1135 int res;
1136
1137 spin_lock_irqsave(&ha->tgt.sess_lock, flags);
83548fe2
QT		 1138 ql_dbg(ql_dbg_init, vha, 0x00ec,
1139 "tgt %p, fcport_count=%d\n",
1140 vha, vha->fcport_count);
726b8548
QT		 1141 res = (vha->fcport_count == 0);
1142 spin_unlock_irqrestore(&ha->tgt.sess_lock, flags);
1143
1144 return res;
1145}
1146
1147/*
1148 * qla2x00_wait_for_sess_deletion can only be called from remove_one.
1149 * it has dependency on UNLOADING flag to stop device discovery
1150 */
efa93f48 1151void
726b8548
QT		 1152qla2x00_wait_for_sess_deletion(scsi_qla_host_t *vha)
1153{
1154 qla2x00_mark_all_devices_lost(vha, 0);
1155
b85e0957 1156 wait_event_timeout(vha->fcport_waitQ, test_fcport_count(vha), 10*HZ);
726b8548
QT		 1157}
1158
86fbee86 1159/*
638a1a01
SC		 1160 * qla2x00_wait_for_hba_ready
1161 * Wait till the HBA is ready before doing driver unload
86fbee86
LC		 1162 *
1163 * Input:
1164 * ha - pointer to host adapter structure
1165 *
1166 * Note:
1167 * Does context switching-Release SPIN_LOCK
1168 * (if any) before calling this routine.
1169 *
86fbee86 1170 */
638a1a01
SC		 1171static void
1172qla2x00_wait_for_hba_ready(scsi_qla_host_t *vha)
86fbee86 1173{
86fbee86 1174 struct qla_hw_data *ha = vha->hw;
783e0dc4 1175 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
86fbee86 1176
1d483901
DC		 1177 while ((qla2x00_reset_active(vha) || ha->dpc_active ||
1178 ha->flags.mbox_busy) ||
1179 test_bit(FX00_RESET_RECOVERY, &vha->dpc_flags) ||
1180 test_bit(FX00_TARGET_SCAN, &vha->dpc_flags)) {
1181 if (test_bit(UNLOADING, &base_vha->dpc_flags))
1182 break;
86fbee86 1183 msleep(1000);
783e0dc4 1184 }
86fbee86
LC		 1185}
1186
2533cf67
LC		 1187int
1188qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha)
1189{
1190 int return_status;
1191 unsigned long wait_reset;
1192 struct qla_hw_data *ha = vha->hw;
1193 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1194
1195 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ);
1196 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
1197 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
1198 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
1199 ha->dpc_active) && time_before(jiffies, wait_reset)) {
1200
1201 msleep(1000);
1202
1203 if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) &&
1204 ha->flags.chip_reset_done)
1205 break;
1206 }
1207 if (ha->flags.chip_reset_done)
1208 return_status = QLA_SUCCESS;
1209 else
1210 return_status = QLA_FUNCTION_FAILED;
1211
1212 return return_status;
1213}
1214
083a469d
GM		 1215static void
1216sp_get(struct srb *sp)
1217{
1218 atomic_inc(&sp->ref_count);
1219}
1220
a465537a
SC		 1221#define ISP_REG_DISCONNECT 0xffffffffU
1222/**************************************************************************
1223* qla2x00_isp_reg_stat
1224*
1225* Description:
1226* Read the host status register of ISP before aborting the command.
1227*
1228* Input:
1229* ha = pointer to host adapter structure.
1230*
1231*
1232* Returns:
1233* Either true or false.
1234*
1235* Note: Return true if there is register disconnect.
1236**************************************************************************/
1237static inline
1238uint32_t qla2x00_isp_reg_stat(struct qla_hw_data *ha)
1239{
1240 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
bf6061b1 1241 struct device_reg_82xx __iomem *reg82 = &ha->iobase->isp82;
a465537a 1242
bf6061b1
SC		 1243 if (IS_P3P_TYPE(ha))
1244 return ((RD_REG_DWORD(&reg82->host_int)) == ISP_REG_DISCONNECT);
1245 else
1246 return ((RD_REG_DWORD(&reg->host_status)) ==
1247 ISP_REG_DISCONNECT);
a465537a
SC		 1248}
1249
1da177e4
LT		 1250/**************************************************************************
1251* qla2xxx_eh_abort
1252*
1253* Description:
1254* The abort function will abort the specified command.
1255*
1256* Input:
1257* cmd = Linux SCSI command packet to be aborted.
1258*
1259* Returns:
1260* Either SUCCESS or FAILED.
1261*
1262* Note:
2ea00202 1263* Only return FAILED if command not returned by firmware.
1da177e4 1264**************************************************************************/
e5f82ab8 1265static int
1da177e4
LT		 1266qla2xxx_eh_abort(struct scsi_cmnd *cmd)
1267{
e315cd28 1268 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
f4f051eb 1269 srb_t *sp;
4e98d3b8 1270 int ret;
9cb78c16
HR		 1271 unsigned int id;
1272 uint64_t lun;
18e144d3 1273 unsigned long flags;
f934c9d0 1274 int rval, wait = 0;
e315cd28 1275 struct qla_hw_data *ha = vha->hw;
1da177e4 1276
a465537a
SC		 1277 if (qla2x00_isp_reg_stat(ha)) {
1278 ql_log(ql_log_info, vha, 0x8042,
1279 "PCI/Register disconnect, exiting.\n");
1280 return FAILED;
1281 }
f4f051eb 1282 if (!CMD_SP(cmd))
2ea00202 1283 return SUCCESS;
1da177e4 1284
4e98d3b8
AV		 1285 ret = fc_block_scsi_eh(cmd);
1286 if (ret != 0)
1287 return ret;
1288 ret = SUCCESS;
1289
f4f051eb 1290 id = cmd->device->id;
1291 lun = cmd->device->lun;
1da177e4 1292
e315cd28 1293 spin_lock_irqsave(&ha->hardware_lock, flags);
170babc3
MC		 1294 sp = (srb_t *) CMD_SP(cmd);
1295 if (!sp) {
1296 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1297 return SUCCESS;
1298 }
1da177e4 1299
7c3df132 1300 ql_dbg(ql_dbg_taskm, vha, 0x8002,
c7bc4cae
CD		 1301 "Aborting from RISC nexus=%ld:%d:%llu sp=%p cmd=%p handle=%x\n",
1302 vha->host_no, id, lun, sp, cmd, sp->handle);
17d98630 1303
170babc3
MC		 1304 /* Get a reference to the sp and drop the lock.*/
1305 sp_get(sp);
083a469d 1306
e315cd28 1307 spin_unlock_irqrestore(&ha->hardware_lock, flags);
f934c9d0
CD		 1308 rval = ha->isp_ops->abort_command(sp);
1309 if (rval) {
96219424 1310 if (rval == QLA_FUNCTION_PARAMETER_ERROR)
f934c9d0 1311 ret = SUCCESS;
96219424 1312 else
f934c9d0
CD		 1313 ret = FAILED;
1314
7c3df132 1315 ql_dbg(ql_dbg_taskm, vha, 0x8003,
f934c9d0 1316 "Abort command mbx failed cmd=%p, rval=%x.\n", cmd, rval);
170babc3 1317 } else {
7c3df132 1318 ql_dbg(ql_dbg_taskm, vha, 0x8004,
cfb0919c 1319 "Abort command mbx success cmd=%p.\n", cmd);
170babc3
MC		 1320 wait = 1;
1321 }
75942064
SK		 1322
1323 spin_lock_irqsave(&ha->hardware_lock, flags);
25ff6af1 1324 sp->done(sp, 0);
75942064 1325 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1da177e4 1326
bc91ade9
CD		 1327 /* Did the command return during mailbox execution? */
1328 if (ret == FAILED && !CMD_SP(cmd))
1329 ret = SUCCESS;
1330
f4f051eb 1331 /* Wait for the command to be returned. */
2ea00202 1332 if (wait) {
e315cd28 1333 if (qla2x00_eh_wait_on_command(cmd) != QLA_SUCCESS) {
7c3df132 1334 ql_log(ql_log_warn, vha, 0x8006,
cfb0919c 1335 "Abort handler timed out cmd=%p.\n", cmd);
2ea00202 1336 ret = FAILED;
f4f051eb 1337 }
1da177e4 1338 }
1da177e4 1339
7c3df132 1340 ql_log(ql_log_info, vha, 0x801c,
9cb78c16 1341 "Abort command issued nexus=%ld:%d:%llu -- %d %x.\n",
cfb0919c 1342 vha->host_no, id, lun, wait, ret);
1da177e4 1343
f4f051eb 1344 return ret;
1345}
1da177e4 1346
4d78c973 1347int
e315cd28 1348qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t,
9cb78c16 1349 uint64_t l, enum nexus_wait_type type)
f4f051eb 1350{
17d98630 1351 int cnt, match, status;
18e144d3 1352 unsigned long flags;
e315cd28 1353 struct qla_hw_data *ha = vha->hw;
73208dfd 1354 struct req_que *req;
4d78c973 1355 srb_t *sp;
9ba56b95 1356 struct scsi_cmnd *cmd;
1da177e4 1357
523ec773 1358 status = QLA_SUCCESS;
17d98630 1359
e315cd28 1360 spin_lock_irqsave(&ha->hardware_lock, flags);
67c2e93a 1361 req = vha->req;
17d98630 1362 for (cnt = 1; status == QLA_SUCCESS &&
8d93f550 1363 cnt < req->num_outstanding_cmds; cnt++) {
17d98630
AC		 1364 sp = req->outstanding_cmds[cnt];
1365 if (!sp)
523ec773 1366 continue;
9ba56b95 1367 if (sp->type != SRB_SCSI_CMD)
cf53b069 1368 continue;
25ff6af1 1369 if (vha->vp_idx != sp->vha->vp_idx)
17d98630
AC		 1370 continue;
1371 match = 0;
9ba56b95 1372 cmd = GET_CMD_SP(sp);
17d98630
AC		 1373 switch (type) {
1374 case WAIT_HOST:
1375 match = 1;
1376 break;
1377 case WAIT_TARGET:
9ba56b95 1378 match = cmd->device->id == t;
17d98630
AC		 1379 break;
1380 case WAIT_LUN:
9ba56b95
GM		 1381 match = (cmd->device->id == t &&
1382 cmd->device->lun == l);
17d98630 1383 break;
73208dfd 1384 }
17d98630
AC		 1385 if (!match)
1386 continue;
1387
1388 spin_unlock_irqrestore(&ha->hardware_lock, flags);
9ba56b95 1389 status = qla2x00_eh_wait_on_command(cmd);
17d98630 1390 spin_lock_irqsave(&ha->hardware_lock, flags);
1da177e4 1391 }
e315cd28 1392 spin_unlock_irqrestore(&ha->hardware_lock, flags);
523ec773
AV		 1393
1394 return status;
1da177e4
LT		 1395}
1396
523ec773
AV		 1397static char *reset_errors[] = {
1398 "HBA not online",
1399 "HBA not ready",
1400 "Task management failed",
1401 "Waiting for command completions",
1402};
1da177e4 1403
e5f82ab8 1404static int
523ec773 1405__qla2xxx_eh_generic_reset(char *name, enum nexus_wait_type type,
9cb78c16 1406 struct scsi_cmnd *cmd, int (*do_reset)(struct fc_port *, uint64_t, int))
1da177e4 1407{
e315cd28 1408 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
bdf79621 1409 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
523ec773 1410 int err;
1da177e4 1411
7c3df132 1412 if (!fcport) {
523ec773 1413 return FAILED;
7c3df132 1414 }
1da177e4 1415
4e98d3b8
AV		 1416 err = fc_block_scsi_eh(cmd);
1417 if (err != 0)
1418 return err;
1419
7c3df132 1420 ql_log(ql_log_info, vha, 0x8009,
9cb78c16 1421 "%s RESET ISSUED nexus=%ld:%d:%llu cmd=%p.\n", name, vha->host_no,
7c3df132 1422 cmd->device->id, cmd->device->lun, cmd);
1da177e4 1423
523ec773 1424 err = 0;
7c3df132
SK		 1425 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1426 ql_log(ql_log_warn, vha, 0x800a,
1427 "Wait for hba online failed for cmd=%p.\n", cmd);
523ec773 1428 goto eh_reset_failed;
7c3df132 1429 }
523ec773 1430 err = 2;
2afa19a9 1431 if (do_reset(fcport, cmd->device->lun, cmd->request->cpu + 1)
7c3df132
SK		 1432 != QLA_SUCCESS) {
1433 ql_log(ql_log_warn, vha, 0x800c,
1434 "do_reset failed for cmd=%p.\n", cmd);
523ec773 1435 goto eh_reset_failed;
7c3df132 1436 }
523ec773 1437 err = 3;
e315cd28 1438 if (qla2x00_eh_wait_for_pending_commands(vha, cmd->device->id,
7c3df132
SK		 1439 cmd->device->lun, type) != QLA_SUCCESS) {
1440 ql_log(ql_log_warn, vha, 0x800d,
d6a03581 1441 "wait for pending cmds failed for cmd=%p.\n", cmd);
523ec773 1442 goto eh_reset_failed;
7c3df132 1443 }
523ec773 1444
7c3df132 1445 ql_log(ql_log_info, vha, 0x800e,
9cb78c16 1446 "%s RESET SUCCEEDED nexus:%ld:%d:%llu cmd=%p.\n", name,
cfb0919c 1447 vha->host_no, cmd->device->id, cmd->device->lun, cmd);
523ec773
AV		 1448
1449 return SUCCESS;
1450
4d78c973 1451eh_reset_failed:
7c3df132 1452 ql_log(ql_log_info, vha, 0x800f,
9cb78c16 1453 "%s RESET FAILED: %s nexus=%ld:%d:%llu cmd=%p.\n", name,
cfb0919c
CD		 1454 reset_errors[err], vha->host_no, cmd->device->id, cmd->device->lun,
1455 cmd);
523ec773
AV		 1456 return FAILED;
1457}
1da177e4 1458
523ec773
AV		 1459static int
1460qla2xxx_eh_device_reset(struct scsi_cmnd *cmd)
1461{
e315cd28
AC		 1462 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1463 struct qla_hw_data *ha = vha->hw;
1da177e4 1464
a465537a
SC		 1465 if (qla2x00_isp_reg_stat(ha)) {
1466 ql_log(ql_log_info, vha, 0x803e,
1467 "PCI/Register disconnect, exiting.\n");
1468 return FAILED;
1469 }
1470
523ec773
AV		 1471 return __qla2xxx_eh_generic_reset("DEVICE", WAIT_LUN, cmd,
1472 ha->isp_ops->lun_reset);
1da177e4
LT		 1473}
1474
1da177e4 1475static int
523ec773 1476qla2xxx_eh_target_reset(struct scsi_cmnd *cmd)
1da177e4 1477{
e315cd28
AC		 1478 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1479 struct qla_hw_data *ha = vha->hw;
1da177e4 1480
a465537a
SC		 1481 if (qla2x00_isp_reg_stat(ha)) {
1482 ql_log(ql_log_info, vha, 0x803f,
1483 "PCI/Register disconnect, exiting.\n");
1484 return FAILED;
1485 }
1486
523ec773
AV		 1487 return __qla2xxx_eh_generic_reset("TARGET", WAIT_TARGET, cmd,
1488 ha->isp_ops->target_reset);
1da177e4
LT		 1489}
1490
1da177e4
LT		 1491/**************************************************************************
1492* qla2xxx_eh_bus_reset
1493*
1494* Description:
1495* The bus reset function will reset the bus and abort any executing
1496* commands.
1497*
1498* Input:
1499* cmd = Linux SCSI command packet of the command that cause the
1500* bus reset.
1501*
1502* Returns:
1503* SUCCESS/FAILURE (defined as macro in scsi.h).
1504*
1505**************************************************************************/
e5f82ab8 1506static int
1da177e4
LT		 1507qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd)
1508{
e315cd28 1509 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
bdf79621 1510 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
2c3dfe3f 1511 int ret = FAILED;
9cb78c16
HR		 1512 unsigned int id;
1513 uint64_t lun;
a465537a
SC		 1514 struct qla_hw_data *ha = vha->hw;
1515
1516 if (qla2x00_isp_reg_stat(ha)) {
1517 ql_log(ql_log_info, vha, 0x8040,
1518 "PCI/Register disconnect, exiting.\n");
1519 return FAILED;
1520 }
f4f051eb 1521
f4f051eb 1522 id = cmd->device->id;
1523 lun = cmd->device->lun;
1da177e4 1524
7c3df132 1525 if (!fcport) {
f4f051eb 1526 return ret;
7c3df132 1527 }
1da177e4 1528
4e98d3b8
AV		 1529 ret = fc_block_scsi_eh(cmd);
1530 if (ret != 0)
1531 return ret;
1532 ret = FAILED;
1533
7c3df132 1534 ql_log(ql_log_info, vha, 0x8012,
9cb78c16 1535 "BUS RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun);
1da177e4 1536
e315cd28 1537 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
7c3df132
SK		 1538 ql_log(ql_log_fatal, vha, 0x8013,
1539 "Wait for hba online failed board disabled.\n");
f4f051eb 1540 goto eh_bus_reset_done;
1da177e4
LT		 1541 }
1542
ad537689
SK		 1543 if (qla2x00_loop_reset(vha) == QLA_SUCCESS)
1544 ret = SUCCESS;
1545
f4f051eb 1546 if (ret == FAILED)
1547 goto eh_bus_reset_done;
1da177e4 1548
9a41a62b 1549 /* Flush outstanding commands. */
4d78c973 1550 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) !=
7c3df132
SK		 1551 QLA_SUCCESS) {
1552 ql_log(ql_log_warn, vha, 0x8014,
1553 "Wait for pending commands failed.\n");
9a41a62b 1554 ret = FAILED;
7c3df132 1555 }
1da177e4 1556
f4f051eb 1557eh_bus_reset_done:
7c3df132 1558 ql_log(ql_log_warn, vha, 0x802b,
9cb78c16 1559 "BUS RESET %s nexus=%ld:%d:%llu.\n",
d6a03581 1560 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1da177e4 1561
f4f051eb 1562 return ret;
1da177e4
LT		 1563}
1564
1565/**************************************************************************
1566* qla2xxx_eh_host_reset
1567*
1568* Description:
1569* The reset function will reset the Adapter.
1570*
1571* Input:
1572* cmd = Linux SCSI command packet of the command that cause the
1573* adapter reset.
1574*
1575* Returns:
1576* Either SUCCESS or FAILED.
1577*
1578* Note:
1579**************************************************************************/
e5f82ab8 1580static int
1da177e4
LT		 1581qla2xxx_eh_host_reset(struct scsi_cmnd *cmd)
1582{
e315cd28 1583 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
e315cd28 1584 struct qla_hw_data *ha = vha->hw;
2c3dfe3f 1585 int ret = FAILED;
9cb78c16
HR		 1586 unsigned int id;
1587 uint64_t lun;
e315cd28 1588 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4 1589
a465537a
SC		 1590 if (qla2x00_isp_reg_stat(ha)) {
1591 ql_log(ql_log_info, vha, 0x8041,
1592 "PCI/Register disconnect, exiting.\n");
1593 schedule_work(&ha->board_disable);
1594 return SUCCESS;
1595 }
1596
f4f051eb 1597 id = cmd->device->id;
1598 lun = cmd->device->lun;
f4f051eb 1599
7c3df132 1600 ql_log(ql_log_info, vha, 0x8018,
9cb78c16 1601 "ADAPTER RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun);
1da177e4 1602
63ee7072
CD		 1603 /*
1604 * No point in issuing another reset if one is active. Also do not
1605 * attempt a reset if we are updating flash.
1606 */
1607 if (qla2x00_reset_active(vha) || ha->optrom_state != QLA_SWAITING)
f4f051eb 1608 goto eh_host_reset_lock;
1da177e4 1609
e315cd28
AC		 1610 if (vha != base_vha) {
1611 if (qla2x00_vp_abort_isp(vha))
f4f051eb 1612 goto eh_host_reset_lock;
e315cd28 1613 } else {
7ec0effd 1614 if (IS_P3P_TYPE(vha->hw)) {
a9083016
GM		 1615 if (!qla82xx_fcoe_ctx_reset(vha)) {
1616 /* Ctx reset success */
1617 ret = SUCCESS;
1618 goto eh_host_reset_lock;
1619 }
1620 /* fall thru if ctx reset failed */
1621 }
68ca949c
AC		 1622 if (ha->wq)
1623 flush_workqueue(ha->wq);
1624
e315cd28 1625 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
a9083016 1626 if (ha->isp_ops->abort_isp(base_vha)) {
e315cd28
AC		 1627 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1628 /* failed. schedule dpc to try */
1629 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
1630
7c3df132
SK		 1631 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1632 ql_log(ql_log_warn, vha, 0x802a,
1633 "wait for hba online failed.\n");
e315cd28 1634 goto eh_host_reset_lock;
7c3df132 1635 }
e315cd28
AC		 1636 }
1637 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
fa2a1ce5 1638 }
1da177e4 1639
e315cd28 1640 /* Waiting for command to be returned to OS.*/
4d78c973 1641 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) ==
e315cd28 1642 QLA_SUCCESS)
f4f051eb 1643 ret = SUCCESS;
1da177e4 1644
f4f051eb 1645eh_host_reset_lock:
cfb0919c 1646 ql_log(ql_log_info, vha, 0x8017,
9cb78c16 1647 "ADAPTER RESET %s nexus=%ld:%d:%llu.\n",
cfb0919c 1648 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1da177e4 1649
f4f051eb 1650 return ret;
1651}
1da177e4
LT		 1652
1653/*
1654* qla2x00_loop_reset
1655* Issue loop reset.
1656*
1657* Input:
1658* ha = adapter block pointer.
1659*
1660* Returns:
1661* 0 = success
1662*/
a4722cf2 1663int
e315cd28 1664qla2x00_loop_reset(scsi_qla_host_t *vha)
1da177e4 1665{
0c8c39af 1666 int ret;
bdf79621 1667 struct fc_port *fcport;
e315cd28 1668 struct qla_hw_data *ha = vha->hw;
1da177e4 1669
5854771e
AB		 1670 if (IS_QLAFX00(ha)) {
1671 return qlafx00_loop_reset(vha);
1672 }
1673
f4c496c1 1674 if (ql2xtargetreset == 1 && ha->flags.enable_target_reset) {
55e5ed27
AV		 1675 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1676 if (fcport->port_type != FCT_TARGET)
1677 continue;
1678
1679 ret = ha->isp_ops->target_reset(fcport, 0, 0);
1680 if (ret != QLA_SUCCESS) {
7c3df132 1681 ql_dbg(ql_dbg_taskm, vha, 0x802c,
5854771e 1682 "Bus Reset failed: Reset=%d "
7c3df132 1683 "d_id=%x.\n", ret, fcport->d_id.b24);
55e5ed27
AV		 1684 }
1685 }
1686 }
1687
8ae6d9c7 1688
6246b8a1 1689 if (ha->flags.enable_lip_full_login && !IS_CNA_CAPABLE(ha)) {
0b7e7c53
AV		 1690 atomic_set(&vha->loop_state, LOOP_DOWN);
1691 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
1692 qla2x00_mark_all_devices_lost(vha, 0);
e315cd28 1693 ret = qla2x00_full_login_lip(vha);
0c8c39af 1694 if (ret != QLA_SUCCESS) {
7c3df132
SK		 1695 ql_dbg(ql_dbg_taskm, vha, 0x802d,
1696 "full_login_lip=%d.\n", ret);
749af3d5 1697 }
0c8c39af
AV		 1698 }
1699
0d6e61bc 1700 if (ha->flags.enable_lip_reset) {
e315cd28 1701 ret = qla2x00_lip_reset(vha);
ad537689 1702 if (ret != QLA_SUCCESS)
7c3df132
SK		 1703 ql_dbg(ql_dbg_taskm, vha, 0x802e,
1704 "lip_reset failed (%d).\n", ret);
1da177e4
LT		 1705 }
1706
1da177e4 1707 /* Issue marker command only when we are going to start the I/O */
e315cd28 1708 vha->marker_needed = 1;
1da177e4 1709
0c8c39af 1710 return QLA_SUCCESS;
1da177e4
LT		 1711}
1712
bbead493
QT		 1713static void
1714__qla2x00_abort_all_cmds(struct qla_qpair *qp, int res)
df4bf0bb 1715{
bbead493 1716 int cnt, status;
df4bf0bb
AV		 1717 unsigned long flags;
1718 srb_t *sp;
bbead493 1719 scsi_qla_host_t *vha = qp->vha;
e315cd28 1720 struct qla_hw_data *ha = vha->hw;
73208dfd 1721 struct req_que *req;
c5419e26
QT		 1722 struct qla_tgt *tgt = vha->vha_tgt.qla_tgt;
1723 struct qla_tgt_cmd *cmd;
1724 uint8_t trace = 0;
c0cb4496 1725
6a2cf8d3
BK		 1726 if (!ha->req_q_map)
1727 return;
bbead493
QT		 1728 spin_lock_irqsave(qp->qp_lock_ptr, flags);
1729 req = qp->req;
1730 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) {
1731 sp = req->outstanding_cmds[cnt];
1732 if (sp) {
1733 req->outstanding_cmds[cnt] = NULL;
1734 if (sp->cmd_type == TYPE_SRB) {
1735 if (sp->type == SRB_NVME_CMD ||
1736 sp->type == SRB_NVME_LS) {
1737 sp_get(sp);
1738 spin_unlock_irqrestore(qp->qp_lock_ptr,
1739 flags);
623ee824 1740 qla_nvme_abort(ha, sp, res);
bbead493
QT		 1741 spin_lock_irqsave(qp->qp_lock_ptr,
1742 flags);
1743 } else if (GET_CMD_SP(sp) &&
1744 !ha->flags.eeh_busy &&
1745 (!test_bit(ABORT_ISP_ACTIVE,
1746 &vha->dpc_flags)) &&
1747 (sp->type == SRB_SCSI_CMD)) {
1748 /*
1749 * Don't abort commands in
1750 * adapter during EEH
1751 * recovery as it's not
1752 * accessible/responding.
1753 *
1754 * Get a reference to the sp
1755 * and drop the lock. The
1756 * reference ensures this
1757 * sp->done() call and not the
1758 * call in qla2xxx_eh_abort()
1759 * ends the SCSI command (with
1760 * result 'res').
1761 */
1762 sp_get(sp);
1763 spin_unlock_irqrestore(qp->qp_lock_ptr,
1764 flags);
1765 status = qla2xxx_eh_abort(
1766 GET_CMD_SP(sp));
1767 spin_lock_irqsave(qp->qp_lock_ptr,
1768 flags);
1769 /*
1770 * Get rid of extra reference
1771 * if immediate exit from
1772 * ql2xxx_eh_abort
1773 */
1774 if (status == FAILED &&
1775 (qla2x00_isp_reg_stat(ha)))
1776 atomic_dec(
1777 &sp->ref_count);
1778 }
1779 sp->done(sp, res);
1780 } else {
1781 if (!vha->hw->tgt.tgt_ops || !tgt ||
1782 qla_ini_mode_enabled(vha)) {
1783 if (!trace)
1784 ql_dbg(ql_dbg_tgt_mgt,
1785 vha, 0xf003,
1786 "HOST-ABORT-HNDLR: dpc_flags=%lx. Target mode disabled\n",
1787 vha->dpc_flags);
1788 continue;
c733ab35 1789 }
bbead493
QT		 1790 cmd = (struct qla_tgt_cmd *)sp;
1791 qlt_abort_cmd_on_host_reset(cmd->vha, cmd);
73208dfd 1792 }
df4bf0bb
AV		 1793 }
1794 }
bbead493
QT		 1795 spin_unlock_irqrestore(qp->qp_lock_ptr, flags);
1796}
1797
1798void
1799qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res)
1800{
1801 int que;
1802 struct qla_hw_data *ha = vha->hw;
1803
1804 __qla2x00_abort_all_cmds(ha->base_qpair, res);
1805
1806 for (que = 0; que < ha->max_qpairs; que++) {
1807 if (!ha->queue_pair_map[que])
1808 continue;
1809
1810 __qla2x00_abort_all_cmds(ha->queue_pair_map[que], res);
1811 }
df4bf0bb
AV		 1812}
1813
f4f051eb 1814static int
1815qla2xxx_slave_alloc(struct scsi_device *sdev)
1da177e4 1816{
bdf79621 1817 struct fc_rport *rport = starget_to_rport(scsi_target(sdev));
1da177e4 1818
19a7b4ae 1819 if (!rport || fc_remote_port_chkready(rport))
f4f051eb 1820 return -ENXIO;
bdf79621 1821
19a7b4ae 1822 sdev->hostdata = *(fc_port_t **)rport->dd_data;
1da177e4 1823
f4f051eb 1824 return 0;
1825}
1da177e4 1826
f4f051eb 1827static int
1828qla2xxx_slave_configure(struct scsi_device *sdev)
1829{
e315cd28 1830 scsi_qla_host_t *vha = shost_priv(sdev->host);
2afa19a9 1831 struct req_que *req = vha->req;
8482e118 1832
9e522cd8
AE		 1833 if (IS_T10_PI_CAPABLE(vha->hw))
1834 blk_queue_update_dma_alignment(sdev->request_queue, 0x7);
1835
db5ed4df 1836 scsi_change_queue_depth(sdev, req->max_q_depth);
f4f051eb 1837 return 0;
1838}
1da177e4 1839
f4f051eb 1840static void
1841qla2xxx_slave_destroy(struct scsi_device *sdev)
1842{
1843 sdev->hostdata = NULL;
1da177e4
LT		 1844}
1845
1846/**
1847 * qla2x00_config_dma_addressing() - Configure OS DMA addressing method.
1848 * @ha: HA context
1849 *
1850 * At exit, the @ha's flags.enable_64bit_addressing set to indicated
1851 * supported addressing method.
1852 */
1853static void
53303c42 1854qla2x00_config_dma_addressing(struct qla_hw_data *ha)
1da177e4 1855{
7524f9b9 1856 /* Assume a 32bit DMA mask. */
1da177e4 1857 ha->flags.enable_64bit_addressing = 0;
1da177e4 1858
6a35528a 1859 if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) {
7524f9b9
AV		 1860 /* Any upper-dword bits set? */
1861 if (MSD(dma_get_required_mask(&ha->pdev->dev)) &&
6a35528a 1862 !pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(64))) {
7524f9b9 1863 /* Ok, a 64bit DMA mask is applicable. */
1da177e4 1864 ha->flags.enable_64bit_addressing = 1;
fd34f556
AV		 1865 ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64;
1866 ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64;
7524f9b9 1867 return;
1da177e4 1868 }
1da177e4 1869 }
7524f9b9 1870
284901a9
YH		 1871 dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32));
1872 pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(32));
1da177e4
LT		 1873}
1874
fd34f556 1875static void
e315cd28 1876qla2x00_enable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1877{
1878 unsigned long flags = 0;
1879 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1880
1881 spin_lock_irqsave(&ha->hardware_lock, flags);
1882 ha->interrupts_on = 1;
1883 /* enable risc and host interrupts */
1884 WRT_REG_WORD(&reg->ictrl, ICR_EN_INT | ICR_EN_RISC);
1885 RD_REG_WORD(&reg->ictrl);
1886 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1887
1888}
1889
1890static void
e315cd28 1891qla2x00_disable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1892{
1893 unsigned long flags = 0;
1894 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1895
1896 spin_lock_irqsave(&ha->hardware_lock, flags);
1897 ha->interrupts_on = 0;
1898 /* disable risc and host interrupts */
1899 WRT_REG_WORD(&reg->ictrl, 0);
1900 RD_REG_WORD(&reg->ictrl);
1901 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1902}
1903
1904static void
e315cd28 1905qla24xx_enable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1906{
1907 unsigned long flags = 0;
1908 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1909
1910 spin_lock_irqsave(&ha->hardware_lock, flags);
1911 ha->interrupts_on = 1;
1912 WRT_REG_DWORD(&reg->ictrl, ICRX_EN_RISC_INT);
1913 RD_REG_DWORD(&reg->ictrl);
1914 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1915}
1916
1917static void
e315cd28 1918qla24xx_disable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1919{
1920 unsigned long flags = 0;
1921 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1922
124f85e6
AV		 1923 if (IS_NOPOLLING_TYPE(ha))
1924 return;
fd34f556
AV		 1925 spin_lock_irqsave(&ha->hardware_lock, flags);
1926 ha->interrupts_on = 0;
1927 WRT_REG_DWORD(&reg->ictrl, 0);
1928 RD_REG_DWORD(&reg->ictrl);
1929 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1930}
1931
706f457d
GM		 1932static int
1933qla2x00_iospace_config(struct qla_hw_data *ha)
1934{
1935 resource_size_t pio;
1936 uint16_t msix;
706f457d 1937
706f457d
GM		 1938 if (pci_request_selected_regions(ha->pdev, ha->bars,
1939 QLA2XXX_DRIVER_NAME)) {
1940 ql_log_pci(ql_log_fatal, ha->pdev, 0x0011,
1941 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
1942 pci_name(ha->pdev));
1943 goto iospace_error_exit;
1944 }
1945 if (!(ha->bars & 1))
1946 goto skip_pio;
1947
1948 /* We only need PIO for Flash operations on ISP2312 v2 chips. */
1949 pio = pci_resource_start(ha->pdev, 0);
1950 if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) {
1951 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
1952 ql_log_pci(ql_log_warn, ha->pdev, 0x0012,
1953 "Invalid pci I/O region size (%s).\n",
1954 pci_name(ha->pdev));
1955 pio = 0;
1956 }
1957 } else {
1958 ql_log_pci(ql_log_warn, ha->pdev, 0x0013,
1959 "Region #0 no a PIO resource (%s).\n",
1960 pci_name(ha->pdev));
1961 pio = 0;
1962 }
1963 ha->pio_address = pio;
1964 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014,
1965 "PIO address=%llu.\n",
1966 (unsigned long long)ha->pio_address);
1967
1968skip_pio:
1969 /* Use MMIO operations for all accesses. */
1970 if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) {
1971 ql_log_pci(ql_log_fatal, ha->pdev, 0x0015,
1972 "Region #1 not an MMIO resource (%s), aborting.\n",
1973 pci_name(ha->pdev));
1974 goto iospace_error_exit;
1975 }
1976 if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) {
1977 ql_log_pci(ql_log_fatal, ha->pdev, 0x0016,
1978 "Invalid PCI mem region size (%s), aborting.\n",
1979 pci_name(ha->pdev));
1980 goto iospace_error_exit;
1981 }
1982
1983 ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN);
1984 if (!ha->iobase) {
1985 ql_log_pci(ql_log_fatal, ha->pdev, 0x0017,
1986 "Cannot remap MMIO (%s), aborting.\n",
1987 pci_name(ha->pdev));
1988 goto iospace_error_exit;
1989 }
1990
1991 /* Determine queue resources */
1992 ha->max_req_queues = ha->max_rsp_queues = 1;
f54f2cb5 1993 ha->msix_count = QLA_BASE_VECTORS;
c38d1baf
HM		 1994 if (!ql2xmqsupport || !ql2xnvmeenable ||
1995 (!IS_QLA25XX(ha) && !IS_QLA81XX(ha)))
706f457d
GM		 1996 goto mqiobase_exit;
1997
1998 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3),
1999 pci_resource_len(ha->pdev, 3));
2000 if (ha->mqiobase) {
2001 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018,
2002 "MQIO Base=%p.\n", ha->mqiobase);
2003 /* Read MSIX vector size of the board */
2004 pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix);
d7459527 2005 ha->msix_count = msix + 1;
706f457d 2006 /* Max queues are bounded by available msix vectors */
d7459527
MH		 2007 /* MB interrupt uses 1 vector */
2008 ha->max_req_queues = ha->msix_count - 1;
2009 ha->max_rsp_queues = ha->max_req_queues;
2010 /* Queue pairs is the max value minus the base queue pair */
2011 ha->max_qpairs = ha->max_rsp_queues - 1;
2012 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0188,
2013 "Max no of queues pairs: %d.\n", ha->max_qpairs);
2014
706f457d 2015 ql_log_pci(ql_log_info, ha->pdev, 0x001a,
d7459527 2016 "MSI-X vector count: %d.\n", ha->msix_count);
706f457d
GM		 2017 } else
2018 ql_log_pci(ql_log_info, ha->pdev, 0x001b,
2019 "BAR 3 not enabled.\n");
2020
2021mqiobase_exit:
706f457d 2022 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c,
f54f2cb5 2023 "MSIX Count: %d.\n", ha->msix_count);
706f457d
GM		 2024 return (0);
2025
2026iospace_error_exit:
2027 return (-ENOMEM);
2028}
2029
2030
6246b8a1
GM		 2031static int
2032qla83xx_iospace_config(struct qla_hw_data *ha)
2033{
2034 uint16_t msix;
6246b8a1
GM		 2035
2036 if (pci_request_selected_regions(ha->pdev, ha->bars,
2037 QLA2XXX_DRIVER_NAME)) {
2038 ql_log_pci(ql_log_fatal, ha->pdev, 0x0117,
2039 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
2040 pci_name(ha->pdev));
2041
2042 goto iospace_error_exit;
2043 }
2044
2045 /* Use MMIO operations for all accesses. */
2046 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) {
2047 ql_log_pci(ql_log_warn, ha->pdev, 0x0118,
2048 "Invalid pci I/O region size (%s).\n",
2049 pci_name(ha->pdev));
2050 goto iospace_error_exit;
2051 }
2052 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
2053 ql_log_pci(ql_log_warn, ha->pdev, 0x0119,
2054 "Invalid PCI mem region size (%s), aborting\n",
2055 pci_name(ha->pdev));
2056 goto iospace_error_exit;
2057 }
2058
2059 ha->iobase = ioremap(pci_resource_start(ha->pdev, 0), MIN_IOBASE_LEN);
2060 if (!ha->iobase) {
2061 ql_log_pci(ql_log_fatal, ha->pdev, 0x011a,
2062 "Cannot remap MMIO (%s), aborting.\n",
2063 pci_name(ha->pdev));
2064 goto iospace_error_exit;
2065 }
2066
2067 /* 64bit PCI BAR - BAR2 will correspoond to region 4 */
2068 /* 83XX 26XX always use MQ type access for queues
2069 * - mbar 2, a.k.a region 4 */
2070 ha->max_req_queues = ha->max_rsp_queues = 1;
f54f2cb5 2071 ha->msix_count = QLA_BASE_VECTORS;
6246b8a1
GM		 2072 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 4),
2073 pci_resource_len(ha->pdev, 4));
2074
2075 if (!ha->mqiobase) {
2076 ql_log_pci(ql_log_fatal, ha->pdev, 0x011d,
2077 "BAR2/region4 not enabled\n");
2078 goto mqiobase_exit;
2079 }
2080
2081 ha->msixbase = ioremap(pci_resource_start(ha->pdev, 2),
2082 pci_resource_len(ha->pdev, 2));
2083 if (ha->msixbase) {
2084 /* Read MSIX vector size of the board */
2085 pci_read_config_word(ha->pdev,
2086 QLA_83XX_PCI_MSIX_CONTROL, &msix);
e326d22a 2087 ha->msix_count = (msix & PCI_MSIX_FLAGS_QSIZE) + 1;
093df737
QT		 2088 /*
2089 * By default, driver uses at least two msix vectors
2090 * (default & rspq)
2091 */
c38d1baf 2092 if (ql2xmqsupport || ql2xnvmeenable) {
d7459527
MH		 2093 /* MB interrupt uses 1 vector */
2094 ha->max_req_queues = ha->msix_count - 1;
093df737
QT		 2095
2096 /* ATIOQ needs 1 vector. That's 1 less QPair */
2097 if (QLA_TGT_MODE_ENABLED())
2098 ha->max_req_queues--;
2099
d0d2c68b
MH		 2100 ha->max_rsp_queues = ha->max_req_queues;
2101
d7459527
MH		 2102 /* Queue pairs is the max value minus
2103 * the base queue pair */
2104 ha->max_qpairs = ha->max_req_queues - 1;
83548fe2 2105 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x00e3,
d7459527 2106 "Max no of queues pairs: %d.\n", ha->max_qpairs);
6246b8a1
GM		 2107 }
2108 ql_log_pci(ql_log_info, ha->pdev, 0x011c,
d7459527 2109 "MSI-X vector count: %d.\n", ha->msix_count);
6246b8a1
GM		 2110 } else
2111 ql_log_pci(ql_log_info, ha->pdev, 0x011e,
2112 "BAR 1 not enabled.\n");
2113
2114mqiobase_exit:
6246b8a1 2115 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011f,
f54f2cb5 2116 "MSIX Count: %d.\n", ha->msix_count);
6246b8a1
GM		 2117 return 0;
2118
2119iospace_error_exit:
2120 return -ENOMEM;
2121}
2122
fd34f556
AV		 2123static struct isp_operations qla2100_isp_ops = {
2124 .pci_config = qla2100_pci_config,
2125 .reset_chip = qla2x00_reset_chip,
2126 .chip_diag = qla2x00_chip_diag,
2127 .config_rings = qla2x00_config_rings,
2128 .reset_adapter = qla2x00_reset_adapter,
2129 .nvram_config = qla2x00_nvram_config,
2130 .update_fw_options = qla2x00_update_fw_options,
2131 .load_risc = qla2x00_load_risc,
2132 .pci_info_str = qla2x00_pci_info_str,
2133 .fw_version_str = qla2x00_fw_version_str,
2134 .intr_handler = qla2100_intr_handler,
2135 .enable_intrs = qla2x00_enable_intrs,
2136 .disable_intrs = qla2x00_disable_intrs,
2137 .abort_command = qla2x00_abort_command,
523ec773
AV		 2138 .target_reset = qla2x00_abort_target,
2139 .lun_reset = qla2x00_lun_reset,
fd34f556
AV		 2140 .fabric_login = qla2x00_login_fabric,
2141 .fabric_logout = qla2x00_fabric_logout,
2142 .calc_req_entries = qla2x00_calc_iocbs_32,
2143 .build_iocbs = qla2x00_build_scsi_iocbs_32,
2144 .prep_ms_iocb = qla2x00_prep_ms_iocb,
2145 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
2146 .read_nvram = qla2x00_read_nvram_data,
2147 .write_nvram = qla2x00_write_nvram_data,
2148 .fw_dump = qla2100_fw_dump,
2149 .beacon_on = NULL,
2150 .beacon_off = NULL,
2151 .beacon_blink = NULL,
2152 .read_optrom = qla2x00_read_optrom_data,
2153 .write_optrom = qla2x00_write_optrom_data,
2154 .get_flash_version = qla2x00_get_flash_version,
e315cd28 2155 .start_scsi = qla2x00_start_scsi,
d7459527 2156 .start_scsi_mq = NULL,
a9083016 2157 .abort_isp = qla2x00_abort_isp,
706f457d 2158 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2159 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 2160};
2161
2162static struct isp_operations qla2300_isp_ops = {
2163 .pci_config = qla2300_pci_config,
2164 .reset_chip = qla2x00_reset_chip,
2165 .chip_diag = qla2x00_chip_diag,
2166 .config_rings = qla2x00_config_rings,
2167 .reset_adapter = qla2x00_reset_adapter,
2168 .nvram_config = qla2x00_nvram_config,
2169 .update_fw_options = qla2x00_update_fw_options,
2170 .load_risc = qla2x00_load_risc,
2171 .pci_info_str = qla2x00_pci_info_str,
2172 .fw_version_str = qla2x00_fw_version_str,
2173 .intr_handler = qla2300_intr_handler,
2174 .enable_intrs = qla2x00_enable_intrs,
2175 .disable_intrs = qla2x00_disable_intrs,
2176 .abort_command = qla2x00_abort_command,
523ec773
AV		 2177 .target_reset = qla2x00_abort_target,
2178 .lun_reset = qla2x00_lun_reset,
fd34f556
AV		 2179 .fabric_login = qla2x00_login_fabric,
2180 .fabric_logout = qla2x00_fabric_logout,
2181 .calc_req_entries = qla2x00_calc_iocbs_32,
2182 .build_iocbs = qla2x00_build_scsi_iocbs_32,
2183 .prep_ms_iocb = qla2x00_prep_ms_iocb,
2184 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
2185 .read_nvram = qla2x00_read_nvram_data,
2186 .write_nvram = qla2x00_write_nvram_data,
2187 .fw_dump = qla2300_fw_dump,
2188 .beacon_on = qla2x00_beacon_on,
2189 .beacon_off = qla2x00_beacon_off,
2190 .beacon_blink = qla2x00_beacon_blink,
2191 .read_optrom = qla2x00_read_optrom_data,
2192 .write_optrom = qla2x00_write_optrom_data,
2193 .get_flash_version = qla2x00_get_flash_version,
e315cd28 2194 .start_scsi = qla2x00_start_scsi,
d7459527 2195 .start_scsi_mq = NULL,
a9083016 2196 .abort_isp = qla2x00_abort_isp,
7ec0effd 2197 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2198 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 2199};
2200
2201static struct isp_operations qla24xx_isp_ops = {
2202 .pci_config = qla24xx_pci_config,
2203 .reset_chip = qla24xx_reset_chip,
2204 .chip_diag = qla24xx_chip_diag,
2205 .config_rings = qla24xx_config_rings,
2206 .reset_adapter = qla24xx_reset_adapter,
2207 .nvram_config = qla24xx_nvram_config,
2208 .update_fw_options = qla24xx_update_fw_options,
2209 .load_risc = qla24xx_load_risc,
2210 .pci_info_str = qla24xx_pci_info_str,
2211 .fw_version_str = qla24xx_fw_version_str,
2212 .intr_handler = qla24xx_intr_handler,
2213 .enable_intrs = qla24xx_enable_intrs,
2214 .disable_intrs = qla24xx_disable_intrs,
2215 .abort_command = qla24xx_abort_command,
523ec773
AV		 2216 .target_reset = qla24xx_abort_target,
2217 .lun_reset = qla24xx_lun_reset,
fd34f556
AV		 2218 .fabric_login = qla24xx_login_fabric,
2219 .fabric_logout = qla24xx_fabric_logout,
2220 .calc_req_entries = NULL,
2221 .build_iocbs = NULL,
2222 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2223 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2224 .read_nvram = qla24xx_read_nvram_data,
2225 .write_nvram = qla24xx_write_nvram_data,
2226 .fw_dump = qla24xx_fw_dump,
2227 .beacon_on = qla24xx_beacon_on,
2228 .beacon_off = qla24xx_beacon_off,
2229 .beacon_blink = qla24xx_beacon_blink,
2230 .read_optrom = qla24xx_read_optrom_data,
2231 .write_optrom = qla24xx_write_optrom_data,
2232 .get_flash_version = qla24xx_get_flash_version,
e315cd28 2233 .start_scsi = qla24xx_start_scsi,
d7459527 2234 .start_scsi_mq = NULL,
a9083016 2235 .abort_isp = qla2x00_abort_isp,
7ec0effd 2236 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2237 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 2238};
2239
c3a2f0df
AV		 2240static struct isp_operations qla25xx_isp_ops = {
2241 .pci_config = qla25xx_pci_config,
2242 .reset_chip = qla24xx_reset_chip,
2243 .chip_diag = qla24xx_chip_diag,
2244 .config_rings = qla24xx_config_rings,
2245 .reset_adapter = qla24xx_reset_adapter,
2246 .nvram_config = qla24xx_nvram_config,
2247 .update_fw_options = qla24xx_update_fw_options,
2248 .load_risc = qla24xx_load_risc,
2249 .pci_info_str = qla24xx_pci_info_str,
2250 .fw_version_str = qla24xx_fw_version_str,
2251 .intr_handler = qla24xx_intr_handler,
2252 .enable_intrs = qla24xx_enable_intrs,
2253 .disable_intrs = qla24xx_disable_intrs,
2254 .abort_command = qla24xx_abort_command,
523ec773
AV		 2255 .target_reset = qla24xx_abort_target,
2256 .lun_reset = qla24xx_lun_reset,
c3a2f0df
AV		 2257 .fabric_login = qla24xx_login_fabric,
2258 .fabric_logout = qla24xx_fabric_logout,
2259 .calc_req_entries = NULL,
2260 .build_iocbs = NULL,
2261 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2262 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2263 .read_nvram = qla25xx_read_nvram_data,
2264 .write_nvram = qla25xx_write_nvram_data,
2265 .fw_dump = qla25xx_fw_dump,
2266 .beacon_on = qla24xx_beacon_on,
2267 .beacon_off = qla24xx_beacon_off,
2268 .beacon_blink = qla24xx_beacon_blink,
338c9161 2269 .read_optrom = qla25xx_read_optrom_data,
c3a2f0df
AV		 2270 .write_optrom = qla24xx_write_optrom_data,
2271 .get_flash_version = qla24xx_get_flash_version,
bad75002 2272 .start_scsi = qla24xx_dif_start_scsi,
d7459527 2273 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
a9083016 2274 .abort_isp = qla2x00_abort_isp,
7ec0effd 2275 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2276 .initialize_adapter = qla2x00_initialize_adapter,
c3a2f0df
AV		 2277};
2278
3a03eb79
AV		 2279static struct isp_operations qla81xx_isp_ops = {
2280 .pci_config = qla25xx_pci_config,
2281 .reset_chip = qla24xx_reset_chip,
2282 .chip_diag = qla24xx_chip_diag,
2283 .config_rings = qla24xx_config_rings,
2284 .reset_adapter = qla24xx_reset_adapter,
2285 .nvram_config = qla81xx_nvram_config,
2286 .update_fw_options = qla81xx_update_fw_options,
eaac30be 2287 .load_risc = qla81xx_load_risc,
3a03eb79
AV		 2288 .pci_info_str = qla24xx_pci_info_str,
2289 .fw_version_str = qla24xx_fw_version_str,
2290 .intr_handler = qla24xx_intr_handler,
2291 .enable_intrs = qla24xx_enable_intrs,
2292 .disable_intrs = qla24xx_disable_intrs,
2293 .abort_command = qla24xx_abort_command,
2294 .target_reset = qla24xx_abort_target,
2295 .lun_reset = qla24xx_lun_reset,
2296 .fabric_login = qla24xx_login_fabric,
2297 .fabric_logout = qla24xx_fabric_logout,
2298 .calc_req_entries = NULL,
2299 .build_iocbs = NULL,
2300 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2301 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
3d79038f
AV		 2302 .read_nvram = NULL,
2303 .write_nvram = NULL,
3a03eb79
AV		 2304 .fw_dump = qla81xx_fw_dump,
2305 .beacon_on = qla24xx_beacon_on,
2306 .beacon_off = qla24xx_beacon_off,
6246b8a1 2307 .beacon_blink = qla83xx_beacon_blink,
3a03eb79
AV		 2308 .read_optrom = qla25xx_read_optrom_data,
2309 .write_optrom = qla24xx_write_optrom_data,
2310 .get_flash_version = qla24xx_get_flash_version,
ba77ef53 2311 .start_scsi = qla24xx_dif_start_scsi,
d7459527 2312 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
a9083016 2313 .abort_isp = qla2x00_abort_isp,
7ec0effd 2314 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2315 .initialize_adapter = qla2x00_initialize_adapter,
a9083016
GM		 2316};
2317
2318static struct isp_operations qla82xx_isp_ops = {
2319 .pci_config = qla82xx_pci_config,
2320 .reset_chip = qla82xx_reset_chip,
2321 .chip_diag = qla24xx_chip_diag,
2322 .config_rings = qla82xx_config_rings,
2323 .reset_adapter = qla24xx_reset_adapter,
2324 .nvram_config = qla81xx_nvram_config,
2325 .update_fw_options = qla24xx_update_fw_options,
2326 .load_risc = qla82xx_load_risc,
9d55ca66 2327 .pci_info_str = qla24xx_pci_info_str,
a9083016
GM		 2328 .fw_version_str = qla24xx_fw_version_str,
2329 .intr_handler = qla82xx_intr_handler,
2330 .enable_intrs = qla82xx_enable_intrs,
2331 .disable_intrs = qla82xx_disable_intrs,
2332 .abort_command = qla24xx_abort_command,
2333 .target_reset = qla24xx_abort_target,
2334 .lun_reset = qla24xx_lun_reset,
2335 .fabric_login = qla24xx_login_fabric,
2336 .fabric_logout = qla24xx_fabric_logout,
2337 .calc_req_entries = NULL,
2338 .build_iocbs = NULL,
2339 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2340 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2341 .read_nvram = qla24xx_read_nvram_data,
2342 .write_nvram = qla24xx_write_nvram_data,
a1b23c5a 2343 .fw_dump = qla82xx_fw_dump,
999916dc
SK		 2344 .beacon_on = qla82xx_beacon_on,
2345 .beacon_off = qla82xx_beacon_off,
2346 .beacon_blink = NULL,
a9083016
GM		 2347 .read_optrom = qla82xx_read_optrom_data,
2348 .write_optrom = qla82xx_write_optrom_data,
7ec0effd 2349 .get_flash_version = qla82xx_get_flash_version,
a9083016 2350 .start_scsi = qla82xx_start_scsi,
d7459527 2351 .start_scsi_mq = NULL,
a9083016 2352 .abort_isp = qla82xx_abort_isp,
706f457d 2353 .iospace_config = qla82xx_iospace_config,
8ae6d9c7 2354 .initialize_adapter = qla2x00_initialize_adapter,
3a03eb79
AV		 2355};
2356
7ec0effd
AD		 2357static struct isp_operations qla8044_isp_ops = {
2358 .pci_config = qla82xx_pci_config,
2359 .reset_chip = qla82xx_reset_chip,
2360 .chip_diag = qla24xx_chip_diag,
2361 .config_rings = qla82xx_config_rings,
2362 .reset_adapter = qla24xx_reset_adapter,
2363 .nvram_config = qla81xx_nvram_config,
2364 .update_fw_options = qla24xx_update_fw_options,
2365 .load_risc = qla82xx_load_risc,
2366 .pci_info_str = qla24xx_pci_info_str,
2367 .fw_version_str = qla24xx_fw_version_str,
2368 .intr_handler = qla8044_intr_handler,
2369 .enable_intrs = qla82xx_enable_intrs,
2370 .disable_intrs = qla82xx_disable_intrs,
2371 .abort_command = qla24xx_abort_command,
2372 .target_reset = qla24xx_abort_target,
2373 .lun_reset = qla24xx_lun_reset,
2374 .fabric_login = qla24xx_login_fabric,
2375 .fabric_logout = qla24xx_fabric_logout,
2376 .calc_req_entries = NULL,
2377 .build_iocbs = NULL,
2378 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2379 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2380 .read_nvram = NULL,
2381 .write_nvram = NULL,
a1b23c5a 2382 .fw_dump = qla8044_fw_dump,
7ec0effd
AD		 2383 .beacon_on = qla82xx_beacon_on,
2384 .beacon_off = qla82xx_beacon_off,
2385 .beacon_blink = NULL,
888e639d 2386 .read_optrom = qla8044_read_optrom_data,
7ec0effd
AD		 2387 .write_optrom = qla8044_write_optrom_data,
2388 .get_flash_version = qla82xx_get_flash_version,
2389 .start_scsi = qla82xx_start_scsi,
d7459527 2390 .start_scsi_mq = NULL,
7ec0effd
AD		 2391 .abort_isp = qla8044_abort_isp,
2392 .iospace_config = qla82xx_iospace_config,
2393 .initialize_adapter = qla2x00_initialize_adapter,
2394};
2395
6246b8a1
GM		 2396static struct isp_operations qla83xx_isp_ops = {
2397 .pci_config = qla25xx_pci_config,
2398 .reset_chip = qla24xx_reset_chip,
2399 .chip_diag = qla24xx_chip_diag,
2400 .config_rings = qla24xx_config_rings,
2401 .reset_adapter = qla24xx_reset_adapter,
2402 .nvram_config = qla81xx_nvram_config,
2403 .update_fw_options = qla81xx_update_fw_options,
2404 .load_risc = qla81xx_load_risc,
2405 .pci_info_str = qla24xx_pci_info_str,
2406 .fw_version_str = qla24xx_fw_version_str,
2407 .intr_handler = qla24xx_intr_handler,
2408 .enable_intrs = qla24xx_enable_intrs,
2409 .disable_intrs = qla24xx_disable_intrs,
2410 .abort_command = qla24xx_abort_command,
2411 .target_reset = qla24xx_abort_target,
2412 .lun_reset = qla24xx_lun_reset,
2413 .fabric_login = qla24xx_login_fabric,
2414 .fabric_logout = qla24xx_fabric_logout,
2415 .calc_req_entries = NULL,
2416 .build_iocbs = NULL,
2417 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2418 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2419 .read_nvram = NULL,
2420 .write_nvram = NULL,
2421 .fw_dump = qla83xx_fw_dump,
2422 .beacon_on = qla24xx_beacon_on,
2423 .beacon_off = qla24xx_beacon_off,
2424 .beacon_blink = qla83xx_beacon_blink,
2425 .read_optrom = qla25xx_read_optrom_data,
2426 .write_optrom = qla24xx_write_optrom_data,
2427 .get_flash_version = qla24xx_get_flash_version,
2428 .start_scsi = qla24xx_dif_start_scsi,
d7459527 2429 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
6246b8a1
GM		 2430 .abort_isp = qla2x00_abort_isp,
2431 .iospace_config = qla83xx_iospace_config,
8ae6d9c7
GM		 2432 .initialize_adapter = qla2x00_initialize_adapter,
2433};
2434
2435static struct isp_operations qlafx00_isp_ops = {
2436 .pci_config = qlafx00_pci_config,
2437 .reset_chip = qlafx00_soft_reset,
2438 .chip_diag = qlafx00_chip_diag,
2439 .config_rings = qlafx00_config_rings,
2440 .reset_adapter = qlafx00_soft_reset,
2441 .nvram_config = NULL,
2442 .update_fw_options = NULL,
2443 .load_risc = NULL,
2444 .pci_info_str = qlafx00_pci_info_str,
2445 .fw_version_str = qlafx00_fw_version_str,
2446 .intr_handler = qlafx00_intr_handler,
2447 .enable_intrs = qlafx00_enable_intrs,
2448 .disable_intrs = qlafx00_disable_intrs,
4440e46d 2449 .abort_command = qla24xx_async_abort_command,
8ae6d9c7
GM		 2450 .target_reset = qlafx00_abort_target,
2451 .lun_reset = qlafx00_lun_reset,
2452 .fabric_login = NULL,
2453 .fabric_logout = NULL,
2454 .calc_req_entries = NULL,
2455 .build_iocbs = NULL,
2456 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2457 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2458 .read_nvram = qla24xx_read_nvram_data,
2459 .write_nvram = qla24xx_write_nvram_data,
2460 .fw_dump = NULL,
2461 .beacon_on = qla24xx_beacon_on,
2462 .beacon_off = qla24xx_beacon_off,
2463 .beacon_blink = NULL,
2464 .read_optrom = qla24xx_read_optrom_data,
2465 .write_optrom = qla24xx_write_optrom_data,
2466 .get_flash_version = qla24xx_get_flash_version,
2467 .start_scsi = qlafx00_start_scsi,
d7459527 2468 .start_scsi_mq = NULL,
8ae6d9c7
GM		 2469 .abort_isp = qlafx00_abort_isp,
2470 .iospace_config = qlafx00_iospace_config,
2471 .initialize_adapter = qlafx00_initialize_adapter,
6246b8a1
GM		 2472};
2473
f73cb695
CD		 2474static struct isp_operations qla27xx_isp_ops = {
2475 .pci_config = qla25xx_pci_config,
2476 .reset_chip = qla24xx_reset_chip,
2477 .chip_diag = qla24xx_chip_diag,
2478 .config_rings = qla24xx_config_rings,
2479 .reset_adapter = qla24xx_reset_adapter,
2480 .nvram_config = qla81xx_nvram_config,
2481 .update_fw_options = qla81xx_update_fw_options,
2482 .load_risc = qla81xx_load_risc,
2483 .pci_info_str = qla24xx_pci_info_str,
2484 .fw_version_str = qla24xx_fw_version_str,
2485 .intr_handler = qla24xx_intr_handler,
2486 .enable_intrs = qla24xx_enable_intrs,
2487 .disable_intrs = qla24xx_disable_intrs,
2488 .abort_command = qla24xx_abort_command,
2489 .target_reset = qla24xx_abort_target,
2490 .lun_reset = qla24xx_lun_reset,
2491 .fabric_login = qla24xx_login_fabric,
2492 .fabric_logout = qla24xx_fabric_logout,
2493 .calc_req_entries = NULL,
2494 .build_iocbs = NULL,
2495 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2496 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2497 .read_nvram = NULL,
2498 .write_nvram = NULL,
2499 .fw_dump = qla27xx_fwdump,
2500 .beacon_on = qla24xx_beacon_on,
2501 .beacon_off = qla24xx_beacon_off,
2502 .beacon_blink = qla83xx_beacon_blink,
2503 .read_optrom = qla25xx_read_optrom_data,
2504 .write_optrom = qla24xx_write_optrom_data,
2505 .get_flash_version = qla24xx_get_flash_version,
2506 .start_scsi = qla24xx_dif_start_scsi,
d7459527 2507 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
f73cb695
CD		 2508 .abort_isp = qla2x00_abort_isp,
2509 .iospace_config = qla83xx_iospace_config,
2510 .initialize_adapter = qla2x00_initialize_adapter,
2511};
2512
ea5b6382 2513static inline void
e315cd28 2514qla2x00_set_isp_flags(struct qla_hw_data *ha)
ea5b6382 2515{
2516 ha->device_type = DT_EXTENDED_IDS;
2517 switch (ha->pdev->device) {
2518 case PCI_DEVICE_ID_QLOGIC_ISP2100:
9e052e2d 2519 ha->isp_type |= DT_ISP2100;
ea5b6382 2520 ha->device_type &= ~DT_EXTENDED_IDS;
441d1072 2521 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
ea5b6382 2522 break;
2523 case PCI_DEVICE_ID_QLOGIC_ISP2200:
9e052e2d 2524 ha->isp_type |= DT_ISP2200;
ea5b6382 2525 ha->device_type &= ~DT_EXTENDED_IDS;
441d1072 2526 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
ea5b6382 2527 break;
2528 case PCI_DEVICE_ID_QLOGIC_ISP2300:
9e052e2d 2529 ha->isp_type |= DT_ISP2300;
4a59f71d 2530 ha->device_type |= DT_ZIO_SUPPORTED;
441d1072 2531 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 2532 break;
2533 case PCI_DEVICE_ID_QLOGIC_ISP2312:
9e052e2d 2534 ha->isp_type |= DT_ISP2312;
4a59f71d 2535 ha->device_type |= DT_ZIO_SUPPORTED;
441d1072 2536 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 2537 break;
2538 case PCI_DEVICE_ID_QLOGIC_ISP2322:
9e052e2d 2539 ha->isp_type |= DT_ISP2322;
4a59f71d 2540 ha->device_type |= DT_ZIO_SUPPORTED;
ea5b6382 2541 if (ha->pdev->subsystem_vendor == 0x1028 &&
2542 ha->pdev->subsystem_device == 0x0170)
2543 ha->device_type |= DT_OEM_001;
441d1072 2544 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 2545 break;
2546 case PCI_DEVICE_ID_QLOGIC_ISP6312:
9e052e2d 2547 ha->isp_type |= DT_ISP6312;
441d1072 2548 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 2549 break;
2550 case PCI_DEVICE_ID_QLOGIC_ISP6322:
9e052e2d 2551 ha->isp_type |= DT_ISP6322;
441d1072 2552 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 2553 break;
2554 case PCI_DEVICE_ID_QLOGIC_ISP2422:
9e052e2d 2555 ha->isp_type |= DT_ISP2422;
4a59f71d 2556 ha->device_type |= DT_ZIO_SUPPORTED;
e428924c 2557 ha->device_type |= DT_FWI2;
c76f2c01 2558 ha->device_type |= DT_IIDMA;
441d1072 2559 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2560 break;
2561 case PCI_DEVICE_ID_QLOGIC_ISP2432:
9e052e2d 2562 ha->isp_type |= DT_ISP2432;
4a59f71d 2563 ha->device_type |= DT_ZIO_SUPPORTED;
e428924c 2564 ha->device_type |= DT_FWI2;
c76f2c01 2565 ha->device_type |= DT_IIDMA;
441d1072 2566 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2567 break;
4d4df193 2568 case PCI_DEVICE_ID_QLOGIC_ISP8432:
9e052e2d 2569 ha->isp_type |= DT_ISP8432;
4d4df193
HK		 2570 ha->device_type |= DT_ZIO_SUPPORTED;
2571 ha->device_type |= DT_FWI2;
2572 ha->device_type |= DT_IIDMA;
2573 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2574 break;
044cc6c8 2575 case PCI_DEVICE_ID_QLOGIC_ISP5422:
9e052e2d 2576 ha->isp_type |= DT_ISP5422;
e428924c 2577 ha->device_type |= DT_FWI2;
441d1072 2578 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2579 break;
044cc6c8 2580 case PCI_DEVICE_ID_QLOGIC_ISP5432:
9e052e2d 2581 ha->isp_type |= DT_ISP5432;
e428924c 2582 ha->device_type |= DT_FWI2;
441d1072 2583 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2584 break;
c3a2f0df 2585 case PCI_DEVICE_ID_QLOGIC_ISP2532:
9e052e2d 2586 ha->isp_type |= DT_ISP2532;
c3a2f0df
AV		 2587 ha->device_type |= DT_ZIO_SUPPORTED;
2588 ha->device_type |= DT_FWI2;
2589 ha->device_type |= DT_IIDMA;
441d1072 2590 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2591 break;
3a03eb79 2592 case PCI_DEVICE_ID_QLOGIC_ISP8001:
9e052e2d 2593 ha->isp_type |= DT_ISP8001;
3a03eb79
AV		 2594 ha->device_type |= DT_ZIO_SUPPORTED;
2595 ha->device_type |= DT_FWI2;
2596 ha->device_type |= DT_IIDMA;
2597 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2598 break;
a9083016 2599 case PCI_DEVICE_ID_QLOGIC_ISP8021:
9e052e2d 2600 ha->isp_type |= DT_ISP8021;
a9083016
GM		 2601 ha->device_type |= DT_ZIO_SUPPORTED;
2602 ha->device_type |= DT_FWI2;
2603 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2604 /* Initialize 82XX ISP flags */
2605 qla82xx_init_flags(ha);
2606 break;
7ec0effd 2607 case PCI_DEVICE_ID_QLOGIC_ISP8044:
9e052e2d 2608 ha->isp_type |= DT_ISP8044;
7ec0effd
AD		 2609 ha->device_type |= DT_ZIO_SUPPORTED;
2610 ha->device_type |= DT_FWI2;
2611 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2612 /* Initialize 82XX ISP flags */
2613 qla82xx_init_flags(ha);
2614 break;
6246b8a1 2615 case PCI_DEVICE_ID_QLOGIC_ISP2031:
9e052e2d 2616 ha->isp_type |= DT_ISP2031;
6246b8a1
GM		 2617 ha->device_type |= DT_ZIO_SUPPORTED;
2618 ha->device_type |= DT_FWI2;
2619 ha->device_type |= DT_IIDMA;
2620 ha->device_type |= DT_T10_PI;
2621 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2622 break;
2623 case PCI_DEVICE_ID_QLOGIC_ISP8031:
9e052e2d 2624 ha->isp_type |= DT_ISP8031;
6246b8a1
GM		 2625 ha->device_type |= DT_ZIO_SUPPORTED;
2626 ha->device_type |= DT_FWI2;
2627 ha->device_type |= DT_IIDMA;
2628 ha->device_type |= DT_T10_PI;
2629 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2630 break;
8ae6d9c7 2631 case PCI_DEVICE_ID_QLOGIC_ISPF001:
9e052e2d 2632 ha->isp_type |= DT_ISPFX00;
8ae6d9c7 2633 break;
f73cb695 2634 case PCI_DEVICE_ID_QLOGIC_ISP2071:
9e052e2d 2635 ha->isp_type |= DT_ISP2071;
f73cb695
CD		 2636 ha->device_type |= DT_ZIO_SUPPORTED;
2637 ha->device_type |= DT_FWI2;
2638 ha->device_type |= DT_IIDMA;
8ce3f570 2639 ha->device_type |= DT_T10_PI;
f73cb695
CD		 2640 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2641 break;
2c5bbbb2 2642 case PCI_DEVICE_ID_QLOGIC_ISP2271:
9e052e2d 2643 ha->isp_type |= DT_ISP2271;
2c5bbbb2
JC		 2644 ha->device_type |= DT_ZIO_SUPPORTED;
2645 ha->device_type |= DT_FWI2;
2646 ha->device_type |= DT_IIDMA;
8ce3f570 2647 ha->device_type |= DT_T10_PI;
2c5bbbb2
JC		 2648 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2649 break;
2b48992f 2650 case PCI_DEVICE_ID_QLOGIC_ISP2261:
9e052e2d 2651 ha->isp_type |= DT_ISP2261;
2b48992f
SC		 2652 ha->device_type |= DT_ZIO_SUPPORTED;
2653 ha->device_type |= DT_FWI2;
2654 ha->device_type |= DT_IIDMA;
8ce3f570 2655 ha->device_type |= DT_T10_PI;
2b48992f
SC		 2656 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2657 break;
ea5b6382 2658 }
e5b68a61 2659
a9083016 2660 if (IS_QLA82XX(ha))
43a9c38b 2661 ha->port_no = ha->portnum & 1;
f73cb695 2662 else {
a9083016
GM		 2663 /* Get adapter physical port no from interrupt pin register. */
2664 pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no);
f73cb695
CD		 2665 if (IS_QLA27XX(ha))
2666 ha->port_no--;
2667 else
2668 ha->port_no = !(ha->port_no & 1);
2669 }
a9083016 2670
7c3df132 2671 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b,
d8424f68 2672 "device_type=0x%x port=%d fw_srisc_address=0x%x.\n",
f73cb695 2673 ha->device_type, ha->port_no, ha->fw_srisc_address);
ea5b6382 2674}
2675
1e99e33a
AV		 2676static void
2677qla2xxx_scan_start(struct Scsi_Host *shost)
2678{
e315cd28 2679 scsi_qla_host_t *vha = shost_priv(shost);
1e99e33a 2680
cbc8eb67
AV		 2681 if (vha->hw->flags.running_gold_fw)
2682 return;
2683
e315cd28
AC		 2684 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
2685 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
2686 set_bit(RSCN_UPDATE, &vha->dpc_flags);
2687 set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags);
1e99e33a
AV		 2688}
2689
2690static int
2691qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time)
2692{
e315cd28 2693 scsi_qla_host_t *vha = shost_priv(shost);
1e99e33a 2694
a5dd506e
BK		 2695 if (test_bit(UNLOADING, &vha->dpc_flags))
2696 return 1;
e315cd28 2697 if (!vha->host)
1e99e33a 2698 return 1;
e315cd28 2699 if (time > vha->hw->loop_reset_delay * HZ)
1e99e33a
AV		 2700 return 1;
2701
e315cd28 2702 return atomic_read(&vha->loop_state) == LOOP_READY;
1e99e33a
AV		 2703}
2704
ec7193e2
QT		 2705static void qla2x00_iocb_work_fn(struct work_struct *work)
2706{
2707 struct scsi_qla_host *vha = container_of(work,
2708 struct scsi_qla_host, iocb_work);
9b3e0f4d
QT		 2709 struct qla_hw_data *ha = vha->hw;
2710 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
2711 int i = 20;
2712 unsigned long flags;
2713
2714 if (test_bit(UNLOADING, &base_vha->dpc_flags))
2715 return;
ec7193e2 2716
9b3e0f4d 2717 while (!list_empty(&vha->work_list) && i > 0) {
ec7193e2 2718 qla2x00_do_work(vha);
9b3e0f4d 2719 i--;
ec7193e2 2720 }
9b3e0f4d
QT		 2721
2722 spin_lock_irqsave(&vha->work_lock, flags);
2723 clear_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags);
2724 spin_unlock_irqrestore(&vha->work_lock, flags);
ec7193e2
QT		 2725}
2726
1da177e4
LT		 2727/*
2728 * PCI driver interface
2729 */
6f039790 2730static int
7ee61397 2731qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
1da177e4 2732{
a1541d5a 2733 int ret = -ENODEV;
1da177e4 2734 struct Scsi_Host *host;
e315cd28
AC		 2735 scsi_qla_host_t *base_vha = NULL;
2736 struct qla_hw_data *ha;
29856e28 2737 char pci_info[30];
7d613ac6 2738 char fw_str[30], wq_name[30];
5433383e 2739 struct scsi_host_template *sht;
642ef983 2740 int bars, mem_only = 0;
e315cd28 2741 uint16_t req_length = 0, rsp_length = 0;
73208dfd
AC		 2742 struct req_que *req = NULL;
2743 struct rsp_que *rsp = NULL;
5601236b 2744 int i;
d7459527 2745
285d0321 2746 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO);
a5326f86 2747 sht = &qla2xxx_driver_template;
5433383e 2748 if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 ||
8bc69e7d 2749 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 ||
4d4df193 2750 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 ||
8bc69e7d 2751 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 ||
c3a2f0df 2752 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 ||
3a03eb79 2753 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 ||
a9083016 2754 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 ||
6246b8a1
GM		 2755 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021 ||
2756 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2031 ||
8ae6d9c7 2757 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8031 ||
7ec0effd 2758 pdev->device == PCI_DEVICE_ID_QLOGIC_ISPF001 ||
f73cb695 2759 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8044 ||
2c5bbbb2 2760 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2071 ||
2b48992f
SC		 2761 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2271 ||
2762 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2261) {
285d0321 2763 bars = pci_select_bars(pdev, IORESOURCE_MEM);
09483916 2764 mem_only = 1;
7c3df132
SK		 2765 ql_dbg_pci(ql_dbg_init, pdev, 0x0007,
2766 "Mem only adapter.\n");
285d0321 2767 }
7c3df132
SK		 2768 ql_dbg_pci(ql_dbg_init, pdev, 0x0008,
2769 "Bars=%d.\n", bars);
285d0321 2770
09483916
BH		 2771 if (mem_only) {
2772 if (pci_enable_device_mem(pdev))
ddff7ed4 2773 return ret;
09483916
BH		 2774 } else {
2775 if (pci_enable_device(pdev))
ddff7ed4 2776 return ret;
09483916 2777 }
285d0321 2778
0927678f
JB		 2779 /* This may fail but that's ok */
2780 pci_enable_pcie_error_reporting(pdev);
285d0321 2781
e315cd28
AC		 2782 ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL);
2783 if (!ha) {
7c3df132
SK		 2784 ql_log_pci(ql_log_fatal, pdev, 0x0009,
2785 "Unable to allocate memory for ha.\n");
ddff7ed4 2786 goto disable_device;
1da177e4 2787 }
7c3df132
SK		 2788 ql_dbg_pci(ql_dbg_init, pdev, 0x000a,
2789 "Memory allocated for ha=%p.\n", ha);
e315cd28 2790 ha->pdev = pdev;
33e79977
QT		 2791 INIT_LIST_HEAD(&ha->tgt.q_full_list);
2792 spin_lock_init(&ha->tgt.q_full_lock);
7560151b 2793 spin_lock_init(&ha->tgt.sess_lock);
2f424b9b
QT		 2794 spin_lock_init(&ha->tgt.atio_lock);
2795
deeae7a6 2796 atomic_set(&ha->nvme_active_aen_cnt, 0);
1da177e4
LT		 2797
2798 /* Clear our data area */
285d0321 2799 ha->bars = bars;
09483916 2800 ha->mem_only = mem_only;
df4bf0bb 2801 spin_lock_init(&ha->hardware_lock);
339aa70e 2802 spin_lock_init(&ha->vport_slock);
a9b6f722 2803 mutex_init(&ha->selflogin_lock);
7a8ab9c8 2804 mutex_init(&ha->optrom_mutex);
1da177e4 2805
ea5b6382 2806 /* Set ISP-type information. */
2807 qla2x00_set_isp_flags(ha);
ca79cf66
DG		 2808
2809 /* Set EEH reset type to fundamental if required by hba */
95676112 2810 if (IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha) ||
f73cb695 2811 IS_QLA83XX(ha) || IS_QLA27XX(ha))
ca79cf66 2812 pdev->needs_freset = 1;
ca79cf66 2813
cba1e47f
CD		 2814 ha->prev_topology = 0;
2815 ha->init_cb_size = sizeof(init_cb_t);
2816 ha->link_data_rate = PORT_SPEED_UNKNOWN;
2817 ha->optrom_size = OPTROM_SIZE_2300;
d1e3635a 2818 ha->max_exchg = FW_MAX_EXCHANGES_CNT;
b2000805
QT		 2819 atomic_set(&ha->num_pend_mbx_stage1, 0);
2820 atomic_set(&ha->num_pend_mbx_stage2, 0);
2821 atomic_set(&ha->num_pend_mbx_stage3, 0);
cba1e47f 2822
abbd8870 2823 /* Assign ISP specific operations. */
1da177e4 2824 if (IS_QLA2100(ha)) {
642ef983 2825 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
1da177e4 2826 ha->mbx_count = MAILBOX_REGISTER_COUNT_2100;
e315cd28
AC		 2827 req_length = REQUEST_ENTRY_CNT_2100;
2828 rsp_length = RESPONSE_ENTRY_CNT_2100;
2829 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
abbd8870 2830 ha->gid_list_info_size = 4;
3a03eb79
AV		 2831 ha->flash_conf_off = ~0;
2832 ha->flash_data_off = ~0;
2833 ha->nvram_conf_off = ~0;
2834 ha->nvram_data_off = ~0;
fd34f556 2835 ha->isp_ops = &qla2100_isp_ops;
1da177e4 2836 } else if (IS_QLA2200(ha)) {
642ef983 2837 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
67ddda35 2838 ha->mbx_count = MAILBOX_REGISTER_COUNT_2200;
e315cd28
AC		 2839 req_length = REQUEST_ENTRY_CNT_2200;
2840 rsp_length = RESPONSE_ENTRY_CNT_2100;
2841 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
abbd8870 2842 ha->gid_list_info_size = 4;
3a03eb79
AV		 2843 ha->flash_conf_off = ~0;
2844 ha->flash_data_off = ~0;
2845 ha->nvram_conf_off = ~0;
2846 ha->nvram_data_off = ~0;
fd34f556 2847 ha->isp_ops = &qla2100_isp_ops;
fca29703 2848 } else if (IS_QLA23XX(ha)) {
642ef983 2849 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
1da177e4 2850 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2851 req_length = REQUEST_ENTRY_CNT_2200;
2852 rsp_length = RESPONSE_ENTRY_CNT_2300;
2853 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
abbd8870 2854 ha->gid_list_info_size = 6;
854165f4 2855 if (IS_QLA2322(ha) || IS_QLA6322(ha))
2856 ha->optrom_size = OPTROM_SIZE_2322;
3a03eb79
AV		 2857 ha->flash_conf_off = ~0;
2858 ha->flash_data_off = ~0;
2859 ha->nvram_conf_off = ~0;
2860 ha->nvram_data_off = ~0;
fd34f556 2861 ha->isp_ops = &qla2300_isp_ops;
4d4df193 2862 } else if (IS_QLA24XX_TYPE(ha)) {
642ef983 2863 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
fca29703 2864 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2865 req_length = REQUEST_ENTRY_CNT_24XX;
2866 rsp_length = RESPONSE_ENTRY_CNT_2300;
2d70c103 2867 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
e315cd28 2868 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2c3dfe3f 2869 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
fca29703 2870 ha->gid_list_info_size = 8;
854165f4 2871 ha->optrom_size = OPTROM_SIZE_24XX;
73208dfd 2872 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX;
fd34f556 2873 ha->isp_ops = &qla24xx_isp_ops;
3a03eb79
AV		 2874 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2875 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2876 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2877 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
c3a2f0df 2878 } else if (IS_QLA25XX(ha)) {
642ef983 2879 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
c3a2f0df 2880 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2881 req_length = REQUEST_ENTRY_CNT_24XX;
2882 rsp_length = RESPONSE_ENTRY_CNT_2300;
2d70c103 2883 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
e315cd28 2884 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
c3a2f0df 2885 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
c3a2f0df
AV		 2886 ha->gid_list_info_size = 8;
2887 ha->optrom_size = OPTROM_SIZE_25XX;
73208dfd 2888 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
c3a2f0df 2889 ha->isp_ops = &qla25xx_isp_ops;
3a03eb79
AV		 2890 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2891 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2892 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2893 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
2894 } else if (IS_QLA81XX(ha)) {
642ef983 2895 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3a03eb79
AV		 2896 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2897 req_length = REQUEST_ENTRY_CNT_24XX;
2898 rsp_length = RESPONSE_ENTRY_CNT_2300;
aa230bc5 2899 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
3a03eb79
AV		 2900 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2901 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2902 ha->gid_list_info_size = 8;
2903 ha->optrom_size = OPTROM_SIZE_81XX;
40859ae5 2904 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3a03eb79
AV		 2905 ha->isp_ops = &qla81xx_isp_ops;
2906 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2907 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2908 ha->nvram_conf_off = ~0;
2909 ha->nvram_data_off = ~0;
a9083016 2910 } else if (IS_QLA82XX(ha)) {
642ef983 2911 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
a9083016
GM		 2912 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2913 req_length = REQUEST_ENTRY_CNT_82XX;
2914 rsp_length = RESPONSE_ENTRY_CNT_82XX;
2915 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2916 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2917 ha->gid_list_info_size = 8;
2918 ha->optrom_size = OPTROM_SIZE_82XX;
087c621e 2919 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
a9083016
GM		 2920 ha->isp_ops = &qla82xx_isp_ops;
2921 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2922 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2923 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2924 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
7ec0effd
AD		 2925 } else if (IS_QLA8044(ha)) {
2926 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2927 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2928 req_length = REQUEST_ENTRY_CNT_82XX;
2929 rsp_length = RESPONSE_ENTRY_CNT_82XX;
2930 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2931 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2932 ha->gid_list_info_size = 8;
2933 ha->optrom_size = OPTROM_SIZE_83XX;
2934 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2935 ha->isp_ops = &qla8044_isp_ops;
2936 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2937 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2938 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2939 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
6246b8a1 2940 } else if (IS_QLA83XX(ha)) {
7d613ac6 2941 ha->portnum = PCI_FUNC(ha->pdev->devfn);
642ef983 2942 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
6246b8a1 2943 ha->mbx_count = MAILBOX_REGISTER_COUNT;
f2ea653f 2944 req_length = REQUEST_ENTRY_CNT_83XX;
e7b42e33 2945 rsp_length = RESPONSE_ENTRY_CNT_83XX;
b8aa4bdf 2946 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
6246b8a1
GM		 2947 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2948 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2949 ha->gid_list_info_size = 8;
2950 ha->optrom_size = OPTROM_SIZE_83XX;
2951 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2952 ha->isp_ops = &qla83xx_isp_ops;
2953 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2954 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2955 ha->nvram_conf_off = ~0;
2956 ha->nvram_data_off = ~0;
8ae6d9c7
GM		 2957 } else if (IS_QLAFX00(ha)) {
2958 ha->max_fibre_devices = MAX_FIBRE_DEVICES_FX00;
2959 ha->mbx_count = MAILBOX_REGISTER_COUNT_FX00;
2960 ha->aen_mbx_count = AEN_MAILBOX_REGISTER_COUNT_FX00;
2961 req_length = REQUEST_ENTRY_CNT_FX00;
2962 rsp_length = RESPONSE_ENTRY_CNT_FX00;
8ae6d9c7
GM		 2963 ha->isp_ops = &qlafx00_isp_ops;
2964 ha->port_down_retry_count = 30; /* default value */
2965 ha->mr.fw_hbt_cnt = QLAFX00_HEARTBEAT_INTERVAL;
2966 ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL;
71e56003 2967 ha->mr.fw_critemp_timer_tick = QLAFX00_CRITEMP_INTERVAL;
8ae6d9c7 2968 ha->mr.fw_hbt_en = 1;
e8f5e95d
AB		 2969 ha->mr.host_info_resend = false;
2970 ha->mr.hinfo_resend_timer_tick = QLAFX00_HINFO_RESEND_INTERVAL;
f73cb695
CD		 2971 } else if (IS_QLA27XX(ha)) {
2972 ha->portnum = PCI_FUNC(ha->pdev->devfn);
2973 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2974 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e7b42e33
QT		 2975 req_length = REQUEST_ENTRY_CNT_83XX;
2976 rsp_length = RESPONSE_ENTRY_CNT_83XX;
b20f02e1 2977 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
f73cb695
CD		 2978 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2979 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2980 ha->gid_list_info_size = 8;
2981 ha->optrom_size = OPTROM_SIZE_83XX;
2982 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2983 ha->isp_ops = &qla27xx_isp_ops;
2984 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2985 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2986 ha->nvram_conf_off = ~0;
2987 ha->nvram_data_off = ~0;
1da177e4 2988 }
6246b8a1 2989
7c3df132
SK		 2990 ql_dbg_pci(ql_dbg_init, pdev, 0x001e,
2991 "mbx_count=%d, req_length=%d, "
2992 "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, "
642ef983
CD		 2993 "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, "
2994 "max_fibre_devices=%d.\n",
7c3df132
SK		 2995 ha->mbx_count, req_length, rsp_length, ha->max_loop_id,
2996 ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size,
642ef983 2997 ha->nvram_npiv_size, ha->max_fibre_devices);
7c3df132
SK		 2998 ql_dbg_pci(ql_dbg_init, pdev, 0x001f,
2999 "isp_ops=%p, flash_conf_off=%d, "
3000 "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n",
3001 ha->isp_ops, ha->flash_conf_off, ha->flash_data_off,
3002 ha->nvram_conf_off, ha->nvram_data_off);
706f457d
GM		 3003
3004 /* Configure PCI I/O space */
3005 ret = ha->isp_ops->iospace_config(ha);
3006 if (ret)
0a63ad12 3007 goto iospace_config_failed;
706f457d
GM		 3008
3009 ql_log_pci(ql_log_info, pdev, 0x001d,
3010 "Found an ISP%04X irq %d iobase 0x%p.\n",
3011 pdev->device, pdev->irq, ha->iobase);
6c2f527c 3012 mutex_init(&ha->vport_lock);
d7459527 3013 mutex_init(&ha->mq_lock);
0b05a1f0
MB		 3014 init_completion(&ha->mbx_cmd_comp);
3015 complete(&ha->mbx_cmd_comp);
3016 init_completion(&ha->mbx_intr_comp);
23f2ebd1 3017 init_completion(&ha->dcbx_comp);
f356bef1 3018 init_completion(&ha->lb_portup_comp);
1da177e4 3019
2c3dfe3f 3020 set_bit(0, (unsigned long *) ha->vp_idx_map);
1da177e4 3021
53303c42 3022 qla2x00_config_dma_addressing(ha);
7c3df132
SK		 3023 ql_dbg_pci(ql_dbg_init, pdev, 0x0020,
3024 "64 Bit addressing is %s.\n",
3025 ha->flags.enable_64bit_addressing ? "enable" :
3026 "disable");
73208dfd 3027 ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp);
b2a72ec3 3028 if (ret) {
7c3df132
SK		 3029 ql_log_pci(ql_log_fatal, pdev, 0x0031,
3030 "Failed to allocate memory for adapter, aborting.\n");
1da177e4 3031
e315cd28
AC		 3032 goto probe_hw_failed;
3033 }
3034
73208dfd 3035 req->max_q_depth = MAX_Q_DEPTH;
e315cd28 3036 if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU)
73208dfd
AC		 3037 req->max_q_depth = ql2xmaxqdepth;
3038
e315cd28
AC		 3039
3040 base_vha = qla2x00_create_host(sht, ha);
3041 if (!base_vha) {
a1541d5a 3042 ret = -ENOMEM;
e315cd28 3043 goto probe_hw_failed;
1da177e4
LT		 3044 }
3045
e315cd28 3046 pci_set_drvdata(pdev, base_vha);
6b383979 3047 set_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags);
e315cd28 3048
e315cd28 3049 host = base_vha->host;
2afa19a9 3050 base_vha->req = req;
73208dfd 3051 if (IS_QLA2XXX_MIDTYPE(ha))
f6602f3b
QT		 3052 base_vha->mgmt_svr_loop_id =
3053 qla2x00_reserve_mgmt_server_loop_id(base_vha);
73208dfd 3054 else
e315cd28
AC		 3055 base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER +
3056 base_vha->vp_idx;
58548cb5 3057
8ae6d9c7
GM		 3058 /* Setup fcport template structure. */
3059 ha->mr.fcport.vha = base_vha;
3060 ha->mr.fcport.port_type = FCT_UNKNOWN;
3061 ha->mr.fcport.loop_id = FC_NO_LOOP_ID;
3062 qla2x00_set_fcport_state(&ha->mr.fcport, FCS_UNCONFIGURED);
3063 ha->mr.fcport.supported_classes = FC_COS_UNSPECIFIED;
3064 ha->mr.fcport.scan_state = 1;
3065
58548cb5
GM		 3066 /* Set the SG table size based on ISP type */
3067 if (!IS_FWI2_CAPABLE(ha)) {
3068 if (IS_QLA2100(ha))
3069 host->sg_tablesize = 32;
3070 } else {
3071 if (!IS_QLA82XX(ha))
3072 host->sg_tablesize = QLA_SG_ALL;
3073 }
642ef983 3074 host->max_id = ha->max_fibre_devices;
e315cd28
AC		 3075 host->cmd_per_lun = 3;
3076 host->unique_id = host->host_no;
e02587d7 3077 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif)
0c470874
AE		 3078 host->max_cmd_len = 32;
3079 else
3080 host->max_cmd_len = MAX_CMDSZ;
e315cd28 3081 host->max_channel = MAX_BUSES - 1;
755f516b
HR		 3082 /* Older HBAs support only 16-bit LUNs */
3083 if (!IS_QLAFX00(ha) && !IS_FWI2_CAPABLE(ha) &&
3084 ql2xmaxlun > 0xffff)
3085 host->max_lun = 0xffff;
3086 else
3087 host->max_lun = ql2xmaxlun;
e315cd28 3088 host->transportt = qla2xxx_transport_template;
9a069e19 3089 sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC);
e315cd28 3090
7c3df132
SK		 3091 ql_dbg(ql_dbg_init, base_vha, 0x0033,
3092 "max_id=%d this_id=%d "
3093 "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d "
1abf635d 3094 "max_lun=%llu transportt=%p, vendor_id=%llu.\n", host->max_id,
7c3df132
SK		 3095 host->this_id, host->cmd_per_lun, host->unique_id,
3096 host->max_cmd_len, host->max_channel, host->max_lun,
3097 host->transportt, sht->vendor_id);
3098
1010f21e
HM		 3099 INIT_WORK(&base_vha->iocb_work, qla2x00_iocb_work_fn);
3100
d7459527
MH		 3101 /* Set up the irqs */
3102 ret = qla2x00_request_irqs(ha, rsp);
3103 if (ret)
6a2cf8d3 3104 goto probe_failed;
d7459527 3105
9a347ff4 3106 /* Alloc arrays of request and response ring ptrs */
6d634067
BK		 3107 ret = qla2x00_alloc_queues(ha, req, rsp);
3108 if (ret) {
9a347ff4
CD		 3109 ql_log(ql_log_fatal, base_vha, 0x003d,
3110 "Failed to allocate memory for queue pointers..."
3111 "aborting.\n");
6a2cf8d3 3112 goto probe_failed;
9a347ff4
CD		 3113 }
3114
5601236b
MH		 3115 if (ha->mqenable && shost_use_blk_mq(host)) {
3116 /* number of hardware queues supported by blk/scsi-mq*/
3117 host->nr_hw_queues = ha->max_qpairs;
3118
3119 ql_dbg(ql_dbg_init, base_vha, 0x0192,
3120 "blk/scsi-mq enabled, HW queues = %d.\n", host->nr_hw_queues);
c38d1baf
HM		 3121 } else {
3122 if (ql2xnvmeenable) {
3123 host->nr_hw_queues = ha->max_qpairs;
3124 ql_dbg(ql_dbg_init, base_vha, 0x0194,
3125 "FC-NVMe support is enabled, HW queues=%d\n",
3126 host->nr_hw_queues);
3127 } else {
3128 ql_dbg(ql_dbg_init, base_vha, 0x0193,
3129 "blk/scsi-mq disabled.\n");
3130 }
3131 }
5601236b 3132
2d70c103 3133 qlt_probe_one_stage1(base_vha, ha);
9a347ff4 3134
90a86fc0
JC		 3135 pci_save_state(pdev);
3136
9a347ff4 3137 /* Assign back pointers */
2afa19a9
AC		 3138 rsp->req = req;
3139 req->rsp = rsp;
9a347ff4 3140
8ae6d9c7
GM		 3141 if (IS_QLAFX00(ha)) {
3142 ha->rsp_q_map[0] = rsp;
3143 ha->req_q_map[0] = req;
3144 set_bit(0, ha->req_qid_map);
3145 set_bit(0, ha->rsp_qid_map);
3146 }
3147
08029990
AV		 3148 /* FWI2-capable only. */
3149 req->req_q_in = &ha->iobase->isp24.req_q_in;
3150 req->req_q_out = &ha->iobase->isp24.req_q_out;
3151 rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in;
3152 rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out;
f73cb695 3153 if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
08029990
AV		 3154 req->req_q_in = &ha->mqiobase->isp25mq.req_q_in;
3155 req->req_q_out = &ha->mqiobase->isp25mq.req_q_out;
3156 rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in;
3157 rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out;
17d98630
AC		 3158 }
3159
8ae6d9c7
GM		 3160 if (IS_QLAFX00(ha)) {
3161 req->req_q_in = &ha->iobase->ispfx00.req_q_in;
3162 req->req_q_out = &ha->iobase->ispfx00.req_q_out;
3163 rsp->rsp_q_in = &ha->iobase->ispfx00.rsp_q_in;
3164 rsp->rsp_q_out = &ha->iobase->ispfx00.rsp_q_out;
3165 }
3166
7ec0effd 3167 if (IS_P3P_TYPE(ha)) {
a9083016
GM		 3168 req->req_q_out = &ha->iobase->isp82.req_q_out[0];
3169 rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0];
3170 rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0];
3171 }
3172
7c3df132
SK		 3173 ql_dbg(ql_dbg_multiq, base_vha, 0xc009,
3174 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
3175 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
3176 ql_dbg(ql_dbg_multiq, base_vha, 0xc00a,
3177 "req->req_q_in=%p req->req_q_out=%p "
3178 "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
3179 req->req_q_in, req->req_q_out,
3180 rsp->rsp_q_in, rsp->rsp_q_out);
3181 ql_dbg(ql_dbg_init, base_vha, 0x003e,
3182 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
3183 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
3184 ql_dbg(ql_dbg_init, base_vha, 0x003f,
3185 "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
3186 req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out);
1da177e4 3187
d48cc67c 3188 ha->wq = alloc_workqueue("qla2xxx_wq", 0, 0);
3189
8ae6d9c7 3190 if (ha->isp_ops->initialize_adapter(base_vha)) {
7c3df132
SK		 3191 ql_log(ql_log_fatal, base_vha, 0x00d6,
3192 "Failed to initialize adapter - Adapter flags %x.\n",
3193 base_vha->device_flags);
1da177e4 3194
a9083016
GM		 3195 if (IS_QLA82XX(ha)) {
3196 qla82xx_idc_lock(ha);
3197 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 3198 QLA8XXX_DEV_FAILED);
a9083016 3199 qla82xx_idc_unlock(ha);
7c3df132
SK		 3200 ql_log(ql_log_fatal, base_vha, 0x00d7,
3201 "HW State: FAILED.\n");
7ec0effd
AD		 3202 } else if (IS_QLA8044(ha)) {
3203 qla8044_idc_lock(ha);
3204 qla8044_wr_direct(base_vha,
3205 QLA8044_CRB_DEV_STATE_INDEX,
3206 QLA8XXX_DEV_FAILED);
3207 qla8044_idc_unlock(ha);
3208 ql_log(ql_log_fatal, base_vha, 0x0150,
3209 "HW State: FAILED.\n");
a9083016
GM		 3210 }
3211
a1541d5a 3212 ret = -ENODEV;
1da177e4
LT		 3213 goto probe_failed;
3214 }
3215
3b1bef64
CD		 3216 if (IS_QLAFX00(ha))
3217 host->can_queue = QLAFX00_MAX_CANQUEUE;
3218 else
3219 host->can_queue = req->num_outstanding_cmds - 10;
3220
3221 ql_dbg(ql_dbg_init, base_vha, 0x0032,
3222 "can_queue=%d, req=%p, mgmt_svr_loop_id=%d, sg_tablesize=%d.\n",
3223 host->can_queue, base_vha->req,
3224 base_vha->mgmt_svr_loop_id, host->sg_tablesize);
3225
e326d22a
QT		 3226 if (ha->mqenable) {
3227 bool mq = false;
3228 bool startit = false;
e326d22a
QT		 3229
3230 if (QLA_TGT_MODE_ENABLED()) {
3231 mq = true;
3232 startit = false;
3233 }
3234
3235 if ((ql2x_ini_mode == QLA2XXX_INI_MODE_ENABLED) &&
3236 shost_use_blk_mq(host)) {
3237 mq = true;
3238 startit = true;
3239 }
3240
3241 if (mq) {
3242 /* Create start of day qpairs for Block MQ */
5601236b 3243 for (i = 0; i < ha->max_qpairs; i++)
e326d22a 3244 qla2xxx_create_qpair(base_vha, 5, 0, startit);
5601236b
MH		 3245 }
3246 }
68ca949c 3247
cbc8eb67
AV		 3248 if (ha->flags.running_gold_fw)
3249 goto skip_dpc;
3250
1da177e4
LT		 3251 /*
3252 * Startup the kernel thread for this host adapter
3253 */
39a11240 3254 ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha,
7c3df132 3255 "%s_dpc", base_vha->host_str);
39a11240 3256 if (IS_ERR(ha->dpc_thread)) {
7c3df132
SK		 3257 ql_log(ql_log_fatal, base_vha, 0x00ed,
3258 "Failed to start DPC thread.\n");
39a11240 3259 ret = PTR_ERR(ha->dpc_thread);
e2532b4a 3260 ha->dpc_thread = NULL;
1da177e4
LT		 3261 goto probe_failed;
3262 }
7c3df132
SK		 3263 ql_dbg(ql_dbg_init, base_vha, 0x00ee,
3264 "DPC thread started successfully.\n");
1da177e4 3265
2d70c103
NB		 3266 /*
3267 * If we're not coming up in initiator mode, we might sit for
3268 * a while without waking up the dpc thread, which leads to a
3269 * stuck process warning. So just kick the dpc once here and
3270 * let the kthread start (and go back to sleep in qla2x00_do_dpc).
3271 */
3272 qla2xxx_wake_dpc(base_vha);
3273
f3ddac19
CD		 3274 INIT_WORK(&ha->board_disable, qla2x00_disable_board_on_pci_error);
3275
81178772
SK		 3276 if (IS_QLA8031(ha) || IS_MCTP_CAPABLE(ha)) {
3277 sprintf(wq_name, "qla2xxx_%lu_dpc_lp_wq", base_vha->host_no);
3278 ha->dpc_lp_wq = create_singlethread_workqueue(wq_name);
3279 INIT_WORK(&ha->idc_aen, qla83xx_service_idc_aen);
3280
3281 sprintf(wq_name, "qla2xxx_%lu_dpc_hp_wq", base_vha->host_no);
3282 ha->dpc_hp_wq = create_singlethread_workqueue(wq_name);
3283 INIT_WORK(&ha->nic_core_reset, qla83xx_nic_core_reset_work);
3284 INIT_WORK(&ha->idc_state_handler,
3285 qla83xx_idc_state_handler_work);
3286 INIT_WORK(&ha->nic_core_unrecoverable,
3287 qla83xx_nic_core_unrecoverable_work);
3288 }
3289
cbc8eb67 3290skip_dpc:
e315cd28
AC		 3291 list_add_tail(&base_vha->list, &ha->vp_list);
3292 base_vha->host->irq = ha->pdev->irq;
1da177e4
LT		 3293
3294 /* Initialized the timer */
8e5f4ba0 3295 qla2x00_start_timer(base_vha, WATCH_INTERVAL);
7c3df132
SK		 3296 ql_dbg(ql_dbg_init, base_vha, 0x00ef,
3297 "Started qla2x00_timer with "
3298 "interval=%d.\n", WATCH_INTERVAL);
3299 ql_dbg(ql_dbg_init, base_vha, 0x00f0,
3300 "Detected hba at address=%p.\n",
3301 ha);
d19044c3 3302
e02587d7 3303 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) {
bad75002 3304 if (ha->fw_attributes & BIT_4) {
9e522cd8 3305 int prot = 0, guard;
bad75002 3306 base_vha->flags.difdix_supported = 1;
7c3df132
SK		 3307 ql_dbg(ql_dbg_init, base_vha, 0x00f1,
3308 "Registering for DIF/DIX type 1 and 3 protection.\n");
8cb2049c
AE		 3309 if (ql2xenabledif == 1)
3310 prot = SHOST_DIX_TYPE0_PROTECTION;
bad75002 3311 scsi_host_set_prot(host,
8cb2049c 3312 prot | SHOST_DIF_TYPE1_PROTECTION
0c470874 3313 | SHOST_DIF_TYPE2_PROTECTION
bad75002
AE		 3314 | SHOST_DIF_TYPE3_PROTECTION
3315 | SHOST_DIX_TYPE1_PROTECTION
0c470874 3316 | SHOST_DIX_TYPE2_PROTECTION
bad75002 3317 | SHOST_DIX_TYPE3_PROTECTION);
9e522cd8
AE		 3318
3319 guard = SHOST_DIX_GUARD_CRC;
3320
3321 if (IS_PI_IPGUARD_CAPABLE(ha) &&
3322 (ql2xenabledif > 1 || IS_PI_DIFB_DIX0_CAPABLE(ha)))
3323 guard |= SHOST_DIX_GUARD_IP;
3324
3325 scsi_host_set_guard(host, guard);
bad75002
AE		 3326 } else
3327 base_vha->flags.difdix_supported = 0;
3328 }
3329
a9083016
GM		 3330 ha->isp_ops->enable_intrs(ha);
3331
1fe19ee4
AB		 3332 if (IS_QLAFX00(ha)) {
3333 ret = qlafx00_fx_disc(base_vha,
3334 &base_vha->hw->mr.fcport, FXDISC_GET_CONFIG_INFO);
3335 host->sg_tablesize = (ha->mr.extended_io_enabled) ?
3336 QLA_SG_ALL : 128;
3337 }
3338
a1541d5a
AV		 3339 ret = scsi_add_host(host, &pdev->dev);
3340 if (ret)
3341 goto probe_failed;
3342
1486400f
MR		 3343 base_vha->flags.init_done = 1;
3344 base_vha->flags.online = 1;
edaa5c74 3345 ha->prev_minidump_failed = 0;
1486400f 3346
7c3df132
SK		 3347 ql_dbg(ql_dbg_init, base_vha, 0x00f2,
3348 "Init done and hba is online.\n");
3349
726b8548
QT		 3350 if (qla_ini_mode_enabled(base_vha) ||
3351 qla_dual_mode_enabled(base_vha))
2d70c103
NB		 3352 scsi_scan_host(host);
3353 else
3354 ql_dbg(ql_dbg_init, base_vha, 0x0122,
3355 "skipping scsi_scan_host() for non-initiator port\n");
1e99e33a 3356
e315cd28 3357 qla2x00_alloc_sysfs_attr(base_vha);
a1541d5a 3358
8ae6d9c7 3359 if (IS_QLAFX00(ha)) {
8ae6d9c7
GM		 3360 ret = qlafx00_fx_disc(base_vha,
3361 &base_vha->hw->mr.fcport, FXDISC_GET_PORT_INFO);
3362
3363 /* Register system information */
3364 ret = qlafx00_fx_disc(base_vha,
3365 &base_vha->hw->mr.fcport, FXDISC_REG_HOST_INFO);
3366 }
3367
e315cd28 3368 qla2x00_init_host_attr(base_vha);
a1541d5a 3369
e315cd28 3370 qla2x00_dfs_setup(base_vha);
df613b96 3371
03eb912a
AB		 3372 ql_log(ql_log_info, base_vha, 0x00fb,
3373 "QLogic %s - %s.\n", ha->model_number, ha->model_desc);
7c3df132
SK		 3374 ql_log(ql_log_info, base_vha, 0x00fc,
3375 "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n",
3376 pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info),
3377 pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-',
3378 base_vha->host_no,
df57caba 3379 ha->isp_ops->fw_version_str(base_vha, fw_str, sizeof(fw_str)));
1da177e4 3380
2d70c103
NB		 3381 qlt_add_target(ha, base_vha);
3382
6b383979 3383 clear_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags);
a29b3dd7
JC		 3384
3385 if (test_bit(UNLOADING, &base_vha->dpc_flags))
3386 return -ENODEV;
3387
e4e3a2ce
QT		 3388 if (ha->flags.detected_lr_sfp) {
3389 ql_log(ql_log_info, base_vha, 0xffff,
3390 "Reset chip to pick up LR SFP setting\n");
3391 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
3392 qla2xxx_wake_dpc(base_vha);
3393 }
3394
1da177e4
LT		 3395 return 0;
3396
3397probe_failed:
b9978769
AV		 3398 if (base_vha->timer_active)
3399 qla2x00_stop_timer(base_vha);
3400 base_vha->flags.online = 0;
3401 if (ha->dpc_thread) {
3402 struct task_struct *t = ha->dpc_thread;
3403
3404 ha->dpc_thread = NULL;
3405 kthread_stop(t);
3406 }
3407
e315cd28 3408 qla2x00_free_device(base_vha);
e315cd28 3409 scsi_host_put(base_vha->host);
6d634067
BK		 3410 /*
3411 * Need to NULL out local req/rsp after
3412 * qla2x00_free_device => qla2x00_free_queues frees
3413 * what these are pointing to. Or else we'll
3414 * fall over below in qla2x00_free_req/rsp_que.
3415 */
3416 req = NULL;
3417 rsp = NULL;
1da177e4 3418
e315cd28 3419probe_hw_failed:
d64d6c56 3420 qla2x00_mem_free(ha);
3421 qla2x00_free_req_que(ha, req);
3422 qla2x00_free_rsp_que(ha, rsp);
1a2fbf18
JL		 3423 qla2x00_clear_drv_active(ha);
3424
0a63ad12 3425iospace_config_failed:
7ec0effd 3426 if (IS_P3P_TYPE(ha)) {
0a63ad12 3427 if (!ha->nx_pcibase)
f73cb695 3428 iounmap((device_reg_t *)ha->nx_pcibase);
a9083016 3429 if (!ql2xdbwr)
f73cb695 3430 iounmap((device_reg_t *)ha->nxdb_wr_ptr);
a9083016
GM		 3431 } else {
3432 if (ha->iobase)
3433 iounmap(ha->iobase);
8ae6d9c7
GM		 3434 if (ha->cregbase)
3435 iounmap(ha->cregbase);
a9083016 3436 }
e315cd28
AC		 3437 pci_release_selected_regions(ha->pdev, ha->bars);
3438 kfree(ha);
1da177e4 3439
ddff7ed4 3440disable_device:
e315cd28 3441 pci_disable_device(pdev);
a1541d5a 3442 return ret;
1da177e4 3443}
1da177e4 3444
e30d1756
MI		 3445static void
3446qla2x00_shutdown(struct pci_dev *pdev)
3447{
3448 scsi_qla_host_t *vha;
3449 struct qla_hw_data *ha;
3450
3451 vha = pci_get_drvdata(pdev);
3452 ha = vha->hw;
3453
efdb5760
SC		 3454 ql_log(ql_log_info, vha, 0xfffa,
3455 "Adapter shutdown\n");
3456
3457 /*
3458 * Prevent future board_disable and wait
3459 * until any pending board_disable has completed.
3460 */
3461 set_bit(PFLG_DRIVER_REMOVING, &vha->pci_flags);
3462 cancel_work_sync(&ha->board_disable);
3463
3464 if (!atomic_read(&pdev->enable_cnt))
3465 return;
3466
42479343
AB		 3467 /* Notify ISPFX00 firmware */
3468 if (IS_QLAFX00(ha))
3469 qlafx00_driver_shutdown(vha, 20);
3470
e30d1756
MI		 3471 /* Turn-off FCE trace */
3472 if (ha->flags.fce_enabled) {
3473 qla2x00_disable_fce_trace(vha, NULL, NULL);
3474 ha->flags.fce_enabled = 0;
3475 }
3476
3477 /* Turn-off EFT trace */
3478 if (ha->eft)
3479 qla2x00_disable_eft_trace(vha);
3480
3407fc37
QT		 3481 if (IS_QLA25XX(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha)) {
3482 if (ha->flags.fw_started)
3483 qla2x00_abort_isp_cleanup(vha);
3484 } else {
3485 /* Stop currently executing firmware. */
3486 qla2x00_try_to_stop_firmware(vha);
3487 }
e30d1756
MI		 3488
3489 /* Turn adapter off line */
3490 vha->flags.online = 0;
3491
3492 /* turn-off interrupts on the card */
3493 if (ha->interrupts_on) {
3494 vha->flags.init_done = 0;
3495 ha->isp_ops->disable_intrs(ha);
3496 }
3497
3498 qla2x00_free_irqs(vha);
3499
3500 qla2x00_free_fw_dump(ha);
61d41f61 3501
61d41f61 3502 pci_disable_device(pdev);
efdb5760
SC		 3503 ql_log(ql_log_info, vha, 0xfffe,
3504 "Adapter shutdown successfully.\n");
e30d1756
MI		 3505}
3506
fe1b806f 3507/* Deletes all the virtual ports for a given ha */
4c993f76 3508static void
fe1b806f 3509qla2x00_delete_all_vps(struct qla_hw_data *ha, scsi_qla_host_t *base_vha)
1da177e4 3510{
fe1b806f 3511 scsi_qla_host_t *vha;
feafb7b1 3512 unsigned long flags;
e315cd28 3513
43ebf16d
AE		 3514 mutex_lock(&ha->vport_lock);
3515 while (ha->cur_vport_count) {
43ebf16d 3516 spin_lock_irqsave(&ha->vport_slock, flags);
feafb7b1 3517
43ebf16d
AE		 3518 BUG_ON(base_vha->list.next == &ha->vp_list);
3519 /* This assumes first entry in ha->vp_list is always base vha */
3520 vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list);
52c82823 3521 scsi_host_get(vha->host);
feafb7b1 3522
43ebf16d
AE		 3523 spin_unlock_irqrestore(&ha->vport_slock, flags);
3524 mutex_unlock(&ha->vport_lock);
3525
3526 fc_vport_terminate(vha->fc_vport);
3527 scsi_host_put(vha->host);
feafb7b1 3528
43ebf16d 3529 mutex_lock(&ha->vport_lock);
e315cd28 3530 }
43ebf16d 3531 mutex_unlock(&ha->vport_lock);
fe1b806f 3532}
1da177e4 3533
fe1b806f
CD		 3534/* Stops all deferred work threads */
3535static void
3536qla2x00_destroy_deferred_work(struct qla_hw_data *ha)
3537{
7d613ac6
SV		 3538 /* Cancel all work and destroy DPC workqueues */
3539 if (ha->dpc_lp_wq) {
3540 cancel_work_sync(&ha->idc_aen);
3541 destroy_workqueue(ha->dpc_lp_wq);
3542 ha->dpc_lp_wq = NULL;
3543 }
3544
3545 if (ha->dpc_hp_wq) {
3546 cancel_work_sync(&ha->nic_core_reset);
3547 cancel_work_sync(&ha->idc_state_handler);
3548 cancel_work_sync(&ha->nic_core_unrecoverable);
3549 destroy_workqueue(ha->dpc_hp_wq);
3550 ha->dpc_hp_wq = NULL;
3551 }
3552
b9978769
AV		 3553 /* Kill the kernel thread for this host */
3554 if (ha->dpc_thread) {
3555 struct task_struct *t = ha->dpc_thread;
3556
3557 /*
3558 * qla2xxx_wake_dpc checks for ->dpc_thread
3559 * so we need to zero it out.
3560 */
3561 ha->dpc_thread = NULL;
3562 kthread_stop(t);
3563 }
fe1b806f 3564}
1da177e4 3565
fe1b806f
CD		 3566static void
3567qla2x00_unmap_iobases(struct qla_hw_data *ha)
3568{
a9083016 3569 if (IS_QLA82XX(ha)) {
b963752f 3570
f73cb695 3571 iounmap((device_reg_t *)ha->nx_pcibase);
a9083016 3572 if (!ql2xdbwr)
f73cb695 3573 iounmap((device_reg_t *)ha->nxdb_wr_ptr);
a9083016
GM		 3574 } else {
3575 if (ha->iobase)
3576 iounmap(ha->iobase);
1da177e4 3577
8ae6d9c7
GM		 3578 if (ha->cregbase)
3579 iounmap(ha->cregbase);
3580
a9083016
GM		 3581 if (ha->mqiobase)
3582 iounmap(ha->mqiobase);
6246b8a1 3583
f73cb695 3584 if ((IS_QLA83XX(ha) || IS_QLA27XX(ha)) && ha->msixbase)
6246b8a1 3585 iounmap(ha->msixbase);
a9083016 3586 }
fe1b806f
CD		 3587}
3588
3589static void
db7157d4 3590qla2x00_clear_drv_active(struct qla_hw_data *ha)
fe1b806f 3591{
fe1b806f
CD		 3592 if (IS_QLA8044(ha)) {
3593 qla8044_idc_lock(ha);
c41afc9a 3594 qla8044_clear_drv_active(ha);
fe1b806f
CD		 3595 qla8044_idc_unlock(ha);
3596 } else if (IS_QLA82XX(ha)) {
3597 qla82xx_idc_lock(ha);
3598 qla82xx_clear_drv_active(ha);
3599 qla82xx_idc_unlock(ha);
3600 }
3601}
3602
3603static void
3604qla2x00_remove_one(struct pci_dev *pdev)
3605{
3606 scsi_qla_host_t *base_vha;
3607 struct qla_hw_data *ha;
3608
beb9e315
JL		 3609 base_vha = pci_get_drvdata(pdev);
3610 ha = base_vha->hw;
45235022
QT		 3611 ql_log(ql_log_info, base_vha, 0xb079,
3612 "Removing driver\n");
beb9e315
JL		 3613
3614 /* Indicate device removal to prevent future board_disable and wait
3615 * until any pending board_disable has completed. */
3616 set_bit(PFLG_DRIVER_REMOVING, &base_vha->pci_flags);
3617 cancel_work_sync(&ha->board_disable);
3618
fe1b806f 3619 /*
beb9e315
JL		 3620 * If the PCI device is disabled then there was a PCI-disconnect and
3621 * qla2x00_disable_board_on_pci_error has taken care of most of the
3622 * resources.
fe1b806f 3623 */
beb9e315 3624 if (!atomic_read(&pdev->enable_cnt)) {
726b8548
QT		 3625 dma_free_coherent(&ha->pdev->dev, base_vha->gnl.size,
3626 base_vha->gnl.l, base_vha->gnl.ldma);
3627
beb9e315
JL		 3628 scsi_host_put(base_vha->host);
3629 kfree(ha);
3630 pci_set_drvdata(pdev, NULL);
fe1b806f 3631 return;
beb9e315 3632 }
638a1a01
SC		 3633 qla2x00_wait_for_hba_ready(base_vha);
3634
45235022
QT		 3635 if (IS_QLA25XX(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha)) {
3636 if (ha->flags.fw_started)
3637 qla2x00_abort_isp_cleanup(base_vha);
3638 } else if (!IS_QLAFX00(ha)) {
3639 if (IS_QLA8031(ha)) {
3640 ql_dbg(ql_dbg_p3p, base_vha, 0xb07e,
3641 "Clearing fcoe driver presence.\n");
3642 if (qla83xx_clear_drv_presence(base_vha) != QLA_SUCCESS)
3643 ql_dbg(ql_dbg_p3p, base_vha, 0xb079,
3644 "Error while clearing DRV-Presence.\n");
3645 }
3646
3647 qla2x00_try_to_stop_firmware(base_vha);
3648 }
3649
2ce87cc5
QT		 3650 qla2x00_wait_for_sess_deletion(base_vha);
3651
726b8548
QT		 3652 /*
3653 * if UNLOAD flag is already set, then continue unload,
783e0dc4
SC		 3654 * where it was set first.
3655 */
3656 if (test_bit(UNLOADING, &base_vha->dpc_flags))
3657 return;
3658
fe1b806f 3659 set_bit(UNLOADING, &base_vha->dpc_flags);
e84067d7
DG		 3660
3661 qla_nvme_delete(base_vha);
3662
726b8548
QT		 3663 dma_free_coherent(&ha->pdev->dev,
3664 base_vha->gnl.size, base_vha->gnl.l, base_vha->gnl.ldma);
fe1b806f 3665
a4239945
QT		 3666 vfree(base_vha->scan.l);
3667
fe1b806f
CD		 3668 if (IS_QLAFX00(ha))
3669 qlafx00_driver_shutdown(base_vha, 20);
3670
3671 qla2x00_delete_all_vps(ha, base_vha);
3672
fe1b806f
CD		 3673 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
3674
3675 qla2x00_dfs_remove(base_vha);
3676
3677 qla84xx_put_chip(base_vha);
3678
3679 /* Disable timer */
3680 if (base_vha->timer_active)
3681 qla2x00_stop_timer(base_vha);
3682
3683 base_vha->flags.online = 0;
3684
b0d6cabd
HM		 3685 /* free DMA memory */
3686 if (ha->exlogin_buf)
3687 qla2x00_free_exlogin_buffer(ha);
3688
2f56a7f1
HM		 3689 /* free DMA memory */
3690 if (ha->exchoffld_buf)
3691 qla2x00_free_exchoffld_buffer(ha);
3692
fe1b806f
CD		 3693 qla2x00_destroy_deferred_work(ha);
3694
3695 qlt_remove_target(ha, base_vha);
3696
3697 qla2x00_free_sysfs_attr(base_vha, true);
3698
3699 fc_remove_host(base_vha->host);
482c9dc7 3700 qlt_remove_target_resources(ha);
fe1b806f
CD		 3701
3702 scsi_remove_host(base_vha->host);
3703
3704 qla2x00_free_device(base_vha);
3705
db7157d4 3706 qla2x00_clear_drv_active(ha);
fe1b806f 3707
d2749ffa
AE		 3708 scsi_host_put(base_vha->host);
3709
fe1b806f 3710 qla2x00_unmap_iobases(ha);
73208dfd 3711
e315cd28
AC		 3712 pci_release_selected_regions(ha->pdev, ha->bars);
3713 kfree(ha);
1da177e4 3714
90a86fc0
JC		 3715 pci_disable_pcie_error_reporting(pdev);
3716
665db93b 3717 pci_disable_device(pdev);
1da177e4 3718}
1da177e4
LT		 3719
3720static void
e315cd28 3721qla2x00_free_device(scsi_qla_host_t *vha)
1da177e4 3722{
e315cd28 3723 struct qla_hw_data *ha = vha->hw;
1da177e4 3724
85880801
AV		 3725 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
3726
3727 /* Disable timer */
3728 if (vha->timer_active)
3729 qla2x00_stop_timer(vha);
3730
2afa19a9 3731 qla25xx_delete_queues(vha);
85880801
AV		 3732 vha->flags.online = 0;
3733
f6ef3b18 3734 /* turn-off interrupts on the card */
a9083016
GM		 3735 if (ha->interrupts_on) {
3736 vha->flags.init_done = 0;
fd34f556 3737 ha->isp_ops->disable_intrs(ha);
a9083016 3738 }
f6ef3b18 3739
093df737
QT		 3740 qla2x00_free_fcports(vha);
3741
e315cd28 3742 qla2x00_free_irqs(vha);
1da177e4 3743
093df737
QT		 3744 /* Flush the work queue and remove it */
3745 if (ha->wq) {
3746 flush_workqueue(ha->wq);
3747 destroy_workqueue(ha->wq);
3748 ha->wq = NULL;
3749 }
3750
8867048b 3751
e315cd28 3752 qla2x00_mem_free(ha);
73208dfd 3753
08de2844
GM		 3754 qla82xx_md_free(vha);
3755
73208dfd 3756 qla2x00_free_queues(ha);
1da177e4
LT		 3757}
3758
8867048b
CD		 3759void qla2x00_free_fcports(struct scsi_qla_host *vha)
3760{
3761 fc_port_t *fcport, *tfcport;
3762
3763 list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list) {
3764 list_del(&fcport->list);
5f16b331 3765 qla2x00_clear_loop_id(fcport);
8867048b 3766 kfree(fcport);
8867048b
CD		 3767 }
3768}
3769
d97994dc 3770static inline void
e315cd28 3771qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport,
d97994dc 3772 int defer)
3773{
d97994dc 3774 struct fc_rport *rport;
67becc00 3775 scsi_qla_host_t *base_vha;
044d78e1 3776 unsigned long flags;
d97994dc 3777
3778 if (!fcport->rport)
3779 return;
3780
3781 rport = fcport->rport;
3782 if (defer) {
67becc00 3783 base_vha = pci_get_drvdata(vha->hw->pdev);
044d78e1 3784 spin_lock_irqsave(vha->host->host_lock, flags);
d97994dc 3785 fcport->drport = rport;
044d78e1 3786 spin_unlock_irqrestore(vha->host->host_lock, flags);
df673274 3787 qlt_do_generation_tick(vha, &base_vha->total_fcport_update_gen);
67becc00
AV		 3788 set_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags);
3789 qla2xxx_wake_dpc(base_vha);
2d70c103 3790 } else {
df673274 3791 int now;
726b8548 3792 if (rport) {
83548fe2
QT		 3793 ql_dbg(ql_dbg_disc, fcport->vha, 0x2109,
3794 "%s %8phN. rport %p roles %x\n",
3795 __func__, fcport->port_name, rport,
3796 rport->roles);
d20ed91b 3797 fc_remote_port_delete(rport);
726b8548 3798 }
df673274 3799 qlt_do_generation_tick(vha, &now);
2d70c103 3800 }
d97994dc 3801}
3802
1da177e4
LT		 3803/*
3804 * qla2x00_mark_device_lost Updates fcport state when device goes offline.
3805 *
3806 * Input: ha = adapter block pointer. fcport = port structure pointer.
3807 *
3808 * Return: None.
3809 *
3810 * Context:
3811 */
e315cd28 3812void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport,
d97994dc 3813 int do_login, int defer)
1da177e4 3814{
8ae6d9c7
GM		 3815 if (IS_QLAFX00(vha->hw)) {
3816 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
3817 qla2x00_schedule_rport_del(vha, fcport, defer);
3818 return;
3819 }
3820
2c3dfe3f 3821 if (atomic_read(&fcport->state) == FCS_ONLINE &&
c6d39e23 3822 vha->vp_idx == fcport->vha->vp_idx) {
ec426e10 3823 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
e315cd28
AC		 3824 qla2x00_schedule_rport_del(vha, fcport, defer);
3825 }
fa2a1ce5 3826 /*
1da177e4
LT		 3827 * We may need to retry the login, so don't change the state of the
3828 * port but do the retries.
3829 */
3830 if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD)
ec426e10 3831 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
1da177e4
LT		 3832
3833 if (!do_login)
3834 return;
3835
a1d0285e 3836 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
1da177e4
LT		 3837}
3838
3839/*
3840 * qla2x00_mark_all_devices_lost
3841 * Updates fcport state when device goes offline.
3842 *
3843 * Input:
3844 * ha = adapter block pointer.
3845 * fcport = port structure pointer.
3846 *
3847 * Return:
3848 * None.
3849 *
3850 * Context:
3851 */
3852void
e315cd28 3853qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha, int defer)
1da177e4
LT		 3854{
3855 fc_port_t *fcport;
3856
83548fe2
QT		 3857 ql_dbg(ql_dbg_disc, vha, 0x20f1,
3858 "Mark all dev lost\n");
726b8548 3859
e315cd28 3860 list_for_each_entry(fcport, &vha->vp_fcports, list) {
726b8548 3861 fcport->scan_state = 0;
d8630bb9 3862 qlt_schedule_sess_for_deletion(fcport);
726b8548 3863
c6d39e23 3864 if (vha->vp_idx != 0 && vha->vp_idx != fcport->vha->vp_idx)
1da177e4 3865 continue;
0d6e61bc 3866
1da177e4
LT		 3867 /*
3868 * No point in marking the device as lost, if the device is
3869 * already DEAD.
3870 */
3871 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD)
3872 continue;
e315cd28 3873 if (atomic_read(&fcport->state) == FCS_ONLINE) {
ec426e10 3874 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
0d6e61bc
AV		 3875 if (defer)
3876 qla2x00_schedule_rport_del(vha, fcport, defer);
c6d39e23 3877 else if (vha->vp_idx == fcport->vha->vp_idx)
0d6e61bc
AV		 3878 qla2x00_schedule_rport_del(vha, fcport, defer);
3879 }
1da177e4
LT		 3880 }
3881}
3882
3883/*
3884* qla2x00_mem_alloc
3885* Allocates adapter memory.
3886*
3887* Returns:
3888* 0 = success.
e8711085 3889* !0 = failure.
1da177e4 3890*/
e8711085 3891static int
73208dfd
AC		 3892qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len,
3893 struct req_que **req, struct rsp_que **rsp)
1da177e4
LT		 3894{
3895 char name[16];
1da177e4 3896
e8711085 3897 ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size,
e315cd28 3898 &ha->init_cb_dma, GFP_KERNEL);
e8711085 3899 if (!ha->init_cb)
e315cd28 3900 goto fail;
e8711085 3901
2d70c103
NB		 3902 if (qlt_mem_alloc(ha) < 0)
3903 goto fail_free_init_cb;
3904
642ef983
CD		 3905 ha->gid_list = dma_alloc_coherent(&ha->pdev->dev,
3906 qla2x00_gid_list_size(ha), &ha->gid_list_dma, GFP_KERNEL);
e315cd28 3907 if (!ha->gid_list)
2d70c103 3908 goto fail_free_tgt_mem;
1da177e4 3909
e8711085
AV		 3910 ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep);
3911 if (!ha->srb_mempool)
e315cd28 3912 goto fail_free_gid_list;
e8711085 3913
7ec0effd 3914 if (IS_P3P_TYPE(ha)) {
a9083016
GM		 3915 /* Allocate cache for CT6 Ctx. */
3916 if (!ctx_cachep) {
3917 ctx_cachep = kmem_cache_create("qla2xxx_ctx",
3918 sizeof(struct ct6_dsd), 0,
3919 SLAB_HWCACHE_ALIGN, NULL);
3920 if (!ctx_cachep)
fc1ffd6c 3921 goto fail_free_srb_mempool;
a9083016
GM		 3922 }
3923 ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ,
3924 ctx_cachep);
3925 if (!ha->ctx_mempool)
3926 goto fail_free_srb_mempool;
7c3df132
SK		 3927 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021,
3928 "ctx_cachep=%p ctx_mempool=%p.\n",
3929 ctx_cachep, ha->ctx_mempool);
a9083016
GM		 3930 }
3931
e8711085
AV		 3932 /* Get memory for cached NVRAM */
3933 ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL);
3934 if (!ha->nvram)
a9083016 3935 goto fail_free_ctx_mempool;
e8711085 3936
e315cd28
AC		 3937 snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME,
3938 ha->pdev->device);
3939 ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3940 DMA_POOL_SIZE, 8, 0);
3941 if (!ha->s_dma_pool)
3942 goto fail_free_nvram;
3943
7c3df132
SK		 3944 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022,
3945 "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n",
3946 ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool);
3947
7ec0effd 3948 if (IS_P3P_TYPE(ha) || ql2xenabledif) {
a9083016
GM		 3949 ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3950 DSD_LIST_DMA_POOL_SIZE, 8, 0);
3951 if (!ha->dl_dma_pool) {
7c3df132
SK		 3952 ql_log_pci(ql_log_fatal, ha->pdev, 0x0023,
3953 "Failed to allocate memory for dl_dma_pool.\n");
a9083016
GM		 3954 goto fail_s_dma_pool;
3955 }
3956
3957 ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3958 FCP_CMND_DMA_POOL_SIZE, 8, 0);
3959 if (!ha->fcp_cmnd_dma_pool) {
7c3df132
SK		 3960 ql_log_pci(ql_log_fatal, ha->pdev, 0x0024,
3961 "Failed to allocate memory for fcp_cmnd_dma_pool.\n");
a9083016
GM		 3962 goto fail_dl_dma_pool;
3963 }
7c3df132
SK		 3964 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025,
3965 "dl_dma_pool=%p fcp_cmnd_dma_pool=%p.\n",
3966 ha->dl_dma_pool, ha->fcp_cmnd_dma_pool);
a9083016
GM		 3967 }
3968
e8711085
AV		 3969 /* Allocate memory for SNS commands */
3970 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
e315cd28 3971 /* Get consistent memory allocated for SNS commands */
e8711085 3972 ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev,
e315cd28 3973 sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL);
e8711085 3974 if (!ha->sns_cmd)
e315cd28 3975 goto fail_dma_pool;
7c3df132 3976 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026,
d8424f68 3977 "sns_cmd: %p.\n", ha->sns_cmd);
e8711085 3978 } else {
e315cd28 3979 /* Get consistent memory allocated for MS IOCB */
e8711085 3980 ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
e315cd28 3981 &ha->ms_iocb_dma);
e8711085 3982 if (!ha->ms_iocb)
e315cd28
AC		 3983 goto fail_dma_pool;
3984 /* Get consistent memory allocated for CT SNS commands */
e8711085 3985 ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev,
e315cd28 3986 sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL);
e8711085
AV		 3987 if (!ha->ct_sns)
3988 goto fail_free_ms_iocb;
7c3df132
SK		 3989 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027,
3990 "ms_iocb=%p ct_sns=%p.\n",
3991 ha->ms_iocb, ha->ct_sns);
1da177e4
LT		 3992 }
3993
e315cd28 3994 /* Allocate memory for request ring */
73208dfd
AC		 3995 *req = kzalloc(sizeof(struct req_que), GFP_KERNEL);
3996 if (!*req) {
7c3df132
SK		 3997 ql_log_pci(ql_log_fatal, ha->pdev, 0x0028,
3998 "Failed to allocate memory for req.\n");
e315cd28
AC		 3999 goto fail_req;
4000 }
73208dfd
AC		 4001 (*req)->length = req_len;
4002 (*req)->ring = dma_alloc_coherent(&ha->pdev->dev,
4003 ((*req)->length + 1) * sizeof(request_t),
4004 &(*req)->dma, GFP_KERNEL);
4005 if (!(*req)->ring) {
7c3df132
SK		 4006 ql_log_pci(ql_log_fatal, ha->pdev, 0x0029,
4007 "Failed to allocate memory for req_ring.\n");
e315cd28
AC		 4008 goto fail_req_ring;
4009 }
4010 /* Allocate memory for response ring */
73208dfd
AC		 4011 *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL);
4012 if (!*rsp) {
7c3df132
SK		 4013 ql_log_pci(ql_log_fatal, ha->pdev, 0x002a,
4014 "Failed to allocate memory for rsp.\n");
e315cd28
AC		 4015 goto fail_rsp;
4016 }
73208dfd
AC		 4017 (*rsp)->hw = ha;
4018 (*rsp)->length = rsp_len;
4019 (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev,
4020 ((*rsp)->length + 1) * sizeof(response_t),
4021 &(*rsp)->dma, GFP_KERNEL);
4022 if (!(*rsp)->ring) {
7c3df132
SK		 4023 ql_log_pci(ql_log_fatal, ha->pdev, 0x002b,
4024 "Failed to allocate memory for rsp_ring.\n");
e315cd28
AC		 4025 goto fail_rsp_ring;
4026 }
73208dfd
AC		 4027 (*req)->rsp = *rsp;
4028 (*rsp)->req = *req;
7c3df132
SK		 4029 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c,
4030 "req=%p req->length=%d req->ring=%p rsp=%p "
4031 "rsp->length=%d rsp->ring=%p.\n",
4032 *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length,
4033 (*rsp)->ring);
73208dfd
AC		 4034 /* Allocate memory for NVRAM data for vports */
4035 if (ha->nvram_npiv_size) {
6396bb22
KC		 4036 ha->npiv_info = kcalloc(ha->nvram_npiv_size,
4037 sizeof(struct qla_npiv_entry),
4038 GFP_KERNEL);
73208dfd 4039 if (!ha->npiv_info) {
7c3df132
SK		 4040 ql_log_pci(ql_log_fatal, ha->pdev, 0x002d,
4041 "Failed to allocate memory for npiv_info.\n");
73208dfd
AC		 4042 goto fail_npiv_info;
4043 }
4044 } else
4045 ha->npiv_info = NULL;
e8711085 4046
b64b0e8f 4047 /* Get consistent memory allocated for EX-INIT-CB. */
f73cb695 4048 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha)) {
b64b0e8f
AV		 4049 ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
4050 &ha->ex_init_cb_dma);
4051 if (!ha->ex_init_cb)
4052 goto fail_ex_init_cb;
7c3df132
SK		 4053 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e,
4054 "ex_init_cb=%p.\n", ha->ex_init_cb);
b64b0e8f
AV		 4055 }
4056
a9083016
GM		 4057 INIT_LIST_HEAD(&ha->gbl_dsd_list);
4058
5ff1d584
AV		 4059 /* Get consistent memory allocated for Async Port-Database. */
4060 if (!IS_FWI2_CAPABLE(ha)) {
4061 ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
4062 &ha->async_pd_dma);
4063 if (!ha->async_pd)
4064 goto fail_async_pd;
7c3df132
SK		 4065 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f,
4066 "async_pd=%p.\n", ha->async_pd);
5ff1d584
AV		 4067 }
4068
e315cd28 4069 INIT_LIST_HEAD(&ha->vp_list);
5f16b331
CD		 4070
4071 /* Allocate memory for our loop_id bitmap */
6396bb22
KC		 4072 ha->loop_id_map = kcalloc(BITS_TO_LONGS(LOOPID_MAP_SIZE),
4073 sizeof(long),
4074 GFP_KERNEL);
5f16b331 4075 if (!ha->loop_id_map)
fc1ffd6c 4076 goto fail_loop_id_map;
5f16b331
CD		 4077 else {
4078 qla2x00_set_reserved_loop_ids(ha);
4079 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0123,
b2a72ec3 4080 "loop_id_map=%p.\n", ha->loop_id_map);
5f16b331
CD		 4081 }
4082
e4e3a2ce
QT		 4083 ha->sfp_data = dma_alloc_coherent(&ha->pdev->dev,
4084 SFP_DEV_SIZE, &ha->sfp_data_dma, GFP_KERNEL);
4085 if (!ha->sfp_data) {
4086 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b,
4087 "Unable to allocate memory for SFP read-data.\n");
4088 goto fail_sfp_data;
4089 }
4090
b2a72ec3 4091 return 0;
e315cd28 4092
e4e3a2ce
QT		 4093fail_sfp_data:
4094 kfree(ha->loop_id_map);
fc1ffd6c
QT		 4095fail_loop_id_map:
4096 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
5ff1d584
AV		 4097fail_async_pd:
4098 dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma);
b64b0e8f
AV		 4099fail_ex_init_cb:
4100 kfree(ha->npiv_info);
73208dfd
AC		 4101fail_npiv_info:
4102 dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) *
4103 sizeof(response_t), (*rsp)->ring, (*rsp)->dma);
4104 (*rsp)->ring = NULL;
4105 (*rsp)->dma = 0;
e315cd28 4106fail_rsp_ring:
73208dfd 4107 kfree(*rsp);
6d634067 4108 *rsp = NULL;
e315cd28 4109fail_rsp:
73208dfd
AC		 4110 dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) *
4111 sizeof(request_t), (*req)->ring, (*req)->dma);
4112 (*req)->ring = NULL;
4113 (*req)->dma = 0;
e315cd28 4114fail_req_ring:
73208dfd 4115 kfree(*req);
6d634067 4116 *req = NULL;
e315cd28
AC		 4117fail_req:
4118 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
4119 ha->ct_sns, ha->ct_sns_dma);
4120 ha->ct_sns = NULL;
4121 ha->ct_sns_dma = 0;
e8711085
AV		 4122fail_free_ms_iocb:
4123 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
4124 ha->ms_iocb = NULL;
4125 ha->ms_iocb_dma = 0;
fc1ffd6c
QT		 4126
4127 if (ha->sns_cmd)
4128 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
4129 ha->sns_cmd, ha->sns_cmd_dma);
e315cd28 4130fail_dma_pool:
bad75002 4131 if (IS_QLA82XX(ha) || ql2xenabledif) {
a9083016
GM		 4132 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
4133 ha->fcp_cmnd_dma_pool = NULL;
4134 }
4135fail_dl_dma_pool:
bad75002 4136 if (IS_QLA82XX(ha) || ql2xenabledif) {
a9083016
GM		 4137 dma_pool_destroy(ha->dl_dma_pool);
4138 ha->dl_dma_pool = NULL;
4139 }
4140fail_s_dma_pool:
e315cd28
AC		 4141 dma_pool_destroy(ha->s_dma_pool);
4142 ha->s_dma_pool = NULL;
e8711085
AV		 4143fail_free_nvram:
4144 kfree(ha->nvram);
4145 ha->nvram = NULL;
a9083016 4146fail_free_ctx_mempool:
fc1ffd6c
QT		 4147 if (ha->ctx_mempool)
4148 mempool_destroy(ha->ctx_mempool);
a9083016 4149 ha->ctx_mempool = NULL;
e8711085 4150fail_free_srb_mempool:
fc1ffd6c
QT		 4151 if (ha->srb_mempool)
4152 mempool_destroy(ha->srb_mempool);
e8711085 4153 ha->srb_mempool = NULL;
e8711085 4154fail_free_gid_list:
642ef983
CD		 4155 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
4156 ha->gid_list,
e315cd28 4157 ha->gid_list_dma);
e8711085
AV		 4158 ha->gid_list = NULL;
4159 ha->gid_list_dma = 0;
2d70c103
NB		 4160fail_free_tgt_mem:
4161 qlt_mem_free(ha);
e315cd28
AC		 4162fail_free_init_cb:
4163 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb,
4164 ha->init_cb_dma);
4165 ha->init_cb = NULL;
4166 ha->init_cb_dma = 0;
e8711085 4167fail:
7c3df132
SK		 4168 ql_log(ql_log_fatal, NULL, 0x0030,
4169 "Memory allocation failure.\n");
e8711085 4170 return -ENOMEM;
1da177e4
LT		 4171}
4172
b0d6cabd
HM		 4173int
4174qla2x00_set_exlogins_buffer(scsi_qla_host_t *vha)
4175{
4176 int rval;
4177 uint16_t size, max_cnt, temp;
4178 struct qla_hw_data *ha = vha->hw;
4179
4180 /* Return if we don't need to alloacate any extended logins */
4181 if (!ql2xexlogins)
4182 return QLA_SUCCESS;
4183
99e1b683
QT		 4184 if (!IS_EXLOGIN_OFFLD_CAPABLE(ha))
4185 return QLA_SUCCESS;
4186
b0d6cabd
HM		 4187 ql_log(ql_log_info, vha, 0xd021, "EXLOGIN count: %d.\n", ql2xexlogins);
4188 max_cnt = 0;
4189 rval = qla_get_exlogin_status(vha, &size, &max_cnt);
4190 if (rval != QLA_SUCCESS) {
4191 ql_log_pci(ql_log_fatal, ha->pdev, 0xd029,
4192 "Failed to get exlogin status.\n");
4193 return rval;
4194 }
4195
4196 temp = (ql2xexlogins > max_cnt) ? max_cnt : ql2xexlogins;
99e1b683
QT		 4197 temp *= size;
4198
4199 if (temp != ha->exlogin_size) {
4200 qla2x00_free_exlogin_buffer(ha);
4201 ha->exlogin_size = temp;
4202
4203 ql_log(ql_log_info, vha, 0xd024,
4204 "EXLOGIN: max_logins=%d, portdb=0x%x, total=%d.\n",
4205 max_cnt, size, temp);
4206
4207 ql_log(ql_log_info, vha, 0xd025,
4208 "EXLOGIN: requested size=0x%x\n", ha->exlogin_size);
4209
4210 /* Get consistent memory for extended logins */
4211 ha->exlogin_buf = dma_alloc_coherent(&ha->pdev->dev,
4212 ha->exlogin_size, &ha->exlogin_buf_dma, GFP_KERNEL);
4213 if (!ha->exlogin_buf) {
4214 ql_log_pci(ql_log_fatal, ha->pdev, 0xd02a,
b0d6cabd 4215 "Failed to allocate memory for exlogin_buf_dma.\n");
99e1b683
QT		 4216 return -ENOMEM;
4217 }
b0d6cabd
HM		 4218 }
4219
4220 /* Now configure the dma buffer */
4221 rval = qla_set_exlogin_mem_cfg(vha, ha->exlogin_buf_dma);
4222 if (rval) {
83548fe2 4223 ql_log(ql_log_fatal, vha, 0xd033,
b0d6cabd
HM		 4224 "Setup extended login buffer ****FAILED****.\n");
4225 qla2x00_free_exlogin_buffer(ha);
4226 }
4227
4228 return rval;
4229}
4230
4231/*
4232* qla2x00_free_exlogin_buffer
4233*
4234* Input:
4235* ha = adapter block pointer
4236*/
4237void
4238qla2x00_free_exlogin_buffer(struct qla_hw_data *ha)
4239{
4240 if (ha->exlogin_buf) {
4241 dma_free_coherent(&ha->pdev->dev, ha->exlogin_size,
4242 ha->exlogin_buf, ha->exlogin_buf_dma);
4243 ha->exlogin_buf = NULL;
4244 ha->exlogin_size = 0;
4245 }
4246}
4247
99e1b683
QT		 4248static void
4249qla2x00_number_of_exch(scsi_qla_host_t *vha, u32 *ret_cnt, u16 max_cnt)
4250{
4251 u32 temp;
4252 *ret_cnt = FW_DEF_EXCHANGES_CNT;
4253
d1e3635a
QT		 4254 if (max_cnt > vha->hw->max_exchg)
4255 max_cnt = vha->hw->max_exchg;
4256
99e1b683
QT		 4257 if (qla_ini_mode_enabled(vha)) {
4258 if (ql2xiniexchg > max_cnt)
4259 ql2xiniexchg = max_cnt;
4260
4261 if (ql2xiniexchg > FW_DEF_EXCHANGES_CNT)
4262 *ret_cnt = ql2xiniexchg;
4263 } else if (qla_tgt_mode_enabled(vha)) {
4264 if (ql2xexchoffld > max_cnt)
4265 ql2xexchoffld = max_cnt;
4266
4267 if (ql2xexchoffld > FW_DEF_EXCHANGES_CNT)
4268 *ret_cnt = ql2xexchoffld;
4269 } else if (qla_dual_mode_enabled(vha)) {
4270 temp = ql2xiniexchg + ql2xexchoffld;
4271 if (temp > max_cnt) {
4272 ql2xiniexchg -= (temp - max_cnt)/2;
4273 ql2xexchoffld -= (((temp - max_cnt)/2) + 1);
4274 temp = max_cnt;
4275 }
4276
4277 if (temp > FW_DEF_EXCHANGES_CNT)
4278 *ret_cnt = temp;
4279 }
4280}
4281
2f56a7f1
HM		 4282int
4283qla2x00_set_exchoffld_buffer(scsi_qla_host_t *vha)
4284{
4285 int rval;
d1e3635a
QT		 4286 u16 size, max_cnt;
4287 u32 actual_cnt, totsz;
2f56a7f1
HM		 4288 struct qla_hw_data *ha = vha->hw;
4289
99e1b683
QT		 4290 if (!ha->flags.exchoffld_enabled)
4291 return QLA_SUCCESS;
4292
4293 if (!IS_EXCHG_OFFLD_CAPABLE(ha))
2f56a7f1
HM		 4294 return QLA_SUCCESS;
4295
2f56a7f1
HM		 4296 max_cnt = 0;
4297 rval = qla_get_exchoffld_status(vha, &size, &max_cnt);
4298 if (rval != QLA_SUCCESS) {
4299 ql_log_pci(ql_log_fatal, ha->pdev, 0xd012,
4300 "Failed to get exlogin status.\n");
4301 return rval;
4302 }
4303
d1e3635a
QT		 4304 qla2x00_number_of_exch(vha, &actual_cnt, max_cnt);
4305 ql_log(ql_log_info, vha, 0xd014,
4306 "Actual exchange offload count: %d.\n", actual_cnt);
4307
4308 totsz = actual_cnt * size;
2f56a7f1 4309
d1e3635a 4310 if (totsz != ha->exchoffld_size) {
99e1b683 4311 qla2x00_free_exchoffld_buffer(ha);
d1e3635a 4312 ha->exchoffld_size = totsz;
99e1b683
QT		 4313
4314 ql_log(ql_log_info, vha, 0xd016,
d1e3635a
QT		 4315 "Exchange offload: max_count=%d, actual count=%d entry sz=0x%x, total sz=0x%x\n",
4316 max_cnt, actual_cnt, size, totsz);
99e1b683
QT		 4317
4318 ql_log(ql_log_info, vha, 0xd017,
4319 "Exchange Buffers requested size = 0x%x\n",
4320 ha->exchoffld_size);
4321
4322 /* Get consistent memory for extended logins */
4323 ha->exchoffld_buf = dma_alloc_coherent(&ha->pdev->dev,
4324 ha->exchoffld_size, &ha->exchoffld_buf_dma, GFP_KERNEL);
4325 if (!ha->exchoffld_buf) {
4326 ql_log_pci(ql_log_fatal, ha->pdev, 0xd013,
d1e3635a
QT		 4327 "Failed to allocate memory for Exchange Offload.\n");
4328
4329 if (ha->max_exchg >
4330 (FW_DEF_EXCHANGES_CNT + REDUCE_EXCHANGES_CNT)) {
4331 ha->max_exchg -= REDUCE_EXCHANGES_CNT;
4332 } else if (ha->max_exchg >
4333 (FW_DEF_EXCHANGES_CNT + 512)) {
4334 ha->max_exchg -= 512;
4335 } else {
4336 ha->flags.exchoffld_enabled = 0;
4337 ql_log_pci(ql_log_fatal, ha->pdev, 0xd013,
4338 "Disabling Exchange offload due to lack of memory\n");
4339 }
4340 ha->exchoffld_size = 0;
4341
99e1b683
QT		 4342 return -ENOMEM;
4343 }
2f56a7f1
HM		 4344 }
4345
4346 /* Now configure the dma buffer */
99e1b683 4347 rval = qla_set_exchoffld_mem_cfg(vha);
2f56a7f1
HM		 4348 if (rval) {
4349 ql_log(ql_log_fatal, vha, 0xd02e,
4350 "Setup exchange offload buffer ****FAILED****.\n");
4351 qla2x00_free_exchoffld_buffer(ha);
99e1b683
QT		 4352 } else {
4353 /* re-adjust number of target exchange */
4354 struct init_cb_81xx *icb = (struct init_cb_81xx *)ha->init_cb;
4355
4356 if (qla_ini_mode_enabled(vha))
4357 icb->exchange_count = 0;
4358 else
4359 icb->exchange_count = cpu_to_le16(ql2xexchoffld);
2f56a7f1
HM		 4360 }
4361
4362 return rval;
4363}
4364
4365/*
4366* qla2x00_free_exchoffld_buffer
4367*
4368* Input:
4369* ha = adapter block pointer
4370*/
4371void
4372qla2x00_free_exchoffld_buffer(struct qla_hw_data *ha)
4373{
4374 if (ha->exchoffld_buf) {
4375 dma_free_coherent(&ha->pdev->dev, ha->exchoffld_size,
4376 ha->exchoffld_buf, ha->exchoffld_buf_dma);
4377 ha->exchoffld_buf = NULL;
4378 ha->exchoffld_size = 0;
4379 }
4380}
4381
1da177e4 4382/*
e30d1756
MI		 4383* qla2x00_free_fw_dump
4384* Frees fw dump stuff.
1da177e4
LT		 4385*
4386* Input:
7ec0effd 4387* ha = adapter block pointer
1da177e4 4388*/
a824ebb3 4389static void
e30d1756 4390qla2x00_free_fw_dump(struct qla_hw_data *ha)
1da177e4 4391{
df613b96 4392 if (ha->fce)
f73cb695
CD		 4393 dma_free_coherent(&ha->pdev->dev,
4394 FCE_SIZE, ha->fce, ha->fce_dma);
df613b96 4395
f73cb695
CD		 4396 if (ha->eft)
4397 dma_free_coherent(&ha->pdev->dev,
4398 EFT_SIZE, ha->eft, ha->eft_dma);
4399
4400 if (ha->fw_dump)
a7a167bf 4401 vfree(ha->fw_dump);
f73cb695
CD		 4402 if (ha->fw_dump_template)
4403 vfree(ha->fw_dump_template);
4404
e30d1756
MI		 4405 ha->fce = NULL;
4406 ha->fce_dma = 0;
4407 ha->eft = NULL;
4408 ha->eft_dma = 0;
e30d1756 4409 ha->fw_dumped = 0;
61f098dd 4410 ha->fw_dump_cap_flags = 0;
e30d1756 4411 ha->fw_dump_reading = 0;
f73cb695
CD		 4412 ha->fw_dump = NULL;
4413 ha->fw_dump_len = 0;
4414 ha->fw_dump_template = NULL;
4415 ha->fw_dump_template_len = 0;
e30d1756
MI		 4416}
4417
4418/*
4419* qla2x00_mem_free
4420* Frees all adapter allocated memory.
4421*
4422* Input:
4423* ha = adapter block pointer.
4424*/
4425static void
4426qla2x00_mem_free(struct qla_hw_data *ha)
4427{
4428 qla2x00_free_fw_dump(ha);
4429
81178772
SK		 4430 if (ha->mctp_dump)
4431 dma_free_coherent(&ha->pdev->dev, MCTP_DUMP_SIZE, ha->mctp_dump,
4432 ha->mctp_dump_dma);
4433
e30d1756
MI		 4434 if (ha->srb_mempool)
4435 mempool_destroy(ha->srb_mempool);
a7a167bf 4436
11bbc1d8
AV		 4437 if (ha->dcbx_tlv)
4438 dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE,
4439 ha->dcbx_tlv, ha->dcbx_tlv_dma);
4440
ce0423f4
AV		 4441 if (ha->xgmac_data)
4442 dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE,
4443 ha->xgmac_data, ha->xgmac_data_dma);
4444
1da177e4
LT		 4445 if (ha->sns_cmd)
4446 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
e315cd28 4447 ha->sns_cmd, ha->sns_cmd_dma);
1da177e4
LT		 4448
4449 if (ha->ct_sns)
4450 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
e315cd28 4451 ha->ct_sns, ha->ct_sns_dma);
1da177e4 4452
88729e53 4453 if (ha->sfp_data)
e4e3a2ce
QT		 4454 dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE, ha->sfp_data,
4455 ha->sfp_data_dma);
88729e53 4456
1da177e4
LT		 4457 if (ha->ms_iocb)
4458 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
4459
b64b0e8f 4460 if (ha->ex_init_cb)
a9083016
GM		 4461 dma_pool_free(ha->s_dma_pool,
4462 ha->ex_init_cb, ha->ex_init_cb_dma);
b64b0e8f 4463
5ff1d584
AV		 4464 if (ha->async_pd)
4465 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
4466
1da177e4
LT		 4467 if (ha->s_dma_pool)
4468 dma_pool_destroy(ha->s_dma_pool);
4469
1da177e4 4470 if (ha->gid_list)
642ef983
CD		 4471 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
4472 ha->gid_list, ha->gid_list_dma);
1da177e4 4473
a9083016
GM		 4474 if (IS_QLA82XX(ha)) {
4475 if (!list_empty(&ha->gbl_dsd_list)) {
4476 struct dsd_dma *dsd_ptr, *tdsd_ptr;
4477
4478 /* clean up allocated prev pool */
4479 list_for_each_entry_safe(dsd_ptr,
4480 tdsd_ptr, &ha->gbl_dsd_list, list) {
4481 dma_pool_free(ha->dl_dma_pool,
4482 dsd_ptr->dsd_addr, dsd_ptr->dsd_list_dma);
4483 list_del(&dsd_ptr->list);
4484 kfree(dsd_ptr);
4485 }
4486 }
4487 }
4488
4489 if (ha->dl_dma_pool)
4490 dma_pool_destroy(ha->dl_dma_pool);
4491
4492 if (ha->fcp_cmnd_dma_pool)
4493 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
4494
4495 if (ha->ctx_mempool)
4496 mempool_destroy(ha->ctx_mempool);
4497
2d70c103
NB		 4498 qlt_mem_free(ha);
4499
e315cd28
AC		 4500 if (ha->init_cb)
4501 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size,
a9083016 4502 ha->init_cb, ha->init_cb_dma);
6a2cf8d3 4503
6d634067
BK		 4504 vfree(ha->optrom_buffer);
4505 kfree(ha->nvram);
4506 kfree(ha->npiv_info);
4507 kfree(ha->swl);
4508 kfree(ha->loop_id_map);
1da177e4 4509
e8711085 4510 ha->srb_mempool = NULL;
a9083016 4511 ha->ctx_mempool = NULL;
1da177e4
LT		 4512 ha->sns_cmd = NULL;
4513 ha->sns_cmd_dma = 0;
4514 ha->ct_sns = NULL;
4515 ha->ct_sns_dma = 0;
4516 ha->ms_iocb = NULL;
4517 ha->ms_iocb_dma = 0;
1da177e4
LT		 4518 ha->init_cb = NULL;
4519 ha->init_cb_dma = 0;
b64b0e8f
AV		 4520 ha->ex_init_cb = NULL;
4521 ha->ex_init_cb_dma = 0;
5ff1d584
AV		 4522 ha->async_pd = NULL;
4523 ha->async_pd_dma = 0;
6a2cf8d3
BK		 4524 ha->loop_id_map = NULL;
4525 ha->npiv_info = NULL;
4526 ha->optrom_buffer = NULL;
4527 ha->swl = NULL;
4528 ha->nvram = NULL;
4529 ha->mctp_dump = NULL;
4530 ha->dcbx_tlv = NULL;
4531 ha->xgmac_data = NULL;
4532 ha->sfp_data = NULL;
1da177e4
LT		 4533
4534 ha->s_dma_pool = NULL;
a9083016
GM		 4535 ha->dl_dma_pool = NULL;
4536 ha->fcp_cmnd_dma_pool = NULL;
1da177e4 4537
1da177e4
LT		 4538 ha->gid_list = NULL;
4539 ha->gid_list_dma = 0;
2d70c103
NB		 4540
4541 ha->tgt.atio_ring = NULL;
4542 ha->tgt.atio_dma = 0;
4543 ha->tgt.tgt_vp_map = NULL;
e315cd28 4544}
1da177e4 4545
e315cd28
AC		 4546struct scsi_qla_host *qla2x00_create_host(struct scsi_host_template *sht,
4547 struct qla_hw_data *ha)
4548{
4549 struct Scsi_Host *host;
4550 struct scsi_qla_host *vha = NULL;
854165f4 4551
e315cd28 4552 host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t));
41dc529a 4553 if (!host) {
7c3df132
SK		 4554 ql_log_pci(ql_log_fatal, ha->pdev, 0x0107,
4555 "Failed to allocate host from the scsi layer, aborting.\n");
41dc529a 4556 return NULL;
e315cd28
AC		 4557 }
4558
4559 /* Clear our data area */
4560 vha = shost_priv(host);
4561 memset(vha, 0, sizeof(scsi_qla_host_t));
4562
4563 vha->host = host;
4564 vha->host_no = host->host_no;
4565 vha->hw = ha;
4566
4567 INIT_LIST_HEAD(&vha->vp_fcports);
4568 INIT_LIST_HEAD(&vha->work_list);
4569 INIT_LIST_HEAD(&vha->list);
8b2f5ff3
SN		 4570 INIT_LIST_HEAD(&vha->qla_cmd_list);
4571 INIT_LIST_HEAD(&vha->qla_sess_op_cmd_list);
71cdc079 4572 INIT_LIST_HEAD(&vha->logo_list);
b7bd104e 4573 INIT_LIST_HEAD(&vha->plogi_ack_list);
d7459527 4574 INIT_LIST_HEAD(&vha->qp_list);
41dc529a 4575 INIT_LIST_HEAD(&vha->gnl.fcports);
a5d42f4c 4576 INIT_LIST_HEAD(&vha->nvme_rport_list);
2d73ac61 4577 INIT_LIST_HEAD(&vha->gpnid_list);
9b3e0f4d 4578 INIT_WORK(&vha->iocb_work, qla2x00_iocb_work_fn);
e315cd28 4579
f999f4c1 4580 spin_lock_init(&vha->work_lock);
8b2f5ff3 4581 spin_lock_init(&vha->cmd_list_lock);
1c6cacf4 4582 spin_lock_init(&vha->gnl.fcports_lock);
726b8548 4583 init_waitqueue_head(&vha->fcport_waitQ);
c4a9b538 4584 init_waitqueue_head(&vha->vref_waitq);
f999f4c1 4585
2fdbc65e
BVA		 4586 vha->gnl.size = sizeof(struct get_name_list_extended) *
4587 (ha->max_loop_id + 1);
41dc529a
QT		 4588 vha->gnl.l = dma_alloc_coherent(&ha->pdev->dev,
4589 vha->gnl.size, &vha->gnl.ldma, GFP_KERNEL);
4590 if (!vha->gnl.l) {
83548fe2 4591 ql_log(ql_log_fatal, vha, 0xd04a,
41dc529a
QT		 4592 "Alloc failed for name list.\n");
4593 scsi_remove_host(vha->host);
4594 return NULL;
4595 }
f999f4c1 4596
a4239945
QT		 4597 /* todo: what about ext login? */
4598 vha->scan.size = ha->max_fibre_devices * sizeof(struct fab_scan_rp);
4599 vha->scan.l = vmalloc(vha->scan.size);
4600 if (!vha->scan.l) {
4601 ql_log(ql_log_fatal, vha, 0xd04a,
4602 "Alloc failed for scan database.\n");
4603 dma_free_coherent(&ha->pdev->dev, vha->gnl.size,
4604 vha->gnl.l, vha->gnl.ldma);
4605 scsi_remove_host(vha->host);
4606 return NULL;
4607 }
f352eeb7 4608 INIT_DELAYED_WORK(&vha->scan.scan_work, qla_scan_work_fn);
a4239945 4609
e315cd28 4610 sprintf(vha->host_str, "%s_%ld", QLA2XXX_DRIVER_NAME, vha->host_no);
7c3df132
SK		 4611 ql_dbg(ql_dbg_init, vha, 0x0041,
4612 "Allocated the host=%p hw=%p vha=%p dev_name=%s",
4613 vha->host, vha->hw, vha,
4614 dev_name(&(ha->pdev->dev)));
4615
e315cd28 4616 return vha;
1da177e4
LT		 4617}
4618
726b8548 4619struct qla_work_evt *
f999f4c1 4620qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type)
0971de7f
AV		 4621{
4622 struct qla_work_evt *e;
feafb7b1
AE		 4623 uint8_t bail;
4624
4625 QLA_VHA_MARK_BUSY(vha, bail);
4626 if (bail)
4627 return NULL;
0971de7f 4628
f999f4c1 4629 e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC);
feafb7b1
AE		 4630 if (!e) {
4631 QLA_VHA_MARK_NOT_BUSY(vha);
0971de7f 4632 return NULL;
feafb7b1 4633 }
0971de7f
AV		 4634
4635 INIT_LIST_HEAD(&e->list);
4636 e->type = type;
4637 e->flags = QLA_EVT_FLAG_FREE;
4638 return e;
4639}
4640
726b8548 4641int
f999f4c1 4642qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e)
0971de7f 4643{
f999f4c1 4644 unsigned long flags;
9b3e0f4d 4645 bool q = false;
0971de7f 4646
f999f4c1 4647 spin_lock_irqsave(&vha->work_lock, flags);
e315cd28 4648 list_add_tail(&e->list, &vha->work_list);
9b3e0f4d
QT		 4649
4650 if (!test_and_set_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags))
4651 q = true;
4652
f999f4c1 4653 spin_unlock_irqrestore(&vha->work_lock, flags);
ec7193e2 4654
9b3e0f4d
QT		 4655 if (q)
4656 queue_work(vha->hw->wq, &vha->iocb_work);
f999f4c1 4657
0971de7f
AV		 4658 return QLA_SUCCESS;
4659}
4660
4661int
e315cd28 4662qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code,
0971de7f
AV		 4663 u32 data)
4664{
4665 struct qla_work_evt *e;
4666
f999f4c1 4667 e = qla2x00_alloc_work(vha, QLA_EVT_AEN);
0971de7f
AV		 4668 if (!e)
4669 return QLA_FUNCTION_FAILED;
4670
4671 e->u.aen.code = code;
4672 e->u.aen.data = data;
f999f4c1 4673 return qla2x00_post_work(vha, e);
0971de7f
AV		 4674}
4675
8a659571
AV		 4676int
4677qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb)
4678{
4679 struct qla_work_evt *e;
4680
f999f4c1 4681 e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK);
8a659571
AV		 4682 if (!e)
4683 return QLA_FUNCTION_FAILED;
4684
4685 memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t));
f999f4c1 4686 return qla2x00_post_work(vha, e);
8a659571
AV		 4687}
4688
ac280b67
AV		 4689#define qla2x00_post_async_work(name, type) \
4690int qla2x00_post_async_##name##_work( \
4691 struct scsi_qla_host *vha, \
4692 fc_port_t *fcport, uint16_t *data) \
4693{ \
4694 struct qla_work_evt *e; \
4695 \
4696 e = qla2x00_alloc_work(vha, type); \
4697 if (!e) \
4698 return QLA_FUNCTION_FAILED; \
4699 \
4700 e->u.logio.fcport = fcport; \
4701 if (data) { \
4702 e->u.logio.data[0] = data[0]; \
4703 e->u.logio.data[1] = data[1]; \
4704 } \
6d674927 4705 fcport->flags |= FCF_ASYNC_ACTIVE; \
ac280b67
AV		 4706 return qla2x00_post_work(vha, e); \
4707}
4708
4709qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN);
ac280b67
AV		 4710qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT);
4711qla2x00_post_async_work(logout_done, QLA_EVT_ASYNC_LOGOUT_DONE);
5ff1d584
AV		 4712qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC);
4713qla2x00_post_async_work(adisc_done, QLA_EVT_ASYNC_ADISC_DONE);
11aea16a
QT		 4714qla2x00_post_async_work(prlo, QLA_EVT_ASYNC_PRLO);
4715qla2x00_post_async_work(prlo_done, QLA_EVT_ASYNC_PRLO_DONE);
ac280b67 4716
3420d36c
AV		 4717int
4718qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code)
4719{
4720 struct qla_work_evt *e;
4721
4722 e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT);
4723 if (!e)
4724 return QLA_FUNCTION_FAILED;
4725
4726 e->u.uevent.code = code;
4727 return qla2x00_post_work(vha, e);
4728}
4729
4730static void
4731qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code)
4732{
4733 char event_string[40];
4734 char *envp[] = { event_string, NULL };
4735
4736 switch (code) {
4737 case QLA_UEVENT_CODE_FW_DUMP:
4738 snprintf(event_string, sizeof(event_string), "FW_DUMP=%ld",
4739 vha->host_no);
4740 break;
4741 default:
4742 /* do nothing */
4743 break;
4744 }
4745 kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp);
4746}
4747
8ae6d9c7
GM		 4748int
4749qlafx00_post_aenfx_work(struct scsi_qla_host *vha, uint32_t evtcode,
4750 uint32_t *data, int cnt)
4751{
4752 struct qla_work_evt *e;
4753
4754 e = qla2x00_alloc_work(vha, QLA_EVT_AENFX);
4755 if (!e)
4756 return QLA_FUNCTION_FAILED;
4757
4758 e->u.aenfx.evtcode = evtcode;
4759 e->u.aenfx.count = cnt;
4760 memcpy(e->u.aenfx.mbx, data, sizeof(*data) * cnt);
4761 return qla2x00_post_work(vha, e);
4762}
4763
cd4ed6b4 4764void qla24xx_sched_upd_fcport(fc_port_t *fcport)
726b8548 4765{
cd4ed6b4 4766 unsigned long flags;
726b8548 4767
cd4ed6b4
QT		 4768 if (IS_SW_RESV_ADDR(fcport->d_id))
4769 return;
726b8548 4770
cd4ed6b4
QT		 4771 spin_lock_irqsave(&fcport->vha->work_lock, flags);
4772 if (fcport->disc_state == DSC_UPD_FCPORT) {
4773 spin_unlock_irqrestore(&fcport->vha->work_lock, flags);
4774 return;
4775 }
4776 fcport->jiffies_at_registration = jiffies;
4777 fcport->sec_since_registration = 0;
4778 fcport->next_disc_state = DSC_DELETED;
4779 fcport->disc_state = DSC_UPD_FCPORT;
4780 spin_unlock_irqrestore(&fcport->vha->work_lock, flags);
4781
4782 queue_work(system_unbound_wq, &fcport->reg_work);
726b8548
QT		 4783}
4784
4785static
4786void qla24xx_create_new_sess(struct scsi_qla_host *vha, struct qla_work_evt *e)
4787{
4788 unsigned long flags;
b5d15312 4789 fc_port_t *fcport = NULL, *tfcp;
726b8548
QT		 4790 struct qlt_plogi_ack_t *pla =
4791 (struct qlt_plogi_ack_t *)e->u.new_sess.pla;
b5d15312 4792 uint8_t free_fcport = 0;
726b8548 4793
9cd883f0
QT		 4794 ql_dbg(ql_dbg_disc, vha, 0xffff,
4795 "%s %d %8phC enter\n",
4796 __func__, __LINE__, e->u.new_sess.port_name);
4797
726b8548
QT		 4798 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
4799 fcport = qla2x00_find_fcport_by_wwpn(vha, e->u.new_sess.port_name, 1);
4800 if (fcport) {
4801 fcport->d_id = e->u.new_sess.id;
4802 if (pla) {
4803 fcport->fw_login_state = DSC_LS_PLOGI_PEND;
9b3e0f4d
QT		 4804 memcpy(fcport->node_name,
4805 pla->iocb.u.isp24.u.plogi.node_name,
4806 WWN_SIZE);
726b8548
QT		 4807 qlt_plogi_ack_link(vha, pla, fcport, QLT_PLOGI_LINK_SAME_WWN);
4808 /* we took an extra ref_count to prevent PLOGI ACK when
4809 * fcport/sess has not been created.
4810 */
4811 pla->ref_count--;
4812 }
4813 } else {
b5d15312 4814 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
726b8548
QT		 4815 fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
4816 if (fcport) {
4817 fcport->d_id = e->u.new_sess.id;
726b8548
QT		 4818 fcport->flags |= FCF_FABRIC_DEVICE;
4819 fcport->fw_login_state = DSC_LS_PLOGI_PEND;
8777e431 4820 if (e->u.new_sess.fc4_type == FS_FC4TYPE_FCP)
a4239945 4821 fcport->fc4_type = FC4_TYPE_FCP_SCSI;
726b8548 4822
8777e431 4823 if (e->u.new_sess.fc4_type == FS_FC4TYPE_NVME) {
2b5b9647
DT		 4824 fcport->fc4_type = FC4_TYPE_OTHER;
4825 fcport->fc4f_nvme = FC4_TYPE_NVME;
4826 }
33b28357 4827
726b8548
QT		 4828 memcpy(fcport->port_name, e->u.new_sess.port_name,
4829 WWN_SIZE);
b5d15312
QT		 4830 } else {
4831 ql_dbg(ql_dbg_disc, vha, 0xffff,
4832 "%s %8phC mem alloc fail.\n",
4833 __func__, e->u.new_sess.port_name);
4834
4835 if (pla)
4836 kmem_cache_free(qla_tgt_plogi_cachep, pla);
4837 return;
4838 }
4839
4840 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
a4239945 4841 /* search again to make sure no one else got ahead */
b5d15312
QT		 4842 tfcp = qla2x00_find_fcport_by_wwpn(vha,
4843 e->u.new_sess.port_name, 1);
4844 if (tfcp) {
4845 /* should rarily happen */
4846 ql_dbg(ql_dbg_disc, vha, 0xffff,
4847 "%s %8phC found existing fcport b4 add. DS %d LS %d\n",
4848 __func__, tfcp->port_name, tfcp->disc_state,
4849 tfcp->fw_login_state);
4850
4851 free_fcport = 1;
4852 } else {
726b8548
QT		 4853 list_add_tail(&fcport->list, &vha->vp_fcports);
4854
19759033
QT		 4855 }
4856 if (pla) {
4857 qlt_plogi_ack_link(vha, pla, fcport,
4858 QLT_PLOGI_LINK_SAME_WWN);
4859 pla->ref_count--;
726b8548
QT		 4860 }
4861 }
4862 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
4863
4864 if (fcport) {
a4239945
QT		 4865 fcport->id_changed = 1;
4866 fcport->scan_state = QLA_FCPORT_FOUND;
4867 memcpy(fcport->node_name, e->u.new_sess.node_name, WWN_SIZE);
4868
5ef696aa 4869 if (pla) {
9cd883f0
QT		 4870 if (pla->iocb.u.isp24.status_subcode == ELS_PRLI) {
4871 u16 wd3_lo;
4872
4873 fcport->fw_login_state = DSC_LS_PRLI_PEND;
4874 fcport->local = 0;
4875 fcport->loop_id =
4876 le16_to_cpu(
4877 pla->iocb.u.isp24.nport_handle);
4878 fcport->fw_login_state = DSC_LS_PRLI_PEND;
4879 wd3_lo =
4880 le16_to_cpu(
4881 pla->iocb.u.isp24.u.prli.wd3_lo);
4882
4883 if (wd3_lo & BIT_7)
4884 fcport->conf_compl_supported = 1;
4885
4886 if ((wd3_lo & BIT_4) == 0)
4887 fcport->port_type = FCT_INITIATOR;
4888 else
4889 fcport->port_type = FCT_TARGET;
4890 }
726b8548 4891 qlt_plogi_ack_unref(vha, pla);
5ef696aa 4892 } else {
1c6cacf4
HR		 4893 fc_port_t *dfcp = NULL;
4894
5ef696aa
QT		 4895 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
4896 tfcp = qla2x00_find_fcport_by_nportid(vha,
4897 &e->u.new_sess.id, 1);
4898 if (tfcp && (tfcp != fcport)) {
4899 /*
4900 * We have a conflict fcport with same NportID.
4901 */
4902 ql_dbg(ql_dbg_disc, vha, 0xffff,
4903 "%s %8phC found conflict b4 add. DS %d LS %d\n",
4904 __func__, tfcp->port_name, tfcp->disc_state,
4905 tfcp->fw_login_state);
4906
4907 switch (tfcp->disc_state) {
4908 case DSC_DELETED:
4909 break;
4910 case DSC_DELETE_PEND:
4911 fcport->login_pause = 1;
4912 tfcp->conflict = fcport;
4913 break;
4914 default:
4915 fcport->login_pause = 1;
4916 tfcp->conflict = fcport;
1c6cacf4 4917 dfcp = tfcp;
5ef696aa
QT		 4918 break;
4919 }
4920 }
4921 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
1c6cacf4
HR		 4922 if (dfcp)
4923 qlt_schedule_sess_for_deletion(tfcp);
a4239945 4924
a4239945 4925
8777e431
QT		 4926 if (N2N_TOPO(vha->hw))
4927 fcport->flags &= ~FCF_FABRIC_DEVICE;
4928
4929 if (N2N_TOPO(vha->hw)) {
4930 if (vha->flags.nvme_enabled) {
4931 fcport->fc4f_nvme = 1;
4932 fcport->n2n_flag = 1;
4933 }
4934 fcport->fw_login_state = 0;
4935 /*
4936 * wait link init done before sending login
4937 */
4938 } else {
4939 qla24xx_fcport_handle_login(vha, fcport);
4940 }
5ef696aa 4941 }
726b8548 4942 }
b5d15312
QT		 4943
4944 if (free_fcport) {
4945 qla2x00_free_fcport(fcport);
4946 if (pla)
4947 kmem_cache_free(qla_tgt_plogi_cachep, pla);
4948 }
726b8548
QT		 4949}
4950
e374f9f5
QT		 4951static void qla_sp_retry(struct scsi_qla_host *vha, struct qla_work_evt *e)
4952{
4953 struct srb *sp = e->u.iosb.sp;
4954 int rval;
4955
4956 rval = qla2x00_start_sp(sp);
4957 if (rval != QLA_SUCCESS) {
4958 ql_dbg(ql_dbg_disc, vha, 0x2043,
4959 "%s: %s: Re-issue IOCB failed (%d).\n",
4960 __func__, sp->name, rval);
4961 qla24xx_sp_unmap(vha, sp);
4962 }
4963}
4964
ac280b67 4965void
e315cd28 4966qla2x00_do_work(struct scsi_qla_host *vha)
0971de7f 4967{
f999f4c1
AV		 4968 struct qla_work_evt *e, *tmp;
4969 unsigned long flags;
4970 LIST_HEAD(work);
0971de7f 4971
f999f4c1
AV		 4972 spin_lock_irqsave(&vha->work_lock, flags);
4973 list_splice_init(&vha->work_list, &work);
4974 spin_unlock_irqrestore(&vha->work_lock, flags);
4975
4976 list_for_each_entry_safe(e, tmp, &work, list) {
0971de7f 4977 list_del_init(&e->list);
0971de7f
AV		 4978
4979 switch (e->type) {
4980 case QLA_EVT_AEN:
e315cd28 4981 fc_host_post_event(vha->host, fc_get_event_number(),
0971de7f
AV		 4982 e->u.aen.code, e->u.aen.data);
4983 break;
8a659571
AV		 4984 case QLA_EVT_IDC_ACK:
4985 qla81xx_idc_ack(vha, e->u.idc_ack.mb);
4986 break;
ac280b67
AV		 4987 case QLA_EVT_ASYNC_LOGIN:
4988 qla2x00_async_login(vha, e->u.logio.fcport,
4989 e->u.logio.data);
4990 break;
ac280b67
AV		 4991 case QLA_EVT_ASYNC_LOGOUT:
4992 qla2x00_async_logout(vha, e->u.logio.fcport);
4993 break;
4994 case QLA_EVT_ASYNC_LOGOUT_DONE:
4995 qla2x00_async_logout_done(vha, e->u.logio.fcport,
4996 e->u.logio.data);
4997 break;
5ff1d584
AV		 4998 case QLA_EVT_ASYNC_ADISC:
4999 qla2x00_async_adisc(vha, e->u.logio.fcport,
5000 e->u.logio.data);
5001 break;
5002 case QLA_EVT_ASYNC_ADISC_DONE:
5003 qla2x00_async_adisc_done(vha, e->u.logio.fcport,
5004 e->u.logio.data);
5005 break;
3420d36c
AV		 5006 case QLA_EVT_UEVENT:
5007 qla2x00_uevent_emit(vha, e->u.uevent.code);
5008 break;
8ae6d9c7
GM		 5009 case QLA_EVT_AENFX:
5010 qlafx00_process_aen(vha, e);
5011 break;
726b8548
QT		 5012 case QLA_EVT_GIDPN:
5013 qla24xx_async_gidpn(vha, e->u.fcport.fcport);
5014 break;
5015 case QLA_EVT_GPNID:
5016 qla24xx_async_gpnid(vha, &e->u.gpnid.id);
5017 break;
e374f9f5
QT		 5018 case QLA_EVT_UNMAP:
5019 qla24xx_sp_unmap(vha, e->u.iosb.sp);
726b8548 5020 break;
9b3e0f4d
QT		 5021 case QLA_EVT_RELOGIN:
5022 qla2x00_relogin(vha);
5023 break;
726b8548
QT		 5024 case QLA_EVT_NEW_SESS:
5025 qla24xx_create_new_sess(vha, e);
5026 break;
5027 case QLA_EVT_GPDB:
5028 qla24xx_async_gpdb(vha, e->u.fcport.fcport,
5029 e->u.fcport.opt);
5030 break;
a5d42f4c
DG		 5031 case QLA_EVT_PRLI:
5032 qla24xx_async_prli(vha, e->u.fcport.fcport);
5033 break;
726b8548
QT		 5034 case QLA_EVT_GPSC:
5035 qla24xx_async_gpsc(vha, e->u.fcport.fcport);
5036 break;
726b8548
QT		 5037 case QLA_EVT_GNL:
5038 qla24xx_async_gnl(vha, e->u.fcport.fcport);
5039 break;
5040 case QLA_EVT_NACK:
5041 qla24xx_do_nack_work(vha, e);
5042 break;
11aea16a
QT		 5043 case QLA_EVT_ASYNC_PRLO:
5044 qla2x00_async_prlo(vha, e->u.logio.fcport);
5045 break;
5046 case QLA_EVT_ASYNC_PRLO_DONE:
5047 qla2x00_async_prlo_done(vha, e->u.logio.fcport,
5048 e->u.logio.data);
5049 break;
a4239945 5050 case QLA_EVT_GPNFT:
33b28357
QT		 5051 qla24xx_async_gpnft(vha, e->u.gpnft.fc4_type,
5052 e->u.gpnft.sp);
a4239945
QT		 5053 break;
5054 case QLA_EVT_GPNFT_DONE:
5055 qla24xx_async_gpnft_done(vha, e->u.iosb.sp);
5056 break;
5057 case QLA_EVT_GNNFT_DONE:
5058 qla24xx_async_gnnft_done(vha, e->u.iosb.sp);
5059 break;
5060 case QLA_EVT_GNNID:
5061 qla24xx_async_gnnid(vha, e->u.fcport.fcport);
5062 break;
5063 case QLA_EVT_GFPNID:
5064 qla24xx_async_gfpnid(vha, e->u.fcport.fcport);
5065 break;
e374f9f5
QT		 5066 case QLA_EVT_SP_RETRY:
5067 qla_sp_retry(vha, e);
cc28e0ac
QT		 5068 break;
5069 case QLA_EVT_IIDMA:
5070 qla_do_iidma_work(vha, e->u.fcport.fcport);
5071 break;
8777e431
QT		 5072 case QLA_EVT_ELS_PLOGI:
5073 qla24xx_els_dcmd2_iocb(vha, ELS_DCMD_PLOGI,
5074 e->u.fcport.fcport, false);
5075 break;
0971de7f
AV		 5076 }
5077 if (e->flags & QLA_EVT_FLAG_FREE)
5078 kfree(e);
feafb7b1
AE		 5079
5080 /* For each work completed decrement vha ref count */
5081 QLA_VHA_MARK_NOT_BUSY(vha);
e315cd28 5082 }
e315cd28 5083}
f999f4c1 5084
9b3e0f4d
QT		 5085int qla24xx_post_relogin_work(struct scsi_qla_host *vha)
5086{
5087 struct qla_work_evt *e;
5088
5089 e = qla2x00_alloc_work(vha, QLA_EVT_RELOGIN);
5090
5091 if (!e) {
5092 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
5093 return QLA_FUNCTION_FAILED;
5094 }
5095
5096 return qla2x00_post_work(vha, e);
5097}
5098
e315cd28
AC		 5099/* Relogins all the fcports of a vport
5100 * Context: dpc thread
5101 */
5102void qla2x00_relogin(struct scsi_qla_host *vha)
5103{
5104 fc_port_t *fcport;
23dd98a6 5105 int status, relogin_needed = 0;
726b8548 5106 struct event_arg ea;
e315cd28
AC		 5107
5108 list_for_each_entry(fcport, &vha->vp_fcports, list) {
9cd883f0
QT		 5109 /*
5110 * If the port is not ONLINE then try to login
5111 * to it if we haven't run out of retries.
5112 */
5ff1d584 5113 if (atomic_read(&fcport->state) != FCS_ONLINE &&
23dd98a6
QT		 5114 fcport->login_retry) {
5115 if (fcport->scan_state != QLA_FCPORT_FOUND ||
5116 fcport->disc_state == DSC_LOGIN_COMPLETE)
5117 continue;
e315cd28 5118
23dd98a6
QT		 5119 if (fcport->flags & (FCF_ASYNC_SENT|FCF_ASYNC_ACTIVE) ||
5120 fcport->disc_state == DSC_DELETE_PEND) {
5121 relogin_needed = 1;
5122 } else {
5123 if (vha->hw->current_topology != ISP_CFG_NL) {
5124 memset(&ea, 0, sizeof(ea));
5125 ea.event = FCME_RELOGIN;
5126 ea.fcport = fcport;
5127 qla2x00_fcport_event_handler(vha, &ea);
5128 } else if (vha->hw->current_topology ==
5129 ISP_CFG_NL) {
5130 fcport->login_retry--;
5131 status =
5132 qla2x00_local_device_login(vha,
5133 fcport);
5134 if (status == QLA_SUCCESS) {
5135 fcport->old_loop_id =
5136 fcport->loop_id;
5137 ql_dbg(ql_dbg_disc, vha, 0x2003,
5138 "Port login OK: logged in ID 0x%x.\n",
5139 fcport->loop_id);
5140 qla2x00_update_fcport
5141 (vha, fcport);
5142 } else if (status == 1) {
5143 set_bit(RELOGIN_NEEDED,
5144 &vha->dpc_flags);
5145 /* retry the login again */
5146 ql_dbg(ql_dbg_disc, vha, 0x2007,
5147 "Retrying %d login again loop_id 0x%x.\n",
5148 fcport->login_retry,
5149 fcport->loop_id);
5150 } else {
5151 fcport->login_retry = 0;
5152 }
e315cd28 5153
23dd98a6
QT		 5154 if (fcport->login_retry == 0 &&
5155 status != QLA_SUCCESS)
5156 qla2x00_clear_loop_id(fcport);
5157 }
e315cd28 5158 }
e315cd28
AC		 5159 }
5160 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
5161 break;
0971de7f 5162 }
9b3e0f4d 5163
23dd98a6
QT		 5164 if (relogin_needed)
5165 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
5166
9b3e0f4d
QT		 5167 ql_dbg(ql_dbg_disc, vha, 0x400e,
5168 "Relogin end.\n");
0971de7f
AV		 5169}
5170
7d613ac6
SV		 5171/* Schedule work on any of the dpc-workqueues */
5172void
5173qla83xx_schedule_work(scsi_qla_host_t *base_vha, int work_code)
5174{
5175 struct qla_hw_data *ha = base_vha->hw;
5176
5177 switch (work_code) {
5178 case MBA_IDC_AEN: /* 0x8200 */
5179 if (ha->dpc_lp_wq)
5180 queue_work(ha->dpc_lp_wq, &ha->idc_aen);
5181 break;
5182
5183 case QLA83XX_NIC_CORE_RESET: /* 0x1 */
5184 if (!ha->flags.nic_core_reset_hdlr_active) {
5185 if (ha->dpc_hp_wq)
5186 queue_work(ha->dpc_hp_wq, &ha->nic_core_reset);
5187 } else
5188 ql_dbg(ql_dbg_p3p, base_vha, 0xb05e,
5189 "NIC Core reset is already active. Skip "
5190 "scheduling it again.\n");
5191 break;
5192 case QLA83XX_IDC_STATE_HANDLER: /* 0x2 */
5193 if (ha->dpc_hp_wq)
5194 queue_work(ha->dpc_hp_wq, &ha->idc_state_handler);
5195 break;
5196 case QLA83XX_NIC_CORE_UNRECOVERABLE: /* 0x3 */
5197 if (ha->dpc_hp_wq)
5198 queue_work(ha->dpc_hp_wq, &ha->nic_core_unrecoverable);
5199 break;
5200 default:
5201 ql_log(ql_log_warn, base_vha, 0xb05f,
d939be3a 5202 "Unknown work-code=0x%x.\n", work_code);
7d613ac6
SV		 5203 }
5204
5205 return;
5206}
5207
5208/* Work: Perform NIC Core Unrecoverable state handling */
5209void
5210qla83xx_nic_core_unrecoverable_work(struct work_struct *work)
5211{
5212 struct qla_hw_data *ha =
2ad1b67c 5213 container_of(work, struct qla_hw_data, nic_core_unrecoverable);
7d613ac6
SV		 5214 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5215 uint32_t dev_state = 0;
5216
5217 qla83xx_idc_lock(base_vha, 0);
5218 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
5219 qla83xx_reset_ownership(base_vha);
5220 if (ha->flags.nic_core_reset_owner) {
5221 ha->flags.nic_core_reset_owner = 0;
5222 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
5223 QLA8XXX_DEV_FAILED);
5224 ql_log(ql_log_info, base_vha, 0xb060, "HW State: FAILED.\n");
5225 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
5226 }
5227 qla83xx_idc_unlock(base_vha, 0);
5228}
5229
5230/* Work: Execute IDC state handler */
5231void
5232qla83xx_idc_state_handler_work(struct work_struct *work)
5233{
5234 struct qla_hw_data *ha =
2ad1b67c 5235 container_of(work, struct qla_hw_data, idc_state_handler);
7d613ac6
SV		 5236 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5237 uint32_t dev_state = 0;
5238
5239 qla83xx_idc_lock(base_vha, 0);
5240 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
5241 if (dev_state == QLA8XXX_DEV_FAILED ||
5242 dev_state == QLA8XXX_DEV_NEED_QUIESCENT)
5243 qla83xx_idc_state_handler(base_vha);
5244 qla83xx_idc_unlock(base_vha, 0);
5245}
5246
fa492630 5247static int
7d613ac6
SV		 5248qla83xx_check_nic_core_fw_alive(scsi_qla_host_t *base_vha)
5249{
5250 int rval = QLA_SUCCESS;
5251 unsigned long heart_beat_wait = jiffies + (1 * HZ);
5252 uint32_t heart_beat_counter1, heart_beat_counter2;
5253
5254 do {
5255 if (time_after(jiffies, heart_beat_wait)) {
5256 ql_dbg(ql_dbg_p3p, base_vha, 0xb07c,
5257 "Nic Core f/w is not alive.\n");
5258 rval = QLA_FUNCTION_FAILED;
5259 break;
5260 }
5261
5262 qla83xx_idc_lock(base_vha, 0);
5263 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
5264 &heart_beat_counter1);
5265 qla83xx_idc_unlock(base_vha, 0);
5266 msleep(100);
5267 qla83xx_idc_lock(base_vha, 0);
5268 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
5269 &heart_beat_counter2);
5270 qla83xx_idc_unlock(base_vha, 0);
5271 } while (heart_beat_counter1 == heart_beat_counter2);
5272
5273 return rval;
5274}
5275
5276/* Work: Perform NIC Core Reset handling */
5277void
5278qla83xx_nic_core_reset_work(struct work_struct *work)
5279{
5280 struct qla_hw_data *ha =
5281 container_of(work, struct qla_hw_data, nic_core_reset);
5282 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5283 uint32_t dev_state = 0;
5284
81178772
SK		 5285 if (IS_QLA2031(ha)) {
5286 if (qla2xxx_mctp_dump(base_vha) != QLA_SUCCESS)
5287 ql_log(ql_log_warn, base_vha, 0xb081,
5288 "Failed to dump mctp\n");
5289 return;
5290 }
5291
7d613ac6
SV		 5292 if (!ha->flags.nic_core_reset_hdlr_active) {
5293 if (qla83xx_check_nic_core_fw_alive(base_vha) == QLA_SUCCESS) {
5294 qla83xx_idc_lock(base_vha, 0);
5295 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE,
5296 &dev_state);
5297 qla83xx_idc_unlock(base_vha, 0);
5298 if (dev_state != QLA8XXX_DEV_NEED_RESET) {
5299 ql_dbg(ql_dbg_p3p, base_vha, 0xb07a,
5300 "Nic Core f/w is alive.\n");
5301 return;
5302 }
5303 }
5304
5305 ha->flags.nic_core_reset_hdlr_active = 1;
5306 if (qla83xx_nic_core_reset(base_vha)) {
5307 /* NIC Core reset failed. */
5308 ql_dbg(ql_dbg_p3p, base_vha, 0xb061,
5309 "NIC Core reset failed.\n");
5310 }
5311 ha->flags.nic_core_reset_hdlr_active = 0;
5312 }
5313}
5314
5315/* Work: Handle 8200 IDC aens */
5316void
5317qla83xx_service_idc_aen(struct work_struct *work)
5318{
5319 struct qla_hw_data *ha =
5320 container_of(work, struct qla_hw_data, idc_aen);
5321 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5322 uint32_t dev_state, idc_control;
5323
5324 qla83xx_idc_lock(base_vha, 0);
5325 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
5326 qla83xx_rd_reg(base_vha, QLA83XX_IDC_CONTROL, &idc_control);
5327 qla83xx_idc_unlock(base_vha, 0);
5328 if (dev_state == QLA8XXX_DEV_NEED_RESET) {
5329 if (idc_control & QLA83XX_IDC_GRACEFUL_RESET) {
5330 ql_dbg(ql_dbg_p3p, base_vha, 0xb062,
5331 "Application requested NIC Core Reset.\n");
5332 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
5333 } else if (qla83xx_check_nic_core_fw_alive(base_vha) ==
5334 QLA_SUCCESS) {
5335 ql_dbg(ql_dbg_p3p, base_vha, 0xb07b,
5336 "Other protocol driver requested NIC Core Reset.\n");
5337 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
5338 }
5339 } else if (dev_state == QLA8XXX_DEV_FAILED ||
5340 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) {
5341 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
5342 }
5343}
5344
5345static void
5346qla83xx_wait_logic(void)
5347{
5348 int i;
5349
5350 /* Yield CPU */
5351 if (!in_interrupt()) {
5352 /*
5353 * Wait about 200ms before retrying again.
5354 * This controls the number of retries for single
5355 * lock operation.
5356 */
5357 msleep(100);
5358 schedule();
5359 } else {
5360 for (i = 0; i < 20; i++)
5361 cpu_relax(); /* This a nop instr on i386 */
5362 }
5363}
5364
fa492630 5365static int
7d613ac6
SV		 5366qla83xx_force_lock_recovery(scsi_qla_host_t *base_vha)
5367{
5368 int rval;
5369 uint32_t data;
5370 uint32_t idc_lck_rcvry_stage_mask = 0x3;
5371 uint32_t idc_lck_rcvry_owner_mask = 0x3c;
5372 struct qla_hw_data *ha = base_vha->hw;
6c315553
SK		 5373 ql_dbg(ql_dbg_p3p, base_vha, 0xb086,
5374 "Trying force recovery of the IDC lock.\n");
7d613ac6
SV		 5375
5376 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, &data);
5377 if (rval)
5378 return rval;
5379
5380 if ((data & idc_lck_rcvry_stage_mask) > 0) {
5381 return QLA_SUCCESS;
5382 } else {
5383 data = (IDC_LOCK_RECOVERY_STAGE1) | (ha->portnum << 2);
5384 rval = qla83xx_wr_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
5385 data);
5386 if (rval)
5387 return rval;
5388
5389 msleep(200);
5390
5391 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
5392 &data);
5393 if (rval)
5394 return rval;
5395
5396 if (((data & idc_lck_rcvry_owner_mask) >> 2) == ha->portnum) {
5397 data &= (IDC_LOCK_RECOVERY_STAGE2 |
5398 ~(idc_lck_rcvry_stage_mask));
5399 rval = qla83xx_wr_reg(base_vha,
5400 QLA83XX_IDC_LOCK_RECOVERY, data);
5401 if (rval)
5402 return rval;
5403
5404 /* Forcefully perform IDC UnLock */
5405 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK,
5406 &data);
5407 if (rval)
5408 return rval;
5409 /* Clear lock-id by setting 0xff */
5410 rval = qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
5411 0xff);
5412 if (rval)
5413 return rval;
5414 /* Clear lock-recovery by setting 0x0 */
5415 rval = qla83xx_wr_reg(base_vha,
5416 QLA83XX_IDC_LOCK_RECOVERY, 0x0);
5417 if (rval)
5418 return rval;
5419 } else
5420 return QLA_SUCCESS;
5421 }
5422
5423 return rval;
5424}
5425
fa492630 5426static int
7d613ac6
SV		 5427qla83xx_idc_lock_recovery(scsi_qla_host_t *base_vha)
5428{
5429 int rval = QLA_SUCCESS;
5430 uint32_t o_drv_lockid, n_drv_lockid;
5431 unsigned long lock_recovery_timeout;
5432
5433 lock_recovery_timeout = jiffies + QLA83XX_MAX_LOCK_RECOVERY_WAIT;
5434retry_lockid:
5435 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &o_drv_lockid);
5436 if (rval)
5437 goto exit;
5438
5439 /* MAX wait time before forcing IDC Lock recovery = 2 secs */
5440 if (time_after_eq(jiffies, lock_recovery_timeout)) {
5441 if (qla83xx_force_lock_recovery(base_vha) == QLA_SUCCESS)
5442 return QLA_SUCCESS;
5443 else
5444 return QLA_FUNCTION_FAILED;
5445 }
5446
5447 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &n_drv_lockid);
5448 if (rval)
5449 goto exit;
5450
5451 if (o_drv_lockid == n_drv_lockid) {
5452 qla83xx_wait_logic();
5453 goto retry_lockid;
5454 } else
5455 return QLA_SUCCESS;
5456
5457exit:
5458 return rval;
5459}
5460
5461void
5462qla83xx_idc_lock(scsi_qla_host_t *base_vha, uint16_t requester_id)
5463{
5464 uint16_t options = (requester_id << 15) | BIT_6;
5465 uint32_t data;
6c315553 5466 uint32_t lock_owner;
7d613ac6
SV		 5467 struct qla_hw_data *ha = base_vha->hw;
5468
5469 /* IDC-lock implementation using driver-lock/lock-id remote registers */
5470retry_lock:
5471 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCK, &data)
5472 == QLA_SUCCESS) {
5473 if (data) {
5474 /* Setting lock-id to our function-number */
5475 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
5476 ha->portnum);
5477 } else {
6c315553
SK		 5478 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID,
5479 &lock_owner);
7d613ac6 5480 ql_dbg(ql_dbg_p3p, base_vha, 0xb063,
6c315553
SK		 5481 "Failed to acquire IDC lock, acquired by %d, "
5482 "retrying...\n", lock_owner);
7d613ac6
SV		 5483
5484 /* Retry/Perform IDC-Lock recovery */
5485 if (qla83xx_idc_lock_recovery(base_vha)
5486 == QLA_SUCCESS) {
5487 qla83xx_wait_logic();
5488 goto retry_lock;
5489 } else
5490 ql_log(ql_log_warn, base_vha, 0xb075,
5491 "IDC Lock recovery FAILED.\n");
5492 }
5493
5494 }
5495
5496 return;
5497
5498 /* XXX: IDC-lock implementation using access-control mbx */
5499retry_lock2:
5500 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
5501 ql_dbg(ql_dbg_p3p, base_vha, 0xb072,
5502 "Failed to acquire IDC lock. retrying...\n");
5503 /* Retry/Perform IDC-Lock recovery */
5504 if (qla83xx_idc_lock_recovery(base_vha) == QLA_SUCCESS) {
5505 qla83xx_wait_logic();
5506 goto retry_lock2;
5507 } else
5508 ql_log(ql_log_warn, base_vha, 0xb076,
5509 "IDC Lock recovery FAILED.\n");
5510 }
5511
5512 return;
5513}
5514
5515void
5516qla83xx_idc_unlock(scsi_qla_host_t *base_vha, uint16_t requester_id)
5517{
5897cb2f
BVA		 5518#if 0
5519 uint16_t options = (requester_id << 15) | BIT_7;
5520#endif
5521 uint16_t retry;
7d613ac6
SV		 5522 uint32_t data;
5523 struct qla_hw_data *ha = base_vha->hw;
5524
5525 /* IDC-unlock implementation using driver-unlock/lock-id
5526 * remote registers
5527 */
5528 retry = 0;
5529retry_unlock:
5530 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &data)
5531 == QLA_SUCCESS) {
5532 if (data == ha->portnum) {
5533 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, &data);
5534 /* Clearing lock-id by setting 0xff */
5535 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 0xff);
5536 } else if (retry < 10) {
5537 /* SV: XXX: IDC unlock retrying needed here? */
5538
5539 /* Retry for IDC-unlock */
5540 qla83xx_wait_logic();
5541 retry++;
5542 ql_dbg(ql_dbg_p3p, base_vha, 0xb064,
ee6a8773 5543 "Failed to release IDC lock, retrying=%d\n", retry);
7d613ac6
SV		 5544 goto retry_unlock;
5545 }
5546 } else if (retry < 10) {
5547 /* Retry for IDC-unlock */
5548 qla83xx_wait_logic();
5549 retry++;
5550 ql_dbg(ql_dbg_p3p, base_vha, 0xb065,
ee6a8773 5551 "Failed to read drv-lockid, retrying=%d\n", retry);
7d613ac6
SV		 5552 goto retry_unlock;
5553 }
5554
5555 return;
5556
5897cb2f 5557#if 0
7d613ac6
SV		 5558 /* XXX: IDC-unlock implementation using access-control mbx */
5559 retry = 0;
5560retry_unlock2:
5561 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
5562 if (retry < 10) {
5563 /* Retry for IDC-unlock */
5564 qla83xx_wait_logic();
5565 retry++;
5566 ql_dbg(ql_dbg_p3p, base_vha, 0xb066,
ee6a8773 5567 "Failed to release IDC lock, retrying=%d\n", retry);
7d613ac6
SV		 5568 goto retry_unlock2;
5569 }
5570 }
5571
5572 return;
5897cb2f 5573#endif
7d613ac6
SV		 5574}
5575
5576int
5577__qla83xx_set_drv_presence(scsi_qla_host_t *vha)
5578{
5579 int rval = QLA_SUCCESS;
5580 struct qla_hw_data *ha = vha->hw;
5581 uint32_t drv_presence;
5582
5583 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
5584 if (rval == QLA_SUCCESS) {
5585 drv_presence |= (1 << ha->portnum);
5586 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
5587 drv_presence);
5588 }
5589
5590 return rval;
5591}
5592
5593int
5594qla83xx_set_drv_presence(scsi_qla_host_t *vha)
5595{
5596 int rval = QLA_SUCCESS;
5597
5598 qla83xx_idc_lock(vha, 0);
5599 rval = __qla83xx_set_drv_presence(vha);
5600 qla83xx_idc_unlock(vha, 0);
5601
5602 return rval;
5603}
5604
5605int
5606__qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
5607{
5608 int rval = QLA_SUCCESS;
5609 struct qla_hw_data *ha = vha->hw;
5610 uint32_t drv_presence;
5611
5612 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
5613 if (rval == QLA_SUCCESS) {
5614 drv_presence &= ~(1 << ha->portnum);
5615 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
5616 drv_presence);
5617 }
5618
5619 return rval;
5620}
5621
5622int
5623qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
5624{
5625 int rval = QLA_SUCCESS;
5626
5627 qla83xx_idc_lock(vha, 0);
5628 rval = __qla83xx_clear_drv_presence(vha);
5629 qla83xx_idc_unlock(vha, 0);
5630
5631 return rval;
5632}
5633
fa492630 5634static void
7d613ac6
SV		 5635qla83xx_need_reset_handler(scsi_qla_host_t *vha)
5636{
5637 struct qla_hw_data *ha = vha->hw;
5638 uint32_t drv_ack, drv_presence;
5639 unsigned long ack_timeout;
5640
5641 /* Wait for IDC ACK from all functions (DRV-ACK == DRV-PRESENCE) */
5642 ack_timeout = jiffies + (ha->fcoe_reset_timeout * HZ);
5643 while (1) {
5644 qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
5645 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
807fb6d8 5646 if ((drv_ack & drv_presence) == drv_presence)
7d613ac6
SV		 5647 break;
5648
5649 if (time_after_eq(jiffies, ack_timeout)) {
5650 ql_log(ql_log_warn, vha, 0xb067,
5651 "RESET ACK TIMEOUT! drv_presence=0x%x "
5652 "drv_ack=0x%x\n", drv_presence, drv_ack);
5653 /*
5654 * The function(s) which did not ack in time are forced
5655 * to withdraw any further participation in the IDC
5656 * reset.
5657 */
5658 if (drv_ack != drv_presence)
5659 qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
5660 drv_ack);
5661 break;
5662 }
5663
5664 qla83xx_idc_unlock(vha, 0);
5665 msleep(1000);
5666 qla83xx_idc_lock(vha, 0);
5667 }
5668
5669 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_COLD);
5670 ql_log(ql_log_info, vha, 0xb068, "HW State: COLD/RE-INIT.\n");
5671}
5672
fa492630 5673static int
7d613ac6
SV		 5674qla83xx_device_bootstrap(scsi_qla_host_t *vha)
5675{
5676 int rval = QLA_SUCCESS;
5677 uint32_t idc_control;
5678
5679 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_INITIALIZING);
5680 ql_log(ql_log_info, vha, 0xb069, "HW State: INITIALIZING.\n");
5681
5682 /* Clearing IDC-Control Graceful-Reset Bit before resetting f/w */
5683 __qla83xx_get_idc_control(vha, &idc_control);
5684 idc_control &= ~QLA83XX_IDC_GRACEFUL_RESET;
5685 __qla83xx_set_idc_control(vha, 0);
5686
5687 qla83xx_idc_unlock(vha, 0);
5688 rval = qla83xx_restart_nic_firmware(vha);
5689 qla83xx_idc_lock(vha, 0);
5690
5691 if (rval != QLA_SUCCESS) {
5692 ql_log(ql_log_fatal, vha, 0xb06a,
5693 "Failed to restart NIC f/w.\n");
5694 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_FAILED);
5695 ql_log(ql_log_info, vha, 0xb06b, "HW State: FAILED.\n");
5696 } else {
5697 ql_dbg(ql_dbg_p3p, vha, 0xb06c,
5698 "Success in restarting nic f/w.\n");
5699 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_READY);
5700 ql_log(ql_log_info, vha, 0xb06d, "HW State: READY.\n");
5701 }
5702
5703 return rval;
5704}
5705
5706/* Assumes idc_lock always held on entry */
5707int
5708qla83xx_idc_state_handler(scsi_qla_host_t *base_vha)
5709{
5710 struct qla_hw_data *ha = base_vha->hw;
5711 int rval = QLA_SUCCESS;
5712 unsigned long dev_init_timeout;
5713 uint32_t dev_state;
5714
5715 /* Wait for MAX-INIT-TIMEOUT for the device to go ready */
5716 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ);
5717
5718 while (1) {
5719
5720 if (time_after_eq(jiffies, dev_init_timeout)) {
5721 ql_log(ql_log_warn, base_vha, 0xb06e,
5722 "Initialization TIMEOUT!\n");
5723 /* Init timeout. Disable further NIC Core
5724 * communication.
5725 */
5726 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
5727 QLA8XXX_DEV_FAILED);
5728 ql_log(ql_log_info, base_vha, 0xb06f,
5729 "HW State: FAILED.\n");
5730 }
5731
5732 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
5733 switch (dev_state) {
5734 case QLA8XXX_DEV_READY:
5735 if (ha->flags.nic_core_reset_owner)
5736 qla83xx_idc_audit(base_vha,
5737 IDC_AUDIT_COMPLETION);
5738 ha->flags.nic_core_reset_owner = 0;
5739 ql_dbg(ql_dbg_p3p, base_vha, 0xb070,
5740 "Reset_owner reset by 0x%x.\n",
5741 ha->portnum);
5742 goto exit;
5743 case QLA8XXX_DEV_COLD:
5744 if (ha->flags.nic_core_reset_owner)
5745 rval = qla83xx_device_bootstrap(base_vha);
5746 else {
5747 /* Wait for AEN to change device-state */
5748 qla83xx_idc_unlock(base_vha, 0);
5749 msleep(1000);
5750 qla83xx_idc_lock(base_vha, 0);
5751 }
5752 break;
5753 case QLA8XXX_DEV_INITIALIZING:
5754 /* Wait for AEN to change device-state */
5755 qla83xx_idc_unlock(base_vha, 0);
5756 msleep(1000);
5757 qla83xx_idc_lock(base_vha, 0);
5758 break;
5759 case QLA8XXX_DEV_NEED_RESET:
5760 if (!ql2xdontresethba && ha->flags.nic_core_reset_owner)
5761 qla83xx_need_reset_handler(base_vha);
5762 else {
5763 /* Wait for AEN to change device-state */
5764 qla83xx_idc_unlock(base_vha, 0);
5765 msleep(1000);
5766 qla83xx_idc_lock(base_vha, 0);
5767 }
5768 /* reset timeout value after need reset handler */
5769 dev_init_timeout = jiffies +
5770 (ha->fcoe_dev_init_timeout * HZ);
5771 break;
5772 case QLA8XXX_DEV_NEED_QUIESCENT:
5773 /* XXX: DEBUG for now */
5774 qla83xx_idc_unlock(base_vha, 0);
5775 msleep(1000);
5776 qla83xx_idc_lock(base_vha, 0);
5777 break;
5778 case QLA8XXX_DEV_QUIESCENT:
5779 /* XXX: DEBUG for now */
5780 if (ha->flags.quiesce_owner)
5781 goto exit;
5782
5783 qla83xx_idc_unlock(base_vha, 0);
5784 msleep(1000);
5785 qla83xx_idc_lock(base_vha, 0);
5786 dev_init_timeout = jiffies +
5787 (ha->fcoe_dev_init_timeout * HZ);
5788 break;
5789 case QLA8XXX_DEV_FAILED:
5790 if (ha->flags.nic_core_reset_owner)
5791 qla83xx_idc_audit(base_vha,
5792 IDC_AUDIT_COMPLETION);
5793 ha->flags.nic_core_reset_owner = 0;
5794 __qla83xx_clear_drv_presence(base_vha);
5795 qla83xx_idc_unlock(base_vha, 0);
5796 qla8xxx_dev_failed_handler(base_vha);
5797 rval = QLA_FUNCTION_FAILED;
5798 qla83xx_idc_lock(base_vha, 0);
5799 goto exit;
5800 case QLA8XXX_BAD_VALUE:
5801 qla83xx_idc_unlock(base_vha, 0);
5802 msleep(1000);
5803 qla83xx_idc_lock(base_vha, 0);
5804 break;
5805 default:
5806 ql_log(ql_log_warn, base_vha, 0xb071,
d939be3a 5807 "Unknown Device State: %x.\n", dev_state);
7d613ac6
SV		 5808 qla83xx_idc_unlock(base_vha, 0);
5809 qla8xxx_dev_failed_handler(base_vha);
5810 rval = QLA_FUNCTION_FAILED;
5811 qla83xx_idc_lock(base_vha, 0);
5812 goto exit;
5813 }
5814 }
5815
5816exit:
5817 return rval;
5818}
5819
f3ddac19
CD		 5820void
5821qla2x00_disable_board_on_pci_error(struct work_struct *work)
5822{
5823 struct qla_hw_data *ha = container_of(work, struct qla_hw_data,
5824 board_disable);
5825 struct pci_dev *pdev = ha->pdev;
5826 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5827
726b8548
QT		 5828 /*
5829 * if UNLOAD flag is already set, then continue unload,
783e0dc4
SC		 5830 * where it was set first.
5831 */
5832 if (test_bit(UNLOADING, &base_vha->dpc_flags))
5833 return;
5834
f3ddac19
CD		 5835 ql_log(ql_log_warn, base_vha, 0x015b,
5836 "Disabling adapter.\n");
5837
efdb5760
SC		 5838 if (!atomic_read(&pdev->enable_cnt)) {
5839 ql_log(ql_log_info, base_vha, 0xfffc,
5840 "PCI device disabled, no action req for PCI error=%lx\n",
5841 base_vha->pci_flags);
5842 return;
5843 }
5844
726b8548
QT		 5845 qla2x00_wait_for_sess_deletion(base_vha);
5846
f3ddac19
CD		 5847 set_bit(UNLOADING, &base_vha->dpc_flags);
5848
5849 qla2x00_delete_all_vps(ha, base_vha);
5850
5851 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
5852
5853 qla2x00_dfs_remove(base_vha);
5854
5855 qla84xx_put_chip(base_vha);
5856
5857 if (base_vha->timer_active)
5858 qla2x00_stop_timer(base_vha);
5859
5860 base_vha->flags.online = 0;
5861
5862 qla2x00_destroy_deferred_work(ha);
5863
5864 /*
5865 * Do not try to stop beacon blink as it will issue a mailbox
5866 * command.
5867 */
5868 qla2x00_free_sysfs_attr(base_vha, false);
5869
5870 fc_remove_host(base_vha->host);
5871
5872 scsi_remove_host(base_vha->host);
5873
5874 base_vha->flags.init_done = 0;
5875 qla25xx_delete_queues(base_vha);
f3ddac19 5876 qla2x00_free_fcports(base_vha);
093df737 5877 qla2x00_free_irqs(base_vha);
f3ddac19
CD		 5878 qla2x00_mem_free(ha);
5879 qla82xx_md_free(base_vha);
5880 qla2x00_free_queues(ha);
5881
f3ddac19
CD		 5882 qla2x00_unmap_iobases(ha);
5883
5884 pci_release_selected_regions(ha->pdev, ha->bars);
f3ddac19
CD		 5885 pci_disable_pcie_error_reporting(pdev);
5886 pci_disable_device(pdev);
f3ddac19 5887
beb9e315
JL		 5888 /*
5889 * Let qla2x00_remove_one cleanup qla_hw_data on device removal.
5890 */
f3ddac19
CD		 5891}
5892
1da177e4
LT		 5893/**************************************************************************
5894* qla2x00_do_dpc
5895* This kernel thread is a task that is schedule by the interrupt handler
5896* to perform the background processing for interrupts.
5897*
5898* Notes:
5899* This task always run in the context of a kernel thread. It
5900* is kick-off by the driver's detect code and starts up
5901* up one per adapter. It immediately goes to sleep and waits for
5902* some fibre event. When either the interrupt handler or
5903* the timer routine detects a event it will one of the task
5904* bits then wake us up.
5905**************************************************************************/
5906static int
5907qla2x00_do_dpc(void *data)
5908{
e315cd28
AC		 5909 scsi_qla_host_t *base_vha;
5910 struct qla_hw_data *ha;
d7459527
MH		 5911 uint32_t online;
5912 struct qla_qpair *qpair;
1da177e4 5913
e315cd28
AC		 5914 ha = (struct qla_hw_data *)data;
5915 base_vha = pci_get_drvdata(ha->pdev);
1da177e4 5916
8698a745 5917 set_user_nice(current, MIN_NICE);
1da177e4 5918
563585ec 5919 set_current_state(TASK_INTERRUPTIBLE);
39a11240 5920 while (!kthread_should_stop()) {
7c3df132
SK		 5921 ql_dbg(ql_dbg_dpc, base_vha, 0x4000,
5922 "DPC handler sleeping.\n");
1da177e4 5923
39a11240 5924 schedule();
1da177e4 5925
c142caf0
AV		 5926 if (!base_vha->flags.init_done || ha->flags.mbox_busy)
5927 goto end_loop;
1da177e4 5928
85880801 5929 if (ha->flags.eeh_busy) {
7c3df132
SK		 5930 ql_dbg(ql_dbg_dpc, base_vha, 0x4003,
5931 "eeh_busy=%d.\n", ha->flags.eeh_busy);
c142caf0 5932 goto end_loop;
85880801
AV		 5933 }
5934
1da177e4
LT		 5935 ha->dpc_active = 1;
5936
5f28d2d7
SK		 5937 ql_dbg(ql_dbg_dpc + ql_dbg_verbose, base_vha, 0x4001,
5938 "DPC handler waking up, dpc_flags=0x%lx.\n",
5939 base_vha->dpc_flags);
1da177e4 5940
a29b3dd7
JC		 5941 if (test_bit(UNLOADING, &base_vha->dpc_flags))
5942 break;
5943
7ec0effd
AD		 5944 if (IS_P3P_TYPE(ha)) {
5945 if (IS_QLA8044(ha)) {
5946 if (test_and_clear_bit(ISP_UNRECOVERABLE,
5947 &base_vha->dpc_flags)) {
5948 qla8044_idc_lock(ha);
5949 qla8044_wr_direct(base_vha,
5950 QLA8044_CRB_DEV_STATE_INDEX,
5951 QLA8XXX_DEV_FAILED);
5952 qla8044_idc_unlock(ha);
5953 ql_log(ql_log_info, base_vha, 0x4004,
5954 "HW State: FAILED.\n");
5955 qla8044_device_state_handler(base_vha);
5956 continue;
5957 }
5958
5959 } else {
5960 if (test_and_clear_bit(ISP_UNRECOVERABLE,
5961 &base_vha->dpc_flags)) {
5962 qla82xx_idc_lock(ha);
5963 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
5964 QLA8XXX_DEV_FAILED);
5965 qla82xx_idc_unlock(ha);
5966 ql_log(ql_log_info, base_vha, 0x0151,
5967 "HW State: FAILED.\n");
5968 qla82xx_device_state_handler(base_vha);
5969 continue;
5970 }
a9083016
GM		 5971 }
5972
5973 if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED,
5974 &base_vha->dpc_flags)) {
5975
7c3df132
SK		 5976 ql_dbg(ql_dbg_dpc, base_vha, 0x4005,
5977 "FCoE context reset scheduled.\n");
a9083016
GM		 5978 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
5979 &base_vha->dpc_flags))) {
5980 if (qla82xx_fcoe_ctx_reset(base_vha)) {
5981 /* FCoE-ctx reset failed.
5982 * Escalate to chip-reset
5983 */
5984 set_bit(ISP_ABORT_NEEDED,
5985 &base_vha->dpc_flags);
5986 }
5987 clear_bit(ABORT_ISP_ACTIVE,
5988 &base_vha->dpc_flags);
5989 }
5990
7c3df132
SK		 5991 ql_dbg(ql_dbg_dpc, base_vha, 0x4006,
5992 "FCoE context reset end.\n");
a9083016 5993 }
8ae6d9c7
GM		 5994 } else if (IS_QLAFX00(ha)) {
5995 if (test_and_clear_bit(ISP_UNRECOVERABLE,
5996 &base_vha->dpc_flags)) {
5997 ql_dbg(ql_dbg_dpc, base_vha, 0x4020,
5998 "Firmware Reset Recovery\n");
5999 if (qlafx00_reset_initialize(base_vha)) {
6000 /* Failed. Abort isp later. */
6001 if (!test_bit(UNLOADING,
f92f82d6 6002 &base_vha->dpc_flags)) {
8ae6d9c7
GM		 6003 set_bit(ISP_UNRECOVERABLE,
6004 &base_vha->dpc_flags);
6005 ql_dbg(ql_dbg_dpc, base_vha,
6006 0x4021,
6007 "Reset Recovery Failed\n");
f92f82d6 6008 }
8ae6d9c7
GM		 6009 }
6010 }
6011
6012 if (test_and_clear_bit(FX00_TARGET_SCAN,
6013 &base_vha->dpc_flags)) {
6014 ql_dbg(ql_dbg_dpc, base_vha, 0x4022,
6015 "ISPFx00 Target Scan scheduled\n");
6016 if (qlafx00_rescan_isp(base_vha)) {
6017 if (!test_bit(UNLOADING,
6018 &base_vha->dpc_flags))
6019 set_bit(ISP_UNRECOVERABLE,
6020 &base_vha->dpc_flags);
6021 ql_dbg(ql_dbg_dpc, base_vha, 0x401e,
6022 "ISPFx00 Target Scan Failed\n");
6023 }
6024 ql_dbg(ql_dbg_dpc, base_vha, 0x401f,
6025 "ISPFx00 Target Scan End\n");
6026 }
e8f5e95d
AB		 6027 if (test_and_clear_bit(FX00_HOST_INFO_RESEND,
6028 &base_vha->dpc_flags)) {
6029 ql_dbg(ql_dbg_dpc, base_vha, 0x4023,
6030 "ISPFx00 Host Info resend scheduled\n");
6031 qlafx00_fx_disc(base_vha,
6032 &base_vha->hw->mr.fcport,
6033 FXDISC_REG_HOST_INFO);
6034 }
a9083016
GM		 6035 }
6036
e4e3a2ce
QT		 6037 if (test_and_clear_bit(DETECT_SFP_CHANGE,
6038 &base_vha->dpc_flags) &&
6039 !test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) {
6040 qla24xx_detect_sfp(base_vha);
6041
6042 if (ha->flags.detected_lr_sfp !=
6043 ha->flags.using_lr_setting)
6044 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
6045 }
6046
b08abbd9
QT		 6047 if (test_and_clear_bit
6048 (ISP_ABORT_NEEDED, &base_vha->dpc_flags) &&
6049 !test_bit(UNLOADING, &base_vha->dpc_flags)) {
93eca613
QT		 6050 bool do_reset = true;
6051
6052 switch (ql2x_ini_mode) {
6053 case QLA2XXX_INI_MODE_ENABLED:
6054 break;
6055 case QLA2XXX_INI_MODE_DISABLED:
6056 if (!qla_tgt_mode_enabled(base_vha))
6057 do_reset = false;
6058 break;
6059 case QLA2XXX_INI_MODE_DUAL:
6060 if (!qla_dual_mode_enabled(base_vha))
6061 do_reset = false;
6062 break;
6063 default:
6064 break;
6065 }
1da177e4 6066
93eca613 6067 if (do_reset && !(test_and_set_bit(ABORT_ISP_ACTIVE,
e315cd28 6068 &base_vha->dpc_flags))) {
93eca613
QT		 6069 ql_dbg(ql_dbg_dpc, base_vha, 0x4007,
6070 "ISP abort scheduled.\n");
a9083016 6071 if (ha->isp_ops->abort_isp(base_vha)) {
1da177e4
LT		 6072 /* failed. retry later */
6073 set_bit(ISP_ABORT_NEEDED,
e315cd28 6074 &base_vha->dpc_flags);
99363ef8 6075 }
e315cd28
AC		 6076 clear_bit(ABORT_ISP_ACTIVE,
6077 &base_vha->dpc_flags);
93eca613
QT		 6078 ql_dbg(ql_dbg_dpc, base_vha, 0x4008,
6079 "ISP abort end.\n");
99363ef8 6080 }
1da177e4
LT		 6081 }
6082
a394aac8
DJ		 6083 if (test_and_clear_bit(FCPORT_UPDATE_NEEDED,
6084 &base_vha->dpc_flags)) {
e315cd28 6085 qla2x00_update_fcports(base_vha);
c9c5ced9 6086 }
d97994dc 6087
8ae6d9c7
GM		 6088 if (IS_QLAFX00(ha))
6089 goto loop_resync_check;
6090
579d12b5 6091 if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) {
7c3df132
SK		 6092 ql_dbg(ql_dbg_dpc, base_vha, 0x4009,
6093 "Quiescence mode scheduled.\n");
7ec0effd
AD		 6094 if (IS_P3P_TYPE(ha)) {
6095 if (IS_QLA82XX(ha))
6096 qla82xx_device_state_handler(base_vha);
6097 if (IS_QLA8044(ha))
6098 qla8044_device_state_handler(base_vha);
8fcd6b8b
CD		 6099 clear_bit(ISP_QUIESCE_NEEDED,
6100 &base_vha->dpc_flags);
6101 if (!ha->flags.quiesce_owner) {
6102 qla2x00_perform_loop_resync(base_vha);
7ec0effd
AD		 6103 if (IS_QLA82XX(ha)) {
6104 qla82xx_idc_lock(ha);
6105 qla82xx_clear_qsnt_ready(
6106 base_vha);
6107 qla82xx_idc_unlock(ha);
6108 } else if (IS_QLA8044(ha)) {
6109 qla8044_idc_lock(ha);
6110 qla8044_clear_qsnt_ready(
6111 base_vha);
6112 qla8044_idc_unlock(ha);
6113 }
8fcd6b8b
CD		 6114 }
6115 } else {
6116 clear_bit(ISP_QUIESCE_NEEDED,
6117 &base_vha->dpc_flags);
6118 qla2x00_quiesce_io(base_vha);
579d12b5 6119 }
7c3df132
SK		 6120 ql_dbg(ql_dbg_dpc, base_vha, 0x400a,
6121 "Quiescence mode end.\n");
579d12b5
SK		 6122 }
6123
e315cd28 6124 if (test_and_clear_bit(RESET_MARKER_NEEDED,
8ae6d9c7 6125 &base_vha->dpc_flags) &&
e315cd28 6126 (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) {
1da177e4 6127
7c3df132
SK		 6128 ql_dbg(ql_dbg_dpc, base_vha, 0x400b,
6129 "Reset marker scheduled.\n");
e315cd28
AC		 6130 qla2x00_rst_aen(base_vha);
6131 clear_bit(RESET_ACTIVE, &base_vha->dpc_flags);
7c3df132
SK		 6132 ql_dbg(ql_dbg_dpc, base_vha, 0x400c,
6133 "Reset marker end.\n");
1da177e4
LT		 6134 }
6135
6136 /* Retry each device up to login retry count */
4005a995 6137 if (test_bit(RELOGIN_NEEDED, &base_vha->dpc_flags) &&
e315cd28
AC		 6138 !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) &&
6139 atomic_read(&base_vha->loop_state) != LOOP_DOWN) {
1da177e4 6140
4005a995
QT		 6141 if (!base_vha->relogin_jif ||
6142 time_after_eq(jiffies, base_vha->relogin_jif)) {
6143 base_vha->relogin_jif = jiffies + HZ;
6144 clear_bit(RELOGIN_NEEDED, &base_vha->dpc_flags);
6145
9b3e0f4d 6146 ql_dbg(ql_dbg_disc, base_vha, 0x400d,
4005a995 6147 "Relogin scheduled.\n");
9b3e0f4d 6148 qla24xx_post_relogin_work(base_vha);
4005a995 6149 }
1da177e4 6150 }
8ae6d9c7 6151loop_resync_check:
e315cd28 6152 if (test_and_clear_bit(LOOP_RESYNC_NEEDED,
8ae6d9c7 6153 &base_vha->dpc_flags)) {
1da177e4 6154
7c3df132
SK		 6155 ql_dbg(ql_dbg_dpc, base_vha, 0x400f,
6156 "Loop resync scheduled.\n");
1da177e4
LT		 6157
6158 if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE,
e315cd28 6159 &base_vha->dpc_flags))) {
1da177e4 6160
52c82823 6161 qla2x00_loop_resync(base_vha);
1da177e4 6162
e315cd28
AC		 6163 clear_bit(LOOP_RESYNC_ACTIVE,
6164 &base_vha->dpc_flags);
1da177e4
LT		 6165 }
6166
7c3df132
SK		 6167 ql_dbg(ql_dbg_dpc, base_vha, 0x4010,
6168 "Loop resync end.\n");
1da177e4
LT		 6169 }
6170
8ae6d9c7
GM		 6171 if (IS_QLAFX00(ha))
6172 goto intr_on_check;
6173
e315cd28
AC		 6174 if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) &&
6175 atomic_read(&base_vha->loop_state) == LOOP_READY) {
6176 clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags);
6177 qla2xxx_flash_npiv_conf(base_vha);
272976ca
AV		 6178 }
6179
8ae6d9c7 6180intr_on_check:
1da177e4 6181 if (!ha->interrupts_on)
fd34f556 6182 ha->isp_ops->enable_intrs(ha);
1da177e4 6183
e315cd28 6184 if (test_and_clear_bit(BEACON_BLINK_NEEDED,
90b604f2
HM		 6185 &base_vha->dpc_flags)) {
6186 if (ha->beacon_blink_led == 1)
6187 ha->isp_ops->beacon_blink(base_vha);
6188 }
f6df144c 6189
d7459527
MH		 6190 /* qpair online check */
6191 if (test_and_clear_bit(QPAIR_ONLINE_CHECK_NEEDED,
6192 &base_vha->dpc_flags)) {
6193 if (ha->flags.eeh_busy ||
6194 ha->flags.pci_channel_io_perm_failure)
6195 online = 0;
6196 else
6197 online = 1;
6198
6199 mutex_lock(&ha->mq_lock);
6200 list_for_each_entry(qpair, &base_vha->qp_list,
6201 qp_list_elem)
6202 qpair->online = online;
6203 mutex_unlock(&ha->mq_lock);
6204 }
6205
deeae7a6
DG		 6206 if (test_and_clear_bit(SET_ZIO_THRESHOLD_NEEDED, &base_vha->dpc_flags)) {
6207 ql_log(ql_log_info, base_vha, 0xffffff,
6208 "nvme: SET ZIO Activity exchange threshold to %d.\n",
6209 ha->nvme_last_rptd_aen);
6210 if (qla27xx_set_zio_threshold(base_vha, ha->nvme_last_rptd_aen)) {
6211 ql_log(ql_log_info, base_vha, 0xffffff,
6212 "nvme: Unable to SET ZIO Activity exchange threshold to %d.\n",
6213 ha->nvme_last_rptd_aen);
6214 }
6215 }
6216
8ae6d9c7
GM		 6217 if (!IS_QLAFX00(ha))
6218 qla2x00_do_dpc_all_vps(base_vha);
2c3dfe3f 6219
48acad09
QT		 6220 if (test_and_clear_bit(N2N_LINK_RESET,
6221 &base_vha->dpc_flags)) {
6222 qla2x00_lip_reset(base_vha);
6223 }
6224
1da177e4 6225 ha->dpc_active = 0;
c142caf0 6226end_loop:
563585ec 6227 set_current_state(TASK_INTERRUPTIBLE);
1da177e4 6228 } /* End of while(1) */
563585ec 6229 __set_current_state(TASK_RUNNING);
1da177e4 6230
7c3df132
SK		 6231 ql_dbg(ql_dbg_dpc, base_vha, 0x4011,
6232 "DPC handler exiting.\n");
1da177e4
LT		 6233
6234 /*
6235 * Make sure that nobody tries to wake us up again.
6236 */
1da177e4
LT		 6237 ha->dpc_active = 0;
6238
ac280b67
AV		 6239 /* Cleanup any residual CTX SRBs. */
6240 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
6241
39a11240
CH		 6242 return 0;
6243}
6244
6245void
e315cd28 6246qla2xxx_wake_dpc(struct scsi_qla_host *vha)
39a11240 6247{
e315cd28 6248 struct qla_hw_data *ha = vha->hw;
c795c1e4
AV		 6249 struct task_struct *t = ha->dpc_thread;
6250
e315cd28 6251 if (!test_bit(UNLOADING, &vha->dpc_flags) && t)
c795c1e4 6252 wake_up_process(t);
1da177e4
LT		 6253}
6254
1da177e4
LT		 6255/*
6256* qla2x00_rst_aen
6257* Processes asynchronous reset.
6258*
6259* Input:
6260* ha = adapter block pointer.
6261*/
6262static void
e315cd28 6263qla2x00_rst_aen(scsi_qla_host_t *vha)
1da177e4 6264{
e315cd28
AC		 6265 if (vha->flags.online && !vha->flags.reset_active &&
6266 !atomic_read(&vha->loop_down_timer) &&
6267 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) {
1da177e4 6268 do {
e315cd28 6269 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
1da177e4
LT		 6270
6271 /*
6272 * Issue marker command only when we are going to start
6273 * the I/O.
6274 */
e315cd28
AC		 6275 vha->marker_needed = 1;
6276 } while (!atomic_read(&vha->loop_down_timer) &&
6277 (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)));
1da177e4
LT		 6278 }
6279}
6280
1da177e4
LT		 6281/**************************************************************************
6282* qla2x00_timer
6283*
6284* Description:
6285* One second timer
6286*
6287* Context: Interrupt
6288***************************************************************************/
2c3dfe3f 6289void
8e5f4ba0 6290qla2x00_timer(struct timer_list *t)
1da177e4 6291{
8e5f4ba0 6292 scsi_qla_host_t *vha = from_timer(vha, t, timer);
1da177e4 6293 unsigned long cpu_flags = 0;
1da177e4
LT		 6294 int start_dpc = 0;
6295 int index;
6296 srb_t *sp;
85880801 6297 uint16_t w;
e315cd28 6298 struct qla_hw_data *ha = vha->hw;
73208dfd 6299 struct req_que *req;
85880801 6300
a5b36321 6301 if (ha->flags.eeh_busy) {
7c3df132
SK		 6302 ql_dbg(ql_dbg_timer, vha, 0x6000,
6303 "EEH = %d, restarting timer.\n",
6304 ha->flags.eeh_busy);
a5b36321
LC		 6305 qla2x00_restart_timer(vha, WATCH_INTERVAL);
6306 return;
6307 }
6308
f3ddac19
CD		 6309 /*
6310 * Hardware read to raise pending EEH errors during mailbox waits. If
6311 * the read returns -1 then disable the board.
6312 */
6313 if (!pci_channel_offline(ha->pdev)) {
85880801 6314 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w);
c821e0d5 6315 qla2x00_check_reg16_for_disconnect(vha, w);
f3ddac19 6316 }
1da177e4 6317
cefcaba6 6318 /* Make sure qla82xx_watchdog is run only for physical port */
7ec0effd 6319 if (!vha->vp_idx && IS_P3P_TYPE(ha)) {
579d12b5
SK		 6320 if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags))
6321 start_dpc++;
7ec0effd
AD		 6322 if (IS_QLA82XX(ha))
6323 qla82xx_watchdog(vha);
6324 else if (IS_QLA8044(ha))
6325 qla8044_watchdog(vha);
579d12b5
SK		 6326 }
6327
8ae6d9c7
GM		 6328 if (!vha->vp_idx && IS_QLAFX00(ha))
6329 qlafx00_timer_routine(vha);
6330
1da177e4 6331 /* Loop down handler. */
e315cd28 6332 if (atomic_read(&vha->loop_down_timer) > 0 &&
8f7daead
GM		 6333 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) &&
6334 !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags))
e315cd28 6335 && vha->flags.online) {
1da177e4 6336
e315cd28
AC		 6337 if (atomic_read(&vha->loop_down_timer) ==
6338 vha->loop_down_abort_time) {
1da177e4 6339
7c3df132
SK		 6340 ql_log(ql_log_info, vha, 0x6008,
6341 "Loop down - aborting the queues before time expires.\n");
1da177e4 6342
e315cd28
AC		 6343 if (!IS_QLA2100(ha) && vha->link_down_timeout)
6344 atomic_set(&vha->loop_state, LOOP_DEAD);
1da177e4 6345
f08b7251
AV		 6346 /*
6347 * Schedule an ISP abort to return any FCP2-device
6348 * commands.
6349 */
2c3dfe3f 6350 /* NPIV - scan physical port only */
e315cd28 6351 if (!vha->vp_idx) {
2c3dfe3f
SJ		 6352 spin_lock_irqsave(&ha->hardware_lock,
6353 cpu_flags);
73208dfd 6354 req = ha->req_q_map[0];
2c3dfe3f 6355 for (index = 1;
8d93f550 6356 index < req->num_outstanding_cmds;
2c3dfe3f
SJ		 6357 index++) {
6358 fc_port_t *sfcp;
6359
e315cd28 6360 sp = req->outstanding_cmds[index];
2c3dfe3f
SJ		 6361 if (!sp)
6362 continue;
c5419e26
QT		 6363 if (sp->cmd_type != TYPE_SRB)
6364 continue;
9ba56b95 6365 if (sp->type != SRB_SCSI_CMD)
cf53b069 6366 continue;
2c3dfe3f 6367 sfcp = sp->fcport;
f08b7251 6368 if (!(sfcp->flags & FCF_FCP2_DEVICE))
2c3dfe3f 6369 continue;
bdf79621 6370
8f7daead
GM		 6371 if (IS_QLA82XX(ha))
6372 set_bit(FCOE_CTX_RESET_NEEDED,
6373 &vha->dpc_flags);
6374 else
6375 set_bit(ISP_ABORT_NEEDED,
e315cd28 6376 &vha->dpc_flags);
2c3dfe3f
SJ		 6377 break;
6378 }
6379 spin_unlock_irqrestore(&ha->hardware_lock,
e315cd28 6380 cpu_flags);
1da177e4 6381 }
1da177e4
LT		 6382 start_dpc++;
6383 }
6384
6385 /* if the loop has been down for 4 minutes, reinit adapter */
e315cd28 6386 if (atomic_dec_and_test(&vha->loop_down_timer) != 0) {
0d6e61bc 6387 if (!(vha->device_flags & DFLG_NO_CABLE)) {
7c3df132 6388 ql_log(ql_log_warn, vha, 0x6009,
1da177e4
LT		 6389 "Loop down - aborting ISP.\n");
6390
8f7daead
GM		 6391 if (IS_QLA82XX(ha))
6392 set_bit(FCOE_CTX_RESET_NEEDED,
6393 &vha->dpc_flags);
6394 else
6395 set_bit(ISP_ABORT_NEEDED,
6396 &vha->dpc_flags);
1da177e4
LT		 6397 }
6398 }
7c3df132
SK		 6399 ql_dbg(ql_dbg_timer, vha, 0x600a,
6400 "Loop down - seconds remaining %d.\n",
6401 atomic_read(&vha->loop_down_timer));
1da177e4 6402 }
cefcaba6
SK		 6403 /* Check if beacon LED needs to be blinked for physical host only */
6404 if (!vha->vp_idx && (ha->beacon_blink_led == 1)) {
999916dc 6405 /* There is no beacon_blink function for ISP82xx */
7ec0effd 6406 if (!IS_P3P_TYPE(ha)) {
999916dc
SK		 6407 set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags);
6408 start_dpc++;
6409 }
f6df144c 6410 }
6411
550bf57d 6412 /* Process any deferred work. */
9b3e0f4d
QT		 6413 if (!list_empty(&vha->work_list)) {
6414 unsigned long flags;
6415 bool q = false;
6416
6417 spin_lock_irqsave(&vha->work_lock, flags);
6418 if (!test_and_set_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags))
6419 q = true;
6420 spin_unlock_irqrestore(&vha->work_lock, flags);
6421 if (q)
6422 queue_work(vha->hw->wq, &vha->iocb_work);
6423 }
550bf57d 6424
7401bc18
DG		 6425 /*
6426 * FC-NVME
6427 * see if the active AEN count has changed from what was last reported.
6428 */
deeae7a6
DG		 6429 if (!vha->vp_idx &&
6430 atomic_read(&ha->nvme_active_aen_cnt) != ha->nvme_last_rptd_aen &&
6431 ha->zio_mode == QLA_ZIO_MODE_6) {
7401bc18 6432 ql_log(ql_log_info, vha, 0x3002,
deeae7a6
DG		 6433 "nvme: Sched: Set ZIO exchange threshold to %d.\n",
6434 ha->nvme_last_rptd_aen);
6435 ha->nvme_last_rptd_aen = atomic_read(&ha->nvme_active_aen_cnt);
6436 set_bit(SET_ZIO_THRESHOLD_NEEDED, &vha->dpc_flags);
6437 start_dpc++;
7401bc18
DG		 6438 }
6439
1da177e4 6440 /* Schedule the DPC routine if needed */
e315cd28
AC		 6441 if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) ||
6442 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) ||
6443 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags) ||
1da177e4 6444 start_dpc ||
e315cd28
AC		 6445 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) ||
6446 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) ||
a9083016
GM		 6447 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) ||
6448 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) ||
e315cd28 6449 test_bit(VP_DPC_NEEDED, &vha->dpc_flags) ||
50280c01 6450 test_bit(RELOGIN_NEEDED, &vha->dpc_flags))) {
7c3df132
SK		 6451 ql_dbg(ql_dbg_timer, vha, 0x600b,
6452 "isp_abort_needed=%d loop_resync_needed=%d "
6453 "fcport_update_needed=%d start_dpc=%d "
6454 "reset_marker_needed=%d",
6455 test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags),
6456 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags),
6457 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags),
6458 start_dpc,
6459 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags));
6460 ql_dbg(ql_dbg_timer, vha, 0x600c,
6461 "beacon_blink_needed=%d isp_unrecoverable=%d "
6462 "fcoe_ctx_reset_needed=%d vp_dpc_needed=%d "
50280c01 6463 "relogin_needed=%d.\n",
7c3df132
SK		 6464 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags),
6465 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags),
6466 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags),
6467 test_bit(VP_DPC_NEEDED, &vha->dpc_flags),
50280c01 6468 test_bit(RELOGIN_NEEDED, &vha->dpc_flags));
e315cd28 6469 qla2xxx_wake_dpc(vha);
7c3df132 6470 }
1da177e4 6471
e315cd28 6472 qla2x00_restart_timer(vha, WATCH_INTERVAL);
1da177e4
LT		 6473}
6474
5433383e
AV		 6475/* Firmware interface routines. */
6476
f73cb695 6477#define FW_BLOBS 11
5433383e
AV		 6478#define FW_ISP21XX 0
6479#define FW_ISP22XX 1
6480#define FW_ISP2300 2
6481#define FW_ISP2322 3
48c02fde 6482#define FW_ISP24XX 4
c3a2f0df 6483#define FW_ISP25XX 5
3a03eb79 6484#define FW_ISP81XX 6
a9083016 6485#define FW_ISP82XX 7
6246b8a1
GM		 6486#define FW_ISP2031 8
6487#define FW_ISP8031 9
2c5bbbb2 6488#define FW_ISP27XX 10
5433383e 6489
bb8ee499
AV		 6490#define FW_FILE_ISP21XX "ql2100_fw.bin"
6491#define FW_FILE_ISP22XX "ql2200_fw.bin"
6492#define FW_FILE_ISP2300 "ql2300_fw.bin"
6493#define FW_FILE_ISP2322 "ql2322_fw.bin"
6494#define FW_FILE_ISP24XX "ql2400_fw.bin"
c3a2f0df 6495#define FW_FILE_ISP25XX "ql2500_fw.bin"
3a03eb79 6496#define FW_FILE_ISP81XX "ql8100_fw.bin"
a9083016 6497#define FW_FILE_ISP82XX "ql8200_fw.bin"
6246b8a1
GM		 6498#define FW_FILE_ISP2031 "ql2600_fw.bin"
6499#define FW_FILE_ISP8031 "ql8300_fw.bin"
2c5bbbb2 6500#define FW_FILE_ISP27XX "ql2700_fw.bin"
f73cb695 6501
bb8ee499 6502
e1e82b6f 6503static DEFINE_MUTEX(qla_fw_lock);
5433383e
AV		 6504
6505static struct fw_blob qla_fw_blobs[FW_BLOBS] = {
bb8ee499
AV		 6506 { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, },
6507 { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, },
6508 { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, },
6509 { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, },
6510 { .name = FW_FILE_ISP24XX, },
c3a2f0df 6511 { .name = FW_FILE_ISP25XX, },
3a03eb79 6512 { .name = FW_FILE_ISP81XX, },
a9083016 6513 { .name = FW_FILE_ISP82XX, },
6246b8a1
GM		 6514 { .name = FW_FILE_ISP2031, },
6515 { .name = FW_FILE_ISP8031, },
2c5bbbb2 6516 { .name = FW_FILE_ISP27XX, },
5433383e
AV		 6517};
6518
6519struct fw_blob *
e315cd28 6520qla2x00_request_firmware(scsi_qla_host_t *vha)
5433383e 6521{
e315cd28 6522 struct qla_hw_data *ha = vha->hw;
5433383e
AV		 6523 struct fw_blob *blob;
6524
5433383e
AV		 6525 if (IS_QLA2100(ha)) {
6526 blob = &qla_fw_blobs[FW_ISP21XX];
6527 } else if (IS_QLA2200(ha)) {
6528 blob = &qla_fw_blobs[FW_ISP22XX];
48c02fde 6529 } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
5433383e 6530 blob = &qla_fw_blobs[FW_ISP2300];
48c02fde 6531 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
5433383e 6532 blob = &qla_fw_blobs[FW_ISP2322];
4d4df193 6533 } else if (IS_QLA24XX_TYPE(ha)) {
5433383e 6534 blob = &qla_fw_blobs[FW_ISP24XX];
c3a2f0df
AV		 6535 } else if (IS_QLA25XX(ha)) {
6536 blob = &qla_fw_blobs[FW_ISP25XX];
3a03eb79
AV		 6537 } else if (IS_QLA81XX(ha)) {
6538 blob = &qla_fw_blobs[FW_ISP81XX];
a9083016
GM		 6539 } else if (IS_QLA82XX(ha)) {
6540 blob = &qla_fw_blobs[FW_ISP82XX];
6246b8a1
GM		 6541 } else if (IS_QLA2031(ha)) {
6542 blob = &qla_fw_blobs[FW_ISP2031];
6543 } else if (IS_QLA8031(ha)) {
6544 blob = &qla_fw_blobs[FW_ISP8031];
2c5bbbb2
JC		 6545 } else if (IS_QLA27XX(ha)) {
6546 blob = &qla_fw_blobs[FW_ISP27XX];
8a655229
DC		 6547 } else {
6548 return NULL;
5433383e
AV		 6549 }
6550
e1e82b6f 6551 mutex_lock(&qla_fw_lock);
5433383e
AV		 6552 if (blob->fw)
6553 goto out;
6554
6555 if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) {
7c3df132
SK		 6556 ql_log(ql_log_warn, vha, 0x0063,
6557 "Failed to load firmware image (%s).\n", blob->name);
5433383e
AV		 6558 blob->fw = NULL;
6559 blob = NULL;
6560 goto out;
6561 }
6562
6563out:
e1e82b6f 6564 mutex_unlock(&qla_fw_lock);
5433383e
AV		 6565 return blob;
6566}
6567
6568static void
6569qla2x00_release_firmware(void)
6570{
6571 int idx;
6572
e1e82b6f 6573 mutex_lock(&qla_fw_lock);
5433383e 6574 for (idx = 0; idx < FW_BLOBS; idx++)
cf92549f 6575 release_firmware(qla_fw_blobs[idx].fw);
e1e82b6f 6576 mutex_unlock(&qla_fw_lock);
5433383e
AV		 6577}
6578
14e660e6
SJ		 6579static pci_ers_result_t
6580qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
6581{
85880801
AV		 6582 scsi_qla_host_t *vha = pci_get_drvdata(pdev);
6583 struct qla_hw_data *ha = vha->hw;
6584
7c3df132
SK		 6585 ql_dbg(ql_dbg_aer, vha, 0x9000,
6586 "PCI error detected, state %x.\n", state);
b9b12f73 6587
efdb5760
SC		 6588 if (!atomic_read(&pdev->enable_cnt)) {
6589 ql_log(ql_log_info, vha, 0xffff,
6590 "PCI device is disabled,state %x\n", state);
6591 return PCI_ERS_RESULT_NEED_RESET;
6592 }
6593
14e660e6
SJ		 6594 switch (state) {
6595 case pci_channel_io_normal:
85880801 6596 ha->flags.eeh_busy = 0;
c38d1baf 6597 if (ql2xmqsupport || ql2xnvmeenable) {
d7459527
MH		 6598 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags);
6599 qla2xxx_wake_dpc(vha);
6600 }
14e660e6
SJ		 6601 return PCI_ERS_RESULT_CAN_RECOVER;
6602 case pci_channel_io_frozen:
85880801 6603 ha->flags.eeh_busy = 1;
a5b36321
LC		 6604 /* For ISP82XX complete any pending mailbox cmd */
6605 if (IS_QLA82XX(ha)) {
7190575f 6606 ha->flags.isp82xx_fw_hung = 1;
c8f6544e
CD		 6607 ql_dbg(ql_dbg_aer, vha, 0x9001, "Pci channel io frozen\n");
6608 qla82xx_clear_pending_mbx(vha);
a5b36321 6609 }
90a86fc0 6610 qla2x00_free_irqs(vha);
14e660e6 6611 pci_disable_device(pdev);
bddd2d65
LC		 6612 /* Return back all IOs */
6613 qla2x00_abort_all_cmds(vha, DID_RESET << 16);
c38d1baf 6614 if (ql2xmqsupport || ql2xnvmeenable) {
d7459527
MH		 6615 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags);
6616 qla2xxx_wake_dpc(vha);
6617 }
14e660e6
SJ		 6618 return PCI_ERS_RESULT_NEED_RESET;
6619 case pci_channel_io_perm_failure:
85880801
AV		 6620 ha->flags.pci_channel_io_perm_failure = 1;
6621 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
c38d1baf 6622 if (ql2xmqsupport || ql2xnvmeenable) {
d7459527
MH		 6623 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags);
6624 qla2xxx_wake_dpc(vha);
6625 }
14e660e6
SJ		 6626 return PCI_ERS_RESULT_DISCONNECT;
6627 }
6628 return PCI_ERS_RESULT_NEED_RESET;
6629}
6630
6631static pci_ers_result_t
6632qla2xxx_pci_mmio_enabled(struct pci_dev *pdev)
6633{
6634 int risc_paused = 0;
6635 uint32_t stat;
6636 unsigned long flags;
e315cd28
AC		 6637 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
6638 struct qla_hw_data *ha = base_vha->hw;
14e660e6
SJ		 6639 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
6640 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
6641
bcc5b6d3
SK		 6642 if (IS_QLA82XX(ha))
6643 return PCI_ERS_RESULT_RECOVERED;
6644
14e660e6
SJ		 6645 spin_lock_irqsave(&ha->hardware_lock, flags);
6646 if (IS_QLA2100(ha) || IS_QLA2200(ha)){
6647 stat = RD_REG_DWORD(&reg->hccr);
6648 if (stat & HCCR_RISC_PAUSE)
6649 risc_paused = 1;
6650 } else if (IS_QLA23XX(ha)) {
6651 stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
6652 if (stat & HSR_RISC_PAUSED)
6653 risc_paused = 1;
6654 } else if (IS_FWI2_CAPABLE(ha)) {
6655 stat = RD_REG_DWORD(&reg24->host_status);
6656 if (stat & HSRX_RISC_PAUSED)
6657 risc_paused = 1;
6658 }
6659 spin_unlock_irqrestore(&ha->hardware_lock, flags);
6660
6661 if (risc_paused) {
7c3df132
SK		 6662 ql_log(ql_log_info, base_vha, 0x9003,
6663 "RISC paused -- mmio_enabled, Dumping firmware.\n");
e315cd28 6664 ha->isp_ops->fw_dump(base_vha, 0);
14e660e6
SJ		 6665
6666 return PCI_ERS_RESULT_NEED_RESET;
6667 } else
6668 return PCI_ERS_RESULT_RECOVERED;
6669}
6670
fa492630
SK		 6671static uint32_t
6672qla82xx_error_recovery(scsi_qla_host_t *base_vha)
a5b36321
LC		 6673{
6674 uint32_t rval = QLA_FUNCTION_FAILED;
6675 uint32_t drv_active = 0;
6676 struct qla_hw_data *ha = base_vha->hw;
6677 int fn;
6678 struct pci_dev *other_pdev = NULL;
6679
7c3df132
SK		 6680 ql_dbg(ql_dbg_aer, base_vha, 0x9006,
6681 "Entered %s.\n", __func__);
a5b36321
LC		 6682
6683 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
6684
6685 if (base_vha->flags.online) {
6686 /* Abort all outstanding commands,
6687 * so as to be requeued later */
6688 qla2x00_abort_isp_cleanup(base_vha);
6689 }
6690
6691
6692 fn = PCI_FUNC(ha->pdev->devfn);
6693 while (fn > 0) {
6694 fn--;
7c3df132
SK		 6695 ql_dbg(ql_dbg_aer, base_vha, 0x9007,
6696 "Finding pci device at function = 0x%x.\n", fn);
a5b36321
LC		 6697 other_pdev =
6698 pci_get_domain_bus_and_slot(pci_domain_nr(ha->pdev->bus),
6699 ha->pdev->bus->number, PCI_DEVFN(PCI_SLOT(ha->pdev->devfn),
6700 fn));
6701
6702 if (!other_pdev)
6703 continue;
6704 if (atomic_read(&other_pdev->enable_cnt)) {
7c3df132
SK		 6705 ql_dbg(ql_dbg_aer, base_vha, 0x9008,
6706 "Found PCI func available and enable at 0x%x.\n",
6707 fn);
a5b36321
LC		 6708 pci_dev_put(other_pdev);
6709 break;
6710 }
6711 pci_dev_put(other_pdev);
6712 }
6713
6714 if (!fn) {
6715 /* Reset owner */
7c3df132
SK		 6716 ql_dbg(ql_dbg_aer, base_vha, 0x9009,
6717 "This devfn is reset owner = 0x%x.\n",
6718 ha->pdev->devfn);
a5b36321
LC		 6719 qla82xx_idc_lock(ha);
6720
6721 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 6722 QLA8XXX_DEV_INITIALIZING);
a5b36321
LC		 6723
6724 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION,
6725 QLA82XX_IDC_VERSION);
6726
6727 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
7c3df132
SK		 6728 ql_dbg(ql_dbg_aer, base_vha, 0x900a,
6729 "drv_active = 0x%x.\n", drv_active);
a5b36321
LC		 6730
6731 qla82xx_idc_unlock(ha);
6732 /* Reset if device is not already reset
6733 * drv_active would be 0 if a reset has already been done
6734 */
6735 if (drv_active)
6736 rval = qla82xx_start_firmware(base_vha);
6737 else
6738 rval = QLA_SUCCESS;
6739 qla82xx_idc_lock(ha);
6740
6741 if (rval != QLA_SUCCESS) {
7c3df132
SK		 6742 ql_log(ql_log_info, base_vha, 0x900b,
6743 "HW State: FAILED.\n");
a5b36321
LC		 6744 qla82xx_clear_drv_active(ha);
6745 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 6746 QLA8XXX_DEV_FAILED);
a5b36321 6747 } else {
7c3df132
SK		 6748 ql_log(ql_log_info, base_vha, 0x900c,
6749 "HW State: READY.\n");
a5b36321 6750 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 6751 QLA8XXX_DEV_READY);
a5b36321 6752 qla82xx_idc_unlock(ha);
7190575f 6753 ha->flags.isp82xx_fw_hung = 0;
a5b36321
LC		 6754 rval = qla82xx_restart_isp(base_vha);
6755 qla82xx_idc_lock(ha);
6756 /* Clear driver state register */
6757 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, 0);
6758 qla82xx_set_drv_active(base_vha);
6759 }
6760 qla82xx_idc_unlock(ha);
6761 } else {
7c3df132
SK		 6762 ql_dbg(ql_dbg_aer, base_vha, 0x900d,
6763 "This devfn is not reset owner = 0x%x.\n",
6764 ha->pdev->devfn);
a5b36321 6765 if ((qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE) ==
7d613ac6 6766 QLA8XXX_DEV_READY)) {
7190575f 6767 ha->flags.isp82xx_fw_hung = 0;
a5b36321
LC		 6768 rval = qla82xx_restart_isp(base_vha);
6769 qla82xx_idc_lock(ha);
6770 qla82xx_set_drv_active(base_vha);
6771 qla82xx_idc_unlock(ha);
6772 }
6773 }
6774 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
6775
6776 return rval;
6777}
6778
14e660e6
SJ		 6779static pci_ers_result_t
6780qla2xxx_pci_slot_reset(struct pci_dev *pdev)
6781{
6782 pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT;
e315cd28
AC		 6783 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
6784 struct qla_hw_data *ha = base_vha->hw;
90a86fc0
JC		 6785 struct rsp_que *rsp;
6786 int rc, retries = 10;
09483916 6787
7c3df132
SK		 6788 ql_dbg(ql_dbg_aer, base_vha, 0x9004,
6789 "Slot Reset.\n");
85880801 6790
90a86fc0
JC		 6791 /* Workaround: qla2xxx driver which access hardware earlier
6792 * needs error state to be pci_channel_io_online.
6793 * Otherwise mailbox command timesout.
6794 */
6795 pdev->error_state = pci_channel_io_normal;
6796
6797 pci_restore_state(pdev);
6798
8c1496bd
RL		 6799 /* pci_restore_state() clears the saved_state flag of the device
6800 * save restored state which resets saved_state flag
6801 */
6802 pci_save_state(pdev);
6803
09483916
BH		 6804 if (ha->mem_only)
6805 rc = pci_enable_device_mem(pdev);
6806 else
6807 rc = pci_enable_device(pdev);
14e660e6 6808
09483916 6809 if (rc) {
7c3df132 6810 ql_log(ql_log_warn, base_vha, 0x9005,
14e660e6 6811 "Can't re-enable PCI device after reset.\n");
a5b36321 6812 goto exit_slot_reset;
14e660e6 6813 }
14e660e6 6814
90a86fc0
JC		 6815 rsp = ha->rsp_q_map[0];
6816 if (qla2x00_request_irqs(ha, rsp))
a5b36321 6817 goto exit_slot_reset;
90a86fc0 6818
e315cd28 6819 if (ha->isp_ops->pci_config(base_vha))
a5b36321
LC		 6820 goto exit_slot_reset;
6821
6822 if (IS_QLA82XX(ha)) {
6823 if (qla82xx_error_recovery(base_vha) == QLA_SUCCESS) {
6824 ret = PCI_ERS_RESULT_RECOVERED;
6825 goto exit_slot_reset;
6826 } else
6827 goto exit_slot_reset;
6828 }
14e660e6 6829
90a86fc0
JC		 6830 while (ha->flags.mbox_busy && retries--)
6831 msleep(1000);
85880801 6832
e315cd28 6833 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
a9083016 6834 if (ha->isp_ops->abort_isp(base_vha) == QLA_SUCCESS)
14e660e6 6835 ret = PCI_ERS_RESULT_RECOVERED;
e315cd28 6836 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
14e660e6 6837
90a86fc0 6838
a5b36321 6839exit_slot_reset:
7c3df132
SK		 6840 ql_dbg(ql_dbg_aer, base_vha, 0x900e,
6841 "slot_reset return %x.\n", ret);
85880801 6842
14e660e6
SJ		 6843 return ret;
6844}
6845
6846static void
6847qla2xxx_pci_resume(struct pci_dev *pdev)
6848{
e315cd28
AC		 6849 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
6850 struct qla_hw_data *ha = base_vha->hw;
14e660e6
SJ		 6851 int ret;
6852
7c3df132
SK		 6853 ql_dbg(ql_dbg_aer, base_vha, 0x900f,
6854 "pci_resume.\n");
85880801 6855
e315cd28 6856 ret = qla2x00_wait_for_hba_online(base_vha);
14e660e6 6857 if (ret != QLA_SUCCESS) {
7c3df132
SK		 6858 ql_log(ql_log_fatal, base_vha, 0x9002,
6859 "The device failed to resume I/O from slot/link_reset.\n");
14e660e6 6860 }
85880801 6861
3e46f031
LC		 6862 pci_cleanup_aer_uncorrect_error_status(pdev);
6863
85880801 6864 ha->flags.eeh_busy = 0;
14e660e6
SJ		 6865}
6866
5601236b
MH		 6867static int qla2xxx_map_queues(struct Scsi_Host *shost)
6868{
d68b850e 6869 int rc;
5601236b
MH		 6870 scsi_qla_host_t *vha = (scsi_qla_host_t *)shost->hostdata;
6871
d68b850e
QT		 6872 if (USER_CTRL_IRQ(vha->hw))
6873 rc = blk_mq_map_queues(&shost->tag_set);
6874 else
f23f5bec 6875 rc = blk_mq_pci_map_queues(&shost->tag_set, vha->hw->pdev, 0);
d68b850e 6876 return rc;
5601236b
MH		 6877}
6878
a55b2d21 6879static const struct pci_error_handlers qla2xxx_err_handler = {
14e660e6
SJ		 6880 .error_detected = qla2xxx_pci_error_detected,
6881 .mmio_enabled = qla2xxx_pci_mmio_enabled,
6882 .slot_reset = qla2xxx_pci_slot_reset,
6883 .resume = qla2xxx_pci_resume,
6884};
6885
5433383e 6886static struct pci_device_id qla2xxx_pci_tbl[] = {
47f5e069
AV		 6887 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) },
6888 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) },
6889 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) },
6890 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) },
6891 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) },
6892 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) },
6893 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) },
6894 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) },
6895 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) },
4d4df193 6896 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) },
47f5e069
AV		 6897 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) },
6898 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) },
c3a2f0df 6899 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) },
6246b8a1 6900 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2031) },
3a03eb79 6901 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) },
a9083016 6902 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) },
650f528f 6903 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8031) },
8ae6d9c7 6904 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISPF001) },
7ec0effd 6905 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8044) },
f73cb695 6906 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2071) },
2c5bbbb2 6907 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2271) },
2b48992f 6908 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2261) },
5433383e
AV		 6909 { 0 },
6910};
6911MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl);
6912
fca29703 6913static struct pci_driver qla2xxx_pci_driver = {
cb63067a 6914 .name = QLA2XXX_DRIVER_NAME,
0a21ef1e
JB		 6915 .driver = {
6916 .owner = THIS_MODULE,
6917 },
fca29703 6918 .id_table = qla2xxx_pci_tbl,
7ee61397 6919 .probe = qla2x00_probe_one,
4c993f76 6920 .remove = qla2x00_remove_one,
e30d1756 6921 .shutdown = qla2x00_shutdown,
14e660e6 6922 .err_handler = &qla2xxx_err_handler,
fca29703
AV		 6923};
6924
75ef9de1 6925static const struct file_operations apidev_fops = {
6a03b4cd 6926 .owner = THIS_MODULE,
6038f373 6927 .llseek = noop_llseek,
6a03b4cd
HZ		 6928};
6929
1da177e4
LT		 6930/**
6931 * qla2x00_module_init - Module initialization.
6932 **/
6933static int __init
6934qla2x00_module_init(void)
6935{
fca29703
AV		 6936 int ret = 0;
6937
1da177e4 6938 /* Allocate cache for SRBs. */
354d6b21 6939 srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0,
20c2df83 6940 SLAB_HWCACHE_ALIGN, NULL);
1da177e4 6941 if (srb_cachep == NULL) {
7c3df132
SK		 6942 ql_log(ql_log_fatal, NULL, 0x0001,
6943 "Unable to allocate SRB cache...Failing load!.\n");
1da177e4
LT		 6944 return -ENOMEM;
6945 }
6946
2d70c103
NB		 6947 /* Initialize target kmem_cache and mem_pools */
6948 ret = qlt_init();
6949 if (ret < 0) {
6950 kmem_cache_destroy(srb_cachep);
6951 return ret;
6952 } else if (ret > 0) {
6953 /*
6954 * If initiator mode is explictly disabled by qlt_init(),
6955 * prevent scsi_transport_fc.c:fc_scsi_scan_rport() from
6956 * performing scsi_scan_target() during LOOP UP event.
6957 */
6958 qla2xxx_transport_functions.disable_target_scan = 1;
6959 qla2xxx_transport_vport_functions.disable_target_scan = 1;
6960 }
6961
1da177e4
LT		 6962 /* Derive version string. */
6963 strcpy(qla2x00_version_str, QLA2XXX_VERSION);
11010fec 6964 if (ql2xextended_error_logging)
0181944f 6965 strcat(qla2x00_version_str, "-debug");
fed0f68a
JC		 6966 if (ql2xextended_error_logging == 1)
6967 ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK;
0181944f 6968
1c97a12a
AV		 6969 qla2xxx_transport_template =
6970 fc_attach_transport(&qla2xxx_transport_functions);
2c3dfe3f
SJ		 6971 if (!qla2xxx_transport_template) {
6972 kmem_cache_destroy(srb_cachep);
7c3df132
SK		 6973 ql_log(ql_log_fatal, NULL, 0x0002,
6974 "fc_attach_transport failed...Failing load!.\n");
2d70c103 6975 qlt_exit();
1da177e4 6976 return -ENODEV;
2c3dfe3f 6977 }
6a03b4cd
HZ		 6978
6979 apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops);
6980 if (apidev_major < 0) {
7c3df132
SK		 6981 ql_log(ql_log_fatal, NULL, 0x0003,
6982 "Unable to register char device %s.\n", QLA2XXX_APIDEV);
6a03b4cd
HZ		 6983 }
6984
2c3dfe3f
SJ		 6985 qla2xxx_transport_vport_template =
6986 fc_attach_transport(&qla2xxx_transport_vport_functions);
6987 if (!qla2xxx_transport_vport_template) {
6988 kmem_cache_destroy(srb_cachep);
2d70c103 6989 qlt_exit();
2c3dfe3f 6990 fc_release_transport(qla2xxx_transport_template);
7c3df132
SK		 6991 ql_log(ql_log_fatal, NULL, 0x0004,
6992 "fc_attach_transport vport failed...Failing load!.\n");
1da177e4 6993 return -ENODEV;
2c3dfe3f 6994 }
7c3df132
SK		 6995 ql_log(ql_log_info, NULL, 0x0005,
6996 "QLogic Fibre Channel HBA Driver: %s.\n",
fd9a29f0 6997 qla2x00_version_str);
7ee61397 6998 ret = pci_register_driver(&qla2xxx_pci_driver);
fca29703
AV		 6999 if (ret) {
7000 kmem_cache_destroy(srb_cachep);
2d70c103 7001 qlt_exit();
fca29703 7002 fc_release_transport(qla2xxx_transport_template);
2c3dfe3f 7003 fc_release_transport(qla2xxx_transport_vport_template);
7c3df132
SK		 7004 ql_log(ql_log_fatal, NULL, 0x0006,
7005 "pci_register_driver failed...ret=%d Failing load!.\n",
7006 ret);
fca29703
AV		 7007 }
7008 return ret;
1da177e4
LT		 7009}
7010
7011/**
7012 * qla2x00_module_exit - Module cleanup.
7013 **/
7014static void __exit
7015qla2x00_module_exit(void)
7016{
6a03b4cd 7017 unregister_chrdev(apidev_major, QLA2XXX_APIDEV);
7ee61397 7018 pci_unregister_driver(&qla2xxx_pci_driver);
5433383e 7019 qla2x00_release_firmware();
354d6b21 7020 kmem_cache_destroy(srb_cachep);
2d70c103 7021 qlt_exit();
a9083016
GM		 7022 if (ctx_cachep)
7023 kmem_cache_destroy(ctx_cachep);
1da177e4 7024 fc_release_transport(qla2xxx_transport_template);
2c3dfe3f 7025 fc_release_transport(qla2xxx_transport_vport_template);
1da177e4
LT		 7026}
7027
7028module_init(qla2x00_module_init);
7029module_exit(qla2x00_module_exit);
7030
7031MODULE_AUTHOR("QLogic Corporation");
7032MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver");
7033MODULE_LICENSE("GPL");
7034MODULE_VERSION(QLA2XXX_VERSION);
bb8ee499
AV		 7035MODULE_FIRMWARE(FW_FILE_ISP21XX);
7036MODULE_FIRMWARE(FW_FILE_ISP22XX);
7037MODULE_FIRMWARE(FW_FILE_ISP2300);
7038MODULE_FIRMWARE(FW_FILE_ISP2322);
7039MODULE_FIRMWARE(FW_FILE_ISP24XX);
61623fc3 7040MODULE_FIRMWARE(FW_FILE_ISP25XX);
Linux 6.x block layer and io_uring tree(s)