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qla2xxx: Fix driver version string message.
[linux-2.6-block.git] / drivers / scsi / qla2xxx / qla_os.c
CommitLineData
1da177e4 1/*
fa90c54f 2 * QLogic Fibre Channel HBA Driver
bd21eaf9 3 * Copyright (c) 2003-2014 QLogic Corporation
1da177e4 4 *
fa90c54f 5 * See LICENSE.qla2xxx for copyright and licensing details.
1da177e4
LT		 6 */
7#include "qla_def.h"
8
9#include <linux/moduleparam.h>
10#include <linux/vmalloc.h>
1da177e4 11#include <linux/delay.h>
39a11240 12#include <linux/kthread.h>
e1e82b6f 13#include <linux/mutex.h>
3420d36c 14#include <linux/kobject.h>
5a0e3ad6 15#include <linux/slab.h>
1da177e4
LT		 16#include <scsi/scsi_tcq.h>
17#include <scsi/scsicam.h>
18#include <scsi/scsi_transport.h>
19#include <scsi/scsi_transport_fc.h>
20
2d70c103
NB		 21#include "qla_target.h"
22
1da177e4
LT		 23/*
24 * Driver version
25 */
26char qla2x00_version_str[40];
27
6a03b4cd
HZ		 28static int apidev_major;
29
1da177e4
LT		 30/*
31 * SRB allocation cache
32 */
e18b890b 33static struct kmem_cache *srb_cachep;
1da177e4 34
a9083016
GM		 35/*
36 * CT6 CTX allocation cache
37 */
38static struct kmem_cache *ctx_cachep;
3ce8866c
SK		 39/*
40 * error level for logging
41 */
42int ql_errlev = ql_log_all;
a9083016 43
fa492630 44static int ql2xenableclass2;
2d70c103
NB		 45module_param(ql2xenableclass2, int, S_IRUGO|S_IRUSR);
46MODULE_PARM_DESC(ql2xenableclass2,
47 "Specify if Class 2 operations are supported from the very "
48 "beginning. Default is 0 - class 2 not supported.");
49
8ae6d9c7 50
1da177e4 51int ql2xlogintimeout = 20;
f2019cb1 52module_param(ql2xlogintimeout, int, S_IRUGO);
1da177e4
LT		 53MODULE_PARM_DESC(ql2xlogintimeout,
54 "Login timeout value in seconds.");
55
a7b61842 56int qlport_down_retry;
f2019cb1 57module_param(qlport_down_retry, int, S_IRUGO);
1da177e4 58MODULE_PARM_DESC(qlport_down_retry,
900d9f98 59 "Maximum number of command retries to a port that returns "
1da177e4
LT		 60 "a PORT-DOWN status.");
61
1da177e4
LT		 62int ql2xplogiabsentdevice;
63module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR);
64MODULE_PARM_DESC(ql2xplogiabsentdevice,
65 "Option to enable PLOGI to devices that are not present after "
900d9f98 66 "a Fabric scan. This is needed for several broken switches. "
1da177e4
LT		 67 "Default is 0 - no PLOGI. 1 - perfom PLOGI.");
68
1da177e4 69int ql2xloginretrycount = 0;
f2019cb1 70module_param(ql2xloginretrycount, int, S_IRUGO);
1da177e4
LT		 71MODULE_PARM_DESC(ql2xloginretrycount,
72 "Specify an alternate value for the NVRAM login retry count.");
73
a7a167bf 74int ql2xallocfwdump = 1;
f2019cb1 75module_param(ql2xallocfwdump, int, S_IRUGO);
a7a167bf
AV		 76MODULE_PARM_DESC(ql2xallocfwdump,
77 "Option to enable allocation of memory for a firmware dump "
78 "during HBA initialization. Memory allocation requirements "
79 "vary by ISP type. Default is 1 - allocate memory.");
80
11010fec 81int ql2xextended_error_logging;
27d94035 82module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
11010fec 83MODULE_PARM_DESC(ql2xextended_error_logging,
3ce8866c
SK		 84 "Option to enable extended error logging,\n"
85 "\t\tDefault is 0 - no logging. 0x40000000 - Module Init & Probe.\n"
86 "\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n"
87 "\t\t0x08000000 - IO tracing. 0x04000000 - DPC Thread.\n"
88 "\t\t0x02000000 - Async events. 0x01000000 - Timer routines.\n"
89 "\t\t0x00800000 - User space. 0x00400000 - Task Management.\n"
90 "\t\t0x00200000 - AER/EEH. 0x00100000 - Multi Q.\n"
91 "\t\t0x00080000 - P3P Specific. 0x00040000 - Virtual Port.\n"
92 "\t\t0x00020000 - Buffer Dump. 0x00010000 - Misc.\n"
29f9f90c
CD		 93 "\t\t0x00008000 - Verbose. 0x00004000 - Target.\n"
94 "\t\t0x00002000 - Target Mgmt. 0x00001000 - Target TMF.\n"
3ce8866c 95 "\t\t0x7fffffff - For enabling all logs, can be too many logs.\n"
cfb0919c
CD		 96 "\t\t0x1e400000 - Preferred value for capturing essential "
97 "debug information (equivalent to old "
98 "ql2xextended_error_logging=1).\n"
3ce8866c 99 "\t\tDo LOGICAL OR of the value to enable more than one level");
0181944f 100
a9083016 101int ql2xshiftctondsd = 6;
f2019cb1 102module_param(ql2xshiftctondsd, int, S_IRUGO);
a9083016
GM		 103MODULE_PARM_DESC(ql2xshiftctondsd,
104 "Set to control shifting of command type processing "
105 "based on total number of SG elements.");
106
7e47e5ca 107int ql2xfdmienable=1;
f2019cb1 108module_param(ql2xfdmienable, int, S_IRUGO);
cca5335c 109MODULE_PARM_DESC(ql2xfdmienable,
7794a5af
FW		 110 "Enables FDMI registrations. "
111 "0 - no FDMI. Default is 1 - perform FDMI.");
cca5335c 112
50280c01
CD		 113#define MAX_Q_DEPTH 32
114static int ql2xmaxqdepth = MAX_Q_DEPTH;
df7baa50
AV		 115module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR);
116MODULE_PARM_DESC(ql2xmaxqdepth,
e92e4a8f
CD		 117 "Maximum queue depth to set for each LUN. "
118 "Default is 32.");
df7baa50 119
9e522cd8
AE		 120int ql2xenabledif = 2;
121module_param(ql2xenabledif, int, S_IRUGO);
bad75002 122MODULE_PARM_DESC(ql2xenabledif,
b97f5d0b
SM		 123 " Enable T10-CRC-DIF:\n"
124 " Default is 2.\n"
125 " 0 -- No DIF Support\n"
126 " 1 -- Enable DIF for all types\n"
127 " 2 -- Enable DIF for all types, except Type 0.\n");
bad75002 128
8cb2049c 129int ql2xenablehba_err_chk = 2;
bad75002
AE		 130module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR);
131MODULE_PARM_DESC(ql2xenablehba_err_chk,
8cb2049c 132 " Enable T10-CRC-DIF Error isolation by HBA:\n"
b97f5d0b 133 " Default is 2.\n"
8cb2049c
AE		 134 " 0 -- Error isolation disabled\n"
135 " 1 -- Error isolation enabled only for DIX Type 0\n"
136 " 2 -- Error isolation enabled for all Types\n");
bad75002 137
e5896bd5 138int ql2xiidmaenable=1;
f2019cb1 139module_param(ql2xiidmaenable, int, S_IRUGO);
e5896bd5
AV		 140MODULE_PARM_DESC(ql2xiidmaenable,
141 "Enables iIDMA settings "
142 "Default is 1 - perform iIDMA. 0 - no iIDMA.");
143
73208dfd 144int ql2xmaxqueues = 1;
f2019cb1 145module_param(ql2xmaxqueues, int, S_IRUGO);
73208dfd
AC		 146MODULE_PARM_DESC(ql2xmaxqueues,
147 "Enables MQ settings "
ae68230c
JP		 148 "Default is 1 for single queue. Set it to number "
149 "of queues in MQ mode.");
68ca949c
AC		 150
151int ql2xmultique_tag;
f2019cb1 152module_param(ql2xmultique_tag, int, S_IRUGO);
68ca949c
AC		 153MODULE_PARM_DESC(ql2xmultique_tag,
154 "Enables CPU affinity settings for the driver "
155 "Default is 0 for no affinity of request and response IO. "
156 "Set it to 1 to turn on the cpu affinity.");
e337d907
AV		 157
158int ql2xfwloadbin;
86e45bf6 159module_param(ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
e337d907 160MODULE_PARM_DESC(ql2xfwloadbin,
7c3df132
SK		 161 "Option to specify location from which to load ISP firmware:.\n"
162 " 2 -- load firmware via the request_firmware() (hotplug).\n"
e337d907
AV		 163 " interface.\n"
164 " 1 -- load firmware from flash.\n"
165 " 0 -- use default semantics.\n");
166
ae97c91e 167int ql2xetsenable;
f2019cb1 168module_param(ql2xetsenable, int, S_IRUGO);
ae97c91e
AV		 169MODULE_PARM_DESC(ql2xetsenable,
170 "Enables firmware ETS burst."
171 "Default is 0 - skip ETS enablement.");
172
6907869d 173int ql2xdbwr = 1;
86e45bf6 174module_param(ql2xdbwr, int, S_IRUGO|S_IWUSR);
a9083016 175MODULE_PARM_DESC(ql2xdbwr,
08de2844
GM		 176 "Option to specify scheme for request queue posting.\n"
177 " 0 -- Regular doorbell.\n"
178 " 1 -- CAMRAM doorbell (faster).\n");
a9083016 179
f4c496c1 180int ql2xtargetreset = 1;
f2019cb1 181module_param(ql2xtargetreset, int, S_IRUGO);
f4c496c1
GM		 182MODULE_PARM_DESC(ql2xtargetreset,
183 "Enable target reset."
184 "Default is 1 - use hw defaults.");
185
4da26e16 186int ql2xgffidenable;
f2019cb1 187module_param(ql2xgffidenable, int, S_IRUGO);
4da26e16
CD		 188MODULE_PARM_DESC(ql2xgffidenable,
189 "Enables GFF_ID checks of port type. "
190 "Default is 0 - Do not use GFF_ID information.");
a9083016 191
3822263e 192int ql2xasynctmfenable;
f2019cb1 193module_param(ql2xasynctmfenable, int, S_IRUGO);
3822263e
MI		 194MODULE_PARM_DESC(ql2xasynctmfenable,
195 "Enables issue of TM IOCBs asynchronously via IOCB mechanism"
196 "Default is 0 - Issue TM IOCBs via mailbox mechanism.");
ed0de87c
GM		 197
198int ql2xdontresethba;
86e45bf6 199module_param(ql2xdontresethba, int, S_IRUGO|S_IWUSR);
ed0de87c 200MODULE_PARM_DESC(ql2xdontresethba,
08de2844
GM		 201 "Option to specify reset behaviour.\n"
202 " 0 (Default) -- Reset on failure.\n"
203 " 1 -- Do not reset on failure.\n");
ed0de87c 204
1abf635d
HR		 205uint64_t ql2xmaxlun = MAX_LUNS;
206module_param(ql2xmaxlun, ullong, S_IRUGO);
82515920
AV		 207MODULE_PARM_DESC(ql2xmaxlun,
208 "Defines the maximum LU number to register with the SCSI "
209 "midlayer. Default is 65535.");
210
08de2844
GM		 211int ql2xmdcapmask = 0x1F;
212module_param(ql2xmdcapmask, int, S_IRUGO);
213MODULE_PARM_DESC(ql2xmdcapmask,
214 "Set the Minidump driver capture mask level. "
6e96fa7b 215 "Default is 0x1F - Can be set to 0x3, 0x7, 0xF, 0x1F, 0x7F.");
08de2844 216
3aadff35 217int ql2xmdenable = 1;
08de2844
GM		 218module_param(ql2xmdenable, int, S_IRUGO);
219MODULE_PARM_DESC(ql2xmdenable,
220 "Enable/disable MiniDump. "
3aadff35
GM		 221 "0 - MiniDump disabled. "
222 "1 (Default) - MiniDump enabled.");
08de2844 223
1da177e4 224/*
fa2a1ce5 225 * SCSI host template entry points
1da177e4
LT		 226 */
227static int qla2xxx_slave_configure(struct scsi_device * device);
f4f051eb 228static int qla2xxx_slave_alloc(struct scsi_device *);
1e99e33a
AV		 229static int qla2xxx_scan_finished(struct Scsi_Host *, unsigned long time);
230static void qla2xxx_scan_start(struct Scsi_Host *);
f4f051eb 231static void qla2xxx_slave_destroy(struct scsi_device *);
f281233d 232static int qla2xxx_queuecommand(struct Scsi_Host *h, struct scsi_cmnd *cmd);
1da177e4
LT		 233static int qla2xxx_eh_abort(struct scsi_cmnd *);
234static int qla2xxx_eh_device_reset(struct scsi_cmnd *);
523ec773 235static int qla2xxx_eh_target_reset(struct scsi_cmnd *);
1da177e4
LT		 236static int qla2xxx_eh_bus_reset(struct scsi_cmnd *);
237static int qla2xxx_eh_host_reset(struct scsi_cmnd *);
1da177e4 238
e881a172 239static int qla2x00_change_queue_depth(struct scsi_device *, int, int);
ce7e4af7 240static int qla2x00_change_queue_type(struct scsi_device *, int);
1a2fbf18 241static void qla2x00_clear_drv_active(struct qla_hw_data *);
3491255e 242static void qla2x00_free_device(scsi_qla_host_t *);
ce7e4af7 243
a5326f86 244struct scsi_host_template qla2xxx_driver_template = {
1da177e4 245 .module = THIS_MODULE,
cb63067a 246 .name = QLA2XXX_DRIVER_NAME,
a5326f86 247 .queuecommand = qla2xxx_queuecommand,
fca29703
AV		 248
249 .eh_abort_handler = qla2xxx_eh_abort,
250 .eh_device_reset_handler = qla2xxx_eh_device_reset,
523ec773 251 .eh_target_reset_handler = qla2xxx_eh_target_reset,
fca29703
AV		 252 .eh_bus_reset_handler = qla2xxx_eh_bus_reset,
253 .eh_host_reset_handler = qla2xxx_eh_host_reset,
254
255 .slave_configure = qla2xxx_slave_configure,
256
257 .slave_alloc = qla2xxx_slave_alloc,
258 .slave_destroy = qla2xxx_slave_destroy,
ed677086
AV		 259 .scan_finished = qla2xxx_scan_finished,
260 .scan_start = qla2xxx_scan_start,
ce7e4af7
AV		 261 .change_queue_depth = qla2x00_change_queue_depth,
262 .change_queue_type = qla2x00_change_queue_type,
fca29703
AV		 263 .this_id = -1,
264 .cmd_per_lun = 3,
265 .use_clustering = ENABLE_CLUSTERING,
266 .sg_tablesize = SG_ALL,
267
268 .max_sectors = 0xFFFF,
afb046e2 269 .shost_attrs = qla2x00_host_attrs,
2d70c103
NB		 270
271 .supported_mode = MODE_INITIATOR,
fca29703
AV		 272};
273
1da177e4 274static struct scsi_transport_template *qla2xxx_transport_template = NULL;
2c3dfe3f 275struct scsi_transport_template *qla2xxx_transport_vport_template = NULL;
1da177e4 276
1da177e4
LT		 277/* TODO Convert to inlines
278 *
279 * Timer routines
280 */
1da177e4 281
2c3dfe3f 282__inline__ void
e315cd28 283qla2x00_start_timer(scsi_qla_host_t *vha, void *func, unsigned long interval)
1da177e4 284{
e315cd28
AC		 285 init_timer(&vha->timer);
286 vha->timer.expires = jiffies + interval * HZ;
287 vha->timer.data = (unsigned long)vha;
288 vha->timer.function = (void (*)(unsigned long))func;
289 add_timer(&vha->timer);
290 vha->timer_active = 1;
1da177e4
LT		 291}
292
293static inline void
e315cd28 294qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval)
1da177e4 295{
a9083016 296 /* Currently used for 82XX only. */
7c3df132
SK		 297 if (vha->device_flags & DFLG_DEV_FAILED) {
298 ql_dbg(ql_dbg_timer, vha, 0x600d,
299 "Device in a failed state, returning.\n");
a9083016 300 return;
7c3df132 301 }
a9083016 302
e315cd28 303 mod_timer(&vha->timer, jiffies + interval * HZ);
1da177e4
LT		 304}
305
a824ebb3 306static __inline__ void
e315cd28 307qla2x00_stop_timer(scsi_qla_host_t *vha)
1da177e4 308{
e315cd28
AC		 309 del_timer_sync(&vha->timer);
310 vha->timer_active = 0;
1da177e4
LT		 311}
312
1da177e4
LT		 313static int qla2x00_do_dpc(void *data);
314
315static void qla2x00_rst_aen(scsi_qla_host_t *);
316
73208dfd
AC		 317static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t,
318 struct req_que **, struct rsp_que **);
e30d1756 319static void qla2x00_free_fw_dump(struct qla_hw_data *);
e315cd28 320static void qla2x00_mem_free(struct qla_hw_data *);
1da177e4 321
1da177e4 322/* -------------------------------------------------------------------------- */
9a347ff4
CD		 323static int qla2x00_alloc_queues(struct qla_hw_data *ha, struct req_que *req,
324 struct rsp_que *rsp)
73208dfd 325{
7c3df132 326 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2afa19a9 327 ha->req_q_map = kzalloc(sizeof(struct req_que *) * ha->max_req_queues,
73208dfd
AC		 328 GFP_KERNEL);
329 if (!ha->req_q_map) {
7c3df132
SK		 330 ql_log(ql_log_fatal, vha, 0x003b,
331 "Unable to allocate memory for request queue ptrs.\n");
73208dfd
AC		 332 goto fail_req_map;
333 }
334
2afa19a9 335 ha->rsp_q_map = kzalloc(sizeof(struct rsp_que *) * ha->max_rsp_queues,
73208dfd
AC		 336 GFP_KERNEL);
337 if (!ha->rsp_q_map) {
7c3df132
SK		 338 ql_log(ql_log_fatal, vha, 0x003c,
339 "Unable to allocate memory for response queue ptrs.\n");
73208dfd
AC		 340 goto fail_rsp_map;
341 }
9a347ff4
CD		 342 /*
343 * Make sure we record at least the request and response queue zero in
344 * case we need to free them if part of the probe fails.
345 */
346 ha->rsp_q_map[0] = rsp;
347 ha->req_q_map[0] = req;
73208dfd
AC		 348 set_bit(0, ha->rsp_qid_map);
349 set_bit(0, ha->req_qid_map);
350 return 1;
351
352fail_rsp_map:
353 kfree(ha->req_q_map);
354 ha->req_q_map = NULL;
355fail_req_map:
356 return -ENOMEM;
357}
358
2afa19a9 359static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req)
73208dfd 360{
8ae6d9c7
GM		 361 if (IS_QLAFX00(ha)) {
362 if (req && req->ring_fx00)
363 dma_free_coherent(&ha->pdev->dev,
364 (req->length_fx00 + 1) * sizeof(request_t),
365 req->ring_fx00, req->dma_fx00);
366 } else if (req && req->ring)
73208dfd
AC		 367 dma_free_coherent(&ha->pdev->dev,
368 (req->length + 1) * sizeof(request_t),
369 req->ring, req->dma);
370
8d93f550
CD		 371 if (req)
372 kfree(req->outstanding_cmds);
373
73208dfd
AC		 374 kfree(req);
375 req = NULL;
376}
377
2afa19a9
AC		 378static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp)
379{
8ae6d9c7
GM		 380 if (IS_QLAFX00(ha)) {
381 if (rsp && rsp->ring)
382 dma_free_coherent(&ha->pdev->dev,
383 (rsp->length_fx00 + 1) * sizeof(request_t),
384 rsp->ring_fx00, rsp->dma_fx00);
385 } else if (rsp && rsp->ring) {
2afa19a9
AC		 386 dma_free_coherent(&ha->pdev->dev,
387 (rsp->length + 1) * sizeof(response_t),
388 rsp->ring, rsp->dma);
8ae6d9c7 389 }
2afa19a9
AC		 390 kfree(rsp);
391 rsp = NULL;
392}
393
73208dfd
AC		 394static void qla2x00_free_queues(struct qla_hw_data *ha)
395{
396 struct req_que *req;
397 struct rsp_que *rsp;
398 int cnt;
399
2afa19a9 400 for (cnt = 0; cnt < ha->max_req_queues; cnt++) {
73208dfd 401 req = ha->req_q_map[cnt];
2afa19a9 402 qla2x00_free_req_que(ha, req);
73208dfd 403 }
73208dfd
AC		 404 kfree(ha->req_q_map);
405 ha->req_q_map = NULL;
2afa19a9
AC		 406
407 for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) {
408 rsp = ha->rsp_q_map[cnt];
409 qla2x00_free_rsp_que(ha, rsp);
410 }
411 kfree(ha->rsp_q_map);
412 ha->rsp_q_map = NULL;
73208dfd
AC		 413}
414
68ca949c
AC		 415static int qla25xx_setup_mode(struct scsi_qla_host *vha)
416{
417 uint16_t options = 0;
418 int ques, req, ret;
419 struct qla_hw_data *ha = vha->hw;
420
7163ea81 421 if (!(ha->fw_attributes & BIT_6)) {
7c3df132
SK		 422 ql_log(ql_log_warn, vha, 0x00d8,
423 "Firmware is not multi-queue capable.\n");
7163ea81
AC		 424 goto fail;
425 }
68ca949c 426 if (ql2xmultique_tag) {
68ca949c
AC		 427 /* create a request queue for IO */
428 options |= BIT_7;
429 req = qla25xx_create_req_que(ha, options, 0, 0, -1,
430 QLA_DEFAULT_QUE_QOS);
431 if (!req) {
7c3df132
SK		 432 ql_log(ql_log_warn, vha, 0x00e0,
433 "Failed to create request queue.\n");
68ca949c
AC		 434 goto fail;
435 }
278274d5 436 ha->wq = alloc_workqueue("qla2xxx_wq", WQ_MEM_RECLAIM, 1);
68ca949c
AC		 437 vha->req = ha->req_q_map[req];
438 options |= BIT_1;
439 for (ques = 1; ques < ha->max_rsp_queues; ques++) {
440 ret = qla25xx_create_rsp_que(ha, options, 0, 0, req);
441 if (!ret) {
7c3df132
SK		 442 ql_log(ql_log_warn, vha, 0x00e8,
443 "Failed to create response queue.\n");
68ca949c
AC		 444 goto fail2;
445 }
446 }
7163ea81 447 ha->flags.cpu_affinity_enabled = 1;
7c3df132
SK		 448 ql_dbg(ql_dbg_multiq, vha, 0xc007,
449 "CPU affinity mode enalbed, "
450 "no. of response queues:%d no. of request queues:%d.\n",
451 ha->max_rsp_queues, ha->max_req_queues);
452 ql_dbg(ql_dbg_init, vha, 0x00e9,
453 "CPU affinity mode enalbed, "
454 "no. of response queues:%d no. of request queues:%d.\n",
455 ha->max_rsp_queues, ha->max_req_queues);
68ca949c
AC		 456 }
457 return 0;
458fail2:
459 qla25xx_delete_queues(vha);
7163ea81
AC		 460 destroy_workqueue(ha->wq);
461 ha->wq = NULL;
0cd33fcf 462 vha->req = ha->req_q_map[0];
68ca949c
AC		 463fail:
464 ha->mqenable = 0;
7163ea81
AC		 465 kfree(ha->req_q_map);
466 kfree(ha->rsp_q_map);
467 ha->max_req_queues = ha->max_rsp_queues = 1;
68ca949c
AC		 468 return 1;
469}
470
1da177e4 471static char *
e315cd28 472qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str)
1da177e4 473{
e315cd28 474 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 475 static char *pci_bus_modes[] = {
476 "33", "66", "100", "133",
477 };
478 uint16_t pci_bus;
479
480 strcpy(str, "PCI");
481 pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9;
482 if (pci_bus) {
483 strcat(str, "-X (");
484 strcat(str, pci_bus_modes[pci_bus]);
485 } else {
486 pci_bus = (ha->pci_attr & BIT_8) >> 8;
487 strcat(str, " (");
488 strcat(str, pci_bus_modes[pci_bus]);
489 }
490 strcat(str, " MHz)");
491
492 return (str);
493}
494
fca29703 495static char *
e315cd28 496qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str)
fca29703
AV		 497{
498 static char *pci_bus_modes[] = { "33", "66", "100", "133", };
e315cd28 499 struct qla_hw_data *ha = vha->hw;
fca29703 500 uint32_t pci_bus;
fca29703 501
62a276f8 502 if (pci_is_pcie(ha->pdev)) {
fca29703 503 char lwstr[6];
62a276f8 504 uint32_t lstat, lspeed, lwidth;
fca29703 505
62a276f8
BH		 506 pcie_capability_read_dword(ha->pdev, PCI_EXP_LNKCAP, &lstat);
507 lspeed = lstat & PCI_EXP_LNKCAP_SLS;
508 lwidth = (lstat & PCI_EXP_LNKCAP_MLW) >> 4;
fca29703
AV		 509
510 strcpy(str, "PCIe (");
49300af7
SK		 511 switch (lspeed) {
512 case 1:
c87a0d8c 513 strcat(str, "2.5GT/s ");
49300af7
SK		 514 break;
515 case 2:
c87a0d8c 516 strcat(str, "5.0GT/s ");
49300af7
SK		 517 break;
518 case 3:
519 strcat(str, "8.0GT/s ");
520 break;
521 default:
fca29703 522 strcat(str, "<unknown> ");
49300af7
SK		 523 break;
524 }
fca29703
AV		 525 snprintf(lwstr, sizeof(lwstr), "x%d)", lwidth);
526 strcat(str, lwstr);
527
528 return str;
529 }
530
531 strcpy(str, "PCI");
532 pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8;
533 if (pci_bus == 0 || pci_bus == 8) {
534 strcat(str, " (");
535 strcat(str, pci_bus_modes[pci_bus >> 3]);
536 } else {
537 strcat(str, "-X ");
538 if (pci_bus & BIT_2)
539 strcat(str, "Mode 2");
540 else
541 strcat(str, "Mode 1");
542 strcat(str, " (");
543 strcat(str, pci_bus_modes[pci_bus & ~BIT_2]);
544 }
545 strcat(str, " MHz)");
546
547 return str;
548}
549
e5f82ab8 550static char *
df57caba 551qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
1da177e4
LT		 552{
553 char un_str[10];
e315cd28 554 struct qla_hw_data *ha = vha->hw;
fa2a1ce5 555
df57caba
HM		 556 snprintf(str, size, "%d.%02d.%02d ", ha->fw_major_version,
557 ha->fw_minor_version, ha->fw_subminor_version);
1da177e4
LT		 558
559 if (ha->fw_attributes & BIT_9) {
560 strcat(str, "FLX");
561 return (str);
562 }
563
564 switch (ha->fw_attributes & 0xFF) {
565 case 0x7:
566 strcat(str, "EF");
567 break;
568 case 0x17:
569 strcat(str, "TP");
570 break;
571 case 0x37:
572 strcat(str, "IP");
573 break;
574 case 0x77:
575 strcat(str, "VI");
576 break;
577 default:
578 sprintf(un_str, "(%x)", ha->fw_attributes);
579 strcat(str, un_str);
580 break;
581 }
582 if (ha->fw_attributes & 0x100)
583 strcat(str, "X");
584
585 return (str);
586}
587
e5f82ab8 588static char *
df57caba 589qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
fca29703 590{
e315cd28 591 struct qla_hw_data *ha = vha->hw;
f0883ac6 592
df57caba 593 snprintf(str, size, "%d.%02d.%02d (%x)", ha->fw_major_version,
3a03eb79 594 ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes);
fca29703 595 return str;
fca29703
AV		 596}
597
9ba56b95
GM		 598void
599qla2x00_sp_free_dma(void *vha, void *ptr)
fca29703 600{
9ba56b95
GM		 601 srb_t *sp = (srb_t *)ptr;
602 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
603 struct qla_hw_data *ha = sp->fcport->vha->hw;
604 void *ctx = GET_CMD_CTX_SP(sp);
fca29703 605
9ba56b95
GM		 606 if (sp->flags & SRB_DMA_VALID) {
607 scsi_dma_unmap(cmd);
608 sp->flags &= ~SRB_DMA_VALID;
7c3df132 609 }
fca29703 610
9ba56b95
GM		 611 if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
612 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
613 scsi_prot_sg_count(cmd), cmd->sc_data_direction);
614 sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
615 }
616
617 if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
618 /* List assured to be having elements */
f83adb61 619 qla2x00_clean_dsd_pool(ha, sp, NULL);
9ba56b95
GM		 620 sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
621 }
622
623 if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
624 dma_pool_free(ha->dl_dma_pool, ctx,
625 ((struct crc_context *)ctx)->crc_ctx_dma);
626 sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
627 }
628
629 if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
630 struct ct6_dsd *ctx1 = (struct ct6_dsd *)ctx;
fca29703 631
9ba56b95
GM		 632 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd,
633 ctx1->fcp_cmnd_dma);
634 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list);
635 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt;
636 ha->gbl_dsd_avail += ctx1->dsd_use_cnt;
637 mempool_free(ctx1, ha->ctx_mempool);
638 ctx1 = NULL;
639 }
640
641 CMD_SP(cmd) = NULL;
b00ee7d7 642 qla2x00_rel_sp(sp->fcport->vha, sp);
9ba56b95
GM		 643}
644
14b06808 645static void
9ba56b95
GM		 646qla2x00_sp_compl(void *data, void *ptr, int res)
647{
648 struct qla_hw_data *ha = (struct qla_hw_data *)data;
649 srb_t *sp = (srb_t *)ptr;
650 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
651
652 cmd->result = res;
653
654 if (atomic_read(&sp->ref_count) == 0) {
655 ql_dbg(ql_dbg_io, sp->fcport->vha, 0x3015,
656 "SP reference-count to ZERO -- sp=%p cmd=%p.\n",
657 sp, GET_CMD_SP(sp));
658 if (ql2xextended_error_logging & ql_dbg_io)
659 BUG();
660 return;
661 }
662 if (!atomic_dec_and_test(&sp->ref_count))
663 return;
664
665 qla2x00_sp_free_dma(ha, sp);
666 cmd->scsi_done(cmd);
fca29703
AV		 667}
668
8ae6d9c7
GM		 669/* If we are SP1 here, we need to still take and release the host_lock as SP1
670 * does not have the changes necessary to avoid taking host->host_lock.
671 */
1da177e4 672static int
f5e3e40b 673qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
fca29703 674{
134ae078 675 scsi_qla_host_t *vha = shost_priv(host);
fca29703 676 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
19a7b4ae 677 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
e315cd28
AC		 678 struct qla_hw_data *ha = vha->hw;
679 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
fca29703
AV		 680 srb_t *sp;
681 int rval;
682
85880801 683 if (ha->flags.eeh_busy) {
7c3df132 684 if (ha->flags.pci_channel_io_perm_failure) {
5f28d2d7 685 ql_dbg(ql_dbg_aer, vha, 0x9010,
7c3df132
SK		 686 "PCI Channel IO permanent failure, exiting "
687 "cmd=%p.\n", cmd);
b9b12f73 688 cmd->result = DID_NO_CONNECT << 16;
7c3df132 689 } else {
5f28d2d7 690 ql_dbg(ql_dbg_aer, vha, 0x9011,
7c3df132 691 "EEH_Busy, Requeuing the cmd=%p.\n", cmd);
85880801 692 cmd->result = DID_REQUEUE << 16;
7c3df132 693 }
14e660e6
SJ		 694 goto qc24_fail_command;
695 }
696
19a7b4ae
JSEC		 697 rval = fc_remote_port_chkready(rport);
698 if (rval) {
699 cmd->result = rval;
5f28d2d7 700 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3003,
7c3df132
SK		 701 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
702 cmd, rval);
fca29703
AV		 703 goto qc24_fail_command;
704 }
705
bad75002
AE		 706 if (!vha->flags.difdix_supported &&
707 scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) {
7c3df132
SK		 708 ql_dbg(ql_dbg_io, vha, 0x3004,
709 "DIF Cap not reg, fail DIF capable cmd's:%p.\n",
710 cmd);
bad75002
AE		 711 cmd->result = DID_NO_CONNECT << 16;
712 goto qc24_fail_command;
713 }
aa651be8
CD		 714
715 if (!fcport) {
716 cmd->result = DID_NO_CONNECT << 16;
717 goto qc24_fail_command;
718 }
719
fca29703
AV		 720 if (atomic_read(&fcport->state) != FCS_ONLINE) {
721 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
38170fa8 722 atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
7c3df132
SK		 723 ql_dbg(ql_dbg_io, vha, 0x3005,
724 "Returning DNC, fcport_state=%d loop_state=%d.\n",
725 atomic_read(&fcport->state),
726 atomic_read(&base_vha->loop_state));
fca29703
AV		 727 cmd->result = DID_NO_CONNECT << 16;
728 goto qc24_fail_command;
729 }
7b594131 730 goto qc24_target_busy;
fca29703
AV		 731 }
732
b00ee7d7 733 sp = qla2x00_get_sp(vha, fcport, GFP_ATOMIC);
50280c01 734 if (!sp)
f5e3e40b 735 goto qc24_host_busy;
fca29703 736
9ba56b95
GM		 737 sp->u.scmd.cmd = cmd;
738 sp->type = SRB_SCSI_CMD;
739 atomic_set(&sp->ref_count, 1);
740 CMD_SP(cmd) = (void *)sp;
741 sp->free = qla2x00_sp_free_dma;
742 sp->done = qla2x00_sp_compl;
743
e315cd28 744 rval = ha->isp_ops->start_scsi(sp);
7c3df132 745 if (rval != QLA_SUCCESS) {
53016ed3 746 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3013,
7c3df132 747 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
fca29703 748 goto qc24_host_busy_free_sp;
7c3df132 749 }
fca29703 750
fca29703
AV		 751 return 0;
752
753qc24_host_busy_free_sp:
9ba56b95 754 qla2x00_sp_free_dma(ha, sp);
fca29703 755
f5e3e40b 756qc24_host_busy:
fca29703
AV		 757 return SCSI_MLQUEUE_HOST_BUSY;
758
7b594131
MC		 759qc24_target_busy:
760 return SCSI_MLQUEUE_TARGET_BUSY;
761
fca29703 762qc24_fail_command:
f5e3e40b 763 cmd->scsi_done(cmd);
fca29703
AV		 764
765 return 0;
766}
767
1da177e4
LT		 768/*
769 * qla2x00_eh_wait_on_command
770 * Waits for the command to be returned by the Firmware for some
771 * max time.
772 *
773 * Input:
1da177e4 774 * cmd = Scsi Command to wait on.
1da177e4
LT		 775 *
776 * Return:
777 * Not Found : 0
778 * Found : 1
779 */
780static int
e315cd28 781qla2x00_eh_wait_on_command(struct scsi_cmnd *cmd)
1da177e4 782{
fe74c71f 783#define ABORT_POLLING_PERIOD 1000
478c3b03 784#define ABORT_WAIT_ITER ((2 * 1000) / (ABORT_POLLING_PERIOD))
f4f051eb 785 unsigned long wait_iter = ABORT_WAIT_ITER;
85880801
AV		 786 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
787 struct qla_hw_data *ha = vha->hw;
f4f051eb 788 int ret = QLA_SUCCESS;
1da177e4 789
85880801 790 if (unlikely(pci_channel_offline(ha->pdev)) || ha->flags.eeh_busy) {
7c3df132
SK		 791 ql_dbg(ql_dbg_taskm, vha, 0x8005,
792 "Return:eh_wait.\n");
85880801
AV		 793 return ret;
794 }
795
d970432c 796 while (CMD_SP(cmd) && wait_iter--) {
fe74c71f 797 msleep(ABORT_POLLING_PERIOD);
f4f051eb 798 }
799 if (CMD_SP(cmd))
800 ret = QLA_FUNCTION_FAILED;
1da177e4 801
f4f051eb 802 return ret;
1da177e4
LT		 803}
804
805/*
806 * qla2x00_wait_for_hba_online
fa2a1ce5 807 * Wait till the HBA is online after going through
1da177e4
LT		 808 * <= MAX_RETRIES_OF_ISP_ABORT or
809 * finally HBA is disabled ie marked offline
810 *
811 * Input:
812 * ha - pointer to host adapter structure
fa2a1ce5
AV		 813 *
814 * Note:
1da177e4
LT		 815 * Does context switching-Release SPIN_LOCK
816 * (if any) before calling this routine.
817 *
818 * Return:
819 * Success (Adapter is online) : 0
820 * Failed (Adapter is offline/disabled) : 1
821 */
854165f4 822int
e315cd28 823qla2x00_wait_for_hba_online(scsi_qla_host_t *vha)
1da177e4 824{
fca29703
AV		 825 int return_status;
826 unsigned long wait_online;
e315cd28
AC		 827 struct qla_hw_data *ha = vha->hw;
828 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4 829
fa2a1ce5 830 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ);
e315cd28
AC		 831 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
832 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
833 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
834 ha->dpc_active) && time_before(jiffies, wait_online)) {
1da177e4
LT		 835
836 msleep(1000);
837 }
e315cd28 838 if (base_vha->flags.online)
fa2a1ce5 839 return_status = QLA_SUCCESS;
1da177e4
LT		 840 else
841 return_status = QLA_FUNCTION_FAILED;
842
1da177e4
LT		 843 return (return_status);
844}
845
86fbee86 846/*
638a1a01
SC		 847 * qla2x00_wait_for_hba_ready
848 * Wait till the HBA is ready before doing driver unload
86fbee86
LC		 849 *
850 * Input:
851 * ha - pointer to host adapter structure
852 *
853 * Note:
854 * Does context switching-Release SPIN_LOCK
855 * (if any) before calling this routine.
856 *
86fbee86 857 */
638a1a01
SC		 858static void
859qla2x00_wait_for_hba_ready(scsi_qla_host_t *vha)
86fbee86 860{
86fbee86 861 struct qla_hw_data *ha = vha->hw;
86fbee86 862
638a1a01
SC		 863 while ((!(vha->flags.online) || ha->dpc_active ||
864 ha->flags.mbox_busy))
86fbee86 865 msleep(1000);
86fbee86
LC		 866}
867
2533cf67
LC		 868int
869qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha)
870{
871 int return_status;
872 unsigned long wait_reset;
873 struct qla_hw_data *ha = vha->hw;
874 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
875
876 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ);
877 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
878 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
879 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
880 ha->dpc_active) && time_before(jiffies, wait_reset)) {
881
882 msleep(1000);
883
884 if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) &&
885 ha->flags.chip_reset_done)
886 break;
887 }
888 if (ha->flags.chip_reset_done)
889 return_status = QLA_SUCCESS;
890 else
891 return_status = QLA_FUNCTION_FAILED;
892
893 return return_status;
894}
895
083a469d
GM		 896static void
897sp_get(struct srb *sp)
898{
899 atomic_inc(&sp->ref_count);
900}
901
1da177e4
LT		 902/**************************************************************************
903* qla2xxx_eh_abort
904*
905* Description:
906* The abort function will abort the specified command.
907*
908* Input:
909* cmd = Linux SCSI command packet to be aborted.
910*
911* Returns:
912* Either SUCCESS or FAILED.
913*
914* Note:
2ea00202 915* Only return FAILED if command not returned by firmware.
1da177e4 916**************************************************************************/
e5f82ab8 917static int
1da177e4
LT		 918qla2xxx_eh_abort(struct scsi_cmnd *cmd)
919{
e315cd28 920 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
f4f051eb 921 srb_t *sp;
4e98d3b8 922 int ret;
9cb78c16
HR		 923 unsigned int id;
924 uint64_t lun;
18e144d3 925 unsigned long flags;
f934c9d0 926 int rval, wait = 0;
e315cd28 927 struct qla_hw_data *ha = vha->hw;
1da177e4 928
f4f051eb 929 if (!CMD_SP(cmd))
2ea00202 930 return SUCCESS;
1da177e4 931
4e98d3b8
AV		 932 ret = fc_block_scsi_eh(cmd);
933 if (ret != 0)
934 return ret;
935 ret = SUCCESS;
936
f4f051eb 937 id = cmd->device->id;
938 lun = cmd->device->lun;
1da177e4 939
e315cd28 940 spin_lock_irqsave(&ha->hardware_lock, flags);
170babc3
MC		 941 sp = (srb_t *) CMD_SP(cmd);
942 if (!sp) {
943 spin_unlock_irqrestore(&ha->hardware_lock, flags);
944 return SUCCESS;
945 }
1da177e4 946
7c3df132 947 ql_dbg(ql_dbg_taskm, vha, 0x8002,
9cb78c16 948 "Aborting from RISC nexus=%ld:%d:%llu sp=%p cmd=%p\n",
cfb0919c 949 vha->host_no, id, lun, sp, cmd);
17d98630 950
170babc3
MC		 951 /* Get a reference to the sp and drop the lock.*/
952 sp_get(sp);
083a469d 953
e315cd28 954 spin_unlock_irqrestore(&ha->hardware_lock, flags);
f934c9d0
CD		 955 rval = ha->isp_ops->abort_command(sp);
956 if (rval) {
957 if (rval == QLA_FUNCTION_PARAMETER_ERROR) {
958 /*
959 * Decrement the ref_count since we can't find the
960 * command
961 */
962 atomic_dec(&sp->ref_count);
963 ret = SUCCESS;
964 } else
965 ret = FAILED;
966
7c3df132 967 ql_dbg(ql_dbg_taskm, vha, 0x8003,
f934c9d0 968 "Abort command mbx failed cmd=%p, rval=%x.\n", cmd, rval);
170babc3 969 } else {
7c3df132 970 ql_dbg(ql_dbg_taskm, vha, 0x8004,
cfb0919c 971 "Abort command mbx success cmd=%p.\n", cmd);
170babc3
MC		 972 wait = 1;
973 }
75942064
SK		 974
975 spin_lock_irqsave(&ha->hardware_lock, flags);
f934c9d0
CD		 976 /*
977 * Clear the slot in the oustanding_cmds array if we can't find the
978 * command to reclaim the resources.
979 */
980 if (rval == QLA_FUNCTION_PARAMETER_ERROR)
981 vha->req->outstanding_cmds[sp->handle] = NULL;
9ba56b95 982 sp->done(ha, sp, 0);
75942064 983 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1da177e4 984
bc91ade9
CD		 985 /* Did the command return during mailbox execution? */
986 if (ret == FAILED && !CMD_SP(cmd))
987 ret = SUCCESS;
988
f4f051eb 989 /* Wait for the command to be returned. */
2ea00202 990 if (wait) {
e315cd28 991 if (qla2x00_eh_wait_on_command(cmd) != QLA_SUCCESS) {
7c3df132 992 ql_log(ql_log_warn, vha, 0x8006,
cfb0919c 993 "Abort handler timed out cmd=%p.\n", cmd);
2ea00202 994 ret = FAILED;
f4f051eb 995 }
1da177e4 996 }
1da177e4 997
7c3df132 998 ql_log(ql_log_info, vha, 0x801c,
9cb78c16 999 "Abort command issued nexus=%ld:%d:%llu -- %d %x.\n",
cfb0919c 1000 vha->host_no, id, lun, wait, ret);
1da177e4 1001
f4f051eb 1002 return ret;
1003}
1da177e4 1004
4d78c973 1005int
e315cd28 1006qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t,
9cb78c16 1007 uint64_t l, enum nexus_wait_type type)
f4f051eb 1008{
17d98630 1009 int cnt, match, status;
18e144d3 1010 unsigned long flags;
e315cd28 1011 struct qla_hw_data *ha = vha->hw;
73208dfd 1012 struct req_que *req;
4d78c973 1013 srb_t *sp;
9ba56b95 1014 struct scsi_cmnd *cmd;
1da177e4 1015
523ec773 1016 status = QLA_SUCCESS;
17d98630 1017
e315cd28 1018 spin_lock_irqsave(&ha->hardware_lock, flags);
67c2e93a 1019 req = vha->req;
17d98630 1020 for (cnt = 1; status == QLA_SUCCESS &&
8d93f550 1021 cnt < req->num_outstanding_cmds; cnt++) {
17d98630
AC		 1022 sp = req->outstanding_cmds[cnt];
1023 if (!sp)
523ec773 1024 continue;
9ba56b95 1025 if (sp->type != SRB_SCSI_CMD)
cf53b069 1026 continue;
17d98630
AC		 1027 if (vha->vp_idx != sp->fcport->vha->vp_idx)
1028 continue;
1029 match = 0;
9ba56b95 1030 cmd = GET_CMD_SP(sp);
17d98630
AC		 1031 switch (type) {
1032 case WAIT_HOST:
1033 match = 1;
1034 break;
1035 case WAIT_TARGET:
9ba56b95 1036 match = cmd->device->id == t;
17d98630
AC		 1037 break;
1038 case WAIT_LUN:
9ba56b95
GM		 1039 match = (cmd->device->id == t &&
1040 cmd->device->lun == l);
17d98630 1041 break;
73208dfd 1042 }
17d98630
AC		 1043 if (!match)
1044 continue;
1045
1046 spin_unlock_irqrestore(&ha->hardware_lock, flags);
9ba56b95 1047 status = qla2x00_eh_wait_on_command(cmd);
17d98630 1048 spin_lock_irqsave(&ha->hardware_lock, flags);
1da177e4 1049 }
e315cd28 1050 spin_unlock_irqrestore(&ha->hardware_lock, flags);
523ec773
AV		 1051
1052 return status;
1da177e4
LT		 1053}
1054
523ec773
AV		 1055static char *reset_errors[] = {
1056 "HBA not online",
1057 "HBA not ready",
1058 "Task management failed",
1059 "Waiting for command completions",
1060};
1da177e4 1061
e5f82ab8 1062static int
523ec773 1063__qla2xxx_eh_generic_reset(char *name, enum nexus_wait_type type,
9cb78c16 1064 struct scsi_cmnd *cmd, int (*do_reset)(struct fc_port *, uint64_t, int))
1da177e4 1065{
e315cd28 1066 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
bdf79621 1067 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
523ec773 1068 int err;
1da177e4 1069
7c3df132 1070 if (!fcport) {
523ec773 1071 return FAILED;
7c3df132 1072 }
1da177e4 1073
4e98d3b8
AV		 1074 err = fc_block_scsi_eh(cmd);
1075 if (err != 0)
1076 return err;
1077
7c3df132 1078 ql_log(ql_log_info, vha, 0x8009,
9cb78c16 1079 "%s RESET ISSUED nexus=%ld:%d:%llu cmd=%p.\n", name, vha->host_no,
7c3df132 1080 cmd->device->id, cmd->device->lun, cmd);
1da177e4 1081
523ec773 1082 err = 0;
7c3df132
SK		 1083 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1084 ql_log(ql_log_warn, vha, 0x800a,
1085 "Wait for hba online failed for cmd=%p.\n", cmd);
523ec773 1086 goto eh_reset_failed;
7c3df132 1087 }
523ec773 1088 err = 2;
2afa19a9 1089 if (do_reset(fcport, cmd->device->lun, cmd->request->cpu + 1)
7c3df132
SK		 1090 != QLA_SUCCESS) {
1091 ql_log(ql_log_warn, vha, 0x800c,
1092 "do_reset failed for cmd=%p.\n", cmd);
523ec773 1093 goto eh_reset_failed;
7c3df132 1094 }
523ec773 1095 err = 3;
e315cd28 1096 if (qla2x00_eh_wait_for_pending_commands(vha, cmd->device->id,
7c3df132
SK		 1097 cmd->device->lun, type) != QLA_SUCCESS) {
1098 ql_log(ql_log_warn, vha, 0x800d,
d6a03581 1099 "wait for pending cmds failed for cmd=%p.\n", cmd);
523ec773 1100 goto eh_reset_failed;
7c3df132 1101 }
523ec773 1102
7c3df132 1103 ql_log(ql_log_info, vha, 0x800e,
9cb78c16 1104 "%s RESET SUCCEEDED nexus:%ld:%d:%llu cmd=%p.\n", name,
cfb0919c 1105 vha->host_no, cmd->device->id, cmd->device->lun, cmd);
523ec773
AV		 1106
1107 return SUCCESS;
1108
4d78c973 1109eh_reset_failed:
7c3df132 1110 ql_log(ql_log_info, vha, 0x800f,
9cb78c16 1111 "%s RESET FAILED: %s nexus=%ld:%d:%llu cmd=%p.\n", name,
cfb0919c
CD		 1112 reset_errors[err], vha->host_no, cmd->device->id, cmd->device->lun,
1113 cmd);
523ec773
AV		 1114 return FAILED;
1115}
1da177e4 1116
523ec773
AV		 1117static int
1118qla2xxx_eh_device_reset(struct scsi_cmnd *cmd)
1119{
e315cd28
AC		 1120 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1121 struct qla_hw_data *ha = vha->hw;
1da177e4 1122
523ec773
AV		 1123 return __qla2xxx_eh_generic_reset("DEVICE", WAIT_LUN, cmd,
1124 ha->isp_ops->lun_reset);
1da177e4
LT		 1125}
1126
1da177e4 1127static int
523ec773 1128qla2xxx_eh_target_reset(struct scsi_cmnd *cmd)
1da177e4 1129{
e315cd28
AC		 1130 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1131 struct qla_hw_data *ha = vha->hw;
1da177e4 1132
523ec773
AV		 1133 return __qla2xxx_eh_generic_reset("TARGET", WAIT_TARGET, cmd,
1134 ha->isp_ops->target_reset);
1da177e4
LT		 1135}
1136
1da177e4
LT		 1137/**************************************************************************
1138* qla2xxx_eh_bus_reset
1139*
1140* Description:
1141* The bus reset function will reset the bus and abort any executing
1142* commands.
1143*
1144* Input:
1145* cmd = Linux SCSI command packet of the command that cause the
1146* bus reset.
1147*
1148* Returns:
1149* SUCCESS/FAILURE (defined as macro in scsi.h).
1150*
1151**************************************************************************/
e5f82ab8 1152static int
1da177e4
LT		 1153qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd)
1154{
e315cd28 1155 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
bdf79621 1156 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
2c3dfe3f 1157 int ret = FAILED;
9cb78c16
HR		 1158 unsigned int id;
1159 uint64_t lun;
f4f051eb 1160
f4f051eb 1161 id = cmd->device->id;
1162 lun = cmd->device->lun;
1da177e4 1163
7c3df132 1164 if (!fcport) {
f4f051eb 1165 return ret;
7c3df132 1166 }
1da177e4 1167
4e98d3b8
AV		 1168 ret = fc_block_scsi_eh(cmd);
1169 if (ret != 0)
1170 return ret;
1171 ret = FAILED;
1172
7c3df132 1173 ql_log(ql_log_info, vha, 0x8012,
9cb78c16 1174 "BUS RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun);
1da177e4 1175
e315cd28 1176 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
7c3df132
SK		 1177 ql_log(ql_log_fatal, vha, 0x8013,
1178 "Wait for hba online failed board disabled.\n");
f4f051eb 1179 goto eh_bus_reset_done;
1da177e4
LT		 1180 }
1181
ad537689
SK		 1182 if (qla2x00_loop_reset(vha) == QLA_SUCCESS)
1183 ret = SUCCESS;
1184
f4f051eb 1185 if (ret == FAILED)
1186 goto eh_bus_reset_done;
1da177e4 1187
9a41a62b 1188 /* Flush outstanding commands. */
4d78c973 1189 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) !=
7c3df132
SK		 1190 QLA_SUCCESS) {
1191 ql_log(ql_log_warn, vha, 0x8014,
1192 "Wait for pending commands failed.\n");
9a41a62b 1193 ret = FAILED;
7c3df132 1194 }
1da177e4 1195
f4f051eb 1196eh_bus_reset_done:
7c3df132 1197 ql_log(ql_log_warn, vha, 0x802b,
9cb78c16 1198 "BUS RESET %s nexus=%ld:%d:%llu.\n",
d6a03581 1199 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1da177e4 1200
f4f051eb 1201 return ret;
1da177e4
LT		 1202}
1203
1204/**************************************************************************
1205* qla2xxx_eh_host_reset
1206*
1207* Description:
1208* The reset function will reset the Adapter.
1209*
1210* Input:
1211* cmd = Linux SCSI command packet of the command that cause the
1212* adapter reset.
1213*
1214* Returns:
1215* Either SUCCESS or FAILED.
1216*
1217* Note:
1218**************************************************************************/
e5f82ab8 1219static int
1da177e4
LT		 1220qla2xxx_eh_host_reset(struct scsi_cmnd *cmd)
1221{
e315cd28 1222 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
e315cd28 1223 struct qla_hw_data *ha = vha->hw;
2c3dfe3f 1224 int ret = FAILED;
9cb78c16
HR		 1225 unsigned int id;
1226 uint64_t lun;
e315cd28 1227 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4 1228
f4f051eb 1229 id = cmd->device->id;
1230 lun = cmd->device->lun;
f4f051eb 1231
7c3df132 1232 ql_log(ql_log_info, vha, 0x8018,
9cb78c16 1233 "ADAPTER RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun);
1da177e4 1234
63ee7072
CD		 1235 /*
1236 * No point in issuing another reset if one is active. Also do not
1237 * attempt a reset if we are updating flash.
1238 */
1239 if (qla2x00_reset_active(vha) || ha->optrom_state != QLA_SWAITING)
f4f051eb 1240 goto eh_host_reset_lock;
1da177e4 1241
e315cd28
AC		 1242 if (vha != base_vha) {
1243 if (qla2x00_vp_abort_isp(vha))
f4f051eb 1244 goto eh_host_reset_lock;
e315cd28 1245 } else {
7ec0effd 1246 if (IS_P3P_TYPE(vha->hw)) {
a9083016
GM		 1247 if (!qla82xx_fcoe_ctx_reset(vha)) {
1248 /* Ctx reset success */
1249 ret = SUCCESS;
1250 goto eh_host_reset_lock;
1251 }
1252 /* fall thru if ctx reset failed */
1253 }
68ca949c
AC		 1254 if (ha->wq)
1255 flush_workqueue(ha->wq);
1256
e315cd28 1257 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
a9083016 1258 if (ha->isp_ops->abort_isp(base_vha)) {
e315cd28
AC		 1259 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1260 /* failed. schedule dpc to try */
1261 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
1262
7c3df132
SK		 1263 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1264 ql_log(ql_log_warn, vha, 0x802a,
1265 "wait for hba online failed.\n");
e315cd28 1266 goto eh_host_reset_lock;
7c3df132 1267 }
e315cd28
AC		 1268 }
1269 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
fa2a1ce5 1270 }
1da177e4 1271
e315cd28 1272 /* Waiting for command to be returned to OS.*/
4d78c973 1273 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) ==
e315cd28 1274 QLA_SUCCESS)
f4f051eb 1275 ret = SUCCESS;
1da177e4 1276
f4f051eb 1277eh_host_reset_lock:
cfb0919c 1278 ql_log(ql_log_info, vha, 0x8017,
9cb78c16 1279 "ADAPTER RESET %s nexus=%ld:%d:%llu.\n",
cfb0919c 1280 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1da177e4 1281
f4f051eb 1282 return ret;
1283}
1da177e4
LT		 1284
1285/*
1286* qla2x00_loop_reset
1287* Issue loop reset.
1288*
1289* Input:
1290* ha = adapter block pointer.
1291*
1292* Returns:
1293* 0 = success
1294*/
a4722cf2 1295int
e315cd28 1296qla2x00_loop_reset(scsi_qla_host_t *vha)
1da177e4 1297{
0c8c39af 1298 int ret;
bdf79621 1299 struct fc_port *fcport;
e315cd28 1300 struct qla_hw_data *ha = vha->hw;
1da177e4 1301
5854771e
AB		 1302 if (IS_QLAFX00(ha)) {
1303 return qlafx00_loop_reset(vha);
1304 }
1305
f4c496c1 1306 if (ql2xtargetreset == 1 && ha->flags.enable_target_reset) {
55e5ed27
AV		 1307 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1308 if (fcport->port_type != FCT_TARGET)
1309 continue;
1310
1311 ret = ha->isp_ops->target_reset(fcport, 0, 0);
1312 if (ret != QLA_SUCCESS) {
7c3df132 1313 ql_dbg(ql_dbg_taskm, vha, 0x802c,
5854771e 1314 "Bus Reset failed: Reset=%d "
7c3df132 1315 "d_id=%x.\n", ret, fcport->d_id.b24);
55e5ed27
AV		 1316 }
1317 }
1318 }
1319
8ae6d9c7 1320
6246b8a1 1321 if (ha->flags.enable_lip_full_login && !IS_CNA_CAPABLE(ha)) {
0b7e7c53
AV		 1322 atomic_set(&vha->loop_state, LOOP_DOWN);
1323 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
1324 qla2x00_mark_all_devices_lost(vha, 0);
e315cd28 1325 ret = qla2x00_full_login_lip(vha);
0c8c39af 1326 if (ret != QLA_SUCCESS) {
7c3df132
SK		 1327 ql_dbg(ql_dbg_taskm, vha, 0x802d,
1328 "full_login_lip=%d.\n", ret);
749af3d5 1329 }
0c8c39af
AV		 1330 }
1331
0d6e61bc 1332 if (ha->flags.enable_lip_reset) {
e315cd28 1333 ret = qla2x00_lip_reset(vha);
ad537689 1334 if (ret != QLA_SUCCESS)
7c3df132
SK		 1335 ql_dbg(ql_dbg_taskm, vha, 0x802e,
1336 "lip_reset failed (%d).\n", ret);
1da177e4
LT		 1337 }
1338
1da177e4 1339 /* Issue marker command only when we are going to start the I/O */
e315cd28 1340 vha->marker_needed = 1;
1da177e4 1341
0c8c39af 1342 return QLA_SUCCESS;
1da177e4
LT		 1343}
1344
df4bf0bb 1345void
e315cd28 1346qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res)
df4bf0bb 1347{
73208dfd 1348 int que, cnt;
df4bf0bb
AV		 1349 unsigned long flags;
1350 srb_t *sp;
e315cd28 1351 struct qla_hw_data *ha = vha->hw;
73208dfd 1352 struct req_que *req;
df4bf0bb
AV		 1353
1354 spin_lock_irqsave(&ha->hardware_lock, flags);
2afa19a9 1355 for (que = 0; que < ha->max_req_queues; que++) {
29bdccbe 1356 req = ha->req_q_map[que];
73208dfd
AC		 1357 if (!req)
1358 continue;
8d93f550
CD		 1359 if (!req->outstanding_cmds)
1360 continue;
1361 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) {
73208dfd 1362 sp = req->outstanding_cmds[cnt];
e612d465 1363 if (sp) {
73208dfd 1364 req->outstanding_cmds[cnt] = NULL;
9ba56b95 1365 sp->done(vha, sp, res);
73208dfd 1366 }
df4bf0bb
AV		 1367 }
1368 }
1369 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1370}
1371
f4f051eb 1372static int
1373qla2xxx_slave_alloc(struct scsi_device *sdev)
1da177e4 1374{
bdf79621 1375 struct fc_rport *rport = starget_to_rport(scsi_target(sdev));
1da177e4 1376
19a7b4ae 1377 if (!rport || fc_remote_port_chkready(rport))
f4f051eb 1378 return -ENXIO;
bdf79621 1379
19a7b4ae 1380 sdev->hostdata = *(fc_port_t **)rport->dd_data;
1da177e4 1381
f4f051eb 1382 return 0;
1383}
1da177e4 1384
f4f051eb 1385static int
1386qla2xxx_slave_configure(struct scsi_device *sdev)
1387{
e315cd28 1388 scsi_qla_host_t *vha = shost_priv(sdev->host);
2afa19a9 1389 struct req_que *req = vha->req;
8482e118 1390
9e522cd8
AE		 1391 if (IS_T10_PI_CAPABLE(vha->hw))
1392 blk_queue_update_dma_alignment(sdev->request_queue, 0x7);
1393
f4f051eb 1394 if (sdev->tagged_supported)
73208dfd 1395 scsi_activate_tcq(sdev, req->max_q_depth);
f4f051eb 1396 else
73208dfd 1397 scsi_deactivate_tcq(sdev, req->max_q_depth);
f4f051eb 1398 return 0;
1399}
1da177e4 1400
f4f051eb 1401static void
1402qla2xxx_slave_destroy(struct scsi_device *sdev)
1403{
1404 sdev->hostdata = NULL;
1da177e4
LT		 1405}
1406
c45dd305
GM		 1407static void qla2x00_handle_queue_full(struct scsi_device *sdev, int qdepth)
1408{
1409 fc_port_t *fcport = (struct fc_port *) sdev->hostdata;
1410
1411 if (!scsi_track_queue_full(sdev, qdepth))
1412 return;
1413
7c3df132 1414 ql_dbg(ql_dbg_io, fcport->vha, 0x3029,
9cb78c16 1415 "Queue depth adjusted-down to %d for nexus=%ld:%d:%llu.\n",
cfb0919c 1416 sdev->queue_depth, fcport->vha->host_no, sdev->id, sdev->lun);
c45dd305
GM		 1417}
1418
1419static void qla2x00_adjust_sdev_qdepth_up(struct scsi_device *sdev, int qdepth)
1420{
1421 fc_port_t *fcport = sdev->hostdata;
1422 struct scsi_qla_host *vha = fcport->vha;
c45dd305
GM		 1423 struct req_que *req = NULL;
1424
1425 req = vha->req;
1426 if (!req)
1427 return;
1428
1429 if (req->max_q_depth <= sdev->queue_depth || req->max_q_depth < qdepth)
1430 return;
1431
1432 if (sdev->ordered_tags)
1433 scsi_adjust_queue_depth(sdev, MSG_ORDERED_TAG, qdepth);
1434 else
1435 scsi_adjust_queue_depth(sdev, MSG_SIMPLE_TAG, qdepth);
1436
7c3df132 1437 ql_dbg(ql_dbg_io, vha, 0x302a,
9cb78c16 1438 "Queue depth adjusted-up to %d for nexus=%ld:%d:%llu.\n",
cfb0919c 1439 sdev->queue_depth, fcport->vha->host_no, sdev->id, sdev->lun);
c45dd305
GM		 1440}
1441
ce7e4af7 1442static int
e881a172 1443qla2x00_change_queue_depth(struct scsi_device *sdev, int qdepth, int reason)
ce7e4af7 1444{
c45dd305
GM		 1445 switch (reason) {
1446 case SCSI_QDEPTH_DEFAULT:
1447 scsi_adjust_queue_depth(sdev, scsi_get_tag_type(sdev), qdepth);
1448 break;
1449 case SCSI_QDEPTH_QFULL:
1450 qla2x00_handle_queue_full(sdev, qdepth);
1451 break;
1452 case SCSI_QDEPTH_RAMP_UP:
1453 qla2x00_adjust_sdev_qdepth_up(sdev, qdepth);
1454 break;
1455 default:
08002af2 1456 return -EOPNOTSUPP;
c45dd305 1457 }
e881a172 1458
ce7e4af7
AV		 1459 return sdev->queue_depth;
1460}
1461
1462static int
1463qla2x00_change_queue_type(struct scsi_device *sdev, int tag_type)
1464{
1465 if (sdev->tagged_supported) {
1466 scsi_set_tag_type(sdev, tag_type);
1467 if (tag_type)
1468 scsi_activate_tcq(sdev, sdev->queue_depth);
1469 else
1470 scsi_deactivate_tcq(sdev, sdev->queue_depth);
1471 } else
1472 tag_type = 0;
1473
1474 return tag_type;
1475}
1476
1da177e4
LT		 1477/**
1478 * qla2x00_config_dma_addressing() - Configure OS DMA addressing method.
1479 * @ha: HA context
1480 *
1481 * At exit, the @ha's flags.enable_64bit_addressing set to indicated
1482 * supported addressing method.
1483 */
1484static void
53303c42 1485qla2x00_config_dma_addressing(struct qla_hw_data *ha)
1da177e4 1486{
7524f9b9 1487 /* Assume a 32bit DMA mask. */
1da177e4 1488 ha->flags.enable_64bit_addressing = 0;
1da177e4 1489
6a35528a 1490 if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) {
7524f9b9
AV		 1491 /* Any upper-dword bits set? */
1492 if (MSD(dma_get_required_mask(&ha->pdev->dev)) &&
6a35528a 1493 !pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(64))) {
7524f9b9 1494 /* Ok, a 64bit DMA mask is applicable. */
1da177e4 1495 ha->flags.enable_64bit_addressing = 1;
fd34f556
AV		 1496 ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64;
1497 ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64;
7524f9b9 1498 return;
1da177e4 1499 }
1da177e4 1500 }
7524f9b9 1501
284901a9
YH		 1502 dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32));
1503 pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(32));
1da177e4
LT		 1504}
1505
fd34f556 1506static void
e315cd28 1507qla2x00_enable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1508{
1509 unsigned long flags = 0;
1510 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1511
1512 spin_lock_irqsave(&ha->hardware_lock, flags);
1513 ha->interrupts_on = 1;
1514 /* enable risc and host interrupts */
1515 WRT_REG_WORD(&reg->ictrl, ICR_EN_INT | ICR_EN_RISC);
1516 RD_REG_WORD(&reg->ictrl);
1517 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1518
1519}
1520
1521static void
e315cd28 1522qla2x00_disable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1523{
1524 unsigned long flags = 0;
1525 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1526
1527 spin_lock_irqsave(&ha->hardware_lock, flags);
1528 ha->interrupts_on = 0;
1529 /* disable risc and host interrupts */
1530 WRT_REG_WORD(&reg->ictrl, 0);
1531 RD_REG_WORD(&reg->ictrl);
1532 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1533}
1534
1535static void
e315cd28 1536qla24xx_enable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1537{
1538 unsigned long flags = 0;
1539 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1540
1541 spin_lock_irqsave(&ha->hardware_lock, flags);
1542 ha->interrupts_on = 1;
1543 WRT_REG_DWORD(&reg->ictrl, ICRX_EN_RISC_INT);
1544 RD_REG_DWORD(&reg->ictrl);
1545 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1546}
1547
1548static void
e315cd28 1549qla24xx_disable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1550{
1551 unsigned long flags = 0;
1552 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1553
124f85e6
AV		 1554 if (IS_NOPOLLING_TYPE(ha))
1555 return;
fd34f556
AV		 1556 spin_lock_irqsave(&ha->hardware_lock, flags);
1557 ha->interrupts_on = 0;
1558 WRT_REG_DWORD(&reg->ictrl, 0);
1559 RD_REG_DWORD(&reg->ictrl);
1560 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1561}
1562
706f457d
GM		 1563static int
1564qla2x00_iospace_config(struct qla_hw_data *ha)
1565{
1566 resource_size_t pio;
1567 uint16_t msix;
1568 int cpus;
1569
706f457d
GM		 1570 if (pci_request_selected_regions(ha->pdev, ha->bars,
1571 QLA2XXX_DRIVER_NAME)) {
1572 ql_log_pci(ql_log_fatal, ha->pdev, 0x0011,
1573 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
1574 pci_name(ha->pdev));
1575 goto iospace_error_exit;
1576 }
1577 if (!(ha->bars & 1))
1578 goto skip_pio;
1579
1580 /* We only need PIO for Flash operations on ISP2312 v2 chips. */
1581 pio = pci_resource_start(ha->pdev, 0);
1582 if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) {
1583 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
1584 ql_log_pci(ql_log_warn, ha->pdev, 0x0012,
1585 "Invalid pci I/O region size (%s).\n",
1586 pci_name(ha->pdev));
1587 pio = 0;
1588 }
1589 } else {
1590 ql_log_pci(ql_log_warn, ha->pdev, 0x0013,
1591 "Region #0 no a PIO resource (%s).\n",
1592 pci_name(ha->pdev));
1593 pio = 0;
1594 }
1595 ha->pio_address = pio;
1596 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014,
1597 "PIO address=%llu.\n",
1598 (unsigned long long)ha->pio_address);
1599
1600skip_pio:
1601 /* Use MMIO operations for all accesses. */
1602 if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) {
1603 ql_log_pci(ql_log_fatal, ha->pdev, 0x0015,
1604 "Region #1 not an MMIO resource (%s), aborting.\n",
1605 pci_name(ha->pdev));
1606 goto iospace_error_exit;
1607 }
1608 if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) {
1609 ql_log_pci(ql_log_fatal, ha->pdev, 0x0016,
1610 "Invalid PCI mem region size (%s), aborting.\n",
1611 pci_name(ha->pdev));
1612 goto iospace_error_exit;
1613 }
1614
1615 ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN);
1616 if (!ha->iobase) {
1617 ql_log_pci(ql_log_fatal, ha->pdev, 0x0017,
1618 "Cannot remap MMIO (%s), aborting.\n",
1619 pci_name(ha->pdev));
1620 goto iospace_error_exit;
1621 }
1622
1623 /* Determine queue resources */
1624 ha->max_req_queues = ha->max_rsp_queues = 1;
1625 if ((ql2xmaxqueues <= 1 && !ql2xmultique_tag) ||
1626 (ql2xmaxqueues > 1 && ql2xmultique_tag) ||
1627 (!IS_QLA25XX(ha) && !IS_QLA81XX(ha)))
1628 goto mqiobase_exit;
1629
1630 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3),
1631 pci_resource_len(ha->pdev, 3));
1632 if (ha->mqiobase) {
1633 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018,
1634 "MQIO Base=%p.\n", ha->mqiobase);
1635 /* Read MSIX vector size of the board */
1636 pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix);
1637 ha->msix_count = msix;
1638 /* Max queues are bounded by available msix vectors */
1639 /* queue 0 uses two msix vectors */
1640 if (ql2xmultique_tag) {
1641 cpus = num_online_cpus();
1642 ha->max_rsp_queues = (ha->msix_count - 1 > cpus) ?
1643 (cpus + 1) : (ha->msix_count - 1);
1644 ha->max_req_queues = 2;
1645 } else if (ql2xmaxqueues > 1) {
1646 ha->max_req_queues = ql2xmaxqueues > QLA_MQ_SIZE ?
1647 QLA_MQ_SIZE : ql2xmaxqueues;
1648 ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc008,
1649 "QoS mode set, max no of request queues:%d.\n",
1650 ha->max_req_queues);
1651 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0019,
1652 "QoS mode set, max no of request queues:%d.\n",
1653 ha->max_req_queues);
1654 }
1655 ql_log_pci(ql_log_info, ha->pdev, 0x001a,
1656 "MSI-X vector count: %d.\n", msix);
1657 } else
1658 ql_log_pci(ql_log_info, ha->pdev, 0x001b,
1659 "BAR 3 not enabled.\n");
1660
1661mqiobase_exit:
1662 ha->msix_count = ha->max_rsp_queues + 1;
1663 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c,
1664 "MSIX Count:%d.\n", ha->msix_count);
1665 return (0);
1666
1667iospace_error_exit:
1668 return (-ENOMEM);
1669}
1670
1671
6246b8a1
GM		 1672static int
1673qla83xx_iospace_config(struct qla_hw_data *ha)
1674{
1675 uint16_t msix;
1676 int cpus;
1677
1678 if (pci_request_selected_regions(ha->pdev, ha->bars,
1679 QLA2XXX_DRIVER_NAME)) {
1680 ql_log_pci(ql_log_fatal, ha->pdev, 0x0117,
1681 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
1682 pci_name(ha->pdev));
1683
1684 goto iospace_error_exit;
1685 }
1686
1687 /* Use MMIO operations for all accesses. */
1688 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) {
1689 ql_log_pci(ql_log_warn, ha->pdev, 0x0118,
1690 "Invalid pci I/O region size (%s).\n",
1691 pci_name(ha->pdev));
1692 goto iospace_error_exit;
1693 }
1694 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
1695 ql_log_pci(ql_log_warn, ha->pdev, 0x0119,
1696 "Invalid PCI mem region size (%s), aborting\n",
1697 pci_name(ha->pdev));
1698 goto iospace_error_exit;
1699 }
1700
1701 ha->iobase = ioremap(pci_resource_start(ha->pdev, 0), MIN_IOBASE_LEN);
1702 if (!ha->iobase) {
1703 ql_log_pci(ql_log_fatal, ha->pdev, 0x011a,
1704 "Cannot remap MMIO (%s), aborting.\n",
1705 pci_name(ha->pdev));
1706 goto iospace_error_exit;
1707 }
1708
1709 /* 64bit PCI BAR - BAR2 will correspoond to region 4 */
1710 /* 83XX 26XX always use MQ type access for queues
1711 * - mbar 2, a.k.a region 4 */
1712 ha->max_req_queues = ha->max_rsp_queues = 1;
1713 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 4),
1714 pci_resource_len(ha->pdev, 4));
1715
1716 if (!ha->mqiobase) {
1717 ql_log_pci(ql_log_fatal, ha->pdev, 0x011d,
1718 "BAR2/region4 not enabled\n");
1719 goto mqiobase_exit;
1720 }
1721
1722 ha->msixbase = ioremap(pci_resource_start(ha->pdev, 2),
1723 pci_resource_len(ha->pdev, 2));
1724 if (ha->msixbase) {
1725 /* Read MSIX vector size of the board */
1726 pci_read_config_word(ha->pdev,
1727 QLA_83XX_PCI_MSIX_CONTROL, &msix);
1728 ha->msix_count = msix;
1729 /* Max queues are bounded by available msix vectors */
1730 /* queue 0 uses two msix vectors */
1731 if (ql2xmultique_tag) {
1732 cpus = num_online_cpus();
1733 ha->max_rsp_queues = (ha->msix_count - 1 > cpus) ?
1734 (cpus + 1) : (ha->msix_count - 1);
1735 ha->max_req_queues = 2;
1736 } else if (ql2xmaxqueues > 1) {
1737 ha->max_req_queues = ql2xmaxqueues > QLA_MQ_SIZE ?
1738 QLA_MQ_SIZE : ql2xmaxqueues;
1739 ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc00c,
1740 "QoS mode set, max no of request queues:%d.\n",
1741 ha->max_req_queues);
1742 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b,
1743 "QoS mode set, max no of request queues:%d.\n",
1744 ha->max_req_queues);
1745 }
1746 ql_log_pci(ql_log_info, ha->pdev, 0x011c,
1747 "MSI-X vector count: %d.\n", msix);
1748 } else
1749 ql_log_pci(ql_log_info, ha->pdev, 0x011e,
1750 "BAR 1 not enabled.\n");
1751
1752mqiobase_exit:
1753 ha->msix_count = ha->max_rsp_queues + 1;
aa230bc5
AE		 1754
1755 qlt_83xx_iospace_config(ha);
1756
6246b8a1
GM		 1757 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011f,
1758 "MSIX Count:%d.\n", ha->msix_count);
1759 return 0;
1760
1761iospace_error_exit:
1762 return -ENOMEM;
1763}
1764
fd34f556
AV		 1765static struct isp_operations qla2100_isp_ops = {
1766 .pci_config = qla2100_pci_config,
1767 .reset_chip = qla2x00_reset_chip,
1768 .chip_diag = qla2x00_chip_diag,
1769 .config_rings = qla2x00_config_rings,
1770 .reset_adapter = qla2x00_reset_adapter,
1771 .nvram_config = qla2x00_nvram_config,
1772 .update_fw_options = qla2x00_update_fw_options,
1773 .load_risc = qla2x00_load_risc,
1774 .pci_info_str = qla2x00_pci_info_str,
1775 .fw_version_str = qla2x00_fw_version_str,
1776 .intr_handler = qla2100_intr_handler,
1777 .enable_intrs = qla2x00_enable_intrs,
1778 .disable_intrs = qla2x00_disable_intrs,
1779 .abort_command = qla2x00_abort_command,
523ec773
AV		 1780 .target_reset = qla2x00_abort_target,
1781 .lun_reset = qla2x00_lun_reset,
fd34f556
AV		 1782 .fabric_login = qla2x00_login_fabric,
1783 .fabric_logout = qla2x00_fabric_logout,
1784 .calc_req_entries = qla2x00_calc_iocbs_32,
1785 .build_iocbs = qla2x00_build_scsi_iocbs_32,
1786 .prep_ms_iocb = qla2x00_prep_ms_iocb,
1787 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
1788 .read_nvram = qla2x00_read_nvram_data,
1789 .write_nvram = qla2x00_write_nvram_data,
1790 .fw_dump = qla2100_fw_dump,
1791 .beacon_on = NULL,
1792 .beacon_off = NULL,
1793 .beacon_blink = NULL,
1794 .read_optrom = qla2x00_read_optrom_data,
1795 .write_optrom = qla2x00_write_optrom_data,
1796 .get_flash_version = qla2x00_get_flash_version,
e315cd28 1797 .start_scsi = qla2x00_start_scsi,
a9083016 1798 .abort_isp = qla2x00_abort_isp,
706f457d 1799 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 1800 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 1801};
1802
1803static struct isp_operations qla2300_isp_ops = {
1804 .pci_config = qla2300_pci_config,
1805 .reset_chip = qla2x00_reset_chip,
1806 .chip_diag = qla2x00_chip_diag,
1807 .config_rings = qla2x00_config_rings,
1808 .reset_adapter = qla2x00_reset_adapter,
1809 .nvram_config = qla2x00_nvram_config,
1810 .update_fw_options = qla2x00_update_fw_options,
1811 .load_risc = qla2x00_load_risc,
1812 .pci_info_str = qla2x00_pci_info_str,
1813 .fw_version_str = qla2x00_fw_version_str,
1814 .intr_handler = qla2300_intr_handler,
1815 .enable_intrs = qla2x00_enable_intrs,
1816 .disable_intrs = qla2x00_disable_intrs,
1817 .abort_command = qla2x00_abort_command,
523ec773
AV		 1818 .target_reset = qla2x00_abort_target,
1819 .lun_reset = qla2x00_lun_reset,
fd34f556
AV		 1820 .fabric_login = qla2x00_login_fabric,
1821 .fabric_logout = qla2x00_fabric_logout,
1822 .calc_req_entries = qla2x00_calc_iocbs_32,
1823 .build_iocbs = qla2x00_build_scsi_iocbs_32,
1824 .prep_ms_iocb = qla2x00_prep_ms_iocb,
1825 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
1826 .read_nvram = qla2x00_read_nvram_data,
1827 .write_nvram = qla2x00_write_nvram_data,
1828 .fw_dump = qla2300_fw_dump,
1829 .beacon_on = qla2x00_beacon_on,
1830 .beacon_off = qla2x00_beacon_off,
1831 .beacon_blink = qla2x00_beacon_blink,
1832 .read_optrom = qla2x00_read_optrom_data,
1833 .write_optrom = qla2x00_write_optrom_data,
1834 .get_flash_version = qla2x00_get_flash_version,
e315cd28 1835 .start_scsi = qla2x00_start_scsi,
a9083016 1836 .abort_isp = qla2x00_abort_isp,
7ec0effd 1837 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 1838 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 1839};
1840
1841static struct isp_operations qla24xx_isp_ops = {
1842 .pci_config = qla24xx_pci_config,
1843 .reset_chip = qla24xx_reset_chip,
1844 .chip_diag = qla24xx_chip_diag,
1845 .config_rings = qla24xx_config_rings,
1846 .reset_adapter = qla24xx_reset_adapter,
1847 .nvram_config = qla24xx_nvram_config,
1848 .update_fw_options = qla24xx_update_fw_options,
1849 .load_risc = qla24xx_load_risc,
1850 .pci_info_str = qla24xx_pci_info_str,
1851 .fw_version_str = qla24xx_fw_version_str,
1852 .intr_handler = qla24xx_intr_handler,
1853 .enable_intrs = qla24xx_enable_intrs,
1854 .disable_intrs = qla24xx_disable_intrs,
1855 .abort_command = qla24xx_abort_command,
523ec773
AV		 1856 .target_reset = qla24xx_abort_target,
1857 .lun_reset = qla24xx_lun_reset,
fd34f556
AV		 1858 .fabric_login = qla24xx_login_fabric,
1859 .fabric_logout = qla24xx_fabric_logout,
1860 .calc_req_entries = NULL,
1861 .build_iocbs = NULL,
1862 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1863 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1864 .read_nvram = qla24xx_read_nvram_data,
1865 .write_nvram = qla24xx_write_nvram_data,
1866 .fw_dump = qla24xx_fw_dump,
1867 .beacon_on = qla24xx_beacon_on,
1868 .beacon_off = qla24xx_beacon_off,
1869 .beacon_blink = qla24xx_beacon_blink,
1870 .read_optrom = qla24xx_read_optrom_data,
1871 .write_optrom = qla24xx_write_optrom_data,
1872 .get_flash_version = qla24xx_get_flash_version,
e315cd28 1873 .start_scsi = qla24xx_start_scsi,
a9083016 1874 .abort_isp = qla2x00_abort_isp,
7ec0effd 1875 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 1876 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 1877};
1878
c3a2f0df
AV		 1879static struct isp_operations qla25xx_isp_ops = {
1880 .pci_config = qla25xx_pci_config,
1881 .reset_chip = qla24xx_reset_chip,
1882 .chip_diag = qla24xx_chip_diag,
1883 .config_rings = qla24xx_config_rings,
1884 .reset_adapter = qla24xx_reset_adapter,
1885 .nvram_config = qla24xx_nvram_config,
1886 .update_fw_options = qla24xx_update_fw_options,
1887 .load_risc = qla24xx_load_risc,
1888 .pci_info_str = qla24xx_pci_info_str,
1889 .fw_version_str = qla24xx_fw_version_str,
1890 .intr_handler = qla24xx_intr_handler,
1891 .enable_intrs = qla24xx_enable_intrs,
1892 .disable_intrs = qla24xx_disable_intrs,
1893 .abort_command = qla24xx_abort_command,
523ec773
AV		 1894 .target_reset = qla24xx_abort_target,
1895 .lun_reset = qla24xx_lun_reset,
c3a2f0df
AV		 1896 .fabric_login = qla24xx_login_fabric,
1897 .fabric_logout = qla24xx_fabric_logout,
1898 .calc_req_entries = NULL,
1899 .build_iocbs = NULL,
1900 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1901 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1902 .read_nvram = qla25xx_read_nvram_data,
1903 .write_nvram = qla25xx_write_nvram_data,
1904 .fw_dump = qla25xx_fw_dump,
1905 .beacon_on = qla24xx_beacon_on,
1906 .beacon_off = qla24xx_beacon_off,
1907 .beacon_blink = qla24xx_beacon_blink,
338c9161 1908 .read_optrom = qla25xx_read_optrom_data,
c3a2f0df
AV		 1909 .write_optrom = qla24xx_write_optrom_data,
1910 .get_flash_version = qla24xx_get_flash_version,
bad75002 1911 .start_scsi = qla24xx_dif_start_scsi,
a9083016 1912 .abort_isp = qla2x00_abort_isp,
7ec0effd 1913 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 1914 .initialize_adapter = qla2x00_initialize_adapter,
c3a2f0df
AV		 1915};
1916
3a03eb79
AV		 1917static struct isp_operations qla81xx_isp_ops = {
1918 .pci_config = qla25xx_pci_config,
1919 .reset_chip = qla24xx_reset_chip,
1920 .chip_diag = qla24xx_chip_diag,
1921 .config_rings = qla24xx_config_rings,
1922 .reset_adapter = qla24xx_reset_adapter,
1923 .nvram_config = qla81xx_nvram_config,
1924 .update_fw_options = qla81xx_update_fw_options,
eaac30be 1925 .load_risc = qla81xx_load_risc,
3a03eb79
AV		 1926 .pci_info_str = qla24xx_pci_info_str,
1927 .fw_version_str = qla24xx_fw_version_str,
1928 .intr_handler = qla24xx_intr_handler,
1929 .enable_intrs = qla24xx_enable_intrs,
1930 .disable_intrs = qla24xx_disable_intrs,
1931 .abort_command = qla24xx_abort_command,
1932 .target_reset = qla24xx_abort_target,
1933 .lun_reset = qla24xx_lun_reset,
1934 .fabric_login = qla24xx_login_fabric,
1935 .fabric_logout = qla24xx_fabric_logout,
1936 .calc_req_entries = NULL,
1937 .build_iocbs = NULL,
1938 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1939 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
3d79038f
AV		 1940 .read_nvram = NULL,
1941 .write_nvram = NULL,
3a03eb79
AV		 1942 .fw_dump = qla81xx_fw_dump,
1943 .beacon_on = qla24xx_beacon_on,
1944 .beacon_off = qla24xx_beacon_off,
6246b8a1 1945 .beacon_blink = qla83xx_beacon_blink,
3a03eb79
AV		 1946 .read_optrom = qla25xx_read_optrom_data,
1947 .write_optrom = qla24xx_write_optrom_data,
1948 .get_flash_version = qla24xx_get_flash_version,
ba77ef53 1949 .start_scsi = qla24xx_dif_start_scsi,
a9083016 1950 .abort_isp = qla2x00_abort_isp,
7ec0effd 1951 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 1952 .initialize_adapter = qla2x00_initialize_adapter,
a9083016
GM		 1953};
1954
1955static struct isp_operations qla82xx_isp_ops = {
1956 .pci_config = qla82xx_pci_config,
1957 .reset_chip = qla82xx_reset_chip,
1958 .chip_diag = qla24xx_chip_diag,
1959 .config_rings = qla82xx_config_rings,
1960 .reset_adapter = qla24xx_reset_adapter,
1961 .nvram_config = qla81xx_nvram_config,
1962 .update_fw_options = qla24xx_update_fw_options,
1963 .load_risc = qla82xx_load_risc,
9d55ca66 1964 .pci_info_str = qla24xx_pci_info_str,
a9083016
GM		 1965 .fw_version_str = qla24xx_fw_version_str,
1966 .intr_handler = qla82xx_intr_handler,
1967 .enable_intrs = qla82xx_enable_intrs,
1968 .disable_intrs = qla82xx_disable_intrs,
1969 .abort_command = qla24xx_abort_command,
1970 .target_reset = qla24xx_abort_target,
1971 .lun_reset = qla24xx_lun_reset,
1972 .fabric_login = qla24xx_login_fabric,
1973 .fabric_logout = qla24xx_fabric_logout,
1974 .calc_req_entries = NULL,
1975 .build_iocbs = NULL,
1976 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1977 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1978 .read_nvram = qla24xx_read_nvram_data,
1979 .write_nvram = qla24xx_write_nvram_data,
a1b23c5a 1980 .fw_dump = qla82xx_fw_dump,
999916dc
SK		 1981 .beacon_on = qla82xx_beacon_on,
1982 .beacon_off = qla82xx_beacon_off,
1983 .beacon_blink = NULL,
a9083016
GM		 1984 .read_optrom = qla82xx_read_optrom_data,
1985 .write_optrom = qla82xx_write_optrom_data,
7ec0effd 1986 .get_flash_version = qla82xx_get_flash_version,
a9083016
GM		 1987 .start_scsi = qla82xx_start_scsi,
1988 .abort_isp = qla82xx_abort_isp,
706f457d 1989 .iospace_config = qla82xx_iospace_config,
8ae6d9c7 1990 .initialize_adapter = qla2x00_initialize_adapter,
3a03eb79
AV		 1991};
1992
7ec0effd
AD		 1993static struct isp_operations qla8044_isp_ops = {
1994 .pci_config = qla82xx_pci_config,
1995 .reset_chip = qla82xx_reset_chip,
1996 .chip_diag = qla24xx_chip_diag,
1997 .config_rings = qla82xx_config_rings,
1998 .reset_adapter = qla24xx_reset_adapter,
1999 .nvram_config = qla81xx_nvram_config,
2000 .update_fw_options = qla24xx_update_fw_options,
2001 .load_risc = qla82xx_load_risc,
2002 .pci_info_str = qla24xx_pci_info_str,
2003 .fw_version_str = qla24xx_fw_version_str,
2004 .intr_handler = qla8044_intr_handler,
2005 .enable_intrs = qla82xx_enable_intrs,
2006 .disable_intrs = qla82xx_disable_intrs,
2007 .abort_command = qla24xx_abort_command,
2008 .target_reset = qla24xx_abort_target,
2009 .lun_reset = qla24xx_lun_reset,
2010 .fabric_login = qla24xx_login_fabric,
2011 .fabric_logout = qla24xx_fabric_logout,
2012 .calc_req_entries = NULL,
2013 .build_iocbs = NULL,
2014 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2015 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2016 .read_nvram = NULL,
2017 .write_nvram = NULL,
a1b23c5a 2018 .fw_dump = qla8044_fw_dump,
7ec0effd
AD		 2019 .beacon_on = qla82xx_beacon_on,
2020 .beacon_off = qla82xx_beacon_off,
2021 .beacon_blink = NULL,
888e639d 2022 .read_optrom = qla8044_read_optrom_data,
7ec0effd
AD		 2023 .write_optrom = qla8044_write_optrom_data,
2024 .get_flash_version = qla82xx_get_flash_version,
2025 .start_scsi = qla82xx_start_scsi,
2026 .abort_isp = qla8044_abort_isp,
2027 .iospace_config = qla82xx_iospace_config,
2028 .initialize_adapter = qla2x00_initialize_adapter,
2029};
2030
6246b8a1
GM		 2031static struct isp_operations qla83xx_isp_ops = {
2032 .pci_config = qla25xx_pci_config,
2033 .reset_chip = qla24xx_reset_chip,
2034 .chip_diag = qla24xx_chip_diag,
2035 .config_rings = qla24xx_config_rings,
2036 .reset_adapter = qla24xx_reset_adapter,
2037 .nvram_config = qla81xx_nvram_config,
2038 .update_fw_options = qla81xx_update_fw_options,
2039 .load_risc = qla81xx_load_risc,
2040 .pci_info_str = qla24xx_pci_info_str,
2041 .fw_version_str = qla24xx_fw_version_str,
2042 .intr_handler = qla24xx_intr_handler,
2043 .enable_intrs = qla24xx_enable_intrs,
2044 .disable_intrs = qla24xx_disable_intrs,
2045 .abort_command = qla24xx_abort_command,
2046 .target_reset = qla24xx_abort_target,
2047 .lun_reset = qla24xx_lun_reset,
2048 .fabric_login = qla24xx_login_fabric,
2049 .fabric_logout = qla24xx_fabric_logout,
2050 .calc_req_entries = NULL,
2051 .build_iocbs = NULL,
2052 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2053 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2054 .read_nvram = NULL,
2055 .write_nvram = NULL,
2056 .fw_dump = qla83xx_fw_dump,
2057 .beacon_on = qla24xx_beacon_on,
2058 .beacon_off = qla24xx_beacon_off,
2059 .beacon_blink = qla83xx_beacon_blink,
2060 .read_optrom = qla25xx_read_optrom_data,
2061 .write_optrom = qla24xx_write_optrom_data,
2062 .get_flash_version = qla24xx_get_flash_version,
2063 .start_scsi = qla24xx_dif_start_scsi,
2064 .abort_isp = qla2x00_abort_isp,
2065 .iospace_config = qla83xx_iospace_config,
8ae6d9c7
GM		 2066 .initialize_adapter = qla2x00_initialize_adapter,
2067};
2068
2069static struct isp_operations qlafx00_isp_ops = {
2070 .pci_config = qlafx00_pci_config,
2071 .reset_chip = qlafx00_soft_reset,
2072 .chip_diag = qlafx00_chip_diag,
2073 .config_rings = qlafx00_config_rings,
2074 .reset_adapter = qlafx00_soft_reset,
2075 .nvram_config = NULL,
2076 .update_fw_options = NULL,
2077 .load_risc = NULL,
2078 .pci_info_str = qlafx00_pci_info_str,
2079 .fw_version_str = qlafx00_fw_version_str,
2080 .intr_handler = qlafx00_intr_handler,
2081 .enable_intrs = qlafx00_enable_intrs,
2082 .disable_intrs = qlafx00_disable_intrs,
4440e46d 2083 .abort_command = qla24xx_async_abort_command,
8ae6d9c7
GM		 2084 .target_reset = qlafx00_abort_target,
2085 .lun_reset = qlafx00_lun_reset,
2086 .fabric_login = NULL,
2087 .fabric_logout = NULL,
2088 .calc_req_entries = NULL,
2089 .build_iocbs = NULL,
2090 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2091 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2092 .read_nvram = qla24xx_read_nvram_data,
2093 .write_nvram = qla24xx_write_nvram_data,
2094 .fw_dump = NULL,
2095 .beacon_on = qla24xx_beacon_on,
2096 .beacon_off = qla24xx_beacon_off,
2097 .beacon_blink = NULL,
2098 .read_optrom = qla24xx_read_optrom_data,
2099 .write_optrom = qla24xx_write_optrom_data,
2100 .get_flash_version = qla24xx_get_flash_version,
2101 .start_scsi = qlafx00_start_scsi,
2102 .abort_isp = qlafx00_abort_isp,
2103 .iospace_config = qlafx00_iospace_config,
2104 .initialize_adapter = qlafx00_initialize_adapter,
6246b8a1
GM		 2105};
2106
f73cb695
CD		 2107static struct isp_operations qla27xx_isp_ops = {
2108 .pci_config = qla25xx_pci_config,
2109 .reset_chip = qla24xx_reset_chip,
2110 .chip_diag = qla24xx_chip_diag,
2111 .config_rings = qla24xx_config_rings,
2112 .reset_adapter = qla24xx_reset_adapter,
2113 .nvram_config = qla81xx_nvram_config,
2114 .update_fw_options = qla81xx_update_fw_options,
2115 .load_risc = qla81xx_load_risc,
2116 .pci_info_str = qla24xx_pci_info_str,
2117 .fw_version_str = qla24xx_fw_version_str,
2118 .intr_handler = qla24xx_intr_handler,
2119 .enable_intrs = qla24xx_enable_intrs,
2120 .disable_intrs = qla24xx_disable_intrs,
2121 .abort_command = qla24xx_abort_command,
2122 .target_reset = qla24xx_abort_target,
2123 .lun_reset = qla24xx_lun_reset,
2124 .fabric_login = qla24xx_login_fabric,
2125 .fabric_logout = qla24xx_fabric_logout,
2126 .calc_req_entries = NULL,
2127 .build_iocbs = NULL,
2128 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2129 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2130 .read_nvram = NULL,
2131 .write_nvram = NULL,
2132 .fw_dump = qla27xx_fwdump,
2133 .beacon_on = qla24xx_beacon_on,
2134 .beacon_off = qla24xx_beacon_off,
2135 .beacon_blink = qla83xx_beacon_blink,
2136 .read_optrom = qla25xx_read_optrom_data,
2137 .write_optrom = qla24xx_write_optrom_data,
2138 .get_flash_version = qla24xx_get_flash_version,
2139 .start_scsi = qla24xx_dif_start_scsi,
2140 .abort_isp = qla2x00_abort_isp,
2141 .iospace_config = qla83xx_iospace_config,
2142 .initialize_adapter = qla2x00_initialize_adapter,
2143};
2144
ea5b6382 2145static inline void
e315cd28 2146qla2x00_set_isp_flags(struct qla_hw_data *ha)
ea5b6382 2147{
2148 ha->device_type = DT_EXTENDED_IDS;
2149 switch (ha->pdev->device) {
2150 case PCI_DEVICE_ID_QLOGIC_ISP2100:
2151 ha->device_type |= DT_ISP2100;
2152 ha->device_type &= ~DT_EXTENDED_IDS;
441d1072 2153 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
ea5b6382 2154 break;
2155 case PCI_DEVICE_ID_QLOGIC_ISP2200:
2156 ha->device_type |= DT_ISP2200;
2157 ha->device_type &= ~DT_EXTENDED_IDS;
441d1072 2158 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
ea5b6382 2159 break;
2160 case PCI_DEVICE_ID_QLOGIC_ISP2300:
2161 ha->device_type |= DT_ISP2300;
4a59f71d 2162 ha->device_type |= DT_ZIO_SUPPORTED;
441d1072 2163 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 2164 break;
2165 case PCI_DEVICE_ID_QLOGIC_ISP2312:
2166 ha->device_type |= DT_ISP2312;
4a59f71d 2167 ha->device_type |= DT_ZIO_SUPPORTED;
441d1072 2168 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 2169 break;
2170 case PCI_DEVICE_ID_QLOGIC_ISP2322:
2171 ha->device_type |= DT_ISP2322;
4a59f71d 2172 ha->device_type |= DT_ZIO_SUPPORTED;
ea5b6382 2173 if (ha->pdev->subsystem_vendor == 0x1028 &&
2174 ha->pdev->subsystem_device == 0x0170)
2175 ha->device_type |= DT_OEM_001;
441d1072 2176 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 2177 break;
2178 case PCI_DEVICE_ID_QLOGIC_ISP6312:
2179 ha->device_type |= DT_ISP6312;
441d1072 2180 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 2181 break;
2182 case PCI_DEVICE_ID_QLOGIC_ISP6322:
2183 ha->device_type |= DT_ISP6322;
441d1072 2184 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 2185 break;
2186 case PCI_DEVICE_ID_QLOGIC_ISP2422:
2187 ha->device_type |= DT_ISP2422;
4a59f71d 2188 ha->device_type |= DT_ZIO_SUPPORTED;
e428924c 2189 ha->device_type |= DT_FWI2;
c76f2c01 2190 ha->device_type |= DT_IIDMA;
441d1072 2191 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2192 break;
2193 case PCI_DEVICE_ID_QLOGIC_ISP2432:
2194 ha->device_type |= DT_ISP2432;
4a59f71d 2195 ha->device_type |= DT_ZIO_SUPPORTED;
e428924c 2196 ha->device_type |= DT_FWI2;
c76f2c01 2197 ha->device_type |= DT_IIDMA;
441d1072 2198 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2199 break;
4d4df193
HK		 2200 case PCI_DEVICE_ID_QLOGIC_ISP8432:
2201 ha->device_type |= DT_ISP8432;
2202 ha->device_type |= DT_ZIO_SUPPORTED;
2203 ha->device_type |= DT_FWI2;
2204 ha->device_type |= DT_IIDMA;
2205 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2206 break;
044cc6c8 2207 case PCI_DEVICE_ID_QLOGIC_ISP5422:
2208 ha->device_type |= DT_ISP5422;
e428924c 2209 ha->device_type |= DT_FWI2;
441d1072 2210 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2211 break;
044cc6c8 2212 case PCI_DEVICE_ID_QLOGIC_ISP5432:
2213 ha->device_type |= DT_ISP5432;
e428924c 2214 ha->device_type |= DT_FWI2;
441d1072 2215 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2216 break;
c3a2f0df
AV		 2217 case PCI_DEVICE_ID_QLOGIC_ISP2532:
2218 ha->device_type |= DT_ISP2532;
2219 ha->device_type |= DT_ZIO_SUPPORTED;
2220 ha->device_type |= DT_FWI2;
2221 ha->device_type |= DT_IIDMA;
441d1072 2222 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2223 break;
3a03eb79
AV		 2224 case PCI_DEVICE_ID_QLOGIC_ISP8001:
2225 ha->device_type |= DT_ISP8001;
2226 ha->device_type |= DT_ZIO_SUPPORTED;
2227 ha->device_type |= DT_FWI2;
2228 ha->device_type |= DT_IIDMA;
2229 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2230 break;
a9083016
GM		 2231 case PCI_DEVICE_ID_QLOGIC_ISP8021:
2232 ha->device_type |= DT_ISP8021;
2233 ha->device_type |= DT_ZIO_SUPPORTED;
2234 ha->device_type |= DT_FWI2;
2235 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2236 /* Initialize 82XX ISP flags */
2237 qla82xx_init_flags(ha);
2238 break;
7ec0effd
AD		 2239 case PCI_DEVICE_ID_QLOGIC_ISP8044:
2240 ha->device_type |= DT_ISP8044;
2241 ha->device_type |= DT_ZIO_SUPPORTED;
2242 ha->device_type |= DT_FWI2;
2243 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2244 /* Initialize 82XX ISP flags */
2245 qla82xx_init_flags(ha);
2246 break;
6246b8a1
GM		 2247 case PCI_DEVICE_ID_QLOGIC_ISP2031:
2248 ha->device_type |= DT_ISP2031;
2249 ha->device_type |= DT_ZIO_SUPPORTED;
2250 ha->device_type |= DT_FWI2;
2251 ha->device_type |= DT_IIDMA;
2252 ha->device_type |= DT_T10_PI;
2253 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2254 break;
2255 case PCI_DEVICE_ID_QLOGIC_ISP8031:
2256 ha->device_type |= DT_ISP8031;
2257 ha->device_type |= DT_ZIO_SUPPORTED;
2258 ha->device_type |= DT_FWI2;
2259 ha->device_type |= DT_IIDMA;
2260 ha->device_type |= DT_T10_PI;
2261 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2262 break;
8ae6d9c7
GM		 2263 case PCI_DEVICE_ID_QLOGIC_ISPF001:
2264 ha->device_type |= DT_ISPFX00;
2265 break;
f73cb695
CD		 2266 case PCI_DEVICE_ID_QLOGIC_ISP2071:
2267 ha->device_type |= DT_ISP2071;
2268 ha->device_type |= DT_ZIO_SUPPORTED;
2269 ha->device_type |= DT_FWI2;
2270 ha->device_type |= DT_IIDMA;
2271 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2272 break;
2c5bbbb2
JC		 2273 case PCI_DEVICE_ID_QLOGIC_ISP2271:
2274 ha->device_type |= DT_ISP2271;
2275 ha->device_type |= DT_ZIO_SUPPORTED;
2276 ha->device_type |= DT_FWI2;
2277 ha->device_type |= DT_IIDMA;
2278 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2279 break;
ea5b6382 2280 }
e5b68a61 2281
a9083016 2282 if (IS_QLA82XX(ha))
43a9c38b 2283 ha->port_no = ha->portnum & 1;
f73cb695 2284 else {
a9083016
GM		 2285 /* Get adapter physical port no from interrupt pin register. */
2286 pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no);
f73cb695
CD		 2287 if (IS_QLA27XX(ha))
2288 ha->port_no--;
2289 else
2290 ha->port_no = !(ha->port_no & 1);
2291 }
a9083016 2292
7c3df132 2293 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b,
d8424f68 2294 "device_type=0x%x port=%d fw_srisc_address=0x%x.\n",
f73cb695 2295 ha->device_type, ha->port_no, ha->fw_srisc_address);
ea5b6382 2296}
2297
1e99e33a
AV		 2298static void
2299qla2xxx_scan_start(struct Scsi_Host *shost)
2300{
e315cd28 2301 scsi_qla_host_t *vha = shost_priv(shost);
1e99e33a 2302
cbc8eb67
AV		 2303 if (vha->hw->flags.running_gold_fw)
2304 return;
2305
e315cd28
AC		 2306 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
2307 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
2308 set_bit(RSCN_UPDATE, &vha->dpc_flags);
2309 set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags);
1e99e33a
AV		 2310}
2311
2312static int
2313qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time)
2314{
e315cd28 2315 scsi_qla_host_t *vha = shost_priv(shost);
1e99e33a 2316
e315cd28 2317 if (!vha->host)
1e99e33a 2318 return 1;
e315cd28 2319 if (time > vha->hw->loop_reset_delay * HZ)
1e99e33a
AV		 2320 return 1;
2321
e315cd28 2322 return atomic_read(&vha->loop_state) == LOOP_READY;
1e99e33a
AV		 2323}
2324
1da177e4
LT		 2325/*
2326 * PCI driver interface
2327 */
6f039790 2328static int
7ee61397 2329qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
1da177e4 2330{
a1541d5a 2331 int ret = -ENODEV;
1da177e4 2332 struct Scsi_Host *host;
e315cd28
AC		 2333 scsi_qla_host_t *base_vha = NULL;
2334 struct qla_hw_data *ha;
29856e28 2335 char pci_info[30];
7d613ac6 2336 char fw_str[30], wq_name[30];
5433383e 2337 struct scsi_host_template *sht;
642ef983 2338 int bars, mem_only = 0;
e315cd28 2339 uint16_t req_length = 0, rsp_length = 0;
73208dfd
AC		 2340 struct req_que *req = NULL;
2341 struct rsp_que *rsp = NULL;
285d0321 2342 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO);
a5326f86 2343 sht = &qla2xxx_driver_template;
5433383e 2344 if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 ||
8bc69e7d 2345 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 ||
4d4df193 2346 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 ||
8bc69e7d 2347 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 ||
c3a2f0df 2348 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 ||
3a03eb79 2349 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 ||
a9083016 2350 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 ||
6246b8a1
GM		 2351 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021 ||
2352 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2031 ||
8ae6d9c7 2353 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8031 ||
7ec0effd 2354 pdev->device == PCI_DEVICE_ID_QLOGIC_ISPF001 ||
f73cb695 2355 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8044 ||
2c5bbbb2
JC		 2356 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2071 ||
2357 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2271) {
285d0321 2358 bars = pci_select_bars(pdev, IORESOURCE_MEM);
09483916 2359 mem_only = 1;
7c3df132
SK		 2360 ql_dbg_pci(ql_dbg_init, pdev, 0x0007,
2361 "Mem only adapter.\n");
285d0321 2362 }
7c3df132
SK		 2363 ql_dbg_pci(ql_dbg_init, pdev, 0x0008,
2364 "Bars=%d.\n", bars);
285d0321 2365
09483916
BH		 2366 if (mem_only) {
2367 if (pci_enable_device_mem(pdev))
2368 goto probe_out;
2369 } else {
2370 if (pci_enable_device(pdev))
2371 goto probe_out;
2372 }
285d0321 2373
0927678f
JB		 2374 /* This may fail but that's ok */
2375 pci_enable_pcie_error_reporting(pdev);
285d0321 2376
e315cd28
AC		 2377 ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL);
2378 if (!ha) {
7c3df132
SK		 2379 ql_log_pci(ql_log_fatal, pdev, 0x0009,
2380 "Unable to allocate memory for ha.\n");
e315cd28 2381 goto probe_out;
1da177e4 2382 }
7c3df132
SK		 2383 ql_dbg_pci(ql_dbg_init, pdev, 0x000a,
2384 "Memory allocated for ha=%p.\n", ha);
e315cd28 2385 ha->pdev = pdev;
2d70c103 2386 ha->tgt.enable_class_2 = ql2xenableclass2;
1da177e4
LT		 2387
2388 /* Clear our data area */
285d0321 2389 ha->bars = bars;
09483916 2390 ha->mem_only = mem_only;
df4bf0bb 2391 spin_lock_init(&ha->hardware_lock);
339aa70e 2392 spin_lock_init(&ha->vport_slock);
a9b6f722 2393 mutex_init(&ha->selflogin_lock);
7a8ab9c8 2394 mutex_init(&ha->optrom_mutex);
1da177e4 2395
ea5b6382 2396 /* Set ISP-type information. */
2397 qla2x00_set_isp_flags(ha);
ca79cf66
DG		 2398
2399 /* Set EEH reset type to fundamental if required by hba */
95676112 2400 if (IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha) ||
f73cb695 2401 IS_QLA83XX(ha) || IS_QLA27XX(ha))
ca79cf66 2402 pdev->needs_freset = 1;
ca79cf66 2403
cba1e47f
CD		 2404 ha->prev_topology = 0;
2405 ha->init_cb_size = sizeof(init_cb_t);
2406 ha->link_data_rate = PORT_SPEED_UNKNOWN;
2407 ha->optrom_size = OPTROM_SIZE_2300;
2408
abbd8870 2409 /* Assign ISP specific operations. */
1da177e4 2410 if (IS_QLA2100(ha)) {
642ef983 2411 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
1da177e4 2412 ha->mbx_count = MAILBOX_REGISTER_COUNT_2100;
e315cd28
AC		 2413 req_length = REQUEST_ENTRY_CNT_2100;
2414 rsp_length = RESPONSE_ENTRY_CNT_2100;
2415 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
abbd8870 2416 ha->gid_list_info_size = 4;
3a03eb79
AV		 2417 ha->flash_conf_off = ~0;
2418 ha->flash_data_off = ~0;
2419 ha->nvram_conf_off = ~0;
2420 ha->nvram_data_off = ~0;
fd34f556 2421 ha->isp_ops = &qla2100_isp_ops;
1da177e4 2422 } else if (IS_QLA2200(ha)) {
642ef983 2423 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
67ddda35 2424 ha->mbx_count = MAILBOX_REGISTER_COUNT_2200;
e315cd28
AC		 2425 req_length = REQUEST_ENTRY_CNT_2200;
2426 rsp_length = RESPONSE_ENTRY_CNT_2100;
2427 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
abbd8870 2428 ha->gid_list_info_size = 4;
3a03eb79
AV		 2429 ha->flash_conf_off = ~0;
2430 ha->flash_data_off = ~0;
2431 ha->nvram_conf_off = ~0;
2432 ha->nvram_data_off = ~0;
fd34f556 2433 ha->isp_ops = &qla2100_isp_ops;
fca29703 2434 } else if (IS_QLA23XX(ha)) {
642ef983 2435 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
1da177e4 2436 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2437 req_length = REQUEST_ENTRY_CNT_2200;
2438 rsp_length = RESPONSE_ENTRY_CNT_2300;
2439 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
abbd8870 2440 ha->gid_list_info_size = 6;
854165f4 2441 if (IS_QLA2322(ha) || IS_QLA6322(ha))
2442 ha->optrom_size = OPTROM_SIZE_2322;
3a03eb79
AV		 2443 ha->flash_conf_off = ~0;
2444 ha->flash_data_off = ~0;
2445 ha->nvram_conf_off = ~0;
2446 ha->nvram_data_off = ~0;
fd34f556 2447 ha->isp_ops = &qla2300_isp_ops;
4d4df193 2448 } else if (IS_QLA24XX_TYPE(ha)) {
642ef983 2449 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
fca29703 2450 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2451 req_length = REQUEST_ENTRY_CNT_24XX;
2452 rsp_length = RESPONSE_ENTRY_CNT_2300;
2d70c103 2453 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
e315cd28 2454 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2c3dfe3f 2455 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
fca29703 2456 ha->gid_list_info_size = 8;
854165f4 2457 ha->optrom_size = OPTROM_SIZE_24XX;
73208dfd 2458 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX;
fd34f556 2459 ha->isp_ops = &qla24xx_isp_ops;
3a03eb79
AV		 2460 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2461 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2462 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2463 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
c3a2f0df 2464 } else if (IS_QLA25XX(ha)) {
642ef983 2465 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
c3a2f0df 2466 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2467 req_length = REQUEST_ENTRY_CNT_24XX;
2468 rsp_length = RESPONSE_ENTRY_CNT_2300;
2d70c103 2469 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
e315cd28 2470 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
c3a2f0df 2471 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
c3a2f0df
AV		 2472 ha->gid_list_info_size = 8;
2473 ha->optrom_size = OPTROM_SIZE_25XX;
73208dfd 2474 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
c3a2f0df 2475 ha->isp_ops = &qla25xx_isp_ops;
3a03eb79
AV		 2476 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2477 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2478 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2479 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
2480 } else if (IS_QLA81XX(ha)) {
642ef983 2481 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3a03eb79
AV		 2482 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2483 req_length = REQUEST_ENTRY_CNT_24XX;
2484 rsp_length = RESPONSE_ENTRY_CNT_2300;
aa230bc5 2485 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
3a03eb79
AV		 2486 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2487 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2488 ha->gid_list_info_size = 8;
2489 ha->optrom_size = OPTROM_SIZE_81XX;
40859ae5 2490 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3a03eb79
AV		 2491 ha->isp_ops = &qla81xx_isp_ops;
2492 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2493 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2494 ha->nvram_conf_off = ~0;
2495 ha->nvram_data_off = ~0;
a9083016 2496 } else if (IS_QLA82XX(ha)) {
642ef983 2497 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
a9083016
GM		 2498 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2499 req_length = REQUEST_ENTRY_CNT_82XX;
2500 rsp_length = RESPONSE_ENTRY_CNT_82XX;
2501 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2502 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2503 ha->gid_list_info_size = 8;
2504 ha->optrom_size = OPTROM_SIZE_82XX;
087c621e 2505 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
a9083016
GM		 2506 ha->isp_ops = &qla82xx_isp_ops;
2507 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2508 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2509 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2510 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
7ec0effd
AD		 2511 } else if (IS_QLA8044(ha)) {
2512 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2513 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2514 req_length = REQUEST_ENTRY_CNT_82XX;
2515 rsp_length = RESPONSE_ENTRY_CNT_82XX;
2516 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2517 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2518 ha->gid_list_info_size = 8;
2519 ha->optrom_size = OPTROM_SIZE_83XX;
2520 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2521 ha->isp_ops = &qla8044_isp_ops;
2522 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2523 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2524 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2525 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
6246b8a1 2526 } else if (IS_QLA83XX(ha)) {
7d613ac6 2527 ha->portnum = PCI_FUNC(ha->pdev->devfn);
642ef983 2528 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
6246b8a1
GM		 2529 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2530 req_length = REQUEST_ENTRY_CNT_24XX;
2531 rsp_length = RESPONSE_ENTRY_CNT_2300;
b8aa4bdf 2532 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
6246b8a1
GM		 2533 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2534 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2535 ha->gid_list_info_size = 8;
2536 ha->optrom_size = OPTROM_SIZE_83XX;
2537 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2538 ha->isp_ops = &qla83xx_isp_ops;
2539 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2540 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2541 ha->nvram_conf_off = ~0;
2542 ha->nvram_data_off = ~0;
8ae6d9c7
GM		 2543 } else if (IS_QLAFX00(ha)) {
2544 ha->max_fibre_devices = MAX_FIBRE_DEVICES_FX00;
2545 ha->mbx_count = MAILBOX_REGISTER_COUNT_FX00;
2546 ha->aen_mbx_count = AEN_MAILBOX_REGISTER_COUNT_FX00;
2547 req_length = REQUEST_ENTRY_CNT_FX00;
2548 rsp_length = RESPONSE_ENTRY_CNT_FX00;
8ae6d9c7
GM		 2549 ha->isp_ops = &qlafx00_isp_ops;
2550 ha->port_down_retry_count = 30; /* default value */
2551 ha->mr.fw_hbt_cnt = QLAFX00_HEARTBEAT_INTERVAL;
2552 ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL;
71e56003 2553 ha->mr.fw_critemp_timer_tick = QLAFX00_CRITEMP_INTERVAL;
8ae6d9c7 2554 ha->mr.fw_hbt_en = 1;
e8f5e95d
AB		 2555 ha->mr.host_info_resend = false;
2556 ha->mr.hinfo_resend_timer_tick = QLAFX00_HINFO_RESEND_INTERVAL;
f73cb695
CD		 2557 } else if (IS_QLA27XX(ha)) {
2558 ha->portnum = PCI_FUNC(ha->pdev->devfn);
2559 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2560 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2561 req_length = REQUEST_ENTRY_CNT_24XX;
2562 rsp_length = RESPONSE_ENTRY_CNT_2300;
2563 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2564 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2565 ha->gid_list_info_size = 8;
2566 ha->optrom_size = OPTROM_SIZE_83XX;
2567 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2568 ha->isp_ops = &qla27xx_isp_ops;
2569 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2570 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2571 ha->nvram_conf_off = ~0;
2572 ha->nvram_data_off = ~0;
1da177e4 2573 }
6246b8a1 2574
7c3df132
SK		 2575 ql_dbg_pci(ql_dbg_init, pdev, 0x001e,
2576 "mbx_count=%d, req_length=%d, "
2577 "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, "
642ef983
CD		 2578 "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, "
2579 "max_fibre_devices=%d.\n",
7c3df132
SK		 2580 ha->mbx_count, req_length, rsp_length, ha->max_loop_id,
2581 ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size,
642ef983 2582 ha->nvram_npiv_size, ha->max_fibre_devices);
7c3df132
SK		 2583 ql_dbg_pci(ql_dbg_init, pdev, 0x001f,
2584 "isp_ops=%p, flash_conf_off=%d, "
2585 "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n",
2586 ha->isp_ops, ha->flash_conf_off, ha->flash_data_off,
2587 ha->nvram_conf_off, ha->nvram_data_off);
706f457d
GM		 2588
2589 /* Configure PCI I/O space */
2590 ret = ha->isp_ops->iospace_config(ha);
2591 if (ret)
0a63ad12 2592 goto iospace_config_failed;
706f457d
GM		 2593
2594 ql_log_pci(ql_log_info, pdev, 0x001d,
2595 "Found an ISP%04X irq %d iobase 0x%p.\n",
2596 pdev->device, pdev->irq, ha->iobase);
6c2f527c 2597 mutex_init(&ha->vport_lock);
0b05a1f0
MB		 2598 init_completion(&ha->mbx_cmd_comp);
2599 complete(&ha->mbx_cmd_comp);
2600 init_completion(&ha->mbx_intr_comp);
23f2ebd1 2601 init_completion(&ha->dcbx_comp);
f356bef1 2602 init_completion(&ha->lb_portup_comp);
1da177e4 2603
2c3dfe3f 2604 set_bit(0, (unsigned long *) ha->vp_idx_map);
1da177e4 2605
53303c42 2606 qla2x00_config_dma_addressing(ha);
7c3df132
SK		 2607 ql_dbg_pci(ql_dbg_init, pdev, 0x0020,
2608 "64 Bit addressing is %s.\n",
2609 ha->flags.enable_64bit_addressing ? "enable" :
2610 "disable");
73208dfd 2611 ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp);
b2a72ec3 2612 if (ret) {
7c3df132
SK		 2613 ql_log_pci(ql_log_fatal, pdev, 0x0031,
2614 "Failed to allocate memory for adapter, aborting.\n");
1da177e4 2615
e315cd28
AC		 2616 goto probe_hw_failed;
2617 }
2618
73208dfd 2619 req->max_q_depth = MAX_Q_DEPTH;
e315cd28 2620 if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU)
73208dfd
AC		 2621 req->max_q_depth = ql2xmaxqdepth;
2622
e315cd28
AC		 2623
2624 base_vha = qla2x00_create_host(sht, ha);
2625 if (!base_vha) {
a1541d5a 2626 ret = -ENOMEM;
6e9f21f3 2627 qla2x00_mem_free(ha);
2afa19a9
AC		 2628 qla2x00_free_req_que(ha, req);
2629 qla2x00_free_rsp_que(ha, rsp);
e315cd28 2630 goto probe_hw_failed;
1da177e4
LT		 2631 }
2632
e315cd28 2633 pci_set_drvdata(pdev, base_vha);
6b383979 2634 set_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags);
e315cd28 2635
e315cd28 2636 host = base_vha->host;
2afa19a9 2637 base_vha->req = req;
73208dfd 2638 if (IS_QLA2XXX_MIDTYPE(ha))
e315cd28 2639 base_vha->mgmt_svr_loop_id = 10 + base_vha->vp_idx;
73208dfd 2640 else
e315cd28
AC		 2641 base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER +
2642 base_vha->vp_idx;
58548cb5 2643
8ae6d9c7
GM		 2644 /* Setup fcport template structure. */
2645 ha->mr.fcport.vha = base_vha;
2646 ha->mr.fcport.port_type = FCT_UNKNOWN;
2647 ha->mr.fcport.loop_id = FC_NO_LOOP_ID;
2648 qla2x00_set_fcport_state(&ha->mr.fcport, FCS_UNCONFIGURED);
2649 ha->mr.fcport.supported_classes = FC_COS_UNSPECIFIED;
2650 ha->mr.fcport.scan_state = 1;
2651
58548cb5
GM		 2652 /* Set the SG table size based on ISP type */
2653 if (!IS_FWI2_CAPABLE(ha)) {
2654 if (IS_QLA2100(ha))
2655 host->sg_tablesize = 32;
2656 } else {
2657 if (!IS_QLA82XX(ha))
2658 host->sg_tablesize = QLA_SG_ALL;
2659 }
642ef983 2660 host->max_id = ha->max_fibre_devices;
e315cd28
AC		 2661 host->cmd_per_lun = 3;
2662 host->unique_id = host->host_no;
e02587d7 2663 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif)
0c470874
AE		 2664 host->max_cmd_len = 32;
2665 else
2666 host->max_cmd_len = MAX_CMDSZ;
e315cd28 2667 host->max_channel = MAX_BUSES - 1;
755f516b
HR		 2668 /* Older HBAs support only 16-bit LUNs */
2669 if (!IS_QLAFX00(ha) && !IS_FWI2_CAPABLE(ha) &&
2670 ql2xmaxlun > 0xffff)
2671 host->max_lun = 0xffff;
2672 else
2673 host->max_lun = ql2xmaxlun;
e315cd28 2674 host->transportt = qla2xxx_transport_template;
9a069e19 2675 sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC);
e315cd28 2676
7c3df132
SK		 2677 ql_dbg(ql_dbg_init, base_vha, 0x0033,
2678 "max_id=%d this_id=%d "
2679 "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d "
1abf635d 2680 "max_lun=%llu transportt=%p, vendor_id=%llu.\n", host->max_id,
7c3df132
SK		 2681 host->this_id, host->cmd_per_lun, host->unique_id,
2682 host->max_cmd_len, host->max_channel, host->max_lun,
2683 host->transportt, sht->vendor_id);
2684
9a347ff4
CD		 2685que_init:
2686 /* Alloc arrays of request and response ring ptrs */
2687 if (!qla2x00_alloc_queues(ha, req, rsp)) {
2688 ql_log(ql_log_fatal, base_vha, 0x003d,
2689 "Failed to allocate memory for queue pointers..."
2690 "aborting.\n");
2691 goto probe_init_failed;
2692 }
2693
2d70c103 2694 qlt_probe_one_stage1(base_vha, ha);
9a347ff4 2695
73208dfd
AC		 2696 /* Set up the irqs */
2697 ret = qla2x00_request_irqs(ha, rsp);
2698 if (ret)
6e9f21f3 2699 goto probe_init_failed;
90a86fc0
JC		 2700
2701 pci_save_state(pdev);
2702
9a347ff4 2703 /* Assign back pointers */
2afa19a9
AC		 2704 rsp->req = req;
2705 req->rsp = rsp;
9a347ff4 2706
8ae6d9c7
GM		 2707 if (IS_QLAFX00(ha)) {
2708 ha->rsp_q_map[0] = rsp;
2709 ha->req_q_map[0] = req;
2710 set_bit(0, ha->req_qid_map);
2711 set_bit(0, ha->rsp_qid_map);
2712 }
2713
08029990
AV		 2714 /* FWI2-capable only. */
2715 req->req_q_in = &ha->iobase->isp24.req_q_in;
2716 req->req_q_out = &ha->iobase->isp24.req_q_out;
2717 rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in;
2718 rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out;
f73cb695 2719 if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
08029990
AV		 2720 req->req_q_in = &ha->mqiobase->isp25mq.req_q_in;
2721 req->req_q_out = &ha->mqiobase->isp25mq.req_q_out;
2722 rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in;
2723 rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out;
17d98630
AC		 2724 }
2725
8ae6d9c7
GM		 2726 if (IS_QLAFX00(ha)) {
2727 req->req_q_in = &ha->iobase->ispfx00.req_q_in;
2728 req->req_q_out = &ha->iobase->ispfx00.req_q_out;
2729 rsp->rsp_q_in = &ha->iobase->ispfx00.rsp_q_in;
2730 rsp->rsp_q_out = &ha->iobase->ispfx00.rsp_q_out;
2731 }
2732
7ec0effd 2733 if (IS_P3P_TYPE(ha)) {
a9083016
GM		 2734 req->req_q_out = &ha->iobase->isp82.req_q_out[0];
2735 rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0];
2736 rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0];
2737 }
2738
7c3df132
SK		 2739 ql_dbg(ql_dbg_multiq, base_vha, 0xc009,
2740 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
2741 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
2742 ql_dbg(ql_dbg_multiq, base_vha, 0xc00a,
2743 "req->req_q_in=%p req->req_q_out=%p "
2744 "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
2745 req->req_q_in, req->req_q_out,
2746 rsp->rsp_q_in, rsp->rsp_q_out);
2747 ql_dbg(ql_dbg_init, base_vha, 0x003e,
2748 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
2749 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
2750 ql_dbg(ql_dbg_init, base_vha, 0x003f,
2751 "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
2752 req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out);
1da177e4 2753
8ae6d9c7 2754 if (ha->isp_ops->initialize_adapter(base_vha)) {
7c3df132
SK		 2755 ql_log(ql_log_fatal, base_vha, 0x00d6,
2756 "Failed to initialize adapter - Adapter flags %x.\n",
2757 base_vha->device_flags);
1da177e4 2758
a9083016
GM		 2759 if (IS_QLA82XX(ha)) {
2760 qla82xx_idc_lock(ha);
2761 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 2762 QLA8XXX_DEV_FAILED);
a9083016 2763 qla82xx_idc_unlock(ha);
7c3df132
SK		 2764 ql_log(ql_log_fatal, base_vha, 0x00d7,
2765 "HW State: FAILED.\n");
7ec0effd
AD		 2766 } else if (IS_QLA8044(ha)) {
2767 qla8044_idc_lock(ha);
2768 qla8044_wr_direct(base_vha,
2769 QLA8044_CRB_DEV_STATE_INDEX,
2770 QLA8XXX_DEV_FAILED);
2771 qla8044_idc_unlock(ha);
2772 ql_log(ql_log_fatal, base_vha, 0x0150,
2773 "HW State: FAILED.\n");
a9083016
GM		 2774 }
2775
a1541d5a 2776 ret = -ENODEV;
1da177e4
LT		 2777 goto probe_failed;
2778 }
2779
3b1bef64
CD		 2780 if (IS_QLAFX00(ha))
2781 host->can_queue = QLAFX00_MAX_CANQUEUE;
2782 else
2783 host->can_queue = req->num_outstanding_cmds - 10;
2784
2785 ql_dbg(ql_dbg_init, base_vha, 0x0032,
2786 "can_queue=%d, req=%p, mgmt_svr_loop_id=%d, sg_tablesize=%d.\n",
2787 host->can_queue, base_vha->req,
2788 base_vha->mgmt_svr_loop_id, host->sg_tablesize);
2789
7163ea81
AC		 2790 if (ha->mqenable) {
2791 if (qla25xx_setup_mode(base_vha)) {
7c3df132
SK		 2792 ql_log(ql_log_warn, base_vha, 0x00ec,
2793 "Failed to create queues, falling back to single queue mode.\n");
7163ea81
AC		 2794 goto que_init;
2795 }
2796 }
68ca949c 2797
cbc8eb67
AV		 2798 if (ha->flags.running_gold_fw)
2799 goto skip_dpc;
2800
1da177e4
LT		 2801 /*
2802 * Startup the kernel thread for this host adapter
2803 */
39a11240 2804 ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha,
7c3df132 2805 "%s_dpc", base_vha->host_str);
39a11240 2806 if (IS_ERR(ha->dpc_thread)) {
7c3df132
SK		 2807 ql_log(ql_log_fatal, base_vha, 0x00ed,
2808 "Failed to start DPC thread.\n");
39a11240 2809 ret = PTR_ERR(ha->dpc_thread);
1da177e4
LT		 2810 goto probe_failed;
2811 }
7c3df132
SK		 2812 ql_dbg(ql_dbg_init, base_vha, 0x00ee,
2813 "DPC thread started successfully.\n");
1da177e4 2814
2d70c103
NB		 2815 /*
2816 * If we're not coming up in initiator mode, we might sit for
2817 * a while without waking up the dpc thread, which leads to a
2818 * stuck process warning. So just kick the dpc once here and
2819 * let the kthread start (and go back to sleep in qla2x00_do_dpc).
2820 */
2821 qla2xxx_wake_dpc(base_vha);
2822
f3ddac19
CD		 2823 INIT_WORK(&ha->board_disable, qla2x00_disable_board_on_pci_error);
2824
81178772
SK		 2825 if (IS_QLA8031(ha) || IS_MCTP_CAPABLE(ha)) {
2826 sprintf(wq_name, "qla2xxx_%lu_dpc_lp_wq", base_vha->host_no);
2827 ha->dpc_lp_wq = create_singlethread_workqueue(wq_name);
2828 INIT_WORK(&ha->idc_aen, qla83xx_service_idc_aen);
2829
2830 sprintf(wq_name, "qla2xxx_%lu_dpc_hp_wq", base_vha->host_no);
2831 ha->dpc_hp_wq = create_singlethread_workqueue(wq_name);
2832 INIT_WORK(&ha->nic_core_reset, qla83xx_nic_core_reset_work);
2833 INIT_WORK(&ha->idc_state_handler,
2834 qla83xx_idc_state_handler_work);
2835 INIT_WORK(&ha->nic_core_unrecoverable,
2836 qla83xx_nic_core_unrecoverable_work);
2837 }
2838
cbc8eb67 2839skip_dpc:
e315cd28
AC		 2840 list_add_tail(&base_vha->list, &ha->vp_list);
2841 base_vha->host->irq = ha->pdev->irq;
1da177e4
LT		 2842
2843 /* Initialized the timer */
e315cd28 2844 qla2x00_start_timer(base_vha, qla2x00_timer, WATCH_INTERVAL);
7c3df132
SK		 2845 ql_dbg(ql_dbg_init, base_vha, 0x00ef,
2846 "Started qla2x00_timer with "
2847 "interval=%d.\n", WATCH_INTERVAL);
2848 ql_dbg(ql_dbg_init, base_vha, 0x00f0,
2849 "Detected hba at address=%p.\n",
2850 ha);
d19044c3 2851
e02587d7 2852 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) {
bad75002 2853 if (ha->fw_attributes & BIT_4) {
9e522cd8 2854 int prot = 0, guard;
bad75002 2855 base_vha->flags.difdix_supported = 1;
7c3df132
SK		 2856 ql_dbg(ql_dbg_init, base_vha, 0x00f1,
2857 "Registering for DIF/DIX type 1 and 3 protection.\n");
8cb2049c
AE		 2858 if (ql2xenabledif == 1)
2859 prot = SHOST_DIX_TYPE0_PROTECTION;
bad75002 2860 scsi_host_set_prot(host,
8cb2049c 2861 prot | SHOST_DIF_TYPE1_PROTECTION
0c470874 2862 | SHOST_DIF_TYPE2_PROTECTION
bad75002
AE		 2863 | SHOST_DIF_TYPE3_PROTECTION
2864 | SHOST_DIX_TYPE1_PROTECTION
0c470874 2865 | SHOST_DIX_TYPE2_PROTECTION
bad75002 2866 | SHOST_DIX_TYPE3_PROTECTION);
9e522cd8
AE		 2867
2868 guard = SHOST_DIX_GUARD_CRC;
2869
2870 if (IS_PI_IPGUARD_CAPABLE(ha) &&
2871 (ql2xenabledif > 1 || IS_PI_DIFB_DIX0_CAPABLE(ha)))
2872 guard |= SHOST_DIX_GUARD_IP;
2873
2874 scsi_host_set_guard(host, guard);
bad75002
AE		 2875 } else
2876 base_vha->flags.difdix_supported = 0;
2877 }
2878
a9083016
GM		 2879 ha->isp_ops->enable_intrs(ha);
2880
1fe19ee4
AB		 2881 if (IS_QLAFX00(ha)) {
2882 ret = qlafx00_fx_disc(base_vha,
2883 &base_vha->hw->mr.fcport, FXDISC_GET_CONFIG_INFO);
2884 host->sg_tablesize = (ha->mr.extended_io_enabled) ?
2885 QLA_SG_ALL : 128;
2886 }
2887
a1541d5a
AV		 2888 ret = scsi_add_host(host, &pdev->dev);
2889 if (ret)
2890 goto probe_failed;
2891
1486400f
MR		 2892 base_vha->flags.init_done = 1;
2893 base_vha->flags.online = 1;
edaa5c74 2894 ha->prev_minidump_failed = 0;
1486400f 2895
7c3df132
SK		 2896 ql_dbg(ql_dbg_init, base_vha, 0x00f2,
2897 "Init done and hba is online.\n");
2898
2d70c103
NB		 2899 if (qla_ini_mode_enabled(base_vha))
2900 scsi_scan_host(host);
2901 else
2902 ql_dbg(ql_dbg_init, base_vha, 0x0122,
2903 "skipping scsi_scan_host() for non-initiator port\n");
1e99e33a 2904
e315cd28 2905 qla2x00_alloc_sysfs_attr(base_vha);
a1541d5a 2906
8ae6d9c7 2907 if (IS_QLAFX00(ha)) {
8ae6d9c7
GM		 2908 ret = qlafx00_fx_disc(base_vha,
2909 &base_vha->hw->mr.fcport, FXDISC_GET_PORT_INFO);
2910
2911 /* Register system information */
2912 ret = qlafx00_fx_disc(base_vha,
2913 &base_vha->hw->mr.fcport, FXDISC_REG_HOST_INFO);
2914 }
2915
e315cd28 2916 qla2x00_init_host_attr(base_vha);
a1541d5a 2917
e315cd28 2918 qla2x00_dfs_setup(base_vha);
df613b96 2919
03eb912a
AB		 2920 ql_log(ql_log_info, base_vha, 0x00fb,
2921 "QLogic %s - %s.\n", ha->model_number, ha->model_desc);
7c3df132
SK		 2922 ql_log(ql_log_info, base_vha, 0x00fc,
2923 "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n",
2924 pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info),
2925 pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-',
2926 base_vha->host_no,
df57caba 2927 ha->isp_ops->fw_version_str(base_vha, fw_str, sizeof(fw_str)));
1da177e4 2928
2d70c103
NB		 2929 qlt_add_target(ha, base_vha);
2930
6b383979 2931 clear_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags);
1da177e4
LT		 2932 return 0;
2933
6e9f21f3 2934probe_init_failed:
2afa19a9 2935 qla2x00_free_req_que(ha, req);
9a347ff4
CD		 2936 ha->req_q_map[0] = NULL;
2937 clear_bit(0, ha->req_qid_map);
2afa19a9 2938 qla2x00_free_rsp_que(ha, rsp);
9a347ff4
CD		 2939 ha->rsp_q_map[0] = NULL;
2940 clear_bit(0, ha->rsp_qid_map);
2afa19a9 2941 ha->max_req_queues = ha->max_rsp_queues = 0;
6e9f21f3 2942
1da177e4 2943probe_failed:
b9978769
AV		 2944 if (base_vha->timer_active)
2945 qla2x00_stop_timer(base_vha);
2946 base_vha->flags.online = 0;
2947 if (ha->dpc_thread) {
2948 struct task_struct *t = ha->dpc_thread;
2949
2950 ha->dpc_thread = NULL;
2951 kthread_stop(t);
2952 }
2953
e315cd28 2954 qla2x00_free_device(base_vha);
1da177e4 2955
e315cd28 2956 scsi_host_put(base_vha->host);
1da177e4 2957
e315cd28 2958probe_hw_failed:
1a2fbf18
JL		 2959 qla2x00_clear_drv_active(ha);
2960
0a63ad12 2961iospace_config_failed:
7ec0effd 2962 if (IS_P3P_TYPE(ha)) {
0a63ad12 2963 if (!ha->nx_pcibase)
f73cb695 2964 iounmap((device_reg_t *)ha->nx_pcibase);
a9083016 2965 if (!ql2xdbwr)
f73cb695 2966 iounmap((device_reg_t *)ha->nxdb_wr_ptr);
a9083016
GM		 2967 } else {
2968 if (ha->iobase)
2969 iounmap(ha->iobase);
8ae6d9c7
GM		 2970 if (ha->cregbase)
2971 iounmap(ha->cregbase);
a9083016 2972 }
e315cd28
AC		 2973 pci_release_selected_regions(ha->pdev, ha->bars);
2974 kfree(ha);
2975 ha = NULL;
1da177e4 2976
a1541d5a 2977probe_out:
e315cd28 2978 pci_disable_device(pdev);
a1541d5a 2979 return ret;
1da177e4 2980}
1da177e4 2981
e30d1756
MI		 2982static void
2983qla2x00_shutdown(struct pci_dev *pdev)
2984{
2985 scsi_qla_host_t *vha;
2986 struct qla_hw_data *ha;
2987
552f3f9a
MI		 2988 if (!atomic_read(&pdev->enable_cnt))
2989 return;
2990
e30d1756
MI		 2991 vha = pci_get_drvdata(pdev);
2992 ha = vha->hw;
2993
42479343
AB		 2994 /* Notify ISPFX00 firmware */
2995 if (IS_QLAFX00(ha))
2996 qlafx00_driver_shutdown(vha, 20);
2997
e30d1756
MI		 2998 /* Turn-off FCE trace */
2999 if (ha->flags.fce_enabled) {
3000 qla2x00_disable_fce_trace(vha, NULL, NULL);
3001 ha->flags.fce_enabled = 0;
3002 }
3003
3004 /* Turn-off EFT trace */
3005 if (ha->eft)
3006 qla2x00_disable_eft_trace(vha);
3007
3008 /* Stop currently executing firmware. */
3009 qla2x00_try_to_stop_firmware(vha);
3010
3011 /* Turn adapter off line */
3012 vha->flags.online = 0;
3013
3014 /* turn-off interrupts on the card */
3015 if (ha->interrupts_on) {
3016 vha->flags.init_done = 0;
3017 ha->isp_ops->disable_intrs(ha);
3018 }
3019
3020 qla2x00_free_irqs(vha);
3021
3022 qla2x00_free_fw_dump(ha);
3023}
3024
fe1b806f 3025/* Deletes all the virtual ports for a given ha */
4c993f76 3026static void
fe1b806f 3027qla2x00_delete_all_vps(struct qla_hw_data *ha, scsi_qla_host_t *base_vha)
1da177e4 3028{
fe1b806f
CD		 3029 struct Scsi_Host *scsi_host;
3030 scsi_qla_host_t *vha;
feafb7b1 3031 unsigned long flags;
e315cd28 3032
43ebf16d
AE		 3033 mutex_lock(&ha->vport_lock);
3034 while (ha->cur_vport_count) {
43ebf16d 3035 spin_lock_irqsave(&ha->vport_slock, flags);
feafb7b1 3036
43ebf16d
AE		 3037 BUG_ON(base_vha->list.next == &ha->vp_list);
3038 /* This assumes first entry in ha->vp_list is always base vha */
3039 vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list);
fe1b806f 3040 scsi_host = scsi_host_get(vha->host);
feafb7b1 3041
43ebf16d
AE		 3042 spin_unlock_irqrestore(&ha->vport_slock, flags);
3043 mutex_unlock(&ha->vport_lock);
3044
3045 fc_vport_terminate(vha->fc_vport);
3046 scsi_host_put(vha->host);
feafb7b1 3047
43ebf16d 3048 mutex_lock(&ha->vport_lock);
e315cd28 3049 }
43ebf16d 3050 mutex_unlock(&ha->vport_lock);
fe1b806f 3051}
1da177e4 3052
fe1b806f
CD		 3053/* Stops all deferred work threads */
3054static void
3055qla2x00_destroy_deferred_work(struct qla_hw_data *ha)
3056{
68ca949c
AC		 3057 /* Flush the work queue and remove it */
3058 if (ha->wq) {
3059 flush_workqueue(ha->wq);
3060 destroy_workqueue(ha->wq);
3061 ha->wq = NULL;
3062 }
3063
7d613ac6
SV		 3064 /* Cancel all work and destroy DPC workqueues */
3065 if (ha->dpc_lp_wq) {
3066 cancel_work_sync(&ha->idc_aen);
3067 destroy_workqueue(ha->dpc_lp_wq);
3068 ha->dpc_lp_wq = NULL;
3069 }
3070
3071 if (ha->dpc_hp_wq) {
3072 cancel_work_sync(&ha->nic_core_reset);
3073 cancel_work_sync(&ha->idc_state_handler);
3074 cancel_work_sync(&ha->nic_core_unrecoverable);
3075 destroy_workqueue(ha->dpc_hp_wq);
3076 ha->dpc_hp_wq = NULL;
3077 }
3078
b9978769
AV		 3079 /* Kill the kernel thread for this host */
3080 if (ha->dpc_thread) {
3081 struct task_struct *t = ha->dpc_thread;
3082
3083 /*
3084 * qla2xxx_wake_dpc checks for ->dpc_thread
3085 * so we need to zero it out.
3086 */
3087 ha->dpc_thread = NULL;
3088 kthread_stop(t);
3089 }
fe1b806f 3090}
1da177e4 3091
fe1b806f
CD		 3092static void
3093qla2x00_unmap_iobases(struct qla_hw_data *ha)
3094{
a9083016 3095 if (IS_QLA82XX(ha)) {
b963752f 3096
f73cb695 3097 iounmap((device_reg_t *)ha->nx_pcibase);
a9083016 3098 if (!ql2xdbwr)
f73cb695 3099 iounmap((device_reg_t *)ha->nxdb_wr_ptr);
a9083016
GM		 3100 } else {
3101 if (ha->iobase)
3102 iounmap(ha->iobase);
1da177e4 3103
8ae6d9c7
GM		 3104 if (ha->cregbase)
3105 iounmap(ha->cregbase);
3106
a9083016
GM		 3107 if (ha->mqiobase)
3108 iounmap(ha->mqiobase);
6246b8a1 3109
f73cb695 3110 if ((IS_QLA83XX(ha) || IS_QLA27XX(ha)) && ha->msixbase)
6246b8a1 3111 iounmap(ha->msixbase);
a9083016 3112 }
fe1b806f
CD		 3113}
3114
3115static void
db7157d4 3116qla2x00_clear_drv_active(struct qla_hw_data *ha)
fe1b806f 3117{
fe1b806f
CD		 3118 if (IS_QLA8044(ha)) {
3119 qla8044_idc_lock(ha);
c41afc9a 3120 qla8044_clear_drv_active(ha);
fe1b806f
CD		 3121 qla8044_idc_unlock(ha);
3122 } else if (IS_QLA82XX(ha)) {
3123 qla82xx_idc_lock(ha);
3124 qla82xx_clear_drv_active(ha);
3125 qla82xx_idc_unlock(ha);
3126 }
3127}
3128
3129static void
3130qla2x00_remove_one(struct pci_dev *pdev)
3131{
3132 scsi_qla_host_t *base_vha;
3133 struct qla_hw_data *ha;
3134
beb9e315
JL		 3135 base_vha = pci_get_drvdata(pdev);
3136 ha = base_vha->hw;
3137
3138 /* Indicate device removal to prevent future board_disable and wait
3139 * until any pending board_disable has completed. */
3140 set_bit(PFLG_DRIVER_REMOVING, &base_vha->pci_flags);
3141 cancel_work_sync(&ha->board_disable);
3142
fe1b806f 3143 /*
beb9e315
JL		 3144 * If the PCI device is disabled then there was a PCI-disconnect and
3145 * qla2x00_disable_board_on_pci_error has taken care of most of the
3146 * resources.
fe1b806f 3147 */
beb9e315
JL		 3148 if (!atomic_read(&pdev->enable_cnt)) {
3149 scsi_host_put(base_vha->host);
3150 kfree(ha);
3151 pci_set_drvdata(pdev, NULL);
fe1b806f 3152 return;
beb9e315 3153 }
fe1b806f 3154
638a1a01
SC		 3155 qla2x00_wait_for_hba_ready(base_vha);
3156
fe1b806f
CD		 3157 set_bit(UNLOADING, &base_vha->dpc_flags);
3158
3159 if (IS_QLAFX00(ha))
3160 qlafx00_driver_shutdown(base_vha, 20);
3161
3162 qla2x00_delete_all_vps(ha, base_vha);
3163
3164 if (IS_QLA8031(ha)) {
3165 ql_dbg(ql_dbg_p3p, base_vha, 0xb07e,
3166 "Clearing fcoe driver presence.\n");
3167 if (qla83xx_clear_drv_presence(base_vha) != QLA_SUCCESS)
3168 ql_dbg(ql_dbg_p3p, base_vha, 0xb079,
3169 "Error while clearing DRV-Presence.\n");
3170 }
3171
3172 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
3173
3174 qla2x00_dfs_remove(base_vha);
3175
3176 qla84xx_put_chip(base_vha);
3177
3178 /* Disable timer */
3179 if (base_vha->timer_active)
3180 qla2x00_stop_timer(base_vha);
3181
3182 base_vha->flags.online = 0;
3183
3184 qla2x00_destroy_deferred_work(ha);
3185
3186 qlt_remove_target(ha, base_vha);
3187
3188 qla2x00_free_sysfs_attr(base_vha, true);
3189
3190 fc_remove_host(base_vha->host);
3191
3192 scsi_remove_host(base_vha->host);
3193
3194 qla2x00_free_device(base_vha);
3195
3196 scsi_host_put(base_vha->host);
3197
db7157d4 3198 qla2x00_clear_drv_active(ha);
fe1b806f
CD		 3199
3200 qla2x00_unmap_iobases(ha);
73208dfd 3201
e315cd28
AC		 3202 pci_release_selected_regions(ha->pdev, ha->bars);
3203 kfree(ha);
3204 ha = NULL;
1da177e4 3205
90a86fc0
JC		 3206 pci_disable_pcie_error_reporting(pdev);
3207
665db93b 3208 pci_disable_device(pdev);
1da177e4 3209}
1da177e4
LT		 3210
3211static void
e315cd28 3212qla2x00_free_device(scsi_qla_host_t *vha)
1da177e4 3213{
e315cd28 3214 struct qla_hw_data *ha = vha->hw;
1da177e4 3215
85880801
AV		 3216 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
3217
3218 /* Disable timer */
3219 if (vha->timer_active)
3220 qla2x00_stop_timer(vha);
3221
2afa19a9 3222 qla25xx_delete_queues(vha);
fe1b806f 3223
df613b96 3224 if (ha->flags.fce_enabled)
e315cd28 3225 qla2x00_disable_fce_trace(vha, NULL, NULL);
df613b96 3226
a7a167bf 3227 if (ha->eft)
e315cd28 3228 qla2x00_disable_eft_trace(vha);
a7a167bf 3229
f6ef3b18 3230 /* Stop currently executing firmware. */
e315cd28 3231 qla2x00_try_to_stop_firmware(vha);
1da177e4 3232
85880801
AV		 3233 vha->flags.online = 0;
3234
f6ef3b18 3235 /* turn-off interrupts on the card */
a9083016
GM		 3236 if (ha->interrupts_on) {
3237 vha->flags.init_done = 0;
fd34f556 3238 ha->isp_ops->disable_intrs(ha);
a9083016 3239 }
f6ef3b18 3240
e315cd28 3241 qla2x00_free_irqs(vha);
1da177e4 3242
8867048b
CD		 3243 qla2x00_free_fcports(vha);
3244
e315cd28 3245 qla2x00_mem_free(ha);
73208dfd 3246
08de2844
GM		 3247 qla82xx_md_free(vha);
3248
73208dfd 3249 qla2x00_free_queues(ha);
1da177e4
LT		 3250}
3251
8867048b
CD		 3252void qla2x00_free_fcports(struct scsi_qla_host *vha)
3253{
3254 fc_port_t *fcport, *tfcport;
3255
3256 list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list) {
3257 list_del(&fcport->list);
5f16b331 3258 qla2x00_clear_loop_id(fcport);
8867048b
CD		 3259 kfree(fcport);
3260 fcport = NULL;
3261 }
3262}
3263
d97994dc 3264static inline void
e315cd28 3265qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport,
d97994dc 3266 int defer)
3267{
d97994dc 3268 struct fc_rport *rport;
67becc00 3269 scsi_qla_host_t *base_vha;
044d78e1 3270 unsigned long flags;
d97994dc 3271
3272 if (!fcport->rport)
3273 return;
3274
3275 rport = fcport->rport;
3276 if (defer) {
67becc00 3277 base_vha = pci_get_drvdata(vha->hw->pdev);
044d78e1 3278 spin_lock_irqsave(vha->host->host_lock, flags);
d97994dc 3279 fcport->drport = rport;
044d78e1 3280 spin_unlock_irqrestore(vha->host->host_lock, flags);
67becc00
AV		 3281 set_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags);
3282 qla2xxx_wake_dpc(base_vha);
2d70c103 3283 } else {
d97994dc 3284 fc_remote_port_delete(rport);
2d70c103
NB		 3285 qlt_fc_port_deleted(vha, fcport);
3286 }
d97994dc 3287}
3288
1da177e4
LT		 3289/*
3290 * qla2x00_mark_device_lost Updates fcport state when device goes offline.
3291 *
3292 * Input: ha = adapter block pointer. fcport = port structure pointer.
3293 *
3294 * Return: None.
3295 *
3296 * Context:
3297 */
e315cd28 3298void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport,
d97994dc 3299 int do_login, int defer)
1da177e4 3300{
8ae6d9c7
GM		 3301 if (IS_QLAFX00(vha->hw)) {
3302 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
3303 qla2x00_schedule_rport_del(vha, fcport, defer);
3304 return;
3305 }
3306
2c3dfe3f 3307 if (atomic_read(&fcport->state) == FCS_ONLINE &&
c6d39e23 3308 vha->vp_idx == fcport->vha->vp_idx) {
ec426e10 3309 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
e315cd28
AC		 3310 qla2x00_schedule_rport_del(vha, fcport, defer);
3311 }
fa2a1ce5 3312 /*
1da177e4
LT		 3313 * We may need to retry the login, so don't change the state of the
3314 * port but do the retries.
3315 */
3316 if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD)
ec426e10 3317 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
1da177e4
LT		 3318
3319 if (!do_login)
3320 return;
3321
3322 if (fcport->login_retry == 0) {
e315cd28
AC		 3323 fcport->login_retry = vha->hw->login_retry_count;
3324 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
1da177e4 3325
7c3df132 3326 ql_dbg(ql_dbg_disc, vha, 0x2067,
7b833558
OK		 3327 "Port login retry %8phN, id = 0x%04x retry cnt=%d.\n",
3328 fcport->port_name, fcport->loop_id, fcport->login_retry);
1da177e4
LT		 3329 }
3330}
3331
3332/*
3333 * qla2x00_mark_all_devices_lost
3334 * Updates fcport state when device goes offline.
3335 *
3336 * Input:
3337 * ha = adapter block pointer.
3338 * fcport = port structure pointer.
3339 *
3340 * Return:
3341 * None.
3342 *
3343 * Context:
3344 */
3345void
e315cd28 3346qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha, int defer)
1da177e4
LT		 3347{
3348 fc_port_t *fcport;
3349
e315cd28 3350 list_for_each_entry(fcport, &vha->vp_fcports, list) {
c6d39e23 3351 if (vha->vp_idx != 0 && vha->vp_idx != fcport->vha->vp_idx)
1da177e4 3352 continue;
0d6e61bc 3353
1da177e4
LT		 3354 /*
3355 * No point in marking the device as lost, if the device is
3356 * already DEAD.
3357 */
3358 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD)
3359 continue;
e315cd28 3360 if (atomic_read(&fcport->state) == FCS_ONLINE) {
ec426e10 3361 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
0d6e61bc
AV		 3362 if (defer)
3363 qla2x00_schedule_rport_del(vha, fcport, defer);
c6d39e23 3364 else if (vha->vp_idx == fcport->vha->vp_idx)
0d6e61bc
AV		 3365 qla2x00_schedule_rport_del(vha, fcport, defer);
3366 }
1da177e4
LT		 3367 }
3368}
3369
3370/*
3371* qla2x00_mem_alloc
3372* Allocates adapter memory.
3373*
3374* Returns:
3375* 0 = success.
e8711085 3376* !0 = failure.
1da177e4 3377*/
e8711085 3378static int
73208dfd
AC		 3379qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len,
3380 struct req_que **req, struct rsp_que **rsp)
1da177e4
LT		 3381{
3382 char name[16];
1da177e4 3383
e8711085 3384 ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size,
e315cd28 3385 &ha->init_cb_dma, GFP_KERNEL);
e8711085 3386 if (!ha->init_cb)
e315cd28 3387 goto fail;
e8711085 3388
2d70c103
NB		 3389 if (qlt_mem_alloc(ha) < 0)
3390 goto fail_free_init_cb;
3391
642ef983
CD		 3392 ha->gid_list = dma_alloc_coherent(&ha->pdev->dev,
3393 qla2x00_gid_list_size(ha), &ha->gid_list_dma, GFP_KERNEL);
e315cd28 3394 if (!ha->gid_list)
2d70c103 3395 goto fail_free_tgt_mem;
1da177e4 3396
e8711085
AV		 3397 ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep);
3398 if (!ha->srb_mempool)
e315cd28 3399 goto fail_free_gid_list;
e8711085 3400
7ec0effd 3401 if (IS_P3P_TYPE(ha)) {
a9083016
GM		 3402 /* Allocate cache for CT6 Ctx. */
3403 if (!ctx_cachep) {
3404 ctx_cachep = kmem_cache_create("qla2xxx_ctx",
3405 sizeof(struct ct6_dsd), 0,
3406 SLAB_HWCACHE_ALIGN, NULL);
3407 if (!ctx_cachep)
3408 goto fail_free_gid_list;
3409 }
3410 ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ,
3411 ctx_cachep);
3412 if (!ha->ctx_mempool)
3413 goto fail_free_srb_mempool;
7c3df132
SK		 3414 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021,
3415 "ctx_cachep=%p ctx_mempool=%p.\n",
3416 ctx_cachep, ha->ctx_mempool);
a9083016
GM		 3417 }
3418
e8711085
AV		 3419 /* Get memory for cached NVRAM */
3420 ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL);
3421 if (!ha->nvram)
a9083016 3422 goto fail_free_ctx_mempool;
e8711085 3423
e315cd28
AC		 3424 snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME,
3425 ha->pdev->device);
3426 ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3427 DMA_POOL_SIZE, 8, 0);
3428 if (!ha->s_dma_pool)
3429 goto fail_free_nvram;
3430
7c3df132
SK		 3431 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022,
3432 "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n",
3433 ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool);
3434
7ec0effd 3435 if (IS_P3P_TYPE(ha) || ql2xenabledif) {
a9083016
GM		 3436 ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3437 DSD_LIST_DMA_POOL_SIZE, 8, 0);
3438 if (!ha->dl_dma_pool) {
7c3df132
SK		 3439 ql_log_pci(ql_log_fatal, ha->pdev, 0x0023,
3440 "Failed to allocate memory for dl_dma_pool.\n");
a9083016
GM		 3441 goto fail_s_dma_pool;
3442 }
3443
3444 ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3445 FCP_CMND_DMA_POOL_SIZE, 8, 0);
3446 if (!ha->fcp_cmnd_dma_pool) {
7c3df132
SK		 3447 ql_log_pci(ql_log_fatal, ha->pdev, 0x0024,
3448 "Failed to allocate memory for fcp_cmnd_dma_pool.\n");
a9083016
GM		 3449 goto fail_dl_dma_pool;
3450 }
7c3df132
SK		 3451 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025,
3452 "dl_dma_pool=%p fcp_cmnd_dma_pool=%p.\n",
3453 ha->dl_dma_pool, ha->fcp_cmnd_dma_pool);
a9083016
GM		 3454 }
3455
e8711085
AV		 3456 /* Allocate memory for SNS commands */
3457 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
e315cd28 3458 /* Get consistent memory allocated for SNS commands */
e8711085 3459 ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev,
e315cd28 3460 sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL);
e8711085 3461 if (!ha->sns_cmd)
e315cd28 3462 goto fail_dma_pool;
7c3df132 3463 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026,
d8424f68 3464 "sns_cmd: %p.\n", ha->sns_cmd);
e8711085 3465 } else {
e315cd28 3466 /* Get consistent memory allocated for MS IOCB */
e8711085 3467 ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
e315cd28 3468 &ha->ms_iocb_dma);
e8711085 3469 if (!ha->ms_iocb)
e315cd28
AC		 3470 goto fail_dma_pool;
3471 /* Get consistent memory allocated for CT SNS commands */
e8711085 3472 ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev,
e315cd28 3473 sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL);
e8711085
AV		 3474 if (!ha->ct_sns)
3475 goto fail_free_ms_iocb;
7c3df132
SK		 3476 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027,
3477 "ms_iocb=%p ct_sns=%p.\n",
3478 ha->ms_iocb, ha->ct_sns);
1da177e4
LT		 3479 }
3480
e315cd28 3481 /* Allocate memory for request ring */
73208dfd
AC		 3482 *req = kzalloc(sizeof(struct req_que), GFP_KERNEL);
3483 if (!*req) {
7c3df132
SK		 3484 ql_log_pci(ql_log_fatal, ha->pdev, 0x0028,
3485 "Failed to allocate memory for req.\n");
e315cd28
AC		 3486 goto fail_req;
3487 }
73208dfd
AC		 3488 (*req)->length = req_len;
3489 (*req)->ring = dma_alloc_coherent(&ha->pdev->dev,
3490 ((*req)->length + 1) * sizeof(request_t),
3491 &(*req)->dma, GFP_KERNEL);
3492 if (!(*req)->ring) {
7c3df132
SK		 3493 ql_log_pci(ql_log_fatal, ha->pdev, 0x0029,
3494 "Failed to allocate memory for req_ring.\n");
e315cd28
AC		 3495 goto fail_req_ring;
3496 }
3497 /* Allocate memory for response ring */
73208dfd
AC		 3498 *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL);
3499 if (!*rsp) {
7c3df132
SK		 3500 ql_log_pci(ql_log_fatal, ha->pdev, 0x002a,
3501 "Failed to allocate memory for rsp.\n");
e315cd28
AC		 3502 goto fail_rsp;
3503 }
73208dfd
AC		 3504 (*rsp)->hw = ha;
3505 (*rsp)->length = rsp_len;
3506 (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev,
3507 ((*rsp)->length + 1) * sizeof(response_t),
3508 &(*rsp)->dma, GFP_KERNEL);
3509 if (!(*rsp)->ring) {
7c3df132
SK		 3510 ql_log_pci(ql_log_fatal, ha->pdev, 0x002b,
3511 "Failed to allocate memory for rsp_ring.\n");
e315cd28
AC		 3512 goto fail_rsp_ring;
3513 }
73208dfd
AC		 3514 (*req)->rsp = *rsp;
3515 (*rsp)->req = *req;
7c3df132
SK		 3516 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c,
3517 "req=%p req->length=%d req->ring=%p rsp=%p "
3518 "rsp->length=%d rsp->ring=%p.\n",
3519 *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length,
3520 (*rsp)->ring);
73208dfd
AC		 3521 /* Allocate memory for NVRAM data for vports */
3522 if (ha->nvram_npiv_size) {
3523 ha->npiv_info = kzalloc(sizeof(struct qla_npiv_entry) *
7c3df132 3524 ha->nvram_npiv_size, GFP_KERNEL);
73208dfd 3525 if (!ha->npiv_info) {
7c3df132
SK		 3526 ql_log_pci(ql_log_fatal, ha->pdev, 0x002d,
3527 "Failed to allocate memory for npiv_info.\n");
73208dfd
AC		 3528 goto fail_npiv_info;
3529 }
3530 } else
3531 ha->npiv_info = NULL;
e8711085 3532
b64b0e8f 3533 /* Get consistent memory allocated for EX-INIT-CB. */
f73cb695 3534 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha)) {
b64b0e8f
AV		 3535 ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
3536 &ha->ex_init_cb_dma);
3537 if (!ha->ex_init_cb)
3538 goto fail_ex_init_cb;
7c3df132
SK		 3539 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e,
3540 "ex_init_cb=%p.\n", ha->ex_init_cb);
b64b0e8f
AV		 3541 }
3542
a9083016
GM		 3543 INIT_LIST_HEAD(&ha->gbl_dsd_list);
3544
5ff1d584
AV		 3545 /* Get consistent memory allocated for Async Port-Database. */
3546 if (!IS_FWI2_CAPABLE(ha)) {
3547 ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
3548 &ha->async_pd_dma);
3549 if (!ha->async_pd)
3550 goto fail_async_pd;
7c3df132
SK		 3551 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f,
3552 "async_pd=%p.\n", ha->async_pd);
5ff1d584
AV		 3553 }
3554
e315cd28 3555 INIT_LIST_HEAD(&ha->vp_list);
5f16b331
CD		 3556
3557 /* Allocate memory for our loop_id bitmap */
3558 ha->loop_id_map = kzalloc(BITS_TO_LONGS(LOOPID_MAP_SIZE) * sizeof(long),
3559 GFP_KERNEL);
3560 if (!ha->loop_id_map)
3561 goto fail_async_pd;
3562 else {
3563 qla2x00_set_reserved_loop_ids(ha);
3564 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0123,
b2a72ec3 3565 "loop_id_map=%p.\n", ha->loop_id_map);
5f16b331
CD		 3566 }
3567
b2a72ec3 3568 return 0;
e315cd28 3569
5ff1d584
AV		 3570fail_async_pd:
3571 dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma);
b64b0e8f
AV		 3572fail_ex_init_cb:
3573 kfree(ha->npiv_info);
73208dfd
AC		 3574fail_npiv_info:
3575 dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) *
3576 sizeof(response_t), (*rsp)->ring, (*rsp)->dma);
3577 (*rsp)->ring = NULL;
3578 (*rsp)->dma = 0;
e315cd28 3579fail_rsp_ring:
73208dfd 3580 kfree(*rsp);
e315cd28 3581fail_rsp:
73208dfd
AC		 3582 dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) *
3583 sizeof(request_t), (*req)->ring, (*req)->dma);
3584 (*req)->ring = NULL;
3585 (*req)->dma = 0;
e315cd28 3586fail_req_ring:
73208dfd 3587 kfree(*req);
e315cd28
AC		 3588fail_req:
3589 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
3590 ha->ct_sns, ha->ct_sns_dma);
3591 ha->ct_sns = NULL;
3592 ha->ct_sns_dma = 0;
e8711085
AV		 3593fail_free_ms_iocb:
3594 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
3595 ha->ms_iocb = NULL;
3596 ha->ms_iocb_dma = 0;
e315cd28 3597fail_dma_pool:
bad75002 3598 if (IS_QLA82XX(ha) || ql2xenabledif) {
a9083016
GM		 3599 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
3600 ha->fcp_cmnd_dma_pool = NULL;
3601 }
3602fail_dl_dma_pool:
bad75002 3603 if (IS_QLA82XX(ha) || ql2xenabledif) {
a9083016
GM		 3604 dma_pool_destroy(ha->dl_dma_pool);
3605 ha->dl_dma_pool = NULL;
3606 }
3607fail_s_dma_pool:
e315cd28
AC		 3608 dma_pool_destroy(ha->s_dma_pool);
3609 ha->s_dma_pool = NULL;
e8711085
AV		 3610fail_free_nvram:
3611 kfree(ha->nvram);
3612 ha->nvram = NULL;
a9083016
GM		 3613fail_free_ctx_mempool:
3614 mempool_destroy(ha->ctx_mempool);
3615 ha->ctx_mempool = NULL;
e8711085
AV		 3616fail_free_srb_mempool:
3617 mempool_destroy(ha->srb_mempool);
3618 ha->srb_mempool = NULL;
e8711085 3619fail_free_gid_list:
642ef983
CD		 3620 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
3621 ha->gid_list,
e315cd28 3622 ha->gid_list_dma);
e8711085
AV		 3623 ha->gid_list = NULL;
3624 ha->gid_list_dma = 0;
2d70c103
NB		 3625fail_free_tgt_mem:
3626 qlt_mem_free(ha);
e315cd28
AC		 3627fail_free_init_cb:
3628 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb,
3629 ha->init_cb_dma);
3630 ha->init_cb = NULL;
3631 ha->init_cb_dma = 0;
e8711085 3632fail:
7c3df132
SK		 3633 ql_log(ql_log_fatal, NULL, 0x0030,
3634 "Memory allocation failure.\n");
e8711085 3635 return -ENOMEM;
1da177e4
LT		 3636}
3637
3638/*
e30d1756
MI		 3639* qla2x00_free_fw_dump
3640* Frees fw dump stuff.
1da177e4
LT		 3641*
3642* Input:
7ec0effd 3643* ha = adapter block pointer
1da177e4 3644*/
a824ebb3 3645static void
e30d1756 3646qla2x00_free_fw_dump(struct qla_hw_data *ha)
1da177e4 3647{
df613b96 3648 if (ha->fce)
f73cb695
CD		 3649 dma_free_coherent(&ha->pdev->dev,
3650 FCE_SIZE, ha->fce, ha->fce_dma);
df613b96 3651
f73cb695
CD		 3652 if (ha->eft)
3653 dma_free_coherent(&ha->pdev->dev,
3654 EFT_SIZE, ha->eft, ha->eft_dma);
3655
3656 if (ha->fw_dump)
a7a167bf 3657 vfree(ha->fw_dump);
f73cb695
CD		 3658 if (ha->fw_dump_template)
3659 vfree(ha->fw_dump_template);
3660
e30d1756
MI		 3661 ha->fce = NULL;
3662 ha->fce_dma = 0;
3663 ha->eft = NULL;
3664 ha->eft_dma = 0;
e30d1756 3665 ha->fw_dumped = 0;
61f098dd 3666 ha->fw_dump_cap_flags = 0;
e30d1756 3667 ha->fw_dump_reading = 0;
f73cb695
CD		 3668 ha->fw_dump = NULL;
3669 ha->fw_dump_len = 0;
3670 ha->fw_dump_template = NULL;
3671 ha->fw_dump_template_len = 0;
e30d1756
MI		 3672}
3673
3674/*
3675* qla2x00_mem_free
3676* Frees all adapter allocated memory.
3677*
3678* Input:
3679* ha = adapter block pointer.
3680*/
3681static void
3682qla2x00_mem_free(struct qla_hw_data *ha)
3683{
3684 qla2x00_free_fw_dump(ha);
3685
81178772
SK		 3686 if (ha->mctp_dump)
3687 dma_free_coherent(&ha->pdev->dev, MCTP_DUMP_SIZE, ha->mctp_dump,
3688 ha->mctp_dump_dma);
3689
e30d1756
MI		 3690 if (ha->srb_mempool)
3691 mempool_destroy(ha->srb_mempool);
a7a167bf 3692
11bbc1d8
AV		 3693 if (ha->dcbx_tlv)
3694 dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE,
3695 ha->dcbx_tlv, ha->dcbx_tlv_dma);
3696
ce0423f4
AV		 3697 if (ha->xgmac_data)
3698 dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE,
3699 ha->xgmac_data, ha->xgmac_data_dma);
3700
1da177e4
LT		 3701 if (ha->sns_cmd)
3702 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
e315cd28 3703 ha->sns_cmd, ha->sns_cmd_dma);
1da177e4
LT		 3704
3705 if (ha->ct_sns)
3706 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
e315cd28 3707 ha->ct_sns, ha->ct_sns_dma);
1da177e4 3708
88729e53
AV		 3709 if (ha->sfp_data)
3710 dma_pool_free(ha->s_dma_pool, ha->sfp_data, ha->sfp_data_dma);
3711
1da177e4
LT		 3712 if (ha->ms_iocb)
3713 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
3714
b64b0e8f 3715 if (ha->ex_init_cb)
a9083016
GM		 3716 dma_pool_free(ha->s_dma_pool,
3717 ha->ex_init_cb, ha->ex_init_cb_dma);
b64b0e8f 3718
5ff1d584
AV		 3719 if (ha->async_pd)
3720 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
3721
1da177e4
LT		 3722 if (ha->s_dma_pool)
3723 dma_pool_destroy(ha->s_dma_pool);
3724
1da177e4 3725 if (ha->gid_list)
642ef983
CD		 3726 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
3727 ha->gid_list, ha->gid_list_dma);
1da177e4 3728
a9083016
GM		 3729 if (IS_QLA82XX(ha)) {
3730 if (!list_empty(&ha->gbl_dsd_list)) {
3731 struct dsd_dma *dsd_ptr, *tdsd_ptr;
3732
3733 /* clean up allocated prev pool */
3734 list_for_each_entry_safe(dsd_ptr,
3735 tdsd_ptr, &ha->gbl_dsd_list, list) {
3736 dma_pool_free(ha->dl_dma_pool,
3737 dsd_ptr->dsd_addr, dsd_ptr->dsd_list_dma);
3738 list_del(&dsd_ptr->list);
3739 kfree(dsd_ptr);
3740 }
3741 }
3742 }
3743
3744 if (ha->dl_dma_pool)
3745 dma_pool_destroy(ha->dl_dma_pool);
3746
3747 if (ha->fcp_cmnd_dma_pool)
3748 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
3749
3750 if (ha->ctx_mempool)
3751 mempool_destroy(ha->ctx_mempool);
3752
2d70c103
NB		 3753 qlt_mem_free(ha);
3754
e315cd28
AC		 3755 if (ha->init_cb)
3756 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size,
a9083016 3757 ha->init_cb, ha->init_cb_dma);
e315cd28
AC		 3758 vfree(ha->optrom_buffer);
3759 kfree(ha->nvram);
73208dfd 3760 kfree(ha->npiv_info);
7a67735b 3761 kfree(ha->swl);
5f16b331 3762 kfree(ha->loop_id_map);
1da177e4 3763
e8711085 3764 ha->srb_mempool = NULL;
a9083016 3765 ha->ctx_mempool = NULL;
1da177e4
LT		 3766 ha->sns_cmd = NULL;
3767 ha->sns_cmd_dma = 0;
3768 ha->ct_sns = NULL;
3769 ha->ct_sns_dma = 0;
3770 ha->ms_iocb = NULL;
3771 ha->ms_iocb_dma = 0;
1da177e4
LT		 3772 ha->init_cb = NULL;
3773 ha->init_cb_dma = 0;
b64b0e8f
AV		 3774 ha->ex_init_cb = NULL;
3775 ha->ex_init_cb_dma = 0;
5ff1d584
AV		 3776 ha->async_pd = NULL;
3777 ha->async_pd_dma = 0;
1da177e4
LT		 3778
3779 ha->s_dma_pool = NULL;
a9083016
GM		 3780 ha->dl_dma_pool = NULL;
3781 ha->fcp_cmnd_dma_pool = NULL;
1da177e4 3782
1da177e4
LT		 3783 ha->gid_list = NULL;
3784 ha->gid_list_dma = 0;
2d70c103
NB		 3785
3786 ha->tgt.atio_ring = NULL;
3787 ha->tgt.atio_dma = 0;
3788 ha->tgt.tgt_vp_map = NULL;
e315cd28 3789}
1da177e4 3790
e315cd28
AC		 3791struct scsi_qla_host *qla2x00_create_host(struct scsi_host_template *sht,
3792 struct qla_hw_data *ha)
3793{
3794 struct Scsi_Host *host;
3795 struct scsi_qla_host *vha = NULL;
854165f4 3796
e315cd28
AC		 3797 host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t));
3798 if (host == NULL) {
7c3df132
SK		 3799 ql_log_pci(ql_log_fatal, ha->pdev, 0x0107,
3800 "Failed to allocate host from the scsi layer, aborting.\n");
e315cd28
AC		 3801 goto fail;
3802 }
3803
3804 /* Clear our data area */
3805 vha = shost_priv(host);
3806 memset(vha, 0, sizeof(scsi_qla_host_t));
3807
3808 vha->host = host;
3809 vha->host_no = host->host_no;
3810 vha->hw = ha;
3811
3812 INIT_LIST_HEAD(&vha->vp_fcports);
3813 INIT_LIST_HEAD(&vha->work_list);
3814 INIT_LIST_HEAD(&vha->list);
3815
f999f4c1
AV		 3816 spin_lock_init(&vha->work_lock);
3817
e315cd28 3818 sprintf(vha->host_str, "%s_%ld", QLA2XXX_DRIVER_NAME, vha->host_no);
7c3df132
SK		 3819 ql_dbg(ql_dbg_init, vha, 0x0041,
3820 "Allocated the host=%p hw=%p vha=%p dev_name=%s",
3821 vha->host, vha->hw, vha,
3822 dev_name(&(ha->pdev->dev)));
3823
e315cd28
AC		 3824 return vha;
3825
3826fail:
3827 return vha;
1da177e4
LT		 3828}
3829
01ef66bb 3830static struct qla_work_evt *
f999f4c1 3831qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type)
0971de7f
AV		 3832{
3833 struct qla_work_evt *e;
feafb7b1
AE		 3834 uint8_t bail;
3835
3836 QLA_VHA_MARK_BUSY(vha, bail);
3837 if (bail)
3838 return NULL;
0971de7f 3839
f999f4c1 3840 e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC);
feafb7b1
AE		 3841 if (!e) {
3842 QLA_VHA_MARK_NOT_BUSY(vha);
0971de7f 3843 return NULL;
feafb7b1 3844 }
0971de7f
AV		 3845
3846 INIT_LIST_HEAD(&e->list);
3847 e->type = type;
3848 e->flags = QLA_EVT_FLAG_FREE;
3849 return e;
3850}
3851
01ef66bb 3852static int
f999f4c1 3853qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e)
0971de7f 3854{
f999f4c1 3855 unsigned long flags;
0971de7f 3856
f999f4c1 3857 spin_lock_irqsave(&vha->work_lock, flags);
e315cd28 3858 list_add_tail(&e->list, &vha->work_list);
f999f4c1 3859 spin_unlock_irqrestore(&vha->work_lock, flags);
e315cd28 3860 qla2xxx_wake_dpc(vha);
f999f4c1 3861
0971de7f
AV		 3862 return QLA_SUCCESS;
3863}
3864
3865int
e315cd28 3866qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code,
0971de7f
AV		 3867 u32 data)
3868{
3869 struct qla_work_evt *e;
3870
f999f4c1 3871 e = qla2x00_alloc_work(vha, QLA_EVT_AEN);
0971de7f
AV		 3872 if (!e)
3873 return QLA_FUNCTION_FAILED;
3874
3875 e->u.aen.code = code;
3876 e->u.aen.data = data;
f999f4c1 3877 return qla2x00_post_work(vha, e);
0971de7f
AV		 3878}
3879
8a659571
AV		 3880int
3881qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb)
3882{
3883 struct qla_work_evt *e;
3884
f999f4c1 3885 e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK);
8a659571
AV		 3886 if (!e)
3887 return QLA_FUNCTION_FAILED;
3888
3889 memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t));
f999f4c1 3890 return qla2x00_post_work(vha, e);
8a659571
AV		 3891}
3892
ac280b67
AV		 3893#define qla2x00_post_async_work(name, type) \
3894int qla2x00_post_async_##name##_work( \
3895 struct scsi_qla_host *vha, \
3896 fc_port_t *fcport, uint16_t *data) \
3897{ \
3898 struct qla_work_evt *e; \
3899 \
3900 e = qla2x00_alloc_work(vha, type); \
3901 if (!e) \
3902 return QLA_FUNCTION_FAILED; \
3903 \
3904 e->u.logio.fcport = fcport; \
3905 if (data) { \
3906 e->u.logio.data[0] = data[0]; \
3907 e->u.logio.data[1] = data[1]; \
3908 } \
3909 return qla2x00_post_work(vha, e); \
3910}
3911
3912qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN);
3913qla2x00_post_async_work(login_done, QLA_EVT_ASYNC_LOGIN_DONE);
3914qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT);
3915qla2x00_post_async_work(logout_done, QLA_EVT_ASYNC_LOGOUT_DONE);
5ff1d584
AV		 3916qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC);
3917qla2x00_post_async_work(adisc_done, QLA_EVT_ASYNC_ADISC_DONE);
ac280b67 3918
3420d36c
AV		 3919int
3920qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code)
3921{
3922 struct qla_work_evt *e;
3923
3924 e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT);
3925 if (!e)
3926 return QLA_FUNCTION_FAILED;
3927
3928 e->u.uevent.code = code;
3929 return qla2x00_post_work(vha, e);
3930}
3931
3932static void
3933qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code)
3934{
3935 char event_string[40];
3936 char *envp[] = { event_string, NULL };
3937
3938 switch (code) {
3939 case QLA_UEVENT_CODE_FW_DUMP:
3940 snprintf(event_string, sizeof(event_string), "FW_DUMP=%ld",
3941 vha->host_no);
3942 break;
3943 default:
3944 /* do nothing */
3945 break;
3946 }
3947 kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp);
3948}
3949
8ae6d9c7
GM		 3950int
3951qlafx00_post_aenfx_work(struct scsi_qla_host *vha, uint32_t evtcode,
3952 uint32_t *data, int cnt)
3953{
3954 struct qla_work_evt *e;
3955
3956 e = qla2x00_alloc_work(vha, QLA_EVT_AENFX);
3957 if (!e)
3958 return QLA_FUNCTION_FAILED;
3959
3960 e->u.aenfx.evtcode = evtcode;
3961 e->u.aenfx.count = cnt;
3962 memcpy(e->u.aenfx.mbx, data, sizeof(*data) * cnt);
3963 return qla2x00_post_work(vha, e);
3964}
3965
ac280b67 3966void
e315cd28 3967qla2x00_do_work(struct scsi_qla_host *vha)
0971de7f 3968{
f999f4c1
AV		 3969 struct qla_work_evt *e, *tmp;
3970 unsigned long flags;
3971 LIST_HEAD(work);
0971de7f 3972
f999f4c1
AV		 3973 spin_lock_irqsave(&vha->work_lock, flags);
3974 list_splice_init(&vha->work_list, &work);
3975 spin_unlock_irqrestore(&vha->work_lock, flags);
3976
3977 list_for_each_entry_safe(e, tmp, &work, list) {
0971de7f 3978 list_del_init(&e->list);
0971de7f
AV		 3979
3980 switch (e->type) {
3981 case QLA_EVT_AEN:
e315cd28 3982 fc_host_post_event(vha->host, fc_get_event_number(),
0971de7f
AV		 3983 e->u.aen.code, e->u.aen.data);
3984 break;
8a659571
AV		 3985 case QLA_EVT_IDC_ACK:
3986 qla81xx_idc_ack(vha, e->u.idc_ack.mb);
3987 break;
ac280b67
AV		 3988 case QLA_EVT_ASYNC_LOGIN:
3989 qla2x00_async_login(vha, e->u.logio.fcport,
3990 e->u.logio.data);
3991 break;
3992 case QLA_EVT_ASYNC_LOGIN_DONE:
3993 qla2x00_async_login_done(vha, e->u.logio.fcport,
3994 e->u.logio.data);
3995 break;
3996 case QLA_EVT_ASYNC_LOGOUT:
3997 qla2x00_async_logout(vha, e->u.logio.fcport);
3998 break;
3999 case QLA_EVT_ASYNC_LOGOUT_DONE:
4000 qla2x00_async_logout_done(vha, e->u.logio.fcport,
4001 e->u.logio.data);
4002 break;
5ff1d584
AV		 4003 case QLA_EVT_ASYNC_ADISC:
4004 qla2x00_async_adisc(vha, e->u.logio.fcport,
4005 e->u.logio.data);
4006 break;
4007 case QLA_EVT_ASYNC_ADISC_DONE:
4008 qla2x00_async_adisc_done(vha, e->u.logio.fcport,
4009 e->u.logio.data);
4010 break;
3420d36c
AV		 4011 case QLA_EVT_UEVENT:
4012 qla2x00_uevent_emit(vha, e->u.uevent.code);
4013 break;
8ae6d9c7
GM		 4014 case QLA_EVT_AENFX:
4015 qlafx00_process_aen(vha, e);
4016 break;
0971de7f
AV		 4017 }
4018 if (e->flags & QLA_EVT_FLAG_FREE)
4019 kfree(e);
feafb7b1
AE		 4020
4021 /* For each work completed decrement vha ref count */
4022 QLA_VHA_MARK_NOT_BUSY(vha);
e315cd28 4023 }
e315cd28 4024}
f999f4c1 4025
e315cd28
AC		 4026/* Relogins all the fcports of a vport
4027 * Context: dpc thread
4028 */
4029void qla2x00_relogin(struct scsi_qla_host *vha)
4030{
4031 fc_port_t *fcport;
c6b2fca8 4032 int status;
e315cd28
AC		 4033 uint16_t next_loopid = 0;
4034 struct qla_hw_data *ha = vha->hw;
ac280b67 4035 uint16_t data[2];
e315cd28
AC		 4036
4037 list_for_each_entry(fcport, &vha->vp_fcports, list) {
4038 /*
4039 * If the port is not ONLINE then try to login
4040 * to it if we haven't run out of retries.
4041 */
5ff1d584
AV		 4042 if (atomic_read(&fcport->state) != FCS_ONLINE &&
4043 fcport->login_retry && !(fcport->flags & FCF_ASYNC_SENT)) {
ac280b67 4044 fcport->login_retry--;
e315cd28 4045 if (fcport->flags & FCF_FABRIC_DEVICE) {
f08b7251 4046 if (fcport->flags & FCF_FCP2_DEVICE)
e315cd28
AC		 4047 ha->isp_ops->fabric_logout(vha,
4048 fcport->loop_id,
4049 fcport->d_id.b.domain,
4050 fcport->d_id.b.area,
4051 fcport->d_id.b.al_pa);
4052
03bcfb57
JC		 4053 if (fcport->loop_id == FC_NO_LOOP_ID) {
4054 fcport->loop_id = next_loopid =
4055 ha->min_external_loopid;
4056 status = qla2x00_find_new_loop_id(
4057 vha, fcport);
4058 if (status != QLA_SUCCESS) {
4059 /* Ran out of IDs to use */
4060 break;
4061 }
4062 }
4063
ac280b67 4064 if (IS_ALOGIO_CAPABLE(ha)) {
5ff1d584 4065 fcport->flags |= FCF_ASYNC_SENT;
ac280b67
AV		 4066 data[0] = 0;
4067 data[1] = QLA_LOGIO_LOGIN_RETRIED;
4068 status = qla2x00_post_async_login_work(
4069 vha, fcport, data);
4070 if (status == QLA_SUCCESS)
4071 continue;
4072 /* Attempt a retry. */
4073 status = 1;
aaf4d3e2 4074 } else {
ac280b67
AV		 4075 status = qla2x00_fabric_login(vha,
4076 fcport, &next_loopid);
aaf4d3e2
SK		 4077 if (status == QLA_SUCCESS) {
4078 int status2;
4079 uint8_t opts;
4080
4081 opts = 0;
4082 if (fcport->flags &
4083 FCF_FCP2_DEVICE)
4084 opts |= BIT_1;
03003960
SK		 4085 status2 =
4086 qla2x00_get_port_database(
4087 vha, fcport, opts);
aaf4d3e2
SK		 4088 if (status2 != QLA_SUCCESS)
4089 status = 1;
4090 }
4091 }
e315cd28
AC		 4092 } else
4093 status = qla2x00_local_device_login(vha,
4094 fcport);
4095
e315cd28
AC		 4096 if (status == QLA_SUCCESS) {
4097 fcport->old_loop_id = fcport->loop_id;
4098
7c3df132
SK		 4099 ql_dbg(ql_dbg_disc, vha, 0x2003,
4100 "Port login OK: logged in ID 0x%x.\n",
4101 fcport->loop_id);
e315cd28
AC		 4102
4103 qla2x00_update_fcport(vha, fcport);
4104
4105 } else if (status == 1) {
4106 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
4107 /* retry the login again */
7c3df132
SK		 4108 ql_dbg(ql_dbg_disc, vha, 0x2007,
4109 "Retrying %d login again loop_id 0x%x.\n",
4110 fcport->login_retry, fcport->loop_id);
e315cd28
AC		 4111 } else {
4112 fcport->login_retry = 0;
4113 }
4114
4115 if (fcport->login_retry == 0 && status != QLA_SUCCESS)
5f16b331 4116 qla2x00_clear_loop_id(fcport);
e315cd28
AC		 4117 }
4118 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
4119 break;
0971de7f 4120 }
0971de7f
AV		 4121}
4122
7d613ac6
SV		 4123/* Schedule work on any of the dpc-workqueues */
4124void
4125qla83xx_schedule_work(scsi_qla_host_t *base_vha, int work_code)
4126{
4127 struct qla_hw_data *ha = base_vha->hw;
4128
4129 switch (work_code) {
4130 case MBA_IDC_AEN: /* 0x8200 */
4131 if (ha->dpc_lp_wq)
4132 queue_work(ha->dpc_lp_wq, &ha->idc_aen);
4133 break;
4134
4135 case QLA83XX_NIC_CORE_RESET: /* 0x1 */
4136 if (!ha->flags.nic_core_reset_hdlr_active) {
4137 if (ha->dpc_hp_wq)
4138 queue_work(ha->dpc_hp_wq, &ha->nic_core_reset);
4139 } else
4140 ql_dbg(ql_dbg_p3p, base_vha, 0xb05e,
4141 "NIC Core reset is already active. Skip "
4142 "scheduling it again.\n");
4143 break;
4144 case QLA83XX_IDC_STATE_HANDLER: /* 0x2 */
4145 if (ha->dpc_hp_wq)
4146 queue_work(ha->dpc_hp_wq, &ha->idc_state_handler);
4147 break;
4148 case QLA83XX_NIC_CORE_UNRECOVERABLE: /* 0x3 */
4149 if (ha->dpc_hp_wq)
4150 queue_work(ha->dpc_hp_wq, &ha->nic_core_unrecoverable);
4151 break;
4152 default:
4153 ql_log(ql_log_warn, base_vha, 0xb05f,
4154 "Unknow work-code=0x%x.\n", work_code);
4155 }
4156
4157 return;
4158}
4159
4160/* Work: Perform NIC Core Unrecoverable state handling */
4161void
4162qla83xx_nic_core_unrecoverable_work(struct work_struct *work)
4163{
4164 struct qla_hw_data *ha =
2ad1b67c 4165 container_of(work, struct qla_hw_data, nic_core_unrecoverable);
7d613ac6
SV		 4166 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4167 uint32_t dev_state = 0;
4168
4169 qla83xx_idc_lock(base_vha, 0);
4170 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4171 qla83xx_reset_ownership(base_vha);
4172 if (ha->flags.nic_core_reset_owner) {
4173 ha->flags.nic_core_reset_owner = 0;
4174 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
4175 QLA8XXX_DEV_FAILED);
4176 ql_log(ql_log_info, base_vha, 0xb060, "HW State: FAILED.\n");
4177 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
4178 }
4179 qla83xx_idc_unlock(base_vha, 0);
4180}
4181
4182/* Work: Execute IDC state handler */
4183void
4184qla83xx_idc_state_handler_work(struct work_struct *work)
4185{
4186 struct qla_hw_data *ha =
2ad1b67c 4187 container_of(work, struct qla_hw_data, idc_state_handler);
7d613ac6
SV		 4188 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4189 uint32_t dev_state = 0;
4190
4191 qla83xx_idc_lock(base_vha, 0);
4192 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4193 if (dev_state == QLA8XXX_DEV_FAILED ||
4194 dev_state == QLA8XXX_DEV_NEED_QUIESCENT)
4195 qla83xx_idc_state_handler(base_vha);
4196 qla83xx_idc_unlock(base_vha, 0);
4197}
4198
fa492630 4199static int
7d613ac6
SV		 4200qla83xx_check_nic_core_fw_alive(scsi_qla_host_t *base_vha)
4201{
4202 int rval = QLA_SUCCESS;
4203 unsigned long heart_beat_wait = jiffies + (1 * HZ);
4204 uint32_t heart_beat_counter1, heart_beat_counter2;
4205
4206 do {
4207 if (time_after(jiffies, heart_beat_wait)) {
4208 ql_dbg(ql_dbg_p3p, base_vha, 0xb07c,
4209 "Nic Core f/w is not alive.\n");
4210 rval = QLA_FUNCTION_FAILED;
4211 break;
4212 }
4213
4214 qla83xx_idc_lock(base_vha, 0);
4215 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
4216 &heart_beat_counter1);
4217 qla83xx_idc_unlock(base_vha, 0);
4218 msleep(100);
4219 qla83xx_idc_lock(base_vha, 0);
4220 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
4221 &heart_beat_counter2);
4222 qla83xx_idc_unlock(base_vha, 0);
4223 } while (heart_beat_counter1 == heart_beat_counter2);
4224
4225 return rval;
4226}
4227
4228/* Work: Perform NIC Core Reset handling */
4229void
4230qla83xx_nic_core_reset_work(struct work_struct *work)
4231{
4232 struct qla_hw_data *ha =
4233 container_of(work, struct qla_hw_data, nic_core_reset);
4234 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4235 uint32_t dev_state = 0;
4236
81178772
SK		 4237 if (IS_QLA2031(ha)) {
4238 if (qla2xxx_mctp_dump(base_vha) != QLA_SUCCESS)
4239 ql_log(ql_log_warn, base_vha, 0xb081,
4240 "Failed to dump mctp\n");
4241 return;
4242 }
4243
7d613ac6
SV		 4244 if (!ha->flags.nic_core_reset_hdlr_active) {
4245 if (qla83xx_check_nic_core_fw_alive(base_vha) == QLA_SUCCESS) {
4246 qla83xx_idc_lock(base_vha, 0);
4247 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE,
4248 &dev_state);
4249 qla83xx_idc_unlock(base_vha, 0);
4250 if (dev_state != QLA8XXX_DEV_NEED_RESET) {
4251 ql_dbg(ql_dbg_p3p, base_vha, 0xb07a,
4252 "Nic Core f/w is alive.\n");
4253 return;
4254 }
4255 }
4256
4257 ha->flags.nic_core_reset_hdlr_active = 1;
4258 if (qla83xx_nic_core_reset(base_vha)) {
4259 /* NIC Core reset failed. */
4260 ql_dbg(ql_dbg_p3p, base_vha, 0xb061,
4261 "NIC Core reset failed.\n");
4262 }
4263 ha->flags.nic_core_reset_hdlr_active = 0;
4264 }
4265}
4266
4267/* Work: Handle 8200 IDC aens */
4268void
4269qla83xx_service_idc_aen(struct work_struct *work)
4270{
4271 struct qla_hw_data *ha =
4272 container_of(work, struct qla_hw_data, idc_aen);
4273 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4274 uint32_t dev_state, idc_control;
4275
4276 qla83xx_idc_lock(base_vha, 0);
4277 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4278 qla83xx_rd_reg(base_vha, QLA83XX_IDC_CONTROL, &idc_control);
4279 qla83xx_idc_unlock(base_vha, 0);
4280 if (dev_state == QLA8XXX_DEV_NEED_RESET) {
4281 if (idc_control & QLA83XX_IDC_GRACEFUL_RESET) {
4282 ql_dbg(ql_dbg_p3p, base_vha, 0xb062,
4283 "Application requested NIC Core Reset.\n");
4284 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
4285 } else if (qla83xx_check_nic_core_fw_alive(base_vha) ==
4286 QLA_SUCCESS) {
4287 ql_dbg(ql_dbg_p3p, base_vha, 0xb07b,
4288 "Other protocol driver requested NIC Core Reset.\n");
4289 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
4290 }
4291 } else if (dev_state == QLA8XXX_DEV_FAILED ||
4292 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) {
4293 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
4294 }
4295}
4296
4297static void
4298qla83xx_wait_logic(void)
4299{
4300 int i;
4301
4302 /* Yield CPU */
4303 if (!in_interrupt()) {
4304 /*
4305 * Wait about 200ms before retrying again.
4306 * This controls the number of retries for single
4307 * lock operation.
4308 */
4309 msleep(100);
4310 schedule();
4311 } else {
4312 for (i = 0; i < 20; i++)
4313 cpu_relax(); /* This a nop instr on i386 */
4314 }
4315}
4316
fa492630 4317static int
7d613ac6
SV		 4318qla83xx_force_lock_recovery(scsi_qla_host_t *base_vha)
4319{
4320 int rval;
4321 uint32_t data;
4322 uint32_t idc_lck_rcvry_stage_mask = 0x3;
4323 uint32_t idc_lck_rcvry_owner_mask = 0x3c;
4324 struct qla_hw_data *ha = base_vha->hw;
6c315553
SK		 4325 ql_dbg(ql_dbg_p3p, base_vha, 0xb086,
4326 "Trying force recovery of the IDC lock.\n");
7d613ac6
SV		 4327
4328 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, &data);
4329 if (rval)
4330 return rval;
4331
4332 if ((data & idc_lck_rcvry_stage_mask) > 0) {
4333 return QLA_SUCCESS;
4334 } else {
4335 data = (IDC_LOCK_RECOVERY_STAGE1) | (ha->portnum << 2);
4336 rval = qla83xx_wr_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
4337 data);
4338 if (rval)
4339 return rval;
4340
4341 msleep(200);
4342
4343 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
4344 &data);
4345 if (rval)
4346 return rval;
4347
4348 if (((data & idc_lck_rcvry_owner_mask) >> 2) == ha->portnum) {
4349 data &= (IDC_LOCK_RECOVERY_STAGE2 |
4350 ~(idc_lck_rcvry_stage_mask));
4351 rval = qla83xx_wr_reg(base_vha,
4352 QLA83XX_IDC_LOCK_RECOVERY, data);
4353 if (rval)
4354 return rval;
4355
4356 /* Forcefully perform IDC UnLock */
4357 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK,
4358 &data);
4359 if (rval)
4360 return rval;
4361 /* Clear lock-id by setting 0xff */
4362 rval = qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
4363 0xff);
4364 if (rval)
4365 return rval;
4366 /* Clear lock-recovery by setting 0x0 */
4367 rval = qla83xx_wr_reg(base_vha,
4368 QLA83XX_IDC_LOCK_RECOVERY, 0x0);
4369 if (rval)
4370 return rval;
4371 } else
4372 return QLA_SUCCESS;
4373 }
4374
4375 return rval;
4376}
4377
fa492630 4378static int
7d613ac6
SV		 4379qla83xx_idc_lock_recovery(scsi_qla_host_t *base_vha)
4380{
4381 int rval = QLA_SUCCESS;
4382 uint32_t o_drv_lockid, n_drv_lockid;
4383 unsigned long lock_recovery_timeout;
4384
4385 lock_recovery_timeout = jiffies + QLA83XX_MAX_LOCK_RECOVERY_WAIT;
4386retry_lockid:
4387 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &o_drv_lockid);
4388 if (rval)
4389 goto exit;
4390
4391 /* MAX wait time before forcing IDC Lock recovery = 2 secs */
4392 if (time_after_eq(jiffies, lock_recovery_timeout)) {
4393 if (qla83xx_force_lock_recovery(base_vha) == QLA_SUCCESS)
4394 return QLA_SUCCESS;
4395 else
4396 return QLA_FUNCTION_FAILED;
4397 }
4398
4399 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &n_drv_lockid);
4400 if (rval)
4401 goto exit;
4402
4403 if (o_drv_lockid == n_drv_lockid) {
4404 qla83xx_wait_logic();
4405 goto retry_lockid;
4406 } else
4407 return QLA_SUCCESS;
4408
4409exit:
4410 return rval;
4411}
4412
4413void
4414qla83xx_idc_lock(scsi_qla_host_t *base_vha, uint16_t requester_id)
4415{
4416 uint16_t options = (requester_id << 15) | BIT_6;
4417 uint32_t data;
6c315553 4418 uint32_t lock_owner;
7d613ac6
SV		 4419 struct qla_hw_data *ha = base_vha->hw;
4420
4421 /* IDC-lock implementation using driver-lock/lock-id remote registers */
4422retry_lock:
4423 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCK, &data)
4424 == QLA_SUCCESS) {
4425 if (data) {
4426 /* Setting lock-id to our function-number */
4427 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
4428 ha->portnum);
4429 } else {
6c315553
SK		 4430 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID,
4431 &lock_owner);
7d613ac6 4432 ql_dbg(ql_dbg_p3p, base_vha, 0xb063,
6c315553
SK		 4433 "Failed to acquire IDC lock, acquired by %d, "
4434 "retrying...\n", lock_owner);
7d613ac6
SV		 4435
4436 /* Retry/Perform IDC-Lock recovery */
4437 if (qla83xx_idc_lock_recovery(base_vha)
4438 == QLA_SUCCESS) {
4439 qla83xx_wait_logic();
4440 goto retry_lock;
4441 } else
4442 ql_log(ql_log_warn, base_vha, 0xb075,
4443 "IDC Lock recovery FAILED.\n");
4444 }
4445
4446 }
4447
4448 return;
4449
4450 /* XXX: IDC-lock implementation using access-control mbx */
4451retry_lock2:
4452 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
4453 ql_dbg(ql_dbg_p3p, base_vha, 0xb072,
4454 "Failed to acquire IDC lock. retrying...\n");
4455 /* Retry/Perform IDC-Lock recovery */
4456 if (qla83xx_idc_lock_recovery(base_vha) == QLA_SUCCESS) {
4457 qla83xx_wait_logic();
4458 goto retry_lock2;
4459 } else
4460 ql_log(ql_log_warn, base_vha, 0xb076,
4461 "IDC Lock recovery FAILED.\n");
4462 }
4463
4464 return;
4465}
4466
4467void
4468qla83xx_idc_unlock(scsi_qla_host_t *base_vha, uint16_t requester_id)
4469{
4470 uint16_t options = (requester_id << 15) | BIT_7, retry;
4471 uint32_t data;
4472 struct qla_hw_data *ha = base_vha->hw;
4473
4474 /* IDC-unlock implementation using driver-unlock/lock-id
4475 * remote registers
4476 */
4477 retry = 0;
4478retry_unlock:
4479 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &data)
4480 == QLA_SUCCESS) {
4481 if (data == ha->portnum) {
4482 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, &data);
4483 /* Clearing lock-id by setting 0xff */
4484 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 0xff);
4485 } else if (retry < 10) {
4486 /* SV: XXX: IDC unlock retrying needed here? */
4487
4488 /* Retry for IDC-unlock */
4489 qla83xx_wait_logic();
4490 retry++;
4491 ql_dbg(ql_dbg_p3p, base_vha, 0xb064,
4492 "Failed to release IDC lock, retyring=%d\n", retry);
4493 goto retry_unlock;
4494 }
4495 } else if (retry < 10) {
4496 /* Retry for IDC-unlock */
4497 qla83xx_wait_logic();
4498 retry++;
4499 ql_dbg(ql_dbg_p3p, base_vha, 0xb065,
4500 "Failed to read drv-lockid, retyring=%d\n", retry);
4501 goto retry_unlock;
4502 }
4503
4504 return;
4505
4506 /* XXX: IDC-unlock implementation using access-control mbx */
4507 retry = 0;
4508retry_unlock2:
4509 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
4510 if (retry < 10) {
4511 /* Retry for IDC-unlock */
4512 qla83xx_wait_logic();
4513 retry++;
4514 ql_dbg(ql_dbg_p3p, base_vha, 0xb066,
4515 "Failed to release IDC lock, retyring=%d\n", retry);
4516 goto retry_unlock2;
4517 }
4518 }
4519
4520 return;
4521}
4522
4523int
4524__qla83xx_set_drv_presence(scsi_qla_host_t *vha)
4525{
4526 int rval = QLA_SUCCESS;
4527 struct qla_hw_data *ha = vha->hw;
4528 uint32_t drv_presence;
4529
4530 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
4531 if (rval == QLA_SUCCESS) {
4532 drv_presence |= (1 << ha->portnum);
4533 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
4534 drv_presence);
4535 }
4536
4537 return rval;
4538}
4539
4540int
4541qla83xx_set_drv_presence(scsi_qla_host_t *vha)
4542{
4543 int rval = QLA_SUCCESS;
4544
4545 qla83xx_idc_lock(vha, 0);
4546 rval = __qla83xx_set_drv_presence(vha);
4547 qla83xx_idc_unlock(vha, 0);
4548
4549 return rval;
4550}
4551
4552int
4553__qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
4554{
4555 int rval = QLA_SUCCESS;
4556 struct qla_hw_data *ha = vha->hw;
4557 uint32_t drv_presence;
4558
4559 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
4560 if (rval == QLA_SUCCESS) {
4561 drv_presence &= ~(1 << ha->portnum);
4562 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
4563 drv_presence);
4564 }
4565
4566 return rval;
4567}
4568
4569int
4570qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
4571{
4572 int rval = QLA_SUCCESS;
4573
4574 qla83xx_idc_lock(vha, 0);
4575 rval = __qla83xx_clear_drv_presence(vha);
4576 qla83xx_idc_unlock(vha, 0);
4577
4578 return rval;
4579}
4580
fa492630 4581static void
7d613ac6
SV		 4582qla83xx_need_reset_handler(scsi_qla_host_t *vha)
4583{
4584 struct qla_hw_data *ha = vha->hw;
4585 uint32_t drv_ack, drv_presence;
4586 unsigned long ack_timeout;
4587
4588 /* Wait for IDC ACK from all functions (DRV-ACK == DRV-PRESENCE) */
4589 ack_timeout = jiffies + (ha->fcoe_reset_timeout * HZ);
4590 while (1) {
4591 qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
4592 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
807fb6d8 4593 if ((drv_ack & drv_presence) == drv_presence)
7d613ac6
SV		 4594 break;
4595
4596 if (time_after_eq(jiffies, ack_timeout)) {
4597 ql_log(ql_log_warn, vha, 0xb067,
4598 "RESET ACK TIMEOUT! drv_presence=0x%x "
4599 "drv_ack=0x%x\n", drv_presence, drv_ack);
4600 /*
4601 * The function(s) which did not ack in time are forced
4602 * to withdraw any further participation in the IDC
4603 * reset.
4604 */
4605 if (drv_ack != drv_presence)
4606 qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
4607 drv_ack);
4608 break;
4609 }
4610
4611 qla83xx_idc_unlock(vha, 0);
4612 msleep(1000);
4613 qla83xx_idc_lock(vha, 0);
4614 }
4615
4616 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_COLD);
4617 ql_log(ql_log_info, vha, 0xb068, "HW State: COLD/RE-INIT.\n");
4618}
4619
fa492630 4620static int
7d613ac6
SV		 4621qla83xx_device_bootstrap(scsi_qla_host_t *vha)
4622{
4623 int rval = QLA_SUCCESS;
4624 uint32_t idc_control;
4625
4626 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_INITIALIZING);
4627 ql_log(ql_log_info, vha, 0xb069, "HW State: INITIALIZING.\n");
4628
4629 /* Clearing IDC-Control Graceful-Reset Bit before resetting f/w */
4630 __qla83xx_get_idc_control(vha, &idc_control);
4631 idc_control &= ~QLA83XX_IDC_GRACEFUL_RESET;
4632 __qla83xx_set_idc_control(vha, 0);
4633
4634 qla83xx_idc_unlock(vha, 0);
4635 rval = qla83xx_restart_nic_firmware(vha);
4636 qla83xx_idc_lock(vha, 0);
4637
4638 if (rval != QLA_SUCCESS) {
4639 ql_log(ql_log_fatal, vha, 0xb06a,
4640 "Failed to restart NIC f/w.\n");
4641 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_FAILED);
4642 ql_log(ql_log_info, vha, 0xb06b, "HW State: FAILED.\n");
4643 } else {
4644 ql_dbg(ql_dbg_p3p, vha, 0xb06c,
4645 "Success in restarting nic f/w.\n");
4646 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_READY);
4647 ql_log(ql_log_info, vha, 0xb06d, "HW State: READY.\n");
4648 }
4649
4650 return rval;
4651}
4652
4653/* Assumes idc_lock always held on entry */
4654int
4655qla83xx_idc_state_handler(scsi_qla_host_t *base_vha)
4656{
4657 struct qla_hw_data *ha = base_vha->hw;
4658 int rval = QLA_SUCCESS;
4659 unsigned long dev_init_timeout;
4660 uint32_t dev_state;
4661
4662 /* Wait for MAX-INIT-TIMEOUT for the device to go ready */
4663 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ);
4664
4665 while (1) {
4666
4667 if (time_after_eq(jiffies, dev_init_timeout)) {
4668 ql_log(ql_log_warn, base_vha, 0xb06e,
4669 "Initialization TIMEOUT!\n");
4670 /* Init timeout. Disable further NIC Core
4671 * communication.
4672 */
4673 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
4674 QLA8XXX_DEV_FAILED);
4675 ql_log(ql_log_info, base_vha, 0xb06f,
4676 "HW State: FAILED.\n");
4677 }
4678
4679 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4680 switch (dev_state) {
4681 case QLA8XXX_DEV_READY:
4682 if (ha->flags.nic_core_reset_owner)
4683 qla83xx_idc_audit(base_vha,
4684 IDC_AUDIT_COMPLETION);
4685 ha->flags.nic_core_reset_owner = 0;
4686 ql_dbg(ql_dbg_p3p, base_vha, 0xb070,
4687 "Reset_owner reset by 0x%x.\n",
4688 ha->portnum);
4689 goto exit;
4690 case QLA8XXX_DEV_COLD:
4691 if (ha->flags.nic_core_reset_owner)
4692 rval = qla83xx_device_bootstrap(base_vha);
4693 else {
4694 /* Wait for AEN to change device-state */
4695 qla83xx_idc_unlock(base_vha, 0);
4696 msleep(1000);
4697 qla83xx_idc_lock(base_vha, 0);
4698 }
4699 break;
4700 case QLA8XXX_DEV_INITIALIZING:
4701 /* Wait for AEN to change device-state */
4702 qla83xx_idc_unlock(base_vha, 0);
4703 msleep(1000);
4704 qla83xx_idc_lock(base_vha, 0);
4705 break;
4706 case QLA8XXX_DEV_NEED_RESET:
4707 if (!ql2xdontresethba && ha->flags.nic_core_reset_owner)
4708 qla83xx_need_reset_handler(base_vha);
4709 else {
4710 /* Wait for AEN to change device-state */
4711 qla83xx_idc_unlock(base_vha, 0);
4712 msleep(1000);
4713 qla83xx_idc_lock(base_vha, 0);
4714 }
4715 /* reset timeout value after need reset handler */
4716 dev_init_timeout = jiffies +
4717 (ha->fcoe_dev_init_timeout * HZ);
4718 break;
4719 case QLA8XXX_DEV_NEED_QUIESCENT:
4720 /* XXX: DEBUG for now */
4721 qla83xx_idc_unlock(base_vha, 0);
4722 msleep(1000);
4723 qla83xx_idc_lock(base_vha, 0);
4724 break;
4725 case QLA8XXX_DEV_QUIESCENT:
4726 /* XXX: DEBUG for now */
4727 if (ha->flags.quiesce_owner)
4728 goto exit;
4729
4730 qla83xx_idc_unlock(base_vha, 0);
4731 msleep(1000);
4732 qla83xx_idc_lock(base_vha, 0);
4733 dev_init_timeout = jiffies +
4734 (ha->fcoe_dev_init_timeout * HZ);
4735 break;
4736 case QLA8XXX_DEV_FAILED:
4737 if (ha->flags.nic_core_reset_owner)
4738 qla83xx_idc_audit(base_vha,
4739 IDC_AUDIT_COMPLETION);
4740 ha->flags.nic_core_reset_owner = 0;
4741 __qla83xx_clear_drv_presence(base_vha);
4742 qla83xx_idc_unlock(base_vha, 0);
4743 qla8xxx_dev_failed_handler(base_vha);
4744 rval = QLA_FUNCTION_FAILED;
4745 qla83xx_idc_lock(base_vha, 0);
4746 goto exit;
4747 case QLA8XXX_BAD_VALUE:
4748 qla83xx_idc_unlock(base_vha, 0);
4749 msleep(1000);
4750 qla83xx_idc_lock(base_vha, 0);
4751 break;
4752 default:
4753 ql_log(ql_log_warn, base_vha, 0xb071,
4754 "Unknow Device State: %x.\n", dev_state);
4755 qla83xx_idc_unlock(base_vha, 0);
4756 qla8xxx_dev_failed_handler(base_vha);
4757 rval = QLA_FUNCTION_FAILED;
4758 qla83xx_idc_lock(base_vha, 0);
4759 goto exit;
4760 }
4761 }
4762
4763exit:
4764 return rval;
4765}
4766
f3ddac19
CD		 4767void
4768qla2x00_disable_board_on_pci_error(struct work_struct *work)
4769{
4770 struct qla_hw_data *ha = container_of(work, struct qla_hw_data,
4771 board_disable);
4772 struct pci_dev *pdev = ha->pdev;
4773 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4774
4775 ql_log(ql_log_warn, base_vha, 0x015b,
4776 "Disabling adapter.\n");
4777
4778 set_bit(UNLOADING, &base_vha->dpc_flags);
4779
4780 qla2x00_delete_all_vps(ha, base_vha);
4781
4782 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
4783
4784 qla2x00_dfs_remove(base_vha);
4785
4786 qla84xx_put_chip(base_vha);
4787
4788 if (base_vha->timer_active)
4789 qla2x00_stop_timer(base_vha);
4790
4791 base_vha->flags.online = 0;
4792
4793 qla2x00_destroy_deferred_work(ha);
4794
4795 /*
4796 * Do not try to stop beacon blink as it will issue a mailbox
4797 * command.
4798 */
4799 qla2x00_free_sysfs_attr(base_vha, false);
4800
4801 fc_remove_host(base_vha->host);
4802
4803 scsi_remove_host(base_vha->host);
4804
4805 base_vha->flags.init_done = 0;
4806 qla25xx_delete_queues(base_vha);
4807 qla2x00_free_irqs(base_vha);
4808 qla2x00_free_fcports(base_vha);
4809 qla2x00_mem_free(ha);
4810 qla82xx_md_free(base_vha);
4811 qla2x00_free_queues(ha);
4812
f3ddac19
CD		 4813 qla2x00_unmap_iobases(ha);
4814
4815 pci_release_selected_regions(ha->pdev, ha->bars);
f3ddac19
CD		 4816 pci_disable_pcie_error_reporting(pdev);
4817 pci_disable_device(pdev);
f3ddac19 4818
beb9e315
JL		 4819 /*
4820 * Let qla2x00_remove_one cleanup qla_hw_data on device removal.
4821 */
f3ddac19
CD		 4822}
4823
1da177e4
LT		 4824/**************************************************************************
4825* qla2x00_do_dpc
4826* This kernel thread is a task that is schedule by the interrupt handler
4827* to perform the background processing for interrupts.
4828*
4829* Notes:
4830* This task always run in the context of a kernel thread. It
4831* is kick-off by the driver's detect code and starts up
4832* up one per adapter. It immediately goes to sleep and waits for
4833* some fibre event. When either the interrupt handler or
4834* the timer routine detects a event it will one of the task
4835* bits then wake us up.
4836**************************************************************************/
4837static int
4838qla2x00_do_dpc(void *data)
4839{
2c3dfe3f 4840 int rval;
e315cd28
AC		 4841 scsi_qla_host_t *base_vha;
4842 struct qla_hw_data *ha;
1da177e4 4843
e315cd28
AC		 4844 ha = (struct qla_hw_data *)data;
4845 base_vha = pci_get_drvdata(ha->pdev);
1da177e4 4846
8698a745 4847 set_user_nice(current, MIN_NICE);
1da177e4 4848
563585ec 4849 set_current_state(TASK_INTERRUPTIBLE);
39a11240 4850 while (!kthread_should_stop()) {
7c3df132
SK		 4851 ql_dbg(ql_dbg_dpc, base_vha, 0x4000,
4852 "DPC handler sleeping.\n");
1da177e4 4853
39a11240
CH		 4854 schedule();
4855 __set_current_state(TASK_RUNNING);
1da177e4 4856
c142caf0
AV		 4857 if (!base_vha->flags.init_done || ha->flags.mbox_busy)
4858 goto end_loop;
1da177e4 4859
85880801 4860 if (ha->flags.eeh_busy) {
7c3df132
SK		 4861 ql_dbg(ql_dbg_dpc, base_vha, 0x4003,
4862 "eeh_busy=%d.\n", ha->flags.eeh_busy);
c142caf0 4863 goto end_loop;
85880801
AV		 4864 }
4865
1da177e4
LT		 4866 ha->dpc_active = 1;
4867
5f28d2d7
SK		 4868 ql_dbg(ql_dbg_dpc + ql_dbg_verbose, base_vha, 0x4001,
4869 "DPC handler waking up, dpc_flags=0x%lx.\n",
4870 base_vha->dpc_flags);
1da177e4 4871
e315cd28 4872 qla2x00_do_work(base_vha);
0971de7f 4873
7ec0effd
AD		 4874 if (IS_P3P_TYPE(ha)) {
4875 if (IS_QLA8044(ha)) {
4876 if (test_and_clear_bit(ISP_UNRECOVERABLE,
4877 &base_vha->dpc_flags)) {
4878 qla8044_idc_lock(ha);
4879 qla8044_wr_direct(base_vha,
4880 QLA8044_CRB_DEV_STATE_INDEX,
4881 QLA8XXX_DEV_FAILED);
4882 qla8044_idc_unlock(ha);
4883 ql_log(ql_log_info, base_vha, 0x4004,
4884 "HW State: FAILED.\n");
4885 qla8044_device_state_handler(base_vha);
4886 continue;
4887 }
4888
4889 } else {
4890 if (test_and_clear_bit(ISP_UNRECOVERABLE,
4891 &base_vha->dpc_flags)) {
4892 qla82xx_idc_lock(ha);
4893 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
4894 QLA8XXX_DEV_FAILED);
4895 qla82xx_idc_unlock(ha);
4896 ql_log(ql_log_info, base_vha, 0x0151,
4897 "HW State: FAILED.\n");
4898 qla82xx_device_state_handler(base_vha);
4899 continue;
4900 }
a9083016
GM		 4901 }
4902
4903 if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED,
4904 &base_vha->dpc_flags)) {
4905
7c3df132
SK		 4906 ql_dbg(ql_dbg_dpc, base_vha, 0x4005,
4907 "FCoE context reset scheduled.\n");
a9083016
GM		 4908 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
4909 &base_vha->dpc_flags))) {
4910 if (qla82xx_fcoe_ctx_reset(base_vha)) {
4911 /* FCoE-ctx reset failed.
4912 * Escalate to chip-reset
4913 */
4914 set_bit(ISP_ABORT_NEEDED,
4915 &base_vha->dpc_flags);
4916 }
4917 clear_bit(ABORT_ISP_ACTIVE,
4918 &base_vha->dpc_flags);
4919 }
4920
7c3df132
SK		 4921 ql_dbg(ql_dbg_dpc, base_vha, 0x4006,
4922 "FCoE context reset end.\n");
a9083016 4923 }
8ae6d9c7
GM		 4924 } else if (IS_QLAFX00(ha)) {
4925 if (test_and_clear_bit(ISP_UNRECOVERABLE,
4926 &base_vha->dpc_flags)) {
4927 ql_dbg(ql_dbg_dpc, base_vha, 0x4020,
4928 "Firmware Reset Recovery\n");
4929 if (qlafx00_reset_initialize(base_vha)) {
4930 /* Failed. Abort isp later. */
4931 if (!test_bit(UNLOADING,
f92f82d6 4932 &base_vha->dpc_flags)) {
8ae6d9c7
GM		 4933 set_bit(ISP_UNRECOVERABLE,
4934 &base_vha->dpc_flags);
4935 ql_dbg(ql_dbg_dpc, base_vha,
4936 0x4021,
4937 "Reset Recovery Failed\n");
f92f82d6 4938 }
8ae6d9c7
GM		 4939 }
4940 }
4941
4942 if (test_and_clear_bit(FX00_TARGET_SCAN,
4943 &base_vha->dpc_flags)) {
4944 ql_dbg(ql_dbg_dpc, base_vha, 0x4022,
4945 "ISPFx00 Target Scan scheduled\n");
4946 if (qlafx00_rescan_isp(base_vha)) {
4947 if (!test_bit(UNLOADING,
4948 &base_vha->dpc_flags))
4949 set_bit(ISP_UNRECOVERABLE,
4950 &base_vha->dpc_flags);
4951 ql_dbg(ql_dbg_dpc, base_vha, 0x401e,
4952 "ISPFx00 Target Scan Failed\n");
4953 }
4954 ql_dbg(ql_dbg_dpc, base_vha, 0x401f,
4955 "ISPFx00 Target Scan End\n");
4956 }
e8f5e95d
AB		 4957 if (test_and_clear_bit(FX00_HOST_INFO_RESEND,
4958 &base_vha->dpc_flags)) {
4959 ql_dbg(ql_dbg_dpc, base_vha, 0x4023,
4960 "ISPFx00 Host Info resend scheduled\n");
4961 qlafx00_fx_disc(base_vha,
4962 &base_vha->hw->mr.fcport,
4963 FXDISC_REG_HOST_INFO);
4964 }
a9083016
GM		 4965 }
4966
e315cd28
AC		 4967 if (test_and_clear_bit(ISP_ABORT_NEEDED,
4968 &base_vha->dpc_flags)) {
1da177e4 4969
7c3df132
SK		 4970 ql_dbg(ql_dbg_dpc, base_vha, 0x4007,
4971 "ISP abort scheduled.\n");
1da177e4 4972 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
e315cd28 4973 &base_vha->dpc_flags))) {
1da177e4 4974
a9083016 4975 if (ha->isp_ops->abort_isp(base_vha)) {
1da177e4
LT		 4976 /* failed. retry later */
4977 set_bit(ISP_ABORT_NEEDED,
e315cd28 4978 &base_vha->dpc_flags);
99363ef8 4979 }
e315cd28
AC		 4980 clear_bit(ABORT_ISP_ACTIVE,
4981 &base_vha->dpc_flags);
99363ef8
SJ		 4982 }
4983
7c3df132
SK		 4984 ql_dbg(ql_dbg_dpc, base_vha, 0x4008,
4985 "ISP abort end.\n");
1da177e4
LT		 4986 }
4987
a394aac8
DJ		 4988 if (test_and_clear_bit(FCPORT_UPDATE_NEEDED,
4989 &base_vha->dpc_flags)) {
e315cd28 4990 qla2x00_update_fcports(base_vha);
c9c5ced9 4991 }
d97994dc 4992
2d70c103
NB		 4993 if (test_bit(SCR_PENDING, &base_vha->dpc_flags)) {
4994 int ret;
4995 ret = qla2x00_send_change_request(base_vha, 0x3, 0);
4996 if (ret != QLA_SUCCESS)
4997 ql_log(ql_log_warn, base_vha, 0x121,
4998 "Failed to enable receiving of RSCN "
4999 "requests: 0x%x.\n", ret);
5000 clear_bit(SCR_PENDING, &base_vha->dpc_flags);
5001 }
5002
8ae6d9c7
GM		 5003 if (IS_QLAFX00(ha))
5004 goto loop_resync_check;
5005
579d12b5 5006 if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) {
7c3df132
SK		 5007 ql_dbg(ql_dbg_dpc, base_vha, 0x4009,
5008 "Quiescence mode scheduled.\n");
7ec0effd
AD		 5009 if (IS_P3P_TYPE(ha)) {
5010 if (IS_QLA82XX(ha))
5011 qla82xx_device_state_handler(base_vha);
5012 if (IS_QLA8044(ha))
5013 qla8044_device_state_handler(base_vha);
8fcd6b8b
CD		 5014 clear_bit(ISP_QUIESCE_NEEDED,
5015 &base_vha->dpc_flags);
5016 if (!ha->flags.quiesce_owner) {
5017 qla2x00_perform_loop_resync(base_vha);
7ec0effd
AD		 5018 if (IS_QLA82XX(ha)) {
5019 qla82xx_idc_lock(ha);
5020 qla82xx_clear_qsnt_ready(
5021 base_vha);
5022 qla82xx_idc_unlock(ha);
5023 } else if (IS_QLA8044(ha)) {
5024 qla8044_idc_lock(ha);
5025 qla8044_clear_qsnt_ready(
5026 base_vha);
5027 qla8044_idc_unlock(ha);
5028 }
8fcd6b8b
CD		 5029 }
5030 } else {
5031 clear_bit(ISP_QUIESCE_NEEDED,
5032 &base_vha->dpc_flags);
5033 qla2x00_quiesce_io(base_vha);
579d12b5 5034 }
7c3df132
SK		 5035 ql_dbg(ql_dbg_dpc, base_vha, 0x400a,
5036 "Quiescence mode end.\n");
579d12b5
SK		 5037 }
5038
e315cd28 5039 if (test_and_clear_bit(RESET_MARKER_NEEDED,
8ae6d9c7 5040 &base_vha->dpc_flags) &&
e315cd28 5041 (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) {
1da177e4 5042
7c3df132
SK		 5043 ql_dbg(ql_dbg_dpc, base_vha, 0x400b,
5044 "Reset marker scheduled.\n");
e315cd28
AC		 5045 qla2x00_rst_aen(base_vha);
5046 clear_bit(RESET_ACTIVE, &base_vha->dpc_flags);
7c3df132
SK		 5047 ql_dbg(ql_dbg_dpc, base_vha, 0x400c,
5048 "Reset marker end.\n");
1da177e4
LT		 5049 }
5050
5051 /* Retry each device up to login retry count */
e315cd28
AC		 5052 if ((test_and_clear_bit(RELOGIN_NEEDED,
5053 &base_vha->dpc_flags)) &&
5054 !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) &&
5055 atomic_read(&base_vha->loop_state) != LOOP_DOWN) {
1da177e4 5056
7c3df132
SK		 5057 ql_dbg(ql_dbg_dpc, base_vha, 0x400d,
5058 "Relogin scheduled.\n");
e315cd28 5059 qla2x00_relogin(base_vha);
7c3df132
SK		 5060 ql_dbg(ql_dbg_dpc, base_vha, 0x400e,
5061 "Relogin end.\n");
1da177e4 5062 }
8ae6d9c7 5063loop_resync_check:
e315cd28 5064 if (test_and_clear_bit(LOOP_RESYNC_NEEDED,
8ae6d9c7 5065 &base_vha->dpc_flags)) {
1da177e4 5066
7c3df132
SK		 5067 ql_dbg(ql_dbg_dpc, base_vha, 0x400f,
5068 "Loop resync scheduled.\n");
1da177e4
LT		 5069
5070 if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE,
e315cd28 5071 &base_vha->dpc_flags))) {
1da177e4 5072
e315cd28 5073 rval = qla2x00_loop_resync(base_vha);
1da177e4 5074
e315cd28
AC		 5075 clear_bit(LOOP_RESYNC_ACTIVE,
5076 &base_vha->dpc_flags);
1da177e4
LT		 5077 }
5078
7c3df132
SK		 5079 ql_dbg(ql_dbg_dpc, base_vha, 0x4010,
5080 "Loop resync end.\n");
1da177e4
LT		 5081 }
5082
8ae6d9c7
GM		 5083 if (IS_QLAFX00(ha))
5084 goto intr_on_check;
5085
e315cd28
AC		 5086 if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) &&
5087 atomic_read(&base_vha->loop_state) == LOOP_READY) {
5088 clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags);
5089 qla2xxx_flash_npiv_conf(base_vha);
272976ca
AV		 5090 }
5091
8ae6d9c7 5092intr_on_check:
1da177e4 5093 if (!ha->interrupts_on)
fd34f556 5094 ha->isp_ops->enable_intrs(ha);
1da177e4 5095
e315cd28 5096 if (test_and_clear_bit(BEACON_BLINK_NEEDED,
90b604f2
HM		 5097 &base_vha->dpc_flags)) {
5098 if (ha->beacon_blink_led == 1)
5099 ha->isp_ops->beacon_blink(base_vha);
5100 }
f6df144c 5101
8ae6d9c7
GM		 5102 if (!IS_QLAFX00(ha))
5103 qla2x00_do_dpc_all_vps(base_vha);
2c3dfe3f 5104
1da177e4 5105 ha->dpc_active = 0;
c142caf0 5106end_loop:
563585ec 5107 set_current_state(TASK_INTERRUPTIBLE);
1da177e4 5108 } /* End of while(1) */
563585ec 5109 __set_current_state(TASK_RUNNING);
1da177e4 5110
7c3df132
SK		 5111 ql_dbg(ql_dbg_dpc, base_vha, 0x4011,
5112 "DPC handler exiting.\n");
1da177e4
LT		 5113
5114 /*
5115 * Make sure that nobody tries to wake us up again.
5116 */
1da177e4
LT		 5117 ha->dpc_active = 0;
5118
ac280b67
AV		 5119 /* Cleanup any residual CTX SRBs. */
5120 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
5121
39a11240
CH		 5122 return 0;
5123}
5124
5125void
e315cd28 5126qla2xxx_wake_dpc(struct scsi_qla_host *vha)
39a11240 5127{
e315cd28 5128 struct qla_hw_data *ha = vha->hw;
c795c1e4
AV		 5129 struct task_struct *t = ha->dpc_thread;
5130
e315cd28 5131 if (!test_bit(UNLOADING, &vha->dpc_flags) && t)
c795c1e4 5132 wake_up_process(t);
1da177e4
LT		 5133}
5134
1da177e4
LT		 5135/*
5136* qla2x00_rst_aen
5137* Processes asynchronous reset.
5138*
5139* Input:
5140* ha = adapter block pointer.
5141*/
5142static void
e315cd28 5143qla2x00_rst_aen(scsi_qla_host_t *vha)
1da177e4 5144{
e315cd28
AC		 5145 if (vha->flags.online && !vha->flags.reset_active &&
5146 !atomic_read(&vha->loop_down_timer) &&
5147 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) {
1da177e4 5148 do {
e315cd28 5149 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
1da177e4
LT		 5150
5151 /*
5152 * Issue marker command only when we are going to start
5153 * the I/O.
5154 */
e315cd28
AC		 5155 vha->marker_needed = 1;
5156 } while (!atomic_read(&vha->loop_down_timer) &&
5157 (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)));
1da177e4
LT		 5158 }
5159}
5160
1da177e4
LT		 5161/**************************************************************************
5162* qla2x00_timer
5163*
5164* Description:
5165* One second timer
5166*
5167* Context: Interrupt
5168***************************************************************************/
2c3dfe3f 5169void
e315cd28 5170qla2x00_timer(scsi_qla_host_t *vha)
1da177e4 5171{
1da177e4 5172 unsigned long cpu_flags = 0;
1da177e4
LT		 5173 int start_dpc = 0;
5174 int index;
5175 srb_t *sp;
85880801 5176 uint16_t w;
e315cd28 5177 struct qla_hw_data *ha = vha->hw;
73208dfd 5178 struct req_que *req;
85880801 5179
a5b36321 5180 if (ha->flags.eeh_busy) {
7c3df132
SK		 5181 ql_dbg(ql_dbg_timer, vha, 0x6000,
5182 "EEH = %d, restarting timer.\n",
5183 ha->flags.eeh_busy);
a5b36321
LC		 5184 qla2x00_restart_timer(vha, WATCH_INTERVAL);
5185 return;
5186 }
5187
f3ddac19
CD		 5188 /*
5189 * Hardware read to raise pending EEH errors during mailbox waits. If
5190 * the read returns -1 then disable the board.
5191 */
5192 if (!pci_channel_offline(ha->pdev)) {
85880801 5193 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w);
c821e0d5 5194 qla2x00_check_reg16_for_disconnect(vha, w);
f3ddac19 5195 }
1da177e4 5196
cefcaba6 5197 /* Make sure qla82xx_watchdog is run only for physical port */
7ec0effd 5198 if (!vha->vp_idx && IS_P3P_TYPE(ha)) {
579d12b5
SK		 5199 if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags))
5200 start_dpc++;
7ec0effd
AD		 5201 if (IS_QLA82XX(ha))
5202 qla82xx_watchdog(vha);
5203 else if (IS_QLA8044(ha))
5204 qla8044_watchdog(vha);
579d12b5
SK		 5205 }
5206
8ae6d9c7
GM		 5207 if (!vha->vp_idx && IS_QLAFX00(ha))
5208 qlafx00_timer_routine(vha);
5209
1da177e4 5210 /* Loop down handler. */
e315cd28 5211 if (atomic_read(&vha->loop_down_timer) > 0 &&
8f7daead
GM		 5212 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) &&
5213 !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags))
e315cd28 5214 && vha->flags.online) {
1da177e4 5215
e315cd28
AC		 5216 if (atomic_read(&vha->loop_down_timer) ==
5217 vha->loop_down_abort_time) {
1da177e4 5218
7c3df132
SK		 5219 ql_log(ql_log_info, vha, 0x6008,
5220 "Loop down - aborting the queues before time expires.\n");
1da177e4 5221
e315cd28
AC		 5222 if (!IS_QLA2100(ha) && vha->link_down_timeout)
5223 atomic_set(&vha->loop_state, LOOP_DEAD);
1da177e4 5224
f08b7251
AV		 5225 /*
5226 * Schedule an ISP abort to return any FCP2-device
5227 * commands.
5228 */
2c3dfe3f 5229 /* NPIV - scan physical port only */
e315cd28 5230 if (!vha->vp_idx) {
2c3dfe3f
SJ		 5231 spin_lock_irqsave(&ha->hardware_lock,
5232 cpu_flags);
73208dfd 5233 req = ha->req_q_map[0];
2c3dfe3f 5234 for (index = 1;
8d93f550 5235 index < req->num_outstanding_cmds;
2c3dfe3f
SJ		 5236 index++) {
5237 fc_port_t *sfcp;
5238
e315cd28 5239 sp = req->outstanding_cmds[index];
2c3dfe3f
SJ		 5240 if (!sp)
5241 continue;
9ba56b95 5242 if (sp->type != SRB_SCSI_CMD)
cf53b069 5243 continue;
2c3dfe3f 5244 sfcp = sp->fcport;
f08b7251 5245 if (!(sfcp->flags & FCF_FCP2_DEVICE))
2c3dfe3f 5246 continue;
bdf79621 5247
8f7daead
GM		 5248 if (IS_QLA82XX(ha))
5249 set_bit(FCOE_CTX_RESET_NEEDED,
5250 &vha->dpc_flags);
5251 else
5252 set_bit(ISP_ABORT_NEEDED,
e315cd28 5253 &vha->dpc_flags);
2c3dfe3f
SJ		 5254 break;
5255 }
5256 spin_unlock_irqrestore(&ha->hardware_lock,
e315cd28 5257 cpu_flags);
1da177e4 5258 }
1da177e4
LT		 5259 start_dpc++;
5260 }
5261
5262 /* if the loop has been down for 4 minutes, reinit adapter */
e315cd28 5263 if (atomic_dec_and_test(&vha->loop_down_timer) != 0) {
0d6e61bc 5264 if (!(vha->device_flags & DFLG_NO_CABLE)) {
7c3df132 5265 ql_log(ql_log_warn, vha, 0x6009,
1da177e4
LT		 5266 "Loop down - aborting ISP.\n");
5267
8f7daead
GM		 5268 if (IS_QLA82XX(ha))
5269 set_bit(FCOE_CTX_RESET_NEEDED,
5270 &vha->dpc_flags);
5271 else
5272 set_bit(ISP_ABORT_NEEDED,
5273 &vha->dpc_flags);
1da177e4
LT		 5274 }
5275 }
7c3df132
SK		 5276 ql_dbg(ql_dbg_timer, vha, 0x600a,
5277 "Loop down - seconds remaining %d.\n",
5278 atomic_read(&vha->loop_down_timer));
1da177e4 5279 }
cefcaba6
SK		 5280 /* Check if beacon LED needs to be blinked for physical host only */
5281 if (!vha->vp_idx && (ha->beacon_blink_led == 1)) {
999916dc 5282 /* There is no beacon_blink function for ISP82xx */
7ec0effd 5283 if (!IS_P3P_TYPE(ha)) {
999916dc
SK		 5284 set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags);
5285 start_dpc++;
5286 }
f6df144c 5287 }
5288
550bf57d 5289 /* Process any deferred work. */
e315cd28 5290 if (!list_empty(&vha->work_list))
550bf57d
AV		 5291 start_dpc++;
5292
1da177e4 5293 /* Schedule the DPC routine if needed */
e315cd28
AC		 5294 if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) ||
5295 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) ||
5296 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags) ||
1da177e4 5297 start_dpc ||
e315cd28
AC		 5298 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) ||
5299 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) ||
a9083016
GM		 5300 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) ||
5301 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) ||
e315cd28 5302 test_bit(VP_DPC_NEEDED, &vha->dpc_flags) ||
50280c01 5303 test_bit(RELOGIN_NEEDED, &vha->dpc_flags))) {
7c3df132
SK		 5304 ql_dbg(ql_dbg_timer, vha, 0x600b,
5305 "isp_abort_needed=%d loop_resync_needed=%d "
5306 "fcport_update_needed=%d start_dpc=%d "
5307 "reset_marker_needed=%d",
5308 test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags),
5309 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags),
5310 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags),
5311 start_dpc,
5312 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags));
5313 ql_dbg(ql_dbg_timer, vha, 0x600c,
5314 "beacon_blink_needed=%d isp_unrecoverable=%d "
5315 "fcoe_ctx_reset_needed=%d vp_dpc_needed=%d "
50280c01 5316 "relogin_needed=%d.\n",
7c3df132
SK		 5317 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags),
5318 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags),
5319 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags),
5320 test_bit(VP_DPC_NEEDED, &vha->dpc_flags),
50280c01 5321 test_bit(RELOGIN_NEEDED, &vha->dpc_flags));
e315cd28 5322 qla2xxx_wake_dpc(vha);
7c3df132 5323 }
1da177e4 5324
e315cd28 5325 qla2x00_restart_timer(vha, WATCH_INTERVAL);
1da177e4
LT		 5326}
5327
5433383e
AV		 5328/* Firmware interface routines. */
5329
f73cb695 5330#define FW_BLOBS 11
5433383e
AV		 5331#define FW_ISP21XX 0
5332#define FW_ISP22XX 1
5333#define FW_ISP2300 2
5334#define FW_ISP2322 3
48c02fde 5335#define FW_ISP24XX 4
c3a2f0df 5336#define FW_ISP25XX 5
3a03eb79 5337#define FW_ISP81XX 6
a9083016 5338#define FW_ISP82XX 7
6246b8a1
GM		 5339#define FW_ISP2031 8
5340#define FW_ISP8031 9
2c5bbbb2 5341#define FW_ISP27XX 10
5433383e 5342
bb8ee499
AV		 5343#define FW_FILE_ISP21XX "ql2100_fw.bin"
5344#define FW_FILE_ISP22XX "ql2200_fw.bin"
5345#define FW_FILE_ISP2300 "ql2300_fw.bin"
5346#define FW_FILE_ISP2322 "ql2322_fw.bin"
5347#define FW_FILE_ISP24XX "ql2400_fw.bin"
c3a2f0df 5348#define FW_FILE_ISP25XX "ql2500_fw.bin"
3a03eb79 5349#define FW_FILE_ISP81XX "ql8100_fw.bin"
a9083016 5350#define FW_FILE_ISP82XX "ql8200_fw.bin"
6246b8a1
GM		 5351#define FW_FILE_ISP2031 "ql2600_fw.bin"
5352#define FW_FILE_ISP8031 "ql8300_fw.bin"
2c5bbbb2 5353#define FW_FILE_ISP27XX "ql2700_fw.bin"
f73cb695 5354
bb8ee499 5355
e1e82b6f 5356static DEFINE_MUTEX(qla_fw_lock);
5433383e
AV		 5357
5358static struct fw_blob qla_fw_blobs[FW_BLOBS] = {
bb8ee499
AV		 5359 { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, },
5360 { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, },
5361 { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, },
5362 { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, },
5363 { .name = FW_FILE_ISP24XX, },
c3a2f0df 5364 { .name = FW_FILE_ISP25XX, },
3a03eb79 5365 { .name = FW_FILE_ISP81XX, },
a9083016 5366 { .name = FW_FILE_ISP82XX, },
6246b8a1
GM		 5367 { .name = FW_FILE_ISP2031, },
5368 { .name = FW_FILE_ISP8031, },
2c5bbbb2 5369 { .name = FW_FILE_ISP27XX, },
5433383e
AV		 5370};
5371
5372struct fw_blob *
e315cd28 5373qla2x00_request_firmware(scsi_qla_host_t *vha)
5433383e 5374{
e315cd28 5375 struct qla_hw_data *ha = vha->hw;
5433383e
AV		 5376 struct fw_blob *blob;
5377
5433383e
AV		 5378 if (IS_QLA2100(ha)) {
5379 blob = &qla_fw_blobs[FW_ISP21XX];
5380 } else if (IS_QLA2200(ha)) {
5381 blob = &qla_fw_blobs[FW_ISP22XX];
48c02fde 5382 } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
5433383e 5383 blob = &qla_fw_blobs[FW_ISP2300];
48c02fde 5384 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
5433383e 5385 blob = &qla_fw_blobs[FW_ISP2322];
4d4df193 5386 } else if (IS_QLA24XX_TYPE(ha)) {
5433383e 5387 blob = &qla_fw_blobs[FW_ISP24XX];
c3a2f0df
AV		 5388 } else if (IS_QLA25XX(ha)) {
5389 blob = &qla_fw_blobs[FW_ISP25XX];
3a03eb79
AV		 5390 } else if (IS_QLA81XX(ha)) {
5391 blob = &qla_fw_blobs[FW_ISP81XX];
a9083016
GM		 5392 } else if (IS_QLA82XX(ha)) {
5393 blob = &qla_fw_blobs[FW_ISP82XX];
6246b8a1
GM		 5394 } else if (IS_QLA2031(ha)) {
5395 blob = &qla_fw_blobs[FW_ISP2031];
5396 } else if (IS_QLA8031(ha)) {
5397 blob = &qla_fw_blobs[FW_ISP8031];
2c5bbbb2
JC		 5398 } else if (IS_QLA27XX(ha)) {
5399 blob = &qla_fw_blobs[FW_ISP27XX];
8a655229
DC		 5400 } else {
5401 return NULL;
5433383e
AV		 5402 }
5403
e1e82b6f 5404 mutex_lock(&qla_fw_lock);
5433383e
AV		 5405 if (blob->fw)
5406 goto out;
5407
5408 if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) {
7c3df132
SK		 5409 ql_log(ql_log_warn, vha, 0x0063,
5410 "Failed to load firmware image (%s).\n", blob->name);
5433383e
AV		 5411 blob->fw = NULL;
5412 blob = NULL;
5413 goto out;
5414 }
5415
5416out:
e1e82b6f 5417 mutex_unlock(&qla_fw_lock);
5433383e
AV		 5418 return blob;
5419}
5420
5421static void
5422qla2x00_release_firmware(void)
5423{
5424 int idx;
5425
e1e82b6f 5426 mutex_lock(&qla_fw_lock);
5433383e 5427 for (idx = 0; idx < FW_BLOBS; idx++)
cf92549f 5428 release_firmware(qla_fw_blobs[idx].fw);
e1e82b6f 5429 mutex_unlock(&qla_fw_lock);
5433383e
AV		 5430}
5431
14e660e6
SJ		 5432static pci_ers_result_t
5433qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
5434{
85880801
AV		 5435 scsi_qla_host_t *vha = pci_get_drvdata(pdev);
5436 struct qla_hw_data *ha = vha->hw;
5437
7c3df132
SK		 5438 ql_dbg(ql_dbg_aer, vha, 0x9000,
5439 "PCI error detected, state %x.\n", state);
b9b12f73 5440
14e660e6
SJ		 5441 switch (state) {
5442 case pci_channel_io_normal:
85880801 5443 ha->flags.eeh_busy = 0;
14e660e6
SJ		 5444 return PCI_ERS_RESULT_CAN_RECOVER;
5445 case pci_channel_io_frozen:
85880801 5446 ha->flags.eeh_busy = 1;
a5b36321
LC		 5447 /* For ISP82XX complete any pending mailbox cmd */
5448 if (IS_QLA82XX(ha)) {
7190575f 5449 ha->flags.isp82xx_fw_hung = 1;
c8f6544e
CD		 5450 ql_dbg(ql_dbg_aer, vha, 0x9001, "Pci channel io frozen\n");
5451 qla82xx_clear_pending_mbx(vha);
a5b36321 5452 }
90a86fc0 5453 qla2x00_free_irqs(vha);
14e660e6 5454 pci_disable_device(pdev);
bddd2d65
LC		 5455 /* Return back all IOs */
5456 qla2x00_abort_all_cmds(vha, DID_RESET << 16);
14e660e6
SJ		 5457 return PCI_ERS_RESULT_NEED_RESET;
5458 case pci_channel_io_perm_failure:
85880801
AV		 5459 ha->flags.pci_channel_io_perm_failure = 1;
5460 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
14e660e6
SJ		 5461 return PCI_ERS_RESULT_DISCONNECT;
5462 }
5463 return PCI_ERS_RESULT_NEED_RESET;
5464}
5465
5466static pci_ers_result_t
5467qla2xxx_pci_mmio_enabled(struct pci_dev *pdev)
5468{
5469 int risc_paused = 0;
5470 uint32_t stat;
5471 unsigned long flags;
e315cd28
AC		 5472 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
5473 struct qla_hw_data *ha = base_vha->hw;
14e660e6
SJ		 5474 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
5475 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
5476
bcc5b6d3
SK		 5477 if (IS_QLA82XX(ha))
5478 return PCI_ERS_RESULT_RECOVERED;
5479
14e660e6
SJ		 5480 spin_lock_irqsave(&ha->hardware_lock, flags);
5481 if (IS_QLA2100(ha) || IS_QLA2200(ha)){
5482 stat = RD_REG_DWORD(&reg->hccr);
5483 if (stat & HCCR_RISC_PAUSE)
5484 risc_paused = 1;
5485 } else if (IS_QLA23XX(ha)) {
5486 stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
5487 if (stat & HSR_RISC_PAUSED)
5488 risc_paused = 1;
5489 } else if (IS_FWI2_CAPABLE(ha)) {
5490 stat = RD_REG_DWORD(&reg24->host_status);
5491 if (stat & HSRX_RISC_PAUSED)
5492 risc_paused = 1;
5493 }
5494 spin_unlock_irqrestore(&ha->hardware_lock, flags);
5495
5496 if (risc_paused) {
7c3df132
SK		 5497 ql_log(ql_log_info, base_vha, 0x9003,
5498 "RISC paused -- mmio_enabled, Dumping firmware.\n");
e315cd28 5499 ha->isp_ops->fw_dump(base_vha, 0);
14e660e6
SJ		 5500
5501 return PCI_ERS_RESULT_NEED_RESET;
5502 } else
5503 return PCI_ERS_RESULT_RECOVERED;
5504}
5505
fa492630
SK		 5506static uint32_t
5507qla82xx_error_recovery(scsi_qla_host_t *base_vha)
a5b36321
LC		 5508{
5509 uint32_t rval = QLA_FUNCTION_FAILED;
5510 uint32_t drv_active = 0;
5511 struct qla_hw_data *ha = base_vha->hw;
5512 int fn;
5513 struct pci_dev *other_pdev = NULL;
5514
7c3df132
SK		 5515 ql_dbg(ql_dbg_aer, base_vha, 0x9006,
5516 "Entered %s.\n", __func__);
a5b36321
LC		 5517
5518 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
5519
5520 if (base_vha->flags.online) {
5521 /* Abort all outstanding commands,
5522 * so as to be requeued later */
5523 qla2x00_abort_isp_cleanup(base_vha);
5524 }
5525
5526
5527 fn = PCI_FUNC(ha->pdev->devfn);
5528 while (fn > 0) {
5529 fn--;
7c3df132
SK		 5530 ql_dbg(ql_dbg_aer, base_vha, 0x9007,
5531 "Finding pci device at function = 0x%x.\n", fn);
a5b36321
LC		 5532 other_pdev =
5533 pci_get_domain_bus_and_slot(pci_domain_nr(ha->pdev->bus),
5534 ha->pdev->bus->number, PCI_DEVFN(PCI_SLOT(ha->pdev->devfn),
5535 fn));
5536
5537 if (!other_pdev)
5538 continue;
5539 if (atomic_read(&other_pdev->enable_cnt)) {
7c3df132
SK		 5540 ql_dbg(ql_dbg_aer, base_vha, 0x9008,
5541 "Found PCI func available and enable at 0x%x.\n",
5542 fn);
a5b36321
LC		 5543 pci_dev_put(other_pdev);
5544 break;
5545 }
5546 pci_dev_put(other_pdev);
5547 }
5548
5549 if (!fn) {
5550 /* Reset owner */
7c3df132
SK		 5551 ql_dbg(ql_dbg_aer, base_vha, 0x9009,
5552 "This devfn is reset owner = 0x%x.\n",
5553 ha->pdev->devfn);
a5b36321
LC		 5554 qla82xx_idc_lock(ha);
5555
5556 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 5557 QLA8XXX_DEV_INITIALIZING);
a5b36321
LC		 5558
5559 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION,
5560 QLA82XX_IDC_VERSION);
5561
5562 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
7c3df132
SK		 5563 ql_dbg(ql_dbg_aer, base_vha, 0x900a,
5564 "drv_active = 0x%x.\n", drv_active);
a5b36321
LC		 5565
5566 qla82xx_idc_unlock(ha);
5567 /* Reset if device is not already reset
5568 * drv_active would be 0 if a reset has already been done
5569 */
5570 if (drv_active)
5571 rval = qla82xx_start_firmware(base_vha);
5572 else
5573 rval = QLA_SUCCESS;
5574 qla82xx_idc_lock(ha);
5575
5576 if (rval != QLA_SUCCESS) {
7c3df132
SK		 5577 ql_log(ql_log_info, base_vha, 0x900b,
5578 "HW State: FAILED.\n");
a5b36321
LC		 5579 qla82xx_clear_drv_active(ha);
5580 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 5581 QLA8XXX_DEV_FAILED);
a5b36321 5582 } else {
7c3df132
SK		 5583 ql_log(ql_log_info, base_vha, 0x900c,
5584 "HW State: READY.\n");
a5b36321 5585 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 5586 QLA8XXX_DEV_READY);
a5b36321 5587 qla82xx_idc_unlock(ha);
7190575f 5588 ha->flags.isp82xx_fw_hung = 0;
a5b36321
LC		 5589 rval = qla82xx_restart_isp(base_vha);
5590 qla82xx_idc_lock(ha);
5591 /* Clear driver state register */
5592 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, 0);
5593 qla82xx_set_drv_active(base_vha);
5594 }
5595 qla82xx_idc_unlock(ha);
5596 } else {
7c3df132
SK		 5597 ql_dbg(ql_dbg_aer, base_vha, 0x900d,
5598 "This devfn is not reset owner = 0x%x.\n",
5599 ha->pdev->devfn);
a5b36321 5600 if ((qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE) ==
7d613ac6 5601 QLA8XXX_DEV_READY)) {
7190575f 5602 ha->flags.isp82xx_fw_hung = 0;
a5b36321
LC		 5603 rval = qla82xx_restart_isp(base_vha);
5604 qla82xx_idc_lock(ha);
5605 qla82xx_set_drv_active(base_vha);
5606 qla82xx_idc_unlock(ha);
5607 }
5608 }
5609 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
5610
5611 return rval;
5612}
5613
14e660e6
SJ		 5614static pci_ers_result_t
5615qla2xxx_pci_slot_reset(struct pci_dev *pdev)
5616{
5617 pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT;
e315cd28
AC		 5618 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
5619 struct qla_hw_data *ha = base_vha->hw;
90a86fc0
JC		 5620 struct rsp_que *rsp;
5621 int rc, retries = 10;
09483916 5622
7c3df132
SK		 5623 ql_dbg(ql_dbg_aer, base_vha, 0x9004,
5624 "Slot Reset.\n");
85880801 5625
90a86fc0
JC		 5626 /* Workaround: qla2xxx driver which access hardware earlier
5627 * needs error state to be pci_channel_io_online.
5628 * Otherwise mailbox command timesout.
5629 */
5630 pdev->error_state = pci_channel_io_normal;
5631
5632 pci_restore_state(pdev);
5633
8c1496bd
RL		 5634 /* pci_restore_state() clears the saved_state flag of the device
5635 * save restored state which resets saved_state flag
5636 */
5637 pci_save_state(pdev);
5638
09483916
BH		 5639 if (ha->mem_only)
5640 rc = pci_enable_device_mem(pdev);
5641 else
5642 rc = pci_enable_device(pdev);
14e660e6 5643
09483916 5644 if (rc) {
7c3df132 5645 ql_log(ql_log_warn, base_vha, 0x9005,
14e660e6 5646 "Can't re-enable PCI device after reset.\n");
a5b36321 5647 goto exit_slot_reset;
14e660e6 5648 }
14e660e6 5649
90a86fc0
JC		 5650 rsp = ha->rsp_q_map[0];
5651 if (qla2x00_request_irqs(ha, rsp))
a5b36321 5652 goto exit_slot_reset;
90a86fc0 5653
e315cd28 5654 if (ha->isp_ops->pci_config(base_vha))
a5b36321
LC		 5655 goto exit_slot_reset;
5656
5657 if (IS_QLA82XX(ha)) {
5658 if (qla82xx_error_recovery(base_vha) == QLA_SUCCESS) {
5659 ret = PCI_ERS_RESULT_RECOVERED;
5660 goto exit_slot_reset;
5661 } else
5662 goto exit_slot_reset;
5663 }
14e660e6 5664
90a86fc0
JC		 5665 while (ha->flags.mbox_busy && retries--)
5666 msleep(1000);
85880801 5667
e315cd28 5668 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
a9083016 5669 if (ha->isp_ops->abort_isp(base_vha) == QLA_SUCCESS)
14e660e6 5670 ret = PCI_ERS_RESULT_RECOVERED;
e315cd28 5671 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
14e660e6 5672
90a86fc0 5673
a5b36321 5674exit_slot_reset:
7c3df132
SK		 5675 ql_dbg(ql_dbg_aer, base_vha, 0x900e,
5676 "slot_reset return %x.\n", ret);
85880801 5677
14e660e6
SJ		 5678 return ret;
5679}
5680
5681static void
5682qla2xxx_pci_resume(struct pci_dev *pdev)
5683{
e315cd28
AC		 5684 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
5685 struct qla_hw_data *ha = base_vha->hw;
14e660e6
SJ		 5686 int ret;
5687
7c3df132
SK		 5688 ql_dbg(ql_dbg_aer, base_vha, 0x900f,
5689 "pci_resume.\n");
85880801 5690
e315cd28 5691 ret = qla2x00_wait_for_hba_online(base_vha);
14e660e6 5692 if (ret != QLA_SUCCESS) {
7c3df132
SK		 5693 ql_log(ql_log_fatal, base_vha, 0x9002,
5694 "The device failed to resume I/O from slot/link_reset.\n");
14e660e6 5695 }
85880801 5696
3e46f031
LC		 5697 pci_cleanup_aer_uncorrect_error_status(pdev);
5698
85880801 5699 ha->flags.eeh_busy = 0;
14e660e6
SJ		 5700}
5701
a55b2d21 5702static const struct pci_error_handlers qla2xxx_err_handler = {
14e660e6
SJ		 5703 .error_detected = qla2xxx_pci_error_detected,
5704 .mmio_enabled = qla2xxx_pci_mmio_enabled,
5705 .slot_reset = qla2xxx_pci_slot_reset,
5706 .resume = qla2xxx_pci_resume,
5707};
5708
5433383e 5709static struct pci_device_id qla2xxx_pci_tbl[] = {
47f5e069
AV		 5710 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) },
5711 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) },
5712 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) },
5713 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) },
5714 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) },
5715 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) },
5716 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) },
5717 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) },
5718 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) },
4d4df193 5719 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) },
47f5e069
AV		 5720 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) },
5721 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) },
c3a2f0df 5722 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) },
6246b8a1 5723 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2031) },
3a03eb79 5724 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) },
a9083016 5725 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) },
650f528f 5726 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8031) },
8ae6d9c7 5727 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISPF001) },
7ec0effd 5728 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8044) },
f73cb695 5729 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2071) },
2c5bbbb2 5730 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2271) },
5433383e
AV		 5731 { 0 },
5732};
5733MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl);
5734
fca29703 5735static struct pci_driver qla2xxx_pci_driver = {
cb63067a 5736 .name = QLA2XXX_DRIVER_NAME,
0a21ef1e
JB		 5737 .driver = {
5738 .owner = THIS_MODULE,
5739 },
fca29703 5740 .id_table = qla2xxx_pci_tbl,
7ee61397 5741 .probe = qla2x00_probe_one,
4c993f76 5742 .remove = qla2x00_remove_one,
e30d1756 5743 .shutdown = qla2x00_shutdown,
14e660e6 5744 .err_handler = &qla2xxx_err_handler,
fca29703
AV		 5745};
5746
75ef9de1 5747static const struct file_operations apidev_fops = {
6a03b4cd 5748 .owner = THIS_MODULE,
6038f373 5749 .llseek = noop_llseek,
6a03b4cd
HZ		 5750};
5751
1da177e4
LT		 5752/**
5753 * qla2x00_module_init - Module initialization.
5754 **/
5755static int __init
5756qla2x00_module_init(void)
5757{
fca29703
AV		 5758 int ret = 0;
5759
1da177e4 5760 /* Allocate cache for SRBs. */
354d6b21 5761 srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0,
20c2df83 5762 SLAB_HWCACHE_ALIGN, NULL);
1da177e4 5763 if (srb_cachep == NULL) {
7c3df132
SK		 5764 ql_log(ql_log_fatal, NULL, 0x0001,
5765 "Unable to allocate SRB cache...Failing load!.\n");
1da177e4
LT		 5766 return -ENOMEM;
5767 }
5768
2d70c103
NB		 5769 /* Initialize target kmem_cache and mem_pools */
5770 ret = qlt_init();
5771 if (ret < 0) {
5772 kmem_cache_destroy(srb_cachep);
5773 return ret;
5774 } else if (ret > 0) {
5775 /*
5776 * If initiator mode is explictly disabled by qlt_init(),
5777 * prevent scsi_transport_fc.c:fc_scsi_scan_rport() from
5778 * performing scsi_scan_target() during LOOP UP event.
5779 */
5780 qla2xxx_transport_functions.disable_target_scan = 1;
5781 qla2xxx_transport_vport_functions.disable_target_scan = 1;
5782 }
5783
1da177e4
LT		 5784 /* Derive version string. */
5785 strcpy(qla2x00_version_str, QLA2XXX_VERSION);
11010fec 5786 if (ql2xextended_error_logging)
0181944f
AV		 5787 strcat(qla2x00_version_str, "-debug");
5788
1c97a12a
AV		 5789 qla2xxx_transport_template =
5790 fc_attach_transport(&qla2xxx_transport_functions);
2c3dfe3f
SJ		 5791 if (!qla2xxx_transport_template) {
5792 kmem_cache_destroy(srb_cachep);
7c3df132
SK		 5793 ql_log(ql_log_fatal, NULL, 0x0002,
5794 "fc_attach_transport failed...Failing load!.\n");
2d70c103 5795 qlt_exit();
1da177e4 5796 return -ENODEV;
2c3dfe3f 5797 }
6a03b4cd
HZ		 5798
5799 apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops);
5800 if (apidev_major < 0) {
7c3df132
SK		 5801 ql_log(ql_log_fatal, NULL, 0x0003,
5802 "Unable to register char device %s.\n", QLA2XXX_APIDEV);
6a03b4cd
HZ		 5803 }
5804
2c3dfe3f
SJ		 5805 qla2xxx_transport_vport_template =
5806 fc_attach_transport(&qla2xxx_transport_vport_functions);
5807 if (!qla2xxx_transport_vport_template) {
5808 kmem_cache_destroy(srb_cachep);
2d70c103 5809 qlt_exit();
2c3dfe3f 5810 fc_release_transport(qla2xxx_transport_template);
7c3df132
SK		 5811 ql_log(ql_log_fatal, NULL, 0x0004,
5812 "fc_attach_transport vport failed...Failing load!.\n");
1da177e4 5813 return -ENODEV;
2c3dfe3f 5814 }
7c3df132
SK		 5815 ql_log(ql_log_info, NULL, 0x0005,
5816 "QLogic Fibre Channel HBA Driver: %s.\n",
fd9a29f0 5817 qla2x00_version_str);
7ee61397 5818 ret = pci_register_driver(&qla2xxx_pci_driver);
fca29703
AV		 5819 if (ret) {
5820 kmem_cache_destroy(srb_cachep);
2d70c103 5821 qlt_exit();
fca29703 5822 fc_release_transport(qla2xxx_transport_template);
2c3dfe3f 5823 fc_release_transport(qla2xxx_transport_vport_template);
7c3df132
SK		 5824 ql_log(ql_log_fatal, NULL, 0x0006,
5825 "pci_register_driver failed...ret=%d Failing load!.\n",
5826 ret);
fca29703
AV		 5827 }
5828 return ret;
1da177e4
LT		 5829}
5830
5831/**
5832 * qla2x00_module_exit - Module cleanup.
5833 **/
5834static void __exit
5835qla2x00_module_exit(void)
5836{
6a03b4cd 5837 unregister_chrdev(apidev_major, QLA2XXX_APIDEV);
7ee61397 5838 pci_unregister_driver(&qla2xxx_pci_driver);
5433383e 5839 qla2x00_release_firmware();
354d6b21 5840 kmem_cache_destroy(srb_cachep);
2d70c103 5841 qlt_exit();
a9083016
GM		 5842 if (ctx_cachep)
5843 kmem_cache_destroy(ctx_cachep);
1da177e4 5844 fc_release_transport(qla2xxx_transport_template);
2c3dfe3f 5845 fc_release_transport(qla2xxx_transport_vport_template);
1da177e4
LT		 5846}
5847
5848module_init(qla2x00_module_init);
5849module_exit(qla2x00_module_exit);
5850
5851MODULE_AUTHOR("QLogic Corporation");
5852MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver");
5853MODULE_LICENSE("GPL");
5854MODULE_VERSION(QLA2XXX_VERSION);
bb8ee499
AV		 5855MODULE_FIRMWARE(FW_FILE_ISP21XX);
5856MODULE_FIRMWARE(FW_FILE_ISP22XX);
5857MODULE_FIRMWARE(FW_FILE_ISP2300);
5858MODULE_FIRMWARE(FW_FILE_ISP2322);
5859MODULE_FIRMWARE(FW_FILE_ISP24XX);
61623fc3 5860MODULE_FIRMWARE(FW_FILE_ISP25XX);
Linux 6.x block layer and io_uring tree(s)