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scsi: mvsas: replace kfree with scsi_host_put
[linux-2.6-block.git] / drivers / scsi / qla2xxx / qla_mbx.c
CommitLineData
1da177e4 1/*
fa90c54f 2 * QLogic Fibre Channel HBA Driver
bd21eaf9 3 * Copyright (c) 2003-2014 QLogic Corporation
1da177e4 4 *
fa90c54f 5 * See LICENSE.qla2xxx for copyright and licensing details.
1da177e4
LT		 6 */
7#include "qla_def.h"
2d70c103 8#include "qla_target.h"
1da177e4
LT		 9
10#include <linux/delay.h>
5a0e3ad6 11#include <linux/gfp.h>
1da177e4 12
15f30a57
QT		 13static struct mb_cmd_name {
14 uint16_t cmd;
15 const char *str;
16} mb_str[] = {
17 {MBC_GET_PORT_DATABASE, "GPDB"},
18 {MBC_GET_ID_LIST, "GIDList"},
19 {MBC_GET_LINK_PRIV_STATS, "Stats"},
20};
21
22static const char *mb_to_str(uint16_t cmd)
23{
24 int i;
25 struct mb_cmd_name *e;
26
27 for (i = 0; i < ARRAY_SIZE(mb_str); i++) {
28 e = mb_str + i;
29 if (cmd == e->cmd)
30 return e->str;
31 }
32 return "unknown";
33}
34
ca825828 35static struct rom_cmd {
77ddb94a 36 uint16_t cmd;
37} rom_cmds[] = {
38 { MBC_LOAD_RAM },
39 { MBC_EXECUTE_FIRMWARE },
40 { MBC_READ_RAM_WORD },
41 { MBC_MAILBOX_REGISTER_TEST },
42 { MBC_VERIFY_CHECKSUM },
43 { MBC_GET_FIRMWARE_VERSION },
44 { MBC_LOAD_RISC_RAM },
45 { MBC_DUMP_RISC_RAM },
46 { MBC_LOAD_RISC_RAM_EXTENDED },
47 { MBC_DUMP_RISC_RAM_EXTENDED },
48 { MBC_WRITE_RAM_WORD_EXTENDED },
49 { MBC_READ_RAM_EXTENDED },
50 { MBC_GET_RESOURCE_COUNTS },
51 { MBC_SET_FIRMWARE_OPTION },
52 { MBC_MID_INITIALIZE_FIRMWARE },
53 { MBC_GET_FIRMWARE_STATE },
54 { MBC_GET_MEM_OFFLOAD_CNTRL_STAT },
55 { MBC_GET_RETRY_COUNT },
56 { MBC_TRACE_CONTROL },
57};
58
59static int is_rom_cmd(uint16_t cmd)
60{
61 int i;
62 struct rom_cmd *wc;
63
64 for (i = 0; i < ARRAY_SIZE(rom_cmds); i++) {
65 wc = rom_cmds + i;
66 if (wc->cmd == cmd)
67 return 1;
68 }
69
70 return 0;
71}
1da177e4
LT		 72
73/*
74 * qla2x00_mailbox_command
75 * Issue mailbox command and waits for completion.
76 *
77 * Input:
78 * ha = adapter block pointer.
79 * mcp = driver internal mbx struct pointer.
80 *
81 * Output:
82 * mb[MAX_MAILBOX_REGISTER_COUNT] = returned mailbox data.
83 *
84 * Returns:
85 * 0 : QLA_SUCCESS = cmd performed success
86 * 1 : QLA_FUNCTION_FAILED (error encountered)
87 * 6 : QLA_FUNCTION_TIMEOUT (timeout condition encountered)
88 *
89 * Context:
90 * Kernel context.
91 */
92static int
7b867cf7 93qla2x00_mailbox_command(scsi_qla_host_t *vha, mbx_cmd_t *mcp)
1da177e4 94{
d14e72fb 95 int rval, i;
1da177e4 96 unsigned long flags = 0;
f73cb695 97 device_reg_t *reg;
1c7c6357 98 uint8_t abort_active;
2c3dfe3f 99 uint8_t io_lock_on;
cdbb0a4f 100 uint16_t command = 0;
1da177e4
LT		 101 uint16_t *iptr;
102 uint16_t __iomem *optr;
103 uint32_t cnt;
104 uint32_t mboxes;
d14e72fb 105 uint16_t __iomem *mbx_reg;
1da177e4 106 unsigned long wait_time;
7b867cf7
AC		 107 struct qla_hw_data *ha = vha->hw;
108 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
2c3dfe3f 109
d14e72fb 110
5e19ed90 111 ql_dbg(ql_dbg_mbx, vha, 0x1000, "Entered %s.\n", __func__);
7c3df132
SK		 112
113 if (ha->pdev->error_state > pci_channel_io_frozen) {
5e19ed90 114 ql_log(ql_log_warn, vha, 0x1001,
7c3df132
SK		 115 "error_state is greater than pci_channel_io_frozen, "
116 "exiting.\n");
b9b12f73 117 return QLA_FUNCTION_TIMEOUT;
7c3df132 118 }
b9b12f73 119
a9083016 120 if (vha->device_flags & DFLG_DEV_FAILED) {
5e19ed90 121 ql_log(ql_log_warn, vha, 0x1002,
7c3df132 122 "Device in failed state, exiting.\n");
a9083016
GM		 123 return QLA_FUNCTION_TIMEOUT;
124 }
125
c2a5d94f 126 /* if PCI error, then avoid mbx processing.*/
ba175891
SC		 127 if (test_bit(PFLG_DISCONNECTED, &base_vha->dpc_flags) &&
128 test_bit(UNLOADING, &base_vha->dpc_flags)) {
83548fe2 129 ql_log(ql_log_warn, vha, 0xd04e,
783e0dc4
SC		 130 "PCI error, exiting.\n");
131 return QLA_FUNCTION_TIMEOUT;
c2a5d94f 132 }
783e0dc4 133
2c3dfe3f 134 reg = ha->iobase;
7b867cf7 135 io_lock_on = base_vha->flags.init_done;
1da177e4
LT		 136
137 rval = QLA_SUCCESS;
7b867cf7 138 abort_active = test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1c7c6357 139
1da177e4 140
85880801 141 if (ha->flags.pci_channel_io_perm_failure) {
5e19ed90 142 ql_log(ql_log_warn, vha, 0x1003,
7c3df132 143 "Perm failure on EEH timeout MBX, exiting.\n");
85880801
AV		 144 return QLA_FUNCTION_TIMEOUT;
145 }
146
7ec0effd 147 if (IS_P3P_TYPE(ha) && ha->flags.isp82xx_fw_hung) {
862cd01e
GM		 148 /* Setting Link-Down error */
149 mcp->mb[0] = MBS_LINK_DOWN_ERROR;
5e19ed90 150 ql_log(ql_log_warn, vha, 0x1004,
7c3df132 151 "FW hung = %d.\n", ha->flags.isp82xx_fw_hung);
1806fcd5 152 return QLA_FUNCTION_TIMEOUT;
862cd01e
GM		 153 }
154
77ddb94a 155 /* check if ISP abort is active and return cmd with timeout */
156 if ((test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
157 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
158 test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) &&
159 !is_rom_cmd(mcp->mb[0])) {
160 ql_log(ql_log_info, vha, 0x1005,
161 "Cmd 0x%x aborted with timeout since ISP Abort is pending\n",
162 mcp->mb[0]);
163 return QLA_FUNCTION_TIMEOUT;
164 }
165
1da177e4 166 /*
1c7c6357
AV		 167 * Wait for active mailbox commands to finish by waiting at most tov
168 * seconds. This is to serialize actual issuing of mailbox cmds during
169 * non ISP abort time.
1da177e4 170 */
8eca3f39
AV		 171 if (!wait_for_completion_timeout(&ha->mbx_cmd_comp, mcp->tov * HZ)) {
172 /* Timeout occurred. Return error. */
83548fe2 173 ql_log(ql_log_warn, vha, 0xd035,
d8c0d546
CD		 174 "Cmd access timeout, cmd=0x%x, Exiting.\n",
175 mcp->mb[0]);
8eca3f39 176 return QLA_FUNCTION_TIMEOUT;
1da177e4
LT		 177 }
178
179 ha->flags.mbox_busy = 1;
180 /* Save mailbox command for debug */
181 ha->mcp = mcp;
182
5e19ed90 183 ql_dbg(ql_dbg_mbx, vha, 0x1006,
7c3df132 184 "Prepare to issue mbox cmd=0x%x.\n", mcp->mb[0]);
1da177e4
LT		 185
186 spin_lock_irqsave(&ha->hardware_lock, flags);
187
188 /* Load mailbox registers. */
7ec0effd 189 if (IS_P3P_TYPE(ha))
a9083016 190 optr = (uint16_t __iomem *)&reg->isp82.mailbox_in[0];
7ec0effd 191 else if (IS_FWI2_CAPABLE(ha) && !(IS_P3P_TYPE(ha)))
1c7c6357
AV		 192 optr = (uint16_t __iomem *)&reg->isp24.mailbox0;
193 else
194 optr = (uint16_t __iomem *)MAILBOX_REG(ha, &reg->isp, 0);
1da177e4
LT		 195
196 iptr = mcp->mb;
197 command = mcp->mb[0];
198 mboxes = mcp->out_mb;
199
7b711623 200 ql_dbg(ql_dbg_mbx, vha, 0x1111,
0e31a2c8 201 "Mailbox registers (OUT):\n");
1da177e4
LT		 202 for (cnt = 0; cnt < ha->mbx_count; cnt++) {
203 if (IS_QLA2200(ha) && cnt == 8)
1c7c6357
AV		 204 optr =
205 (uint16_t __iomem *)MAILBOX_REG(ha, &reg->isp, 8);
0e31a2c8
JC		 206 if (mboxes & BIT_0) {
207 ql_dbg(ql_dbg_mbx, vha, 0x1112,
208 "mbox[%d]<-0x%04x\n", cnt, *iptr);
1da177e4 209 WRT_REG_WORD(optr, *iptr);
0e31a2c8 210 }
1da177e4
LT		 211
212 mboxes >>= 1;
213 optr++;
214 iptr++;
215 }
216
5e19ed90 217 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1117,
7c3df132 218 "I/O Address = %p.\n", optr);
1da177e4
LT		 219
220 /* Issue set host interrupt command to send cmd out. */
221 ha->flags.mbox_int = 0;
222 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
223
224 /* Unlock mbx registers and wait for interrupt */
5e19ed90 225 ql_dbg(ql_dbg_mbx, vha, 0x100f,
7c3df132
SK		 226 "Going to unlock irq & waiting for interrupts. "
227 "jiffies=%lx.\n", jiffies);
1da177e4
LT		 228
229 /* Wait for mbx cmd completion until timeout */
230
124f85e6 231 if ((!abort_active && io_lock_on) || IS_NOPOLLING_TYPE(ha)) {
1da177e4
LT		 232 set_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags);
233
7ec0effd 234 if (IS_P3P_TYPE(ha)) {
a9083016
GM		 235 if (RD_REG_DWORD(&reg->isp82.hint) &
236 HINT_MBX_INT_PENDING) {
237 spin_unlock_irqrestore(&ha->hardware_lock,
238 flags);
8937f2f1 239 ha->flags.mbox_busy = 0;
5e19ed90 240 ql_dbg(ql_dbg_mbx, vha, 0x1010,
7c3df132 241 "Pending mailbox timeout, exiting.\n");
cdbb0a4f
SV		 242 rval = QLA_FUNCTION_TIMEOUT;
243 goto premature_exit;
a9083016
GM		 244 }
245 WRT_REG_DWORD(&reg->isp82.hint, HINT_MBX_INT_PENDING);
246 } else if (IS_FWI2_CAPABLE(ha))
1c7c6357
AV		 247 WRT_REG_DWORD(&reg->isp24.hccr, HCCRX_SET_HOST_INT);
248 else
249 WRT_REG_WORD(&reg->isp.hccr, HCCR_SET_HOST_INT);
1da177e4
LT		 250 spin_unlock_irqrestore(&ha->hardware_lock, flags);
251
77ddb94a 252 wait_time = jiffies;
754d1243
GM		 253 if (!wait_for_completion_timeout(&ha->mbx_intr_comp,
254 mcp->tov * HZ)) {
255 ql_dbg(ql_dbg_mbx, vha, 0x117a,
256 "cmd=%x Timeout.\n", command);
257 spin_lock_irqsave(&ha->hardware_lock, flags);
258 clear_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags);
259 spin_unlock_irqrestore(&ha->hardware_lock, flags);
260 }
77ddb94a 261 if (time_after(jiffies, wait_time + 5 * HZ))
262 ql_log(ql_log_warn, vha, 0x1015, "cmd=0x%x, waited %d msecs\n",
263 command, jiffies_to_msecs(jiffies - wait_time));
1da177e4 264 } else {
5e19ed90 265 ql_dbg(ql_dbg_mbx, vha, 0x1011,
7c3df132 266 "Cmd=%x Polling Mode.\n", command);
1da177e4 267
7ec0effd 268 if (IS_P3P_TYPE(ha)) {
a9083016
GM		 269 if (RD_REG_DWORD(&reg->isp82.hint) &
270 HINT_MBX_INT_PENDING) {
271 spin_unlock_irqrestore(&ha->hardware_lock,
272 flags);
8937f2f1 273 ha->flags.mbox_busy = 0;
5e19ed90 274 ql_dbg(ql_dbg_mbx, vha, 0x1012,
7c3df132 275 "Pending mailbox timeout, exiting.\n");
cdbb0a4f
SV		 276 rval = QLA_FUNCTION_TIMEOUT;
277 goto premature_exit;
a9083016
GM		 278 }
279 WRT_REG_DWORD(&reg->isp82.hint, HINT_MBX_INT_PENDING);
280 } else if (IS_FWI2_CAPABLE(ha))
1c7c6357
AV		 281 WRT_REG_DWORD(&reg->isp24.hccr, HCCRX_SET_HOST_INT);
282 else
283 WRT_REG_WORD(&reg->isp.hccr, HCCR_SET_HOST_INT);
1da177e4 284 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1da177e4
LT		 285
286 wait_time = jiffies + mcp->tov * HZ; /* wait at most tov secs */
287 while (!ha->flags.mbox_int) {
288 if (time_after(jiffies, wait_time))
289 break;
290
291 /* Check for pending interrupts. */
73208dfd 292 qla2x00_poll(ha->rsp_q_map[0]);
1da177e4 293
85880801
AV		 294 if (!ha->flags.mbox_int &&
295 !(IS_QLA2200(ha) &&
296 command == MBC_LOAD_RISC_RAM_EXTENDED))
59989831 297 msleep(10);
1da177e4 298 } /* while */
5e19ed90 299 ql_dbg(ql_dbg_mbx, vha, 0x1013,
7c3df132
SK		 300 "Waited %d sec.\n",
301 (uint)((jiffies - (wait_time - (mcp->tov * HZ)))/HZ));
1da177e4
LT		 302 }
303
1da177e4
LT		 304 /* Check whether we timed out */
305 if (ha->flags.mbox_int) {
306 uint16_t *iptr2;
307
5e19ed90 308 ql_dbg(ql_dbg_mbx, vha, 0x1014,
7c3df132 309 "Cmd=%x completed.\n", command);
1da177e4
LT		 310
311 /* Got interrupt. Clear the flag. */
312 ha->flags.mbox_int = 0;
313 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
314
7ec0effd 315 if (IS_P3P_TYPE(ha) && ha->flags.isp82xx_fw_hung) {
cdbb0a4f
SV		 316 ha->flags.mbox_busy = 0;
317 /* Setting Link-Down error */
318 mcp->mb[0] = MBS_LINK_DOWN_ERROR;
319 ha->mcp = NULL;
320 rval = QLA_FUNCTION_FAILED;
83548fe2 321 ql_log(ql_log_warn, vha, 0xd048,
7c3df132 322 "FW hung = %d.\n", ha->flags.isp82xx_fw_hung);
cdbb0a4f
SV		 323 goto premature_exit;
324 }
325
354d6b21 326 if (ha->mailbox_out[0] != MBS_COMMAND_COMPLETE)
1da177e4 327 rval = QLA_FUNCTION_FAILED;
1da177e4
LT		 328
329 /* Load return mailbox registers. */
330 iptr2 = mcp->mb;
331 iptr = (uint16_t *)&ha->mailbox_out[0];
332 mboxes = mcp->in_mb;
0e31a2c8
JC		 333
334 ql_dbg(ql_dbg_mbx, vha, 0x1113,
335 "Mailbox registers (IN):\n");
1da177e4 336 for (cnt = 0; cnt < ha->mbx_count; cnt++) {
0e31a2c8 337 if (mboxes & BIT_0) {
1da177e4 338 *iptr2 = *iptr;
0e31a2c8
JC		 339 ql_dbg(ql_dbg_mbx, vha, 0x1114,
340 "mbox[%d]->0x%04x\n", cnt, *iptr2);
341 }
1da177e4
LT		 342
343 mboxes >>= 1;
344 iptr2++;
345 iptr++;
346 }
347 } else {
348
8d3c9c23
QT		 349 uint16_t mb[8];
350 uint32_t ictrl, host_status, hccr;
783e0dc4 351 uint16_t w;
1c7c6357 352
e428924c 353 if (IS_FWI2_CAPABLE(ha)) {
8d3c9c23
QT		 354 mb[0] = RD_REG_WORD(&reg->isp24.mailbox0);
355 mb[1] = RD_REG_WORD(&reg->isp24.mailbox1);
356 mb[2] = RD_REG_WORD(&reg->isp24.mailbox2);
357 mb[3] = RD_REG_WORD(&reg->isp24.mailbox3);
358 mb[7] = RD_REG_WORD(&reg->isp24.mailbox7);
1c7c6357 359 ictrl = RD_REG_DWORD(&reg->isp24.ictrl);
8d3c9c23
QT		 360 host_status = RD_REG_DWORD(&reg->isp24.host_status);
361 hccr = RD_REG_DWORD(&reg->isp24.hccr);
362
83548fe2 363 ql_log(ql_log_warn, vha, 0xd04c,
8d3c9c23
QT		 364 "MBX Command timeout for cmd %x, iocontrol=%x jiffies=%lx "
365 "mb[0-3]=[0x%x 0x%x 0x%x 0x%x] mb7 0x%x host_status 0x%x hccr 0x%x\n",
366 command, ictrl, jiffies, mb[0], mb[1], mb[2], mb[3],
367 mb[7], host_status, hccr);
368
1c7c6357 369 } else {
8d3c9c23 370 mb[0] = RD_MAILBOX_REG(ha, &reg->isp, 0);
1c7c6357 371 ictrl = RD_REG_WORD(&reg->isp.ictrl);
8d3c9c23
QT		 372 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1119,
373 "MBX Command timeout for cmd %x, iocontrol=%x jiffies=%lx "
374 "mb[0]=0x%x\n", command, ictrl, jiffies, mb[0]);
1c7c6357 375 }
5e19ed90 376 ql_dump_regs(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1019);
1da177e4 377
783e0dc4
SC		 378 /* Capture FW dump only, if PCI device active */
379 if (!pci_channel_offline(vha->hw->pdev)) {
380 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w);
381 if (w == 0xffff || ictrl == 0xffffffff) {
382 /* This is special case if there is unload
383 * of driver happening and if PCI device go
384 * into bad state due to PCI error condition
385 * then only PCI ERR flag would be set.
386 * we will do premature exit for above case.
387 */
783e0dc4
SC		 388 ha->flags.mbox_busy = 0;
389 rval = QLA_FUNCTION_TIMEOUT;
390 goto premature_exit;
391 }
f55bfc88 392
783e0dc4
SC		 393 /* Attempt to capture firmware dump for further
394 * anallysis of the current formware state. we do not
395 * need to do this if we are intentionally generating
396 * a dump
397 */
398 if (mcp->mb[0] != MBC_GEN_SYSTEM_ERROR)
399 ha->isp_ops->fw_dump(vha, 0);
400 rval = QLA_FUNCTION_TIMEOUT;
401 }
1da177e4
LT		 402 }
403
1da177e4
LT		 404 ha->flags.mbox_busy = 0;
405
406 /* Clean up */
407 ha->mcp = NULL;
408
124f85e6 409 if ((abort_active || !io_lock_on) && !IS_NOPOLLING_TYPE(ha)) {
5e19ed90 410 ql_dbg(ql_dbg_mbx, vha, 0x101a,
7c3df132 411 "Checking for additional resp interrupt.\n");
1da177e4
LT		 412
413 /* polling mode for non isp_abort commands. */
73208dfd 414 qla2x00_poll(ha->rsp_q_map[0]);
1da177e4
LT		 415 }
416
1c7c6357
AV		 417 if (rval == QLA_FUNCTION_TIMEOUT &&
418 mcp->mb[0] != MBC_GEN_SYSTEM_ERROR) {
85880801
AV		 419 if (!io_lock_on || (mcp->flags & IOCTL_CMD) ||
420 ha->flags.eeh_busy) {
1da177e4 421 /* not in dpc. schedule it for dpc to take over. */
5e19ed90 422 ql_dbg(ql_dbg_mbx, vha, 0x101b,
7c3df132 423 "Timeout, schedule isp_abort_needed.\n");
cdbb0a4f
SV		 424
425 if (!test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) &&
426 !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) &&
427 !test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
63154916
GM		 428 if (IS_QLA82XX(ha)) {
429 ql_dbg(ql_dbg_mbx, vha, 0x112a,
430 "disabling pause transmit on port "
431 "0 & 1.\n");
432 qla82xx_wr_32(ha,
433 QLA82XX_CRB_NIU + 0x98,
434 CRB_NIU_XG_PAUSE_CTL_P0|
435 CRB_NIU_XG_PAUSE_CTL_P1);
436 }
7c3df132 437 ql_log(ql_log_info, base_vha, 0x101c,
24d9ee85 438 "Mailbox cmd timeout occurred, cmd=0x%x, "
d8c0d546
CD		 439 "mb[0]=0x%x, eeh_busy=0x%x. Scheduling ISP "
440 "abort.\n", command, mcp->mb[0],
441 ha->flags.eeh_busy);
cdbb0a4f
SV		 442 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
443 qla2xxx_wake_dpc(vha);
444 }
1da177e4 445 } else if (!abort_active) {
1da177e4 446 /* call abort directly since we are in the DPC thread */
5e19ed90 447 ql_dbg(ql_dbg_mbx, vha, 0x101d,
7c3df132 448 "Timeout, calling abort_isp.\n");
cdbb0a4f
SV		 449
450 if (!test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) &&
451 !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) &&
452 !test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
63154916
GM		 453 if (IS_QLA82XX(ha)) {
454 ql_dbg(ql_dbg_mbx, vha, 0x112b,
455 "disabling pause transmit on port "
456 "0 & 1.\n");
457 qla82xx_wr_32(ha,
458 QLA82XX_CRB_NIU + 0x98,
459 CRB_NIU_XG_PAUSE_CTL_P0|
460 CRB_NIU_XG_PAUSE_CTL_P1);
461 }
7c3df132 462 ql_log(ql_log_info, base_vha, 0x101e,
24d9ee85 463 "Mailbox cmd timeout occurred, cmd=0x%x, "
d8c0d546
CD		 464 "mb[0]=0x%x. Scheduling ISP abort ",
465 command, mcp->mb[0]);
cdbb0a4f
SV		 466 set_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags);
467 clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
d3360960
GM		 468 /* Allow next mbx cmd to come in. */
469 complete(&ha->mbx_cmd_comp);
cdbb0a4f
SV		 470 if (ha->isp_ops->abort_isp(vha)) {
471 /* Failed. retry later. */
472 set_bit(ISP_ABORT_NEEDED,
473 &vha->dpc_flags);
474 }
475 clear_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags);
5e19ed90 476 ql_dbg(ql_dbg_mbx, vha, 0x101f,
7c3df132 477 "Finished abort_isp.\n");
d3360960 478 goto mbx_done;
1da177e4 479 }
1da177e4
LT		 480 }
481 }
482
cdbb0a4f 483premature_exit:
1da177e4 484 /* Allow next mbx cmd to come in. */
8eca3f39 485 complete(&ha->mbx_cmd_comp);
1da177e4 486
d3360960 487mbx_done:
1da177e4 488 if (rval) {
34c5801d 489 ql_dbg(ql_dbg_disc, base_vha, 0x1020,
6246b8a1
GM		 490 "**** Failed mbx[0]=%x, mb[1]=%x, mb[2]=%x, mb[3]=%x, cmd=%x ****.\n",
491 mcp->mb[0], mcp->mb[1], mcp->mb[2], mcp->mb[3], command);
d14e72fb 492
75d560e0 493 ql_dbg(ql_dbg_mbx, vha, 0x1198,
d14e72fb
HM		 494 "host status: 0x%x, flags:0x%lx, intr ctrl reg:0x%x, intr status:0x%x\n",
495 RD_REG_DWORD(&reg->isp24.host_status),
496 ha->fw_dump_cap_flags,
497 RD_REG_DWORD(&reg->isp24.ictrl),
498 RD_REG_DWORD(&reg->isp24.istatus));
499
500 mbx_reg = &reg->isp24.mailbox0;
501 for (i = 0; i < 6; i++)
75d560e0 502 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1199,
d14e72fb 503 "mbox[%d] 0x%04x\n", i, RD_REG_WORD(mbx_reg++));
1da177e4 504 } else {
7c3df132 505 ql_dbg(ql_dbg_mbx, base_vha, 0x1021, "Done %s.\n", __func__);
1da177e4
LT		 506 }
507
1da177e4
LT		 508 return rval;
509}
510
1da177e4 511int
7b867cf7 512qla2x00_load_ram(scsi_qla_host_t *vha, dma_addr_t req_dma, uint32_t risc_addr,
590f98e5 513 uint32_t risc_code_size)
1da177e4
LT		 514{
515 int rval;
7b867cf7 516 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 517 mbx_cmd_t mc;
518 mbx_cmd_t *mcp = &mc;
1da177e4 519
5f28d2d7
SK		 520 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1022,
521 "Entered %s.\n", __func__);
1da177e4 522
e428924c 523 if (MSW(risc_addr) || IS_FWI2_CAPABLE(ha)) {
590f98e5 524 mcp->mb[0] = MBC_LOAD_RISC_RAM_EXTENDED;
525 mcp->mb[8] = MSW(risc_addr);
526 mcp->out_mb = MBX_8|MBX_0;
1da177e4 527 } else {
590f98e5 528 mcp->mb[0] = MBC_LOAD_RISC_RAM;
529 mcp->out_mb = MBX_0;
1da177e4 530 }
1da177e4
LT		 531 mcp->mb[1] = LSW(risc_addr);
532 mcp->mb[2] = MSW(req_dma);
533 mcp->mb[3] = LSW(req_dma);
1da177e4
LT		 534 mcp->mb[6] = MSW(MSD(req_dma));
535 mcp->mb[7] = LSW(MSD(req_dma));
590f98e5 536 mcp->out_mb |= MBX_7|MBX_6|MBX_3|MBX_2|MBX_1;
e428924c 537 if (IS_FWI2_CAPABLE(ha)) {
1c7c6357
AV		 538 mcp->mb[4] = MSW(risc_code_size);
539 mcp->mb[5] = LSW(risc_code_size);
540 mcp->out_mb |= MBX_5|MBX_4;
541 } else {
542 mcp->mb[4] = LSW(risc_code_size);
543 mcp->out_mb |= MBX_4;
544 }
545
1da177e4 546 mcp->in_mb = MBX_0;
b93480e3 547 mcp->tov = MBX_TOV_SECONDS;
1da177e4 548 mcp->flags = 0;
7b867cf7 549 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4 550
1da177e4 551 if (rval != QLA_SUCCESS) {
7c3df132
SK		 552 ql_dbg(ql_dbg_mbx, vha, 0x1023,
553 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
1da177e4 554 } else {
5f28d2d7
SK		 555 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1024,
556 "Done %s.\n", __func__);
1da177e4
LT		 557 }
558
559 return rval;
560}
561
cad454b1 562#define EXTENDED_BB_CREDITS BIT_0
e84067d7
DG		 563#define NVME_ENABLE_FLAG BIT_3
564
1da177e4
LT		 565/*
566 * qla2x00_execute_fw
1c7c6357 567 * Start adapter firmware.
1da177e4
LT		 568 *
569 * Input:
1c7c6357
AV		 570 * ha = adapter block pointer.
571 * TARGET_QUEUE_LOCK must be released.
572 * ADAPTER_STATE_LOCK must be released.
1da177e4
LT		 573 *
574 * Returns:
1c7c6357 575 * qla2x00 local function return status code.
1da177e4
LT		 576 *
577 * Context:
1c7c6357 578 * Kernel context.
1da177e4
LT		 579 */
580int
7b867cf7 581qla2x00_execute_fw(scsi_qla_host_t *vha, uint32_t risc_addr)
1da177e4
LT		 582{
583 int rval;
7b867cf7 584 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 585 mbx_cmd_t mc;
586 mbx_cmd_t *mcp = &mc;
587
5f28d2d7
SK		 588 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1025,
589 "Entered %s.\n", __func__);
1da177e4
LT		 590
591 mcp->mb[0] = MBC_EXECUTE_FIRMWARE;
1c7c6357
AV		 592 mcp->out_mb = MBX_0;
593 mcp->in_mb = MBX_0;
e428924c 594 if (IS_FWI2_CAPABLE(ha)) {
1c7c6357
AV		 595 mcp->mb[1] = MSW(risc_addr);
596 mcp->mb[2] = LSW(risc_addr);
597 mcp->mb[3] = 0;
f73cb695
CD		 598 if (IS_QLA25XX(ha) || IS_QLA81XX(ha) || IS_QLA83XX(ha) ||
599 IS_QLA27XX(ha)) {
cad454b1
SV		 600 struct nvram_81xx *nv = ha->nvram;
601 mcp->mb[4] = (nv->enhanced_features &
602 EXTENDED_BB_CREDITS);
603 } else
604 mcp->mb[4] = 0;
b0d6cabd 605
e84067d7
DG		 606 if (ql2xnvmeenable && IS_QLA27XX(ha))
607 mcp->mb[4] |= NVME_ENABLE_FLAG;
608
b0d6cabd
HM		 609 if (ha->flags.exlogins_enabled)
610 mcp->mb[4] |= ENABLE_EXTENDED_LOGIN;
611
2f56a7f1
HM		 612 if (ha->flags.exchoffld_enabled)
613 mcp->mb[4] |= ENABLE_EXCHANGE_OFFLD;
614
8b3253d1 615 mcp->out_mb |= MBX_4|MBX_3|MBX_2|MBX_1;
1c7c6357
AV		 616 mcp->in_mb |= MBX_1;
617 } else {
618 mcp->mb[1] = LSW(risc_addr);
619 mcp->out_mb |= MBX_1;
620 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
621 mcp->mb[2] = 0;
622 mcp->out_mb |= MBX_2;
623 }
1da177e4
LT		 624 }
625
b93480e3 626 mcp->tov = MBX_TOV_SECONDS;
1da177e4 627 mcp->flags = 0;
7b867cf7 628 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4 629
1c7c6357 630 if (rval != QLA_SUCCESS) {
7c3df132
SK		 631 ql_dbg(ql_dbg_mbx, vha, 0x1026,
632 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
1c7c6357 633 } else {
e428924c 634 if (IS_FWI2_CAPABLE(ha)) {
5f28d2d7 635 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1027,
7c3df132 636 "Done exchanges=%x.\n", mcp->mb[1]);
1c7c6357 637 } else {
5f28d2d7
SK		 638 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1028,
639 "Done %s.\n", __func__);
1c7c6357
AV		 640 }
641 }
1da177e4
LT		 642
643 return rval;
644}
645
b0d6cabd
HM		 646/*
647 * qla_get_exlogin_status
648 * Get extended login status
649 * uses the memory offload control/status Mailbox
650 *
651 * Input:
652 * ha: adapter state pointer.
653 * fwopt: firmware options
654 *
655 * Returns:
656 * qla2x00 local function status
657 *
658 * Context:
659 * Kernel context.
660 */
661#define FETCH_XLOGINS_STAT 0x8
662int
663qla_get_exlogin_status(scsi_qla_host_t *vha, uint16_t *buf_sz,
664 uint16_t *ex_logins_cnt)
665{
666 int rval;
667 mbx_cmd_t mc;
668 mbx_cmd_t *mcp = &mc;
669
670 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x118f,
671 "Entered %s\n", __func__);
672
673 memset(mcp->mb, 0 , sizeof(mcp->mb));
674 mcp->mb[0] = MBC_GET_MEM_OFFLOAD_CNTRL_STAT;
675 mcp->mb[1] = FETCH_XLOGINS_STAT;
676 mcp->out_mb = MBX_1|MBX_0;
677 mcp->in_mb = MBX_10|MBX_4|MBX_0;
678 mcp->tov = MBX_TOV_SECONDS;
679 mcp->flags = 0;
680
681 rval = qla2x00_mailbox_command(vha, mcp);
682 if (rval != QLA_SUCCESS) {
683 ql_dbg(ql_dbg_mbx, vha, 0x1115, "Failed=%x.\n", rval);
684 } else {
685 *buf_sz = mcp->mb[4];
686 *ex_logins_cnt = mcp->mb[10];
687
688 ql_log(ql_log_info, vha, 0x1190,
689 "buffer size 0x%x, exchange login count=%d\n",
690 mcp->mb[4], mcp->mb[10]);
691
692 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1116,
693 "Done %s.\n", __func__);
694 }
695
696 return rval;
697}
698
699/*
700 * qla_set_exlogin_mem_cfg
701 * set extended login memory configuration
702 * Mbx needs to be issues before init_cb is set
703 *
704 * Input:
705 * ha: adapter state pointer.
706 * buffer: buffer pointer
707 * phys_addr: physical address of buffer
708 * size: size of buffer
709 * TARGET_QUEUE_LOCK must be released
710 * ADAPTER_STATE_LOCK must be release
711 *
712 * Returns:
713 * qla2x00 local funxtion status code.
714 *
715 * Context:
716 * Kernel context.
717 */
718#define CONFIG_XLOGINS_MEM 0x3
719int
720qla_set_exlogin_mem_cfg(scsi_qla_host_t *vha, dma_addr_t phys_addr)
721{
722 int rval;
723 mbx_cmd_t mc;
724 mbx_cmd_t *mcp = &mc;
725 struct qla_hw_data *ha = vha->hw;
b0d6cabd
HM		 726
727 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x111a,
728 "Entered %s.\n", __func__);
729
730 memset(mcp->mb, 0 , sizeof(mcp->mb));
731 mcp->mb[0] = MBC_GET_MEM_OFFLOAD_CNTRL_STAT;
732 mcp->mb[1] = CONFIG_XLOGINS_MEM;
733 mcp->mb[2] = MSW(phys_addr);
734 mcp->mb[3] = LSW(phys_addr);
735 mcp->mb[6] = MSW(MSD(phys_addr));
736 mcp->mb[7] = LSW(MSD(phys_addr));
737 mcp->mb[8] = MSW(ha->exlogin_size);
738 mcp->mb[9] = LSW(ha->exlogin_size);
739 mcp->out_mb = MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
740 mcp->in_mb = MBX_11|MBX_0;
741 mcp->tov = MBX_TOV_SECONDS;
742 mcp->flags = 0;
743 rval = qla2x00_mailbox_command(vha, mcp);
744 if (rval != QLA_SUCCESS) {
745 /*EMPTY*/
746 ql_dbg(ql_dbg_mbx, vha, 0x111b, "Failed=%x.\n", rval);
747 } else {
b0d6cabd
HM		 748 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x118c,
749 "Done %s.\n", __func__);
750 }
751
752 return rval;
753}
754
2f56a7f1
HM		 755/*
756 * qla_get_exchoffld_status
757 * Get exchange offload status
758 * uses the memory offload control/status Mailbox
759 *
760 * Input:
761 * ha: adapter state pointer.
762 * fwopt: firmware options
763 *
764 * Returns:
765 * qla2x00 local function status
766 *
767 * Context:
768 * Kernel context.
769 */
770#define FETCH_XCHOFFLD_STAT 0x2
771int
772qla_get_exchoffld_status(scsi_qla_host_t *vha, uint16_t *buf_sz,
773 uint16_t *ex_logins_cnt)
774{
775 int rval;
776 mbx_cmd_t mc;
777 mbx_cmd_t *mcp = &mc;
778
779 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1019,
780 "Entered %s\n", __func__);
781
782 memset(mcp->mb, 0 , sizeof(mcp->mb));
783 mcp->mb[0] = MBC_GET_MEM_OFFLOAD_CNTRL_STAT;
784 mcp->mb[1] = FETCH_XCHOFFLD_STAT;
785 mcp->out_mb = MBX_1|MBX_0;
786 mcp->in_mb = MBX_10|MBX_4|MBX_0;
787 mcp->tov = MBX_TOV_SECONDS;
788 mcp->flags = 0;
789
790 rval = qla2x00_mailbox_command(vha, mcp);
791 if (rval != QLA_SUCCESS) {
792 ql_dbg(ql_dbg_mbx, vha, 0x1155, "Failed=%x.\n", rval);
793 } else {
794 *buf_sz = mcp->mb[4];
795 *ex_logins_cnt = mcp->mb[10];
796
797 ql_log(ql_log_info, vha, 0x118e,
798 "buffer size 0x%x, exchange offload count=%d\n",
799 mcp->mb[4], mcp->mb[10]);
800
801 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1156,
802 "Done %s.\n", __func__);
803 }
804
805 return rval;
806}
807
808/*
809 * qla_set_exchoffld_mem_cfg
810 * Set exchange offload memory configuration
811 * Mbx needs to be issues before init_cb is set
812 *
813 * Input:
814 * ha: adapter state pointer.
815 * buffer: buffer pointer
816 * phys_addr: physical address of buffer
817 * size: size of buffer
818 * TARGET_QUEUE_LOCK must be released
819 * ADAPTER_STATE_LOCK must be release
820 *
821 * Returns:
822 * qla2x00 local funxtion status code.
823 *
824 * Context:
825 * Kernel context.
826 */
827#define CONFIG_XCHOFFLD_MEM 0x3
828int
99e1b683 829qla_set_exchoffld_mem_cfg(scsi_qla_host_t *vha)
2f56a7f1
HM		 830{
831 int rval;
832 mbx_cmd_t mc;
833 mbx_cmd_t *mcp = &mc;
834 struct qla_hw_data *ha = vha->hw;
835
836 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1157,
837 "Entered %s.\n", __func__);
838
839 memset(mcp->mb, 0 , sizeof(mcp->mb));
840 mcp->mb[0] = MBC_GET_MEM_OFFLOAD_CNTRL_STAT;
841 mcp->mb[1] = CONFIG_XCHOFFLD_MEM;
99e1b683
QT		 842 mcp->mb[2] = MSW(ha->exchoffld_buf_dma);
843 mcp->mb[3] = LSW(ha->exchoffld_buf_dma);
844 mcp->mb[6] = MSW(MSD(ha->exchoffld_buf_dma));
845 mcp->mb[7] = LSW(MSD(ha->exchoffld_buf_dma));
846 mcp->mb[8] = MSW(ha->exchoffld_size);
847 mcp->mb[9] = LSW(ha->exchoffld_size);
2f56a7f1
HM		 848 mcp->out_mb = MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
849 mcp->in_mb = MBX_11|MBX_0;
850 mcp->tov = MBX_TOV_SECONDS;
851 mcp->flags = 0;
852 rval = qla2x00_mailbox_command(vha, mcp);
853 if (rval != QLA_SUCCESS) {
854 /*EMPTY*/
855 ql_dbg(ql_dbg_mbx, vha, 0x1158, "Failed=%x.\n", rval);
856 } else {
857 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1192,
858 "Done %s.\n", __func__);
859 }
860
861 return rval;
862}
863
1da177e4
LT		 864/*
865 * qla2x00_get_fw_version
866 * Get firmware version.
867 *
868 * Input:
869 * ha: adapter state pointer.
870 * major: pointer for major number.
871 * minor: pointer for minor number.
872 * subminor: pointer for subminor number.
873 *
874 * Returns:
875 * qla2x00 local function return status code.
876 *
877 * Context:
878 * Kernel context.
879 */
ca9e9c3e 880int
6246b8a1 881qla2x00_get_fw_version(scsi_qla_host_t *vha)
1da177e4
LT		 882{
883 int rval;
884 mbx_cmd_t mc;
885 mbx_cmd_t *mcp = &mc;
6246b8a1 886 struct qla_hw_data *ha = vha->hw;
1da177e4 887
5f28d2d7
SK		 888 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1029,
889 "Entered %s.\n", __func__);
1da177e4
LT		 890
891 mcp->mb[0] = MBC_GET_FIRMWARE_VERSION;
892 mcp->out_mb = MBX_0;
893 mcp->in_mb = MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
7ec0effd 894 if (IS_QLA81XX(vha->hw) || IS_QLA8031(ha) || IS_QLA8044(ha))
55a96158 895 mcp->in_mb |= MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8;
fb0effee 896 if (IS_FWI2_CAPABLE(ha))
6246b8a1 897 mcp->in_mb |= MBX_17|MBX_16|MBX_15;
f73cb695 898 if (IS_QLA27XX(ha))
ad1ef177
JC		 899 mcp->in_mb |=
900 MBX_25|MBX_24|MBX_23|MBX_22|MBX_21|MBX_20|MBX_19|MBX_18|
901 MBX_14|MBX_13|MBX_11|MBX_10|MBX_9|MBX_8;
03aa868c 902
1da177e4 903 mcp->flags = 0;
b93480e3 904 mcp->tov = MBX_TOV_SECONDS;
7b867cf7 905 rval = qla2x00_mailbox_command(vha, mcp);
ca9e9c3e
AV		 906 if (rval != QLA_SUCCESS)
907 goto failed;
1da177e4
LT		 908
909 /* Return mailbox data. */
6246b8a1
GM		 910 ha->fw_major_version = mcp->mb[1];
911 ha->fw_minor_version = mcp->mb[2];
912 ha->fw_subminor_version = mcp->mb[3];
913 ha->fw_attributes = mcp->mb[6];
7b867cf7 914 if (IS_QLA2100(vha->hw) || IS_QLA2200(vha->hw))
6246b8a1 915 ha->fw_memory_size = 0x1FFFF; /* Defaults to 128KB. */
1da177e4 916 else
6246b8a1 917 ha->fw_memory_size = (mcp->mb[5] << 16) | mcp->mb[4];
03aa868c 918
7ec0effd 919 if (IS_QLA81XX(vha->hw) || IS_QLA8031(vha->hw) || IS_QLA8044(ha)) {
6246b8a1
GM		 920 ha->mpi_version[0] = mcp->mb[10] & 0xff;
921 ha->mpi_version[1] = mcp->mb[11] >> 8;
922 ha->mpi_version[2] = mcp->mb[11] & 0xff;
923 ha->mpi_capabilities = (mcp->mb[12] << 16) | mcp->mb[13];
924 ha->phy_version[0] = mcp->mb[8] & 0xff;
925 ha->phy_version[1] = mcp->mb[9] >> 8;
926 ha->phy_version[2] = mcp->mb[9] & 0xff;
927 }
03aa868c 928
81178772
SK		 929 if (IS_FWI2_CAPABLE(ha)) {
930 ha->fw_attributes_h = mcp->mb[15];
931 ha->fw_attributes_ext[0] = mcp->mb[16];
932 ha->fw_attributes_ext[1] = mcp->mb[17];
933 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1139,
934 "%s: FW_attributes Upper: 0x%x, Lower: 0x%x.\n",
935 __func__, mcp->mb[15], mcp->mb[6]);
936 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x112f,
937 "%s: Ext_FwAttributes Upper: 0x%x, Lower: 0x%x.\n",
938 __func__, mcp->mb[17], mcp->mb[16]);
2f56a7f1 939
b0d6cabd
HM		 940 if (ha->fw_attributes_h & 0x4)
941 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x118d,
942 "%s: Firmware supports Extended Login 0x%x\n",
943 __func__, ha->fw_attributes_h);
2f56a7f1
HM		 944
945 if (ha->fw_attributes_h & 0x8)
946 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1191,
947 "%s: Firmware supports Exchange Offload 0x%x\n",
948 __func__, ha->fw_attributes_h);
e84067d7 949
deeae7a6
DG		 950 /*
951 * FW supports nvme and driver load parameter requested nvme.
952 * BIT 26 of fw_attributes indicates NVMe support.
953 */
954 if ((ha->fw_attributes_h & 0x400) && ql2xnvmeenable)
e84067d7 955 vha->flags.nvme_enabled = 1;
e84067d7 956
3a03eb79 957 }
03aa868c 958
f73cb695 959 if (IS_QLA27XX(ha)) {
03aa868c
SC		 960 ha->mpi_version[0] = mcp->mb[10] & 0xff;
961 ha->mpi_version[1] = mcp->mb[11] >> 8;
962 ha->mpi_version[2] = mcp->mb[11] & 0xff;
963 ha->pep_version[0] = mcp->mb[13] & 0xff;
964 ha->pep_version[1] = mcp->mb[14] >> 8;
965 ha->pep_version[2] = mcp->mb[14] & 0xff;
f73cb695
CD		 966 ha->fw_shared_ram_start = (mcp->mb[19] << 16) | mcp->mb[18];
967 ha->fw_shared_ram_end = (mcp->mb[21] << 16) | mcp->mb[20];
ad1ef177
JC		 968 ha->fw_ddr_ram_start = (mcp->mb[23] << 16) | mcp->mb[22];
969 ha->fw_ddr_ram_end = (mcp->mb[25] << 16) | mcp->mb[24];
f73cb695 970 }
6246b8a1 971
ca9e9c3e 972failed:
1da177e4
LT		 973 if (rval != QLA_SUCCESS) {
974 /*EMPTY*/
7c3df132 975 ql_dbg(ql_dbg_mbx, vha, 0x102a, "Failed=%x.\n", rval);
1da177e4
LT		 976 } else {
977 /*EMPTY*/
5f28d2d7
SK		 978 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x102b,
979 "Done %s.\n", __func__);
1da177e4 980 }
ca9e9c3e 981 return rval;
1da177e4
LT		 982}
983
984/*
985 * qla2x00_get_fw_options
986 * Set firmware options.
987 *
988 * Input:
989 * ha = adapter block pointer.
990 * fwopt = pointer for firmware options.
991 *
992 * Returns:
993 * qla2x00 local function return status code.
994 *
995 * Context:
996 * Kernel context.
997 */
998int
7b867cf7 999qla2x00_get_fw_options(scsi_qla_host_t *vha, uint16_t *fwopts)
1da177e4
LT		 1000{
1001 int rval;
1002 mbx_cmd_t mc;
1003 mbx_cmd_t *mcp = &mc;
1004
5f28d2d7
SK		 1005 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x102c,
1006 "Entered %s.\n", __func__);
1da177e4
LT		 1007
1008 mcp->mb[0] = MBC_GET_FIRMWARE_OPTION;
1009 mcp->out_mb = MBX_0;
1010 mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0;
b93480e3 1011 mcp->tov = MBX_TOV_SECONDS;
1da177e4 1012 mcp->flags = 0;
7b867cf7 1013 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 1014
1015 if (rval != QLA_SUCCESS) {
1016 /*EMPTY*/
7c3df132 1017 ql_dbg(ql_dbg_mbx, vha, 0x102d, "Failed=%x.\n", rval);
1da177e4 1018 } else {
1c7c6357 1019 fwopts[0] = mcp->mb[0];
1da177e4
LT		 1020 fwopts[1] = mcp->mb[1];
1021 fwopts[2] = mcp->mb[2];
1022 fwopts[3] = mcp->mb[3];
1023
5f28d2d7
SK		 1024 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x102e,
1025 "Done %s.\n", __func__);
1da177e4
LT		 1026 }
1027
1028 return rval;
1029}
1030
1031
1032/*
1033 * qla2x00_set_fw_options
1034 * Set firmware options.
1035 *
1036 * Input:
1037 * ha = adapter block pointer.
1038 * fwopt = pointer for firmware options.
1039 *
1040 * Returns:
1041 * qla2x00 local function return status code.
1042 *
1043 * Context:
1044 * Kernel context.
1045 */
1046int
7b867cf7 1047qla2x00_set_fw_options(scsi_qla_host_t *vha, uint16_t *fwopts)
1da177e4
LT		 1048{
1049 int rval;
1050 mbx_cmd_t mc;
1051 mbx_cmd_t *mcp = &mc;
1052
5f28d2d7
SK		 1053 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x102f,
1054 "Entered %s.\n", __func__);
1da177e4
LT		 1055
1056 mcp->mb[0] = MBC_SET_FIRMWARE_OPTION;
1057 mcp->mb[1] = fwopts[1];
1058 mcp->mb[2] = fwopts[2];
1059 mcp->mb[3] = fwopts[3];
1c7c6357 1060 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
1da177e4 1061 mcp->in_mb = MBX_0;
7b867cf7 1062 if (IS_FWI2_CAPABLE(vha->hw)) {
1c7c6357 1063 mcp->in_mb |= MBX_1;
2da52737
QT		 1064 mcp->mb[10] = fwopts[10];
1065 mcp->out_mb |= MBX_10;
1c7c6357
AV		 1066 } else {
1067 mcp->mb[10] = fwopts[10];
1068 mcp->mb[11] = fwopts[11];
1069 mcp->mb[12] = 0; /* Undocumented, but used */
1070 mcp->out_mb |= MBX_12|MBX_11|MBX_10;
1071 }
b93480e3 1072 mcp->tov = MBX_TOV_SECONDS;
1da177e4 1073 mcp->flags = 0;
7b867cf7 1074 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4 1075
1c7c6357
AV		 1076 fwopts[0] = mcp->mb[0];
1077
1da177e4
LT		 1078 if (rval != QLA_SUCCESS) {
1079 /*EMPTY*/
7c3df132
SK		 1080 ql_dbg(ql_dbg_mbx, vha, 0x1030,
1081 "Failed=%x (%x/%x).\n", rval, mcp->mb[0], mcp->mb[1]);
1da177e4
LT		 1082 } else {
1083 /*EMPTY*/
5f28d2d7
SK		 1084 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1031,
1085 "Done %s.\n", __func__);
1da177e4
LT		 1086 }
1087
1088 return rval;
1089}
1090
1091/*
1092 * qla2x00_mbx_reg_test
1093 * Mailbox register wrap test.
1094 *
1095 * Input:
1096 * ha = adapter block pointer.
1097 * TARGET_QUEUE_LOCK must be released.
1098 * ADAPTER_STATE_LOCK must be released.
1099 *
1100 * Returns:
1101 * qla2x00 local function return status code.
1102 *
1103 * Context:
1104 * Kernel context.
1105 */
1106int
7b867cf7 1107qla2x00_mbx_reg_test(scsi_qla_host_t *vha)
1da177e4
LT		 1108{
1109 int rval;
1110 mbx_cmd_t mc;
1111 mbx_cmd_t *mcp = &mc;
1112
5f28d2d7
SK		 1113 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1032,
1114 "Entered %s.\n", __func__);
1da177e4
LT		 1115
1116 mcp->mb[0] = MBC_MAILBOX_REGISTER_TEST;
1117 mcp->mb[1] = 0xAAAA;
1118 mcp->mb[2] = 0x5555;
1119 mcp->mb[3] = 0xAA55;
1120 mcp->mb[4] = 0x55AA;
1121 mcp->mb[5] = 0xA5A5;
1122 mcp->mb[6] = 0x5A5A;
1123 mcp->mb[7] = 0x2525;
1124 mcp->out_mb = MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
1125 mcp->in_mb = MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
b93480e3 1126 mcp->tov = MBX_TOV_SECONDS;
1da177e4 1127 mcp->flags = 0;
7b867cf7 1128 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 1129
1130 if (rval == QLA_SUCCESS) {
1131 if (mcp->mb[1] != 0xAAAA || mcp->mb[2] != 0x5555 ||
1132 mcp->mb[3] != 0xAA55 || mcp->mb[4] != 0x55AA)
1133 rval = QLA_FUNCTION_FAILED;
1134 if (mcp->mb[5] != 0xA5A5 || mcp->mb[6] != 0x5A5A ||
1135 mcp->mb[7] != 0x2525)
1136 rval = QLA_FUNCTION_FAILED;
1137 }
1138
1139 if (rval != QLA_SUCCESS) {
1140 /*EMPTY*/
7c3df132 1141 ql_dbg(ql_dbg_mbx, vha, 0x1033, "Failed=%x.\n", rval);
1da177e4
LT		 1142 } else {
1143 /*EMPTY*/
5f28d2d7
SK		 1144 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1034,
1145 "Done %s.\n", __func__);
1da177e4
LT		 1146 }
1147
1148 return rval;
1149}
1150
1151/*
1152 * qla2x00_verify_checksum
1153 * Verify firmware checksum.
1154 *
1155 * Input:
1156 * ha = adapter block pointer.
1157 * TARGET_QUEUE_LOCK must be released.
1158 * ADAPTER_STATE_LOCK must be released.
1159 *
1160 * Returns:
1161 * qla2x00 local function return status code.
1162 *
1163 * Context:
1164 * Kernel context.
1165 */
1166int
7b867cf7 1167qla2x00_verify_checksum(scsi_qla_host_t *vha, uint32_t risc_addr)
1da177e4
LT		 1168{
1169 int rval;
1170 mbx_cmd_t mc;
1171 mbx_cmd_t *mcp = &mc;
1172
5f28d2d7
SK		 1173 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1035,
1174 "Entered %s.\n", __func__);
1da177e4
LT		 1175
1176 mcp->mb[0] = MBC_VERIFY_CHECKSUM;
1c7c6357
AV		 1177 mcp->out_mb = MBX_0;
1178 mcp->in_mb = MBX_0;
7b867cf7 1179 if (IS_FWI2_CAPABLE(vha->hw)) {
1c7c6357
AV		 1180 mcp->mb[1] = MSW(risc_addr);
1181 mcp->mb[2] = LSW(risc_addr);
1182 mcp->out_mb |= MBX_2|MBX_1;
1183 mcp->in_mb |= MBX_2|MBX_1;
1184 } else {
1185 mcp->mb[1] = LSW(risc_addr);
1186 mcp->out_mb |= MBX_1;
1187 mcp->in_mb |= MBX_1;
1188 }
1189
b93480e3 1190 mcp->tov = MBX_TOV_SECONDS;
1da177e4 1191 mcp->flags = 0;
7b867cf7 1192 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 1193
1194 if (rval != QLA_SUCCESS) {
7c3df132
SK		 1195 ql_dbg(ql_dbg_mbx, vha, 0x1036,
1196 "Failed=%x chm sum=%x.\n", rval, IS_FWI2_CAPABLE(vha->hw) ?
1197 (mcp->mb[2] << 16) | mcp->mb[1] : mcp->mb[1]);
1da177e4 1198 } else {
5f28d2d7
SK		 1199 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1037,
1200 "Done %s.\n", __func__);
1da177e4
LT		 1201 }
1202
1203 return rval;
1204}
1205
1206/*
1207 * qla2x00_issue_iocb
1208 * Issue IOCB using mailbox command
1209 *
1210 * Input:
1211 * ha = adapter state pointer.
1212 * buffer = buffer pointer.
1213 * phys_addr = physical address of buffer.
1214 * size = size of buffer.
1215 * TARGET_QUEUE_LOCK must be released.
1216 * ADAPTER_STATE_LOCK must be released.
1217 *
1218 * Returns:
1219 * qla2x00 local function return status code.
1220 *
1221 * Context:
1222 * Kernel context.
1223 */
6e98016c 1224int
7b867cf7 1225qla2x00_issue_iocb_timeout(scsi_qla_host_t *vha, void *buffer,
4d4df193 1226 dma_addr_t phys_addr, size_t size, uint32_t tov)
1da177e4
LT		 1227{
1228 int rval;
1229 mbx_cmd_t mc;
1230 mbx_cmd_t *mcp = &mc;
1231
5f28d2d7
SK		 1232 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1038,
1233 "Entered %s.\n", __func__);
7c3df132 1234
1da177e4
LT		 1235 mcp->mb[0] = MBC_IOCB_COMMAND_A64;
1236 mcp->mb[1] = 0;
1237 mcp->mb[2] = MSW(phys_addr);
1238 mcp->mb[3] = LSW(phys_addr);
1239 mcp->mb[6] = MSW(MSD(phys_addr));
1240 mcp->mb[7] = LSW(MSD(phys_addr));
1241 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
1242 mcp->in_mb = MBX_2|MBX_0;
4d4df193 1243 mcp->tov = tov;
1da177e4 1244 mcp->flags = 0;
7b867cf7 1245 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 1246
1247 if (rval != QLA_SUCCESS) {
1248 /*EMPTY*/
7c3df132 1249 ql_dbg(ql_dbg_mbx, vha, 0x1039, "Failed=%x.\n", rval);
1da177e4 1250 } else {
8c958a99
AV		 1251 sts_entry_t *sts_entry = (sts_entry_t *) buffer;
1252
1253 /* Mask reserved bits. */
1254 sts_entry->entry_status &=
7b867cf7 1255 IS_FWI2_CAPABLE(vha->hw) ? RF_MASK_24XX : RF_MASK;
5f28d2d7
SK		 1256 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103a,
1257 "Done %s.\n", __func__);
1da177e4
LT		 1258 }
1259
1260 return rval;
1261}
1262
4d4df193 1263int
7b867cf7 1264qla2x00_issue_iocb(scsi_qla_host_t *vha, void *buffer, dma_addr_t phys_addr,
4d4df193
HK		 1265 size_t size)
1266{
7b867cf7 1267 return qla2x00_issue_iocb_timeout(vha, buffer, phys_addr, size,
4d4df193
HK		 1268 MBX_TOV_SECONDS);
1269}
1270
1da177e4
LT		 1271/*
1272 * qla2x00_abort_command
1273 * Abort command aborts a specified IOCB.
1274 *
1275 * Input:
1276 * ha = adapter block pointer.
1277 * sp = SB structure pointer.
1278 *
1279 * Returns:
1280 * qla2x00 local function return status code.
1281 *
1282 * Context:
1283 * Kernel context.
1284 */
1285int
2afa19a9 1286qla2x00_abort_command(srb_t *sp)
1da177e4
LT		 1287{
1288 unsigned long flags = 0;
1da177e4 1289 int rval;
73208dfd 1290 uint32_t handle = 0;
1da177e4
LT		 1291 mbx_cmd_t mc;
1292 mbx_cmd_t *mcp = &mc;
2afa19a9
AC		 1293 fc_port_t *fcport = sp->fcport;
1294 scsi_qla_host_t *vha = fcport->vha;
7b867cf7 1295 struct qla_hw_data *ha = vha->hw;
d7459527 1296 struct req_que *req;
9ba56b95 1297 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
1da177e4 1298
5f28d2d7
SK		 1299 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103b,
1300 "Entered %s.\n", __func__);
1da177e4 1301
d7459527
MH		 1302 if (vha->flags.qpairs_available && sp->qpair)
1303 req = sp->qpair->req;
1304 else
1305 req = vha->req;
1306
c9c5ced9 1307 spin_lock_irqsave(&ha->hardware_lock, flags);
8d93f550 1308 for (handle = 1; handle < req->num_outstanding_cmds; handle++) {
7b867cf7 1309 if (req->outstanding_cmds[handle] == sp)
1da177e4
LT		 1310 break;
1311 }
c9c5ced9 1312 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1da177e4 1313
8d93f550 1314 if (handle == req->num_outstanding_cmds) {
1da177e4
LT		 1315 /* command not found */
1316 return QLA_FUNCTION_FAILED;
1317 }
1318
1319 mcp->mb[0] = MBC_ABORT_COMMAND;
1320 if (HAS_EXTENDED_IDS(ha))
1321 mcp->mb[1] = fcport->loop_id;
1322 else
1323 mcp->mb[1] = fcport->loop_id << 8;
1324 mcp->mb[2] = (uint16_t)handle;
1325 mcp->mb[3] = (uint16_t)(handle >> 16);
9ba56b95 1326 mcp->mb[6] = (uint16_t)cmd->device->lun;
1da177e4
LT		 1327 mcp->out_mb = MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
1328 mcp->in_mb = MBX_0;
b93480e3 1329 mcp->tov = MBX_TOV_SECONDS;
1da177e4 1330 mcp->flags = 0;
7b867cf7 1331 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 1332
1333 if (rval != QLA_SUCCESS) {
7c3df132 1334 ql_dbg(ql_dbg_mbx, vha, 0x103c, "Failed=%x.\n", rval);
1da177e4 1335 } else {
5f28d2d7
SK		 1336 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103d,
1337 "Done %s.\n", __func__);
1da177e4
LT		 1338 }
1339
1340 return rval;
1341}
1342
1da177e4 1343int
9cb78c16 1344qla2x00_abort_target(struct fc_port *fcport, uint64_t l, int tag)
1da177e4 1345{
523ec773 1346 int rval, rval2;
1da177e4
LT		 1347 mbx_cmd_t mc;
1348 mbx_cmd_t *mcp = &mc;
7b867cf7 1349 scsi_qla_host_t *vha;
73208dfd
AC		 1350 struct req_que *req;
1351 struct rsp_que *rsp;
1da177e4 1352
523ec773 1353 l = l;
7b867cf7 1354 vha = fcport->vha;
7c3df132 1355
5f28d2d7
SK		 1356 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103e,
1357 "Entered %s.\n", __func__);
7c3df132 1358
7e2b895b
GM		 1359 req = vha->hw->req_q_map[0];
1360 rsp = req->rsp;
1da177e4 1361 mcp->mb[0] = MBC_ABORT_TARGET;
523ec773 1362 mcp->out_mb = MBX_9|MBX_2|MBX_1|MBX_0;
7b867cf7 1363 if (HAS_EXTENDED_IDS(vha->hw)) {
1da177e4
LT		 1364 mcp->mb[1] = fcport->loop_id;
1365 mcp->mb[10] = 0;
1366 mcp->out_mb |= MBX_10;
1367 } else {
1368 mcp->mb[1] = fcport->loop_id << 8;
1369 }
7b867cf7
AC		 1370 mcp->mb[2] = vha->hw->loop_reset_delay;
1371 mcp->mb[9] = vha->vp_idx;
1da177e4
LT		 1372
1373 mcp->in_mb = MBX_0;
b93480e3 1374 mcp->tov = MBX_TOV_SECONDS;
1da177e4 1375 mcp->flags = 0;
7b867cf7 1376 rval = qla2x00_mailbox_command(vha, mcp);
523ec773 1377 if (rval != QLA_SUCCESS) {
5f28d2d7
SK		 1378 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103f,
1379 "Failed=%x.\n", rval);
523ec773
AV		 1380 }
1381
1382 /* Issue marker IOCB. */
73208dfd
AC		 1383 rval2 = qla2x00_marker(vha, req, rsp, fcport->loop_id, 0,
1384 MK_SYNC_ID);
523ec773 1385 if (rval2 != QLA_SUCCESS) {
7c3df132
SK		 1386 ql_dbg(ql_dbg_mbx, vha, 0x1040,
1387 "Failed to issue marker IOCB (%x).\n", rval2);
523ec773 1388 } else {
5f28d2d7
SK		 1389 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1041,
1390 "Done %s.\n", __func__);
523ec773
AV		 1391 }
1392
1393 return rval;
1394}
1395
1396int
9cb78c16 1397qla2x00_lun_reset(struct fc_port *fcport, uint64_t l, int tag)
523ec773
AV		 1398{
1399 int rval, rval2;
1400 mbx_cmd_t mc;
1401 mbx_cmd_t *mcp = &mc;
7b867cf7 1402 scsi_qla_host_t *vha;
73208dfd
AC		 1403 struct req_que *req;
1404 struct rsp_que *rsp;
523ec773 1405
7b867cf7 1406 vha = fcport->vha;
7c3df132 1407
5f28d2d7
SK		 1408 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1042,
1409 "Entered %s.\n", __func__);
7c3df132 1410
7e2b895b
GM		 1411 req = vha->hw->req_q_map[0];
1412 rsp = req->rsp;
523ec773
AV		 1413 mcp->mb[0] = MBC_LUN_RESET;
1414 mcp->out_mb = MBX_9|MBX_3|MBX_2|MBX_1|MBX_0;
7b867cf7 1415 if (HAS_EXTENDED_IDS(vha->hw))
523ec773
AV		 1416 mcp->mb[1] = fcport->loop_id;
1417 else
1418 mcp->mb[1] = fcport->loop_id << 8;
9cb78c16 1419 mcp->mb[2] = (u32)l;
523ec773 1420 mcp->mb[3] = 0;
7b867cf7 1421 mcp->mb[9] = vha->vp_idx;
1da177e4 1422
523ec773 1423 mcp->in_mb = MBX_0;
b93480e3 1424 mcp->tov = MBX_TOV_SECONDS;
523ec773 1425 mcp->flags = 0;
7b867cf7 1426 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4 1427 if (rval != QLA_SUCCESS) {
7c3df132 1428 ql_dbg(ql_dbg_mbx, vha, 0x1043, "Failed=%x.\n", rval);
523ec773
AV		 1429 }
1430
1431 /* Issue marker IOCB. */
73208dfd
AC		 1432 rval2 = qla2x00_marker(vha, req, rsp, fcport->loop_id, l,
1433 MK_SYNC_ID_LUN);
523ec773 1434 if (rval2 != QLA_SUCCESS) {
7c3df132
SK		 1435 ql_dbg(ql_dbg_mbx, vha, 0x1044,
1436 "Failed to issue marker IOCB (%x).\n", rval2);
1da177e4 1437 } else {
5f28d2d7
SK		 1438 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1045,
1439 "Done %s.\n", __func__);
1da177e4
LT		 1440 }
1441
1442 return rval;
1443}
1da177e4 1444
1da177e4
LT		 1445/*
1446 * qla2x00_get_adapter_id
1447 * Get adapter ID and topology.
1448 *
1449 * Input:
1450 * ha = adapter block pointer.
1451 * id = pointer for loop ID.
1452 * al_pa = pointer for AL_PA.
1453 * area = pointer for area.
1454 * domain = pointer for domain.
1455 * top = pointer for topology.
1456 * TARGET_QUEUE_LOCK must be released.
1457 * ADAPTER_STATE_LOCK must be released.
1458 *
1459 * Returns:
1460 * qla2x00 local function return status code.
1461 *
1462 * Context:
1463 * Kernel context.
1464 */
1465int
7b867cf7 1466qla2x00_get_adapter_id(scsi_qla_host_t *vha, uint16_t *id, uint8_t *al_pa,
2c3dfe3f 1467 uint8_t *area, uint8_t *domain, uint16_t *top, uint16_t *sw_cap)
1da177e4
LT		 1468{
1469 int rval;
1470 mbx_cmd_t mc;
1471 mbx_cmd_t *mcp = &mc;
1472
5f28d2d7
SK		 1473 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1046,
1474 "Entered %s.\n", __func__);
1da177e4
LT		 1475
1476 mcp->mb[0] = MBC_GET_ADAPTER_LOOP_ID;
7b867cf7 1477 mcp->mb[9] = vha->vp_idx;
eb66dc60 1478 mcp->out_mb = MBX_9|MBX_0;
2c3dfe3f 1479 mcp->in_mb = MBX_9|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
6246b8a1 1480 if (IS_CNA_CAPABLE(vha->hw))
bad7001c 1481 mcp->in_mb |= MBX_13|MBX_12|MBX_11|MBX_10;
7c9c4766
JC		 1482 if (IS_FWI2_CAPABLE(vha->hw))
1483 mcp->in_mb |= MBX_19|MBX_18|MBX_17|MBX_16;
969a6199
SC		 1484 if (IS_QLA27XX(vha->hw))
1485 mcp->in_mb |= MBX_15;
b93480e3 1486 mcp->tov = MBX_TOV_SECONDS;
1da177e4 1487 mcp->flags = 0;
7b867cf7 1488 rval = qla2x00_mailbox_command(vha, mcp);
33135aa2
RA		 1489 if (mcp->mb[0] == MBS_COMMAND_ERROR)
1490 rval = QLA_COMMAND_ERROR;
42e421b1
AV		 1491 else if (mcp->mb[0] == MBS_INVALID_COMMAND)
1492 rval = QLA_INVALID_COMMAND;
1da177e4
LT		 1493
1494 /* Return data. */
1495 *id = mcp->mb[1];
1496 *al_pa = LSB(mcp->mb[2]);
1497 *area = MSB(mcp->mb[2]);
1498 *domain = LSB(mcp->mb[3]);
1499 *top = mcp->mb[6];
2c3dfe3f 1500 *sw_cap = mcp->mb[7];
1da177e4
LT		 1501
1502 if (rval != QLA_SUCCESS) {
1503 /*EMPTY*/
7c3df132 1504 ql_dbg(ql_dbg_mbx, vha, 0x1047, "Failed=%x.\n", rval);
1da177e4 1505 } else {
5f28d2d7
SK		 1506 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1048,
1507 "Done %s.\n", __func__);
bad7001c 1508
6246b8a1 1509 if (IS_CNA_CAPABLE(vha->hw)) {
bad7001c
AV		 1510 vha->fcoe_vlan_id = mcp->mb[9] & 0xfff;
1511 vha->fcoe_fcf_idx = mcp->mb[10];
1512 vha->fcoe_vn_port_mac[5] = mcp->mb[11] >> 8;
1513 vha->fcoe_vn_port_mac[4] = mcp->mb[11] & 0xff;
1514 vha->fcoe_vn_port_mac[3] = mcp->mb[12] >> 8;
1515 vha->fcoe_vn_port_mac[2] = mcp->mb[12] & 0xff;
1516 vha->fcoe_vn_port_mac[1] = mcp->mb[13] >> 8;
1517 vha->fcoe_vn_port_mac[0] = mcp->mb[13] & 0xff;
1518 }
7c9c4766 1519 /* If FA-WWN supported */
d6b9b42b
SK		 1520 if (IS_FAWWN_CAPABLE(vha->hw)) {
1521 if (mcp->mb[7] & BIT_14) {
1522 vha->port_name[0] = MSB(mcp->mb[16]);
1523 vha->port_name[1] = LSB(mcp->mb[16]);
1524 vha->port_name[2] = MSB(mcp->mb[17]);
1525 vha->port_name[3] = LSB(mcp->mb[17]);
1526 vha->port_name[4] = MSB(mcp->mb[18]);
1527 vha->port_name[5] = LSB(mcp->mb[18]);
1528 vha->port_name[6] = MSB(mcp->mb[19]);
1529 vha->port_name[7] = LSB(mcp->mb[19]);
1530 fc_host_port_name(vha->host) =
1531 wwn_to_u64(vha->port_name);
1532 ql_dbg(ql_dbg_mbx, vha, 0x10ca,
1533 "FA-WWN acquired %016llx\n",
1534 wwn_to_u64(vha->port_name));
1535 }
7c9c4766 1536 }
969a6199
SC		 1537
1538 if (IS_QLA27XX(vha->hw))
1539 vha->bbcr = mcp->mb[15];
1da177e4
LT		 1540 }
1541
1542 return rval;
1543}
1544
1545/*
1546 * qla2x00_get_retry_cnt
1547 * Get current firmware login retry count and delay.
1548 *
1549 * Input:
1550 * ha = adapter block pointer.
1551 * retry_cnt = pointer to login retry count.
1552 * tov = pointer to login timeout value.
1553 *
1554 * Returns:
1555 * qla2x00 local function return status code.
1556 *
1557 * Context:
1558 * Kernel context.
1559 */
1560int
7b867cf7 1561qla2x00_get_retry_cnt(scsi_qla_host_t *vha, uint8_t *retry_cnt, uint8_t *tov,
1da177e4
LT		 1562 uint16_t *r_a_tov)
1563{
1564 int rval;
1565 uint16_t ratov;
1566 mbx_cmd_t mc;
1567 mbx_cmd_t *mcp = &mc;
1568
5f28d2d7
SK		 1569 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1049,
1570 "Entered %s.\n", __func__);
1da177e4
LT		 1571
1572 mcp->mb[0] = MBC_GET_RETRY_COUNT;
1573 mcp->out_mb = MBX_0;
1574 mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0;
b93480e3 1575 mcp->tov = MBX_TOV_SECONDS;
1da177e4 1576 mcp->flags = 0;
7b867cf7 1577 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 1578
1579 if (rval != QLA_SUCCESS) {
1580 /*EMPTY*/
7c3df132
SK		 1581 ql_dbg(ql_dbg_mbx, vha, 0x104a,
1582 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
1da177e4
LT		 1583 } else {
1584 /* Convert returned data and check our values. */
1585 *r_a_tov = mcp->mb[3] / 2;
1586 ratov = (mcp->mb[3]/2) / 10; /* mb[3] value is in 100ms */
1587 if (mcp->mb[1] * ratov > (*retry_cnt) * (*tov)) {
1588 /* Update to the larger values */
1589 *retry_cnt = (uint8_t)mcp->mb[1];
1590 *tov = ratov;
1591 }
1592
5f28d2d7 1593 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x104b,
7c3df132 1594 "Done %s mb3=%d ratov=%d.\n", __func__, mcp->mb[3], ratov);
1da177e4
LT		 1595 }
1596
1597 return rval;
1598}
1599
1600/*
1601 * qla2x00_init_firmware
1602 * Initialize adapter firmware.
1603 *
1604 * Input:
1605 * ha = adapter block pointer.
1606 * dptr = Initialization control block pointer.
1607 * size = size of initialization control block.
1608 * TARGET_QUEUE_LOCK must be released.
1609 * ADAPTER_STATE_LOCK must be released.
1610 *
1611 * Returns:
1612 * qla2x00 local function return status code.
1613 *
1614 * Context:
1615 * Kernel context.
1616 */
1617int
7b867cf7 1618qla2x00_init_firmware(scsi_qla_host_t *vha, uint16_t size)
1da177e4
LT		 1619{
1620 int rval;
1621 mbx_cmd_t mc;
1622 mbx_cmd_t *mcp = &mc;
7b867cf7 1623 struct qla_hw_data *ha = vha->hw;
1da177e4 1624
5f28d2d7
SK		 1625 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x104c,
1626 "Entered %s.\n", __func__);
1da177e4 1627
7ec0effd 1628 if (IS_P3P_TYPE(ha) && ql2xdbwr)
8dfa4b5a 1629 qla82xx_wr_32(ha, (uintptr_t __force)ha->nxdb_wr_ptr,
a9083016
GM		 1630 (0x04 | (ha->portnum << 5) | (0 << 8) | (0 << 16)));
1631
e6e074f1 1632 if (ha->flags.npiv_supported)
2c3dfe3f
SJ		 1633 mcp->mb[0] = MBC_MID_INITIALIZE_FIRMWARE;
1634 else
1635 mcp->mb[0] = MBC_INITIALIZE_FIRMWARE;
1636
b64b0e8f 1637 mcp->mb[1] = 0;
1da177e4
LT		 1638 mcp->mb[2] = MSW(ha->init_cb_dma);
1639 mcp->mb[3] = LSW(ha->init_cb_dma);
1da177e4
LT		 1640 mcp->mb[6] = MSW(MSD(ha->init_cb_dma));
1641 mcp->mb[7] = LSW(MSD(ha->init_cb_dma));
b64b0e8f 1642 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
4ef21bd4 1643 if (ha->ex_init_cb && ha->ex_init_cb->ex_version) {
b64b0e8f
AV		 1644 mcp->mb[1] = BIT_0;
1645 mcp->mb[10] = MSW(ha->ex_init_cb_dma);
1646 mcp->mb[11] = LSW(ha->ex_init_cb_dma);
1647 mcp->mb[12] = MSW(MSD(ha->ex_init_cb_dma));
1648 mcp->mb[13] = LSW(MSD(ha->ex_init_cb_dma));
1649 mcp->mb[14] = sizeof(*ha->ex_init_cb);
1650 mcp->out_mb |= MBX_14|MBX_13|MBX_12|MBX_11|MBX_10;
1651 }
6246b8a1
GM		 1652 /* 1 and 2 should normally be captured. */
1653 mcp->in_mb = MBX_2|MBX_1|MBX_0;
f73cb695 1654 if (IS_QLA83XX(ha) || IS_QLA27XX(ha))
6246b8a1
GM		 1655 /* mb3 is additional info about the installed SFP. */
1656 mcp->in_mb |= MBX_3;
1da177e4
LT		 1657 mcp->buf_size = size;
1658 mcp->flags = MBX_DMA_OUT;
b93480e3 1659 mcp->tov = MBX_TOV_SECONDS;
7b867cf7 1660 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 1661
1662 if (rval != QLA_SUCCESS) {
1663 /*EMPTY*/
7c3df132 1664 ql_dbg(ql_dbg_mbx, vha, 0x104d,
6246b8a1
GM		 1665 "Failed=%x mb[0]=%x, mb[1]=%x, mb[2]=%x, mb[3]=%x,.\n",
1666 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2], mcp->mb[3]);
1da177e4
LT		 1667 } else {
1668 /*EMPTY*/
5f28d2d7
SK		 1669 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x104e,
1670 "Done %s.\n", __func__);
1da177e4
LT		 1671 }
1672
1673 return rval;
1674}
1675
2d70c103 1676
1da177e4
LT		 1677/*
1678 * qla2x00_get_port_database
1679 * Issue normal/enhanced get port database mailbox command
1680 * and copy device name as necessary.
1681 *
1682 * Input:
1683 * ha = adapter state pointer.
1684 * dev = structure pointer.
1685 * opt = enhanced cmd option byte.
1686 *
1687 * Returns:
1688 * qla2x00 local function return status code.
1689 *
1690 * Context:
1691 * Kernel context.
1692 */
1693int
7b867cf7 1694qla2x00_get_port_database(scsi_qla_host_t *vha, fc_port_t *fcport, uint8_t opt)
1da177e4
LT		 1695{
1696 int rval;
1697 mbx_cmd_t mc;
1698 mbx_cmd_t *mcp = &mc;
1699 port_database_t *pd;
1c7c6357 1700 struct port_database_24xx *pd24;
1da177e4 1701 dma_addr_t pd_dma;
7b867cf7 1702 struct qla_hw_data *ha = vha->hw;
1da177e4 1703
5f28d2d7
SK		 1704 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x104f,
1705 "Entered %s.\n", __func__);
1da177e4 1706
1c7c6357
AV		 1707 pd24 = NULL;
1708 pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &pd_dma);
1da177e4 1709 if (pd == NULL) {
7c3df132
SK		 1710 ql_log(ql_log_warn, vha, 0x1050,
1711 "Failed to allocate port database structure.\n");
1da177e4
LT		 1712 return QLA_MEMORY_ALLOC_FAILED;
1713 }
1c7c6357 1714 memset(pd, 0, max(PORT_DATABASE_SIZE, PORT_DATABASE_24XX_SIZE));
1da177e4 1715
1c7c6357 1716 mcp->mb[0] = MBC_GET_PORT_DATABASE;
e428924c 1717 if (opt != 0 && !IS_FWI2_CAPABLE(ha))
1da177e4 1718 mcp->mb[0] = MBC_ENHANCED_GET_PORT_DATABASE;
1da177e4
LT		 1719 mcp->mb[2] = MSW(pd_dma);
1720 mcp->mb[3] = LSW(pd_dma);
1721 mcp->mb[6] = MSW(MSD(pd_dma));
1722 mcp->mb[7] = LSW(MSD(pd_dma));
7b867cf7 1723 mcp->mb[9] = vha->vp_idx;
2c3dfe3f 1724 mcp->out_mb = MBX_9|MBX_7|MBX_6|MBX_3|MBX_2|MBX_0;
1da177e4 1725 mcp->in_mb = MBX_0;
e428924c 1726 if (IS_FWI2_CAPABLE(ha)) {
1c7c6357
AV		 1727 mcp->mb[1] = fcport->loop_id;
1728 mcp->mb[10] = opt;
1729 mcp->out_mb |= MBX_10|MBX_1;
1730 mcp->in_mb |= MBX_1;
1731 } else if (HAS_EXTENDED_IDS(ha)) {
1732 mcp->mb[1] = fcport->loop_id;
1733 mcp->mb[10] = opt;
1734 mcp->out_mb |= MBX_10|MBX_1;
1735 } else {
1736 mcp->mb[1] = fcport->loop_id << 8 | opt;
1737 mcp->out_mb |= MBX_1;
1738 }
e428924c
AV		 1739 mcp->buf_size = IS_FWI2_CAPABLE(ha) ?
1740 PORT_DATABASE_24XX_SIZE : PORT_DATABASE_SIZE;
1da177e4
LT		 1741 mcp->flags = MBX_DMA_IN;
1742 mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2);
7b867cf7 1743 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 1744 if (rval != QLA_SUCCESS)
1745 goto gpd_error_out;
1746
e428924c 1747 if (IS_FWI2_CAPABLE(ha)) {
0eba25df 1748 uint64_t zero = 0;
1c7c6357
AV		 1749 pd24 = (struct port_database_24xx *) pd;
1750
1751 /* Check for logged in state. */
1752 if (pd24->current_login_state != PDS_PRLI_COMPLETE &&
1753 pd24->last_login_state != PDS_PRLI_COMPLETE) {
7c3df132
SK		 1754 ql_dbg(ql_dbg_mbx, vha, 0x1051,
1755 "Unable to verify login-state (%x/%x) for "
1756 "loop_id %x.\n", pd24->current_login_state,
1757 pd24->last_login_state, fcport->loop_id);
1c7c6357
AV		 1758 rval = QLA_FUNCTION_FAILED;
1759 goto gpd_error_out;
1760 }
1da177e4 1761
0eba25df
AE		 1762 if (fcport->loop_id == FC_NO_LOOP_ID ||
1763 (memcmp(fcport->port_name, (uint8_t *)&zero, 8) &&
1764 memcmp(fcport->port_name, pd24->port_name, 8))) {
1765 /* We lost the device mid way. */
1766 rval = QLA_NOT_LOGGED_IN;
1767 goto gpd_error_out;
1768 }
1769
1c7c6357
AV		 1770 /* Names are little-endian. */
1771 memcpy(fcport->node_name, pd24->node_name, WWN_SIZE);
1772 memcpy(fcport->port_name, pd24->port_name, WWN_SIZE);
1773
1774 /* Get port_id of device. */
1775 fcport->d_id.b.domain = pd24->port_id[0];
1776 fcport->d_id.b.area = pd24->port_id[1];
1777 fcport->d_id.b.al_pa = pd24->port_id[2];
1778 fcport->d_id.b.rsvd_1 = 0;
1779
1780 /* If not target must be initiator or unknown type. */
1781 if ((pd24->prli_svc_param_word_3[0] & BIT_4) == 0)
1782 fcport->port_type = FCT_INITIATOR;
1783 else
1784 fcport->port_type = FCT_TARGET;
2d70c103
NB		 1785
1786 /* Passback COS information. */
1787 fcport->supported_classes = (pd24->flags & PDF_CLASS_2) ?
1788 FC_COS_CLASS2 : FC_COS_CLASS3;
1789
1790 if (pd24->prli_svc_param_word_3[0] & BIT_7)
1791 fcport->flags |= FCF_CONF_COMP_SUPPORTED;
1c7c6357 1792 } else {
0eba25df
AE		 1793 uint64_t zero = 0;
1794
1c7c6357
AV		 1795 /* Check for logged in state. */
1796 if (pd->master_state != PD_STATE_PORT_LOGGED_IN &&
1797 pd->slave_state != PD_STATE_PORT_LOGGED_IN) {
7c3df132
SK		 1798 ql_dbg(ql_dbg_mbx, vha, 0x100a,
1799 "Unable to verify login-state (%x/%x) - "
1800 "portid=%02x%02x%02x.\n", pd->master_state,
1801 pd->slave_state, fcport->d_id.b.domain,
1802 fcport->d_id.b.area, fcport->d_id.b.al_pa);
1c7c6357
AV		 1803 rval = QLA_FUNCTION_FAILED;
1804 goto gpd_error_out;
1805 }
1da177e4 1806
0eba25df
AE		 1807 if (fcport->loop_id == FC_NO_LOOP_ID ||
1808 (memcmp(fcport->port_name, (uint8_t *)&zero, 8) &&
1809 memcmp(fcport->port_name, pd->port_name, 8))) {
1810 /* We lost the device mid way. */
1811 rval = QLA_NOT_LOGGED_IN;
1812 goto gpd_error_out;
1813 }
1814
1c7c6357
AV		 1815 /* Names are little-endian. */
1816 memcpy(fcport->node_name, pd->node_name, WWN_SIZE);
1817 memcpy(fcport->port_name, pd->port_name, WWN_SIZE);
1818
1819 /* Get port_id of device. */
1820 fcport->d_id.b.domain = pd->port_id[0];
1821 fcport->d_id.b.area = pd->port_id[3];
1822 fcport->d_id.b.al_pa = pd->port_id[2];
1823 fcport->d_id.b.rsvd_1 = 0;
1824
1c7c6357
AV		 1825 /* If not target must be initiator or unknown type. */
1826 if ((pd->prli_svc_param_word_3[0] & BIT_4) == 0)
1827 fcport->port_type = FCT_INITIATOR;
1828 else
1829 fcport->port_type = FCT_TARGET;
ad3e0eda
AV		 1830
1831 /* Passback COS information. */
1832 fcport->supported_classes = (pd->options & BIT_4) ?
1833 FC_COS_CLASS2: FC_COS_CLASS3;
1c7c6357 1834 }
1da177e4
LT		 1835
1836gpd_error_out:
1837 dma_pool_free(ha->s_dma_pool, pd, pd_dma);
1838
1839 if (rval != QLA_SUCCESS) {
7c3df132
SK		 1840 ql_dbg(ql_dbg_mbx, vha, 0x1052,
1841 "Failed=%x mb[0]=%x mb[1]=%x.\n", rval,
1842 mcp->mb[0], mcp->mb[1]);
1da177e4 1843 } else {
5f28d2d7
SK		 1844 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1053,
1845 "Done %s.\n", __func__);
1da177e4
LT		 1846 }
1847
1848 return rval;
1849}
1850
1851/*
1852 * qla2x00_get_firmware_state
1853 * Get adapter firmware state.
1854 *
1855 * Input:
1856 * ha = adapter block pointer.
1857 * dptr = pointer for firmware state.
1858 * TARGET_QUEUE_LOCK must be released.
1859 * ADAPTER_STATE_LOCK must be released.
1860 *
1861 * Returns:
1862 * qla2x00 local function return status code.
1863 *
1864 * Context:
1865 * Kernel context.
1866 */
1867int
7b867cf7 1868qla2x00_get_firmware_state(scsi_qla_host_t *vha, uint16_t *states)
1da177e4
LT		 1869{
1870 int rval;
1871 mbx_cmd_t mc;
1872 mbx_cmd_t *mcp = &mc;
1873
5f28d2d7
SK		 1874 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1054,
1875 "Entered %s.\n", __func__);
1da177e4
LT		 1876
1877 mcp->mb[0] = MBC_GET_FIRMWARE_STATE;
1878 mcp->out_mb = MBX_0;
9d2683c0 1879 if (IS_FWI2_CAPABLE(vha->hw))
b5a340dd 1880 mcp->in_mb = MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
9d2683c0
AV		 1881 else
1882 mcp->in_mb = MBX_1|MBX_0;
b93480e3 1883 mcp->tov = MBX_TOV_SECONDS;
1da177e4 1884 mcp->flags = 0;
7b867cf7 1885 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4 1886
4d4df193
HK		 1887 /* Return firmware states. */
1888 states[0] = mcp->mb[1];
9d2683c0
AV		 1889 if (IS_FWI2_CAPABLE(vha->hw)) {
1890 states[1] = mcp->mb[2];
ec891462 1891 states[2] = mcp->mb[3]; /* SFP info */
9d2683c0
AV		 1892 states[3] = mcp->mb[4];
1893 states[4] = mcp->mb[5];
b5a340dd 1894 states[5] = mcp->mb[6]; /* DPORT status */
9d2683c0 1895 }
1da177e4
LT		 1896
1897 if (rval != QLA_SUCCESS) {
1898 /*EMPTY*/
7c3df132 1899 ql_dbg(ql_dbg_mbx, vha, 0x1055, "Failed=%x.\n", rval);
1da177e4
LT		 1900 } else {
1901 /*EMPTY*/
5f28d2d7
SK		 1902 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1056,
1903 "Done %s.\n", __func__);
1da177e4
LT		 1904 }
1905
1906 return rval;
1907}
1908
1909/*
1910 * qla2x00_get_port_name
1911 * Issue get port name mailbox command.
1912 * Returned name is in big endian format.
1913 *
1914 * Input:
1915 * ha = adapter block pointer.
1916 * loop_id = loop ID of device.
1917 * name = pointer for name.
1918 * TARGET_QUEUE_LOCK must be released.
1919 * ADAPTER_STATE_LOCK must be released.
1920 *
1921 * Returns:
1922 * qla2x00 local function return status code.
1923 *
1924 * Context:
1925 * Kernel context.
1926 */
1927int
7b867cf7 1928qla2x00_get_port_name(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t *name,
1da177e4
LT		 1929 uint8_t opt)
1930{
1931 int rval;
1932 mbx_cmd_t mc;
1933 mbx_cmd_t *mcp = &mc;
1934
5f28d2d7
SK		 1935 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1057,
1936 "Entered %s.\n", __func__);
1da177e4
LT		 1937
1938 mcp->mb[0] = MBC_GET_PORT_NAME;
7b867cf7 1939 mcp->mb[9] = vha->vp_idx;
2c3dfe3f 1940 mcp->out_mb = MBX_9|MBX_1|MBX_0;
7b867cf7 1941 if (HAS_EXTENDED_IDS(vha->hw)) {
1da177e4
LT		 1942 mcp->mb[1] = loop_id;
1943 mcp->mb[10] = opt;
1944 mcp->out_mb |= MBX_10;
1945 } else {
1946 mcp->mb[1] = loop_id << 8 | opt;
1947 }
1948
1949 mcp->in_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
b93480e3 1950 mcp->tov = MBX_TOV_SECONDS;
1da177e4 1951 mcp->flags = 0;
7b867cf7 1952 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 1953
1954 if (rval != QLA_SUCCESS) {
1955 /*EMPTY*/
7c3df132 1956 ql_dbg(ql_dbg_mbx, vha, 0x1058, "Failed=%x.\n", rval);
1da177e4
LT		 1957 } else {
1958 if (name != NULL) {
1959 /* This function returns name in big endian. */
1196ae02
RL		 1960 name[0] = MSB(mcp->mb[2]);
1961 name[1] = LSB(mcp->mb[2]);
1962 name[2] = MSB(mcp->mb[3]);
1963 name[3] = LSB(mcp->mb[3]);
1964 name[4] = MSB(mcp->mb[6]);
1965 name[5] = LSB(mcp->mb[6]);
1966 name[6] = MSB(mcp->mb[7]);
1967 name[7] = LSB(mcp->mb[7]);
1da177e4
LT		 1968 }
1969
5f28d2d7
SK		 1970 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1059,
1971 "Done %s.\n", __func__);
1da177e4
LT		 1972 }
1973
1974 return rval;
1975}
1976
61e1b269
JC		 1977/*
1978 * qla24xx_link_initialization
1979 * Issue link initialization mailbox command.
1980 *
1981 * Input:
1982 * ha = adapter block pointer.
1983 * TARGET_QUEUE_LOCK must be released.
1984 * ADAPTER_STATE_LOCK must be released.
1985 *
1986 * Returns:
1987 * qla2x00 local function return status code.
1988 *
1989 * Context:
1990 * Kernel context.
1991 */
1992int
1993qla24xx_link_initialize(scsi_qla_host_t *vha)
1994{
1995 int rval;
1996 mbx_cmd_t mc;
1997 mbx_cmd_t *mcp = &mc;
1998
1999 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1152,
2000 "Entered %s.\n", __func__);
2001
2002 if (!IS_FWI2_CAPABLE(vha->hw) || IS_CNA_CAPABLE(vha->hw))
2003 return QLA_FUNCTION_FAILED;
2004
2005 mcp->mb[0] = MBC_LINK_INITIALIZATION;
5a5c27b6
JC		 2006 mcp->mb[1] = BIT_4;
2007 if (vha->hw->operating_mode == LOOP)
2008 mcp->mb[1] |= BIT_6;
2009 else
2010 mcp->mb[1] |= BIT_5;
61e1b269
JC		 2011 mcp->mb[2] = 0;
2012 mcp->mb[3] = 0;
2013 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
2014 mcp->in_mb = MBX_0;
2015 mcp->tov = MBX_TOV_SECONDS;
2016 mcp->flags = 0;
2017 rval = qla2x00_mailbox_command(vha, mcp);
2018
2019 if (rval != QLA_SUCCESS) {
2020 ql_dbg(ql_dbg_mbx, vha, 0x1153, "Failed=%x.\n", rval);
2021 } else {
2022 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1154,
2023 "Done %s.\n", __func__);
2024 }
2025
2026 return rval;
2027}
2028
1da177e4
LT		 2029/*
2030 * qla2x00_lip_reset
2031 * Issue LIP reset mailbox command.
2032 *
2033 * Input:
2034 * ha = adapter block pointer.
2035 * TARGET_QUEUE_LOCK must be released.
2036 * ADAPTER_STATE_LOCK must be released.
2037 *
2038 * Returns:
2039 * qla2x00 local function return status code.
2040 *
2041 * Context:
2042 * Kernel context.
2043 */
2044int
7b867cf7 2045qla2x00_lip_reset(scsi_qla_host_t *vha)
1da177e4
LT		 2046{
2047 int rval;
2048 mbx_cmd_t mc;
2049 mbx_cmd_t *mcp = &mc;
2050
5f28d2d7
SK		 2051 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x105a,
2052 "Entered %s.\n", __func__);
1da177e4 2053
6246b8a1 2054 if (IS_CNA_CAPABLE(vha->hw)) {
3a03eb79
AV		 2055 /* Logout across all FCFs. */
2056 mcp->mb[0] = MBC_LIP_FULL_LOGIN;
2057 mcp->mb[1] = BIT_1;
2058 mcp->mb[2] = 0;
2059 mcp->out_mb = MBX_2|MBX_1|MBX_0;
2060 } else if (IS_FWI2_CAPABLE(vha->hw)) {
1c7c6357 2061 mcp->mb[0] = MBC_LIP_FULL_LOGIN;
0c8c39af
AV		 2062 mcp->mb[1] = BIT_6;
2063 mcp->mb[2] = 0;
7b867cf7 2064 mcp->mb[3] = vha->hw->loop_reset_delay;
1c7c6357 2065 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
1da177e4 2066 } else {
1c7c6357
AV		 2067 mcp->mb[0] = MBC_LIP_RESET;
2068 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
7b867cf7 2069 if (HAS_EXTENDED_IDS(vha->hw)) {
1c7c6357
AV		 2070 mcp->mb[1] = 0x00ff;
2071 mcp->mb[10] = 0;
2072 mcp->out_mb |= MBX_10;
2073 } else {
2074 mcp->mb[1] = 0xff00;
2075 }
7b867cf7 2076 mcp->mb[2] = vha->hw->loop_reset_delay;
1c7c6357 2077 mcp->mb[3] = 0;
1da177e4 2078 }
1da177e4 2079 mcp->in_mb = MBX_0;
b93480e3 2080 mcp->tov = MBX_TOV_SECONDS;
1da177e4 2081 mcp->flags = 0;
7b867cf7 2082 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 2083
2084 if (rval != QLA_SUCCESS) {
2085 /*EMPTY*/
7c3df132 2086 ql_dbg(ql_dbg_mbx, vha, 0x105b, "Failed=%x.\n", rval);
1da177e4
LT		 2087 } else {
2088 /*EMPTY*/
5f28d2d7
SK		 2089 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x105c,
2090 "Done %s.\n", __func__);
1da177e4
LT		 2091 }
2092
2093 return rval;
2094}
2095
2096/*
2097 * qla2x00_send_sns
2098 * Send SNS command.
2099 *
2100 * Input:
2101 * ha = adapter block pointer.
2102 * sns = pointer for command.
2103 * cmd_size = command size.
2104 * buf_size = response/command size.
2105 * TARGET_QUEUE_LOCK must be released.
2106 * ADAPTER_STATE_LOCK must be released.
2107 *
2108 * Returns:
2109 * qla2x00 local function return status code.
2110 *
2111 * Context:
2112 * Kernel context.
2113 */
2114int
7b867cf7 2115qla2x00_send_sns(scsi_qla_host_t *vha, dma_addr_t sns_phys_address,
1da177e4
LT		 2116 uint16_t cmd_size, size_t buf_size)
2117{
2118 int rval;
2119 mbx_cmd_t mc;
2120 mbx_cmd_t *mcp = &mc;
2121
5f28d2d7
SK		 2122 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x105d,
2123 "Entered %s.\n", __func__);
1da177e4 2124
5f28d2d7 2125 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x105e,
7c3df132
SK		 2126 "Retry cnt=%d ratov=%d total tov=%d.\n",
2127 vha->hw->retry_count, vha->hw->login_timeout, mcp->tov);
1da177e4
LT		 2128
2129 mcp->mb[0] = MBC_SEND_SNS_COMMAND;
2130 mcp->mb[1] = cmd_size;
2131 mcp->mb[2] = MSW(sns_phys_address);
2132 mcp->mb[3] = LSW(sns_phys_address);
2133 mcp->mb[6] = MSW(MSD(sns_phys_address));
2134 mcp->mb[7] = LSW(MSD(sns_phys_address));
2135 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
2136 mcp->in_mb = MBX_0|MBX_1;
2137 mcp->buf_size = buf_size;
2138 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN;
7b867cf7
AC		 2139 mcp->tov = (vha->hw->login_timeout * 2) + (vha->hw->login_timeout / 2);
2140 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 2141
2142 if (rval != QLA_SUCCESS) {
2143 /*EMPTY*/
7c3df132
SK		 2144 ql_dbg(ql_dbg_mbx, vha, 0x105f,
2145 "Failed=%x mb[0]=%x mb[1]=%x.\n",
2146 rval, mcp->mb[0], mcp->mb[1]);
1da177e4
LT		 2147 } else {
2148 /*EMPTY*/
5f28d2d7
SK		 2149 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1060,
2150 "Done %s.\n", __func__);
1da177e4
LT		 2151 }
2152
2153 return rval;
2154}
2155
1c7c6357 2156int
7b867cf7 2157qla24xx_login_fabric(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain,
1c7c6357
AV		 2158 uint8_t area, uint8_t al_pa, uint16_t *mb, uint8_t opt)
2159{
2160 int rval;
2161
2162 struct logio_entry_24xx *lg;
2163 dma_addr_t lg_dma;
2164 uint32_t iop[2];
7b867cf7 2165 struct qla_hw_data *ha = vha->hw;
2afa19a9 2166 struct req_que *req;
1c7c6357 2167
5f28d2d7
SK		 2168 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1061,
2169 "Entered %s.\n", __func__);
1c7c6357 2170
d7459527
MH		 2171 if (vha->vp_idx && vha->qpair)
2172 req = vha->qpair->req;
68ca949c 2173 else
d7459527 2174 req = ha->req_q_map[0];
2afa19a9 2175
1c7c6357
AV		 2176 lg = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &lg_dma);
2177 if (lg == NULL) {
7c3df132
SK		 2178 ql_log(ql_log_warn, vha, 0x1062,
2179 "Failed to allocate login IOCB.\n");
1c7c6357
AV		 2180 return QLA_MEMORY_ALLOC_FAILED;
2181 }
2182 memset(lg, 0, sizeof(struct logio_entry_24xx));
2183
2184 lg->entry_type = LOGINOUT_PORT_IOCB_TYPE;
2185 lg->entry_count = 1;
2afa19a9 2186 lg->handle = MAKE_HANDLE(req->id, lg->handle);
1c7c6357 2187 lg->nport_handle = cpu_to_le16(loop_id);
ad950360 2188 lg->control_flags = cpu_to_le16(LCF_COMMAND_PLOGI);
1c7c6357 2189 if (opt & BIT_0)
ad950360 2190 lg->control_flags |= cpu_to_le16(LCF_COND_PLOGI);
8baa51a6 2191 if (opt & BIT_1)
ad950360 2192 lg->control_flags |= cpu_to_le16(LCF_SKIP_PRLI);
1c7c6357
AV		 2193 lg->port_id[0] = al_pa;
2194 lg->port_id[1] = area;
2195 lg->port_id[2] = domain;
7b867cf7 2196 lg->vp_index = vha->vp_idx;
7f45dd0b
AV		 2197 rval = qla2x00_issue_iocb_timeout(vha, lg, lg_dma, 0,
2198 (ha->r_a_tov / 10 * 2) + 2);
1c7c6357 2199 if (rval != QLA_SUCCESS) {
7c3df132
SK		 2200 ql_dbg(ql_dbg_mbx, vha, 0x1063,
2201 "Failed to issue login IOCB (%x).\n", rval);
1c7c6357 2202 } else if (lg->entry_status != 0) {
7c3df132
SK		 2203 ql_dbg(ql_dbg_mbx, vha, 0x1064,
2204 "Failed to complete IOCB -- error status (%x).\n",
2205 lg->entry_status);
1c7c6357 2206 rval = QLA_FUNCTION_FAILED;
ad950360 2207 } else if (lg->comp_status != cpu_to_le16(CS_COMPLETE)) {
1c7c6357
AV		 2208 iop[0] = le32_to_cpu(lg->io_parameter[0]);
2209 iop[1] = le32_to_cpu(lg->io_parameter[1]);
2210
7c3df132
SK		 2211 ql_dbg(ql_dbg_mbx, vha, 0x1065,
2212 "Failed to complete IOCB -- completion status (%x) "
2213 "ioparam=%x/%x.\n", le16_to_cpu(lg->comp_status),
2214 iop[0], iop[1]);
1c7c6357
AV		 2215
2216 switch (iop[0]) {
2217 case LSC_SCODE_PORTID_USED:
2218 mb[0] = MBS_PORT_ID_USED;
2219 mb[1] = LSW(iop[1]);
2220 break;
2221 case LSC_SCODE_NPORT_USED:
2222 mb[0] = MBS_LOOP_ID_USED;
2223 break;
2224 case LSC_SCODE_NOLINK:
2225 case LSC_SCODE_NOIOCB:
2226 case LSC_SCODE_NOXCB:
2227 case LSC_SCODE_CMD_FAILED:
2228 case LSC_SCODE_NOFABRIC:
2229 case LSC_SCODE_FW_NOT_READY:
2230 case LSC_SCODE_NOT_LOGGED_IN:
2231 case LSC_SCODE_NOPCB:
2232 case LSC_SCODE_ELS_REJECT:
2233 case LSC_SCODE_CMD_PARAM_ERR:
2234 case LSC_SCODE_NONPORT:
2235 case LSC_SCODE_LOGGED_IN:
2236 case LSC_SCODE_NOFLOGI_ACC:
2237 default:
2238 mb[0] = MBS_COMMAND_ERROR;
2239 break;
2240 }
2241 } else {
5f28d2d7
SK		 2242 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1066,
2243 "Done %s.\n", __func__);
1c7c6357
AV		 2244
2245 iop[0] = le32_to_cpu(lg->io_parameter[0]);
2246
2247 mb[0] = MBS_COMMAND_COMPLETE;
2248 mb[1] = 0;
2249 if (iop[0] & BIT_4) {
2250 if (iop[0] & BIT_8)
2251 mb[1] |= BIT_1;
2252 } else
2253 mb[1] = BIT_0;
ad3e0eda
AV		 2254
2255 /* Passback COS information. */
2256 mb[10] = 0;
2257 if (lg->io_parameter[7] || lg->io_parameter[8])
2258 mb[10] |= BIT_0; /* Class 2. */
2259 if (lg->io_parameter[9] || lg->io_parameter[10])
2260 mb[10] |= BIT_1; /* Class 3. */
ad950360 2261 if (lg->io_parameter[0] & cpu_to_le32(BIT_7))
2d70c103
NB		 2262 mb[10] |= BIT_7; /* Confirmed Completion
2263 * Allowed
2264 */
1c7c6357
AV		 2265 }
2266
2267 dma_pool_free(ha->s_dma_pool, lg, lg_dma);
2268
2269 return rval;
2270}
2271
1da177e4
LT		 2272/*
2273 * qla2x00_login_fabric
2274 * Issue login fabric port mailbox command.
2275 *
2276 * Input:
2277 * ha = adapter block pointer.
2278 * loop_id = device loop ID.
2279 * domain = device domain.
2280 * area = device area.
2281 * al_pa = device AL_PA.
2282 * status = pointer for return status.
2283 * opt = command options.
2284 * TARGET_QUEUE_LOCK must be released.
2285 * ADAPTER_STATE_LOCK must be released.
2286 *
2287 * Returns:
2288 * qla2x00 local function return status code.
2289 *
2290 * Context:
2291 * Kernel context.
2292 */
2293int
7b867cf7 2294qla2x00_login_fabric(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain,
1da177e4
LT		 2295 uint8_t area, uint8_t al_pa, uint16_t *mb, uint8_t opt)
2296{
2297 int rval;
2298 mbx_cmd_t mc;
2299 mbx_cmd_t *mcp = &mc;
7b867cf7 2300 struct qla_hw_data *ha = vha->hw;
1da177e4 2301
5f28d2d7
SK		 2302 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1067,
2303 "Entered %s.\n", __func__);
1da177e4
LT		 2304
2305 mcp->mb[0] = MBC_LOGIN_FABRIC_PORT;
2306 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
2307 if (HAS_EXTENDED_IDS(ha)) {
2308 mcp->mb[1] = loop_id;
2309 mcp->mb[10] = opt;
2310 mcp->out_mb |= MBX_10;
2311 } else {
2312 mcp->mb[1] = (loop_id << 8) | opt;
2313 }
2314 mcp->mb[2] = domain;
2315 mcp->mb[3] = area << 8 | al_pa;
2316
2317 mcp->in_mb = MBX_7|MBX_6|MBX_2|MBX_1|MBX_0;
2318 mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2);
2319 mcp->flags = 0;
7b867cf7 2320 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 2321
2322 /* Return mailbox statuses. */
2323 if (mb != NULL) {
2324 mb[0] = mcp->mb[0];
2325 mb[1] = mcp->mb[1];
2326 mb[2] = mcp->mb[2];
2327 mb[6] = mcp->mb[6];
2328 mb[7] = mcp->mb[7];
ad3e0eda
AV		 2329 /* COS retrieved from Get-Port-Database mailbox command. */
2330 mb[10] = 0;
1da177e4
LT		 2331 }
2332
2333 if (rval != QLA_SUCCESS) {
2334 /* RLU tmp code: need to change main mailbox_command function to
2335 * return ok even when the mailbox completion value is not
2336 * SUCCESS. The caller needs to be responsible to interpret
2337 * the return values of this mailbox command if we're not
2338 * to change too much of the existing code.
2339 */
2340 if (mcp->mb[0] == 0x4001 || mcp->mb[0] == 0x4002 ||
2341 mcp->mb[0] == 0x4003 || mcp->mb[0] == 0x4005 ||
2342 mcp->mb[0] == 0x4006)
2343 rval = QLA_SUCCESS;
2344
2345 /*EMPTY*/
7c3df132
SK		 2346 ql_dbg(ql_dbg_mbx, vha, 0x1068,
2347 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n",
2348 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]);
1da177e4
LT		 2349 } else {
2350 /*EMPTY*/
5f28d2d7
SK		 2351 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1069,
2352 "Done %s.\n", __func__);
1da177e4
LT		 2353 }
2354
2355 return rval;
2356}
2357
2358/*
2359 * qla2x00_login_local_device
2360 * Issue login loop port mailbox command.
fa2a1ce5 2361 *
1da177e4
LT		 2362 * Input:
2363 * ha = adapter block pointer.
2364 * loop_id = device loop ID.
2365 * opt = command options.
fa2a1ce5 2366 *
1da177e4
LT		 2367 * Returns:
2368 * Return status code.
fa2a1ce5 2369 *
1da177e4
LT		 2370 * Context:
2371 * Kernel context.
fa2a1ce5 2372 *
1da177e4
LT		 2373 */
2374int
7b867cf7 2375qla2x00_login_local_device(scsi_qla_host_t *vha, fc_port_t *fcport,
1da177e4
LT		 2376 uint16_t *mb_ret, uint8_t opt)
2377{
2378 int rval;
2379 mbx_cmd_t mc;
2380 mbx_cmd_t *mcp = &mc;
7b867cf7 2381 struct qla_hw_data *ha = vha->hw;
1da177e4 2382
5f28d2d7
SK		 2383 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x106a,
2384 "Entered %s.\n", __func__);
7c3df132 2385
e428924c 2386 if (IS_FWI2_CAPABLE(ha))
7b867cf7 2387 return qla24xx_login_fabric(vha, fcport->loop_id,
9a52a57c 2388 fcport->d_id.b.domain, fcport->d_id.b.area,
2389 fcport->d_id.b.al_pa, mb_ret, opt);
2390
1da177e4
LT		 2391 mcp->mb[0] = MBC_LOGIN_LOOP_PORT;
2392 if (HAS_EXTENDED_IDS(ha))
9a52a57c 2393 mcp->mb[1] = fcport->loop_id;
1da177e4 2394 else
9a52a57c 2395 mcp->mb[1] = fcport->loop_id << 8;
1da177e4
LT		 2396 mcp->mb[2] = opt;
2397 mcp->out_mb = MBX_2|MBX_1|MBX_0;
2398 mcp->in_mb = MBX_7|MBX_6|MBX_1|MBX_0;
2399 mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2);
2400 mcp->flags = 0;
7b867cf7 2401 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 2402
2403 /* Return mailbox statuses. */
2404 if (mb_ret != NULL) {
2405 mb_ret[0] = mcp->mb[0];
2406 mb_ret[1] = mcp->mb[1];
2407 mb_ret[6] = mcp->mb[6];
2408 mb_ret[7] = mcp->mb[7];
2409 }
2410
2411 if (rval != QLA_SUCCESS) {
2412 /* AV tmp code: need to change main mailbox_command function to
2413 * return ok even when the mailbox completion value is not
2414 * SUCCESS. The caller needs to be responsible to interpret
2415 * the return values of this mailbox command if we're not
2416 * to change too much of the existing code.
2417 */
2418 if (mcp->mb[0] == 0x4005 || mcp->mb[0] == 0x4006)
2419 rval = QLA_SUCCESS;
2420
7c3df132
SK		 2421 ql_dbg(ql_dbg_mbx, vha, 0x106b,
2422 "Failed=%x mb[0]=%x mb[1]=%x mb[6]=%x mb[7]=%x.\n",
2423 rval, mcp->mb[0], mcp->mb[1], mcp->mb[6], mcp->mb[7]);
1da177e4
LT		 2424 } else {
2425 /*EMPTY*/
5f28d2d7
SK		 2426 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x106c,
2427 "Done %s.\n", __func__);
1da177e4
LT		 2428 }
2429
2430 return (rval);
2431}
2432
1c7c6357 2433int
7b867cf7 2434qla24xx_fabric_logout(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain,
1c7c6357
AV		 2435 uint8_t area, uint8_t al_pa)
2436{
2437 int rval;
2438 struct logio_entry_24xx *lg;
2439 dma_addr_t lg_dma;
7b867cf7 2440 struct qla_hw_data *ha = vha->hw;
2afa19a9 2441 struct req_que *req;
1c7c6357 2442
5f28d2d7
SK		 2443 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x106d,
2444 "Entered %s.\n", __func__);
1c7c6357
AV		 2445
2446 lg = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &lg_dma);
2447 if (lg == NULL) {
7c3df132
SK		 2448 ql_log(ql_log_warn, vha, 0x106e,
2449 "Failed to allocate logout IOCB.\n");
1c7c6357
AV		 2450 return QLA_MEMORY_ALLOC_FAILED;
2451 }
2452 memset(lg, 0, sizeof(struct logio_entry_24xx));
2453
d7459527 2454 req = vha->req;
1c7c6357
AV		 2455 lg->entry_type = LOGINOUT_PORT_IOCB_TYPE;
2456 lg->entry_count = 1;
2afa19a9 2457 lg->handle = MAKE_HANDLE(req->id, lg->handle);
1c7c6357
AV		 2458 lg->nport_handle = cpu_to_le16(loop_id);
2459 lg->control_flags =
ad950360 2460 cpu_to_le16(LCF_COMMAND_LOGO|LCF_IMPL_LOGO|
c8d6691b 2461 LCF_FREE_NPORT);
1c7c6357
AV		 2462 lg->port_id[0] = al_pa;
2463 lg->port_id[1] = area;
2464 lg->port_id[2] = domain;
7b867cf7 2465 lg->vp_index = vha->vp_idx;
7f45dd0b
AV		 2466 rval = qla2x00_issue_iocb_timeout(vha, lg, lg_dma, 0,
2467 (ha->r_a_tov / 10 * 2) + 2);
1c7c6357 2468 if (rval != QLA_SUCCESS) {
7c3df132
SK		 2469 ql_dbg(ql_dbg_mbx, vha, 0x106f,
2470 "Failed to issue logout IOCB (%x).\n", rval);
1c7c6357 2471 } else if (lg->entry_status != 0) {
7c3df132
SK		 2472 ql_dbg(ql_dbg_mbx, vha, 0x1070,
2473 "Failed to complete IOCB -- error status (%x).\n",
2474 lg->entry_status);
1c7c6357 2475 rval = QLA_FUNCTION_FAILED;
ad950360 2476 } else if (lg->comp_status != cpu_to_le16(CS_COMPLETE)) {
7c3df132
SK		 2477 ql_dbg(ql_dbg_mbx, vha, 0x1071,
2478 "Failed to complete IOCB -- completion status (%x) "
2479 "ioparam=%x/%x.\n", le16_to_cpu(lg->comp_status),
1c7c6357 2480 le32_to_cpu(lg->io_parameter[0]),
7c3df132 2481 le32_to_cpu(lg->io_parameter[1]));
1c7c6357
AV		 2482 } else {
2483 /*EMPTY*/
5f28d2d7
SK		 2484 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1072,
2485 "Done %s.\n", __func__);
1c7c6357
AV		 2486 }
2487
2488 dma_pool_free(ha->s_dma_pool, lg, lg_dma);
2489
2490 return rval;
2491}
2492
1da177e4
LT		 2493/*
2494 * qla2x00_fabric_logout
2495 * Issue logout fabric port mailbox command.
2496 *
2497 * Input:
2498 * ha = adapter block pointer.
2499 * loop_id = device loop ID.
2500 * TARGET_QUEUE_LOCK must be released.
2501 * ADAPTER_STATE_LOCK must be released.
2502 *
2503 * Returns:
2504 * qla2x00 local function return status code.
2505 *
2506 * Context:
2507 * Kernel context.
2508 */
2509int
7b867cf7 2510qla2x00_fabric_logout(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain,
1c7c6357 2511 uint8_t area, uint8_t al_pa)
1da177e4
LT		 2512{
2513 int rval;
2514 mbx_cmd_t mc;
2515 mbx_cmd_t *mcp = &mc;
2516
5f28d2d7
SK		 2517 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1073,
2518 "Entered %s.\n", __func__);
1da177e4
LT		 2519
2520 mcp->mb[0] = MBC_LOGOUT_FABRIC_PORT;
2521 mcp->out_mb = MBX_1|MBX_0;
7b867cf7 2522 if (HAS_EXTENDED_IDS(vha->hw)) {
1da177e4
LT		 2523 mcp->mb[1] = loop_id;
2524 mcp->mb[10] = 0;
2525 mcp->out_mb |= MBX_10;
2526 } else {
2527 mcp->mb[1] = loop_id << 8;
2528 }
2529
2530 mcp->in_mb = MBX_1|MBX_0;
b93480e3 2531 mcp->tov = MBX_TOV_SECONDS;
1da177e4 2532 mcp->flags = 0;
7b867cf7 2533 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 2534
2535 if (rval != QLA_SUCCESS) {
2536 /*EMPTY*/
7c3df132
SK		 2537 ql_dbg(ql_dbg_mbx, vha, 0x1074,
2538 "Failed=%x mb[1]=%x.\n", rval, mcp->mb[1]);
1da177e4
LT		 2539 } else {
2540 /*EMPTY*/
5f28d2d7
SK		 2541 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1075,
2542 "Done %s.\n", __func__);
1da177e4
LT		 2543 }
2544
2545 return rval;
2546}
2547
2548/*
2549 * qla2x00_full_login_lip
2550 * Issue full login LIP mailbox command.
2551 *
2552 * Input:
2553 * ha = adapter block pointer.
2554 * TARGET_QUEUE_LOCK must be released.
2555 * ADAPTER_STATE_LOCK must be released.
2556 *
2557 * Returns:
2558 * qla2x00 local function return status code.
2559 *
2560 * Context:
2561 * Kernel context.
2562 */
2563int
7b867cf7 2564qla2x00_full_login_lip(scsi_qla_host_t *vha)
1da177e4
LT		 2565{
2566 int rval;
2567 mbx_cmd_t mc;
2568 mbx_cmd_t *mcp = &mc;
2569
5f28d2d7
SK		 2570 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1076,
2571 "Entered %s.\n", __func__);
1da177e4
LT		 2572
2573 mcp->mb[0] = MBC_LIP_FULL_LOGIN;
7b867cf7 2574 mcp->mb[1] = IS_FWI2_CAPABLE(vha->hw) ? BIT_3 : 0;
0c8c39af 2575 mcp->mb[2] = 0;
1da177e4
LT		 2576 mcp->mb[3] = 0;
2577 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
2578 mcp->in_mb = MBX_0;
b93480e3 2579 mcp->tov = MBX_TOV_SECONDS;
1da177e4 2580 mcp->flags = 0;
7b867cf7 2581 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 2582
2583 if (rval != QLA_SUCCESS) {
2584 /*EMPTY*/
7c3df132 2585 ql_dbg(ql_dbg_mbx, vha, 0x1077, "Failed=%x.\n", rval);
1da177e4
LT		 2586 } else {
2587 /*EMPTY*/
5f28d2d7
SK		 2588 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1078,
2589 "Done %s.\n", __func__);
1da177e4
LT		 2590 }
2591
2592 return rval;
2593}
2594
2595/*
2596 * qla2x00_get_id_list
2597 *
2598 * Input:
2599 * ha = adapter block pointer.
2600 *
2601 * Returns:
2602 * qla2x00 local function return status code.
2603 *
2604 * Context:
2605 * Kernel context.
2606 */
2607int
7b867cf7 2608qla2x00_get_id_list(scsi_qla_host_t *vha, void *id_list, dma_addr_t id_list_dma,
1da177e4
LT		 2609 uint16_t *entries)
2610{
2611 int rval;
2612 mbx_cmd_t mc;
2613 mbx_cmd_t *mcp = &mc;
2614
5f28d2d7
SK		 2615 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1079,
2616 "Entered %s.\n", __func__);
1da177e4
LT		 2617
2618 if (id_list == NULL)
2619 return QLA_FUNCTION_FAILED;
2620
2621 mcp->mb[0] = MBC_GET_ID_LIST;
1c7c6357 2622 mcp->out_mb = MBX_0;
7b867cf7 2623 if (IS_FWI2_CAPABLE(vha->hw)) {
1c7c6357
AV		 2624 mcp->mb[2] = MSW(id_list_dma);
2625 mcp->mb[3] = LSW(id_list_dma);
2626 mcp->mb[6] = MSW(MSD(id_list_dma));
2627 mcp->mb[7] = LSW(MSD(id_list_dma));
247ec457 2628 mcp->mb[8] = 0;
7b867cf7 2629 mcp->mb[9] = vha->vp_idx;
2c3dfe3f 2630 mcp->out_mb |= MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2;
1c7c6357
AV		 2631 } else {
2632 mcp->mb[1] = MSW(id_list_dma);
2633 mcp->mb[2] = LSW(id_list_dma);
2634 mcp->mb[3] = MSW(MSD(id_list_dma));
2635 mcp->mb[6] = LSW(MSD(id_list_dma));
2636 mcp->out_mb |= MBX_6|MBX_3|MBX_2|MBX_1;
2637 }
1da177e4 2638 mcp->in_mb = MBX_1|MBX_0;
b93480e3 2639 mcp->tov = MBX_TOV_SECONDS;
1da177e4 2640 mcp->flags = 0;
7b867cf7 2641 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 2642
2643 if (rval != QLA_SUCCESS) {
2644 /*EMPTY*/
7c3df132 2645 ql_dbg(ql_dbg_mbx, vha, 0x107a, "Failed=%x.\n", rval);
1da177e4
LT		 2646 } else {
2647 *entries = mcp->mb[1];
5f28d2d7
SK		 2648 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x107b,
2649 "Done %s.\n", __func__);
1da177e4
LT		 2650 }
2651
2652 return rval;
2653}
2654
2655/*
2656 * qla2x00_get_resource_cnts
2657 * Get current firmware resource counts.
2658 *
2659 * Input:
2660 * ha = adapter block pointer.
2661 *
2662 * Returns:
2663 * qla2x00 local function return status code.
2664 *
2665 * Context:
2666 * Kernel context.
2667 */
2668int
03e8c680 2669qla2x00_get_resource_cnts(scsi_qla_host_t *vha)
1da177e4 2670{
03e8c680 2671 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 2672 int rval;
2673 mbx_cmd_t mc;
2674 mbx_cmd_t *mcp = &mc;
2675
5f28d2d7
SK		 2676 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x107c,
2677 "Entered %s.\n", __func__);
1da177e4
LT		 2678
2679 mcp->mb[0] = MBC_GET_RESOURCE_COUNTS;
2680 mcp->out_mb = MBX_0;
4d0ea247 2681 mcp->in_mb = MBX_11|MBX_10|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
f73cb695 2682 if (IS_QLA81XX(vha->hw) || IS_QLA83XX(vha->hw) || IS_QLA27XX(vha->hw))
f3a0a77e 2683 mcp->in_mb |= MBX_12;
b93480e3 2684 mcp->tov = MBX_TOV_SECONDS;
1da177e4 2685 mcp->flags = 0;
7b867cf7 2686 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 2687
2688 if (rval != QLA_SUCCESS) {
2689 /*EMPTY*/
7c3df132
SK		 2690 ql_dbg(ql_dbg_mbx, vha, 0x107d,
2691 "Failed mb[0]=%x.\n", mcp->mb[0]);
1da177e4 2692 } else {
5f28d2d7 2693 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x107e,
7c3df132
SK		 2694 "Done %s mb1=%x mb2=%x mb3=%x mb6=%x mb7=%x mb10=%x "
2695 "mb11=%x mb12=%x.\n", __func__, mcp->mb[1], mcp->mb[2],
2696 mcp->mb[3], mcp->mb[6], mcp->mb[7], mcp->mb[10],
2697 mcp->mb[11], mcp->mb[12]);
1da177e4 2698
03e8c680
QT		 2699 ha->orig_fw_tgt_xcb_count = mcp->mb[1];
2700 ha->cur_fw_tgt_xcb_count = mcp->mb[2];
2701 ha->cur_fw_xcb_count = mcp->mb[3];
2702 ha->orig_fw_xcb_count = mcp->mb[6];
2703 ha->cur_fw_iocb_count = mcp->mb[7];
2704 ha->orig_fw_iocb_count = mcp->mb[10];
2705 if (ha->flags.npiv_supported)
2706 ha->max_npiv_vports = mcp->mb[11];
2707 if (IS_QLA81XX(ha) || IS_QLA83XX(ha) || IS_QLA27XX(ha))
2708 ha->fw_max_fcf_count = mcp->mb[12];
1da177e4
LT		 2709 }
2710
2711 return (rval);
2712}
2713
1da177e4
LT		 2714/*
2715 * qla2x00_get_fcal_position_map
2716 * Get FCAL (LILP) position map using mailbox command
2717 *
2718 * Input:
2719 * ha = adapter state pointer.
2720 * pos_map = buffer pointer (can be NULL).
2721 *
2722 * Returns:
2723 * qla2x00 local function return status code.
2724 *
2725 * Context:
2726 * Kernel context.
2727 */
2728int
7b867cf7 2729qla2x00_get_fcal_position_map(scsi_qla_host_t *vha, char *pos_map)
1da177e4
LT		 2730{
2731 int rval;
2732 mbx_cmd_t mc;
2733 mbx_cmd_t *mcp = &mc;
2734 char *pmap;
2735 dma_addr_t pmap_dma;
7b867cf7 2736 struct qla_hw_data *ha = vha->hw;
1da177e4 2737
5f28d2d7
SK		 2738 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x107f,
2739 "Entered %s.\n", __func__);
7c3df132 2740
4b89258c 2741 pmap = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &pmap_dma);
1da177e4 2742 if (pmap == NULL) {
7c3df132
SK		 2743 ql_log(ql_log_warn, vha, 0x1080,
2744 "Memory alloc failed.\n");
1da177e4
LT		 2745 return QLA_MEMORY_ALLOC_FAILED;
2746 }
2747 memset(pmap, 0, FCAL_MAP_SIZE);
2748
2749 mcp->mb[0] = MBC_GET_FC_AL_POSITION_MAP;
2750 mcp->mb[2] = MSW(pmap_dma);
2751 mcp->mb[3] = LSW(pmap_dma);
2752 mcp->mb[6] = MSW(MSD(pmap_dma));
2753 mcp->mb[7] = LSW(MSD(pmap_dma));
2754 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_0;
2755 mcp->in_mb = MBX_1|MBX_0;
2756 mcp->buf_size = FCAL_MAP_SIZE;
2757 mcp->flags = MBX_DMA_IN;
2758 mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2);
7b867cf7 2759 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 2760
2761 if (rval == QLA_SUCCESS) {
5f28d2d7 2762 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1081,
7c3df132
SK		 2763 "mb0/mb1=%x/%X FC/AL position map size (%x).\n",
2764 mcp->mb[0], mcp->mb[1], (unsigned)pmap[0]);
2765 ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x111d,
2766 pmap, pmap[0] + 1);
1da177e4
LT		 2767
2768 if (pos_map)
2769 memcpy(pos_map, pmap, FCAL_MAP_SIZE);
2770 }
2771 dma_pool_free(ha->s_dma_pool, pmap, pmap_dma);
2772
2773 if (rval != QLA_SUCCESS) {
7c3df132 2774 ql_dbg(ql_dbg_mbx, vha, 0x1082, "Failed=%x.\n", rval);
1da177e4 2775 } else {
5f28d2d7
SK		 2776 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1083,
2777 "Done %s.\n", __func__);
1da177e4
LT		 2778 }
2779
2780 return rval;
2781}
392e2f65 2782
2783/*
2784 * qla2x00_get_link_status
2785 *
2786 * Input:
2787 * ha = adapter block pointer.
2788 * loop_id = device loop ID.
2789 * ret_buf = pointer to link status return buffer.
2790 *
2791 * Returns:
2792 * 0 = success.
2793 * BIT_0 = mem alloc error.
2794 * BIT_1 = mailbox error.
2795 */
2796int
7b867cf7 2797qla2x00_get_link_status(scsi_qla_host_t *vha, uint16_t loop_id,
43ef0580 2798 struct link_statistics *stats, dma_addr_t stats_dma)
392e2f65 2799{
2800 int rval;
2801 mbx_cmd_t mc;
2802 mbx_cmd_t *mcp = &mc;
c6dc9905
JC		 2803 uint32_t *iter = (void *)stats;
2804 ushort dwords = offsetof(typeof(*stats), link_up_cnt)/sizeof(*iter);
7b867cf7 2805 struct qla_hw_data *ha = vha->hw;
392e2f65 2806
5f28d2d7
SK		 2807 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1084,
2808 "Entered %s.\n", __func__);
392e2f65 2809
392e2f65 2810 mcp->mb[0] = MBC_GET_LINK_STATUS;
c6dc9905
JC		 2811 mcp->mb[2] = MSW(LSD(stats_dma));
2812 mcp->mb[3] = LSW(LSD(stats_dma));
43ef0580
AV		 2813 mcp->mb[6] = MSW(MSD(stats_dma));
2814 mcp->mb[7] = LSW(MSD(stats_dma));
392e2f65 2815 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_0;
2816 mcp->in_mb = MBX_0;
e428924c 2817 if (IS_FWI2_CAPABLE(ha)) {
392e2f65 2818 mcp->mb[1] = loop_id;
2819 mcp->mb[4] = 0;
2820 mcp->mb[10] = 0;
2821 mcp->out_mb |= MBX_10|MBX_4|MBX_1;
2822 mcp->in_mb |= MBX_1;
2823 } else if (HAS_EXTENDED_IDS(ha)) {
2824 mcp->mb[1] = loop_id;
2825 mcp->mb[10] = 0;
2826 mcp->out_mb |= MBX_10|MBX_1;
2827 } else {
2828 mcp->mb[1] = loop_id << 8;
2829 mcp->out_mb |= MBX_1;
2830 }
b93480e3 2831 mcp->tov = MBX_TOV_SECONDS;
392e2f65 2832 mcp->flags = IOCTL_CMD;
7b867cf7 2833 rval = qla2x00_mailbox_command(vha, mcp);
392e2f65 2834
2835 if (rval == QLA_SUCCESS) {
2836 if (mcp->mb[0] != MBS_COMMAND_COMPLETE) {
7c3df132
SK		 2837 ql_dbg(ql_dbg_mbx, vha, 0x1085,
2838 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
43ef0580 2839 rval = QLA_FUNCTION_FAILED;
392e2f65 2840 } else {
c6dc9905 2841 /* Re-endianize - firmware data is le32. */
5f28d2d7
SK		 2842 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1086,
2843 "Done %s.\n", __func__);
da08ef5c
JC		 2844 for ( ; dwords--; iter++)
2845 le32_to_cpus(iter);
392e2f65 2846 }
2847 } else {
2848 /* Failed. */
7c3df132 2849 ql_dbg(ql_dbg_mbx, vha, 0x1087, "Failed=%x.\n", rval);
392e2f65 2850 }
2851
392e2f65 2852 return rval;
2853}
2854
2855int
7b867cf7 2856qla24xx_get_isp_stats(scsi_qla_host_t *vha, struct link_statistics *stats,
15f30a57 2857 dma_addr_t stats_dma, uint16_t options)
1c7c6357
AV		 2858{
2859 int rval;
2860 mbx_cmd_t mc;
2861 mbx_cmd_t *mcp = &mc;
da08ef5c 2862 uint32_t *iter, dwords;
1c7c6357 2863
5f28d2d7
SK		 2864 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1088,
2865 "Entered %s.\n", __func__);
1c7c6357 2866
15f30a57
QT		 2867 memset(&mc, 0, sizeof(mc));
2868 mc.mb[0] = MBC_GET_LINK_PRIV_STATS;
2869 mc.mb[2] = MSW(stats_dma);
2870 mc.mb[3] = LSW(stats_dma);
2871 mc.mb[6] = MSW(MSD(stats_dma));
2872 mc.mb[7] = LSW(MSD(stats_dma));
2873 mc.mb[8] = sizeof(struct link_statistics) / 4;
2874 mc.mb[9] = cpu_to_le16(vha->vp_idx);
2875 mc.mb[10] = cpu_to_le16(options);
2876
2877 rval = qla24xx_send_mb_cmd(vha, &mc);
1c7c6357
AV		 2878
2879 if (rval == QLA_SUCCESS) {
2880 if (mcp->mb[0] != MBS_COMMAND_COMPLETE) {
7c3df132
SK		 2881 ql_dbg(ql_dbg_mbx, vha, 0x1089,
2882 "Failed mb[0]=%x.\n", mcp->mb[0]);
43ef0580 2883 rval = QLA_FUNCTION_FAILED;
1c7c6357 2884 } else {
5f28d2d7
SK		 2885 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x108a,
2886 "Done %s.\n", __func__);
c6dc9905 2887 /* Re-endianize - firmware data is le32. */
43ef0580 2888 dwords = sizeof(struct link_statistics) / 4;
da08ef5c
JC		 2889 iter = &stats->link_fail_cnt;
2890 for ( ; dwords--; iter++)
2891 le32_to_cpus(iter);
1c7c6357
AV		 2892 }
2893 } else {
2894 /* Failed. */
7c3df132 2895 ql_dbg(ql_dbg_mbx, vha, 0x108b, "Failed=%x.\n", rval);
1c7c6357
AV		 2896 }
2897
1c7c6357
AV		 2898 return rval;
2899}
1c7c6357
AV		 2900
2901int
2afa19a9 2902qla24xx_abort_command(srb_t *sp)
1c7c6357
AV		 2903{
2904 int rval;
1c7c6357
AV		 2905 unsigned long flags = 0;
2906
2907 struct abort_entry_24xx *abt;
2908 dma_addr_t abt_dma;
2909 uint32_t handle;
2afa19a9
AC		 2910 fc_port_t *fcport = sp->fcport;
2911 struct scsi_qla_host *vha = fcport->vha;
7b867cf7 2912 struct qla_hw_data *ha = vha->hw;
67c2e93a 2913 struct req_que *req = vha->req;
1c7c6357 2914
5f28d2d7
SK		 2915 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x108c,
2916 "Entered %s.\n", __func__);
1c7c6357 2917
d7459527
MH		 2918 if (vha->flags.qpairs_available && sp->qpair)
2919 req = sp->qpair->req;
2920
4440e46d
AB		 2921 if (ql2xasynctmfenable)
2922 return qla24xx_async_abort_command(sp);
2923
7b867cf7 2924 spin_lock_irqsave(&ha->hardware_lock, flags);
8d93f550 2925 for (handle = 1; handle < req->num_outstanding_cmds; handle++) {
7b867cf7 2926 if (req->outstanding_cmds[handle] == sp)
1c7c6357
AV		 2927 break;
2928 }
7b867cf7 2929 spin_unlock_irqrestore(&ha->hardware_lock, flags);
8d93f550 2930 if (handle == req->num_outstanding_cmds) {
1c7c6357
AV		 2931 /* Command not found. */
2932 return QLA_FUNCTION_FAILED;
2933 }
2934
2935 abt = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &abt_dma);
2936 if (abt == NULL) {
7c3df132
SK		 2937 ql_log(ql_log_warn, vha, 0x108d,
2938 "Failed to allocate abort IOCB.\n");
1c7c6357
AV		 2939 return QLA_MEMORY_ALLOC_FAILED;
2940 }
2941 memset(abt, 0, sizeof(struct abort_entry_24xx));
2942
2943 abt->entry_type = ABORT_IOCB_TYPE;
2944 abt->entry_count = 1;
2afa19a9 2945 abt->handle = MAKE_HANDLE(req->id, abt->handle);
1c7c6357 2946 abt->nport_handle = cpu_to_le16(fcport->loop_id);
a74ec14f 2947 abt->handle_to_abort = MAKE_HANDLE(req->id, handle);
1c7c6357
AV		 2948 abt->port_id[0] = fcport->d_id.b.al_pa;
2949 abt->port_id[1] = fcport->d_id.b.area;
2950 abt->port_id[2] = fcport->d_id.b.domain;
c6d39e23 2951 abt->vp_index = fcport->vha->vp_idx;
73208dfd
AC		 2952
2953 abt->req_que_no = cpu_to_le16(req->id);
2954
7b867cf7 2955 rval = qla2x00_issue_iocb(vha, abt, abt_dma, 0);
1c7c6357 2956 if (rval != QLA_SUCCESS) {
7c3df132
SK		 2957 ql_dbg(ql_dbg_mbx, vha, 0x108e,
2958 "Failed to issue IOCB (%x).\n", rval);
1c7c6357 2959 } else if (abt->entry_status != 0) {
7c3df132
SK		 2960 ql_dbg(ql_dbg_mbx, vha, 0x108f,
2961 "Failed to complete IOCB -- error status (%x).\n",
2962 abt->entry_status);
1c7c6357 2963 rval = QLA_FUNCTION_FAILED;
ad950360 2964 } else if (abt->nport_handle != cpu_to_le16(0)) {
7c3df132
SK		 2965 ql_dbg(ql_dbg_mbx, vha, 0x1090,
2966 "Failed to complete IOCB -- completion status (%x).\n",
2967 le16_to_cpu(abt->nport_handle));
f934c9d0
CD		 2968 if (abt->nport_handle == CS_IOCB_ERROR)
2969 rval = QLA_FUNCTION_PARAMETER_ERROR;
2970 else
2971 rval = QLA_FUNCTION_FAILED;
1c7c6357 2972 } else {
5f28d2d7
SK		 2973 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1091,
2974 "Done %s.\n", __func__);
1c7c6357
AV		 2975 }
2976
2977 dma_pool_free(ha->s_dma_pool, abt, abt_dma);
2978
2979 return rval;
2980}
2981
2982struct tsk_mgmt_cmd {
2983 union {
2984 struct tsk_mgmt_entry tsk;
2985 struct sts_entry_24xx sts;
2986 } p;
2987};
2988
523ec773
AV		 2989static int
2990__qla24xx_issue_tmf(char *name, uint32_t type, struct fc_port *fcport,
9cb78c16 2991 uint64_t l, int tag)
1c7c6357 2992{
523ec773 2993 int rval, rval2;
1c7c6357 2994 struct tsk_mgmt_cmd *tsk;
9ca1d01f 2995 struct sts_entry_24xx *sts;
1c7c6357 2996 dma_addr_t tsk_dma;
7b867cf7
AC		 2997 scsi_qla_host_t *vha;
2998 struct qla_hw_data *ha;
73208dfd
AC		 2999 struct req_que *req;
3000 struct rsp_que *rsp;
d7459527 3001 struct qla_qpair *qpair;
1c7c6357 3002
7b867cf7
AC		 3003 vha = fcport->vha;
3004 ha = vha->hw;
2afa19a9 3005 req = vha->req;
7c3df132 3006
5f28d2d7
SK		 3007 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1092,
3008 "Entered %s.\n", __func__);
7c3df132 3009
d7459527
MH		 3010 if (vha->vp_idx && vha->qpair) {
3011 /* NPIV port */
3012 qpair = vha->qpair;
3013 rsp = qpair->rsp;
3014 req = qpair->req;
3015 } else {
68ca949c 3016 rsp = req->rsp;
d7459527
MH		 3017 }
3018
7b867cf7 3019 tsk = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &tsk_dma);
1c7c6357 3020 if (tsk == NULL) {
7c3df132
SK		 3021 ql_log(ql_log_warn, vha, 0x1093,
3022 "Failed to allocate task management IOCB.\n");
1c7c6357
AV		 3023 return QLA_MEMORY_ALLOC_FAILED;
3024 }
3025 memset(tsk, 0, sizeof(struct tsk_mgmt_cmd));
3026
3027 tsk->p.tsk.entry_type = TSK_MGMT_IOCB_TYPE;
3028 tsk->p.tsk.entry_count = 1;
2afa19a9 3029 tsk->p.tsk.handle = MAKE_HANDLE(req->id, tsk->p.tsk.handle);
1c7c6357 3030 tsk->p.tsk.nport_handle = cpu_to_le16(fcport->loop_id);
00a537b8 3031 tsk->p.tsk.timeout = cpu_to_le16(ha->r_a_tov / 10 * 2);
523ec773 3032 tsk->p.tsk.control_flags = cpu_to_le32(type);
1c7c6357
AV		 3033 tsk->p.tsk.port_id[0] = fcport->d_id.b.al_pa;
3034 tsk->p.tsk.port_id[1] = fcport->d_id.b.area;
3035 tsk->p.tsk.port_id[2] = fcport->d_id.b.domain;
c6d39e23 3036 tsk->p.tsk.vp_index = fcport->vha->vp_idx;
523ec773
AV		 3037 if (type == TCF_LUN_RESET) {
3038 int_to_scsilun(l, &tsk->p.tsk.lun);
3039 host_to_fcp_swap((uint8_t *)&tsk->p.tsk.lun,
3040 sizeof(tsk->p.tsk.lun));
3041 }
2c3dfe3f 3042
9ca1d01f 3043 sts = &tsk->p.sts;
7b867cf7 3044 rval = qla2x00_issue_iocb(vha, tsk, tsk_dma, 0);
1c7c6357 3045 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3046 ql_dbg(ql_dbg_mbx, vha, 0x1094,
3047 "Failed to issue %s reset IOCB (%x).\n", name, rval);
9ca1d01f 3048 } else if (sts->entry_status != 0) {
7c3df132
SK		 3049 ql_dbg(ql_dbg_mbx, vha, 0x1095,
3050 "Failed to complete IOCB -- error status (%x).\n",
3051 sts->entry_status);
1c7c6357 3052 rval = QLA_FUNCTION_FAILED;
ad950360 3053 } else if (sts->comp_status != cpu_to_le16(CS_COMPLETE)) {
7c3df132
SK		 3054 ql_dbg(ql_dbg_mbx, vha, 0x1096,
3055 "Failed to complete IOCB -- completion status (%x).\n",
3056 le16_to_cpu(sts->comp_status));
9ca1d01f 3057 rval = QLA_FUNCTION_FAILED;
97dec564
AV		 3058 } else if (le16_to_cpu(sts->scsi_status) &
3059 SS_RESPONSE_INFO_LEN_VALID) {
3060 if (le32_to_cpu(sts->rsp_data_len) < 4) {
5f28d2d7 3061 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1097,
7c3df132
SK		 3062 "Ignoring inconsistent data length -- not enough "
3063 "response info (%d).\n",
3064 le32_to_cpu(sts->rsp_data_len));
97dec564 3065 } else if (sts->data[3]) {
7c3df132
SK		 3066 ql_dbg(ql_dbg_mbx, vha, 0x1098,
3067 "Failed to complete IOCB -- response (%x).\n",
3068 sts->data[3]);
97dec564
AV		 3069 rval = QLA_FUNCTION_FAILED;
3070 }
1c7c6357
AV		 3071 }
3072
3073 /* Issue marker IOCB. */
73208dfd 3074 rval2 = qla2x00_marker(vha, req, rsp, fcport->loop_id, l,
523ec773
AV		 3075 type == TCF_LUN_RESET ? MK_SYNC_ID_LUN: MK_SYNC_ID);
3076 if (rval2 != QLA_SUCCESS) {
7c3df132
SK		 3077 ql_dbg(ql_dbg_mbx, vha, 0x1099,
3078 "Failed to issue marker IOCB (%x).\n", rval2);
1c7c6357 3079 } else {
5f28d2d7
SK		 3080 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x109a,
3081 "Done %s.\n", __func__);
1c7c6357
AV		 3082 }
3083
7b867cf7 3084 dma_pool_free(ha->s_dma_pool, tsk, tsk_dma);
1c7c6357
AV		 3085
3086 return rval;
3087}
3088
523ec773 3089int
9cb78c16 3090qla24xx_abort_target(struct fc_port *fcport, uint64_t l, int tag)
523ec773 3091{
3822263e
MI		 3092 struct qla_hw_data *ha = fcport->vha->hw;
3093
3094 if ((ql2xasynctmfenable) && IS_FWI2_CAPABLE(ha))
3095 return qla2x00_async_tm_cmd(fcport, TCF_TARGET_RESET, l, tag);
3096
2afa19a9 3097 return __qla24xx_issue_tmf("Target", TCF_TARGET_RESET, fcport, l, tag);
523ec773
AV		 3098}
3099
3100int
9cb78c16 3101qla24xx_lun_reset(struct fc_port *fcport, uint64_t l, int tag)
523ec773 3102{
3822263e
MI		 3103 struct qla_hw_data *ha = fcport->vha->hw;
3104
3105 if ((ql2xasynctmfenable) && IS_FWI2_CAPABLE(ha))
3106 return qla2x00_async_tm_cmd(fcport, TCF_LUN_RESET, l, tag);
3107
2afa19a9 3108 return __qla24xx_issue_tmf("Lun", TCF_LUN_RESET, fcport, l, tag);
523ec773
AV		 3109}
3110
1c7c6357 3111int
7b867cf7 3112qla2x00_system_error(scsi_qla_host_t *vha)
1c7c6357
AV		 3113{
3114 int rval;
3115 mbx_cmd_t mc;
3116 mbx_cmd_t *mcp = &mc;
7b867cf7 3117 struct qla_hw_data *ha = vha->hw;
1c7c6357 3118
68af0811 3119 if (!IS_QLA23XX(ha) && !IS_FWI2_CAPABLE(ha))
1c7c6357
AV		 3120 return QLA_FUNCTION_FAILED;
3121
5f28d2d7
SK		 3122 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x109b,
3123 "Entered %s.\n", __func__);
1c7c6357
AV		 3124
3125 mcp->mb[0] = MBC_GEN_SYSTEM_ERROR;
3126 mcp->out_mb = MBX_0;
3127 mcp->in_mb = MBX_0;
3128 mcp->tov = 5;
3129 mcp->flags = 0;
7b867cf7 3130 rval = qla2x00_mailbox_command(vha, mcp);
1c7c6357
AV		 3131
3132 if (rval != QLA_SUCCESS) {
7c3df132 3133 ql_dbg(ql_dbg_mbx, vha, 0x109c, "Failed=%x.\n", rval);
1c7c6357 3134 } else {
5f28d2d7
SK		 3135 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x109d,
3136 "Done %s.\n", __func__);
1c7c6357
AV		 3137 }
3138
3139 return rval;
3140}
3141
db64e930
JC		 3142int
3143qla2x00_write_serdes_word(scsi_qla_host_t *vha, uint16_t addr, uint16_t data)
3144{
3145 int rval;
3146 mbx_cmd_t mc;
3147 mbx_cmd_t *mcp = &mc;
3148
f299c7c2
JC		 3149 if (!IS_QLA25XX(vha->hw) && !IS_QLA2031(vha->hw) &&
3150 !IS_QLA27XX(vha->hw))
db64e930
JC		 3151 return QLA_FUNCTION_FAILED;
3152
3153 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1182,
3154 "Entered %s.\n", __func__);
3155
3156 mcp->mb[0] = MBC_WRITE_SERDES;
3157 mcp->mb[1] = addr;
064135e0
AV		 3158 if (IS_QLA2031(vha->hw))
3159 mcp->mb[2] = data & 0xff;
3160 else
3161 mcp->mb[2] = data;
3162
db64e930
JC		 3163 mcp->mb[3] = 0;
3164 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
3165 mcp->in_mb = MBX_0;
3166 mcp->tov = MBX_TOV_SECONDS;
3167 mcp->flags = 0;
3168 rval = qla2x00_mailbox_command(vha, mcp);
3169
3170 if (rval != QLA_SUCCESS) {
3171 ql_dbg(ql_dbg_mbx, vha, 0x1183,
3172 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
3173 } else {
3174 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1184,
3175 "Done %s.\n", __func__);
3176 }
3177
3178 return rval;
3179}
3180
3181int
3182qla2x00_read_serdes_word(scsi_qla_host_t *vha, uint16_t addr, uint16_t *data)
3183{
3184 int rval;
3185 mbx_cmd_t mc;
3186 mbx_cmd_t *mcp = &mc;
3187
f299c7c2
JC		 3188 if (!IS_QLA25XX(vha->hw) && !IS_QLA2031(vha->hw) &&
3189 !IS_QLA27XX(vha->hw))
db64e930
JC		 3190 return QLA_FUNCTION_FAILED;
3191
3192 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1185,
3193 "Entered %s.\n", __func__);
3194
3195 mcp->mb[0] = MBC_READ_SERDES;
3196 mcp->mb[1] = addr;
3197 mcp->mb[3] = 0;
3198 mcp->out_mb = MBX_3|MBX_1|MBX_0;
3199 mcp->in_mb = MBX_1|MBX_0;
3200 mcp->tov = MBX_TOV_SECONDS;
3201 mcp->flags = 0;
3202 rval = qla2x00_mailbox_command(vha, mcp);
3203
064135e0
AV		 3204 if (IS_QLA2031(vha->hw))
3205 *data = mcp->mb[1] & 0xff;
3206 else
3207 *data = mcp->mb[1];
db64e930
JC		 3208
3209 if (rval != QLA_SUCCESS) {
3210 ql_dbg(ql_dbg_mbx, vha, 0x1186,
3211 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
3212 } else {
3213 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1187,
3214 "Done %s.\n", __func__);
3215 }
3216
3217 return rval;
3218}
3219
e8887c51
JC		 3220int
3221qla8044_write_serdes_word(scsi_qla_host_t *vha, uint32_t addr, uint32_t data)
3222{
3223 int rval;
3224 mbx_cmd_t mc;
3225 mbx_cmd_t *mcp = &mc;
3226
3227 if (!IS_QLA8044(vha->hw))
3228 return QLA_FUNCTION_FAILED;
3229
83548fe2 3230 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x11a0,
e8887c51
JC		 3231 "Entered %s.\n", __func__);
3232
3233 mcp->mb[0] = MBC_SET_GET_ETH_SERDES_REG;
3234 mcp->mb[1] = HCS_WRITE_SERDES;
3235 mcp->mb[3] = LSW(addr);
3236 mcp->mb[4] = MSW(addr);
3237 mcp->mb[5] = LSW(data);
3238 mcp->mb[6] = MSW(data);
3239 mcp->out_mb = MBX_6|MBX_5|MBX_4|MBX_3|MBX_1|MBX_0;
3240 mcp->in_mb = MBX_0;
3241 mcp->tov = MBX_TOV_SECONDS;
3242 mcp->flags = 0;
3243 rval = qla2x00_mailbox_command(vha, mcp);
3244
3245 if (rval != QLA_SUCCESS) {
83548fe2 3246 ql_dbg(ql_dbg_mbx, vha, 0x11a1,
e8887c51
JC		 3247 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
3248 } else {
3249 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1188,
3250 "Done %s.\n", __func__);
3251 }
3252
3253 return rval;
3254}
3255
3256int
3257qla8044_read_serdes_word(scsi_qla_host_t *vha, uint32_t addr, uint32_t *data)
3258{
3259 int rval;
3260 mbx_cmd_t mc;
3261 mbx_cmd_t *mcp = &mc;
3262
3263 if (!IS_QLA8044(vha->hw))
3264 return QLA_FUNCTION_FAILED;
3265
3266 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1189,
3267 "Entered %s.\n", __func__);
3268
3269 mcp->mb[0] = MBC_SET_GET_ETH_SERDES_REG;
3270 mcp->mb[1] = HCS_READ_SERDES;
3271 mcp->mb[3] = LSW(addr);
3272 mcp->mb[4] = MSW(addr);
3273 mcp->out_mb = MBX_4|MBX_3|MBX_1|MBX_0;
3274 mcp->in_mb = MBX_2|MBX_1|MBX_0;
3275 mcp->tov = MBX_TOV_SECONDS;
3276 mcp->flags = 0;
3277 rval = qla2x00_mailbox_command(vha, mcp);
3278
3279 *data = mcp->mb[2] << 16 | mcp->mb[1];
3280
3281 if (rval != QLA_SUCCESS) {
3282 ql_dbg(ql_dbg_mbx, vha, 0x118a,
3283 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
3284 } else {
3285 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x118b,
3286 "Done %s.\n", __func__);
3287 }
3288
3289 return rval;
3290}
3291
1c7c6357
AV		 3292/**
3293 * qla2x00_set_serdes_params() -
3294 * @ha: HA context
3295 *
3296 * Returns
3297 */
3298int
7b867cf7 3299qla2x00_set_serdes_params(scsi_qla_host_t *vha, uint16_t sw_em_1g,
1c7c6357
AV		 3300 uint16_t sw_em_2g, uint16_t sw_em_4g)
3301{
3302 int rval;
3303 mbx_cmd_t mc;
3304 mbx_cmd_t *mcp = &mc;
3305
5f28d2d7
SK		 3306 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x109e,
3307 "Entered %s.\n", __func__);
1c7c6357
AV		 3308
3309 mcp->mb[0] = MBC_SERDES_PARAMS;
3310 mcp->mb[1] = BIT_0;
fdbc6833 3311 mcp->mb[2] = sw_em_1g | BIT_15;
3312 mcp->mb[3] = sw_em_2g | BIT_15;
3313 mcp->mb[4] = sw_em_4g | BIT_15;
1c7c6357
AV		 3314 mcp->out_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
3315 mcp->in_mb = MBX_0;
b93480e3 3316 mcp->tov = MBX_TOV_SECONDS;
1c7c6357 3317 mcp->flags = 0;
7b867cf7 3318 rval = qla2x00_mailbox_command(vha, mcp);
1c7c6357
AV		 3319
3320 if (rval != QLA_SUCCESS) {
3321 /*EMPTY*/
7c3df132
SK		 3322 ql_dbg(ql_dbg_mbx, vha, 0x109f,
3323 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
1c7c6357
AV		 3324 } else {
3325 /*EMPTY*/
5f28d2d7
SK		 3326 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a0,
3327 "Done %s.\n", __func__);
1c7c6357
AV		 3328 }
3329
3330 return rval;
3331}
f6ef3b18
AV		 3332
3333int
7b867cf7 3334qla2x00_stop_firmware(scsi_qla_host_t *vha)
f6ef3b18
AV		 3335{
3336 int rval;
3337 mbx_cmd_t mc;
3338 mbx_cmd_t *mcp = &mc;
3339
7b867cf7 3340 if (!IS_FWI2_CAPABLE(vha->hw))
f6ef3b18
AV		 3341 return QLA_FUNCTION_FAILED;
3342
5f28d2d7
SK		 3343 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a1,
3344 "Entered %s.\n", __func__);
f6ef3b18
AV		 3345
3346 mcp->mb[0] = MBC_STOP_FIRMWARE;
4ba988db
AV		 3347 mcp->mb[1] = 0;
3348 mcp->out_mb = MBX_1|MBX_0;
f6ef3b18
AV		 3349 mcp->in_mb = MBX_0;
3350 mcp->tov = 5;
3351 mcp->flags = 0;
7b867cf7 3352 rval = qla2x00_mailbox_command(vha, mcp);
f6ef3b18
AV		 3353
3354 if (rval != QLA_SUCCESS) {
7c3df132 3355 ql_dbg(ql_dbg_mbx, vha, 0x10a2, "Failed=%x.\n", rval);
b469a7cb
AV		 3356 if (mcp->mb[0] == MBS_INVALID_COMMAND)
3357 rval = QLA_INVALID_COMMAND;
f6ef3b18 3358 } else {
5f28d2d7
SK		 3359 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a3,
3360 "Done %s.\n", __func__);
f6ef3b18
AV		 3361 }
3362
3363 return rval;
3364}
a7a167bf
AV		 3365
3366int
7b867cf7 3367qla2x00_enable_eft_trace(scsi_qla_host_t *vha, dma_addr_t eft_dma,
a7a167bf
AV		 3368 uint16_t buffers)
3369{
3370 int rval;
3371 mbx_cmd_t mc;
3372 mbx_cmd_t *mcp = &mc;
3373
5f28d2d7
SK		 3374 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a4,
3375 "Entered %s.\n", __func__);
7c3df132 3376
7b867cf7 3377 if (!IS_FWI2_CAPABLE(vha->hw))
a7a167bf
AV		 3378 return QLA_FUNCTION_FAILED;
3379
85880801
AV		 3380 if (unlikely(pci_channel_offline(vha->hw->pdev)))
3381 return QLA_FUNCTION_FAILED;
3382
a7a167bf 3383 mcp->mb[0] = MBC_TRACE_CONTROL;
00b6bd25
AV		 3384 mcp->mb[1] = TC_EFT_ENABLE;
3385 mcp->mb[2] = LSW(eft_dma);
3386 mcp->mb[3] = MSW(eft_dma);
3387 mcp->mb[4] = LSW(MSD(eft_dma));
3388 mcp->mb[5] = MSW(MSD(eft_dma));
3389 mcp->mb[6] = buffers;
3390 mcp->mb[7] = TC_AEN_DISABLE;
3391 mcp->out_mb = MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
a7a167bf 3392 mcp->in_mb = MBX_1|MBX_0;
b93480e3 3393 mcp->tov = MBX_TOV_SECONDS;
a7a167bf 3394 mcp->flags = 0;
7b867cf7 3395 rval = qla2x00_mailbox_command(vha, mcp);
00b6bd25 3396 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3397 ql_dbg(ql_dbg_mbx, vha, 0x10a5,
3398 "Failed=%x mb[0]=%x mb[1]=%x.\n",
3399 rval, mcp->mb[0], mcp->mb[1]);
00b6bd25 3400 } else {
5f28d2d7
SK		 3401 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a6,
3402 "Done %s.\n", __func__);
00b6bd25
AV		 3403 }
3404
3405 return rval;
3406}
a7a167bf 3407
00b6bd25 3408int
7b867cf7 3409qla2x00_disable_eft_trace(scsi_qla_host_t *vha)
00b6bd25
AV		 3410{
3411 int rval;
3412 mbx_cmd_t mc;
3413 mbx_cmd_t *mcp = &mc;
3414
5f28d2d7
SK		 3415 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a7,
3416 "Entered %s.\n", __func__);
7c3df132 3417
7b867cf7 3418 if (!IS_FWI2_CAPABLE(vha->hw))
00b6bd25
AV		 3419 return QLA_FUNCTION_FAILED;
3420
85880801
AV		 3421 if (unlikely(pci_channel_offline(vha->hw->pdev)))
3422 return QLA_FUNCTION_FAILED;
3423
00b6bd25
AV		 3424 mcp->mb[0] = MBC_TRACE_CONTROL;
3425 mcp->mb[1] = TC_EFT_DISABLE;
3426 mcp->out_mb = MBX_1|MBX_0;
3427 mcp->in_mb = MBX_1|MBX_0;
b93480e3 3428 mcp->tov = MBX_TOV_SECONDS;
00b6bd25 3429 mcp->flags = 0;
7b867cf7 3430 rval = qla2x00_mailbox_command(vha, mcp);
a7a167bf 3431 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3432 ql_dbg(ql_dbg_mbx, vha, 0x10a8,
3433 "Failed=%x mb[0]=%x mb[1]=%x.\n",
3434 rval, mcp->mb[0], mcp->mb[1]);
a7a167bf 3435 } else {
5f28d2d7
SK		 3436 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a9,
3437 "Done %s.\n", __func__);
a7a167bf
AV		 3438 }
3439
3440 return rval;
3441}
3442
df613b96 3443int
7b867cf7 3444qla2x00_enable_fce_trace(scsi_qla_host_t *vha, dma_addr_t fce_dma,
df613b96
AV		 3445 uint16_t buffers, uint16_t *mb, uint32_t *dwords)
3446{
3447 int rval;
3448 mbx_cmd_t mc;
3449 mbx_cmd_t *mcp = &mc;
3450
5f28d2d7
SK		 3451 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10aa,
3452 "Entered %s.\n", __func__);
7c3df132 3453
6246b8a1 3454 if (!IS_QLA25XX(vha->hw) && !IS_QLA81XX(vha->hw) &&
f73cb695 3455 !IS_QLA83XX(vha->hw) && !IS_QLA27XX(vha->hw))
df613b96
AV		 3456 return QLA_FUNCTION_FAILED;
3457
85880801
AV		 3458 if (unlikely(pci_channel_offline(vha->hw->pdev)))
3459 return QLA_FUNCTION_FAILED;
3460
df613b96
AV		 3461 mcp->mb[0] = MBC_TRACE_CONTROL;
3462 mcp->mb[1] = TC_FCE_ENABLE;
3463 mcp->mb[2] = LSW(fce_dma);
3464 mcp->mb[3] = MSW(fce_dma);
3465 mcp->mb[4] = LSW(MSD(fce_dma));
3466 mcp->mb[5] = MSW(MSD(fce_dma));
3467 mcp->mb[6] = buffers;
3468 mcp->mb[7] = TC_AEN_DISABLE;
3469 mcp->mb[8] = 0;
3470 mcp->mb[9] = TC_FCE_DEFAULT_RX_SIZE;
3471 mcp->mb[10] = TC_FCE_DEFAULT_TX_SIZE;
3472 mcp->out_mb = MBX_10|MBX_9|MBX_8|MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|
3473 MBX_1|MBX_0;
3474 mcp->in_mb = MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
b93480e3 3475 mcp->tov = MBX_TOV_SECONDS;
df613b96 3476 mcp->flags = 0;
7b867cf7 3477 rval = qla2x00_mailbox_command(vha, mcp);
df613b96 3478 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3479 ql_dbg(ql_dbg_mbx, vha, 0x10ab,
3480 "Failed=%x mb[0]=%x mb[1]=%x.\n",
3481 rval, mcp->mb[0], mcp->mb[1]);
df613b96 3482 } else {
5f28d2d7
SK		 3483 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ac,
3484 "Done %s.\n", __func__);
df613b96
AV		 3485
3486 if (mb)
3487 memcpy(mb, mcp->mb, 8 * sizeof(*mb));
3488 if (dwords)
fa0926df 3489 *dwords = buffers;
df613b96
AV		 3490 }
3491
3492 return rval;
3493}
3494
3495int
7b867cf7 3496qla2x00_disable_fce_trace(scsi_qla_host_t *vha, uint64_t *wr, uint64_t *rd)
df613b96
AV		 3497{
3498 int rval;
3499 mbx_cmd_t mc;
3500 mbx_cmd_t *mcp = &mc;
3501
5f28d2d7
SK		 3502 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ad,
3503 "Entered %s.\n", __func__);
7c3df132 3504
7b867cf7 3505 if (!IS_FWI2_CAPABLE(vha->hw))
df613b96
AV		 3506 return QLA_FUNCTION_FAILED;
3507
85880801
AV		 3508 if (unlikely(pci_channel_offline(vha->hw->pdev)))
3509 return QLA_FUNCTION_FAILED;
3510
df613b96
AV		 3511 mcp->mb[0] = MBC_TRACE_CONTROL;
3512 mcp->mb[1] = TC_FCE_DISABLE;
3513 mcp->mb[2] = TC_FCE_DISABLE_TRACE;
3514 mcp->out_mb = MBX_2|MBX_1|MBX_0;
3515 mcp->in_mb = MBX_9|MBX_8|MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|
3516 MBX_1|MBX_0;
b93480e3 3517 mcp->tov = MBX_TOV_SECONDS;
df613b96 3518 mcp->flags = 0;
7b867cf7 3519 rval = qla2x00_mailbox_command(vha, mcp);
df613b96 3520 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3521 ql_dbg(ql_dbg_mbx, vha, 0x10ae,
3522 "Failed=%x mb[0]=%x mb[1]=%x.\n",
3523 rval, mcp->mb[0], mcp->mb[1]);
df613b96 3524 } else {
5f28d2d7
SK		 3525 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10af,
3526 "Done %s.\n", __func__);
df613b96
AV		 3527
3528 if (wr)
3529 *wr = (uint64_t) mcp->mb[5] << 48 |
3530 (uint64_t) mcp->mb[4] << 32 |
3531 (uint64_t) mcp->mb[3] << 16 |
3532 (uint64_t) mcp->mb[2];
3533 if (rd)
3534 *rd = (uint64_t) mcp->mb[9] << 48 |
3535 (uint64_t) mcp->mb[8] << 32 |
3536 (uint64_t) mcp->mb[7] << 16 |
3537 (uint64_t) mcp->mb[6];
3538 }
3539
3540 return rval;
3541}
3542
6e98016c
GM		 3543int
3544qla2x00_get_idma_speed(scsi_qla_host_t *vha, uint16_t loop_id,
3545 uint16_t *port_speed, uint16_t *mb)
3546{
3547 int rval;
3548 mbx_cmd_t mc;
3549 mbx_cmd_t *mcp = &mc;
3550
5f28d2d7
SK		 3551 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b0,
3552 "Entered %s.\n", __func__);
7c3df132 3553
6e98016c
GM		 3554 if (!IS_IIDMA_CAPABLE(vha->hw))
3555 return QLA_FUNCTION_FAILED;
3556
6e98016c
GM		 3557 mcp->mb[0] = MBC_PORT_PARAMS;
3558 mcp->mb[1] = loop_id;
3559 mcp->mb[2] = mcp->mb[3] = 0;
3560 mcp->mb[9] = vha->vp_idx;
3561 mcp->out_mb = MBX_9|MBX_3|MBX_2|MBX_1|MBX_0;
3562 mcp->in_mb = MBX_3|MBX_1|MBX_0;
3563 mcp->tov = MBX_TOV_SECONDS;
3564 mcp->flags = 0;
3565 rval = qla2x00_mailbox_command(vha, mcp);
3566
3567 /* Return mailbox statuses. */
3568 if (mb != NULL) {
3569 mb[0] = mcp->mb[0];
3570 mb[1] = mcp->mb[1];
3571 mb[3] = mcp->mb[3];
3572 }
3573
3574 if (rval != QLA_SUCCESS) {
7c3df132 3575 ql_dbg(ql_dbg_mbx, vha, 0x10b1, "Failed=%x.\n", rval);
6e98016c 3576 } else {
5f28d2d7
SK		 3577 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b2,
3578 "Done %s.\n", __func__);
6e98016c
GM		 3579 if (port_speed)
3580 *port_speed = mcp->mb[3];
3581 }
3582
3583 return rval;
3584}
3585
d8b45213 3586int
7b867cf7 3587qla2x00_set_idma_speed(scsi_qla_host_t *vha, uint16_t loop_id,
d8b45213
AV		 3588 uint16_t port_speed, uint16_t *mb)
3589{
3590 int rval;
3591 mbx_cmd_t mc;
3592 mbx_cmd_t *mcp = &mc;
3593
5f28d2d7
SK		 3594 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b3,
3595 "Entered %s.\n", __func__);
7c3df132 3596
7b867cf7 3597 if (!IS_IIDMA_CAPABLE(vha->hw))
d8b45213
AV		 3598 return QLA_FUNCTION_FAILED;
3599
d8b45213
AV		 3600 mcp->mb[0] = MBC_PORT_PARAMS;
3601 mcp->mb[1] = loop_id;
3602 mcp->mb[2] = BIT_0;
6246b8a1 3603 if (IS_CNA_CAPABLE(vha->hw))
1bb39548
HZ		 3604 mcp->mb[3] = port_speed & (BIT_5|BIT_4|BIT_3|BIT_2|BIT_1|BIT_0);
3605 else
3606 mcp->mb[3] = port_speed & (BIT_2|BIT_1|BIT_0);
3607 mcp->mb[9] = vha->vp_idx;
3608 mcp->out_mb = MBX_9|MBX_3|MBX_2|MBX_1|MBX_0;
3609 mcp->in_mb = MBX_3|MBX_1|MBX_0;
b93480e3 3610 mcp->tov = MBX_TOV_SECONDS;
d8b45213 3611 mcp->flags = 0;
7b867cf7 3612 rval = qla2x00_mailbox_command(vha, mcp);
d8b45213
AV		 3613
3614 /* Return mailbox statuses. */
3615 if (mb != NULL) {
3616 mb[0] = mcp->mb[0];
3617 mb[1] = mcp->mb[1];
3618 mb[3] = mcp->mb[3];
d8b45213
AV		 3619 }
3620
3621 if (rval != QLA_SUCCESS) {
5f28d2d7
SK		 3622 ql_dbg(ql_dbg_mbx, vha, 0x10b4,
3623 "Failed=%x.\n", rval);
d8b45213 3624 } else {
5f28d2d7
SK		 3625 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b5,
3626 "Done %s.\n", __func__);
d8b45213
AV		 3627 }
3628
3629 return rval;
3630}
2c3dfe3f 3631
2c3dfe3f 3632void
7b867cf7 3633qla24xx_report_id_acquisition(scsi_qla_host_t *vha,
2c3dfe3f
SJ		 3634 struct vp_rpt_id_entry_24xx *rptid_entry)
3635{
7b867cf7 3636 struct qla_hw_data *ha = vha->hw;
41dc529a 3637 scsi_qla_host_t *vp = NULL;
feafb7b1 3638 unsigned long flags;
4ac8d4ca 3639 int found;
482c9dc7 3640 port_id_t id;
2c3dfe3f 3641
5f28d2d7
SK		 3642 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b6,
3643 "Entered %s.\n", __func__);
7c3df132 3644
2c3dfe3f
SJ		 3645 if (rptid_entry->entry_status != 0)
3646 return;
2c3dfe3f 3647
482c9dc7
QT		 3648 id.b.domain = rptid_entry->port_id[2];
3649 id.b.area = rptid_entry->port_id[1];
3650 id.b.al_pa = rptid_entry->port_id[0];
3651 id.b.rsvd_1 = 0;
3652
2c3dfe3f 3653 if (rptid_entry->format == 0) {
41dc529a 3654 /* loop */
ec7193e2 3655 ql_dbg(ql_dbg_async, vha, 0x10b7,
7c3df132 3656 "Format 0 : Number of VPs setup %d, number of "
41dc529a
QT		 3657 "VPs acquired %d.\n", rptid_entry->vp_setup,
3658 rptid_entry->vp_acquired);
ec7193e2 3659 ql_dbg(ql_dbg_async, vha, 0x10b8,
7c3df132
SK		 3660 "Primary port id %02x%02x%02x.\n",
3661 rptid_entry->port_id[2], rptid_entry->port_id[1],
3662 rptid_entry->port_id[0]);
41dc529a 3663
482c9dc7 3664 qlt_update_host_map(vha, id);
41dc529a 3665
2c3dfe3f 3666 } else if (rptid_entry->format == 1) {
41dc529a 3667 /* fabric */
ec7193e2 3668 ql_dbg(ql_dbg_async, vha, 0x10b9,
7c3df132 3669 "Format 1: VP[%d] enabled - status %d - with "
41dc529a
QT		 3670 "port id %02x%02x%02x.\n", rptid_entry->vp_idx,
3671 rptid_entry->vp_status,
2c3dfe3f 3672 rptid_entry->port_id[2], rptid_entry->port_id[1],
7c3df132 3673 rptid_entry->port_id[0]);
531a82d1 3674
969a6199 3675 /* buffer to buffer credit flag */
41dc529a
QT		 3676 vha->flags.bbcr_enable = (rptid_entry->u.f1.bbcr & 0xf) != 0;
3677
3678 if (rptid_entry->vp_idx == 0) {
3679 if (rptid_entry->vp_status == VP_STAT_COMPL) {
3680 /* FA-WWN is only for physical port */
3681 if (qla_ini_mode_enabled(vha) &&
3682 ha->flags.fawwpn_enabled &&
3683 (rptid_entry->u.f1.flags &
3684 VP_FLAGS_NAME_VALID)) {
3685 memcpy(vha->port_name,
3686 rptid_entry->u.f1.port_name,
3687 WWN_SIZE);
3688 }
7c9c4766 3689
482c9dc7 3690 qlt_update_host_map(vha, id);
7c9c4766 3691 }
41dc529a 3692
41dc529a
QT		 3693 set_bit(REGISTER_FC4_NEEDED, &vha->dpc_flags);
3694 set_bit(REGISTER_FDMI_NEEDED, &vha->dpc_flags);
3695 } else {
3696 if (rptid_entry->vp_status != VP_STAT_COMPL &&
3697 rptid_entry->vp_status != VP_STAT_ID_CHG) {
3698 ql_dbg(ql_dbg_mbx, vha, 0x10ba,
3699 "Could not acquire ID for VP[%d].\n",
3700 rptid_entry->vp_idx);
3701 return;
4ac8d4ca 3702 }
feafb7b1 3703
41dc529a
QT		 3704 found = 0;
3705 spin_lock_irqsave(&ha->vport_slock, flags);
3706 list_for_each_entry(vp, &ha->vp_list, list) {
3707 if (rptid_entry->vp_idx == vp->vp_idx) {
3708 found = 1;
3709 break;
3710 }
3711 }
3712 spin_unlock_irqrestore(&ha->vport_slock, flags);
2c3dfe3f 3713
41dc529a
QT		 3714 if (!found)
3715 return;
2c3dfe3f 3716
482c9dc7 3717 qlt_update_host_map(vp, id);
2c3dfe3f 3718
41dc529a
QT		 3719 /*
3720 * Cannot configure here as we are still sitting on the
3721 * response queue. Handle it in dpc context.
3722 */
3723 set_bit(VP_IDX_ACQUIRED, &vp->vp_flags);
3724 set_bit(REGISTER_FC4_NEEDED, &vp->dpc_flags);
3725 set_bit(REGISTER_FDMI_NEEDED, &vp->dpc_flags);
3726 }
531a82d1 3727 set_bit(VP_DPC_NEEDED, &vha->dpc_flags);
7b867cf7 3728 qla2xxx_wake_dpc(vha);
41dc529a 3729 } else if (rptid_entry->format == 2) {
83548fe2 3730 ql_dbg(ql_dbg_async, vha, 0x505f,
41dc529a
QT		 3731 "RIDA: format 2/N2N Primary port id %02x%02x%02x.\n",
3732 rptid_entry->port_id[2], rptid_entry->port_id[1],
3733 rptid_entry->port_id[0]);
3734
83548fe2 3735 ql_dbg(ql_dbg_async, vha, 0x5075,
41dc529a
QT		 3736 "N2N: Remote WWPN %8phC.\n",
3737 rptid_entry->u.f2.port_name);
3738
3739 /* N2N. direct connect */
3740 vha->d_id.b.domain = rptid_entry->port_id[2];
3741 vha->d_id.b.area = rptid_entry->port_id[1];
3742 vha->d_id.b.al_pa = rptid_entry->port_id[0];
3743
3744 spin_lock_irqsave(&ha->vport_slock, flags);
3745 qlt_update_vp_map(vha, SET_AL_PA);
3746 spin_unlock_irqrestore(&ha->vport_slock, flags);
2c3dfe3f
SJ		 3747 }
3748}
3749
3750/*
3751 * qla24xx_modify_vp_config
3752 * Change VP configuration for vha
3753 *
3754 * Input:
3755 * vha = adapter block pointer.
3756 *
3757 * Returns:
3758 * qla2xxx local function return status code.
3759 *
3760 * Context:
3761 * Kernel context.
3762 */
3763int
3764qla24xx_modify_vp_config(scsi_qla_host_t *vha)
3765{
3766 int rval;
3767 struct vp_config_entry_24xx *vpmod;
3768 dma_addr_t vpmod_dma;
7b867cf7
AC		 3769 struct qla_hw_data *ha = vha->hw;
3770 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
2c3dfe3f
SJ		 3771
3772 /* This can be called by the parent */
2c3dfe3f 3773
5f28d2d7
SK		 3774 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10bb,
3775 "Entered %s.\n", __func__);
7c3df132 3776
7b867cf7 3777 vpmod = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &vpmod_dma);
2c3dfe3f 3778 if (!vpmod) {
7c3df132
SK		 3779 ql_log(ql_log_warn, vha, 0x10bc,
3780 "Failed to allocate modify VP IOCB.\n");
2c3dfe3f
SJ		 3781 return QLA_MEMORY_ALLOC_FAILED;
3782 }
3783
3784 memset(vpmod, 0, sizeof(struct vp_config_entry_24xx));
3785 vpmod->entry_type = VP_CONFIG_IOCB_TYPE;
3786 vpmod->entry_count = 1;
3787 vpmod->command = VCT_COMMAND_MOD_ENABLE_VPS;
3788 vpmod->vp_count = 1;
3789 vpmod->vp_index1 = vha->vp_idx;
3790 vpmod->options_idx1 = BIT_3|BIT_4|BIT_5;
2d70c103
NB		 3791
3792 qlt_modify_vp_config(vha, vpmod);
3793
2c3dfe3f
SJ		 3794 memcpy(vpmod->node_name_idx1, vha->node_name, WWN_SIZE);
3795 memcpy(vpmod->port_name_idx1, vha->port_name, WWN_SIZE);
3796 vpmod->entry_count = 1;
3797
7b867cf7 3798 rval = qla2x00_issue_iocb(base_vha, vpmod, vpmod_dma, 0);
2c3dfe3f 3799 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3800 ql_dbg(ql_dbg_mbx, vha, 0x10bd,
3801 "Failed to issue VP config IOCB (%x).\n", rval);
2c3dfe3f 3802 } else if (vpmod->comp_status != 0) {
7c3df132
SK		 3803 ql_dbg(ql_dbg_mbx, vha, 0x10be,
3804 "Failed to complete IOCB -- error status (%x).\n",
3805 vpmod->comp_status);
2c3dfe3f 3806 rval = QLA_FUNCTION_FAILED;
ad950360 3807 } else if (vpmod->comp_status != cpu_to_le16(CS_COMPLETE)) {
7c3df132
SK		 3808 ql_dbg(ql_dbg_mbx, vha, 0x10bf,
3809 "Failed to complete IOCB -- completion status (%x).\n",
3810 le16_to_cpu(vpmod->comp_status));
2c3dfe3f
SJ		 3811 rval = QLA_FUNCTION_FAILED;
3812 } else {
3813 /* EMPTY */
5f28d2d7
SK		 3814 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10c0,
3815 "Done %s.\n", __func__);
2c3dfe3f
SJ		 3816 fc_vport_set_state(vha->fc_vport, FC_VPORT_INITIALIZING);
3817 }
7b867cf7 3818 dma_pool_free(ha->s_dma_pool, vpmod, vpmod_dma);
2c3dfe3f
SJ		 3819
3820 return rval;
3821}
3822
3823/*
3824 * qla24xx_control_vp
3825 * Enable a virtual port for given host
3826 *
3827 * Input:
3828 * ha = adapter block pointer.
3829 * vhba = virtual adapter (unused)
3830 * index = index number for enabled VP
3831 *
3832 * Returns:
3833 * qla2xxx local function return status code.
3834 *
3835 * Context:
3836 * Kernel context.
3837 */
3838int
3839qla24xx_control_vp(scsi_qla_host_t *vha, int cmd)
3840{
3841 int rval;
3842 int map, pos;
3843 struct vp_ctrl_entry_24xx *vce;
3844 dma_addr_t vce_dma;
7b867cf7 3845 struct qla_hw_data *ha = vha->hw;
2c3dfe3f 3846 int vp_index = vha->vp_idx;
7b867cf7 3847 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
2c3dfe3f 3848
5f28d2d7 3849 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10c1,
7c3df132 3850 "Entered %s enabling index %d.\n", __func__, vp_index);
2c3dfe3f 3851
eb66dc60 3852 if (vp_index == 0 || vp_index >= ha->max_npiv_vports)
2c3dfe3f
SJ		 3853 return QLA_PARAMETER_ERROR;
3854
3855 vce = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &vce_dma);
3856 if (!vce) {
7c3df132
SK		 3857 ql_log(ql_log_warn, vha, 0x10c2,
3858 "Failed to allocate VP control IOCB.\n");
2c3dfe3f
SJ		 3859 return QLA_MEMORY_ALLOC_FAILED;
3860 }
3861 memset(vce, 0, sizeof(struct vp_ctrl_entry_24xx));
3862
3863 vce->entry_type = VP_CTRL_IOCB_TYPE;
3864 vce->entry_count = 1;
3865 vce->command = cpu_to_le16(cmd);
ad950360 3866 vce->vp_count = cpu_to_le16(1);
2c3dfe3f
SJ		 3867
3868 /* index map in firmware starts with 1; decrement index
3869 * this is ok as we never use index 0
3870 */
3871 map = (vp_index - 1) / 8;
3872 pos = (vp_index - 1) & 7;
6c2f527c 3873 mutex_lock(&ha->vport_lock);
2c3dfe3f 3874 vce->vp_idx_map[map] |= 1 << pos;
6c2f527c 3875 mutex_unlock(&ha->vport_lock);
2c3dfe3f 3876
7b867cf7 3877 rval = qla2x00_issue_iocb(base_vha, vce, vce_dma, 0);
2c3dfe3f 3878 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3879 ql_dbg(ql_dbg_mbx, vha, 0x10c3,
3880 "Failed to issue VP control IOCB (%x).\n", rval);
2c3dfe3f 3881 } else if (vce->entry_status != 0) {
7c3df132
SK		 3882 ql_dbg(ql_dbg_mbx, vha, 0x10c4,
3883 "Failed to complete IOCB -- error status (%x).\n",
2c3dfe3f
SJ		 3884 vce->entry_status);
3885 rval = QLA_FUNCTION_FAILED;
ad950360 3886 } else if (vce->comp_status != cpu_to_le16(CS_COMPLETE)) {
7c3df132 3887 ql_dbg(ql_dbg_mbx, vha, 0x10c5,
0bf0efa1 3888 "Failed to complete IOCB -- completion status (%x).\n",
2c3dfe3f
SJ		 3889 le16_to_cpu(vce->comp_status));
3890 rval = QLA_FUNCTION_FAILED;
3891 } else {
5f28d2d7
SK		 3892 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10c6,
3893 "Done %s.\n", __func__);
2c3dfe3f
SJ		 3894 }
3895
3896 dma_pool_free(ha->s_dma_pool, vce, vce_dma);
3897
3898 return rval;
3899}
3900
3901/*
3902 * qla2x00_send_change_request
3903 * Receive or disable RSCN request from fabric controller
3904 *
3905 * Input:
3906 * ha = adapter block pointer
3907 * format = registration format:
3908 * 0 - Reserved
3909 * 1 - Fabric detected registration
3910 * 2 - N_port detected registration
3911 * 3 - Full registration
3912 * FF - clear registration
3913 * vp_idx = Virtual port index
3914 *
3915 * Returns:
3916 * qla2x00 local function return status code.
3917 *
3918 * Context:
3919 * Kernel Context
3920 */
3921
3922int
7b867cf7 3923qla2x00_send_change_request(scsi_qla_host_t *vha, uint16_t format,
2c3dfe3f
SJ		 3924 uint16_t vp_idx)
3925{
3926 int rval;
3927 mbx_cmd_t mc;
3928 mbx_cmd_t *mcp = &mc;
3929
5f28d2d7
SK		 3930 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10c7,
3931 "Entered %s.\n", __func__);
7c3df132 3932
2c3dfe3f
SJ		 3933 mcp->mb[0] = MBC_SEND_CHANGE_REQUEST;
3934 mcp->mb[1] = format;
3935 mcp->mb[9] = vp_idx;
3936 mcp->out_mb = MBX_9|MBX_1|MBX_0;
3937 mcp->in_mb = MBX_0|MBX_1;
3938 mcp->tov = MBX_TOV_SECONDS;
3939 mcp->flags = 0;
7b867cf7 3940 rval = qla2x00_mailbox_command(vha, mcp);
2c3dfe3f
SJ		 3941
3942 if (rval == QLA_SUCCESS) {
3943 if (mcp->mb[0] != MBS_COMMAND_COMPLETE) {
3944 rval = BIT_1;
3945 }
3946 } else
3947 rval = BIT_1;
3948
3949 return rval;
3950}
338c9161
AV		 3951
3952int
7b867cf7 3953qla2x00_dump_ram(scsi_qla_host_t *vha, dma_addr_t req_dma, uint32_t addr,
338c9161
AV		 3954 uint32_t size)
3955{
3956 int rval;
3957 mbx_cmd_t mc;
3958 mbx_cmd_t *mcp = &mc;
3959
5f28d2d7
SK		 3960 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1009,
3961 "Entered %s.\n", __func__);
338c9161 3962
7b867cf7 3963 if (MSW(addr) || IS_FWI2_CAPABLE(vha->hw)) {
338c9161
AV		 3964 mcp->mb[0] = MBC_DUMP_RISC_RAM_EXTENDED;
3965 mcp->mb[8] = MSW(addr);
3966 mcp->out_mb = MBX_8|MBX_0;
3967 } else {
3968 mcp->mb[0] = MBC_DUMP_RISC_RAM;
3969 mcp->out_mb = MBX_0;
3970 }
3971 mcp->mb[1] = LSW(addr);
3972 mcp->mb[2] = MSW(req_dma);
3973 mcp->mb[3] = LSW(req_dma);
3974 mcp->mb[6] = MSW(MSD(req_dma));
3975 mcp->mb[7] = LSW(MSD(req_dma));
3976 mcp->out_mb |= MBX_7|MBX_6|MBX_3|MBX_2|MBX_1;
7b867cf7 3977 if (IS_FWI2_CAPABLE(vha->hw)) {
338c9161
AV		 3978 mcp->mb[4] = MSW(size);
3979 mcp->mb[5] = LSW(size);
3980 mcp->out_mb |= MBX_5|MBX_4;
3981 } else {
3982 mcp->mb[4] = LSW(size);
3983 mcp->out_mb |= MBX_4;
3984 }
3985
3986 mcp->in_mb = MBX_0;
b93480e3 3987 mcp->tov = MBX_TOV_SECONDS;
338c9161 3988 mcp->flags = 0;
7b867cf7 3989 rval = qla2x00_mailbox_command(vha, mcp);
338c9161
AV		 3990
3991 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3992 ql_dbg(ql_dbg_mbx, vha, 0x1008,
3993 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
338c9161 3994 } else {
5f28d2d7
SK		 3995 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1007,
3996 "Done %s.\n", __func__);
338c9161
AV		 3997 }
3998
3999 return rval;
4000}
4d4df193
HK		 4001/* 84XX Support **************************************************************/
4002
4003struct cs84xx_mgmt_cmd {
4004 union {
4005 struct verify_chip_entry_84xx req;
4006 struct verify_chip_rsp_84xx rsp;
4007 } p;
4008};
4009
4010int
7b867cf7 4011qla84xx_verify_chip(struct scsi_qla_host *vha, uint16_t *status)
4d4df193
HK		 4012{
4013 int rval, retry;
4014 struct cs84xx_mgmt_cmd *mn;
4015 dma_addr_t mn_dma;
4016 uint16_t options;
4017 unsigned long flags;
7b867cf7 4018 struct qla_hw_data *ha = vha->hw;
4d4df193 4019
5f28d2d7
SK		 4020 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10c8,
4021 "Entered %s.\n", __func__);
4d4df193
HK		 4022
4023 mn = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &mn_dma);
4024 if (mn == NULL) {
4d4df193
HK		 4025 return QLA_MEMORY_ALLOC_FAILED;
4026 }
4027
4028 /* Force Update? */
4029 options = ha->cs84xx->fw_update ? VCO_FORCE_UPDATE : 0;
4030 /* Diagnostic firmware? */
4031 /* options |= MENLO_DIAG_FW; */
4032 /* We update the firmware with only one data sequence. */
4033 options |= VCO_END_OF_DATA;
4034
4d4df193 4035 do {
c1ec1f1b 4036 retry = 0;
4d4df193
HK		 4037 memset(mn, 0, sizeof(*mn));
4038 mn->p.req.entry_type = VERIFY_CHIP_IOCB_TYPE;
4039 mn->p.req.entry_count = 1;
4040 mn->p.req.options = cpu_to_le16(options);
4041
7c3df132
SK		 4042 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x111c,
4043 "Dump of Verify Request.\n");
4044 ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x111e,
4045 (uint8_t *)mn, sizeof(*mn));
4d4df193 4046
7b867cf7 4047 rval = qla2x00_issue_iocb_timeout(vha, mn, mn_dma, 0, 120);
4d4df193 4048 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4049 ql_dbg(ql_dbg_mbx, vha, 0x10cb,
4050 "Failed to issue verify IOCB (%x).\n", rval);
4d4df193
HK		 4051 goto verify_done;
4052 }
4053
7c3df132
SK		 4054 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1110,
4055 "Dump of Verify Response.\n");
4056 ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1118,
4057 (uint8_t *)mn, sizeof(*mn));
4d4df193
HK		 4058
4059 status[0] = le16_to_cpu(mn->p.rsp.comp_status);
4060 status[1] = status[0] == CS_VCS_CHIP_FAILURE ?
4061 le16_to_cpu(mn->p.rsp.failure_code) : 0;
5f28d2d7 4062 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ce,
7c3df132 4063 "cs=%x fc=%x.\n", status[0], status[1]);
4d4df193
HK		 4064
4065 if (status[0] != CS_COMPLETE) {
4066 rval = QLA_FUNCTION_FAILED;
4067 if (!(options & VCO_DONT_UPDATE_FW)) {
7c3df132
SK		 4068 ql_dbg(ql_dbg_mbx, vha, 0x10cf,
4069 "Firmware update failed. Retrying "
4070 "without update firmware.\n");
4d4df193
HK		 4071 options |= VCO_DONT_UPDATE_FW;
4072 options &= ~VCO_FORCE_UPDATE;
4073 retry = 1;
4074 }
4075 } else {
5f28d2d7 4076 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d0,
7c3df132
SK		 4077 "Firmware updated to %x.\n",
4078 le32_to_cpu(mn->p.rsp.fw_ver));
4d4df193
HK		 4079
4080 /* NOTE: we only update OP firmware. */
4081 spin_lock_irqsave(&ha->cs84xx->access_lock, flags);
4082 ha->cs84xx->op_fw_version =
4083 le32_to_cpu(mn->p.rsp.fw_ver);
4084 spin_unlock_irqrestore(&ha->cs84xx->access_lock,
4085 flags);
4086 }
4087 } while (retry);
4088
4089verify_done:
4090 dma_pool_free(ha->s_dma_pool, mn, mn_dma);
4091
4092 if (rval != QLA_SUCCESS) {
5f28d2d7
SK		 4093 ql_dbg(ql_dbg_mbx, vha, 0x10d1,
4094 "Failed=%x.\n", rval);
4d4df193 4095 } else {
5f28d2d7
SK		 4096 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d2,
4097 "Done %s.\n", __func__);
4d4df193
HK		 4098 }
4099
4100 return rval;
4101}
73208dfd
AC		 4102
4103int
618a7523 4104qla25xx_init_req_que(struct scsi_qla_host *vha, struct req_que *req)
73208dfd
AC		 4105{
4106 int rval;
4107 unsigned long flags;
4108 mbx_cmd_t mc;
4109 mbx_cmd_t *mcp = &mc;
73208dfd
AC		 4110 struct qla_hw_data *ha = vha->hw;
4111
5f28d2d7
SK		 4112 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d3,
4113 "Entered %s.\n", __func__);
7c3df132 4114
7c6300e3
JC		 4115 if (IS_SHADOW_REG_CAPABLE(ha))
4116 req->options |= BIT_13;
4117
73208dfd 4118 mcp->mb[0] = MBC_INITIALIZE_MULTIQ;
618a7523 4119 mcp->mb[1] = req->options;
73208dfd
AC		 4120 mcp->mb[2] = MSW(LSD(req->dma));
4121 mcp->mb[3] = LSW(LSD(req->dma));
4122 mcp->mb[6] = MSW(MSD(req->dma));
4123 mcp->mb[7] = LSW(MSD(req->dma));
4124 mcp->mb[5] = req->length;
4125 if (req->rsp)
4126 mcp->mb[10] = req->rsp->id;
4127 mcp->mb[12] = req->qos;
4128 mcp->mb[11] = req->vp_idx;
4129 mcp->mb[13] = req->rid;
f73cb695 4130 if (IS_QLA83XX(ha) || IS_QLA27XX(ha))
6246b8a1 4131 mcp->mb[15] = 0;
73208dfd 4132
73208dfd
AC		 4133 mcp->mb[4] = req->id;
4134 /* que in ptr index */
4135 mcp->mb[8] = 0;
4136 /* que out ptr index */
7c6300e3 4137 mcp->mb[9] = *req->out_ptr = 0;
73208dfd
AC		 4138 mcp->out_mb = MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8|MBX_7|
4139 MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
4140 mcp->in_mb = MBX_0;
4141 mcp->flags = MBX_DMA_OUT;
6246b8a1
GM		 4142 mcp->tov = MBX_TOV_SECONDS * 2;
4143
f73cb695 4144 if (IS_QLA81XX(ha) || IS_QLA83XX(ha) || IS_QLA27XX(ha))
6246b8a1 4145 mcp->in_mb |= MBX_1;
ba4828b7 4146 if (IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
6246b8a1
GM		 4147 mcp->out_mb |= MBX_15;
4148 /* debug q create issue in SR-IOV */
4149 mcp->in_mb |= MBX_9 | MBX_8 | MBX_7;
4150 }
73208dfd
AC		 4151
4152 spin_lock_irqsave(&ha->hardware_lock, flags);
618a7523 4153 if (!(req->options & BIT_0)) {
da9b1d5c 4154 WRT_REG_DWORD(req->req_q_in, 0);
29db41c3 4155 if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha))
da9b1d5c 4156 WRT_REG_DWORD(req->req_q_out, 0);
73208dfd
AC		 4157 }
4158 spin_unlock_irqrestore(&ha->hardware_lock, flags);
4159
17d98630 4160 rval = qla2x00_mailbox_command(vha, mcp);
7c3df132
SK		 4161 if (rval != QLA_SUCCESS) {
4162 ql_dbg(ql_dbg_mbx, vha, 0x10d4,
4163 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
4164 } else {
5f28d2d7
SK		 4165 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d5,
4166 "Done %s.\n", __func__);
7c3df132
SK		 4167 }
4168
73208dfd
AC		 4169 return rval;
4170}
4171
4172int
618a7523 4173qla25xx_init_rsp_que(struct scsi_qla_host *vha, struct rsp_que *rsp)
73208dfd
AC		 4174{
4175 int rval;
4176 unsigned long flags;
4177 mbx_cmd_t mc;
4178 mbx_cmd_t *mcp = &mc;
73208dfd
AC		 4179 struct qla_hw_data *ha = vha->hw;
4180
5f28d2d7
SK		 4181 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d6,
4182 "Entered %s.\n", __func__);
7c3df132 4183
7c6300e3
JC		 4184 if (IS_SHADOW_REG_CAPABLE(ha))
4185 rsp->options |= BIT_13;
4186
73208dfd 4187 mcp->mb[0] = MBC_INITIALIZE_MULTIQ;
618a7523 4188 mcp->mb[1] = rsp->options;
73208dfd
AC		 4189 mcp->mb[2] = MSW(LSD(rsp->dma));
4190 mcp->mb[3] = LSW(LSD(rsp->dma));
4191 mcp->mb[6] = MSW(MSD(rsp->dma));
4192 mcp->mb[7] = LSW(MSD(rsp->dma));
4193 mcp->mb[5] = rsp->length;
444786d7 4194 mcp->mb[14] = rsp->msix->entry;
73208dfd 4195 mcp->mb[13] = rsp->rid;
f73cb695 4196 if (IS_QLA83XX(ha) || IS_QLA27XX(ha))
6246b8a1 4197 mcp->mb[15] = 0;
73208dfd 4198
73208dfd
AC		 4199 mcp->mb[4] = rsp->id;
4200 /* que in ptr index */
7c6300e3 4201 mcp->mb[8] = *rsp->in_ptr = 0;
73208dfd
AC		 4202 /* que out ptr index */
4203 mcp->mb[9] = 0;
2afa19a9 4204 mcp->out_mb = MBX_14|MBX_13|MBX_9|MBX_8|MBX_7
73208dfd
AC		 4205 |MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
4206 mcp->in_mb = MBX_0;
4207 mcp->flags = MBX_DMA_OUT;
6246b8a1
GM		 4208 mcp->tov = MBX_TOV_SECONDS * 2;
4209
4210 if (IS_QLA81XX(ha)) {
4211 mcp->out_mb |= MBX_12|MBX_11|MBX_10;
4212 mcp->in_mb |= MBX_1;
f73cb695 4213 } else if (IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
6246b8a1
GM		 4214 mcp->out_mb |= MBX_15|MBX_12|MBX_11|MBX_10;
4215 mcp->in_mb |= MBX_1;
4216 /* debug q create issue in SR-IOV */
4217 mcp->in_mb |= MBX_9 | MBX_8 | MBX_7;
4218 }
73208dfd
AC		 4219
4220 spin_lock_irqsave(&ha->hardware_lock, flags);
618a7523 4221 if (!(rsp->options & BIT_0)) {
da9b1d5c 4222 WRT_REG_DWORD(rsp->rsp_q_out, 0);
b20f02e1 4223 if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha))
da9b1d5c 4224 WRT_REG_DWORD(rsp->rsp_q_in, 0);
73208dfd
AC		 4225 }
4226
4227 spin_unlock_irqrestore(&ha->hardware_lock, flags);
4228
17d98630 4229 rval = qla2x00_mailbox_command(vha, mcp);
7c3df132
SK		 4230 if (rval != QLA_SUCCESS) {
4231 ql_dbg(ql_dbg_mbx, vha, 0x10d7,
4232 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
4233 } else {
5f28d2d7
SK		 4234 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d8,
4235 "Done %s.\n", __func__);
7c3df132
SK		 4236 }
4237
73208dfd
AC		 4238 return rval;
4239}
4240
8a659571
AV		 4241int
4242qla81xx_idc_ack(scsi_qla_host_t *vha, uint16_t *mb)
4243{
4244 int rval;
4245 mbx_cmd_t mc;
4246 mbx_cmd_t *mcp = &mc;
4247
5f28d2d7
SK		 4248 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d9,
4249 "Entered %s.\n", __func__);
8a659571
AV		 4250
4251 mcp->mb[0] = MBC_IDC_ACK;
4252 memcpy(&mcp->mb[1], mb, QLA_IDC_ACK_REGS * sizeof(uint16_t));
4253 mcp->out_mb = MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
4254 mcp->in_mb = MBX_0;
4255 mcp->tov = MBX_TOV_SECONDS;
4256 mcp->flags = 0;
4257 rval = qla2x00_mailbox_command(vha, mcp);
4258
4259 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4260 ql_dbg(ql_dbg_mbx, vha, 0x10da,
4261 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
8a659571 4262 } else {
5f28d2d7
SK		 4263 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10db,
4264 "Done %s.\n", __func__);
8a659571
AV		 4265 }
4266
4267 return rval;
4268}
1d2874de
JC		 4269
4270int
4271qla81xx_fac_get_sector_size(scsi_qla_host_t *vha, uint32_t *sector_size)
4272{
4273 int rval;
4274 mbx_cmd_t mc;
4275 mbx_cmd_t *mcp = &mc;
4276
5f28d2d7
SK		 4277 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10dc,
4278 "Entered %s.\n", __func__);
7c3df132 4279
f73cb695
CD		 4280 if (!IS_QLA81XX(vha->hw) && !IS_QLA83XX(vha->hw) &&
4281 !IS_QLA27XX(vha->hw))
1d2874de
JC		 4282 return QLA_FUNCTION_FAILED;
4283
1d2874de
JC		 4284 mcp->mb[0] = MBC_FLASH_ACCESS_CTRL;
4285 mcp->mb[1] = FAC_OPT_CMD_GET_SECTOR_SIZE;
4286 mcp->out_mb = MBX_1|MBX_0;
4287 mcp->in_mb = MBX_1|MBX_0;
4288 mcp->tov = MBX_TOV_SECONDS;
4289 mcp->flags = 0;
4290 rval = qla2x00_mailbox_command(vha, mcp);
4291
4292 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4293 ql_dbg(ql_dbg_mbx, vha, 0x10dd,
4294 "Failed=%x mb[0]=%x mb[1]=%x.\n",
4295 rval, mcp->mb[0], mcp->mb[1]);
1d2874de 4296 } else {
5f28d2d7
SK		 4297 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10de,
4298 "Done %s.\n", __func__);
1d2874de
JC		 4299 *sector_size = mcp->mb[1];
4300 }
4301
4302 return rval;
4303}
4304
4305int
4306qla81xx_fac_do_write_enable(scsi_qla_host_t *vha, int enable)
4307{
4308 int rval;
4309 mbx_cmd_t mc;
4310 mbx_cmd_t *mcp = &mc;
4311
f73cb695
CD		 4312 if (!IS_QLA81XX(vha->hw) && !IS_QLA83XX(vha->hw) &&
4313 !IS_QLA27XX(vha->hw))
1d2874de
JC		 4314 return QLA_FUNCTION_FAILED;
4315
5f28d2d7
SK		 4316 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10df,
4317 "Entered %s.\n", __func__);
1d2874de
JC		 4318
4319 mcp->mb[0] = MBC_FLASH_ACCESS_CTRL;
4320 mcp->mb[1] = enable ? FAC_OPT_CMD_WRITE_ENABLE :
4321 FAC_OPT_CMD_WRITE_PROTECT;
4322 mcp->out_mb = MBX_1|MBX_0;
4323 mcp->in_mb = MBX_1|MBX_0;
4324 mcp->tov = MBX_TOV_SECONDS;
4325 mcp->flags = 0;
4326 rval = qla2x00_mailbox_command(vha, mcp);
4327
4328 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4329 ql_dbg(ql_dbg_mbx, vha, 0x10e0,
4330 "Failed=%x mb[0]=%x mb[1]=%x.\n",
4331 rval, mcp->mb[0], mcp->mb[1]);
1d2874de 4332 } else {
5f28d2d7
SK		 4333 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e1,
4334 "Done %s.\n", __func__);
1d2874de
JC		 4335 }
4336
4337 return rval;
4338}
4339
4340int
4341qla81xx_fac_erase_sector(scsi_qla_host_t *vha, uint32_t start, uint32_t finish)
4342{
4343 int rval;
4344 mbx_cmd_t mc;
4345 mbx_cmd_t *mcp = &mc;
4346
f73cb695
CD		 4347 if (!IS_QLA81XX(vha->hw) && !IS_QLA83XX(vha->hw) &&
4348 !IS_QLA27XX(vha->hw))
1d2874de
JC		 4349 return QLA_FUNCTION_FAILED;
4350
5f28d2d7
SK		 4351 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e2,
4352 "Entered %s.\n", __func__);
1d2874de
JC		 4353
4354 mcp->mb[0] = MBC_FLASH_ACCESS_CTRL;
4355 mcp->mb[1] = FAC_OPT_CMD_ERASE_SECTOR;
4356 mcp->mb[2] = LSW(start);
4357 mcp->mb[3] = MSW(start);
4358 mcp->mb[4] = LSW(finish);
4359 mcp->mb[5] = MSW(finish);
4360 mcp->out_mb = MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
4361 mcp->in_mb = MBX_2|MBX_1|MBX_0;
4362 mcp->tov = MBX_TOV_SECONDS;
4363 mcp->flags = 0;
4364 rval = qla2x00_mailbox_command(vha, mcp);
4365
4366 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4367 ql_dbg(ql_dbg_mbx, vha, 0x10e3,
4368 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n",
4369 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]);
1d2874de 4370 } else {
5f28d2d7
SK		 4371 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e4,
4372 "Done %s.\n", __func__);
1d2874de
JC		 4373 }
4374
4375 return rval;
4376}
6e181be5
LC		 4377
4378int
4379qla81xx_restart_mpi_firmware(scsi_qla_host_t *vha)
4380{
4381 int rval = 0;
4382 mbx_cmd_t mc;
4383 mbx_cmd_t *mcp = &mc;
4384
5f28d2d7
SK		 4385 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e5,
4386 "Entered %s.\n", __func__);
6e181be5
LC		 4387
4388 mcp->mb[0] = MBC_RESTART_MPI_FW;
4389 mcp->out_mb = MBX_0;
4390 mcp->in_mb = MBX_0|MBX_1;
4391 mcp->tov = MBX_TOV_SECONDS;
4392 mcp->flags = 0;
4393 rval = qla2x00_mailbox_command(vha, mcp);
4394
4395 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4396 ql_dbg(ql_dbg_mbx, vha, 0x10e6,
4397 "Failed=%x mb[0]=%x mb[1]=%x.\n",
4398 rval, mcp->mb[0], mcp->mb[1]);
6e181be5 4399 } else {
5f28d2d7
SK		 4400 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e7,
4401 "Done %s.\n", __func__);
6e181be5
LC		 4402 }
4403
4404 return rval;
4405}
ad0ecd61 4406
c46e65c7
JC		 4407int
4408qla82xx_set_driver_version(scsi_qla_host_t *vha, char *version)
4409{
4410 int rval;
4411 mbx_cmd_t mc;
4412 mbx_cmd_t *mcp = &mc;
4413 int i;
4414 int len;
4415 uint16_t *str;
4416 struct qla_hw_data *ha = vha->hw;
4417
4418 if (!IS_P3P_TYPE(ha))
4419 return QLA_FUNCTION_FAILED;
4420
4421 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x117b,
4422 "Entered %s.\n", __func__);
4423
4424 str = (void *)version;
4425 len = strlen(version);
4426
4427 mcp->mb[0] = MBC_SET_RNID_PARAMS;
4428 mcp->mb[1] = RNID_TYPE_SET_VERSION << 8;
4429 mcp->out_mb = MBX_1|MBX_0;
4430 for (i = 4; i < 16 && len; i++, str++, len -= 2) {
4431 mcp->mb[i] = cpu_to_le16p(str);
4432 mcp->out_mb |= 1<<i;
4433 }
4434 for (; i < 16; i++) {
4435 mcp->mb[i] = 0;
4436 mcp->out_mb |= 1<<i;
4437 }
4438 mcp->in_mb = MBX_1|MBX_0;
4439 mcp->tov = MBX_TOV_SECONDS;
4440 mcp->flags = 0;
4441 rval = qla2x00_mailbox_command(vha, mcp);
4442
4443 if (rval != QLA_SUCCESS) {
4444 ql_dbg(ql_dbg_mbx, vha, 0x117c,
4445 "Failed=%x mb[0]=%x,%x.\n", rval, mcp->mb[0], mcp->mb[1]);
4446 } else {
4447 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x117d,
4448 "Done %s.\n", __func__);
4449 }
4450
4451 return rval;
4452}
4453
4454int
4455qla25xx_set_driver_version(scsi_qla_host_t *vha, char *version)
4456{
4457 int rval;
4458 mbx_cmd_t mc;
4459 mbx_cmd_t *mcp = &mc;
4460 int len;
4461 uint16_t dwlen;
4462 uint8_t *str;
4463 dma_addr_t str_dma;
4464 struct qla_hw_data *ha = vha->hw;
4465
4466 if (!IS_FWI2_CAPABLE(ha) || IS_QLA24XX_TYPE(ha) || IS_QLA81XX(ha) ||
4467 IS_P3P_TYPE(ha))
4468 return QLA_FUNCTION_FAILED;
4469
4470 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x117e,
4471 "Entered %s.\n", __func__);
4472
4473 str = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &str_dma);
4474 if (!str) {
4475 ql_log(ql_log_warn, vha, 0x117f,
4476 "Failed to allocate driver version param.\n");
4477 return QLA_MEMORY_ALLOC_FAILED;
4478 }
4479
4480 memcpy(str, "\x7\x3\x11\x0", 4);
4481 dwlen = str[0];
4482 len = dwlen * 4 - 4;
4483 memset(str + 4, 0, len);
4484 if (len > strlen(version))
4485 len = strlen(version);
4486 memcpy(str + 4, version, len);
4487
4488 mcp->mb[0] = MBC_SET_RNID_PARAMS;
4489 mcp->mb[1] = RNID_TYPE_SET_VERSION << 8 | dwlen;
4490 mcp->mb[2] = MSW(LSD(str_dma));
4491 mcp->mb[3] = LSW(LSD(str_dma));
4492 mcp->mb[6] = MSW(MSD(str_dma));
4493 mcp->mb[7] = LSW(MSD(str_dma));
4494 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
4495 mcp->in_mb = MBX_1|MBX_0;
4496 mcp->tov = MBX_TOV_SECONDS;
4497 mcp->flags = 0;
4498 rval = qla2x00_mailbox_command(vha, mcp);
4499
4500 if (rval != QLA_SUCCESS) {
4501 ql_dbg(ql_dbg_mbx, vha, 0x1180,
4502 "Failed=%x mb[0]=%x,%x.\n", rval, mcp->mb[0], mcp->mb[1]);
4503 } else {
4504 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1181,
4505 "Done %s.\n", __func__);
4506 }
4507
4508 dma_pool_free(ha->s_dma_pool, str, str_dma);
4509
4510 return rval;
4511}
4512
fe52f6e1
JC		 4513static int
4514qla2x00_read_asic_temperature(scsi_qla_host_t *vha, uint16_t *temp)
4515{
4516 int rval;
4517 mbx_cmd_t mc;
4518 mbx_cmd_t *mcp = &mc;
4519
4520 if (!IS_FWI2_CAPABLE(vha->hw))
4521 return QLA_FUNCTION_FAILED;
4522
4523 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1159,
4524 "Entered %s.\n", __func__);
4525
4526 mcp->mb[0] = MBC_GET_RNID_PARAMS;
4527 mcp->mb[1] = RNID_TYPE_ASIC_TEMP << 8;
4528 mcp->out_mb = MBX_1|MBX_0;
4529 mcp->in_mb = MBX_1|MBX_0;
4530 mcp->tov = MBX_TOV_SECONDS;
4531 mcp->flags = 0;
4532 rval = qla2x00_mailbox_command(vha, mcp);
4533 *temp = mcp->mb[1];
4534
4535 if (rval != QLA_SUCCESS) {
4536 ql_dbg(ql_dbg_mbx, vha, 0x115a,
4537 "Failed=%x mb[0]=%x,%x.\n", rval, mcp->mb[0], mcp->mb[1]);
4538 } else {
4539 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x115b,
4540 "Done %s.\n", __func__);
4541 }
4542
4543 return rval;
4544}
4545
ad0ecd61 4546int
6766df9e
JC		 4547qla2x00_read_sfp(scsi_qla_host_t *vha, dma_addr_t sfp_dma, uint8_t *sfp,
4548 uint16_t dev, uint16_t off, uint16_t len, uint16_t opt)
ad0ecd61
JC		 4549{
4550 int rval;
4551 mbx_cmd_t mc;
4552 mbx_cmd_t *mcp = &mc;
6766df9e
JC		 4553 struct qla_hw_data *ha = vha->hw;
4554
5f28d2d7
SK		 4555 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e8,
4556 "Entered %s.\n", __func__);
7c3df132 4557
6766df9e
JC		 4558 if (!IS_FWI2_CAPABLE(ha))
4559 return QLA_FUNCTION_FAILED;
ad0ecd61 4560
6766df9e
JC		 4561 if (len == 1)
4562 opt |= BIT_0;
4563
ad0ecd61
JC		 4564 mcp->mb[0] = MBC_READ_SFP;
4565 mcp->mb[1] = dev;
4566 mcp->mb[2] = MSW(sfp_dma);
4567 mcp->mb[3] = LSW(sfp_dma);
4568 mcp->mb[6] = MSW(MSD(sfp_dma));
4569 mcp->mb[7] = LSW(MSD(sfp_dma));
4570 mcp->mb[8] = len;
6766df9e 4571 mcp->mb[9] = off;
ad0ecd61
JC		 4572 mcp->mb[10] = opt;
4573 mcp->out_mb = MBX_10|MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
1bff6cc8 4574 mcp->in_mb = MBX_1|MBX_0;
ad0ecd61
JC		 4575 mcp->tov = MBX_TOV_SECONDS;
4576 mcp->flags = 0;
4577 rval = qla2x00_mailbox_command(vha, mcp);
4578
4579 if (opt & BIT_0)
6766df9e 4580 *sfp = mcp->mb[1];
ad0ecd61
JC		 4581
4582 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4583 ql_dbg(ql_dbg_mbx, vha, 0x10e9,
4584 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
ad0ecd61 4585 } else {
5f28d2d7
SK		 4586 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ea,
4587 "Done %s.\n", __func__);
ad0ecd61
JC		 4588 }
4589
4590 return rval;
4591}
4592
4593int
6766df9e
JC		 4594qla2x00_write_sfp(scsi_qla_host_t *vha, dma_addr_t sfp_dma, uint8_t *sfp,
4595 uint16_t dev, uint16_t off, uint16_t len, uint16_t opt)
ad0ecd61
JC		 4596{
4597 int rval;
4598 mbx_cmd_t mc;
4599 mbx_cmd_t *mcp = &mc;
6766df9e
JC		 4600 struct qla_hw_data *ha = vha->hw;
4601
5f28d2d7
SK		 4602 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10eb,
4603 "Entered %s.\n", __func__);
7c3df132 4604
6766df9e
JC		 4605 if (!IS_FWI2_CAPABLE(ha))
4606 return QLA_FUNCTION_FAILED;
ad0ecd61 4607
6766df9e
JC		 4608 if (len == 1)
4609 opt |= BIT_0;
4610
ad0ecd61 4611 if (opt & BIT_0)
6766df9e 4612 len = *sfp;
ad0ecd61
JC		 4613
4614 mcp->mb[0] = MBC_WRITE_SFP;
4615 mcp->mb[1] = dev;
4616 mcp->mb[2] = MSW(sfp_dma);
4617 mcp->mb[3] = LSW(sfp_dma);
4618 mcp->mb[6] = MSW(MSD(sfp_dma));
4619 mcp->mb[7] = LSW(MSD(sfp_dma));
4620 mcp->mb[8] = len;
6766df9e 4621 mcp->mb[9] = off;
ad0ecd61
JC		 4622 mcp->mb[10] = opt;
4623 mcp->out_mb = MBX_10|MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
6766df9e 4624 mcp->in_mb = MBX_1|MBX_0;
ad0ecd61
JC		 4625 mcp->tov = MBX_TOV_SECONDS;
4626 mcp->flags = 0;
4627 rval = qla2x00_mailbox_command(vha, mcp);
4628
4629 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4630 ql_dbg(ql_dbg_mbx, vha, 0x10ec,
4631 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
ad0ecd61 4632 } else {
5f28d2d7
SK		 4633 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ed,
4634 "Done %s.\n", __func__);
ad0ecd61
JC		 4635 }
4636
4637 return rval;
4638}
ce0423f4
AV		 4639
4640int
4641qla2x00_get_xgmac_stats(scsi_qla_host_t *vha, dma_addr_t stats_dma,
4642 uint16_t size_in_bytes, uint16_t *actual_size)
4643{
4644 int rval;
4645 mbx_cmd_t mc;
4646 mbx_cmd_t *mcp = &mc;
4647
5f28d2d7
SK		 4648 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ee,
4649 "Entered %s.\n", __func__);
7c3df132 4650
6246b8a1 4651 if (!IS_CNA_CAPABLE(vha->hw))
ce0423f4
AV		 4652 return QLA_FUNCTION_FAILED;
4653
ce0423f4
AV		 4654 mcp->mb[0] = MBC_GET_XGMAC_STATS;
4655 mcp->mb[2] = MSW(stats_dma);
4656 mcp->mb[3] = LSW(stats_dma);
4657 mcp->mb[6] = MSW(MSD(stats_dma));
4658 mcp->mb[7] = LSW(MSD(stats_dma));
4659 mcp->mb[8] = size_in_bytes >> 2;
4660 mcp->out_mb = MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_0;
4661 mcp->in_mb = MBX_2|MBX_1|MBX_0;
4662 mcp->tov = MBX_TOV_SECONDS;
4663 mcp->flags = 0;
4664 rval = qla2x00_mailbox_command(vha, mcp);
4665
4666 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4667 ql_dbg(ql_dbg_mbx, vha, 0x10ef,
4668 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n",
4669 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]);
ce0423f4 4670 } else {
5f28d2d7
SK		 4671 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f0,
4672 "Done %s.\n", __func__);
7c3df132 4673
ce0423f4
AV		 4674
4675 *actual_size = mcp->mb[2] << 2;
4676 }
4677
4678 return rval;
4679}
11bbc1d8
AV		 4680
4681int
4682qla2x00_get_dcbx_params(scsi_qla_host_t *vha, dma_addr_t tlv_dma,
4683 uint16_t size)
4684{
4685 int rval;
4686 mbx_cmd_t mc;
4687 mbx_cmd_t *mcp = &mc;
4688
5f28d2d7
SK		 4689 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f1,
4690 "Entered %s.\n", __func__);
7c3df132 4691
6246b8a1 4692 if (!IS_CNA_CAPABLE(vha->hw))
11bbc1d8
AV		 4693 return QLA_FUNCTION_FAILED;
4694
11bbc1d8
AV		 4695 mcp->mb[0] = MBC_GET_DCBX_PARAMS;
4696 mcp->mb[1] = 0;
4697 mcp->mb[2] = MSW(tlv_dma);
4698 mcp->mb[3] = LSW(tlv_dma);
4699 mcp->mb[6] = MSW(MSD(tlv_dma));
4700 mcp->mb[7] = LSW(MSD(tlv_dma));
4701 mcp->mb[8] = size;
4702 mcp->out_mb = MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
4703 mcp->in_mb = MBX_2|MBX_1|MBX_0;
4704 mcp->tov = MBX_TOV_SECONDS;
4705 mcp->flags = 0;
4706 rval = qla2x00_mailbox_command(vha, mcp);
4707
4708 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4709 ql_dbg(ql_dbg_mbx, vha, 0x10f2,
4710 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n",
4711 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]);
11bbc1d8 4712 } else {
5f28d2d7
SK		 4713 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f3,
4714 "Done %s.\n", __func__);
11bbc1d8
AV		 4715 }
4716
4717 return rval;
4718}
18e7555a
AV		 4719
4720int
4721qla2x00_read_ram_word(scsi_qla_host_t *vha, uint32_t risc_addr, uint32_t *data)
4722{
4723 int rval;
4724 mbx_cmd_t mc;
4725 mbx_cmd_t *mcp = &mc;
4726
5f28d2d7
SK		 4727 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f4,
4728 "Entered %s.\n", __func__);
7c3df132 4729
18e7555a
AV		 4730 if (!IS_FWI2_CAPABLE(vha->hw))
4731 return QLA_FUNCTION_FAILED;
4732
18e7555a
AV		 4733 mcp->mb[0] = MBC_READ_RAM_EXTENDED;
4734 mcp->mb[1] = LSW(risc_addr);
4735 mcp->mb[8] = MSW(risc_addr);
4736 mcp->out_mb = MBX_8|MBX_1|MBX_0;
4737 mcp->in_mb = MBX_3|MBX_2|MBX_0;
4738 mcp->tov = 30;
4739 mcp->flags = 0;
4740 rval = qla2x00_mailbox_command(vha, mcp);
4741 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4742 ql_dbg(ql_dbg_mbx, vha, 0x10f5,
4743 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
18e7555a 4744 } else {
5f28d2d7
SK		 4745 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f6,
4746 "Done %s.\n", __func__);
18e7555a
AV		 4747 *data = mcp->mb[3] << 16 | mcp->mb[2];
4748 }
4749
4750 return rval;
4751}
4752
9a069e19 4753int
a9083016
GM		 4754qla2x00_loopback_test(scsi_qla_host_t *vha, struct msg_echo_lb *mreq,
4755 uint16_t *mresp)
9a069e19
GM		 4756{
4757 int rval;
4758 mbx_cmd_t mc;
4759 mbx_cmd_t *mcp = &mc;
9a069e19 4760
5f28d2d7
SK		 4761 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f7,
4762 "Entered %s.\n", __func__);
9a069e19
GM		 4763
4764 memset(mcp->mb, 0 , sizeof(mcp->mb));
4765 mcp->mb[0] = MBC_DIAGNOSTIC_LOOP_BACK;
4766 mcp->mb[1] = mreq->options | BIT_6; // BIT_6 specifies 64 bit addressing
4767
4768 /* transfer count */
4769 mcp->mb[10] = LSW(mreq->transfer_size);
4770 mcp->mb[11] = MSW(mreq->transfer_size);
4771
4772 /* send data address */
4773 mcp->mb[14] = LSW(mreq->send_dma);
4774 mcp->mb[15] = MSW(mreq->send_dma);
4775 mcp->mb[20] = LSW(MSD(mreq->send_dma));
4776 mcp->mb[21] = MSW(MSD(mreq->send_dma));
4777
25985edc 4778 /* receive data address */
9a069e19
GM		 4779 mcp->mb[16] = LSW(mreq->rcv_dma);
4780 mcp->mb[17] = MSW(mreq->rcv_dma);
4781 mcp->mb[6] = LSW(MSD(mreq->rcv_dma));
4782 mcp->mb[7] = MSW(MSD(mreq->rcv_dma));
4783
4784 /* Iteration count */
1b98b421
JC		 4785 mcp->mb[18] = LSW(mreq->iteration_count);
4786 mcp->mb[19] = MSW(mreq->iteration_count);
9a069e19
GM		 4787
4788 mcp->out_mb = MBX_21|MBX_20|MBX_19|MBX_18|MBX_17|MBX_16|MBX_15|
4789 MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_7|MBX_6|MBX_1|MBX_0;
6246b8a1 4790 if (IS_CNA_CAPABLE(vha->hw))
9a069e19
GM		 4791 mcp->out_mb |= MBX_2;
4792 mcp->in_mb = MBX_19|MBX_18|MBX_3|MBX_2|MBX_1|MBX_0;
4793
4794 mcp->buf_size = mreq->transfer_size;
4795 mcp->tov = MBX_TOV_SECONDS;
4796 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
4797
4798 rval = qla2x00_mailbox_command(vha, mcp);
4799
4800 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4801 ql_dbg(ql_dbg_mbx, vha, 0x10f8,
4802 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x mb[3]=%x mb[18]=%x "
4803 "mb[19]=%x.\n", rval, mcp->mb[0], mcp->mb[1], mcp->mb[2],
4804 mcp->mb[3], mcp->mb[18], mcp->mb[19]);
9a069e19 4805 } else {
5f28d2d7
SK		 4806 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f9,
4807 "Done %s.\n", __func__);
9a069e19
GM		 4808 }
4809
4810 /* Copy mailbox information */
4811 memcpy( mresp, mcp->mb, 64);
9a069e19
GM		 4812 return rval;
4813}
4814
4815int
a9083016
GM		 4816qla2x00_echo_test(scsi_qla_host_t *vha, struct msg_echo_lb *mreq,
4817 uint16_t *mresp)
9a069e19
GM		 4818{
4819 int rval;
4820 mbx_cmd_t mc;
4821 mbx_cmd_t *mcp = &mc;
4822 struct qla_hw_data *ha = vha->hw;
4823
5f28d2d7
SK		 4824 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10fa,
4825 "Entered %s.\n", __func__);
9a069e19
GM		 4826
4827 memset(mcp->mb, 0 , sizeof(mcp->mb));
4828 mcp->mb[0] = MBC_DIAGNOSTIC_ECHO;
1d634965
JC		 4829 /* BIT_6 specifies 64bit address */
4830 mcp->mb[1] = mreq->options | BIT_15 | BIT_6;
6246b8a1 4831 if (IS_CNA_CAPABLE(ha)) {
a9083016
GM		 4832 mcp->mb[2] = vha->fcoe_fcf_idx;
4833 }
9a069e19
GM		 4834 mcp->mb[16] = LSW(mreq->rcv_dma);
4835 mcp->mb[17] = MSW(mreq->rcv_dma);
4836 mcp->mb[6] = LSW(MSD(mreq->rcv_dma));
4837 mcp->mb[7] = MSW(MSD(mreq->rcv_dma));
4838
4839 mcp->mb[10] = LSW(mreq->transfer_size);
4840
4841 mcp->mb[14] = LSW(mreq->send_dma);
4842 mcp->mb[15] = MSW(mreq->send_dma);
4843 mcp->mb[20] = LSW(MSD(mreq->send_dma));
4844 mcp->mb[21] = MSW(MSD(mreq->send_dma));
4845
4846 mcp->out_mb = MBX_21|MBX_20|MBX_17|MBX_16|MBX_15|
4847 MBX_14|MBX_10|MBX_7|MBX_6|MBX_1|MBX_0;
6246b8a1 4848 if (IS_CNA_CAPABLE(ha))
9a069e19
GM		 4849 mcp->out_mb |= MBX_2;
4850
4851 mcp->in_mb = MBX_0;
6246b8a1
GM		 4852 if (IS_QLA24XX_TYPE(ha) || IS_QLA25XX(ha) ||
4853 IS_CNA_CAPABLE(ha) || IS_QLA2031(ha))
9a069e19 4854 mcp->in_mb |= MBX_1;
6246b8a1 4855 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha))
9a069e19
GM		 4856 mcp->in_mb |= MBX_3;
4857
4858 mcp->tov = MBX_TOV_SECONDS;
4859 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
4860 mcp->buf_size = mreq->transfer_size;
4861
4862 rval = qla2x00_mailbox_command(vha, mcp);
4863
4864 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4865 ql_dbg(ql_dbg_mbx, vha, 0x10fb,
4866 "Failed=%x mb[0]=%x mb[1]=%x.\n",
4867 rval, mcp->mb[0], mcp->mb[1]);
9a069e19 4868 } else {
5f28d2d7
SK		 4869 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10fc,
4870 "Done %s.\n", __func__);
9a069e19
GM		 4871 }
4872
4873 /* Copy mailbox information */
6dbdda4d 4874 memcpy(mresp, mcp->mb, 64);
9a069e19
GM		 4875 return rval;
4876}
6dbdda4d 4877
9a069e19 4878int
7c3df132 4879qla84xx_reset_chip(scsi_qla_host_t *vha, uint16_t enable_diagnostic)
9a069e19
GM		 4880{
4881 int rval;
4882 mbx_cmd_t mc;
4883 mbx_cmd_t *mcp = &mc;
4884
5f28d2d7 4885 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10fd,
7c3df132 4886 "Entered %s enable_diag=%d.\n", __func__, enable_diagnostic);
9a069e19
GM		 4887
4888 mcp->mb[0] = MBC_ISP84XX_RESET;
4889 mcp->mb[1] = enable_diagnostic;
4890 mcp->out_mb = MBX_1|MBX_0;
4891 mcp->in_mb = MBX_1|MBX_0;
4892 mcp->tov = MBX_TOV_SECONDS;
4893 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
7c3df132 4894 rval = qla2x00_mailbox_command(vha, mcp);
9a069e19 4895
9a069e19 4896 if (rval != QLA_SUCCESS)
7c3df132 4897 ql_dbg(ql_dbg_mbx, vha, 0x10fe, "Failed=%x.\n", rval);
9a069e19 4898 else
5f28d2d7
SK		 4899 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ff,
4900 "Done %s.\n", __func__);
9a069e19
GM		 4901
4902 return rval;
4903}
4904
18e7555a
AV		 4905int
4906qla2x00_write_ram_word(scsi_qla_host_t *vha, uint32_t risc_addr, uint32_t data)
4907{
4908 int rval;
4909 mbx_cmd_t mc;
4910 mbx_cmd_t *mcp = &mc;
4911
5f28d2d7
SK		 4912 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1100,
4913 "Entered %s.\n", __func__);
7c3df132 4914
18e7555a 4915 if (!IS_FWI2_CAPABLE(vha->hw))
6c452a45 4916 return QLA_FUNCTION_FAILED;
18e7555a 4917
18e7555a
AV		 4918 mcp->mb[0] = MBC_WRITE_RAM_WORD_EXTENDED;
4919 mcp->mb[1] = LSW(risc_addr);
4920 mcp->mb[2] = LSW(data);
4921 mcp->mb[3] = MSW(data);
4922 mcp->mb[8] = MSW(risc_addr);
4923 mcp->out_mb = MBX_8|MBX_3|MBX_2|MBX_1|MBX_0;
4924 mcp->in_mb = MBX_0;
4925 mcp->tov = 30;
4926 mcp->flags = 0;
4927 rval = qla2x00_mailbox_command(vha, mcp);
4928 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4929 ql_dbg(ql_dbg_mbx, vha, 0x1101,
4930 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
18e7555a 4931 } else {
5f28d2d7
SK		 4932 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1102,
4933 "Done %s.\n", __func__);
18e7555a
AV		 4934 }
4935
4936 return rval;
4937}
3064ff39 4938
b1d46989
MI		 4939int
4940qla81xx_write_mpi_register(scsi_qla_host_t *vha, uint16_t *mb)
4941{
4942 int rval;
4943 uint32_t stat, timer;
4944 uint16_t mb0 = 0;
4945 struct qla_hw_data *ha = vha->hw;
4946 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
4947
4948 rval = QLA_SUCCESS;
4949
5f28d2d7
SK		 4950 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1103,
4951 "Entered %s.\n", __func__);
b1d46989
MI		 4952
4953 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
4954
4955 /* Write the MBC data to the registers */
4956 WRT_REG_WORD(&reg->mailbox0, MBC_WRITE_MPI_REGISTER);
4957 WRT_REG_WORD(&reg->mailbox1, mb[0]);
4958 WRT_REG_WORD(&reg->mailbox2, mb[1]);
4959 WRT_REG_WORD(&reg->mailbox3, mb[2]);
4960 WRT_REG_WORD(&reg->mailbox4, mb[3]);
4961
4962 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_HOST_INT);
4963
4964 /* Poll for MBC interrupt */
4965 for (timer = 6000000; timer; timer--) {
4966 /* Check for pending interrupts. */
4967 stat = RD_REG_DWORD(&reg->host_status);
4968 if (stat & HSRX_RISC_INT) {
4969 stat &= 0xff;
4970
4971 if (stat == 0x1 || stat == 0x2 ||
4972 stat == 0x10 || stat == 0x11) {
4973 set_bit(MBX_INTERRUPT,
4974 &ha->mbx_cmd_flags);
4975 mb0 = RD_REG_WORD(&reg->mailbox0);
4976 WRT_REG_DWORD(&reg->hccr,
4977 HCCRX_CLR_RISC_INT);
4978 RD_REG_DWORD(&reg->hccr);
4979 break;
4980 }
4981 }
4982 udelay(5);
4983 }
4984
4985 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags))
4986 rval = mb0 & MBS_MASK;
4987 else
4988 rval = QLA_FUNCTION_FAILED;
4989
4990 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4991 ql_dbg(ql_dbg_mbx, vha, 0x1104,
4992 "Failed=%x mb[0]=%x.\n", rval, mb[0]);
b1d46989 4993 } else {
5f28d2d7
SK		 4994 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1105,
4995 "Done %s.\n", __func__);
b1d46989
MI		 4996 }
4997
4998 return rval;
4999}
6246b8a1 5000
3064ff39
MH		 5001int
5002qla2x00_get_data_rate(scsi_qla_host_t *vha)
5003{
5004 int rval;
5005 mbx_cmd_t mc;
5006 mbx_cmd_t *mcp = &mc;
5007 struct qla_hw_data *ha = vha->hw;
5008
5f28d2d7
SK		 5009 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1106,
5010 "Entered %s.\n", __func__);
7c3df132 5011
3064ff39
MH		 5012 if (!IS_FWI2_CAPABLE(ha))
5013 return QLA_FUNCTION_FAILED;
5014
3064ff39
MH		 5015 mcp->mb[0] = MBC_DATA_RATE;
5016 mcp->mb[1] = 0;
5017 mcp->out_mb = MBX_1|MBX_0;
5018 mcp->in_mb = MBX_2|MBX_1|MBX_0;
f73cb695 5019 if (IS_QLA83XX(ha) || IS_QLA27XX(ha))
6246b8a1 5020 mcp->in_mb |= MBX_3;
3064ff39
MH		 5021 mcp->tov = MBX_TOV_SECONDS;
5022 mcp->flags = 0;
5023 rval = qla2x00_mailbox_command(vha, mcp);
5024 if (rval != QLA_SUCCESS) {
7c3df132
SK		 5025 ql_dbg(ql_dbg_mbx, vha, 0x1107,
5026 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
3064ff39 5027 } else {
5f28d2d7
SK		 5028 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1108,
5029 "Done %s.\n", __func__);
3064ff39
MH		 5030 if (mcp->mb[1] != 0x7)
5031 ha->link_data_rate = mcp->mb[1];
5032 }
5033
5034 return rval;
5035}
09ff701a 5036
23f2ebd1
SR		 5037int
5038qla81xx_get_port_config(scsi_qla_host_t *vha, uint16_t *mb)
5039{
5040 int rval;
5041 mbx_cmd_t mc;
5042 mbx_cmd_t *mcp = &mc;
5043 struct qla_hw_data *ha = vha->hw;
5044
5f28d2d7
SK		 5045 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1109,
5046 "Entered %s.\n", __func__);
23f2ebd1 5047
f73cb695
CD		 5048 if (!IS_QLA81XX(ha) && !IS_QLA83XX(ha) && !IS_QLA8044(ha) &&
5049 !IS_QLA27XX(ha))
23f2ebd1
SR		 5050 return QLA_FUNCTION_FAILED;
5051 mcp->mb[0] = MBC_GET_PORT_CONFIG;
5052 mcp->out_mb = MBX_0;
5053 mcp->in_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
5054 mcp->tov = MBX_TOV_SECONDS;
5055 mcp->flags = 0;
5056
5057 rval = qla2x00_mailbox_command(vha, mcp);
5058
5059 if (rval != QLA_SUCCESS) {
7c3df132
SK		 5060 ql_dbg(ql_dbg_mbx, vha, 0x110a,
5061 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
23f2ebd1
SR		 5062 } else {
5063 /* Copy all bits to preserve original value */
5064 memcpy(mb, &mcp->mb[1], sizeof(uint16_t) * 4);
5065
5f28d2d7
SK		 5066 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x110b,
5067 "Done %s.\n", __func__);
23f2ebd1
SR		 5068 }
5069 return rval;
5070}
5071
5072int
5073qla81xx_set_port_config(scsi_qla_host_t *vha, uint16_t *mb)
5074{
5075 int rval;
5076 mbx_cmd_t mc;
5077 mbx_cmd_t *mcp = &mc;
5078
5f28d2d7
SK		 5079 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x110c,
5080 "Entered %s.\n", __func__);
23f2ebd1
SR		 5081
5082 mcp->mb[0] = MBC_SET_PORT_CONFIG;
5083 /* Copy all bits to preserve original setting */
5084 memcpy(&mcp->mb[1], mb, sizeof(uint16_t) * 4);
5085 mcp->out_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
5086 mcp->in_mb = MBX_0;
5087 mcp->tov = MBX_TOV_SECONDS;
5088 mcp->flags = 0;
5089 rval = qla2x00_mailbox_command(vha, mcp);
5090
5091 if (rval != QLA_SUCCESS) {
7c3df132
SK		 5092 ql_dbg(ql_dbg_mbx, vha, 0x110d,
5093 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
23f2ebd1 5094 } else
5f28d2d7
SK		 5095 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x110e,
5096 "Done %s.\n", __func__);
23f2ebd1
SR		 5097
5098 return rval;
5099}
5100
5101
09ff701a
SR		 5102int
5103qla24xx_set_fcp_prio(scsi_qla_host_t *vha, uint16_t loop_id, uint16_t priority,
5104 uint16_t *mb)
5105{
5106 int rval;
5107 mbx_cmd_t mc;
5108 mbx_cmd_t *mcp = &mc;
5109 struct qla_hw_data *ha = vha->hw;
5110
5f28d2d7
SK		 5111 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x110f,
5112 "Entered %s.\n", __func__);
7c3df132 5113
09ff701a
SR		 5114 if (!IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha))
5115 return QLA_FUNCTION_FAILED;
5116
09ff701a
SR		 5117 mcp->mb[0] = MBC_PORT_PARAMS;
5118 mcp->mb[1] = loop_id;
5119 if (ha->flags.fcp_prio_enabled)
5120 mcp->mb[2] = BIT_1;
5121 else
5122 mcp->mb[2] = BIT_2;
5123 mcp->mb[4] = priority & 0xf;
5124 mcp->mb[9] = vha->vp_idx;
5125 mcp->out_mb = MBX_9|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
5126 mcp->in_mb = MBX_4|MBX_3|MBX_1|MBX_0;
5127 mcp->tov = 30;
5128 mcp->flags = 0;
5129 rval = qla2x00_mailbox_command(vha, mcp);
5130 if (mb != NULL) {
5131 mb[0] = mcp->mb[0];
5132 mb[1] = mcp->mb[1];
5133 mb[3] = mcp->mb[3];
5134 mb[4] = mcp->mb[4];
5135 }
5136
5137 if (rval != QLA_SUCCESS) {
7c3df132 5138 ql_dbg(ql_dbg_mbx, vha, 0x10cd, "Failed=%x.\n", rval);
09ff701a 5139 } else {
5f28d2d7
SK		 5140 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10cc,
5141 "Done %s.\n", __func__);
09ff701a
SR		 5142 }
5143
5144 return rval;
5145}
a9083016 5146
794a5691 5147int
fe52f6e1 5148qla2x00_get_thermal_temp(scsi_qla_host_t *vha, uint16_t *temp)
794a5691 5149{
fe52f6e1 5150 int rval = QLA_FUNCTION_FAILED;
794a5691 5151 struct qla_hw_data *ha = vha->hw;
fe52f6e1 5152 uint8_t byte;
794a5691 5153
1ae47cf3
JC		 5154 if (!IS_FWI2_CAPABLE(ha) || IS_QLA24XX_TYPE(ha) || IS_QLA81XX(ha)) {
5155 ql_dbg(ql_dbg_mbx, vha, 0x1150,
5156 "Thermal not supported by this card.\n");
5157 return rval;
5158 }
5159
5160 if (IS_QLA25XX(ha)) {
5161 if (ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC &&
5162 ha->pdev->subsystem_device == 0x0175) {
5163 rval = qla2x00_read_sfp(vha, 0, &byte,
5164 0x98, 0x1, 1, BIT_13|BIT_0);
5165 *temp = byte;
5166 return rval;
5167 }
5168 if (ha->pdev->subsystem_vendor == PCI_VENDOR_ID_HP &&
5169 ha->pdev->subsystem_device == 0x338e) {
5170 rval = qla2x00_read_sfp(vha, 0, &byte,
5171 0x98, 0x1, 1, BIT_15|BIT_14|BIT_0);
5172 *temp = byte;
5173 return rval;
5174 }
5175 ql_dbg(ql_dbg_mbx, vha, 0x10c9,
5176 "Thermal not supported by this card.\n");
5177 return rval;
794a5691 5178 }
794a5691 5179
1ae47cf3
JC		 5180 if (IS_QLA82XX(ha)) {
5181 *temp = qla82xx_read_temperature(vha);
5182 rval = QLA_SUCCESS;
5183 return rval;
5184 } else if (IS_QLA8044(ha)) {
5185 *temp = qla8044_read_temperature(vha);
5186 rval = QLA_SUCCESS;
5187 return rval;
794a5691 5188 }
794a5691 5189
1ae47cf3 5190 rval = qla2x00_read_asic_temperature(vha, temp);
794a5691
AV		 5191 return rval;
5192}
5193
a9083016
GM		 5194int
5195qla82xx_mbx_intr_enable(scsi_qla_host_t *vha)
5196{
5197 int rval;
5198 struct qla_hw_data *ha = vha->hw;
5199 mbx_cmd_t mc;
5200 mbx_cmd_t *mcp = &mc;
5201
5f28d2d7
SK		 5202 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1017,
5203 "Entered %s.\n", __func__);
7c3df132 5204
a9083016
GM		 5205 if (!IS_FWI2_CAPABLE(ha))
5206 return QLA_FUNCTION_FAILED;
5207
a9083016 5208 memset(mcp, 0, sizeof(mbx_cmd_t));
3711333d 5209 mcp->mb[0] = MBC_TOGGLE_INTERRUPT;
a9083016
GM		 5210 mcp->mb[1] = 1;
5211
5212 mcp->out_mb = MBX_1|MBX_0;
5213 mcp->in_mb = MBX_0;
5214 mcp->tov = 30;
5215 mcp->flags = 0;
5216
5217 rval = qla2x00_mailbox_command(vha, mcp);
5218 if (rval != QLA_SUCCESS) {
7c3df132
SK		 5219 ql_dbg(ql_dbg_mbx, vha, 0x1016,
5220 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
a9083016 5221 } else {
5f28d2d7
SK		 5222 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x100e,
5223 "Done %s.\n", __func__);
a9083016
GM		 5224 }
5225
5226 return rval;
5227}
5228
5229int
5230qla82xx_mbx_intr_disable(scsi_qla_host_t *vha)
5231{
5232 int rval;
5233 struct qla_hw_data *ha = vha->hw;
5234 mbx_cmd_t mc;
5235 mbx_cmd_t *mcp = &mc;
5236
5f28d2d7
SK		 5237 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x100d,
5238 "Entered %s.\n", __func__);
7c3df132 5239
7ec0effd 5240 if (!IS_P3P_TYPE(ha))
a9083016
GM		 5241 return QLA_FUNCTION_FAILED;
5242
a9083016 5243 memset(mcp, 0, sizeof(mbx_cmd_t));
3711333d 5244 mcp->mb[0] = MBC_TOGGLE_INTERRUPT;
a9083016
GM		 5245 mcp->mb[1] = 0;
5246
5247 mcp->out_mb = MBX_1|MBX_0;
5248 mcp->in_mb = MBX_0;
5249 mcp->tov = 30;
5250 mcp->flags = 0;
5251
5252 rval = qla2x00_mailbox_command(vha, mcp);
5253 if (rval != QLA_SUCCESS) {
7c3df132
SK		 5254 ql_dbg(ql_dbg_mbx, vha, 0x100c,
5255 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
a9083016 5256 } else {
5f28d2d7
SK		 5257 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x100b,
5258 "Done %s.\n", __func__);
a9083016
GM		 5259 }
5260
5261 return rval;
5262}
08de2844
GM		 5263
5264int
5265qla82xx_md_get_template_size(scsi_qla_host_t *vha)
5266{
5267 struct qla_hw_data *ha = vha->hw;
5268 mbx_cmd_t mc;
5269 mbx_cmd_t *mcp = &mc;
5270 int rval = QLA_FUNCTION_FAILED;
5271
5f28d2d7
SK		 5272 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x111f,
5273 "Entered %s.\n", __func__);
08de2844
GM		 5274
5275 memset(mcp->mb, 0 , sizeof(mcp->mb));
5276 mcp->mb[0] = LSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE);
5277 mcp->mb[1] = MSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE);
5278 mcp->mb[2] = LSW(RQST_TMPLT_SIZE);
5279 mcp->mb[3] = MSW(RQST_TMPLT_SIZE);
5280
5281 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
5282 mcp->in_mb = MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8|
5283 MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
5284
5285 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
5286 mcp->tov = MBX_TOV_SECONDS;
5287 rval = qla2x00_mailbox_command(vha, mcp);
5288
5289 /* Always copy back return mailbox values. */
5290 if (rval != QLA_SUCCESS) {
5291 ql_dbg(ql_dbg_mbx, vha, 0x1120,
5292 "mailbox command FAILED=0x%x, subcode=%x.\n",
5293 (mcp->mb[1] << 16) | mcp->mb[0],
5294 (mcp->mb[3] << 16) | mcp->mb[2]);
5295 } else {
5f28d2d7
SK		 5296 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1121,
5297 "Done %s.\n", __func__);
08de2844
GM		 5298 ha->md_template_size = ((mcp->mb[3] << 16) | mcp->mb[2]);
5299 if (!ha->md_template_size) {
5300 ql_dbg(ql_dbg_mbx, vha, 0x1122,
5301 "Null template size obtained.\n");
5302 rval = QLA_FUNCTION_FAILED;
5303 }
5304 }
5305 return rval;
5306}
5307
5308int
5309qla82xx_md_get_template(scsi_qla_host_t *vha)
5310{
5311 struct qla_hw_data *ha = vha->hw;
5312 mbx_cmd_t mc;
5313 mbx_cmd_t *mcp = &mc;
5314 int rval = QLA_FUNCTION_FAILED;
5315
5f28d2d7
SK		 5316 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1123,
5317 "Entered %s.\n", __func__);
08de2844
GM		 5318
5319 ha->md_tmplt_hdr = dma_alloc_coherent(&ha->pdev->dev,
5320 ha->md_template_size, &ha->md_tmplt_hdr_dma, GFP_KERNEL);
5321 if (!ha->md_tmplt_hdr) {
5322 ql_log(ql_log_warn, vha, 0x1124,
5323 "Unable to allocate memory for Minidump template.\n");
5324 return rval;
5325 }
5326
5327 memset(mcp->mb, 0 , sizeof(mcp->mb));
5328 mcp->mb[0] = LSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE);
5329 mcp->mb[1] = MSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE);
5330 mcp->mb[2] = LSW(RQST_TMPLT);
5331 mcp->mb[3] = MSW(RQST_TMPLT);
5332 mcp->mb[4] = LSW(LSD(ha->md_tmplt_hdr_dma));
5333 mcp->mb[5] = MSW(LSD(ha->md_tmplt_hdr_dma));
5334 mcp->mb[6] = LSW(MSD(ha->md_tmplt_hdr_dma));
5335 mcp->mb[7] = MSW(MSD(ha->md_tmplt_hdr_dma));
5336 mcp->mb[8] = LSW(ha->md_template_size);
5337 mcp->mb[9] = MSW(ha->md_template_size);
5338
5339 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
5340 mcp->tov = MBX_TOV_SECONDS;
5341 mcp->out_mb = MBX_11|MBX_10|MBX_9|MBX_8|
5342 MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
5343 mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0;
5344 rval = qla2x00_mailbox_command(vha, mcp);
5345
5346 if (rval != QLA_SUCCESS) {
5347 ql_dbg(ql_dbg_mbx, vha, 0x1125,
5348 "mailbox command FAILED=0x%x, subcode=%x.\n",
5349 ((mcp->mb[1] << 16) | mcp->mb[0]),
5350 ((mcp->mb[3] << 16) | mcp->mb[2]));
5351 } else
5f28d2d7
SK		 5352 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1126,
5353 "Done %s.\n", __func__);
08de2844
GM		 5354 return rval;
5355}
999916dc 5356
7ec0effd
AD		 5357int
5358qla8044_md_get_template(scsi_qla_host_t *vha)
5359{
5360 struct qla_hw_data *ha = vha->hw;
5361 mbx_cmd_t mc;
5362 mbx_cmd_t *mcp = &mc;
5363 int rval = QLA_FUNCTION_FAILED;
5364 int offset = 0, size = MINIDUMP_SIZE_36K;
5365 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0xb11f,
5366 "Entered %s.\n", __func__);
5367
5368 ha->md_tmplt_hdr = dma_alloc_coherent(&ha->pdev->dev,
5369 ha->md_template_size, &ha->md_tmplt_hdr_dma, GFP_KERNEL);
5370 if (!ha->md_tmplt_hdr) {
5371 ql_log(ql_log_warn, vha, 0xb11b,
5372 "Unable to allocate memory for Minidump template.\n");
5373 return rval;
5374 }
5375
5376 memset(mcp->mb, 0 , sizeof(mcp->mb));
5377 while (offset < ha->md_template_size) {
5378 mcp->mb[0] = LSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE);
5379 mcp->mb[1] = MSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE);
5380 mcp->mb[2] = LSW(RQST_TMPLT);
5381 mcp->mb[3] = MSW(RQST_TMPLT);
5382 mcp->mb[4] = LSW(LSD(ha->md_tmplt_hdr_dma + offset));
5383 mcp->mb[5] = MSW(LSD(ha->md_tmplt_hdr_dma + offset));
5384 mcp->mb[6] = LSW(MSD(ha->md_tmplt_hdr_dma + offset));
5385 mcp->mb[7] = MSW(MSD(ha->md_tmplt_hdr_dma + offset));
5386 mcp->mb[8] = LSW(size);
5387 mcp->mb[9] = MSW(size);
5388 mcp->mb[10] = offset & 0x0000FFFF;
5389 mcp->mb[11] = offset & 0xFFFF0000;
5390 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
5391 mcp->tov = MBX_TOV_SECONDS;
5392 mcp->out_mb = MBX_11|MBX_10|MBX_9|MBX_8|
5393 MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
5394 mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0;
5395 rval = qla2x00_mailbox_command(vha, mcp);
5396
5397 if (rval != QLA_SUCCESS) {
5398 ql_dbg(ql_dbg_mbx, vha, 0xb11c,
5399 "mailbox command FAILED=0x%x, subcode=%x.\n",
5400 ((mcp->mb[1] << 16) | mcp->mb[0]),
5401 ((mcp->mb[3] << 16) | mcp->mb[2]));
5402 return rval;
5403 } else
5404 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0xb11d,
5405 "Done %s.\n", __func__);
5406 offset = offset + size;
5407 }
5408 return rval;
5409}
5410
6246b8a1
GM		 5411int
5412qla81xx_set_led_config(scsi_qla_host_t *vha, uint16_t *led_cfg)
5413{
5414 int rval;
5415 struct qla_hw_data *ha = vha->hw;
5416 mbx_cmd_t mc;
5417 mbx_cmd_t *mcp = &mc;
5418
5419 if (!IS_QLA81XX(ha) && !IS_QLA8031(ha))
5420 return QLA_FUNCTION_FAILED;
5421
5f28d2d7
SK		 5422 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1133,
5423 "Entered %s.\n", __func__);
6246b8a1
GM		 5424
5425 memset(mcp, 0, sizeof(mbx_cmd_t));
5426 mcp->mb[0] = MBC_SET_LED_CONFIG;
5427 mcp->mb[1] = led_cfg[0];
5428 mcp->mb[2] = led_cfg[1];
5429 if (IS_QLA8031(ha)) {
5430 mcp->mb[3] = led_cfg[2];
5431 mcp->mb[4] = led_cfg[3];
5432 mcp->mb[5] = led_cfg[4];
5433 mcp->mb[6] = led_cfg[5];
5434 }
5435
5436 mcp->out_mb = MBX_2|MBX_1|MBX_0;
5437 if (IS_QLA8031(ha))
5438 mcp->out_mb |= MBX_6|MBX_5|MBX_4|MBX_3;
5439 mcp->in_mb = MBX_0;
5440 mcp->tov = 30;
5441 mcp->flags = 0;
5442
5443 rval = qla2x00_mailbox_command(vha, mcp);
5444 if (rval != QLA_SUCCESS) {
5445 ql_dbg(ql_dbg_mbx, vha, 0x1134,
5446 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
5447 } else {
5f28d2d7
SK		 5448 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1135,
5449 "Done %s.\n", __func__);
6246b8a1
GM		 5450 }
5451
5452 return rval;
5453}
5454
5455int
5456qla81xx_get_led_config(scsi_qla_host_t *vha, uint16_t *led_cfg)
5457{
5458 int rval;
5459 struct qla_hw_data *ha = vha->hw;
5460 mbx_cmd_t mc;
5461 mbx_cmd_t *mcp = &mc;
5462
5463 if (!IS_QLA81XX(ha) && !IS_QLA8031(ha))
5464 return QLA_FUNCTION_FAILED;
5465
5f28d2d7
SK		 5466 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1136,
5467 "Entered %s.\n", __func__);
6246b8a1
GM		 5468
5469 memset(mcp, 0, sizeof(mbx_cmd_t));
5470 mcp->mb[0] = MBC_GET_LED_CONFIG;
5471
5472 mcp->out_mb = MBX_0;
5473 mcp->in_mb = MBX_2|MBX_1|MBX_0;
5474 if (IS_QLA8031(ha))
5475 mcp->in_mb |= MBX_6|MBX_5|MBX_4|MBX_3;
5476 mcp->tov = 30;
5477 mcp->flags = 0;
5478
5479 rval = qla2x00_mailbox_command(vha, mcp);
5480 if (rval != QLA_SUCCESS) {
5481 ql_dbg(ql_dbg_mbx, vha, 0x1137,
5482 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
5483 } else {
5484 led_cfg[0] = mcp->mb[1];
5485 led_cfg[1] = mcp->mb[2];
5486 if (IS_QLA8031(ha)) {
5487 led_cfg[2] = mcp->mb[3];
5488 led_cfg[3] = mcp->mb[4];
5489 led_cfg[4] = mcp->mb[5];
5490 led_cfg[5] = mcp->mb[6];
5491 }
5f28d2d7
SK		 5492 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1138,
5493 "Done %s.\n", __func__);
6246b8a1
GM		 5494 }
5495
5496 return rval;
5497}
5498
999916dc
SK		 5499int
5500qla82xx_mbx_beacon_ctl(scsi_qla_host_t *vha, int enable)
5501{
5502 int rval;
5503 struct qla_hw_data *ha = vha->hw;
5504 mbx_cmd_t mc;
5505 mbx_cmd_t *mcp = &mc;
5506
7ec0effd 5507 if (!IS_P3P_TYPE(ha))
999916dc
SK		 5508 return QLA_FUNCTION_FAILED;
5509
5f28d2d7 5510 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1127,
999916dc
SK		 5511 "Entered %s.\n", __func__);
5512
5513 memset(mcp, 0, sizeof(mbx_cmd_t));
5514 mcp->mb[0] = MBC_SET_LED_CONFIG;
5515 if (enable)
5516 mcp->mb[7] = 0xE;
5517 else
5518 mcp->mb[7] = 0xD;
5519
5520 mcp->out_mb = MBX_7|MBX_0;
5521 mcp->in_mb = MBX_0;
6246b8a1 5522 mcp->tov = MBX_TOV_SECONDS;
999916dc
SK		 5523 mcp->flags = 0;
5524
5525 rval = qla2x00_mailbox_command(vha, mcp);
5526 if (rval != QLA_SUCCESS) {
5527 ql_dbg(ql_dbg_mbx, vha, 0x1128,
5528 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
5529 } else {
5f28d2d7 5530 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1129,
999916dc
SK		 5531 "Done %s.\n", __func__);
5532 }
5533
5534 return rval;
5535}
6246b8a1
GM		 5536
5537int
7d613ac6 5538qla83xx_wr_reg(scsi_qla_host_t *vha, uint32_t reg, uint32_t data)
6246b8a1
GM		 5539{
5540 int rval;
5541 struct qla_hw_data *ha = vha->hw;
5542 mbx_cmd_t mc;
5543 mbx_cmd_t *mcp = &mc;
5544
f73cb695 5545 if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha))
6246b8a1
GM		 5546 return QLA_FUNCTION_FAILED;
5547
5f28d2d7
SK		 5548 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1130,
5549 "Entered %s.\n", __func__);
6246b8a1
GM		 5550
5551 mcp->mb[0] = MBC_WRITE_REMOTE_REG;
5552 mcp->mb[1] = LSW(reg);
5553 mcp->mb[2] = MSW(reg);
5554 mcp->mb[3] = LSW(data);
5555 mcp->mb[4] = MSW(data);
5556 mcp->out_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
5557
5558 mcp->in_mb = MBX_1|MBX_0;
5559 mcp->tov = MBX_TOV_SECONDS;
5560 mcp->flags = 0;
5561 rval = qla2x00_mailbox_command(vha, mcp);
5562
5563 if (rval != QLA_SUCCESS) {
5564 ql_dbg(ql_dbg_mbx, vha, 0x1131,
5565 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
5566 } else {
5f28d2d7 5567 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1132,
6246b8a1
GM		 5568 "Done %s.\n", __func__);
5569 }
af11f64d 5570
6246b8a1
GM		 5571 return rval;
5572}
af11f64d
AV		 5573
5574int
5575qla2x00_port_logout(scsi_qla_host_t *vha, struct fc_port *fcport)
5576{
5577 int rval;
5578 struct qla_hw_data *ha = vha->hw;
5579 mbx_cmd_t mc;
5580 mbx_cmd_t *mcp = &mc;
5581
5582 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
5f28d2d7 5583 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x113b,
af11f64d
AV		 5584 "Implicit LOGO Unsupported.\n");
5585 return QLA_FUNCTION_FAILED;
5586 }
5587
5588
5f28d2d7
SK		 5589 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x113c,
5590 "Entering %s.\n", __func__);
af11f64d
AV		 5591
5592 /* Perform Implicit LOGO. */
5593 mcp->mb[0] = MBC_PORT_LOGOUT;
5594 mcp->mb[1] = fcport->loop_id;
5595 mcp->mb[10] = BIT_15;
5596 mcp->out_mb = MBX_10|MBX_1|MBX_0;
5597 mcp->in_mb = MBX_0;
5598 mcp->tov = MBX_TOV_SECONDS;
5599 mcp->flags = 0;
5600 rval = qla2x00_mailbox_command(vha, mcp);
5601 if (rval != QLA_SUCCESS)
5602 ql_dbg(ql_dbg_mbx, vha, 0x113d,
5603 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
5604 else
5f28d2d7
SK		 5605 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x113e,
5606 "Done %s.\n", __func__);
af11f64d
AV		 5607
5608 return rval;
5609}
5610
7d613ac6
SV		 5611int
5612qla83xx_rd_reg(scsi_qla_host_t *vha, uint32_t reg, uint32_t *data)
5613{
5614 int rval;
5615 mbx_cmd_t mc;
5616 mbx_cmd_t *mcp = &mc;
5617 struct qla_hw_data *ha = vha->hw;
5618 unsigned long retry_max_time = jiffies + (2 * HZ);
5619
f73cb695 5620 if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha))
7d613ac6
SV		 5621 return QLA_FUNCTION_FAILED;
5622
5623 ql_dbg(ql_dbg_mbx, vha, 0x114b, "Entered %s.\n", __func__);
5624
5625retry_rd_reg:
5626 mcp->mb[0] = MBC_READ_REMOTE_REG;
5627 mcp->mb[1] = LSW(reg);
5628 mcp->mb[2] = MSW(reg);
5629 mcp->out_mb = MBX_2|MBX_1|MBX_0;
5630 mcp->in_mb = MBX_4|MBX_3|MBX_1|MBX_0;
5631 mcp->tov = MBX_TOV_SECONDS;
5632 mcp->flags = 0;
5633 rval = qla2x00_mailbox_command(vha, mcp);
5634
5635 if (rval != QLA_SUCCESS) {
5636 ql_dbg(ql_dbg_mbx, vha, 0x114c,
5637 "Failed=%x mb[0]=%x mb[1]=%x.\n",
5638 rval, mcp->mb[0], mcp->mb[1]);
5639 } else {
5640 *data = (mcp->mb[3] | (mcp->mb[4] << 16));
5641 if (*data == QLA8XXX_BAD_VALUE) {
5642 /*
5643 * During soft-reset CAMRAM register reads might
5644 * return 0xbad0bad0. So retry for MAX of 2 sec
5645 * while reading camram registers.
5646 */
5647 if (time_after(jiffies, retry_max_time)) {
5648 ql_dbg(ql_dbg_mbx, vha, 0x1141,
5649 "Failure to read CAMRAM register. "
5650 "data=0x%x.\n", *data);
5651 return QLA_FUNCTION_FAILED;
5652 }
5653 msleep(100);
5654 goto retry_rd_reg;
5655 }
5656 ql_dbg(ql_dbg_mbx, vha, 0x1142, "Done %s.\n", __func__);
5657 }
5658
5659 return rval;
5660}
5661
5662int
5663qla83xx_restart_nic_firmware(scsi_qla_host_t *vha)
5664{
5665 int rval;
5666 mbx_cmd_t mc;
5667 mbx_cmd_t *mcp = &mc;
5668 struct qla_hw_data *ha = vha->hw;
5669
b20f02e1 5670 if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha))
7d613ac6
SV		 5671 return QLA_FUNCTION_FAILED;
5672
5673 ql_dbg(ql_dbg_mbx, vha, 0x1143, "Entered %s.\n", __func__);
5674
5675 mcp->mb[0] = MBC_RESTART_NIC_FIRMWARE;
5676 mcp->out_mb = MBX_0;
5677 mcp->in_mb = MBX_1|MBX_0;
5678 mcp->tov = MBX_TOV_SECONDS;
5679 mcp->flags = 0;
5680 rval = qla2x00_mailbox_command(vha, mcp);
5681
5682 if (rval != QLA_SUCCESS) {
5683 ql_dbg(ql_dbg_mbx, vha, 0x1144,
5684 "Failed=%x mb[0]=%x mb[1]=%x.\n",
5685 rval, mcp->mb[0], mcp->mb[1]);
5686 ha->isp_ops->fw_dump(vha, 0);
5687 } else {
5688 ql_dbg(ql_dbg_mbx, vha, 0x1145, "Done %s.\n", __func__);
5689 }
5690
5691 return rval;
5692}
5693
5694int
5695qla83xx_access_control(scsi_qla_host_t *vha, uint16_t options,
5696 uint32_t start_addr, uint32_t end_addr, uint16_t *sector_size)
5697{
5698 int rval;
5699 mbx_cmd_t mc;
5700 mbx_cmd_t *mcp = &mc;
5701 uint8_t subcode = (uint8_t)options;
5702 struct qla_hw_data *ha = vha->hw;
5703
5704 if (!IS_QLA8031(ha))
5705 return QLA_FUNCTION_FAILED;
5706
5707 ql_dbg(ql_dbg_mbx, vha, 0x1146, "Entered %s.\n", __func__);
5708
5709 mcp->mb[0] = MBC_SET_ACCESS_CONTROL;
5710 mcp->mb[1] = options;
5711 mcp->out_mb = MBX_1|MBX_0;
5712 if (subcode & BIT_2) {
5713 mcp->mb[2] = LSW(start_addr);
5714 mcp->mb[3] = MSW(start_addr);
5715 mcp->mb[4] = LSW(end_addr);
5716 mcp->mb[5] = MSW(end_addr);
5717 mcp->out_mb |= MBX_5|MBX_4|MBX_3|MBX_2;
5718 }
5719 mcp->in_mb = MBX_2|MBX_1|MBX_0;
5720 if (!(subcode & (BIT_2 | BIT_5)))
5721 mcp->in_mb |= MBX_4|MBX_3;
5722 mcp->tov = MBX_TOV_SECONDS;
5723 mcp->flags = 0;
5724 rval = qla2x00_mailbox_command(vha, mcp);
5725
5726 if (rval != QLA_SUCCESS) {
5727 ql_dbg(ql_dbg_mbx, vha, 0x1147,
5728 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x mb[3]=%x mb[4]=%x.\n",
5729 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2], mcp->mb[3],
5730 mcp->mb[4]);
5731 ha->isp_ops->fw_dump(vha, 0);
5732 } else {
5733 if (subcode & BIT_5)
5734 *sector_size = mcp->mb[1];
5735 else if (subcode & (BIT_6 | BIT_7)) {
5736 ql_dbg(ql_dbg_mbx, vha, 0x1148,
5737 "Driver-lock id=%x%x", mcp->mb[4], mcp->mb[3]);
5738 } else if (subcode & (BIT_3 | BIT_4)) {
5739 ql_dbg(ql_dbg_mbx, vha, 0x1149,
5740 "Flash-lock id=%x%x", mcp->mb[4], mcp->mb[3]);
5741 }
5742 ql_dbg(ql_dbg_mbx, vha, 0x114a, "Done %s.\n", __func__);
5743 }
5744
5745 return rval;
5746}
81178772
SK		 5747
5748int
5749qla2x00_dump_mctp_data(scsi_qla_host_t *vha, dma_addr_t req_dma, uint32_t addr,
5750 uint32_t size)
5751{
5752 int rval;
5753 mbx_cmd_t mc;
5754 mbx_cmd_t *mcp = &mc;
5755
5756 if (!IS_MCTP_CAPABLE(vha->hw))
5757 return QLA_FUNCTION_FAILED;
5758
5759 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x114f,
5760 "Entered %s.\n", __func__);
5761
5762 mcp->mb[0] = MBC_DUMP_RISC_RAM_EXTENDED;
5763 mcp->mb[1] = LSW(addr);
5764 mcp->mb[2] = MSW(req_dma);
5765 mcp->mb[3] = LSW(req_dma);
5766 mcp->mb[4] = MSW(size);
5767 mcp->mb[5] = LSW(size);
5768 mcp->mb[6] = MSW(MSD(req_dma));
5769 mcp->mb[7] = LSW(MSD(req_dma));
5770 mcp->mb[8] = MSW(addr);
5771 /* Setting RAM ID to valid */
5772 mcp->mb[10] |= BIT_7;
5773 /* For MCTP RAM ID is 0x40 */
5774 mcp->mb[10] |= 0x40;
5775
5776 mcp->out_mb |= MBX_10|MBX_8|MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|
5777 MBX_0;
5778
5779 mcp->in_mb = MBX_0;
5780 mcp->tov = MBX_TOV_SECONDS;
5781 mcp->flags = 0;
5782 rval = qla2x00_mailbox_command(vha, mcp);
5783
5784 if (rval != QLA_SUCCESS) {
5785 ql_dbg(ql_dbg_mbx, vha, 0x114e,
5786 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
5787 } else {
5788 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x114d,
5789 "Done %s.\n", __func__);
5790 }
5791
5792 return rval;
5793}
ec891462
JC		 5794
5795int
5796qla26xx_dport_diagnostics(scsi_qla_host_t *vha,
5797 void *dd_buf, uint size, uint options)
5798{
5799 int rval;
5800 mbx_cmd_t mc;
5801 mbx_cmd_t *mcp = &mc;
5802 dma_addr_t dd_dma;
5803
5804 if (!IS_QLA83XX(vha->hw) && !IS_QLA27XX(vha->hw))
5805 return QLA_FUNCTION_FAILED;
5806
83548fe2 5807 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x119f,
ec891462
JC		 5808 "Entered %s.\n", __func__);
5809
ec891462
JC		 5810 dd_dma = dma_map_single(&vha->hw->pdev->dev,
5811 dd_buf, size, DMA_FROM_DEVICE);
5812 if (!dd_dma) {
5813 ql_log(ql_log_warn, vha, 0x1194, "Failed to map dma buffer.\n");
5814 return QLA_MEMORY_ALLOC_FAILED;
5815 }
5816
5817 memset(dd_buf, 0, size);
5818
5819 mcp->mb[0] = MBC_DPORT_DIAGNOSTICS;
5820 mcp->mb[1] = options;
5821 mcp->mb[2] = MSW(LSD(dd_dma));
5822 mcp->mb[3] = LSW(LSD(dd_dma));
5823 mcp->mb[6] = MSW(MSD(dd_dma));
5824 mcp->mb[7] = LSW(MSD(dd_dma));
5825 mcp->mb[8] = size;
5826 mcp->out_mb = MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
5827 mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0;
5828 mcp->buf_size = size;
5829 mcp->flags = MBX_DMA_IN;
5830 mcp->tov = MBX_TOV_SECONDS * 4;
5831 rval = qla2x00_mailbox_command(vha, mcp);
5832
5833 if (rval != QLA_SUCCESS) {
5834 ql_dbg(ql_dbg_mbx, vha, 0x1195, "Failed=%x.\n", rval);
5835 } else {
5836 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1196,
5837 "Done %s.\n", __func__);
5838 }
5839
5840 dma_unmap_single(&vha->hw->pdev->dev, dd_dma,
5841 size, DMA_FROM_DEVICE);
5842
5843 return rval;
5844}
15f30a57
QT		 5845
5846static void qla2x00_async_mb_sp_done(void *s, int res)
5847{
5848 struct srb *sp = s;
5849
5850 sp->u.iocb_cmd.u.mbx.rc = res;
5851
5852 complete(&sp->u.iocb_cmd.u.mbx.comp);
5853 /* don't free sp here. Let the caller do the free */
5854}
5855
5856/*
5857 * This mailbox uses the iocb interface to send MB command.
5858 * This allows non-critial (non chip setup) command to go
5859 * out in parrallel.
5860 */
5861int qla24xx_send_mb_cmd(struct scsi_qla_host *vha, mbx_cmd_t *mcp)
5862{
5863 int rval = QLA_FUNCTION_FAILED;
5864 srb_t *sp;
5865 struct srb_iocb *c;
5866
5867 if (!vha->hw->flags.fw_started)
5868 goto done;
5869
5870 sp = qla2x00_get_sp(vha, NULL, GFP_KERNEL);
5871 if (!sp)
5872 goto done;
5873
5874 sp->type = SRB_MB_IOCB;
5875 sp->name = mb_to_str(mcp->mb[0]);
5876
5877 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
5878
5879 memcpy(sp->u.iocb_cmd.u.mbx.out_mb, mcp->mb, SIZEOF_IOCB_MB_REG);
5880
5881 c = &sp->u.iocb_cmd;
5882 c->timeout = qla2x00_async_iocb_timeout;
5883 init_completion(&c->u.mbx.comp);
5884
5885 sp->done = qla2x00_async_mb_sp_done;
5886
5887 rval = qla2x00_start_sp(sp);
5888 if (rval != QLA_SUCCESS) {
83548fe2 5889 ql_dbg(ql_dbg_mbx, vha, 0x1018,
15f30a57
QT		 5890 "%s: %s Failed submission. %x.\n",
5891 __func__, sp->name, rval);
5892 goto done_free_sp;
5893 }
5894
83548fe2 5895 ql_dbg(ql_dbg_mbx, vha, 0x113f, "MB:%s hndl %x submitted\n",
15f30a57
QT		 5896 sp->name, sp->handle);
5897
5898 wait_for_completion(&c->u.mbx.comp);
5899 memcpy(mcp->mb, sp->u.iocb_cmd.u.mbx.in_mb, SIZEOF_IOCB_MB_REG);
5900
5901 rval = c->u.mbx.rc;
5902 switch (rval) {
5903 case QLA_FUNCTION_TIMEOUT:
83548fe2 5904 ql_dbg(ql_dbg_mbx, vha, 0x1140, "%s: %s Timeout. %x.\n",
15f30a57
QT		 5905 __func__, sp->name, rval);
5906 break;
5907 case QLA_SUCCESS:
83548fe2 5908 ql_dbg(ql_dbg_mbx, vha, 0x119d, "%s: %s done.\n",
15f30a57
QT		 5909 __func__, sp->name);
5910 sp->free(sp);
5911 break;
5912 default:
83548fe2 5913 ql_dbg(ql_dbg_mbx, vha, 0x119e, "%s: %s Failed. %x.\n",
15f30a57
QT		 5914 __func__, sp->name, rval);
5915 sp->free(sp);
5916 break;
5917 }
5918
5919 return rval;
5920
5921done_free_sp:
5922 sp->free(sp);
5923done:
5924 return rval;
5925}
5926
5927/*
5928 * qla24xx_gpdb_wait
5929 * NOTE: Do not call this routine from DPC thread
5930 */
5931int qla24xx_gpdb_wait(struct scsi_qla_host *vha, fc_port_t *fcport, u8 opt)
5932{
5933 int rval = QLA_FUNCTION_FAILED;
5934 dma_addr_t pd_dma;
5935 struct port_database_24xx *pd;
5936 struct qla_hw_data *ha = vha->hw;
5937 mbx_cmd_t mc;
5938
5939 if (!vha->hw->flags.fw_started)
5940 goto done;
5941
5942 pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &pd_dma);
5943 if (pd == NULL) {
83548fe2
QT		 5944 ql_log(ql_log_warn, vha, 0xd047,
5945 "Failed to allocate port database structure.\n");
15f30a57
QT		 5946 goto done_free_sp;
5947 }
5948 memset(pd, 0, max(PORT_DATABASE_SIZE, PORT_DATABASE_24XX_SIZE));
5949
5950 memset(&mc, 0, sizeof(mc));
5951 mc.mb[0] = MBC_GET_PORT_DATABASE;
5952 mc.mb[1] = cpu_to_le16(fcport->loop_id);
5953 mc.mb[2] = MSW(pd_dma);
5954 mc.mb[3] = LSW(pd_dma);
5955 mc.mb[6] = MSW(MSD(pd_dma));
5956 mc.mb[7] = LSW(MSD(pd_dma));
5957 mc.mb[9] = cpu_to_le16(vha->vp_idx);
5958 mc.mb[10] = cpu_to_le16((uint16_t)opt);
5959
5960 rval = qla24xx_send_mb_cmd(vha, &mc);
5961 if (rval != QLA_SUCCESS) {
83548fe2 5962 ql_dbg(ql_dbg_mbx, vha, 0x1193,
15f30a57
QT		 5963 "%s: %8phC fail\n", __func__, fcport->port_name);
5964 goto done_free_sp;
5965 }
5966
5967 rval = __qla24xx_parse_gpdb(vha, fcport, pd);
5968
83548fe2 5969 ql_dbg(ql_dbg_mbx, vha, 0x1197, "%s: %8phC done\n",
15f30a57
QT		 5970 __func__, fcport->port_name);
5971
5972done_free_sp:
5973 if (pd)
5974 dma_pool_free(ha->s_dma_pool, pd, pd_dma);
5975done:
5976 return rval;
5977}
5978
5979int __qla24xx_parse_gpdb(struct scsi_qla_host *vha, fc_port_t *fcport,
5980 struct port_database_24xx *pd)
5981{
5982 int rval = QLA_SUCCESS;
5983 uint64_t zero = 0;
a5d42f4c
DG		 5984 u8 current_login_state, last_login_state;
5985
5986 if (fcport->fc4f_nvme) {
5987 current_login_state = pd->current_login_state >> 4;
5988 last_login_state = pd->last_login_state >> 4;
5989 } else {
5990 current_login_state = pd->current_login_state & 0xf;
5991 last_login_state = pd->last_login_state & 0xf;
5992 }
15f30a57
QT		 5993
5994 /* Check for logged in state. */
a5d42f4c
DG		 5995 if (current_login_state != PDS_PRLI_COMPLETE &&
5996 last_login_state != PDS_PRLI_COMPLETE) {
83548fe2
QT		 5997 ql_dbg(ql_dbg_mbx, vha, 0x119a,
5998 "Unable to verify login-state (%x/%x) for loop_id %x.\n",
a5d42f4c 5999 current_login_state, last_login_state, fcport->loop_id);
15f30a57
QT		 6000 rval = QLA_FUNCTION_FAILED;
6001 goto gpd_error_out;
6002 }
6003
6004 if (fcport->loop_id == FC_NO_LOOP_ID ||
6005 (memcmp(fcport->port_name, (uint8_t *)&zero, 8) &&
6006 memcmp(fcport->port_name, pd->port_name, 8))) {
6007 /* We lost the device mid way. */
6008 rval = QLA_NOT_LOGGED_IN;
6009 goto gpd_error_out;
6010 }
6011
6012 /* Names are little-endian. */
6013 memcpy(fcport->node_name, pd->node_name, WWN_SIZE);
6014 memcpy(fcport->port_name, pd->port_name, WWN_SIZE);
6015
6016 /* Get port_id of device. */
6017 fcport->d_id.b.domain = pd->port_id[0];
6018 fcport->d_id.b.area = pd->port_id[1];
6019 fcport->d_id.b.al_pa = pd->port_id[2];
6020 fcport->d_id.b.rsvd_1 = 0;
6021
a5d42f4c
DG		 6022 if (fcport->fc4f_nvme) {
6023 fcport->nvme_prli_service_param =
6024 pd->prli_nvme_svc_param_word_3;
6025 fcport->port_type = FCT_NVME;
6026 } else {
6027 /* If not target must be initiator or unknown type. */
6028 if ((pd->prli_svc_param_word_3[0] & BIT_4) == 0)
6029 fcport->port_type = FCT_INITIATOR;
6030 else
6031 fcport->port_type = FCT_TARGET;
6032 }
15f30a57
QT		 6033 /* Passback COS information. */
6034 fcport->supported_classes = (pd->flags & PDF_CLASS_2) ?
6035 FC_COS_CLASS2 : FC_COS_CLASS3;
6036
6037 if (pd->prli_svc_param_word_3[0] & BIT_7) {
6038 fcport->flags |= FCF_CONF_COMP_SUPPORTED;
6039 fcport->conf_compl_supported = 1;
6040 }
6041
6042gpd_error_out:
6043 return rval;
6044}
6045
6046/*
6047 * qla24xx_gidlist__wait
6048 * NOTE: don't call this routine from DPC thread.
6049 */
6050int qla24xx_gidlist_wait(struct scsi_qla_host *vha,
6051 void *id_list, dma_addr_t id_list_dma, uint16_t *entries)
6052{
6053 int rval = QLA_FUNCTION_FAILED;
6054 mbx_cmd_t mc;
6055
6056 if (!vha->hw->flags.fw_started)
6057 goto done;
6058
6059 memset(&mc, 0, sizeof(mc));
6060 mc.mb[0] = MBC_GET_ID_LIST;
6061 mc.mb[2] = MSW(id_list_dma);
6062 mc.mb[3] = LSW(id_list_dma);
6063 mc.mb[6] = MSW(MSD(id_list_dma));
6064 mc.mb[7] = LSW(MSD(id_list_dma));
6065 mc.mb[8] = 0;
6066 mc.mb[9] = cpu_to_le16(vha->vp_idx);
6067
6068 rval = qla24xx_send_mb_cmd(vha, &mc);
6069 if (rval != QLA_SUCCESS) {
83548fe2
QT		 6070 ql_dbg(ql_dbg_mbx, vha, 0x119b,
6071 "%s: fail\n", __func__);
15f30a57
QT		 6072 } else {
6073 *entries = mc.mb[1];
83548fe2
QT		 6074 ql_dbg(ql_dbg_mbx, vha, 0x119c,
6075 "%s: done\n", __func__);
15f30a57
QT		 6076 }
6077done:
6078 return rval;
6079}
deeae7a6
DG		 6080
6081int qla27xx_set_zio_threshold(scsi_qla_host_t *vha, uint16_t value)
6082{
6083 int rval;
6084 mbx_cmd_t mc;
6085 mbx_cmd_t *mcp = &mc;
6086
6087 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1200,
6088 "Entered %s\n", __func__);
6089
6090 memset(mcp->mb, 0 , sizeof(mcp->mb));
6091 mcp->mb[0] = MBC_GET_SET_ZIO_THRESHOLD;
6092 mcp->mb[1] = cpu_to_le16(1);
6093 mcp->mb[2] = cpu_to_le16(value);
6094 mcp->out_mb = MBX_2 | MBX_1 | MBX_0;
6095 mcp->in_mb = MBX_2 | MBX_0;
6096 mcp->tov = MBX_TOV_SECONDS;
6097 mcp->flags = 0;
6098
6099 rval = qla2x00_mailbox_command(vha, mcp);
6100
6101 ql_dbg(ql_dbg_mbx, vha, 0x1201, "%s %x\n",
6102 (rval != QLA_SUCCESS) ? "Failed" : "Done", rval);
6103
6104 return rval;
6105}
6106
6107int qla27xx_get_zio_threshold(scsi_qla_host_t *vha, uint16_t *value)
6108{
6109 int rval;
6110 mbx_cmd_t mc;
6111 mbx_cmd_t *mcp = &mc;
6112
6113 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1203,
6114 "Entered %s\n", __func__);
6115
6116 memset(mcp->mb, 0, sizeof(mcp->mb));
6117 mcp->mb[0] = MBC_GET_SET_ZIO_THRESHOLD;
6118 mcp->mb[1] = cpu_to_le16(0);
6119 mcp->out_mb = MBX_1 | MBX_0;
6120 mcp->in_mb = MBX_2 | MBX_0;
6121 mcp->tov = MBX_TOV_SECONDS;
6122 mcp->flags = 0;
6123
6124 rval = qla2x00_mailbox_command(vha, mcp);
6125 if (rval == QLA_SUCCESS)
6126 *value = mc.mb[2];
6127
6128 ql_dbg(ql_dbg_mbx, vha, 0x1205, "%s %x\n",
6129 (rval != QLA_SUCCESS) ? "Failed" : "Done", rval);
6130
6131 return rval;
6132}
Linux 6.x block layer and io_uring tree(s)