projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
scsi: qla2xxx: Tweak resource count dump
[linux-2.6-block.git] / drivers / scsi / qla2xxx / qla_mbx.c
CommitLineData
1da177e4 1/*
fa90c54f 2 * QLogic Fibre Channel HBA Driver
bd21eaf9 3 * Copyright (c) 2003-2014 QLogic Corporation
1da177e4 4 *
fa90c54f 5 * See LICENSE.qla2xxx for copyright and licensing details.
1da177e4
LT		 6 */
7#include "qla_def.h"
2d70c103 8#include "qla_target.h"
1da177e4
LT		 9
10#include <linux/delay.h>
5a0e3ad6 11#include <linux/gfp.h>
1da177e4 12
15f30a57
QT		 13static struct mb_cmd_name {
14 uint16_t cmd;
15 const char *str;
16} mb_str[] = {
17 {MBC_GET_PORT_DATABASE, "GPDB"},
18 {MBC_GET_ID_LIST, "GIDList"},
19 {MBC_GET_LINK_PRIV_STATS, "Stats"},
94d83e36 20 {MBC_GET_RESOURCE_COUNTS, "ResCnt"},
15f30a57
QT		 21};
22
23static const char *mb_to_str(uint16_t cmd)
24{
25 int i;
26 struct mb_cmd_name *e;
27
28 for (i = 0; i < ARRAY_SIZE(mb_str); i++) {
29 e = mb_str + i;
30 if (cmd == e->cmd)
31 return e->str;
32 }
33 return "unknown";
34}
35
ca825828 36static struct rom_cmd {
77ddb94a 37 uint16_t cmd;
38} rom_cmds[] = {
39 { MBC_LOAD_RAM },
40 { MBC_EXECUTE_FIRMWARE },
41 { MBC_READ_RAM_WORD },
42 { MBC_MAILBOX_REGISTER_TEST },
43 { MBC_VERIFY_CHECKSUM },
44 { MBC_GET_FIRMWARE_VERSION },
45 { MBC_LOAD_RISC_RAM },
46 { MBC_DUMP_RISC_RAM },
47 { MBC_LOAD_RISC_RAM_EXTENDED },
48 { MBC_DUMP_RISC_RAM_EXTENDED },
49 { MBC_WRITE_RAM_WORD_EXTENDED },
50 { MBC_READ_RAM_EXTENDED },
51 { MBC_GET_RESOURCE_COUNTS },
52 { MBC_SET_FIRMWARE_OPTION },
53 { MBC_MID_INITIALIZE_FIRMWARE },
54 { MBC_GET_FIRMWARE_STATE },
55 { MBC_GET_MEM_OFFLOAD_CNTRL_STAT },
56 { MBC_GET_RETRY_COUNT },
57 { MBC_TRACE_CONTROL },
b7edfa23 58 { MBC_INITIALIZE_MULTIQ },
1608cc4a
QT		 59 { MBC_IOCB_COMMAND_A64 },
60 { MBC_GET_ADAPTER_LOOP_ID },
e4e3a2ce 61 { MBC_READ_SFP },
77ddb94a 62};
63
64static int is_rom_cmd(uint16_t cmd)
65{
66 int i;
67 struct rom_cmd *wc;
68
69 for (i = 0; i < ARRAY_SIZE(rom_cmds); i++) {
70 wc = rom_cmds + i;
71 if (wc->cmd == cmd)
72 return 1;
73 }
74
75 return 0;
76}
1da177e4
LT		 77
78/*
79 * qla2x00_mailbox_command
80 * Issue mailbox command and waits for completion.
81 *
82 * Input:
83 * ha = adapter block pointer.
84 * mcp = driver internal mbx struct pointer.
85 *
86 * Output:
87 * mb[MAX_MAILBOX_REGISTER_COUNT] = returned mailbox data.
88 *
89 * Returns:
90 * 0 : QLA_SUCCESS = cmd performed success
91 * 1 : QLA_FUNCTION_FAILED (error encountered)
92 * 6 : QLA_FUNCTION_TIMEOUT (timeout condition encountered)
93 *
94 * Context:
95 * Kernel context.
96 */
97static int
7b867cf7 98qla2x00_mailbox_command(scsi_qla_host_t *vha, mbx_cmd_t *mcp)
1da177e4 99{
d14e72fb 100 int rval, i;
1da177e4 101 unsigned long flags = 0;
f73cb695 102 device_reg_t *reg;
1c7c6357 103 uint8_t abort_active;
2c3dfe3f 104 uint8_t io_lock_on;
cdbb0a4f 105 uint16_t command = 0;
1da177e4
LT		 106 uint16_t *iptr;
107 uint16_t __iomem *optr;
108 uint32_t cnt;
109 uint32_t mboxes;
1da177e4 110 unsigned long wait_time;
7b867cf7
AC		 111 struct qla_hw_data *ha = vha->hw;
112 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
2c3dfe3f 113
d14e72fb 114
5e19ed90 115 ql_dbg(ql_dbg_mbx, vha, 0x1000, "Entered %s.\n", __func__);
7c3df132
SK		 116
117 if (ha->pdev->error_state > pci_channel_io_frozen) {
5e19ed90 118 ql_log(ql_log_warn, vha, 0x1001,
7c3df132
SK		 119 "error_state is greater than pci_channel_io_frozen, "
120 "exiting.\n");
b9b12f73 121 return QLA_FUNCTION_TIMEOUT;
7c3df132 122 }
b9b12f73 123
a9083016 124 if (vha->device_flags & DFLG_DEV_FAILED) {
5e19ed90 125 ql_log(ql_log_warn, vha, 0x1002,
7c3df132 126 "Device in failed state, exiting.\n");
a9083016
GM		 127 return QLA_FUNCTION_TIMEOUT;
128 }
129
c2a5d94f 130 /* if PCI error, then avoid mbx processing.*/
ba175891
SC		 131 if (test_bit(PFLG_DISCONNECTED, &base_vha->dpc_flags) &&
132 test_bit(UNLOADING, &base_vha->dpc_flags)) {
83548fe2 133 ql_log(ql_log_warn, vha, 0xd04e,
783e0dc4
SC		 134 "PCI error, exiting.\n");
135 return QLA_FUNCTION_TIMEOUT;
c2a5d94f 136 }
783e0dc4 137
2c3dfe3f 138 reg = ha->iobase;
7b867cf7 139 io_lock_on = base_vha->flags.init_done;
1da177e4
LT		 140
141 rval = QLA_SUCCESS;
7b867cf7 142 abort_active = test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1c7c6357 143
1da177e4 144
85880801 145 if (ha->flags.pci_channel_io_perm_failure) {
5e19ed90 146 ql_log(ql_log_warn, vha, 0x1003,
7c3df132 147 "Perm failure on EEH timeout MBX, exiting.\n");
85880801
AV		 148 return QLA_FUNCTION_TIMEOUT;
149 }
150
7ec0effd 151 if (IS_P3P_TYPE(ha) && ha->flags.isp82xx_fw_hung) {
862cd01e
GM		 152 /* Setting Link-Down error */
153 mcp->mb[0] = MBS_LINK_DOWN_ERROR;
5e19ed90 154 ql_log(ql_log_warn, vha, 0x1004,
7c3df132 155 "FW hung = %d.\n", ha->flags.isp82xx_fw_hung);
1806fcd5 156 return QLA_FUNCTION_TIMEOUT;
862cd01e
GM		 157 }
158
77ddb94a 159 /* check if ISP abort is active and return cmd with timeout */
160 if ((test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
161 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
162 test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) &&
163 !is_rom_cmd(mcp->mb[0])) {
164 ql_log(ql_log_info, vha, 0x1005,
165 "Cmd 0x%x aborted with timeout since ISP Abort is pending\n",
166 mcp->mb[0]);
167 return QLA_FUNCTION_TIMEOUT;
168 }
169
1da177e4 170 /*
1c7c6357
AV		 171 * Wait for active mailbox commands to finish by waiting at most tov
172 * seconds. This is to serialize actual issuing of mailbox cmds during
173 * non ISP abort time.
1da177e4 174 */
8eca3f39
AV		 175 if (!wait_for_completion_timeout(&ha->mbx_cmd_comp, mcp->tov * HZ)) {
176 /* Timeout occurred. Return error. */
83548fe2 177 ql_log(ql_log_warn, vha, 0xd035,
d8c0d546
CD		 178 "Cmd access timeout, cmd=0x%x, Exiting.\n",
179 mcp->mb[0]);
8eca3f39 180 return QLA_FUNCTION_TIMEOUT;
1da177e4
LT		 181 }
182
183 ha->flags.mbox_busy = 1;
184 /* Save mailbox command for debug */
185 ha->mcp = mcp;
186
5e19ed90 187 ql_dbg(ql_dbg_mbx, vha, 0x1006,
7c3df132 188 "Prepare to issue mbox cmd=0x%x.\n", mcp->mb[0]);
1da177e4
LT		 189
190 spin_lock_irqsave(&ha->hardware_lock, flags);
191
192 /* Load mailbox registers. */
7ec0effd 193 if (IS_P3P_TYPE(ha))
a9083016 194 optr = (uint16_t __iomem *)&reg->isp82.mailbox_in[0];
7ec0effd 195 else if (IS_FWI2_CAPABLE(ha) && !(IS_P3P_TYPE(ha)))
1c7c6357
AV		 196 optr = (uint16_t __iomem *)&reg->isp24.mailbox0;
197 else
198 optr = (uint16_t __iomem *)MAILBOX_REG(ha, &reg->isp, 0);
1da177e4
LT		 199
200 iptr = mcp->mb;
201 command = mcp->mb[0];
202 mboxes = mcp->out_mb;
203
7b711623 204 ql_dbg(ql_dbg_mbx, vha, 0x1111,
0e31a2c8 205 "Mailbox registers (OUT):\n");
1da177e4
LT		 206 for (cnt = 0; cnt < ha->mbx_count; cnt++) {
207 if (IS_QLA2200(ha) && cnt == 8)
1c7c6357
AV		 208 optr =
209 (uint16_t __iomem *)MAILBOX_REG(ha, &reg->isp, 8);
0e31a2c8
JC		 210 if (mboxes & BIT_0) {
211 ql_dbg(ql_dbg_mbx, vha, 0x1112,
212 "mbox[%d]<-0x%04x\n", cnt, *iptr);
1da177e4 213 WRT_REG_WORD(optr, *iptr);
0e31a2c8 214 }
1da177e4
LT		 215
216 mboxes >>= 1;
217 optr++;
218 iptr++;
219 }
220
5e19ed90 221 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1117,
7c3df132 222 "I/O Address = %p.\n", optr);
1da177e4
LT		 223
224 /* Issue set host interrupt command to send cmd out. */
225 ha->flags.mbox_int = 0;
226 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
227
228 /* Unlock mbx registers and wait for interrupt */
5e19ed90 229 ql_dbg(ql_dbg_mbx, vha, 0x100f,
7c3df132
SK		 230 "Going to unlock irq & waiting for interrupts. "
231 "jiffies=%lx.\n", jiffies);
1da177e4
LT		 232
233 /* Wait for mbx cmd completion until timeout */
234
124f85e6 235 if ((!abort_active && io_lock_on) || IS_NOPOLLING_TYPE(ha)) {
1da177e4
LT		 236 set_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags);
237
7ec0effd 238 if (IS_P3P_TYPE(ha)) {
a9083016
GM		 239 if (RD_REG_DWORD(&reg->isp82.hint) &
240 HINT_MBX_INT_PENDING) {
241 spin_unlock_irqrestore(&ha->hardware_lock,
242 flags);
8937f2f1 243 ha->flags.mbox_busy = 0;
5e19ed90 244 ql_dbg(ql_dbg_mbx, vha, 0x1010,
7c3df132 245 "Pending mailbox timeout, exiting.\n");
cdbb0a4f
SV		 246 rval = QLA_FUNCTION_TIMEOUT;
247 goto premature_exit;
a9083016
GM		 248 }
249 WRT_REG_DWORD(&reg->isp82.hint, HINT_MBX_INT_PENDING);
250 } else if (IS_FWI2_CAPABLE(ha))
1c7c6357
AV		 251 WRT_REG_DWORD(&reg->isp24.hccr, HCCRX_SET_HOST_INT);
252 else
253 WRT_REG_WORD(&reg->isp.hccr, HCCR_SET_HOST_INT);
1da177e4
LT		 254 spin_unlock_irqrestore(&ha->hardware_lock, flags);
255
77ddb94a 256 wait_time = jiffies;
754d1243
GM		 257 if (!wait_for_completion_timeout(&ha->mbx_intr_comp,
258 mcp->tov * HZ)) {
259 ql_dbg(ql_dbg_mbx, vha, 0x117a,
260 "cmd=%x Timeout.\n", command);
261 spin_lock_irqsave(&ha->hardware_lock, flags);
262 clear_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags);
263 spin_unlock_irqrestore(&ha->hardware_lock, flags);
264 }
77ddb94a 265 if (time_after(jiffies, wait_time + 5 * HZ))
266 ql_log(ql_log_warn, vha, 0x1015, "cmd=0x%x, waited %d msecs\n",
267 command, jiffies_to_msecs(jiffies - wait_time));
1da177e4 268 } else {
5e19ed90 269 ql_dbg(ql_dbg_mbx, vha, 0x1011,
7c3df132 270 "Cmd=%x Polling Mode.\n", command);
1da177e4 271
7ec0effd 272 if (IS_P3P_TYPE(ha)) {
a9083016
GM		 273 if (RD_REG_DWORD(&reg->isp82.hint) &
274 HINT_MBX_INT_PENDING) {
275 spin_unlock_irqrestore(&ha->hardware_lock,
276 flags);
8937f2f1 277 ha->flags.mbox_busy = 0;
5e19ed90 278 ql_dbg(ql_dbg_mbx, vha, 0x1012,
7c3df132 279 "Pending mailbox timeout, exiting.\n");
cdbb0a4f
SV		 280 rval = QLA_FUNCTION_TIMEOUT;
281 goto premature_exit;
a9083016
GM		 282 }
283 WRT_REG_DWORD(&reg->isp82.hint, HINT_MBX_INT_PENDING);
284 } else if (IS_FWI2_CAPABLE(ha))
1c7c6357
AV		 285 WRT_REG_DWORD(&reg->isp24.hccr, HCCRX_SET_HOST_INT);
286 else
287 WRT_REG_WORD(&reg->isp.hccr, HCCR_SET_HOST_INT);
1da177e4 288 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1da177e4
LT		 289
290 wait_time = jiffies + mcp->tov * HZ; /* wait at most tov secs */
291 while (!ha->flags.mbox_int) {
292 if (time_after(jiffies, wait_time))
293 break;
294
295 /* Check for pending interrupts. */
73208dfd 296 qla2x00_poll(ha->rsp_q_map[0]);
1da177e4 297
85880801
AV		 298 if (!ha->flags.mbox_int &&
299 !(IS_QLA2200(ha) &&
300 command == MBC_LOAD_RISC_RAM_EXTENDED))
59989831 301 msleep(10);
1da177e4 302 } /* while */
5e19ed90 303 ql_dbg(ql_dbg_mbx, vha, 0x1013,
7c3df132
SK		 304 "Waited %d sec.\n",
305 (uint)((jiffies - (wait_time - (mcp->tov * HZ)))/HZ));
1da177e4
LT		 306 }
307
1da177e4
LT		 308 /* Check whether we timed out */
309 if (ha->flags.mbox_int) {
310 uint16_t *iptr2;
311
5e19ed90 312 ql_dbg(ql_dbg_mbx, vha, 0x1014,
7c3df132 313 "Cmd=%x completed.\n", command);
1da177e4
LT		 314
315 /* Got interrupt. Clear the flag. */
316 ha->flags.mbox_int = 0;
317 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
318
7ec0effd 319 if (IS_P3P_TYPE(ha) && ha->flags.isp82xx_fw_hung) {
cdbb0a4f
SV		 320 ha->flags.mbox_busy = 0;
321 /* Setting Link-Down error */
322 mcp->mb[0] = MBS_LINK_DOWN_ERROR;
323 ha->mcp = NULL;
324 rval = QLA_FUNCTION_FAILED;
83548fe2 325 ql_log(ql_log_warn, vha, 0xd048,
7c3df132 326 "FW hung = %d.\n", ha->flags.isp82xx_fw_hung);
cdbb0a4f
SV		 327 goto premature_exit;
328 }
329
354d6b21 330 if (ha->mailbox_out[0] != MBS_COMMAND_COMPLETE)
1da177e4 331 rval = QLA_FUNCTION_FAILED;
1da177e4
LT		 332
333 /* Load return mailbox registers. */
334 iptr2 = mcp->mb;
335 iptr = (uint16_t *)&ha->mailbox_out[0];
336 mboxes = mcp->in_mb;
0e31a2c8
JC		 337
338 ql_dbg(ql_dbg_mbx, vha, 0x1113,
339 "Mailbox registers (IN):\n");
1da177e4 340 for (cnt = 0; cnt < ha->mbx_count; cnt++) {
0e31a2c8 341 if (mboxes & BIT_0) {
1da177e4 342 *iptr2 = *iptr;
0e31a2c8
JC		 343 ql_dbg(ql_dbg_mbx, vha, 0x1114,
344 "mbox[%d]->0x%04x\n", cnt, *iptr2);
345 }
1da177e4
LT		 346
347 mboxes >>= 1;
348 iptr2++;
349 iptr++;
350 }
351 } else {
352
8d3c9c23
QT		 353 uint16_t mb[8];
354 uint32_t ictrl, host_status, hccr;
783e0dc4 355 uint16_t w;
1c7c6357 356
e428924c 357 if (IS_FWI2_CAPABLE(ha)) {
8d3c9c23
QT		 358 mb[0] = RD_REG_WORD(&reg->isp24.mailbox0);
359 mb[1] = RD_REG_WORD(&reg->isp24.mailbox1);
360 mb[2] = RD_REG_WORD(&reg->isp24.mailbox2);
361 mb[3] = RD_REG_WORD(&reg->isp24.mailbox3);
362 mb[7] = RD_REG_WORD(&reg->isp24.mailbox7);
1c7c6357 363 ictrl = RD_REG_DWORD(&reg->isp24.ictrl);
8d3c9c23
QT		 364 host_status = RD_REG_DWORD(&reg->isp24.host_status);
365 hccr = RD_REG_DWORD(&reg->isp24.hccr);
366
83548fe2 367 ql_log(ql_log_warn, vha, 0xd04c,
8d3c9c23
QT		 368 "MBX Command timeout for cmd %x, iocontrol=%x jiffies=%lx "
369 "mb[0-3]=[0x%x 0x%x 0x%x 0x%x] mb7 0x%x host_status 0x%x hccr 0x%x\n",
370 command, ictrl, jiffies, mb[0], mb[1], mb[2], mb[3],
371 mb[7], host_status, hccr);
372
1c7c6357 373 } else {
8d3c9c23 374 mb[0] = RD_MAILBOX_REG(ha, &reg->isp, 0);
1c7c6357 375 ictrl = RD_REG_WORD(&reg->isp.ictrl);
8d3c9c23
QT		 376 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1119,
377 "MBX Command timeout for cmd %x, iocontrol=%x jiffies=%lx "
378 "mb[0]=0x%x\n", command, ictrl, jiffies, mb[0]);
1c7c6357 379 }
5e19ed90 380 ql_dump_regs(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1019);
1da177e4 381
783e0dc4
SC		 382 /* Capture FW dump only, if PCI device active */
383 if (!pci_channel_offline(vha->hw->pdev)) {
384 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w);
385 if (w == 0xffff || ictrl == 0xffffffff) {
386 /* This is special case if there is unload
387 * of driver happening and if PCI device go
388 * into bad state due to PCI error condition
389 * then only PCI ERR flag would be set.
390 * we will do premature exit for above case.
391 */
783e0dc4
SC		 392 ha->flags.mbox_busy = 0;
393 rval = QLA_FUNCTION_TIMEOUT;
394 goto premature_exit;
395 }
f55bfc88 396
783e0dc4
SC		 397 /* Attempt to capture firmware dump for further
398 * anallysis of the current formware state. we do not
399 * need to do this if we are intentionally generating
400 * a dump
401 */
402 if (mcp->mb[0] != MBC_GEN_SYSTEM_ERROR)
403 ha->isp_ops->fw_dump(vha, 0);
404 rval = QLA_FUNCTION_TIMEOUT;
405 }
1da177e4
LT		 406 }
407
1da177e4
LT		 408 ha->flags.mbox_busy = 0;
409
410 /* Clean up */
411 ha->mcp = NULL;
412
124f85e6 413 if ((abort_active || !io_lock_on) && !IS_NOPOLLING_TYPE(ha)) {
5e19ed90 414 ql_dbg(ql_dbg_mbx, vha, 0x101a,
7c3df132 415 "Checking for additional resp interrupt.\n");
1da177e4
LT		 416
417 /* polling mode for non isp_abort commands. */
73208dfd 418 qla2x00_poll(ha->rsp_q_map[0]);
1da177e4
LT		 419 }
420
1c7c6357
AV		 421 if (rval == QLA_FUNCTION_TIMEOUT &&
422 mcp->mb[0] != MBC_GEN_SYSTEM_ERROR) {
85880801
AV		 423 if (!io_lock_on || (mcp->flags & IOCTL_CMD) ||
424 ha->flags.eeh_busy) {
1da177e4 425 /* not in dpc. schedule it for dpc to take over. */
5e19ed90 426 ql_dbg(ql_dbg_mbx, vha, 0x101b,
7c3df132 427 "Timeout, schedule isp_abort_needed.\n");
cdbb0a4f
SV		 428
429 if (!test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) &&
430 !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) &&
431 !test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
63154916
GM		 432 if (IS_QLA82XX(ha)) {
433 ql_dbg(ql_dbg_mbx, vha, 0x112a,
434 "disabling pause transmit on port "
435 "0 & 1.\n");
436 qla82xx_wr_32(ha,
437 QLA82XX_CRB_NIU + 0x98,
438 CRB_NIU_XG_PAUSE_CTL_P0|
439 CRB_NIU_XG_PAUSE_CTL_P1);
440 }
7c3df132 441 ql_log(ql_log_info, base_vha, 0x101c,
24d9ee85 442 "Mailbox cmd timeout occurred, cmd=0x%x, "
d8c0d546
CD		 443 "mb[0]=0x%x, eeh_busy=0x%x. Scheduling ISP "
444 "abort.\n", command, mcp->mb[0],
445 ha->flags.eeh_busy);
cdbb0a4f
SV		 446 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
447 qla2xxx_wake_dpc(vha);
448 }
1da177e4 449 } else if (!abort_active) {
1da177e4 450 /* call abort directly since we are in the DPC thread */
5e19ed90 451 ql_dbg(ql_dbg_mbx, vha, 0x101d,
7c3df132 452 "Timeout, calling abort_isp.\n");
cdbb0a4f
SV		 453
454 if (!test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) &&
455 !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) &&
456 !test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
63154916
GM		 457 if (IS_QLA82XX(ha)) {
458 ql_dbg(ql_dbg_mbx, vha, 0x112b,
459 "disabling pause transmit on port "
460 "0 & 1.\n");
461 qla82xx_wr_32(ha,
462 QLA82XX_CRB_NIU + 0x98,
463 CRB_NIU_XG_PAUSE_CTL_P0|
464 CRB_NIU_XG_PAUSE_CTL_P1);
465 }
7c3df132 466 ql_log(ql_log_info, base_vha, 0x101e,
24d9ee85 467 "Mailbox cmd timeout occurred, cmd=0x%x, "
d8c0d546
CD		 468 "mb[0]=0x%x. Scheduling ISP abort ",
469 command, mcp->mb[0]);
cdbb0a4f
SV		 470 set_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags);
471 clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
d3360960
GM		 472 /* Allow next mbx cmd to come in. */
473 complete(&ha->mbx_cmd_comp);
cdbb0a4f
SV		 474 if (ha->isp_ops->abort_isp(vha)) {
475 /* Failed. retry later. */
476 set_bit(ISP_ABORT_NEEDED,
477 &vha->dpc_flags);
478 }
479 clear_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags);
5e19ed90 480 ql_dbg(ql_dbg_mbx, vha, 0x101f,
7c3df132 481 "Finished abort_isp.\n");
d3360960 482 goto mbx_done;
1da177e4 483 }
1da177e4
LT		 484 }
485 }
486
cdbb0a4f 487premature_exit:
1da177e4 488 /* Allow next mbx cmd to come in. */
8eca3f39 489 complete(&ha->mbx_cmd_comp);
1da177e4 490
d3360960 491mbx_done:
1da177e4 492 if (rval) {
050dc76a
JC		 493 if (ql2xextended_error_logging & (ql_dbg_disc|ql_dbg_mbx)) {
494 pr_warn("%s [%s]-%04x:%ld: **** Failed", QL_MSGHDR,
495 dev_name(&ha->pdev->dev), 0x1020+0x800,
496 vha->host_no);
497 mboxes = mcp->in_mb;
498 cnt = 4;
499 for (i = 0; i < ha->mbx_count && cnt; i++, mboxes >>= 1)
500 if (mboxes & BIT_0) {
501 printk(" mb[%u]=%x", i, mcp->mb[i]);
502 cnt--;
503 }
504 pr_warn(" cmd=%x ****\n", command);
505 }
75d560e0 506 ql_dbg(ql_dbg_mbx, vha, 0x1198,
050dc76a 507 "host_status=%#x intr_ctrl=%#x intr_status=%#x\n",
d14e72fb 508 RD_REG_DWORD(&reg->isp24.host_status),
d14e72fb
HM		 509 RD_REG_DWORD(&reg->isp24.ictrl),
510 RD_REG_DWORD(&reg->isp24.istatus));
1da177e4 511 } else {
7c3df132 512 ql_dbg(ql_dbg_mbx, base_vha, 0x1021, "Done %s.\n", __func__);
1da177e4
LT		 513 }
514
1da177e4
LT		 515 return rval;
516}
517
1da177e4 518int
7b867cf7 519qla2x00_load_ram(scsi_qla_host_t *vha, dma_addr_t req_dma, uint32_t risc_addr,
590f98e5 520 uint32_t risc_code_size)
1da177e4
LT		 521{
522 int rval;
7b867cf7 523 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 524 mbx_cmd_t mc;
525 mbx_cmd_t *mcp = &mc;
1da177e4 526
5f28d2d7
SK		 527 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1022,
528 "Entered %s.\n", __func__);
1da177e4 529
e428924c 530 if (MSW(risc_addr) || IS_FWI2_CAPABLE(ha)) {
590f98e5 531 mcp->mb[0] = MBC_LOAD_RISC_RAM_EXTENDED;
532 mcp->mb[8] = MSW(risc_addr);
533 mcp->out_mb = MBX_8|MBX_0;
1da177e4 534 } else {
590f98e5 535 mcp->mb[0] = MBC_LOAD_RISC_RAM;
536 mcp->out_mb = MBX_0;
1da177e4 537 }
1da177e4
LT		 538 mcp->mb[1] = LSW(risc_addr);
539 mcp->mb[2] = MSW(req_dma);
540 mcp->mb[3] = LSW(req_dma);
1da177e4
LT		 541 mcp->mb[6] = MSW(MSD(req_dma));
542 mcp->mb[7] = LSW(MSD(req_dma));
590f98e5 543 mcp->out_mb |= MBX_7|MBX_6|MBX_3|MBX_2|MBX_1;
e428924c 544 if (IS_FWI2_CAPABLE(ha)) {
1c7c6357
AV		 545 mcp->mb[4] = MSW(risc_code_size);
546 mcp->mb[5] = LSW(risc_code_size);
547 mcp->out_mb |= MBX_5|MBX_4;
548 } else {
549 mcp->mb[4] = LSW(risc_code_size);
550 mcp->out_mb |= MBX_4;
551 }
552
1da177e4 553 mcp->in_mb = MBX_0;
b93480e3 554 mcp->tov = MBX_TOV_SECONDS;
1da177e4 555 mcp->flags = 0;
7b867cf7 556 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4 557
1da177e4 558 if (rval != QLA_SUCCESS) {
7c3df132
SK		 559 ql_dbg(ql_dbg_mbx, vha, 0x1023,
560 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
1da177e4 561 } else {
5f28d2d7
SK		 562 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1024,
563 "Done %s.\n", __func__);
1da177e4
LT		 564 }
565
566 return rval;
567}
568
cad454b1 569#define EXTENDED_BB_CREDITS BIT_0
e84067d7 570#define NVME_ENABLE_FLAG BIT_3
1f4c7c38
JC		 571static inline uint16_t qla25xx_set_sfp_lr_dist(struct qla_hw_data *ha)
572{
573 uint16_t mb4 = BIT_0;
574
575 if (IS_QLA83XX(ha) || IS_QLA27XX(ha))
576 mb4 |= ha->long_range_distance << LR_DIST_FW_POS;
577
578 return mb4;
579}
580
581static inline uint16_t qla25xx_set_nvr_lr_dist(struct qla_hw_data *ha)
582{
583 uint16_t mb4 = BIT_0;
584
585 if (IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
586 struct nvram_81xx *nv = ha->nvram;
587
588 mb4 |= LR_DIST_FW_FIELD(nv->enhanced_features);
589 }
590
591 return mb4;
592}
e84067d7 593
1da177e4
LT		 594/*
595 * qla2x00_execute_fw
1c7c6357 596 * Start adapter firmware.
1da177e4
LT		 597 *
598 * Input:
1c7c6357
AV		 599 * ha = adapter block pointer.
600 * TARGET_QUEUE_LOCK must be released.
601 * ADAPTER_STATE_LOCK must be released.
1da177e4
LT		 602 *
603 * Returns:
1c7c6357 604 * qla2x00 local function return status code.
1da177e4
LT		 605 *
606 * Context:
1c7c6357 607 * Kernel context.
1da177e4
LT		 608 */
609int
7b867cf7 610qla2x00_execute_fw(scsi_qla_host_t *vha, uint32_t risc_addr)
1da177e4
LT		 611{
612 int rval;
7b867cf7 613 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 614 mbx_cmd_t mc;
615 mbx_cmd_t *mcp = &mc;
616
5f28d2d7
SK		 617 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1025,
618 "Entered %s.\n", __func__);
1da177e4
LT		 619
620 mcp->mb[0] = MBC_EXECUTE_FIRMWARE;
1c7c6357
AV		 621 mcp->out_mb = MBX_0;
622 mcp->in_mb = MBX_0;
e428924c 623 if (IS_FWI2_CAPABLE(ha)) {
1c7c6357
AV		 624 mcp->mb[1] = MSW(risc_addr);
625 mcp->mb[2] = LSW(risc_addr);
626 mcp->mb[3] = 0;
e4e3a2ce 627 mcp->mb[4] = 0;
1f4c7c38 628 ha->flags.using_lr_setting = 0;
f73cb695
CD		 629 if (IS_QLA25XX(ha) || IS_QLA81XX(ha) || IS_QLA83XX(ha) ||
630 IS_QLA27XX(ha)) {
e4e3a2ce
QT		 631 if (ql2xautodetectsfp) {
632 if (ha->flags.detected_lr_sfp) {
1f4c7c38
JC		 633 mcp->mb[4] |=
634 qla25xx_set_sfp_lr_dist(ha);
e4e3a2ce
QT		 635 ha->flags.using_lr_setting = 1;
636 }
637 } else {
638 struct nvram_81xx *nv = ha->nvram;
1f4c7c38 639 /* set LR distance if specified in nvram */
e4e3a2ce 640 if (nv->enhanced_features &
1f4c7c38
JC		 641 NEF_LR_DIST_ENABLE) {
642 mcp->mb[4] |=
643 qla25xx_set_nvr_lr_dist(ha);
e4e3a2ce
QT		 644 ha->flags.using_lr_setting = 1;
645 }
646 }
e4e3a2ce 647 }
b0d6cabd 648
e84067d7
DG		 649 if (ql2xnvmeenable && IS_QLA27XX(ha))
650 mcp->mb[4] |= NVME_ENABLE_FLAG;
651
92d4408e
SC		 652 if (IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
653 struct nvram_81xx *nv = ha->nvram;
654 /* set minimum speed if specified in nvram */
655 if (nv->min_link_speed >= 2 &&
656 nv->min_link_speed <= 5) {
657 mcp->mb[4] |= BIT_4;
658 mcp->mb[11] = nv->min_link_speed;
659 mcp->out_mb |= MBX_11;
660 mcp->in_mb |= BIT_5;
661 vha->min_link_speed_feat = nv->min_link_speed;
662 }
663 }
664
b0d6cabd
HM		 665 if (ha->flags.exlogins_enabled)
666 mcp->mb[4] |= ENABLE_EXTENDED_LOGIN;
667
2f56a7f1
HM		 668 if (ha->flags.exchoffld_enabled)
669 mcp->mb[4] |= ENABLE_EXCHANGE_OFFLD;
670
8b3253d1 671 mcp->out_mb |= MBX_4|MBX_3|MBX_2|MBX_1;
1f4c7c38 672 mcp->in_mb |= MBX_3 | MBX_2 | MBX_1;
1c7c6357
AV		 673 } else {
674 mcp->mb[1] = LSW(risc_addr);
675 mcp->out_mb |= MBX_1;
676 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
677 mcp->mb[2] = 0;
678 mcp->out_mb |= MBX_2;
679 }
1da177e4
LT		 680 }
681
b93480e3 682 mcp->tov = MBX_TOV_SECONDS;
1da177e4 683 mcp->flags = 0;
7b867cf7 684 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4 685
1c7c6357 686 if (rval != QLA_SUCCESS) {
7c3df132
SK		 687 ql_dbg(ql_dbg_mbx, vha, 0x1026,
688 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
1c7c6357 689 } else {
e428924c 690 if (IS_FWI2_CAPABLE(ha)) {
1f4c7c38
JC		 691 ha->fw_ability_mask = mcp->mb[3] << 16 | mcp->mb[2];
692 ql_dbg(ql_dbg_mbx, vha, 0x119a,
693 "fw_ability_mask=%x.\n", ha->fw_ability_mask);
92d4408e
SC		 694 ql_dbg(ql_dbg_mbx, vha, 0x1027,
695 "exchanges=%x.\n", mcp->mb[1]);
1f4c7c38
JC		 696 if (IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
697 ha->max_speed_sup = mcp->mb[2] & BIT_0;
92d4408e
SC		 698 ql_dbg(ql_dbg_mbx, vha, 0x119b,
699 "Maximum speed supported=%s.\n",
700 ha->max_speed_sup ? "32Gps" : "16Gps");
701 if (vha->min_link_speed_feat) {
702 ha->min_link_speed = mcp->mb[5];
703 ql_dbg(ql_dbg_mbx, vha, 0x119c,
704 "Minimum speed set=%s.\n",
705 mcp->mb[5] == 5 ? "32Gps" :
706 mcp->mb[5] == 4 ? "16Gps" :
707 mcp->mb[5] == 3 ? "8Gps" :
708 mcp->mb[5] == 2 ? "4Gps" :
1f4c7c38 709 "unknown");
92d4408e
SC		 710 }
711 }
1c7c6357 712 }
1f4c7c38
JC		 713 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1028,
714 "Done.\n");
1c7c6357 715 }
1da177e4
LT		 716
717 return rval;
718}
719
b0d6cabd
HM		 720/*
721 * qla_get_exlogin_status
722 * Get extended login status
723 * uses the memory offload control/status Mailbox
724 *
725 * Input:
726 * ha: adapter state pointer.
727 * fwopt: firmware options
728 *
729 * Returns:
730 * qla2x00 local function status
731 *
732 * Context:
733 * Kernel context.
734 */
735#define FETCH_XLOGINS_STAT 0x8
736int
737qla_get_exlogin_status(scsi_qla_host_t *vha, uint16_t *buf_sz,
738 uint16_t *ex_logins_cnt)
739{
740 int rval;
741 mbx_cmd_t mc;
742 mbx_cmd_t *mcp = &mc;
743
744 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x118f,
745 "Entered %s\n", __func__);
746
747 memset(mcp->mb, 0 , sizeof(mcp->mb));
748 mcp->mb[0] = MBC_GET_MEM_OFFLOAD_CNTRL_STAT;
749 mcp->mb[1] = FETCH_XLOGINS_STAT;
750 mcp->out_mb = MBX_1|MBX_0;
751 mcp->in_mb = MBX_10|MBX_4|MBX_0;
752 mcp->tov = MBX_TOV_SECONDS;
753 mcp->flags = 0;
754
755 rval = qla2x00_mailbox_command(vha, mcp);
756 if (rval != QLA_SUCCESS) {
757 ql_dbg(ql_dbg_mbx, vha, 0x1115, "Failed=%x.\n", rval);
758 } else {
759 *buf_sz = mcp->mb[4];
760 *ex_logins_cnt = mcp->mb[10];
761
762 ql_log(ql_log_info, vha, 0x1190,
763 "buffer size 0x%x, exchange login count=%d\n",
764 mcp->mb[4], mcp->mb[10]);
765
766 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1116,
767 "Done %s.\n", __func__);
768 }
769
770 return rval;
771}
772
773/*
774 * qla_set_exlogin_mem_cfg
775 * set extended login memory configuration
776 * Mbx needs to be issues before init_cb is set
777 *
778 * Input:
779 * ha: adapter state pointer.
780 * buffer: buffer pointer
781 * phys_addr: physical address of buffer
782 * size: size of buffer
783 * TARGET_QUEUE_LOCK must be released
784 * ADAPTER_STATE_LOCK must be release
785 *
786 * Returns:
787 * qla2x00 local funxtion status code.
788 *
789 * Context:
790 * Kernel context.
791 */
792#define CONFIG_XLOGINS_MEM 0x3
793int
794qla_set_exlogin_mem_cfg(scsi_qla_host_t *vha, dma_addr_t phys_addr)
795{
796 int rval;
797 mbx_cmd_t mc;
798 mbx_cmd_t *mcp = &mc;
799 struct qla_hw_data *ha = vha->hw;
b0d6cabd
HM		 800
801 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x111a,
802 "Entered %s.\n", __func__);
803
804 memset(mcp->mb, 0 , sizeof(mcp->mb));
805 mcp->mb[0] = MBC_GET_MEM_OFFLOAD_CNTRL_STAT;
806 mcp->mb[1] = CONFIG_XLOGINS_MEM;
807 mcp->mb[2] = MSW(phys_addr);
808 mcp->mb[3] = LSW(phys_addr);
809 mcp->mb[6] = MSW(MSD(phys_addr));
810 mcp->mb[7] = LSW(MSD(phys_addr));
811 mcp->mb[8] = MSW(ha->exlogin_size);
812 mcp->mb[9] = LSW(ha->exlogin_size);
813 mcp->out_mb = MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
814 mcp->in_mb = MBX_11|MBX_0;
815 mcp->tov = MBX_TOV_SECONDS;
816 mcp->flags = 0;
817 rval = qla2x00_mailbox_command(vha, mcp);
818 if (rval != QLA_SUCCESS) {
819 /*EMPTY*/
820 ql_dbg(ql_dbg_mbx, vha, 0x111b, "Failed=%x.\n", rval);
821 } else {
b0d6cabd
HM		 822 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x118c,
823 "Done %s.\n", __func__);
824 }
825
826 return rval;
827}
828
2f56a7f1
HM		 829/*
830 * qla_get_exchoffld_status
831 * Get exchange offload status
832 * uses the memory offload control/status Mailbox
833 *
834 * Input:
835 * ha: adapter state pointer.
836 * fwopt: firmware options
837 *
838 * Returns:
839 * qla2x00 local function status
840 *
841 * Context:
842 * Kernel context.
843 */
844#define FETCH_XCHOFFLD_STAT 0x2
845int
846qla_get_exchoffld_status(scsi_qla_host_t *vha, uint16_t *buf_sz,
847 uint16_t *ex_logins_cnt)
848{
849 int rval;
850 mbx_cmd_t mc;
851 mbx_cmd_t *mcp = &mc;
852
853 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1019,
854 "Entered %s\n", __func__);
855
856 memset(mcp->mb, 0 , sizeof(mcp->mb));
857 mcp->mb[0] = MBC_GET_MEM_OFFLOAD_CNTRL_STAT;
858 mcp->mb[1] = FETCH_XCHOFFLD_STAT;
859 mcp->out_mb = MBX_1|MBX_0;
860 mcp->in_mb = MBX_10|MBX_4|MBX_0;
861 mcp->tov = MBX_TOV_SECONDS;
862 mcp->flags = 0;
863
864 rval = qla2x00_mailbox_command(vha, mcp);
865 if (rval != QLA_SUCCESS) {
866 ql_dbg(ql_dbg_mbx, vha, 0x1155, "Failed=%x.\n", rval);
867 } else {
868 *buf_sz = mcp->mb[4];
869 *ex_logins_cnt = mcp->mb[10];
870
871 ql_log(ql_log_info, vha, 0x118e,
872 "buffer size 0x%x, exchange offload count=%d\n",
873 mcp->mb[4], mcp->mb[10]);
874
875 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1156,
876 "Done %s.\n", __func__);
877 }
878
879 return rval;
880}
881
882/*
883 * qla_set_exchoffld_mem_cfg
884 * Set exchange offload memory configuration
885 * Mbx needs to be issues before init_cb is set
886 *
887 * Input:
888 * ha: adapter state pointer.
889 * buffer: buffer pointer
890 * phys_addr: physical address of buffer
891 * size: size of buffer
892 * TARGET_QUEUE_LOCK must be released
893 * ADAPTER_STATE_LOCK must be release
894 *
895 * Returns:
896 * qla2x00 local funxtion status code.
897 *
898 * Context:
899 * Kernel context.
900 */
901#define CONFIG_XCHOFFLD_MEM 0x3
902int
99e1b683 903qla_set_exchoffld_mem_cfg(scsi_qla_host_t *vha)
2f56a7f1
HM		 904{
905 int rval;
906 mbx_cmd_t mc;
907 mbx_cmd_t *mcp = &mc;
908 struct qla_hw_data *ha = vha->hw;
909
910 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1157,
911 "Entered %s.\n", __func__);
912
913 memset(mcp->mb, 0 , sizeof(mcp->mb));
914 mcp->mb[0] = MBC_GET_MEM_OFFLOAD_CNTRL_STAT;
915 mcp->mb[1] = CONFIG_XCHOFFLD_MEM;
99e1b683
QT		 916 mcp->mb[2] = MSW(ha->exchoffld_buf_dma);
917 mcp->mb[3] = LSW(ha->exchoffld_buf_dma);
918 mcp->mb[6] = MSW(MSD(ha->exchoffld_buf_dma));
919 mcp->mb[7] = LSW(MSD(ha->exchoffld_buf_dma));
920 mcp->mb[8] = MSW(ha->exchoffld_size);
921 mcp->mb[9] = LSW(ha->exchoffld_size);
2f56a7f1
HM		 922 mcp->out_mb = MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
923 mcp->in_mb = MBX_11|MBX_0;
924 mcp->tov = MBX_TOV_SECONDS;
925 mcp->flags = 0;
926 rval = qla2x00_mailbox_command(vha, mcp);
927 if (rval != QLA_SUCCESS) {
928 /*EMPTY*/
929 ql_dbg(ql_dbg_mbx, vha, 0x1158, "Failed=%x.\n", rval);
930 } else {
931 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1192,
932 "Done %s.\n", __func__);
933 }
934
935 return rval;
936}
937
1da177e4
LT		 938/*
939 * qla2x00_get_fw_version
940 * Get firmware version.
941 *
942 * Input:
943 * ha: adapter state pointer.
944 * major: pointer for major number.
945 * minor: pointer for minor number.
946 * subminor: pointer for subminor number.
947 *
948 * Returns:
949 * qla2x00 local function return status code.
950 *
951 * Context:
952 * Kernel context.
953 */
ca9e9c3e 954int
6246b8a1 955qla2x00_get_fw_version(scsi_qla_host_t *vha)
1da177e4
LT		 956{
957 int rval;
958 mbx_cmd_t mc;
959 mbx_cmd_t *mcp = &mc;
6246b8a1 960 struct qla_hw_data *ha = vha->hw;
1da177e4 961
5f28d2d7
SK		 962 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1029,
963 "Entered %s.\n", __func__);
1da177e4
LT		 964
965 mcp->mb[0] = MBC_GET_FIRMWARE_VERSION;
966 mcp->out_mb = MBX_0;
967 mcp->in_mb = MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
7ec0effd 968 if (IS_QLA81XX(vha->hw) || IS_QLA8031(ha) || IS_QLA8044(ha))
55a96158 969 mcp->in_mb |= MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8;
fb0effee 970 if (IS_FWI2_CAPABLE(ha))
6246b8a1 971 mcp->in_mb |= MBX_17|MBX_16|MBX_15;
f73cb695 972 if (IS_QLA27XX(ha))
ad1ef177
JC		 973 mcp->in_mb |=
974 MBX_25|MBX_24|MBX_23|MBX_22|MBX_21|MBX_20|MBX_19|MBX_18|
975 MBX_14|MBX_13|MBX_11|MBX_10|MBX_9|MBX_8;
03aa868c 976
1da177e4 977 mcp->flags = 0;
b93480e3 978 mcp->tov = MBX_TOV_SECONDS;
7b867cf7 979 rval = qla2x00_mailbox_command(vha, mcp);
ca9e9c3e
AV		 980 if (rval != QLA_SUCCESS)
981 goto failed;
1da177e4
LT		 982
983 /* Return mailbox data. */
6246b8a1
GM		 984 ha->fw_major_version = mcp->mb[1];
985 ha->fw_minor_version = mcp->mb[2];
986 ha->fw_subminor_version = mcp->mb[3];
987 ha->fw_attributes = mcp->mb[6];
7b867cf7 988 if (IS_QLA2100(vha->hw) || IS_QLA2200(vha->hw))
6246b8a1 989 ha->fw_memory_size = 0x1FFFF; /* Defaults to 128KB. */
1da177e4 990 else
6246b8a1 991 ha->fw_memory_size = (mcp->mb[5] << 16) | mcp->mb[4];
03aa868c 992
7ec0effd 993 if (IS_QLA81XX(vha->hw) || IS_QLA8031(vha->hw) || IS_QLA8044(ha)) {
6246b8a1
GM		 994 ha->mpi_version[0] = mcp->mb[10] & 0xff;
995 ha->mpi_version[1] = mcp->mb[11] >> 8;
996 ha->mpi_version[2] = mcp->mb[11] & 0xff;
997 ha->mpi_capabilities = (mcp->mb[12] << 16) | mcp->mb[13];
998 ha->phy_version[0] = mcp->mb[8] & 0xff;
999 ha->phy_version[1] = mcp->mb[9] >> 8;
1000 ha->phy_version[2] = mcp->mb[9] & 0xff;
1001 }
03aa868c 1002
81178772
SK		 1003 if (IS_FWI2_CAPABLE(ha)) {
1004 ha->fw_attributes_h = mcp->mb[15];
1005 ha->fw_attributes_ext[0] = mcp->mb[16];
1006 ha->fw_attributes_ext[1] = mcp->mb[17];
1007 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1139,
1008 "%s: FW_attributes Upper: 0x%x, Lower: 0x%x.\n",
1009 __func__, mcp->mb[15], mcp->mb[6]);
1010 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x112f,
1011 "%s: Ext_FwAttributes Upper: 0x%x, Lower: 0x%x.\n",
1012 __func__, mcp->mb[17], mcp->mb[16]);
2f56a7f1 1013
b0d6cabd
HM		 1014 if (ha->fw_attributes_h & 0x4)
1015 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x118d,
1016 "%s: Firmware supports Extended Login 0x%x\n",
1017 __func__, ha->fw_attributes_h);
2f56a7f1
HM		 1018
1019 if (ha->fw_attributes_h & 0x8)
1020 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1191,
1021 "%s: Firmware supports Exchange Offload 0x%x\n",
1022 __func__, ha->fw_attributes_h);
e84067d7 1023
deeae7a6
DG		 1024 /*
1025 * FW supports nvme and driver load parameter requested nvme.
1026 * BIT 26 of fw_attributes indicates NVMe support.
1027 */
1028 if ((ha->fw_attributes_h & 0x400) && ql2xnvmeenable)
e84067d7 1029 vha->flags.nvme_enabled = 1;
e84067d7 1030
3a03eb79 1031 }
03aa868c 1032
f73cb695 1033 if (IS_QLA27XX(ha)) {
03aa868c
SC		 1034 ha->mpi_version[0] = mcp->mb[10] & 0xff;
1035 ha->mpi_version[1] = mcp->mb[11] >> 8;
1036 ha->mpi_version[2] = mcp->mb[11] & 0xff;
1037 ha->pep_version[0] = mcp->mb[13] & 0xff;
1038 ha->pep_version[1] = mcp->mb[14] >> 8;
1039 ha->pep_version[2] = mcp->mb[14] & 0xff;
f73cb695
CD		 1040 ha->fw_shared_ram_start = (mcp->mb[19] << 16) | mcp->mb[18];
1041 ha->fw_shared_ram_end = (mcp->mb[21] << 16) | mcp->mb[20];
ad1ef177
JC		 1042 ha->fw_ddr_ram_start = (mcp->mb[23] << 16) | mcp->mb[22];
1043 ha->fw_ddr_ram_end = (mcp->mb[25] << 16) | mcp->mb[24];
f73cb695 1044 }
6246b8a1 1045
ca9e9c3e 1046failed:
1da177e4
LT		 1047 if (rval != QLA_SUCCESS) {
1048 /*EMPTY*/
7c3df132 1049 ql_dbg(ql_dbg_mbx, vha, 0x102a, "Failed=%x.\n", rval);
1da177e4
LT		 1050 } else {
1051 /*EMPTY*/
5f28d2d7
SK		 1052 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x102b,
1053 "Done %s.\n", __func__);
1da177e4 1054 }
ca9e9c3e 1055 return rval;
1da177e4
LT		 1056}
1057
1058/*
1059 * qla2x00_get_fw_options
1060 * Set firmware options.
1061 *
1062 * Input:
1063 * ha = adapter block pointer.
1064 * fwopt = pointer for firmware options.
1065 *
1066 * Returns:
1067 * qla2x00 local function return status code.
1068 *
1069 * Context:
1070 * Kernel context.
1071 */
1072int
7b867cf7 1073qla2x00_get_fw_options(scsi_qla_host_t *vha, uint16_t *fwopts)
1da177e4
LT		 1074{
1075 int rval;
1076 mbx_cmd_t mc;
1077 mbx_cmd_t *mcp = &mc;
1078
5f28d2d7
SK		 1079 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x102c,
1080 "Entered %s.\n", __func__);
1da177e4
LT		 1081
1082 mcp->mb[0] = MBC_GET_FIRMWARE_OPTION;
1083 mcp->out_mb = MBX_0;
1084 mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0;
b93480e3 1085 mcp->tov = MBX_TOV_SECONDS;
1da177e4 1086 mcp->flags = 0;
7b867cf7 1087 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 1088
1089 if (rval != QLA_SUCCESS) {
1090 /*EMPTY*/
7c3df132 1091 ql_dbg(ql_dbg_mbx, vha, 0x102d, "Failed=%x.\n", rval);
1da177e4 1092 } else {
1c7c6357 1093 fwopts[0] = mcp->mb[0];
1da177e4
LT		 1094 fwopts[1] = mcp->mb[1];
1095 fwopts[2] = mcp->mb[2];
1096 fwopts[3] = mcp->mb[3];
1097
5f28d2d7
SK		 1098 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x102e,
1099 "Done %s.\n", __func__);
1da177e4
LT		 1100 }
1101
1102 return rval;
1103}
1104
1105
1106/*
1107 * qla2x00_set_fw_options
1108 * Set firmware options.
1109 *
1110 * Input:
1111 * ha = adapter block pointer.
1112 * fwopt = pointer for firmware options.
1113 *
1114 * Returns:
1115 * qla2x00 local function return status code.
1116 *
1117 * Context:
1118 * Kernel context.
1119 */
1120int
7b867cf7 1121qla2x00_set_fw_options(scsi_qla_host_t *vha, uint16_t *fwopts)
1da177e4
LT		 1122{
1123 int rval;
1124 mbx_cmd_t mc;
1125 mbx_cmd_t *mcp = &mc;
1126
5f28d2d7
SK		 1127 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x102f,
1128 "Entered %s.\n", __func__);
1da177e4
LT		 1129
1130 mcp->mb[0] = MBC_SET_FIRMWARE_OPTION;
1131 mcp->mb[1] = fwopts[1];
1132 mcp->mb[2] = fwopts[2];
1133 mcp->mb[3] = fwopts[3];
1c7c6357 1134 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
1da177e4 1135 mcp->in_mb = MBX_0;
7b867cf7 1136 if (IS_FWI2_CAPABLE(vha->hw)) {
1c7c6357 1137 mcp->in_mb |= MBX_1;
2da52737
QT		 1138 mcp->mb[10] = fwopts[10];
1139 mcp->out_mb |= MBX_10;
1c7c6357
AV		 1140 } else {
1141 mcp->mb[10] = fwopts[10];
1142 mcp->mb[11] = fwopts[11];
1143 mcp->mb[12] = 0; /* Undocumented, but used */
1144 mcp->out_mb |= MBX_12|MBX_11|MBX_10;
1145 }
b93480e3 1146 mcp->tov = MBX_TOV_SECONDS;
1da177e4 1147 mcp->flags = 0;
7b867cf7 1148 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4 1149
1c7c6357
AV		 1150 fwopts[0] = mcp->mb[0];
1151
1da177e4
LT		 1152 if (rval != QLA_SUCCESS) {
1153 /*EMPTY*/
7c3df132
SK		 1154 ql_dbg(ql_dbg_mbx, vha, 0x1030,
1155 "Failed=%x (%x/%x).\n", rval, mcp->mb[0], mcp->mb[1]);
1da177e4
LT		 1156 } else {
1157 /*EMPTY*/
5f28d2d7
SK		 1158 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1031,
1159 "Done %s.\n", __func__);
1da177e4
LT		 1160 }
1161
1162 return rval;
1163}
1164
1165/*
1166 * qla2x00_mbx_reg_test
1167 * Mailbox register wrap test.
1168 *
1169 * Input:
1170 * ha = adapter block pointer.
1171 * TARGET_QUEUE_LOCK must be released.
1172 * ADAPTER_STATE_LOCK must be released.
1173 *
1174 * Returns:
1175 * qla2x00 local function return status code.
1176 *
1177 * Context:
1178 * Kernel context.
1179 */
1180int
7b867cf7 1181qla2x00_mbx_reg_test(scsi_qla_host_t *vha)
1da177e4
LT		 1182{
1183 int rval;
1184 mbx_cmd_t mc;
1185 mbx_cmd_t *mcp = &mc;
1186
5f28d2d7
SK		 1187 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1032,
1188 "Entered %s.\n", __func__);
1da177e4
LT		 1189
1190 mcp->mb[0] = MBC_MAILBOX_REGISTER_TEST;
1191 mcp->mb[1] = 0xAAAA;
1192 mcp->mb[2] = 0x5555;
1193 mcp->mb[3] = 0xAA55;
1194 mcp->mb[4] = 0x55AA;
1195 mcp->mb[5] = 0xA5A5;
1196 mcp->mb[6] = 0x5A5A;
1197 mcp->mb[7] = 0x2525;
1198 mcp->out_mb = MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
1199 mcp->in_mb = MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
b93480e3 1200 mcp->tov = MBX_TOV_SECONDS;
1da177e4 1201 mcp->flags = 0;
7b867cf7 1202 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 1203
1204 if (rval == QLA_SUCCESS) {
1205 if (mcp->mb[1] != 0xAAAA || mcp->mb[2] != 0x5555 ||
1206 mcp->mb[3] != 0xAA55 || mcp->mb[4] != 0x55AA)
1207 rval = QLA_FUNCTION_FAILED;
1208 if (mcp->mb[5] != 0xA5A5 || mcp->mb[6] != 0x5A5A ||
1209 mcp->mb[7] != 0x2525)
1210 rval = QLA_FUNCTION_FAILED;
1211 }
1212
1213 if (rval != QLA_SUCCESS) {
1214 /*EMPTY*/
7c3df132 1215 ql_dbg(ql_dbg_mbx, vha, 0x1033, "Failed=%x.\n", rval);
1da177e4
LT		 1216 } else {
1217 /*EMPTY*/
5f28d2d7
SK		 1218 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1034,
1219 "Done %s.\n", __func__);
1da177e4
LT		 1220 }
1221
1222 return rval;
1223}
1224
1225/*
1226 * qla2x00_verify_checksum
1227 * Verify firmware checksum.
1228 *
1229 * Input:
1230 * ha = adapter block pointer.
1231 * TARGET_QUEUE_LOCK must be released.
1232 * ADAPTER_STATE_LOCK must be released.
1233 *
1234 * Returns:
1235 * qla2x00 local function return status code.
1236 *
1237 * Context:
1238 * Kernel context.
1239 */
1240int
7b867cf7 1241qla2x00_verify_checksum(scsi_qla_host_t *vha, uint32_t risc_addr)
1da177e4
LT		 1242{
1243 int rval;
1244 mbx_cmd_t mc;
1245 mbx_cmd_t *mcp = &mc;
1246
5f28d2d7
SK		 1247 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1035,
1248 "Entered %s.\n", __func__);
1da177e4
LT		 1249
1250 mcp->mb[0] = MBC_VERIFY_CHECKSUM;
1c7c6357
AV		 1251 mcp->out_mb = MBX_0;
1252 mcp->in_mb = MBX_0;
7b867cf7 1253 if (IS_FWI2_CAPABLE(vha->hw)) {
1c7c6357
AV		 1254 mcp->mb[1] = MSW(risc_addr);
1255 mcp->mb[2] = LSW(risc_addr);
1256 mcp->out_mb |= MBX_2|MBX_1;
1257 mcp->in_mb |= MBX_2|MBX_1;
1258 } else {
1259 mcp->mb[1] = LSW(risc_addr);
1260 mcp->out_mb |= MBX_1;
1261 mcp->in_mb |= MBX_1;
1262 }
1263
b93480e3 1264 mcp->tov = MBX_TOV_SECONDS;
1da177e4 1265 mcp->flags = 0;
7b867cf7 1266 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 1267
1268 if (rval != QLA_SUCCESS) {
7c3df132
SK		 1269 ql_dbg(ql_dbg_mbx, vha, 0x1036,
1270 "Failed=%x chm sum=%x.\n", rval, IS_FWI2_CAPABLE(vha->hw) ?
1271 (mcp->mb[2] << 16) | mcp->mb[1] : mcp->mb[1]);
1da177e4 1272 } else {
5f28d2d7
SK		 1273 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1037,
1274 "Done %s.\n", __func__);
1da177e4
LT		 1275 }
1276
1277 return rval;
1278}
1279
1280/*
1281 * qla2x00_issue_iocb
1282 * Issue IOCB using mailbox command
1283 *
1284 * Input:
1285 * ha = adapter state pointer.
1286 * buffer = buffer pointer.
1287 * phys_addr = physical address of buffer.
1288 * size = size of buffer.
1289 * TARGET_QUEUE_LOCK must be released.
1290 * ADAPTER_STATE_LOCK must be released.
1291 *
1292 * Returns:
1293 * qla2x00 local function return status code.
1294 *
1295 * Context:
1296 * Kernel context.
1297 */
6e98016c 1298int
7b867cf7 1299qla2x00_issue_iocb_timeout(scsi_qla_host_t *vha, void *buffer,
4d4df193 1300 dma_addr_t phys_addr, size_t size, uint32_t tov)
1da177e4
LT		 1301{
1302 int rval;
1303 mbx_cmd_t mc;
1304 mbx_cmd_t *mcp = &mc;
1305
5f28d2d7
SK		 1306 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1038,
1307 "Entered %s.\n", __func__);
7c3df132 1308
1da177e4
LT		 1309 mcp->mb[0] = MBC_IOCB_COMMAND_A64;
1310 mcp->mb[1] = 0;
1311 mcp->mb[2] = MSW(phys_addr);
1312 mcp->mb[3] = LSW(phys_addr);
1313 mcp->mb[6] = MSW(MSD(phys_addr));
1314 mcp->mb[7] = LSW(MSD(phys_addr));
1315 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
1316 mcp->in_mb = MBX_2|MBX_0;
4d4df193 1317 mcp->tov = tov;
1da177e4 1318 mcp->flags = 0;
7b867cf7 1319 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 1320
1321 if (rval != QLA_SUCCESS) {
1322 /*EMPTY*/
7c3df132 1323 ql_dbg(ql_dbg_mbx, vha, 0x1039, "Failed=%x.\n", rval);
1da177e4 1324 } else {
8c958a99
AV		 1325 sts_entry_t *sts_entry = (sts_entry_t *) buffer;
1326
1327 /* Mask reserved bits. */
1328 sts_entry->entry_status &=
7b867cf7 1329 IS_FWI2_CAPABLE(vha->hw) ? RF_MASK_24XX : RF_MASK;
5f28d2d7
SK		 1330 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103a,
1331 "Done %s.\n", __func__);
1da177e4
LT		 1332 }
1333
1334 return rval;
1335}
1336
4d4df193 1337int
7b867cf7 1338qla2x00_issue_iocb(scsi_qla_host_t *vha, void *buffer, dma_addr_t phys_addr,
4d4df193
HK		 1339 size_t size)
1340{
7b867cf7 1341 return qla2x00_issue_iocb_timeout(vha, buffer, phys_addr, size,
4d4df193
HK		 1342 MBX_TOV_SECONDS);
1343}
1344
1da177e4
LT		 1345/*
1346 * qla2x00_abort_command
1347 * Abort command aborts a specified IOCB.
1348 *
1349 * Input:
1350 * ha = adapter block pointer.
1351 * sp = SB structure pointer.
1352 *
1353 * Returns:
1354 * qla2x00 local function return status code.
1355 *
1356 * Context:
1357 * Kernel context.
1358 */
1359int
2afa19a9 1360qla2x00_abort_command(srb_t *sp)
1da177e4
LT		 1361{
1362 unsigned long flags = 0;
1da177e4 1363 int rval;
73208dfd 1364 uint32_t handle = 0;
1da177e4
LT		 1365 mbx_cmd_t mc;
1366 mbx_cmd_t *mcp = &mc;
2afa19a9
AC		 1367 fc_port_t *fcport = sp->fcport;
1368 scsi_qla_host_t *vha = fcport->vha;
7b867cf7 1369 struct qla_hw_data *ha = vha->hw;
d7459527 1370 struct req_que *req;
9ba56b95 1371 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
1da177e4 1372
5f28d2d7
SK		 1373 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103b,
1374 "Entered %s.\n", __func__);
1da177e4 1375
d7459527
MH		 1376 if (vha->flags.qpairs_available && sp->qpair)
1377 req = sp->qpair->req;
1378 else
1379 req = vha->req;
1380
c9c5ced9 1381 spin_lock_irqsave(&ha->hardware_lock, flags);
8d93f550 1382 for (handle = 1; handle < req->num_outstanding_cmds; handle++) {
7b867cf7 1383 if (req->outstanding_cmds[handle] == sp)
1da177e4
LT		 1384 break;
1385 }
c9c5ced9 1386 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1da177e4 1387
8d93f550 1388 if (handle == req->num_outstanding_cmds) {
1da177e4
LT		 1389 /* command not found */
1390 return QLA_FUNCTION_FAILED;
1391 }
1392
1393 mcp->mb[0] = MBC_ABORT_COMMAND;
1394 if (HAS_EXTENDED_IDS(ha))
1395 mcp->mb[1] = fcport->loop_id;
1396 else
1397 mcp->mb[1] = fcport->loop_id << 8;
1398 mcp->mb[2] = (uint16_t)handle;
1399 mcp->mb[3] = (uint16_t)(handle >> 16);
9ba56b95 1400 mcp->mb[6] = (uint16_t)cmd->device->lun;
1da177e4
LT		 1401 mcp->out_mb = MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
1402 mcp->in_mb = MBX_0;
b93480e3 1403 mcp->tov = MBX_TOV_SECONDS;
1da177e4 1404 mcp->flags = 0;
7b867cf7 1405 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 1406
1407 if (rval != QLA_SUCCESS) {
7c3df132 1408 ql_dbg(ql_dbg_mbx, vha, 0x103c, "Failed=%x.\n", rval);
1da177e4 1409 } else {
5f28d2d7
SK		 1410 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103d,
1411 "Done %s.\n", __func__);
1da177e4
LT		 1412 }
1413
1414 return rval;
1415}
1416
1da177e4 1417int
9cb78c16 1418qla2x00_abort_target(struct fc_port *fcport, uint64_t l, int tag)
1da177e4 1419{
523ec773 1420 int rval, rval2;
1da177e4
LT		 1421 mbx_cmd_t mc;
1422 mbx_cmd_t *mcp = &mc;
7b867cf7 1423 scsi_qla_host_t *vha;
73208dfd
AC		 1424 struct req_que *req;
1425 struct rsp_que *rsp;
1da177e4 1426
523ec773 1427 l = l;
7b867cf7 1428 vha = fcport->vha;
7c3df132 1429
5f28d2d7
SK		 1430 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103e,
1431 "Entered %s.\n", __func__);
7c3df132 1432
7e2b895b
GM		 1433 req = vha->hw->req_q_map[0];
1434 rsp = req->rsp;
1da177e4 1435 mcp->mb[0] = MBC_ABORT_TARGET;
523ec773 1436 mcp->out_mb = MBX_9|MBX_2|MBX_1|MBX_0;
7b867cf7 1437 if (HAS_EXTENDED_IDS(vha->hw)) {
1da177e4
LT		 1438 mcp->mb[1] = fcport->loop_id;
1439 mcp->mb[10] = 0;
1440 mcp->out_mb |= MBX_10;
1441 } else {
1442 mcp->mb[1] = fcport->loop_id << 8;
1443 }
7b867cf7
AC		 1444 mcp->mb[2] = vha->hw->loop_reset_delay;
1445 mcp->mb[9] = vha->vp_idx;
1da177e4
LT		 1446
1447 mcp->in_mb = MBX_0;
b93480e3 1448 mcp->tov = MBX_TOV_SECONDS;
1da177e4 1449 mcp->flags = 0;
7b867cf7 1450 rval = qla2x00_mailbox_command(vha, mcp);
523ec773 1451 if (rval != QLA_SUCCESS) {
5f28d2d7
SK		 1452 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103f,
1453 "Failed=%x.\n", rval);
523ec773
AV		 1454 }
1455
1456 /* Issue marker IOCB. */
73208dfd
AC		 1457 rval2 = qla2x00_marker(vha, req, rsp, fcport->loop_id, 0,
1458 MK_SYNC_ID);
523ec773 1459 if (rval2 != QLA_SUCCESS) {
7c3df132
SK		 1460 ql_dbg(ql_dbg_mbx, vha, 0x1040,
1461 "Failed to issue marker IOCB (%x).\n", rval2);
523ec773 1462 } else {
5f28d2d7
SK		 1463 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1041,
1464 "Done %s.\n", __func__);
523ec773
AV		 1465 }
1466
1467 return rval;
1468}
1469
1470int
9cb78c16 1471qla2x00_lun_reset(struct fc_port *fcport, uint64_t l, int tag)
523ec773
AV		 1472{
1473 int rval, rval2;
1474 mbx_cmd_t mc;
1475 mbx_cmd_t *mcp = &mc;
7b867cf7 1476 scsi_qla_host_t *vha;
73208dfd
AC		 1477 struct req_que *req;
1478 struct rsp_que *rsp;
523ec773 1479
7b867cf7 1480 vha = fcport->vha;
7c3df132 1481
5f28d2d7
SK		 1482 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1042,
1483 "Entered %s.\n", __func__);
7c3df132 1484
7e2b895b
GM		 1485 req = vha->hw->req_q_map[0];
1486 rsp = req->rsp;
523ec773
AV		 1487 mcp->mb[0] = MBC_LUN_RESET;
1488 mcp->out_mb = MBX_9|MBX_3|MBX_2|MBX_1|MBX_0;
7b867cf7 1489 if (HAS_EXTENDED_IDS(vha->hw))
523ec773
AV		 1490 mcp->mb[1] = fcport->loop_id;
1491 else
1492 mcp->mb[1] = fcport->loop_id << 8;
9cb78c16 1493 mcp->mb[2] = (u32)l;
523ec773 1494 mcp->mb[3] = 0;
7b867cf7 1495 mcp->mb[9] = vha->vp_idx;
1da177e4 1496
523ec773 1497 mcp->in_mb = MBX_0;
b93480e3 1498 mcp->tov = MBX_TOV_SECONDS;
523ec773 1499 mcp->flags = 0;
7b867cf7 1500 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4 1501 if (rval != QLA_SUCCESS) {
7c3df132 1502 ql_dbg(ql_dbg_mbx, vha, 0x1043, "Failed=%x.\n", rval);
523ec773
AV		 1503 }
1504
1505 /* Issue marker IOCB. */
73208dfd
AC		 1506 rval2 = qla2x00_marker(vha, req, rsp, fcport->loop_id, l,
1507 MK_SYNC_ID_LUN);
523ec773 1508 if (rval2 != QLA_SUCCESS) {
7c3df132
SK		 1509 ql_dbg(ql_dbg_mbx, vha, 0x1044,
1510 "Failed to issue marker IOCB (%x).\n", rval2);
1da177e4 1511 } else {
5f28d2d7
SK		 1512 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1045,
1513 "Done %s.\n", __func__);
1da177e4
LT		 1514 }
1515
1516 return rval;
1517}
1da177e4 1518
1da177e4
LT		 1519/*
1520 * qla2x00_get_adapter_id
1521 * Get adapter ID and topology.
1522 *
1523 * Input:
1524 * ha = adapter block pointer.
1525 * id = pointer for loop ID.
1526 * al_pa = pointer for AL_PA.
1527 * area = pointer for area.
1528 * domain = pointer for domain.
1529 * top = pointer for topology.
1530 * TARGET_QUEUE_LOCK must be released.
1531 * ADAPTER_STATE_LOCK must be released.
1532 *
1533 * Returns:
1534 * qla2x00 local function return status code.
1535 *
1536 * Context:
1537 * Kernel context.
1538 */
1539int
7b867cf7 1540qla2x00_get_adapter_id(scsi_qla_host_t *vha, uint16_t *id, uint8_t *al_pa,
2c3dfe3f 1541 uint8_t *area, uint8_t *domain, uint16_t *top, uint16_t *sw_cap)
1da177e4
LT		 1542{
1543 int rval;
1544 mbx_cmd_t mc;
1545 mbx_cmd_t *mcp = &mc;
1546
5f28d2d7
SK		 1547 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1046,
1548 "Entered %s.\n", __func__);
1da177e4
LT		 1549
1550 mcp->mb[0] = MBC_GET_ADAPTER_LOOP_ID;
7b867cf7 1551 mcp->mb[9] = vha->vp_idx;
eb66dc60 1552 mcp->out_mb = MBX_9|MBX_0;
2c3dfe3f 1553 mcp->in_mb = MBX_9|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
6246b8a1 1554 if (IS_CNA_CAPABLE(vha->hw))
bad7001c 1555 mcp->in_mb |= MBX_13|MBX_12|MBX_11|MBX_10;
7c9c4766
JC		 1556 if (IS_FWI2_CAPABLE(vha->hw))
1557 mcp->in_mb |= MBX_19|MBX_18|MBX_17|MBX_16;
969a6199
SC		 1558 if (IS_QLA27XX(vha->hw))
1559 mcp->in_mb |= MBX_15;
b93480e3 1560 mcp->tov = MBX_TOV_SECONDS;
1da177e4 1561 mcp->flags = 0;
7b867cf7 1562 rval = qla2x00_mailbox_command(vha, mcp);
33135aa2
RA		 1563 if (mcp->mb[0] == MBS_COMMAND_ERROR)
1564 rval = QLA_COMMAND_ERROR;
42e421b1
AV		 1565 else if (mcp->mb[0] == MBS_INVALID_COMMAND)
1566 rval = QLA_INVALID_COMMAND;
1da177e4
LT		 1567
1568 /* Return data. */
1569 *id = mcp->mb[1];
1570 *al_pa = LSB(mcp->mb[2]);
1571 *area = MSB(mcp->mb[2]);
1572 *domain = LSB(mcp->mb[3]);
1573 *top = mcp->mb[6];
2c3dfe3f 1574 *sw_cap = mcp->mb[7];
1da177e4
LT		 1575
1576 if (rval != QLA_SUCCESS) {
1577 /*EMPTY*/
7c3df132 1578 ql_dbg(ql_dbg_mbx, vha, 0x1047, "Failed=%x.\n", rval);
1da177e4 1579 } else {
5f28d2d7
SK		 1580 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1048,
1581 "Done %s.\n", __func__);
bad7001c 1582
6246b8a1 1583 if (IS_CNA_CAPABLE(vha->hw)) {
bad7001c
AV		 1584 vha->fcoe_vlan_id = mcp->mb[9] & 0xfff;
1585 vha->fcoe_fcf_idx = mcp->mb[10];
1586 vha->fcoe_vn_port_mac[5] = mcp->mb[11] >> 8;
1587 vha->fcoe_vn_port_mac[4] = mcp->mb[11] & 0xff;
1588 vha->fcoe_vn_port_mac[3] = mcp->mb[12] >> 8;
1589 vha->fcoe_vn_port_mac[2] = mcp->mb[12] & 0xff;
1590 vha->fcoe_vn_port_mac[1] = mcp->mb[13] >> 8;
1591 vha->fcoe_vn_port_mac[0] = mcp->mb[13] & 0xff;
1592 }
7c9c4766 1593 /* If FA-WWN supported */
d6b9b42b
SK		 1594 if (IS_FAWWN_CAPABLE(vha->hw)) {
1595 if (mcp->mb[7] & BIT_14) {
1596 vha->port_name[0] = MSB(mcp->mb[16]);
1597 vha->port_name[1] = LSB(mcp->mb[16]);
1598 vha->port_name[2] = MSB(mcp->mb[17]);
1599 vha->port_name[3] = LSB(mcp->mb[17]);
1600 vha->port_name[4] = MSB(mcp->mb[18]);
1601 vha->port_name[5] = LSB(mcp->mb[18]);
1602 vha->port_name[6] = MSB(mcp->mb[19]);
1603 vha->port_name[7] = LSB(mcp->mb[19]);
1604 fc_host_port_name(vha->host) =
1605 wwn_to_u64(vha->port_name);
1606 ql_dbg(ql_dbg_mbx, vha, 0x10ca,
1607 "FA-WWN acquired %016llx\n",
1608 wwn_to_u64(vha->port_name));
1609 }
7c9c4766 1610 }
969a6199
SC		 1611
1612 if (IS_QLA27XX(vha->hw))
1613 vha->bbcr = mcp->mb[15];
1da177e4
LT		 1614 }
1615
1616 return rval;
1617}
1618
1619/*
1620 * qla2x00_get_retry_cnt
1621 * Get current firmware login retry count and delay.
1622 *
1623 * Input:
1624 * ha = adapter block pointer.
1625 * retry_cnt = pointer to login retry count.
1626 * tov = pointer to login timeout value.
1627 *
1628 * Returns:
1629 * qla2x00 local function return status code.
1630 *
1631 * Context:
1632 * Kernel context.
1633 */
1634int
7b867cf7 1635qla2x00_get_retry_cnt(scsi_qla_host_t *vha, uint8_t *retry_cnt, uint8_t *tov,
1da177e4
LT		 1636 uint16_t *r_a_tov)
1637{
1638 int rval;
1639 uint16_t ratov;
1640 mbx_cmd_t mc;
1641 mbx_cmd_t *mcp = &mc;
1642
5f28d2d7
SK		 1643 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1049,
1644 "Entered %s.\n", __func__);
1da177e4
LT		 1645
1646 mcp->mb[0] = MBC_GET_RETRY_COUNT;
1647 mcp->out_mb = MBX_0;
1648 mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0;
b93480e3 1649 mcp->tov = MBX_TOV_SECONDS;
1da177e4 1650 mcp->flags = 0;
7b867cf7 1651 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 1652
1653 if (rval != QLA_SUCCESS) {
1654 /*EMPTY*/
7c3df132
SK		 1655 ql_dbg(ql_dbg_mbx, vha, 0x104a,
1656 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
1da177e4
LT		 1657 } else {
1658 /* Convert returned data and check our values. */
1659 *r_a_tov = mcp->mb[3] / 2;
1660 ratov = (mcp->mb[3]/2) / 10; /* mb[3] value is in 100ms */
1661 if (mcp->mb[1] * ratov > (*retry_cnt) * (*tov)) {
1662 /* Update to the larger values */
1663 *retry_cnt = (uint8_t)mcp->mb[1];
1664 *tov = ratov;
1665 }
1666
5f28d2d7 1667 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x104b,
7c3df132 1668 "Done %s mb3=%d ratov=%d.\n", __func__, mcp->mb[3], ratov);
1da177e4
LT		 1669 }
1670
1671 return rval;
1672}
1673
1674/*
1675 * qla2x00_init_firmware
1676 * Initialize adapter firmware.
1677 *
1678 * Input:
1679 * ha = adapter block pointer.
1680 * dptr = Initialization control block pointer.
1681 * size = size of initialization control block.
1682 * TARGET_QUEUE_LOCK must be released.
1683 * ADAPTER_STATE_LOCK must be released.
1684 *
1685 * Returns:
1686 * qla2x00 local function return status code.
1687 *
1688 * Context:
1689 * Kernel context.
1690 */
1691int
7b867cf7 1692qla2x00_init_firmware(scsi_qla_host_t *vha, uint16_t size)
1da177e4
LT		 1693{
1694 int rval;
1695 mbx_cmd_t mc;
1696 mbx_cmd_t *mcp = &mc;
7b867cf7 1697 struct qla_hw_data *ha = vha->hw;
1da177e4 1698
5f28d2d7
SK		 1699 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x104c,
1700 "Entered %s.\n", __func__);
1da177e4 1701
7ec0effd 1702 if (IS_P3P_TYPE(ha) && ql2xdbwr)
8dfa4b5a 1703 qla82xx_wr_32(ha, (uintptr_t __force)ha->nxdb_wr_ptr,
a9083016
GM		 1704 (0x04 | (ha->portnum << 5) | (0 << 8) | (0 << 16)));
1705
e6e074f1 1706 if (ha->flags.npiv_supported)
2c3dfe3f
SJ		 1707 mcp->mb[0] = MBC_MID_INITIALIZE_FIRMWARE;
1708 else
1709 mcp->mb[0] = MBC_INITIALIZE_FIRMWARE;
1710
b64b0e8f 1711 mcp->mb[1] = 0;
1da177e4
LT		 1712 mcp->mb[2] = MSW(ha->init_cb_dma);
1713 mcp->mb[3] = LSW(ha->init_cb_dma);
1da177e4
LT		 1714 mcp->mb[6] = MSW(MSD(ha->init_cb_dma));
1715 mcp->mb[7] = LSW(MSD(ha->init_cb_dma));
b64b0e8f 1716 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
4ef21bd4 1717 if (ha->ex_init_cb && ha->ex_init_cb->ex_version) {
b64b0e8f
AV		 1718 mcp->mb[1] = BIT_0;
1719 mcp->mb[10] = MSW(ha->ex_init_cb_dma);
1720 mcp->mb[11] = LSW(ha->ex_init_cb_dma);
1721 mcp->mb[12] = MSW(MSD(ha->ex_init_cb_dma));
1722 mcp->mb[13] = LSW(MSD(ha->ex_init_cb_dma));
1723 mcp->mb[14] = sizeof(*ha->ex_init_cb);
1724 mcp->out_mb |= MBX_14|MBX_13|MBX_12|MBX_11|MBX_10;
1725 }
6246b8a1
GM		 1726 /* 1 and 2 should normally be captured. */
1727 mcp->in_mb = MBX_2|MBX_1|MBX_0;
f73cb695 1728 if (IS_QLA83XX(ha) || IS_QLA27XX(ha))
6246b8a1
GM		 1729 /* mb3 is additional info about the installed SFP. */
1730 mcp->in_mb |= MBX_3;
1da177e4
LT		 1731 mcp->buf_size = size;
1732 mcp->flags = MBX_DMA_OUT;
b93480e3 1733 mcp->tov = MBX_TOV_SECONDS;
7b867cf7 1734 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 1735
1736 if (rval != QLA_SUCCESS) {
1737 /*EMPTY*/
7c3df132 1738 ql_dbg(ql_dbg_mbx, vha, 0x104d,
6246b8a1
GM		 1739 "Failed=%x mb[0]=%x, mb[1]=%x, mb[2]=%x, mb[3]=%x,.\n",
1740 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2], mcp->mb[3]);
1da177e4 1741 } else {
92d4408e
SC		 1742 if (IS_QLA27XX(ha)) {
1743 if (mcp->mb[2] == 6 || mcp->mb[3] == 2)
1744 ql_dbg(ql_dbg_mbx, vha, 0x119d,
1745 "Invalid SFP/Validation Failed\n");
1746 }
5f28d2d7
SK		 1747 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x104e,
1748 "Done %s.\n", __func__);
1da177e4
LT		 1749 }
1750
1751 return rval;
1752}
1753
2d70c103 1754
1da177e4
LT		 1755/*
1756 * qla2x00_get_port_database
1757 * Issue normal/enhanced get port database mailbox command
1758 * and copy device name as necessary.
1759 *
1760 * Input:
1761 * ha = adapter state pointer.
1762 * dev = structure pointer.
1763 * opt = enhanced cmd option byte.
1764 *
1765 * Returns:
1766 * qla2x00 local function return status code.
1767 *
1768 * Context:
1769 * Kernel context.
1770 */
1771int
7b867cf7 1772qla2x00_get_port_database(scsi_qla_host_t *vha, fc_port_t *fcport, uint8_t opt)
1da177e4
LT		 1773{
1774 int rval;
1775 mbx_cmd_t mc;
1776 mbx_cmd_t *mcp = &mc;
1777 port_database_t *pd;
1c7c6357 1778 struct port_database_24xx *pd24;
1da177e4 1779 dma_addr_t pd_dma;
7b867cf7 1780 struct qla_hw_data *ha = vha->hw;
1da177e4 1781
5f28d2d7
SK		 1782 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x104f,
1783 "Entered %s.\n", __func__);
1da177e4 1784
1c7c6357 1785 pd24 = NULL;
08eb7f45 1786 pd = dma_pool_zalloc(ha->s_dma_pool, GFP_KERNEL, &pd_dma);
1da177e4 1787 if (pd == NULL) {
7c3df132
SK		 1788 ql_log(ql_log_warn, vha, 0x1050,
1789 "Failed to allocate port database structure.\n");
edd05de1 1790 fcport->query = 0;
1da177e4
LT		 1791 return QLA_MEMORY_ALLOC_FAILED;
1792 }
1da177e4 1793
1c7c6357 1794 mcp->mb[0] = MBC_GET_PORT_DATABASE;
e428924c 1795 if (opt != 0 && !IS_FWI2_CAPABLE(ha))
1da177e4 1796 mcp->mb[0] = MBC_ENHANCED_GET_PORT_DATABASE;
1da177e4
LT		 1797 mcp->mb[2] = MSW(pd_dma);
1798 mcp->mb[3] = LSW(pd_dma);
1799 mcp->mb[6] = MSW(MSD(pd_dma));
1800 mcp->mb[7] = LSW(MSD(pd_dma));
7b867cf7 1801 mcp->mb[9] = vha->vp_idx;
2c3dfe3f 1802 mcp->out_mb = MBX_9|MBX_7|MBX_6|MBX_3|MBX_2|MBX_0;
1da177e4 1803 mcp->in_mb = MBX_0;
e428924c 1804 if (IS_FWI2_CAPABLE(ha)) {
1c7c6357
AV		 1805 mcp->mb[1] = fcport->loop_id;
1806 mcp->mb[10] = opt;
1807 mcp->out_mb |= MBX_10|MBX_1;
1808 mcp->in_mb |= MBX_1;
1809 } else if (HAS_EXTENDED_IDS(ha)) {
1810 mcp->mb[1] = fcport->loop_id;
1811 mcp->mb[10] = opt;
1812 mcp->out_mb |= MBX_10|MBX_1;
1813 } else {
1814 mcp->mb[1] = fcport->loop_id << 8 | opt;
1815 mcp->out_mb |= MBX_1;
1816 }
e428924c
AV		 1817 mcp->buf_size = IS_FWI2_CAPABLE(ha) ?
1818 PORT_DATABASE_24XX_SIZE : PORT_DATABASE_SIZE;
1da177e4
LT		 1819 mcp->flags = MBX_DMA_IN;
1820 mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2);
7b867cf7 1821 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 1822 if (rval != QLA_SUCCESS)
1823 goto gpd_error_out;
1824
e428924c 1825 if (IS_FWI2_CAPABLE(ha)) {
0eba25df 1826 uint64_t zero = 0;
c0c462c8
DG		 1827 u8 current_login_state, last_login_state;
1828
1c7c6357
AV		 1829 pd24 = (struct port_database_24xx *) pd;
1830
1831 /* Check for logged in state. */
c0c462c8
DG		 1832 if (fcport->fc4f_nvme) {
1833 current_login_state = pd24->current_login_state >> 4;
1834 last_login_state = pd24->last_login_state >> 4;
1835 } else {
1836 current_login_state = pd24->current_login_state & 0xf;
1837 last_login_state = pd24->last_login_state & 0xf;
1838 }
1839 fcport->current_login_state = pd24->current_login_state;
1840 fcport->last_login_state = pd24->last_login_state;
1841
1842 /* Check for logged in state. */
1843 if (current_login_state != PDS_PRLI_COMPLETE &&
1844 last_login_state != PDS_PRLI_COMPLETE) {
1845 ql_dbg(ql_dbg_mbx, vha, 0x119a,
1846 "Unable to verify login-state (%x/%x) for loop_id %x.\n",
1847 current_login_state, last_login_state,
1848 fcport->loop_id);
1c7c6357 1849 rval = QLA_FUNCTION_FAILED;
c0c462c8
DG		 1850
1851 if (!fcport->query)
1852 goto gpd_error_out;
1c7c6357 1853 }
1da177e4 1854
0eba25df
AE		 1855 if (fcport->loop_id == FC_NO_LOOP_ID ||
1856 (memcmp(fcport->port_name, (uint8_t *)&zero, 8) &&
1857 memcmp(fcport->port_name, pd24->port_name, 8))) {
1858 /* We lost the device mid way. */
1859 rval = QLA_NOT_LOGGED_IN;
1860 goto gpd_error_out;
1861 }
1862
1c7c6357
AV		 1863 /* Names are little-endian. */
1864 memcpy(fcport->node_name, pd24->node_name, WWN_SIZE);
1865 memcpy(fcport->port_name, pd24->port_name, WWN_SIZE);
1866
1867 /* Get port_id of device. */
1868 fcport->d_id.b.domain = pd24->port_id[0];
1869 fcport->d_id.b.area = pd24->port_id[1];
1870 fcport->d_id.b.al_pa = pd24->port_id[2];
1871 fcport->d_id.b.rsvd_1 = 0;
1872
1873 /* If not target must be initiator or unknown type. */
1874 if ((pd24->prli_svc_param_word_3[0] & BIT_4) == 0)
1875 fcport->port_type = FCT_INITIATOR;
1876 else
1877 fcport->port_type = FCT_TARGET;
2d70c103
NB		 1878
1879 /* Passback COS information. */
1880 fcport->supported_classes = (pd24->flags & PDF_CLASS_2) ?
1881 FC_COS_CLASS2 : FC_COS_CLASS3;
1882
1883 if (pd24->prli_svc_param_word_3[0] & BIT_7)
1884 fcport->flags |= FCF_CONF_COMP_SUPPORTED;
1c7c6357 1885 } else {
0eba25df
AE		 1886 uint64_t zero = 0;
1887
1c7c6357
AV		 1888 /* Check for logged in state. */
1889 if (pd->master_state != PD_STATE_PORT_LOGGED_IN &&
1890 pd->slave_state != PD_STATE_PORT_LOGGED_IN) {
7c3df132
SK		 1891 ql_dbg(ql_dbg_mbx, vha, 0x100a,
1892 "Unable to verify login-state (%x/%x) - "
1893 "portid=%02x%02x%02x.\n", pd->master_state,
1894 pd->slave_state, fcport->d_id.b.domain,
1895 fcport->d_id.b.area, fcport->d_id.b.al_pa);
1c7c6357
AV		 1896 rval = QLA_FUNCTION_FAILED;
1897 goto gpd_error_out;
1898 }
1da177e4 1899
0eba25df
AE		 1900 if (fcport->loop_id == FC_NO_LOOP_ID ||
1901 (memcmp(fcport->port_name, (uint8_t *)&zero, 8) &&
1902 memcmp(fcport->port_name, pd->port_name, 8))) {
1903 /* We lost the device mid way. */
1904 rval = QLA_NOT_LOGGED_IN;
1905 goto gpd_error_out;
1906 }
1907
1c7c6357
AV		 1908 /* Names are little-endian. */
1909 memcpy(fcport->node_name, pd->node_name, WWN_SIZE);
1910 memcpy(fcport->port_name, pd->port_name, WWN_SIZE);
1911
1912 /* Get port_id of device. */
1913 fcport->d_id.b.domain = pd->port_id[0];
1914 fcport->d_id.b.area = pd->port_id[3];
1915 fcport->d_id.b.al_pa = pd->port_id[2];
1916 fcport->d_id.b.rsvd_1 = 0;
1917
1c7c6357
AV		 1918 /* If not target must be initiator or unknown type. */
1919 if ((pd->prli_svc_param_word_3[0] & BIT_4) == 0)
1920 fcport->port_type = FCT_INITIATOR;
1921 else
1922 fcport->port_type = FCT_TARGET;
ad3e0eda
AV		 1923
1924 /* Passback COS information. */
1925 fcport->supported_classes = (pd->options & BIT_4) ?
1926 FC_COS_CLASS2: FC_COS_CLASS3;
1c7c6357 1927 }
1da177e4
LT		 1928
1929gpd_error_out:
1930 dma_pool_free(ha->s_dma_pool, pd, pd_dma);
edd05de1 1931 fcport->query = 0;
1da177e4
LT		 1932
1933 if (rval != QLA_SUCCESS) {
7c3df132
SK		 1934 ql_dbg(ql_dbg_mbx, vha, 0x1052,
1935 "Failed=%x mb[0]=%x mb[1]=%x.\n", rval,
1936 mcp->mb[0], mcp->mb[1]);
1da177e4 1937 } else {
5f28d2d7
SK		 1938 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1053,
1939 "Done %s.\n", __func__);
1da177e4
LT		 1940 }
1941
1942 return rval;
1943}
1944
1945/*
1946 * qla2x00_get_firmware_state
1947 * Get adapter firmware state.
1948 *
1949 * Input:
1950 * ha = adapter block pointer.
1951 * dptr = pointer for firmware state.
1952 * TARGET_QUEUE_LOCK must be released.
1953 * ADAPTER_STATE_LOCK must be released.
1954 *
1955 * Returns:
1956 * qla2x00 local function return status code.
1957 *
1958 * Context:
1959 * Kernel context.
1960 */
1961int
7b867cf7 1962qla2x00_get_firmware_state(scsi_qla_host_t *vha, uint16_t *states)
1da177e4
LT		 1963{
1964 int rval;
1965 mbx_cmd_t mc;
1966 mbx_cmd_t *mcp = &mc;
92d4408e 1967 struct qla_hw_data *ha = vha->hw;
1da177e4 1968
5f28d2d7
SK		 1969 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1054,
1970 "Entered %s.\n", __func__);
1da177e4
LT		 1971
1972 mcp->mb[0] = MBC_GET_FIRMWARE_STATE;
1973 mcp->out_mb = MBX_0;
9d2683c0 1974 if (IS_FWI2_CAPABLE(vha->hw))
b5a340dd 1975 mcp->in_mb = MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
9d2683c0
AV		 1976 else
1977 mcp->in_mb = MBX_1|MBX_0;
b93480e3 1978 mcp->tov = MBX_TOV_SECONDS;
1da177e4 1979 mcp->flags = 0;
7b867cf7 1980 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4 1981
4d4df193
HK		 1982 /* Return firmware states. */
1983 states[0] = mcp->mb[1];
9d2683c0
AV		 1984 if (IS_FWI2_CAPABLE(vha->hw)) {
1985 states[1] = mcp->mb[2];
ec891462 1986 states[2] = mcp->mb[3]; /* SFP info */
9d2683c0
AV		 1987 states[3] = mcp->mb[4];
1988 states[4] = mcp->mb[5];
b5a340dd 1989 states[5] = mcp->mb[6]; /* DPORT status */
9d2683c0 1990 }
1da177e4
LT		 1991
1992 if (rval != QLA_SUCCESS) {
1993 /*EMPTY*/
7c3df132 1994 ql_dbg(ql_dbg_mbx, vha, 0x1055, "Failed=%x.\n", rval);
1da177e4 1995 } else {
92d4408e
SC		 1996 if (IS_QLA27XX(ha)) {
1997 if (mcp->mb[2] == 6 || mcp->mb[3] == 2)
1998 ql_dbg(ql_dbg_mbx, vha, 0x119e,
1999 "Invalid SFP/Validation Failed\n");
2000 }
5f28d2d7
SK		 2001 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1056,
2002 "Done %s.\n", __func__);
1da177e4
LT		 2003 }
2004
2005 return rval;
2006}
2007
2008/*
2009 * qla2x00_get_port_name
2010 * Issue get port name mailbox command.
2011 * Returned name is in big endian format.
2012 *
2013 * Input:
2014 * ha = adapter block pointer.
2015 * loop_id = loop ID of device.
2016 * name = pointer for name.
2017 * TARGET_QUEUE_LOCK must be released.
2018 * ADAPTER_STATE_LOCK must be released.
2019 *
2020 * Returns:
2021 * qla2x00 local function return status code.
2022 *
2023 * Context:
2024 * Kernel context.
2025 */
2026int
7b867cf7 2027qla2x00_get_port_name(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t *name,
1da177e4
LT		 2028 uint8_t opt)
2029{
2030 int rval;
2031 mbx_cmd_t mc;
2032 mbx_cmd_t *mcp = &mc;
2033
5f28d2d7
SK		 2034 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1057,
2035 "Entered %s.\n", __func__);
1da177e4
LT		 2036
2037 mcp->mb[0] = MBC_GET_PORT_NAME;
7b867cf7 2038 mcp->mb[9] = vha->vp_idx;
2c3dfe3f 2039 mcp->out_mb = MBX_9|MBX_1|MBX_0;
7b867cf7 2040 if (HAS_EXTENDED_IDS(vha->hw)) {
1da177e4
LT		 2041 mcp->mb[1] = loop_id;
2042 mcp->mb[10] = opt;
2043 mcp->out_mb |= MBX_10;
2044 } else {
2045 mcp->mb[1] = loop_id << 8 | opt;
2046 }
2047
2048 mcp->in_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
b93480e3 2049 mcp->tov = MBX_TOV_SECONDS;
1da177e4 2050 mcp->flags = 0;
7b867cf7 2051 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 2052
2053 if (rval != QLA_SUCCESS) {
2054 /*EMPTY*/
7c3df132 2055 ql_dbg(ql_dbg_mbx, vha, 0x1058, "Failed=%x.\n", rval);
1da177e4
LT		 2056 } else {
2057 if (name != NULL) {
2058 /* This function returns name in big endian. */
1196ae02
RL		 2059 name[0] = MSB(mcp->mb[2]);
2060 name[1] = LSB(mcp->mb[2]);
2061 name[2] = MSB(mcp->mb[3]);
2062 name[3] = LSB(mcp->mb[3]);
2063 name[4] = MSB(mcp->mb[6]);
2064 name[5] = LSB(mcp->mb[6]);
2065 name[6] = MSB(mcp->mb[7]);
2066 name[7] = LSB(mcp->mb[7]);
1da177e4
LT		 2067 }
2068
5f28d2d7
SK		 2069 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1059,
2070 "Done %s.\n", __func__);
1da177e4
LT		 2071 }
2072
2073 return rval;
2074}
2075
61e1b269
JC		 2076/*
2077 * qla24xx_link_initialization
2078 * Issue link initialization mailbox command.
2079 *
2080 * Input:
2081 * ha = adapter block pointer.
2082 * TARGET_QUEUE_LOCK must be released.
2083 * ADAPTER_STATE_LOCK must be released.
2084 *
2085 * Returns:
2086 * qla2x00 local function return status code.
2087 *
2088 * Context:
2089 * Kernel context.
2090 */
2091int
2092qla24xx_link_initialize(scsi_qla_host_t *vha)
2093{
2094 int rval;
2095 mbx_cmd_t mc;
2096 mbx_cmd_t *mcp = &mc;
2097
2098 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1152,
2099 "Entered %s.\n", __func__);
2100
2101 if (!IS_FWI2_CAPABLE(vha->hw) || IS_CNA_CAPABLE(vha->hw))
2102 return QLA_FUNCTION_FAILED;
2103
2104 mcp->mb[0] = MBC_LINK_INITIALIZATION;
5a5c27b6
JC		 2105 mcp->mb[1] = BIT_4;
2106 if (vha->hw->operating_mode == LOOP)
2107 mcp->mb[1] |= BIT_6;
2108 else
2109 mcp->mb[1] |= BIT_5;
61e1b269
JC		 2110 mcp->mb[2] = 0;
2111 mcp->mb[3] = 0;
2112 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
2113 mcp->in_mb = MBX_0;
2114 mcp->tov = MBX_TOV_SECONDS;
2115 mcp->flags = 0;
2116 rval = qla2x00_mailbox_command(vha, mcp);
2117
2118 if (rval != QLA_SUCCESS) {
2119 ql_dbg(ql_dbg_mbx, vha, 0x1153, "Failed=%x.\n", rval);
2120 } else {
2121 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1154,
2122 "Done %s.\n", __func__);
2123 }
2124
2125 return rval;
2126}
2127
1da177e4
LT		 2128/*
2129 * qla2x00_lip_reset
2130 * Issue LIP reset mailbox command.
2131 *
2132 * Input:
2133 * ha = adapter block pointer.
2134 * TARGET_QUEUE_LOCK must be released.
2135 * ADAPTER_STATE_LOCK must be released.
2136 *
2137 * Returns:
2138 * qla2x00 local function return status code.
2139 *
2140 * Context:
2141 * Kernel context.
2142 */
2143int
7b867cf7 2144qla2x00_lip_reset(scsi_qla_host_t *vha)
1da177e4
LT		 2145{
2146 int rval;
2147 mbx_cmd_t mc;
2148 mbx_cmd_t *mcp = &mc;
2149
5f28d2d7
SK		 2150 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x105a,
2151 "Entered %s.\n", __func__);
1da177e4 2152
6246b8a1 2153 if (IS_CNA_CAPABLE(vha->hw)) {
3a03eb79
AV		 2154 /* Logout across all FCFs. */
2155 mcp->mb[0] = MBC_LIP_FULL_LOGIN;
2156 mcp->mb[1] = BIT_1;
2157 mcp->mb[2] = 0;
2158 mcp->out_mb = MBX_2|MBX_1|MBX_0;
2159 } else if (IS_FWI2_CAPABLE(vha->hw)) {
1c7c6357 2160 mcp->mb[0] = MBC_LIP_FULL_LOGIN;
0c8c39af
AV		 2161 mcp->mb[1] = BIT_6;
2162 mcp->mb[2] = 0;
7b867cf7 2163 mcp->mb[3] = vha->hw->loop_reset_delay;
1c7c6357 2164 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
1da177e4 2165 } else {
1c7c6357
AV		 2166 mcp->mb[0] = MBC_LIP_RESET;
2167 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
7b867cf7 2168 if (HAS_EXTENDED_IDS(vha->hw)) {
1c7c6357
AV		 2169 mcp->mb[1] = 0x00ff;
2170 mcp->mb[10] = 0;
2171 mcp->out_mb |= MBX_10;
2172 } else {
2173 mcp->mb[1] = 0xff00;
2174 }
7b867cf7 2175 mcp->mb[2] = vha->hw->loop_reset_delay;
1c7c6357 2176 mcp->mb[3] = 0;
1da177e4 2177 }
1da177e4 2178 mcp->in_mb = MBX_0;
b93480e3 2179 mcp->tov = MBX_TOV_SECONDS;
1da177e4 2180 mcp->flags = 0;
7b867cf7 2181 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 2182
2183 if (rval != QLA_SUCCESS) {
2184 /*EMPTY*/
7c3df132 2185 ql_dbg(ql_dbg_mbx, vha, 0x105b, "Failed=%x.\n", rval);
1da177e4
LT		 2186 } else {
2187 /*EMPTY*/
5f28d2d7
SK		 2188 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x105c,
2189 "Done %s.\n", __func__);
1da177e4
LT		 2190 }
2191
2192 return rval;
2193}
2194
2195/*
2196 * qla2x00_send_sns
2197 * Send SNS command.
2198 *
2199 * Input:
2200 * ha = adapter block pointer.
2201 * sns = pointer for command.
2202 * cmd_size = command size.
2203 * buf_size = response/command size.
2204 * TARGET_QUEUE_LOCK must be released.
2205 * ADAPTER_STATE_LOCK must be released.
2206 *
2207 * Returns:
2208 * qla2x00 local function return status code.
2209 *
2210 * Context:
2211 * Kernel context.
2212 */
2213int
7b867cf7 2214qla2x00_send_sns(scsi_qla_host_t *vha, dma_addr_t sns_phys_address,
1da177e4
LT		 2215 uint16_t cmd_size, size_t buf_size)
2216{
2217 int rval;
2218 mbx_cmd_t mc;
2219 mbx_cmd_t *mcp = &mc;
2220
5f28d2d7
SK		 2221 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x105d,
2222 "Entered %s.\n", __func__);
1da177e4 2223
5f28d2d7 2224 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x105e,
7c3df132
SK		 2225 "Retry cnt=%d ratov=%d total tov=%d.\n",
2226 vha->hw->retry_count, vha->hw->login_timeout, mcp->tov);
1da177e4
LT		 2227
2228 mcp->mb[0] = MBC_SEND_SNS_COMMAND;
2229 mcp->mb[1] = cmd_size;
2230 mcp->mb[2] = MSW(sns_phys_address);
2231 mcp->mb[3] = LSW(sns_phys_address);
2232 mcp->mb[6] = MSW(MSD(sns_phys_address));
2233 mcp->mb[7] = LSW(MSD(sns_phys_address));
2234 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
2235 mcp->in_mb = MBX_0|MBX_1;
2236 mcp->buf_size = buf_size;
2237 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN;
7b867cf7
AC		 2238 mcp->tov = (vha->hw->login_timeout * 2) + (vha->hw->login_timeout / 2);
2239 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 2240
2241 if (rval != QLA_SUCCESS) {
2242 /*EMPTY*/
7c3df132
SK		 2243 ql_dbg(ql_dbg_mbx, vha, 0x105f,
2244 "Failed=%x mb[0]=%x mb[1]=%x.\n",
2245 rval, mcp->mb[0], mcp->mb[1]);
1da177e4
LT		 2246 } else {
2247 /*EMPTY*/
5f28d2d7
SK		 2248 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1060,
2249 "Done %s.\n", __func__);
1da177e4
LT		 2250 }
2251
2252 return rval;
2253}
2254
1c7c6357 2255int
7b867cf7 2256qla24xx_login_fabric(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain,
1c7c6357
AV		 2257 uint8_t area, uint8_t al_pa, uint16_t *mb, uint8_t opt)
2258{
2259 int rval;
2260
2261 struct logio_entry_24xx *lg;
2262 dma_addr_t lg_dma;
2263 uint32_t iop[2];
7b867cf7 2264 struct qla_hw_data *ha = vha->hw;
2afa19a9 2265 struct req_que *req;
1c7c6357 2266
5f28d2d7
SK		 2267 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1061,
2268 "Entered %s.\n", __func__);
1c7c6357 2269
d7459527
MH		 2270 if (vha->vp_idx && vha->qpair)
2271 req = vha->qpair->req;
68ca949c 2272 else
d7459527 2273 req = ha->req_q_map[0];
2afa19a9 2274
08eb7f45 2275 lg = dma_pool_zalloc(ha->s_dma_pool, GFP_KERNEL, &lg_dma);
1c7c6357 2276 if (lg == NULL) {
7c3df132
SK		 2277 ql_log(ql_log_warn, vha, 0x1062,
2278 "Failed to allocate login IOCB.\n");
1c7c6357
AV		 2279 return QLA_MEMORY_ALLOC_FAILED;
2280 }
1c7c6357
AV		 2281
2282 lg->entry_type = LOGINOUT_PORT_IOCB_TYPE;
2283 lg->entry_count = 1;
2afa19a9 2284 lg->handle = MAKE_HANDLE(req->id, lg->handle);
1c7c6357 2285 lg->nport_handle = cpu_to_le16(loop_id);
ad950360 2286 lg->control_flags = cpu_to_le16(LCF_COMMAND_PLOGI);
1c7c6357 2287 if (opt & BIT_0)
ad950360 2288 lg->control_flags |= cpu_to_le16(LCF_COND_PLOGI);
8baa51a6 2289 if (opt & BIT_1)
ad950360 2290 lg->control_flags |= cpu_to_le16(LCF_SKIP_PRLI);
1c7c6357
AV		 2291 lg->port_id[0] = al_pa;
2292 lg->port_id[1] = area;
2293 lg->port_id[2] = domain;
7b867cf7 2294 lg->vp_index = vha->vp_idx;
7f45dd0b
AV		 2295 rval = qla2x00_issue_iocb_timeout(vha, lg, lg_dma, 0,
2296 (ha->r_a_tov / 10 * 2) + 2);
1c7c6357 2297 if (rval != QLA_SUCCESS) {
7c3df132
SK		 2298 ql_dbg(ql_dbg_mbx, vha, 0x1063,
2299 "Failed to issue login IOCB (%x).\n", rval);
1c7c6357 2300 } else if (lg->entry_status != 0) {
7c3df132
SK		 2301 ql_dbg(ql_dbg_mbx, vha, 0x1064,
2302 "Failed to complete IOCB -- error status (%x).\n",
2303 lg->entry_status);
1c7c6357 2304 rval = QLA_FUNCTION_FAILED;
ad950360 2305 } else if (lg->comp_status != cpu_to_le16(CS_COMPLETE)) {
1c7c6357
AV		 2306 iop[0] = le32_to_cpu(lg->io_parameter[0]);
2307 iop[1] = le32_to_cpu(lg->io_parameter[1]);
2308
7c3df132
SK		 2309 ql_dbg(ql_dbg_mbx, vha, 0x1065,
2310 "Failed to complete IOCB -- completion status (%x) "
2311 "ioparam=%x/%x.\n", le16_to_cpu(lg->comp_status),
2312 iop[0], iop[1]);
1c7c6357
AV		 2313
2314 switch (iop[0]) {
2315 case LSC_SCODE_PORTID_USED:
2316 mb[0] = MBS_PORT_ID_USED;
2317 mb[1] = LSW(iop[1]);
2318 break;
2319 case LSC_SCODE_NPORT_USED:
2320 mb[0] = MBS_LOOP_ID_USED;
2321 break;
2322 case LSC_SCODE_NOLINK:
2323 case LSC_SCODE_NOIOCB:
2324 case LSC_SCODE_NOXCB:
2325 case LSC_SCODE_CMD_FAILED:
2326 case LSC_SCODE_NOFABRIC:
2327 case LSC_SCODE_FW_NOT_READY:
2328 case LSC_SCODE_NOT_LOGGED_IN:
2329 case LSC_SCODE_NOPCB:
2330 case LSC_SCODE_ELS_REJECT:
2331 case LSC_SCODE_CMD_PARAM_ERR:
2332 case LSC_SCODE_NONPORT:
2333 case LSC_SCODE_LOGGED_IN:
2334 case LSC_SCODE_NOFLOGI_ACC:
2335 default:
2336 mb[0] = MBS_COMMAND_ERROR;
2337 break;
2338 }
2339 } else {
5f28d2d7
SK		 2340 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1066,
2341 "Done %s.\n", __func__);
1c7c6357
AV		 2342
2343 iop[0] = le32_to_cpu(lg->io_parameter[0]);
2344
2345 mb[0] = MBS_COMMAND_COMPLETE;
2346 mb[1] = 0;
2347 if (iop[0] & BIT_4) {
2348 if (iop[0] & BIT_8)
2349 mb[1] |= BIT_1;
2350 } else
2351 mb[1] = BIT_0;
ad3e0eda
AV		 2352
2353 /* Passback COS information. */
2354 mb[10] = 0;
2355 if (lg->io_parameter[7] || lg->io_parameter[8])
2356 mb[10] |= BIT_0; /* Class 2. */
2357 if (lg->io_parameter[9] || lg->io_parameter[10])
2358 mb[10] |= BIT_1; /* Class 3. */
ad950360 2359 if (lg->io_parameter[0] & cpu_to_le32(BIT_7))
2d70c103
NB		 2360 mb[10] |= BIT_7; /* Confirmed Completion
2361 * Allowed
2362 */
1c7c6357
AV		 2363 }
2364
2365 dma_pool_free(ha->s_dma_pool, lg, lg_dma);
2366
2367 return rval;
2368}
2369
1da177e4
LT		 2370/*
2371 * qla2x00_login_fabric
2372 * Issue login fabric port mailbox command.
2373 *
2374 * Input:
2375 * ha = adapter block pointer.
2376 * loop_id = device loop ID.
2377 * domain = device domain.
2378 * area = device area.
2379 * al_pa = device AL_PA.
2380 * status = pointer for return status.
2381 * opt = command options.
2382 * TARGET_QUEUE_LOCK must be released.
2383 * ADAPTER_STATE_LOCK must be released.
2384 *
2385 * Returns:
2386 * qla2x00 local function return status code.
2387 *
2388 * Context:
2389 * Kernel context.
2390 */
2391int
7b867cf7 2392qla2x00_login_fabric(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain,
1da177e4
LT		 2393 uint8_t area, uint8_t al_pa, uint16_t *mb, uint8_t opt)
2394{
2395 int rval;
2396 mbx_cmd_t mc;
2397 mbx_cmd_t *mcp = &mc;
7b867cf7 2398 struct qla_hw_data *ha = vha->hw;
1da177e4 2399
5f28d2d7
SK		 2400 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1067,
2401 "Entered %s.\n", __func__);
1da177e4
LT		 2402
2403 mcp->mb[0] = MBC_LOGIN_FABRIC_PORT;
2404 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
2405 if (HAS_EXTENDED_IDS(ha)) {
2406 mcp->mb[1] = loop_id;
2407 mcp->mb[10] = opt;
2408 mcp->out_mb |= MBX_10;
2409 } else {
2410 mcp->mb[1] = (loop_id << 8) | opt;
2411 }
2412 mcp->mb[2] = domain;
2413 mcp->mb[3] = area << 8 | al_pa;
2414
2415 mcp->in_mb = MBX_7|MBX_6|MBX_2|MBX_1|MBX_0;
2416 mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2);
2417 mcp->flags = 0;
7b867cf7 2418 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 2419
2420 /* Return mailbox statuses. */
2421 if (mb != NULL) {
2422 mb[0] = mcp->mb[0];
2423 mb[1] = mcp->mb[1];
2424 mb[2] = mcp->mb[2];
2425 mb[6] = mcp->mb[6];
2426 mb[7] = mcp->mb[7];
ad3e0eda
AV		 2427 /* COS retrieved from Get-Port-Database mailbox command. */
2428 mb[10] = 0;
1da177e4
LT		 2429 }
2430
2431 if (rval != QLA_SUCCESS) {
2432 /* RLU tmp code: need to change main mailbox_command function to
2433 * return ok even when the mailbox completion value is not
2434 * SUCCESS. The caller needs to be responsible to interpret
2435 * the return values of this mailbox command if we're not
2436 * to change too much of the existing code.
2437 */
2438 if (mcp->mb[0] == 0x4001 || mcp->mb[0] == 0x4002 ||
2439 mcp->mb[0] == 0x4003 || mcp->mb[0] == 0x4005 ||
2440 mcp->mb[0] == 0x4006)
2441 rval = QLA_SUCCESS;
2442
2443 /*EMPTY*/
7c3df132
SK		 2444 ql_dbg(ql_dbg_mbx, vha, 0x1068,
2445 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n",
2446 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]);
1da177e4
LT		 2447 } else {
2448 /*EMPTY*/
5f28d2d7
SK		 2449 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1069,
2450 "Done %s.\n", __func__);
1da177e4
LT		 2451 }
2452
2453 return rval;
2454}
2455
2456/*
2457 * qla2x00_login_local_device
2458 * Issue login loop port mailbox command.
fa2a1ce5 2459 *
1da177e4
LT		 2460 * Input:
2461 * ha = adapter block pointer.
2462 * loop_id = device loop ID.
2463 * opt = command options.
fa2a1ce5 2464 *
1da177e4
LT		 2465 * Returns:
2466 * Return status code.
fa2a1ce5 2467 *
1da177e4
LT		 2468 * Context:
2469 * Kernel context.
fa2a1ce5 2470 *
1da177e4
LT		 2471 */
2472int
7b867cf7 2473qla2x00_login_local_device(scsi_qla_host_t *vha, fc_port_t *fcport,
1da177e4
LT		 2474 uint16_t *mb_ret, uint8_t opt)
2475{
2476 int rval;
2477 mbx_cmd_t mc;
2478 mbx_cmd_t *mcp = &mc;
7b867cf7 2479 struct qla_hw_data *ha = vha->hw;
1da177e4 2480
5f28d2d7
SK		 2481 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x106a,
2482 "Entered %s.\n", __func__);
7c3df132 2483
e428924c 2484 if (IS_FWI2_CAPABLE(ha))
7b867cf7 2485 return qla24xx_login_fabric(vha, fcport->loop_id,
9a52a57c 2486 fcport->d_id.b.domain, fcport->d_id.b.area,
2487 fcport->d_id.b.al_pa, mb_ret, opt);
2488
1da177e4
LT		 2489 mcp->mb[0] = MBC_LOGIN_LOOP_PORT;
2490 if (HAS_EXTENDED_IDS(ha))
9a52a57c 2491 mcp->mb[1] = fcport->loop_id;
1da177e4 2492 else
9a52a57c 2493 mcp->mb[1] = fcport->loop_id << 8;
1da177e4
LT		 2494 mcp->mb[2] = opt;
2495 mcp->out_mb = MBX_2|MBX_1|MBX_0;
2496 mcp->in_mb = MBX_7|MBX_6|MBX_1|MBX_0;
2497 mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2);
2498 mcp->flags = 0;
7b867cf7 2499 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 2500
2501 /* Return mailbox statuses. */
2502 if (mb_ret != NULL) {
2503 mb_ret[0] = mcp->mb[0];
2504 mb_ret[1] = mcp->mb[1];
2505 mb_ret[6] = mcp->mb[6];
2506 mb_ret[7] = mcp->mb[7];
2507 }
2508
2509 if (rval != QLA_SUCCESS) {
2510 /* AV tmp code: need to change main mailbox_command function to
2511 * return ok even when the mailbox completion value is not
2512 * SUCCESS. The caller needs to be responsible to interpret
2513 * the return values of this mailbox command if we're not
2514 * to change too much of the existing code.
2515 */
2516 if (mcp->mb[0] == 0x4005 || mcp->mb[0] == 0x4006)
2517 rval = QLA_SUCCESS;
2518
7c3df132
SK		 2519 ql_dbg(ql_dbg_mbx, vha, 0x106b,
2520 "Failed=%x mb[0]=%x mb[1]=%x mb[6]=%x mb[7]=%x.\n",
2521 rval, mcp->mb[0], mcp->mb[1], mcp->mb[6], mcp->mb[7]);
1da177e4
LT		 2522 } else {
2523 /*EMPTY*/
5f28d2d7
SK		 2524 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x106c,
2525 "Done %s.\n", __func__);
1da177e4
LT		 2526 }
2527
2528 return (rval);
2529}
2530
1c7c6357 2531int
7b867cf7 2532qla24xx_fabric_logout(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain,
1c7c6357
AV		 2533 uint8_t area, uint8_t al_pa)
2534{
2535 int rval;
2536 struct logio_entry_24xx *lg;
2537 dma_addr_t lg_dma;
7b867cf7 2538 struct qla_hw_data *ha = vha->hw;
2afa19a9 2539 struct req_que *req;
1c7c6357 2540
5f28d2d7
SK		 2541 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x106d,
2542 "Entered %s.\n", __func__);
1c7c6357 2543
08eb7f45 2544 lg = dma_pool_zalloc(ha->s_dma_pool, GFP_KERNEL, &lg_dma);
1c7c6357 2545 if (lg == NULL) {
7c3df132
SK		 2546 ql_log(ql_log_warn, vha, 0x106e,
2547 "Failed to allocate logout IOCB.\n");
1c7c6357
AV		 2548 return QLA_MEMORY_ALLOC_FAILED;
2549 }
1c7c6357 2550
d7459527 2551 req = vha->req;
1c7c6357
AV		 2552 lg->entry_type = LOGINOUT_PORT_IOCB_TYPE;
2553 lg->entry_count = 1;
2afa19a9 2554 lg->handle = MAKE_HANDLE(req->id, lg->handle);
1c7c6357
AV		 2555 lg->nport_handle = cpu_to_le16(loop_id);
2556 lg->control_flags =
ad950360 2557 cpu_to_le16(LCF_COMMAND_LOGO|LCF_IMPL_LOGO|
c8d6691b 2558 LCF_FREE_NPORT);
1c7c6357
AV		 2559 lg->port_id[0] = al_pa;
2560 lg->port_id[1] = area;
2561 lg->port_id[2] = domain;
7b867cf7 2562 lg->vp_index = vha->vp_idx;
7f45dd0b
AV		 2563 rval = qla2x00_issue_iocb_timeout(vha, lg, lg_dma, 0,
2564 (ha->r_a_tov / 10 * 2) + 2);
1c7c6357 2565 if (rval != QLA_SUCCESS) {
7c3df132
SK		 2566 ql_dbg(ql_dbg_mbx, vha, 0x106f,
2567 "Failed to issue logout IOCB (%x).\n", rval);
1c7c6357 2568 } else if (lg->entry_status != 0) {
7c3df132
SK		 2569 ql_dbg(ql_dbg_mbx, vha, 0x1070,
2570 "Failed to complete IOCB -- error status (%x).\n",
2571 lg->entry_status);
1c7c6357 2572 rval = QLA_FUNCTION_FAILED;
ad950360 2573 } else if (lg->comp_status != cpu_to_le16(CS_COMPLETE)) {
7c3df132
SK		 2574 ql_dbg(ql_dbg_mbx, vha, 0x1071,
2575 "Failed to complete IOCB -- completion status (%x) "
2576 "ioparam=%x/%x.\n", le16_to_cpu(lg->comp_status),
1c7c6357 2577 le32_to_cpu(lg->io_parameter[0]),
7c3df132 2578 le32_to_cpu(lg->io_parameter[1]));
1c7c6357
AV		 2579 } else {
2580 /*EMPTY*/
5f28d2d7
SK		 2581 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1072,
2582 "Done %s.\n", __func__);
1c7c6357
AV		 2583 }
2584
2585 dma_pool_free(ha->s_dma_pool, lg, lg_dma);
2586
2587 return rval;
2588}
2589
1da177e4
LT		 2590/*
2591 * qla2x00_fabric_logout
2592 * Issue logout fabric port mailbox command.
2593 *
2594 * Input:
2595 * ha = adapter block pointer.
2596 * loop_id = device loop ID.
2597 * TARGET_QUEUE_LOCK must be released.
2598 * ADAPTER_STATE_LOCK must be released.
2599 *
2600 * Returns:
2601 * qla2x00 local function return status code.
2602 *
2603 * Context:
2604 * Kernel context.
2605 */
2606int
7b867cf7 2607qla2x00_fabric_logout(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain,
1c7c6357 2608 uint8_t area, uint8_t al_pa)
1da177e4
LT		 2609{
2610 int rval;
2611 mbx_cmd_t mc;
2612 mbx_cmd_t *mcp = &mc;
2613
5f28d2d7
SK		 2614 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1073,
2615 "Entered %s.\n", __func__);
1da177e4
LT		 2616
2617 mcp->mb[0] = MBC_LOGOUT_FABRIC_PORT;
2618 mcp->out_mb = MBX_1|MBX_0;
7b867cf7 2619 if (HAS_EXTENDED_IDS(vha->hw)) {
1da177e4
LT		 2620 mcp->mb[1] = loop_id;
2621 mcp->mb[10] = 0;
2622 mcp->out_mb |= MBX_10;
2623 } else {
2624 mcp->mb[1] = loop_id << 8;
2625 }
2626
2627 mcp->in_mb = MBX_1|MBX_0;
b93480e3 2628 mcp->tov = MBX_TOV_SECONDS;
1da177e4 2629 mcp->flags = 0;
7b867cf7 2630 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 2631
2632 if (rval != QLA_SUCCESS) {
2633 /*EMPTY*/
7c3df132
SK		 2634 ql_dbg(ql_dbg_mbx, vha, 0x1074,
2635 "Failed=%x mb[1]=%x.\n", rval, mcp->mb[1]);
1da177e4
LT		 2636 } else {
2637 /*EMPTY*/
5f28d2d7
SK		 2638 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1075,
2639 "Done %s.\n", __func__);
1da177e4
LT		 2640 }
2641
2642 return rval;
2643}
2644
2645/*
2646 * qla2x00_full_login_lip
2647 * Issue full login LIP mailbox command.
2648 *
2649 * Input:
2650 * ha = adapter block pointer.
2651 * TARGET_QUEUE_LOCK must be released.
2652 * ADAPTER_STATE_LOCK must be released.
2653 *
2654 * Returns:
2655 * qla2x00 local function return status code.
2656 *
2657 * Context:
2658 * Kernel context.
2659 */
2660int
7b867cf7 2661qla2x00_full_login_lip(scsi_qla_host_t *vha)
1da177e4
LT		 2662{
2663 int rval;
2664 mbx_cmd_t mc;
2665 mbx_cmd_t *mcp = &mc;
2666
5f28d2d7
SK		 2667 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1076,
2668 "Entered %s.\n", __func__);
1da177e4
LT		 2669
2670 mcp->mb[0] = MBC_LIP_FULL_LOGIN;
7b867cf7 2671 mcp->mb[1] = IS_FWI2_CAPABLE(vha->hw) ? BIT_3 : 0;
0c8c39af 2672 mcp->mb[2] = 0;
1da177e4
LT		 2673 mcp->mb[3] = 0;
2674 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
2675 mcp->in_mb = MBX_0;
b93480e3 2676 mcp->tov = MBX_TOV_SECONDS;
1da177e4 2677 mcp->flags = 0;
7b867cf7 2678 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 2679
2680 if (rval != QLA_SUCCESS) {
2681 /*EMPTY*/
7c3df132 2682 ql_dbg(ql_dbg_mbx, vha, 0x1077, "Failed=%x.\n", rval);
1da177e4
LT		 2683 } else {
2684 /*EMPTY*/
5f28d2d7
SK		 2685 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1078,
2686 "Done %s.\n", __func__);
1da177e4
LT		 2687 }
2688
2689 return rval;
2690}
2691
2692/*
2693 * qla2x00_get_id_list
2694 *
2695 * Input:
2696 * ha = adapter block pointer.
2697 *
2698 * Returns:
2699 * qla2x00 local function return status code.
2700 *
2701 * Context:
2702 * Kernel context.
2703 */
2704int
7b867cf7 2705qla2x00_get_id_list(scsi_qla_host_t *vha, void *id_list, dma_addr_t id_list_dma,
1da177e4
LT		 2706 uint16_t *entries)
2707{
2708 int rval;
2709 mbx_cmd_t mc;
2710 mbx_cmd_t *mcp = &mc;
2711
5f28d2d7
SK		 2712 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1079,
2713 "Entered %s.\n", __func__);
1da177e4
LT		 2714
2715 if (id_list == NULL)
2716 return QLA_FUNCTION_FAILED;
2717
2718 mcp->mb[0] = MBC_GET_ID_LIST;
1c7c6357 2719 mcp->out_mb = MBX_0;
7b867cf7 2720 if (IS_FWI2_CAPABLE(vha->hw)) {
1c7c6357
AV		 2721 mcp->mb[2] = MSW(id_list_dma);
2722 mcp->mb[3] = LSW(id_list_dma);
2723 mcp->mb[6] = MSW(MSD(id_list_dma));
2724 mcp->mb[7] = LSW(MSD(id_list_dma));
247ec457 2725 mcp->mb[8] = 0;
7b867cf7 2726 mcp->mb[9] = vha->vp_idx;
2c3dfe3f 2727 mcp->out_mb |= MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2;
1c7c6357
AV		 2728 } else {
2729 mcp->mb[1] = MSW(id_list_dma);
2730 mcp->mb[2] = LSW(id_list_dma);
2731 mcp->mb[3] = MSW(MSD(id_list_dma));
2732 mcp->mb[6] = LSW(MSD(id_list_dma));
2733 mcp->out_mb |= MBX_6|MBX_3|MBX_2|MBX_1;
2734 }
1da177e4 2735 mcp->in_mb = MBX_1|MBX_0;
b93480e3 2736 mcp->tov = MBX_TOV_SECONDS;
1da177e4 2737 mcp->flags = 0;
7b867cf7 2738 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 2739
2740 if (rval != QLA_SUCCESS) {
2741 /*EMPTY*/
7c3df132 2742 ql_dbg(ql_dbg_mbx, vha, 0x107a, "Failed=%x.\n", rval);
1da177e4
LT		 2743 } else {
2744 *entries = mcp->mb[1];
5f28d2d7
SK		 2745 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x107b,
2746 "Done %s.\n", __func__);
1da177e4
LT		 2747 }
2748
2749 return rval;
2750}
2751
2752/*
2753 * qla2x00_get_resource_cnts
2754 * Get current firmware resource counts.
2755 *
2756 * Input:
2757 * ha = adapter block pointer.
2758 *
2759 * Returns:
2760 * qla2x00 local function return status code.
2761 *
2762 * Context:
2763 * Kernel context.
2764 */
2765int
03e8c680 2766qla2x00_get_resource_cnts(scsi_qla_host_t *vha)
1da177e4 2767{
03e8c680 2768 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 2769 int rval;
2770 mbx_cmd_t mc;
2771 mbx_cmd_t *mcp = &mc;
2772
5f28d2d7
SK		 2773 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x107c,
2774 "Entered %s.\n", __func__);
1da177e4
LT		 2775
2776 mcp->mb[0] = MBC_GET_RESOURCE_COUNTS;
2777 mcp->out_mb = MBX_0;
4d0ea247 2778 mcp->in_mb = MBX_11|MBX_10|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
f73cb695 2779 if (IS_QLA81XX(vha->hw) || IS_QLA83XX(vha->hw) || IS_QLA27XX(vha->hw))
f3a0a77e 2780 mcp->in_mb |= MBX_12;
b93480e3 2781 mcp->tov = MBX_TOV_SECONDS;
1da177e4 2782 mcp->flags = 0;
7b867cf7 2783 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 2784
2785 if (rval != QLA_SUCCESS) {
2786 /*EMPTY*/
7c3df132
SK		 2787 ql_dbg(ql_dbg_mbx, vha, 0x107d,
2788 "Failed mb[0]=%x.\n", mcp->mb[0]);
1da177e4 2789 } else {
5f28d2d7 2790 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x107e,
7c3df132
SK		 2791 "Done %s mb1=%x mb2=%x mb3=%x mb6=%x mb7=%x mb10=%x "
2792 "mb11=%x mb12=%x.\n", __func__, mcp->mb[1], mcp->mb[2],
2793 mcp->mb[3], mcp->mb[6], mcp->mb[7], mcp->mb[10],
2794 mcp->mb[11], mcp->mb[12]);
1da177e4 2795
03e8c680
QT		 2796 ha->orig_fw_tgt_xcb_count = mcp->mb[1];
2797 ha->cur_fw_tgt_xcb_count = mcp->mb[2];
2798 ha->cur_fw_xcb_count = mcp->mb[3];
2799 ha->orig_fw_xcb_count = mcp->mb[6];
2800 ha->cur_fw_iocb_count = mcp->mb[7];
2801 ha->orig_fw_iocb_count = mcp->mb[10];
2802 if (ha->flags.npiv_supported)
2803 ha->max_npiv_vports = mcp->mb[11];
2804 if (IS_QLA81XX(ha) || IS_QLA83XX(ha) || IS_QLA27XX(ha))
2805 ha->fw_max_fcf_count = mcp->mb[12];
1da177e4
LT		 2806 }
2807
2808 return (rval);
2809}
2810
1da177e4
LT		 2811/*
2812 * qla2x00_get_fcal_position_map
2813 * Get FCAL (LILP) position map using mailbox command
2814 *
2815 * Input:
2816 * ha = adapter state pointer.
2817 * pos_map = buffer pointer (can be NULL).
2818 *
2819 * Returns:
2820 * qla2x00 local function return status code.
2821 *
2822 * Context:
2823 * Kernel context.
2824 */
2825int
7b867cf7 2826qla2x00_get_fcal_position_map(scsi_qla_host_t *vha, char *pos_map)
1da177e4
LT		 2827{
2828 int rval;
2829 mbx_cmd_t mc;
2830 mbx_cmd_t *mcp = &mc;
2831 char *pmap;
2832 dma_addr_t pmap_dma;
7b867cf7 2833 struct qla_hw_data *ha = vha->hw;
1da177e4 2834
5f28d2d7
SK		 2835 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x107f,
2836 "Entered %s.\n", __func__);
7c3df132 2837
08eb7f45 2838 pmap = dma_pool_zalloc(ha->s_dma_pool, GFP_KERNEL, &pmap_dma);
1da177e4 2839 if (pmap == NULL) {
7c3df132
SK		 2840 ql_log(ql_log_warn, vha, 0x1080,
2841 "Memory alloc failed.\n");
1da177e4
LT		 2842 return QLA_MEMORY_ALLOC_FAILED;
2843 }
1da177e4
LT		 2844
2845 mcp->mb[0] = MBC_GET_FC_AL_POSITION_MAP;
2846 mcp->mb[2] = MSW(pmap_dma);
2847 mcp->mb[3] = LSW(pmap_dma);
2848 mcp->mb[6] = MSW(MSD(pmap_dma));
2849 mcp->mb[7] = LSW(MSD(pmap_dma));
2850 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_0;
2851 mcp->in_mb = MBX_1|MBX_0;
2852 mcp->buf_size = FCAL_MAP_SIZE;
2853 mcp->flags = MBX_DMA_IN;
2854 mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2);
7b867cf7 2855 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 2856
2857 if (rval == QLA_SUCCESS) {
5f28d2d7 2858 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1081,
7c3df132
SK		 2859 "mb0/mb1=%x/%X FC/AL position map size (%x).\n",
2860 mcp->mb[0], mcp->mb[1], (unsigned)pmap[0]);
2861 ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x111d,
2862 pmap, pmap[0] + 1);
1da177e4
LT		 2863
2864 if (pos_map)
2865 memcpy(pos_map, pmap, FCAL_MAP_SIZE);
2866 }
2867 dma_pool_free(ha->s_dma_pool, pmap, pmap_dma);
2868
2869 if (rval != QLA_SUCCESS) {
7c3df132 2870 ql_dbg(ql_dbg_mbx, vha, 0x1082, "Failed=%x.\n", rval);
1da177e4 2871 } else {
5f28d2d7
SK		 2872 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1083,
2873 "Done %s.\n", __func__);
1da177e4
LT		 2874 }
2875
2876 return rval;
2877}
392e2f65 2878
2879/*
2880 * qla2x00_get_link_status
2881 *
2882 * Input:
2883 * ha = adapter block pointer.
2884 * loop_id = device loop ID.
2885 * ret_buf = pointer to link status return buffer.
2886 *
2887 * Returns:
2888 * 0 = success.
2889 * BIT_0 = mem alloc error.
2890 * BIT_1 = mailbox error.
2891 */
2892int
7b867cf7 2893qla2x00_get_link_status(scsi_qla_host_t *vha, uint16_t loop_id,
43ef0580 2894 struct link_statistics *stats, dma_addr_t stats_dma)
392e2f65 2895{
2896 int rval;
2897 mbx_cmd_t mc;
2898 mbx_cmd_t *mcp = &mc;
c6dc9905
JC		 2899 uint32_t *iter = (void *)stats;
2900 ushort dwords = offsetof(typeof(*stats), link_up_cnt)/sizeof(*iter);
7b867cf7 2901 struct qla_hw_data *ha = vha->hw;
392e2f65 2902
5f28d2d7
SK		 2903 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1084,
2904 "Entered %s.\n", __func__);
392e2f65 2905
392e2f65 2906 mcp->mb[0] = MBC_GET_LINK_STATUS;
c6dc9905
JC		 2907 mcp->mb[2] = MSW(LSD(stats_dma));
2908 mcp->mb[3] = LSW(LSD(stats_dma));
43ef0580
AV		 2909 mcp->mb[6] = MSW(MSD(stats_dma));
2910 mcp->mb[7] = LSW(MSD(stats_dma));
392e2f65 2911 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_0;
2912 mcp->in_mb = MBX_0;
e428924c 2913 if (IS_FWI2_CAPABLE(ha)) {
392e2f65 2914 mcp->mb[1] = loop_id;
2915 mcp->mb[4] = 0;
2916 mcp->mb[10] = 0;
2917 mcp->out_mb |= MBX_10|MBX_4|MBX_1;
2918 mcp->in_mb |= MBX_1;
2919 } else if (HAS_EXTENDED_IDS(ha)) {
2920 mcp->mb[1] = loop_id;
2921 mcp->mb[10] = 0;
2922 mcp->out_mb |= MBX_10|MBX_1;
2923 } else {
2924 mcp->mb[1] = loop_id << 8;
2925 mcp->out_mb |= MBX_1;
2926 }
b93480e3 2927 mcp->tov = MBX_TOV_SECONDS;
392e2f65 2928 mcp->flags = IOCTL_CMD;
7b867cf7 2929 rval = qla2x00_mailbox_command(vha, mcp);
392e2f65 2930
2931 if (rval == QLA_SUCCESS) {
2932 if (mcp->mb[0] != MBS_COMMAND_COMPLETE) {
7c3df132
SK		 2933 ql_dbg(ql_dbg_mbx, vha, 0x1085,
2934 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
43ef0580 2935 rval = QLA_FUNCTION_FAILED;
392e2f65 2936 } else {
c6dc9905 2937 /* Re-endianize - firmware data is le32. */
5f28d2d7
SK		 2938 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1086,
2939 "Done %s.\n", __func__);
da08ef5c
JC		 2940 for ( ; dwords--; iter++)
2941 le32_to_cpus(iter);
392e2f65 2942 }
2943 } else {
2944 /* Failed. */
7c3df132 2945 ql_dbg(ql_dbg_mbx, vha, 0x1087, "Failed=%x.\n", rval);
392e2f65 2946 }
2947
392e2f65 2948 return rval;
2949}
2950
2951int
7b867cf7 2952qla24xx_get_isp_stats(scsi_qla_host_t *vha, struct link_statistics *stats,
15f30a57 2953 dma_addr_t stats_dma, uint16_t options)
1c7c6357
AV		 2954{
2955 int rval;
2956 mbx_cmd_t mc;
2957 mbx_cmd_t *mcp = &mc;
da08ef5c 2958 uint32_t *iter, dwords;
1c7c6357 2959
5f28d2d7
SK		 2960 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1088,
2961 "Entered %s.\n", __func__);
1c7c6357 2962
15f30a57
QT		 2963 memset(&mc, 0, sizeof(mc));
2964 mc.mb[0] = MBC_GET_LINK_PRIV_STATS;
2965 mc.mb[2] = MSW(stats_dma);
2966 mc.mb[3] = LSW(stats_dma);
2967 mc.mb[6] = MSW(MSD(stats_dma));
2968 mc.mb[7] = LSW(MSD(stats_dma));
2969 mc.mb[8] = sizeof(struct link_statistics) / 4;
2970 mc.mb[9] = cpu_to_le16(vha->vp_idx);
2971 mc.mb[10] = cpu_to_le16(options);
2972
2973 rval = qla24xx_send_mb_cmd(vha, &mc);
1c7c6357
AV		 2974
2975 if (rval == QLA_SUCCESS) {
2976 if (mcp->mb[0] != MBS_COMMAND_COMPLETE) {
7c3df132
SK		 2977 ql_dbg(ql_dbg_mbx, vha, 0x1089,
2978 "Failed mb[0]=%x.\n", mcp->mb[0]);
43ef0580 2979 rval = QLA_FUNCTION_FAILED;
1c7c6357 2980 } else {
5f28d2d7
SK		 2981 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x108a,
2982 "Done %s.\n", __func__);
c6dc9905 2983 /* Re-endianize - firmware data is le32. */
43ef0580 2984 dwords = sizeof(struct link_statistics) / 4;
da08ef5c
JC		 2985 iter = &stats->link_fail_cnt;
2986 for ( ; dwords--; iter++)
2987 le32_to_cpus(iter);
1c7c6357
AV		 2988 }
2989 } else {
2990 /* Failed. */
7c3df132 2991 ql_dbg(ql_dbg_mbx, vha, 0x108b, "Failed=%x.\n", rval);
1c7c6357
AV		 2992 }
2993
1c7c6357
AV		 2994 return rval;
2995}
1c7c6357
AV		 2996
2997int
2afa19a9 2998qla24xx_abort_command(srb_t *sp)
1c7c6357
AV		 2999{
3000 int rval;
1c7c6357
AV		 3001 unsigned long flags = 0;
3002
3003 struct abort_entry_24xx *abt;
3004 dma_addr_t abt_dma;
3005 uint32_t handle;
2afa19a9
AC		 3006 fc_port_t *fcport = sp->fcport;
3007 struct scsi_qla_host *vha = fcport->vha;
7b867cf7 3008 struct qla_hw_data *ha = vha->hw;
67c2e93a 3009 struct req_que *req = vha->req;
1c7c6357 3010
5f28d2d7
SK		 3011 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x108c,
3012 "Entered %s.\n", __func__);
1c7c6357 3013
d7459527
MH		 3014 if (vha->flags.qpairs_available && sp->qpair)
3015 req = sp->qpair->req;
3016
4440e46d
AB		 3017 if (ql2xasynctmfenable)
3018 return qla24xx_async_abort_command(sp);
3019
7b867cf7 3020 spin_lock_irqsave(&ha->hardware_lock, flags);
8d93f550 3021 for (handle = 1; handle < req->num_outstanding_cmds; handle++) {
7b867cf7 3022 if (req->outstanding_cmds[handle] == sp)
1c7c6357
AV		 3023 break;
3024 }
7b867cf7 3025 spin_unlock_irqrestore(&ha->hardware_lock, flags);
8d93f550 3026 if (handle == req->num_outstanding_cmds) {
1c7c6357
AV		 3027 /* Command not found. */
3028 return QLA_FUNCTION_FAILED;
3029 }
3030
08eb7f45 3031 abt = dma_pool_zalloc(ha->s_dma_pool, GFP_KERNEL, &abt_dma);
1c7c6357 3032 if (abt == NULL) {
7c3df132
SK		 3033 ql_log(ql_log_warn, vha, 0x108d,
3034 "Failed to allocate abort IOCB.\n");
1c7c6357
AV		 3035 return QLA_MEMORY_ALLOC_FAILED;
3036 }
1c7c6357
AV		 3037
3038 abt->entry_type = ABORT_IOCB_TYPE;
3039 abt->entry_count = 1;
2afa19a9 3040 abt->handle = MAKE_HANDLE(req->id, abt->handle);
1c7c6357 3041 abt->nport_handle = cpu_to_le16(fcport->loop_id);
a74ec14f 3042 abt->handle_to_abort = MAKE_HANDLE(req->id, handle);
1c7c6357
AV		 3043 abt->port_id[0] = fcport->d_id.b.al_pa;
3044 abt->port_id[1] = fcport->d_id.b.area;
3045 abt->port_id[2] = fcport->d_id.b.domain;
c6d39e23 3046 abt->vp_index = fcport->vha->vp_idx;
73208dfd
AC		 3047
3048 abt->req_que_no = cpu_to_le16(req->id);
3049
7b867cf7 3050 rval = qla2x00_issue_iocb(vha, abt, abt_dma, 0);
1c7c6357 3051 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3052 ql_dbg(ql_dbg_mbx, vha, 0x108e,
3053 "Failed to issue IOCB (%x).\n", rval);
1c7c6357 3054 } else if (abt->entry_status != 0) {
7c3df132
SK		 3055 ql_dbg(ql_dbg_mbx, vha, 0x108f,
3056 "Failed to complete IOCB -- error status (%x).\n",
3057 abt->entry_status);
1c7c6357 3058 rval = QLA_FUNCTION_FAILED;
ad950360 3059 } else if (abt->nport_handle != cpu_to_le16(0)) {
7c3df132
SK		 3060 ql_dbg(ql_dbg_mbx, vha, 0x1090,
3061 "Failed to complete IOCB -- completion status (%x).\n",
3062 le16_to_cpu(abt->nport_handle));
f934c9d0
CD		 3063 if (abt->nport_handle == CS_IOCB_ERROR)
3064 rval = QLA_FUNCTION_PARAMETER_ERROR;
3065 else
3066 rval = QLA_FUNCTION_FAILED;
1c7c6357 3067 } else {
5f28d2d7
SK		 3068 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1091,
3069 "Done %s.\n", __func__);
1c7c6357
AV		 3070 }
3071
3072 dma_pool_free(ha->s_dma_pool, abt, abt_dma);
3073
3074 return rval;
3075}
3076
3077struct tsk_mgmt_cmd {
3078 union {
3079 struct tsk_mgmt_entry tsk;
3080 struct sts_entry_24xx sts;
3081 } p;
3082};
3083
523ec773
AV		 3084static int
3085__qla24xx_issue_tmf(char *name, uint32_t type, struct fc_port *fcport,
9cb78c16 3086 uint64_t l, int tag)
1c7c6357 3087{
523ec773 3088 int rval, rval2;
1c7c6357 3089 struct tsk_mgmt_cmd *tsk;
9ca1d01f 3090 struct sts_entry_24xx *sts;
1c7c6357 3091 dma_addr_t tsk_dma;
7b867cf7
AC		 3092 scsi_qla_host_t *vha;
3093 struct qla_hw_data *ha;
73208dfd
AC		 3094 struct req_que *req;
3095 struct rsp_que *rsp;
d7459527 3096 struct qla_qpair *qpair;
1c7c6357 3097
7b867cf7
AC		 3098 vha = fcport->vha;
3099 ha = vha->hw;
2afa19a9 3100 req = vha->req;
7c3df132 3101
5f28d2d7
SK		 3102 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1092,
3103 "Entered %s.\n", __func__);
7c3df132 3104
d7459527
MH		 3105 if (vha->vp_idx && vha->qpair) {
3106 /* NPIV port */
3107 qpair = vha->qpair;
3108 rsp = qpair->rsp;
3109 req = qpair->req;
3110 } else {
68ca949c 3111 rsp = req->rsp;
d7459527
MH		 3112 }
3113
08eb7f45 3114 tsk = dma_pool_zalloc(ha->s_dma_pool, GFP_KERNEL, &tsk_dma);
1c7c6357 3115 if (tsk == NULL) {
7c3df132
SK		 3116 ql_log(ql_log_warn, vha, 0x1093,
3117 "Failed to allocate task management IOCB.\n");
1c7c6357
AV		 3118 return QLA_MEMORY_ALLOC_FAILED;
3119 }
1c7c6357
AV		 3120
3121 tsk->p.tsk.entry_type = TSK_MGMT_IOCB_TYPE;
3122 tsk->p.tsk.entry_count = 1;
2afa19a9 3123 tsk->p.tsk.handle = MAKE_HANDLE(req->id, tsk->p.tsk.handle);
1c7c6357 3124 tsk->p.tsk.nport_handle = cpu_to_le16(fcport->loop_id);
00a537b8 3125 tsk->p.tsk.timeout = cpu_to_le16(ha->r_a_tov / 10 * 2);
523ec773 3126 tsk->p.tsk.control_flags = cpu_to_le32(type);
1c7c6357
AV		 3127 tsk->p.tsk.port_id[0] = fcport->d_id.b.al_pa;
3128 tsk->p.tsk.port_id[1] = fcport->d_id.b.area;
3129 tsk->p.tsk.port_id[2] = fcport->d_id.b.domain;
c6d39e23 3130 tsk->p.tsk.vp_index = fcport->vha->vp_idx;
523ec773
AV		 3131 if (type == TCF_LUN_RESET) {
3132 int_to_scsilun(l, &tsk->p.tsk.lun);
3133 host_to_fcp_swap((uint8_t *)&tsk->p.tsk.lun,
3134 sizeof(tsk->p.tsk.lun));
3135 }
2c3dfe3f 3136
9ca1d01f 3137 sts = &tsk->p.sts;
7b867cf7 3138 rval = qla2x00_issue_iocb(vha, tsk, tsk_dma, 0);
1c7c6357 3139 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3140 ql_dbg(ql_dbg_mbx, vha, 0x1094,
3141 "Failed to issue %s reset IOCB (%x).\n", name, rval);
9ca1d01f 3142 } else if (sts->entry_status != 0) {
7c3df132
SK		 3143 ql_dbg(ql_dbg_mbx, vha, 0x1095,
3144 "Failed to complete IOCB -- error status (%x).\n",
3145 sts->entry_status);
1c7c6357 3146 rval = QLA_FUNCTION_FAILED;
ad950360 3147 } else if (sts->comp_status != cpu_to_le16(CS_COMPLETE)) {
7c3df132
SK		 3148 ql_dbg(ql_dbg_mbx, vha, 0x1096,
3149 "Failed to complete IOCB -- completion status (%x).\n",
3150 le16_to_cpu(sts->comp_status));
9ca1d01f 3151 rval = QLA_FUNCTION_FAILED;
97dec564
AV		 3152 } else if (le16_to_cpu(sts->scsi_status) &
3153 SS_RESPONSE_INFO_LEN_VALID) {
3154 if (le32_to_cpu(sts->rsp_data_len) < 4) {
5f28d2d7 3155 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1097,
7c3df132
SK		 3156 "Ignoring inconsistent data length -- not enough "
3157 "response info (%d).\n",
3158 le32_to_cpu(sts->rsp_data_len));
97dec564 3159 } else if (sts->data[3]) {
7c3df132
SK		 3160 ql_dbg(ql_dbg_mbx, vha, 0x1098,
3161 "Failed to complete IOCB -- response (%x).\n",
3162 sts->data[3]);
97dec564
AV		 3163 rval = QLA_FUNCTION_FAILED;
3164 }
1c7c6357
AV		 3165 }
3166
3167 /* Issue marker IOCB. */
73208dfd 3168 rval2 = qla2x00_marker(vha, req, rsp, fcport->loop_id, l,
523ec773
AV		 3169 type == TCF_LUN_RESET ? MK_SYNC_ID_LUN: MK_SYNC_ID);
3170 if (rval2 != QLA_SUCCESS) {
7c3df132
SK		 3171 ql_dbg(ql_dbg_mbx, vha, 0x1099,
3172 "Failed to issue marker IOCB (%x).\n", rval2);
1c7c6357 3173 } else {
5f28d2d7
SK		 3174 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x109a,
3175 "Done %s.\n", __func__);
1c7c6357
AV		 3176 }
3177
7b867cf7 3178 dma_pool_free(ha->s_dma_pool, tsk, tsk_dma);
1c7c6357
AV		 3179
3180 return rval;
3181}
3182
523ec773 3183int
9cb78c16 3184qla24xx_abort_target(struct fc_port *fcport, uint64_t l, int tag)
523ec773 3185{
3822263e
MI		 3186 struct qla_hw_data *ha = fcport->vha->hw;
3187
3188 if ((ql2xasynctmfenable) && IS_FWI2_CAPABLE(ha))
3189 return qla2x00_async_tm_cmd(fcport, TCF_TARGET_RESET, l, tag);
3190
2afa19a9 3191 return __qla24xx_issue_tmf("Target", TCF_TARGET_RESET, fcport, l, tag);
523ec773
AV		 3192}
3193
3194int
9cb78c16 3195qla24xx_lun_reset(struct fc_port *fcport, uint64_t l, int tag)
523ec773 3196{
3822263e
MI		 3197 struct qla_hw_data *ha = fcport->vha->hw;
3198
3199 if ((ql2xasynctmfenable) && IS_FWI2_CAPABLE(ha))
3200 return qla2x00_async_tm_cmd(fcport, TCF_LUN_RESET, l, tag);
3201
2afa19a9 3202 return __qla24xx_issue_tmf("Lun", TCF_LUN_RESET, fcport, l, tag);
523ec773
AV		 3203}
3204
1c7c6357 3205int
7b867cf7 3206qla2x00_system_error(scsi_qla_host_t *vha)
1c7c6357
AV		 3207{
3208 int rval;
3209 mbx_cmd_t mc;
3210 mbx_cmd_t *mcp = &mc;
7b867cf7 3211 struct qla_hw_data *ha = vha->hw;
1c7c6357 3212
68af0811 3213 if (!IS_QLA23XX(ha) && !IS_FWI2_CAPABLE(ha))
1c7c6357
AV		 3214 return QLA_FUNCTION_FAILED;
3215
5f28d2d7
SK		 3216 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x109b,
3217 "Entered %s.\n", __func__);
1c7c6357
AV		 3218
3219 mcp->mb[0] = MBC_GEN_SYSTEM_ERROR;
3220 mcp->out_mb = MBX_0;
3221 mcp->in_mb = MBX_0;
3222 mcp->tov = 5;
3223 mcp->flags = 0;
7b867cf7 3224 rval = qla2x00_mailbox_command(vha, mcp);
1c7c6357
AV		 3225
3226 if (rval != QLA_SUCCESS) {
7c3df132 3227 ql_dbg(ql_dbg_mbx, vha, 0x109c, "Failed=%x.\n", rval);
1c7c6357 3228 } else {
5f28d2d7
SK		 3229 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x109d,
3230 "Done %s.\n", __func__);
1c7c6357
AV		 3231 }
3232
3233 return rval;
3234}
3235
db64e930
JC		 3236int
3237qla2x00_write_serdes_word(scsi_qla_host_t *vha, uint16_t addr, uint16_t data)
3238{
3239 int rval;
3240 mbx_cmd_t mc;
3241 mbx_cmd_t *mcp = &mc;
3242
f299c7c2
JC		 3243 if (!IS_QLA25XX(vha->hw) && !IS_QLA2031(vha->hw) &&
3244 !IS_QLA27XX(vha->hw))
db64e930
JC		 3245 return QLA_FUNCTION_FAILED;
3246
3247 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1182,
3248 "Entered %s.\n", __func__);
3249
3250 mcp->mb[0] = MBC_WRITE_SERDES;
3251 mcp->mb[1] = addr;
064135e0
AV		 3252 if (IS_QLA2031(vha->hw))
3253 mcp->mb[2] = data & 0xff;
3254 else
3255 mcp->mb[2] = data;
3256
db64e930
JC		 3257 mcp->mb[3] = 0;
3258 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
3259 mcp->in_mb = MBX_0;
3260 mcp->tov = MBX_TOV_SECONDS;
3261 mcp->flags = 0;
3262 rval = qla2x00_mailbox_command(vha, mcp);
3263
3264 if (rval != QLA_SUCCESS) {
3265 ql_dbg(ql_dbg_mbx, vha, 0x1183,
3266 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
3267 } else {
3268 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1184,
3269 "Done %s.\n", __func__);
3270 }
3271
3272 return rval;
3273}
3274
3275int
3276qla2x00_read_serdes_word(scsi_qla_host_t *vha, uint16_t addr, uint16_t *data)
3277{
3278 int rval;
3279 mbx_cmd_t mc;
3280 mbx_cmd_t *mcp = &mc;
3281
f299c7c2
JC		 3282 if (!IS_QLA25XX(vha->hw) && !IS_QLA2031(vha->hw) &&
3283 !IS_QLA27XX(vha->hw))
db64e930
JC		 3284 return QLA_FUNCTION_FAILED;
3285
3286 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1185,
3287 "Entered %s.\n", __func__);
3288
3289 mcp->mb[0] = MBC_READ_SERDES;
3290 mcp->mb[1] = addr;
3291 mcp->mb[3] = 0;
3292 mcp->out_mb = MBX_3|MBX_1|MBX_0;
3293 mcp->in_mb = MBX_1|MBX_0;
3294 mcp->tov = MBX_TOV_SECONDS;
3295 mcp->flags = 0;
3296 rval = qla2x00_mailbox_command(vha, mcp);
3297
064135e0
AV		 3298 if (IS_QLA2031(vha->hw))
3299 *data = mcp->mb[1] & 0xff;
3300 else
3301 *data = mcp->mb[1];
db64e930
JC		 3302
3303 if (rval != QLA_SUCCESS) {
3304 ql_dbg(ql_dbg_mbx, vha, 0x1186,
3305 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
3306 } else {
3307 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1187,
3308 "Done %s.\n", __func__);
3309 }
3310
3311 return rval;
3312}
3313
e8887c51
JC		 3314int
3315qla8044_write_serdes_word(scsi_qla_host_t *vha, uint32_t addr, uint32_t data)
3316{
3317 int rval;
3318 mbx_cmd_t mc;
3319 mbx_cmd_t *mcp = &mc;
3320
3321 if (!IS_QLA8044(vha->hw))
3322 return QLA_FUNCTION_FAILED;
3323
83548fe2 3324 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x11a0,
e8887c51
JC		 3325 "Entered %s.\n", __func__);
3326
3327 mcp->mb[0] = MBC_SET_GET_ETH_SERDES_REG;
3328 mcp->mb[1] = HCS_WRITE_SERDES;
3329 mcp->mb[3] = LSW(addr);
3330 mcp->mb[4] = MSW(addr);
3331 mcp->mb[5] = LSW(data);
3332 mcp->mb[6] = MSW(data);
3333 mcp->out_mb = MBX_6|MBX_5|MBX_4|MBX_3|MBX_1|MBX_0;
3334 mcp->in_mb = MBX_0;
3335 mcp->tov = MBX_TOV_SECONDS;
3336 mcp->flags = 0;
3337 rval = qla2x00_mailbox_command(vha, mcp);
3338
3339 if (rval != QLA_SUCCESS) {
83548fe2 3340 ql_dbg(ql_dbg_mbx, vha, 0x11a1,
e8887c51
JC		 3341 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
3342 } else {
3343 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1188,
3344 "Done %s.\n", __func__);
3345 }
3346
3347 return rval;
3348}
3349
3350int
3351qla8044_read_serdes_word(scsi_qla_host_t *vha, uint32_t addr, uint32_t *data)
3352{
3353 int rval;
3354 mbx_cmd_t mc;
3355 mbx_cmd_t *mcp = &mc;
3356
3357 if (!IS_QLA8044(vha->hw))
3358 return QLA_FUNCTION_FAILED;
3359
3360 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1189,
3361 "Entered %s.\n", __func__);
3362
3363 mcp->mb[0] = MBC_SET_GET_ETH_SERDES_REG;
3364 mcp->mb[1] = HCS_READ_SERDES;
3365 mcp->mb[3] = LSW(addr);
3366 mcp->mb[4] = MSW(addr);
3367 mcp->out_mb = MBX_4|MBX_3|MBX_1|MBX_0;
3368 mcp->in_mb = MBX_2|MBX_1|MBX_0;
3369 mcp->tov = MBX_TOV_SECONDS;
3370 mcp->flags = 0;
3371 rval = qla2x00_mailbox_command(vha, mcp);
3372
3373 *data = mcp->mb[2] << 16 | mcp->mb[1];
3374
3375 if (rval != QLA_SUCCESS) {
3376 ql_dbg(ql_dbg_mbx, vha, 0x118a,
3377 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
3378 } else {
3379 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x118b,
3380 "Done %s.\n", __func__);
3381 }
3382
3383 return rval;
3384}
3385
1c7c6357
AV		 3386/**
3387 * qla2x00_set_serdes_params() -
3388 * @ha: HA context
3389 *
3390 * Returns
3391 */
3392int
7b867cf7 3393qla2x00_set_serdes_params(scsi_qla_host_t *vha, uint16_t sw_em_1g,
1c7c6357
AV		 3394 uint16_t sw_em_2g, uint16_t sw_em_4g)
3395{
3396 int rval;
3397 mbx_cmd_t mc;
3398 mbx_cmd_t *mcp = &mc;
3399
5f28d2d7
SK		 3400 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x109e,
3401 "Entered %s.\n", __func__);
1c7c6357
AV		 3402
3403 mcp->mb[0] = MBC_SERDES_PARAMS;
3404 mcp->mb[1] = BIT_0;
fdbc6833 3405 mcp->mb[2] = sw_em_1g | BIT_15;
3406 mcp->mb[3] = sw_em_2g | BIT_15;
3407 mcp->mb[4] = sw_em_4g | BIT_15;
1c7c6357
AV		 3408 mcp->out_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
3409 mcp->in_mb = MBX_0;
b93480e3 3410 mcp->tov = MBX_TOV_SECONDS;
1c7c6357 3411 mcp->flags = 0;
7b867cf7 3412 rval = qla2x00_mailbox_command(vha, mcp);
1c7c6357
AV		 3413
3414 if (rval != QLA_SUCCESS) {
3415 /*EMPTY*/
7c3df132
SK		 3416 ql_dbg(ql_dbg_mbx, vha, 0x109f,
3417 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
1c7c6357
AV		 3418 } else {
3419 /*EMPTY*/
5f28d2d7
SK		 3420 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a0,
3421 "Done %s.\n", __func__);
1c7c6357
AV		 3422 }
3423
3424 return rval;
3425}
f6ef3b18
AV		 3426
3427int
7b867cf7 3428qla2x00_stop_firmware(scsi_qla_host_t *vha)
f6ef3b18
AV		 3429{
3430 int rval;
3431 mbx_cmd_t mc;
3432 mbx_cmd_t *mcp = &mc;
3433
7b867cf7 3434 if (!IS_FWI2_CAPABLE(vha->hw))
f6ef3b18
AV		 3435 return QLA_FUNCTION_FAILED;
3436
5f28d2d7
SK		 3437 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a1,
3438 "Entered %s.\n", __func__);
f6ef3b18
AV		 3439
3440 mcp->mb[0] = MBC_STOP_FIRMWARE;
4ba988db
AV		 3441 mcp->mb[1] = 0;
3442 mcp->out_mb = MBX_1|MBX_0;
f6ef3b18
AV		 3443 mcp->in_mb = MBX_0;
3444 mcp->tov = 5;
3445 mcp->flags = 0;
7b867cf7 3446 rval = qla2x00_mailbox_command(vha, mcp);
f6ef3b18
AV		 3447
3448 if (rval != QLA_SUCCESS) {
7c3df132 3449 ql_dbg(ql_dbg_mbx, vha, 0x10a2, "Failed=%x.\n", rval);
b469a7cb
AV		 3450 if (mcp->mb[0] == MBS_INVALID_COMMAND)
3451 rval = QLA_INVALID_COMMAND;
f6ef3b18 3452 } else {
5f28d2d7
SK		 3453 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a3,
3454 "Done %s.\n", __func__);
f6ef3b18
AV		 3455 }
3456
3457 return rval;
3458}
a7a167bf
AV		 3459
3460int
7b867cf7 3461qla2x00_enable_eft_trace(scsi_qla_host_t *vha, dma_addr_t eft_dma,
a7a167bf
AV		 3462 uint16_t buffers)
3463{
3464 int rval;
3465 mbx_cmd_t mc;
3466 mbx_cmd_t *mcp = &mc;
3467
5f28d2d7
SK		 3468 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a4,
3469 "Entered %s.\n", __func__);
7c3df132 3470
7b867cf7 3471 if (!IS_FWI2_CAPABLE(vha->hw))
a7a167bf
AV		 3472 return QLA_FUNCTION_FAILED;
3473
85880801
AV		 3474 if (unlikely(pci_channel_offline(vha->hw->pdev)))
3475 return QLA_FUNCTION_FAILED;
3476
a7a167bf 3477 mcp->mb[0] = MBC_TRACE_CONTROL;
00b6bd25
AV		 3478 mcp->mb[1] = TC_EFT_ENABLE;
3479 mcp->mb[2] = LSW(eft_dma);
3480 mcp->mb[3] = MSW(eft_dma);
3481 mcp->mb[4] = LSW(MSD(eft_dma));
3482 mcp->mb[5] = MSW(MSD(eft_dma));
3483 mcp->mb[6] = buffers;
3484 mcp->mb[7] = TC_AEN_DISABLE;
3485 mcp->out_mb = MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
a7a167bf 3486 mcp->in_mb = MBX_1|MBX_0;
b93480e3 3487 mcp->tov = MBX_TOV_SECONDS;
a7a167bf 3488 mcp->flags = 0;
7b867cf7 3489 rval = qla2x00_mailbox_command(vha, mcp);
00b6bd25 3490 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3491 ql_dbg(ql_dbg_mbx, vha, 0x10a5,
3492 "Failed=%x mb[0]=%x mb[1]=%x.\n",
3493 rval, mcp->mb[0], mcp->mb[1]);
00b6bd25 3494 } else {
5f28d2d7
SK		 3495 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a6,
3496 "Done %s.\n", __func__);
00b6bd25
AV		 3497 }
3498
3499 return rval;
3500}
a7a167bf 3501
00b6bd25 3502int
7b867cf7 3503qla2x00_disable_eft_trace(scsi_qla_host_t *vha)
00b6bd25
AV		 3504{
3505 int rval;
3506 mbx_cmd_t mc;
3507 mbx_cmd_t *mcp = &mc;
3508
5f28d2d7
SK		 3509 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a7,
3510 "Entered %s.\n", __func__);
7c3df132 3511
7b867cf7 3512 if (!IS_FWI2_CAPABLE(vha->hw))
00b6bd25
AV		 3513 return QLA_FUNCTION_FAILED;
3514
85880801
AV		 3515 if (unlikely(pci_channel_offline(vha->hw->pdev)))
3516 return QLA_FUNCTION_FAILED;
3517
00b6bd25
AV		 3518 mcp->mb[0] = MBC_TRACE_CONTROL;
3519 mcp->mb[1] = TC_EFT_DISABLE;
3520 mcp->out_mb = MBX_1|MBX_0;
3521 mcp->in_mb = MBX_1|MBX_0;
b93480e3 3522 mcp->tov = MBX_TOV_SECONDS;
00b6bd25 3523 mcp->flags = 0;
7b867cf7 3524 rval = qla2x00_mailbox_command(vha, mcp);
a7a167bf 3525 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3526 ql_dbg(ql_dbg_mbx, vha, 0x10a8,
3527 "Failed=%x mb[0]=%x mb[1]=%x.\n",
3528 rval, mcp->mb[0], mcp->mb[1]);
a7a167bf 3529 } else {
5f28d2d7
SK		 3530 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a9,
3531 "Done %s.\n", __func__);
a7a167bf
AV		 3532 }
3533
3534 return rval;
3535}
3536
df613b96 3537int
7b867cf7 3538qla2x00_enable_fce_trace(scsi_qla_host_t *vha, dma_addr_t fce_dma,
df613b96
AV		 3539 uint16_t buffers, uint16_t *mb, uint32_t *dwords)
3540{
3541 int rval;
3542 mbx_cmd_t mc;
3543 mbx_cmd_t *mcp = &mc;
3544
5f28d2d7
SK		 3545 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10aa,
3546 "Entered %s.\n", __func__);
7c3df132 3547
6246b8a1 3548 if (!IS_QLA25XX(vha->hw) && !IS_QLA81XX(vha->hw) &&
f73cb695 3549 !IS_QLA83XX(vha->hw) && !IS_QLA27XX(vha->hw))
df613b96
AV		 3550 return QLA_FUNCTION_FAILED;
3551
85880801
AV		 3552 if (unlikely(pci_channel_offline(vha->hw->pdev)))
3553 return QLA_FUNCTION_FAILED;
3554
df613b96
AV		 3555 mcp->mb[0] = MBC_TRACE_CONTROL;
3556 mcp->mb[1] = TC_FCE_ENABLE;
3557 mcp->mb[2] = LSW(fce_dma);
3558 mcp->mb[3] = MSW(fce_dma);
3559 mcp->mb[4] = LSW(MSD(fce_dma));
3560 mcp->mb[5] = MSW(MSD(fce_dma));
3561 mcp->mb[6] = buffers;
3562 mcp->mb[7] = TC_AEN_DISABLE;
3563 mcp->mb[8] = 0;
3564 mcp->mb[9] = TC_FCE_DEFAULT_RX_SIZE;
3565 mcp->mb[10] = TC_FCE_DEFAULT_TX_SIZE;
3566 mcp->out_mb = MBX_10|MBX_9|MBX_8|MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|
3567 MBX_1|MBX_0;
3568 mcp->in_mb = MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
b93480e3 3569 mcp->tov = MBX_TOV_SECONDS;
df613b96 3570 mcp->flags = 0;
7b867cf7 3571 rval = qla2x00_mailbox_command(vha, mcp);
df613b96 3572 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3573 ql_dbg(ql_dbg_mbx, vha, 0x10ab,
3574 "Failed=%x mb[0]=%x mb[1]=%x.\n",
3575 rval, mcp->mb[0], mcp->mb[1]);
df613b96 3576 } else {
5f28d2d7
SK		 3577 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ac,
3578 "Done %s.\n", __func__);
df613b96
AV		 3579
3580 if (mb)
3581 memcpy(mb, mcp->mb, 8 * sizeof(*mb));
3582 if (dwords)
fa0926df 3583 *dwords = buffers;
df613b96
AV		 3584 }
3585
3586 return rval;
3587}
3588
3589int
7b867cf7 3590qla2x00_disable_fce_trace(scsi_qla_host_t *vha, uint64_t *wr, uint64_t *rd)
df613b96
AV		 3591{
3592 int rval;
3593 mbx_cmd_t mc;
3594 mbx_cmd_t *mcp = &mc;
3595
5f28d2d7
SK		 3596 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ad,
3597 "Entered %s.\n", __func__);
7c3df132 3598
7b867cf7 3599 if (!IS_FWI2_CAPABLE(vha->hw))
df613b96
AV		 3600 return QLA_FUNCTION_FAILED;
3601
85880801
AV		 3602 if (unlikely(pci_channel_offline(vha->hw->pdev)))
3603 return QLA_FUNCTION_FAILED;
3604
df613b96
AV		 3605 mcp->mb[0] = MBC_TRACE_CONTROL;
3606 mcp->mb[1] = TC_FCE_DISABLE;
3607 mcp->mb[2] = TC_FCE_DISABLE_TRACE;
3608 mcp->out_mb = MBX_2|MBX_1|MBX_0;
3609 mcp->in_mb = MBX_9|MBX_8|MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|
3610 MBX_1|MBX_0;
b93480e3 3611 mcp->tov = MBX_TOV_SECONDS;
df613b96 3612 mcp->flags = 0;
7b867cf7 3613 rval = qla2x00_mailbox_command(vha, mcp);
df613b96 3614 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3615 ql_dbg(ql_dbg_mbx, vha, 0x10ae,
3616 "Failed=%x mb[0]=%x mb[1]=%x.\n",
3617 rval, mcp->mb[0], mcp->mb[1]);
df613b96 3618 } else {
5f28d2d7
SK		 3619 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10af,
3620 "Done %s.\n", __func__);
df613b96
AV		 3621
3622 if (wr)
3623 *wr = (uint64_t) mcp->mb[5] << 48 |
3624 (uint64_t) mcp->mb[4] << 32 |
3625 (uint64_t) mcp->mb[3] << 16 |
3626 (uint64_t) mcp->mb[2];
3627 if (rd)
3628 *rd = (uint64_t) mcp->mb[9] << 48 |
3629 (uint64_t) mcp->mb[8] << 32 |
3630 (uint64_t) mcp->mb[7] << 16 |
3631 (uint64_t) mcp->mb[6];
3632 }
3633
3634 return rval;
3635}
3636
6e98016c
GM		 3637int
3638qla2x00_get_idma_speed(scsi_qla_host_t *vha, uint16_t loop_id,
3639 uint16_t *port_speed, uint16_t *mb)
3640{
3641 int rval;
3642 mbx_cmd_t mc;
3643 mbx_cmd_t *mcp = &mc;
3644
5f28d2d7
SK		 3645 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b0,
3646 "Entered %s.\n", __func__);
7c3df132 3647
6e98016c
GM		 3648 if (!IS_IIDMA_CAPABLE(vha->hw))
3649 return QLA_FUNCTION_FAILED;
3650
6e98016c
GM		 3651 mcp->mb[0] = MBC_PORT_PARAMS;
3652 mcp->mb[1] = loop_id;
3653 mcp->mb[2] = mcp->mb[3] = 0;
3654 mcp->mb[9] = vha->vp_idx;
3655 mcp->out_mb = MBX_9|MBX_3|MBX_2|MBX_1|MBX_0;
3656 mcp->in_mb = MBX_3|MBX_1|MBX_0;
3657 mcp->tov = MBX_TOV_SECONDS;
3658 mcp->flags = 0;
3659 rval = qla2x00_mailbox_command(vha, mcp);
3660
3661 /* Return mailbox statuses. */
3662 if (mb != NULL) {
3663 mb[0] = mcp->mb[0];
3664 mb[1] = mcp->mb[1];
3665 mb[3] = mcp->mb[3];
3666 }
3667
3668 if (rval != QLA_SUCCESS) {
7c3df132 3669 ql_dbg(ql_dbg_mbx, vha, 0x10b1, "Failed=%x.\n", rval);
6e98016c 3670 } else {
5f28d2d7
SK		 3671 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b2,
3672 "Done %s.\n", __func__);
6e98016c
GM		 3673 if (port_speed)
3674 *port_speed = mcp->mb[3];
3675 }
3676
3677 return rval;
3678}
3679
d8b45213 3680int
7b867cf7 3681qla2x00_set_idma_speed(scsi_qla_host_t *vha, uint16_t loop_id,
d8b45213
AV		 3682 uint16_t port_speed, uint16_t *mb)
3683{
3684 int rval;
3685 mbx_cmd_t mc;
3686 mbx_cmd_t *mcp = &mc;
3687
5f28d2d7
SK		 3688 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b3,
3689 "Entered %s.\n", __func__);
7c3df132 3690
7b867cf7 3691 if (!IS_IIDMA_CAPABLE(vha->hw))
d8b45213
AV		 3692 return QLA_FUNCTION_FAILED;
3693
d8b45213
AV		 3694 mcp->mb[0] = MBC_PORT_PARAMS;
3695 mcp->mb[1] = loop_id;
3696 mcp->mb[2] = BIT_0;
6246b8a1 3697 if (IS_CNA_CAPABLE(vha->hw))
1bb39548
HZ		 3698 mcp->mb[3] = port_speed & (BIT_5|BIT_4|BIT_3|BIT_2|BIT_1|BIT_0);
3699 else
3700 mcp->mb[3] = port_speed & (BIT_2|BIT_1|BIT_0);
3701 mcp->mb[9] = vha->vp_idx;
3702 mcp->out_mb = MBX_9|MBX_3|MBX_2|MBX_1|MBX_0;
3703 mcp->in_mb = MBX_3|MBX_1|MBX_0;
b93480e3 3704 mcp->tov = MBX_TOV_SECONDS;
d8b45213 3705 mcp->flags = 0;
7b867cf7 3706 rval = qla2x00_mailbox_command(vha, mcp);
d8b45213
AV		 3707
3708 /* Return mailbox statuses. */
3709 if (mb != NULL) {
3710 mb[0] = mcp->mb[0];
3711 mb[1] = mcp->mb[1];
3712 mb[3] = mcp->mb[3];
d8b45213
AV		 3713 }
3714
3715 if (rval != QLA_SUCCESS) {
5f28d2d7
SK		 3716 ql_dbg(ql_dbg_mbx, vha, 0x10b4,
3717 "Failed=%x.\n", rval);
d8b45213 3718 } else {
5f28d2d7
SK		 3719 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b5,
3720 "Done %s.\n", __func__);
d8b45213
AV		 3721 }
3722
3723 return rval;
3724}
2c3dfe3f 3725
2c3dfe3f 3726void
7b867cf7 3727qla24xx_report_id_acquisition(scsi_qla_host_t *vha,
2c3dfe3f
SJ		 3728 struct vp_rpt_id_entry_24xx *rptid_entry)
3729{
7b867cf7 3730 struct qla_hw_data *ha = vha->hw;
41dc529a 3731 scsi_qla_host_t *vp = NULL;
feafb7b1 3732 unsigned long flags;
4ac8d4ca 3733 int found;
482c9dc7 3734 port_id_t id;
2c3dfe3f 3735
5f28d2d7
SK		 3736 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b6,
3737 "Entered %s.\n", __func__);
7c3df132 3738
2c3dfe3f
SJ		 3739 if (rptid_entry->entry_status != 0)
3740 return;
2c3dfe3f 3741
482c9dc7
QT		 3742 id.b.domain = rptid_entry->port_id[2];
3743 id.b.area = rptid_entry->port_id[1];
3744 id.b.al_pa = rptid_entry->port_id[0];
3745 id.b.rsvd_1 = 0;
3746
2c3dfe3f 3747 if (rptid_entry->format == 0) {
41dc529a 3748 /* loop */
ec7193e2 3749 ql_dbg(ql_dbg_async, vha, 0x10b7,
7c3df132 3750 "Format 0 : Number of VPs setup %d, number of "
41dc529a
QT		 3751 "VPs acquired %d.\n", rptid_entry->vp_setup,
3752 rptid_entry->vp_acquired);
ec7193e2 3753 ql_dbg(ql_dbg_async, vha, 0x10b8,
7c3df132
SK		 3754 "Primary port id %02x%02x%02x.\n",
3755 rptid_entry->port_id[2], rptid_entry->port_id[1],
3756 rptid_entry->port_id[0]);
41dc529a 3757
482c9dc7 3758 qlt_update_host_map(vha, id);
41dc529a 3759
2c3dfe3f 3760 } else if (rptid_entry->format == 1) {
41dc529a 3761 /* fabric */
ec7193e2 3762 ql_dbg(ql_dbg_async, vha, 0x10b9,
7c3df132 3763 "Format 1: VP[%d] enabled - status %d - with "
41dc529a
QT		 3764 "port id %02x%02x%02x.\n", rptid_entry->vp_idx,
3765 rptid_entry->vp_status,
2c3dfe3f 3766 rptid_entry->port_id[2], rptid_entry->port_id[1],
7c3df132 3767 rptid_entry->port_id[0]);
edd05de1
DG		 3768 ql_dbg(ql_dbg_async, vha, 0x5075,
3769 "Format 1: Remote WWPN %8phC.\n",
3770 rptid_entry->u.f1.port_name);
3771
3772 ql_dbg(ql_dbg_async, vha, 0x5075,
3773 "Format 1: WWPN %8phC.\n",
3774 vha->port_name);
3775
3776 /* N2N. direct connect */
3777 if (IS_QLA27XX(ha) &&
3778 ((rptid_entry->u.f1.flags>>1) & 0x7) == 2) {
3779 /* if our portname is higher then initiate N2N login */
3780 if (wwn_to_u64(vha->port_name) >
3781 wwn_to_u64(rptid_entry->u.f1.port_name)) {
3782 // ??? qlt_update_host_map(vha, id);
3783 vha->n2n_id = 0x1;
3784 ql_dbg(ql_dbg_async, vha, 0x5075,
3785 "Format 1: Setting n2n_update_needed for id %d\n",
3786 vha->n2n_id);
3787 } else {
3788 ql_dbg(ql_dbg_async, vha, 0x5075,
3789 "Format 1: Remote login - Waiting for WWPN %8phC.\n",
3790 rptid_entry->u.f1.port_name);
3791 }
3792
3793 memcpy(vha->n2n_port_name, rptid_entry->u.f1.port_name,
3794 WWN_SIZE);
3795 set_bit(N2N_LOGIN_NEEDED, &vha->dpc_flags);
3796 set_bit(REGISTER_FC4_NEEDED, &vha->dpc_flags);
3797 set_bit(REGISTER_FDMI_NEEDED, &vha->dpc_flags);
3798 return;
3799 }
531a82d1 3800
969a6199 3801 /* buffer to buffer credit flag */
41dc529a
QT		 3802 vha->flags.bbcr_enable = (rptid_entry->u.f1.bbcr & 0xf) != 0;
3803
3804 if (rptid_entry->vp_idx == 0) {
3805 if (rptid_entry->vp_status == VP_STAT_COMPL) {
3806 /* FA-WWN is only for physical port */
3807 if (qla_ini_mode_enabled(vha) &&
3808 ha->flags.fawwpn_enabled &&
3809 (rptid_entry->u.f1.flags &
fcc5b5cd 3810 BIT_6)) {
41dc529a
QT		 3811 memcpy(vha->port_name,
3812 rptid_entry->u.f1.port_name,
3813 WWN_SIZE);
3814 }
7c9c4766 3815
482c9dc7 3816 qlt_update_host_map(vha, id);
7c9c4766 3817 }
41dc529a 3818
41dc529a
QT		 3819 set_bit(REGISTER_FC4_NEEDED, &vha->dpc_flags);
3820 set_bit(REGISTER_FDMI_NEEDED, &vha->dpc_flags);
3821 } else {
3822 if (rptid_entry->vp_status != VP_STAT_COMPL &&
3823 rptid_entry->vp_status != VP_STAT_ID_CHG) {
3824 ql_dbg(ql_dbg_mbx, vha, 0x10ba,
3825 "Could not acquire ID for VP[%d].\n",
3826 rptid_entry->vp_idx);
3827 return;
4ac8d4ca 3828 }
feafb7b1 3829
41dc529a
QT		 3830 found = 0;
3831 spin_lock_irqsave(&ha->vport_slock, flags);
3832 list_for_each_entry(vp, &ha->vp_list, list) {
3833 if (rptid_entry->vp_idx == vp->vp_idx) {
3834 found = 1;
3835 break;
3836 }
3837 }
3838 spin_unlock_irqrestore(&ha->vport_slock, flags);
2c3dfe3f 3839
41dc529a
QT		 3840 if (!found)
3841 return;
2c3dfe3f 3842
482c9dc7 3843 qlt_update_host_map(vp, id);
2c3dfe3f 3844
41dc529a
QT		 3845 /*
3846 * Cannot configure here as we are still sitting on the
3847 * response queue. Handle it in dpc context.
3848 */
3849 set_bit(VP_IDX_ACQUIRED, &vp->vp_flags);
3850 set_bit(REGISTER_FC4_NEEDED, &vp->dpc_flags);
3851 set_bit(REGISTER_FDMI_NEEDED, &vp->dpc_flags);
3852 }
531a82d1 3853 set_bit(VP_DPC_NEEDED, &vha->dpc_flags);
7b867cf7 3854 qla2xxx_wake_dpc(vha);
41dc529a 3855 } else if (rptid_entry->format == 2) {
83548fe2 3856 ql_dbg(ql_dbg_async, vha, 0x505f,
41dc529a
QT		 3857 "RIDA: format 2/N2N Primary port id %02x%02x%02x.\n",
3858 rptid_entry->port_id[2], rptid_entry->port_id[1],
3859 rptid_entry->port_id[0]);
3860
83548fe2 3861 ql_dbg(ql_dbg_async, vha, 0x5075,
41dc529a
QT		 3862 "N2N: Remote WWPN %8phC.\n",
3863 rptid_entry->u.f2.port_name);
3864
3865 /* N2N. direct connect */
3866 vha->d_id.b.domain = rptid_entry->port_id[2];
3867 vha->d_id.b.area = rptid_entry->port_id[1];
3868 vha->d_id.b.al_pa = rptid_entry->port_id[0];
3869
3870 spin_lock_irqsave(&ha->vport_slock, flags);
3871 qlt_update_vp_map(vha, SET_AL_PA);
3872 spin_unlock_irqrestore(&ha->vport_slock, flags);
2c3dfe3f
SJ		 3873 }
3874}
3875
3876/*
3877 * qla24xx_modify_vp_config
3878 * Change VP configuration for vha
3879 *
3880 * Input:
3881 * vha = adapter block pointer.
3882 *
3883 * Returns:
3884 * qla2xxx local function return status code.
3885 *
3886 * Context:
3887 * Kernel context.
3888 */
3889int
3890qla24xx_modify_vp_config(scsi_qla_host_t *vha)
3891{
3892 int rval;
3893 struct vp_config_entry_24xx *vpmod;
3894 dma_addr_t vpmod_dma;
7b867cf7
AC		 3895 struct qla_hw_data *ha = vha->hw;
3896 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
2c3dfe3f
SJ		 3897
3898 /* This can be called by the parent */
2c3dfe3f 3899
5f28d2d7
SK		 3900 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10bb,
3901 "Entered %s.\n", __func__);
7c3df132 3902
08eb7f45 3903 vpmod = dma_pool_zalloc(ha->s_dma_pool, GFP_KERNEL, &vpmod_dma);
2c3dfe3f 3904 if (!vpmod) {
7c3df132
SK		 3905 ql_log(ql_log_warn, vha, 0x10bc,
3906 "Failed to allocate modify VP IOCB.\n");
2c3dfe3f
SJ		 3907 return QLA_MEMORY_ALLOC_FAILED;
3908 }
3909
2c3dfe3f
SJ		 3910 vpmod->entry_type = VP_CONFIG_IOCB_TYPE;
3911 vpmod->entry_count = 1;
3912 vpmod->command = VCT_COMMAND_MOD_ENABLE_VPS;
3913 vpmod->vp_count = 1;
3914 vpmod->vp_index1 = vha->vp_idx;
3915 vpmod->options_idx1 = BIT_3|BIT_4|BIT_5;
2d70c103
NB		 3916
3917 qlt_modify_vp_config(vha, vpmod);
3918
2c3dfe3f
SJ		 3919 memcpy(vpmod->node_name_idx1, vha->node_name, WWN_SIZE);
3920 memcpy(vpmod->port_name_idx1, vha->port_name, WWN_SIZE);
3921 vpmod->entry_count = 1;
3922
7b867cf7 3923 rval = qla2x00_issue_iocb(base_vha, vpmod, vpmod_dma, 0);
2c3dfe3f 3924 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3925 ql_dbg(ql_dbg_mbx, vha, 0x10bd,
3926 "Failed to issue VP config IOCB (%x).\n", rval);
2c3dfe3f 3927 } else if (vpmod->comp_status != 0) {
7c3df132
SK		 3928 ql_dbg(ql_dbg_mbx, vha, 0x10be,
3929 "Failed to complete IOCB -- error status (%x).\n",
3930 vpmod->comp_status);
2c3dfe3f 3931 rval = QLA_FUNCTION_FAILED;
ad950360 3932 } else if (vpmod->comp_status != cpu_to_le16(CS_COMPLETE)) {
7c3df132
SK		 3933 ql_dbg(ql_dbg_mbx, vha, 0x10bf,
3934 "Failed to complete IOCB -- completion status (%x).\n",
3935 le16_to_cpu(vpmod->comp_status));
2c3dfe3f
SJ		 3936 rval = QLA_FUNCTION_FAILED;
3937 } else {
3938 /* EMPTY */
5f28d2d7
SK		 3939 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10c0,
3940 "Done %s.\n", __func__);
2c3dfe3f
SJ		 3941 fc_vport_set_state(vha->fc_vport, FC_VPORT_INITIALIZING);
3942 }
7b867cf7 3943 dma_pool_free(ha->s_dma_pool, vpmod, vpmod_dma);
2c3dfe3f
SJ		 3944
3945 return rval;
3946}
3947
2c3dfe3f
SJ		 3948/*
3949 * qla2x00_send_change_request
3950 * Receive or disable RSCN request from fabric controller
3951 *
3952 * Input:
3953 * ha = adapter block pointer
3954 * format = registration format:
3955 * 0 - Reserved
3956 * 1 - Fabric detected registration
3957 * 2 - N_port detected registration
3958 * 3 - Full registration
3959 * FF - clear registration
3960 * vp_idx = Virtual port index
3961 *
3962 * Returns:
3963 * qla2x00 local function return status code.
3964 *
3965 * Context:
3966 * Kernel Context
3967 */
3968
3969int
7b867cf7 3970qla2x00_send_change_request(scsi_qla_host_t *vha, uint16_t format,
2c3dfe3f
SJ		 3971 uint16_t vp_idx)
3972{
3973 int rval;
3974 mbx_cmd_t mc;
3975 mbx_cmd_t *mcp = &mc;
3976
5f28d2d7
SK		 3977 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10c7,
3978 "Entered %s.\n", __func__);
7c3df132 3979
2c3dfe3f
SJ		 3980 mcp->mb[0] = MBC_SEND_CHANGE_REQUEST;
3981 mcp->mb[1] = format;
3982 mcp->mb[9] = vp_idx;
3983 mcp->out_mb = MBX_9|MBX_1|MBX_0;
3984 mcp->in_mb = MBX_0|MBX_1;
3985 mcp->tov = MBX_TOV_SECONDS;
3986 mcp->flags = 0;
7b867cf7 3987 rval = qla2x00_mailbox_command(vha, mcp);
2c3dfe3f
SJ		 3988
3989 if (rval == QLA_SUCCESS) {
3990 if (mcp->mb[0] != MBS_COMMAND_COMPLETE) {
3991 rval = BIT_1;
3992 }
3993 } else
3994 rval = BIT_1;
3995
3996 return rval;
3997}
338c9161
AV		 3998
3999int
7b867cf7 4000qla2x00_dump_ram(scsi_qla_host_t *vha, dma_addr_t req_dma, uint32_t addr,
338c9161
AV		 4001 uint32_t size)
4002{
4003 int rval;
4004 mbx_cmd_t mc;
4005 mbx_cmd_t *mcp = &mc;
4006
5f28d2d7
SK		 4007 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1009,
4008 "Entered %s.\n", __func__);
338c9161 4009
7b867cf7 4010 if (MSW(addr) || IS_FWI2_CAPABLE(vha->hw)) {
338c9161
AV		 4011 mcp->mb[0] = MBC_DUMP_RISC_RAM_EXTENDED;
4012 mcp->mb[8] = MSW(addr);
4013 mcp->out_mb = MBX_8|MBX_0;
4014 } else {
4015 mcp->mb[0] = MBC_DUMP_RISC_RAM;
4016 mcp->out_mb = MBX_0;
4017 }
4018 mcp->mb[1] = LSW(addr);
4019 mcp->mb[2] = MSW(req_dma);
4020 mcp->mb[3] = LSW(req_dma);
4021 mcp->mb[6] = MSW(MSD(req_dma));
4022 mcp->mb[7] = LSW(MSD(req_dma));
4023 mcp->out_mb |= MBX_7|MBX_6|MBX_3|MBX_2|MBX_1;
7b867cf7 4024 if (IS_FWI2_CAPABLE(vha->hw)) {
338c9161
AV		 4025 mcp->mb[4] = MSW(size);
4026 mcp->mb[5] = LSW(size);
4027 mcp->out_mb |= MBX_5|MBX_4;
4028 } else {
4029 mcp->mb[4] = LSW(size);
4030 mcp->out_mb |= MBX_4;
4031 }
4032
4033 mcp->in_mb = MBX_0;
b93480e3 4034 mcp->tov = MBX_TOV_SECONDS;
338c9161 4035 mcp->flags = 0;
7b867cf7 4036 rval = qla2x00_mailbox_command(vha, mcp);
338c9161
AV		 4037
4038 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4039 ql_dbg(ql_dbg_mbx, vha, 0x1008,
4040 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
338c9161 4041 } else {
5f28d2d7
SK		 4042 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1007,
4043 "Done %s.\n", __func__);
338c9161
AV		 4044 }
4045
4046 return rval;
4047}
4d4df193
HK		 4048/* 84XX Support **************************************************************/
4049
4050struct cs84xx_mgmt_cmd {
4051 union {
4052 struct verify_chip_entry_84xx req;
4053 struct verify_chip_rsp_84xx rsp;
4054 } p;
4055};
4056
4057int
7b867cf7 4058qla84xx_verify_chip(struct scsi_qla_host *vha, uint16_t *status)
4d4df193
HK		 4059{
4060 int rval, retry;
4061 struct cs84xx_mgmt_cmd *mn;
4062 dma_addr_t mn_dma;
4063 uint16_t options;
4064 unsigned long flags;
7b867cf7 4065 struct qla_hw_data *ha = vha->hw;
4d4df193 4066
5f28d2d7
SK		 4067 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10c8,
4068 "Entered %s.\n", __func__);
4d4df193
HK		 4069
4070 mn = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &mn_dma);
4071 if (mn == NULL) {
4d4df193
HK		 4072 return QLA_MEMORY_ALLOC_FAILED;
4073 }
4074
4075 /* Force Update? */
4076 options = ha->cs84xx->fw_update ? VCO_FORCE_UPDATE : 0;
4077 /* Diagnostic firmware? */
4078 /* options |= MENLO_DIAG_FW; */
4079 /* We update the firmware with only one data sequence. */
4080 options |= VCO_END_OF_DATA;
4081
4d4df193 4082 do {
c1ec1f1b 4083 retry = 0;
4d4df193
HK		 4084 memset(mn, 0, sizeof(*mn));
4085 mn->p.req.entry_type = VERIFY_CHIP_IOCB_TYPE;
4086 mn->p.req.entry_count = 1;
4087 mn->p.req.options = cpu_to_le16(options);
4088
7c3df132
SK		 4089 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x111c,
4090 "Dump of Verify Request.\n");
4091 ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x111e,
4092 (uint8_t *)mn, sizeof(*mn));
4d4df193 4093
7b867cf7 4094 rval = qla2x00_issue_iocb_timeout(vha, mn, mn_dma, 0, 120);
4d4df193 4095 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4096 ql_dbg(ql_dbg_mbx, vha, 0x10cb,
4097 "Failed to issue verify IOCB (%x).\n", rval);
4d4df193
HK		 4098 goto verify_done;
4099 }
4100
7c3df132
SK		 4101 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1110,
4102 "Dump of Verify Response.\n");
4103 ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1118,
4104 (uint8_t *)mn, sizeof(*mn));
4d4df193
HK		 4105
4106 status[0] = le16_to_cpu(mn->p.rsp.comp_status);
4107 status[1] = status[0] == CS_VCS_CHIP_FAILURE ?
4108 le16_to_cpu(mn->p.rsp.failure_code) : 0;
5f28d2d7 4109 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ce,
7c3df132 4110 "cs=%x fc=%x.\n", status[0], status[1]);
4d4df193
HK		 4111
4112 if (status[0] != CS_COMPLETE) {
4113 rval = QLA_FUNCTION_FAILED;
4114 if (!(options & VCO_DONT_UPDATE_FW)) {
7c3df132
SK		 4115 ql_dbg(ql_dbg_mbx, vha, 0x10cf,
4116 "Firmware update failed. Retrying "
4117 "without update firmware.\n");
4d4df193
HK		 4118 options |= VCO_DONT_UPDATE_FW;
4119 options &= ~VCO_FORCE_UPDATE;
4120 retry = 1;
4121 }
4122 } else {
5f28d2d7 4123 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d0,
7c3df132
SK		 4124 "Firmware updated to %x.\n",
4125 le32_to_cpu(mn->p.rsp.fw_ver));
4d4df193
HK		 4126
4127 /* NOTE: we only update OP firmware. */
4128 spin_lock_irqsave(&ha->cs84xx->access_lock, flags);
4129 ha->cs84xx->op_fw_version =
4130 le32_to_cpu(mn->p.rsp.fw_ver);
4131 spin_unlock_irqrestore(&ha->cs84xx->access_lock,
4132 flags);
4133 }
4134 } while (retry);
4135
4136verify_done:
4137 dma_pool_free(ha->s_dma_pool, mn, mn_dma);
4138
4139 if (rval != QLA_SUCCESS) {
5f28d2d7
SK		 4140 ql_dbg(ql_dbg_mbx, vha, 0x10d1,
4141 "Failed=%x.\n", rval);
4d4df193 4142 } else {
5f28d2d7
SK		 4143 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d2,
4144 "Done %s.\n", __func__);
4d4df193
HK		 4145 }
4146
4147 return rval;
4148}
73208dfd
AC		 4149
4150int
618a7523 4151qla25xx_init_req_que(struct scsi_qla_host *vha, struct req_que *req)
73208dfd
AC		 4152{
4153 int rval;
4154 unsigned long flags;
4155 mbx_cmd_t mc;
4156 mbx_cmd_t *mcp = &mc;
73208dfd
AC		 4157 struct qla_hw_data *ha = vha->hw;
4158
5f28d2d7
SK		 4159 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d3,
4160 "Entered %s.\n", __func__);
7c3df132 4161
7c6300e3
JC		 4162 if (IS_SHADOW_REG_CAPABLE(ha))
4163 req->options |= BIT_13;
4164
73208dfd 4165 mcp->mb[0] = MBC_INITIALIZE_MULTIQ;
618a7523 4166 mcp->mb[1] = req->options;
73208dfd
AC		 4167 mcp->mb[2] = MSW(LSD(req->dma));
4168 mcp->mb[3] = LSW(LSD(req->dma));
4169 mcp->mb[6] = MSW(MSD(req->dma));
4170 mcp->mb[7] = LSW(MSD(req->dma));
4171 mcp->mb[5] = req->length;
4172 if (req->rsp)
4173 mcp->mb[10] = req->rsp->id;
4174 mcp->mb[12] = req->qos;
4175 mcp->mb[11] = req->vp_idx;
4176 mcp->mb[13] = req->rid;
f73cb695 4177 if (IS_QLA83XX(ha) || IS_QLA27XX(ha))
6246b8a1 4178 mcp->mb[15] = 0;
73208dfd 4179
73208dfd
AC		 4180 mcp->mb[4] = req->id;
4181 /* que in ptr index */
4182 mcp->mb[8] = 0;
4183 /* que out ptr index */
7c6300e3 4184 mcp->mb[9] = *req->out_ptr = 0;
73208dfd
AC		 4185 mcp->out_mb = MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8|MBX_7|
4186 MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
4187 mcp->in_mb = MBX_0;
4188 mcp->flags = MBX_DMA_OUT;
6246b8a1
GM		 4189 mcp->tov = MBX_TOV_SECONDS * 2;
4190
f73cb695 4191 if (IS_QLA81XX(ha) || IS_QLA83XX(ha) || IS_QLA27XX(ha))
6246b8a1 4192 mcp->in_mb |= MBX_1;
ba4828b7 4193 if (IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
6246b8a1
GM		 4194 mcp->out_mb |= MBX_15;
4195 /* debug q create issue in SR-IOV */
4196 mcp->in_mb |= MBX_9 | MBX_8 | MBX_7;
4197 }
73208dfd
AC		 4198
4199 spin_lock_irqsave(&ha->hardware_lock, flags);
618a7523 4200 if (!(req->options & BIT_0)) {
da9b1d5c 4201 WRT_REG_DWORD(req->req_q_in, 0);
29db41c3 4202 if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha))
da9b1d5c 4203 WRT_REG_DWORD(req->req_q_out, 0);
73208dfd
AC		 4204 }
4205 spin_unlock_irqrestore(&ha->hardware_lock, flags);
4206
17d98630 4207 rval = qla2x00_mailbox_command(vha, mcp);
7c3df132
SK		 4208 if (rval != QLA_SUCCESS) {
4209 ql_dbg(ql_dbg_mbx, vha, 0x10d4,
4210 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
4211 } else {
5f28d2d7
SK		 4212 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d5,
4213 "Done %s.\n", __func__);
7c3df132
SK		 4214 }
4215
73208dfd
AC		 4216 return rval;
4217}
4218
4219int
618a7523 4220qla25xx_init_rsp_que(struct scsi_qla_host *vha, struct rsp_que *rsp)
73208dfd
AC		 4221{
4222 int rval;
4223 unsigned long flags;
4224 mbx_cmd_t mc;
4225 mbx_cmd_t *mcp = &mc;
73208dfd
AC		 4226 struct qla_hw_data *ha = vha->hw;
4227
5f28d2d7
SK		 4228 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d6,
4229 "Entered %s.\n", __func__);
7c3df132 4230
7c6300e3
JC		 4231 if (IS_SHADOW_REG_CAPABLE(ha))
4232 rsp->options |= BIT_13;
4233
73208dfd 4234 mcp->mb[0] = MBC_INITIALIZE_MULTIQ;
618a7523 4235 mcp->mb[1] = rsp->options;
73208dfd
AC		 4236 mcp->mb[2] = MSW(LSD(rsp->dma));
4237 mcp->mb[3] = LSW(LSD(rsp->dma));
4238 mcp->mb[6] = MSW(MSD(rsp->dma));
4239 mcp->mb[7] = LSW(MSD(rsp->dma));
4240 mcp->mb[5] = rsp->length;
444786d7 4241 mcp->mb[14] = rsp->msix->entry;
73208dfd 4242 mcp->mb[13] = rsp->rid;
f73cb695 4243 if (IS_QLA83XX(ha) || IS_QLA27XX(ha))
6246b8a1 4244 mcp->mb[15] = 0;
73208dfd 4245
73208dfd
AC		 4246 mcp->mb[4] = rsp->id;
4247 /* que in ptr index */
7c6300e3 4248 mcp->mb[8] = *rsp->in_ptr = 0;
73208dfd
AC		 4249 /* que out ptr index */
4250 mcp->mb[9] = 0;
2afa19a9 4251 mcp->out_mb = MBX_14|MBX_13|MBX_9|MBX_8|MBX_7
73208dfd
AC		 4252 |MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
4253 mcp->in_mb = MBX_0;
4254 mcp->flags = MBX_DMA_OUT;
6246b8a1
GM		 4255 mcp->tov = MBX_TOV_SECONDS * 2;
4256
4257 if (IS_QLA81XX(ha)) {
4258 mcp->out_mb |= MBX_12|MBX_11|MBX_10;
4259 mcp->in_mb |= MBX_1;
f73cb695 4260 } else if (IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
6246b8a1
GM		 4261 mcp->out_mb |= MBX_15|MBX_12|MBX_11|MBX_10;
4262 mcp->in_mb |= MBX_1;
4263 /* debug q create issue in SR-IOV */
4264 mcp->in_mb |= MBX_9 | MBX_8 | MBX_7;
4265 }
73208dfd
AC		 4266
4267 spin_lock_irqsave(&ha->hardware_lock, flags);
618a7523 4268 if (!(rsp->options & BIT_0)) {
da9b1d5c 4269 WRT_REG_DWORD(rsp->rsp_q_out, 0);
b20f02e1 4270 if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha))
da9b1d5c 4271 WRT_REG_DWORD(rsp->rsp_q_in, 0);
73208dfd
AC		 4272 }
4273
4274 spin_unlock_irqrestore(&ha->hardware_lock, flags);
4275
17d98630 4276 rval = qla2x00_mailbox_command(vha, mcp);
7c3df132
SK		 4277 if (rval != QLA_SUCCESS) {
4278 ql_dbg(ql_dbg_mbx, vha, 0x10d7,
4279 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
4280 } else {
5f28d2d7
SK		 4281 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d8,
4282 "Done %s.\n", __func__);
7c3df132
SK		 4283 }
4284
73208dfd
AC		 4285 return rval;
4286}
4287
8a659571
AV		 4288int
4289qla81xx_idc_ack(scsi_qla_host_t *vha, uint16_t *mb)
4290{
4291 int rval;
4292 mbx_cmd_t mc;
4293 mbx_cmd_t *mcp = &mc;
4294
5f28d2d7
SK		 4295 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d9,
4296 "Entered %s.\n", __func__);
8a659571
AV		 4297
4298 mcp->mb[0] = MBC_IDC_ACK;
4299 memcpy(&mcp->mb[1], mb, QLA_IDC_ACK_REGS * sizeof(uint16_t));
4300 mcp->out_mb = MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
4301 mcp->in_mb = MBX_0;
4302 mcp->tov = MBX_TOV_SECONDS;
4303 mcp->flags = 0;
4304 rval = qla2x00_mailbox_command(vha, mcp);
4305
4306 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4307 ql_dbg(ql_dbg_mbx, vha, 0x10da,
4308 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
8a659571 4309 } else {
5f28d2d7
SK		 4310 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10db,
4311 "Done %s.\n", __func__);
8a659571
AV		 4312 }
4313
4314 return rval;
4315}
1d2874de
JC		 4316
4317int
4318qla81xx_fac_get_sector_size(scsi_qla_host_t *vha, uint32_t *sector_size)
4319{
4320 int rval;
4321 mbx_cmd_t mc;
4322 mbx_cmd_t *mcp = &mc;
4323
5f28d2d7
SK		 4324 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10dc,
4325 "Entered %s.\n", __func__);
7c3df132 4326
f73cb695
CD		 4327 if (!IS_QLA81XX(vha->hw) && !IS_QLA83XX(vha->hw) &&
4328 !IS_QLA27XX(vha->hw))
1d2874de
JC		 4329 return QLA_FUNCTION_FAILED;
4330
1d2874de
JC		 4331 mcp->mb[0] = MBC_FLASH_ACCESS_CTRL;
4332 mcp->mb[1] = FAC_OPT_CMD_GET_SECTOR_SIZE;
4333 mcp->out_mb = MBX_1|MBX_0;
4334 mcp->in_mb = MBX_1|MBX_0;
4335 mcp->tov = MBX_TOV_SECONDS;
4336 mcp->flags = 0;
4337 rval = qla2x00_mailbox_command(vha, mcp);
4338
4339 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4340 ql_dbg(ql_dbg_mbx, vha, 0x10dd,
4341 "Failed=%x mb[0]=%x mb[1]=%x.\n",
4342 rval, mcp->mb[0], mcp->mb[1]);
1d2874de 4343 } else {
5f28d2d7
SK		 4344 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10de,
4345 "Done %s.\n", __func__);
1d2874de
JC		 4346 *sector_size = mcp->mb[1];
4347 }
4348
4349 return rval;
4350}
4351
4352int
4353qla81xx_fac_do_write_enable(scsi_qla_host_t *vha, int enable)
4354{
4355 int rval;
4356 mbx_cmd_t mc;
4357 mbx_cmd_t *mcp = &mc;
4358
f73cb695
CD		 4359 if (!IS_QLA81XX(vha->hw) && !IS_QLA83XX(vha->hw) &&
4360 !IS_QLA27XX(vha->hw))
1d2874de
JC		 4361 return QLA_FUNCTION_FAILED;
4362
5f28d2d7
SK		 4363 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10df,
4364 "Entered %s.\n", __func__);
1d2874de
JC		 4365
4366 mcp->mb[0] = MBC_FLASH_ACCESS_CTRL;
4367 mcp->mb[1] = enable ? FAC_OPT_CMD_WRITE_ENABLE :
4368 FAC_OPT_CMD_WRITE_PROTECT;
4369 mcp->out_mb = MBX_1|MBX_0;
4370 mcp->in_mb = MBX_1|MBX_0;
4371 mcp->tov = MBX_TOV_SECONDS;
4372 mcp->flags = 0;
4373 rval = qla2x00_mailbox_command(vha, mcp);
4374
4375 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4376 ql_dbg(ql_dbg_mbx, vha, 0x10e0,
4377 "Failed=%x mb[0]=%x mb[1]=%x.\n",
4378 rval, mcp->mb[0], mcp->mb[1]);
1d2874de 4379 } else {
5f28d2d7
SK		 4380 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e1,
4381 "Done %s.\n", __func__);
1d2874de
JC		 4382 }
4383
4384 return rval;
4385}
4386
4387int
4388qla81xx_fac_erase_sector(scsi_qla_host_t *vha, uint32_t start, uint32_t finish)
4389{
4390 int rval;
4391 mbx_cmd_t mc;
4392 mbx_cmd_t *mcp = &mc;
4393
f73cb695
CD		 4394 if (!IS_QLA81XX(vha->hw) && !IS_QLA83XX(vha->hw) &&
4395 !IS_QLA27XX(vha->hw))
1d2874de
JC		 4396 return QLA_FUNCTION_FAILED;
4397
5f28d2d7
SK		 4398 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e2,
4399 "Entered %s.\n", __func__);
1d2874de
JC		 4400
4401 mcp->mb[0] = MBC_FLASH_ACCESS_CTRL;
4402 mcp->mb[1] = FAC_OPT_CMD_ERASE_SECTOR;
4403 mcp->mb[2] = LSW(start);
4404 mcp->mb[3] = MSW(start);
4405 mcp->mb[4] = LSW(finish);
4406 mcp->mb[5] = MSW(finish);
4407 mcp->out_mb = MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
4408 mcp->in_mb = MBX_2|MBX_1|MBX_0;
4409 mcp->tov = MBX_TOV_SECONDS;
4410 mcp->flags = 0;
4411 rval = qla2x00_mailbox_command(vha, mcp);
4412
4413 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4414 ql_dbg(ql_dbg_mbx, vha, 0x10e3,
4415 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n",
4416 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]);
1d2874de 4417 } else {
5f28d2d7
SK		 4418 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e4,
4419 "Done %s.\n", __func__);
1d2874de
JC		 4420 }
4421
4422 return rval;
4423}
6e181be5
LC		 4424
4425int
4426qla81xx_restart_mpi_firmware(scsi_qla_host_t *vha)
4427{
4428 int rval = 0;
4429 mbx_cmd_t mc;
4430 mbx_cmd_t *mcp = &mc;
4431
5f28d2d7
SK		 4432 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e5,
4433 "Entered %s.\n", __func__);
6e181be5
LC		 4434
4435 mcp->mb[0] = MBC_RESTART_MPI_FW;
4436 mcp->out_mb = MBX_0;
4437 mcp->in_mb = MBX_0|MBX_1;
4438 mcp->tov = MBX_TOV_SECONDS;
4439 mcp->flags = 0;
4440 rval = qla2x00_mailbox_command(vha, mcp);
4441
4442 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4443 ql_dbg(ql_dbg_mbx, vha, 0x10e6,
4444 "Failed=%x mb[0]=%x mb[1]=%x.\n",
4445 rval, mcp->mb[0], mcp->mb[1]);
6e181be5 4446 } else {
5f28d2d7
SK		 4447 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e7,
4448 "Done %s.\n", __func__);
6e181be5
LC		 4449 }
4450
4451 return rval;
4452}
ad0ecd61 4453
c46e65c7
JC		 4454int
4455qla82xx_set_driver_version(scsi_qla_host_t *vha, char *version)
4456{
4457 int rval;
4458 mbx_cmd_t mc;
4459 mbx_cmd_t *mcp = &mc;
4460 int i;
4461 int len;
4462 uint16_t *str;
4463 struct qla_hw_data *ha = vha->hw;
4464
4465 if (!IS_P3P_TYPE(ha))
4466 return QLA_FUNCTION_FAILED;
4467
4468 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x117b,
4469 "Entered %s.\n", __func__);
4470
4471 str = (void *)version;
4472 len = strlen(version);
4473
4474 mcp->mb[0] = MBC_SET_RNID_PARAMS;
4475 mcp->mb[1] = RNID_TYPE_SET_VERSION << 8;
4476 mcp->out_mb = MBX_1|MBX_0;
4477 for (i = 4; i < 16 && len; i++, str++, len -= 2) {
4478 mcp->mb[i] = cpu_to_le16p(str);
4479 mcp->out_mb |= 1<<i;
4480 }
4481 for (; i < 16; i++) {
4482 mcp->mb[i] = 0;
4483 mcp->out_mb |= 1<<i;
4484 }
4485 mcp->in_mb = MBX_1|MBX_0;
4486 mcp->tov = MBX_TOV_SECONDS;
4487 mcp->flags = 0;
4488 rval = qla2x00_mailbox_command(vha, mcp);
4489
4490 if (rval != QLA_SUCCESS) {
4491 ql_dbg(ql_dbg_mbx, vha, 0x117c,
4492 "Failed=%x mb[0]=%x,%x.\n", rval, mcp->mb[0], mcp->mb[1]);
4493 } else {
4494 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x117d,
4495 "Done %s.\n", __func__);
4496 }
4497
4498 return rval;
4499}
4500
4501int
4502qla25xx_set_driver_version(scsi_qla_host_t *vha, char *version)
4503{
4504 int rval;
4505 mbx_cmd_t mc;
4506 mbx_cmd_t *mcp = &mc;
4507 int len;
4508 uint16_t dwlen;
4509 uint8_t *str;
4510 dma_addr_t str_dma;
4511 struct qla_hw_data *ha = vha->hw;
4512
4513 if (!IS_FWI2_CAPABLE(ha) || IS_QLA24XX_TYPE(ha) || IS_QLA81XX(ha) ||
4514 IS_P3P_TYPE(ha))
4515 return QLA_FUNCTION_FAILED;
4516
4517 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x117e,
4518 "Entered %s.\n", __func__);
4519
4520 str = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &str_dma);
4521 if (!str) {
4522 ql_log(ql_log_warn, vha, 0x117f,
4523 "Failed to allocate driver version param.\n");
4524 return QLA_MEMORY_ALLOC_FAILED;
4525 }
4526
4527 memcpy(str, "\x7\x3\x11\x0", 4);
4528 dwlen = str[0];
4529 len = dwlen * 4 - 4;
4530 memset(str + 4, 0, len);
4531 if (len > strlen(version))
4532 len = strlen(version);
4533 memcpy(str + 4, version, len);
4534
4535 mcp->mb[0] = MBC_SET_RNID_PARAMS;
4536 mcp->mb[1] = RNID_TYPE_SET_VERSION << 8 | dwlen;
4537 mcp->mb[2] = MSW(LSD(str_dma));
4538 mcp->mb[3] = LSW(LSD(str_dma));
4539 mcp->mb[6] = MSW(MSD(str_dma));
4540 mcp->mb[7] = LSW(MSD(str_dma));
4541 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
4542 mcp->in_mb = MBX_1|MBX_0;
4543 mcp->tov = MBX_TOV_SECONDS;
4544 mcp->flags = 0;
4545 rval = qla2x00_mailbox_command(vha, mcp);
4546
4547 if (rval != QLA_SUCCESS) {
4548 ql_dbg(ql_dbg_mbx, vha, 0x1180,
4549 "Failed=%x mb[0]=%x,%x.\n", rval, mcp->mb[0], mcp->mb[1]);
4550 } else {
4551 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1181,
4552 "Done %s.\n", __func__);
4553 }
4554
4555 dma_pool_free(ha->s_dma_pool, str, str_dma);
4556
4557 return rval;
4558}
4559
edd05de1
DG		 4560int
4561qla24xx_get_port_login_templ(scsi_qla_host_t *vha, dma_addr_t buf_dma,
4562 void *buf, uint16_t bufsiz)
4563{
4564 int rval, i;
4565 mbx_cmd_t mc;
4566 mbx_cmd_t *mcp = &mc;
4567 uint32_t *bp;
4568
4569 if (!IS_FWI2_CAPABLE(vha->hw))
4570 return QLA_FUNCTION_FAILED;
4571
4572 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1159,
4573 "Entered %s.\n", __func__);
4574
4575 mcp->mb[0] = MBC_GET_RNID_PARAMS;
4576 mcp->mb[1] = RNID_TYPE_PORT_LOGIN << 8;
4577 mcp->mb[2] = MSW(buf_dma);
4578 mcp->mb[3] = LSW(buf_dma);
4579 mcp->mb[6] = MSW(MSD(buf_dma));
4580 mcp->mb[7] = LSW(MSD(buf_dma));
4581 mcp->mb[8] = bufsiz/4;
4582 mcp->out_mb = MBX_8|MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
4583 mcp->in_mb = MBX_1|MBX_0;
4584 mcp->tov = MBX_TOV_SECONDS;
4585 mcp->flags = 0;
4586 rval = qla2x00_mailbox_command(vha, mcp);
4587
4588 if (rval != QLA_SUCCESS) {
4589 ql_dbg(ql_dbg_mbx, vha, 0x115a,
4590 "Failed=%x mb[0]=%x,%x.\n", rval, mcp->mb[0], mcp->mb[1]);
4591 } else {
4592 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x115b,
4593 "Done %s.\n", __func__);
4594 bp = (uint32_t *) buf;
4595 for (i = 0; i < (bufsiz-4)/4; i++, bp++)
4596 *bp = cpu_to_be32(*bp);
4597 }
4598
4599 return rval;
4600}
4601
fe52f6e1
JC		 4602static int
4603qla2x00_read_asic_temperature(scsi_qla_host_t *vha, uint16_t *temp)
4604{
4605 int rval;
4606 mbx_cmd_t mc;
4607 mbx_cmd_t *mcp = &mc;
4608
4609 if (!IS_FWI2_CAPABLE(vha->hw))
4610 return QLA_FUNCTION_FAILED;
4611
4612 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1159,
4613 "Entered %s.\n", __func__);
4614
4615 mcp->mb[0] = MBC_GET_RNID_PARAMS;
4616 mcp->mb[1] = RNID_TYPE_ASIC_TEMP << 8;
4617 mcp->out_mb = MBX_1|MBX_0;
4618 mcp->in_mb = MBX_1|MBX_0;
4619 mcp->tov = MBX_TOV_SECONDS;
4620 mcp->flags = 0;
4621 rval = qla2x00_mailbox_command(vha, mcp);
4622 *temp = mcp->mb[1];
4623
4624 if (rval != QLA_SUCCESS) {
4625 ql_dbg(ql_dbg_mbx, vha, 0x115a,
4626 "Failed=%x mb[0]=%x,%x.\n", rval, mcp->mb[0], mcp->mb[1]);
4627 } else {
4628 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x115b,
4629 "Done %s.\n", __func__);
4630 }
4631
4632 return rval;
4633}
4634
ad0ecd61 4635int
6766df9e
JC		 4636qla2x00_read_sfp(scsi_qla_host_t *vha, dma_addr_t sfp_dma, uint8_t *sfp,
4637 uint16_t dev, uint16_t off, uint16_t len, uint16_t opt)
ad0ecd61
JC		 4638{
4639 int rval;
4640 mbx_cmd_t mc;
4641 mbx_cmd_t *mcp = &mc;
6766df9e
JC		 4642 struct qla_hw_data *ha = vha->hw;
4643
5f28d2d7
SK		 4644 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e8,
4645 "Entered %s.\n", __func__);
7c3df132 4646
6766df9e
JC		 4647 if (!IS_FWI2_CAPABLE(ha))
4648 return QLA_FUNCTION_FAILED;
ad0ecd61 4649
6766df9e
JC		 4650 if (len == 1)
4651 opt |= BIT_0;
4652
ad0ecd61
JC		 4653 mcp->mb[0] = MBC_READ_SFP;
4654 mcp->mb[1] = dev;
4655 mcp->mb[2] = MSW(sfp_dma);
4656 mcp->mb[3] = LSW(sfp_dma);
4657 mcp->mb[6] = MSW(MSD(sfp_dma));
4658 mcp->mb[7] = LSW(MSD(sfp_dma));
4659 mcp->mb[8] = len;
6766df9e 4660 mcp->mb[9] = off;
ad0ecd61
JC		 4661 mcp->mb[10] = opt;
4662 mcp->out_mb = MBX_10|MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
1bff6cc8 4663 mcp->in_mb = MBX_1|MBX_0;
ad0ecd61
JC		 4664 mcp->tov = MBX_TOV_SECONDS;
4665 mcp->flags = 0;
4666 rval = qla2x00_mailbox_command(vha, mcp);
4667
4668 if (opt & BIT_0)
6766df9e 4669 *sfp = mcp->mb[1];
ad0ecd61
JC		 4670
4671 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4672 ql_dbg(ql_dbg_mbx, vha, 0x10e9,
4673 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
e4e3a2ce
QT		 4674 if (mcp->mb[0] == MBS_COMMAND_ERROR &&
4675 mcp->mb[1] == 0x22)
4676 /* sfp is not there */
4677 rval = QLA_INTERFACE_ERROR;
ad0ecd61 4678 } else {
5f28d2d7
SK		 4679 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ea,
4680 "Done %s.\n", __func__);
ad0ecd61
JC		 4681 }
4682
4683 return rval;
4684}
4685
4686int
6766df9e
JC		 4687qla2x00_write_sfp(scsi_qla_host_t *vha, dma_addr_t sfp_dma, uint8_t *sfp,
4688 uint16_t dev, uint16_t off, uint16_t len, uint16_t opt)
ad0ecd61
JC		 4689{
4690 int rval;
4691 mbx_cmd_t mc;
4692 mbx_cmd_t *mcp = &mc;
6766df9e
JC		 4693 struct qla_hw_data *ha = vha->hw;
4694
5f28d2d7
SK		 4695 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10eb,
4696 "Entered %s.\n", __func__);
7c3df132 4697
6766df9e
JC		 4698 if (!IS_FWI2_CAPABLE(ha))
4699 return QLA_FUNCTION_FAILED;
ad0ecd61 4700
6766df9e
JC		 4701 if (len == 1)
4702 opt |= BIT_0;
4703
ad0ecd61 4704 if (opt & BIT_0)
6766df9e 4705 len = *sfp;
ad0ecd61
JC		 4706
4707 mcp->mb[0] = MBC_WRITE_SFP;
4708 mcp->mb[1] = dev;
4709 mcp->mb[2] = MSW(sfp_dma);
4710 mcp->mb[3] = LSW(sfp_dma);
4711 mcp->mb[6] = MSW(MSD(sfp_dma));
4712 mcp->mb[7] = LSW(MSD(sfp_dma));
4713 mcp->mb[8] = len;
6766df9e 4714 mcp->mb[9] = off;
ad0ecd61
JC		 4715 mcp->mb[10] = opt;
4716 mcp->out_mb = MBX_10|MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
6766df9e 4717 mcp->in_mb = MBX_1|MBX_0;
ad0ecd61
JC		 4718 mcp->tov = MBX_TOV_SECONDS;
4719 mcp->flags = 0;
4720 rval = qla2x00_mailbox_command(vha, mcp);
4721
4722 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4723 ql_dbg(ql_dbg_mbx, vha, 0x10ec,
4724 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
ad0ecd61 4725 } else {
5f28d2d7
SK		 4726 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ed,
4727 "Done %s.\n", __func__);
ad0ecd61
JC		 4728 }
4729
4730 return rval;
4731}
ce0423f4
AV		 4732
4733int
4734qla2x00_get_xgmac_stats(scsi_qla_host_t *vha, dma_addr_t stats_dma,
4735 uint16_t size_in_bytes, uint16_t *actual_size)
4736{
4737 int rval;
4738 mbx_cmd_t mc;
4739 mbx_cmd_t *mcp = &mc;
4740
5f28d2d7
SK		 4741 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ee,
4742 "Entered %s.\n", __func__);
7c3df132 4743
6246b8a1 4744 if (!IS_CNA_CAPABLE(vha->hw))
ce0423f4
AV		 4745 return QLA_FUNCTION_FAILED;
4746
ce0423f4
AV		 4747 mcp->mb[0] = MBC_GET_XGMAC_STATS;
4748 mcp->mb[2] = MSW(stats_dma);
4749 mcp->mb[3] = LSW(stats_dma);
4750 mcp->mb[6] = MSW(MSD(stats_dma));
4751 mcp->mb[7] = LSW(MSD(stats_dma));
4752 mcp->mb[8] = size_in_bytes >> 2;
4753 mcp->out_mb = MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_0;
4754 mcp->in_mb = MBX_2|MBX_1|MBX_0;
4755 mcp->tov = MBX_TOV_SECONDS;
4756 mcp->flags = 0;
4757 rval = qla2x00_mailbox_command(vha, mcp);
4758
4759 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4760 ql_dbg(ql_dbg_mbx, vha, 0x10ef,
4761 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n",
4762 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]);
ce0423f4 4763 } else {
5f28d2d7
SK		 4764 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f0,
4765 "Done %s.\n", __func__);
7c3df132 4766
ce0423f4
AV		 4767
4768 *actual_size = mcp->mb[2] << 2;
4769 }
4770
4771 return rval;
4772}
11bbc1d8
AV		 4773
4774int
4775qla2x00_get_dcbx_params(scsi_qla_host_t *vha, dma_addr_t tlv_dma,
4776 uint16_t size)
4777{
4778 int rval;
4779 mbx_cmd_t mc;
4780 mbx_cmd_t *mcp = &mc;
4781
5f28d2d7
SK		 4782 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f1,
4783 "Entered %s.\n", __func__);
7c3df132 4784
6246b8a1 4785 if (!IS_CNA_CAPABLE(vha->hw))
11bbc1d8
AV		 4786 return QLA_FUNCTION_FAILED;
4787
11bbc1d8
AV		 4788 mcp->mb[0] = MBC_GET_DCBX_PARAMS;
4789 mcp->mb[1] = 0;
4790 mcp->mb[2] = MSW(tlv_dma);
4791 mcp->mb[3] = LSW(tlv_dma);
4792 mcp->mb[6] = MSW(MSD(tlv_dma));
4793 mcp->mb[7] = LSW(MSD(tlv_dma));
4794 mcp->mb[8] = size;
4795 mcp->out_mb = MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
4796 mcp->in_mb = MBX_2|MBX_1|MBX_0;
4797 mcp->tov = MBX_TOV_SECONDS;
4798 mcp->flags = 0;
4799 rval = qla2x00_mailbox_command(vha, mcp);
4800
4801 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4802 ql_dbg(ql_dbg_mbx, vha, 0x10f2,
4803 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n",
4804 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]);
11bbc1d8 4805 } else {
5f28d2d7
SK		 4806 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f3,
4807 "Done %s.\n", __func__);
11bbc1d8
AV		 4808 }
4809
4810 return rval;
4811}
18e7555a
AV		 4812
4813int
4814qla2x00_read_ram_word(scsi_qla_host_t *vha, uint32_t risc_addr, uint32_t *data)
4815{
4816 int rval;
4817 mbx_cmd_t mc;
4818 mbx_cmd_t *mcp = &mc;
4819
5f28d2d7
SK		 4820 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f4,
4821 "Entered %s.\n", __func__);
7c3df132 4822
18e7555a
AV		 4823 if (!IS_FWI2_CAPABLE(vha->hw))
4824 return QLA_FUNCTION_FAILED;
4825
18e7555a
AV		 4826 mcp->mb[0] = MBC_READ_RAM_EXTENDED;
4827 mcp->mb[1] = LSW(risc_addr);
4828 mcp->mb[8] = MSW(risc_addr);
4829 mcp->out_mb = MBX_8|MBX_1|MBX_0;
4830 mcp->in_mb = MBX_3|MBX_2|MBX_0;
4831 mcp->tov = 30;
4832 mcp->flags = 0;
4833 rval = qla2x00_mailbox_command(vha, mcp);
4834 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4835 ql_dbg(ql_dbg_mbx, vha, 0x10f5,
4836 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
18e7555a 4837 } else {
5f28d2d7
SK		 4838 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f6,
4839 "Done %s.\n", __func__);
18e7555a
AV		 4840 *data = mcp->mb[3] << 16 | mcp->mb[2];
4841 }
4842
4843 return rval;
4844}
4845
9a069e19 4846int
a9083016
GM		 4847qla2x00_loopback_test(scsi_qla_host_t *vha, struct msg_echo_lb *mreq,
4848 uint16_t *mresp)
9a069e19
GM		 4849{
4850 int rval;
4851 mbx_cmd_t mc;
4852 mbx_cmd_t *mcp = &mc;
9a069e19 4853
5f28d2d7
SK		 4854 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f7,
4855 "Entered %s.\n", __func__);
9a069e19
GM		 4856
4857 memset(mcp->mb, 0 , sizeof(mcp->mb));
4858 mcp->mb[0] = MBC_DIAGNOSTIC_LOOP_BACK;
4859 mcp->mb[1] = mreq->options | BIT_6; // BIT_6 specifies 64 bit addressing
4860
4861 /* transfer count */
4862 mcp->mb[10] = LSW(mreq->transfer_size);
4863 mcp->mb[11] = MSW(mreq->transfer_size);
4864
4865 /* send data address */
4866 mcp->mb[14] = LSW(mreq->send_dma);
4867 mcp->mb[15] = MSW(mreq->send_dma);
4868 mcp->mb[20] = LSW(MSD(mreq->send_dma));
4869 mcp->mb[21] = MSW(MSD(mreq->send_dma));
4870
25985edc 4871 /* receive data address */
9a069e19
GM		 4872 mcp->mb[16] = LSW(mreq->rcv_dma);
4873 mcp->mb[17] = MSW(mreq->rcv_dma);
4874 mcp->mb[6] = LSW(MSD(mreq->rcv_dma));
4875 mcp->mb[7] = MSW(MSD(mreq->rcv_dma));
4876
4877 /* Iteration count */
1b98b421
JC		 4878 mcp->mb[18] = LSW(mreq->iteration_count);
4879 mcp->mb[19] = MSW(mreq->iteration_count);
9a069e19
GM		 4880
4881 mcp->out_mb = MBX_21|MBX_20|MBX_19|MBX_18|MBX_17|MBX_16|MBX_15|
4882 MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_7|MBX_6|MBX_1|MBX_0;
6246b8a1 4883 if (IS_CNA_CAPABLE(vha->hw))
9a069e19
GM		 4884 mcp->out_mb |= MBX_2;
4885 mcp->in_mb = MBX_19|MBX_18|MBX_3|MBX_2|MBX_1|MBX_0;
4886
4887 mcp->buf_size = mreq->transfer_size;
4888 mcp->tov = MBX_TOV_SECONDS;
4889 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
4890
4891 rval = qla2x00_mailbox_command(vha, mcp);
4892
4893 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4894 ql_dbg(ql_dbg_mbx, vha, 0x10f8,
4895 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x mb[3]=%x mb[18]=%x "
4896 "mb[19]=%x.\n", rval, mcp->mb[0], mcp->mb[1], mcp->mb[2],
4897 mcp->mb[3], mcp->mb[18], mcp->mb[19]);
9a069e19 4898 } else {
5f28d2d7
SK		 4899 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f9,
4900 "Done %s.\n", __func__);
9a069e19
GM		 4901 }
4902
4903 /* Copy mailbox information */
4904 memcpy( mresp, mcp->mb, 64);
9a069e19
GM		 4905 return rval;
4906}
4907
4908int
a9083016
GM		 4909qla2x00_echo_test(scsi_qla_host_t *vha, struct msg_echo_lb *mreq,
4910 uint16_t *mresp)
9a069e19
GM		 4911{
4912 int rval;
4913 mbx_cmd_t mc;
4914 mbx_cmd_t *mcp = &mc;
4915 struct qla_hw_data *ha = vha->hw;
4916
5f28d2d7
SK		 4917 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10fa,
4918 "Entered %s.\n", __func__);
9a069e19
GM		 4919
4920 memset(mcp->mb, 0 , sizeof(mcp->mb));
4921 mcp->mb[0] = MBC_DIAGNOSTIC_ECHO;
1d634965
JC		 4922 /* BIT_6 specifies 64bit address */
4923 mcp->mb[1] = mreq->options | BIT_15 | BIT_6;
6246b8a1 4924 if (IS_CNA_CAPABLE(ha)) {
a9083016
GM		 4925 mcp->mb[2] = vha->fcoe_fcf_idx;
4926 }
9a069e19
GM		 4927 mcp->mb[16] = LSW(mreq->rcv_dma);
4928 mcp->mb[17] = MSW(mreq->rcv_dma);
4929 mcp->mb[6] = LSW(MSD(mreq->rcv_dma));
4930 mcp->mb[7] = MSW(MSD(mreq->rcv_dma));
4931
4932 mcp->mb[10] = LSW(mreq->transfer_size);
4933
4934 mcp->mb[14] = LSW(mreq->send_dma);
4935 mcp->mb[15] = MSW(mreq->send_dma);
4936 mcp->mb[20] = LSW(MSD(mreq->send_dma));
4937 mcp->mb[21] = MSW(MSD(mreq->send_dma));
4938
4939 mcp->out_mb = MBX_21|MBX_20|MBX_17|MBX_16|MBX_15|
4940 MBX_14|MBX_10|MBX_7|MBX_6|MBX_1|MBX_0;
6246b8a1 4941 if (IS_CNA_CAPABLE(ha))
9a069e19
GM		 4942 mcp->out_mb |= MBX_2;
4943
4944 mcp->in_mb = MBX_0;
6246b8a1
GM		 4945 if (IS_QLA24XX_TYPE(ha) || IS_QLA25XX(ha) ||
4946 IS_CNA_CAPABLE(ha) || IS_QLA2031(ha))
9a069e19 4947 mcp->in_mb |= MBX_1;
6246b8a1 4948 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha))
9a069e19
GM		 4949 mcp->in_mb |= MBX_3;
4950
4951 mcp->tov = MBX_TOV_SECONDS;
4952 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
4953 mcp->buf_size = mreq->transfer_size;
4954
4955 rval = qla2x00_mailbox_command(vha, mcp);
4956
4957 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4958 ql_dbg(ql_dbg_mbx, vha, 0x10fb,
4959 "Failed=%x mb[0]=%x mb[1]=%x.\n",
4960 rval, mcp->mb[0], mcp->mb[1]);
9a069e19 4961 } else {
5f28d2d7
SK		 4962 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10fc,
4963 "Done %s.\n", __func__);
9a069e19
GM		 4964 }
4965
4966 /* Copy mailbox information */
6dbdda4d 4967 memcpy(mresp, mcp->mb, 64);
9a069e19
GM		 4968 return rval;
4969}
6dbdda4d 4970
9a069e19 4971int
7c3df132 4972qla84xx_reset_chip(scsi_qla_host_t *vha, uint16_t enable_diagnostic)
9a069e19
GM		 4973{
4974 int rval;
4975 mbx_cmd_t mc;
4976 mbx_cmd_t *mcp = &mc;
4977
5f28d2d7 4978 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10fd,
7c3df132 4979 "Entered %s enable_diag=%d.\n", __func__, enable_diagnostic);
9a069e19
GM		 4980
4981 mcp->mb[0] = MBC_ISP84XX_RESET;
4982 mcp->mb[1] = enable_diagnostic;
4983 mcp->out_mb = MBX_1|MBX_0;
4984 mcp->in_mb = MBX_1|MBX_0;
4985 mcp->tov = MBX_TOV_SECONDS;
4986 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
7c3df132 4987 rval = qla2x00_mailbox_command(vha, mcp);
9a069e19 4988
9a069e19 4989 if (rval != QLA_SUCCESS)
7c3df132 4990 ql_dbg(ql_dbg_mbx, vha, 0x10fe, "Failed=%x.\n", rval);
9a069e19 4991 else
5f28d2d7
SK		 4992 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ff,
4993 "Done %s.\n", __func__);
9a069e19
GM		 4994
4995 return rval;
4996}
4997
18e7555a
AV		 4998int
4999qla2x00_write_ram_word(scsi_qla_host_t *vha, uint32_t risc_addr, uint32_t data)
5000{
5001 int rval;
5002 mbx_cmd_t mc;
5003 mbx_cmd_t *mcp = &mc;
5004
5f28d2d7
SK		 5005 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1100,
5006 "Entered %s.\n", __func__);
7c3df132 5007
18e7555a 5008 if (!IS_FWI2_CAPABLE(vha->hw))
6c452a45 5009 return QLA_FUNCTION_FAILED;
18e7555a 5010
18e7555a
AV		 5011 mcp->mb[0] = MBC_WRITE_RAM_WORD_EXTENDED;
5012 mcp->mb[1] = LSW(risc_addr);
5013 mcp->mb[2] = LSW(data);
5014 mcp->mb[3] = MSW(data);
5015 mcp->mb[8] = MSW(risc_addr);
5016 mcp->out_mb = MBX_8|MBX_3|MBX_2|MBX_1|MBX_0;
5017 mcp->in_mb = MBX_0;
5018 mcp->tov = 30;
5019 mcp->flags = 0;
5020 rval = qla2x00_mailbox_command(vha, mcp);
5021 if (rval != QLA_SUCCESS) {
7c3df132
SK		 5022 ql_dbg(ql_dbg_mbx, vha, 0x1101,
5023 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
18e7555a 5024 } else {
5f28d2d7
SK		 5025 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1102,
5026 "Done %s.\n", __func__);
18e7555a
AV		 5027 }
5028
5029 return rval;
5030}
3064ff39 5031
b1d46989
MI		 5032int
5033qla81xx_write_mpi_register(scsi_qla_host_t *vha, uint16_t *mb)
5034{
5035 int rval;
5036 uint32_t stat, timer;
5037 uint16_t mb0 = 0;
5038 struct qla_hw_data *ha = vha->hw;
5039 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
5040
5041 rval = QLA_SUCCESS;
5042
5f28d2d7
SK		 5043 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1103,
5044 "Entered %s.\n", __func__);
b1d46989
MI		 5045
5046 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
5047
5048 /* Write the MBC data to the registers */
5049 WRT_REG_WORD(&reg->mailbox0, MBC_WRITE_MPI_REGISTER);
5050 WRT_REG_WORD(&reg->mailbox1, mb[0]);
5051 WRT_REG_WORD(&reg->mailbox2, mb[1]);
5052 WRT_REG_WORD(&reg->mailbox3, mb[2]);
5053 WRT_REG_WORD(&reg->mailbox4, mb[3]);
5054
5055 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_HOST_INT);
5056
5057 /* Poll for MBC interrupt */
5058 for (timer = 6000000; timer; timer--) {
5059 /* Check for pending interrupts. */
5060 stat = RD_REG_DWORD(&reg->host_status);
5061 if (stat & HSRX_RISC_INT) {
5062 stat &= 0xff;
5063
5064 if (stat == 0x1 || stat == 0x2 ||
5065 stat == 0x10 || stat == 0x11) {
5066 set_bit(MBX_INTERRUPT,
5067 &ha->mbx_cmd_flags);
5068 mb0 = RD_REG_WORD(&reg->mailbox0);
5069 WRT_REG_DWORD(&reg->hccr,
5070 HCCRX_CLR_RISC_INT);
5071 RD_REG_DWORD(&reg->hccr);
5072 break;
5073 }
5074 }
5075 udelay(5);
5076 }
5077
5078 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags))
5079 rval = mb0 & MBS_MASK;
5080 else
5081 rval = QLA_FUNCTION_FAILED;
5082
5083 if (rval != QLA_SUCCESS) {
7c3df132
SK		 5084 ql_dbg(ql_dbg_mbx, vha, 0x1104,
5085 "Failed=%x mb[0]=%x.\n", rval, mb[0]);
b1d46989 5086 } else {
5f28d2d7
SK		 5087 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1105,
5088 "Done %s.\n", __func__);
b1d46989
MI		 5089 }
5090
5091 return rval;
5092}
6246b8a1 5093
3064ff39
MH		 5094int
5095qla2x00_get_data_rate(scsi_qla_host_t *vha)
5096{
5097 int rval;
5098 mbx_cmd_t mc;
5099 mbx_cmd_t *mcp = &mc;
5100 struct qla_hw_data *ha = vha->hw;
5101
5f28d2d7
SK		 5102 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1106,
5103 "Entered %s.\n", __func__);
7c3df132 5104
3064ff39
MH		 5105 if (!IS_FWI2_CAPABLE(ha))
5106 return QLA_FUNCTION_FAILED;
5107
3064ff39
MH		 5108 mcp->mb[0] = MBC_DATA_RATE;
5109 mcp->mb[1] = 0;
5110 mcp->out_mb = MBX_1|MBX_0;
5111 mcp->in_mb = MBX_2|MBX_1|MBX_0;
f73cb695 5112 if (IS_QLA83XX(ha) || IS_QLA27XX(ha))
6246b8a1 5113 mcp->in_mb |= MBX_3;
3064ff39
MH		 5114 mcp->tov = MBX_TOV_SECONDS;
5115 mcp->flags = 0;
5116 rval = qla2x00_mailbox_command(vha, mcp);
5117 if (rval != QLA_SUCCESS) {
7c3df132
SK		 5118 ql_dbg(ql_dbg_mbx, vha, 0x1107,
5119 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
3064ff39 5120 } else {
5f28d2d7
SK		 5121 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1108,
5122 "Done %s.\n", __func__);
3064ff39
MH		 5123 if (mcp->mb[1] != 0x7)
5124 ha->link_data_rate = mcp->mb[1];
5125 }
5126
5127 return rval;
5128}
09ff701a 5129
23f2ebd1
SR		 5130int
5131qla81xx_get_port_config(scsi_qla_host_t *vha, uint16_t *mb)
5132{
5133 int rval;
5134 mbx_cmd_t mc;
5135 mbx_cmd_t *mcp = &mc;
5136 struct qla_hw_data *ha = vha->hw;
5137
5f28d2d7
SK		 5138 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1109,
5139 "Entered %s.\n", __func__);
23f2ebd1 5140
f73cb695
CD		 5141 if (!IS_QLA81XX(ha) && !IS_QLA83XX(ha) && !IS_QLA8044(ha) &&
5142 !IS_QLA27XX(ha))
23f2ebd1
SR		 5143 return QLA_FUNCTION_FAILED;
5144 mcp->mb[0] = MBC_GET_PORT_CONFIG;
5145 mcp->out_mb = MBX_0;
5146 mcp->in_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
5147 mcp->tov = MBX_TOV_SECONDS;
5148 mcp->flags = 0;
5149
5150 rval = qla2x00_mailbox_command(vha, mcp);
5151
5152 if (rval != QLA_SUCCESS) {
7c3df132
SK		 5153 ql_dbg(ql_dbg_mbx, vha, 0x110a,
5154 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
23f2ebd1
SR		 5155 } else {
5156 /* Copy all bits to preserve original value */
5157 memcpy(mb, &mcp->mb[1], sizeof(uint16_t) * 4);
5158
5f28d2d7
SK		 5159 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x110b,
5160 "Done %s.\n", __func__);
23f2ebd1
SR		 5161 }
5162 return rval;
5163}
5164
5165int
5166qla81xx_set_port_config(scsi_qla_host_t *vha, uint16_t *mb)
5167{
5168 int rval;
5169 mbx_cmd_t mc;
5170 mbx_cmd_t *mcp = &mc;
5171
5f28d2d7
SK		 5172 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x110c,
5173 "Entered %s.\n", __func__);
23f2ebd1
SR		 5174
5175 mcp->mb[0] = MBC_SET_PORT_CONFIG;
5176 /* Copy all bits to preserve original setting */
5177 memcpy(&mcp->mb[1], mb, sizeof(uint16_t) * 4);
5178 mcp->out_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
5179 mcp->in_mb = MBX_0;
5180 mcp->tov = MBX_TOV_SECONDS;
5181 mcp->flags = 0;
5182 rval = qla2x00_mailbox_command(vha, mcp);
5183
5184 if (rval != QLA_SUCCESS) {
7c3df132
SK		 5185 ql_dbg(ql_dbg_mbx, vha, 0x110d,
5186 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
23f2ebd1 5187 } else
5f28d2d7
SK		 5188 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x110e,
5189 "Done %s.\n", __func__);
23f2ebd1
SR		 5190
5191 return rval;
5192}
5193
5194
09ff701a
SR		 5195int
5196qla24xx_set_fcp_prio(scsi_qla_host_t *vha, uint16_t loop_id, uint16_t priority,
5197 uint16_t *mb)
5198{
5199 int rval;
5200 mbx_cmd_t mc;
5201 mbx_cmd_t *mcp = &mc;
5202 struct qla_hw_data *ha = vha->hw;
5203
5f28d2d7
SK		 5204 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x110f,
5205 "Entered %s.\n", __func__);
7c3df132 5206
09ff701a
SR		 5207 if (!IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha))
5208 return QLA_FUNCTION_FAILED;
5209
09ff701a
SR		 5210 mcp->mb[0] = MBC_PORT_PARAMS;
5211 mcp->mb[1] = loop_id;
5212 if (ha->flags.fcp_prio_enabled)
5213 mcp->mb[2] = BIT_1;
5214 else
5215 mcp->mb[2] = BIT_2;
5216 mcp->mb[4] = priority & 0xf;
5217 mcp->mb[9] = vha->vp_idx;
5218 mcp->out_mb = MBX_9|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
5219 mcp->in_mb = MBX_4|MBX_3|MBX_1|MBX_0;
5220 mcp->tov = 30;
5221 mcp->flags = 0;
5222 rval = qla2x00_mailbox_command(vha, mcp);
5223 if (mb != NULL) {
5224 mb[0] = mcp->mb[0];
5225 mb[1] = mcp->mb[1];
5226 mb[3] = mcp->mb[3];
5227 mb[4] = mcp->mb[4];
5228 }
5229
5230 if (rval != QLA_SUCCESS) {
7c3df132 5231 ql_dbg(ql_dbg_mbx, vha, 0x10cd, "Failed=%x.\n", rval);
09ff701a 5232 } else {
5f28d2d7
SK		 5233 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10cc,
5234 "Done %s.\n", __func__);
09ff701a
SR		 5235 }
5236
5237 return rval;
5238}
a9083016 5239
794a5691 5240int
fe52f6e1 5241qla2x00_get_thermal_temp(scsi_qla_host_t *vha, uint16_t *temp)
794a5691 5242{
fe52f6e1 5243 int rval = QLA_FUNCTION_FAILED;
794a5691 5244 struct qla_hw_data *ha = vha->hw;
fe52f6e1 5245 uint8_t byte;
794a5691 5246
1ae47cf3
JC		 5247 if (!IS_FWI2_CAPABLE(ha) || IS_QLA24XX_TYPE(ha) || IS_QLA81XX(ha)) {
5248 ql_dbg(ql_dbg_mbx, vha, 0x1150,
5249 "Thermal not supported by this card.\n");
5250 return rval;
5251 }
5252
5253 if (IS_QLA25XX(ha)) {
5254 if (ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC &&
5255 ha->pdev->subsystem_device == 0x0175) {
5256 rval = qla2x00_read_sfp(vha, 0, &byte,
5257 0x98, 0x1, 1, BIT_13|BIT_0);
5258 *temp = byte;
5259 return rval;
5260 }
5261 if (ha->pdev->subsystem_vendor == PCI_VENDOR_ID_HP &&
5262 ha->pdev->subsystem_device == 0x338e) {
5263 rval = qla2x00_read_sfp(vha, 0, &byte,
5264 0x98, 0x1, 1, BIT_15|BIT_14|BIT_0);
5265 *temp = byte;
5266 return rval;
5267 }
5268 ql_dbg(ql_dbg_mbx, vha, 0x10c9,
5269 "Thermal not supported by this card.\n");
5270 return rval;
794a5691 5271 }
794a5691 5272
1ae47cf3
JC		 5273 if (IS_QLA82XX(ha)) {
5274 *temp = qla82xx_read_temperature(vha);
5275 rval = QLA_SUCCESS;
5276 return rval;
5277 } else if (IS_QLA8044(ha)) {
5278 *temp = qla8044_read_temperature(vha);
5279 rval = QLA_SUCCESS;
5280 return rval;
794a5691 5281 }
794a5691 5282
1ae47cf3 5283 rval = qla2x00_read_asic_temperature(vha, temp);
794a5691
AV		 5284 return rval;
5285}
5286
a9083016
GM		 5287int
5288qla82xx_mbx_intr_enable(scsi_qla_host_t *vha)
5289{
5290 int rval;
5291 struct qla_hw_data *ha = vha->hw;
5292 mbx_cmd_t mc;
5293 mbx_cmd_t *mcp = &mc;
5294
5f28d2d7
SK		 5295 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1017,
5296 "Entered %s.\n", __func__);
7c3df132 5297
a9083016
GM		 5298 if (!IS_FWI2_CAPABLE(ha))
5299 return QLA_FUNCTION_FAILED;
5300
a9083016 5301 memset(mcp, 0, sizeof(mbx_cmd_t));
3711333d 5302 mcp->mb[0] = MBC_TOGGLE_INTERRUPT;
a9083016
GM		 5303 mcp->mb[1] = 1;
5304
5305 mcp->out_mb = MBX_1|MBX_0;
5306 mcp->in_mb = MBX_0;
5307 mcp->tov = 30;
5308 mcp->flags = 0;
5309
5310 rval = qla2x00_mailbox_command(vha, mcp);
5311 if (rval != QLA_SUCCESS) {
7c3df132
SK		 5312 ql_dbg(ql_dbg_mbx, vha, 0x1016,
5313 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
a9083016 5314 } else {
5f28d2d7
SK		 5315 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x100e,
5316 "Done %s.\n", __func__);
a9083016
GM		 5317 }
5318
5319 return rval;
5320}
5321
5322int
5323qla82xx_mbx_intr_disable(scsi_qla_host_t *vha)
5324{
5325 int rval;
5326 struct qla_hw_data *ha = vha->hw;
5327 mbx_cmd_t mc;
5328 mbx_cmd_t *mcp = &mc;
5329
5f28d2d7
SK		 5330 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x100d,
5331 "Entered %s.\n", __func__);
7c3df132 5332
7ec0effd 5333 if (!IS_P3P_TYPE(ha))
a9083016
GM		 5334 return QLA_FUNCTION_FAILED;
5335
a9083016 5336 memset(mcp, 0, sizeof(mbx_cmd_t));
3711333d 5337 mcp->mb[0] = MBC_TOGGLE_INTERRUPT;
a9083016
GM		 5338 mcp->mb[1] = 0;
5339
5340 mcp->out_mb = MBX_1|MBX_0;
5341 mcp->in_mb = MBX_0;
5342 mcp->tov = 30;
5343 mcp->flags = 0;
5344
5345 rval = qla2x00_mailbox_command(vha, mcp);
5346 if (rval != QLA_SUCCESS) {
7c3df132
SK		 5347 ql_dbg(ql_dbg_mbx, vha, 0x100c,
5348 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
a9083016 5349 } else {
5f28d2d7
SK		 5350 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x100b,
5351 "Done %s.\n", __func__);
a9083016
GM		 5352 }
5353
5354 return rval;
5355}
08de2844
GM		 5356
5357int
5358qla82xx_md_get_template_size(scsi_qla_host_t *vha)
5359{
5360 struct qla_hw_data *ha = vha->hw;
5361 mbx_cmd_t mc;
5362 mbx_cmd_t *mcp = &mc;
5363 int rval = QLA_FUNCTION_FAILED;
5364
5f28d2d7
SK		 5365 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x111f,
5366 "Entered %s.\n", __func__);
08de2844
GM		 5367
5368 memset(mcp->mb, 0 , sizeof(mcp->mb));
5369 mcp->mb[0] = LSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE);
5370 mcp->mb[1] = MSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE);
5371 mcp->mb[2] = LSW(RQST_TMPLT_SIZE);
5372 mcp->mb[3] = MSW(RQST_TMPLT_SIZE);
5373
5374 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
5375 mcp->in_mb = MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8|
5376 MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
5377
5378 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
5379 mcp->tov = MBX_TOV_SECONDS;
5380 rval = qla2x00_mailbox_command(vha, mcp);
5381
5382 /* Always copy back return mailbox values. */
5383 if (rval != QLA_SUCCESS) {
5384 ql_dbg(ql_dbg_mbx, vha, 0x1120,
5385 "mailbox command FAILED=0x%x, subcode=%x.\n",
5386 (mcp->mb[1] << 16) | mcp->mb[0],
5387 (mcp->mb[3] << 16) | mcp->mb[2]);
5388 } else {
5f28d2d7
SK		 5389 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1121,
5390 "Done %s.\n", __func__);
08de2844
GM		 5391 ha->md_template_size = ((mcp->mb[3] << 16) | mcp->mb[2]);
5392 if (!ha->md_template_size) {
5393 ql_dbg(ql_dbg_mbx, vha, 0x1122,
5394 "Null template size obtained.\n");
5395 rval = QLA_FUNCTION_FAILED;
5396 }
5397 }
5398 return rval;
5399}
5400
5401int
5402qla82xx_md_get_template(scsi_qla_host_t *vha)
5403{
5404 struct qla_hw_data *ha = vha->hw;
5405 mbx_cmd_t mc;
5406 mbx_cmd_t *mcp = &mc;
5407 int rval = QLA_FUNCTION_FAILED;
5408
5f28d2d7
SK		 5409 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1123,
5410 "Entered %s.\n", __func__);
08de2844
GM		 5411
5412 ha->md_tmplt_hdr = dma_alloc_coherent(&ha->pdev->dev,
5413 ha->md_template_size, &ha->md_tmplt_hdr_dma, GFP_KERNEL);
5414 if (!ha->md_tmplt_hdr) {
5415 ql_log(ql_log_warn, vha, 0x1124,
5416 "Unable to allocate memory for Minidump template.\n");
5417 return rval;
5418 }
5419
5420 memset(mcp->mb, 0 , sizeof(mcp->mb));
5421 mcp->mb[0] = LSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE);
5422 mcp->mb[1] = MSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE);
5423 mcp->mb[2] = LSW(RQST_TMPLT);
5424 mcp->mb[3] = MSW(RQST_TMPLT);
5425 mcp->mb[4] = LSW(LSD(ha->md_tmplt_hdr_dma));
5426 mcp->mb[5] = MSW(LSD(ha->md_tmplt_hdr_dma));
5427 mcp->mb[6] = LSW(MSD(ha->md_tmplt_hdr_dma));
5428 mcp->mb[7] = MSW(MSD(ha->md_tmplt_hdr_dma));
5429 mcp->mb[8] = LSW(ha->md_template_size);
5430 mcp->mb[9] = MSW(ha->md_template_size);
5431
5432 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
5433 mcp->tov = MBX_TOV_SECONDS;
5434 mcp->out_mb = MBX_11|MBX_10|MBX_9|MBX_8|
5435 MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
5436 mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0;
5437 rval = qla2x00_mailbox_command(vha, mcp);
5438
5439 if (rval != QLA_SUCCESS) {
5440 ql_dbg(ql_dbg_mbx, vha, 0x1125,
5441 "mailbox command FAILED=0x%x, subcode=%x.\n",
5442 ((mcp->mb[1] << 16) | mcp->mb[0]),
5443 ((mcp->mb[3] << 16) | mcp->mb[2]));
5444 } else
5f28d2d7
SK		 5445 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1126,
5446 "Done %s.\n", __func__);
08de2844
GM		 5447 return rval;
5448}
999916dc 5449
7ec0effd
AD		 5450int
5451qla8044_md_get_template(scsi_qla_host_t *vha)
5452{
5453 struct qla_hw_data *ha = vha->hw;
5454 mbx_cmd_t mc;
5455 mbx_cmd_t *mcp = &mc;
5456 int rval = QLA_FUNCTION_FAILED;
5457 int offset = 0, size = MINIDUMP_SIZE_36K;
5458 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0xb11f,
5459 "Entered %s.\n", __func__);
5460
5461 ha->md_tmplt_hdr = dma_alloc_coherent(&ha->pdev->dev,
5462 ha->md_template_size, &ha->md_tmplt_hdr_dma, GFP_KERNEL);
5463 if (!ha->md_tmplt_hdr) {
5464 ql_log(ql_log_warn, vha, 0xb11b,
5465 "Unable to allocate memory for Minidump template.\n");
5466 return rval;
5467 }
5468
5469 memset(mcp->mb, 0 , sizeof(mcp->mb));
5470 while (offset < ha->md_template_size) {
5471 mcp->mb[0] = LSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE);
5472 mcp->mb[1] = MSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE);
5473 mcp->mb[2] = LSW(RQST_TMPLT);
5474 mcp->mb[3] = MSW(RQST_TMPLT);
5475 mcp->mb[4] = LSW(LSD(ha->md_tmplt_hdr_dma + offset));
5476 mcp->mb[5] = MSW(LSD(ha->md_tmplt_hdr_dma + offset));
5477 mcp->mb[6] = LSW(MSD(ha->md_tmplt_hdr_dma + offset));
5478 mcp->mb[7] = MSW(MSD(ha->md_tmplt_hdr_dma + offset));
5479 mcp->mb[8] = LSW(size);
5480 mcp->mb[9] = MSW(size);
5481 mcp->mb[10] = offset & 0x0000FFFF;
5482 mcp->mb[11] = offset & 0xFFFF0000;
5483 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
5484 mcp->tov = MBX_TOV_SECONDS;
5485 mcp->out_mb = MBX_11|MBX_10|MBX_9|MBX_8|
5486 MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
5487 mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0;
5488 rval = qla2x00_mailbox_command(vha, mcp);
5489
5490 if (rval != QLA_SUCCESS) {
5491 ql_dbg(ql_dbg_mbx, vha, 0xb11c,
5492 "mailbox command FAILED=0x%x, subcode=%x.\n",
5493 ((mcp->mb[1] << 16) | mcp->mb[0]),
5494 ((mcp->mb[3] << 16) | mcp->mb[2]));
5495 return rval;
5496 } else
5497 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0xb11d,
5498 "Done %s.\n", __func__);
5499 offset = offset + size;
5500 }
5501 return rval;
5502}
5503
6246b8a1
GM		 5504int
5505qla81xx_set_led_config(scsi_qla_host_t *vha, uint16_t *led_cfg)
5506{
5507 int rval;
5508 struct qla_hw_data *ha = vha->hw;
5509 mbx_cmd_t mc;
5510 mbx_cmd_t *mcp = &mc;
5511
5512 if (!IS_QLA81XX(ha) && !IS_QLA8031(ha))
5513 return QLA_FUNCTION_FAILED;
5514
5f28d2d7
SK		 5515 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1133,
5516 "Entered %s.\n", __func__);
6246b8a1
GM		 5517
5518 memset(mcp, 0, sizeof(mbx_cmd_t));
5519 mcp->mb[0] = MBC_SET_LED_CONFIG;
5520 mcp->mb[1] = led_cfg[0];
5521 mcp->mb[2] = led_cfg[1];
5522 if (IS_QLA8031(ha)) {
5523 mcp->mb[3] = led_cfg[2];
5524 mcp->mb[4] = led_cfg[3];
5525 mcp->mb[5] = led_cfg[4];
5526 mcp->mb[6] = led_cfg[5];
5527 }
5528
5529 mcp->out_mb = MBX_2|MBX_1|MBX_0;
5530 if (IS_QLA8031(ha))
5531 mcp->out_mb |= MBX_6|MBX_5|MBX_4|MBX_3;
5532 mcp->in_mb = MBX_0;
5533 mcp->tov = 30;
5534 mcp->flags = 0;
5535
5536 rval = qla2x00_mailbox_command(vha, mcp);
5537 if (rval != QLA_SUCCESS) {
5538 ql_dbg(ql_dbg_mbx, vha, 0x1134,
5539 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
5540 } else {
5f28d2d7
SK		 5541 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1135,
5542 "Done %s.\n", __func__);
6246b8a1
GM		 5543 }
5544
5545 return rval;
5546}
5547
5548int
5549qla81xx_get_led_config(scsi_qla_host_t *vha, uint16_t *led_cfg)
5550{
5551 int rval;
5552 struct qla_hw_data *ha = vha->hw;
5553 mbx_cmd_t mc;
5554 mbx_cmd_t *mcp = &mc;
5555
5556 if (!IS_QLA81XX(ha) && !IS_QLA8031(ha))
5557 return QLA_FUNCTION_FAILED;
5558
5f28d2d7
SK		 5559 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1136,
5560 "Entered %s.\n", __func__);
6246b8a1
GM		 5561
5562 memset(mcp, 0, sizeof(mbx_cmd_t));
5563 mcp->mb[0] = MBC_GET_LED_CONFIG;
5564
5565 mcp->out_mb = MBX_0;
5566 mcp->in_mb = MBX_2|MBX_1|MBX_0;
5567 if (IS_QLA8031(ha))
5568 mcp->in_mb |= MBX_6|MBX_5|MBX_4|MBX_3;
5569 mcp->tov = 30;
5570 mcp->flags = 0;
5571
5572 rval = qla2x00_mailbox_command(vha, mcp);
5573 if (rval != QLA_SUCCESS) {
5574 ql_dbg(ql_dbg_mbx, vha, 0x1137,
5575 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
5576 } else {
5577 led_cfg[0] = mcp->mb[1];
5578 led_cfg[1] = mcp->mb[2];
5579 if (IS_QLA8031(ha)) {
5580 led_cfg[2] = mcp->mb[3];
5581 led_cfg[3] = mcp->mb[4];
5582 led_cfg[4] = mcp->mb[5];
5583 led_cfg[5] = mcp->mb[6];
5584 }
5f28d2d7
SK		 5585 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1138,
5586 "Done %s.\n", __func__);
6246b8a1
GM		 5587 }
5588
5589 return rval;
5590}
5591
999916dc
SK		 5592int
5593qla82xx_mbx_beacon_ctl(scsi_qla_host_t *vha, int enable)
5594{
5595 int rval;
5596 struct qla_hw_data *ha = vha->hw;
5597 mbx_cmd_t mc;
5598 mbx_cmd_t *mcp = &mc;
5599
7ec0effd 5600 if (!IS_P3P_TYPE(ha))
999916dc
SK		 5601 return QLA_FUNCTION_FAILED;
5602
5f28d2d7 5603 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1127,
999916dc
SK		 5604 "Entered %s.\n", __func__);
5605
5606 memset(mcp, 0, sizeof(mbx_cmd_t));
5607 mcp->mb[0] = MBC_SET_LED_CONFIG;
5608 if (enable)
5609 mcp->mb[7] = 0xE;
5610 else
5611 mcp->mb[7] = 0xD;
5612
5613 mcp->out_mb = MBX_7|MBX_0;
5614 mcp->in_mb = MBX_0;
6246b8a1 5615 mcp->tov = MBX_TOV_SECONDS;
999916dc
SK		 5616 mcp->flags = 0;
5617
5618 rval = qla2x00_mailbox_command(vha, mcp);
5619 if (rval != QLA_SUCCESS) {
5620 ql_dbg(ql_dbg_mbx, vha, 0x1128,
5621 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
5622 } else {
5f28d2d7 5623 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1129,
999916dc
SK		 5624 "Done %s.\n", __func__);
5625 }
5626
5627 return rval;
5628}
6246b8a1
GM		 5629
5630int
7d613ac6 5631qla83xx_wr_reg(scsi_qla_host_t *vha, uint32_t reg, uint32_t data)
6246b8a1
GM		 5632{
5633 int rval;
5634 struct qla_hw_data *ha = vha->hw;
5635 mbx_cmd_t mc;
5636 mbx_cmd_t *mcp = &mc;
5637
f73cb695 5638 if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha))
6246b8a1
GM		 5639 return QLA_FUNCTION_FAILED;
5640
5f28d2d7
SK		 5641 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1130,
5642 "Entered %s.\n", __func__);
6246b8a1
GM		 5643
5644 mcp->mb[0] = MBC_WRITE_REMOTE_REG;
5645 mcp->mb[1] = LSW(reg);
5646 mcp->mb[2] = MSW(reg);
5647 mcp->mb[3] = LSW(data);
5648 mcp->mb[4] = MSW(data);
5649 mcp->out_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
5650
5651 mcp->in_mb = MBX_1|MBX_0;
5652 mcp->tov = MBX_TOV_SECONDS;
5653 mcp->flags = 0;
5654 rval = qla2x00_mailbox_command(vha, mcp);
5655
5656 if (rval != QLA_SUCCESS) {
5657 ql_dbg(ql_dbg_mbx, vha, 0x1131,
5658 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
5659 } else {
5f28d2d7 5660 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1132,
6246b8a1
GM		 5661 "Done %s.\n", __func__);
5662 }
af11f64d 5663
6246b8a1
GM		 5664 return rval;
5665}
af11f64d
AV		 5666
5667int
5668qla2x00_port_logout(scsi_qla_host_t *vha, struct fc_port *fcport)
5669{
5670 int rval;
5671 struct qla_hw_data *ha = vha->hw;
5672 mbx_cmd_t mc;
5673 mbx_cmd_t *mcp = &mc;
5674
5675 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
5f28d2d7 5676 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x113b,
af11f64d
AV		 5677 "Implicit LOGO Unsupported.\n");
5678 return QLA_FUNCTION_FAILED;
5679 }
5680
5681
5f28d2d7
SK		 5682 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x113c,
5683 "Entering %s.\n", __func__);
af11f64d
AV		 5684
5685 /* Perform Implicit LOGO. */
5686 mcp->mb[0] = MBC_PORT_LOGOUT;
5687 mcp->mb[1] = fcport->loop_id;
5688 mcp->mb[10] = BIT_15;
5689 mcp->out_mb = MBX_10|MBX_1|MBX_0;
5690 mcp->in_mb = MBX_0;
5691 mcp->tov = MBX_TOV_SECONDS;
5692 mcp->flags = 0;
5693 rval = qla2x00_mailbox_command(vha, mcp);
5694 if (rval != QLA_SUCCESS)
5695 ql_dbg(ql_dbg_mbx, vha, 0x113d,
5696 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
5697 else
5f28d2d7
SK		 5698 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x113e,
5699 "Done %s.\n", __func__);
af11f64d
AV		 5700
5701 return rval;
5702}
5703
7d613ac6
SV		 5704int
5705qla83xx_rd_reg(scsi_qla_host_t *vha, uint32_t reg, uint32_t *data)
5706{
5707 int rval;
5708 mbx_cmd_t mc;
5709 mbx_cmd_t *mcp = &mc;
5710 struct qla_hw_data *ha = vha->hw;
5711 unsigned long retry_max_time = jiffies + (2 * HZ);
5712
f73cb695 5713 if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha))
7d613ac6
SV		 5714 return QLA_FUNCTION_FAILED;
5715
5716 ql_dbg(ql_dbg_mbx, vha, 0x114b, "Entered %s.\n", __func__);
5717
5718retry_rd_reg:
5719 mcp->mb[0] = MBC_READ_REMOTE_REG;
5720 mcp->mb[1] = LSW(reg);
5721 mcp->mb[2] = MSW(reg);
5722 mcp->out_mb = MBX_2|MBX_1|MBX_0;
5723 mcp->in_mb = MBX_4|MBX_3|MBX_1|MBX_0;
5724 mcp->tov = MBX_TOV_SECONDS;
5725 mcp->flags = 0;
5726 rval = qla2x00_mailbox_command(vha, mcp);
5727
5728 if (rval != QLA_SUCCESS) {
5729 ql_dbg(ql_dbg_mbx, vha, 0x114c,
5730 "Failed=%x mb[0]=%x mb[1]=%x.\n",
5731 rval, mcp->mb[0], mcp->mb[1]);
5732 } else {
5733 *data = (mcp->mb[3] | (mcp->mb[4] << 16));
5734 if (*data == QLA8XXX_BAD_VALUE) {
5735 /*
5736 * During soft-reset CAMRAM register reads might
5737 * return 0xbad0bad0. So retry for MAX of 2 sec
5738 * while reading camram registers.
5739 */
5740 if (time_after(jiffies, retry_max_time)) {
5741 ql_dbg(ql_dbg_mbx, vha, 0x1141,
5742 "Failure to read CAMRAM register. "
5743 "data=0x%x.\n", *data);
5744 return QLA_FUNCTION_FAILED;
5745 }
5746 msleep(100);
5747 goto retry_rd_reg;
5748 }
5749 ql_dbg(ql_dbg_mbx, vha, 0x1142, "Done %s.\n", __func__);
5750 }
5751
5752 return rval;
5753}
5754
5755int
5756qla83xx_restart_nic_firmware(scsi_qla_host_t *vha)
5757{
5758 int rval;
5759 mbx_cmd_t mc;
5760 mbx_cmd_t *mcp = &mc;
5761 struct qla_hw_data *ha = vha->hw;
5762
b20f02e1 5763 if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha))
7d613ac6
SV		 5764 return QLA_FUNCTION_FAILED;
5765
5766 ql_dbg(ql_dbg_mbx, vha, 0x1143, "Entered %s.\n", __func__);
5767
5768 mcp->mb[0] = MBC_RESTART_NIC_FIRMWARE;
5769 mcp->out_mb = MBX_0;
5770 mcp->in_mb = MBX_1|MBX_0;
5771 mcp->tov = MBX_TOV_SECONDS;
5772 mcp->flags = 0;
5773 rval = qla2x00_mailbox_command(vha, mcp);
5774
5775 if (rval != QLA_SUCCESS) {
5776 ql_dbg(ql_dbg_mbx, vha, 0x1144,
5777 "Failed=%x mb[0]=%x mb[1]=%x.\n",
5778 rval, mcp->mb[0], mcp->mb[1]);
5779 ha->isp_ops->fw_dump(vha, 0);
5780 } else {
5781 ql_dbg(ql_dbg_mbx, vha, 0x1145, "Done %s.\n", __func__);
5782 }
5783
5784 return rval;
5785}
5786
5787int
5788qla83xx_access_control(scsi_qla_host_t *vha, uint16_t options,
5789 uint32_t start_addr, uint32_t end_addr, uint16_t *sector_size)
5790{
5791 int rval;
5792 mbx_cmd_t mc;
5793 mbx_cmd_t *mcp = &mc;
5794 uint8_t subcode = (uint8_t)options;
5795 struct qla_hw_data *ha = vha->hw;
5796
5797 if (!IS_QLA8031(ha))
5798 return QLA_FUNCTION_FAILED;
5799
5800 ql_dbg(ql_dbg_mbx, vha, 0x1146, "Entered %s.\n", __func__);
5801
5802 mcp->mb[0] = MBC_SET_ACCESS_CONTROL;
5803 mcp->mb[1] = options;
5804 mcp->out_mb = MBX_1|MBX_0;
5805 if (subcode & BIT_2) {
5806 mcp->mb[2] = LSW(start_addr);
5807 mcp->mb[3] = MSW(start_addr);
5808 mcp->mb[4] = LSW(end_addr);
5809 mcp->mb[5] = MSW(end_addr);
5810 mcp->out_mb |= MBX_5|MBX_4|MBX_3|MBX_2;
5811 }
5812 mcp->in_mb = MBX_2|MBX_1|MBX_0;
5813 if (!(subcode & (BIT_2 | BIT_5)))
5814 mcp->in_mb |= MBX_4|MBX_3;
5815 mcp->tov = MBX_TOV_SECONDS;
5816 mcp->flags = 0;
5817 rval = qla2x00_mailbox_command(vha, mcp);
5818
5819 if (rval != QLA_SUCCESS) {
5820 ql_dbg(ql_dbg_mbx, vha, 0x1147,
5821 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x mb[3]=%x mb[4]=%x.\n",
5822 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2], mcp->mb[3],
5823 mcp->mb[4]);
5824 ha->isp_ops->fw_dump(vha, 0);
5825 } else {
5826 if (subcode & BIT_5)
5827 *sector_size = mcp->mb[1];
5828 else if (subcode & (BIT_6 | BIT_7)) {
5829 ql_dbg(ql_dbg_mbx, vha, 0x1148,
5830 "Driver-lock id=%x%x", mcp->mb[4], mcp->mb[3]);
5831 } else if (subcode & (BIT_3 | BIT_4)) {
5832 ql_dbg(ql_dbg_mbx, vha, 0x1149,
5833 "Flash-lock id=%x%x", mcp->mb[4], mcp->mb[3]);
5834 }
5835 ql_dbg(ql_dbg_mbx, vha, 0x114a, "Done %s.\n", __func__);
5836 }
5837
5838 return rval;
5839}
81178772
SK		 5840
5841int
5842qla2x00_dump_mctp_data(scsi_qla_host_t *vha, dma_addr_t req_dma, uint32_t addr,
5843 uint32_t size)
5844{
5845 int rval;
5846 mbx_cmd_t mc;
5847 mbx_cmd_t *mcp = &mc;
5848
5849 if (!IS_MCTP_CAPABLE(vha->hw))
5850 return QLA_FUNCTION_FAILED;
5851
5852 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x114f,
5853 "Entered %s.\n", __func__);
5854
5855 mcp->mb[0] = MBC_DUMP_RISC_RAM_EXTENDED;
5856 mcp->mb[1] = LSW(addr);
5857 mcp->mb[2] = MSW(req_dma);
5858 mcp->mb[3] = LSW(req_dma);
5859 mcp->mb[4] = MSW(size);
5860 mcp->mb[5] = LSW(size);
5861 mcp->mb[6] = MSW(MSD(req_dma));
5862 mcp->mb[7] = LSW(MSD(req_dma));
5863 mcp->mb[8] = MSW(addr);
5864 /* Setting RAM ID to valid */
5865 mcp->mb[10] |= BIT_7;
5866 /* For MCTP RAM ID is 0x40 */
5867 mcp->mb[10] |= 0x40;
5868
5869 mcp->out_mb |= MBX_10|MBX_8|MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|
5870 MBX_0;
5871
5872 mcp->in_mb = MBX_0;
5873 mcp->tov = MBX_TOV_SECONDS;
5874 mcp->flags = 0;
5875 rval = qla2x00_mailbox_command(vha, mcp);
5876
5877 if (rval != QLA_SUCCESS) {
5878 ql_dbg(ql_dbg_mbx, vha, 0x114e,
5879 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
5880 } else {
5881 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x114d,
5882 "Done %s.\n", __func__);
5883 }
5884
5885 return rval;
5886}
ec891462
JC		 5887
5888int
5889qla26xx_dport_diagnostics(scsi_qla_host_t *vha,
5890 void *dd_buf, uint size, uint options)
5891{
5892 int rval;
5893 mbx_cmd_t mc;
5894 mbx_cmd_t *mcp = &mc;
5895 dma_addr_t dd_dma;
5896
5897 if (!IS_QLA83XX(vha->hw) && !IS_QLA27XX(vha->hw))
5898 return QLA_FUNCTION_FAILED;
5899
83548fe2 5900 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x119f,
ec891462
JC		 5901 "Entered %s.\n", __func__);
5902
ec891462
JC		 5903 dd_dma = dma_map_single(&vha->hw->pdev->dev,
5904 dd_buf, size, DMA_FROM_DEVICE);
0b2ce198 5905 if (dma_mapping_error(&vha->hw->pdev->dev, dd_dma)) {
ec891462
JC		 5906 ql_log(ql_log_warn, vha, 0x1194, "Failed to map dma buffer.\n");
5907 return QLA_MEMORY_ALLOC_FAILED;
5908 }
5909
5910 memset(dd_buf, 0, size);
5911
5912 mcp->mb[0] = MBC_DPORT_DIAGNOSTICS;
5913 mcp->mb[1] = options;
5914 mcp->mb[2] = MSW(LSD(dd_dma));
5915 mcp->mb[3] = LSW(LSD(dd_dma));
5916 mcp->mb[6] = MSW(MSD(dd_dma));
5917 mcp->mb[7] = LSW(MSD(dd_dma));
5918 mcp->mb[8] = size;
5919 mcp->out_mb = MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
5920 mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0;
5921 mcp->buf_size = size;
5922 mcp->flags = MBX_DMA_IN;
5923 mcp->tov = MBX_TOV_SECONDS * 4;
5924 rval = qla2x00_mailbox_command(vha, mcp);
5925
5926 if (rval != QLA_SUCCESS) {
5927 ql_dbg(ql_dbg_mbx, vha, 0x1195, "Failed=%x.\n", rval);
5928 } else {
5929 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1196,
5930 "Done %s.\n", __func__);
5931 }
5932
5933 dma_unmap_single(&vha->hw->pdev->dev, dd_dma,
5934 size, DMA_FROM_DEVICE);
5935
5936 return rval;
5937}
15f30a57
QT		 5938
5939static void qla2x00_async_mb_sp_done(void *s, int res)
5940{
5941 struct srb *sp = s;
5942
5943 sp->u.iocb_cmd.u.mbx.rc = res;
5944
5945 complete(&sp->u.iocb_cmd.u.mbx.comp);
5946 /* don't free sp here. Let the caller do the free */
5947}
5948
5949/*
5950 * This mailbox uses the iocb interface to send MB command.
5951 * This allows non-critial (non chip setup) command to go
5952 * out in parrallel.
5953 */
5954int qla24xx_send_mb_cmd(struct scsi_qla_host *vha, mbx_cmd_t *mcp)
5955{
5956 int rval = QLA_FUNCTION_FAILED;
5957 srb_t *sp;
5958 struct srb_iocb *c;
5959
5960 if (!vha->hw->flags.fw_started)
5961 goto done;
5962
5963 sp = qla2x00_get_sp(vha, NULL, GFP_KERNEL);
5964 if (!sp)
5965 goto done;
5966
5967 sp->type = SRB_MB_IOCB;
5968 sp->name = mb_to_str(mcp->mb[0]);
5969
5970 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
5971
5972 memcpy(sp->u.iocb_cmd.u.mbx.out_mb, mcp->mb, SIZEOF_IOCB_MB_REG);
5973
5974 c = &sp->u.iocb_cmd;
5975 c->timeout = qla2x00_async_iocb_timeout;
5976 init_completion(&c->u.mbx.comp);
5977
5978 sp->done = qla2x00_async_mb_sp_done;
5979
5980 rval = qla2x00_start_sp(sp);
5981 if (rval != QLA_SUCCESS) {
83548fe2 5982 ql_dbg(ql_dbg_mbx, vha, 0x1018,
15f30a57
QT		 5983 "%s: %s Failed submission. %x.\n",
5984 __func__, sp->name, rval);
5985 goto done_free_sp;
5986 }
5987
83548fe2 5988 ql_dbg(ql_dbg_mbx, vha, 0x113f, "MB:%s hndl %x submitted\n",
15f30a57
QT		 5989 sp->name, sp->handle);
5990
5991 wait_for_completion(&c->u.mbx.comp);
5992 memcpy(mcp->mb, sp->u.iocb_cmd.u.mbx.in_mb, SIZEOF_IOCB_MB_REG);
5993
5994 rval = c->u.mbx.rc;
5995 switch (rval) {
5996 case QLA_FUNCTION_TIMEOUT:
83548fe2 5997 ql_dbg(ql_dbg_mbx, vha, 0x1140, "%s: %s Timeout. %x.\n",
15f30a57
QT		 5998 __func__, sp->name, rval);
5999 break;
6000 case QLA_SUCCESS:
83548fe2 6001 ql_dbg(ql_dbg_mbx, vha, 0x119d, "%s: %s done.\n",
15f30a57
QT		 6002 __func__, sp->name);
6003 sp->free(sp);
6004 break;
6005 default:
83548fe2 6006 ql_dbg(ql_dbg_mbx, vha, 0x119e, "%s: %s Failed. %x.\n",
15f30a57
QT		 6007 __func__, sp->name, rval);
6008 sp->free(sp);
6009 break;
6010 }
6011
6012 return rval;
6013
6014done_free_sp:
6015 sp->free(sp);
6016done:
6017 return rval;
6018}
6019
6020/*
6021 * qla24xx_gpdb_wait
6022 * NOTE: Do not call this routine from DPC thread
6023 */
6024int qla24xx_gpdb_wait(struct scsi_qla_host *vha, fc_port_t *fcport, u8 opt)
6025{
6026 int rval = QLA_FUNCTION_FAILED;
6027 dma_addr_t pd_dma;
6028 struct port_database_24xx *pd;
6029 struct qla_hw_data *ha = vha->hw;
6030 mbx_cmd_t mc;
6031
6032 if (!vha->hw->flags.fw_started)
6033 goto done;
6034
08eb7f45 6035 pd = dma_pool_zalloc(ha->s_dma_pool, GFP_KERNEL, &pd_dma);
15f30a57 6036 if (pd == NULL) {
83548fe2
QT		 6037 ql_log(ql_log_warn, vha, 0xd047,
6038 "Failed to allocate port database structure.\n");
15f30a57
QT		 6039 goto done_free_sp;
6040 }
15f30a57
QT		 6041
6042 memset(&mc, 0, sizeof(mc));
6043 mc.mb[0] = MBC_GET_PORT_DATABASE;
6044 mc.mb[1] = cpu_to_le16(fcport->loop_id);
6045 mc.mb[2] = MSW(pd_dma);
6046 mc.mb[3] = LSW(pd_dma);
6047 mc.mb[6] = MSW(MSD(pd_dma));
6048 mc.mb[7] = LSW(MSD(pd_dma));
6049 mc.mb[9] = cpu_to_le16(vha->vp_idx);
6050 mc.mb[10] = cpu_to_le16((uint16_t)opt);
6051
6052 rval = qla24xx_send_mb_cmd(vha, &mc);
6053 if (rval != QLA_SUCCESS) {
83548fe2 6054 ql_dbg(ql_dbg_mbx, vha, 0x1193,
15f30a57
QT		 6055 "%s: %8phC fail\n", __func__, fcport->port_name);
6056 goto done_free_sp;
6057 }
6058
6059 rval = __qla24xx_parse_gpdb(vha, fcport, pd);
6060
83548fe2 6061 ql_dbg(ql_dbg_mbx, vha, 0x1197, "%s: %8phC done\n",
15f30a57
QT		 6062 __func__, fcport->port_name);
6063
6064done_free_sp:
6065 if (pd)
6066 dma_pool_free(ha->s_dma_pool, pd, pd_dma);
6067done:
6068 return rval;
6069}
6070
6071int __qla24xx_parse_gpdb(struct scsi_qla_host *vha, fc_port_t *fcport,
6072 struct port_database_24xx *pd)
6073{
6074 int rval = QLA_SUCCESS;
6075 uint64_t zero = 0;
a5d42f4c
DG		 6076 u8 current_login_state, last_login_state;
6077
6078 if (fcport->fc4f_nvme) {
6079 current_login_state = pd->current_login_state >> 4;
6080 last_login_state = pd->last_login_state >> 4;
6081 } else {
6082 current_login_state = pd->current_login_state & 0xf;
6083 last_login_state = pd->last_login_state & 0xf;
6084 }
15f30a57
QT		 6085
6086 /* Check for logged in state. */
23c64559 6087 if (current_login_state != PDS_PRLI_COMPLETE) {
83548fe2
QT		 6088 ql_dbg(ql_dbg_mbx, vha, 0x119a,
6089 "Unable to verify login-state (%x/%x) for loop_id %x.\n",
a5d42f4c 6090 current_login_state, last_login_state, fcport->loop_id);
15f30a57
QT		 6091 rval = QLA_FUNCTION_FAILED;
6092 goto gpd_error_out;
6093 }
6094
6095 if (fcport->loop_id == FC_NO_LOOP_ID ||
6096 (memcmp(fcport->port_name, (uint8_t *)&zero, 8) &&
6097 memcmp(fcport->port_name, pd->port_name, 8))) {
6098 /* We lost the device mid way. */
6099 rval = QLA_NOT_LOGGED_IN;
6100 goto gpd_error_out;
6101 }
6102
6103 /* Names are little-endian. */
6104 memcpy(fcport->node_name, pd->node_name, WWN_SIZE);
6105 memcpy(fcport->port_name, pd->port_name, WWN_SIZE);
6106
6107 /* Get port_id of device. */
6108 fcport->d_id.b.domain = pd->port_id[0];
6109 fcport->d_id.b.area = pd->port_id[1];
6110 fcport->d_id.b.al_pa = pd->port_id[2];
6111 fcport->d_id.b.rsvd_1 = 0;
6112
a5d42f4c
DG		 6113 if (fcport->fc4f_nvme) {
6114 fcport->nvme_prli_service_param =
6115 pd->prli_nvme_svc_param_word_3;
6116 fcport->port_type = FCT_NVME;
6117 } else {
6118 /* If not target must be initiator or unknown type. */
6119 if ((pd->prli_svc_param_word_3[0] & BIT_4) == 0)
6120 fcport->port_type = FCT_INITIATOR;
6121 else
6122 fcport->port_type = FCT_TARGET;
6123 }
15f30a57
QT		 6124 /* Passback COS information. */
6125 fcport->supported_classes = (pd->flags & PDF_CLASS_2) ?
6126 FC_COS_CLASS2 : FC_COS_CLASS3;
6127
6128 if (pd->prli_svc_param_word_3[0] & BIT_7) {
6129 fcport->flags |= FCF_CONF_COMP_SUPPORTED;
6130 fcport->conf_compl_supported = 1;
6131 }
6132
6133gpd_error_out:
6134 return rval;
6135}
6136
6137/*
6138 * qla24xx_gidlist__wait
6139 * NOTE: don't call this routine from DPC thread.
6140 */
6141int qla24xx_gidlist_wait(struct scsi_qla_host *vha,
6142 void *id_list, dma_addr_t id_list_dma, uint16_t *entries)
6143{
6144 int rval = QLA_FUNCTION_FAILED;
6145 mbx_cmd_t mc;
6146
6147 if (!vha->hw->flags.fw_started)
6148 goto done;
6149
6150 memset(&mc, 0, sizeof(mc));
6151 mc.mb[0] = MBC_GET_ID_LIST;
6152 mc.mb[2] = MSW(id_list_dma);
6153 mc.mb[3] = LSW(id_list_dma);
6154 mc.mb[6] = MSW(MSD(id_list_dma));
6155 mc.mb[7] = LSW(MSD(id_list_dma));
6156 mc.mb[8] = 0;
6157 mc.mb[9] = cpu_to_le16(vha->vp_idx);
6158
6159 rval = qla24xx_send_mb_cmd(vha, &mc);
6160 if (rval != QLA_SUCCESS) {
83548fe2
QT		 6161 ql_dbg(ql_dbg_mbx, vha, 0x119b,
6162 "%s: fail\n", __func__);
15f30a57
QT		 6163 } else {
6164 *entries = mc.mb[1];
83548fe2
QT		 6165 ql_dbg(ql_dbg_mbx, vha, 0x119c,
6166 "%s: done\n", __func__);
15f30a57
QT		 6167 }
6168done:
6169 return rval;
6170}
deeae7a6
DG		 6171
6172int qla27xx_set_zio_threshold(scsi_qla_host_t *vha, uint16_t value)
6173{
6174 int rval;
6175 mbx_cmd_t mc;
6176 mbx_cmd_t *mcp = &mc;
6177
6178 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1200,
6179 "Entered %s\n", __func__);
6180
6181 memset(mcp->mb, 0 , sizeof(mcp->mb));
6182 mcp->mb[0] = MBC_GET_SET_ZIO_THRESHOLD;
6183 mcp->mb[1] = cpu_to_le16(1);
6184 mcp->mb[2] = cpu_to_le16(value);
6185 mcp->out_mb = MBX_2 | MBX_1 | MBX_0;
6186 mcp->in_mb = MBX_2 | MBX_0;
6187 mcp->tov = MBX_TOV_SECONDS;
6188 mcp->flags = 0;
6189
6190 rval = qla2x00_mailbox_command(vha, mcp);
6191
6192 ql_dbg(ql_dbg_mbx, vha, 0x1201, "%s %x\n",
6193 (rval != QLA_SUCCESS) ? "Failed" : "Done", rval);
6194
6195 return rval;
6196}
6197
6198int qla27xx_get_zio_threshold(scsi_qla_host_t *vha, uint16_t *value)
6199{
6200 int rval;
6201 mbx_cmd_t mc;
6202 mbx_cmd_t *mcp = &mc;
6203
6204 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1203,
6205 "Entered %s\n", __func__);
6206
6207 memset(mcp->mb, 0, sizeof(mcp->mb));
6208 mcp->mb[0] = MBC_GET_SET_ZIO_THRESHOLD;
6209 mcp->mb[1] = cpu_to_le16(0);
6210 mcp->out_mb = MBX_1 | MBX_0;
6211 mcp->in_mb = MBX_2 | MBX_0;
6212 mcp->tov = MBX_TOV_SECONDS;
6213 mcp->flags = 0;
6214
6215 rval = qla2x00_mailbox_command(vha, mcp);
6216 if (rval == QLA_SUCCESS)
6217 *value = mc.mb[2];
6218
6219 ql_dbg(ql_dbg_mbx, vha, 0x1205, "%s %x\n",
6220 (rval != QLA_SUCCESS) ? "Failed" : "Done", rval);
6221
6222 return rval;
6223}
e4e3a2ce
QT		 6224
6225int
6226qla2x00_read_sfp_dev(struct scsi_qla_host *vha, char *buf, int count)
6227{
6228 struct qla_hw_data *ha = vha->hw;
6229 uint16_t iter, addr, offset;
6230 dma_addr_t phys_addr;
6231 int rval, c;
6232 u8 *sfp_data;
6233
6234 memset(ha->sfp_data, 0, SFP_DEV_SIZE);
6235 addr = 0xa0;
6236 phys_addr = ha->sfp_data_dma;
6237 sfp_data = ha->sfp_data;
6238 offset = c = 0;
6239
6240 for (iter = 0; iter < SFP_DEV_SIZE / SFP_BLOCK_SIZE; iter++) {
6241 if (iter == 4) {
6242 /* Skip to next device address. */
6243 addr = 0xa2;
6244 offset = 0;
6245 }
6246
6247 rval = qla2x00_read_sfp(vha, phys_addr, sfp_data,
6248 addr, offset, SFP_BLOCK_SIZE, BIT_1);
6249 if (rval != QLA_SUCCESS) {
6250 ql_log(ql_log_warn, vha, 0x706d,
6251 "Unable to read SFP data (%x/%x/%x).\n", rval,
6252 addr, offset);
6253
6254 return rval;
6255 }
6256
6257 if (buf && (c < count)) {
6258 u16 sz;
6259
6260 if ((count - c) >= SFP_BLOCK_SIZE)
6261 sz = SFP_BLOCK_SIZE;
6262 else
6263 sz = count - c;
6264
6265 memcpy(buf, sfp_data, sz);
6266 buf += SFP_BLOCK_SIZE;
6267 c += sz;
6268 }
6269 phys_addr += SFP_BLOCK_SIZE;
6270 sfp_data += SFP_BLOCK_SIZE;
6271 offset += SFP_BLOCK_SIZE;
6272 }
6273
6274 return rval;
6275}
94d83e36
QT		 6276
6277int qla24xx_res_count_wait(struct scsi_qla_host *vha,
6278 uint16_t *out_mb, int out_mb_sz)
6279{
6280 int rval = QLA_FUNCTION_FAILED;
6281 mbx_cmd_t mc;
6282
6283 if (!vha->hw->flags.fw_started)
6284 goto done;
6285
6286 memset(&mc, 0, sizeof(mc));
6287 mc.mb[0] = MBC_GET_RESOURCE_COUNTS;
6288
6289 rval = qla24xx_send_mb_cmd(vha, &mc);
6290 if (rval != QLA_SUCCESS) {
6291 ql_dbg(ql_dbg_mbx, vha, 0xffff,
6292 "%s: fail\n", __func__);
6293 } else {
6294 if (out_mb_sz <= SIZEOF_IOCB_MB_REG)
6295 memcpy(out_mb, mc.mb, out_mb_sz);
6296 else
6297 memcpy(out_mb, mc.mb, SIZEOF_IOCB_MB_REG);
6298
6299 ql_dbg(ql_dbg_mbx, vha, 0xffff,
6300 "%s: done\n", __func__);
6301 }
6302done:
6303 return rval;
6304}
Linux 6.x block layer and io_uring tree(s)